changelog.txt

BitConnector v5Xe:
	- Optimize the distance between the two pin headers
	- Optimize the placement of the CPLD by 2 degrees to the left
	- As a result of the rotation, all data lines now have at least one width of 10 mils (0.254 mm).
	- Further grounding surfaces were introduced on the top
	- Turn decoupling capacitors to bring them closer to VCC
	- PCB pin label now contains the CPLD pins

BitConnector v5X:
	- switch solder pad for resistors from 1.15mm to 1.20mm
	- add additional 10nF bypass capacitor according to 
	  Xilinx XAPP104 (3.0.1) specification
	- Completely new board layout created to improve 
	  GND and Vcc connection and suppress interference signals
	- fallback to v3X (minimal configuration) is retained 
	- 74LVC2G14 (schmitt trigger) now has a better footprint
	- change logo to tux from ti-band
	
BitConnector v4X:
	- Add hardware debouncing via schmitt trigger action via 74LVC2G14
	- A low-pass filter in front of the schmitt trigger is provided.
	- The schmnitt trigger adds another external inverter. Usable over J2.
 	- As an alternative, add jumper to bridge the schmitt trigger IC 74LVC2G14.
          Use this to fallback to v3X. (Push Button is now active low)
 	- Partial redesign of the routing
	- Move copper logo to the silkscreen on the back

BitConnector v3X:
	- optimize DIP pin spacing for use on a breadboard
	- change JTAG IDC pin header from 8 to 6 pins
	- optimize some circuit paths
	- change logo on copper print