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Intermittent ram issues on Carambola 2 boards #5
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Hi, Carambola2 actually uses 200MHz DDR clock so: Have you tried running memtest on unstable devices, if not please try (https://github.com/mantas-p/files/blob/master/memtest_mipsbe/memtester?raw=true) Are there any specific conditions when issue happens, or it is completely random? Are you using 8devices devboard or your own design? If it's your design, please contact [email protected] we may have suggestions regarding HW design. |
This is a custom design. I have memtester running now on some units [ 0.000000] Clocks: CPU:400.000MHz, DDR:400.000MHz, AHB:200.000MHz, Ref:40.000MHz The crashes are quite random. Sometimes often, sometimes never even under stress loads, such as Here is a crashlog <6>[ 0.000013] sched_clock: 32 bits at 200MHz, resolution 5ns, wraps every 10737418237ns |
This is PLL output to DDR controller, DRAM clock line runs at 200MHz, I've checked with oscilloscope. Crash log definitely looks like DRAM issue. Did you find anything with How many Carambola2 samples you're having issue with? Did any previous batch worked well in your design? |
History Testing stress -c 64 -m 16 --vm-bytes 1M I am ran 5 overnight tests..
[38599.019192] epc = 003fdad5 in I am not sure if this a bug in the kernel, DRAM error, or userland error. I will take the rest of this issue to the support email, but I would still like to document the final resolution here. |
@codehero , I get a similar crash ( on a custom board too) but its fairly repeatable when I cycle the Wifi system ( change channel or tx power and then reload wifi ). a bug report on LEDE's bug system was logged, but I did not get anywhere other than it possibly being a DRAM issue. What in the crashlog leads one to the DRAM issue ( corrupt addresses ? ) I'm running Do you have inline Resistors on your DRAM lines ( like Arduino Yun and some other AR9331 designs ) or are they directly connected and only length matched ? We're also using Winbond W9751G6KB RAM ( like in pepe2k/u-boot_mod#207 ) |
I am having very intermittent stability issues using both Caraboot and pepe-2k.
Both u-boot versions assume a tRAS value of 40 ns
This was true when the Carambola2 module used the W9751G6JB25 DDR2 module.
However, I popped off the cap of a newer Carambola2 module and it now uses W9751G6KB25
According to line in include/configs/carambola2.h
#define CFG_DDR_CONFIG_VAL 0x7fbc8cd0
tRAS is still specified at 40 ns
Should the default safe value be at 45 ns???
See datasheets
Page 45 of
http://digichip.ru/datasheet/PDF/df799b2e552ae92d5acb3f8b9c437f77/68da5750c408c276e3bcd1df60096ddc/W9751G6JB25.pdf
Page 45 of
https://www.winbond.com/resource-files/da00-w9751g6kbg1.pdf
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