timing

Introduction

These repository illustrates how to perform timing optimization (or timing closure) using Intel Quartus software. The provided examples are designed to work on the Intel DevCloud, but can also be performed by installing Quartus locally.

The exercises folder includes simple circuits that explain the basics of timing optimization by providing the reader with unoptimized code that they can analyze to identify timing bottlenecks, and then optimize using the presented techniques. Each exercise includes a solution for reference. The examples folder demonstrates timing optimization examples without corresponding exercises.

Suggested Study Order

1. DevCloud Instructions (Optional if using Quartus locally)
2. Video: Background and Challenges, Slides
   • Description: Provides an overview of necessary background material for understanding challenges of timing optimization.
3. Video: Optimization Strategies, Slides
   • Description: Describes different types of bottlenecks and common optimization strategies for eliminating those bottlenecks.
4. Exercise: Add Tree
   • Description: Illustrates how to identify a logic-delay bottleneck with the Quartus Timing Analyzer, and then resolve that bottleneck using pipelining.
   • Video: Quartus Timing Analyzer Overview and Add Tree Explanation, Slides
5. Exercise: Timer
   • Description: Illustrates how to reduce LUT delays by shrinking logic inputs using constants.
   • Video: Reducing LUT Delays (Timer Example), Slides
6. Exercise: Timer2
   • Description: Improves upon the timer example to show how to further improve timing by simplifying logic.
7. Example: Register Duplication
   • Description: Demonstrates how to reduce fanout bottlenecks resulting from high register fanout via register duplication.
8. Example: Reset Reduction
   • Description: Demonstrates how high fanout reset signals can create timing bottlenecks, and that be removing resets from registers that don't need them is a simple way to improve clock frequencies.
9. Example: Reset Tree
   • Description: Demonstrates an advanced technique for distributing a reset with a register tree to reduce maximum reset fanout.
10. Example: Multicycle Path
    • Description: Demonstrates how to use multicycle paths to improve timing.
11. Example: Count
    • Description: Demonstrates how to reduce resources and improve timing for multiple conditional add/sub operations.
12. Example: 3-input Adder (REQUIRES QUARTUS PRIME PRO)
    • Description: Demonstrates how 10-series FPGAs can implement some 3-input adders with the same number of resources as 2-input adders.
13. Example: Add/Sub (REQUIRES QUARTUS PRIME PRO)
    • Description: Demonstrates resource and timing tradeoffs between different adder/subtractor implementations.

DevCloud Instructions