From 4608de3e1a59274efd492c1bd51be27ca8cb1a26 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Teppo=20J=C3=A4rvelin?= Date: Fri, 24 May 2019 13:57:23 +0300 Subject: [PATCH 001/227] Cellular: fix ATHandler destructor possible crash on delete In some multithread cases there is possibility that process_oob function was called after ATHandler was deleted. Fix is to wait if oob processing is ongoing. --- .../AT/at_cellularbase/unittest.cmake | 2 + .../AT/at_cellularcontext/unittest.cmake | 2 + .../AT/at_cellulardevice/unittest.cmake | 2 + .../AT/at_cellularinformation/unittest.cmake | 2 + .../AT/at_cellularnetwork/unittest.cmake | 2 + .../AT/at_cellularsms/unittest.cmake | 3 + .../AT/at_cellularstack/unittest.cmake | 2 + .../framework/AT/athandler/athandlertest.cpp | 2 + .../framework/AT/athandler/unittest.cmake | 8 ++- .../device/cellularcontext/unittest.cmake | 2 + .../device/cellulardevice/unittest.cmake | 2 + .../cellularstatemachine/unittest.cmake | 2 + .../features/lorawan/loramac/unittest.cmake | 5 +- .../lorawan/lorawaninterface/unittest.cmake | 1 + .../lorawan/lorawanstack/unittest.cmake | 2 +- UNITTESTS/stubs/ATHandler_stub.cpp | 3 + UNITTESTS/stubs/ConditionVariable_stub.cpp | 55 +++++++++++++++++++ UNITTESTS/stubs/ConditionVariable_stub.h | 27 +++++++++ UNITTESTS/stubs/mbed_rtos_rtx_stub.c | 20 +++++++ UNITTESTS/stubs/rtx_mutex_stub.c | 28 ++++++++++ UNITTESTS/target_h/cmsis_os2.h | 36 +++++++++++- features/cellular/framework/AT/ATHandler.cpp | 51 ++++++++++++----- features/cellular/framework/AT/ATHandler.h | 21 ++++--- .../cellular/framework/AT/AT_CellularStack.h | 1 + 24 files changed, 254 insertions(+), 27 deletions(-) create mode 100644 UNITTESTS/stubs/ConditionVariable_stub.cpp create mode 100644 UNITTESTS/stubs/ConditionVariable_stub.h create mode 100644 UNITTESTS/stubs/mbed_rtos_rtx_stub.c create mode 100644 UNITTESTS/stubs/rtx_mutex_stub.c diff --git a/UNITTESTS/features/cellular/framework/AT/at_cellularbase/unittest.cmake b/UNITTESTS/features/cellular/framework/AT/at_cellularbase/unittest.cmake index eab77c34ebd..beff24981a9 100644 --- a/UNITTESTS/features/cellular/framework/AT/at_cellularbase/unittest.cmake +++ b/UNITTESTS/features/cellular/framework/AT/at_cellularbase/unittest.cmake @@ -25,4 +25,6 @@ set(unittest-test-sources stubs/ATHandler_stub.cpp stubs/EventQueue_stub.cpp stubs/FileHandle_stub.cpp + stubs/ConditionVariable_stub.cpp + stubs/Mutex_stub.cpp ) diff --git a/UNITTESTS/features/cellular/framework/AT/at_cellularcontext/unittest.cmake b/UNITTESTS/features/cellular/framework/AT/at_cellularcontext/unittest.cmake index dae0f2e2689..15bcccf2318 100644 --- a/UNITTESTS/features/cellular/framework/AT/at_cellularcontext/unittest.cmake +++ b/UNITTESTS/features/cellular/framework/AT/at_cellularcontext/unittest.cmake @@ -42,4 +42,6 @@ set(unittest-test-sources stubs/CellularContext_stub.cpp stubs/CellularUtil_stub.cpp stubs/SocketAddress_stub.cpp + stubs/ConditionVariable_stub.cpp + stubs/Mutex_stub.cpp ) diff --git a/UNITTESTS/features/cellular/framework/AT/at_cellulardevice/unittest.cmake b/UNITTESTS/features/cellular/framework/AT/at_cellulardevice/unittest.cmake index 5a4f1bd3b27..f7ead9eaf2e 100644 --- a/UNITTESTS/features/cellular/framework/AT/at_cellulardevice/unittest.cmake +++ b/UNITTESTS/features/cellular/framework/AT/at_cellulardevice/unittest.cmake @@ -43,6 +43,8 @@ set(unittest-test-sources stubs/SerialBase_stub.cpp stubs/CellularStateMachine_stub.cpp stubs/CellularContext_stub.cpp + stubs/ConditionVariable_stub.cpp + stubs/Mutex_stub.cpp ) # defines diff --git a/UNITTESTS/features/cellular/framework/AT/at_cellularinformation/unittest.cmake b/UNITTESTS/features/cellular/framework/AT/at_cellularinformation/unittest.cmake index 57748f5e83f..c8a646694f6 100644 --- a/UNITTESTS/features/cellular/framework/AT/at_cellularinformation/unittest.cmake +++ b/UNITTESTS/features/cellular/framework/AT/at_cellularinformation/unittest.cmake @@ -25,4 +25,6 @@ set(unittest-test-sources stubs/EventQueue_stub.cpp stubs/FileHandle_stub.cpp stubs/mbed_assert_stub.c + stubs/ConditionVariable_stub.cpp + stubs/Mutex_stub.cpp ) diff --git a/UNITTESTS/features/cellular/framework/AT/at_cellularnetwork/unittest.cmake b/UNITTESTS/features/cellular/framework/AT/at_cellularnetwork/unittest.cmake index b9e4405a281..d2e63302398 100644 --- a/UNITTESTS/features/cellular/framework/AT/at_cellularnetwork/unittest.cmake +++ b/UNITTESTS/features/cellular/framework/AT/at_cellularnetwork/unittest.cmake @@ -28,4 +28,6 @@ set(unittest-test-sources stubs/mbed_assert_stub.c stubs/SocketAddress_stub.cpp stubs/randLIB_stub.cpp + stubs/ConditionVariable_stub.cpp + stubs/Mutex_stub.cpp ) diff --git a/UNITTESTS/features/cellular/framework/AT/at_cellularsms/unittest.cmake b/UNITTESTS/features/cellular/framework/AT/at_cellularsms/unittest.cmake index 484235c8188..c2407a6adf7 100644 --- a/UNITTESTS/features/cellular/framework/AT/at_cellularsms/unittest.cmake +++ b/UNITTESTS/features/cellular/framework/AT/at_cellularsms/unittest.cmake @@ -27,4 +27,7 @@ set(unittest-test-sources stubs/us_ticker_stub.cpp stubs/mbed_assert_stub.c stubs/ThisThread_stub.cpp + stubs/mbed_wait_api_stub.cpp + stubs/ConditionVariable_stub.cpp + stubs/Mutex_stub.cpp ) diff --git a/UNITTESTS/features/cellular/framework/AT/at_cellularstack/unittest.cmake b/UNITTESTS/features/cellular/framework/AT/at_cellularstack/unittest.cmake index f0525045d70..85bd80fd5cb 100644 --- a/UNITTESTS/features/cellular/framework/AT/at_cellularstack/unittest.cmake +++ b/UNITTESTS/features/cellular/framework/AT/at_cellularstack/unittest.cmake @@ -29,4 +29,6 @@ set(unittest-test-sources stubs/SocketAddress_stub.cpp stubs/mbed_assert_stub.c stubs/ThisThread_stub.cpp + stubs/ConditionVariable_stub.cpp + stubs/Mutex_stub.cpp ) diff --git a/UNITTESTS/features/cellular/framework/AT/athandler/athandlertest.cpp b/UNITTESTS/features/cellular/framework/AT/athandler/athandlertest.cpp index 24ef0176620..d168c6a4889 100644 --- a/UNITTESTS/features/cellular/framework/AT/athandler/athandlertest.cpp +++ b/UNITTESTS/features/cellular/framework/AT/athandler/athandlertest.cpp @@ -51,6 +51,7 @@ class TestATHandler : public testing::Test { urc_callback_count = 0; CellularUtil_stub::char_ptr = NULL; CellularUtil_stub::char_pos = 0; + filehandle_stub_short_value_counter = 0; } void TearDown() @@ -352,6 +353,7 @@ TEST_F(TestATHandler, test_ATHandler_cmd_start) { EventQueue que; FileHandle_stub fh1; + fh1.short_value = 0; ATHandler at(&fh1, que, 0, ","); mbed_poll_stub::revents_value = POLLOUT; diff --git a/UNITTESTS/features/cellular/framework/AT/athandler/unittest.cmake b/UNITTESTS/features/cellular/framework/AT/athandler/unittest.cmake index b3e55b52605..84e2ce1b4ca 100644 --- a/UNITTESTS/features/cellular/framework/AT/athandler/unittest.cmake +++ b/UNITTESTS/features/cellular/framework/AT/athandler/unittest.cmake @@ -5,10 +5,12 @@ # Add test specific include paths set(unittest-includes ${unittest-includes} - features/cellular/framework/common/util + ../platform + ../features/cellular/framework/common/util ../features/cellular/framework/common ../features/cellular/framework/AT ../features/frameworks/mbed-client-randlib/mbed-client-randlib + ) # Source files @@ -31,6 +33,10 @@ set(unittest-test-sources stubs/ThisThread_stub.cpp stubs/randLIB_stub.cpp stubs/CellularUtil_stub.cpp + stubs/ConditionVariable_stub.cpp + stubs/Mutex_stub.cpp + stubs/mbed_rtos_rtx_stub.c + stubs/rtx_mutex_stub.c ) set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -DMBED_CONF_CELLULAR_DEBUG_AT=true -DOS_STACK_SIZE=2048") diff --git a/UNITTESTS/features/cellular/framework/device/cellularcontext/unittest.cmake b/UNITTESTS/features/cellular/framework/device/cellularcontext/unittest.cmake index b85f32586eb..fe3072e288f 100644 --- a/UNITTESTS/features/cellular/framework/device/cellularcontext/unittest.cmake +++ b/UNITTESTS/features/cellular/framework/device/cellularcontext/unittest.cmake @@ -35,6 +35,8 @@ set(unittest-test-sources stubs/CellularDevice_stub.cpp stubs/equeue_stub.c stubs/ThisThread_stub.cpp + stubs/ConditionVariable_stub.cpp + stubs/Mutex_stub.cpp ) # defines diff --git a/UNITTESTS/features/cellular/framework/device/cellulardevice/unittest.cmake b/UNITTESTS/features/cellular/framework/device/cellulardevice/unittest.cmake index fc7ce7ac3d6..c6e4ae37679 100644 --- a/UNITTESTS/features/cellular/framework/device/cellulardevice/unittest.cmake +++ b/UNITTESTS/features/cellular/framework/device/cellulardevice/unittest.cmake @@ -33,6 +33,8 @@ set(unittest-test-sources stubs/NetworkInterface_stub.cpp stubs/NetworkInterfaceDefaults_stub.cpp stubs/CellularContext_stub.cpp + stubs/ConditionVariable_stub.cpp + stubs/Mutex_stub.cpp ) # defines diff --git a/UNITTESTS/features/cellular/framework/device/cellularstatemachine/unittest.cmake b/UNITTESTS/features/cellular/framework/device/cellularstatemachine/unittest.cmake index 09603bdedce..c248fcee893 100644 --- a/UNITTESTS/features/cellular/framework/device/cellularstatemachine/unittest.cmake +++ b/UNITTESTS/features/cellular/framework/device/cellularstatemachine/unittest.cmake @@ -38,6 +38,8 @@ set(unittest-test-sources stubs/EventQueue_stub.cpp stubs/equeue_stub.c stubs/CellularContext_stub.cpp + stubs/ConditionVariable_stub.cpp + stubs/Mutex_stub.cpp ) # defines diff --git a/UNITTESTS/features/lorawan/loramac/unittest.cmake b/UNITTESTS/features/lorawan/loramac/unittest.cmake index aff97c04121..24ba9182721 100644 --- a/UNITTESTS/features/lorawan/loramac/unittest.cmake +++ b/UNITTESTS/features/lorawan/loramac/unittest.cmake @@ -40,10 +40,13 @@ set(unittest-test-sources stubs/LoRaWANTimer_stub.cpp stubs/LoRaMacCommand_stub.cpp stubs/EventQueue_stub.cpp - + stubs/Mutex_stub.cpp ) # defines +#set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -DMBED_CONF_RTOS_PRESENT=1") +#set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -DMBED_CONF_RTOS_PRESENT=1") + set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -DMBED_CONF_LORA_ADR_ON=true -DMBED_CONF_LORA_PUBLIC_NETWORK=true -DMBED_CONF_LORA_NB_TRIALS=2 -DMBED_CONF_LORA_DOWNLINK_PREAMBLE_LENGTH=5") set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -DMBED_CONF_LORA_ADR_ON=true -DMBED_CONF_LORA_PUBLIC_NETWORK=true -DMBED_CONF_LORA_NB_TRIALS=2 -DMBED_CONF_LORA_DOWNLINK_PREAMBLE_LENGTH=5") diff --git a/UNITTESTS/features/lorawan/lorawaninterface/unittest.cmake b/UNITTESTS/features/lorawan/lorawaninterface/unittest.cmake index 9e123a1c5e0..f99ccca9baa 100644 --- a/UNITTESTS/features/lorawan/lorawaninterface/unittest.cmake +++ b/UNITTESTS/features/lorawan/lorawaninterface/unittest.cmake @@ -41,6 +41,7 @@ set(unittest-test-sources stubs/LoRaWANTimer_stub.cpp stubs/LoRaMacCommand_stub.cpp stubs/LoRaPHYEU868_stub.cpp + stubs/Mutex_stub.cpp ) # defines diff --git a/UNITTESTS/features/lorawan/lorawanstack/unittest.cmake b/UNITTESTS/features/lorawan/lorawanstack/unittest.cmake index 3b6c2b1d28c..b8b506c044b 100644 --- a/UNITTESTS/features/lorawan/lorawanstack/unittest.cmake +++ b/UNITTESTS/features/lorawan/lorawanstack/unittest.cmake @@ -42,7 +42,7 @@ set(unittest-test-sources stubs/LoRaMacCommand_stub.cpp stubs/EventQueue_stub.cpp stubs/equeue_stub.c - + stubs/Mutex_stub.cpp ) # defines diff --git a/UNITTESTS/stubs/ATHandler_stub.cpp b/UNITTESTS/stubs/ATHandler_stub.cpp index 003a97dc47c..f614cf87884 100644 --- a/UNITTESTS/stubs/ATHandler_stub.cpp +++ b/UNITTESTS/stubs/ATHandler_stub.cpp @@ -83,6 +83,9 @@ void ATHandler_stub::debug_call_count_clear() ATHandler::ATHandler(FileHandle *fh, EventQueue &queue, uint32_t timeout, const char *output_delimiter, uint16_t send_delay) : _nextATHandler(0), +#if defined AT_HANDLER_MUTEX && defined MBED_CONF_RTOS_PRESENT + _oobCv(_fileHandleMutex), +#endif _fileHandle(fh), _queue(queue), _ref_count(1), diff --git a/UNITTESTS/stubs/ConditionVariable_stub.cpp b/UNITTESTS/stubs/ConditionVariable_stub.cpp new file mode 100644 index 00000000000..ee734abc3e6 --- /dev/null +++ b/UNITTESTS/stubs/ConditionVariable_stub.cpp @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2019, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_OS_UNITTESTS_STUBS_CONDITIONVARIABLE_STUB_CPP_ +#define MBED_OS_UNITTESTS_STUBS_CONDITIONVARIABLE_STUB_CPP_ + +#include "ConditionVariable_stub.h" +#include "mbed_error.h" +#include "mbed_assert.h" + +bool ConditionVariable_stub::time_out = false; +#ifdef MBED_CONF_RTOS_PRESENT +using namespace rtos; + +ConditionVariable::ConditionVariable(Mutex &mutex): _mutex(mutex), _wait_list(0) +{ + // No initialization to do +} + +ConditionVariable::~ConditionVariable() +{ +} + +void ConditionVariable::notify_one() +{ + +} + +void ConditionVariable::wait() +{ +} + +bool ConditionVariable::wait_for(uint32_t millisec) +{ + return ConditionVariable_stub::time_out; +} + +void ConditionVariable::notify_all() +{ +} +#endif +#endif /* MBED_OS_UNITTESTS_STUBS_CONDITIONVARIABLE_STUB_CPP_ */ diff --git a/UNITTESTS/stubs/ConditionVariable_stub.h b/UNITTESTS/stubs/ConditionVariable_stub.h new file mode 100644 index 00000000000..ddb7197d201 --- /dev/null +++ b/UNITTESTS/stubs/ConditionVariable_stub.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2019, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_OS_UNITTESTS_STUBS_CONDITIONVARIABLE_STUB_H_ +#define MBED_OS_UNITTESTS_STUBS_CONDITIONVARIABLE_STUB_H_ + +#include "rtos/ConditionVariable.h" + +namespace ConditionVariable_stub { +extern bool time_out; +} + + +#endif /* MBED_OS_UNITTESTS_STUBS_CONDITIONVARIABLE_STUB_H_ */ diff --git a/UNITTESTS/stubs/mbed_rtos_rtx_stub.c b/UNITTESTS/stubs/mbed_rtos_rtx_stub.c new file mode 100644 index 00000000000..aa45009fa51 --- /dev/null +++ b/UNITTESTS/stubs/mbed_rtos_rtx_stub.c @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2019, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "cmsis_os2.h" + +osMutexId_t singleton_mutex_id; diff --git a/UNITTESTS/stubs/rtx_mutex_stub.c b/UNITTESTS/stubs/rtx_mutex_stub.c new file mode 100644 index 00000000000..de5aed92bd1 --- /dev/null +++ b/UNITTESTS/stubs/rtx_mutex_stub.c @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2019, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "cmsis_os2.h" + +osStatus_t osMutexAcquire(osMutexId_t mutex_id, uint32_t timeout) +{ + return osOK; +} + +osStatus_t osMutexRelease(osMutexId_t mutex_id) +{ + return osOK; +} diff --git a/UNITTESTS/target_h/cmsis_os2.h b/UNITTESTS/target_h/cmsis_os2.h index 66b1d2f061c..bb05b7dc99e 100644 --- a/UNITTESTS/target_h/cmsis_os2.h +++ b/UNITTESTS/target_h/cmsis_os2.h @@ -18,14 +18,16 @@ #ifndef __CMSIS_OS2_H__ #define __CMSIS_OS2_H__ +#ifdef __cplusplus +extern "C" +{ +#endif + #include //If conflicts, then remove these, copied from cmsis_os.h typedef int32_t osStatus; -#define osOK 0 -#define osErrorNoMemory -5 - //These are from cmsis_os2.h typedef void *osSemaphoreId_t; @@ -37,6 +39,18 @@ typedef struct { uint32_t cb_size; ///< size of provided memory for control block } osSemaphoreAttr_t; +/// Status code values returned by CMSIS-RTOS functions. +typedef enum { + osOK = 0, ///< Operation completed successfully. + osError = -1, ///< Unspecified RTOS error: run-time error but no other error message fits. + osErrorTimeout = -2, ///< Operation not completed within the timeout period. + osErrorResource = -3, ///< Resource not available. + osErrorParameter = -4, ///< Parameter error. + osErrorNoMemory = -5, ///< System is out of memory: it was impossible to allocate or reserve memory for the operation. + osErrorISR = -6, ///< Not allowed in ISR context: the function cannot be called from interrupt service routines. + osStatusReserved = 0x7FFFFFFF ///< Prevents enum down-size compiler optimization. +} osStatus_t; + //Thread typedef enum { osPriorityNormal = 24 ///< Priority: normal @@ -44,6 +58,8 @@ typedef enum { typedef void *osThreadId_t; +typedef void *osMutexId_t; + typedef void *osEventFlagsId_t; /// Attributes structure for thread. @@ -74,5 +90,19 @@ typedef struct { #define osMutexPrioInherit 0x00000002U ///< Priority inherit protocol. #define osMutexRobust 0x00000008U ///< Robust mutex. +/// Acquire a Mutex or timeout if it is locked. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \param[in] timeout \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +osStatus_t osMutexAcquire(osMutexId_t mutex_id, uint32_t timeout); + +/// Release a Mutex that was acquired by \ref osMutexAcquire. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexNew. +/// \return status code that indicates the execution status of the function. +osStatus_t osMutexRelease(osMutexId_t mutex_id); + +#ifdef __cplusplus +} +#endif #endif diff --git a/features/cellular/framework/AT/ATHandler.cpp b/features/cellular/framework/AT/ATHandler.cpp index d464e634f99..88334167edc 100644 --- a/features/cellular/framework/AT/ATHandler.cpp +++ b/features/cellular/framework/AT/ATHandler.cpp @@ -26,6 +26,7 @@ #include "Kernel.h" #include "CellularUtil.h" #include "SingletonPtr.h" +#include "ScopedLock.h" using namespace mbed; using namespace events; @@ -161,6 +162,9 @@ bool ATHandler::ok_to_proceed() ATHandler::ATHandler(FileHandle *fh, EventQueue &queue, uint32_t timeout, const char *output_delimiter, uint16_t send_delay) : _nextATHandler(0), +#if defined AT_HANDLER_MUTEX && defined MBED_CONF_RTOS_PRESENT + _oobCv(_fileHandleMutex), +#endif _fileHandle(NULL), // filehandle is set by set_file_handle() _queue(queue), _last_err(NSAPI_ERROR_OK), @@ -171,7 +175,6 @@ ATHandler::ATHandler(FileHandle *fh, EventQueue &queue, uint32_t timeout, const _previous_at_timeout(timeout), _at_send_delay(send_delay), _last_response_stop(0), - _oob_queued(false), _ref_count(1), _is_fh_usable(false), _stop_tag(NULL), @@ -183,7 +186,8 @@ ATHandler::ATHandler(FileHandle *fh, EventQueue &queue, uint32_t timeout, const _debug_on(MBED_CONF_CELLULAR_DEBUG_AT), _cmd_start(false), _use_delimiter(true), - _start_time(0) + _start_time(0), + _event_id(0) { clear_error(); @@ -218,8 +222,22 @@ bool ATHandler::get_debug() const ATHandler::~ATHandler() { + ScopedLock lock(*this); set_file_handle(NULL); + if (_event_id != 0 && _queue.cancel(_event_id)) { + _event_id = 0; + } + + while (_event_id != 0) { +#if defined AT_HANDLER_MUTEX && defined MBED_CONF_RTOS_PRESENT + _oobCv.wait(); +#else + // Cancel will always work in a single threaded environment + MBED_ASSERT(false); +#endif // AT_HANDLER_MUTEX + } + while (_oobs) { struct oob_t *oob = _oobs; _oobs = oob->next; @@ -252,6 +270,7 @@ FileHandle *ATHandler::get_file_handle() void ATHandler::set_file_handle(FileHandle *fh) { + ScopedLock lock(*this); if (_fileHandle) { set_is_filehandle_usable(false); } @@ -263,6 +282,7 @@ void ATHandler::set_file_handle(FileHandle *fh) void ATHandler::set_is_filehandle_usable(bool usable) { + ScopedLock lock(*this); if (_fileHandle) { if (usable) { _fileHandle->set_blocking(false); @@ -337,15 +357,14 @@ bool ATHandler::find_urc_handler(const char *prefix) void ATHandler::event() { - if (!_oob_queued) { - _oob_queued = true; - (void) _queue.call(Callback(this, &ATHandler::process_oob)); + if (_event_id == 0) { + _event_id = _queue.call(callback(this, &ATHandler::process_oob)); } } void ATHandler::lock() { -#ifdef AT_HANDLER_MUTEX +#if defined AT_HANDLER_MUTEX && defined MBED_CONF_RTOS_PRESENT _fileHandleMutex.lock(); #endif clear_error(); @@ -354,12 +373,12 @@ void ATHandler::lock() void ATHandler::unlock() { -#ifdef AT_HANDLER_MUTEX + if (_is_fh_usable && (_fileHandle->readable() || (_recv_pos < _recv_len))) { + _event_id = _queue.call(callback(this, &ATHandler::process_oob)); + } +#if defined AT_HANDLER_MUTEX && defined MBED_CONF_RTOS_PRESENT _fileHandleMutex.unlock(); #endif - if (_fileHandle->readable() || (_recv_pos < _recv_len)) { - (void) _queue.call(Callback(this, &ATHandler::process_oob)); - } } nsapi_error_t ATHandler::unlock_return_error() @@ -393,12 +412,15 @@ void ATHandler::restore_at_timeout() void ATHandler::process_oob() { + ScopedLock lock(*this); if (!_is_fh_usable) { tr_debug("process_oob, filehandle is not usable, return..."); + _event_id = 0; +#if defined AT_HANDLER_MUTEX && defined MBED_CONF_RTOS_PRESENT + _oobCv.notify_all(); +#endif return; } - lock(); - _oob_queued = false; if (_fileHandle->readable() || (_recv_pos < _recv_len)) { tr_debug("AT OoB readable %d, len %u", _fileHandle->readable(), _recv_len - _recv_pos); _current_scope = NotSet; @@ -424,7 +446,10 @@ void ATHandler::process_oob() _at_timeout = timeout; tr_debug("AT OoB done"); } - unlock(); + _event_id = 0; +#if defined AT_HANDLER_MUTEX && defined MBED_CONF_RTOS_PRESENT + _oobCv.notify_all(); +#endif } void ATHandler::reset_buffer() diff --git a/features/cellular/framework/AT/ATHandler.h b/features/cellular/framework/AT/ATHandler.h index ce763de93a6..5a1352ca247 100644 --- a/features/cellular/framework/AT/ATHandler.h +++ b/features/cellular/framework/AT/ATHandler.h @@ -21,17 +21,12 @@ #include "platform/mbed_retarget.h" #include "events/EventQueue.h" -#include "PlatformMutex.h" #include "nsapi_types.h" #include "Callback.h" #include -namespace mbed { - -class FileHandle; - /** * If application calls associated FileHandle only from single thread context * then locking between AT command and response is not needed. However, @@ -40,6 +35,14 @@ class FileHandle; */ #define AT_HANDLER_MUTEX +#if defined AT_HANDLER_MUTEX && defined MBED_CONF_RTOS_PRESENT +#include "ConditionVariable.h" +#endif + +namespace mbed { + +class FileHandle; + extern const char *OK; extern const char *CRLF; @@ -218,8 +221,9 @@ class ATHandler { protected: void event(); -#ifdef AT_HANDLER_MUTEX - PlatformMutex _fileHandleMutex; +#if defined AT_HANDLER_MUTEX && defined MBED_CONF_RTOS_PRESENT + rtos::Mutex _fileHandleMutex; + rtos::ConditionVariable _oobCv; #endif FileHandle *_fileHandle; private: @@ -251,7 +255,6 @@ class ATHandler { uint16_t _at_send_delay; uint64_t _last_response_stop; - bool _oob_queued; int32_t _ref_count; bool _is_fh_usable; @@ -550,6 +553,8 @@ class ATHandler { // time when a command or an URC processing was started uint64_t _start_time; + // eventqueue event id + int _event_id; char _cmd_buffer[BUFF_SIZE]; diff --git a/features/cellular/framework/AT/AT_CellularStack.h b/features/cellular/framework/AT/AT_CellularStack.h index fd9adf28ac8..afa28f90c6b 100644 --- a/features/cellular/framework/AT/AT_CellularStack.h +++ b/features/cellular/framework/AT/AT_CellularStack.h @@ -20,6 +20,7 @@ #include "AT_CellularBase.h" #include "NetworkStack.h" +#include "PlatformMutex.h" namespace mbed { From 34a54c1b2ed0aff0624b3f5ce9bab9a9d0d9b431 Mon Sep 17 00:00:00 2001 From: Hugues Kamba Date: Fri, 23 Aug 2019 15:26:07 +0100 Subject: [PATCH 002/227] Add executable analaysis tool for floating point checks. --- .../elf-float-checker.py | 168 ++++++++++++++++++ .../test_elf-float-checker.py | 120 +++++++++++++ 2 files changed, 288 insertions(+) create mode 100644 tools/executable_analysis_tools/elf-float-checker.py create mode 100644 tools/executable_analysis_tools/test_elf-float-checker.py diff --git a/tools/executable_analysis_tools/elf-float-checker.py b/tools/executable_analysis_tools/elf-float-checker.py new file mode 100644 index 00000000000..c1185a78204 --- /dev/null +++ b/tools/executable_analysis_tools/elf-float-checker.py @@ -0,0 +1,168 @@ +#!/usr/bin/env python3 +# Copyright (c) 2019 Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: Apache-2.0 + +"""Script for checking for floating point symbols in ELF files.""" + +import argparse +import logging +import re +import subprocess +import sys + +log = logging.getLogger(__name__) + +LOG_FORMAT = "%(asctime)s - %(levelname)s - %(message)s" +FLOATING_POINT_SYMBOL_REGEX = r"__aeabi_(cd.+|cf.+|h2f.+|d.+|f.+|.+2d|.+2f)" +OBJECT_FILE_ANALYSIS_CMD = ["objdump", "-t"] + +class SymbolParser: + """Parse the given ELF format file.""" + + def get_symbols_from_table(self, symbol_table, symbol_regex): + """Get symbols matching a regular expression pattern from a table.""" + pattern = re.compile(symbol_regex, re.X) + matched_symbols = [] + symbol_table_lines = symbol_table.split("\n") + for symbol_table_line in symbol_table_lines: + match = pattern.search(symbol_table_line) + if match: + log.debug("Symbol line: {}".format(symbol_table_line)) + log.debug("Match found: {}".format(match)) + matched_symbols.append(match.group(0)) + + log.debug("Symbols found:\n'{}'".format(matched_symbols)) + return matched_symbols + + def get_symbol_table(self, elf_file): + """Get the symbol table from an ELF format file.""" + log.debug( + "Get the symbol table for ELF format file '{}'".format(elf_file) + ) + + cmd = [*OBJECT_FILE_ANALYSIS_CMD, elf_file] + log.debug("command: '{}'".format(cmd)) + try: + process = subprocess.run( + cmd, + check=True, + stdin=None, + stdout=subprocess.PIPE, + stderr=subprocess.STDOUT, + ) + except subprocess.CalledProcessError as error: + err_output = error.stdout.decode() + msg = ( + "Getting symbol table for ELF format file '{}' failed," + " error: {}".format(elf_file, err_output) + ) + raise SymbolTableError(msg) + + symbol_table = process.stdout.decode() + log.debug("Symbol table:\n{}\n".format(symbol_table)) + + return symbol_table + + +class SymbolTableError(Exception): + """An exception for a failure to obtain a symbol table.""" + + +class ArgumentParserWithDefaultHelp(argparse.ArgumentParser): + """Subclass that always shows the help message on invalid arguments.""" + + def error(self, message): + """Error handler.""" + sys.stderr.write("error: {}\n".format(message)) + self.print_help() + + +def set_log_verbosity(increase_verbosity): + """Set the verbosity of the log output.""" + log_level = logging.DEBUG if increase_verbosity else logging.INFO + + log.setLevel(log_level) + logging.basicConfig(level=log_level, format=LOG_FORMAT) + + +def check_float_symbols(elf_file): + """Check for floating point symbols in ELF format file. + + Return the floating point symbols found. + """ + parser = SymbolParser() + symbol_table = parser.get_symbol_table(elf_file) + + float_symbols = parser.get_symbols_from_table( + symbol_table, FLOATING_POINT_SYMBOL_REGEX + ) + + return float_symbols + + +def check_action(args): + """Entry point for checking the ELF file.""" + float_symbols = check_float_symbols(args.elf_file) + if float_symbols: + print("Found float symbols:") + for float_symbol in float_symbols: + print(float_symbol) + else: + print("No float symbols found.") + + +def parse_args(): + """Parse the command line args.""" + parser = ArgumentParserWithDefaultHelp( + description="ELF floats checker", + formatter_class=argparse.ArgumentDefaultsHelpFormatter, + ) + + parser.add_argument( + "elf_file", + type=str, + help=( + "the Executable and Linkable Format (ELF) file to check" + " for floating point instruction inclusion." + ), + ) + + parser.add_argument( + "-v", + "--verbose", + action="store_true", + help="increase verbosity of status information.", + ) + + parser.set_defaults(func=check_action) + + args_namespace = parser.parse_args() + + # We want to fail gracefully, with a consistent + # help message, in the no argument case. + # So here's an obligatory hasattr hack. + if not hasattr(args_namespace, "func"): + parser.error("No arguments given!") + else: + return args_namespace + + +def run_elf_floats_checker(): + """Application main algorithm.""" + args = parse_args() + + set_log_verbosity(args.verbose) + + log.debug("Starting elf-floats-checker") + log.debug("Command line arguments:{}".format(args)) + + args.func(args) + + +if __name__ == "__main__": + """Run elf-floats-checker.""" + try: + run_elf_floats_checker() + except Exception as error: + print(error) diff --git a/tools/executable_analysis_tools/test_elf-float-checker.py b/tools/executable_analysis_tools/test_elf-float-checker.py new file mode 100644 index 00000000000..224dbb2296e --- /dev/null +++ b/tools/executable_analysis_tools/test_elf-float-checker.py @@ -0,0 +1,120 @@ +#!/usr/bin/env python3 +# Copyright (c) 2019 Arm Limited and Contributors. All rights reserved. +# +# SPDX-License-Identifier: Apache-2.0 + +"""Pytest for testing elf-float-checker.""" + +import importlib +import mock +import subprocess +from pathlib import Path + + +TARGET = importlib.import_module("elf-float-checker") + +SYMBOL_TABLE_WITHOUT_FLOATS = ( + " Symbol table '.symtab' contains 2723 entries:\n" + "Num: Value Size Type Bind Vis Ndx Name\n" + " 0: 00000000 0 NOTYPE LOCAL DEFAULT UND \n" + " 1: 000045fd 16 FUNC GLOBAL HIDDEN 3 lp_ticker_clear_interrupt\n" + " 2: 00004609 16 FUNC GLOBAL HIDDEN 3 __aeabi_uwrite4\n" + " 3: 00004615 16 FUNC GLOBAL HIDDEN 3 lp_ticker_fire_interrupt\n" + " 4: 00004625 36 FUNC GLOBAL HIDDEN 3 lp_ticker_free\n" + " 5: 00004645 8 FUNC GLOBAL HIDDEN 3 lp_ticker_get_info\n" + " 6: 0000464d 116 FUNC GLOBAL HIDDEN 3 __aeabi_lasr\n" + " 7: 000046bd 20 FUNC GLOBAL HIDDEN 3 lp_ticker_irq_handler\n" + " 8: 000046d1 16 FUNC GLOBAL HIDDEN 3 lp_ticker_read\n" + " 9: 000046e1 52 FUNC GLOBAL HIDDEN 3 __aeabi_lmul\n" +) + +FLOAT_SYMBOLS = [ + "__aeabi_cdcmpeq", + "__aeabi_cfcmpeq", + "__aeabi_f2iz", + "__aeabi_h2f_alt", + "__aeabi_i2d", + "__aeabi_d2iz", + "__aeabi_i2f", +] + +SYMBOL_TABLE_WITH_FLOATS = ( + " Symbol table '.symtab' contains 2723 entries:\n" + "Num: Value Size Type Bind Vis Ndx Name\n" + f" 0: 00000000 0 NOTYPE LOCAL DEFAULT UND \n" + f" 1: 000045fd 16 FUNC GLOBAL HIDDEN 3 {FLOAT_SYMBOLS[0]}\n" + f" 2: 00004609 16 FUNC GLOBAL HIDDEN 3 lp_ticker_disable_interrupt\n" + f" 3: 00004615 16 FUNC GLOBAL HIDDEN 3 {FLOAT_SYMBOLS[1]}\n" + f" 4: 00004625 36 FUNC GLOBAL HIDDEN 3 {FLOAT_SYMBOLS[2]}\n" + f" 5: 00004645 8 FUNC GLOBAL HIDDEN 3 lp_ticker_get_info\n" + f" 6: 0000464d 116 FUNC GLOBAL HIDDEN 3 {FLOAT_SYMBOLS[3]}\n" + f" 7: 000046bd 20 FUNC GLOBAL HIDDEN 3 lp_ticker_irq_handler\n" + f" 8: 000046d1 16 FUNC GLOBAL HIDDEN 3 {FLOAT_SYMBOLS[4]}\n" + f" 9: 000046e1 52 FUNC GLOBAL HIDDEN 3 {FLOAT_SYMBOLS[5]}\n" + f" 10: 000046f1 52 FUNC GLOBAL HIDDEN 3 {FLOAT_SYMBOLS[6]}\n" +) + + +ELF_FORMAT_FILE = "mbed-os-example.elf" +OBJECT_FILE_ANALYSIS_CMD = [*(TARGET.OBJECT_FILE_ANALYSIS_CMD), f"{ELF_FORMAT_FILE}"] + +class TestElfFloatChecker: + """Test class""" + + @classmethod + def setup_class(cls): + # Create a dummy ELF format file + Path(ELF_FORMAT_FILE).touch() + + @classmethod + def teardown_class(cls): + # Remove the dummy ELF format file + Path(ELF_FORMAT_FILE).unlink() + + @mock.patch("subprocess.run") + def test_correctly_detect_absence_of_float_symbols( + self, mock_subprocess_run + ): + """Test that no false positive occur.""" + mock_subprocess_run.return_value = subprocess.CompletedProcess( + args=( + f"{OBJECT_FILE_ANALYSIS_CMD}" + " check=True, stderr=-2, stdin=None, stdout=-1" + ), + returncode=0, + stdout=SYMBOL_TABLE_WITHOUT_FLOATS.encode(), + stderr=None, + ) + assert [] == TARGET.check_float_symbols(ELF_FORMAT_FILE) + mock_subprocess_run.assert_called_with( + OBJECT_FILE_ANALYSIS_CMD, + check=True, + stdin=None, + stdout=subprocess.PIPE, + stderr=subprocess.STDOUT, + ) + + @mock.patch("subprocess.run") + def test_correctly_detect_presence_of_float_symbols( + self, mock_subprocess_run + ): + """Test that float symbols can be discovered in a symbol table.""" + mock_subprocess_run.return_value = subprocess.CompletedProcess( + args=( + f"{OBJECT_FILE_ANALYSIS_CMD}" + " check=True, stderr=-2, stdin=None, stdout=-1" + ), + returncode=0, + stdout=SYMBOL_TABLE_WITH_FLOATS.encode(), + stderr=None, + ) + assert FLOAT_SYMBOLS == TARGET.check_float_symbols( + ELF_FORMAT_FILE + ) + mock_subprocess_run.assert_called_with( + OBJECT_FILE_ANALYSIS_CMD, + check=True, + stdin=None, + stdout=subprocess.PIPE, + stderr=subprocess.STDOUT, + ) From 1c015bc54ac73cbb09025526f64e29b996f24032 Mon Sep 17 00:00:00 2001 From: Tony Wu Date: Fri, 16 Aug 2019 13:45:10 +0800 Subject: [PATCH 003/227] rtl8195am - enable USTICKER support Signed-off-by: Tony Wu --- targets/targets.json | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/targets/targets.json b/targets/targets.json index 058e9aacac9..f2cba1e1f9b 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -8059,7 +8059,8 @@ "SERIAL", "SPI", "TRNG", - "FLASH" + "FLASH", + "USTICKER" ], "public": false, "supported_toolchains": ["GCC_ARM", "ARM"], From 6b0275f9bbd06c38f3b198dcd328d00c55e17cc2 Mon Sep 17 00:00:00 2001 From: Tony Wu Date: Fri, 16 Aug 2019 13:48:10 +0800 Subject: [PATCH 004/227] rtl8195am - disable IAR support Disable IAR support until HAL library is upgraded to IAR8 Signed-off-by: Tony Wu --- targets/targets.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/targets.json b/targets/targets.json index f2cba1e1f9b..bc448b71e89 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -8066,7 +8066,7 @@ "supported_toolchains": ["GCC_ARM", "ARM"], "post_binary_hook": { "function": "RTL8195ACode.binary_hook", - "toolchains": ["ARM_STD", "GCC_ARM", "IAR"] + "toolchains": ["ARM_STD", "GCC_ARM"] }, "release_versions": [], "overrides": { From 82c5e24d8fd5d14e15df227d2c05283c87629619 Mon Sep 17 00:00:00 2001 From: Tony Wu Date: Fri, 23 Aug 2019 15:09:51 +0800 Subject: [PATCH 005/227] rtl8195am - cleanup gcc linker script Signed-off-by: Tony Wu --- .../device/TOOLCHAIN_GCC_ARM/rtl8195a.ld | 25 +++++++++---------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_GCC_ARM/rtl8195a.ld b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_GCC_ARM/rtl8195a.ld index 9b21748ec0b..01d4ce1969c 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_GCC_ARM/rtl8195a.ld +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/device/TOOLCHAIN_GCC_ARM/rtl8195a.ld @@ -107,20 +107,20 @@ SECTIONS } > SRAM2 __etext = .; - __data_start__ = .; - .data.sram1 : { - . = ALIGN(8); + . = ALIGN(4); + __data_start__ = .; __sram_data_start__ = .; *rtl8195a_crypto*.o (.data*) *mbedtls*.o (.data*) + __data_end__ = .; __sram_data_end__ = .; } > SRAM1 .data.sram2 : { - __sdram_data_start__ = .; + __dram_data_start__ = .; *(vtable) *(.data*) *(.sdram.data*) @@ -145,12 +145,8 @@ SECTIONS KEEP(*(.fini_array)) PROVIDE (__fini_array_end = .); - . = ALIGN(8); - - __sdram_data_end__ = .; - /* All data end */ + __dram_data_end__ = .; } > SRAM2 - __data_end__ = .; __image2_end__ = .; .ARM.extab : @@ -167,6 +163,7 @@ SECTIONS .bss.sram1 (NOLOAD) : { + __bss_start__ = .; __bss_sram_start__ = .; *rtl8195a_crypto*.o (.bss* COMMON) *mbedtls*.o (.bss* COMMON) @@ -174,17 +171,16 @@ SECTIONS *lib_peripheral_mbed_gcc.a: (.bss* COMMON) *mbed_boot*.o (.bss* COMMON) __bss_sram_end__ = .; + __bss_end__ = .; } > SRAM1 .bss.sram2 (NOLOAD) : { - __bss_start__ = .; __bss_dram_start__ = .; *(.bss*) *(COMMON) *(.bdsram.data*) __bss_dram_end__ = .; - __bss_end__ = .; } > SRAM2 .bf_data : @@ -199,7 +195,7 @@ SECTIONS __end__ = .; end = __end__; *(.heap*) - . = ORIGIN(SRAM1) + LENGTH(SRAM1) - StackSize; + . = ORIGIN(SRAM1) + LENGTH(SRAM1) - StackSize; __HeapLimit = .; } > SRAM1 @@ -219,7 +215,7 @@ SECTIONS { __StackLimit = .; *(.stack) - . += StackSize - (. - __StackLimit); + . += StackSize - (. - __StackLimit); } > SRAM1 /* Set stack top to end of RAM, and stack limit move down by @@ -228,6 +224,9 @@ SECTIONS __StackLimit = __StackTop - StackSize; PROVIDE(__stack = __StackTop); + /* Check if reserved stack size is too small */ + ASSERT(StackSize >= SIZEOF(.stack_dummy), "reserved stack size is too small") + /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM exceeds ram limit") } From a168aabdd0d0db7718b9ff73f7b34000e1fcc2ec Mon Sep 17 00:00:00 2001 From: Tony Wu Date: Fri, 23 Aug 2019 15:39:49 +0800 Subject: [PATCH 006/227] rtl8195am - fix missing braces around empty body warning osdep_service.c@214,61: suggest braces around empty body in an 'else' statement [-Wempty-body] Signed-off-by: Tony Wu --- .../TARGET_AMEBA/sdk/os/os_dep/osdep_service.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/os_dep/osdep_service.c b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/os_dep/osdep_service.c index 37bfc9821a1..543b55524ab 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/os_dep/osdep_service.c +++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/os_dep/osdep_service.c @@ -208,10 +208,11 @@ void add_mem_usage(_list *pmem_table, void *ptr, int size, int *used_num, int fl return; } else{ - if(flag == MEM_MONITOR_FLAG_WPAS) + if(flag == MEM_MONITOR_FLAG_WPAS) { DBG_INFO("Alloc memory at %p with size of %d", ptr, size); - else + } else { DBG_INFO("Alloc memory at %p with size of %d", ptr, size); + } } #if CONFIG_MEM_MONITOR & MEM_MONITOR_LEAK mem_entry = (struct mem_entry *) _rtw_malloc(sizeof(struct mem_entry)); From 3345548adc64383f77c2e4304ea17df83de94ca1 Mon Sep 17 00:00:00 2001 From: Tony Wu Date: Fri, 23 Aug 2019 15:45:34 +0800 Subject: [PATCH 007/227] rtl8195am - fix argument format warning [Warning] tcm_heap.c@70,18: format '%x' expects argument of type 'unsigned int', but argument 2 has type 'MemChunk * {aka struct _MemChunk *}' [-Wformat=] [Warning] tcm_heap.c@70,28: format '%x' expects argument of type 'unsigned int', but argument 3 has type 'MemChunk * {aka struct _MemChunk *}' [-Wformat=] Signed-off-by: Tony Wu --- targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/os_dep/tcm_heap.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/os_dep/tcm_heap.c b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/os_dep/tcm_heap.c index 203a83039b9..db4ed916387 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/os_dep/tcm_heap.c +++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/os_dep/tcm_heap.c @@ -67,7 +67,7 @@ void tcm_heap_dump(void) chunk; prev = chunk, chunk = chunk->next) { - printf(" prev %x, chunk %x, size %d \n\r", prev, chunk, chunk->size); + printf(" prev %p, chunk %p, size %d \n\r", prev, chunk, chunk->size); } printf("--------------\n\r"); } From 5ae55c26d105ddf8a31b3beb54e21073f88fd809 Mon Sep 17 00:00:00 2001 From: Tony Wu Date: Fri, 23 Aug 2019 16:38:31 +0800 Subject: [PATCH 008/227] rtl8195am - fix array assumed to have one element warning Signed-off-by: Tony Wu --- .../TARGET_AMEBA/sdk/os/cmsis_rtos/cmsis_rtos_service.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/cmsis_rtos/cmsis_rtos_service.c b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/cmsis_rtos/cmsis_rtos_service.c index ae92b9dc024..13ece1aa534 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/cmsis_rtos/cmsis_rtos_service.c +++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/os/cmsis_rtos/cmsis_rtos_service.c @@ -1212,7 +1212,7 @@ _WEAK void xPortSysTickHandler(void) printf("%s: Should not come over here!\r\n", __func__); } -_WEAK u8 __ram_start_table_start__[]; +_WEAK u8 *__ram_start_table_start__; _WEAK void rtw_odm_acquirespinlock(void * adapter, int type) { From 6b75945eaa4e50a36a7d7e8577dbbc88b8297860 Mon Sep 17 00:00:00 2001 From: Tony Wu Date: Mon, 26 Aug 2019 12:29:03 +0800 Subject: [PATCH 009/227] rtl8195am - remove redundant code Signed-off-by: Tony Wu --- .../TARGET_MCU_RTL8195A/i2c_api.c | 44 ----------------- .../TARGET_MCU_RTL8195A/pwmout_api.c | 24 --------- .../TARGET_MCU_RTL8195A/serial_api.c | 28 ----------- .../TARGET_MCU_RTL8195A/spi_api.c | 49 ------------------- 4 files changed, 145 deletions(-) diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/i2c_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/i2c_api.c index 3881418b14f..c29af82dd34 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/i2c_api.c +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/i2c_api.c @@ -28,50 +28,6 @@ #ifdef CONFIG_MBED_ENABLED #include "PeripheralPins.h" -#else -static const PinMap PinMap_I2C_SDA[] = { - {PD_4, RTL_PIN_PERI(I2C0, 0, S0), RTL_PIN_FUNC(I2C0, S0)}, - {PH_1, RTL_PIN_PERI(I2C0, 0, S1), RTL_PIN_FUNC(I2C0, S1)}, - {PC_8, RTL_PIN_PERI(I2C0, 0, S2), RTL_PIN_FUNC(I2C0, S2)}, - {PE_7, RTL_PIN_PERI(I2C0, 0, S3), RTL_PIN_FUNC(I2C0, S3)}, - - {PC_4, RTL_PIN_PERI(I2C1, 1, S0), RTL_PIN_FUNC(I2C1, S0)}, - {PH_3, RTL_PIN_PERI(I2C1, 1, S1), RTL_PIN_FUNC(I2C1, S1)}, - {PD_7, RTL_PIN_PERI(I2C1, 1, S2), RTL_PIN_FUNC(I2C1, S2)}, - - {PB_7, RTL_PIN_PERI(I2C2, 2, S0), RTL_PIN_FUNC(I2C2, S0)}, - {PE_1, RTL_PIN_PERI(I2C2, 2, S1), RTL_PIN_FUNC(I2C2, S1)}, - {PC_7, RTL_PIN_PERI(I2C2, 2, S2), RTL_PIN_FUNC(I2C2, S2)}, - - {PB_3, RTL_PIN_PERI(I2C3, 3, S0), RTL_PIN_FUNC(I2C3, S0)}, - {PE_3, RTL_PIN_PERI(I2C3, 3, S1), RTL_PIN_FUNC(I2C3, S1)}, - {PE_5, RTL_PIN_PERI(I2C3, 3, S2), RTL_PIN_FUNC(I2C3, S2)}, - {PD_9, RTL_PIN_PERI(I2C3, 3, S3), RTL_PIN_FUNC(I2C3, S3)}, - - {NC, NC, 0} -}; - -static const PinMap PinMap_I2C_SCL[] = { - {PD_5, RTL_PIN_PERI(I2C0, 0, S0), RTL_PIN_FUNC(I2C0, S0)}, - {PH_0, RTL_PIN_PERI(I2C0, 0, S1), RTL_PIN_FUNC(I2C0, S1)}, - {PC_9, RTL_PIN_PERI(I2C0, 0, S2), RTL_PIN_FUNC(I2C0, S2)}, - {PE_6, RTL_PIN_PERI(I2C0, 0, S3), RTL_PIN_FUNC(I2C0, S3)}, - - {PC_5, RTL_PIN_PERI(I2C1, 1, S0), RTL_PIN_FUNC(I2C1, S0)}, - {PH_2, RTL_PIN_PERI(I2C1, 1, S1), RTL_PIN_FUNC(I2C1, S1)}, - {PD_6, RTL_PIN_PERI(I2C1, 1, S2), RTL_PIN_FUNC(I2C1, S2)}, - - {PB_6, RTL_PIN_PERI(I2C2, 2, S0), RTL_PIN_FUNC(I2C2, S0)}, - {PE_0, RTL_PIN_PERI(I2C2, 2, S1), RTL_PIN_FUNC(I2C2, S1)}, - {PC_6, RTL_PIN_PERI(I2C2, 2, S2), RTL_PIN_FUNC(I2C2, S2)}, - - {PB_2, RTL_PIN_PERI(I2C3, 3, S0), RTL_PIN_FUNC(I2C3, S0)}, - {PE_2, RTL_PIN_PERI(I2C3, 3, S1), RTL_PIN_FUNC(I2C3, S1)}, - {PE_4, RTL_PIN_PERI(I2C3, 3, S2), RTL_PIN_FUNC(I2C3, S2)}, - {PD_8, RTL_PIN_PERI(I2C3, 3, S3), RTL_PIN_FUNC(I2C3, S3)}, - - {NC, NC, 0} -}; #endif static int address_save_int[4]; diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/pwmout_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/pwmout_api.c index 2bb1ed0af61..ad03783c6c2 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/pwmout_api.c +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/pwmout_api.c @@ -29,30 +29,6 @@ #ifdef CONFIG_MBED_ENABLED #include "PeripheralPins.h" -#else -static const PinMap PinMap_PWM[] = { - {PB_4, RTL_PIN_PERI(PWM0, 0, S0), RTL_PIN_FUNC(PWM0, S0)}, - {PB_5, RTL_PIN_PERI(PWM1, 1, S0), RTL_PIN_FUNC(PWM1, S0)}, - {PB_6, RTL_PIN_PERI(PWM2, 2, S0), RTL_PIN_FUNC(PWM2, S0)}, - {PB_7, RTL_PIN_PERI(PWM3, 3, S0), RTL_PIN_FUNC(PWM3, S0)}, - - {PC_0, RTL_PIN_PERI(PWM0, 0, S1), RTL_PIN_FUNC(PWM0, S1)}, - {PC_1, RTL_PIN_PERI(PWM1, 1, S1), RTL_PIN_FUNC(PWM1, S1)}, - {PC_2, RTL_PIN_PERI(PWM2, 2, S1), RTL_PIN_FUNC(PWM2, S1)}, - {PC_3, RTL_PIN_PERI(PWM3, 3, S1), RTL_PIN_FUNC(PWM3, S1)}, - - {PD_3, RTL_PIN_PERI(PWM0, 0, S2), RTL_PIN_FUNC(PWM0, S2)}, - {PD_4, RTL_PIN_PERI(PWM1, 1, S2), RTL_PIN_FUNC(PWM1, S2)}, - {PD_5, RTL_PIN_PERI(PWM2, 2, S2), RTL_PIN_FUNC(PWM2, S2)}, - {PD_6, RTL_PIN_PERI(PWM3, 3, S2), RTL_PIN_FUNC(PWM3, S2)}, - - {PE_0, RTL_PIN_PERI(PWM0, 0, S3), RTL_PIN_FUNC(PWM0, S3)}, - {PE_1, RTL_PIN_PERI(PWM1, 1, S3), RTL_PIN_FUNC(PWM1, S3)}, - {PE_2, RTL_PIN_PERI(PWM2, 2, S3), RTL_PIN_FUNC(PWM2, S3)}, - {PE_3, RTL_PIN_PERI(PWM3, 3, S3), RTL_PIN_FUNC(PWM3, S3)}, - - {NC, NC, 0} -}; #endif void pwmout_init(pwmout_t* obj, PinName pin) diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/serial_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/serial_api.c index 3aabdcab849..c972e5d047b 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/serial_api.c +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/serial_api.c @@ -29,34 +29,6 @@ #ifdef CONFIG_MBED_ENABLED #include "PeripheralPins.h" -#else -static const PinMap PinMap_UART_TX[] = { - {PC_3, RTL_PIN_PERI(UART0, 0, S0), RTL_PIN_FUNC(UART0, S0)}, - {PE_0, RTL_PIN_PERI(UART0, 0, S1), RTL_PIN_FUNC(UART0, S1)}, - {PA_7, RTL_PIN_PERI(UART0, 0, S2), RTL_PIN_FUNC(UART0, S2)}, - {PD_3, RTL_PIN_PERI(UART1, 1, S0), RTL_PIN_FUNC(UART1, S0)}, - {PE_4, RTL_PIN_PERI(UART1, 1, S1), RTL_PIN_FUNC(UART1, S1)}, - {PB_5, RTL_PIN_PERI(UART1, 1, S2), RTL_PIN_FUNC(UART1, S2)}, - {PA_4, RTL_PIN_PERI(UART2, 2, S0), RTL_PIN_FUNC(UART2, S0)}, - {PC_9, RTL_PIN_PERI(UART2, 2, S1), RTL_PIN_FUNC(UART2, S1)}, - {PD_7, RTL_PIN_PERI(UART2, 2, S2), RTL_PIN_FUNC(UART2, S2)}, - {PB_0, RTL_PIN_PERI(LOG_UART, 3, S0), RTL_PIN_FUNC(LOG_UART, S0)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_UART_RX[] = { - {PC_0, RTL_PIN_PERI(UART0, 0, S0), RTL_PIN_FUNC(UART0, S0)}, - {PE_3, RTL_PIN_PERI(UART0, 0, S1), RTL_PIN_FUNC(UART0, S1)}, - {PA_6, RTL_PIN_PERI(UART0, 0, S2), RTL_PIN_FUNC(UART0, S2)}, - {PD_0, RTL_PIN_PERI(UART1, 1, S0), RTL_PIN_FUNC(UART1, S0)}, - {PE_7, RTL_PIN_PERI(UART1, 1, S1), RTL_PIN_FUNC(UART1, S1)}, - {PB_4, RTL_PIN_PERI(UART1, 1, S2), RTL_PIN_FUNC(UART1, S2)}, - {PA_0, RTL_PIN_PERI(UART2, 2, S0), RTL_PIN_FUNC(UART2, S0)}, - {PC_6, RTL_PIN_PERI(UART2, 2, S1), RTL_PIN_FUNC(UART2, S1)}, - {PD_4, RTL_PIN_PERI(UART2, 2, S2), RTL_PIN_FUNC(UART2, S2)}, - {PB_1, RTL_PIN_PERI(LOG_UART, 3, S0), RTL_PIN_FUNC(LOG_UART, S0)}, - {NC, NC, 0} -}; #endif #define UART_NUM (3) diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/spi_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/spi_api.c index 5080954f9d1..57ac3bd26e4 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/spi_api.c +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_MCU_RTL8195A/spi_api.c @@ -43,55 +43,6 @@ extern const DW_SSI_DEFAULT_SETTING SpiDefaultSetting; #ifdef CONFIG_MBED_ENABLED #include "PeripheralPins.h" -#else -static const PinMap PinMap_SSI_MOSI[] = { - {PE_2, RTL_PIN_PERI(SPI0, 0, S0), RTL_PIN_FUNC(SPI0, S0)}, - {PC_2, RTL_PIN_PERI(SPI0, 0, S1), RTL_PIN_FUNC(SPI0, S1)}, - {PA_1, RTL_PIN_PERI(SPI1, 1, S0), RTL_PIN_FUNC(SPI1, S0)}, - {PB_6, RTL_PIN_PERI(SPI1, 1, S1), RTL_PIN_FUNC(SPI1, S1)}, - {PD_6, RTL_PIN_PERI(SPI1, 1, S2), RTL_PIN_FUNC(SPI1, S2)}, - {PG_2, RTL_PIN_PERI(SPI2, 2, S0), RTL_PIN_FUNC(SPI2, S0)}, - {PE_6, RTL_PIN_PERI(SPI2, 2, S1), RTL_PIN_FUNC(SPI2, S1)}, - {PD_2, RTL_PIN_PERI(SPI2, 2, S2), RTL_PIN_FUNC(SPI2, S2)}, - {NC, NC, 0} -}; - -static const PinMap PinMap_SSI_MISO[] = { - {PE_3, RTL_PIN_PERI(SPI0, 0, S0), RTL_PIN_FUNC(SPI0, S0)}, - {PC_3, RTL_PIN_PERI(SPI0, 0, S1), RTL_PIN_FUNC(SPI0, S1)}, - {PA_0, RTL_PIN_PERI(SPI1, 1, S0), RTL_PIN_FUNC(SPI1, S0)}, - {PB_7, RTL_PIN_PERI(SPI1, 1, S1), RTL_PIN_FUNC(SPI1, S1)}, - {PD_7, RTL_PIN_PERI(SPI1, 1, S2), RTL_PIN_FUNC(SPI1, S2)}, - {PG_3, RTL_PIN_PERI(SPI2, 2, S0), RTL_PIN_FUNC(SPI2, S0)}, - {PE_7, RTL_PIN_PERI(SPI2, 2, S1), RTL_PIN_FUNC(SPI2, S1)}, - {PD_3, RTL_PIN_PERI(SPI2, 2, S2), RTL_PIN_FUNC(SPI2, S2)}, - {NC, NC, 0} -}; - -// For testing only -static const PinMap PinMap_SSI_SCLK[] = { - {PC_1, RTL_PIN_PERI(SPI0, 0, S1), /* Unused */ 0}, - {PA_2, RTL_PIN_PERI(SPI1, 1, S0), /* Unused */ 0}, - {PA_2, RTL_PIN_PERI(SPI1, 1, S1), /* Unused */ 0}, - {PA_2, RTL_PIN_PERI(SPI1, 1, S2), /* Unused */ 0}, - {PD_5, RTL_PIN_PERI(SPI1, 1, S0), /* Unused */ 0}, - {PD_5, RTL_PIN_PERI(SPI1, 1, S1), /* Unused */ 0}, - {PD_5, RTL_PIN_PERI(SPI1, 1, S2), /* Unused */ 0}, - - {NC, NC, 0} -}; - -// For testing only -static const PinMap PinMap_SSI_SSEL[] = { - {PE_5, RTL_PIN_PERI(SPI0, 0, S2), /* Unused */ 0}, - {PC_5, RTL_PIN_PERI(SPI0, 0, S2), /* Unused */ 0}, - {PC_4, RTL_PIN_PERI(SPI0, 0, S1), /* Unused */ 0}, - {PC_0, RTL_PIN_PERI(SPI0, 0, S0), /* Unused */ 0}, - {PA_4, RTL_PIN_PERI(SPI1, 1, S0), /* Unused */ 0}, - {PD_4, RTL_PIN_PERI(SPI1, 1, S0), /* Unused */ 0}, - - {NC, NC, 0} -}; #endif void spi_init (spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) From 46247ca0298c33c69d5aca1e37fdbe204d989b3d Mon Sep 17 00:00:00 2001 From: Lei Zhang Date: Mon, 26 Aug 2019 12:11:45 -0700 Subject: [PATCH 010/227] Bringdown interface when stopping softap The interface should be brought down when stopping softap. --- .../TARGET_WHD/interface/WhdSoftAPInterface.cpp | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/features/netsocket/emac-drivers/TARGET_WHD/interface/WhdSoftAPInterface.cpp b/features/netsocket/emac-drivers/TARGET_WHD/interface/WhdSoftAPInterface.cpp index 17f99978b85..a13aff0b728 100644 --- a/features/netsocket/emac-drivers/TARGET_WHD/interface/WhdSoftAPInterface.cpp +++ b/features/netsocket/emac-drivers/TARGET_WHD/interface/WhdSoftAPInterface.cpp @@ -173,7 +173,19 @@ int WhdSoftAPInterface::stop(void) return NSAPI_ERROR_DHCP_FAILURE; } _dhcp_server.reset(); - return whd_wifi_stop_ap(_whd_emac.ifp); + + // bring down + int err = _interface->bringdown(); + if (err) { + return err; + } + + // stop softap + whd_result_t res = whd_wifi_stop_ap(_whd_emac.ifp); + if (res != WHD_SUCCESS) { + return whd_toerror(res); + } + return NSAPI_ERROR_OK; } int WhdSoftAPInterface::remove_custom_ie(const whd_custom_ie_info_t *ie_info) From c21f34823bc6499d79b612bc25ca8fabb8e03715 Mon Sep 17 00:00:00 2001 From: Chun-Chieh Li Date: Thu, 29 Aug 2019 18:08:12 +0800 Subject: [PATCH 011/227] M263: Fix mbedmicro-rtos-mbed-systimer/Wake up from deep sleep failing This test requires total latency (tot = h/w + s/w) (wakeup from deepsleep) be under 1ms. To check the issue, measure total latency on Nuvoton targets: TARGET EXP(us) EXP+TOL(us) ACT(us) NANO130 42000 43000 42939 NUC472 42000 43000 42236 M453 42000 43000 43274 M487 42000 43000 42877 M2351 42000 43000 43213 Checking h/w spec, h/w latency (wakeup time from normal power-down mode) on M487/M2351 is just 1us (n/a on other targets). S/W latency plays the major part here. S/W latency relies on system performance. On Nuvoton targets, 'LPTICKER_DELAY_TICKS' possibly complicates the test. Anyway, to pass the test, add extra 1ms latency (deep-sleep-latency) in targets.json for Nuvoton targets. --- targets/targets.json | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/targets/targets.json b/targets/targets.json index bc448b71e89..3c3989fa325 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -9409,7 +9409,10 @@ "release_versions": ["5"], "device_name": "M263KIAAE", "bootloader_supported": true, - "tickless-from-us-ticker": true, + "overrides": { + "deep-sleep-latency": 1, + "tickless-from-us-ticker": true + }, "forced_reset_timeout": 3 }, "__build_tools_metadata__": { From c138ef8baa76a2c777d0d684509b9d671ec131e7 Mon Sep 17 00:00:00 2001 From: int_szyk Date: Fri, 30 Aug 2019 13:54:39 +0200 Subject: [PATCH 012/227] Change LSI_VALUE in STM implementation. Wrong LSI value might be causing problems witch watchdogs. --- targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rcc.h | 2 +- targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_rcc.h | 2 +- targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_rcc.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rcc.h b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rcc.h index 50bba6b2b6d..590bd4b5e75 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rcc.h +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_rcc.h @@ -141,7 +141,7 @@ typedef struct #endif /* LSE_VALUE */ #if !defined (LSI_VALUE) -#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ +#define LSI_VALUE 40000U /*!< Value of the LSI oscillator in Hz */ #endif /* LSI_VALUE */ #if defined(RCC_HSI48_SUPPORT) diff --git a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_rcc.h b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_rcc.h index 20089b752f1..17843975714 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_rcc.h +++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_rcc.h @@ -146,7 +146,7 @@ typedef struct #endif /* LSE_VALUE */ #if !defined (LSI_VALUE) -#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ +#define LSI_VALUE 40000U /*!< Value of the LSI oscillator in Hz */ #endif /* LSI_VALUE */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_rcc.h b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_rcc.h index 8b4b8ce8ed0..196300ec32f 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_rcc.h +++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_rcc.h @@ -131,7 +131,7 @@ typedef struct #endif /* LSE_VALUE */ #if !defined (LSI_VALUE) -#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ +#define LSI_VALUE 37000U /*!< Value of the LSI oscillator in Hz */ #endif /* LSI_VALUE */ /** * @} From 1366602ca70f55e8f6b76ac11a53ea113a8cefb4 Mon Sep 17 00:00:00 2001 From: Chun-Chieh Li Date: Thu, 29 Aug 2019 18:00:45 +0800 Subject: [PATCH 013/227] M263: Enlarge LPTICKER_DELAY_TICKS for safe On Nuvoton targets, lp_ticker_set_interrupt(...) needs around 3 lp-ticker ticks to take effect. It may miss when current tick and match tick are very close (see hal/LowPowerTickerWrapper.cpp). Enlarge LPTICKER_DELAY_TICKS to 4 from 3 to address this boundary case. --- targets/targets.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/targets.json b/targets/targets.json index 3c3989fa325..cd5937f52f6 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -9355,7 +9355,7 @@ ], "macros": [ "MBED_FAULT_HANDLER_DISABLED", - "LPTICKER_DELAY_TICKS=3" + "LPTICKER_DELAY_TICKS=4" ], "is_disk_virtual": true, "supported_toolchains": ["ARMC6", "GCC_ARM", "IAR"], From f84a2df116813478f4f88d277728c9ce06645b98 Mon Sep 17 00:00:00 2001 From: "dolphin\\\\gena" Date: Wed, 28 Aug 2019 22:17:45 +0300 Subject: [PATCH 014/227] Add pin speed controlling interface --- targets/TARGET_STM/PinNamesTypes.h | 49 +++++++++++++++++++----------- targets/TARGET_STM/pinmap.c | 13 ++++++-- 2 files changed, 43 insertions(+), 19 deletions(-) diff --git a/targets/TARGET_STM/PinNamesTypes.h b/targets/TARGET_STM/PinNamesTypes.h index 673f5f58b96..11f6e879142 100644 --- a/targets/TARGET_STM/PinNamesTypes.h +++ b/targets/TARGET_STM/PinNamesTypes.h @@ -40,12 +40,12 @@ extern "C" { * [2:0] Function (like in MODER reg) : Input / Output / Alt / Analog * [3] Output Push-Pull / Open Drain (as in OTYPER reg) * [5:4] as in PUPDR reg: No Pull, Pull-up, Pull-Donc - * [7:6] Reserved for speed config (as in OSPEEDR), but not used yet - * [11:8] Alternate Num (as in AFRL/AFRG reg) - * [16:12] Channel (Analog/Timer specific) - * [17] Inverted (Analog/Timer specific) - * [18] Analog ADC control - Only valid for specific families - * [32:19] Reserved + * [9:6] speed config (as in OSPEEDR) + * [13:10] Alternate Num (as in AFRL/AFRG reg) + * [17:14] Channel (Analog/Timer specific) + * [18] Inverted (Analog/Timer specific) + * [19] Analog ADC control - Only valid for specific families + * [32:21] Reserved */ #define STM_PIN_FUNCTION_MASK 0x07 @@ -60,24 +60,24 @@ extern "C" { #define STM_PIN_PUPD_SHIFT 4 #define STM_PIN_PUPD_BITS (STM_PIN_PUPD_MASK << STM_PIN_PUPD_SHIFT) -#define STM_PIN_SPEED_MASK 0x03 +#define STM_PIN_SPEED_MASK 0x0F #define STM_PIN_SPEED_SHIFT 6 #define STM_PIN_SPEED_BITS (STM_PIN_SPEED_MASK << STM_PIN_SPEED_SHIFT) #define STM_PIN_AFNUM_MASK 0x0F -#define STM_PIN_AFNUM_SHIFT 8 +#define STM_PIN_AFNUM_SHIFT 10 #define STM_PIN_AFNUM_BITS (STM_PIN_AFNUM_MASK << STM_PIN_AFNUM_SHIFT) #define STM_PIN_CHAN_MASK 0x1F -#define STM_PIN_CHAN_SHIFT 12 +#define STM_PIN_CHAN_SHIFT 14 #define STM_PIN_CHANNEL_BIT (STM_PIN_CHAN_MASK << STM_PIN_CHAN_SHIFT) #define STM_PIN_INV_MASK 0x01 -#define STM_PIN_INV_SHIFT 17 +#define STM_PIN_INV_SHIFT 19 #define STM_PIN_INV_BIT (STM_PIN_INV_MASK << STM_PIN_INV_SHIFT) #define STM_PIN_AN_CTRL_MASK 0x01 -#define STM_PIN_AN_CTRL_SHIFT 18 +#define STM_PIN_AN_CTRL_SHIFT 20 #define STM_PIN_ANALOG_CONTROL_BIT (STM_PIN_AN_CTRL_MASK << STM_PIN_AN_CTRL_SHIFT) #define STM_PIN_FUNCTION(X) (((X) >> STM_PIN_FUNCTION_SHIFT) & STM_PIN_FUNCTION_MASK) @@ -90,15 +90,30 @@ extern "C" { #define STM_PIN_ANALOG_CONTROL(X) (((X) >> STM_PIN_AN_CTRL_SHIFT) & STM_PIN_AN_CTRL_MASK) #define STM_PIN_DEFINE(FUNC_OD, PUPD, AFNUM) ((int)(FUNC_OD) |\ - ((PUPD & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\ - ((AFNUM & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT)) + ((STM_PIN_SPEED_MASK & STM_PIN_SPEED_MASK) << STM_PIN_SPEED_SHIFT) |\ + (((PUPD) & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\ + (((AFNUM) & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT)) + +#define STM_PIN_DEFINE_SPEED(FUNC_OD, PUPD, AFNUM, SPEED) ((int)(FUNC_OD) |\ + (((SPEED) & STM_PIN_SPEED_MASK) << STM_PIN_SPEED_SHIFT) |\ + (((PUPD) & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\ + (((AFNUM) & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT)) #define STM_PIN_DEFINE_EXT(FUNC_OD, PUPD, AFNUM, CHAN, INV) \ ((int)(FUNC_OD) |\ - ((PUPD & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\ - ((AFNUM & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT) |\ - ((CHAN & STM_PIN_CHAN_MASK) << STM_PIN_CHAN_SHIFT) |\ - ((INV & STM_PIN_INV_MASK) << STM_PIN_INV_SHIFT)) + ((STM_PIN_SPEED_MASK & STM_PIN_SPEED_MASK) << STM_PIN_SPEED_SHIFT) |\ + (((PUPD) & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\ + (((AFNUM) & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT) |\ + (((CHANv & STM_PIN_CHAN_MASK) << STM_PIN_CHAN_SHIFT) |\ + (((INV) & STM_PIN_INV_MASK) << STM_PIN_INV_SHIFT)) + +#define STM_PIN_DEFINE_EXT2(FUNC_OD, PUPD, AFNUM, CHAN, INV, SPEED) \ + ((int)(FUNC_OD) |\ + (((SPEED) & STM_PIN_SPEED_MASK) << STM_PIN_SPEED_SHIFT) |\ + (((PUPD) & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\ + (((AFNUM) & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT) |\ + (((CHAN) & STM_PIN_CHAN_MASK) << STM_PIN_CHAN_SHIFT) |\ + (((INV) & STM_PIN_INV_MASK) << STM_PIN_INV_SHIFT)) /* * MACROS to support the legacy definition of PIN formats diff --git a/targets/TARGET_STM/pinmap.c b/targets/TARGET_STM/pinmap.c index 5076ef45ba9..a0acdaf7dda 100644 --- a/targets/TARGET_STM/pinmap.c +++ b/targets/TARGET_STM/pinmap.c @@ -64,12 +64,13 @@ void pin_function(PinName pin, int data) // Get the pin informations uint32_t mode = STM_PIN_FUNCTION(data); uint32_t afnum = STM_PIN_AFNUM(data); + uint32_t speed = STM_PIN_SPEED(data); uint32_t port = STM_PORT(pin); uint32_t ll_pin = ll_pin_defines[STM_PIN(pin)]; uint32_t ll_mode = 0; // Enable GPIO clock - GPIO_TypeDef *gpio = Set_GPIO_Clock(port); + GPIO_TypeDef * const gpio = Set_GPIO_Clock(port); /* Set default speed to high. * For most families there are dedicated registers so it is @@ -79,13 +80,21 @@ void pin_function(PinName pin, int data) #if defined (TARGET_STM32F1) if (mode == STM_PIN_OUTPUT) { #endif - + switch (speed) + { + /* Default value for backward compatibility */ + case STM_PIN_SPEED_MASK: #if defined (LL_GPIO_SPEED_FREQ_VERY_HIGH) LL_GPIO_SetPinSpeed(gpio, ll_pin, LL_GPIO_SPEED_FREQ_VERY_HIGH); #else LL_GPIO_SetPinSpeed(gpio, ll_pin, LL_GPIO_SPEED_FREQ_HIGH); #endif + break; + default: + LL_GPIO_SetPinSpeed(gpio, ll_pin, speed); + break; + } #if defined (TARGET_STM32F1) } #endif From e8be6505c4813a85067ae7f01631f6ad4d513490 Mon Sep 17 00:00:00 2001 From: "dolphin\\\\gena" Date: Mon, 2 Sep 2019 10:08:36 +0300 Subject: [PATCH 015/227] mistype fix --- targets/TARGET_STM/PinNamesTypes.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/TARGET_STM/PinNamesTypes.h b/targets/TARGET_STM/PinNamesTypes.h index 11f6e879142..88e3eaeda06 100644 --- a/targets/TARGET_STM/PinNamesTypes.h +++ b/targets/TARGET_STM/PinNamesTypes.h @@ -104,7 +104,7 @@ extern "C" { ((STM_PIN_SPEED_MASK & STM_PIN_SPEED_MASK) << STM_PIN_SPEED_SHIFT) |\ (((PUPD) & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\ (((AFNUM) & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT) |\ - (((CHANv & STM_PIN_CHAN_MASK) << STM_PIN_CHAN_SHIFT) |\ + (((CHAN) & STM_PIN_CHAN_MASK) << STM_PIN_CHAN_SHIFT) |\ (((INV) & STM_PIN_INV_MASK) << STM_PIN_INV_SHIFT)) #define STM_PIN_DEFINE_EXT2(FUNC_OD, PUPD, AFNUM, CHAN, INV, SPEED) \ From 7bc2aae4358fc8aa28132bb01bf5ca499eb998c8 Mon Sep 17 00:00:00 2001 From: "dolphin\\\\gena" Date: Mon, 2 Sep 2019 10:17:54 +0300 Subject: [PATCH 016/227] formatting issue --- targets/TARGET_STM/pinmap.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/targets/TARGET_STM/pinmap.c b/targets/TARGET_STM/pinmap.c index a0acdaf7dda..6de8beaed49 100644 --- a/targets/TARGET_STM/pinmap.c +++ b/targets/TARGET_STM/pinmap.c @@ -84,11 +84,11 @@ void pin_function(PinName pin, int data) { /* Default value for backward compatibility */ case STM_PIN_SPEED_MASK: -#if defined (LL_GPIO_SPEED_FREQ_VERY_HIGH) - LL_GPIO_SetPinSpeed(gpio, ll_pin, LL_GPIO_SPEED_FREQ_VERY_HIGH); -#else - LL_GPIO_SetPinSpeed(gpio, ll_pin, LL_GPIO_SPEED_FREQ_HIGH); -#endif + #if defined (LL_GPIO_SPEED_FREQ_VERY_HIGH) + LL_GPIO_SetPinSpeed(gpio, ll_pin, LL_GPIO_SPEED_FREQ_VERY_HIGH); + #else + LL_GPIO_SetPinSpeed(gpio, ll_pin, LL_GPIO_SPEED_FREQ_HIGH); + #endif break; default: From 954552a7d16c730c05a6ed47c717f61502d7fcc6 Mon Sep 17 00:00:00 2001 From: "dolphin\\\\gena" Date: Mon, 2 Sep 2019 10:21:38 +0300 Subject: [PATCH 017/227] fix mistypes --- targets/TARGET_STM/PinNamesTypes.h | 8 ++++---- targets/TARGET_STM/pinmap.c | 6 +++--- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/targets/TARGET_STM/PinNamesTypes.h b/targets/TARGET_STM/PinNamesTypes.h index 88e3eaeda06..69818b336b2 100644 --- a/targets/TARGET_STM/PinNamesTypes.h +++ b/targets/TARGET_STM/PinNamesTypes.h @@ -94,8 +94,8 @@ extern "C" { (((PUPD) & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\ (((AFNUM) & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT)) -#define STM_PIN_DEFINE_SPEED(FUNC_OD, PUPD, AFNUM, SPEED) ((int)(FUNC_OD) |\ - (((SPEED) & STM_PIN_SPEED_MASK) << STM_PIN_SPEED_SHIFT) |\ +#define STM_PIN_DEFINE_SPEED(FUNC_OD, PUPD, AFNUM, SPEEDV) ((int)(FUNC_OD) |\ + (((SPEEDV) & STM_PIN_SPEED_MASK) << STM_PIN_SPEED_SHIFT) |\ (((PUPD) & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\ (((AFNUM) & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT)) @@ -107,9 +107,9 @@ extern "C" { (((CHAN) & STM_PIN_CHAN_MASK) << STM_PIN_CHAN_SHIFT) |\ (((INV) & STM_PIN_INV_MASK) << STM_PIN_INV_SHIFT)) -#define STM_PIN_DEFINE_EXT2(FUNC_OD, PUPD, AFNUM, CHAN, INV, SPEED) \ +#define STM_PIN_DEFINE_EXT2(FUNC_OD, PUPD, AFNUM, CHAN, INV, SPEEDV) \ ((int)(FUNC_OD) |\ - (((SPEED) & STM_PIN_SPEED_MASK) << STM_PIN_SPEED_SHIFT) |\ + (((SPEEDV) & STM_PIN_SPEED_MASK) << STM_PIN_SPEED_SHIFT) |\ (((PUPD) & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\ (((AFNUM) & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT) |\ (((CHAN) & STM_PIN_CHAN_MASK) << STM_PIN_CHAN_SHIFT) |\ diff --git a/targets/TARGET_STM/pinmap.c b/targets/TARGET_STM/pinmap.c index 6de8beaed49..f860754b301 100644 --- a/targets/TARGET_STM/pinmap.c +++ b/targets/TARGET_STM/pinmap.c @@ -84,11 +84,11 @@ void pin_function(PinName pin, int data) { /* Default value for backward compatibility */ case STM_PIN_SPEED_MASK: - #if defined (LL_GPIO_SPEED_FREQ_VERY_HIGH) + #if defined (LL_GPIO_SPEED_FREQ_VERY_HIGH) LL_GPIO_SetPinSpeed(gpio, ll_pin, LL_GPIO_SPEED_FREQ_VERY_HIGH); - #else + #else LL_GPIO_SetPinSpeed(gpio, ll_pin, LL_GPIO_SPEED_FREQ_HIGH); - #endif + #endif break; default: From 8e9511e4351074848414ede570df80f3aeb233c8 Mon Sep 17 00:00:00 2001 From: "dolphin\\\\gena" Date: Mon, 2 Sep 2019 12:08:07 +0300 Subject: [PATCH 018/227] formatting --- targets/TARGET_STM/pinmap.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/targets/TARGET_STM/pinmap.c b/targets/TARGET_STM/pinmap.c index f860754b301..e16840a80c2 100644 --- a/targets/TARGET_STM/pinmap.c +++ b/targets/TARGET_STM/pinmap.c @@ -80,15 +80,14 @@ void pin_function(PinName pin, int data) #if defined (TARGET_STM32F1) if (mode == STM_PIN_OUTPUT) { #endif - switch (speed) - { + switch (speed) { /* Default value for backward compatibility */ case STM_PIN_SPEED_MASK: - #if defined (LL_GPIO_SPEED_FREQ_VERY_HIGH) +#if defined (LL_GPIO_SPEED_FREQ_VERY_HIGH) LL_GPIO_SetPinSpeed(gpio, ll_pin, LL_GPIO_SPEED_FREQ_VERY_HIGH); - #else +#else LL_GPIO_SetPinSpeed(gpio, ll_pin, LL_GPIO_SPEED_FREQ_HIGH); - #endif +#endif break; default: From 908e7a3e9f058ea4c411bb5a80a5b2a924702dd0 Mon Sep 17 00:00:00 2001 From: Martin Kojtal Date: Mon, 2 Sep 2019 10:32:32 +0100 Subject: [PATCH 019/227] ST pinmap: Fix the style --- targets/TARGET_STM/pinmap.c | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/targets/TARGET_STM/pinmap.c b/targets/TARGET_STM/pinmap.c index e16840a80c2..01f2e1bc092 100644 --- a/targets/TARGET_STM/pinmap.c +++ b/targets/TARGET_STM/pinmap.c @@ -80,23 +80,22 @@ void pin_function(PinName pin, int data) #if defined (TARGET_STM32F1) if (mode == STM_PIN_OUTPUT) { #endif - switch (speed) { - /* Default value for backward compatibility */ - case STM_PIN_SPEED_MASK: + switch (speed) { + /* Default value for backward compatibility */ + case STM_PIN_SPEED_MASK: #if defined (LL_GPIO_SPEED_FREQ_VERY_HIGH) - LL_GPIO_SetPinSpeed(gpio, ll_pin, LL_GPIO_SPEED_FREQ_VERY_HIGH); + LL_GPIO_SetPinSpeed(gpio, ll_pin, LL_GPIO_SPEED_FREQ_VERY_HIGH); #else - LL_GPIO_SetPinSpeed(gpio, ll_pin, LL_GPIO_SPEED_FREQ_HIGH); + LL_GPIO_SetPinSpeed(gpio, ll_pin, LL_GPIO_SPEED_FREQ_HIGH); #endif - break; - - default: - LL_GPIO_SetPinSpeed(gpio, ll_pin, speed); - break; - } + break; + default: + LL_GPIO_SetPinSpeed(gpio, ll_pin, speed); + break; + } #if defined (TARGET_STM32F1) } -#endif +#endiff switch (mode) { case STM_PIN_INPUT: From a35663b171b631a7364e48649796169f51b04440 Mon Sep 17 00:00:00 2001 From: Martin Kojtal Date: Mon, 2 Sep 2019 10:33:20 +0100 Subject: [PATCH 020/227] ST pinmap: remove endif mistype --- targets/TARGET_STM/pinmap.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/TARGET_STM/pinmap.c b/targets/TARGET_STM/pinmap.c index 01f2e1bc092..1331d4eba77 100644 --- a/targets/TARGET_STM/pinmap.c +++ b/targets/TARGET_STM/pinmap.c @@ -95,7 +95,7 @@ void pin_function(PinName pin, int data) } #if defined (TARGET_STM32F1) } -#endiff +#endif switch (mode) { case STM_PIN_INPUT: From 13c202b828bf3681b65f6854871ea1ca0eecb600 Mon Sep 17 00:00:00 2001 From: "dolphin\\\\gena" Date: Mon, 2 Sep 2019 14:02:29 +0300 Subject: [PATCH 021/227] rename macro --- targets/TARGET_STM/PinNamesTypes.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/TARGET_STM/PinNamesTypes.h b/targets/TARGET_STM/PinNamesTypes.h index 69818b336b2..f4067dc3bc9 100644 --- a/targets/TARGET_STM/PinNamesTypes.h +++ b/targets/TARGET_STM/PinNamesTypes.h @@ -107,7 +107,7 @@ extern "C" { (((CHAN) & STM_PIN_CHAN_MASK) << STM_PIN_CHAN_SHIFT) |\ (((INV) & STM_PIN_INV_MASK) << STM_PIN_INV_SHIFT)) -#define STM_PIN_DEFINE_EXT2(FUNC_OD, PUPD, AFNUM, CHAN, INV, SPEEDV) \ +#define STM_PIN_DEFINE_SPEED_EXT(FUNC_OD, PUPD, AFNUM, CHAN, INV, SPEEDV) \ ((int)(FUNC_OD) |\ (((SPEEDV) & STM_PIN_SPEED_MASK) << STM_PIN_SPEED_SHIFT) |\ (((PUPD) & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\ From 495ba7b92c3fcca71237c063e3c0e6ddf7c179f0 Mon Sep 17 00:00:00 2001 From: "dolphin\\\\gena" Date: Tue, 3 Sep 2019 11:45:35 +0300 Subject: [PATCH 022/227] indents correction --- targets/TARGET_STM/PinNamesTypes.h | 36 +++++++++++++++--------------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/targets/TARGET_STM/PinNamesTypes.h b/targets/TARGET_STM/PinNamesTypes.h index f4067dc3bc9..37108e53e1d 100644 --- a/targets/TARGET_STM/PinNamesTypes.h +++ b/targets/TARGET_STM/PinNamesTypes.h @@ -90,30 +90,30 @@ extern "C" { #define STM_PIN_ANALOG_CONTROL(X) (((X) >> STM_PIN_AN_CTRL_SHIFT) & STM_PIN_AN_CTRL_MASK) #define STM_PIN_DEFINE(FUNC_OD, PUPD, AFNUM) ((int)(FUNC_OD) |\ - ((STM_PIN_SPEED_MASK & STM_PIN_SPEED_MASK) << STM_PIN_SPEED_SHIFT) |\ - (((PUPD) & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\ - (((AFNUM) & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT)) + ((STM_PIN_SPEED_MASK & STM_PIN_SPEED_MASK) << STM_PIN_SPEED_SHIFT) |\ + (((PUPD) & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\ + (((AFNUM) & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT)) #define STM_PIN_DEFINE_SPEED(FUNC_OD, PUPD, AFNUM, SPEEDV) ((int)(FUNC_OD) |\ - (((SPEEDV) & STM_PIN_SPEED_MASK) << STM_PIN_SPEED_SHIFT) |\ - (((PUPD) & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\ - (((AFNUM) & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT)) + (((SPEEDV) & STM_PIN_SPEED_MASK) << STM_PIN_SPEED_SHIFT) |\ + (((PUPD) & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\ + (((AFNUM) & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT)) #define STM_PIN_DEFINE_EXT(FUNC_OD, PUPD, AFNUM, CHAN, INV) \ - ((int)(FUNC_OD) |\ - ((STM_PIN_SPEED_MASK & STM_PIN_SPEED_MASK) << STM_PIN_SPEED_SHIFT) |\ - (((PUPD) & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\ - (((AFNUM) & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT) |\ - (((CHAN) & STM_PIN_CHAN_MASK) << STM_PIN_CHAN_SHIFT) |\ - (((INV) & STM_PIN_INV_MASK) << STM_PIN_INV_SHIFT)) + ((int)(FUNC_OD) |\ + ((STM_PIN_SPEED_MASK & STM_PIN_SPEED_MASK) << STM_PIN_SPEED_SHIFT) |\ + (((PUPD) & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\ + (((AFNUM) & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT) |\ + (((CHAN) & STM_PIN_CHAN_MASK) << STM_PIN_CHAN_SHIFT) |\ + (((INV) & STM_PIN_INV_MASK) << STM_PIN_INV_SHIFT)) #define STM_PIN_DEFINE_SPEED_EXT(FUNC_OD, PUPD, AFNUM, CHAN, INV, SPEEDV) \ - ((int)(FUNC_OD) |\ - (((SPEEDV) & STM_PIN_SPEED_MASK) << STM_PIN_SPEED_SHIFT) |\ - (((PUPD) & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\ - (((AFNUM) & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT) |\ - (((CHAN) & STM_PIN_CHAN_MASK) << STM_PIN_CHAN_SHIFT) |\ - (((INV) & STM_PIN_INV_MASK) << STM_PIN_INV_SHIFT)) + ((int)(FUNC_OD) |\ + (((SPEEDV) & STM_PIN_SPEED_MASK) << STM_PIN_SPEED_SHIFT) |\ + (((PUPD) & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\ + (((AFNUM) & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT) |\ + (((CHAN) & STM_PIN_CHAN_MASK) << STM_PIN_CHAN_SHIFT) |\ + (((INV) & STM_PIN_INV_MASK) << STM_PIN_INV_SHIFT)) /* * MACROS to support the legacy definition of PIN formats From 8d734ee055709c472ea4e5609af19fe0d7353443 Mon Sep 17 00:00:00 2001 From: "dolphin\\\\gena" Date: Tue, 3 Sep 2019 11:47:52 +0300 Subject: [PATCH 023/227] bad formatting correction --- targets/TARGET_STM/PinNamesTypes.h | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/targets/TARGET_STM/PinNamesTypes.h b/targets/TARGET_STM/PinNamesTypes.h index 37108e53e1d..e88cee4c7cd 100644 --- a/targets/TARGET_STM/PinNamesTypes.h +++ b/targets/TARGET_STM/PinNamesTypes.h @@ -90,30 +90,30 @@ extern "C" { #define STM_PIN_ANALOG_CONTROL(X) (((X) >> STM_PIN_AN_CTRL_SHIFT) & STM_PIN_AN_CTRL_MASK) #define STM_PIN_DEFINE(FUNC_OD, PUPD, AFNUM) ((int)(FUNC_OD) |\ - ((STM_PIN_SPEED_MASK & STM_PIN_SPEED_MASK) << STM_PIN_SPEED_SHIFT) |\ - (((PUPD) & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\ + ((STM_PIN_SPEED_MASK & STM_PIN_SPEED_MASK) << STM_PIN_SPEED_SHIFT) |\ + (((PUPD) & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\ (((AFNUM) & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT)) #define STM_PIN_DEFINE_SPEED(FUNC_OD, PUPD, AFNUM, SPEEDV) ((int)(FUNC_OD) |\ - (((SPEEDV) & STM_PIN_SPEED_MASK) << STM_PIN_SPEED_SHIFT) |\ - (((PUPD) & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\ + (((SPEEDV) & STM_PIN_SPEED_MASK) << STM_PIN_SPEED_SHIFT) |\ + (((PUPD) & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\ (((AFNUM) & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT)) #define STM_PIN_DEFINE_EXT(FUNC_OD, PUPD, AFNUM, CHAN, INV) \ ((int)(FUNC_OD) |\ ((STM_PIN_SPEED_MASK & STM_PIN_SPEED_MASK) << STM_PIN_SPEED_SHIFT) |\ - (((PUPD) & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\ - (((AFNUM) & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT) |\ - (((CHAN) & STM_PIN_CHAN_MASK) << STM_PIN_CHAN_SHIFT) |\ - (((INV) & STM_PIN_INV_MASK) << STM_PIN_INV_SHIFT)) + (((PUPD) & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\ + (((AFNUM) & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT) |\ + (((CHAN) & STM_PIN_CHAN_MASK) << STM_PIN_CHAN_SHIFT) |\ + (((INV) & STM_PIN_INV_MASK) << STM_PIN_INV_SHIFT)) #define STM_PIN_DEFINE_SPEED_EXT(FUNC_OD, PUPD, AFNUM, CHAN, INV, SPEEDV) \ ((int)(FUNC_OD) |\ - (((SPEEDV) & STM_PIN_SPEED_MASK) << STM_PIN_SPEED_SHIFT) |\ - (((PUPD) & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\ - (((AFNUM) & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT) |\ - (((CHAN) & STM_PIN_CHAN_MASK) << STM_PIN_CHAN_SHIFT) |\ - (((INV) & STM_PIN_INV_MASK) << STM_PIN_INV_SHIFT)) + (((SPEEDV) & STM_PIN_SPEED_MASK) << STM_PIN_SPEED_SHIFT) |\ + (((PUPD) & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\ + (((AFNUM) & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT) |\ + (((CHAN) & STM_PIN_CHAN_MASK) << STM_PIN_CHAN_SHIFT) |\ + (((INV) & STM_PIN_INV_MASK) << STM_PIN_INV_SHIFT)) /* * MACROS to support the legacy definition of PIN formats From 6176f066f4c6d32924603ce0c2d0e766ede4bb84 Mon Sep 17 00:00:00 2001 From: "dolphin\\\\gena" Date: Tue, 3 Sep 2019 12:03:04 +0300 Subject: [PATCH 024/227] formatting --- targets/TARGET_STM/PinNamesTypes.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/TARGET_STM/PinNamesTypes.h b/targets/TARGET_STM/PinNamesTypes.h index e88cee4c7cd..9e75beeff57 100644 --- a/targets/TARGET_STM/PinNamesTypes.h +++ b/targets/TARGET_STM/PinNamesTypes.h @@ -101,7 +101,7 @@ extern "C" { #define STM_PIN_DEFINE_EXT(FUNC_OD, PUPD, AFNUM, CHAN, INV) \ ((int)(FUNC_OD) |\ - ((STM_PIN_SPEED_MASK & STM_PIN_SPEED_MASK) << STM_PIN_SPEED_SHIFT) |\ + ((STM_PIN_SPEED_MASK & STM_PIN_SPEED_MASK) << STM_PIN_SPEED_SHIFT) |\ (((PUPD) & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\ (((AFNUM) & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT) |\ (((CHAN) & STM_PIN_CHAN_MASK) << STM_PIN_CHAN_SHIFT) |\ From 639ee4b3b490069b39e0127623451dd14ea6270c Mon Sep 17 00:00:00 2001 From: Hugues Kamba Date: Mon, 2 Sep 2019 15:15:14 +0100 Subject: [PATCH 025/227] Cast void pointer before deallocating with delete[] The stack memory is a `void*` which creates a warning when using the `delete[]` operator because it is unable to call the destructor of of an unknown object type. --- rtos/source/Thread.cpp | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/rtos/source/Thread.cpp b/rtos/source/Thread.cpp index 0d43391e495..94f1fdb3666 100644 --- a/rtos/source/Thread.cpp +++ b/rtos/source/Thread.cpp @@ -113,7 +113,8 @@ osStatus Thread::start(mbed::Callback task) _tid = osThreadNew(Thread::_thunk, this, &_attr); if (_tid == nullptr) { if (_dynamic_stack) { - delete[] _attr.stack_mem; + // Cast before deallocation as delete[] does not accept void* + delete[] static_cast(_attr.stack_mem); _attr.stack_mem = nullptr; } _mutex.unlock(); @@ -417,7 +418,8 @@ Thread::~Thread() // terminate is thread safe terminate(); if (_dynamic_stack) { - delete[] _attr.stack_mem; + // Cast before deallocation as delete[] does not accept void* + delete[] static_cast(_attr.stack_mem); _attr.stack_mem = nullptr; } } From 99cbd6fe3cc8512fe78c70306d4b96b145134c2f Mon Sep 17 00:00:00 2001 From: Chun-Chieh Li Date: Tue, 20 Aug 2019 16:24:01 +0800 Subject: [PATCH 026/227] M263: Force enum PinName to 32-bit NU_PINNAME_BIND(...) requires enum PinName to be 32-bit to encode module binding information in it. --- targets/TARGET_NUVOTON/TARGET_M261/PinNames.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/targets/TARGET_NUVOTON/TARGET_M261/PinNames.h b/targets/TARGET_NUVOTON/TARGET_M261/PinNames.h index 3b3f428e9da..b35b7d78a1f 100644 --- a/targets/TARGET_NUVOTON/TARGET_M261/PinNames.h +++ b/targets/TARGET_NUVOTON/TARGET_M261/PinNames.h @@ -135,6 +135,9 @@ typedef enum { BUTTON1 = SW2, BUTTON2 = SW3, + // Force PinName to 32-bit required by NU_PINNAME_BIND(...) + FORCE_ENUM_PINNAME_32BIT = 0x7FFFFFFF, + } PinName; #ifdef __cplusplus From 668d3b077e4a89a6a1a26b86af913efc13e1c5f8 Mon Sep 17 00:00:00 2001 From: Chun-Chieh Li Date: Tue, 20 Aug 2019 16:27:47 +0800 Subject: [PATCH 027/227] M263: Exclude USB UART from testing USB UART is dedicated to USB COM and so must exclude from FPGA CI testing. --- targets/TARGET_NUVOTON/TARGET_M261/pinmap.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/targets/TARGET_NUVOTON/TARGET_M261/pinmap.c b/targets/TARGET_NUVOTON/TARGET_M261/pinmap.c index 0cdfb931c62..5c49354bb7c 100644 --- a/targets/TARGET_NUVOTON/TARGET_M261/pinmap.c +++ b/targets/TARGET_NUVOTON/TARGET_M261/pinmap.c @@ -18,6 +18,7 @@ #include "mbed_assert.h" #include "pinmap.h" #include "PortNames.h" +#include "PeripheralNames.h" #include "mbed_error.h" /** @@ -83,3 +84,17 @@ void pin_mode(PinName pin, PinMode mode) */ } +/* List of peripherals excluded from testing */ +const PeripheralList *pinmap_restricted_peripherals() +{ + static const int perifs[] = { + STDIO_UART // Dedicated to USB VCOM + }; + + static const PeripheralList peripheral_list = { + sizeof(perifs) / sizeof(perifs[0]), + perifs + }; + + return &peripheral_list; +} From d6172f0227c8d1d3dd0b0aa63587d22567b76585 Mon Sep 17 00:00:00 2001 From: Chun-Chieh Li Date: Tue, 20 Aug 2019 16:52:05 +0800 Subject: [PATCH 028/227] M263: Fix IP initialization sequence Better IP initialization sequence: 1. Configure IP pins 2. Select IP clock source and then enable it 3. Reset the IP (SYS_ResetModule) NOTE1: IP reset takes effect regardless of IP clock. So it doesn't matter if IP clock enable is before IP reset. NOTE2: Non-configured pins may disturb IP's state, so IP pinout first and then IP reset. NOTE3: IP reset at the end of IP initialization sequence can cover unexpected situation. --- targets/TARGET_NUVOTON/TARGET_M261/analogin_api.c | 12 ++++++------ targets/TARGET_NUVOTON/TARGET_M261/analogout_api.c | 14 +++++++------- targets/TARGET_NUVOTON/TARGET_M261/dma_api.c | 6 +++--- targets/TARGET_NUVOTON/TARGET_M261/i2c_api.c | 8 ++++---- targets/TARGET_NUVOTON/TARGET_M261/lp_ticker.c | 12 ++++++------ targets/TARGET_NUVOTON/TARGET_M261/pwmout_api.c | 14 +++++++------- targets/TARGET_NUVOTON/TARGET_M261/serial_api.c | 8 ++++---- targets/TARGET_NUVOTON/TARGET_M261/spi_api.c | 12 ++++++------ targets/TARGET_NUVOTON/TARGET_M261/us_ticker.c | 6 +++--- 9 files changed, 46 insertions(+), 46 deletions(-) diff --git a/targets/TARGET_NUVOTON/TARGET_M261/analogin_api.c b/targets/TARGET_NUVOTON/TARGET_M261/analogin_api.c index 610b3743dcc..e5a07618ba1 100644 --- a/targets/TARGET_NUVOTON/TARGET_M261/analogin_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M261/analogin_api.c @@ -54,28 +54,28 @@ void analogin_init(analogin_t *obj, PinName pin) MBED_ASSERT(modinit != NULL); MBED_ASSERT(modinit->modname == (int) obj->adc); + // Wire pinout + pinmap_pinout(pin, PinMap_ADC); + EADC_T *eadc_base = (EADC_T *) NU_MODBASE(obj->adc); // NOTE: All channels (identified by ADCName) share a ADC module. This reset will also affect other channels of the same ADC module. if (! eadc_modinit_mask) { - // Reset module - SYS_ResetModule(modinit->rsetidx); - // Select IP clock source CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv); // Enable IP clock CLK_EnableModuleClock(modinit->clkidx); + // Reset module + SYS_ResetModule(modinit->rsetidx); + // Set the ADC internal sampling time, input mode as single-end and enable the A/D converter EADC_Open(eadc_base, EADC_CTL_DIFFEN_SINGLE_END); } uint32_t chn = NU_MODSUBINDEX(obj->adc); - // Wire pinout - pinmap_pinout(pin, PinMap_ADC); - // Configure the sample module Nmod for analog input channel Nch and software trigger source EADC_ConfigSampleModule(eadc_base, chn, EADC_SOFTWARE_TRIGGER, chn); diff --git a/targets/TARGET_NUVOTON/TARGET_M261/analogout_api.c b/targets/TARGET_NUVOTON/TARGET_M261/analogout_api.c index 2b9b9bb5cac..ebaa997afee 100644 --- a/targets/TARGET_NUVOTON/TARGET_M261/analogout_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M261/analogout_api.c @@ -53,6 +53,9 @@ void analogout_init(dac_t *obj, PinName pin) uint32_t chn = NU_MODSUBINDEX(obj->dac); MBED_ASSERT(chn < NU_DACCHN_MAXNUM); + /* Wire pinout */ + pinmap_pinout(pin, PinMap_DAC); + DAC_T *dac_base = (DAC_T *) NU_MODBASE(obj->dac); /* Module-level setup from here */ @@ -66,15 +69,15 @@ void analogout_init(dac_t *obj, PinName pin) * channels are deactivated. */ if ((! dac_modinit_mask[0]) && (! dac_modinit_mask[1])) { - // Reset IP - SYS_ResetModule(modinit->rsetidx); - // Select IP clock source and clock divider CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv); // Enable IP clock CLK_EnableModuleClock(modinit->clkidx); - + + // Reset IP + SYS_ResetModule(modinit->rsetidx); + /* The conversion settling time is 8us when 12-bit input code transition from * lowest code (0x000) to highest code (0xFFF). */ DAC_SetDelayTime(dac_base, 8); @@ -88,9 +91,6 @@ void analogout_init(dac_t *obj, PinName pin) /* Set the software trigger, enable DAC event trigger mode and enable D/A converter */ DAC_Open(dac_base, chn, DAC_SOFTWARE_TRIGGER); - - /* Wire pinout */ - pinmap_pinout(pin, PinMap_DAC); /* Mark channel allocated */ dac_modinit_mask[modidx] |= 1 << chn; diff --git a/targets/TARGET_NUVOTON/TARGET_M261/dma_api.c b/targets/TARGET_NUVOTON/TARGET_M261/dma_api.c index 1e0beeea496..c7fd12486d6 100644 --- a/targets/TARGET_NUVOTON/TARGET_M261/dma_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M261/dma_api.c @@ -54,12 +54,12 @@ void dma_init(void) dma_chn_mask = ~NU_PDMA_CH_Msk; memset(dma_chn_arr, 0x00, sizeof (dma_chn_arr)); - // Reset module - SYS_ResetModule(dma_modinit.rsetidx); - // Enable IP clock CLK_EnableModuleClock(dma_modinit.clkidx); + // Reset module + SYS_ResetModule(dma_modinit.rsetidx); + /* Check PDMA0. */ PDMA_T *pdma_base = dma_modbase(); if (((uint32_t) pdma_base) != PDMA0_BASE) { diff --git a/targets/TARGET_NUVOTON/TARGET_M261/i2c_api.c b/targets/TARGET_NUVOTON/TARGET_M261/i2c_api.c index c86b3227338..26affe8b903 100644 --- a/targets/TARGET_NUVOTON/TARGET_M261/i2c_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M261/i2c_api.c @@ -103,14 +103,14 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) MBED_ASSERT(modinit != NULL); MBED_ASSERT(modinit->modname == (int) obj->i2c.i2c); - // Reset module - SYS_ResetModule(modinit->rsetidx); + pinmap_pinout(sda, PinMap_I2C_SDA); + pinmap_pinout(scl, PinMap_I2C_SCL); // Select IP clock source CLK_EnableModuleClock(modinit->clkidx); - pinmap_pinout(sda, PinMap_I2C_SDA); - pinmap_pinout(scl, PinMap_I2C_SCL); + // Reset module + SYS_ResetModule(modinit->rsetidx); #if DEVICE_I2C_ASYNCH obj->i2c.dma_usage = DMA_USAGE_NEVER; diff --git a/targets/TARGET_NUVOTON/TARGET_M261/lp_ticker.c b/targets/TARGET_NUVOTON/TARGET_M261/lp_ticker.c index 917e48aae2c..379b3ef7dab 100644 --- a/targets/TARGET_NUVOTON/TARGET_M261/lp_ticker.c +++ b/targets/TARGET_NUVOTON/TARGET_M261/lp_ticker.c @@ -82,12 +82,6 @@ void lp_ticker_init(void) } ticker_inited = 1; - /* Reset module - * - * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. - */ - SYS_ResetModule(TIMER_MODINIT.rsetidx); - /* Select IP clock source * * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. @@ -100,6 +94,12 @@ void lp_ticker_init(void) */ CLK_EnableModuleClock(TIMER_MODINIT.clkidx); + /* Reset module + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + SYS_ResetModule(TIMER_MODINIT.rsetidx); + TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); // Configure clock diff --git a/targets/TARGET_NUVOTON/TARGET_M261/pwmout_api.c b/targets/TARGET_NUVOTON/TARGET_M261/pwmout_api.c index 249c0ed1eee..5305557186f 100644 --- a/targets/TARGET_NUVOTON/TARGET_M261/pwmout_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M261/pwmout_api.c @@ -69,11 +69,8 @@ void pwmout_init(pwmout_t* obj, PinName pin) MBED_ASSERT(modinit != NULL); MBED_ASSERT(modinit->modname == (int) obj->pwm); - // NOTE: All channels (identified by PWMName) share a PWM module. This reset will also affect other channels of the same PWM module. - if (! ((struct nu_pwm_var *) modinit->var)->en_msk) { - // Reset this module if no channel enabled - SYS_ResetModule(modinit->rsetidx); - } + // Wire pinout + pinmap_pinout(pin, PinMap_PWM); uint32_t chn = NU_MODSUBINDEX(obj->pwm); @@ -85,8 +82,11 @@ void pwmout_init(pwmout_t* obj, PinName pin) CLK_EnableModuleClock(modinit->clkidx); } - // Wire pinout - pinmap_pinout(pin, PinMap_PWM); + // NOTE: All channels (identified by PWMName) share a PWM module. This reset will also affect other channels of the same PWM module. + if (! ((struct nu_pwm_var *) modinit->var)->en_msk) { + // Reset this module if no channel enabled + SYS_ResetModule(modinit->rsetidx); + } // Default: period = 10 ms, pulse width = 0 ms obj->period_us = 1000 * 10; diff --git a/targets/TARGET_NUVOTON/TARGET_M261/serial_api.c b/targets/TARGET_NUVOTON/TARGET_M261/serial_api.c index 5252cb04c64..b85feb5d3e6 100644 --- a/targets/TARGET_NUVOTON/TARGET_M261/serial_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M261/serial_api.c @@ -201,16 +201,16 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; if (! var->ref_cnt) { - // Reset this module - SYS_ResetModule(modinit->rsetidx); + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); // Select IP clock source CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv); // Enable IP clock CLK_EnableModuleClock(modinit->clkidx); - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); + // Reset this module + SYS_ResetModule(modinit->rsetidx); // Configure baudrate int baudrate = 9600; diff --git a/targets/TARGET_NUVOTON/TARGET_M261/spi_api.c b/targets/TARGET_NUVOTON/TARGET_M261/spi_api.c index a59288a7069..9a89bb03f20 100644 --- a/targets/TARGET_NUVOTON/TARGET_M261/spi_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M261/spi_api.c @@ -141,18 +141,18 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel MBED_ASSERT(modinit != NULL); MBED_ASSERT(modinit->modname == (int) obj->spi.spi); - // Reset this module - SYS_ResetModule(modinit->rsetidx); + pinmap_pinout(mosi, PinMap_SPI_MOSI); + pinmap_pinout(miso, PinMap_SPI_MISO); + pinmap_pinout(sclk, PinMap_SPI_SCLK); + pinmap_pinout(ssel, PinMap_SPI_SSEL); // Select IP clock source CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv); // Enable IP clock CLK_EnableModuleClock(modinit->clkidx); - pinmap_pinout(mosi, PinMap_SPI_MOSI); - pinmap_pinout(miso, PinMap_SPI_MISO); - pinmap_pinout(sclk, PinMap_SPI_SCLK); - pinmap_pinout(ssel, PinMap_SPI_SSEL); + // Reset this module + SYS_ResetModule(modinit->rsetidx); obj->spi.pin_mosi = mosi; obj->spi.pin_miso = miso; diff --git a/targets/TARGET_NUVOTON/TARGET_M261/us_ticker.c b/targets/TARGET_NUVOTON/TARGET_M261/us_ticker.c index 76ca991f4d7..f309aa0cd9f 100644 --- a/targets/TARGET_NUVOTON/TARGET_M261/us_ticker.c +++ b/targets/TARGET_NUVOTON/TARGET_M261/us_ticker.c @@ -57,15 +57,15 @@ void us_ticker_init(void) } ticker_inited = 1; - // Reset IP - SYS_ResetModule(TIMER_MODINIT.rsetidx); - // Select IP clock source CLK_SetModuleClock(TIMER_MODINIT.clkidx, TIMER_MODINIT.clksrc, TIMER_MODINIT.clkdiv); // Enable IP clock CLK_EnableModuleClock(TIMER_MODINIT.clkidx); + // Reset IP + SYS_ResetModule(TIMER_MODINIT.rsetidx); + TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); // Timer for normal counter From 8cd1f10b25f5fa66193729b570f921060e118313 Mon Sep 17 00:00:00 2001 From: Chun-Chieh Li Date: Tue, 20 Aug 2019 17:08:20 +0800 Subject: [PATCH 029/227] M263: Fix I2C NACK error Fix logic error on replying NACK at the end of transfer. This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-i2c/ i2c - test single byte read i2c API. --- targets/TARGET_NUVOTON/TARGET_M261/i2c_api.c | 34 ++++++++++++++++---- 1 file changed, 28 insertions(+), 6 deletions(-) diff --git a/targets/TARGET_NUVOTON/TARGET_M261/i2c_api.c b/targets/TARGET_NUVOTON/TARGET_M261/i2c_api.c index 26affe8b903..b24c2bfbcb0 100644 --- a/targets/TARGET_NUVOTON/TARGET_M261/i2c_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M261/i2c_api.c @@ -86,9 +86,10 @@ static void i2c_enable_vector_interrupt(i2c_t *obj, uint32_t handler, int enable static void i2c_rollback_vector_interrupt(i2c_t *obj); #endif -#define TRANCTRL_STARTED (1) -#define TRANCTRL_NAKLASTDATA (1 << 1) -#define TRANCTRL_LASTDATANAKED (1 << 2) +#define TRANCTRL_STARTED (1) // Guard I2C ISR from data transfer prematurely +#define TRANCTRL_NAKLASTDATA (1 << 1) // Request NACK on last data +#define TRANCTRL_LASTDATANAKED (1 << 2) // Last data NACKed +#define TRANCTRL_RECVDATA (1 << 3) // Receive data available uint32_t us_ticker_read(void); @@ -592,11 +593,17 @@ static void i2c_irq(i2c_t *obj) if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) { if (obj->i2c.tran_pos < obj->i2c.tran_end) { if (status == 0x50 || status == 0x58) { - *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base); + if (obj->i2c.tran_ctrl & TRANCTRL_RECVDATA) { + *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base); + obj->i2c.tran_ctrl &= ~TRANCTRL_RECVDATA; + } } if (status == 0x58) { i2c_fsm_tranfini(obj, 1); + } else if (obj->i2c.tran_pos == obj->i2c.tran_end) { + obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED; + i2c_disable_int(obj); } else { uint32_t i2c_ctl = I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk; if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 && @@ -605,6 +612,7 @@ static void i2c_irq(i2c_t *obj) i2c_ctl &= ~I2C_CTL0_AA_Msk; } I2C_SET_CONTROL_REG(i2c_base, i2c_ctl); + obj->i2c.tran_ctrl |= TRANCTRL_RECVDATA; } } else { obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED; @@ -659,12 +667,18 @@ static void i2c_irq(i2c_t *obj) if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) { if (obj->i2c.tran_pos < obj->i2c.tran_end) { if (status == 0x80 || status == 0x88) { - *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base); + if (obj->i2c.tran_ctrl & TRANCTRL_RECVDATA) { + *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base); + obj->i2c.tran_ctrl &= ~TRANCTRL_RECVDATA; + } } if (status == 0x88) { obj->i2c.slaveaddr_state = NoData; i2c_fsm_reset(obj, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk); + } else if (obj->i2c.tran_pos == obj->i2c.tran_end) { + obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED; + i2c_disable_int(obj); } else { uint32_t i2c_ctl = I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk; if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 && @@ -673,6 +687,7 @@ static void i2c_irq(i2c_t *obj) i2c_ctl &= ~I2C_CTL0_AA_Msk; } I2C_SET_CONTROL_REG(i2c_base, i2c_ctl); + obj->i2c.tran_ctrl |= TRANCTRL_RECVDATA; } } else { obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED; @@ -695,12 +710,18 @@ static void i2c_irq(i2c_t *obj) if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) { if (obj->i2c.tran_pos < obj->i2c.tran_end) { if (status == 0x90 || status == 0x98) { - *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base); + if (obj->i2c.tran_ctrl & TRANCTRL_RECVDATA) { + *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base); + obj->i2c.tran_ctrl &= ~TRANCTRL_RECVDATA; + } } if (status == 0x98) { obj->i2c.slaveaddr_state = NoData; i2c_fsm_reset(obj, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk); + } else if (obj->i2c.tran_pos == obj->i2c.tran_end) { + obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED; + i2c_disable_int(obj); } else { uint32_t i2c_ctl = I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk; if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 && @@ -709,6 +730,7 @@ static void i2c_irq(i2c_t *obj) i2c_ctl &= ~I2C_CTL0_AA_Msk; } I2C_SET_CONTROL_REG(i2c_base, i2c_ctl); + obj->i2c.tran_ctrl |= TRANCTRL_RECVDATA; } } else { obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED; From 950a586ad10e63a77395e275550c45f8e263e938 Mon Sep 17 00:00:00 2001 From: Chun-Chieh Li Date: Tue, 20 Aug 2019 17:17:59 +0800 Subject: [PATCH 030/227] M263: Fix redundant SPI clock generation Fix SPI clocks are generated redundantly at the end of transfer. This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-spi/ SPI - async mode. --- targets/TARGET_NUVOTON/TARGET_M261/objects.h | 2 +- targets/TARGET_NUVOTON/TARGET_M261/spi_api.c | 15 ++++++--------- 2 files changed, 7 insertions(+), 10 deletions(-) diff --git a/targets/TARGET_NUVOTON/TARGET_M261/objects.h b/targets/TARGET_NUVOTON/TARGET_M261/objects.h index f74210ec8cb..3b54a321ed8 100644 --- a/targets/TARGET_NUVOTON/TARGET_M261/objects.h +++ b/targets/TARGET_NUVOTON/TARGET_M261/objects.h @@ -85,7 +85,7 @@ struct spi_s { int dma_chn_id_tx; int dma_chn_id_rx; uint32_t event; - uint32_t hdlr_async; + uint32_t txrx_rmn; // Track tx/rx frames remaining in interrupt way }; struct i2c_s { diff --git a/targets/TARGET_NUVOTON/TARGET_M261/spi_api.c b/targets/TARGET_NUVOTON/TARGET_M261/spi_api.c index 9a89bb03f20..19c7ac89ec8 100644 --- a/targets/TARGET_NUVOTON/TARGET_M261/spi_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M261/spi_api.c @@ -388,6 +388,9 @@ void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, SPI_ENABLE_SYNC(spi_base); + // Initialize total SPI transfer frames + obj->spi.txrx_rmn = NU_MAX(tx_length, rx_length); + if (obj->spi.dma_usage == DMA_USAGE_NEVER) { // Interrupt way spi_master_write_asynch(obj, spi_fifo_depth(obj) / 2); @@ -658,16 +661,12 @@ static uint32_t spi_event_check(spi_t *obj) static uint32_t spi_master_write_asynch(spi_t *obj, uint32_t tx_limit) { uint32_t n_words = 0; - uint32_t tx_rmn = obj->tx_buff.length - obj->tx_buff.pos; - uint32_t rx_rmn = obj->rx_buff.length - obj->rx_buff.pos; - uint32_t max_tx = NU_MAX(tx_rmn, rx_rmn); - max_tx = NU_MIN(max_tx, tx_limit); uint8_t data_width = spi_get_data_width(obj); uint8_t bytes_per_word = (data_width + 7) / 8; uint8_t *tx = (uint8_t *)(obj->tx_buff.buffer) + bytes_per_word * obj->tx_buff.pos; SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); - while ((n_words < max_tx) && spi_writeable(obj)) { + while (obj->spi.txrx_rmn && spi_writeable(obj)) { if (spi_is_tx_complete(obj)) { // Transmit dummy as transmit buffer is empty SPI_WRITE_TX(spi_base, 0); @@ -690,6 +689,7 @@ static uint32_t spi_master_write_asynch(spi_t *obj, uint32_t tx_limit) obj->tx_buff.pos ++; } n_words ++; + obj->spi.txrx_rmn --; } //Return the number of words that have been sent @@ -710,15 +710,12 @@ static uint32_t spi_master_write_asynch(spi_t *obj, uint32_t tx_limit) static uint32_t spi_master_read_asynch(spi_t *obj) { uint32_t n_words = 0; - uint32_t tx_rmn = obj->tx_buff.length - obj->tx_buff.pos; - uint32_t rx_rmn = obj->rx_buff.length - obj->rx_buff.pos; - uint32_t max_rx = NU_MAX(tx_rmn, rx_rmn); uint8_t data_width = spi_get_data_width(obj); uint8_t bytes_per_word = (data_width + 7) / 8; uint8_t *rx = (uint8_t *)(obj->rx_buff.buffer) + bytes_per_word * obj->rx_buff.pos; SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); - while ((n_words < max_rx) && spi_readable(obj)) { + while (spi_readable(obj)) { if (spi_is_rx_complete(obj)) { // Disregard as receive buffer is full SPI_READ_RX(spi_base); From 826ad091a3705c087ef1a56ac0e169aff0c832ca Mon Sep 17 00:00:00 2001 From: Chun-Chieh Li Date: Tue, 20 Aug 2019 17:24:10 +0800 Subject: [PATCH 031/227] M263: Fix redundant call to UART IRQ handler Honor RxIrq/TxIrq to avoid redundant call to UART IRQ handler. This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-uart. --- targets/TARGET_NUVOTON/TARGET_M261/serial_api.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/targets/TARGET_NUVOTON/TARGET_M261/serial_api.c b/targets/TARGET_NUVOTON/TARGET_M261/serial_api.c index b85feb5d3e6..e38d4e90971 100644 --- a/targets/TARGET_NUVOTON/TARGET_M261/serial_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M261/serial_api.c @@ -86,9 +86,10 @@ static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable); static int serial_is_rx_complete(serial_t *obj); static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch); -static int serial_is_irq_en(serial_t *obj, SerialIrq irq); #endif +static int serial_is_irq_en(serial_t *obj, SerialIrq irq); + bool serial_can_deep_sleep(void); static struct nu_uart_var uart0_var = { @@ -519,7 +520,8 @@ static void uart_irq(serial_t *obj) if (uart_base->INTSTS & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) { // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next read. UART_DISABLE_INT(uart_base, (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); - if (obj->serial.irq_handler) { + if (obj->serial.irq_handler && serial_is_irq_en(obj, RxIrq)) { + // Call irq_handler() only when RxIrq is enabled ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, RxIrq); } } @@ -527,7 +529,8 @@ static void uart_irq(serial_t *obj) if (uart_base->INTSTS & UART_INTSTS_THREINT_Msk) { // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next write. UART_DISABLE_INT(uart_base, UART_INTEN_THREIEN_Msk); - if (obj->serial.irq_handler) { + if (obj->serial.irq_handler && serial_is_irq_en(obj, TxIrq)) { + // Call irq_handler() only when TxIrq is enabled ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, TxIrq); } } @@ -1167,6 +1170,8 @@ static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch) } } +#endif // #if DEVICE_SERIAL_ASYNCH + static int serial_is_irq_en(serial_t *obj, SerialIrq irq) { int inten_msk = 0; @@ -1183,8 +1188,6 @@ static int serial_is_irq_en(serial_t *obj, SerialIrq irq) return !! inten_msk; } -#endif // #if DEVICE_SERIAL_ASYNCH - bool serial_can_deep_sleep(void) { bool sleep_allowed = 1; From 863c2a77000bbdfa691a1bd7e9bbf90761e504f4 Mon Sep 17 00:00:00 2001 From: Chun-Chieh Li Date: Tue, 20 Aug 2019 17:37:08 +0800 Subject: [PATCH 032/227] M263: Support GPIO input pull-high/pull-low In Nuvoton, only new-design chips support GPIO input pull-high/pull-low modes. Targets not supporting this feature are listed below: - NUMAKER_PFM_NANO130 - NUMAKER_PFM_NUC472 - NUMAKER_PFM_M453 --- targets/TARGET_NUVOTON/TARGET_M261/gpio_api.c | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/targets/TARGET_NUVOTON/TARGET_M261/gpio_api.c b/targets/TARGET_NUVOTON/TARGET_M261/gpio_api.c index 0bbea6c95f7..7bc7cc34639 100644 --- a/targets/TARGET_NUVOTON/TARGET_M261/gpio_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M261/gpio_api.c @@ -63,10 +63,23 @@ void gpio_mode(gpio_t *obj, PinMode mode) return; } + uint32_t pin_index = NU_PININDEX(obj->pin); + uint32_t port_index = NU_PINPORT(obj->pin); + GPIO_T *gpio_base = NU_PORT_BASE(port_index); + switch (mode) { case PullNone: + if (mode == PullNone) { + GPIO_SetPullCtl(gpio_base, 1 << pin_index, GPIO_PUSEL_DISABLE); + } case PullDown: + if (mode == PullDown) { + GPIO_SetPullCtl(gpio_base, 1 << pin_index, GPIO_PUSEL_PULL_DOWN); + } case PullUp: + if (mode == PullUp) { + GPIO_SetPullCtl(gpio_base, 1 << pin_index, GPIO_PUSEL_PULL_UP); + } /* H/W doesn't support separate configuration for input pull mode/direction. * We translate to input-only/push-pull output I/O mode dependent on direction. */ obj->mode = (obj->direction == PIN_INPUT) ? InputOnly : PushPullOutput; @@ -111,10 +124,23 @@ void gpio_dir(gpio_t *obj, PinDirection direction) obj->direction = direction; + uint32_t pin_index = NU_PININDEX(obj->pin); + uint32_t port_index = NU_PINPORT(obj->pin); + GPIO_T *gpio_base = NU_PORT_BASE(port_index); + switch (obj->mode) { case PullNone: + if (obj->mode == PullNone) { + GPIO_SetPullCtl(gpio_base, 1 << pin_index, GPIO_PUSEL_DISABLE); + } case PullDown: + if (obj->mode == PullDown) { + GPIO_SetPullCtl(gpio_base, 1 << pin_index, GPIO_PUSEL_PULL_DOWN); + } case PullUp: + if (obj->mode == PullUp) { + GPIO_SetPullCtl(gpio_base, 1 << pin_index, GPIO_PUSEL_PULL_UP); + } /* H/W doesn't support separate configuration for input pull mode/direction. * We translate to input-only/push-pull output I/O mode dependent on direction. */ obj->mode = (obj->direction == PIN_INPUT) ? InputOnly : PushPullOutput; From 0722380f9a27b07c6b864293c647e50f06b7e3db Mon Sep 17 00:00:00 2001 From: Chun-Chieh Li Date: Tue, 20 Aug 2019 17:52:03 +0800 Subject: [PATCH 033/227] M263: Free up peripheral pins in peripheral free-up HAL API Without free-up of peripheral pins, peripheral pins of the same peripheral may share by multiple ports after port iteration, and this peripheral may fail with pin interference. --- .../TARGET_NUVOTON/TARGET_M261/analogin_api.c | 2 ++ .../TARGET_M261/analogout_api.c | 6 ++++ targets/TARGET_NUVOTON/TARGET_M261/i2c_api.c | 3 ++ targets/TARGET_NUVOTON/TARGET_M261/objects.h | 13 ++++++-- .../TARGET_NUVOTON/TARGET_M261/pwmout_api.c | 6 ++++ .../TARGET_NUVOTON/TARGET_M261/serial_api.c | 31 +++++++++++++++++-- targets/TARGET_NUVOTON/TARGET_M261/spi_api.c | 21 +++++++++---- 7 files changed, 71 insertions(+), 11 deletions(-) diff --git a/targets/TARGET_NUVOTON/TARGET_M261/analogin_api.c b/targets/TARGET_NUVOTON/TARGET_M261/analogin_api.c index e5a07618ba1..55fddb02a17 100644 --- a/targets/TARGET_NUVOTON/TARGET_M261/analogin_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M261/analogin_api.c @@ -54,6 +54,8 @@ void analogin_init(analogin_t *obj, PinName pin) MBED_ASSERT(modinit != NULL); MBED_ASSERT(modinit->modname == (int) obj->adc); + obj->pin = pin; + // Wire pinout pinmap_pinout(pin, PinMap_ADC); diff --git a/targets/TARGET_NUVOTON/TARGET_M261/analogout_api.c b/targets/TARGET_NUVOTON/TARGET_M261/analogout_api.c index ebaa997afee..f4554122e7f 100644 --- a/targets/TARGET_NUVOTON/TARGET_M261/analogout_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M261/analogout_api.c @@ -53,6 +53,8 @@ void analogout_init(dac_t *obj, PinName pin) uint32_t chn = NU_MODSUBINDEX(obj->dac); MBED_ASSERT(chn < NU_DACCHN_MAXNUM); + obj->pin = pin; + /* Wire pinout */ pinmap_pinout(pin, PinMap_DAC); @@ -128,6 +130,10 @@ void analogout_free(dac_t *obj) // Disable IP clock CLK_DisableModuleClock(modinit->clkidx); } + + // Free up pins + gpio_set(obj->pin); + obj->pin = NC; } void analogout_write(dac_t *obj, float value) diff --git a/targets/TARGET_NUVOTON/TARGET_M261/i2c_api.c b/targets/TARGET_NUVOTON/TARGET_M261/i2c_api.c index b24c2bfbcb0..41929021bd7 100644 --- a/targets/TARGET_NUVOTON/TARGET_M261/i2c_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M261/i2c_api.c @@ -104,6 +104,9 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) MBED_ASSERT(modinit != NULL); MBED_ASSERT(modinit->modname == (int) obj->i2c.i2c); + obj->i2c.pin_sda = sda; + obj->i2c.pin_scl = scl; + pinmap_pinout(sda, PinMap_I2C_SDA); pinmap_pinout(scl, PinMap_I2C_SCL); diff --git a/targets/TARGET_NUVOTON/TARGET_M261/objects.h b/targets/TARGET_NUVOTON/TARGET_M261/objects.h index 3b54a321ed8..fc22f7a28cb 100644 --- a/targets/TARGET_NUVOTON/TARGET_M261/objects.h +++ b/targets/TARGET_NUVOTON/TARGET_M261/objects.h @@ -43,15 +43,21 @@ struct port_s { struct analogin_s { ADCName adc; + PinName pin; }; struct dac_s { DACName dac; + PinName pin; }; struct serial_s { UARTName uart; - + PinName pin_tx; + PinName pin_rx; + PinName pin_rts; + PinName pin_cts; + uint32_t baudrate; uint32_t databits; uint32_t parity; @@ -90,8 +96,10 @@ struct spi_s { struct i2c_s { I2CName i2c; + PinName pin_sda; + PinName pin_scl; int slaveaddr_state; - + uint32_t tran_ctrl; char * tran_beg; char * tran_pos; @@ -108,6 +116,7 @@ struct i2c_s { struct pwmout_s { PWMName pwm; + PinName pin; uint32_t period_us; uint32_t pulsewidth_us; }; diff --git a/targets/TARGET_NUVOTON/TARGET_M261/pwmout_api.c b/targets/TARGET_NUVOTON/TARGET_M261/pwmout_api.c index 5305557186f..4ad6deb2629 100644 --- a/targets/TARGET_NUVOTON/TARGET_M261/pwmout_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M261/pwmout_api.c @@ -69,6 +69,8 @@ void pwmout_init(pwmout_t* obj, PinName pin) MBED_ASSERT(modinit != NULL); MBED_ASSERT(modinit->modname == (int) obj->pwm); + obj->pin = pin; + // Wire pinout pinmap_pinout(pin, PinMap_PWM); @@ -119,6 +121,10 @@ void pwmout_free(pwmout_t* obj) // Mark this module to be deinited. int i = modinit - pwm_modinit_tab; pwm_modinit_mask &= ~(1 << i); + + // Free up pins + gpio_set(obj->pin); + obj->pin = NC; } void pwmout_write(pwmout_t* obj, float value) diff --git a/targets/TARGET_NUVOTON/TARGET_M261/serial_api.c b/targets/TARGET_NUVOTON/TARGET_M261/serial_api.c index e38d4e90971..a57c20204d4 100644 --- a/targets/TARGET_NUVOTON/TARGET_M261/serial_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M261/serial_api.c @@ -201,10 +201,15 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; - if (! var->ref_cnt) { - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); + obj->serial.pin_tx = tx; + obj->serial.pin_rx = rx; + obj->serial.pin_rts = NC; + obj->serial.pin_cts = NC; + + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + if (! var->ref_cnt) { // Select IP clock source CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv); // Enable IP clock @@ -304,6 +309,16 @@ void serial_free(serial_t *obj) int i = modinit - uart_modinit_tab; uart_modinit_mask &= ~(1 << i); } + + // Free up pins + gpio_set(obj->serial.pin_tx); + gpio_set(obj->serial.pin_rx); + gpio_set(obj->serial.pin_rts); + gpio_set(obj->serial.pin_cts); + obj->serial.pin_tx = NC; + obj->serial.pin_rx = NC; + obj->serial.pin_rts = NC; + obj->serial.pin_cts = NC; } void serial_baud(serial_t *obj, int baudrate) @@ -350,6 +365,16 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi { UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart); + // Free up old rts/cts pins when they are different from new ones + if (obj->serial.pin_rts != rxflow) { + gpio_set(obj->serial.pin_rts); + obj->serial.pin_rts = rxflow; + } + if (obj->serial.pin_cts != txflow) { + gpio_set(obj->serial.pin_cts); + obj->serial.pin_cts = txflow; + } + if (rxflow != NC) { // Check if RTS pin matches. uint32_t uart_rts = pinmap_peripheral(rxflow, PinMap_UART_RTS); diff --git a/targets/TARGET_NUVOTON/TARGET_M261/spi_api.c b/targets/TARGET_NUVOTON/TARGET_M261/spi_api.c index 19c7ac89ec8..e41583f566f 100644 --- a/targets/TARGET_NUVOTON/TARGET_M261/spi_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M261/spi_api.c @@ -141,6 +141,11 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel MBED_ASSERT(modinit != NULL); MBED_ASSERT(modinit->modname == (int) obj->spi.spi); + obj->spi.pin_mosi = mosi; + obj->spi.pin_miso = miso; + obj->spi.pin_sclk = sclk; + obj->spi.pin_ssel = ssel; + pinmap_pinout(mosi, PinMap_SPI_MOSI); pinmap_pinout(miso, PinMap_SPI_MISO); pinmap_pinout(sclk, PinMap_SPI_SCLK); @@ -154,12 +159,6 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel // Reset this module SYS_ResetModule(modinit->rsetidx); - obj->spi.pin_mosi = mosi; - obj->spi.pin_miso = miso; - obj->spi.pin_sclk = sclk; - obj->spi.pin_ssel = ssel; - - #if DEVICE_SPI_ASYNCH obj->spi.dma_usage = DMA_USAGE_NEVER; obj->spi.event = 0; @@ -205,6 +204,16 @@ void spi_free(spi_t *obj) // Mark this module to be deinited. int i = modinit - spi_modinit_tab; spi_modinit_mask &= ~(1 << i); + + // Free up pins + gpio_set(obj->spi.pin_mosi); + gpio_set(obj->spi.pin_miso); + gpio_set(obj->spi.pin_sclk); + gpio_set(obj->spi.pin_ssel); + obj->spi.pin_mosi = NC; + obj->spi.pin_miso = NC; + obj->spi.pin_sclk = NC; + obj->spi.pin_ssel = NC; } void spi_format(spi_t *obj, int bits, int mode, int slave) From ef8474de46360ed09e99d7532935f693e875792b Mon Sep 17 00:00:00 2001 From: Chun-Chieh Li Date: Thu, 22 Aug 2019 11:07:28 +0800 Subject: [PATCH 034/227] M263: Remove redundant SPI I2S pins from pinmap The pins suffixed with 'I2SMCLK' are for SPI I2S and cannot be used in normal SPI. This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-spi. --- .../TARGET_M261/PeripheralPins.c | 58 ++++++------------- 1 file changed, 18 insertions(+), 40 deletions(-) diff --git a/targets/TARGET_NUVOTON/TARGET_M261/PeripheralPins.c b/targets/TARGET_NUVOTON/TARGET_M261/PeripheralPins.c index f5cbda3d592..7e088cc7367 100644 --- a/targets/TARGET_NUVOTON/TARGET_M261/PeripheralPins.c +++ b/targets/TARGET_NUVOTON/TARGET_M261/PeripheralPins.c @@ -43,7 +43,7 @@ const PinMap PinMap_GPIO[] = { {PA_13, GPIO_A, SYS_GPA_MFPH_PA13MFP_GPIO}, {PA_14, GPIO_A, SYS_GPA_MFPH_PA14MFP_GPIO}, {PA_15, GPIO_A, SYS_GPA_MFPH_PA15MFP_GPIO}, - + // GPIO B MFP {PB_0, GPIO_B, SYS_GPB_MFPL_PB0MFP_GPIO}, {PB_1, GPIO_B, SYS_GPB_MFPL_PB1MFP_GPIO}, @@ -61,7 +61,7 @@ const PinMap PinMap_GPIO[] = { {PB_13, GPIO_B, SYS_GPB_MFPH_PB13MFP_GPIO}, {PB_14, GPIO_B, SYS_GPB_MFPH_PB14MFP_GPIO}, {PB_15, GPIO_B, SYS_GPB_MFPH_PB15MFP_GPIO}, - + // GPIO C MFP {PC_0, GPIO_C, SYS_GPC_MFPL_PC0MFP_GPIO}, {PC_1, GPIO_C, SYS_GPC_MFPL_PC1MFP_GPIO}, @@ -77,7 +77,7 @@ const PinMap PinMap_GPIO[] = { {PC_11, GPIO_C, SYS_GPC_MFPH_PC11MFP_GPIO}, {PC_12, GPIO_C, SYS_GPC_MFPH_PC12MFP_GPIO}, {PC_13, GPIO_C, SYS_GPC_MFPH_PC13MFP_GPIO}, - + // GPIO D MFP {PD_0, GPIO_D, SYS_GPD_MFPL_PD0MFP_GPIO}, {PD_1, GPIO_D, SYS_GPD_MFPL_PD1MFP_GPIO}, @@ -94,7 +94,7 @@ const PinMap PinMap_GPIO[] = { {PD_12, GPIO_D, SYS_GPD_MFPH_PD12MFP_GPIO}, {PD_13, GPIO_D, SYS_GPD_MFPH_PD13MFP_GPIO}, {PD_14, GPIO_D, SYS_GPD_MFPH_PD14MFP_GPIO}, - + // GPIO E MFP {PE_0, GPIO_E, SYS_GPE_MFPL_PE0MFP_GPIO}, {PE_1, GPIO_E, SYS_GPE_MFPL_PE1MFP_GPIO}, @@ -146,6 +146,7 @@ const PinMap PinMap_GPIO[] = { {PH_9, GPIO_H, SYS_GPH_MFPH_PH9MFP_GPIO}, {PH_10, GPIO_H, SYS_GPH_MFPH_PH10MFP_GPIO}, {PH_11, GPIO_H, SYS_GPH_MFPH_PH11MFP_GPIO}, + {NC, NC, 0} }; #endif @@ -169,7 +170,7 @@ const PinMap PinMap_ADC[] = { {PB_13, ADC_0_13, SYS_GPB_MFPH_PB13MFP_EADC0_CH13}, {PB_14, ADC_0_14, SYS_GPB_MFPH_PB14MFP_EADC0_CH14}, {PB_15, ADC_0_15, SYS_GPB_MFPH_PB15MFP_EADC0_CH15}, - + {NC, NC, 0} }; @@ -209,7 +210,7 @@ const PinMap PinMap_I2C_SDA[] = { {PF_2, I2C_0, SYS_GPF_MFPL_PF2MFP_I2C0_SDA}, {PG_3, I2C_1, SYS_GPG_MFPL_PG3MFP_I2C1_SDA}, {PH_9, I2C_2, SYS_GPH_MFPH_PH9MFP_I2C2_SDA}, - + {NC, NC, 0} }; @@ -238,7 +239,7 @@ const PinMap PinMap_I2C_SCL[] = { {PF_3, I2C_0, SYS_GPF_MFPL_PF3MFP_I2C0_SCL}, {PG_2, I2C_1, SYS_GPG_MFPL_PG2MFP_I2C1_SCL}, {PH_8, I2C_2, SYS_GPH_MFPH_PH8MFP_I2C2_SCL}, - + {NC, NC, 0} }; @@ -355,7 +356,7 @@ const PinMap PinMap_UART_TX[] = { {NU_PINNAME_BIND(PH_10, UART_0), UART_0, SYS_GPH_MFPH_PH10MFP_UART0_TXD}, {PH_10, UART_4, SYS_GPH_MFPH_PH10MFP_UART4_TXD}, {NU_PINNAME_BIND(PH_10, UART_4), UART_4, SYS_GPH_MFPH_PH10MFP_UART4_TXD}, - + {NC, NC, 0} }; @@ -407,7 +408,7 @@ const PinMap PinMap_UART_RX[] = { {NU_PINNAME_BIND(PH_11, UART_0), UART_0, SYS_GPH_MFPH_PH11MFP_UART0_RXD}, {PH_11, UART_4, SYS_GPH_MFPH_PH11MFP_UART4_RXD}, {NU_PINNAME_BIND(PH_11, UART_4), UART_4, SYS_GPH_MFPH_PH11MFP_UART4_RXD}, - + {NC, NC, 0} }; @@ -428,7 +429,7 @@ const PinMap PinMap_UART_RTS[] = { {PE_13, UART_4, SYS_GPE_MFPH_PE13MFP_UART4_nRTS}, {PF_4, UART_2, SYS_GPF_MFPL_PF4MFP_UART2_nRTS}, {PH_8, UART_3, SYS_GPH_MFPH_PH8MFP_UART3_nRTS}, - + {NC, NC, 0} }; @@ -449,7 +450,7 @@ const PinMap PinMap_UART_CTS[] = { {PE_11, UART_1, SYS_GPE_MFPH_PE11MFP_UART1_nCTS}, {PF_5, UART_2, SYS_GPF_MFPL_PF5MFP_UART2_nCTS}, {PH_9, UART_3, SYS_GPH_MFPH_PH9MFP_UART3_nCTS}, - + {NC, NC, 0} }; @@ -474,7 +475,7 @@ const PinMap PinMap_SPI_MOSI[] = { {PF_6, SPI_0, SYS_GPF_MFPL_PF6MFP_SPI0_MOSI}, {PF_11, SPI_2, SYS_GPF_MFPH_PF11MFP_SPI2_MOSI}, {PH_5, SPI_1, SYS_GPH_MFPL_PH5MFP_SPI1_MOSI}, - + {NC, NC, 0} }; @@ -497,54 +498,31 @@ const PinMap PinMap_SPI_MISO[] = { {PF_7, SPI_0, SYS_GPF_MFPL_PF7MFP_SPI0_MISO}, {PG_4, SPI_2, SYS_GPG_MFPL_PG4MFP_SPI2_MISO}, {PH_4, SPI_1, SYS_GPH_MFPL_PH4MFP_SPI1_MISO}, - + {NC, NC, 0} }; const PinMap PinMap_SPI_SCLK[] = { {PA_2, SPI_0, SYS_GPA_MFPL_PA2MFP_SPI0_CLK}, - {PA_4, SPI_0, SYS_GPA_MFPL_PA4MFP_SPI0_I2SMCLK}, - {PA_5, SPI_1, SYS_GPA_MFPL_PA5MFP_SPI1_I2SMCLK}, {PA_7, SPI_1, SYS_GPA_MFPL_PA7MFP_SPI1_CLK}, {PA_10, SPI_2, SYS_GPA_MFPH_PA10MFP_SPI2_CLK}, {PA_13, SPI_2, SYS_GPA_MFPH_PA13MFP_SPI2_CLK}, - {PB_0, SPI_0, SYS_GPB_MFPL_PB0MFP_SPI0_I2SMCLK}, - {PB_1, SPI_1, SYS_GPB_MFPL_PB1MFP_SPI1_I2SMCLK}, - {NU_PINNAME_BIND(PB_1, SPI_1), SPI_1, SYS_GPB_MFPL_PB1MFP_SPI1_I2SMCLK}, - {PB_1, SPI_3, SYS_GPB_MFPL_PB1MFP_SPI3_I2SMCLK}, - {NU_PINNAME_BIND(PB_1, SPI_3), SPI_3, SYS_GPB_MFPL_PB1MFP_SPI3_I2SMCLK}, {PB_3, SPI_1, SYS_GPB_MFPL_PB3MFP_SPI1_CLK}, - {PB_11, SPI_0, SYS_GPB_MFPH_PB11MFP_SPI0_I2SMCLK}, - {NU_PINNAME_BIND(PB_11, SPI_0), SPI_0, SYS_GPB_MFPH_PB11MFP_SPI0_I2SMCLK}, {PB_11, SPI_3, SYS_GPB_MFPH_PB11MFP_SPI3_CLK}, {NU_PINNAME_BIND(PB_11, SPI_3), SPI_3, SYS_GPB_MFPH_PB11MFP_SPI3_CLK}, {PB_14, SPI_0, SYS_GPB_MFPH_PB14MFP_SPI0_CLK}, {PC_1, SPI_1, SYS_GPC_MFPL_PC1MFP_SPI1_CLK}, - {PC_4, SPI_1, SYS_GPC_MFPL_PC4MFP_SPI1_I2SMCLK}, {PC_10, SPI_3, SYS_GPC_MFPH_PC10MFP_SPI3_CLK}, - {PC_13, SPI_2, SYS_GPC_MFPH_PC13MFP_SPI2_I2SMCLK}, {PD_2, SPI_0, SYS_GPD_MFPL_PD2MFP_SPI0_CLK}, {PD_5, SPI_1, SYS_GPD_MFPL_PD5MFP_SPI1_CLK}, - {PD_13, SPI_0, SYS_GPD_MFPH_PD13MFP_SPI0_I2SMCLK}, - {NU_PINNAME_BIND(PD_13, SPI_0), SPI_0, SYS_GPD_MFPH_PD13MFP_SPI0_I2SMCLK}, - {PD_13, SPI_1, SYS_GPD_MFPH_PD13MFP_SPI1_I2SMCLK}, - {NU_PINNAME_BIND(PD_13, SPI_1), SPI_1, SYS_GPD_MFPH_PD13MFP_SPI1_I2SMCLK}, - {PD_14, SPI_0, SYS_GPD_MFPH_PD14MFP_SPI0_I2SMCLK}, - {NU_PINNAME_BIND(PD_14, SPI_0), SPI_0, SYS_GPD_MFPH_PD14MFP_SPI0_I2SMCLK}, - {PD_14, SPI_3, SYS_GPD_MFPH_PD14MFP_SPI3_I2SMCLK}, - {NU_PINNAME_BIND(PD_14, SPI_3), SPI_3, SYS_GPD_MFPH_PD14MFP_SPI3_I2SMCLK}, {PE_4, SPI_3, SYS_GPE_MFPL_PE4MFP_SPI3_CLK}, {NU_PINNAME_BIND(PE_4, SPI_3), SPI_3, SYS_GPE_MFPL_PE4MFP_SPI3_CLK}, - {PE_6, SPI_3, SYS_GPE_MFPL_PE6MFP_SPI3_I2SMCLK}, {PE_8, SPI_2, SYS_GPE_MFPH_PE8MFP_SPI2_CLK}, - {PE_12, SPI_2, SYS_GPE_MFPH_PE12MFP_SPI2_I2SMCLK}, {PF_8, SPI_0, SYS_GPF_MFPH_PF8MFP_SPI0_CLK}, - {PF_10, SPI_0, SYS_GPF_MFPH_PF10MFP_SPI0_I2SMCLK}, {PG_3, SPI_2, SYS_GPG_MFPL_PG3MFP_SPI2_CLK}, {PH_6, SPI_1, SYS_GPH_MFPL_PH6MFP_SPI1_CLK}, {PH_8, SPI_1, SYS_GPH_MFPH_PH8MFP_SPI1_CLK}, - {PH_10, SPI_1, SYS_GPH_MFPH_PH10MFP_SPI1_I2SMCLK}, - + {NC, NC, 0} }; @@ -567,7 +545,7 @@ const PinMap PinMap_SPI_SSEL[] = { {PG_2, SPI_2, SYS_GPG_MFPL_PG2MFP_SPI2_SS}, {PH_7, SPI_1, SYS_GPH_MFPL_PH7MFP_SPI1_SS}, {PH_9, SPI_1, SYS_GPH_MFPH_PH9MFP_SPI1_SS}, - + {NC, NC, 0} }; @@ -629,10 +607,10 @@ const PinMap PinMap_CAN_TD[] = { {PC_5, CAN_0, SYS_GPC_MFPL_PC5MFP_CAN0_TXD}, {PD_11, CAN_0, SYS_GPD_MFPH_PD11MFP_CAN0_TXD}, {PE_14, CAN_0, SYS_GPE_MFPH_PE14MFP_CAN0_TXD}, - + {NC, NC, 0} }; - + const PinMap PinMap_CAN_RD[] = { {PA_4, CAN_0, SYS_GPA_MFPL_PA4MFP_CAN0_RXD}, {PA_13, CAN_0, SYS_GPA_MFPH_PA13MFP_CAN0_RXD}, From b191e6a84a2df129520795bdb35a51e72452211e Mon Sep 17 00:00:00 2001 From: Kostiantyn Tkachov Date: Sun, 14 Jul 2019 13:28:10 +0300 Subject: [PATCH 035/227] Initial commit to add mbedTLS hardware acceleration for Cypress chips to mbed-os sources --- .../TARGET_PSOC6/TARGET_PSOC6_01/sha1_alt.h | 50 + .../TARGET_PSOC6/TARGET_PSOC6_01/sha256_alt.h | 51 + .../TARGET_PSOC6/TARGET_PSOC6_01/sha512_alt.h | 50 + .../TARGET_PSOC6/TARGET_PSOC6_02/sha1_alt.h | 50 + .../TARGET_PSOC6/TARGET_PSOC6_02/sha256_alt.h | 51 + .../TARGET_PSOC6/TARGET_PSOC6_02/sha512_alt.h | 50 + .../TARGET_Cypress/TARGET_PSOC6/aes_alt.c | 747 +++++ .../TARGET_Cypress/TARGET_PSOC6/aes_alt.h | 84 + .../TARGET_PSOC6/crypto_common.c | 172 + .../TARGET_PSOC6/crypto_common.h | 73 + .../TARGET_Cypress/TARGET_PSOC6/ecdsa_alt.c | 252 ++ .../TARGET_Cypress/TARGET_PSOC6/ecp_alt.c | 2829 +++++++++++++++++ .../TARGET_Cypress/TARGET_PSOC6/ecp_alt.h | 183 ++ .../TARGET_PSOC6/ecp_curves_alt.c | 1476 +++++++++ .../TARGET_PSOC6/mbedtls_device.h | 47 + .../TARGET_Cypress/TARGET_PSOC6/sha1_alt.c | 115 + .../TARGET_Cypress/TARGET_PSOC6/sha256_alt.c | 115 + .../TARGET_Cypress/TARGET_PSOC6/sha512_alt.c | 115 + targets/targets.json | 2 +- 19 files changed, 6511 insertions(+), 1 deletion(-) create mode 100644 features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_01/sha1_alt.h create mode 100644 features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_01/sha256_alt.h create mode 100644 features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_01/sha512_alt.h create mode 100644 features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_02/sha1_alt.h create mode 100644 features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_02/sha256_alt.h create mode 100644 features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_02/sha512_alt.h create mode 100644 features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/aes_alt.c create mode 100644 features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/aes_alt.h create mode 100644 features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/crypto_common.c create mode 100644 features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/crypto_common.h create mode 100644 features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecdsa_alt.c create mode 100644 features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecp_alt.c create mode 100644 features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecp_alt.h create mode 100644 features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecp_curves_alt.c create mode 100644 features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/mbedtls_device.h create mode 100644 features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha1_alt.c create mode 100644 features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha256_alt.c create mode 100644 features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha512_alt.c diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_01/sha1_alt.h b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_01/sha1_alt.h new file mode 100644 index 00000000000..d90e68ed5d4 --- /dev/null +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_01/sha1_alt.h @@ -0,0 +1,50 @@ +/* + * mbed Microcontroller Library + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright (C) 2019 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * \file sha1_alt.h + * \version 1.0 + * + * \brief header file - wrapper for mbedtls SHA1 HW acceleration + * + */ + +#if !defined(SHA1_ALT_H) +#define SHA1_ALT_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include "crypto_common.h" + +#if defined(MBEDTLS_SHA1_ALT) + +typedef struct mbedtls_sha1_context { + cy_hw_crypto_t obj; + cy_stc_crypto_sha_state_t hashState; /* Structure used by CY Crypto Driver */ + cy_stc_crypto_v1_sha1_buffers_t shaBuffers; /* Structure used by CY Crypto Driver */ +} +mbedtls_sha1_context; + +#endif /* MBEDTLS_SHA1_ALT */ + +#endif /* (SHA1_ALT_H) */ diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_01/sha256_alt.h b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_01/sha256_alt.h new file mode 100644 index 00000000000..57a5aaa3e57 --- /dev/null +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_01/sha256_alt.h @@ -0,0 +1,51 @@ +/* + * mbed Microcontroller Library + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright (C) 2019 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * \file sha256_alt.h + * \version 1.0 + * + * \brief header file - wrapper for mbedtls SHA256 HW acceleration + * + */ + + +#if !defined(SHA256_ALT_H) +#define SHA256_ALT_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include "crypto_common.h" + +#if defined(MBEDTLS_SHA256_ALT) + +typedef struct mbedtls_sha256_context { + cy_hw_crypto_t obj; + cy_stc_crypto_sha_state_t hashState; /* Structure used by CY Crypto Driver */ + cy_stc_crypto_v1_sha256_buffers_t shaBuffers; /* Structure used by CY Crypto Driver */ +} +mbedtls_sha256_context; + +#endif /* MBEDTLS_SHA256_ALT */ + +#endif /* (SHA256_ALT_H) */ diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_01/sha512_alt.h b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_01/sha512_alt.h new file mode 100644 index 00000000000..0f98be83f2b --- /dev/null +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_01/sha512_alt.h @@ -0,0 +1,50 @@ +/* + * mbed Microcontroller Library + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright (C) 2019 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * \file sha512_alt.h + * \version 1.0 + * + * \brief header file - wrapper for mbedtls SHA512 HW acceleration + * + */ + +#if !defined(SHA512_ALT_H) +#define SHA512_ALT_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include "crypto_common.h" + +#if defined(MBEDTLS_SHA512_ALT) + +typedef struct mbedtls_sha512_context { + cy_hw_crypto_t obj; + cy_stc_crypto_sha_state_t hashState; /* Structure used by CY Crypto Driver */ + cy_stc_crypto_v1_sha512_buffers_t shaBuffers; /* Structure used by CY Crypto Driver */ +} +mbedtls_sha512_context; + +#endif /* MBEDTLS_SHA512_ALT */ + +#endif /* (SHA512_ALT_H) */ diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_02/sha1_alt.h b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_02/sha1_alt.h new file mode 100644 index 00000000000..974654d7615 --- /dev/null +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_02/sha1_alt.h @@ -0,0 +1,50 @@ +/* + * mbed Microcontroller Library + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright (C) 2019 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * \file sha1_alt.h + * \version 1.0 + * + * \brief header file - wrapper for mbedtls SHA1 HW acceleration + * + */ + +#if !defined(SHA1_ALT_H) +#define SHA1_ALT_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include "crypto_common.h" + +#if defined(MBEDTLS_SHA1_ALT) + +typedef struct mbedtls_sha1_context { + cy_hw_crypto_t obj; + cy_stc_crypto_sha_state_t hashState; /* Structure used by CY Crypto Driver */ + cy_stc_crypto_v2_sha1_buffers_t shaBuffers; /* Structure used by CY Crypto Driver */ +} +mbedtls_sha1_context; + +#endif /* MBEDTLS_SHA1_ALT */ + +#endif /* (SHA1_ALT_H) */ diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_02/sha256_alt.h b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_02/sha256_alt.h new file mode 100644 index 00000000000..9d258529160 --- /dev/null +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_02/sha256_alt.h @@ -0,0 +1,51 @@ +/* + * mbed Microcontroller Library + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright (C) 2019 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * \file sha256_alt.h + * \version 1.0 + * + * \brief header file - wrapper for mbedtls SHA256 HW acceleration + * + */ + + +#if !defined(SHA256_ALT_H) +#define SHA256_ALT_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include "crypto_common.h" + +#if defined(MBEDTLS_SHA256_ALT) + +typedef struct mbedtls_sha256_context { + cy_hw_crypto_t obj; + cy_stc_crypto_sha_state_t hashState; /* Structure used by CY Crypto Driver */ + cy_stc_crypto_v2_sha256_buffers_t shaBuffers; /* Structure used by CY Crypto Driver */ +} +mbedtls_sha256_context; + +#endif /* MBEDTLS_SHA256_ALT */ + +#endif /* (SHA256_ALT_H) */ diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_02/sha512_alt.h b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_02/sha512_alt.h new file mode 100644 index 00000000000..f1e0fba5ace --- /dev/null +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_02/sha512_alt.h @@ -0,0 +1,50 @@ +/* + * mbed Microcontroller Library + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright (C) 2019 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * \file sha512_alt.h + * \version 1.0 + * + * \brief header file - wrapper for mbedtls SHA512 HW acceleration + * + */ + +#if !defined(SHA512_ALT_H) +#define SHA512_ALT_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include "crypto_common.h" + +#if defined(MBEDTLS_SHA512_ALT) + +typedef struct mbedtls_sha512_context { + cy_hw_crypto_t obj; + cy_stc_crypto_sha_state_t hashState; /* Structure used by CY Crypto Driver */ + cy_stc_crypto_v2_sha512_buffers_t shaBuffers; /* Structure used by CY Crypto Driver */ +} +mbedtls_sha512_context; + +#endif /* MBEDTLS_SHA512_ALT */ + +#endif /* (SHA512_ALT_H) */ diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/aes_alt.c b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/aes_alt.c new file mode 100644 index 00000000000..156d6dc4a38 --- /dev/null +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/aes_alt.c @@ -0,0 +1,747 @@ +/* + * Source file for mbedtls AES HW acceleration functions + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright (C) 2019 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * \file aes_alt.h + * \ version 1.0 + * + * \brief This file contains AES functions implementation. + * + * The AES block cipher was designed by Vincent Rijmen and Joan Daemen. + * + * http://csrc.nist.gov/encryption/aes/rijndael/Rijndael.pdf + * http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf + */ + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_AES_C) + +#include + +#include "mbedtls/aes.h" +#include "mbedtls/platform.h" +#include "mbedtls/platform_util.h" + +/* Parameter validation macros based on platform_util.h */ +#define AES_VALIDATE_RET( cond ) \ + MBEDTLS_INTERNAL_VALIDATE_RET( cond, MBEDTLS_ERR_AES_BAD_INPUT_DATA ) +#define AES_VALIDATE( cond ) \ + MBEDTLS_INTERNAL_VALIDATE( cond ) + +#if defined(MBEDTLS_AES_ALT) + +#include "crypto_common.h" +#include "cy_crypto_core.h" + +void mbedtls_aes_init( mbedtls_aes_context *ctx ) +{ + AES_VALIDATE( ctx != NULL ); + + cy_hw_zeroize(ctx, sizeof( mbedtls_aes_context ) ); + + (void)cy_hw_crypto_reserve((cy_hw_crypto_t *)ctx, CYHAL_CRYPTO_COMMON); +} + +void mbedtls_aes_free( mbedtls_aes_context *ctx ) +{ + if( ctx == NULL ) + return; + + if (ctx->aes_state.buffers != NULL) { + Cy_Crypto_Core_Aes_Free(ctx->obj.base, &ctx->aes_state); + } + cy_hw_crypto_release((cy_hw_crypto_t *)ctx); + + cy_hw_zeroize(ctx, sizeof( mbedtls_aes_context ) ); +} + +#if defined(MBEDTLS_CIPHER_MODE_XTS) +void mbedtls_aes_xts_init( mbedtls_aes_xts_context *ctx ) +{ + AES_VALIDATE( ctx != NULL ); + + mbedtls_aes_init( &ctx->crypt ); + mbedtls_aes_init( &ctx->tweak ); +} + +void mbedtls_aes_xts_free( mbedtls_aes_xts_context *ctx ) +{ + if( ctx == NULL ) + return; + + mbedtls_aes_free( &ctx->crypt ); + mbedtls_aes_free( &ctx->tweak ); +} +#endif /* MBEDTLS_CIPHER_MODE_XTS */ + +/* + * Set CY HW AES keys + */ + +static int aes_set_keys( mbedtls_aes_context *ctx, const unsigned char *key, + unsigned int keybits ) +{ + int ret = 0; + cy_en_crypto_aes_key_length_t key_length; + cy_en_crypto_status_t status; + + AES_VALIDATE( ctx != NULL ); + + switch( keybits ) + { + case 128: key_length = CY_CRYPTO_KEY_AES_128; break; + case 192: key_length = CY_CRYPTO_KEY_AES_192; break; + case 256: key_length = CY_CRYPTO_KEY_AES_256; break; + default : return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH ); + } + + status = Cy_Crypto_Core_Aes_InitContext(ctx->obj.base, key, key_length, &ctx->aes_state, &ctx->aes_buffers); + + if (CY_CRYPTO_SUCCESS != status) + { + ret = MBEDTLS_ERR_AES_HW_ACCEL_FAILED; + goto exit; + } + +exit: + return( ret ); +} + +/* + * AES key schedule (encryption) + */ +int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, + unsigned int keybits ) +{ + AES_VALIDATE_RET( ctx != NULL ); + AES_VALIDATE_RET( key != NULL ); + + return aes_set_keys( ctx, key, keybits ); +} + +/* + * AES key schedule (decryption) + */ +int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key, + unsigned int keybits ) +{ + AES_VALIDATE_RET( ctx != NULL ); + AES_VALIDATE_RET( key != NULL ); + + return aes_set_keys( ctx, key, keybits ); +} + +#if defined(MBEDTLS_CIPHER_MODE_XTS) +static int mbedtls_aes_xts_decode_keys( const unsigned char *key, + unsigned int keybits, + const unsigned char **key1, + unsigned int *key1bits, + const unsigned char **key2, + unsigned int *key2bits ) +{ + const unsigned int half_keybits = keybits / 2; + const unsigned int half_keybytes = half_keybits / 8; + + switch( keybits ) + { + case 256: break; + case 512: break; + default : return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH ); + } + + *key1bits = half_keybits; + *key2bits = half_keybits; + *key1 = &key[0]; + *key2 = &key[half_keybytes]; + + return 0; +} + +int mbedtls_aes_xts_setkey_enc( mbedtls_aes_xts_context *ctx, + const unsigned char *key, + unsigned int keybits) +{ + int ret; + const unsigned char *key1, *key2; + unsigned int key1bits, key2bits; + + AES_VALIDATE_RET( ctx != NULL ); + AES_VALIDATE_RET( key != NULL ); + + ret = mbedtls_aes_xts_decode_keys( key, keybits, &key1, &key1bits, + &key2, &key2bits ); + if( ret != 0 ) + return( ret ); + + /* Set the tweak key. Always set tweak key for the encryption mode. */ + ret = mbedtls_aes_setkey_enc( &ctx->tweak, key2, key2bits ); + if( ret != 0 ) + return( ret ); + + /* Set crypt key for encryption. */ + return mbedtls_aes_setkey_enc( &ctx->crypt, key1, key1bits ); +} + +int mbedtls_aes_xts_setkey_dec( mbedtls_aes_xts_context *ctx, + const unsigned char *key, + unsigned int keybits) +{ + int ret; + const unsigned char *key1, *key2; + unsigned int key1bits, key2bits; + + AES_VALIDATE_RET( ctx != NULL ); + AES_VALIDATE_RET( key != NULL ); + + ret = mbedtls_aes_xts_decode_keys( key, keybits, &key1, &key1bits, + &key2, &key2bits ); + if( ret != 0 ) + return( ret ); + + /* Set the tweak key. Always set tweak key for encryption. */ + ret = mbedtls_aes_setkey_enc( &ctx->tweak, key2, key2bits ); + if( ret != 0 ) + return( ret ); + + /* Set crypt key for decryption. */ + return mbedtls_aes_setkey_dec( &ctx->crypt, key1, key1bits ); +} +#endif /* MBEDTLS_CIPHER_MODE_XTS */ + +/* + * AES-ECB block encryption + */ +int mbedtls_internal_aes_encrypt( mbedtls_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16] ) +{ + int ret = 0; + cy_en_crypto_status_t status; + + AES_VALIDATE_RET( ctx != NULL ); + AES_VALIDATE_RET( ctx->aes_state.buffers != NULL ); + + status = Cy_Crypto_Core_Aes_Ecb(ctx->obj.base, CY_CRYPTO_ENCRYPT, output, input, &ctx->aes_state); + + if (CY_CRYPTO_SUCCESS != status) + { + ret = MBEDTLS_ERR_AES_HW_ACCEL_FAILED; + } + + return( ret ); +} + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +void mbedtls_aes_encrypt( mbedtls_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16] ) +{ + mbedtls_internal_aes_encrypt( ctx, input, output ); +} +#endif /* !MBEDTLS_DEPRECATED_REMOVED */ + +/* + * AES-ECB block decryption + */ +int mbedtls_internal_aes_decrypt( mbedtls_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16] ) +{ + int ret = 0; + cy_en_crypto_status_t status; + + AES_VALIDATE_RET( ctx != NULL ); + AES_VALIDATE_RET( ctx->aes_state.buffers != NULL ); + + status = Cy_Crypto_Core_Aes_Ecb(ctx->obj.base, CY_CRYPTO_DECRYPT, output, input, &ctx->aes_state); + + if (CY_CRYPTO_SUCCESS != status) + { + ret = MBEDTLS_ERR_AES_HW_ACCEL_FAILED; + } + + return( ret ); +} + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +void mbedtls_aes_decrypt( mbedtls_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16] ) +{ + mbedtls_internal_aes_decrypt( ctx, input, output ); +} +#endif /* !MBEDTLS_DEPRECATED_REMOVED */ + +/* + * AES-ECB block encryption/decryption + */ +int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx, + int mode, + const unsigned char input[16], + unsigned char output[16] ) +{ + AES_VALIDATE_RET( ctx != NULL ); + AES_VALIDATE_RET( input != NULL ); + AES_VALIDATE_RET( output != NULL ); + AES_VALIDATE_RET( mode == MBEDTLS_AES_ENCRYPT || + mode == MBEDTLS_AES_DECRYPT ); + + if( mode == MBEDTLS_AES_ENCRYPT ) + return( mbedtls_internal_aes_encrypt( ctx, input, output ) ); + else + return( mbedtls_internal_aes_decrypt( ctx, input, output ) ); +} + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +/* + * AES-CBC buffer encryption/decryption + */ +int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) +{ + unsigned char temp[CY_CRYPTO_AES_BLOCK_SIZE]; + + int ret = 0; + cy_en_crypto_status_t status; + + AES_VALIDATE_RET( ctx != NULL ); + AES_VALIDATE_RET( mode == MBEDTLS_AES_ENCRYPT || + mode == MBEDTLS_AES_DECRYPT ); + AES_VALIDATE_RET( iv != NULL ); + AES_VALIDATE_RET( input != NULL ); + AES_VALIDATE_RET( output != NULL ); + + if( length % CY_CRYPTO_AES_BLOCK_SIZE ) + return( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH ); + + AES_VALIDATE_RET( ctx->aes_state.buffers != NULL); + + if( mode == MBEDTLS_AES_DECRYPT ) + { + while(( length > 0 ) && (ret == 0)) + { + Cy_Crypto_Core_MemCpy(ctx->obj.base, temp, input, CY_CRYPTO_AES_BLOCK_SIZE); + + status = Cy_Crypto_Core_Aes_Ecb(ctx->obj.base, CY_CRYPTO_DECRYPT, output, input, &ctx->aes_state); + + Cy_Crypto_Core_MemXor(ctx->obj.base, output, output, iv, CY_CRYPTO_AES_BLOCK_SIZE); + Cy_Crypto_Core_MemCpy(ctx->obj.base, iv, temp, CY_CRYPTO_AES_BLOCK_SIZE); + + input += CY_CRYPTO_AES_BLOCK_SIZE; + output += CY_CRYPTO_AES_BLOCK_SIZE; + length -= CY_CRYPTO_AES_BLOCK_SIZE; + + if (CY_CRYPTO_SUCCESS != status) + { + ret = MBEDTLS_ERR_AES_HW_ACCEL_FAILED; + } + } + } + else + { + while(( length > 0 ) && (ret == 0)) + { + Cy_Crypto_Core_MemXor(ctx->obj.base, output, input, iv, CY_CRYPTO_AES_BLOCK_SIZE); + + status = Cy_Crypto_Core_Aes_Ecb(ctx->obj.base, CY_CRYPTO_ENCRYPT, output, output, &ctx->aes_state); + + Cy_Crypto_Core_MemCpy(ctx->obj.base, iv, output, CY_CRYPTO_AES_BLOCK_SIZE); + + input += CY_CRYPTO_AES_BLOCK_SIZE; + output += CY_CRYPTO_AES_BLOCK_SIZE; + length -= CY_CRYPTO_AES_BLOCK_SIZE; + + if (CY_CRYPTO_SUCCESS != status) + { + ret = MBEDTLS_ERR_AES_HW_ACCEL_FAILED; + } + } + } + + return( ret ); +} + +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +#if defined(MBEDTLS_CIPHER_MODE_XTS) + +/* Endianess with 64 bits values */ +#ifndef GET_UINT64_LE +#define GET_UINT64_LE(n,b,i) \ +{ \ + (n) = ( (uint64_t) (b)[(i) + 7] << 56 ) \ + | ( (uint64_t) (b)[(i) + 6] << 48 ) \ + | ( (uint64_t) (b)[(i) + 5] << 40 ) \ + | ( (uint64_t) (b)[(i) + 4] << 32 ) \ + | ( (uint64_t) (b)[(i) + 3] << 24 ) \ + | ( (uint64_t) (b)[(i) + 2] << 16 ) \ + | ( (uint64_t) (b)[(i) + 1] << 8 ) \ + | ( (uint64_t) (b)[(i) ] ); \ +} +#endif + +#ifndef PUT_UINT64_LE +#define PUT_UINT64_LE(n,b,i) \ +{ \ + (b)[(i) + 7] = (unsigned char) ( (n) >> 56 ); \ + (b)[(i) + 6] = (unsigned char) ( (n) >> 48 ); \ + (b)[(i) + 5] = (unsigned char) ( (n) >> 40 ); \ + (b)[(i) + 4] = (unsigned char) ( (n) >> 32 ); \ + (b)[(i) + 3] = (unsigned char) ( (n) >> 24 ); \ + (b)[(i) + 2] = (unsigned char) ( (n) >> 16 ); \ + (b)[(i) + 1] = (unsigned char) ( (n) >> 8 ); \ + (b)[(i) ] = (unsigned char) ( (n) ); \ +} +#endif + +typedef unsigned char mbedtls_be128[16]; + +/* + * GF(2^128) multiplication function + * + * This function multiplies a field element by x in the polynomial field + * representation. It uses 64-bit word operations to gain speed but compensates + * for machine endianess and hence works correctly on both big and little + * endian machines. + */ +static void mbedtls_gf128mul_x_ble( unsigned char r[16], + const unsigned char x[16] ) +{ + uint64_t a, b, ra, rb; + + GET_UINT64_LE( a, x, 0 ); + GET_UINT64_LE( b, x, 8 ); + + ra = ( a << 1 ) ^ 0x0087 >> ( 8 - ( ( b >> 63 ) << 3 ) ); + rb = ( a >> 63 ) | ( b << 1 ); + + PUT_UINT64_LE( ra, r, 0 ); + PUT_UINT64_LE( rb, r, 8 ); +} + +/* + * AES-XTS buffer encryption/decryption + */ +int mbedtls_aes_crypt_xts( mbedtls_aes_xts_context *ctx, + int mode, + size_t length, + const unsigned char data_unit[16], + const unsigned char *input, + unsigned char *output ) +{ + int ret; + size_t blocks = length / 16; + size_t leftover = length % 16; + unsigned char tweak[16]; + unsigned char prev_tweak[16]; + unsigned char tmp[16]; + + AES_VALIDATE_RET( ctx != NULL ); + AES_VALIDATE_RET( mode == MBEDTLS_AES_ENCRYPT || + mode == MBEDTLS_AES_DECRYPT ); + AES_VALIDATE_RET( data_unit != NULL ); + AES_VALIDATE_RET( input != NULL ); + AES_VALIDATE_RET( output != NULL ); + + /* Data units must be at least 16 bytes long. */ + if( length < 16 ) + return MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH; + + /* NIST SP 800-38E disallows data units larger than 2**20 blocks. */ + if( length > ( 1 << 20 ) * 16 ) + return MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH; + + /* Compute the tweak. */ + ret = mbedtls_aes_crypt_ecb( &ctx->tweak, MBEDTLS_AES_ENCRYPT, + data_unit, tweak ); + if( ret != 0 ) + return( ret ); + + while( blocks-- ) + { + size_t i; + + if( leftover && ( mode == MBEDTLS_AES_DECRYPT ) && blocks == 0 ) + { + /* We are on the last block in a decrypt operation that has + * leftover bytes, so we need to use the next tweak for this block, + * and this tweak for the lefover bytes. Save the current tweak for + * the leftovers and then update the current tweak for use on this, + * the last full block. */ + memcpy( prev_tweak, tweak, sizeof( tweak ) ); + mbedtls_gf128mul_x_ble( tweak, tweak ); + } + + for( i = 0; i < 16; i++ ) + tmp[i] = input[i] ^ tweak[i]; + + ret = mbedtls_aes_crypt_ecb( &ctx->crypt, mode, tmp, tmp ); + if( ret != 0 ) + return( ret ); + + for( i = 0; i < 16; i++ ) + output[i] = tmp[i] ^ tweak[i]; + + /* Update the tweak for the next block. */ + mbedtls_gf128mul_x_ble( tweak, tweak ); + + output += 16; + input += 16; + } + + if( leftover ) + { + /* If we are on the leftover bytes in a decrypt operation, we need to + * use the previous tweak for these bytes (as saved in prev_tweak). */ + unsigned char *t = mode == MBEDTLS_AES_DECRYPT ? prev_tweak : tweak; + + /* We are now on the final part of the data unit, which doesn't divide + * evenly by 16. It's time for ciphertext stealing. */ + size_t i; + unsigned char *prev_output = output - 16; + + /* Copy ciphertext bytes from the previous block to our output for each + * byte of cyphertext we won't steal. At the same time, copy the + * remainder of the input for this final round (since the loop bounds + * are the same). */ + for( i = 0; i < leftover; i++ ) + { + output[i] = prev_output[i]; + tmp[i] = input[i] ^ t[i]; + } + + /* Copy ciphertext bytes from the previous block for input in this + * round. */ + for( ; i < 16; i++ ) + tmp[i] = prev_output[i] ^ t[i]; + + ret = mbedtls_aes_crypt_ecb( &ctx->crypt, mode, tmp, tmp ); + if( ret != 0 ) + return ret; + + /* Write the result back to the previous block, overriding the previous + * output we copied. */ + for( i = 0; i < 16; i++ ) + prev_output[i] = tmp[i] ^ t[i]; + } + + return( 0 ); +} +#endif /* MBEDTLS_CIPHER_MODE_XTS */ + +#if defined(MBEDTLS_CIPHER_MODE_CFB) +/* + * AES-CFB128 buffer encryption/decryption + */ +int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, + int mode, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) +{ + int c; + size_t n = *iv_off; + + AES_VALIDATE_RET( ctx != NULL ); + AES_VALIDATE_RET( mode == MBEDTLS_AES_ENCRYPT || + mode == MBEDTLS_AES_DECRYPT ); + AES_VALIDATE_RET( iv_off != NULL ); + AES_VALIDATE_RET( iv != NULL ); + AES_VALIDATE_RET( input != NULL ); + AES_VALIDATE_RET( output != NULL ); + + if( n > 15 ) + return (MBEDTLS_ERR_AES_BAD_INPUT_DATA); + + if( mode == MBEDTLS_AES_DECRYPT ) + { + while( length-- ) + { + if( n == 0 ) + mbedtls_internal_aes_encrypt( ctx, iv, iv ); + + c = *input++; + *output++ = (unsigned char)( c ^ iv[n] ); + iv[n] = (unsigned char) c; + + n = ( n + 1 ) & 0x0F; + } + } + else + { + while( length-- ) + { + if( n == 0 ) + mbedtls_internal_aes_encrypt( ctx, iv, iv ); + + iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ ); + + n = ( n + 1 ) & 0x0F; + } + } + + *iv_off = n; + + return( 0 ); +} + +/* + * AES-CFB8 buffer encryption/decryption + */ +int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) +{ + unsigned char c; + unsigned char ov[17]; + + AES_VALIDATE_RET( ctx != NULL ); + AES_VALIDATE_RET( mode == MBEDTLS_AES_ENCRYPT || + mode == MBEDTLS_AES_DECRYPT ); + AES_VALIDATE_RET( iv != NULL ); + AES_VALIDATE_RET( input != NULL ); + AES_VALIDATE_RET( output != NULL ); + + while( length-- ) + { + memcpy( ov, iv, 16 ); + mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ); + + if( mode == MBEDTLS_AES_DECRYPT ) + ov[16] = *input; + + c = *output++ = (unsigned char)( iv[0] ^ *input++ ); + + if( mode == MBEDTLS_AES_ENCRYPT ) + ov[16] = c; + + memcpy( iv, ov + 1, 16 ); + } + + return( 0 ); +} +#endif /* MBEDTLS_CIPHER_MODE_CFB */ + +#if defined(MBEDTLS_CIPHER_MODE_OFB) +/* + * AES-OFB (Output Feedback Mode) buffer encryption/decryption + */ +int mbedtls_aes_crypt_ofb( mbedtls_aes_context *ctx, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) +{ + int ret = 0; + size_t n = *iv_off; + + AES_VALIDATE_RET( ctx != NULL ); + AES_VALIDATE_RET( iv_off != NULL ); + AES_VALIDATE_RET( iv != NULL ); + AES_VALIDATE_RET( input != NULL ); + AES_VALIDATE_RET( output != NULL ); + + if( n > 15 ) + return (MBEDTLS_ERR_AES_BAD_INPUT_DATA); + + while( length-- ) + { + if( n == 0 ) + { + ret = mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ); + if( ret != 0 ) + goto exit; + } + *output++ = *input++ ^ iv[n]; + + n = ( n + 1 ) & 0x0F; + } + + *iv_off = n; + +exit: + return( ret ); +} +#endif /* MBEDTLS_CIPHER_MODE_OFB */ + +#if defined(MBEDTLS_CIPHER_MODE_CTR) +/* + * AES-CTR buffer encryption/decryption + */ +int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx, + size_t length, + size_t *nc_off, + unsigned char nonce_counter[16], + unsigned char stream_block[16], + const unsigned char *input, + unsigned char *output ) +{ + int c, i; + size_t n = *nc_off; + + AES_VALIDATE_RET( ctx != NULL ); + AES_VALIDATE_RET( nc_off != NULL ); + AES_VALIDATE_RET( nonce_counter != NULL ); + AES_VALIDATE_RET( stream_block != NULL ); + AES_VALIDATE_RET( input != NULL ); + AES_VALIDATE_RET( output != NULL ); + + if ( n > 0x0F ) + return( MBEDTLS_ERR_AES_BAD_INPUT_DATA ); + + while( length-- ) + { + if( n == 0 ) { + mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, nonce_counter, stream_block ); + + for( i = 16; i > 0; i-- ) + if( ++nonce_counter[i - 1] != 0 ) + break; + } + c = *input++; + *output++ = (unsigned char)( c ^ stream_block[n] ); + + n = ( n + 1 ) & 0x0F; + } + + *nc_off = n; + + return( 0 ); +} +#endif /* MBEDTLS_CIPHER_MODE_CTR */ + +#endif /* MBEDTLS_AES_ALT */ + +#endif /* MBEDTLS_AES_C */ diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/aes_alt.h b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/aes_alt.h new file mode 100644 index 00000000000..3804e3d5706 --- /dev/null +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/aes_alt.h @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright (C) 2019 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * \file aes_alt.h + * \ version 1.0 + * + * \brief This file contains AES definitions and functions. + * + * The Advanced Encryption Standard (AES) specifies a FIPS-approved + * cryptographic algorithm that can be used to protect electronic + * data. + * + * The AES algorithm is a symmetric block cipher that can + * encrypt and decrypt information. For more information, see + * FIPS Publication 197: Advanced Encryption Standard and + * ISO/IEC 18033-2:2006: Information technology -- Security + * techniques -- Encryption algorithms -- Part 2: Asymmetric + * ciphers. + * + * The AES-XTS block mode is standardized by NIST SP 800-38E + * + * and described in detail by IEEE P1619 + * . + */ + +#ifndef AES_ALT_H +#define AES_ALT_H + +#if defined(MBEDTLS_AES_ALT) +// Regular implementation + +#define CY_CIPHER_MODE_CBC_ALT + +#include +#include +#include "cy_syslib.h" + +#include "crypto_common.h" + +/** + * \brief The AES context-type definition. + */ +typedef struct mbedtls_aes_context +{ + cy_hw_crypto_t obj; + cy_stc_crypto_aes_state_t aes_state; + cy_stc_crypto_aes_buffers_t aes_buffers; +} +mbedtls_aes_context; + +#if defined(MBEDTLS_CIPHER_MODE_XTS) + +/** + * \brief The AES XTS context-type definition. + */ +typedef struct mbedtls_aes_xts_context +{ + mbedtls_aes_context crypt; /*!< The AES context to use for AES block + encryption or decryption. */ + mbedtls_aes_context tweak; /*!< The AES context used for tweak + computation. */ +} mbedtls_aes_xts_context; + +#endif /* MBEDTLS_CIPHER_MODE_XTS */ + +#endif /* MBEDTLS_AES_ALT */ + +#endif /* aes_alt.h */ diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/crypto_common.c b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/crypto_common.c new file mode 100644 index 00000000000..4c8d96d4d32 --- /dev/null +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/crypto_common.c @@ -0,0 +1,172 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2019 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * \file crypto_common.c + * \version 1.0 + * + * \brief Source file for common mbedtls acceleration functions + * + */ + +#include + +#include "crypto_common.h" +#include "cy_crypto_common.h" +#include "cy_crypto_core_hw.h" +#include "cy_crypto_core_mem.h" + +#define CY_CRYPTO_CHECK_PARAM(cond) do { \ + if( !(cond) ) \ + return; \ + } while( 0 ) + +/******************************************************************************* +* Crypto object manage functions +*******************************************************************************/ +bool cy_hw_crypto_reserve(cy_hw_crypto_t *obj, cyhal_crypto_feature_t feature) +{ + cy_rslt_t status; + CY_ASSERT( obj != NULL ); + + status = cyhal_crypto_reserve(&(obj->base), &(obj->resource), feature); + if (CY_RSLT_SUCCESS == status) + { + obj->feature = feature; + } + + return (CY_RSLT_SUCCESS == status); +} + +void cy_hw_crypto_release(cy_hw_crypto_t *obj) +{ + CY_ASSERT( obj != NULL ); + if (obj->resource.type == CYHAL_RSC_CRYPTO) + { + cyhal_crypto_free(obj->base, &(obj->resource), obj->feature); + } +} + +void cy_hw_zeroize(void *data, uint32_t dataSize) +{ + cy_hw_crypto_t obj; + CY_CRYPTO_CHECK_PARAM( data != NULL ); + CY_CRYPTO_CHECK_PARAM( dataSize > 0u ); + + if (cy_hw_crypto_reserve(&obj, CYHAL_CRYPTO_COMMON)) + { + Cy_Crypto_Core_MemSet(obj.base, data, 0u, (uint16_t)dataSize); + } + cy_hw_crypto_release(&obj); +} + +void cy_hw_sha_init(void *ctx, uint32_t ctxSize) +{ + CY_CRYPTO_CHECK_PARAM( ctx != NULL ); + CY_CRYPTO_CHECK_PARAM( ctxSize > 0u ); + + cy_hw_zeroize(ctx, ctxSize); + + (void)cy_hw_crypto_reserve((cy_hw_crypto_t *)ctx, CYHAL_CRYPTO_COMMON); +} + +void cy_hw_sha_free(void *ctx, uint32_t ctxSize) +{ + CY_CRYPTO_CHECK_PARAM( ctx != NULL ); + CY_CRYPTO_CHECK_PARAM( ctxSize > 0u); + + cy_hw_crypto_release((cy_hw_crypto_t *)ctx); + cy_hw_zeroize(ctx, ctxSize); +} + +int cy_hw_sha_start(cy_hw_crypto_t *obj, cy_stc_crypto_sha_state_t *hashState, + cy_en_crypto_sha_mode_t shaMode, void *shaBuffers) +{ + cy_en_crypto_status_t status; + + if ((hashState == NULL) || (shaBuffers == NULL)) + return (-1); + + status = Cy_Crypto_Core_Sha_Init(obj->base, hashState, shaMode, shaBuffers); + if (CY_CRYPTO_SUCCESS != status) + return (-1); + + status = Cy_Crypto_Core_Sha_Start(obj->base, hashState); + if (CY_CRYPTO_SUCCESS != status) + return (-1); + + return (0); +} + +int cy_hw_sha_update(cy_hw_crypto_t *obj, cy_stc_crypto_sha_state_t *hashState, + const uint8_t *in, uint32_t inlen) +{ + cy_en_crypto_status_t status; + + if ((hashState == NULL) || (in == NULL)) + return (-1); + + if (hashState->blockSize == 0) + return (-1); + + status = Cy_Crypto_Core_Sha_Update(obj->base, hashState, in, inlen); + if (CY_CRYPTO_SUCCESS != status) + return (-1); + + return (0); +} + +int cy_hw_sha_finish(cy_hw_crypto_t *obj, cy_stc_crypto_sha_state_t *hashState, uint8_t *output) +{ + cy_en_crypto_status_t status; + + if ((hashState == NULL) || (output == NULL)) + return (-1); + + if (hashState->blockSize == 0) + return (-1); + + status = Cy_Crypto_Core_Sha_Finish(obj->base, hashState, output); + if (CY_CRYPTO_SUCCESS != status) + return (-1); + + return (0); +} + +int cy_hw_sha_process(cy_hw_crypto_t *obj, cy_stc_crypto_sha_state_t *hashState, const uint8_t *in) +{ + cy_en_crypto_status_t status; + + status = Cy_Crypto_Core_Sha_Update(obj->base, hashState, in, hashState->blockSize); + if (CY_CRYPTO_SUCCESS != status) + return (-1); + + return (0); +} + +void cy_hw_sha_clone( void *ctxDst, const void *ctxSrc, uint32_t ctxSize, + cy_stc_crypto_sha_state_t *hashStateDst, void *shaBuffersDst) +{ + CY_CRYPTO_CHECK_PARAM( ctxDst != NULL ); + CY_CRYPTO_CHECK_PARAM( ctxSrc != NULL ); + CY_CRYPTO_CHECK_PARAM( hashStateDst != NULL ); + CY_CRYPTO_CHECK_PARAM( shaBuffersDst != NULL ); + + Cy_Crypto_Core_MemCpy(((cy_hw_crypto_t *)ctxSrc)->base, ctxDst, ctxSrc, (uint16_t)ctxSize); + Cy_Crypto_Core_Sha_Init(((cy_hw_crypto_t *)ctxSrc)->base, hashStateDst, hashStateDst->mode, shaBuffersDst); +} diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/crypto_common.h b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/crypto_common.h new file mode 100644 index 00000000000..d0f678315f1 --- /dev/null +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/crypto_common.h @@ -0,0 +1,73 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2019 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * \file crypto_common.h + * \version 1.0 + * + * \brief Header file for common mbedtls acceleration functions + * + */ + +#if !defined(CRYPTO_COMMON_H) +#define CRYPTO_COMMON_H + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include "mbedtls/ecp.h" + +#include "cy_crypto_core_sha.h" + +#include "cyhal_crypto_common.h" + +/** CRYPTO object */ +typedef struct { +#if defined(CY_IP_MXCRYPTO_INSTANCES) || defined(CPUSS_CRYPTO_PRESENT) + CRYPTO_Type* base; + cyhal_resource_inst_t resource; + cyhal_crypto_feature_t feature; +#endif +} cy_hw_crypto_t; + +bool cy_hw_crypto_reserve(cy_hw_crypto_t *obj, cyhal_crypto_feature_t feature); +void cy_hw_crypto_release(cy_hw_crypto_t *obj); +void cy_hw_zeroize(void *data, uint32_t dataSize); + +void cy_hw_sha_init(void *ctx, uint32_t ctxSize); +void cy_hw_sha_free(void *ctx, uint32_t ctxSize); + +int cy_hw_sha_start (cy_hw_crypto_t *obj, cy_stc_crypto_sha_state_t *hashState, + cy_en_crypto_sha_mode_t shaMode, void *shaBuffers); + +int cy_hw_sha_update(cy_hw_crypto_t *obj, cy_stc_crypto_sha_state_t *hashState, + const uint8_t *in, uint32_t inlen); + +int cy_hw_sha_finish(cy_hw_crypto_t *obj, cy_stc_crypto_sha_state_t *hashState, + uint8_t *output); + +void cy_hw_sha_clone(void *ctxDst, const void *ctxSrc, uint32_t ctxSize, + cy_stc_crypto_sha_state_t *hashStateDst, void *shaBuffersDst); + +int cy_hw_sha_process(cy_hw_crypto_t *obj, cy_stc_crypto_sha_state_t *hashState, + const uint8_t *in); + +#endif /* (CRYPTO_COMMON_H) */ diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecdsa_alt.c b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecdsa_alt.c new file mode 100644 index 00000000000..563cf739868 --- /dev/null +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecdsa_alt.c @@ -0,0 +1,252 @@ +/* + * ECDSA sign, verify and key generation functions + * + * Copyright (C) 2019 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * \file ecdsa_alt.c + * \version 1.0 + * + * \brief This file provides an API for Elliptic Curves sign and verifications. + * + */ + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_ECDSA_C) + +#include "mbedtls/ecdsa.h" +#include "mbedtls/asn1write.h" +#include "mbedtls/platform_util.h" + +#if defined(MBEDTLS_ECDSA_SIGN_ALT) + +#include "cy_crypto_core_ecc.h" +#include "cy_crypto_core_vu.h" +#include "crypto_common.h" + +#include +#include + +/* Parameter validation macros based on platform_util.h */ +#define ECDSA_VALIDATE_RET( cond ) \ + MBEDTLS_INTERNAL_VALIDATE_RET( cond, MBEDTLS_ERR_ECP_BAD_INPUT_DATA ) +#define ECDSA_VALIDATE( cond ) \ + MBEDTLS_INTERNAL_VALIDATE( cond ) + +/** + * \brief This function computes the ECDSA signature of a + * previously-hashed message. + * + * \note The deterministic version is usually preferred. + * + * \note If the bitlength of the message hash is larger than the + * bitlength of the group order, then the hash is truncated + * as defined in Standards for Efficient Cryptography Group + * (SECG): SEC1 Elliptic Curve Cryptography, section + * 4.1.3, step 5. + * + * \see ecp.h + * + * \param grp The ECP group. + * \param r The first output integer. + * \param s The second output integer. + * \param d The private signing key. + * \param buf The message hash. + * \param blen The length of \p buf. + * \param f_rng The RNG function. + * \param p_rng The RNG context. + * + * \return \c 0 on success. + * \return An \c MBEDTLS_ERR_ECP_XXX + * or \c MBEDTLS_MPI_XXX error code on failure. + */ +int mbedtls_ecdsa_sign( mbedtls_ecp_group *grp, mbedtls_mpi *r, mbedtls_mpi *s, + const mbedtls_mpi *d, const unsigned char *buf, size_t blen, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) +{ + int ret; + size_t bytesize; + uint8_t *sig = NULL; + uint8_t *tmp_k = NULL; + cy_hw_crypto_t crypto_obj; + cy_stc_crypto_ecc_key key; + cy_stc_crypto_ecc_dp_type *dp; + cy_en_crypto_status_t ecdsa_status; + + ECDSA_VALIDATE_RET( grp != NULL ); + ECDSA_VALIDATE_RET( r != NULL ); + ECDSA_VALIDATE_RET( s != NULL ); + ECDSA_VALIDATE_RET( d != NULL ); + ECDSA_VALIDATE_RET( f_rng != NULL ); + ECDSA_VALIDATE_RET( buf != NULL || blen == 0 ); + + /* Fail cleanly on curves such as Curve25519 that can't be used for ECDSA */ + if( grp->N.p == NULL ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + key.curveID = cy_get_dp_idx(grp->id); + ECDSA_VALIDATE_RET( key.curveID != CY_CRYPTO_ECC_ECP_NONE); + + /* Make sure d is in range 1..n-1 */ + if( mbedtls_mpi_cmp_int( d, 1 ) < 0 || mbedtls_mpi_cmp_mpi( d, &grp->N ) >= 0 ) + return( MBEDTLS_ERR_ECP_INVALID_KEY ); + + /* Reserve the crypto hardware for the operation */ + cy_hw_crypto_reserve(&crypto_obj, CYHAL_CRYPTO_VU); + + dp = Cy_Crypto_Core_ECC_GetCurveParams(key.curveID); + + bytesize = CY_CRYPTO_BYTE_SIZE_OF_BITS(dp->size); + + key.k = malloc(bytesize); + MBEDTLS_MPI_CHK((key.k == NULL) ? MBEDTLS_ERR_ECP_ALLOC_FAILED : 0); + + MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary( d, key.k, bytesize ) ); + Cy_Crypto_Core_InvertEndianness(key.k, bytesize); + + sig = malloc(2 * bytesize); + MBEDTLS_MPI_CHK((sig == NULL) ? MBEDTLS_ERR_ECP_ALLOC_FAILED : 0); + + tmp_k = malloc(bytesize); + MBEDTLS_MPI_CHK((tmp_k == NULL) ? MBEDTLS_ERR_ECP_ALLOC_FAILED : 0); + + ecdsa_status = Cy_Crypto_Core_ECC_MakePrivateKey(crypto_obj.base, key.curveID, tmp_k, f_rng, p_rng); + MBEDTLS_MPI_CHK((ecdsa_status == CY_CRYPTO_SUCCESS) ? 0 : MBEDTLS_ERR_ECP_HW_ACCEL_FAILED); + + ecdsa_status = Cy_Crypto_Core_ECC_SignHash(crypto_obj.base, buf, blen, sig, &key, tmp_k); + MBEDTLS_MPI_CHK((ecdsa_status == CY_CRYPTO_SUCCESS) ? 0 : MBEDTLS_ERR_ECP_HW_ACCEL_FAILED); + + /* Prepare a signature to load into an mpi format */ + Cy_Crypto_Core_InvertEndianness(sig, bytesize); + Cy_Crypto_Core_InvertEndianness(sig + bytesize, bytesize); + + MBEDTLS_MPI_CHK( mbedtls_mpi_read_binary( r, sig, bytesize ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_read_binary( s, sig + bytesize, bytesize ) ); + +cleanup: + /* Realease the crypto hardware */ + cy_hw_crypto_release(&crypto_obj); + + if (key.k != NULL) + { + mbedtls_platform_zeroize(key.k, bytesize); + free(key.k); + } + if (sig != NULL) + { + mbedtls_platform_zeroize(sig, 2 * bytesize); + free(sig); + } + if (tmp_k != NULL) + { + mbedtls_platform_zeroize(tmp_k, bytesize); + free(tmp_k); + } + + return( ret ); +} +#endif /* MBEDTLS_ECDSA_SIGN_ALT */ + +#if defined(MBEDTLS_ECDSA_VERIFY_ALT) +/* + * Verify ECDSA signature of hashed message (SEC1 4.1.4) + * Obviously, compared to SEC1 4.1.3, we skip step 2 (hash message) + */ +int mbedtls_ecdsa_verify( mbedtls_ecp_group *grp, + const unsigned char *buf, size_t blen, + const mbedtls_ecp_point *Q, const mbedtls_mpi *r, const mbedtls_mpi *s) +{ + int ret; + uint8_t stat; + size_t bytesize; + size_t olen; + uint8_t *sig = NULL; + uint8_t *point_arr = NULL; + cy_hw_crypto_t crypto_obj; + cy_stc_crypto_ecc_key key; + cy_stc_crypto_ecc_dp_type *dp; + cy_en_crypto_status_t ecdsa_ver_status; + + ECDSA_VALIDATE_RET( grp != NULL ); + ECDSA_VALIDATE_RET( Q != NULL ); + ECDSA_VALIDATE_RET( r != NULL ); + ECDSA_VALIDATE_RET( s != NULL ); + ECDSA_VALIDATE_RET( buf != NULL || blen == 0 ); + + /* Fail cleanly on curves such as Curve25519 that can't be used for ECDSA */ + if( grp->N.p == NULL ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + key.curveID = cy_get_dp_idx(grp->id); + MBEDTLS_MPI_CHK( (key.curveID == CY_CRYPTO_ECC_ECP_NONE) ? MBEDTLS_ERR_ECP_BAD_INPUT_DATA : 0); + + /* Reserve the crypto hardware for the operation */ + cy_hw_crypto_reserve(&crypto_obj, CYHAL_CRYPTO_VU); + + dp = Cy_Crypto_Core_ECC_GetCurveParams(key.curveID); + + bytesize = CY_CRYPTO_BYTE_SIZE_OF_BITS(dp->size); + + point_arr = malloc(2 * bytesize + 1u); + MBEDTLS_MPI_CHK((point_arr == NULL) ? MBEDTLS_ERR_ECP_ALLOC_FAILED : 0); + key.pubkey.x = point_arr + 1u; + key.pubkey.y = point_arr + bytesize + 1u; + + sig = malloc(2 * bytesize); + MBEDTLS_MPI_CHK((sig == NULL) ? MBEDTLS_ERR_ECP_ALLOC_FAILED : 0); + + MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary( r, sig, bytesize ) ); + Cy_Crypto_Core_InvertEndianness(sig, bytesize); + + MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary( s, sig + bytesize, bytesize ) ); + Cy_Crypto_Core_InvertEndianness(sig + bytesize, bytesize); + + /* Export a signature from an mpi format to verify */ + MBEDTLS_MPI_CHK( mbedtls_ecp_point_write_binary( grp, Q, MBEDTLS_ECP_PF_UNCOMPRESSED, &olen, point_arr, 2 * bytesize + 1) ); + Cy_Crypto_Core_InvertEndianness(key.pubkey.x, bytesize); + Cy_Crypto_Core_InvertEndianness(key.pubkey.y, bytesize); + + ecdsa_ver_status = Cy_Crypto_Core_ECC_VerifyHash(crypto_obj.base, sig, buf, blen, &stat, &key); + MBEDTLS_MPI_CHK((ecdsa_ver_status != CY_CRYPTO_SUCCESS) ? MBEDTLS_ERR_ECP_HW_ACCEL_FAILED : 0); + + MBEDTLS_MPI_CHK((stat == 1) ? 0 : MBEDTLS_ERR_ECP_VERIFY_FAILED); + +cleanup: + /* Realease the crypto hardware */ + cy_hw_crypto_release(&crypto_obj); + + if (point_arr != NULL) + { + mbedtls_platform_zeroize(point_arr, 2 * bytesize + 1u); + free(point_arr); + } + if (sig != NULL) + { + mbedtls_platform_zeroize(sig, 2 * bytesize); + free(sig); + } + + return( ret ); +} +#endif /* MBEDTLS_ECDSA_VERIFY_ALT */ + +#endif /* MBEDTLS_ECDSA_C */ diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecp_alt.c b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecp_alt.c new file mode 100644 index 00000000000..37646e5ba74 --- /dev/null +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecp_alt.c @@ -0,0 +1,2829 @@ +/* + * Elliptic curves over GF(p): generic functions + * + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright (C) 2019 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * \file ecp_alt.c + * \version 1.0 + * + * References: + * + * SEC1 http://www.secg.org/index.php?action=secg,docs_secg + * GECC = Guide to Elliptic Curve Cryptography - Hankerson, Menezes, Vanstone + * FIPS 186-3 http://csrc.nist.gov/publications/fips/fips186-3/fips_186-3.pdf + * RFC 4492 for the related TLS structures and constants + * RFC 7748 for the Curve448 and Curve25519 curve definitions + * + * [Curve25519] http://cr.yp.to/ecdh/curve25519-20060209.pdf + * + * [2] CORON, Jean-S'ebastien. Resistance against differential power analysis + * for elliptic curve cryptosystems. In : Cryptographic Hardware and + * Embedded Systems. Springer Berlin Heidelberg, 1999. p. 292-302. + * + * + * [3] HEDABOU, Mustapha, PINEL, Pierre, et B'EN'ETEAU, Lucien. A comb method to + * render ECC resistant against Side Channel Attacks. IACR Cryptology + * ePrint Archive, 2004, vol. 2004, p. 342. + * + */ + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_ECP_C) + +#include "mbedtls/ecp.h" +#include "mbedtls/threading.h" +#include "mbedtls/platform_util.h" + +#if defined(MBEDTLS_ECP_ALT) + +#if defined(MBEDTLS_ECP_RESTARTABLE) +#error MBEDTLS_ECP_RESTARTABLE is not supported by Cypress implementation +#endif + +/* Parameter validation macros based on platform_util.h */ +#define ECP_VALIDATE_RET( cond ) \ + MBEDTLS_INTERNAL_VALIDATE_RET( cond, MBEDTLS_ERR_ECP_BAD_INPUT_DATA ) +#define ECP_VALIDATE( cond ) \ + MBEDTLS_INTERNAL_VALIDATE( cond ) + +#if defined(MBEDTLS_PLATFORM_C) +#include "mbedtls/platform.h" +#else +#include +#include +#define mbedtls_printf printf +#define mbedtls_calloc calloc +#define mbedtls_free free +#endif + +#include +#include "mbedtls/ecp_internal.h" + +#include "crypto_common.h" + +#include "cy_crypto_core_ecc_nist_p.h" + +#if ( defined(__ARMCC_VERSION) || defined(_MSC_VER) ) && \ + !defined(inline) && !defined(__cplusplus) +#define inline __inline +#endif + +#if defined(MBEDTLS_SELF_TEST) +/* + * Counts of point addition and doubling, and field multiplications. + * Used to test resistance of point multiplication to simple timing attacks. + */ +static unsigned long add_count, dbl_count, mul_count; +#endif + +#define ECP_RS_ENTER( sub ) (void) rs_ctx; +#define ECP_RS_LEAVE( sub ) (void) rs_ctx; + +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) +#define ECP_SHORTWEIERSTRASS +#endif + +#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) || \ + defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) +#define ECP_MONTGOMERY +#endif + +/* + * List of supported curves: + * - internal ID + * - TLS NamedCurve ID (RFC 4492 sec. 5.1.1, RFC 7071 sec. 2) + * - size in bits + * - readable name + * + * Curves are listed in order: largest curves first, and for a given size, + * fastest curves first. This provides the default order for the SSL module. + * + * Reminder: update profiles in Mbed TLS's x509_crt.c when adding new curves! + */ +static const mbedtls_ecp_curve_info ecp_supported_curves[] = +{ +#if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) + { MBEDTLS_ECP_DP_SECP521R1, 25, 521, "secp521r1" }, +#endif +#if defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) + { MBEDTLS_ECP_DP_BP512R1, 28, 512, "brainpoolP512r1" }, +#endif +#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) + { MBEDTLS_ECP_DP_SECP384R1, 24, 384, "secp384r1" }, +#endif +#if defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) + { MBEDTLS_ECP_DP_BP384R1, 27, 384, "brainpoolP384r1" }, +#endif +#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) + { MBEDTLS_ECP_DP_SECP256R1, 23, 256, "secp256r1" }, +#endif +#if defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) + { MBEDTLS_ECP_DP_SECP256K1, 22, 256, "secp256k1" }, +#endif +#if defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) + { MBEDTLS_ECP_DP_BP256R1, 26, 256, "brainpoolP256r1" }, +#endif +#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) + { MBEDTLS_ECP_DP_SECP224R1, 21, 224, "secp224r1" }, +#endif +#if defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) + { MBEDTLS_ECP_DP_SECP224K1, 20, 224, "secp224k1" }, +#endif +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) + { MBEDTLS_ECP_DP_SECP192R1, 19, 192, "secp192r1" }, +#endif +#if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) + { MBEDTLS_ECP_DP_SECP192K1, 18, 192, "secp192k1" }, +#endif + { MBEDTLS_ECP_DP_NONE, 0, 0, NULL }, +}; + +#define ECP_NB_CURVES sizeof( ecp_supported_curves ) / \ + sizeof( ecp_supported_curves[0] ) + +static mbedtls_ecp_group_id ecp_supported_grp_id[ECP_NB_CURVES]; + +/* + * List of supported curves and associated info + */ +const mbedtls_ecp_curve_info *mbedtls_ecp_curve_list( void ) +{ + return( ecp_supported_curves ); +} + +/* + * List of supported curves, group ID only + */ +const mbedtls_ecp_group_id *mbedtls_ecp_grp_id_list( void ) +{ + static int init_done = 0; + + if( ! init_done ) + { + size_t i = 0; + const mbedtls_ecp_curve_info *curve_info; + + for( curve_info = mbedtls_ecp_curve_list(); + curve_info->grp_id != MBEDTLS_ECP_DP_NONE; + curve_info++ ) + { + ecp_supported_grp_id[i++] = curve_info->grp_id; + } + ecp_supported_grp_id[i] = MBEDTLS_ECP_DP_NONE; + + init_done = 1; + } + + return( ecp_supported_grp_id ); +} + +/* + * Get the curve info for the internal identifier + */ +const mbedtls_ecp_curve_info *mbedtls_ecp_curve_info_from_grp_id( mbedtls_ecp_group_id grp_id ) +{ + const mbedtls_ecp_curve_info *curve_info; + + for( curve_info = mbedtls_ecp_curve_list(); + curve_info->grp_id != MBEDTLS_ECP_DP_NONE; + curve_info++ ) + { + if( curve_info->grp_id == grp_id ) + return( curve_info ); + } + + return( NULL ); +} + +/* + * Get the curve info from the TLS identifier + */ +const mbedtls_ecp_curve_info *mbedtls_ecp_curve_info_from_tls_id( uint16_t tls_id ) +{ + const mbedtls_ecp_curve_info *curve_info; + + for( curve_info = mbedtls_ecp_curve_list(); + curve_info->grp_id != MBEDTLS_ECP_DP_NONE; + curve_info++ ) + { + if( curve_info->tls_id == tls_id ) + return( curve_info ); + } + + return( NULL ); +} + +/* + * Get the curve info from the name + */ +const mbedtls_ecp_curve_info *mbedtls_ecp_curve_info_from_name( const char *name ) +{ + const mbedtls_ecp_curve_info *curve_info; + + if( name == NULL ) + return( NULL ); + + for( curve_info = mbedtls_ecp_curve_list(); + curve_info->grp_id != MBEDTLS_ECP_DP_NONE; + curve_info++ ) + { + if( strcmp( curve_info->name, name ) == 0 ) + return( curve_info ); + } + + return( NULL ); +} + +/* + * Get the type of a curve + */ +mbedtls_ecp_curve_type mbedtls_ecp_get_type( const mbedtls_ecp_group *grp ) +{ + if( grp->G.X.p == NULL ) + return( MBEDTLS_ECP_TYPE_NONE ); + + if( grp->G.Y.p == NULL ) + return( MBEDTLS_ECP_TYPE_MONTGOMERY ); + else + return( MBEDTLS_ECP_TYPE_SHORT_WEIERSTRASS ); +} + +/* + * Initialize (the components of) a point + */ +void mbedtls_ecp_point_init( mbedtls_ecp_point *pt ) +{ + ECP_VALIDATE( pt != NULL ); + + mbedtls_mpi_init( &pt->X ); + mbedtls_mpi_init( &pt->Y ); + mbedtls_mpi_init( &pt->Z ); +} + +/* + * Initialize (the components of) a group + */ +void mbedtls_ecp_group_init( mbedtls_ecp_group *grp ) +{ + ECP_VALIDATE( grp != NULL ); + + grp->id = MBEDTLS_ECP_DP_NONE; + mbedtls_mpi_init( &grp->P ); + mbedtls_mpi_init( &grp->A ); + mbedtls_mpi_init( &grp->B ); + mbedtls_ecp_point_init( &grp->G ); + mbedtls_mpi_init( &grp->N ); + grp->pbits = 0; + grp->nbits = 0; + grp->h = 0; + grp->modp = NULL; + grp->t_pre = NULL; + grp->t_post = NULL; + grp->t_data = NULL; + grp->T = NULL; + grp->T_size = 0; +} + +/* + * Initialize (the components of) a key pair + */ +void mbedtls_ecp_keypair_init( mbedtls_ecp_keypair *key ) +{ + ECP_VALIDATE( key != NULL ); + + mbedtls_ecp_group_init( &key->grp ); + mbedtls_mpi_init( &key->d ); + mbedtls_ecp_point_init( &key->Q ); +} + +/* + * Unallocate (the components of) a point + */ +void mbedtls_ecp_point_free( mbedtls_ecp_point *pt ) +{ + if( pt == NULL ) + return; + + mbedtls_mpi_free( &( pt->X ) ); + mbedtls_mpi_free( &( pt->Y ) ); + mbedtls_mpi_free( &( pt->Z ) ); +} + +/* + * Unallocate (the components of) a group + */ +void mbedtls_ecp_group_free( mbedtls_ecp_group *grp ) +{ + size_t i; + + if( grp == NULL ) + return; + + if( grp->h != 1 ) + { + mbedtls_mpi_free( &grp->P ); + mbedtls_mpi_free( &grp->A ); + mbedtls_mpi_free( &grp->B ); + mbedtls_ecp_point_free( &grp->G ); + mbedtls_mpi_free( &grp->N ); + } + + if( grp->T != NULL ) + { + for( i = 0; i < grp->T_size; i++ ) + mbedtls_ecp_point_free( &grp->T[i] ); + mbedtls_free( grp->T ); + } + + mbedtls_platform_zeroize( grp, sizeof( mbedtls_ecp_group ) ); +} + +/* + * Unallocate (the components of) a key pair + */ +void mbedtls_ecp_keypair_free( mbedtls_ecp_keypair *key ) +{ + if( key == NULL ) + return; + + mbedtls_ecp_group_free( &key->grp ); + mbedtls_mpi_free( &key->d ); + mbedtls_ecp_point_free( &key->Q ); +} + +/* + * Copy the contents of a point + */ +int mbedtls_ecp_copy( mbedtls_ecp_point *P, const mbedtls_ecp_point *Q ) +{ + int ret; + ECP_VALIDATE_RET( P != NULL ); + ECP_VALIDATE_RET( Q != NULL ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &P->X, &Q->X ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &P->Y, &Q->Y ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &P->Z, &Q->Z ) ); + +cleanup: + return( ret ); +} + +/* + * Copy the contents of a group object + */ +int mbedtls_ecp_group_copy( mbedtls_ecp_group *dst, const mbedtls_ecp_group *src ) +{ + ECP_VALIDATE_RET( dst != NULL ); + ECP_VALIDATE_RET( src != NULL ); + + return( mbedtls_ecp_group_load( dst, src->id ) ); +} + +/* + * Set point to zero + */ +int mbedtls_ecp_set_zero( mbedtls_ecp_point *pt ) +{ + int ret; + ECP_VALIDATE_RET( pt != NULL ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &pt->X , 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &pt->Y , 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &pt->Z , 0 ) ); + +cleanup: + return( ret ); +} + +/* + * Tell if a point is zero + */ +int mbedtls_ecp_is_zero( mbedtls_ecp_point *pt ) +{ + ECP_VALIDATE_RET( pt != NULL ); + + return( mbedtls_mpi_cmp_int( &pt->Z, 0 ) == 0 ); +} + +/* + * Compare two points lazily + */ +int mbedtls_ecp_point_cmp( const mbedtls_ecp_point *P, + const mbedtls_ecp_point *Q ) +{ + ECP_VALIDATE_RET( P != NULL ); + ECP_VALIDATE_RET( Q != NULL ); + + if( mbedtls_mpi_cmp_mpi( &P->X, &Q->X ) == 0 && + mbedtls_mpi_cmp_mpi( &P->Y, &Q->Y ) == 0 && + mbedtls_mpi_cmp_mpi( &P->Z, &Q->Z ) == 0 ) + { + return( 0 ); + } + + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); +} + +/* + * Import a non-zero point from ASCII strings + */ +int mbedtls_ecp_point_read_string( mbedtls_ecp_point *P, int radix, + const char *x, const char *y ) +{ + int ret; + ECP_VALIDATE_RET( P != NULL ); + ECP_VALIDATE_RET( x != NULL ); + ECP_VALIDATE_RET( y != NULL ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &P->X, radix, x ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &P->Y, radix, y ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &P->Z, 1 ) ); + +cleanup: + return( ret ); +} + +/* + * Export a point into unsigned binary data (SEC1 2.3.3 and RFC7748) + */ +int mbedtls_ecp_point_write_binary( const mbedtls_ecp_group *grp, + const mbedtls_ecp_point *P, + int format, size_t *olen, + unsigned char *buf, size_t buflen ) +{ + int ret = MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE; + size_t plen; + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( P != NULL ); + ECP_VALIDATE_RET( olen != NULL ); + ECP_VALIDATE_RET( buf != NULL ); + ECP_VALIDATE_RET( format == MBEDTLS_ECP_PF_UNCOMPRESSED || + format == MBEDTLS_ECP_PF_COMPRESSED ); + + plen = mbedtls_mpi_size( &grp->P ); + +#if defined(ECP_MONTGOMERY) + if( mbedtls_ecp_get_type( grp ) == MBEDTLS_ECP_TYPE_MONTGOMERY ) + { + *olen = plen; + if( buflen < *olen ) + return( MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary_le( &P->X, buf, plen ) ); + } +#endif +#if defined(ECP_SHORTWEIERSTRASS) + if( mbedtls_ecp_get_type( grp ) == MBEDTLS_ECP_TYPE_SHORT_WEIERSTRASS ) + { + /* + * Common case: P == 0 + */ + if( mbedtls_mpi_cmp_int( &P->Z, 0 ) == 0 ) + { + if( buflen < 1 ) + return( MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL ); + + buf[0] = 0x00; + *olen = 1; + + return( 0 ); + } + + if( format == MBEDTLS_ECP_PF_UNCOMPRESSED ) + { + *olen = 2 * plen + 1; + + if( buflen < *olen ) + return( MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL ); + + buf[0] = 0x04; + MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary( &P->X, buf + 1, plen ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary( &P->Y, buf + 1 + plen, plen ) ); + } + else if( format == MBEDTLS_ECP_PF_COMPRESSED ) + { + *olen = plen + 1; + + if( buflen < *olen ) + return( MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL ); + + buf[0] = 0x02 + mbedtls_mpi_get_bit( &P->Y, 0 ); + MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary( &P->X, buf + 1, plen ) ); + } + } +#endif + +cleanup: + return( ret ); +} + +/* + * Import a point from unsigned binary data (SEC1 2.3.4 and RFC7748) + */ +int mbedtls_ecp_point_read_binary( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *pt, + const unsigned char *buf, size_t ilen ) +{ + int ret = MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE; + size_t plen; + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( pt != NULL ); + ECP_VALIDATE_RET( buf != NULL ); + + if( ilen < 1 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + plen = mbedtls_mpi_size( &grp->P ); + +#if defined(ECP_MONTGOMERY) + if( mbedtls_ecp_get_type( grp ) == MBEDTLS_ECP_TYPE_MONTGOMERY ) + { + if( plen != ilen ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_read_binary_le( &pt->X, buf, plen ) ); + mbedtls_mpi_free( &pt->Y ); + + if( grp->id == MBEDTLS_ECP_DP_CURVE25519 ) + /* Set most significant bit to 0 as prescribed in RFC7748 �5 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_set_bit( &pt->X, plen * 8 - 1, 0 ) ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &pt->Z, 1 ) ); + } +#endif +#if defined(ECP_SHORTWEIERSTRASS) + if( mbedtls_ecp_get_type( grp ) == MBEDTLS_ECP_TYPE_SHORT_WEIERSTRASS ) + { + if( buf[0] == 0x00 ) + { + if( ilen == 1 ) + return( mbedtls_ecp_set_zero( pt ) ); + else + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + } + + if( buf[0] != 0x04 ) + return( MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE ); + + if( ilen != 2 * plen + 1 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_read_binary( &pt->X, buf + 1, plen ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_read_binary( &pt->Y, + buf + 1 + plen, plen ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &pt->Z, 1 ) ); + } +#endif + +cleanup: + return( ret ); +} + +/* + * Import a point from a TLS ECPoint record (RFC 4492) + * struct { + * opaque point <1..2^8-1>; + * } ECPoint; + */ +int mbedtls_ecp_tls_read_point( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *pt, + const unsigned char **buf, size_t buf_len ) +{ + unsigned char data_len; + const unsigned char *buf_start; + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( pt != NULL ); + ECP_VALIDATE_RET( buf != NULL ); + ECP_VALIDATE_RET( *buf != NULL ); + + /* + * We must have at least two bytes (1 for length, at least one for data) + */ + if( buf_len < 2 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + data_len = *(*buf)++; + if( data_len < 1 || data_len > buf_len - 1 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + /* + * Save buffer start for read_binary and update buf + */ + buf_start = *buf; + *buf += data_len; + + return( mbedtls_ecp_point_read_binary( grp, pt, buf_start, data_len ) ); +} + +/* + * Export a point as a TLS ECPoint record (RFC 4492) + * struct { + * opaque point <1..2^8-1>; + * } ECPoint; + */ +int mbedtls_ecp_tls_write_point( const mbedtls_ecp_group *grp, const mbedtls_ecp_point *pt, + int format, size_t *olen, + unsigned char *buf, size_t blen ) +{ + int ret; + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( pt != NULL ); + ECP_VALIDATE_RET( olen != NULL ); + ECP_VALIDATE_RET( buf != NULL ); + ECP_VALIDATE_RET( format == MBEDTLS_ECP_PF_UNCOMPRESSED || + format == MBEDTLS_ECP_PF_COMPRESSED ); + + /* + * buffer length must be at least one, for our length byte + */ + if( blen < 1 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + if( ( ret = mbedtls_ecp_point_write_binary( grp, pt, format, + olen, buf + 1, blen - 1) ) != 0 ) + return( ret ); + + /* + * write length to the first byte and update total length + */ + buf[0] = (unsigned char) *olen; + ++*olen; + + return( 0 ); +} + +/* + * Set a group from an ECParameters record (RFC 4492) + */ +int mbedtls_ecp_tls_read_group( mbedtls_ecp_group *grp, + const unsigned char **buf, size_t len ) +{ + int ret; + mbedtls_ecp_group_id grp_id; + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( buf != NULL ); + ECP_VALIDATE_RET( *buf != NULL ); + + if( ( ret = mbedtls_ecp_tls_read_group_id( &grp_id, buf, len ) ) != 0 ) + return( ret ); + + return( mbedtls_ecp_group_load( grp, grp_id ) ); +} + +/* + * Read a group id from an ECParameters record (RFC 4492) and convert it to + * mbedtls_ecp_group_id. + */ +int mbedtls_ecp_tls_read_group_id( mbedtls_ecp_group_id *grp, + const unsigned char **buf, size_t len ) +{ + uint16_t tls_id; + const mbedtls_ecp_curve_info *curve_info; + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( buf != NULL ); + ECP_VALIDATE_RET( *buf != NULL ); + + /* + * We expect at least three bytes (see below) + */ + if( len < 3 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + /* + * First byte is curve_type; only named_curve is handled + */ + if( *(*buf)++ != MBEDTLS_ECP_TLS_NAMED_CURVE ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + /* + * Next two bytes are the namedcurve value + */ + tls_id = *(*buf)++; + tls_id <<= 8; + tls_id |= *(*buf)++; + + if( ( curve_info = mbedtls_ecp_curve_info_from_tls_id( tls_id ) ) == NULL ) + return( MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE ); + + *grp = curve_info->grp_id; + + return( 0 ); +} + +/* + * Write the ECParameters record corresponding to a group (RFC 4492) + */ +int mbedtls_ecp_tls_write_group( const mbedtls_ecp_group *grp, size_t *olen, + unsigned char *buf, size_t blen ) +{ + const mbedtls_ecp_curve_info *curve_info; + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( buf != NULL ); + ECP_VALIDATE_RET( olen != NULL ); + + if( ( curve_info = mbedtls_ecp_curve_info_from_grp_id( grp->id ) ) == NULL ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + /* + * We are going to write 3 bytes (see below) + */ + *olen = 3; + if( blen < *olen ) + return( MBEDTLS_ERR_ECP_BUFFER_TOO_SMALL ); + + /* + * First byte is curve_type, always named_curve + */ + *buf++ = MBEDTLS_ECP_TLS_NAMED_CURVE; + + /* + * Next two bytes are the namedcurve value + */ + buf[0] = curve_info->tls_id >> 8; + buf[1] = curve_info->tls_id & 0xFF; + + return( 0 ); +} + +/* + * Wrapper around fast quasi-modp functions, with fall-back to mbedtls_mpi_mod_mpi. + * See the documentation of struct mbedtls_ecp_group. + * + * This function is in the critial loop for mbedtls_ecp_mul, so pay attention to perf. + */ +static int ecp_modp( mbedtls_mpi *N, const mbedtls_ecp_group *grp ) +{ + int ret; + + if( grp->modp == NULL ) + return( mbedtls_mpi_mod_mpi( N, N, &grp->P ) ); + + /* N->s < 0 is a much faster test, which fails only if N is 0 */ + if( ( N->s < 0 && mbedtls_mpi_cmp_int( N, 0 ) != 0 ) || + mbedtls_mpi_bitlen( N ) > 2 * grp->pbits ) + { + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + } + + MBEDTLS_MPI_CHK( grp->modp( N ) ); + + /* N->s < 0 is a much faster test, which fails only if N is 0 */ + while( N->s < 0 && mbedtls_mpi_cmp_int( N, 0 ) != 0 ) + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( N, N, &grp->P ) ); + + while( mbedtls_mpi_cmp_mpi( N, &grp->P ) >= 0 ) + /* we known P, N and the result are positive */ + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_abs( N, N, &grp->P ) ); + +cleanup: + return( ret ); +} + +/* + * Fast mod-p functions expect their argument to be in the 0..p^2 range. + * + * In order to guarantee that, we need to ensure that operands of + * mbedtls_mpi_mul_mpi are in the 0..p range. So, after each operation we will + * bring the result back to this range. + * + * The following macros are shortcuts for doing that. + */ + +/* + * Reduce a mbedtls_mpi mod p in-place, general case, to use after mbedtls_mpi_mul_mpi + */ +#if defined(MBEDTLS_SELF_TEST) +#define INC_MUL_COUNT mul_count++; +#else +#define INC_MUL_COUNT +#endif + +#define MOD_MUL( N ) \ + do \ + { \ + MBEDTLS_MPI_CHK( ecp_modp( &(N), grp ) ); \ + INC_MUL_COUNT \ + } while( 0 ) + +/* + * Reduce a mbedtls_mpi mod p in-place, to use after mbedtls_mpi_sub_mpi + * N->s < 0 is a very fast test, which fails only if N is 0 + */ +#define MOD_SUB( N ) \ + while( (N).s < 0 && mbedtls_mpi_cmp_int( &(N), 0 ) != 0 ) \ + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &(N), &(N), &grp->P ) ) + +/* + * Reduce a mbedtls_mpi mod p in-place, to use after mbedtls_mpi_add_mpi and mbedtls_mpi_mul_int. + * We known P, N and the result are positive, so sub_abs is correct, and + * a bit faster. + */ +#define MOD_ADD( N ) \ + while( mbedtls_mpi_cmp_mpi( &(N), &grp->P ) >= 0 ) \ + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_abs( &(N), &(N), &grp->P ) ) + +#if defined(ECP_SHORTWEIERSTRASS) +/* + * For curves in short Weierstrass form, we do all the internal operations in + * Jacobian coordinates. + * + * For multiplication, we'll use a comb method with coutermeasueres against + * SPA, hence timing attacks. + */ + +/* + * Normalize jacobian coordinates so that Z == 0 || Z == 1 (GECC 3.2.1) + * Cost: 1N := 1I + 3M + 1S + */ +static int ecp_normalize_jac( const mbedtls_ecp_group *grp, mbedtls_ecp_point *pt ) +{ + int ret; + mbedtls_mpi Zi, ZZi; + + if( mbedtls_mpi_cmp_int( &pt->Z, 0 ) == 0 ) + return( 0 ); + +#if defined(MBEDTLS_ECP_NORMALIZE_JAC_ALT) + if( mbedtls_internal_ecp_grp_capable( grp ) ) + return( mbedtls_internal_ecp_normalize_jac( grp, pt ) ); +#endif /* MBEDTLS_ECP_NORMALIZE_JAC_ALT */ + + mbedtls_mpi_init( &Zi ); mbedtls_mpi_init( &ZZi ); + + /* + * X = X / Z^2 mod p + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_inv_mod( &Zi, &pt->Z, &grp->P ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &ZZi, &Zi, &Zi ) ); MOD_MUL( ZZi ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &pt->X, &pt->X, &ZZi ) ); MOD_MUL( pt->X ); + + /* + * Y = Y / Z^3 mod p + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &pt->Y, &pt->Y, &ZZi ) ); MOD_MUL( pt->Y ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &pt->Y, &pt->Y, &Zi ) ); MOD_MUL( pt->Y ); + + /* + * Z = 1 + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &pt->Z, 1 ) ); + +cleanup: + + mbedtls_mpi_free( &Zi ); mbedtls_mpi_free( &ZZi ); + + return( ret ); +} + +/* + * Normalize jacobian coordinates of an array of (pointers to) points, + * using Montgomery's trick to perform only one inversion mod P. + * (See for example Cohen's "A Course in Computational Algebraic Number + * Theory", Algorithm 10.3.4.) + * + * Warning: fails (returning an error) if one of the points is zero! + * This should never happen, see choice of w in ecp_mul_comb(). + * + * Cost: 1N(t) := 1I + (6t - 3)M + 1S + */ +static int ecp_normalize_jac_many( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *T[], size_t T_size ) +{ + int ret; + size_t i; + mbedtls_mpi *c, u, Zi, ZZi; + + if( T_size < 2 ) + return( ecp_normalize_jac( grp, *T ) ); + +#if defined(MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT) + if( mbedtls_internal_ecp_grp_capable( grp ) ) + return( mbedtls_internal_ecp_normalize_jac_many( grp, T, T_size ) ); +#endif + + if( ( c = mbedtls_calloc( T_size, sizeof( mbedtls_mpi ) ) ) == NULL ) + return( MBEDTLS_ERR_ECP_ALLOC_FAILED ); + + for( i = 0; i < T_size; i++ ) + mbedtls_mpi_init( &c[i] ); + + mbedtls_mpi_init( &u ); mbedtls_mpi_init( &Zi ); mbedtls_mpi_init( &ZZi ); + + /* + * c[i] = Z_0 * ... * Z_i + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &c[0], &T[0]->Z ) ); + for( i = 1; i < T_size; i++ ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &c[i], &c[i-1], &T[i]->Z ) ); + MOD_MUL( c[i] ); + } + + /* + * u = 1 / (Z_0 * ... * Z_n) mod P + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_inv_mod( &u, &c[T_size-1], &grp->P ) ); + + for( i = T_size - 1; ; i-- ) + { + /* + * Zi = 1 / Z_i mod p + * u = 1 / (Z_0 * ... * Z_i) mod P + */ + if( i == 0 ) { + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &Zi, &u ) ); + } + else + { + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &Zi, &u, &c[i-1] ) ); MOD_MUL( Zi ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &u, &u, &T[i]->Z ) ); MOD_MUL( u ); + } + + /* + * proceed as in normalize() + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &ZZi, &Zi, &Zi ) ); MOD_MUL( ZZi ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T[i]->X, &T[i]->X, &ZZi ) ); MOD_MUL( T[i]->X ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T[i]->Y, &T[i]->Y, &ZZi ) ); MOD_MUL( T[i]->Y ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T[i]->Y, &T[i]->Y, &Zi ) ); MOD_MUL( T[i]->Y ); + + /* + * Post-precessing: reclaim some memory by shrinking coordinates + * - not storing Z (always 1) + * - shrinking other coordinates, but still keeping the same number of + * limbs as P, as otherwise it will too likely be regrown too fast. + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_shrink( &T[i]->X, grp->P.n ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shrink( &T[i]->Y, grp->P.n ) ); + mbedtls_mpi_free( &T[i]->Z ); + + if( i == 0 ) + break; + } + +cleanup: + + mbedtls_mpi_free( &u ); mbedtls_mpi_free( &Zi ); mbedtls_mpi_free( &ZZi ); + for( i = 0; i < T_size; i++ ) + mbedtls_mpi_free( &c[i] ); + mbedtls_free( c ); + + return( ret ); +} + +/* + * Conditional point inversion: Q -> -Q = (Q.X, -Q.Y, Q.Z) without leak. + * "inv" must be 0 (don't invert) or 1 (invert) or the result will be invalid + */ +static int ecp_safe_invert_jac( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *Q, + unsigned char inv ) +{ + int ret; + unsigned char nonzero; + mbedtls_mpi mQY; + + mbedtls_mpi_init( &mQY ); + + /* Use the fact that -Q.Y mod P = P - Q.Y unless Q.Y == 0 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &mQY, &grp->P, &Q->Y ) ); + nonzero = mbedtls_mpi_cmp_int( &Q->Y, 0 ) != 0; + MBEDTLS_MPI_CHK( mbedtls_mpi_safe_cond_assign( &Q->Y, &mQY, inv & nonzero ) ); + +cleanup: + mbedtls_mpi_free( &mQY ); + + return( ret ); +} + +/* + * Point doubling R = 2 P, Jacobian coordinates + * + * Based on http://www.hyperelliptic.org/EFD/g1p/auto-shortw-jacobian.html#doubling-dbl-1998-cmo-2 . + * + * We follow the variable naming fairly closely. The formula variations that trade a MUL for a SQR + * (plus a few ADDs) aren't useful as our bignum implementation doesn't distinguish squaring. + * + * Standard optimizations are applied when curve parameter A is one of { 0, -3 }. + * + * Cost: 1D := 3M + 4S (A == 0) + * 4M + 4S (A == -3) + * 3M + 6S + 1a otherwise + */ +static int ecp_double_jac( const mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_ecp_point *P ) +{ + int ret; + mbedtls_mpi M, S, T, U; + +#if defined(MBEDTLS_SELF_TEST) + dbl_count++; +#endif + +#if defined(MBEDTLS_ECP_DOUBLE_JAC_ALT) + if( mbedtls_internal_ecp_grp_capable( grp ) ) + return( mbedtls_internal_ecp_double_jac( grp, R, P ) ); +#endif /* MBEDTLS_ECP_DOUBLE_JAC_ALT */ + + mbedtls_mpi_init( &M ); mbedtls_mpi_init( &S ); mbedtls_mpi_init( &T ); mbedtls_mpi_init( &U ); + + /* Special case for A = -3 */ + if( grp->A.p == NULL ) + { + /* M = 3(X + Z^2)(X - Z^2) */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &S, &P->Z, &P->Z ) ); MOD_MUL( S ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &T, &P->X, &S ) ); MOD_ADD( T ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &U, &P->X, &S ) ); MOD_SUB( U ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &S, &T, &U ) ); MOD_MUL( S ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_int( &M, &S, 3 ) ); MOD_ADD( M ); + } + else + { + /* M = 3.X^2 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &S, &P->X, &P->X ) ); MOD_MUL( S ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_int( &M, &S, 3 ) ); MOD_ADD( M ); + + /* Optimize away for "koblitz" curves with A = 0 */ + if( mbedtls_mpi_cmp_int( &grp->A, 0 ) != 0 ) + { + /* M += A.Z^4 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &S, &P->Z, &P->Z ) ); MOD_MUL( S ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T, &S, &S ) ); MOD_MUL( T ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &S, &T, &grp->A ) ); MOD_MUL( S ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &M, &M, &S ) ); MOD_ADD( M ); + } + } + + /* S = 4.X.Y^2 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T, &P->Y, &P->Y ) ); MOD_MUL( T ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &T, 1 ) ); MOD_ADD( T ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &S, &P->X, &T ) ); MOD_MUL( S ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &S, 1 ) ); MOD_ADD( S ); + + /* U = 8.Y^4 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &U, &T, &T ) ); MOD_MUL( U ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &U, 1 ) ); MOD_ADD( U ); + + /* T = M^2 - 2.S */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T, &M, &M ) ); MOD_MUL( T ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &T, &T, &S ) ); MOD_SUB( T ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &T, &T, &S ) ); MOD_SUB( T ); + + /* S = M(S - T) - U */ + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &S, &S, &T ) ); MOD_SUB( S ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &S, &S, &M ) ); MOD_MUL( S ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &S, &S, &U ) ); MOD_SUB( S ); + + /* U = 2.Y.Z */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &U, &P->Y, &P->Z ) ); MOD_MUL( U ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &U, 1 ) ); MOD_ADD( U ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &R->X, &T ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &R->Y, &S ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &R->Z, &U ) ); + +cleanup: + mbedtls_mpi_free( &M ); mbedtls_mpi_free( &S ); mbedtls_mpi_free( &T ); mbedtls_mpi_free( &U ); + + return( ret ); +} + +/* + * Addition: R = P + Q, mixed affine-Jacobian coordinates (GECC 3.22) + * + * The coordinates of Q must be normalized (= affine), + * but those of P don't need to. R is not normalized. + * + * Special cases: (1) P or Q is zero, (2) R is zero, (3) P == Q. + * None of these cases can happen as intermediate step in ecp_mul_comb(): + * - at each step, P, Q and R are multiples of the base point, the factor + * being less than its order, so none of them is zero; + * - Q is an odd multiple of the base point, P an even multiple, + * due to the choice of precomputed points in the modified comb method. + * So branches for these cases do not leak secret information. + * + * We accept Q->Z being unset (saving memory in tables) as meaning 1. + * + * Cost: 1A := 8M + 3S + */ +static int ecp_add_mixed( const mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_ecp_point *P, const mbedtls_ecp_point *Q ) +{ + int ret; + mbedtls_mpi T1, T2, T3, T4, X, Y, Z; + +#if defined(MBEDTLS_SELF_TEST) + add_count++; +#endif + +#if defined(MBEDTLS_ECP_ADD_MIXED_ALT) + if( mbedtls_internal_ecp_grp_capable( grp ) ) + return( mbedtls_internal_ecp_add_mixed( grp, R, P, Q ) ); +#endif /* MBEDTLS_ECP_ADD_MIXED_ALT */ + + /* + * Trivial cases: P == 0 or Q == 0 (case 1) + */ + if( mbedtls_mpi_cmp_int( &P->Z, 0 ) == 0 ) + return( mbedtls_ecp_copy( R, Q ) ); + + if( Q->Z.p != NULL && mbedtls_mpi_cmp_int( &Q->Z, 0 ) == 0 ) + return( mbedtls_ecp_copy( R, P ) ); + + /* + * Make sure Q coordinates are normalized + */ + if( Q->Z.p != NULL && mbedtls_mpi_cmp_int( &Q->Z, 1 ) != 0 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + mbedtls_mpi_init( &T1 ); mbedtls_mpi_init( &T2 ); mbedtls_mpi_init( &T3 ); mbedtls_mpi_init( &T4 ); + mbedtls_mpi_init( &X ); mbedtls_mpi_init( &Y ); mbedtls_mpi_init( &Z ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T1, &P->Z, &P->Z ) ); MOD_MUL( T1 ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T2, &T1, &P->Z ) ); MOD_MUL( T2 ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T1, &T1, &Q->X ) ); MOD_MUL( T1 ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T2, &T2, &Q->Y ) ); MOD_MUL( T2 ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &T1, &T1, &P->X ) ); MOD_SUB( T1 ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &T2, &T2, &P->Y ) ); MOD_SUB( T2 ); + + /* Special cases (2) and (3) */ + if( mbedtls_mpi_cmp_int( &T1, 0 ) == 0 ) + { + if( mbedtls_mpi_cmp_int( &T2, 0 ) == 0 ) + { + ret = ecp_double_jac( grp, R, P ); + goto cleanup; + } + else + { + ret = mbedtls_ecp_set_zero( R ); + goto cleanup; + } + } + + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &Z, &P->Z, &T1 ) ); MOD_MUL( Z ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T3, &T1, &T1 ) ); MOD_MUL( T3 ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T4, &T3, &T1 ) ); MOD_MUL( T4 ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T3, &T3, &P->X ) ); MOD_MUL( T3 ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_int( &T1, &T3, 2 ) ); MOD_ADD( T1 ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &X, &T2, &T2 ) ); MOD_MUL( X ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &X, &X, &T1 ) ); MOD_SUB( X ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &X, &X, &T4 ) ); MOD_SUB( X ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &T3, &T3, &X ) ); MOD_SUB( T3 ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T3, &T3, &T2 ) ); MOD_MUL( T3 ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &T4, &T4, &P->Y ) ); MOD_MUL( T4 ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &Y, &T3, &T4 ) ); MOD_SUB( Y ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &R->X, &X ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &R->Y, &Y ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &R->Z, &Z ) ); + +cleanup: + + mbedtls_mpi_free( &T1 ); mbedtls_mpi_free( &T2 ); mbedtls_mpi_free( &T3 ); mbedtls_mpi_free( &T4 ); + mbedtls_mpi_free( &X ); mbedtls_mpi_free( &Y ); mbedtls_mpi_free( &Z ); + + return( ret ); +} + +/* + * Randomize jacobian coordinates: + * (X, Y, Z) -> (l^2 X, l^3 Y, l Z) for random l + * This is sort of the reverse operation of ecp_normalize_jac(). + * + * This countermeasure was first suggested in [2]. + */ +static int ecp_randomize_jac( const mbedtls_ecp_group *grp, mbedtls_ecp_point *pt, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) +{ + int ret; + mbedtls_mpi l, ll; + size_t p_size; + int count = 0; + +#if defined(MBEDTLS_ECP_RANDOMIZE_JAC_ALT) + if( mbedtls_internal_ecp_grp_capable( grp ) ) + return( mbedtls_internal_ecp_randomize_jac( grp, pt, f_rng, p_rng ) ); +#endif /* MBEDTLS_ECP_RANDOMIZE_JAC_ALT */ + + p_size = ( grp->pbits + 7 ) / 8; + mbedtls_mpi_init( &l ); mbedtls_mpi_init( &ll ); + + /* Generate l such that 1 < l < p */ + do + { + MBEDTLS_MPI_CHK( mbedtls_mpi_fill_random( &l, p_size, f_rng, p_rng ) ); + + while( mbedtls_mpi_cmp_mpi( &l, &grp->P ) >= 0 ) + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &l, 1 ) ); + + if( count++ > 10 ) + return( MBEDTLS_ERR_ECP_RANDOM_FAILED ); + } + while( mbedtls_mpi_cmp_int( &l, 1 ) <= 0 ); + + /* Z = l * Z */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &pt->Z, &pt->Z, &l ) ); MOD_MUL( pt->Z ); + + /* X = l^2 * X */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &ll, &l, &l ) ); MOD_MUL( ll ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &pt->X, &pt->X, &ll ) ); MOD_MUL( pt->X ); + + /* Y = l^3 * Y */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &ll, &ll, &l ) ); MOD_MUL( ll ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &pt->Y, &pt->Y, &ll ) ); MOD_MUL( pt->Y ); + +cleanup: + mbedtls_mpi_free( &l ); mbedtls_mpi_free( &ll ); + + return( ret ); +} + +/* + * Check and define parameters used by the comb method (see below for details) + */ +#if MBEDTLS_ECP_WINDOW_SIZE < 2 || MBEDTLS_ECP_WINDOW_SIZE > 7 +#error "MBEDTLS_ECP_WINDOW_SIZE out of bounds" +#endif + +/* d = ceil( n / w ) */ +#define COMB_MAX_D ( MBEDTLS_ECP_MAX_BITS + 1 ) / 2 + +/* number of precomputed points */ +#define COMB_MAX_PRE ( 1 << ( MBEDTLS_ECP_WINDOW_SIZE - 1 ) ) + +/* + * Compute the representation of m that will be used with our comb method. + * + * The basic comb method is described in GECC 3.44 for example. We use a + * modified version that provides resistance to SPA by avoiding zero + * digits in the representation as in [3]. We modify the method further by + * requiring that all K_i be odd, which has the small cost that our + * representation uses one more K_i, due to carries, but saves on the size of + * the precomputed table. + * + * Summary of the comb method and its modifications: + * + * - The goal is to compute m*P for some w*d-bit integer m. + * + * - The basic comb method splits m into the w-bit integers + * x[0] .. x[d-1] where x[i] consists of the bits in m whose + * index has residue i modulo d, and computes m * P as + * S[x[0]] + 2 * S[x[1]] + .. + 2^(d-1) S[x[d-1]], where + * S[i_{w-1} .. i_0] := i_{w-1} 2^{(w-1)d} P + ... + i_1 2^d P + i_0 P. + * + * - If it happens that, say, x[i+1]=0 (=> S[x[i+1]]=0), one can replace the sum by + * .. + 2^{i-1} S[x[i-1]] - 2^i S[x[i]] + 2^{i+1} S[x[i]] + 2^{i+2} S[x[i+2]] .., + * thereby successively converting it into a form where all summands + * are nonzero, at the cost of negative summands. This is the basic idea of [3]. + * + * - More generally, even if x[i+1] != 0, we can first transform the sum as + * .. - 2^i S[x[i]] + 2^{i+1} ( S[x[i]] + S[x[i+1]] ) + 2^{i+2} S[x[i+2]] .., + * and then replace S[x[i]] + S[x[i+1]] = S[x[i] ^ x[i+1]] + 2 S[x[i] & x[i+1]]. + * Performing and iterating this procedure for those x[i] that are even + * (keeping track of carry), we can transform the original sum into one of the form + * S[x'[0]] +- 2 S[x'[1]] +- .. +- 2^{d-1} S[x'[d-1]] + 2^d S[x'[d]] + * with all x'[i] odd. It is therefore only necessary to know S at odd indices, + * which is why we are only computing half of it in the first place in + * ecp_precompute_comb and accessing it with index abs(i) / 2 in ecp_select_comb. + * + * - For the sake of compactness, only the seven low-order bits of x[i] + * are used to represent its absolute value (K_i in the paper), and the msb + * of x[i] encodes the sign (s_i in the paper): it is set if and only if + * if s_i == -1; + * + * Calling conventions: + * - x is an array of size d + 1 + * - w is the size, ie number of teeth, of the comb, and must be between + * 2 and 7 (in practice, between 2 and MBEDTLS_ECP_WINDOW_SIZE) + * - m is the MPI, expected to be odd and such that bitlength(m) <= w * d + * (the result will be incorrect if these assumptions are not satisfied) + */ +static void ecp_comb_recode_core( unsigned char x[], size_t d, + unsigned char w, const mbedtls_mpi *m ) +{ + size_t i, j; + unsigned char c, cc, adjust; + + memset( x, 0, d+1 ); + + /* First get the classical comb values (except for x_d = 0) */ + for( i = 0; i < d; i++ ) + for( j = 0; j < w; j++ ) + x[i] |= mbedtls_mpi_get_bit( m, i + d * j ) << j; + + /* Now make sure x_1 .. x_d are odd */ + c = 0; + for( i = 1; i <= d; i++ ) + { + /* Add carry and update it */ + cc = x[i] & c; + x[i] = x[i] ^ c; + c = cc; + + /* Adjust if needed, avoiding branches */ + adjust = 1 - ( x[i] & 0x01 ); + c |= x[i] & ( x[i-1] * adjust ); + x[i] = x[i] ^ ( x[i-1] * adjust ); + x[i-1] |= adjust << 7; + } +} + +/* + * Precompute points for the adapted comb method + * + * Assumption: T must be able to hold 2^{w - 1} elements. + * + * Operation: If i = i_{w-1} ... i_1 is the binary representation of i, + * sets T[i] = i_{w-1} 2^{(w-1)d} P + ... + i_1 2^d P + P. + * + * Cost: d(w-1) D + (2^{w-1} - 1) A + 1 N(w-1) + 1 N(2^{w-1} - 1) + * + * Note: Even comb values (those where P would be omitted from the + * sum defining T[i] above) are not needed in our adaption + * the comb method. See ecp_comb_recode_core(). + * + * This function currently works in four steps: + * (1) [dbl] Computation of intermediate T[i] for 2-power values of i + * (2) [norm_dbl] Normalization of coordinates of these T[i] + * (3) [add] Computation of all T[i] + * (4) [norm_add] Normalization of all T[i] + * + * Step 1 can be interrupted but not the others; together with the final + * coordinate normalization they are the largest steps done at once, depending + * on the window size. Here are operation counts for P-256: + * + * step (2) (3) (4) + * w = 5 142 165 208 + * w = 4 136 77 160 + * w = 3 130 33 136 + * w = 2 124 11 124 + * + * So if ECC operations are blocking for too long even with a low max_ops + * value, it's useful to set MBEDTLS_ECP_WINDOW_SIZE to a lower value in order + * to minimize maximum blocking time. + */ +static int ecp_precompute_comb( const mbedtls_ecp_group *grp, + mbedtls_ecp_point T[], const mbedtls_ecp_point *P, + unsigned char w, size_t d, + mbedtls_ecp_restart_ctx *rs_ctx ) +{ + int ret; + unsigned char i; + size_t j = 0; + const unsigned char T_size = 1U << ( w - 1 ); + mbedtls_ecp_point *cur, *TT[COMB_MAX_PRE - 1]; + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL ) + { + if( rs_ctx->rsm->state == ecp_rsm_pre_dbl ) + goto dbl; + if( rs_ctx->rsm->state == ecp_rsm_pre_norm_dbl ) + goto norm_dbl; + if( rs_ctx->rsm->state == ecp_rsm_pre_add ) + goto add; + if( rs_ctx->rsm->state == ecp_rsm_pre_norm_add ) + goto norm_add; + } +#else + (void) rs_ctx; +#endif + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL ) + { + rs_ctx->rsm->state = ecp_rsm_pre_dbl; + + /* initial state for the loop */ + rs_ctx->rsm->i = 0; + } + +dbl: +#endif + /* + * Set T[0] = P and + * T[2^{l-1}] = 2^{dl} P for l = 1 .. w-1 (this is not the final value) + */ + MBEDTLS_MPI_CHK( mbedtls_ecp_copy( &T[0], P ) ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL && rs_ctx->rsm->i != 0 ) + j = rs_ctx->rsm->i; + else +#endif + j = 0; + + for( ; j < d * ( w - 1 ); j++ ) + { + MBEDTLS_ECP_BUDGET( MBEDTLS_ECP_OPS_DBL ); + + i = 1U << ( j / d ); + cur = T + i; + + if( j % d == 0 ) + MBEDTLS_MPI_CHK( mbedtls_ecp_copy( cur, T + ( i >> 1 ) ) ); + + MBEDTLS_MPI_CHK( ecp_double_jac( grp, cur, cur ) ); + } + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL ) + rs_ctx->rsm->state = ecp_rsm_pre_norm_dbl; + +norm_dbl: +#endif + /* + * Normalize current elements in T. As T has holes, + * use an auxiliary array of pointers to elements in T. + */ + j = 0; + for( i = 1; i < T_size; i <<= 1 ) + TT[j++] = T + i; + + MBEDTLS_ECP_BUDGET( MBEDTLS_ECP_OPS_INV + 6 * j - 2 ); + + MBEDTLS_MPI_CHK( ecp_normalize_jac_many( grp, TT, j ) ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL ) + rs_ctx->rsm->state = ecp_rsm_pre_add; + +add: +#endif + /* + * Compute the remaining ones using the minimal number of additions + * Be careful to update T[2^l] only after using it! + */ + MBEDTLS_ECP_BUDGET( ( T_size - 1 ) * MBEDTLS_ECP_OPS_ADD ); + + for( i = 1; i < T_size; i <<= 1 ) + { + j = i; + while( j-- ) + MBEDTLS_MPI_CHK( ecp_add_mixed( grp, &T[i + j], &T[j], &T[i] ) ); + } + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL ) + rs_ctx->rsm->state = ecp_rsm_pre_norm_add; + +norm_add: +#endif + /* + * Normalize final elements in T. Even though there are no holes now, we + * still need the auxiliary array for homogeneity with the previous + * call. Also, skip T[0] which is already normalised, being a copy of P. + */ + for( j = 0; j + 1 < T_size; j++ ) + TT[j] = T + j + 1; + + MBEDTLS_ECP_BUDGET( MBEDTLS_ECP_OPS_INV + 6 * j - 2 ); + + MBEDTLS_MPI_CHK( ecp_normalize_jac_many( grp, TT, j ) ); + +cleanup: +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL && + ret == MBEDTLS_ERR_ECP_IN_PROGRESS ) + { + if( rs_ctx->rsm->state == ecp_rsm_pre_dbl ) + rs_ctx->rsm->i = j; + } +#endif + + return( ret ); +} + +/* + * Select precomputed point: R = sign(i) * T[ abs(i) / 2 ] + * + * See ecp_comb_recode_core() for background + */ +static int ecp_select_comb( const mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_ecp_point T[], unsigned char T_size, + unsigned char i ) +{ + int ret; + unsigned char ii, j; + + /* Ignore the "sign" bit and scale down */ + ii = ( i & 0x7Fu ) >> 1; + + /* Read the whole table to thwart cache-based timing attacks */ + for( j = 0; j < T_size; j++ ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_safe_cond_assign( &R->X, &T[j].X, j == ii ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_safe_cond_assign( &R->Y, &T[j].Y, j == ii ) ); + } + + /* Safely invert result if i is "negative" */ + MBEDTLS_MPI_CHK( ecp_safe_invert_jac( grp, R, i >> 7 ) ); + +cleanup: + return( ret ); +} + +/* + * Core multiplication algorithm for the (modified) comb method. + * This part is actually common with the basic comb method (GECC 3.44) + * + * Cost: d A + d D + 1 R + */ +static int ecp_mul_comb_core( const mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_ecp_point T[], unsigned char T_size, + const unsigned char x[], size_t d, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + mbedtls_ecp_restart_ctx *rs_ctx ) +{ + int ret; + mbedtls_ecp_point Txi; + size_t i; + + mbedtls_ecp_point_init( &Txi ); + +#if !defined(MBEDTLS_ECP_RESTARTABLE) + (void) rs_ctx; +#endif + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL && + rs_ctx->rsm->state != ecp_rsm_comb_core ) + { + rs_ctx->rsm->i = 0; + rs_ctx->rsm->state = ecp_rsm_comb_core; + } + + /* new 'if' instead of nested for the sake of the 'else' branch */ + if( rs_ctx != NULL && rs_ctx->rsm != NULL && rs_ctx->rsm->i != 0 ) + { + /* restore current index (R already pointing to rs_ctx->rsm->R) */ + i = rs_ctx->rsm->i; + } + else +#endif + { + /* Start with a non-zero point and randomize its coordinates */ + i = d; + MBEDTLS_MPI_CHK( ecp_select_comb( grp, R, T, T_size, x[i] ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &R->Z, 1 ) ); + if( f_rng != 0 ) + MBEDTLS_MPI_CHK( ecp_randomize_jac( grp, R, f_rng, p_rng ) ); + } + + while( i != 0 ) + { + MBEDTLS_ECP_BUDGET( MBEDTLS_ECP_OPS_DBL + MBEDTLS_ECP_OPS_ADD ); + --i; + + MBEDTLS_MPI_CHK( ecp_double_jac( grp, R, R ) ); + MBEDTLS_MPI_CHK( ecp_select_comb( grp, &Txi, T, T_size, x[i] ) ); + MBEDTLS_MPI_CHK( ecp_add_mixed( grp, R, R, &Txi ) ); + } + +cleanup: + + mbedtls_ecp_point_free( &Txi ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL && + ret == MBEDTLS_ERR_ECP_IN_PROGRESS ) + { + rs_ctx->rsm->i = i; + /* no need to save R, already pointing to rs_ctx->rsm->R */ + } +#endif + + return( ret ); +} + +/* + * Recode the scalar to get constant-time comb multiplication + * + * As the actual scalar recoding needs an odd scalar as a starting point, + * this wrapper ensures that by replacing m by N - m if necessary, and + * informs the caller that the result of multiplication will be negated. + * + * This works because we only support large prime order for Short Weierstrass + * curves, so N is always odd hence either m or N - m is. + * + * See ecp_comb_recode_core() for background. + */ +static int ecp_comb_recode_scalar( const mbedtls_ecp_group *grp, + const mbedtls_mpi *m, + unsigned char k[COMB_MAX_D + 1], + size_t d, + unsigned char w, + unsigned char *parity_trick ) +{ + int ret; + mbedtls_mpi M, mm; + + mbedtls_mpi_init( &M ); + mbedtls_mpi_init( &mm ); + + /* N is always odd (see above), just make extra sure */ + if( mbedtls_mpi_get_bit( &grp->N, 0 ) != 1 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + /* do we need the parity trick? */ + *parity_trick = ( mbedtls_mpi_get_bit( m, 0 ) == 0 ); + + /* execute parity fix in constant time */ + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &M, m ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &mm, &grp->N, m ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_safe_cond_assign( &M, &mm, *parity_trick ) ); + + /* actual scalar recoding */ + ecp_comb_recode_core( k, d, w, &M ); + +cleanup: + mbedtls_mpi_free( &mm ); + mbedtls_mpi_free( &M ); + + return( ret ); +} + +/* + * Perform comb multiplication (for short Weierstrass curves) + * once the auxiliary table has been pre-computed. + * + * Scalar recoding may use a parity trick that makes us compute -m * P, + * if that is the case we'll need to recover m * P at the end. + */ +static int ecp_mul_comb_after_precomp( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *R, + const mbedtls_mpi *m, + const mbedtls_ecp_point *T, + unsigned char T_size, + unsigned char w, + size_t d, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + mbedtls_ecp_restart_ctx *rs_ctx ) +{ + int ret; + unsigned char parity_trick; + unsigned char k[COMB_MAX_D + 1]; + mbedtls_ecp_point *RR = R; + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL ) + { + RR = &rs_ctx->rsm->R; + + if( rs_ctx->rsm->state == ecp_rsm_final_norm ) + goto final_norm; + } +#endif + + MBEDTLS_MPI_CHK( ecp_comb_recode_scalar( grp, m, k, d, w, + &parity_trick ) ); + MBEDTLS_MPI_CHK( ecp_mul_comb_core( grp, RR, T, T_size, k, d, + f_rng, p_rng, rs_ctx ) ); + MBEDTLS_MPI_CHK( ecp_safe_invert_jac( grp, RR, parity_trick ) ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL ) + rs_ctx->rsm->state = ecp_rsm_final_norm; + +final_norm: +#endif + MBEDTLS_ECP_BUDGET( MBEDTLS_ECP_OPS_INV ); + MBEDTLS_MPI_CHK( ecp_normalize_jac( grp, RR ) ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->rsm != NULL ) + MBEDTLS_MPI_CHK( mbedtls_ecp_copy( R, RR ) ); +#endif + +cleanup: + return( ret ); +} + +/* + * Pick window size based on curve size and whether we optimize for base point + */ +static unsigned char ecp_pick_window_size( const mbedtls_ecp_group *grp, + unsigned char p_eq_g ) +{ + unsigned char w; + + /* + * Minimize the number of multiplications, that is minimize + * 10 * d * w + 18 * 2^(w-1) + 11 * d + 7 * w, with d = ceil( nbits / w ) + * (see costs of the various parts, with 1S = 1M) + */ + w = grp->nbits >= 384 ? 5 : 4; + + /* + * If P == G, pre-compute a bit more, since this may be re-used later. + * Just adding one avoids upping the cost of the first mul too much, + * and the memory cost too. + */ + if( p_eq_g ) + w++; + + /* + * Make sure w is within bounds. + * (The last test is useful only for very small curves in the test suite.) + */ + if( w > MBEDTLS_ECP_WINDOW_SIZE ) + w = MBEDTLS_ECP_WINDOW_SIZE; + if( w >= grp->nbits ) + w = 2; + + return( w ); +} + +/* + * Multiplication using the comb method - for curves in short Weierstrass form + * + * This function is mainly responsible for administrative work: + * - managing the restart context if enabled + * - managing the table of precomputed points (passed between the below two + * functions): allocation, computation, ownership tranfer, freeing. + * + * It delegates the actual arithmetic work to: + * ecp_precompute_comb() and ecp_mul_comb_with_precomp() + * + * See comments on ecp_comb_recode_core() regarding the computation strategy. + */ +/* + * Multiplication using the comb method, + * for curves in short Weierstrass form + * + * CYPRESS EDITION + */ +static int ecp_mul_comb( mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_mpi *m, const mbedtls_ecp_point *P, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + mbedtls_ecp_restart_ctx *rs_ctx ) +{ + + #define ciL (sizeof(mbedtls_mpi_uint)) /* chars in limb */ + #define biL (ciL << 3) /* bits in limb */ + #define BITS_TO_LIMBS(i) ((i) / biL + ((i) % biL != 0)) + uint32_t data_size = BITS_TO_LIMBS(grp->pbits); + + int ret; + + (void)f_rng; + (void)p_rng; + + mbedtls_mpi di; + mbedtls_ecp_point Pi; + + cy_hw_crypto_t crypto_obj; + + cy_en_crypto_ecc_curve_id_t curveId = cy_get_dp_idx(grp->id); + + if (curveId == CY_CRYPTO_ECC_ECP_NONE) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + /* we need N to be odd to transform m in an odd number, check now */ + if( mbedtls_mpi_get_bit( &grp->N, 0 ) != 1 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + + cy_hw_crypto_reserve(&crypto_obj, CYHAL_CRYPTO_VU); + + mbedtls_mpi_init(&di); + MBEDTLS_MPI_CHK( mbedtls_mpi_copy(&di, m) ); + + mbedtls_ecp_point_init(&Pi); + MBEDTLS_MPI_CHK( mbedtls_ecp_copy( &Pi, P ) ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_grow(&di, data_size) ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_grow(&Pi.X, data_size) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_grow(&Pi.Y, data_size) ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_grow(&R->X, data_size) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_grow(&R->Y, data_size) ); + + Cy_Crypto_Core_EC_NistP_PointMultiplication (crypto_obj.base, + curveId, + (uint8_t *)Pi.X.p, (uint8_t *)Pi.Y.p, + (uint8_t *)di.p, + (uint8_t *)R->X.p, (uint8_t *)R->Y.p); + + /* R.Z coordinate should be 1 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &R->Z, 1 ) ); + +cleanup: + + mbedtls_mpi_free(&di); + mbedtls_ecp_point_free(&Pi); + + if( ret != 0 ) + mbedtls_ecp_point_free( R ); + + cy_hw_crypto_release(&crypto_obj); + + return( ret ); +} + +#endif /* ECP_SHORTWEIERSTRASS */ + +#if defined(ECP_MONTGOMERY) +/* + * For Montgomery curves, we do all the internal arithmetic in projective + * coordinates. Import/export of points uses only the x coordinates, which is + * internaly represented as X / Z. + * + * For scalar multiplication, we'll use a Montgomery ladder. + */ + +/* + * Normalize Montgomery x/z coordinates: X = X/Z, Z = 1 + * Cost: 1M + 1I + */ +static int ecp_normalize_mxz( const mbedtls_ecp_group *grp, mbedtls_ecp_point *P ) +{ + int ret; + +#if defined(MBEDTLS_ECP_NORMALIZE_MXZ_ALT) + if( mbedtls_internal_ecp_grp_capable( grp ) ) + return( mbedtls_internal_ecp_normalize_mxz( grp, P ) ); +#endif /* MBEDTLS_ECP_NORMALIZE_MXZ_ALT */ + + MBEDTLS_MPI_CHK( mbedtls_mpi_inv_mod( &P->Z, &P->Z, &grp->P ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &P->X, &P->X, &P->Z ) ); MOD_MUL( P->X ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &P->Z, 1 ) ); + +cleanup: + return( ret ); +} + +/* + * Randomize projective x/z coordinates: + * (X, Z) -> (l X, l Z) for random l + * This is sort of the reverse operation of ecp_normalize_mxz(). + * + * This countermeasure was first suggested in [2]. + * Cost: 2M + */ +static int ecp_randomize_mxz( const mbedtls_ecp_group *grp, mbedtls_ecp_point *P, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) +{ + int ret; + mbedtls_mpi l; + size_t p_size; + int count = 0; + +#if defined(MBEDTLS_ECP_RANDOMIZE_MXZ_ALT) + if( mbedtls_internal_ecp_grp_capable( grp ) ) + return( mbedtls_internal_ecp_randomize_mxz( grp, P, f_rng, p_rng ); +#endif /* MBEDTLS_ECP_RANDOMIZE_MXZ_ALT */ + + p_size = ( grp->pbits + 7 ) / 8; + mbedtls_mpi_init( &l ); + + /* Generate l such that 1 < l < p */ + do + { + MBEDTLS_MPI_CHK( mbedtls_mpi_fill_random( &l, p_size, f_rng, p_rng ) ); + + while( mbedtls_mpi_cmp_mpi( &l, &grp->P ) >= 0 ) + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &l, 1 ) ); + + if( count++ > 10 ) + return( MBEDTLS_ERR_ECP_RANDOM_FAILED ); + } + while( mbedtls_mpi_cmp_int( &l, 1 ) <= 0 ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &P->X, &P->X, &l ) ); MOD_MUL( P->X ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &P->Z, &P->Z, &l ) ); MOD_MUL( P->Z ); + +cleanup: + mbedtls_mpi_free( &l ); + + return( ret ); +} + +/* + * Double-and-add: R = 2P, S = P + Q, with d = X(P - Q), + * for Montgomery curves in x/z coordinates. + * + * http://www.hyperelliptic.org/EFD/g1p/auto-code/montgom/xz/ladder/mladd-1987-m.op3 + * with + * d = X1 + * P = (X2, Z2) + * Q = (X3, Z3) + * R = (X4, Z4) + * S = (X5, Z5) + * and eliminating temporary variables tO, ..., t4. + * + * Cost: 5M + 4S + */ +static int ecp_double_add_mxz( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *R, mbedtls_ecp_point *S, + const mbedtls_ecp_point *P, const mbedtls_ecp_point *Q, + const mbedtls_mpi *d ) +{ + int ret; + mbedtls_mpi A, AA, B, BB, E, C, D, DA, CB; + +#if defined(MBEDTLS_ECP_DOUBLE_ADD_MXZ_ALT) + if( mbedtls_internal_ecp_grp_capable( grp ) ) + return( mbedtls_internal_ecp_double_add_mxz( grp, R, S, P, Q, d ) ); +#endif /* MBEDTLS_ECP_DOUBLE_ADD_MXZ_ALT */ + + mbedtls_mpi_init( &A ); mbedtls_mpi_init( &AA ); mbedtls_mpi_init( &B ); + mbedtls_mpi_init( &BB ); mbedtls_mpi_init( &E ); mbedtls_mpi_init( &C ); + mbedtls_mpi_init( &D ); mbedtls_mpi_init( &DA ); mbedtls_mpi_init( &CB ); + + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &A, &P->X, &P->Z ) ); MOD_ADD( A ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &AA, &A, &A ) ); MOD_MUL( AA ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &B, &P->X, &P->Z ) ); MOD_SUB( B ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &BB, &B, &B ) ); MOD_MUL( BB ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &E, &AA, &BB ) ); MOD_SUB( E ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &C, &Q->X, &Q->Z ) ); MOD_ADD( C ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &D, &Q->X, &Q->Z ) ); MOD_SUB( D ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &DA, &D, &A ) ); MOD_MUL( DA ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &CB, &C, &B ) ); MOD_MUL( CB ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &S->X, &DA, &CB ) ); MOD_MUL( S->X ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &S->X, &S->X, &S->X ) ); MOD_MUL( S->X ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &S->Z, &DA, &CB ) ); MOD_SUB( S->Z ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &S->Z, &S->Z, &S->Z ) ); MOD_MUL( S->Z ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &S->Z, d, &S->Z ) ); MOD_MUL( S->Z ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &R->X, &AA, &BB ) ); MOD_MUL( R->X ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &R->Z, &grp->A, &E ) ); MOD_MUL( R->Z ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &R->Z, &BB, &R->Z ) ); MOD_ADD( R->Z ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &R->Z, &E, &R->Z ) ); MOD_MUL( R->Z ); + +cleanup: + mbedtls_mpi_free( &A ); mbedtls_mpi_free( &AA ); mbedtls_mpi_free( &B ); + mbedtls_mpi_free( &BB ); mbedtls_mpi_free( &E ); mbedtls_mpi_free( &C ); + mbedtls_mpi_free( &D ); mbedtls_mpi_free( &DA ); mbedtls_mpi_free( &CB ); + + return( ret ); +} + +/* + * Multiplication with Montgomery ladder in x/z coordinates, + * for curves in Montgomery form + */ +static int ecp_mul_mxz( mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_mpi *m, const mbedtls_ecp_point *P, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ) +{ + int ret; + size_t i; + unsigned char b; + mbedtls_ecp_point RP; + mbedtls_mpi PX; + + mbedtls_ecp_point_init( &RP ); mbedtls_mpi_init( &PX ); + + /* Save PX and read from P before writing to R, in case P == R */ + MBEDTLS_MPI_CHK( mbedtls_mpi_copy( &PX, &P->X ) ); + MBEDTLS_MPI_CHK( mbedtls_ecp_copy( &RP, P ) ); + + /* Set R to zero in modified x/z coordinates */ + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &R->X, 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &R->Z, 0 ) ); + mbedtls_mpi_free( &R->Y ); + + /* RP.X might be sligtly larger than P, so reduce it */ + MOD_ADD( RP.X ); + + /* Randomize coordinates of the starting point */ + if( f_rng != NULL ) + MBEDTLS_MPI_CHK( ecp_randomize_mxz( grp, &RP, f_rng, p_rng ) ); + + /* Loop invariant: R = result so far, RP = R + P */ + i = mbedtls_mpi_bitlen( m ); /* one past the (zero-based) most significant bit */ + while( i-- > 0 ) + { + b = mbedtls_mpi_get_bit( m, i ); + /* + * if (b) R = 2R + P else R = 2R, + * which is: + * if (b) double_add( RP, R, RP, R ) + * else double_add( R, RP, R, RP ) + * but using safe conditional swaps to avoid leaks + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_safe_cond_swap( &R->X, &RP.X, b ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_safe_cond_swap( &R->Z, &RP.Z, b ) ); + MBEDTLS_MPI_CHK( ecp_double_add_mxz( grp, R, &RP, R, &RP, &PX ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_safe_cond_swap( &R->X, &RP.X, b ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_safe_cond_swap( &R->Z, &RP.Z, b ) ); + } + + MBEDTLS_MPI_CHK( ecp_normalize_mxz( grp, R ) ); + +cleanup: + mbedtls_ecp_point_free( &RP ); mbedtls_mpi_free( &PX ); + + return( ret ); +} + +#endif /* ECP_MONTGOMERY */ + +/* + * Restartable multiplication R = m * P + */ +int mbedtls_ecp_mul_restartable( mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_mpi *m, const mbedtls_ecp_point *P, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng, + mbedtls_ecp_restart_ctx *rs_ctx ) +{ + int ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA; +#if defined(MBEDTLS_ECP_INTERNAL_ALT) + char is_grp_capable = 0; +#endif + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( R != NULL ); + ECP_VALIDATE_RET( m != NULL ); + ECP_VALIDATE_RET( P != NULL ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + /* reset ops count for this call if top-level */ + if( rs_ctx != NULL && rs_ctx->depth++ == 0 ) + rs_ctx->ops_done = 0; +#endif + +#if defined(MBEDTLS_ECP_INTERNAL_ALT) + if( ( is_grp_capable = mbedtls_internal_ecp_grp_capable( grp ) ) ) + MBEDTLS_MPI_CHK( mbedtls_internal_ecp_init( grp ) ); +#endif /* MBEDTLS_ECP_INTERNAL_ALT */ + +#if defined(MBEDTLS_ECP_RESTARTABLE) + /* skip argument check when restarting */ + if( rs_ctx == NULL || rs_ctx->rsm == NULL ) +#endif + { + /* check_privkey is free */ + MBEDTLS_ECP_BUDGET( MBEDTLS_ECP_OPS_CHK ); + + /* Common sanity checks */ + MBEDTLS_MPI_CHK( mbedtls_ecp_check_privkey( grp, m ) ); + MBEDTLS_MPI_CHK( mbedtls_ecp_check_pubkey( grp, P ) ); + } + + ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA; +#if defined(ECP_MONTGOMERY) + if( mbedtls_ecp_get_type( grp ) == MBEDTLS_ECP_TYPE_MONTGOMERY ) + MBEDTLS_MPI_CHK( ecp_mul_mxz( grp, R, m, P, f_rng, p_rng ) ); +#endif +#if defined(ECP_SHORTWEIERSTRASS) + if( mbedtls_ecp_get_type( grp ) == MBEDTLS_ECP_TYPE_SHORT_WEIERSTRASS ) + MBEDTLS_MPI_CHK( ecp_mul_comb( grp, R, m, P, f_rng, p_rng, rs_ctx ) ); +#endif + +cleanup: + +#if defined(MBEDTLS_ECP_INTERNAL_ALT) + if( is_grp_capable ) + mbedtls_internal_ecp_free( grp ); +#endif /* MBEDTLS_ECP_INTERNAL_ALT */ + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL ) + rs_ctx->depth--; +#endif + + return( ret ); +} + +/* + * Multiplication R = m * P + */ +int mbedtls_ecp_mul( mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_mpi *m, const mbedtls_ecp_point *P, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) +{ + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( R != NULL ); + ECP_VALIDATE_RET( m != NULL ); + ECP_VALIDATE_RET( P != NULL ); + return( mbedtls_ecp_mul_restartable( grp, R, m, P, f_rng, p_rng, NULL ) ); +} + +#if defined(ECP_SHORTWEIERSTRASS) +/* + * Check that an affine point is valid as a public key, + * short weierstrass curves (SEC1 3.2.3.1) + */ +static int ecp_check_pubkey_sw( const mbedtls_ecp_group *grp, const mbedtls_ecp_point *pt ) +{ + int ret; + mbedtls_mpi YY, RHS; + + /* pt coordinates must be normalized for our checks */ + if( mbedtls_mpi_cmp_int( &pt->X, 0 ) < 0 || + mbedtls_mpi_cmp_int( &pt->Y, 0 ) < 0 || + mbedtls_mpi_cmp_mpi( &pt->X, &grp->P ) >= 0 || + mbedtls_mpi_cmp_mpi( &pt->Y, &grp->P ) >= 0 ) + return( MBEDTLS_ERR_ECP_INVALID_KEY ); + + mbedtls_mpi_init( &YY ); mbedtls_mpi_init( &RHS ); + + /* + * YY = Y^2 + * RHS = X (X^2 + A) + B = X^3 + A X + B + */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &YY, &pt->Y, &pt->Y ) ); MOD_MUL( YY ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &RHS, &pt->X, &pt->X ) ); MOD_MUL( RHS ); + + /* Special case for A = -3 */ + if( grp->A.p == NULL ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_int( &RHS, &RHS, 3 ) ); MOD_SUB( RHS ); + } + else + { + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &RHS, &RHS, &grp->A ) ); MOD_ADD( RHS ); + } + + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &RHS, &RHS, &pt->X ) ); MOD_MUL( RHS ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &RHS, &RHS, &grp->B ) ); MOD_ADD( RHS ); + + if( mbedtls_mpi_cmp_mpi( &YY, &RHS ) != 0 ) + ret = MBEDTLS_ERR_ECP_INVALID_KEY; + +cleanup: + + mbedtls_mpi_free( &YY ); mbedtls_mpi_free( &RHS ); + + return( ret ); +} +#endif /* ECP_SHORTWEIERSTRASS */ + +/* + * R = m * P with shortcuts for m == 1 and m == -1 + * NOT constant-time - ONLY for short Weierstrass! + */ +static int mbedtls_ecp_mul_shortcuts( mbedtls_ecp_group *grp, + mbedtls_ecp_point *R, + const mbedtls_mpi *m, + const mbedtls_ecp_point *P, + mbedtls_ecp_restart_ctx *rs_ctx ) +{ + int ret; + + if( mbedtls_mpi_cmp_int( m, 1 ) == 0 ) + { + MBEDTLS_MPI_CHK( mbedtls_ecp_copy( R, P ) ); + } + else if( mbedtls_mpi_cmp_int( m, -1 ) == 0 ) + { + MBEDTLS_MPI_CHK( mbedtls_ecp_copy( R, P ) ); + if( mbedtls_mpi_cmp_int( &R->Y, 0 ) != 0 ) + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &R->Y, &grp->P, &R->Y ) ); + } + else + { + MBEDTLS_MPI_CHK( mbedtls_ecp_mul_restartable( grp, R, m, P, + NULL, NULL, rs_ctx ) ); + } + +cleanup: + return( ret ); +} + +/* + * Restartable linear combination + * NOT constant-time + */ +int mbedtls_ecp_muladd_restartable( + mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_mpi *m, const mbedtls_ecp_point *P, + const mbedtls_mpi *n, const mbedtls_ecp_point *Q, + mbedtls_ecp_restart_ctx *rs_ctx ) +{ + int ret; + mbedtls_ecp_point mP; + mbedtls_ecp_point *pmP = &mP; + mbedtls_ecp_point *pR = R; +#if defined(MBEDTLS_ECP_INTERNAL_ALT) + char is_grp_capable = 0; +#endif + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( R != NULL ); + ECP_VALIDATE_RET( m != NULL ); + ECP_VALIDATE_RET( P != NULL ); + ECP_VALIDATE_RET( n != NULL ); + ECP_VALIDATE_RET( Q != NULL ); + + if( mbedtls_ecp_get_type( grp ) != MBEDTLS_ECP_TYPE_SHORT_WEIERSTRASS ) + return( MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE ); + + mbedtls_ecp_point_init( &mP ); + + ECP_RS_ENTER( ma ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->ma != NULL ) + { + /* redirect intermediate results to restart context */ + pmP = &rs_ctx->ma->mP; + pR = &rs_ctx->ma->R; + + /* jump to next operation */ + if( rs_ctx->ma->state == ecp_rsma_mul2 ) + goto mul2; + if( rs_ctx->ma->state == ecp_rsma_add ) + goto add; + if( rs_ctx->ma->state == ecp_rsma_norm ) + goto norm; + } +#endif /* MBEDTLS_ECP_RESTARTABLE */ + + MBEDTLS_MPI_CHK( mbedtls_ecp_mul_shortcuts( grp, pmP, m, P, rs_ctx ) ); +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->ma != NULL ) + rs_ctx->ma->state = ecp_rsma_mul2; + +mul2: +#endif + MBEDTLS_MPI_CHK( mbedtls_ecp_mul_shortcuts( grp, pR, n, Q, rs_ctx ) ); + +#if defined(MBEDTLS_ECP_INTERNAL_ALT) + if( ( is_grp_capable = mbedtls_internal_ecp_grp_capable( grp ) ) ) + MBEDTLS_MPI_CHK( mbedtls_internal_ecp_init( grp ) ); +#endif /* MBEDTLS_ECP_INTERNAL_ALT */ + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->ma != NULL ) + rs_ctx->ma->state = ecp_rsma_add; + +add: +#endif + MBEDTLS_ECP_BUDGET( MBEDTLS_ECP_OPS_ADD ); + MBEDTLS_MPI_CHK( ecp_add_mixed( grp, pR, pmP, pR ) ); +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->ma != NULL ) + rs_ctx->ma->state = ecp_rsma_norm; + +norm: +#endif + MBEDTLS_ECP_BUDGET( MBEDTLS_ECP_OPS_INV ); + MBEDTLS_MPI_CHK( ecp_normalize_jac( grp, pR ) ); + +#if defined(MBEDTLS_ECP_RESTARTABLE) + if( rs_ctx != NULL && rs_ctx->ma != NULL ) + MBEDTLS_MPI_CHK( mbedtls_ecp_copy( R, pR ) ); +#endif + +cleanup: +#if defined(MBEDTLS_ECP_INTERNAL_ALT) + if( is_grp_capable ) + mbedtls_internal_ecp_free( grp ); +#endif /* MBEDTLS_ECP_INTERNAL_ALT */ + + mbedtls_ecp_point_free( &mP ); + + ECP_RS_LEAVE( ma ); + + return( ret ); +} + +/* + * Linear combination + * NOT constant-time + */ +int mbedtls_ecp_muladd( mbedtls_ecp_group *grp, mbedtls_ecp_point *R, + const mbedtls_mpi *m, const mbedtls_ecp_point *P, + const mbedtls_mpi *n, const mbedtls_ecp_point *Q ) +{ + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( R != NULL ); + ECP_VALIDATE_RET( m != NULL ); + ECP_VALIDATE_RET( P != NULL ); + ECP_VALIDATE_RET( n != NULL ); + ECP_VALIDATE_RET( Q != NULL ); + return( mbedtls_ecp_muladd_restartable( grp, R, m, P, n, Q, NULL ) ); +} + +#if defined(ECP_MONTGOMERY) +/* + * Check validity of a public key for Montgomery curves with x-only schemes + */ +static int ecp_check_pubkey_mx( const mbedtls_ecp_group *grp, const mbedtls_ecp_point *pt ) +{ + /* [Curve25519 p. 5] Just check X is the correct number of bytes */ + /* Allow any public value, if it's too big then we'll just reduce it mod p + * (RFC 7748 sec. 5 para. 3). */ + if( mbedtls_mpi_size( &pt->X ) > ( grp->nbits + 7 ) / 8 ) + return( MBEDTLS_ERR_ECP_INVALID_KEY ); + + return( 0 ); +} +#endif /* ECP_MONTGOMERY */ + +/* + * Check that a point is valid as a public key + */ +int mbedtls_ecp_check_pubkey( const mbedtls_ecp_group *grp, + const mbedtls_ecp_point *pt ) +{ + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( pt != NULL ); + + /* Must use affine coordinates */ + if( mbedtls_mpi_cmp_int( &pt->Z, 1 ) != 0 ) + return( MBEDTLS_ERR_ECP_INVALID_KEY ); + +#if defined(ECP_MONTGOMERY) + if( mbedtls_ecp_get_type( grp ) == MBEDTLS_ECP_TYPE_MONTGOMERY ) + return( ecp_check_pubkey_mx( grp, pt ) ); +#endif +#if defined(ECP_SHORTWEIERSTRASS) + if( mbedtls_ecp_get_type( grp ) == MBEDTLS_ECP_TYPE_SHORT_WEIERSTRASS ) + return( ecp_check_pubkey_sw( grp, pt ) ); +#endif + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); +} + +/* + * Check that an mbedtls_mpi is valid as a private key + */ +int mbedtls_ecp_check_privkey( const mbedtls_ecp_group *grp, + const mbedtls_mpi *d ) +{ + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( d != NULL ); + +#if defined(ECP_MONTGOMERY) + if( mbedtls_ecp_get_type( grp ) == MBEDTLS_ECP_TYPE_MONTGOMERY ) + { + /* see RFC 7748 sec. 5 para. 5 */ + if( mbedtls_mpi_get_bit( d, 0 ) != 0 || + mbedtls_mpi_get_bit( d, 1 ) != 0 || + mbedtls_mpi_bitlen( d ) - 1 != grp->nbits ) /* mbedtls_mpi_bitlen is one-based! */ + return( MBEDTLS_ERR_ECP_INVALID_KEY ); + + /* see [Curve25519] page 5 */ + if( grp->nbits == 254 && mbedtls_mpi_get_bit( d, 2 ) != 0 ) + return( MBEDTLS_ERR_ECP_INVALID_KEY ); + + return( 0 ); + } +#endif /* ECP_MONTGOMERY */ +#if defined(ECP_SHORTWEIERSTRASS) + if( mbedtls_ecp_get_type( grp ) == MBEDTLS_ECP_TYPE_SHORT_WEIERSTRASS ) + { + /* see SEC1 3.2 */ + if( mbedtls_mpi_cmp_int( d, 1 ) < 0 || + mbedtls_mpi_cmp_mpi( d, &grp->N ) >= 0 ) + return( MBEDTLS_ERR_ECP_INVALID_KEY ); + else + return( 0 ); + } +#endif /* ECP_SHORTWEIERSTRASS */ + + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); +} + +/* + * Generate a private key + */ +int mbedtls_ecp_gen_privkey( const mbedtls_ecp_group *grp, + mbedtls_mpi *d, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ) +{ + int ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + size_t n_size; + + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( d != NULL ); + ECP_VALIDATE_RET( f_rng != NULL ); + + n_size = ( grp->nbits + 7 ) / 8; + +#if defined(ECP_MONTGOMERY) + if( mbedtls_ecp_get_type( grp ) == MBEDTLS_ECP_TYPE_MONTGOMERY ) + { + /* [M225] page 5 */ + size_t b; + + do { + MBEDTLS_MPI_CHK( mbedtls_mpi_fill_random( d, n_size, f_rng, p_rng ) ); + } while( mbedtls_mpi_bitlen( d ) == 0); + + /* Make sure the most significant bit is nbits */ + b = mbedtls_mpi_bitlen( d ) - 1; /* mbedtls_mpi_bitlen is one-based */ + if( b > grp->nbits ) + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( d, b - grp->nbits ) ); + else + MBEDTLS_MPI_CHK( mbedtls_mpi_set_bit( d, grp->nbits, 1 ) ); + + /* Make sure the last two bits are unset for Curve448, three bits for + Curve25519 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_set_bit( d, 0, 0 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_set_bit( d, 1, 0 ) ); + if( grp->nbits == 254 ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_set_bit( d, 2, 0 ) ); + } + } +#endif /* ECP_MONTGOMERY */ + +#if defined(ECP_SHORTWEIERSTRASS) + if( mbedtls_ecp_get_type( grp ) == MBEDTLS_ECP_TYPE_SHORT_WEIERSTRASS ) + { + /* SEC1 3.2.1: Generate d such that 1 <= n < N */ + int count = 0; + + /* + * Match the procedure given in RFC 6979 (deterministic ECDSA): + * - use the same byte ordering; + * - keep the leftmost nbits bits of the generated octet string; + * - try until result is in the desired range. + * This also avoids any biais, which is especially important for ECDSA. + */ + do + { + MBEDTLS_MPI_CHK( mbedtls_mpi_fill_random( d, n_size, f_rng, p_rng ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( d, 8 * n_size - grp->nbits ) ); + + /* + * Each try has at worst a probability 1/2 of failing (the msb has + * a probability 1/2 of being 0, and then the result will be < N), + * so after 30 tries failure probability is a most 2**(-30). + * + * For most curves, 1 try is enough with overwhelming probability, + * since N starts with a lot of 1s in binary, but some curves + * such as secp224k1 are actually very close to the worst case. + */ + if( ++count > 30 ) + return( MBEDTLS_ERR_ECP_RANDOM_FAILED ); + } + while( mbedtls_mpi_cmp_int( d, 1 ) < 0 || + mbedtls_mpi_cmp_mpi( d, &grp->N ) >= 0 ); + } +#endif /* ECP_SHORTWEIERSTRASS */ + +cleanup: + return( ret ); +} + +/* + * Generate a keypair with configurable base point + */ +int mbedtls_ecp_gen_keypair_base( mbedtls_ecp_group *grp, + const mbedtls_ecp_point *G, + mbedtls_mpi *d, mbedtls_ecp_point *Q, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ) +{ + int ret; + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( d != NULL ); + ECP_VALIDATE_RET( G != NULL ); + ECP_VALIDATE_RET( Q != NULL ); + ECP_VALIDATE_RET( f_rng != NULL ); + + MBEDTLS_MPI_CHK( mbedtls_ecp_gen_privkey( grp, d, f_rng, p_rng ) ); + MBEDTLS_MPI_CHK( mbedtls_ecp_mul( grp, Q, d, G, f_rng, p_rng ) ); + +cleanup: + return( ret ); +} + +/* + * Generate key pair, wrapper for conventional base point + */ +int mbedtls_ecp_gen_keypair( mbedtls_ecp_group *grp, + mbedtls_mpi *d, mbedtls_ecp_point *Q, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ) +{ + ECP_VALIDATE_RET( grp != NULL ); + ECP_VALIDATE_RET( d != NULL ); + ECP_VALIDATE_RET( Q != NULL ); + ECP_VALIDATE_RET( f_rng != NULL ); + + return( mbedtls_ecp_gen_keypair_base( grp, &grp->G, d, Q, f_rng, p_rng ) ); +} + +/* + * Generate a keypair, prettier wrapper + */ +int mbedtls_ecp_gen_key( mbedtls_ecp_group_id grp_id, mbedtls_ecp_keypair *key, + int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) +{ + int ret; + ECP_VALIDATE_RET( key != NULL ); + ECP_VALIDATE_RET( f_rng != NULL ); + + if( ( ret = mbedtls_ecp_group_load( &key->grp, grp_id ) ) != 0 ) + return( ret ); + + return( mbedtls_ecp_gen_keypair( &key->grp, &key->d, &key->Q, f_rng, p_rng ) ); +} + +#define ECP_CURVE25519_KEY_SIZE 32 +/* + * Read a private key. + */ +int mbedtls_ecp_read_key( mbedtls_ecp_group_id grp_id, mbedtls_ecp_keypair *key, + const unsigned char *buf, size_t buflen ) +{ + int ret = 0; + + ECP_VALIDATE_RET( key != NULL ); + ECP_VALIDATE_RET( buf != NULL ); + + if( ( ret = mbedtls_ecp_group_load( &key->grp, grp_id ) ) != 0 ) + return( ret ); + + ret = MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE; + +#if defined(ECP_MONTGOMERY) + if( mbedtls_ecp_get_type( &key->grp ) == MBEDTLS_ECP_TYPE_MONTGOMERY ) + { + /* + * If it is Curve25519 curve then mask the key as mandated by RFC7748 + */ + if( grp_id == MBEDTLS_ECP_DP_CURVE25519 ) + { + if( buflen != ECP_CURVE25519_KEY_SIZE ) + return MBEDTLS_ERR_ECP_INVALID_KEY; + + MBEDTLS_MPI_CHK( mbedtls_mpi_read_binary_le( &key->d, buf, buflen ) ); + + /* Set the three least significant bits to 0 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_set_bit( &key->d, 0, 0 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_set_bit( &key->d, 1, 0 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_set_bit( &key->d, 2, 0 ) ); + + /* Set the most significant bit to 0 */ + MBEDTLS_MPI_CHK( + mbedtls_mpi_set_bit( &key->d, + ECP_CURVE25519_KEY_SIZE * 8 - 1, 0 ) + ); + + /* Set the second most significant bit to 1 */ + MBEDTLS_MPI_CHK( + mbedtls_mpi_set_bit( &key->d, + ECP_CURVE25519_KEY_SIZE * 8 - 2, 1 ) + ); + } + else + ret = MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE; + } + +#endif +#if defined(ECP_SHORTWEIERSTRASS) + if( mbedtls_ecp_get_type( &key->grp ) == MBEDTLS_ECP_TYPE_SHORT_WEIERSTRASS ) + { + MBEDTLS_MPI_CHK( mbedtls_mpi_read_binary( &key->d, buf, buflen ) ); + + MBEDTLS_MPI_CHK( mbedtls_ecp_check_privkey( &key->grp, &key->d ) ); + } + +#endif +cleanup: + + if( ret != 0 ) + mbedtls_mpi_free( &key->d ); + + return( ret ); +} + +/* + * Check a public-private key pair + */ +int mbedtls_ecp_check_pub_priv( const mbedtls_ecp_keypair *pub, const mbedtls_ecp_keypair *prv ) +{ + int ret; + mbedtls_ecp_point Q; + mbedtls_ecp_group grp; + ECP_VALIDATE_RET( pub != NULL ); + ECP_VALIDATE_RET( prv != NULL ); + + if( pub->grp.id == MBEDTLS_ECP_DP_NONE || + pub->grp.id != prv->grp.id || + mbedtls_mpi_cmp_mpi( &pub->Q.X, &prv->Q.X ) || + mbedtls_mpi_cmp_mpi( &pub->Q.Y, &prv->Q.Y ) || + mbedtls_mpi_cmp_mpi( &pub->Q.Z, &prv->Q.Z ) ) + { + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + } + + mbedtls_ecp_point_init( &Q ); + mbedtls_ecp_group_init( &grp ); + + /* mbedtls_ecp_mul() needs a non-const group... */ + mbedtls_ecp_group_copy( &grp, &prv->grp ); + + /* Also checks d is valid */ + MBEDTLS_MPI_CHK( mbedtls_ecp_mul( &grp, &Q, &prv->d, &prv->grp.G, NULL, NULL ) ); + + if( mbedtls_mpi_cmp_mpi( &Q.X, &prv->Q.X ) || + mbedtls_mpi_cmp_mpi( &Q.Y, &prv->Q.Y ) || + mbedtls_mpi_cmp_mpi( &Q.Z, &prv->Q.Z ) ) + { + ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA; + goto cleanup; + } + +cleanup: + mbedtls_ecp_point_free( &Q ); + mbedtls_ecp_group_free( &grp ); + + return( ret ); +} + +cy_en_crypto_ecc_curve_id_t cy_get_dp_idx(mbedtls_ecp_group_id gid) +{ + cy_en_crypto_ecc_curve_id_t dp_idx; + + switch( gid ) + { + case MBEDTLS_ECP_DP_SECP192R1: + dp_idx = CY_CRYPTO_ECC_ECP_SECP192R1; + break; + case MBEDTLS_ECP_DP_SECP224R1: + dp_idx = CY_CRYPTO_ECC_ECP_SECP224R1; + break; + case MBEDTLS_ECP_DP_SECP256R1: + dp_idx = CY_CRYPTO_ECC_ECP_SECP256R1; + break; + case MBEDTLS_ECP_DP_SECP384R1: + dp_idx = CY_CRYPTO_ECC_ECP_SECP384R1; + break; + case MBEDTLS_ECP_DP_SECP521R1: + dp_idx = CY_CRYPTO_ECC_ECP_SECP521R1; + break; + + default: + dp_idx = CY_CRYPTO_ECC_ECP_NONE; + break; + } + + return dp_idx; +} + +#if defined(MBEDTLS_SELF_TEST) + +/* + * Checkup routine + */ +int mbedtls_ecp_self_test( int verbose ) +{ + int ret; + size_t i; + mbedtls_ecp_group grp; + mbedtls_ecp_point R, P; + mbedtls_mpi m; + unsigned long add_c_prev, dbl_c_prev, mul_c_prev; + /* exponents especially adapted for secp192r1 */ + const char *exponents[] = + { + "000000000000000000000000000000000000000000000001", /* one */ + "FFFFFFFFFFFFFFFFFFFFFFFF99DEF836146BC9B1B4D22830", /* N - 1 */ + "5EA6F389A38B8BC81E767753B15AA5569E1782E30ABE7D25", /* random */ + "400000000000000000000000000000000000000000000000", /* one and zeros */ + "7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", /* all ones */ + "555555555555555555555555555555555555555555555555", /* 101010... */ + }; + + mbedtls_ecp_group_init( &grp ); + mbedtls_ecp_point_init( &R ); + mbedtls_ecp_point_init( &P ); + mbedtls_mpi_init( &m ); + + /* Use secp192r1 if available, or any available curve */ +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) + MBEDTLS_MPI_CHK( mbedtls_ecp_group_load( &grp, MBEDTLS_ECP_DP_SECP192R1 ) ); +#else + MBEDTLS_MPI_CHK( mbedtls_ecp_group_load( &grp, mbedtls_ecp_curve_list()->grp_id ) ); +#endif + + if( verbose != 0 ) + mbedtls_printf( " ECP test #1 (constant op_count, base point G): " ); + + /* Do a dummy multiplication first to trigger precomputation */ + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &m, 2 ) ); + MBEDTLS_MPI_CHK( mbedtls_ecp_mul( &grp, &P, &m, &grp.G, NULL, NULL ) ); + + add_count = 0; + dbl_count = 0; + mul_count = 0; + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &m, 16, exponents[0] ) ); + MBEDTLS_MPI_CHK( mbedtls_ecp_mul( &grp, &R, &m, &grp.G, NULL, NULL ) ); + + for( i = 1; i < sizeof( exponents ) / sizeof( exponents[0] ); i++ ) + { + add_c_prev = add_count; + dbl_c_prev = dbl_count; + mul_c_prev = mul_count; + add_count = 0; + dbl_count = 0; + mul_count = 0; + + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &m, 16, exponents[i] ) ); + MBEDTLS_MPI_CHK( mbedtls_ecp_mul( &grp, &R, &m, &grp.G, NULL, NULL ) ); + + if( add_count != add_c_prev || + dbl_count != dbl_c_prev || + mul_count != mul_c_prev ) + { + if( verbose != 0 ) + mbedtls_printf( "failed (%u)\n", (unsigned int) i ); + + ret = 1; + goto cleanup; + } + } + + if( verbose != 0 ) + mbedtls_printf( "passed\n" ); + + if( verbose != 0 ) + mbedtls_printf( " ECP test #2 (constant op_count, other point): " ); + /* We computed P = 2G last time, use it */ + + add_count = 0; + dbl_count = 0; + mul_count = 0; + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &m, 16, exponents[0] ) ); + MBEDTLS_MPI_CHK( mbedtls_ecp_mul( &grp, &R, &m, &P, NULL, NULL ) ); + + for( i = 1; i < sizeof( exponents ) / sizeof( exponents[0] ); i++ ) + { + add_c_prev = add_count; + dbl_c_prev = dbl_count; + mul_c_prev = mul_count; + add_count = 0; + dbl_count = 0; + mul_count = 0; + + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &m, 16, exponents[i] ) ); + MBEDTLS_MPI_CHK( mbedtls_ecp_mul( &grp, &R, &m, &P, NULL, NULL ) ); + + if( add_count != add_c_prev || + dbl_count != dbl_c_prev || + mul_count != mul_c_prev ) + { + if( verbose != 0 ) + mbedtls_printf( "failed (%u)\n", (unsigned int) i ); + + ret = 1; + goto cleanup; + } + } + + if( verbose != 0 ) + mbedtls_printf( "passed\n" ); + +cleanup: + + if( ret < 0 && verbose != 0 ) + mbedtls_printf( "Unexpected error, return code = %08X\n", ret ); + + mbedtls_ecp_group_free( &grp ); + mbedtls_ecp_point_free( &R ); + mbedtls_ecp_point_free( &P ); + mbedtls_mpi_free( &m ); + + if( verbose != 0 ) + mbedtls_printf( "\n" ); + + return( ret ); +} + +#endif /* MBEDTLS_SELF_TEST */ + +#endif /* MBEDTLS_ECP_ALT */ + +#endif /* MBEDTLS_ECP_C */ diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecp_alt.h b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecp_alt.h new file mode 100644 index 00000000000..a0474783ef8 --- /dev/null +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecp_alt.h @@ -0,0 +1,183 @@ +/* + * mbed Microcontroller Library + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright (C) 2019 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * \file ecp.h + * \version 1.0 + * + * \brief This file provides an API for Elliptic Curves over GF(P) (ECP). + * + * The use of ECP in cryptography and TLS is defined in + * Standards for Efficient Cryptography Group (SECG): SEC1 + * Elliptic Curve Cryptography and + * RFC-4492: Elliptic Curve Cryptography (ECC) Cipher Suites + * for Transport Layer Security (TLS). + * + * RFC-2409: The Internet Key Exchange (IKE) defines ECP + * group types. + * + */ + +#ifndef ECP_ALT_H +#define ECP_ALT_H + +#include "bignum.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(MBEDTLS_ECP_ALT) + +#include "cy_crypto_core_ecc.h" + +/* + * default mbed TLS elliptic curve arithmetic implementation + * + * (in case MBEDTLS_ECP_ALT is defined then the developer has to provide an + * alternative implementation for the whole module and it will replace this + * one.) + */ + +/** + * \brief The ECP group structure. + * + * We consider two types of curve equations: + *
  • Short Weierstrass: y^2 = x^3 + A x + B mod P + * (SEC1 + RFC-4492)
    • + *
  • Montgomery: y^2 = x^3 + A x^2 + x mod P (Curve25519, + * Curve448)
+ * In both cases, the generator (\p G) for a prime-order subgroup is fixed. + * + * For Short Weierstrass, this subgroup is the whole curve, and its + * cardinality is denoted by \p N. Our code requires that \p N is an + * odd prime as mbedtls_ecp_mul() requires an odd number, and + * mbedtls_ecdsa_sign() requires that it is prime for blinding purposes. + * + * For Montgomery curves, we do not store \p A, but (A + 2) / 4, + * which is the quantity used in the formulas. Additionally, \p nbits is + * not the size of \p N but the required size for private keys. + * + * If \p modp is NULL, reduction modulo \p P is done using a generic algorithm. + * Otherwise, \p modp must point to a function that takes an \p mbedtls_mpi in the + * range of 0..2^(2*pbits)-1, and transforms it in-place to an integer + * which is congruent mod \p P to the given MPI, and is close enough to \p pbits + * in size, so that it may be efficiently brought in the 0..P-1 range by a few + * additions or subtractions. Therefore, it is only an approximative modular + * reduction. It must return 0 on success and non-zero on failure. + * + */ +typedef struct mbedtls_ecp_group +{ + mbedtls_ecp_group_id id; /*!< An internal group identifier. */ + mbedtls_mpi P; /*!< The prime modulus of the base field. */ + mbedtls_mpi A; /*!< For Short Weierstrass: \p A in the equation. For + Montgomery curves: (A + 2) / 4. */ + mbedtls_mpi B; /*!< For Short Weierstrass: \p B in the equation. + For Montgomery curves: unused. */ + mbedtls_ecp_point G; /*!< The generator of the subgroup used. */ + mbedtls_mpi N; /*!< The order of \p G. */ + size_t pbits; /*!< The number of bits in \p P.*/ + size_t nbits; /*!< For Short Weierstrass: The number of bits in \p P. + For Montgomery curves: the number of bits in the + private keys. */ + unsigned int h; /*!< \internal 1 if the constants are static. */ + int (*modp)(mbedtls_mpi *); /*!< The function for fast pseudo-reduction + mod \p P (see above).*/ + int (*t_pre)(mbedtls_ecp_point *, void *); /*!< Unused. */ + int (*t_post)(mbedtls_ecp_point *, void *); /*!< Unused. */ + void *t_data; /*!< Unused. */ + mbedtls_ecp_point *T; /*!< Pre-computed points for ecp_mul_comb(). */ + size_t T_size; /*!< The number of pre-computed points. */ +} +mbedtls_ecp_group; + +#define MBEDTLS_ECP_BUDGET( ops ) /* no-op; for compatibility */ + +/* We want to declare restartable versions of existing functions anyway */ +typedef void mbedtls_ecp_restart_ctx; + + +/** + * \name SECTION: Module settings + * + * The configuration options you can set for this module are in this section. + * Either change them in config.h, or define them using the compiler command line. + * \{ + */ + +#if !defined(MBEDTLS_ECP_MAX_BITS) +/** + * The maximum size of the groups, that is, of \c N and \c P. + */ +#define MBEDTLS_ECP_MAX_BITS 521 /**< The maximum size of groups, in bits. */ +#endif + +#define MBEDTLS_ECP_MAX_BYTES ( ( MBEDTLS_ECP_MAX_BITS + 7 ) / 8 ) +#define MBEDTLS_ECP_MAX_PT_LEN ( 2 * MBEDTLS_ECP_MAX_BYTES + 1 ) + +#if !defined(MBEDTLS_ECP_WINDOW_SIZE) +/* + * Maximum "window" size used for point multiplication. + * Default: 6. + * Minimum value: 2. Maximum value: 7. + * + * Result is an array of at most ( 1 << ( MBEDTLS_ECP_WINDOW_SIZE - 1 ) ) + * points used for point multiplication. This value is directly tied to EC + * peak memory usage, so decreasing it by one should roughly cut memory usage + * by two (if large curves are in use). + * + * Reduction in size may reduce speed, but larger curves are impacted first. + * Sample performances (in ECDHE handshakes/s, with FIXED_POINT_OPTIM = 1): + * w-size: 6 5 4 3 2 + * 521 145 141 135 120 97 + * 384 214 209 198 177 146 + * 256 320 320 303 262 226 + * 224 475 475 453 398 342 + * 192 640 640 633 587 476 + */ +#define MBEDTLS_ECP_WINDOW_SIZE 6 /**< The maximum window size used. */ +#endif /* MBEDTLS_ECP_WINDOW_SIZE */ + +#if !defined(MBEDTLS_ECP_FIXED_POINT_OPTIM) +/* + * Trade memory for speed on fixed-point multiplication. + * + * This speeds up repeated multiplication of the generator (that is, the + * multiplication in ECDSA signatures, and half of the multiplications in + * ECDSA verification and ECDHE) by a factor roughly 3 to 4. + * + * The cost is increasing EC peak memory usage by a factor roughly 2. + * + * Change this value to 0 to reduce peak memory usage. + */ +#define MBEDTLS_ECP_FIXED_POINT_OPTIM 1 /**< Enable fixed-point speed-up. */ +#endif /* MBEDTLS_ECP_FIXED_POINT_OPTIM */ + +/* \} name SECTION: Module settings */ + +cy_en_crypto_ecc_curve_id_t cy_get_dp_idx(mbedtls_ecp_group_id gid); + +#endif /* MBEDTLS_ECP_ALT */ + +#ifdef __cplusplus +} +#endif + +#endif /* ecp_alt.h */ diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecp_curves_alt.c b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecp_curves_alt.c new file mode 100644 index 00000000000..62150ef0e53 --- /dev/null +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecp_curves_alt.c @@ -0,0 +1,1476 @@ +/* + * Elliptic curves over GF(p): curve-specific data and functions + * + * mbed Microcontroller Library + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright (C) 2019 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * \file ecp_curves_alt.c + * \version 1.0 + * + */ + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_ECP_C) + +#include "mbedtls/ecp.h" +#include "mbedtls/platform_util.h" + +#include + +#if defined(MBEDTLS_ECP_ALT) + +/* Parameter validation macros based on platform_util.h */ +#define ECP_VALIDATE_RET( cond ) \ + MBEDTLS_INTERNAL_VALIDATE_RET( cond, MBEDTLS_ERR_ECP_BAD_INPUT_DATA ) +#define ECP_VALIDATE( cond ) \ + MBEDTLS_INTERNAL_VALIDATE( cond ) + +#if ( defined(__ARMCC_VERSION) || defined(_MSC_VER) ) && \ + !defined(inline) && !defined(__cplusplus) +#define inline __inline +#endif + +/* + * Conversion macros for embedded constants: + * build lists of mbedtls_mpi_uint's from lists of unsigned char's grouped by 8, 4 or 2 + */ +#if defined(MBEDTLS_HAVE_INT32) + +#define BYTES_TO_T_UINT_4( a, b, c, d ) \ + ( (mbedtls_mpi_uint) (a) << 0 ) | \ + ( (mbedtls_mpi_uint) (b) << 8 ) | \ + ( (mbedtls_mpi_uint) (c) << 16 ) | \ + ( (mbedtls_mpi_uint) (d) << 24 ) + +#define BYTES_TO_T_UINT_2( a, b ) \ + BYTES_TO_T_UINT_4( a, b, 0, 0 ) + +#define BYTES_TO_T_UINT_8( a, b, c, d, e, f, g, h ) \ + BYTES_TO_T_UINT_4( a, b, c, d ), \ + BYTES_TO_T_UINT_4( e, f, g, h ) + +#else /* 64-bits */ + +#define BYTES_TO_T_UINT_8( a, b, c, d, e, f, g, h ) \ + ( (mbedtls_mpi_uint) (a) << 0 ) | \ + ( (mbedtls_mpi_uint) (b) << 8 ) | \ + ( (mbedtls_mpi_uint) (c) << 16 ) | \ + ( (mbedtls_mpi_uint) (d) << 24 ) | \ + ( (mbedtls_mpi_uint) (e) << 32 ) | \ + ( (mbedtls_mpi_uint) (f) << 40 ) | \ + ( (mbedtls_mpi_uint) (g) << 48 ) | \ + ( (mbedtls_mpi_uint) (h) << 56 ) + +#define BYTES_TO_T_UINT_4( a, b, c, d ) \ + BYTES_TO_T_UINT_8( a, b, c, d, 0, 0, 0, 0 ) + +#define BYTES_TO_T_UINT_2( a, b ) \ + BYTES_TO_T_UINT_8( a, b, 0, 0, 0, 0, 0, 0 ) + +#endif /* bits in mbedtls_mpi_uint */ + +/* + * Note: the constants are in little-endian order + * to be directly usable in MPIs + */ + +/* + * Domain parameters for secp192r1 + */ +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) +static const mbedtls_mpi_uint secp192r1_p[] = { + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +static const mbedtls_mpi_uint secp192r1_b[] = { + BYTES_TO_T_UINT_8( 0xB1, 0xB9, 0x46, 0xC1, 0xEC, 0xDE, 0xB8, 0xFE ), + BYTES_TO_T_UINT_8( 0x49, 0x30, 0x24, 0x72, 0xAB, 0xE9, 0xA7, 0x0F ), + BYTES_TO_T_UINT_8( 0xE7, 0x80, 0x9C, 0xE5, 0x19, 0x05, 0x21, 0x64 ), +}; +static const mbedtls_mpi_uint secp192r1_gx[] = { + BYTES_TO_T_UINT_8( 0x12, 0x10, 0xFF, 0x82, 0xFD, 0x0A, 0xFF, 0xF4 ), + BYTES_TO_T_UINT_8( 0x00, 0x88, 0xA1, 0x43, 0xEB, 0x20, 0xBF, 0x7C ), + BYTES_TO_T_UINT_8( 0xF6, 0x90, 0x30, 0xB0, 0x0E, 0xA8, 0x8D, 0x18 ), +}; +static const mbedtls_mpi_uint secp192r1_gy[] = { + BYTES_TO_T_UINT_8( 0x11, 0x48, 0x79, 0x1E, 0xA1, 0x77, 0xF9, 0x73 ), + BYTES_TO_T_UINT_8( 0xD5, 0xCD, 0x24, 0x6B, 0xED, 0x11, 0x10, 0x63 ), + BYTES_TO_T_UINT_8( 0x78, 0xDA, 0xC8, 0xFF, 0x95, 0x2B, 0x19, 0x07 ), +}; +static const mbedtls_mpi_uint secp192r1_n[] = { + BYTES_TO_T_UINT_8( 0x31, 0x28, 0xD2, 0xB4, 0xB1, 0xC9, 0x6B, 0x14 ), + BYTES_TO_T_UINT_8( 0x36, 0xF8, 0xDE, 0x99, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +#endif /* MBEDTLS_ECP_DP_SECP192R1_ENABLED */ + +/* + * Domain parameters for secp224r1 + */ +#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) +static const mbedtls_mpi_uint secp224r1_p[] = { + BYTES_TO_T_UINT_8( 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ), + BYTES_TO_T_UINT_8( 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 ), +}; +static const mbedtls_mpi_uint secp224r1_b[] = { + BYTES_TO_T_UINT_8( 0xB4, 0xFF, 0x55, 0x23, 0x43, 0x39, 0x0B, 0x27 ), + BYTES_TO_T_UINT_8( 0xBA, 0xD8, 0xBF, 0xD7, 0xB7, 0xB0, 0x44, 0x50 ), + BYTES_TO_T_UINT_8( 0x56, 0x32, 0x41, 0xF5, 0xAB, 0xB3, 0x04, 0x0C ), + BYTES_TO_T_UINT_4( 0x85, 0x0A, 0x05, 0xB4 ), +}; +static const mbedtls_mpi_uint secp224r1_gx[] = { + BYTES_TO_T_UINT_8( 0x21, 0x1D, 0x5C, 0x11, 0xD6, 0x80, 0x32, 0x34 ), + BYTES_TO_T_UINT_8( 0x22, 0x11, 0xC2, 0x56, 0xD3, 0xC1, 0x03, 0x4A ), + BYTES_TO_T_UINT_8( 0xB9, 0x90, 0x13, 0x32, 0x7F, 0xBF, 0xB4, 0x6B ), + BYTES_TO_T_UINT_4( 0xBD, 0x0C, 0x0E, 0xB7 ), +}; +static const mbedtls_mpi_uint secp224r1_gy[] = { + BYTES_TO_T_UINT_8( 0x34, 0x7E, 0x00, 0x85, 0x99, 0x81, 0xD5, 0x44 ), + BYTES_TO_T_UINT_8( 0x64, 0x47, 0x07, 0x5A, 0xA0, 0x75, 0x43, 0xCD ), + BYTES_TO_T_UINT_8( 0xE6, 0xDF, 0x22, 0x4C, 0xFB, 0x23, 0xF7, 0xB5 ), + BYTES_TO_T_UINT_4( 0x88, 0x63, 0x37, 0xBD ), +}; +static const mbedtls_mpi_uint secp224r1_n[] = { + BYTES_TO_T_UINT_8( 0x3D, 0x2A, 0x5C, 0x5C, 0x45, 0x29, 0xDD, 0x13 ), + BYTES_TO_T_UINT_8( 0x3E, 0xF0, 0xB8, 0xE0, 0xA2, 0x16, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_4( 0xFF, 0xFF, 0xFF, 0xFF ), +}; +#endif /* MBEDTLS_ECP_DP_SECP224R1_ENABLED */ + +/* + * Domain parameters for secp256r1 + */ +#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) +static const mbedtls_mpi_uint secp256r1_p[] = { + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 ), + BYTES_TO_T_UINT_8( 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ), + BYTES_TO_T_UINT_8( 0x01, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +static const mbedtls_mpi_uint secp256r1_b[] = { + BYTES_TO_T_UINT_8( 0x4B, 0x60, 0xD2, 0x27, 0x3E, 0x3C, 0xCE, 0x3B ), + BYTES_TO_T_UINT_8( 0xF6, 0xB0, 0x53, 0xCC, 0xB0, 0x06, 0x1D, 0x65 ), + BYTES_TO_T_UINT_8( 0xBC, 0x86, 0x98, 0x76, 0x55, 0xBD, 0xEB, 0xB3 ), + BYTES_TO_T_UINT_8( 0xE7, 0x93, 0x3A, 0xAA, 0xD8, 0x35, 0xC6, 0x5A ), +}; +static const mbedtls_mpi_uint secp256r1_gx[] = { + BYTES_TO_T_UINT_8( 0x96, 0xC2, 0x98, 0xD8, 0x45, 0x39, 0xA1, 0xF4 ), + BYTES_TO_T_UINT_8( 0xA0, 0x33, 0xEB, 0x2D, 0x81, 0x7D, 0x03, 0x77 ), + BYTES_TO_T_UINT_8( 0xF2, 0x40, 0xA4, 0x63, 0xE5, 0xE6, 0xBC, 0xF8 ), + BYTES_TO_T_UINT_8( 0x47, 0x42, 0x2C, 0xE1, 0xF2, 0xD1, 0x17, 0x6B ), +}; +static const mbedtls_mpi_uint secp256r1_gy[] = { + BYTES_TO_T_UINT_8( 0xF5, 0x51, 0xBF, 0x37, 0x68, 0x40, 0xB6, 0xCB ), + BYTES_TO_T_UINT_8( 0xCE, 0x5E, 0x31, 0x6B, 0x57, 0x33, 0xCE, 0x2B ), + BYTES_TO_T_UINT_8( 0x16, 0x9E, 0x0F, 0x7C, 0x4A, 0xEB, 0xE7, 0x8E ), + BYTES_TO_T_UINT_8( 0x9B, 0x7F, 0x1A, 0xFE, 0xE2, 0x42, 0xE3, 0x4F ), +}; +static const mbedtls_mpi_uint secp256r1_n[] = { + BYTES_TO_T_UINT_8( 0x51, 0x25, 0x63, 0xFC, 0xC2, 0xCA, 0xB9, 0xF3 ), + BYTES_TO_T_UINT_8( 0x84, 0x9E, 0x17, 0xA7, 0xAD, 0xFA, 0xE6, 0xBC ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +#endif /* MBEDTLS_ECP_DP_SECP256R1_ENABLED */ + +/* + * Domain parameters for secp384r1 + */ +#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) +static const mbedtls_mpi_uint secp384r1_p[] = { + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 ), + BYTES_TO_T_UINT_8( 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +static const mbedtls_mpi_uint secp384r1_b[] = { + BYTES_TO_T_UINT_8( 0xEF, 0x2A, 0xEC, 0xD3, 0xED, 0xC8, 0x85, 0x2A ), + BYTES_TO_T_UINT_8( 0x9D, 0xD1, 0x2E, 0x8A, 0x8D, 0x39, 0x56, 0xC6 ), + BYTES_TO_T_UINT_8( 0x5A, 0x87, 0x13, 0x50, 0x8F, 0x08, 0x14, 0x03 ), + BYTES_TO_T_UINT_8( 0x12, 0x41, 0x81, 0xFE, 0x6E, 0x9C, 0x1D, 0x18 ), + BYTES_TO_T_UINT_8( 0x19, 0x2D, 0xF8, 0xE3, 0x6B, 0x05, 0x8E, 0x98 ), + BYTES_TO_T_UINT_8( 0xE4, 0xE7, 0x3E, 0xE2, 0xA7, 0x2F, 0x31, 0xB3 ), +}; +static const mbedtls_mpi_uint secp384r1_gx[] = { + BYTES_TO_T_UINT_8( 0xB7, 0x0A, 0x76, 0x72, 0x38, 0x5E, 0x54, 0x3A ), + BYTES_TO_T_UINT_8( 0x6C, 0x29, 0x55, 0xBF, 0x5D, 0xF2, 0x02, 0x55 ), + BYTES_TO_T_UINT_8( 0x38, 0x2A, 0x54, 0x82, 0xE0, 0x41, 0xF7, 0x59 ), + BYTES_TO_T_UINT_8( 0x98, 0x9B, 0xA7, 0x8B, 0x62, 0x3B, 0x1D, 0x6E ), + BYTES_TO_T_UINT_8( 0x74, 0xAD, 0x20, 0xF3, 0x1E, 0xC7, 0xB1, 0x8E ), + BYTES_TO_T_UINT_8( 0x37, 0x05, 0x8B, 0xBE, 0x22, 0xCA, 0x87, 0xAA ), +}; +static const mbedtls_mpi_uint secp384r1_gy[] = { + BYTES_TO_T_UINT_8( 0x5F, 0x0E, 0xEA, 0x90, 0x7C, 0x1D, 0x43, 0x7A ), + BYTES_TO_T_UINT_8( 0x9D, 0x81, 0x7E, 0x1D, 0xCE, 0xB1, 0x60, 0x0A ), + BYTES_TO_T_UINT_8( 0xC0, 0xB8, 0xF0, 0xB5, 0x13, 0x31, 0xDA, 0xE9 ), + BYTES_TO_T_UINT_8( 0x7C, 0x14, 0x9A, 0x28, 0xBD, 0x1D, 0xF4, 0xF8 ), + BYTES_TO_T_UINT_8( 0x29, 0xDC, 0x92, 0x92, 0xBF, 0x98, 0x9E, 0x5D ), + BYTES_TO_T_UINT_8( 0x6F, 0x2C, 0x26, 0x96, 0x4A, 0xDE, 0x17, 0x36 ), +}; +static const mbedtls_mpi_uint secp384r1_n[] = { + BYTES_TO_T_UINT_8( 0x73, 0x29, 0xC5, 0xCC, 0x6A, 0x19, 0xEC, 0xEC ), + BYTES_TO_T_UINT_8( 0x7A, 0xA7, 0xB0, 0x48, 0xB2, 0x0D, 0x1A, 0x58 ), + BYTES_TO_T_UINT_8( 0xDF, 0x2D, 0x37, 0xF4, 0x81, 0x4D, 0x63, 0xC7 ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +#endif /* MBEDTLS_ECP_DP_SECP384R1_ENABLED */ + +/* + * Domain parameters for secp521r1 + */ +#if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) +static const mbedtls_mpi_uint secp521r1_p[] = { + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_2( 0xFF, 0x01 ), +}; +static const mbedtls_mpi_uint secp521r1_b[] = { + BYTES_TO_T_UINT_8( 0x00, 0x3F, 0x50, 0x6B, 0xD4, 0x1F, 0x45, 0xEF ), + BYTES_TO_T_UINT_8( 0xF1, 0x34, 0x2C, 0x3D, 0x88, 0xDF, 0x73, 0x35 ), + BYTES_TO_T_UINT_8( 0x07, 0xBF, 0xB1, 0x3B, 0xBD, 0xC0, 0x52, 0x16 ), + BYTES_TO_T_UINT_8( 0x7B, 0x93, 0x7E, 0xEC, 0x51, 0x39, 0x19, 0x56 ), + BYTES_TO_T_UINT_8( 0xE1, 0x09, 0xF1, 0x8E, 0x91, 0x89, 0xB4, 0xB8 ), + BYTES_TO_T_UINT_8( 0xF3, 0x15, 0xB3, 0x99, 0x5B, 0x72, 0xDA, 0xA2 ), + BYTES_TO_T_UINT_8( 0xEE, 0x40, 0x85, 0xB6, 0xA0, 0x21, 0x9A, 0x92 ), + BYTES_TO_T_UINT_8( 0x1F, 0x9A, 0x1C, 0x8E, 0x61, 0xB9, 0x3E, 0x95 ), + BYTES_TO_T_UINT_2( 0x51, 0x00 ), +}; +static const mbedtls_mpi_uint secp521r1_gx[] = { + BYTES_TO_T_UINT_8( 0x66, 0xBD, 0xE5, 0xC2, 0x31, 0x7E, 0x7E, 0xF9 ), + BYTES_TO_T_UINT_8( 0x9B, 0x42, 0x6A, 0x85, 0xC1, 0xB3, 0x48, 0x33 ), + BYTES_TO_T_UINT_8( 0xDE, 0xA8, 0xFF, 0xA2, 0x27, 0xC1, 0x1D, 0xFE ), + BYTES_TO_T_UINT_8( 0x28, 0x59, 0xE7, 0xEF, 0x77, 0x5E, 0x4B, 0xA1 ), + BYTES_TO_T_UINT_8( 0xBA, 0x3D, 0x4D, 0x6B, 0x60, 0xAF, 0x28, 0xF8 ), + BYTES_TO_T_UINT_8( 0x21, 0xB5, 0x3F, 0x05, 0x39, 0x81, 0x64, 0x9C ), + BYTES_TO_T_UINT_8( 0x42, 0xB4, 0x95, 0x23, 0x66, 0xCB, 0x3E, 0x9E ), + BYTES_TO_T_UINT_8( 0xCD, 0xE9, 0x04, 0x04, 0xB7, 0x06, 0x8E, 0x85 ), + BYTES_TO_T_UINT_2( 0xC6, 0x00 ), +}; +static const mbedtls_mpi_uint secp521r1_gy[] = { + BYTES_TO_T_UINT_8( 0x50, 0x66, 0xD1, 0x9F, 0x76, 0x94, 0xBE, 0x88 ), + BYTES_TO_T_UINT_8( 0x40, 0xC2, 0x72, 0xA2, 0x86, 0x70, 0x3C, 0x35 ), + BYTES_TO_T_UINT_8( 0x61, 0x07, 0xAD, 0x3F, 0x01, 0xB9, 0x50, 0xC5 ), + BYTES_TO_T_UINT_8( 0x40, 0x26, 0xF4, 0x5E, 0x99, 0x72, 0xEE, 0x97 ), + BYTES_TO_T_UINT_8( 0x2C, 0x66, 0x3E, 0x27, 0x17, 0xBD, 0xAF, 0x17 ), + BYTES_TO_T_UINT_8( 0x68, 0x44, 0x9B, 0x57, 0x49, 0x44, 0xF5, 0x98 ), + BYTES_TO_T_UINT_8( 0xD9, 0x1B, 0x7D, 0x2C, 0xB4, 0x5F, 0x8A, 0x5C ), + BYTES_TO_T_UINT_8( 0x04, 0xC0, 0x3B, 0x9A, 0x78, 0x6A, 0x29, 0x39 ), + BYTES_TO_T_UINT_2( 0x18, 0x01 ), +}; +static const mbedtls_mpi_uint secp521r1_n[] = { + BYTES_TO_T_UINT_8( 0x09, 0x64, 0x38, 0x91, 0x1E, 0xB7, 0x6F, 0xBB ), + BYTES_TO_T_UINT_8( 0xAE, 0x47, 0x9C, 0x89, 0xB8, 0xC9, 0xB5, 0x3B ), + BYTES_TO_T_UINT_8( 0xD0, 0xA5, 0x09, 0xF7, 0x48, 0x01, 0xCC, 0x7F ), + BYTES_TO_T_UINT_8( 0x6B, 0x96, 0x2F, 0xBF, 0x83, 0x87, 0x86, 0x51 ), + BYTES_TO_T_UINT_8( 0xFA, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_2( 0xFF, 0x01 ), +}; +#endif /* MBEDTLS_ECP_DP_SECP521R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) +static const mbedtls_mpi_uint secp192k1_p[] = { + BYTES_TO_T_UINT_8( 0x37, 0xEE, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +static const mbedtls_mpi_uint secp192k1_a[] = { + BYTES_TO_T_UINT_2( 0x00, 0x00 ), +}; +static const mbedtls_mpi_uint secp192k1_b[] = { + BYTES_TO_T_UINT_2( 0x03, 0x00 ), +}; +static const mbedtls_mpi_uint secp192k1_gx[] = { + BYTES_TO_T_UINT_8( 0x7D, 0x6C, 0xE0, 0xEA, 0xB1, 0xD1, 0xA5, 0x1D ), + BYTES_TO_T_UINT_8( 0x34, 0xF4, 0xB7, 0x80, 0x02, 0x7D, 0xB0, 0x26 ), + BYTES_TO_T_UINT_8( 0xAE, 0xE9, 0x57, 0xC0, 0x0E, 0xF1, 0x4F, 0xDB ), +}; +static const mbedtls_mpi_uint secp192k1_gy[] = { + BYTES_TO_T_UINT_8( 0x9D, 0x2F, 0x5E, 0xD9, 0x88, 0xAA, 0x82, 0x40 ), + BYTES_TO_T_UINT_8( 0x34, 0x86, 0xBE, 0x15, 0xD0, 0x63, 0x41, 0x84 ), + BYTES_TO_T_UINT_8( 0xA7, 0x28, 0x56, 0x9C, 0x6D, 0x2F, 0x2F, 0x9B ), +}; +static const mbedtls_mpi_uint secp192k1_n[] = { + BYTES_TO_T_UINT_8( 0x8D, 0xFD, 0xDE, 0x74, 0x6A, 0x46, 0x69, 0x0F ), + BYTES_TO_T_UINT_8( 0x17, 0xFC, 0xF2, 0x26, 0xFE, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +#endif /* MBEDTLS_ECP_DP_SECP192K1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) +static const mbedtls_mpi_uint secp224k1_p[] = { + BYTES_TO_T_UINT_8( 0x6D, 0xE5, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_4( 0xFF, 0xFF, 0xFF, 0xFF ), +}; +static const mbedtls_mpi_uint secp224k1_a[] = { + BYTES_TO_T_UINT_2( 0x00, 0x00 ), +}; +static const mbedtls_mpi_uint secp224k1_b[] = { + BYTES_TO_T_UINT_2( 0x05, 0x00 ), +}; +static const mbedtls_mpi_uint secp224k1_gx[] = { + BYTES_TO_T_UINT_8( 0x5C, 0xA4, 0xB7, 0xB6, 0x0E, 0x65, 0x7E, 0x0F ), + BYTES_TO_T_UINT_8( 0xA9, 0x75, 0x70, 0xE4, 0xE9, 0x67, 0xA4, 0x69 ), + BYTES_TO_T_UINT_8( 0xA1, 0x28, 0xFC, 0x30, 0xDF, 0x99, 0xF0, 0x4D ), + BYTES_TO_T_UINT_4( 0x33, 0x5B, 0x45, 0xA1 ), +}; +static const mbedtls_mpi_uint secp224k1_gy[] = { + BYTES_TO_T_UINT_8( 0xA5, 0x61, 0x6D, 0x55, 0xDB, 0x4B, 0xCA, 0xE2 ), + BYTES_TO_T_UINT_8( 0x59, 0xBD, 0xB0, 0xC0, 0xF7, 0x19, 0xE3, 0xF7 ), + BYTES_TO_T_UINT_8( 0xD6, 0xFB, 0xCA, 0x82, 0x42, 0x34, 0xBA, 0x7F ), + BYTES_TO_T_UINT_4( 0xED, 0x9F, 0x08, 0x7E ), +}; +static const mbedtls_mpi_uint secp224k1_n[] = { + BYTES_TO_T_UINT_8( 0xF7, 0xB1, 0x9F, 0x76, 0x71, 0xA9, 0xF0, 0xCA ), + BYTES_TO_T_UINT_8( 0x84, 0x61, 0xEC, 0xD2, 0xE8, 0xDC, 0x01, 0x00 ), + BYTES_TO_T_UINT_8( 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ), + BYTES_TO_T_UINT_8( 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 ), +}; +#endif /* MBEDTLS_ECP_DP_SECP224K1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) +static const mbedtls_mpi_uint secp256k1_p[] = { + BYTES_TO_T_UINT_8( 0x2F, 0xFC, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +static const mbedtls_mpi_uint secp256k1_a[] = { + BYTES_TO_T_UINT_2( 0x00, 0x00 ), +}; +static const mbedtls_mpi_uint secp256k1_b[] = { + BYTES_TO_T_UINT_2( 0x07, 0x00 ), +}; +static const mbedtls_mpi_uint secp256k1_gx[] = { + BYTES_TO_T_UINT_8( 0x98, 0x17, 0xF8, 0x16, 0x5B, 0x81, 0xF2, 0x59 ), + BYTES_TO_T_UINT_8( 0xD9, 0x28, 0xCE, 0x2D, 0xDB, 0xFC, 0x9B, 0x02 ), + BYTES_TO_T_UINT_8( 0x07, 0x0B, 0x87, 0xCE, 0x95, 0x62, 0xA0, 0x55 ), + BYTES_TO_T_UINT_8( 0xAC, 0xBB, 0xDC, 0xF9, 0x7E, 0x66, 0xBE, 0x79 ), +}; +static const mbedtls_mpi_uint secp256k1_gy[] = { + BYTES_TO_T_UINT_8( 0xB8, 0xD4, 0x10, 0xFB, 0x8F, 0xD0, 0x47, 0x9C ), + BYTES_TO_T_UINT_8( 0x19, 0x54, 0x85, 0xA6, 0x48, 0xB4, 0x17, 0xFD ), + BYTES_TO_T_UINT_8( 0xA8, 0x08, 0x11, 0x0E, 0xFC, 0xFB, 0xA4, 0x5D ), + BYTES_TO_T_UINT_8( 0x65, 0xC4, 0xA3, 0x26, 0x77, 0xDA, 0x3A, 0x48 ), +}; +static const mbedtls_mpi_uint secp256k1_n[] = { + BYTES_TO_T_UINT_8( 0x41, 0x41, 0x36, 0xD0, 0x8C, 0x5E, 0xD2, 0xBF ), + BYTES_TO_T_UINT_8( 0x3B, 0xA0, 0x48, 0xAF, 0xE6, 0xDC, 0xAE, 0xBA ), + BYTES_TO_T_UINT_8( 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), + BYTES_TO_T_UINT_8( 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ), +}; +#endif /* MBEDTLS_ECP_DP_SECP256K1_ENABLED */ + +/* + * Domain parameters for brainpoolP256r1 (RFC 5639 3.4) + */ +#if defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) +static const mbedtls_mpi_uint brainpoolP256r1_p[] = { + BYTES_TO_T_UINT_8( 0x77, 0x53, 0x6E, 0x1F, 0x1D, 0x48, 0x13, 0x20 ), + BYTES_TO_T_UINT_8( 0x28, 0x20, 0x26, 0xD5, 0x23, 0xF6, 0x3B, 0x6E ), + BYTES_TO_T_UINT_8( 0x72, 0x8D, 0x83, 0x9D, 0x90, 0x0A, 0x66, 0x3E ), + BYTES_TO_T_UINT_8( 0xBC, 0xA9, 0xEE, 0xA1, 0xDB, 0x57, 0xFB, 0xA9 ), +}; +static const mbedtls_mpi_uint brainpoolP256r1_a[] = { + BYTES_TO_T_UINT_8( 0xD9, 0xB5, 0x30, 0xF3, 0x44, 0x4B, 0x4A, 0xE9 ), + BYTES_TO_T_UINT_8( 0x6C, 0x5C, 0xDC, 0x26, 0xC1, 0x55, 0x80, 0xFB ), + BYTES_TO_T_UINT_8( 0xE7, 0xFF, 0x7A, 0x41, 0x30, 0x75, 0xF6, 0xEE ), + BYTES_TO_T_UINT_8( 0x57, 0x30, 0x2C, 0xFC, 0x75, 0x09, 0x5A, 0x7D ), +}; +static const mbedtls_mpi_uint brainpoolP256r1_b[] = { + BYTES_TO_T_UINT_8( 0xB6, 0x07, 0x8C, 0xFF, 0x18, 0xDC, 0xCC, 0x6B ), + BYTES_TO_T_UINT_8( 0xCE, 0xE1, 0xF7, 0x5C, 0x29, 0x16, 0x84, 0x95 ), + BYTES_TO_T_UINT_8( 0xBF, 0x7C, 0xD7, 0xBB, 0xD9, 0xB5, 0x30, 0xF3 ), + BYTES_TO_T_UINT_8( 0x44, 0x4B, 0x4A, 0xE9, 0x6C, 0x5C, 0xDC, 0x26 ), +}; +static const mbedtls_mpi_uint brainpoolP256r1_gx[] = { + BYTES_TO_T_UINT_8( 0x62, 0x32, 0xCE, 0x9A, 0xBD, 0x53, 0x44, 0x3A ), + BYTES_TO_T_UINT_8( 0xC2, 0x23, 0xBD, 0xE3, 0xE1, 0x27, 0xDE, 0xB9 ), + BYTES_TO_T_UINT_8( 0xAF, 0xB7, 0x81, 0xFC, 0x2F, 0x48, 0x4B, 0x2C ), + BYTES_TO_T_UINT_8( 0xCB, 0x57, 0x7E, 0xCB, 0xB9, 0xAE, 0xD2, 0x8B ), +}; +static const mbedtls_mpi_uint brainpoolP256r1_gy[] = { + BYTES_TO_T_UINT_8( 0x97, 0x69, 0x04, 0x2F, 0xC7, 0x54, 0x1D, 0x5C ), + BYTES_TO_T_UINT_8( 0x54, 0x8E, 0xED, 0x2D, 0x13, 0x45, 0x77, 0xC2 ), + BYTES_TO_T_UINT_8( 0xC9, 0x1D, 0x61, 0x14, 0x1A, 0x46, 0xF8, 0x97 ), + BYTES_TO_T_UINT_8( 0xFD, 0xC4, 0xDA, 0xC3, 0x35, 0xF8, 0x7E, 0x54 ), +}; +static const mbedtls_mpi_uint brainpoolP256r1_n[] = { + BYTES_TO_T_UINT_8( 0xA7, 0x56, 0x48, 0x97, 0x82, 0x0E, 0x1E, 0x90 ), + BYTES_TO_T_UINT_8( 0xF7, 0xA6, 0x61, 0xB5, 0xA3, 0x7A, 0x39, 0x8C ), + BYTES_TO_T_UINT_8( 0x71, 0x8D, 0x83, 0x9D, 0x90, 0x0A, 0x66, 0x3E ), + BYTES_TO_T_UINT_8( 0xBC, 0xA9, 0xEE, 0xA1, 0xDB, 0x57, 0xFB, 0xA9 ), +}; +#endif /* MBEDTLS_ECP_DP_BP256R1_ENABLED */ + +/* + * Domain parameters for brainpoolP384r1 (RFC 5639 3.6) + */ +#if defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) +static const mbedtls_mpi_uint brainpoolP384r1_p[] = { + BYTES_TO_T_UINT_8( 0x53, 0xEC, 0x07, 0x31, 0x13, 0x00, 0x47, 0x87 ), + BYTES_TO_T_UINT_8( 0x71, 0x1A, 0x1D, 0x90, 0x29, 0xA7, 0xD3, 0xAC ), + BYTES_TO_T_UINT_8( 0x23, 0x11, 0xB7, 0x7F, 0x19, 0xDA, 0xB1, 0x12 ), + BYTES_TO_T_UINT_8( 0xB4, 0x56, 0x54, 0xED, 0x09, 0x71, 0x2F, 0x15 ), + BYTES_TO_T_UINT_8( 0xDF, 0x41, 0xE6, 0x50, 0x7E, 0x6F, 0x5D, 0x0F ), + BYTES_TO_T_UINT_8( 0x28, 0x6D, 0x38, 0xA3, 0x82, 0x1E, 0xB9, 0x8C ), +}; +static const mbedtls_mpi_uint brainpoolP384r1_a[] = { + BYTES_TO_T_UINT_8( 0x26, 0x28, 0xCE, 0x22, 0xDD, 0xC7, 0xA8, 0x04 ), + BYTES_TO_T_UINT_8( 0xEB, 0xD4, 0x3A, 0x50, 0x4A, 0x81, 0xA5, 0x8A ), + BYTES_TO_T_UINT_8( 0x0F, 0xF9, 0x91, 0xBA, 0xEF, 0x65, 0x91, 0x13 ), + BYTES_TO_T_UINT_8( 0x87, 0x27, 0xB2, 0x4F, 0x8E, 0xA2, 0xBE, 0xC2 ), + BYTES_TO_T_UINT_8( 0xA0, 0xAF, 0x05, 0xCE, 0x0A, 0x08, 0x72, 0x3C ), + BYTES_TO_T_UINT_8( 0x0C, 0x15, 0x8C, 0x3D, 0xC6, 0x82, 0xC3, 0x7B ), +}; +static const mbedtls_mpi_uint brainpoolP384r1_b[] = { + BYTES_TO_T_UINT_8( 0x11, 0x4C, 0x50, 0xFA, 0x96, 0x86, 0xB7, 0x3A ), + BYTES_TO_T_UINT_8( 0x94, 0xC9, 0xDB, 0x95, 0x02, 0x39, 0xB4, 0x7C ), + BYTES_TO_T_UINT_8( 0xD5, 0x62, 0xEB, 0x3E, 0xA5, 0x0E, 0x88, 0x2E ), + BYTES_TO_T_UINT_8( 0xA6, 0xD2, 0xDC, 0x07, 0xE1, 0x7D, 0xB7, 0x2F ), + BYTES_TO_T_UINT_8( 0x7C, 0x44, 0xF0, 0x16, 0x54, 0xB5, 0x39, 0x8B ), + BYTES_TO_T_UINT_8( 0x26, 0x28, 0xCE, 0x22, 0xDD, 0xC7, 0xA8, 0x04 ), +}; +static const mbedtls_mpi_uint brainpoolP384r1_gx[] = { + BYTES_TO_T_UINT_8( 0x1E, 0xAF, 0xD4, 0x47, 0xE2, 0xB2, 0x87, 0xEF ), + BYTES_TO_T_UINT_8( 0xAA, 0x46, 0xD6, 0x36, 0x34, 0xE0, 0x26, 0xE8 ), + BYTES_TO_T_UINT_8( 0xE8, 0x10, 0xBD, 0x0C, 0xFE, 0xCA, 0x7F, 0xDB ), + BYTES_TO_T_UINT_8( 0xE3, 0x4F, 0xF1, 0x7E, 0xE7, 0xA3, 0x47, 0x88 ), + BYTES_TO_T_UINT_8( 0x6B, 0x3F, 0xC1, 0xB7, 0x81, 0x3A, 0xA6, 0xA2 ), + BYTES_TO_T_UINT_8( 0xFF, 0x45, 0xCF, 0x68, 0xF0, 0x64, 0x1C, 0x1D ), +}; +static const mbedtls_mpi_uint brainpoolP384r1_gy[] = { + BYTES_TO_T_UINT_8( 0x15, 0x53, 0x3C, 0x26, 0x41, 0x03, 0x82, 0x42 ), + BYTES_TO_T_UINT_8( 0x11, 0x81, 0x91, 0x77, 0x21, 0x46, 0x46, 0x0E ), + BYTES_TO_T_UINT_8( 0x28, 0x29, 0x91, 0xF9, 0x4F, 0x05, 0x9C, 0xE1 ), + BYTES_TO_T_UINT_8( 0x64, 0x58, 0xEC, 0xFE, 0x29, 0x0B, 0xB7, 0x62 ), + BYTES_TO_T_UINT_8( 0x52, 0xD5, 0xCF, 0x95, 0x8E, 0xEB, 0xB1, 0x5C ), + BYTES_TO_T_UINT_8( 0xA4, 0xC2, 0xF9, 0x20, 0x75, 0x1D, 0xBE, 0x8A ), +}; +static const mbedtls_mpi_uint brainpoolP384r1_n[] = { + BYTES_TO_T_UINT_8( 0x65, 0x65, 0x04, 0xE9, 0x02, 0x32, 0x88, 0x3B ), + BYTES_TO_T_UINT_8( 0x10, 0xC3, 0x7F, 0x6B, 0xAF, 0xB6, 0x3A, 0xCF ), + BYTES_TO_T_UINT_8( 0xA7, 0x25, 0x04, 0xAC, 0x6C, 0x6E, 0x16, 0x1F ), + BYTES_TO_T_UINT_8( 0xB3, 0x56, 0x54, 0xED, 0x09, 0x71, 0x2F, 0x15 ), + BYTES_TO_T_UINT_8( 0xDF, 0x41, 0xE6, 0x50, 0x7E, 0x6F, 0x5D, 0x0F ), + BYTES_TO_T_UINT_8( 0x28, 0x6D, 0x38, 0xA3, 0x82, 0x1E, 0xB9, 0x8C ), +}; +#endif /* MBEDTLS_ECP_DP_BP384R1_ENABLED */ + +/* + * Domain parameters for brainpoolP512r1 (RFC 5639 3.7) + */ +#if defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) +static const mbedtls_mpi_uint brainpoolP512r1_p[] = { + BYTES_TO_T_UINT_8( 0xF3, 0x48, 0x3A, 0x58, 0x56, 0x60, 0xAA, 0x28 ), + BYTES_TO_T_UINT_8( 0x85, 0xC6, 0x82, 0x2D, 0x2F, 0xFF, 0x81, 0x28 ), + BYTES_TO_T_UINT_8( 0xE6, 0x80, 0xA3, 0xE6, 0x2A, 0xA1, 0xCD, 0xAE ), + BYTES_TO_T_UINT_8( 0x42, 0x68, 0xC6, 0x9B, 0x00, 0x9B, 0x4D, 0x7D ), + BYTES_TO_T_UINT_8( 0x71, 0x08, 0x33, 0x70, 0xCA, 0x9C, 0x63, 0xD6 ), + BYTES_TO_T_UINT_8( 0x0E, 0xD2, 0xC9, 0xB3, 0xB3, 0x8D, 0x30, 0xCB ), + BYTES_TO_T_UINT_8( 0x07, 0xFC, 0xC9, 0x33, 0xAE, 0xE6, 0xD4, 0x3F ), + BYTES_TO_T_UINT_8( 0x8B, 0xC4, 0xE9, 0xDB, 0xB8, 0x9D, 0xDD, 0xAA ), +}; +static const mbedtls_mpi_uint brainpoolP512r1_a[] = { + BYTES_TO_T_UINT_8( 0xCA, 0x94, 0xFC, 0x77, 0x4D, 0xAC, 0xC1, 0xE7 ), + BYTES_TO_T_UINT_8( 0xB9, 0xC7, 0xF2, 0x2B, 0xA7, 0x17, 0x11, 0x7F ), + BYTES_TO_T_UINT_8( 0xB5, 0xC8, 0x9A, 0x8B, 0xC9, 0xF1, 0x2E, 0x0A ), + BYTES_TO_T_UINT_8( 0xA1, 0x3A, 0x25, 0xA8, 0x5A, 0x5D, 0xED, 0x2D ), + BYTES_TO_T_UINT_8( 0xBC, 0x63, 0x98, 0xEA, 0xCA, 0x41, 0x34, 0xA8 ), + BYTES_TO_T_UINT_8( 0x10, 0x16, 0xF9, 0x3D, 0x8D, 0xDD, 0xCB, 0x94 ), + BYTES_TO_T_UINT_8( 0xC5, 0x4C, 0x23, 0xAC, 0x45, 0x71, 0x32, 0xE2 ), + BYTES_TO_T_UINT_8( 0x89, 0x3B, 0x60, 0x8B, 0x31, 0xA3, 0x30, 0x78 ), +}; +static const mbedtls_mpi_uint brainpoolP512r1_b[] = { + BYTES_TO_T_UINT_8( 0x23, 0xF7, 0x16, 0x80, 0x63, 0xBD, 0x09, 0x28 ), + BYTES_TO_T_UINT_8( 0xDD, 0xE5, 0xBA, 0x5E, 0xB7, 0x50, 0x40, 0x98 ), + BYTES_TO_T_UINT_8( 0x67, 0x3E, 0x08, 0xDC, 0xCA, 0x94, 0xFC, 0x77 ), + BYTES_TO_T_UINT_8( 0x4D, 0xAC, 0xC1, 0xE7, 0xB9, 0xC7, 0xF2, 0x2B ), + BYTES_TO_T_UINT_8( 0xA7, 0x17, 0x11, 0x7F, 0xB5, 0xC8, 0x9A, 0x8B ), + BYTES_TO_T_UINT_8( 0xC9, 0xF1, 0x2E, 0x0A, 0xA1, 0x3A, 0x25, 0xA8 ), + BYTES_TO_T_UINT_8( 0x5A, 0x5D, 0xED, 0x2D, 0xBC, 0x63, 0x98, 0xEA ), + BYTES_TO_T_UINT_8( 0xCA, 0x41, 0x34, 0xA8, 0x10, 0x16, 0xF9, 0x3D ), +}; +static const mbedtls_mpi_uint brainpoolP512r1_gx[] = { + BYTES_TO_T_UINT_8( 0x22, 0xF8, 0xB9, 0xBC, 0x09, 0x22, 0x35, 0x8B ), + BYTES_TO_T_UINT_8( 0x68, 0x5E, 0x6A, 0x40, 0x47, 0x50, 0x6D, 0x7C ), + BYTES_TO_T_UINT_8( 0x5F, 0x7D, 0xB9, 0x93, 0x7B, 0x68, 0xD1, 0x50 ), + BYTES_TO_T_UINT_8( 0x8D, 0xD4, 0xD0, 0xE2, 0x78, 0x1F, 0x3B, 0xFF ), + BYTES_TO_T_UINT_8( 0x8E, 0x09, 0xD0, 0xF4, 0xEE, 0x62, 0x3B, 0xB4 ), + BYTES_TO_T_UINT_8( 0xC1, 0x16, 0xD9, 0xB5, 0x70, 0x9F, 0xED, 0x85 ), + BYTES_TO_T_UINT_8( 0x93, 0x6A, 0x4C, 0x9C, 0x2E, 0x32, 0x21, 0x5A ), + BYTES_TO_T_UINT_8( 0x64, 0xD9, 0x2E, 0xD8, 0xBD, 0xE4, 0xAE, 0x81 ), +}; +static const mbedtls_mpi_uint brainpoolP512r1_gy[] = { + BYTES_TO_T_UINT_8( 0x92, 0x08, 0xD8, 0x3A, 0x0F, 0x1E, 0xCD, 0x78 ), + BYTES_TO_T_UINT_8( 0x06, 0x54, 0xF0, 0xA8, 0x2F, 0x2B, 0xCA, 0xD1 ), + BYTES_TO_T_UINT_8( 0xAE, 0x63, 0x27, 0x8A, 0xD8, 0x4B, 0xCA, 0x5B ), + BYTES_TO_T_UINT_8( 0x5E, 0x48, 0x5F, 0x4A, 0x49, 0xDE, 0xDC, 0xB2 ), + BYTES_TO_T_UINT_8( 0x11, 0x81, 0x1F, 0x88, 0x5B, 0xC5, 0x00, 0xA0 ), + BYTES_TO_T_UINT_8( 0x1A, 0x7B, 0xA5, 0x24, 0x00, 0xF7, 0x09, 0xF2 ), + BYTES_TO_T_UINT_8( 0xFD, 0x22, 0x78, 0xCF, 0xA9, 0xBF, 0xEA, 0xC0 ), + BYTES_TO_T_UINT_8( 0xEC, 0x32, 0x63, 0x56, 0x5D, 0x38, 0xDE, 0x7D ), +}; +static const mbedtls_mpi_uint brainpoolP512r1_n[] = { + BYTES_TO_T_UINT_8( 0x69, 0x00, 0xA9, 0x9C, 0x82, 0x96, 0x87, 0xB5 ), + BYTES_TO_T_UINT_8( 0xDD, 0xDA, 0x5D, 0x08, 0x81, 0xD3, 0xB1, 0x1D ), + BYTES_TO_T_UINT_8( 0x47, 0x10, 0xAC, 0x7F, 0x19, 0x61, 0x86, 0x41 ), + BYTES_TO_T_UINT_8( 0x19, 0x26, 0xA9, 0x4C, 0x41, 0x5C, 0x3E, 0x55 ), + BYTES_TO_T_UINT_8( 0x70, 0x08, 0x33, 0x70, 0xCA, 0x9C, 0x63, 0xD6 ), + BYTES_TO_T_UINT_8( 0x0E, 0xD2, 0xC9, 0xB3, 0xB3, 0x8D, 0x30, 0xCB ), + BYTES_TO_T_UINT_8( 0x07, 0xFC, 0xC9, 0x33, 0xAE, 0xE6, 0xD4, 0x3F ), + BYTES_TO_T_UINT_8( 0x8B, 0xC4, 0xE9, 0xDB, 0xB8, 0x9D, 0xDD, 0xAA ), +}; +#endif /* MBEDTLS_ECP_DP_BP512R1_ENABLED */ + +/* + * Create an MPI from embedded constants + * (assumes len is an exact multiple of sizeof mbedtls_mpi_uint) + */ +static inline void ecp_mpi_load( mbedtls_mpi *X, const mbedtls_mpi_uint *p, size_t len ) +{ + X->s = 1; + X->n = len / sizeof( mbedtls_mpi_uint ); + X->p = (mbedtls_mpi_uint *) p; +} + +/* + * Set an MPI to static value 1 + */ +static inline void ecp_mpi_set1( mbedtls_mpi *X ) +{ + static mbedtls_mpi_uint one[] = { 1 }; + X->s = 1; + X->n = 1; + X->p = one; +} + +/* + * Make group available from embedded constants + */ +static int ecp_group_load( mbedtls_ecp_group *grp, + const mbedtls_mpi_uint *p, size_t plen, + const mbedtls_mpi_uint *a, size_t alen, + const mbedtls_mpi_uint *b, size_t blen, + const mbedtls_mpi_uint *gx, size_t gxlen, + const mbedtls_mpi_uint *gy, size_t gylen, + const mbedtls_mpi_uint *n, size_t nlen) +{ + ecp_mpi_load( &grp->P, p, plen ); + if( a != NULL ) + ecp_mpi_load( &grp->A, a, alen ); + ecp_mpi_load( &grp->B, b, blen ); + ecp_mpi_load( &grp->N, n, nlen ); + + ecp_mpi_load( &grp->G.X, gx, gxlen ); + ecp_mpi_load( &grp->G.Y, gy, gylen ); + ecp_mpi_set1( &grp->G.Z ); + + grp->pbits = mbedtls_mpi_bitlen( &grp->P ); + grp->nbits = mbedtls_mpi_bitlen( &grp->N ); + + grp->h = 1; + + return( 0 ); +} + +#if defined(MBEDTLS_ECP_NIST_OPTIM) +/* Forward declarations */ +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) +static int ecp_mod_p192( mbedtls_mpi * ); +#endif +#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) +static int ecp_mod_p224( mbedtls_mpi * ); +#endif +#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) +static int ecp_mod_p256( mbedtls_mpi * ); +#endif +#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) +static int ecp_mod_p384( mbedtls_mpi * ); +#endif +#if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) +static int ecp_mod_p521( mbedtls_mpi * ); +#endif + +#define NIST_MODP( P ) grp->modp = ecp_mod_ ## P; +#else +#define NIST_MODP( P ) +#endif /* MBEDTLS_ECP_NIST_OPTIM */ + +/* Additional forward declarations */ +#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) +static int ecp_mod_p255( mbedtls_mpi * ); +#endif +#if defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) +static int ecp_mod_p448( mbedtls_mpi * ); +#endif +#if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) +static int ecp_mod_p192k1( mbedtls_mpi * ); +#endif +#if defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) +static int ecp_mod_p224k1( mbedtls_mpi * ); +#endif +#if defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) +static int ecp_mod_p256k1( mbedtls_mpi * ); +#endif + +#define LOAD_GROUP_A( G ) ecp_group_load( grp, \ + G ## _p, sizeof( G ## _p ), \ + G ## _a, sizeof( G ## _a ), \ + G ## _b, sizeof( G ## _b ), \ + G ## _gx, sizeof( G ## _gx ), \ + G ## _gy, sizeof( G ## _gy ), \ + G ## _n, sizeof( G ## _n ) ) + +#define LOAD_GROUP( G ) ecp_group_load( grp, \ + G ## _p, sizeof( G ## _p ), \ + NULL, 0, \ + G ## _b, sizeof( G ## _b ), \ + G ## _gx, sizeof( G ## _gx ), \ + G ## _gy, sizeof( G ## _gy ), \ + G ## _n, sizeof( G ## _n ) ) + +#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) +/* + * Specialized function for creating the Curve25519 group + */ +static int ecp_use_curve25519( mbedtls_ecp_group *grp ) +{ + int ret; + + /* Actually ( A + 2 ) / 4 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &grp->A, 16, "01DB42" ) ); + + /* P = 2^255 - 19 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &grp->P, 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &grp->P, 255 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_int( &grp->P, &grp->P, 19 ) ); + grp->pbits = mbedtls_mpi_bitlen( &grp->P ); + + /* N = 2^252 + 27742317777372353535851937790883648493 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &grp->N, 16, + "14DEF9DEA2F79CD65812631A5CF5D3ED" ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_set_bit( &grp->N, 252, 1 ) ); + + /* Y intentionally not set, since we use x/z coordinates. + * This is used as a marker to identify Montgomery curves! */ + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &grp->G.X, 9 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &grp->G.Z, 1 ) ); + mbedtls_mpi_free( &grp->G.Y ); + + /* Actually, the required msb for private keys */ + grp->nbits = 254; + +cleanup: + if( ret != 0 ) + mbedtls_ecp_group_free( grp ); + + return( ret ); +} +#endif /* MBEDTLS_ECP_DP_CURVE25519_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) +/* + * Specialized function for creating the Curve448 group + */ +static int ecp_use_curve448( mbedtls_ecp_group *grp ) +{ + mbedtls_mpi Ns; + int ret; + + mbedtls_mpi_init( &Ns ); + + /* Actually ( A + 2 ) / 4 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &grp->A, 16, "98AA" ) ); + + /* P = 2^448 - 2^224 - 1 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &grp->P, 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &grp->P, 224 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_int( &grp->P, &grp->P, 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &grp->P, 224 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_int( &grp->P, &grp->P, 1 ) ); + grp->pbits = mbedtls_mpi_bitlen( &grp->P ); + + /* Y intentionally not set, since we use x/z coordinates. + * This is used as a marker to identify Montgomery curves! */ + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &grp->G.X, 5 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &grp->G.Z, 1 ) ); + mbedtls_mpi_free( &grp->G.Y ); + + /* N = 2^446 - 13818066809895115352007386748515426880336692474882178609894547503885 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_set_bit( &grp->N, 446, 1 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_read_string( &Ns, 16, + "8335DC163BB124B65129C96FDE933D8D723A70AADC873D6D54A7BB0D" ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_mpi( &grp->N, &grp->N, &Ns ) ); + + /* Actually, the required msb for private keys */ + grp->nbits = 447; + +cleanup: + mbedtls_mpi_free( &Ns ); + if( ret != 0 ) + mbedtls_ecp_group_free( grp ); + + return( ret ); +} +#endif /* MBEDTLS_ECP_DP_CURVE448_ENABLED */ + +/* + * Set a group using well-known domain parameters + */ +int mbedtls_ecp_group_load( mbedtls_ecp_group *grp, mbedtls_ecp_group_id id ) +{ + ECP_VALIDATE_RET( grp != NULL ); + mbedtls_ecp_group_free( grp ); + + grp->id = id; + + switch( id ) + { +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) + case MBEDTLS_ECP_DP_SECP192R1: + NIST_MODP( p192 ); + return( LOAD_GROUP( secp192r1 ) ); +#endif /* MBEDTLS_ECP_DP_SECP192R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) + case MBEDTLS_ECP_DP_SECP224R1: + NIST_MODP( p224 ); + return( LOAD_GROUP( secp224r1 ) ); +#endif /* MBEDTLS_ECP_DP_SECP224R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) + case MBEDTLS_ECP_DP_SECP256R1: + NIST_MODP( p256 ); + return( LOAD_GROUP( secp256r1 ) ); +#endif /* MBEDTLS_ECP_DP_SECP256R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) + case MBEDTLS_ECP_DP_SECP384R1: + NIST_MODP( p384 ); + return( LOAD_GROUP( secp384r1 ) ); +#endif /* MBEDTLS_ECP_DP_SECP384R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) + case MBEDTLS_ECP_DP_SECP521R1: + NIST_MODP( p521 ); + return( LOAD_GROUP( secp521r1 ) ); +#endif /* MBEDTLS_ECP_DP_SECP521R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) + case MBEDTLS_ECP_DP_SECP192K1: + grp->modp = ecp_mod_p192k1; + return( LOAD_GROUP_A( secp192k1 ) ); +#endif /* MBEDTLS_ECP_DP_SECP192K1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) + case MBEDTLS_ECP_DP_SECP224K1: + grp->modp = ecp_mod_p224k1; + return( LOAD_GROUP_A( secp224k1 ) ); +#endif /* MBEDTLS_ECP_DP_SECP224K1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) + case MBEDTLS_ECP_DP_SECP256K1: + grp->modp = ecp_mod_p256k1; + return( LOAD_GROUP_A( secp256k1 ) ); +#endif /* MBEDTLS_ECP_DP_SECP256K1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_BP256R1_ENABLED) + case MBEDTLS_ECP_DP_BP256R1: + return( LOAD_GROUP_A( brainpoolP256r1 ) ); +#endif /* MBEDTLS_ECP_DP_BP256R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_BP384R1_ENABLED) + case MBEDTLS_ECP_DP_BP384R1: + return( LOAD_GROUP_A( brainpoolP384r1 ) ); +#endif /* MBEDTLS_ECP_DP_BP384R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_BP512R1_ENABLED) + case MBEDTLS_ECP_DP_BP512R1: + return( LOAD_GROUP_A( brainpoolP512r1 ) ); +#endif /* MBEDTLS_ECP_DP_BP512R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) + case MBEDTLS_ECP_DP_CURVE25519: + grp->modp = ecp_mod_p255; + return( ecp_use_curve25519( grp ) ); +#endif /* MBEDTLS_ECP_DP_CURVE25519_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) + case MBEDTLS_ECP_DP_CURVE448: + grp->modp = ecp_mod_p448; + return( ecp_use_curve448( grp ) ); +#endif /* MBEDTLS_ECP_DP_CURVE448_ENABLED */ + + default: + mbedtls_ecp_group_free( grp ); + return( MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE ); + } +} + +#if defined(MBEDTLS_ECP_NIST_OPTIM) +/* + * Fast reduction modulo the primes used by the NIST curves. + * + * These functions are critical for speed, but not needed for correct + * operations. So, we make the choice to heavily rely on the internals of our + * bignum library, which creates a tight coupling between these functions and + * our MPI implementation. However, the coupling between the ECP module and + * MPI remains loose, since these functions can be deactivated at will. + */ + +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) +/* + * Compared to the way things are presented in FIPS 186-3 D.2, + * we proceed in columns, from right (least significant chunk) to left, + * adding chunks to N in place, and keeping a carry for the next chunk. + * This avoids moving things around in memory, and uselessly adding zeros, + * compared to the more straightforward, line-oriented approach. + * + * For this prime we need to handle data in chunks of 64 bits. + * Since this is always a multiple of our basic mbedtls_mpi_uint, we can + * use a mbedtls_mpi_uint * to designate such a chunk, and small loops to handle it. + */ + +/* Add 64-bit chunks (dst += src) and update carry */ +static inline void add64( mbedtls_mpi_uint *dst, mbedtls_mpi_uint *src, mbedtls_mpi_uint *carry ) +{ + unsigned char i; + mbedtls_mpi_uint c = 0; + for( i = 0; i < 8 / sizeof( mbedtls_mpi_uint ); i++, dst++, src++ ) + { + *dst += c; c = ( *dst < c ); + *dst += *src; c += ( *dst < *src ); + } + *carry += c; +} + +/* Add carry to a 64-bit chunk and update carry */ +static inline void carry64( mbedtls_mpi_uint *dst, mbedtls_mpi_uint *carry ) +{ + unsigned char i; + for( i = 0; i < 8 / sizeof( mbedtls_mpi_uint ); i++, dst++ ) + { + *dst += *carry; + *carry = ( *dst < *carry ); + } +} + +#define WIDTH 8 / sizeof( mbedtls_mpi_uint ) +#define A( i ) N->p + (i) * WIDTH +#define ADD( i ) add64( p, A( i ), &c ) +#define NEXT p += WIDTH; carry64( p, &c ) +#define LAST p += WIDTH; *p = c; while( ++p < end ) *p = 0 + +/* + * Fast quasi-reduction modulo p192 (FIPS 186-3 D.2.1) + */ +static int ecp_mod_p192( mbedtls_mpi *N ) +{ + int ret; + mbedtls_mpi_uint c = 0; + mbedtls_mpi_uint *p, *end; + + /* Make sure we have enough blocks so that A(5) is legal */ + MBEDTLS_MPI_CHK( mbedtls_mpi_grow( N, 6 * WIDTH ) ); + + p = N->p; + end = p + N->n; + + ADD( 3 ); ADD( 5 ); NEXT; // A0 += A3 + A5 + ADD( 3 ); ADD( 4 ); ADD( 5 ); NEXT; // A1 += A3 + A4 + A5 + ADD( 4 ); ADD( 5 ); LAST; // A2 += A4 + A5 + +cleanup: + return( ret ); +} + +#undef WIDTH +#undef A +#undef ADD +#undef NEXT +#undef LAST +#endif /* MBEDTLS_ECP_DP_SECP192R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) +/* + * The reader is advised to first understand ecp_mod_p192() since the same + * general structure is used here, but with additional complications: + * (1) chunks of 32 bits, and (2) subtractions. + */ + +/* + * For these primes, we need to handle data in chunks of 32 bits. + * This makes it more complicated if we use 64 bits limbs in MPI, + * which prevents us from using a uniform access method as for p192. + * + * So, we define a mini abstraction layer to access 32 bit chunks, + * load them in 'cur' for work, and store them back from 'cur' when done. + * + * While at it, also define the size of N in terms of 32-bit chunks. + */ +#define LOAD32 cur = A( i ); + +#if defined(MBEDTLS_HAVE_INT32) /* 32 bit */ + +#define MAX32 N->n +#define A( j ) N->p[j] +#define STORE32 N->p[i] = cur; + +#else /* 64-bit */ + +#define MAX32 N->n * 2 +#define A( j ) (j) % 2 ? (uint32_t)( N->p[(j)/2] >> 32 ) : \ + (uint32_t)( N->p[(j)/2] ) +#define STORE32 \ + if( i % 2 ) { \ + N->p[i/2] &= 0x00000000FFFFFFFF; \ + N->p[i/2] |= ((mbedtls_mpi_uint) cur) << 32; \ + } else { \ + N->p[i/2] &= 0xFFFFFFFF00000000; \ + N->p[i/2] |= (mbedtls_mpi_uint) cur; \ + } + +#endif /* sizeof( mbedtls_mpi_uint ) */ + +/* + * Helpers for addition and subtraction of chunks, with signed carry. + */ +static inline void add32( uint32_t *dst, uint32_t src, signed char *carry ) +{ + *dst += src; + *carry += ( *dst < src ); +} + +static inline void sub32( uint32_t *dst, uint32_t src, signed char *carry ) +{ + *carry -= ( *dst < src ); + *dst -= src; +} + +#define ADD( j ) add32( &cur, A( j ), &c ); +#define SUB( j ) sub32( &cur, A( j ), &c ); + +/* + * Helpers for the main 'loop' + * (see fix_negative for the motivation of C) + */ +#define INIT( b ) \ + int ret; \ + signed char c = 0, cc; \ + uint32_t cur; \ + size_t i = 0, bits = (b); \ + mbedtls_mpi C; \ + mbedtls_mpi_uint Cp[ (b) / 8 / sizeof( mbedtls_mpi_uint) + 1 ]; \ + \ + C.s = 1; \ + C.n = (b) / 8 / sizeof( mbedtls_mpi_uint) + 1; \ + C.p = Cp; \ + memset( Cp, 0, C.n * sizeof( mbedtls_mpi_uint ) ); \ + \ + MBEDTLS_MPI_CHK( mbedtls_mpi_grow( N, (b) * 2 / 8 / \ + sizeof( mbedtls_mpi_uint ) ) ); \ + LOAD32; + +#define NEXT \ + STORE32; i++; LOAD32; \ + cc = c; c = 0; \ + if( cc < 0 ) \ + sub32( &cur, -cc, &c ); \ + else \ + add32( &cur, cc, &c ); \ + +#define LAST \ + STORE32; i++; \ + cur = c > 0 ? c : 0; STORE32; \ + cur = 0; while( ++i < MAX32 ) { STORE32; } \ + if( c < 0 ) fix_negative( N, c, &C, bits ); + +/* + * If the result is negative, we get it in the form + * c * 2^(bits + 32) + N, with c negative and N positive shorter than 'bits' + */ +static inline int fix_negative( mbedtls_mpi *N, signed char c, mbedtls_mpi *C, size_t bits ) +{ + int ret; + + /* C = - c * 2^(bits + 32) */ +#if !defined(MBEDTLS_HAVE_INT64) + ((void) bits); +#else + if( bits == 224 ) + C->p[ C->n - 1 ] = ((mbedtls_mpi_uint) -c) << 32; + else +#endif + C->p[ C->n - 1 ] = (mbedtls_mpi_uint) -c; + + /* N = - ( C - N ) */ + MBEDTLS_MPI_CHK( mbedtls_mpi_sub_abs( N, C, N ) ); + N->s = -1; + +cleanup: + + return( ret ); +} + +#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) +/* + * Fast quasi-reduction modulo p224 (FIPS 186-3 D.2.2) + */ +static int ecp_mod_p224( mbedtls_mpi *N ) +{ + INIT( 224 ); + + SUB( 7 ); SUB( 11 ); NEXT; // A0 += -A7 - A11 + SUB( 8 ); SUB( 12 ); NEXT; // A1 += -A8 - A12 + SUB( 9 ); SUB( 13 ); NEXT; // A2 += -A9 - A13 + SUB( 10 ); ADD( 7 ); ADD( 11 ); NEXT; // A3 += -A10 + A7 + A11 + SUB( 11 ); ADD( 8 ); ADD( 12 ); NEXT; // A4 += -A11 + A8 + A12 + SUB( 12 ); ADD( 9 ); ADD( 13 ); NEXT; // A5 += -A12 + A9 + A13 + SUB( 13 ); ADD( 10 ); LAST; // A6 += -A13 + A10 + +cleanup: + return( ret ); +} +#endif /* MBEDTLS_ECP_DP_SECP224R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) +/* + * Fast quasi-reduction modulo p256 (FIPS 186-3 D.2.3) + */ +static int ecp_mod_p256( mbedtls_mpi *N ) +{ + INIT( 256 ); + + ADD( 8 ); ADD( 9 ); + SUB( 11 ); SUB( 12 ); SUB( 13 ); SUB( 14 ); NEXT; // A0 + + ADD( 9 ); ADD( 10 ); + SUB( 12 ); SUB( 13 ); SUB( 14 ); SUB( 15 ); NEXT; // A1 + + ADD( 10 ); ADD( 11 ); + SUB( 13 ); SUB( 14 ); SUB( 15 ); NEXT; // A2 + + ADD( 11 ); ADD( 11 ); ADD( 12 ); ADD( 12 ); ADD( 13 ); + SUB( 15 ); SUB( 8 ); SUB( 9 ); NEXT; // A3 + + ADD( 12 ); ADD( 12 ); ADD( 13 ); ADD( 13 ); ADD( 14 ); + SUB( 9 ); SUB( 10 ); NEXT; // A4 + + ADD( 13 ); ADD( 13 ); ADD( 14 ); ADD( 14 ); ADD( 15 ); + SUB( 10 ); SUB( 11 ); NEXT; // A5 + + ADD( 14 ); ADD( 14 ); ADD( 15 ); ADD( 15 ); ADD( 14 ); ADD( 13 ); + SUB( 8 ); SUB( 9 ); NEXT; // A6 + + ADD( 15 ); ADD( 15 ); ADD( 15 ); ADD( 8 ); + SUB( 10 ); SUB( 11 ); SUB( 12 ); SUB( 13 ); LAST; // A7 + +cleanup: + return( ret ); +} +#endif /* MBEDTLS_ECP_DP_SECP256R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) +/* + * Fast quasi-reduction modulo p384 (FIPS 186-3 D.2.4) + */ +static int ecp_mod_p384( mbedtls_mpi *N ) +{ + INIT( 384 ); + + ADD( 12 ); ADD( 21 ); ADD( 20 ); + SUB( 23 ); NEXT; // A0 + + ADD( 13 ); ADD( 22 ); ADD( 23 ); + SUB( 12 ); SUB( 20 ); NEXT; // A2 + + ADD( 14 ); ADD( 23 ); + SUB( 13 ); SUB( 21 ); NEXT; // A2 + + ADD( 15 ); ADD( 12 ); ADD( 20 ); ADD( 21 ); + SUB( 14 ); SUB( 22 ); SUB( 23 ); NEXT; // A3 + + ADD( 21 ); ADD( 21 ); ADD( 16 ); ADD( 13 ); ADD( 12 ); ADD( 20 ); ADD( 22 ); + SUB( 15 ); SUB( 23 ); SUB( 23 ); NEXT; // A4 + + ADD( 22 ); ADD( 22 ); ADD( 17 ); ADD( 14 ); ADD( 13 ); ADD( 21 ); ADD( 23 ); + SUB( 16 ); NEXT; // A5 + + ADD( 23 ); ADD( 23 ); ADD( 18 ); ADD( 15 ); ADD( 14 ); ADD( 22 ); + SUB( 17 ); NEXT; // A6 + + ADD( 19 ); ADD( 16 ); ADD( 15 ); ADD( 23 ); + SUB( 18 ); NEXT; // A7 + + ADD( 20 ); ADD( 17 ); ADD( 16 ); + SUB( 19 ); NEXT; // A8 + + ADD( 21 ); ADD( 18 ); ADD( 17 ); + SUB( 20 ); NEXT; // A9 + + ADD( 22 ); ADD( 19 ); ADD( 18 ); + SUB( 21 ); NEXT; // A10 + + ADD( 23 ); ADD( 20 ); ADD( 19 ); + SUB( 22 ); LAST; // A11 + +cleanup: + return( ret ); +} +#endif /* MBEDTLS_ECP_DP_SECP384R1_ENABLED */ + +#undef A +#undef LOAD32 +#undef STORE32 +#undef MAX32 +#undef INIT +#undef NEXT +#undef LAST + +#endif /* MBEDTLS_ECP_DP_SECP224R1_ENABLED || + MBEDTLS_ECP_DP_SECP256R1_ENABLED || + MBEDTLS_ECP_DP_SECP384R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) +/* + * Here we have an actual Mersenne prime, so things are more straightforward. + * However, chunks are aligned on a 'weird' boundary (521 bits). + */ + +/* Size of p521 in terms of mbedtls_mpi_uint */ +#define P521_WIDTH ( 521 / 8 / sizeof( mbedtls_mpi_uint ) + 1 ) + +/* Bits to keep in the most significant mbedtls_mpi_uint */ +#define P521_MASK 0x01FF + +/* + * Fast quasi-reduction modulo p521 (FIPS 186-3 D.2.5) + * Write N as A1 + 2^521 A0, return A0 + A1 + */ +static int ecp_mod_p521( mbedtls_mpi *N ) +{ + int ret; + size_t i; + mbedtls_mpi M; + mbedtls_mpi_uint Mp[P521_WIDTH + 1]; + /* Worst case for the size of M is when mbedtls_mpi_uint is 16 bits: + * we need to hold bits 513 to 1056, which is 34 limbs, that is + * P521_WIDTH + 1. Otherwise P521_WIDTH is enough. */ + + if( N->n < P521_WIDTH ) + return( 0 ); + + /* M = A1 */ + M.s = 1; + M.n = N->n - ( P521_WIDTH - 1 ); + if( M.n > P521_WIDTH + 1 ) + M.n = P521_WIDTH + 1; + M.p = Mp; + memcpy( Mp, N->p + P521_WIDTH - 1, M.n * sizeof( mbedtls_mpi_uint ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &M, 521 % ( 8 * sizeof( mbedtls_mpi_uint ) ) ) ); + + /* N = A0 */ + N->p[P521_WIDTH - 1] &= P521_MASK; + for( i = P521_WIDTH; i < N->n; i++ ) + N->p[i] = 0; + + /* N = A0 + A1 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_add_abs( N, N, &M ) ); + +cleanup: + return( ret ); +} + +#undef P521_WIDTH +#undef P521_MASK +#endif /* MBEDTLS_ECP_DP_SECP521R1_ENABLED */ + +#endif /* MBEDTLS_ECP_NIST_OPTIM */ + +#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) + +/* Size of p255 in terms of mbedtls_mpi_uint */ +#define P255_WIDTH ( 255 / 8 / sizeof( mbedtls_mpi_uint ) + 1 ) + +/* + * Fast quasi-reduction modulo p255 = 2^255 - 19 + * Write N as A0 + 2^255 A1, return A0 + 19 * A1 + */ +static int ecp_mod_p255( mbedtls_mpi *N ) +{ + int ret; + size_t i; + mbedtls_mpi M; + mbedtls_mpi_uint Mp[P255_WIDTH + 2]; + + if( N->n < P255_WIDTH ) + return( 0 ); + + /* M = A1 */ + M.s = 1; + M.n = N->n - ( P255_WIDTH - 1 ); + if( M.n > P255_WIDTH + 1 ) + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + M.p = Mp; + memset( Mp, 0, sizeof Mp ); + memcpy( Mp, N->p + P255_WIDTH - 1, M.n * sizeof( mbedtls_mpi_uint ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &M, 255 % ( 8 * sizeof( mbedtls_mpi_uint ) ) ) ); + M.n++; /* Make room for multiplication by 19 */ + + /* N = A0 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_set_bit( N, 255, 0 ) ); + for( i = P255_WIDTH; i < N->n; i++ ) + N->p[i] = 0; + + /* N = A0 + 19 * A1 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_int( &M, &M, 19 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_abs( N, N, &M ) ); + +cleanup: + return( ret ); +} +#endif /* MBEDTLS_ECP_DP_CURVE25519_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) + +/* Size of p448 in terms of mbedtls_mpi_uint */ +#define P448_WIDTH ( 448 / 8 / sizeof( mbedtls_mpi_uint ) ) + +/* Number of limbs fully occupied by 2^224 (max), and limbs used by it (min) */ +#define DIV_ROUND_UP( X, Y ) ( ( ( X ) + ( Y ) - 1 ) / ( Y ) ) +#define P224_WIDTH_MIN ( 28 / sizeof( mbedtls_mpi_uint ) ) +#define P224_WIDTH_MAX DIV_ROUND_UP( 28, sizeof( mbedtls_mpi_uint ) ) +#define P224_UNUSED_BITS ( ( P224_WIDTH_MAX * sizeof( mbedtls_mpi_uint ) * 8 ) - 224 ) + +/* + * Fast quasi-reduction modulo p448 = 2^448 - 2^224 - 1 + * Write N as A0 + 2^448 A1 and A1 as B0 + 2^224 B1, and return + * A0 + A1 + B1 + (B0 + B1) * 2^224. This is different to the reference + * implementation of Curve448, which uses its own special 56-bit limbs rather + * than a generic bignum library. We could squeeze some extra speed out on + * 32-bit machines by splitting N up into 32-bit limbs and doing the + * arithmetic using the limbs directly as we do for the NIST primes above, + * but for 64-bit targets it should use half the number of operations if we do + * the reduction with 224-bit limbs, since mpi_add_mpi will then use 64-bit adds. + */ +static int ecp_mod_p448( mbedtls_mpi *N ) +{ + int ret; + size_t i; + mbedtls_mpi M, Q; + mbedtls_mpi_uint Mp[P448_WIDTH + 1], Qp[P448_WIDTH]; + + if( N->n <= P448_WIDTH ) + return( 0 ); + + /* M = A1 */ + M.s = 1; + M.n = N->n - ( P448_WIDTH ); + if( M.n > P448_WIDTH ) + /* Shouldn't be called with N larger than 2^896! */ + return( MBEDTLS_ERR_ECP_BAD_INPUT_DATA ); + M.p = Mp; + memset( Mp, 0, sizeof( Mp ) ); + memcpy( Mp, N->p + P448_WIDTH, M.n * sizeof( mbedtls_mpi_uint ) ); + + /* N = A0 */ + for( i = P448_WIDTH; i < N->n; i++ ) + N->p[i] = 0; + + /* N += A1 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( N, N, &M ) ); + + /* Q = B1, N += B1 */ + Q = M; + Q.p = Qp; + memcpy( Qp, Mp, sizeof( Qp ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &Q, 224 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( N, N, &Q ) ); + + /* M = (B0 + B1) * 2^224, N += M */ + if( sizeof( mbedtls_mpi_uint ) > 4 ) + Mp[P224_WIDTH_MIN] &= ( (mbedtls_mpi_uint)-1 ) >> ( P224_UNUSED_BITS ); + for( i = P224_WIDTH_MAX; i < M.n; ++i ) + Mp[i] = 0; + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( &M, &M, &Q ) ); + M.n = P448_WIDTH + 1; /* Make room for shifted carry bit from the addition */ + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_l( &M, 224 ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_mpi( N, N, &M ) ); + +cleanup: + return( ret ); +} +#endif /* MBEDTLS_ECP_DP_CURVE448_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) || \ + defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) +/* + * Fast quasi-reduction modulo P = 2^s - R, + * with R about 33 bits, used by the Koblitz curves. + * + * Write N as A0 + 2^224 A1, return A0 + R * A1. + * Actually do two passes, since R is big. + */ +#define P_KOBLITZ_MAX ( 256 / 8 / sizeof( mbedtls_mpi_uint ) ) // Max limbs in P +#define P_KOBLITZ_R ( 8 / sizeof( mbedtls_mpi_uint ) ) // Limbs in R +static inline int ecp_mod_koblitz( mbedtls_mpi *N, mbedtls_mpi_uint *Rp, size_t p_limbs, + size_t adjust, size_t shift, mbedtls_mpi_uint mask ) +{ + int ret; + size_t i; + mbedtls_mpi M, R; + mbedtls_mpi_uint Mp[P_KOBLITZ_MAX + P_KOBLITZ_R + 1]; + + if( N->n < p_limbs ) + return( 0 ); + + /* Init R */ + R.s = 1; + R.p = Rp; + R.n = P_KOBLITZ_R; + + /* Common setup for M */ + M.s = 1; + M.p = Mp; + + /* M = A1 */ + M.n = N->n - ( p_limbs - adjust ); + if( M.n > p_limbs + adjust ) + M.n = p_limbs + adjust; + memset( Mp, 0, sizeof Mp ); + memcpy( Mp, N->p + p_limbs - adjust, M.n * sizeof( mbedtls_mpi_uint ) ); + if( shift != 0 ) + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &M, shift ) ); + M.n += R.n; /* Make room for multiplication by R */ + + /* N = A0 */ + if( mask != 0 ) + N->p[p_limbs - 1] &= mask; + for( i = p_limbs; i < N->n; i++ ) + N->p[i] = 0; + + /* N = A0 + R * A1 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &M, &M, &R ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_abs( N, N, &M ) ); + + /* Second pass */ + + /* M = A1 */ + M.n = N->n - ( p_limbs - adjust ); + if( M.n > p_limbs + adjust ) + M.n = p_limbs + adjust; + memset( Mp, 0, sizeof Mp ); + memcpy( Mp, N->p + p_limbs - adjust, M.n * sizeof( mbedtls_mpi_uint ) ); + if( shift != 0 ) + MBEDTLS_MPI_CHK( mbedtls_mpi_shift_r( &M, shift ) ); + M.n += R.n; /* Make room for multiplication by R */ + + /* N = A0 */ + if( mask != 0 ) + N->p[p_limbs - 1] &= mask; + for( i = p_limbs; i < N->n; i++ ) + N->p[i] = 0; + + /* N = A0 + R * A1 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &M, &M, &R ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_add_abs( N, N, &M ) ); + +cleanup: + return( ret ); +} +#endif /* MBEDTLS_ECP_DP_SECP192K1_ENABLED) || + MBEDTLS_ECP_DP_SECP224K1_ENABLED) || + MBEDTLS_ECP_DP_SECP256K1_ENABLED) */ + +#if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) +/* + * Fast quasi-reduction modulo p192k1 = 2^192 - R, + * with R = 2^32 + 2^12 + 2^8 + 2^7 + 2^6 + 2^3 + 1 = 0x0100001119 + */ +static int ecp_mod_p192k1( mbedtls_mpi *N ) +{ + static mbedtls_mpi_uint Rp[] = { + BYTES_TO_T_UINT_8( 0xC9, 0x11, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 ) }; + + return( ecp_mod_koblitz( N, Rp, 192 / 8 / sizeof( mbedtls_mpi_uint ), 0, 0, 0 ) ); +} +#endif /* MBEDTLS_ECP_DP_SECP192K1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP224K1_ENABLED) +/* + * Fast quasi-reduction modulo p224k1 = 2^224 - R, + * with R = 2^32 + 2^12 + 2^11 + 2^9 + 2^7 + 2^4 + 2 + 1 = 0x0100001A93 + */ +static int ecp_mod_p224k1( mbedtls_mpi *N ) +{ + static mbedtls_mpi_uint Rp[] = { + BYTES_TO_T_UINT_8( 0x93, 0x1A, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 ) }; + +#if defined(MBEDTLS_HAVE_INT64) + return( ecp_mod_koblitz( N, Rp, 4, 1, 32, 0xFFFFFFFF ) ); +#else + return( ecp_mod_koblitz( N, Rp, 224 / 8 / sizeof( mbedtls_mpi_uint ), 0, 0, 0 ) ); +#endif +} + +#endif /* MBEDTLS_ECP_DP_SECP224K1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP256K1_ENABLED) +/* + * Fast quasi-reduction modulo p256k1 = 2^256 - R, + * with R = 2^32 + 2^9 + 2^8 + 2^7 + 2^6 + 2^4 + 1 = 0x01000003D1 + */ +static int ecp_mod_p256k1( mbedtls_mpi *N ) +{ + static mbedtls_mpi_uint Rp[] = { + BYTES_TO_T_UINT_8( 0xD1, 0x03, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 ) }; + return( ecp_mod_koblitz( N, Rp, 256 / 8 / sizeof( mbedtls_mpi_uint ), 0, 0, 0 ) ); +} +#endif /* MBEDTLS_ECP_DP_SECP256K1_ENABLED */ + +#endif /* MBEDTLS_ECP_ALT */ + +#endif /* MBEDTLS_ECP_C */ diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/mbedtls_device.h b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/mbedtls_device.h new file mode 100644 index 00000000000..ac98f7d07ef --- /dev/null +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/mbedtls_device.h @@ -0,0 +1,47 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2019 Cypress Semiconductor Corporation + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_DEVICE_H +#define MBEDTLS_DEVICE_H + +/* Currently this target supports SHA1 */ +// #define MBEDTLS_SHA1_C + +#define MBEDTLS_SHA1_ALT +#define MBEDTLS_SHA256_ALT +#define MBEDTLS_SHA512_ALT + +/* Currently this target supports CBC, CFB, OFB, CTR and XTS cipher modes */ +#define MBEDTLS_AES_ALT +// #define MBEDTLS_CIPHER_MODE_CBC +// #define MBEDTLS_CIPHER_MODE_CFB +// #define MBEDTLS_CIPHER_MODE_OFB +// #define MBEDTLS_CIPHER_MODE_CTR +// #define MBEDTLS_CIPHER_MODE_XTS + +/* Only NIST-P curves are currently supported */ +#define MBEDTLS_ECP_ALT +// #define MBEDTLS_ECP_DP_SECP192R1_ENABLED +// #define MBEDTLS_ECP_DP_SECP224R1_ENABLED +// #define MBEDTLS_ECP_DP_SECP256R1_ENABLED +// #define MBEDTLS_ECP_DP_SECP384R1_ENABLED +// #define MBEDTLS_ECP_DP_SECP521R1_ENABLED + +#define MBEDTLS_ECDSA_SIGN_ALT +#define MBEDTLS_ECDSA_VERIFY_ALT + +#endif /* MBEDTLS_DEVICE_H */ diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha1_alt.c b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha1_alt.c new file mode 100644 index 00000000000..1ad1b3fb788 --- /dev/null +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha1_alt.c @@ -0,0 +1,115 @@ +/* + * mbed Microcontroller Library + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright (C) 2019 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * \file sha1_alt.c + * \version 1.0 + * + * \brief Source file - wrapper for mbedtls SHA1 HW acceleration + * + */ + + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_SHA1_C) + +#include "mbedtls/sha1.h" +#include "mbedtls/platform_util.h" + +#include + +/* Parameter validation macros based on platform_util.h */ +#define SHA1_VALIDATE_RET(cond) \ + MBEDTLS_INTERNAL_VALIDATE_RET( cond, MBEDTLS_ERR_SHA1_BAD_INPUT_DATA ) +#define SHA1_VALIDATE(cond) MBEDTLS_INTERNAL_VALIDATE( cond ) + +#if defined(MBEDTLS_SHA1_ALT) + +void mbedtls_sha1_init( mbedtls_sha1_context *ctx ) +{ + SHA1_VALIDATE( ctx != NULL ); + + cy_hw_sha_init(ctx, sizeof( mbedtls_sha1_context )); +} + +void mbedtls_sha1_free( mbedtls_sha1_context *ctx ) +{ + SHA1_VALIDATE( ctx != NULL ); + + cy_hw_sha_free(ctx, sizeof( mbedtls_sha1_context )); +} + +void mbedtls_sha1_clone( mbedtls_sha1_context *dst, const mbedtls_sha1_context *src ) +{ + SHA1_VALIDATE( dst != NULL ); + SHA1_VALIDATE( src != NULL ); + + cy_hw_sha_clone(dst, src, sizeof(mbedtls_sha1_context), &dst->hashState, &dst->shaBuffers); +} + +/* + * SHA-1 context setup + */ +int mbedtls_sha1_starts_ret( mbedtls_sha1_context *ctx ) +{ + SHA1_VALIDATE_RET( ctx != NULL ); + + return cy_hw_sha_start(&ctx->obj, &ctx->hashState, CY_CRYPTO_MODE_SHA1, &ctx->shaBuffers); +} + +/* + * SHA-1 process buffer + */ +int mbedtls_sha1_update_ret( mbedtls_sha1_context *ctx, + const unsigned char *input, + size_t ilen ) +{ + SHA1_VALIDATE_RET( ctx != NULL ); + SHA1_VALIDATE_RET( ilen == 0 || input != NULL ); + + return cy_hw_sha_update(&ctx->obj, &ctx->hashState, input, ilen); +} + +/* + * SHA-1 final digest + */ +int mbedtls_sha1_finish_ret( mbedtls_sha1_context *ctx, unsigned char output[20]) +{ + SHA1_VALIDATE_RET( ctx != NULL ); + SHA1_VALIDATE_RET( (unsigned char *)output != NULL ); + + return cy_hw_sha_finish(&ctx->obj, &ctx->hashState, output); +} + +int mbedtls_internal_sha1_process( mbedtls_sha1_context *ctx, const unsigned char data[64] ) +{ + SHA1_VALIDATE_RET( ctx != NULL ); + SHA1_VALIDATE_RET( (const unsigned char *)data != NULL ); + + return cy_hw_sha_process(&ctx->obj, &ctx->hashState, data); +} + +#endif /* MBEDTLS_SHA1_ALT */ + +#endif /* MBEDTLS_SHA1_C */ diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha256_alt.c b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha256_alt.c new file mode 100644 index 00000000000..bb648711b65 --- /dev/null +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha256_alt.c @@ -0,0 +1,115 @@ +/* + * mbed Microcontroller Library + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright (C) 2019 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * \file sha256_alt.c + * \version 1.0 + * + * \brief Source file - wrapper for mbedtls SHA256 HW acceleration + * + */ + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_SHA256_C) + +#include "mbedtls/sha256.h" +#include "mbedtls/platform_util.h" + +#include + +/* Parameter validation macros based on platform_util.h */ +#define SHA256_VALIDATE_RET(cond) \ + MBEDTLS_INTERNAL_VALIDATE_RET( cond, MBEDTLS_ERR_SHA256_BAD_INPUT_DATA ) +#define SHA256_VALIDATE(cond) MBEDTLS_INTERNAL_VALIDATE( cond ) + +#if defined(MBEDTLS_SHA256_ALT) + +void mbedtls_sha256_init( mbedtls_sha256_context *ctx ) +{ + SHA256_VALIDATE( ctx != NULL ); + + cy_hw_sha_init(ctx, sizeof( mbedtls_sha256_context )); +} + +void mbedtls_sha256_free( mbedtls_sha256_context *ctx ) +{ + SHA256_VALIDATE ( ctx != NULL ); + + cy_hw_sha_free(ctx, sizeof( mbedtls_sha256_context )); +} + +void mbedtls_sha256_clone( mbedtls_sha256_context *dst, const mbedtls_sha256_context *src ) +{ + SHA256_VALIDATE( dst != NULL ); + SHA256_VALIDATE( src != NULL ); + + cy_hw_sha_clone(dst, src, sizeof(mbedtls_sha256_context), &dst->hashState, &dst->shaBuffers); +} + +/* + * SHA-256 context setup + */ +int mbedtls_sha256_starts_ret( mbedtls_sha256_context *ctx, int is224) +{ + SHA256_VALIDATE_RET( ctx != NULL ); + SHA256_VALIDATE_RET( is224 == 0 || is224 == 1 ); + + return cy_hw_sha_start(&ctx->obj, &ctx->hashState, + ( is224 == 0 ) ? CY_CRYPTO_MODE_SHA256 : CY_CRYPTO_MODE_SHA224, + &ctx->shaBuffers); +} + +/* + * SHA-256 process buffer + */ +int mbedtls_sha256_update_ret( mbedtls_sha256_context *ctx, const unsigned char *input, size_t ilen ) +{ + SHA256_VALIDATE_RET( ctx != NULL ); + SHA256_VALIDATE_RET( ilen == 0 || input != NULL ); + + return cy_hw_sha_update(&ctx->obj, &ctx->hashState, (uint8_t *)input, ilen); +} + +/* + * SHA-256 final digest + */ +int mbedtls_sha256_finish_ret( mbedtls_sha256_context *ctx, unsigned char output[32] ) +{ + SHA256_VALIDATE_RET( ctx != NULL ); + SHA256_VALIDATE_RET( (unsigned char *)output != NULL ); + + return cy_hw_sha_finish(&ctx->obj, &ctx->hashState, output); +} + +int mbedtls_internal_sha256_process( mbedtls_sha256_context *ctx, const unsigned char data[64] ) +{ + SHA256_VALIDATE_RET( ctx != NULL ); + SHA256_VALIDATE_RET( (const unsigned char *)data != NULL ); + + return cy_hw_sha_process(&ctx->obj, &ctx->hashState, (unsigned char *)data); +} + +#endif /* MBEDTLS_SHA256_ALT */ + +#endif /* MBEDTLS_SHA256_C */ diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha512_alt.c b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha512_alt.c new file mode 100644 index 00000000000..444f6d06b6f --- /dev/null +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha512_alt.c @@ -0,0 +1,115 @@ +/* + * mbed Microcontroller Library + * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved + * Copyright (C) 2019 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * \file sha512_alt.c + * \version 1.0 + * + * \brief Source file - wrapper for mbedtls SHA512 HW acceleration + * + */ + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_SHA512_C) + +#include "mbedtls/sha512.h" +#include "mbedtls/platform_util.h" + +#include + +/* Parameter validation macros based on platform_util.h */ +#define SHA512_VALIDATE_RET(cond) \ + MBEDTLS_INTERNAL_VALIDATE_RET( cond, MBEDTLS_ERR_SHA512_BAD_INPUT_DATA ) +#define SHA512_VALIDATE(cond) MBEDTLS_INTERNAL_VALIDATE( cond ) + +#if defined(MBEDTLS_SHA512_ALT) + +void mbedtls_sha512_init( mbedtls_sha512_context *ctx ) +{ + SHA512_VALIDATE( ctx != NULL ); + + cy_hw_sha_init(ctx, sizeof( mbedtls_sha512_context )); +} + +void mbedtls_sha512_free( mbedtls_sha512_context *ctx ) +{ + SHA512_VALIDATE( ctx != NULL ); + + cy_hw_sha_free(ctx, sizeof( mbedtls_sha512_context )); +} + +void mbedtls_sha512_clone( mbedtls_sha512_context *dst, const mbedtls_sha512_context *src ) +{ + SHA512_VALIDATE( dst != NULL ); + SHA512_VALIDATE( src != NULL ); + + cy_hw_sha_clone(dst, src, sizeof(mbedtls_sha512_context), &dst->hashState, &dst->shaBuffers); +} + +/* + * SHA-512 context setup + */ +int mbedtls_sha512_starts_ret( mbedtls_sha512_context *ctx, int is384) +{ + SHA512_VALIDATE_RET( ctx != NULL ); + SHA512_VALIDATE_RET( is384 == 0 || is384 == 1 ); + + return cy_hw_sha_start(&ctx->obj, &ctx->hashState, + ( is384 == 0 ) ? CY_CRYPTO_MODE_SHA512 : CY_CRYPTO_MODE_SHA384, + &ctx->shaBuffers); +} + +/* + * SHA-512 process buffer + */ +int mbedtls_sha512_update_ret( mbedtls_sha512_context *ctx, const unsigned char *input, size_t ilen ) +{ + SHA512_VALIDATE_RET( ctx != NULL ); + SHA512_VALIDATE_RET( ilen == 0 || input != NULL ); + + return cy_hw_sha_update(&ctx->obj, &ctx->hashState, input, ilen); +} + +/* + * SHA-512 final digest + */ +int mbedtls_sha512_finish_ret( mbedtls_sha512_context *ctx, unsigned char output[64] ) +{ + SHA512_VALIDATE_RET( ctx != NULL ); + SHA512_VALIDATE_RET( (unsigned char *)output != NULL ); + + return cy_hw_sha_finish(&ctx->obj, &ctx->hashState, output); +} + +int mbedtls_internal_sha512_process( mbedtls_sha512_context *ctx, const unsigned char data[128] ) +{ + SHA512_VALIDATE_RET( ctx != NULL ); + SHA512_VALIDATE_RET( (const unsigned char *)data != NULL ); + + return cy_hw_sha_process(&ctx->obj, &ctx->hashState, data); +} + +#endif /* MBEDTLS_SHA512_ALT */ + +#endif /* MBEDTLS_SHA512_C */ diff --git a/targets/targets.json b/targets/targets.json index cd5937f52f6..a5812022456 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -8792,7 +8792,7 @@ }, "MCU_PSOC6": { "inherits": ["Target"], - "macros": ["MBED_MPU_CUSTOM", "LPTICKER_DELAY_TICKS=3"], + "macros": ["MBED_MPU_CUSTOM", "MBEDTLS_CONFIG_HW_SUPPORT", "LPTICKER_DELAY_TICKS=3"], "default_toolchain": "GCC_ARM", "supported_toolchains": ["ARM", "GCC_ARM", "IAR"], "core": "Cortex-M4F", From 3727c827360b6ffec601e3667003c4c3ab951724 Mon Sep 17 00:00:00 2001 From: Kostiantyn Tkachov Date: Fri, 16 Aug 2019 17:21:26 +0300 Subject: [PATCH 036/227] Fixed SHA ctx and ilen parameters checking --- .../mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha1_alt.c | 6 +++++- .../targets/TARGET_Cypress/TARGET_PSOC6/sha256_alt.c | 6 +++++- .../targets/TARGET_Cypress/TARGET_PSOC6/sha512_alt.c | 6 +++++- 3 files changed, 15 insertions(+), 3 deletions(-) diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha1_alt.c b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha1_alt.c index 1ad1b3fb788..ddb0dc81783 100644 --- a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha1_alt.c +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha1_alt.c @@ -55,7 +55,8 @@ void mbedtls_sha1_init( mbedtls_sha1_context *ctx ) void mbedtls_sha1_free( mbedtls_sha1_context *ctx ) { - SHA1_VALIDATE( ctx != NULL ); + if (ctx == NULL) + return; cy_hw_sha_free(ctx, sizeof( mbedtls_sha1_context )); } @@ -88,6 +89,9 @@ int mbedtls_sha1_update_ret( mbedtls_sha1_context *ctx, SHA1_VALIDATE_RET( ctx != NULL ); SHA1_VALIDATE_RET( ilen == 0 || input != NULL ); + if (ilen == 0) + return; + return cy_hw_sha_update(&ctx->obj, &ctx->hashState, input, ilen); } diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha256_alt.c b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha256_alt.c index bb648711b65..daf89404b31 100644 --- a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha256_alt.c +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha256_alt.c @@ -54,7 +54,8 @@ void mbedtls_sha256_init( mbedtls_sha256_context *ctx ) void mbedtls_sha256_free( mbedtls_sha256_context *ctx ) { - SHA256_VALIDATE ( ctx != NULL ); + if (ctx == NULL) + return; cy_hw_sha_free(ctx, sizeof( mbedtls_sha256_context )); } @@ -88,6 +89,9 @@ int mbedtls_sha256_update_ret( mbedtls_sha256_context *ctx, const unsigned char SHA256_VALIDATE_RET( ctx != NULL ); SHA256_VALIDATE_RET( ilen == 0 || input != NULL ); + if (ilen == 0) + return; + return cy_hw_sha_update(&ctx->obj, &ctx->hashState, (uint8_t *)input, ilen); } diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha512_alt.c b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha512_alt.c index 444f6d06b6f..dd6f5fed431 100644 --- a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha512_alt.c +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha512_alt.c @@ -54,7 +54,8 @@ void mbedtls_sha512_init( mbedtls_sha512_context *ctx ) void mbedtls_sha512_free( mbedtls_sha512_context *ctx ) { - SHA512_VALIDATE( ctx != NULL ); + if (ctx == NULL) + return; cy_hw_sha_free(ctx, sizeof( mbedtls_sha512_context )); } @@ -87,6 +88,9 @@ int mbedtls_sha512_update_ret( mbedtls_sha512_context *ctx, const unsigned char { SHA512_VALIDATE_RET( ctx != NULL ); SHA512_VALIDATE_RET( ilen == 0 || input != NULL ); + + if (ilen == 0) + return; return cy_hw_sha_update(&ctx->obj, &ctx->hashState, input, ilen); } From e2a84556e62b2d6f54ee5ca61238595f142972d8 Mon Sep 17 00:00:00 2001 From: Kostiantyn Tkachov Date: Fri, 16 Aug 2019 17:29:58 +0300 Subject: [PATCH 037/227] Fixed SHA ctx and ilen parameters checking --- .../mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha1_alt.c | 2 +- .../mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha256_alt.c | 4 ++-- .../mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha512_alt.c | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha1_alt.c b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha1_alt.c index ddb0dc81783..a8d02543106 100644 --- a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha1_alt.c +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha1_alt.c @@ -90,7 +90,7 @@ int mbedtls_sha1_update_ret( mbedtls_sha1_context *ctx, SHA1_VALIDATE_RET( ilen == 0 || input != NULL ); if (ilen == 0) - return; + return (0); return cy_hw_sha_update(&ctx->obj, &ctx->hashState, input, ilen); } diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha256_alt.c b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha256_alt.c index daf89404b31..efb8552653f 100644 --- a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha256_alt.c +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha256_alt.c @@ -90,8 +90,8 @@ int mbedtls_sha256_update_ret( mbedtls_sha256_context *ctx, const unsigned char SHA256_VALIDATE_RET( ilen == 0 || input != NULL ); if (ilen == 0) - return; - + return (0); + return cy_hw_sha_update(&ctx->obj, &ctx->hashState, (uint8_t *)input, ilen); } diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha512_alt.c b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha512_alt.c index dd6f5fed431..5d9cf48a3ca 100644 --- a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha512_alt.c +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha512_alt.c @@ -88,9 +88,9 @@ int mbedtls_sha512_update_ret( mbedtls_sha512_context *ctx, const unsigned char { SHA512_VALIDATE_RET( ctx != NULL ); SHA512_VALIDATE_RET( ilen == 0 || input != NULL ); - + if (ilen == 0) - return; + return (0); return cy_hw_sha_update(&ctx->obj, &ctx->hashState, input, ilen); } From f583fd8b2699f01564039deb752df4989747f12b Mon Sep 17 00:00:00 2001 From: Kostiantyn Tkachov Date: Mon, 2 Sep 2019 16:29:00 +0300 Subject: [PATCH 038/227] Removed obsoleted typedef for mbedtls_be128[] in aes_alt.c --- features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/aes_alt.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/aes_alt.c b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/aes_alt.c index 156d6dc4a38..07414b990a3 100644 --- a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/aes_alt.c +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/aes_alt.c @@ -420,8 +420,6 @@ int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, } #endif -typedef unsigned char mbedtls_be128[16]; - /* * GF(2^128) multiplication function * From 04e6f79ae8b2fea99c80c132207d1b8ab06d7562 Mon Sep 17 00:00:00 2001 From: Kostiantyn Tkachov Date: Mon, 2 Sep 2019 17:00:13 +0300 Subject: [PATCH 039/227] Removed TABs from the ALT source files --- .../TARGET_Cypress/TARGET_PSOC6/aes_alt.c | 12 +++++----- .../TARGET_PSOC6/crypto_common.c | 2 +- .../TARGET_PSOC6/crypto_common.h | 2 +- .../TARGET_Cypress/TARGET_PSOC6/ecdsa_alt.c | 24 +++++++++---------- .../TARGET_Cypress/TARGET_PSOC6/ecp_alt.c | 8 +++---- 5 files changed, 24 insertions(+), 24 deletions(-) diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/aes_alt.c b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/aes_alt.c index 07414b990a3..745861b1224 100644 --- a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/aes_alt.c +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/aes_alt.c @@ -104,8 +104,8 @@ static int aes_set_keys( mbedtls_aes_context *ctx, const unsigned char *key, unsigned int keybits ) { int ret = 0; - cy_en_crypto_aes_key_length_t key_length; - cy_en_crypto_status_t status; + cy_en_crypto_aes_key_length_t key_length; + cy_en_crypto_status_t status; AES_VALIDATE( ctx != NULL ); @@ -121,8 +121,8 @@ static int aes_set_keys( mbedtls_aes_context *ctx, const unsigned char *key, if (CY_CRYPTO_SUCCESS != status) { - ret = MBEDTLS_ERR_AES_HW_ACCEL_FAILED; - goto exit; + ret = MBEDTLS_ERR_AES_HW_ACCEL_FAILED; + goto exit; } exit: @@ -247,7 +247,7 @@ int mbedtls_internal_aes_encrypt( mbedtls_aes_context *ctx, if (CY_CRYPTO_SUCCESS != status) { - ret = MBEDTLS_ERR_AES_HW_ACCEL_FAILED; + ret = MBEDTLS_ERR_AES_HW_ACCEL_FAILED; } return( ret ); @@ -279,7 +279,7 @@ int mbedtls_internal_aes_decrypt( mbedtls_aes_context *ctx, if (CY_CRYPTO_SUCCESS != status) { - ret = MBEDTLS_ERR_AES_HW_ACCEL_FAILED; + ret = MBEDTLS_ERR_AES_HW_ACCEL_FAILED; } return( ret ); diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/crypto_common.c b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/crypto_common.c index 4c8d96d4d32..4f7cc3becc0 100644 --- a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/crypto_common.c +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/crypto_common.c @@ -152,7 +152,7 @@ int cy_hw_sha_process(cy_hw_crypto_t *obj, cy_stc_crypto_sha_state_t *hashState, { cy_en_crypto_status_t status; - status = Cy_Crypto_Core_Sha_Update(obj->base, hashState, in, hashState->blockSize); + status = Cy_Crypto_Core_Sha_Update(obj->base, hashState, in, hashState->blockSize); if (CY_CRYPTO_SUCCESS != status) return (-1); diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/crypto_common.h b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/crypto_common.h index d0f678315f1..99d0156e0b5 100644 --- a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/crypto_common.h +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/crypto_common.h @@ -59,7 +59,7 @@ int cy_hw_sha_start (cy_hw_crypto_t *obj, cy_stc_crypto_sha_state_t *hashState, cy_en_crypto_sha_mode_t shaMode, void *shaBuffers); int cy_hw_sha_update(cy_hw_crypto_t *obj, cy_stc_crypto_sha_state_t *hashState, - const uint8_t *in, uint32_t inlen); + const uint8_t *in, uint32_t inlen); int cy_hw_sha_finish(cy_hw_crypto_t *obj, cy_stc_crypto_sha_state_t *hashState, uint8_t *output); diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecdsa_alt.c b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecdsa_alt.c index 563cf739868..b0c6e5974fa 100644 --- a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecdsa_alt.c +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecdsa_alt.c @@ -84,7 +84,7 @@ int mbedtls_ecdsa_sign( mbedtls_ecp_group *grp, mbedtls_mpi *r, mbedtls_mpi *s, int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) { int ret; - size_t bytesize; + size_t bytesize; uint8_t *sig = NULL; uint8_t *tmp_k = NULL; cy_hw_crypto_t crypto_obj; @@ -113,11 +113,11 @@ int mbedtls_ecdsa_sign( mbedtls_ecp_group *grp, mbedtls_mpi *r, mbedtls_mpi *s, /* Reserve the crypto hardware for the operation */ cy_hw_crypto_reserve(&crypto_obj, CYHAL_CRYPTO_VU); - dp = Cy_Crypto_Core_ECC_GetCurveParams(key.curveID); + dp = Cy_Crypto_Core_ECC_GetCurveParams(key.curveID); - bytesize = CY_CRYPTO_BYTE_SIZE_OF_BITS(dp->size); + bytesize = CY_CRYPTO_BYTE_SIZE_OF_BITS(dp->size); - key.k = malloc(bytesize); + key.k = malloc(bytesize); MBEDTLS_MPI_CHK((key.k == NULL) ? MBEDTLS_ERR_ECP_ALLOC_FAILED : 0); MBEDTLS_MPI_CHK( mbedtls_mpi_write_binary( d, key.k, bytesize ) ); @@ -149,12 +149,12 @@ int mbedtls_ecdsa_sign( mbedtls_ecp_group *grp, mbedtls_mpi *r, mbedtls_mpi *s, if (key.k != NULL) { mbedtls_platform_zeroize(key.k, bytesize); - free(key.k); + free(key.k); } if (sig != NULL) { mbedtls_platform_zeroize(sig, 2 * bytesize); - free(sig); + free(sig); } if (tmp_k != NULL) { @@ -176,9 +176,9 @@ int mbedtls_ecdsa_verify( mbedtls_ecp_group *grp, const mbedtls_ecp_point *Q, const mbedtls_mpi *r, const mbedtls_mpi *s) { int ret; - uint8_t stat; + uint8_t stat; size_t bytesize; - size_t olen; + size_t olen; uint8_t *sig = NULL; uint8_t *point_arr = NULL; cy_hw_crypto_t crypto_obj; @@ -202,9 +202,9 @@ int mbedtls_ecdsa_verify( mbedtls_ecp_group *grp, /* Reserve the crypto hardware for the operation */ cy_hw_crypto_reserve(&crypto_obj, CYHAL_CRYPTO_VU); - dp = Cy_Crypto_Core_ECC_GetCurveParams(key.curveID); + dp = Cy_Crypto_Core_ECC_GetCurveParams(key.curveID); - bytesize = CY_CRYPTO_BYTE_SIZE_OF_BITS(dp->size); + bytesize = CY_CRYPTO_BYTE_SIZE_OF_BITS(dp->size); point_arr = malloc(2 * bytesize + 1u); MBEDTLS_MPI_CHK((point_arr == NULL) ? MBEDTLS_ERR_ECP_ALLOC_FAILED : 0); @@ -237,12 +237,12 @@ int mbedtls_ecdsa_verify( mbedtls_ecp_group *grp, if (point_arr != NULL) { mbedtls_platform_zeroize(point_arr, 2 * bytesize + 1u); - free(point_arr); + free(point_arr); } if (sig != NULL) { mbedtls_platform_zeroize(sig, 2 * bytesize); - free(sig); + free(sig); } return( ret ); diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecp_alt.c b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecp_alt.c index 37646e5ba74..bb826f2ee02 100644 --- a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecp_alt.c +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecp_alt.c @@ -1835,10 +1835,10 @@ static int ecp_mul_comb( mbedtls_ecp_group *grp, mbedtls_ecp_point *R, MBEDTLS_MPI_CHK( mbedtls_mpi_grow(&R->Y, data_size) ); Cy_Crypto_Core_EC_NistP_PointMultiplication (crypto_obj.base, - curveId, - (uint8_t *)Pi.X.p, (uint8_t *)Pi.Y.p, - (uint8_t *)di.p, - (uint8_t *)R->X.p, (uint8_t *)R->Y.p); + curveId, + (uint8_t *)Pi.X.p, (uint8_t *)Pi.Y.p, + (uint8_t *)di.p, + (uint8_t *)R->X.p, (uint8_t *)R->Y.p); /* R.Z coordinate should be 1 */ MBEDTLS_MPI_CHK( mbedtls_mpi_lset( &R->Z, 1 ) ); From eb1a5e6b1157d12ca6eb4950e1c350d71978e429 Mon Sep 17 00:00:00 2001 From: Kostiantyn Tkachov Date: Mon, 2 Sep 2019 22:17:25 +0300 Subject: [PATCH 040/227] Changed order of config file checking in include defines --- .../TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_01/sha1_alt.h | 6 +++--- .../TARGET_PSOC6/TARGET_PSOC6_01/sha256_alt.h | 6 +++--- .../TARGET_PSOC6/TARGET_PSOC6_01/sha512_alt.h | 6 +++--- .../TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_02/sha1_alt.h | 6 +++--- .../TARGET_PSOC6/TARGET_PSOC6_02/sha256_alt.h | 6 +++--- .../TARGET_PSOC6/TARGET_PSOC6_02/sha512_alt.h | 6 +++--- .../mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/aes_alt.c | 1 - .../targets/TARGET_Cypress/TARGET_PSOC6/crypto_common.h | 6 +++--- .../mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecdsa_alt.c | 6 +++--- .../mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecp_alt.c | 6 +++--- .../targets/TARGET_Cypress/TARGET_PSOC6/ecp_curves_alt.c | 6 +++--- .../mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha1_alt.c | 6 +++--- .../targets/TARGET_Cypress/TARGET_PSOC6/sha256_alt.c | 6 +++--- .../targets/TARGET_Cypress/TARGET_PSOC6/sha512_alt.c | 6 +++--- 14 files changed, 39 insertions(+), 40 deletions(-) diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_01/sha1_alt.h b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_01/sha1_alt.h index d90e68ed5d4..cd86f93fb26 100644 --- a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_01/sha1_alt.h +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_01/sha1_alt.h @@ -28,10 +28,10 @@ #if !defined(SHA1_ALT_H) #define SHA1_ALT_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "config.h" -#else +#if defined(MBEDTLS_CONFIG_FILE) #include MBEDTLS_CONFIG_FILE +#else +#include "config.h" #endif #include "crypto_common.h" diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_01/sha256_alt.h b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_01/sha256_alt.h index 57a5aaa3e57..431ebae15c2 100644 --- a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_01/sha256_alt.h +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_01/sha256_alt.h @@ -29,10 +29,10 @@ #if !defined(SHA256_ALT_H) #define SHA256_ALT_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "config.h" -#else +#if defined(MBEDTLS_CONFIG_FILE) #include MBEDTLS_CONFIG_FILE +#else +#include "config.h" #endif #include "crypto_common.h" diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_01/sha512_alt.h b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_01/sha512_alt.h index 0f98be83f2b..bfe9a1cb993 100644 --- a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_01/sha512_alt.h +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_01/sha512_alt.h @@ -28,10 +28,10 @@ #if !defined(SHA512_ALT_H) #define SHA512_ALT_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "config.h" -#else +#if defined(MBEDTLS_CONFIG_FILE) #include MBEDTLS_CONFIG_FILE +#else +#include "config.h" #endif #include "crypto_common.h" diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_02/sha1_alt.h b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_02/sha1_alt.h index 974654d7615..d19f099bf85 100644 --- a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_02/sha1_alt.h +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_02/sha1_alt.h @@ -28,10 +28,10 @@ #if !defined(SHA1_ALT_H) #define SHA1_ALT_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "config.h" -#else +#if defined(MBEDTLS_CONFIG_FILE) #include MBEDTLS_CONFIG_FILE +#else +#include "config.h" #endif #include "crypto_common.h" diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_02/sha256_alt.h b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_02/sha256_alt.h index 9d258529160..91981605874 100644 --- a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_02/sha256_alt.h +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_02/sha256_alt.h @@ -29,10 +29,10 @@ #if !defined(SHA256_ALT_H) #define SHA256_ALT_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "config.h" -#else +#if defined(MBEDTLS_CONFIG_FILE) #include MBEDTLS_CONFIG_FILE +#else +#include "config.h" #endif #include "crypto_common.h" diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_02/sha512_alt.h b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_02/sha512_alt.h index f1e0fba5ace..7eb6696fe85 100644 --- a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_02/sha512_alt.h +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_02/sha512_alt.h @@ -28,10 +28,10 @@ #if !defined(SHA512_ALT_H) #define SHA512_ALT_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "config.h" -#else +#if defined(MBEDTLS_CONFIG_FILE) #include MBEDTLS_CONFIG_FILE +#else +#include "config.h" #endif #include "crypto_common.h" diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/aes_alt.c b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/aes_alt.c index 745861b1224..d234d22aa0b 100644 --- a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/aes_alt.c +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/aes_alt.c @@ -122,7 +122,6 @@ static int aes_set_keys( mbedtls_aes_context *ctx, const unsigned char *key, if (CY_CRYPTO_SUCCESS != status) { ret = MBEDTLS_ERR_AES_HW_ACCEL_FAILED; - goto exit; } exit: diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/crypto_common.h b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/crypto_common.h index 99d0156e0b5..d11ada79eb2 100644 --- a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/crypto_common.h +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/crypto_common.h @@ -27,10 +27,10 @@ #if !defined(CRYPTO_COMMON_H) #define CRYPTO_COMMON_H -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else +#if defined(MBEDTLS_CONFIG_FILE) #include MBEDTLS_CONFIG_FILE +#else +#include "config.h" #endif #include "mbedtls/ecp.h" diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecdsa_alt.c b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecdsa_alt.c index b0c6e5974fa..e6ffee0082d 100644 --- a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecdsa_alt.c +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecdsa_alt.c @@ -25,10 +25,10 @@ * */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else +#if defined(MBEDTLS_CONFIG_FILE) #include MBEDTLS_CONFIG_FILE +#else +#include "config.h" #endif #if defined(MBEDTLS_ECDSA_C) diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecp_alt.c b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecp_alt.c index bb826f2ee02..811363adb78 100644 --- a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecp_alt.c +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecp_alt.c @@ -43,10 +43,10 @@ * */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else +#if defined(MBEDTLS_CONFIG_FILE) #include MBEDTLS_CONFIG_FILE +#else +#include "config.h" #endif #if defined(MBEDTLS_ECP_C) diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecp_curves_alt.c b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecp_curves_alt.c index 62150ef0e53..a855ca5587a 100644 --- a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecp_curves_alt.c +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecp_curves_alt.c @@ -25,10 +25,10 @@ * */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else +#if defined(MBEDTLS_CONFIG_FILE) #include MBEDTLS_CONFIG_FILE +#else +#include "config.h" #endif #if defined(MBEDTLS_ECP_C) diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha1_alt.c b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha1_alt.c index a8d02543106..7fb5b7404bb 100644 --- a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha1_alt.c +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha1_alt.c @@ -26,10 +26,10 @@ */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else +#if defined(MBEDTLS_CONFIG_FILE) #include MBEDTLS_CONFIG_FILE +#else +#include "config.h" #endif #if defined(MBEDTLS_SHA1_C) diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha256_alt.c b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha256_alt.c index efb8552653f..f3c27ecd7ad 100644 --- a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha256_alt.c +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha256_alt.c @@ -25,10 +25,10 @@ * */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else +#if defined(MBEDTLS_CONFIG_FILE) #include MBEDTLS_CONFIG_FILE +#else +#include "config.h" #endif #if defined(MBEDTLS_SHA256_C) diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha512_alt.c b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha512_alt.c index 5d9cf48a3ca..74de3b9c8ba 100644 --- a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha512_alt.c +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha512_alt.c @@ -25,10 +25,10 @@ * */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else +#if defined(MBEDTLS_CONFIG_FILE) #include MBEDTLS_CONFIG_FILE +#else +#include "config.h" #endif #if defined(MBEDTLS_SHA512_C) From 5c3da11e8306ba8ac34d2088bbc185ceb824bd0c Mon Sep 17 00:00:00 2001 From: Kostiantyn Tkachov Date: Wed, 4 Sep 2019 12:28:20 +0300 Subject: [PATCH 041/227] Removed mbedTLS hardware support from FUTURE_SEQUANA targets --- targets/targets.json | 2 ++ 1 file changed, 2 insertions(+) diff --git a/targets/targets.json b/targets/targets.json index a5812022456..fbf927a9131 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -8983,6 +8983,7 @@ "extra_labels_remove": ["PSOC6"], "device_has_remove": ["TRNG", "CRC", "I2CSLAVE", "USBDEVICE", "QSPI", "WATCHDOG"], "macros_add": ["CY8C6347BZI_BLD53"], + "macros_remove": ["MBEDTLS_CONFIG_HW_SUPPORT"], "detect_code": ["6000"], "post_binary_hook": { "function": "PSOC6Code.complete" @@ -9016,6 +9017,7 @@ "extra_labels_remove": ["PSOC6"], "device_has_remove": ["TRNG", "CRC", "I2CSLAVE", "USBDEVICE", "QSPI", "WATCHDOG"], "macros_add": ["CY8C6347BZI_BLD53"], + "macros_remove": ["MBEDTLS_CONFIG_HW_SUPPORT"], "detect_code": ["6000"], "hex_filename": "psoc63_m0_default_1.03.hex", "post_binary_hook": { From d2bd044b4d734ffb409c4d1995737175ce8de3b9 Mon Sep 17 00:00:00 2001 From: Olli-Pekka Puolitaival Date: Fri, 30 Aug 2019 09:14:06 +0300 Subject: [PATCH 042/227] Use very verbose to see more details in case of problem --- tools/test/examples/examples_lib.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/test/examples/examples_lib.py b/tools/test/examples/examples_lib.py index 51002b3c362..df54d9a8e3c 100644 --- a/tools/test/examples/examples_lib.py +++ b/tools/test/examples/examples_lib.py @@ -398,7 +398,7 @@ def compile_repos(config, toolchains, targets, profile, verbose, examples): valid_choices(example['toolchains'], toolchains), example['features']): - build_command = ["mbed-cli", "compile", "-t", toolchain, "-m", target] + (['-v'] if verbose else []) + build_command = ["mbed-cli", "compile", "-t", toolchain, "-m", target] + (['-vv'] if verbose else []) if profile: build_command.append("--profile") build_command.append(profile) From dbca77dcc58735c9045cd18d217ac0e77d9d5e6b Mon Sep 17 00:00:00 2001 From: Hugues Kamba Date: Mon, 2 Sep 2019 15:16:56 +0100 Subject: [PATCH 043/227] Avoid non-trivial copy when initializing lorastack struct Using memset generates a warning about the non-trivial operation. Use member-initializer-list instead to initialise the structs members. --- features/lorawan/lorastack/mac/LoRaMac.cpp | 32 ++-------------------- 1 file changed, 2 insertions(+), 30 deletions(-) diff --git a/features/lorawan/lorastack/mac/LoRaMac.cpp b/features/lorawan/lorastack/mac/LoRaMac.cpp index f7fce18ebc0..580ffacc29c 100644 --- a/features/lorawan/lorastack/mac/LoRaMac.cpp +++ b/features/lorawan/lorastack/mac/LoRaMac.cpp @@ -71,10 +71,12 @@ LoRaMac::LoRaMac() _mac_commands(), _channel_plan(), _lora_crypto(), + _params(), _ev_queue(NULL), _mcps_indication(), _mcps_confirmation(), _mlme_indication(), + _ongoing_tx_msg(), _mlme_confirmation(), _is_nwk_joined(false), _can_cancel_tx(true), @@ -83,39 +85,9 @@ LoRaMac::LoRaMac() _prev_qos_level(LORAWAN_DEFAULT_QOS), _demod_ongoing(false) { - memset(&_params, 0, sizeof(_params)); - _params.keys.dev_eui = NULL; - _params.keys.app_eui = NULL; - _params.keys.app_key = NULL; - - memset(_params.keys.nwk_skey, 0, sizeof(_params.keys.nwk_skey)); - memset(_params.keys.app_skey, 0, sizeof(_params.keys.app_skey)); - memset(&_ongoing_tx_msg, 0, sizeof(_ongoing_tx_msg)); - memset(&_params.sys_params, 0, sizeof(_params.sys_params)); - - _params.dev_nonce = 0; - _params.net_id = 0; - _params.dev_addr = 0; - _params.tx_buffer_len = 0; - _params.rx_buffer_len = 0; - _params.ul_frame_counter = 0; - _params.dl_frame_counter = 0; _params.is_rx_window_enabled = true; - _params.adr_ack_counter = 0; - _params.is_node_ack_requested = false; - _params.is_srv_ack_requested = false; - _params.ul_nb_rep_counter = 0; - _params.timers.mac_init_time = 0; _params.max_ack_timeout_retries = 1; _params.ack_timeout_retry_counter = 1; - _params.is_ack_retry_timeout_expired = false; - _params.timers.tx_toa = 0; - - _params.multicast_channels = NULL; - - - _params.sys_params.adr_on = false; - _params.sys_params.max_duty_cycle = 0; reset_mcps_confirmation(); reset_mlme_confirmation(); From 908241fb48474006187f2650d082b1c45c1a354d Mon Sep 17 00:00:00 2001 From: Hugues Kamba Date: Mon, 2 Sep 2019 15:11:29 +0100 Subject: [PATCH 044/227] Replace wait_ms calls with rtos::ThisThread::sleep_for `wait_ms` is deprecated and its use generates a warning. --- .../framework/targets/UBLOX/AT/UBLOX_AT_CellularContext.cpp | 4 +++- .../framework/targets/UBLOX/AT/UBLOX_AT_CellularNetwork.cpp | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/features/cellular/framework/targets/UBLOX/AT/UBLOX_AT_CellularContext.cpp b/features/cellular/framework/targets/UBLOX/AT/UBLOX_AT_CellularContext.cpp index 04c049e6fea..54d8856c8fb 100644 --- a/features/cellular/framework/targets/UBLOX/AT/UBLOX_AT_CellularContext.cpp +++ b/features/cellular/framework/targets/UBLOX/AT/UBLOX_AT_CellularContext.cpp @@ -19,6 +19,8 @@ #include "APN_db.h" #include "CellularLog.h" +#include "rtos/ThisThread.h" + namespace mbed { UBLOX_AT_CellularContext::UBLOX_AT_CellularContext(ATHandler &at, CellularDevice *device, const char *apn, bool cp_req, bool nonip_req) : @@ -206,7 +208,7 @@ bool UBLOX_AT_CellularContext::activate_profile(const char *apn, if (activated) { //If context is activated, exit while loop and return status break; } - wait_ms(5000); //Wait for 5 seconds and then try again + rtos::ThisThread::sleep_for(5000); //Wait for 5 seconds and then try again } t1.stop(); } diff --git a/features/cellular/framework/targets/UBLOX/AT/UBLOX_AT_CellularNetwork.cpp b/features/cellular/framework/targets/UBLOX/AT/UBLOX_AT_CellularNetwork.cpp index 18ddee7f733..77851dbd374 100644 --- a/features/cellular/framework/targets/UBLOX/AT/UBLOX_AT_CellularNetwork.cpp +++ b/features/cellular/framework/targets/UBLOX/AT/UBLOX_AT_CellularNetwork.cpp @@ -17,6 +17,8 @@ #include "UBLOX_AT_CellularNetwork.h" +#include "rtos/ThisThread.h" + using namespace mbed; UBLOX_AT_CellularNetwork::UBLOX_AT_CellularNetwork(ATHandler &atHandler) : AT_CellularNetwork(atHandler) @@ -93,7 +95,7 @@ nsapi_error_t UBLOX_AT_CellularNetwork::ubx_reboot() } else { //Don't clear err here so that we get some error in case of failure _at.clear_error(); - wait_ms(1000); + rtos::ThisThread::sleep_for(1000); } } t1.stop(); From 7bdc7b6a69b0914956a2025f6d472ffe69cfe038 Mon Sep 17 00:00:00 2001 From: Hugues Kamba Date: Mon, 2 Sep 2019 15:04:58 +0100 Subject: [PATCH 045/227] Remove minor build warnings --- .../COMPONENT_PSA_SRV_IMPL/tfm_impl/attestation_core.c | 2 +- features/cellular/framework/AT/AT_CellularBase.cpp | 2 +- features/cellular/framework/device/CellularContext.cpp | 2 +- .../targets/QUECTEL/BG96/QUECTEL_BG96_CellularStack.cpp | 1 - features/frameworks/mbed-coap/source/sn_coap_protocol.c | 3 +++ features/storage/filesystem/littlefs/LittleFileSystem.cpp | 6 +++--- 6 files changed, 9 insertions(+), 7 deletions(-) diff --git a/components/TARGET_PSA/services/attestation/COMPONENT_PSA_SRV_IMPL/tfm_impl/attestation_core.c b/components/TARGET_PSA/services/attestation/COMPONENT_PSA_SRV_IMPL/tfm_impl/attestation_core.c index 2df119b6b06..1e3ef463d54 100755 --- a/components/TARGET_PSA/services/attestation/COMPONENT_PSA_SRV_IMPL/tfm_impl/attestation_core.c +++ b/components/TARGET_PSA/services/attestation/COMPONENT_PSA_SRV_IMPL/tfm_impl/attestation_core.c @@ -869,7 +869,7 @@ attest_create_token(struct useful_buf_c *challenge, token_err = attest_token_start(&attest_token_ctx, option_flags, /* option_flags */ key_select, /* key_select */ - COSE_ALGORITHM_ES256, /* alg_select */ + alg_select, /* alg_select */ token); if (token_err != ATTEST_TOKEN_ERR_SUCCESS) { diff --git a/features/cellular/framework/AT/AT_CellularBase.cpp b/features/cellular/framework/AT/AT_CellularBase.cpp index f8f77dbc501..498116e7084 100644 --- a/features/cellular/framework/AT/AT_CellularBase.cpp +++ b/features/cellular/framework/AT/AT_CellularBase.cpp @@ -51,6 +51,6 @@ intptr_t AT_CellularBase::get_property(CellularProperty key) if (_property_array) { return _property_array[key]; } else { - return NULL; + return 0; } } diff --git a/features/cellular/framework/device/CellularContext.cpp b/features/cellular/framework/device/CellularContext.cpp index cf2746ecdbe..3d956355d1d 100644 --- a/features/cellular/framework/device/CellularContext.cpp +++ b/features/cellular/framework/device/CellularContext.cpp @@ -64,7 +64,7 @@ CellularContext::CellularContext() : _next(0), _stack(0), _pdp_type(DEFAULT_PDP_ _apn(0), _uname(0), _pwd(0), _dcd_pin(NC), _active_high(false), _cp_netif(0), _retry_array_length(0), _retry_count(0), _device(0), _nw(0), _is_blocking(true), _nonip_req(false), _cp_in_use(false) { - memset(_retry_timeout_array, 0, CELLULAR_RETRY_ARRAY_SIZE); + memset(_retry_timeout_array, 0, sizeof(_retry_timeout_array)); } void CellularContext::cp_data_received() diff --git a/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularStack.cpp b/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularStack.cpp index 2cfef67cd39..c65fd50edd0 100644 --- a/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularStack.cpp +++ b/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularStack.cpp @@ -413,7 +413,6 @@ void QUECTEL_BG96_CellularStack::ip2dot(const SocketAddress &ip, char *dot) { if (ip.get_ip_version() == NSAPI_IPv6) { const uint8_t *bytes = (uint8_t *)ip.get_ip_bytes(); - char *p = dot; for (int i = 0; i < NSAPI_IPv6_BYTES; i += 2) { if (i != 0) { *dot++ = ':'; diff --git a/features/frameworks/mbed-coap/source/sn_coap_protocol.c b/features/frameworks/mbed-coap/source/sn_coap_protocol.c index 9ead5ddb591..6a6f939e19a 100644 --- a/features/frameworks/mbed-coap/source/sn_coap_protocol.c +++ b/features/frameworks/mbed-coap/source/sn_coap_protocol.c @@ -1197,6 +1197,8 @@ void sn_coap_protocol_linked_list_duplication_info_remove(struct coap_s *handle, (void)msg_id; #endif //SN_COAP_DUPLICATION_MAX_MSGS_COUNT } + +#if SN_COAP_DUPLICATION_MAX_MSGS_COUNT static void sn_coap_protocol_duplication_info_free(struct coap_s *handle, coap_duplication_info_s *duplication_info_ptr) { if (duplication_info_ptr) { @@ -1208,6 +1210,7 @@ static void sn_coap_protocol_duplication_info_free(struct coap_s *handle, coap_d handle->sn_coap_protocol_free(duplication_info_ptr); } } +#endif // SN_COAP_DUPLICATION_MAX_MSGS_COUNT #if SN_COAP_BLOCKWISE_ENABLED || SN_COAP_MAX_BLOCKWISE_PAYLOAD_SIZE /**************************************************************************//** diff --git a/features/storage/filesystem/littlefs/LittleFileSystem.cpp b/features/storage/filesystem/littlefs/LittleFileSystem.cpp index 34ee5f60934..fce176f65c0 100644 --- a/features/storage/filesystem/littlefs/LittleFileSystem.cpp +++ b/features/storage/filesystem/littlefs/LittleFileSystem.cpp @@ -145,13 +145,13 @@ LittleFileSystem::LittleFileSystem(const char *name, BlockDevice *bd, lfs_size_t read_size, lfs_size_t prog_size, lfs_size_t block_size, lfs_size_t lookahead) : FileSystem(name) + , _lfs() + , _config() + , _bd(NULL) , _read_size(read_size) , _prog_size(prog_size) , _block_size(block_size) , _lookahead(lookahead) - , _lfs() - , _config() - , _bd(NULL) { if (bd) { mount(bd); From 95996200d7b16e25d83404413d7017aaa550e55c Mon Sep 17 00:00:00 2001 From: Hugues Kamba Date: Tue, 3 Sep 2019 09:15:22 +0100 Subject: [PATCH 046/227] Use PRIu32 to print uint32_t variable As the variable underlying type size is different depending on the toolchain used --- features/cellular/framework/AT/ATHandler.cpp | 2 +- features/frameworks/TARGET_PSA/val_greentea.cpp | 2 +- platform/source/mbed_error.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/features/cellular/framework/AT/ATHandler.cpp b/features/cellular/framework/AT/ATHandler.cpp index 88334167edc..40d7f3ce62f 100644 --- a/features/cellular/framework/AT/ATHandler.cpp +++ b/features/cellular/framework/AT/ATHandler.cpp @@ -1394,7 +1394,7 @@ void ATHandler::write_int(int32_t param) // write the integer subparameter const int32_t str_len = 12; char number_string[str_len]; - int32_t result = sprintf(number_string, "%ld", param); + int32_t result = sprintf(number_string, "%" PRIi32, param); if (result > 0 && result < str_len) { (void)write(number_string, strlen(number_string)); } diff --git a/features/frameworks/TARGET_PSA/val_greentea.cpp b/features/frameworks/TARGET_PSA/val_greentea.cpp index 6498c9b6ee7..6f71db388f9 100644 --- a/features/frameworks/TARGET_PSA/val_greentea.cpp +++ b/features/frameworks/TARGET_PSA/val_greentea.cpp @@ -67,7 +67,7 @@ val_status_t mbed_val_execute_non_secure_tests(uint32_t test_num, client_test_t while (tests_list[i] != NULL) { memset(testcase_name, 0, 100); - sprintf(testcase_name, "Check%d", i); + sprintf(testcase_name, "Check%" PRIu32, i); GREENTEA_TESTCASE_START(testcase_name); if (server_hs == TRUE) { diff --git a/platform/source/mbed_error.c b/platform/source/mbed_error.c index 8e9b81c6de1..c00c86a5506 100644 --- a/platform/source/mbed_error.c +++ b/platform/source/mbed_error.c @@ -305,7 +305,7 @@ WEAK MBED_NORETURN mbed_error_status_t mbed_error(mbed_error_status_t error_stat mbed_error_printf("\n= System will be rebooted due to a fatal error =\n"); if (report_error_ctx->error_reboot_count >= MBED_CONF_PLATFORM_ERROR_REBOOT_MAX) { //We have rebooted more than enough, hold the system here. - mbed_error_printf("= Reboot count(=%ld) reached maximum, system will halt after rebooting =\n", report_error_ctx->error_reboot_count); + mbed_error_printf("= Reboot count(=%" PRIi32") reached maximum, system will halt after rebooting =\n", report_error_ctx->error_reboot_count); } #endif system_reset();//do a system reset to get the system rebooted From 900787ca968c6698ea9acd979ed32defdd48459a Mon Sep 17 00:00:00 2001 From: Hugues Kamba Date: Tue, 3 Sep 2019 09:29:56 +0100 Subject: [PATCH 047/227] Remove extraneous parentheses. --- drivers/source/usb/USBDevice.cpp | 2 +- features/nfc/stack/transceiver/pn512/pn512_poll.c | 5 ++++- features/nfc/stack/transceiver/pn512/pn512_rf.c | 5 ++++- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/source/usb/USBDevice.cpp b/drivers/source/usb/USBDevice.cpp index 3ee73c8ba7e..b8cc8dc607e 100644 --- a/drivers/source/usb/USBDevice.cpp +++ b/drivers/source/usb/USBDevice.cpp @@ -616,7 +616,7 @@ bool USBDevice::_request_setup() bool success = false; /* Process standard requests */ - if ((_transfer.setup.bmRequestType.Type == STANDARD_TYPE)) { + if (_transfer.setup.bmRequestType.Type == STANDARD_TYPE) { switch (_transfer.setup.bRequest) { case GET_STATUS: success = _request_get_status(); diff --git a/features/nfc/stack/transceiver/pn512/pn512_poll.c b/features/nfc/stack/transceiver/pn512/pn512_poll.c index 1e6245d05d8..ad349c5a4e4 100644 --- a/features/nfc/stack/transceiver/pn512/pn512_poll.c +++ b/features/nfc/stack/transceiver/pn512/pn512_poll.c @@ -537,7 +537,10 @@ void pn512_initiator_isob_anticollision_reqb(pn512_t *pPN512) ac_buffer_builder_write_nu8(pDataOutBldr, REQB); ac_buffer_builder_write_nu8(pDataOutBldr, 0x00); // AFI: All card types should respond uint8_t wup = 0; - if ((pPN512->anticollision.iso_b.slots_num_exponent == 0)) { //&& (pPN512->anticollision.iso_b.slot_number == 0)) + if ( + pPN512->anticollision.iso_b.slots_num_exponent == 0 + //&& (pPN512->anticollision.iso_b.slot_number == 0) + ) { wup |= 0x8; // Send Wake-Up command on first iteration } ac_buffer_builder_write_nu8(pDataOutBldr, wup | (pPN512->anticollision.iso_b.slots_num_exponent & 0x7)); // Param: number of slots diff --git a/features/nfc/stack/transceiver/pn512/pn512_rf.c b/features/nfc/stack/transceiver/pn512/pn512_rf.c index f0d076bcdfd..bbee18f0751 100644 --- a/features/nfc/stack/transceiver/pn512/pn512_rf.c +++ b/features/nfc/stack/transceiver/pn512/pn512_rf.c @@ -107,7 +107,10 @@ nfc_err_t pn512_framing_set(pn512_t *pPN512, nfc_framing_t framing) return NFC_ERR_UNSUPPORTED; } #if 1 - if ((pPN512->framing == nfc_framing_initiator_a_106) /*|| (pPN512->framing == pn512_framing_target_iso14443a_106k)*/) { + if ( + pPN512->framing == nfc_framing_initiator_a_106 + //|| (pPN512->framing == pn512_framing_target_iso14443a_106k) + ) { //Enable 100% ASK Modulation pn512_register_write(pPN512, PN512_REG_TXAUTO, pn512_register_read(pPN512, PN512_REG_TXAUTO) | 0x40); } else { From a840987dfabe33ec0047dc0c889bd0185fc42a25 Mon Sep 17 00:00:00 2001 From: Hugues Kamba Date: Tue, 3 Sep 2019 13:47:06 +0100 Subject: [PATCH 048/227] Sync with TF upstream code as much as possible to remove warning --- .../tfm_impl/attestation_core.c | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/components/TARGET_PSA/services/attestation/COMPONENT_PSA_SRV_IMPL/tfm_impl/attestation_core.c b/components/TARGET_PSA/services/attestation/COMPONENT_PSA_SRV_IMPL/tfm_impl/attestation_core.c index 1e3ef463d54..87a5486ce72 100755 --- a/components/TARGET_PSA/services/attestation/COMPONENT_PSA_SRV_IMPL/tfm_impl/attestation_core.c +++ b/components/TARGET_PSA/services/attestation/COMPONENT_PSA_SRV_IMPL/tfm_impl/attestation_core.c @@ -841,7 +841,6 @@ attest_create_token(struct useful_buf_c *challenge, enum attest_token_err_t token_err; struct attest_token_ctx attest_token_ctx; int32_t key_select; - int32_t alg_select; uint32_t option_flags = 0; if (challenge->len == 36) { @@ -855,21 +854,13 @@ attest_create_token(struct useful_buf_c *challenge, /* Lower three bits are the key select */ key_select = option_flags & 0x7; - /* Map the key select to an algorithm. Maybe someday we'll support something - * other than ES256 - */ - switch (key_select) { - default: - alg_select = COSE_ALGORITHM_ES256; - } - /* Get started creating the token. This sets up the CBOR and COSE contexts * which causes the COSE headers to be constructed. */ token_err = attest_token_start(&attest_token_ctx, option_flags, /* option_flags */ key_select, /* key_select */ - alg_select, /* alg_select */ + COSE_ALGORITHM_ES256, /* alg_select */ token); if (token_err != ATTEST_TOKEN_ERR_SUCCESS) { From cc16a2cfd62e948eaf94b03f96fa400f55765a5c Mon Sep 17 00:00:00 2001 From: George Psimenos Date: Mon, 2 Sep 2019 14:56:56 +0100 Subject: [PATCH 049/227] Replace difftime and float literals --- features/cellular/framework/AT/AT_CellularSMS.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/features/cellular/framework/AT/AT_CellularSMS.cpp b/features/cellular/framework/AT/AT_CellularSMS.cpp index d28f981da9d..fe4031c1387 100644 --- a/features/cellular/framework/AT/AT_CellularSMS.cpp +++ b/features/cellular/framework/AT/AT_CellularSMS.cpp @@ -1114,7 +1114,7 @@ int AT_CellularSMS::compare_time_strings(const char *time_string_1, const char * int retVal = -2; if (success) { - double diff = difftime(t1, t2); + time_t diff = t1 - t2; if (diff > 0) { retVal = 1; @@ -1140,7 +1140,7 @@ bool AT_CellularSMS::create_time(const char *time_string, time_t *time) &time_struct.tm_hour, &time_struct.tm_min, &time_struct.tm_sec, &sign, &gmt) == kNumberOfElements) { *time = mktime(&time_struct); // add timezone as seconds. gmt is in quarter of hours. - int x = 60 * 60 * gmt * 0.25; + int x = (60 * 60 * gmt) / 4; if (sign == '+') { *time += x; } else { From 499bc28a3227f900b228c3306e40fb2af78db7ad Mon Sep 17 00:00:00 2001 From: George Psimenos Date: Mon, 2 Sep 2019 15:48:30 +0100 Subject: [PATCH 050/227] Avoid potential overflow --- features/cellular/framework/AT/AT_CellularSMS.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/features/cellular/framework/AT/AT_CellularSMS.cpp b/features/cellular/framework/AT/AT_CellularSMS.cpp index fe4031c1387..c41d7932d50 100644 --- a/features/cellular/framework/AT/AT_CellularSMS.cpp +++ b/features/cellular/framework/AT/AT_CellularSMS.cpp @@ -1140,7 +1140,7 @@ bool AT_CellularSMS::create_time(const char *time_string, time_t *time) &time_struct.tm_hour, &time_struct.tm_min, &time_struct.tm_sec, &sign, &gmt) == kNumberOfElements) { *time = mktime(&time_struct); // add timezone as seconds. gmt is in quarter of hours. - int x = (60 * 60 * gmt) / 4; + int x = (60 / 4) * 60 * gmt; if (sign == '+') { *time += x; } else { From aea8d824cb268f074a7f1e50989f7b588c0f6f4d Mon Sep 17 00:00:00 2001 From: Ari Parkkila Date: Thu, 29 Aug 2019 04:24:07 -0700 Subject: [PATCH 051/227] Cellular: Fix BG96 power on and connect --- .../AT/at_cellulardevice/unittest.cmake | 1 + features/cellular/framework/AT/ATHandler.cpp | 4 +- .../framework/AT/AT_CellularContext.cpp | 2 + .../framework/AT/AT_CellularDevice.cpp | 27 +++- .../framework/AT/AT_CellularNetwork.cpp | 5 +- .../framework/device/CellularDevice.cpp | 3 + .../framework/device/CellularStateMachine.cpp | 1 + .../targets/QUECTEL/BG96/QUECTEL_BG96.cpp | 140 +++++++++--------- .../targets/QUECTEL/BG96/QUECTEL_BG96.h | 7 +- 9 files changed, 100 insertions(+), 90 deletions(-) diff --git a/UNITTESTS/features/cellular/framework/AT/at_cellulardevice/unittest.cmake b/UNITTESTS/features/cellular/framework/AT/at_cellulardevice/unittest.cmake index f7ead9eaf2e..ac50a142f62 100644 --- a/UNITTESTS/features/cellular/framework/AT/at_cellulardevice/unittest.cmake +++ b/UNITTESTS/features/cellular/framework/AT/at_cellulardevice/unittest.cmake @@ -43,6 +43,7 @@ set(unittest-test-sources stubs/SerialBase_stub.cpp stubs/CellularStateMachine_stub.cpp stubs/CellularContext_stub.cpp + stubs/ThisThread_stub.cpp stubs/ConditionVariable_stub.cpp stubs/Mutex_stub.cpp ) diff --git a/features/cellular/framework/AT/ATHandler.cpp b/features/cellular/framework/AT/ATHandler.cpp index 40d7f3ce62f..1fab9d5e22e 100644 --- a/features/cellular/framework/AT/ATHandler.cpp +++ b/features/cellular/framework/AT/ATHandler.cpp @@ -926,7 +926,7 @@ void ATHandler::set_3gpp_error(int err, DeviceErrorType error_type) for (size_t i = 0; i < sizeof(map_3gpp_errors) / sizeof(map_3gpp_errors[0]); i++) { if (map_3gpp_errors[i][0] == err) { _last_3gpp_error = map_3gpp_errors[i][1]; - tr_debug("AT3GPP error code %d", get_3gpp_error()); + tr_error("AT3GPP error code %d", get_3gpp_error()); break; } } @@ -943,7 +943,7 @@ void ATHandler::at_error(bool error_code_expected, DeviceErrorType error_type) set_3gpp_error(err, error_type); _last_at_err.errCode = err; _last_at_err.errType = error_type; - tr_error("AT error code %ld", err); + tr_warn("AT error code %ld", err); } else { tr_warn("ATHandler ERROR reading failed"); } diff --git a/features/cellular/framework/AT/AT_CellularContext.cpp b/features/cellular/framework/AT/AT_CellularContext.cpp index c1fbbc3b8d5..7bfd6e666f6 100644 --- a/features/cellular/framework/AT/AT_CellularContext.cpp +++ b/features/cellular/framework/AT/AT_CellularContext.cpp @@ -608,6 +608,7 @@ nsapi_error_t AT_CellularContext::open_data_channel() connected, or timeout after 30 seconds*/ nsapi_error_t err = nsapi_ppp_connect(_at.get_file_handle(), callback(this, &AT_CellularContext::ppp_status_cb), _uname, _pwd, (nsapi_ip_stack_t)_pdp_type); if (err) { + tr_error("nsapi_ppp_connect failed"); ppp_disconnected(); } @@ -993,6 +994,7 @@ void AT_CellularContext::cellular_callback(nsapi_event_t ev, intptr_t ptr) tr_info("cellular_callback: PPP mode and NSAPI_STATUS_DISCONNECTED"); _cb_data.error = NSAPI_ERROR_NO_CONNECTION; _is_connected = false; + ppp_disconnected(); } } #else diff --git a/features/cellular/framework/AT/AT_CellularDevice.cpp b/features/cellular/framework/AT/AT_CellularDevice.cpp index 33a0d131d7b..8835d76a1ea 100644 --- a/features/cellular/framework/AT/AT_CellularDevice.cpp +++ b/features/cellular/framework/AT/AT_CellularDevice.cpp @@ -15,6 +15,7 @@ * limitations under the License. */ +#include "rtos/ThisThread.h" #include "CellularUtil.h" #include "AT_CellularDevice.h" #include "AT_CellularInformation.h" @@ -202,6 +203,7 @@ nsapi_error_t AT_CellularDevice::get_sim_state(SimState &state) _at->flush(); nsapi_error_t error = _at->at_cmd_str("+CPIN", "?", simstr, sizeof(simstr)); ssize_t len = strlen(simstr); + device_err_t err = _at->get_last_device_error(); _at->unlock(); if (len != -1) { @@ -213,7 +215,6 @@ nsapi_error_t AT_CellularDevice::get_sim_state(SimState &state) state = SimStatePukNeeded; } else { simstr[len] = '\0'; - tr_error("Unknown SIM state %s", simstr); state = SimStateUnknown; } } else { @@ -229,7 +230,11 @@ nsapi_error_t AT_CellularDevice::get_sim_state(SimState &state) tr_error("SIM PUK required"); break; case SimStateUnknown: - tr_warn("SIM state unknown"); + if (err.errType == DeviceErrorTypeErrorCME && err.errCode == 14) { + tr_info("SIM busy"); + } else { + tr_warn("SIM state unknown"); + } break; default: tr_info("SIM is ready"); @@ -443,12 +448,18 @@ nsapi_error_t AT_CellularDevice::init() setup_at_handler(); _at->lock(); - _at->flush(); - _at->at_cmd_discard("E0", ""); - - _at->at_cmd_discard("+CMEE", "=1"); - - _at->at_cmd_discard("+CFUN", "=1"); + for (int retry = 1; retry <= 3; retry++) { + _at->clear_error(); + _at->flush(); + _at->at_cmd_discard("E0", ""); + _at->at_cmd_discard("+CMEE", "=1"); + _at->at_cmd_discard("+CFUN", "=1"); + if (_at->get_last_error() == NSAPI_ERROR_OK) { + break; + } + tr_debug("Wait 100ms to init modem"); + rtos::ThisThread::sleep_for(100); // let modem have time to get ready + } return _at->unlock_return_error(); } diff --git a/features/cellular/framework/AT/AT_CellularNetwork.cpp b/features/cellular/framework/AT/AT_CellularNetwork.cpp index 0fb1c5b499f..5d3b4f70200 100644 --- a/features/cellular/framework/AT/AT_CellularNetwork.cpp +++ b/features/cellular/framework/AT/AT_CellularNetwork.cpp @@ -211,8 +211,9 @@ nsapi_error_t AT_CellularNetwork::set_registration(const char *plmn) if (!plmn) { tr_debug("Automatic network registration"); NWRegisteringMode mode; - get_network_registering_mode(mode); - + if (get_network_registering_mode(mode) != NSAPI_ERROR_OK) { + return NSAPI_ERROR_DEVICE_ERROR; + } if (mode != NWModeAutomatic) { return _at.at_cmd_discard("+COPS", "=0"); } diff --git a/features/cellular/framework/device/CellularDevice.cpp b/features/cellular/framework/device/CellularDevice.cpp index 51152459967..aea7437b094 100644 --- a/features/cellular/framework/device/CellularDevice.cpp +++ b/features/cellular/framework/device/CellularDevice.cpp @@ -234,6 +234,9 @@ nsapi_error_t CellularDevice::shutdown() } CellularContext *curr = get_context_list(); while (curr) { + if (curr->is_connected()) { + curr->disconnect(); + } curr->cellular_callback(NSAPI_EVENT_CONNECTION_STATUS_CHANGE, NSAPI_STATUS_DISCONNECTED); curr = (CellularContext *)curr->_next; } diff --git a/features/cellular/framework/device/CellularStateMachine.cpp b/features/cellular/framework/device/CellularStateMachine.cpp index 9609f0ad1cb..ca1c09b18a8 100644 --- a/features/cellular/framework/device/CellularStateMachine.cpp +++ b/features/cellular/framework/device/CellularStateMachine.cpp @@ -373,6 +373,7 @@ void CellularStateMachine::state_device_ready() } } else { _status = 0; + _is_retry = true; enter_to_state(STATE_INIT); } } diff --git a/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96.cpp b/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96.cpp index 083bafa4a1b..6136863526b 100644 --- a/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96.cpp +++ b/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96.cpp @@ -97,92 +97,35 @@ void QUECTEL_BG96::set_ready_cb(Callback callback) _at->set_urc_handler(DEVICE_READY_URC, callback); } -nsapi_error_t QUECTEL_BG96::hard_power_on() -{ - if (_pwr.is_connected()) { - tr_info("Modem power on"); - ThisThread::sleep_for(250); - _pwr = !_active_high; - ThisThread::sleep_for(250); // BG96_Hardware_Design_V1.1 says 100 ms, but 250 ms seems to be more robust - _pwr = _active_high; - ThisThread::sleep_for(500); - } - - return NSAPI_ERROR_OK; -} - nsapi_error_t QUECTEL_BG96::soft_power_on() -{ - if (!_rst.is_connected()) { - return NSAPI_ERROR_OK; - } - - tr_info("Reset modem"); - _rst = !_active_high; - ThisThread::sleep_for(100); - _rst = _active_high; - ThisThread::sleep_for(150 + 460); // RESET_N timeout from BG96_Hardware_Design_V1.1 - _rst = !_active_high; - ThisThread::sleep_for(500); - - // wait for RDY - _at->lock(); - _at->set_at_timeout(10 * 1000); - _at->resp_start(); - _at->set_stop_tag("RDY"); - bool rdy = _at->consume_to_stop_tag(); - _at->set_stop_tag(OK); - _at->restore_at_timeout(); - - if (!rdy) { - // check if modem was silently powered on - _at->clear_error(); - _at->set_at_timeout(100); - _at->at_cmd_discard("", ""); //Send AT - _at->restore_at_timeout(); - } - return _at->unlock_return_error(); -} - -nsapi_error_t QUECTEL_BG96::hard_power_off() { if (_pwr.is_connected()) { - tr_info("Modem power off"); - _pwr = _active_high; - ThisThread::sleep_for(650); // from BG96_Hardware_Design_V1.1 - _pwr = !_active_high; + tr_info("QUECTEL_BG96::soft_power_on"); + // check if modem was powered on already + if (wake_up()) { + return NSAPI_ERROR_OK; + } + if (!wake_up(true)) { + tr_error("Modem not responding"); + soft_power_off(); + return NSAPI_ERROR_DEVICE_ERROR; + } } return NSAPI_ERROR_OK; } -nsapi_error_t QUECTEL_BG96::init() +nsapi_error_t QUECTEL_BG96::soft_power_off() { - setup_at_handler(); - - int retry = 0; - _at->lock(); - _at->flush(); - _at->at_cmd_discard("E0", ""); // echo off - - _at->at_cmd_discard("+CMEE", "=1"); // verbose responses - + _at->cmd_start("AT+QPOWD"); + _at->cmd_stop_read_resp(); if (_at->get_last_error() != NSAPI_ERROR_OK) { - return _at->unlock_return_error(); - } - - do { - _at->clear_error(); - _at->at_cmd_discard("+CFUN", "=1"); // set full functionality - if (_at->get_last_error() == NSAPI_ERROR_OK) { - break; + tr_warn("Force modem off"); + if (_pwr.is_connected()) { + press_button(_pwr, 650); // BG96_Hardware_Design_V1.1: Power off signal at least 650 ms } - // wait some time that modem gets ready for CFUN command, and try again - retry++; - ThisThread::sleep_for(64); // experimental value - } while (retry < 3); - + } return _at->unlock_return_error(); } @@ -215,3 +158,52 @@ void QUECTEL_BG96::urc_pdpdeact() } send_disconnect_to_context(cid); } + +void QUECTEL_BG96::press_button(DigitalOut &button, uint32_t timeout) +{ + if (!button.is_connected()) { + return; + } + button = _active_high; + ThisThread::sleep_for(timeout); + button = !_active_high; +} + +bool QUECTEL_BG96::wake_up(bool reset) +{ + // check if modem is already ready + _at->lock(); + _at->flush(); + _at->set_at_timeout(30); + _at->cmd_start("AT"); + _at->cmd_stop_read_resp(); + nsapi_error_t err = _at->get_last_error(); + _at->restore_at_timeout(); + _at->unlock(); + // modem is not responding, power it on + if (err != NSAPI_ERROR_OK) { + if (!reset) { + // BG96_Hardware_Design_V1.1 requires VBAT to be stable over 30 ms, that's handled above + tr_info("Power on modem"); + press_button(_pwr, 250); // BG96_Hardware_Design_V1.1 requires time 100 ms, but 250 ms seems to be more robust + } else { + tr_warn("Reset modem"); + press_button(_rst, 150); // BG96_Hardware_Design_V1.1 requires RESET_N timeout at least 150 ms + } + _at->lock(); + // According to BG96_Hardware_Design_V1.1 USB is active after 4.2s, but it seems to take over 5s + _at->set_at_timeout(6000); + _at->resp_start(); + _at->set_stop_tag("RDY"); + bool rdy = _at->consume_to_stop_tag(); + _at->set_stop_tag(OK); + _at->restore_at_timeout(); + _at->unlock(); + if (!rdy) { + return false; + } + } + + // sync to check that AT is really responsive and to clear garbage + return _at->sync(500); +} diff --git a/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96.h b/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96.h index 60a02cea4bb..592ca3e8c74 100644 --- a/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96.h +++ b/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96.h @@ -41,17 +41,16 @@ class QUECTEL_BG96 : public AT_CellularDevice { virtual AT_CellularContext *create_context_impl(ATHandler &at, const char *apn, bool cp_req = false, bool nonip_req = false); virtual AT_CellularInformation *open_information_impl(ATHandler &at); virtual void set_ready_cb(Callback callback); - virtual nsapi_error_t hard_power_on(); - virtual nsapi_error_t hard_power_off(); virtual nsapi_error_t soft_power_on(); - virtual nsapi_error_t init(); + virtual nsapi_error_t soft_power_off(); virtual void set_at_urcs_impl(); public: void handle_urc(FileHandle *fh); private: - nsapi_error_t press_power_button(uint32_t timeout); + void press_button(DigitalOut &button, uint32_t timeout); + bool wake_up(bool reset = false); bool _active_high; DigitalOut _pwr; DigitalOut _rst; From 0d6fc4608639b57faa26ea0e516b85df6d942e75 Mon Sep 17 00:00:00 2001 From: Ron Eldor Date: Mon, 8 Jul 2019 18:43:39 +0300 Subject: [PATCH 052/227] Explaining how to opt in modules Add a section in the CC Readme file explaining how to enable the optional module. --- features/cryptocell/FEATURE_CRYPTOCELL310/Readme.md | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/features/cryptocell/FEATURE_CRYPTOCELL310/Readme.md b/features/cryptocell/FEATURE_CRYPTOCELL310/Readme.md index 6d584899c2c..39122de702c 100644 --- a/features/cryptocell/FEATURE_CRYPTOCELL310/Readme.md +++ b/features/cryptocell/FEATURE_CRYPTOCELL310/Readme.md @@ -25,4 +25,14 @@ To port your CC 310 driver to Mbed OS on your specific target, do the following: 1. Add your CC setup code: * Implement `crypto_platform_setup()` and `crypto_platform_terminate()` to enable CC on your platform, in case you have board-specific setup functionality, required for CC setup. You MUST call 'SaSi_LibInit()` and 'SaSi_LibFini()' respectively in these functions. * Define `crypto_platform_ctx` in `crypto_device_platform.h` in a way that suits your implementation. - + +## Enabling optional alternative drivers + +There are three additional modules that have alternative implementation support, which are not enabled by default. +The reason is to allow backwards compatability, as these modules don't have full functionality, and return `MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED` for some features. +The modules are: +* `AES` which only supports 128 bit key size, in opposed to previous suipport for all key sizes. +* `CMAC` which only supports AES 128 bit key size, in opposed to previous supporting DES and all key sizes. +* `SHA512` which only supports SHA512, in opposed to previously supporting SHA384 as well. + +In order to enable these modules, you should define `MBEDTLS_AES_ALT`, `MBEDTLS_CMAC_ALT` and `MBEDTLS_SHA512_ALT` respectively, either in `mbed_app.json` or in your `MBEDTLS_USER_CONFIG_FILE` to have hardware accelerated module with reduced RAM size, on the expense of full functionality. From a9cc06536a3f69395acfa24364a902be954ecf13 Mon Sep 17 00:00:00 2001 From: Ron Eldor Date: Tue, 9 Jul 2019 11:42:37 +0300 Subject: [PATCH 053/227] Fix typo suipport -> support --- features/cryptocell/FEATURE_CRYPTOCELL310/Readme.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/features/cryptocell/FEATURE_CRYPTOCELL310/Readme.md b/features/cryptocell/FEATURE_CRYPTOCELL310/Readme.md index 39122de702c..a91c95ec3c9 100644 --- a/features/cryptocell/FEATURE_CRYPTOCELL310/Readme.md +++ b/features/cryptocell/FEATURE_CRYPTOCELL310/Readme.md @@ -31,7 +31,7 @@ To port your CC 310 driver to Mbed OS on your specific target, do the following: There are three additional modules that have alternative implementation support, which are not enabled by default. The reason is to allow backwards compatability, as these modules don't have full functionality, and return `MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED` for some features. The modules are: -* `AES` which only supports 128 bit key size, in opposed to previous suipport for all key sizes. +* `AES` which only supports 128 bit key size, in opposed to previous support for all key sizes. * `CMAC` which only supports AES 128 bit key size, in opposed to previous supporting DES and all key sizes. * `SHA512` which only supports SHA512, in opposed to previously supporting SHA384 as well. From c505987b079afc3993e140cfe6b5760942679502 Mon Sep 17 00:00:00 2001 From: Amanda Butler Date: Tue, 16 Jul 2019 09:46:10 -0500 Subject: [PATCH 054/227] Edit Readme.md Edit file, mostly for active voice, formatting and parallel construction. --- .../FEATURE_CRYPTOCELL310/Readme.md | 29 +++++++++---------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/features/cryptocell/FEATURE_CRYPTOCELL310/Readme.md b/features/cryptocell/FEATURE_CRYPTOCELL310/Readme.md index a91c95ec3c9..f8145b5a35e 100644 --- a/features/cryptocell/FEATURE_CRYPTOCELL310/Readme.md +++ b/features/cryptocell/FEATURE_CRYPTOCELL310/Readme.md @@ -1,38 +1,37 @@ # Guidelines for porting Cryptocell to Mbed OS -Cryptocell (CC) 310 is a hardware accelerator that can be ported to several boards, assuming these boards have CC 310 embedded in their hardware. +Cryptocell (CC) 310 is a hardware accelerator you can port to boards that have CC 310 embedded in their hardware. The CC 310 driver consists of three libraries: -* A common core library(`libcc_core.a`). -* A platform-specific TRNG library, containing TRNG-related information, for sampling sufficient entropy on the specific platform(`libcc_trng.a`). -* A platform-specific library containing extra information, such as the CC register's base addresses on the specific board. (`libcc_ext.a`) +* A common core library (`libcc_core.a`). +* A platform-specific TRNG library containing TRNG-related information for sampling sufficient entropy on the specific platform (`libcc_trng.a`). +* A platform-specific library containing extra information, such as the CC register's base addresses on the specific board (`libcc_ext.a`). Library version information: -* The CC 310 libraries were built from version `arm_sw-cc310-1.1.0.1285` +* The CC 310 libraries were built from version `arm_sw-cc310-1.1.0.1285`. * The `IAR` libraries were built using `IAR ANSI C/C++ Compiler V7.80.1.11864/W32 for ARM` with `--cpu Cortex-M4f`. * The `ARM` libraries were built using `ARM Compiler 5.06 update 4 (build 422)` with `--cpu cortex-m4`. * The `GCC_ARM` libraries were built using `arm-none-eabi-gcc 6.3.1 20170620 (release)` with `-mcpu=cortex-m4`. -To port your CC 310 driver to Mbed OS on your specific target, do the following: +To port your CC 310 driver to Mbed OS on your specific target: -1. In `targets.json` add the following to your target: +1. In `targets.json`, add the following to your target: * `MBEDTLS_CONFIG_HW_SUPPORT` to `macros_add` key. This instructs Mbed TLS to look for an alternative cryptographic implementation. * `CRYPTOCELL310` to `feature`. Use this in your common code that you need to remove from compilation in case CC exists in your board. Use `#if !defined(FEATURE_CRYPTOCELL310)` and `#if defined(FEATURE_CRYPTOCELL310)`. 1. In `objects.h`, include `objects_cryptocell.h`. You can use the `FEATURE_CRYPTOCELL310` precompilation check as defined above. 1. In `features/cryptocell/FEATURE_CRYPTOCELL310/TARGET_`, add your platform-specific libraries for all toolchains in `TOOLCHAIN_ARM`, `TOOLCHAIN_GCC_ARM` and `TOOLCHAIN_IAR` respectively. 1. Add your CC setup code: - * Implement `crypto_platform_setup()` and `crypto_platform_terminate()` to enable CC on your platform, in case you have board-specific setup functionality, required for CC setup. You MUST call 'SaSi_LibInit()` and 'SaSi_LibFini()' respectively in these functions. + * Implement `crypto_platform_setup()` and `crypto_platform_terminate()` to enable CC on your platform, in case you have board-specific setup functionality, required for CC setup. You MUST call `SaSi_LibInit()` and `SaSi_LibFini()` in these functions. * Define `crypto_platform_ctx` in `crypto_device_platform.h` in a way that suits your implementation. ## Enabling optional alternative drivers -There are three additional modules that have alternative implementation support, which are not enabled by default. -The reason is to allow backwards compatability, as these modules don't have full functionality, and return `MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED` for some features. -The modules are: -* `AES` which only supports 128 bit key size, in opposed to previous support for all key sizes. -* `CMAC` which only supports AES 128 bit key size, in opposed to previous supporting DES and all key sizes. -* `SHA512` which only supports SHA512, in opposed to previously supporting SHA384 as well. +Three additional modules that are not enabled by default have alternative implementation support. This allows backward compatability because these modules don't have full functionality and returns `MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED` for some features. The modules are: -In order to enable these modules, you should define `MBEDTLS_AES_ALT`, `MBEDTLS_CMAC_ALT` and `MBEDTLS_SHA512_ALT` respectively, either in `mbed_app.json` or in your `MBEDTLS_USER_CONFIG_FILE` to have hardware accelerated module with reduced RAM size, on the expense of full functionality. +* `AES`, which only supports 128 bit key size, as opposed to previous support for all key sizes. +* `CMAC`, which only supports AES 128 bit key size, as opposed to previous support for DES and all key sizes. +* `SHA512`, which only supports SHA512, as opposed to previous support for SHA384, as well. + +To enable these modules, define `MBEDTLS_AES_ALT`, `MBEDTLS_CMAC_ALT` and `MBEDTLS_SHA512_ALT`, either in `mbed_app.json` or in your `MBEDTLS_USER_CONFIG_FILE`, to have hardware accelerated module with reduced RAM size, on the expense of full functionality. From 392ecdbb5ba28edda46f885ed76a898625249bb4 Mon Sep 17 00:00:00 2001 From: Dominika Maziec Date: Thu, 5 Sep 2019 16:28:47 +0200 Subject: [PATCH 055/227] ESP8266Interface buffer null-terminated and parameters of scan function in correct order --- components/wifi/esp8266-driver/ESP8266Interface.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/components/wifi/esp8266-driver/ESP8266Interface.cpp b/components/wifi/esp8266-driver/ESP8266Interface.cpp index 308de3c9798..31deee4678b 100644 --- a/components/wifi/esp8266-driver/ESP8266Interface.cpp +++ b/components/wifi/esp8266-driver/ESP8266Interface.cpp @@ -319,7 +319,7 @@ int ESP8266Interface::set_credentials(const char *ssid, const char *pass, nsapi_ if (ssid_length > 0 && ssid_length <= ESP8266_SSID_MAX_LENGTH) { memset(ap_ssid, 0, sizeof(ap_ssid)); - strncpy(ap_ssid, ssid, sizeof(ap_ssid)); + strncpy(ap_ssid, ssid, ESP8266_SSID_MAX_LENGTH); } else { return NSAPI_ERROR_PARAMETER; } @@ -438,7 +438,7 @@ int ESP8266Interface::scan(WiFiAccessPoint *res, unsigned count, scan_mode mode, } return _esp.scan(res, count, (mode == SCANMODE_ACTIVE ? ESP8266::SCANMODE_ACTIVE : ESP8266::SCANMODE_PASSIVE), - t_min, t_max); + t_max, t_min); } bool ESP8266Interface::_get_firmware_ok() From 4b846642671c964f899d089834cba991e2ccc9c4 Mon Sep 17 00:00:00 2001 From: Seppo Takalo Date: Wed, 4 Sep 2019 11:19:32 +0300 Subject: [PATCH 056/227] Remove mbed_trace dependency to Nanomesh headers This library only uses standard types from C99, and thus does not need compiler specific tweaks from ns_types.h --- features/frameworks/mbed-trace/mbed-trace/mbed_trace.h | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/features/frameworks/mbed-trace/mbed-trace/mbed_trace.h b/features/frameworks/mbed-trace/mbed-trace/mbed_trace.h index 0562e4a898a..c0cef6a888b 100644 --- a/features/frameworks/mbed-trace/mbed-trace/mbed_trace.h +++ b/features/frameworks/mbed-trace/mbed-trace/mbed_trace.h @@ -48,15 +48,11 @@ extern "C" { #endif -#ifdef YOTTA_CFG #include #include #include -#else -#include "ns_types.h" -#endif - #include +#include #ifndef YOTTA_CFG_MBED_TRACE #define YOTTA_CFG_MBED_TRACE 0 From fb0c22fc239f672aa00ffdcb7cd4057b72c5b12c Mon Sep 17 00:00:00 2001 From: Seppo Takalo Date: Fri, 6 Sep 2019 13:05:19 +0300 Subject: [PATCH 057/227] Include ns_types.h before mbed_trace.h in Nanomesh --- .../nanostack-libservice/mbed-client-libservice/ns_trace.h | 1 + 1 file changed, 1 insertion(+) diff --git a/features/frameworks/nanostack-libservice/mbed-client-libservice/ns_trace.h b/features/frameworks/nanostack-libservice/mbed-client-libservice/ns_trace.h index 206e2399827..2219f8b8082 100644 --- a/features/frameworks/nanostack-libservice/mbed-client-libservice/ns_trace.h +++ b/features/frameworks/nanostack-libservice/mbed-client-libservice/ns_trace.h @@ -28,6 +28,7 @@ #define FEA_TRACE_SUPPORT #endif +#include "ns_types.h" #include "mbed-trace/mbed_trace.h" #endif /* NS_TRACE_H_ */ From 3ee36cb8558b0dad43d35463f8c52aaab05c686e Mon Sep 17 00:00:00 2001 From: Dustin Crossman Date: Thu, 29 Aug 2019 10:42:50 -0700 Subject: [PATCH 058/227] Fixed byte string related TypeError if using python3. --- TESTS/host_tests/pyusb_msd.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/TESTS/host_tests/pyusb_msd.py b/TESTS/host_tests/pyusb_msd.py index 4ab75296576..9d0e0284548 100644 --- a/TESTS/host_tests/pyusb_msd.py +++ b/TESTS/host_tests/pyusb_msd.py @@ -197,7 +197,7 @@ def _disk_path_windows(serial): @staticmethod def _disk_path_linux(serial): - output = subprocess.check_output(['lsblk', '-dnoserial,mountpoint']).split('\n') + output = subprocess.check_output(['lsblk', '-dnoserial,mountpoint']).split(b'\n') for line in output: serial_and_mount_point = line.split() if len(serial_and_mount_point) == 2: From 6de8243e9afe06365f17f9c6d9e0da3e08bed4d8 Mon Sep 17 00:00:00 2001 From: Hugues Kamba Date: Sat, 7 Sep 2019 21:00:21 +0100 Subject: [PATCH 059/227] Correct doxy-spellchecker error message --- tools/test/travis-ci/doxy-spellchecker/spell.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/test/travis-ci/doxy-spellchecker/spell.sh b/tools/test/travis-ci/doxy-spellchecker/spell.sh index 9574e69eb6a..1e4931cbc40 100755 --- a/tools/test/travis-ci/doxy-spellchecker/spell.sh +++ b/tools/test/travis-ci/doxy-spellchecker/spell.sh @@ -121,6 +121,6 @@ echo "Total Errors Found: ${ERRORS}" if [ ${ERRORS} -ne 0 ]; then echo "If any of the failed words should be considered valid please add them to the ignore.en.pws file"\ - "found in tools/test/scripts/doxy-spellchecker between the _code_ and _doxy_ tags." + "found in tools/test/travis-ci/doxy-spellchecker between the _code_ and _doxy_ tags." exit 1 fi From 9c1d3978fb9c0d86bd78faf7a3e562bf62f7ca39 Mon Sep 17 00:00:00 2001 From: int_szyk Date: Wed, 4 Sep 2019 13:54:36 +0200 Subject: [PATCH 060/227] Change stack sizes. Change stack sizes in test stats_cpu and mbedmicro-rtos-mbed-threads. The value 384 was declared to make this test pass on STM32F070RB, but its main stack value has been changed to 3KB so now it passes this test with 512 stack size. The change was needed to make GR_LYCHEE pass this test on ARM compiler. --- TESTS/mbed_platform/stats_cpu/main.cpp | 6 ++++++ TESTS/mbedmicro-rtos-mbed/threads/main.cpp | 12 ++++-------- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/TESTS/mbed_platform/stats_cpu/main.cpp b/TESTS/mbed_platform/stats_cpu/main.cpp index 348da308213..1a3818293d0 100644 --- a/TESTS/mbed_platform/stats_cpu/main.cpp +++ b/TESTS/mbed_platform/stats_cpu/main.cpp @@ -29,7 +29,13 @@ using namespace utest::v1; DigitalOut led1(LED1); +// Targets with these cores have their RAM enough size to create threads with bigger stacks +#if defined(__CORTEX_A9) || defined(__CORTEX_M23) || defined(__CORTEX_M33) || defined(__CORTEX_M7) +#define MAX_THREAD_STACK 512 +#else #define MAX_THREAD_STACK 384 +#endif + #define SAMPLE_TIME 1000 // msec #define LOOP_TIME 2000 // msec diff --git a/TESTS/mbedmicro-rtos-mbed/threads/main.cpp b/TESTS/mbedmicro-rtos-mbed/threads/main.cpp index 470a9f081fc..c66e9fb0308 100644 --- a/TESTS/mbedmicro-rtos-mbed/threads/main.cpp +++ b/TESTS/mbedmicro-rtos-mbed/threads/main.cpp @@ -26,18 +26,14 @@ #else #define THREAD_STACK_SIZE 512 -#if defined(__CORTEX_A9) +#if defined(__CORTEX_A9) || defined(__CORTEX_M23) || defined(__CORTEX_M33) || defined(TARGET_ARM_FM) || defined(TARGET_CY8CKIT_062_WIFI_BT_PSA) #define PARALLEL_THREAD_STACK_SIZE 512 -#elif defined(__CORTEX_M23) || defined(__CORTEX_M33) -#define PARALLEL_THREAD_STACK_SIZE 512 -#elif defined(TARGET_ARM_FM) -#define PARALLEL_THREAD_STACK_SIZE 512 -#elif defined(TARGET_CY8CKIT_062_WIFI_BT_PSA) -#define PARALLEL_THREAD_STACK_SIZE 512 +#define CHILD_THREAD_STACK_SIZE 512 #else #define PARALLEL_THREAD_STACK_SIZE 384 -#endif #define CHILD_THREAD_STACK_SIZE 384 +#endif + using namespace utest::v1; From 7e3e80e230ae2e62ce1d60aaf2e7a8e7a2abadb1 Mon Sep 17 00:00:00 2001 From: Hugues Kamba Date: Fri, 6 Sep 2019 22:58:57 +0100 Subject: [PATCH 061/227] Harmonise Doxygen comments in drivers, events, platform and rtos dirs When a Doxygen group has been defined (created), all its needed to add documentation to that group is `\addtogroup`. Since all the information about the group is preserved, it is not necessary to mention the group hierarchy again with `\ingroup`. This PR removes unnecessary Doxygen lines across the `drivers`, `events`, `platform` and `rtos` directories. It also ensures that new groups are created with `\defgroup` once and referenced with `\addtogroup` whenever documentation needs to be added to an existing group. --- drivers/AnalogIn.h | 2 +- drivers/AnalogOut.h | 2 -- drivers/Ethernet.h | 3 ++- drivers/FlashIAP.h | 2 +- drivers/I2CSlave.h | 2 +- drivers/LowPowerTimeout.h | 2 +- drivers/LowPowerTimer.h | 2 +- drivers/MbedCRC.h | 1 - drivers/ResetReason.h | 2 +- drivers/SPI.h | 2 +- drivers/Ticker.h | 2 +- drivers/Timeout.h | 2 +- drivers/Timer.h | 2 +- drivers/TimerEvent.h | 2 +- drivers/internal/MIDIMessage.h | 2 +- drivers/internal/TableCRC.h | 1 - events/Event.h | 3 +-- events/UserAllocatedEvent.h | 3 +-- events/mbed_shared_queues.h | 1 - platform/ATCmdParser.h | 2 -- platform/CThunk.h | 25 ++++++++----------- platform/Callback.h | 1 - platform/CircularBuffer.h | 1 - platform/CriticalSectionLock.h | 2 -- platform/DeepSleepLock.h | 2 -- platform/DirHandle.h | 1 - platform/FunctionPointer.h | 1 - platform/LocalFileSystem.h | 1 - platform/NonCopyable.h | 2 +- platform/PlatformMutex.h | 1 - platform/ScopedLock.h | 2 +- platform/ScopedRamExecutionLock.h | 1 - platform/ScopedRomWriteLock.h | 1 - platform/SingletonPtr.h | 16 ++++++------ platform/Span.h | 2 +- platform/Stream.h | 2 +- platform/Transaction.h | 2 +- platform/internal/CThunkBase.h | 2 +- platform/mbed_assert.h | 16 ++++++------ platform/mbed_atomic.h | 1 - platform/mbed_critical.h | 2 -- platform/mbed_debug.h | 17 ++++++------- platform/mbed_error.h | 15 +++++------ platform/mbed_interface.h | 17 ++++++------- platform/mbed_mem_trace.h | 8 +++--- platform/mbed_mktime.h | 7 +++--- platform/mbed_mpu_mgmt.h | 16 ++++++------ platform/mbed_poll.h | 2 +- platform/mbed_power_mgmt.h | 16 ++++++------ platform/mbed_preprocessor.h | 15 ++++++----- platform/mbed_retarget.h | 2 +- platform/mbed_rtc_time.h | 16 ++++++------ platform/mbed_stats.h | 16 ++++++------ platform/mbed_toolchain.h | 16 ++++++------ platform/mbed_version.h | 16 ++++++------ platform/mbed_wait_api.h | 17 ++++++------- platform/platform.h | 4 +++ platform/toolchain.h | 6 ----- rtos/ConditionVariable.h | 3 +-- rtos/EventFlags.h | 2 +- rtos/Kernel.h | 2 +- rtos/Mail.h | 2 +- rtos/MemoryPool.h | 3 +-- rtos/Mutex.h | 1 - rtos/Queue.h | 2 +- rtos/RtosTimer.h | 2 +- rtos/Semaphore.h | 2 +- rtos/ThisThread.h | 7 +++++- rtos/Thread.h | 2 +- rtos/mbed_rtos_storage.h | 2 -- rtos/mbed_rtos_types.h | 6 ++++- rtos/rtos.h | 9 ++++--- rtos/source/TARGET_CORTEX/mbed_boot.h | 1 - rtos/source/rtos_handlers.h | 8 +++--- rtos/source/rtos_idle.h | 2 -- .../travis-ci/doxy-spellchecker/ignore.en.pws | 1 + 76 files changed, 176 insertions(+), 211 deletions(-) diff --git a/drivers/AnalogIn.h b/drivers/AnalogIn.h index 60637146a53..6f884920749 100644 --- a/drivers/AnalogIn.h +++ b/drivers/AnalogIn.h @@ -28,7 +28,7 @@ namespace mbed { /** \defgroup mbed-os-public Public API */ -/** \addtogroup drivers-public-api Drivers +/** \defgroup drivers-public-api Drivers * \ingroup mbed-os-public */ diff --git a/drivers/AnalogOut.h b/drivers/AnalogOut.h index fee78fd9401..2eaabefbd6a 100644 --- a/drivers/AnalogOut.h +++ b/drivers/AnalogOut.h @@ -25,8 +25,6 @@ #include "platform/PlatformMutex.h" namespace mbed { -/** \addtogroup drivers-public-api */ - /** * \defgroup drivers_AnalogOut AnalogOut class * \ingroup drivers-public-api-gpio diff --git a/drivers/Ethernet.h b/drivers/Ethernet.h index e14be3a1790..b1eb9c3ecd6 100644 --- a/drivers/Ethernet.h +++ b/drivers/Ethernet.h @@ -23,9 +23,10 @@ #if DEVICE_ETHERNET || defined(DOXYGEN_ONLY) namespace mbed { -/** \ingroup mbed-os-public */ + /** \addtogroup drivers-public-api */ /** @{*/ + /** * \defgroup drivers_Ethernet Ethernet class * @{ diff --git a/drivers/FlashIAP.h b/drivers/FlashIAP.h index fdcda768f03..5ac0a8986cf 100644 --- a/drivers/FlashIAP.h +++ b/drivers/FlashIAP.h @@ -49,9 +49,9 @@ extern uint32_t Load$$LR$$LR_IROM1$$Limit[]; namespace mbed { -/** \ingroup mbed-os-public */ /** \addtogroup drivers-public-api */ /** @{*/ + /** * \defgroup drivers_FlashIAP FlashIAP class * @{ diff --git a/drivers/I2CSlave.h b/drivers/I2CSlave.h index e2d123a9913..000d480f74a 100644 --- a/drivers/I2CSlave.h +++ b/drivers/I2CSlave.h @@ -25,7 +25,7 @@ namespace mbed { /** - * \addtogroup drivers_I2CSlave I2CSlave class + * \defgroup drivers_I2CSlave I2CSlave class * \ingroup drivers-public-api-i2c * @{ */ diff --git a/drivers/LowPowerTimeout.h b/drivers/LowPowerTimeout.h index 08137329fae..91c60b7c101 100644 --- a/drivers/LowPowerTimeout.h +++ b/drivers/LowPowerTimeout.h @@ -27,7 +27,7 @@ namespace mbed { /** - * \addtogroup drivers_LowPowerTimeout LowPowerTimeout class + * \defgroup drivers_LowPowerTimeout LowPowerTimeout class * \ingroup drivers-public-api-ticker * @{ */ diff --git a/drivers/LowPowerTimer.h b/drivers/LowPowerTimer.h index df886c75640..43560362376 100644 --- a/drivers/LowPowerTimer.h +++ b/drivers/LowPowerTimer.h @@ -27,7 +27,7 @@ namespace mbed { /** - * \addtogroup drivers_LowPowerTimer LowPowerTimer class + * \defgroup drivers_LowPowerTimer LowPowerTimer class * \ingroup drivers-public-api-ticker * @{ */ diff --git a/drivers/MbedCRC.h b/drivers/MbedCRC.h index 18ac97abc4e..e4a388d5616 100644 --- a/drivers/MbedCRC.h +++ b/drivers/MbedCRC.h @@ -40,7 +40,6 @@ but we check for ( width < 8) before performing shift, so it should not be an is #endif namespace mbed { -/** \ingroup mbed-os-public */ /** \addtogroup drivers-public-api */ /** @{*/ /** diff --git a/drivers/ResetReason.h b/drivers/ResetReason.h index 289b4b9808e..1ea1d3e6dd7 100644 --- a/drivers/ResetReason.h +++ b/drivers/ResetReason.h @@ -22,9 +22,9 @@ #include "reset_reason_api.h" namespace mbed { -/** \ingroup mbed-os-public */ /** \addtogroup drivers-public-api */ /** @{*/ + /** * \defgroup drivers_ResetReason ResetReason class * @{ diff --git a/drivers/SPI.h b/drivers/SPI.h index eaaabceeef0..c247b3ea708 100644 --- a/drivers/SPI.h +++ b/drivers/SPI.h @@ -46,7 +46,7 @@ namespace mbed { /** - * \addtogroup drivers_SPI SPI class + * \defgroup drivers_SPI SPI class * \ingroup drivers-public-api-spi * @{ */ diff --git a/drivers/Ticker.h b/drivers/Ticker.h index b6c9dc9b02b..362f74c4bd3 100644 --- a/drivers/Ticker.h +++ b/drivers/Ticker.h @@ -26,7 +26,7 @@ namespace mbed { /** - * \addtogroup drivers_Ticker Ticker class + * \defgroup drivers_Ticker Ticker class * \ingroup drivers-public-api-ticker * @{ */ diff --git a/drivers/Timeout.h b/drivers/Timeout.h index d4b63b37e40..bbf71c4c85e 100644 --- a/drivers/Timeout.h +++ b/drivers/Timeout.h @@ -22,7 +22,7 @@ namespace mbed { /** - * \addtogroup drivers_Timeout Timeout class + * \defgroup drivers_Timeout Timeout class * \ingroup drivers-public-api-ticker * @{ */ diff --git a/drivers/Timer.h b/drivers/Timer.h index 8ba20d6e47e..03474cc6f60 100644 --- a/drivers/Timer.h +++ b/drivers/Timer.h @@ -23,7 +23,7 @@ namespace mbed { /** - * \addtogroup drivers_Timer Timer class + * \defgroup drivers_Timer Timer class * \ingroup drivers-public-api-ticker * @{ */ diff --git a/drivers/TimerEvent.h b/drivers/TimerEvent.h index 1c47df0cca4..ff00ef3d3fe 100644 --- a/drivers/TimerEvent.h +++ b/drivers/TimerEvent.h @@ -22,7 +22,7 @@ namespace mbed { /** - * \addtogroup drivers_TimerEvent TimerEvent class + * \defgroup drivers_TimerEvent TimerEvent class * \ingroup drivers-public-api-ticker * @{ */ diff --git a/drivers/internal/MIDIMessage.h b/drivers/internal/MIDIMessage.h index 14b08a1e2b5..5e417657ffc 100644 --- a/drivers/internal/MIDIMessage.h +++ b/drivers/internal/MIDIMessage.h @@ -43,7 +43,7 @@ /** * \defgroup drivers_MIDIMessage MIDIMessage class - * \ingroup drivers-internal-usb + * \ingroup drivers-internal-api-usb * @{ */ diff --git a/drivers/internal/TableCRC.h b/drivers/internal/TableCRC.h index 4960bb478fe..18d2d0d81ad 100644 --- a/drivers/internal/TableCRC.h +++ b/drivers/internal/TableCRC.h @@ -22,7 +22,6 @@ namespace mbed { /** \addtogroup drivers-internal-api - * \ingroup mbed-os-internal * @{ */ diff --git a/events/Event.h b/events/Event.h index 73f43286d16..ef15882489d 100644 --- a/events/Event.h +++ b/events/Event.h @@ -21,8 +21,7 @@ #include "platform/mbed_assert.h" namespace events { -/** - * \addtogroup events-public-api Events +/** \defgroup events-public-api Events * \ingroup mbed-os-public * @{ */ diff --git a/events/UserAllocatedEvent.h b/events/UserAllocatedEvent.h index 71c4b700cbf..225ee895548 100644 --- a/events/UserAllocatedEvent.h +++ b/events/UserAllocatedEvent.h @@ -23,8 +23,7 @@ namespace events { /** - * \addtogroup events-public-api Events - * \ingroup mbed-os-public + * \addtogroup events-public-api * @{ */ template diff --git a/events/mbed_shared_queues.h b/events/mbed_shared_queues.h index acd83a6a290..9be5ff16e56 100644 --- a/events/mbed_shared_queues.h +++ b/events/mbed_shared_queues.h @@ -19,7 +19,6 @@ #include "events/EventQueue.h" namespace mbed { -/** \ingroup mbed-os-public */ /** \addtogroup events-public-api */ /** @{*/ diff --git a/platform/ATCmdParser.h b/platform/ATCmdParser.h index f183cb64e1c..36ffd8752bb 100644 --- a/platform/ATCmdParser.h +++ b/platform/ATCmdParser.h @@ -27,8 +27,6 @@ #include "platform/FileHandle.h" namespace mbed { - -/** \ingroup mbed-os-public */ /** \addtogroup platform-public-api Platform */ /** @{*/ /** diff --git a/platform/CThunk.h b/platform/CThunk.h index 6e350c671d7..2c9c751b65e 100644 --- a/platform/CThunk.h +++ b/platform/CThunk.h @@ -1,18 +1,4 @@ -/** \ingroup mbed-os-public */ -/** \addtogroup platform-public-api */ -/** @{*/ -/** - * \defgroup platform_CThunk CThunk class - * @{ - */ -/* General C++ Object Thunking class - * - * - allows direct callbacks to non-static C++ class functions - * - keeps track for the corresponding class instance - * - supports an optional context parameter for the called function - * - ideally suited for class object receiving interrupts (NVIC_SetVector) - * - * Copyright (c) 2014-2019 ARM Limited +/* Copyright (c) 2014-2019 ARM Limited * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -28,6 +14,15 @@ * limitations under the License. */ + +/** \addtogroup platform-public-api */ +/** @{*/ + +/** + * \defgroup platform_CThunk CThunk class + * @{ + */ + /* General C++ Object Thunking class * * - allows direct callbacks to non-static C++ class functions diff --git a/platform/Callback.h b/platform/Callback.h index 78f299ae590..58b06853f83 100644 --- a/platform/Callback.h +++ b/platform/Callback.h @@ -24,7 +24,6 @@ #include "platform/mbed_toolchain.h" namespace mbed { -/** \ingroup mbed-os-public */ /** \addtogroup platform-public-api */ /** @{*/ /** diff --git a/platform/CircularBuffer.h b/platform/CircularBuffer.h index d5d862a3f20..7678230279e 100644 --- a/platform/CircularBuffer.h +++ b/platform/CircularBuffer.h @@ -51,7 +51,6 @@ struct is_unsigned { }; }; -/** \ingroup mbed-os-public */ /** \addtogroup platform-public-api */ /** @{*/ /** diff --git a/platform/CriticalSectionLock.h b/platform/CriticalSectionLock.h index 2d2291d816b..e1e66f7a646 100644 --- a/platform/CriticalSectionLock.h +++ b/platform/CriticalSectionLock.h @@ -21,8 +21,6 @@ #include "platform/mbed_toolchain.h" namespace mbed { - -/** \ingroup mbed-os-public */ /** \addtogroup platform-public-api */ /** @{*/ /** diff --git a/platform/DeepSleepLock.h b/platform/DeepSleepLock.h index 6211f2d74fc..c4841aa47c8 100644 --- a/platform/DeepSleepLock.h +++ b/platform/DeepSleepLock.h @@ -21,8 +21,6 @@ #include namespace mbed { - -/** \ingroup mbed-os-public */ /** \addtogroup platform-public-api */ /** @{*/ /** diff --git a/platform/DirHandle.h b/platform/DirHandle.h index 60b9e08dde1..3607af09570 100644 --- a/platform/DirHandle.h +++ b/platform/DirHandle.h @@ -22,7 +22,6 @@ #include "platform/NonCopyable.h" namespace mbed { -/** \ingroup mbed-os-public */ /** \addtogroup platform-public-api */ /** @{*/ /** diff --git a/platform/FunctionPointer.h b/platform/FunctionPointer.h index e3fb94fe4d8..7111b8d19bf 100644 --- a/platform/FunctionPointer.h +++ b/platform/FunctionPointer.h @@ -23,7 +23,6 @@ #include namespace mbed { -/** \ingroup mbed-os-public */ /** \addtogroup platform-public-api */ /** @{*/ /** diff --git a/platform/LocalFileSystem.h b/platform/LocalFileSystem.h index 0061ef9f2bf..4ee6b6a18e7 100644 --- a/platform/LocalFileSystem.h +++ b/platform/LocalFileSystem.h @@ -26,7 +26,6 @@ #include "platform/NonCopyable.h" namespace mbed { -/** \ingroup mbed-os-public */ /** \addtogroup platform-public-api */ /** @{*/ /** diff --git a/platform/NonCopyable.h b/platform/NonCopyable.h index 4d78e834274..487aaffbd8d 100644 --- a/platform/NonCopyable.h +++ b/platform/NonCopyable.h @@ -24,9 +24,9 @@ namespace mbed { -/** \ingroup mbed-os-public */ /** \addtogroup platform-public-api */ /** @{*/ + /** * \defgroup platform_NonCopyable NonCopyable class * @{ diff --git a/platform/PlatformMutex.h b/platform/PlatformMutex.h index 7f26c800db6..d2e94e5b87d 100644 --- a/platform/PlatformMutex.h +++ b/platform/PlatformMutex.h @@ -19,7 +19,6 @@ #include "platform/NonCopyable.h" -/** \ingroup mbed-os-public */ /** \addtogroup platform-public-api */ /** @{*/ diff --git a/platform/ScopedLock.h b/platform/ScopedLock.h index e1ddf3bfc93..b2e664d56a4 100644 --- a/platform/ScopedLock.h +++ b/platform/ScopedLock.h @@ -21,9 +21,9 @@ namespace mbed { -/** \ingroup mbed-os-public */ /** \addtogroup platform-public-api */ /** @{*/ + /** * \defgroup platform_ScopedLock ScopedLock functions * @{ diff --git a/platform/ScopedRamExecutionLock.h b/platform/ScopedRamExecutionLock.h index 72e1874cca0..abbf106cfe4 100644 --- a/platform/ScopedRamExecutionLock.h +++ b/platform/ScopedRamExecutionLock.h @@ -21,7 +21,6 @@ namespace mbed { -/** \ingroup mbed-os-public */ /** \addtogroup platform-public-api */ /** @{*/ diff --git a/platform/ScopedRomWriteLock.h b/platform/ScopedRomWriteLock.h index 4e39382d927..ad1b52e26c0 100644 --- a/platform/ScopedRomWriteLock.h +++ b/platform/ScopedRomWriteLock.h @@ -21,7 +21,6 @@ namespace mbed { -/** \ingroup mbed-os-public */ /** \addtogroup platform-public-api */ /** @{*/ diff --git a/platform/SingletonPtr.h b/platform/SingletonPtr.h index a71e0873cec..790287d9ccf 100644 --- a/platform/SingletonPtr.h +++ b/platform/SingletonPtr.h @@ -1,11 +1,3 @@ - -/** \ingroup mbed-os-public */ -/** \addtogroup platform-public-api */ -/** @{*/ -/** - * \defgroup platform_SingletonPtr SingletonPtr class - * @{ - */ /* mbed Microcontroller Library * Copyright (c) 2006-2019 ARM Limited * SPDX-License-Identifier: Apache-2.0 @@ -38,6 +30,14 @@ extern osMutexId_t singleton_mutex_id; #endif +/** \addtogroup platform-public-api */ +/** @{*/ + +/** + * \defgroup platform_SingletonPtr SingletonPtr class + * @{ + */ + /** Lock the singleton mutex * * This function is typically used to provide diff --git a/platform/Span.h b/platform/Span.h index 889cddc333f..c5bac9d6824 100644 --- a/platform/Span.h +++ b/platform/Span.h @@ -26,9 +26,9 @@ namespace mbed { -/** \ingroup mbed-os-public */ /** \addtogroup platform-public-api */ /** @{*/ + /** * \defgroup platform_Span Span class * @{ diff --git a/platform/Stream.h b/platform/Stream.h index ef03d71a8ea..b25783f3faa 100644 --- a/platform/Stream.h +++ b/platform/Stream.h @@ -25,9 +25,9 @@ #include namespace mbed { -/** \ingroup mbed-os-public */ /** \addtogroup platform-public-api */ /** @{*/ + /** * \defgroup platform_Stream Stream class * @{ diff --git a/platform/Transaction.h b/platform/Transaction.h index 8b30ef494c2..1d8d4cd0d0b 100644 --- a/platform/Transaction.h +++ b/platform/Transaction.h @@ -20,9 +20,9 @@ #include "platform/platform.h" namespace mbed { -/** \ingroup mbed-os-public */ /** \addtogroup platform-public-api */ /** @{*/ + /** * \defgroup platform_Transaction Transaction class * @{ diff --git a/platform/internal/CThunkBase.h b/platform/internal/CThunkBase.h index ef0f326646f..212ff446e0a 100644 --- a/platform/internal/CThunkBase.h +++ b/platform/internal/CThunkBase.h @@ -18,7 +18,7 @@ #ifndef __CTHUNK_BASE_H__ #define __CTHUNK_BASE_H__ -/** \addtogroup platform-internal-api Platform +/** \defgroup platform-internal-api Platform * \ingroup mbed-os-internal */ diff --git a/platform/mbed_assert.h b/platform/mbed_assert.h index f43aa8b4bf1..ae011e361d0 100644 --- a/platform/mbed_assert.h +++ b/platform/mbed_assert.h @@ -1,11 +1,3 @@ - -/** \ingroup mbed-os-public */ -/** \addtogroup platform-public-api */ -/** @{*/ -/** - * \defgroup platform_Assert Assert macros - * @{ - */ /* mbed Microcontroller Library * Copyright (c) 2006-2019 ARM Limited * SPDX-License-Identifier: Apache-2.0 @@ -31,6 +23,14 @@ extern "C" { #endif +/** \addtogroup platform-public-api */ +/** @{*/ + +/** + * \defgroup platform_Assert Assert macros + * @{ + */ + /** Internal mbed assert function which is invoked when MBED_ASSERT macro fails. * This function is active only if NDEBUG is not defined prior to including this * assert header file. diff --git a/platform/mbed_atomic.h b/platform/mbed_atomic.h index ca9f8df799c..28e2cb2f81f 100644 --- a/platform/mbed_atomic.h +++ b/platform/mbed_atomic.h @@ -26,7 +26,6 @@ #include #include "platform/mbed_toolchain.h" -/** \ingroup mbed-os-public */ /** \addtogroup platform-public-api */ /** @{*/ diff --git a/platform/mbed_critical.h b/platform/mbed_critical.h index f1a152ef77e..921379488e2 100644 --- a/platform/mbed_critical.h +++ b/platform/mbed_critical.h @@ -1,4 +1,3 @@ - /* * Copyright (c) 2015-2019, ARM Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 @@ -25,7 +24,6 @@ extern "C" { #endif -/** \ingroup mbed-os-public */ /** \addtogroup platform-public-api */ /** @{*/ /** diff --git a/platform/mbed_debug.h b/platform/mbed_debug.h index cfa52bfebb8..ed5e60d532b 100644 --- a/platform/mbed_debug.h +++ b/platform/mbed_debug.h @@ -1,12 +1,3 @@ - -/** \ingroup mbed-os-public */ -/** \addtogroup platform-public-api */ -/** @{*/ -/** - * \defgroup platform_debug Debug functions - * @{ - */ - /* mbed Microcontroller Library * Copyright (c) 2006-2019 ARM Limited * SPDX-License-Identifier: Apache-2.0 @@ -35,6 +26,14 @@ extern "C" { #endif +/** \addtogroup platform-public-api */ +/** @{*/ + +/** + * \defgroup platform_debug Debug functions + * @{ + */ + static inline void debug(const char *format, ...) MBED_PRINTF(1, 2); static inline void debug_if(int condition, const char *format, ...) MBED_PRINTF(2, 3); diff --git a/platform/mbed_error.h b/platform/mbed_error.h index 7a1f7012887..9ba86b279a7 100644 --- a/platform/mbed_error.h +++ b/platform/mbed_error.h @@ -1,10 +1,3 @@ -/** \ingroup mbed-os-public */ -/** \addtogroup platform-public-api */ -/** @{*/ -/** - * \defgroup platform_error Error functions - * @{ - */ /* mbed Microcontroller Library * Copyright (c) 2006-2019 ARM Limited * SPDX-License-Identifier: Apache-2.0 @@ -32,6 +25,14 @@ extern "C" { #endif +/** \addtogroup platform-public-api */ +/** @{*/ + +/** + * \defgroup platform_error Error functions + * @{ + */ + /** Define this macro to include filenames in error context. For release builds, do not include filename to save memory. * MBED_PLATFORM_CONF_ERROR_FILENAME_CAPTURE_ENABLED */ diff --git a/platform/mbed_interface.h b/platform/mbed_interface.h index 44c1f262ea7..279eca727d9 100644 --- a/platform/mbed_interface.h +++ b/platform/mbed_interface.h @@ -1,12 +1,3 @@ - -/** \ingroup mbed-os-public */ -/** \addtogroup platform-public-api */ -/** @{*/ -/** - * \defgroup platform_interface Network interface and other utility functions - * @{ - */ - /* mbed Microcontroller Library * Copyright (c) 2006-2019 ARM Limited * SPDX-License-Identifier: Apache-2.0 @@ -31,6 +22,14 @@ #include "platform/mbed_toolchain.h" #include "device.h" +/** \addtogroup platform-public-api */ +/** @{*/ + +/** + * \defgroup platform_interface Network interface and other utility functions + * @{ + */ + /* Mbed interface mac address * if MBED_MAC_ADD_x are zero, interface uid sets mac address, * otherwise MAC_ADD_x are used. diff --git a/platform/mbed_mem_trace.h b/platform/mbed_mem_trace.h index 12e2c104df7..2c5bc40d851 100644 --- a/platform/mbed_mem_trace.h +++ b/platform/mbed_mem_trace.h @@ -1,8 +1,3 @@ - -/** \ingroup mbed-os-public */ -/** \addtogroup platform-public-api */ -/** @{*/ - /* mbed Microcontroller Library * Copyright (c) 2006-2019 ARM Limited * SPDX-License-Identifier: Apache-2.0 @@ -30,6 +25,9 @@ extern "C" { #include #include +/** \addtogroup platform-public-api */ +/** @{*/ + /** * enum Memory operation types for tracer */ diff --git a/platform/mbed_mktime.h b/platform/mbed_mktime.h index 21448eaaad0..0a748c29737 100644 --- a/platform/mbed_mktime.h +++ b/platform/mbed_mktime.h @@ -1,7 +1,3 @@ - -/** \ingroup mbed-os-public */ -/** \addtogroup platform-public-api */ -/** @{*/ /* mbed Microcontroller Library * Copyright (c) 2017-2019 ARM Limited * SPDX-License-Identifier: Apache-2.0 @@ -30,6 +26,9 @@ extern "C" { #endif +/** \addtogroup platform-public-api */ +/** @{*/ + /** * \defgroup platform_mktime mktime functions * @{ diff --git a/platform/mbed_mpu_mgmt.h b/platform/mbed_mpu_mgmt.h index c3a1cc96c26..34f289165f9 100644 --- a/platform/mbed_mpu_mgmt.h +++ b/platform/mbed_mpu_mgmt.h @@ -1,11 +1,3 @@ -/** \ingroup mbed-os-public */ -/** \addtogroup platform-public-api */ -/** @{*/ -/** - * \defgroup platform_mpu_mgmt MPU management functions - * @{ - */ - /* mbed Microcontroller Library * Copyright (c) 2006-2019 ARM Limited * @@ -30,6 +22,14 @@ extern "C" { #endif +/** \addtogroup platform-public-api */ +/** @{*/ + +/** + * \defgroup platform_mpu_mgmt MPU management functions + * @{ + */ + #if (DEVICE_MPU && MBED_CONF_PLATFORM_USE_MPU) || defined(DOXYGEN_ONLY) #define mbed_mpu_manager_init() mbed_mpu_init() diff --git a/platform/mbed_poll.h b/platform/mbed_poll.h index e293f77edb3..04a71c46172 100644 --- a/platform/mbed_poll.h +++ b/platform/mbed_poll.h @@ -27,9 +27,9 @@ namespace mbed { class FileHandle; -/** \ingroup mbed-os-public */ /** \addtogroup platform-public-api */ /** @{*/ + /** * \defgroup platform_poll poll functions * @{ diff --git a/platform/mbed_power_mgmt.h b/platform/mbed_power_mgmt.h index dc476ffaf70..86d57d16e63 100644 --- a/platform/mbed_power_mgmt.h +++ b/platform/mbed_power_mgmt.h @@ -1,11 +1,3 @@ -/** \ingroup mbed-os-public */ -/** \addtogroup platform-public-api */ -/** @{*/ -/** - * \defgroup platform_power_mgmt Power management functions - * @{ - */ - /* mbed Microcontroller Library * Copyright (c) 2006-2019 ARM Limited * SPDX-License-Identifier: Apache-2.0 @@ -34,6 +26,14 @@ extern "C" { #endif +/** \addtogroup platform-public-api */ +/** @{*/ + +/** + * \defgroup platform_power_mgmt Power management functions + * @{ + */ + /** * @defgroup hal_sleep_manager Sleep manager API * The sleep manager provides API to automatically select sleep mode. diff --git a/platform/mbed_preprocessor.h b/platform/mbed_preprocessor.h index 1b5607ef582..f7be2f1d7d5 100644 --- a/platform/mbed_preprocessor.h +++ b/platform/mbed_preprocessor.h @@ -1,11 +1,3 @@ -/** \ingroup mbed-os-public */ -/** \addtogroup platform-public-api */ -/** @{*/ -/** - * \defgroup platform_preprocessor preprocessor macros - * @{ - */ - /* mbed Microcontroller Library * Copyright (c) 2006-2019 ARM Limited * SPDX-License-Identifier: Apache-2.0 @@ -25,6 +17,13 @@ #ifndef MBED_PREPROCESSOR_H #define MBED_PREPROCESSOR_H +/** \addtogroup platform-public-api */ +/** @{*/ + +/** + * \defgroup platform_preprocessor preprocessor macros + * @{ + */ /** MBED_CONCAT * Concatenate tokens together diff --git a/platform/mbed_retarget.h b/platform/mbed_retarget.h index f8aac6e9c4d..c5058280083 100644 --- a/platform/mbed_retarget.h +++ b/platform/mbed_retarget.h @@ -79,9 +79,9 @@ typedef unsigned int gid_t; ///< Group ID #include -/** \ingroup mbed-os-public */ /** \addtogroup platform-public-api */ /** @{*/ + /** * \defgroup platform_retarget Retarget functions * @{ diff --git a/platform/mbed_rtc_time.h b/platform/mbed_rtc_time.h index 935ff8d3e2b..f86ffc37f57 100644 --- a/platform/mbed_rtc_time.h +++ b/platform/mbed_rtc_time.h @@ -1,11 +1,3 @@ - -/** \ingroup mbed-os-public */ -/** \addtogroup platform-public-api */ -/** @{*/ -/** - * \defgroup platform_rtc_time rtc_time functions - * @{ - */ /* mbed Microcontroller Library * Copyright (c) 2006-2019 ARM Limited * SPDX-License-Identifier: Apache-2.0 @@ -29,6 +21,14 @@ extern "C" { #endif +/** \addtogroup platform-public-api */ +/** @{*/ + +/** + * \defgroup platform_rtc_time rtc_time functions + * @{ + */ + /* Timeval definition for non GCC_ARM toolchains */ #if !defined(__GNUC__) || defined(__CC_ARM) || defined(__clang__) struct timeval { diff --git a/platform/mbed_stats.h b/platform/mbed_stats.h index 8bb8056830f..f331c655be3 100644 --- a/platform/mbed_stats.h +++ b/platform/mbed_stats.h @@ -1,11 +1,3 @@ - -/** \ingroup mbed-os-public */ -/** \addtogroup platform-public-api */ -/** @{*/ -/** - * \defgroup platform_stats stats functions - * @{ - */ /* mbed Microcontroller Library * Copyright (c) 2016-2019 ARM Limited * SPDX-License-Identifier: Apache-2.0 @@ -32,6 +24,14 @@ extern "C" { #endif +/** \addtogroup platform-public-api */ +/** @{*/ + +/** + * \defgroup platform_stats stats functions + * @{ + */ + #ifdef MBED_ALL_STATS_ENABLED #ifndef MBED_SYS_STATS_ENABLED diff --git a/platform/mbed_toolchain.h b/platform/mbed_toolchain.h index 04752ba4f1c..cd60336ce7f 100644 --- a/platform/mbed_toolchain.h +++ b/platform/mbed_toolchain.h @@ -1,12 +1,3 @@ - -/** \ingroup mbed-os-public */ -/** \addtogroup platform-public-api */ -/** @{*/ -/** - * \defgroup platform_toolchain Toolchain functions - * @{ - */ - /* mbed Microcontroller Library * Copyright (c) 2006-2019 ARM Limited * SPDX-License-Identifier: Apache-2.0 @@ -37,6 +28,13 @@ #warning "This compiler is not yet supported." #endif +/** \addtogroup platform-public-api */ +/** @{*/ + +/** + * \defgroup platform_toolchain Toolchain functions + * @{ + */ // Attributes diff --git a/platform/mbed_version.h b/platform/mbed_version.h index bbbdc855232..854e9deb74b 100644 --- a/platform/mbed_version.h +++ b/platform/mbed_version.h @@ -1,11 +1,3 @@ - -/** \ingroup mbed-os-public */ -/** \addtogroup platform-public-api */ -/** @{*/ -/** - * \defgroup platform_version Version macros - * @{ - */ /* mbed Microcontroller Library * Copyright (c) 2018-2019 ARM Limited * SPDX-License-Identifier: Apache-2.0 @@ -26,6 +18,14 @@ #ifndef MBED_VERSION_H #define MBED_VERSION_H +/** \addtogroup platform-public-api */ +/** @{*/ + +/** + * \defgroup platform_version Version macros + * @{ + */ + /** MBED_MAJOR_VERSION * Mbed OS major version * diff --git a/platform/mbed_wait_api.h b/platform/mbed_wait_api.h index edf5075f838..d86a5d48135 100644 --- a/platform/mbed_wait_api.h +++ b/platform/mbed_wait_api.h @@ -1,12 +1,3 @@ - -/** \ingroup mbed-os-public */ -/** \addtogroup platform-public-api */ -/** @{*/ -/** - * \defgroup platform_wait_api wait_api functions - * @{ - */ - /* mbed Microcontroller Library * Copyright (c) 2006-2019 ARM Limited * SPDX-License-Identifier: Apache-2.0 @@ -34,6 +25,14 @@ extern "C" { #endif +/** \addtogroup platform-public-api */ +/** @{*/ + +/** + * \defgroup platform_wait_api wait_api functions + * @{ + */ + /** Generic wait functions. * * These provide simple NOP type wait capabilities. diff --git a/platform/platform.h b/platform/platform.h index da2431ab7d7..3268c7c5bdc 100644 --- a/platform/platform.h +++ b/platform/platform.h @@ -29,4 +29,8 @@ #include "PinNames.h" #include "PeripheralNames.h" +/** \defgroup platform-public-api Platform + * \ingroup mbed-os-public + */ + #endif diff --git a/platform/toolchain.h b/platform/toolchain.h index c69c981178a..6e3c2a88248 100644 --- a/platform/toolchain.h +++ b/platform/toolchain.h @@ -1,7 +1,3 @@ - -/** \ingroup mbed-os-public */ -/** \addtogroup platform-public-api */ -/** @{*/ /* mbed Microcontroller Library * Copyright (c) 2006-2019 ARM Limited * SPDX-License-Identifier: Apache-2.0 @@ -26,5 +22,3 @@ #include "platform/mbed_toolchain.h" #endif - -/** @}*/ diff --git a/rtos/ConditionVariable.h b/rtos/ConditionVariable.h index 7bd46049eec..f76b16dfcdf 100644 --- a/rtos/ConditionVariable.h +++ b/rtos/ConditionVariable.h @@ -32,8 +32,7 @@ #if MBED_CONF_RTOS_PRESENT || defined(DOXYGEN_ONLY) namespace rtos { -/** \ingroup mbed-os-public */ -/** \addtogroup rtos-public-api RTOS */ +/** \addtogroup rtos-public-api */ /** @{*/ struct Waiter; diff --git a/rtos/EventFlags.h b/rtos/EventFlags.h index b18a70e96bf..6ab38272c98 100644 --- a/rtos/EventFlags.h +++ b/rtos/EventFlags.h @@ -31,9 +31,9 @@ #include "platform/NonCopyable.h" namespace rtos { -/** \ingroup mbed-os-public */ /** \addtogroup rtos-public-api */ /** @{*/ + /** * \defgroup rtos_EventFlags EventFlags class * @{ diff --git a/rtos/Kernel.h b/rtos/Kernel.h index b5a4ad4086b..57a86f7eb17 100644 --- a/rtos/Kernel.h +++ b/rtos/Kernel.h @@ -26,7 +26,6 @@ #include "rtos/mbed_rtos_types.h" namespace rtos { -/** \ingroup mbed-os-public */ /** \addtogroup rtos-public-api */ /** @{*/ @@ -62,5 +61,6 @@ void attach_thread_terminate_hook(void (*fptr)(osThreadId_t id)); } // namespace Kernel /** @}*/ + } // namespace rtos #endif diff --git a/rtos/Mail.h b/rtos/Mail.h index a747a9e6649..494aa59560a 100644 --- a/rtos/Mail.h +++ b/rtos/Mail.h @@ -41,9 +41,9 @@ using namespace rtos; #if MBED_CONF_RTOS_PRESENT || defined(DOXYGEN_ONLY) namespace rtos { -/** \ingroup mbed-os-public */ /** \addtogroup rtos-public-api */ /** @{*/ + /** * \defgroup rtos_Mail Mail class * @{ diff --git a/rtos/MemoryPool.h b/rtos/MemoryPool.h index 595734b952c..0f29b7c6945 100644 --- a/rtos/MemoryPool.h +++ b/rtos/MemoryPool.h @@ -35,9 +35,9 @@ #if MBED_CONF_RTOS_PRESENT || defined(DOXYGEN_ONLY) namespace rtos { -/** \ingroup mbed-os-public */ /** \addtogroup rtos-public-api */ /** @{*/ + /** * \defgroup rtos_MemoryPool MemoryPool class * @{ @@ -193,7 +193,6 @@ class MemoryPool : private mbed::NonCopyable > { }; /** @}*/ /** @}*/ - } #endif #endif diff --git a/rtos/Mutex.h b/rtos/Mutex.h index 34d5f58a41a..5a8761c6c2e 100644 --- a/rtos/Mutex.h +++ b/rtos/Mutex.h @@ -32,7 +32,6 @@ #include "platform/mbed_toolchain.h" namespace rtos { -/** \ingroup mbed-os-public */ /** \addtogroup rtos-public-api */ /** @{*/ diff --git a/rtos/Queue.h b/rtos/Queue.h index 156db29d7c9..4f98b1c3887 100644 --- a/rtos/Queue.h +++ b/rtos/Queue.h @@ -31,9 +31,9 @@ #if MBED_CONF_RTOS_PRESENT || defined(DOXYGEN_ONLY) namespace rtos { -/** \ingroup mbed-os-public */ /** \addtogroup rtos-public-api */ /** @{*/ + /** * \defgroup rtos_Queue Queue class * @{ diff --git a/rtos/RtosTimer.h b/rtos/RtosTimer.h index 3628722ef57..9b11a4183ba 100644 --- a/rtos/RtosTimer.h +++ b/rtos/RtosTimer.h @@ -33,9 +33,9 @@ #if MBED_CONF_RTOS_PRESENT || defined(DOXYGEN_ONLY) namespace rtos { -/** \ingroup mbed-os-public */ /** \addtogroup rtos-public-api */ /** @{*/ + /** * \defgroup rtos_RtosTimer RtosTimer class * @{ diff --git a/rtos/Semaphore.h b/rtos/Semaphore.h index f3dba32ec76..11246e5986a 100644 --- a/rtos/Semaphore.h +++ b/rtos/Semaphore.h @@ -30,9 +30,9 @@ #include "platform/NonCopyable.h" namespace rtos { -/** \ingroup mbed-os-public */ /** \addtogroup rtos-public-api */ /** @{*/ + /** * \defgroup rtos_Semaphore Semaphore class * @{ diff --git a/rtos/ThisThread.h b/rtos/ThisThread.h index f4dbc4ace00..abda8026d70 100644 --- a/rtos/ThisThread.h +++ b/rtos/ThisThread.h @@ -26,9 +26,9 @@ #include "rtos/mbed_rtos_types.h" namespace rtos { -/** \ingroup mbed-os-public */ /** \addtogroup rtos-public-api */ /** @{*/ + /** * \defgroup rtos_ThisThread ThisThread namespace * @{ @@ -185,7 +185,11 @@ const char *get_name(); /** @}*/ /** @}*/ + namespace internal { +/** \addtogroup rtos-internal-api */ +/** @{*/ + struct flags_check_capture { uint32_t *flags; uint32_t options; @@ -197,5 +201,6 @@ struct flags_check_capture { bool non_rtos_check_flags(void *handle); } +/** @}*/ } #endif diff --git a/rtos/Thread.h b/rtos/Thread.h index 3d90b76e235..edffa257f39 100644 --- a/rtos/Thread.h +++ b/rtos/Thread.h @@ -35,9 +35,9 @@ #if MBED_CONF_RTOS_PRESENT || defined(DOXYGEN_ONLY) || defined(UNITTEST) namespace rtos { -/** \ingroup mbed-os-public */ /** \addtogroup rtos-public-api */ /** @{*/ + /** * \defgroup rtos_Thread Thread class * @{ diff --git a/rtos/mbed_rtos_storage.h b/rtos/mbed_rtos_storage.h index 58eb8f40628..750725dc4e6 100644 --- a/rtos/mbed_rtos_storage.h +++ b/rtos/mbed_rtos_storage.h @@ -24,5 +24,3 @@ #endif #endif - -/** @}*/ diff --git a/rtos/mbed_rtos_types.h b/rtos/mbed_rtos_types.h index 3584b6dece8..eaf5da0e3d9 100644 --- a/rtos/mbed_rtos_types.h +++ b/rtos/mbed_rtos_types.h @@ -25,6 +25,9 @@ extern "C" { #endif +/** \addtogroup rtos-public-api */ +/** @{*/ + /* Minimal definitions for bare metal form of RTOS */ // Timeout value. @@ -65,6 +68,8 @@ typedef void *osThreadId_t; // \return thread flags after setting or error code if highest bit set. uint32_t osThreadFlagsSet(osThreadId_t thread_id, uint32_t flags); +/** @}*/ + #ifdef __cplusplus } #endif @@ -72,5 +77,4 @@ uint32_t osThreadFlagsSet(osThreadId_t thread_id, uint32_t flags); #endif - #endif /* RTOS_TYPES_H_ */ diff --git a/rtos/rtos.h b/rtos/rtos.h index 22bc2318a94..7987712a985 100644 --- a/rtos/rtos.h +++ b/rtos/rtos.h @@ -36,12 +36,13 @@ #include "rtos/EventFlags.h" #include "rtos/ConditionVariable.h" -/** \ingroup mbed-os-public */ -/** \addtogroup rtos-public-api */ -/** @{*/ + +/** \defgroup rtos-public-api RTOS + * \ingroup mbed-os-public + */ + #ifndef MBED_NO_GLOBAL_USING_DIRECTIVE using namespace rtos; #endif -/** @}*/ #endif diff --git a/rtos/source/TARGET_CORTEX/mbed_boot.h b/rtos/source/TARGET_CORTEX/mbed_boot.h index 1be08b59a19..e7be74f1ead 100644 --- a/rtos/source/TARGET_CORTEX/mbed_boot.h +++ b/rtos/source/TARGET_CORTEX/mbed_boot.h @@ -25,7 +25,6 @@ extern "C" { #include "mbed_rtx.h" -/** \ingroup mbed-os-internal */ /** \addtogroup rtos-internal-api */ /** @{*/ diff --git a/rtos/source/rtos_handlers.h b/rtos/source/rtos_handlers.h index 62b7d545bf6..15e1b7a372a 100644 --- a/rtos/source/rtos_handlers.h +++ b/rtos/source/rtos_handlers.h @@ -28,12 +28,13 @@ extern "C" { #endif -/** \ingroup mbed-os-internal */ -/** \addtogroup rtos-internal-api RTOS */ -/** @{*/ +/** \defgroup rtos-internal-api RTOS + * \ingroup mbed-os-internal + */ /** * \defgroup rtos_handlers RTOS hook functions + * \ingroup rtos-internal-api * @{ */ /** @@ -43,7 +44,6 @@ extern "C" { */ void rtos_attach_thread_terminate_hook(void (*fptr)(osThreadId_t id)); /** @}*/ -/** @}*/ #ifdef __cplusplus } diff --git a/rtos/source/rtos_idle.h b/rtos/source/rtos_idle.h index 447f68a9d32..b0c2984b81d 100644 --- a/rtos/source/rtos_idle.h +++ b/rtos/source/rtos_idle.h @@ -28,8 +28,6 @@ extern "C" { #endif - -/** \ingroup mbed-os-internal */ /** \addtogroup rtos-internal-api */ /** @{*/ diff --git a/tools/test/travis-ci/doxy-spellchecker/ignore.en.pws b/tools/test/travis-ci/doxy-spellchecker/ignore.en.pws index ac5dbcc7717..0352460d147 100644 --- a/tools/test/travis-ci/doxy-spellchecker/ignore.en.pws +++ b/tools/test/travis-ci/doxy-spellchecker/ignore.en.pws @@ -109,4 +109,5 @@ xmit pppd pppdebug ppp +api _doxy_ From 0f12e65b9cd5e545332848def9ee1458d3383f88 Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Tue, 10 Sep 2019 14:24:48 +0200 Subject: [PATCH 062/227] STM license file update Some code have been copied from ST Cube deliveries. ST copyright is then needed. --- targets/TARGET_STM/TARGET_STM32F0/flash_api.c | 2 ++ targets/TARGET_STM/TARGET_STM32F1/flash_api.c | 2 ++ targets/TARGET_STM/TARGET_STM32F2/flash_api.c | 2 ++ targets/TARGET_STM/TARGET_STM32F3/flash_api.c | 2 ++ targets/TARGET_STM/TARGET_STM32F4/flash_api.c | 36 +++++++------------ targets/TARGET_STM/TARGET_STM32F7/flash_api.c | 36 +++++++------------ targets/TARGET_STM/TARGET_STM32H7/flash_api.c | 36 +++++++------------ targets/TARGET_STM/TARGET_STM32L0/flash_api.c | 2 ++ targets/TARGET_STM/TARGET_STM32L1/flash_api.c | 2 ++ targets/TARGET_STM/TARGET_STM32L4/flash_api.c | 2 ++ targets/TARGET_STM/TARGET_STM32WB/flash_api.c | 1 + 11 files changed, 51 insertions(+), 72 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32F0/flash_api.c b/targets/TARGET_STM/TARGET_STM32F0/flash_api.c index 7b74c559883..8ed1709a1ce 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32F0/flash_api.c @@ -1,5 +1,7 @@ /* mbed Microcontroller Library * Copyright (c) 2017 ARM Limited + * Copyright (c) 2017 STMicroelectronics + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/targets/TARGET_STM/TARGET_STM32F1/flash_api.c b/targets/TARGET_STM/TARGET_STM32F1/flash_api.c index 2dd57c45281..8fdb457332d 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32F1/flash_api.c @@ -1,5 +1,7 @@ /* mbed Microcontroller Library * Copyright (c) 2017 ARM Limited + * Copyright (c) 2017 STMicroelectronics + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/targets/TARGET_STM/TARGET_STM32F2/flash_api.c b/targets/TARGET_STM/TARGET_STM32F2/flash_api.c index b5e05aa782f..421d6bcc435 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32F2/flash_api.c @@ -1,5 +1,7 @@ /* mbed Microcontroller Library * Copyright (c) 2017 ARM Limited + * Copyright (c) 2017 STMicroelectronics + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/targets/TARGET_STM/TARGET_STM32F3/flash_api.c b/targets/TARGET_STM/TARGET_STM32F3/flash_api.c index 7b74c559883..8ed1709a1ce 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32F3/flash_api.c @@ -1,5 +1,7 @@ /* mbed Microcontroller Library * Copyright (c) 2017 ARM Limited + * Copyright (c) 2017 STMicroelectronics + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/targets/TARGET_STM/TARGET_STM32F4/flash_api.c b/targets/TARGET_STM/TARGET_STM32F4/flash_api.c index b9334c32d1d..6c366bba948 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32F4/flash_api.c @@ -1,31 +1,19 @@ /* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2017, STMicroelectronics - * All rights reserved. + * Copyright (c) 2017 ARM Limited + * Copyright (c) 2017 STMicroelectronics + * SPDX-License-Identifier: Apache-2.0 * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. + * http://www.apache.org/licenses/LICENSE-2.0 * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. */ #if DEVICE_FLASH diff --git a/targets/TARGET_STM/TARGET_STM32F7/flash_api.c b/targets/TARGET_STM/TARGET_STM32F7/flash_api.c index 19c0f38b4c2..7b6bfeac8ec 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32F7/flash_api.c @@ -1,31 +1,19 @@ /* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2017, STMicroelectronics - * All rights reserved. + * Copyright (c) 2017 ARM Limited + * Copyright (c) 2017 STMicroelectronics + * SPDX-License-Identifier: Apache-2.0 * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. + * http://www.apache.org/licenses/LICENSE-2.0 * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. */ #if DEVICE_FLASH diff --git a/targets/TARGET_STM/TARGET_STM32H7/flash_api.c b/targets/TARGET_STM/TARGET_STM32H7/flash_api.c index 8e54ad1c1ef..1bd2e96847e 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32H7/flash_api.c @@ -1,31 +1,19 @@ /* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2018, STMicroelectronics - * All rights reserved. + * Copyright (c) 2017 ARM Limited + * Copyright (c) 2017 STMicroelectronics + * SPDX-License-Identifier: Apache-2.0 * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. + * http://www.apache.org/licenses/LICENSE-2.0 * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. */ #if DEVICE_FLASH diff --git a/targets/TARGET_STM/TARGET_STM32L0/flash_api.c b/targets/TARGET_STM/TARGET_STM32L0/flash_api.c index 2b954656ed1..0ed01d1425e 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32L0/flash_api.c @@ -1,5 +1,7 @@ /* mbed Microcontroller Library * Copyright (c) 2017 ARM Limited + * Copyright (c) 2017 STMicroelectronics + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/targets/TARGET_STM/TARGET_STM32L1/flash_api.c b/targets/TARGET_STM/TARGET_STM32L1/flash_api.c index 678cc43ea1a..cae36c8c0ba 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32L1/flash_api.c @@ -1,5 +1,7 @@ /* mbed Microcontroller Library * Copyright (c) 2017 ARM Limited + * Copyright (c) 2017 STMicroelectronics + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/targets/TARGET_STM/TARGET_STM32L4/flash_api.c b/targets/TARGET_STM/TARGET_STM32L4/flash_api.c index fe2a44c5023..534894f08a9 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32L4/flash_api.c @@ -1,5 +1,7 @@ /* mbed Microcontroller Library * Copyright (c) 2017 ARM Limited + * Copyright (c) 2017 STMicroelectronics + * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/targets/TARGET_STM/TARGET_STM32WB/flash_api.c b/targets/TARGET_STM/TARGET_STM32WB/flash_api.c index eb63c331424..3be8ad92486 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32WB/flash_api.c @@ -1,5 +1,6 @@ /* mbed Microcontroller Library * Copyright (c) 2019 ARM Limited + * Copyright (c) 2019 STMicroelectronics * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); From 442af0840917bc1260b67ee1287283a457c81eab Mon Sep 17 00:00:00 2001 From: int_szyk Date: Tue, 10 Sep 2019 12:34:47 +0200 Subject: [PATCH 063/227] Coverity changes in USBHID.cpp --- drivers/source/usb/USBHID.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/source/usb/USBHID.cpp b/drivers/source/usb/USBHID.cpp index 1518e2a578a..47738db6a87 100644 --- a/drivers/source/usb/USBHID.cpp +++ b/drivers/source/usb/USBHID.cpp @@ -145,6 +145,9 @@ void USBHID::_init(uint8_t output_report_length, uint8_t input_report_length) _read_idle = true; _output_length = output_report_length; _input_length = input_report_length; + reportLength = 0; + _input_report.length = 0; + _output_report.length = 0; } bool USBHID::ready() From d564897cf93febbd9329c7b8f5ff6bce19c2e347 Mon Sep 17 00:00:00 2001 From: Maciej Bocianski Date: Tue, 10 Sep 2019 09:42:58 +0200 Subject: [PATCH 064/227] add missing asserts to UserAllocatedEvent class Improves code quality by adding MBED_ASSERT to UserAllocatedEvent::delay and UserAllocatedEvent::period function. This prevent changing already posted event. --- events/UserAllocatedEvent.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/events/UserAllocatedEvent.h b/events/UserAllocatedEvent.h index 225ee895548..26a2b5b90c7 100644 --- a/events/UserAllocatedEvent.h +++ b/events/UserAllocatedEvent.h @@ -214,6 +214,7 @@ class UserAllocatedEvent { */ void delay(int delay) { + MBED_ASSERT(!_post_ref); equeue_event_delay(&_e + 1, delay); } @@ -223,6 +224,7 @@ class UserAllocatedEvent { */ void period(int period) { + MBED_ASSERT(!_post_ref); equeue_event_period(&_e + 1, period); } From b65e5e84df9aa9751071cea7d9dc8d882d2a0795 Mon Sep 17 00:00:00 2001 From: Michal Paszta Date: Mon, 9 Sep 2019 08:03:26 +0300 Subject: [PATCH 065/227] Enable async serial for K66F Added DMA definitions and usage for UART, based on K64F's code. --- .../TARGET_K66F/dma_reqs.h | 62 +++ .../TARGET_K66F/serial_api.c | 504 ++++++++++++++++-- targets/targets.json | 1 + 3 files changed, 524 insertions(+), 43 deletions(-) create mode 100644 targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/dma_reqs.h diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/dma_reqs.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/dma_reqs.h new file mode 100644 index 00000000000..b48de64f366 --- /dev/null +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/dma_reqs.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _FSL_DMA_REQS_H_ +#define _FSL_DMA_REQS_H_ + +#include "fsl_common.h" + +/* Array for DSPI DMA TX requests */ +#define SPI_DMA_TX_REQUEST_NUMBERS \ + { \ + kDmaRequestMux0SPI0Tx, kDmaRequestMux0SPI1Tx \ + } + +/* Array for DSPI DMA RX requests */ +#define SPI_DMA_RX_REQUEST_NUMBERS \ + { \ + kDmaRequestMux0SPI0Rx, kDmaRequestMux0SPI1Rx \ + } + +/* Array for UART DMA TX requests */ +#define UART_DMA_TX_REQUEST_NUMBERS \ + { \ + kDmaRequestMux0UART0Tx, kDmaRequestMux0UART1Tx, kDmaRequestMux0UART2Tx, \ + kDmaRequestMux0UART3Tx, kDmaRequestMux0UART4 \ + } + +/* Array for UART DMA RX requests */ +#define UART_DMA_RX_REQUEST_NUMBERS \ + { \ + kDmaRequestMux0UART0Rx, kDmaRequestMux0UART1Rx, kDmaRequestMux0UART2Rx, \ + kDmaRequestMux0UART3Rx, kDmaRequestMux0UART4 \ + } + +#endif /* _FSL_DMA_REQS_H_ */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/serial_api.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/serial_api.c index d1435ab40e6..0981d560584 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/serial_api.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/serial_api.c @@ -24,10 +24,12 @@ #include #include "cmsis.h" +#include "mbed_power_mgmt.h" #include "pinmap.h" #include "fsl_uart.h" #include "peripheral_clock_defines.h" #include "PeripheralPins.h" +#include "dma_reqs.h" #include "fsl_clock_config.h" static uint32_t serial_irq_ids[FSL_FEATURE_SOC_UART_COUNT] = {0}; @@ -37,6 +39,12 @@ static UART_Type *const uart_addrs[] = UART_BASE_PTRS; /* Array of UART bus clock frequencies */ static clock_name_t const uart_clocks[] = UART_CLOCK_FREQS; +/* UART transfer states */ +#define kUART_TxIdle 0 +#define kUART_TxBusy 1 +#define kUART_RxIdle 2 +#define kUART_RxBusy 3 + int stdio_uart_inited = 0; serial_t stdio_uart; @@ -44,8 +52,8 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) { uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX); uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX); - obj->index = pinmap_merge(uart_tx, uart_rx); - MBED_ASSERT((int)obj->index != NC); + obj->serial.index = pinmap_merge(uart_tx, uart_rx); + MBED_ASSERT((int)obj->serial.index != NC); uart_config_t config; @@ -54,40 +62,47 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) config.enableTx = false; config.enableRx = false; - UART_Init(uart_addrs[obj->index], &config, CLOCK_GetFreq(uart_clocks[obj->index])); + UART_Init(uart_addrs[obj->serial.index], &config, CLOCK_GetFreq(uart_clocks[obj->serial.index])); pinmap_pinout(tx, PinMap_UART_TX); pinmap_pinout(rx, PinMap_UART_RX); if (tx != NC) { - UART_EnableTx(uart_addrs[obj->index], true); + UART_EnableTx(uart_addrs[obj->serial.index], true); pin_mode(tx, PullUp); } if (rx != NC) { - UART_EnableRx(uart_addrs[obj->index], true); + UART_EnableRx(uart_addrs[obj->serial.index], true); pin_mode(rx, PullUp); } - if (obj->index == STDIO_UART) { + if (obj->serial.index == STDIO_UART) { stdio_uart_inited = 1; memcpy(&stdio_uart, obj, sizeof(serial_t)); } + + obj->serial.uartDmaRx.dmaUsageState = DMA_USAGE_OPPORTUNISTIC;; + obj->serial.txstate = kUART_TxIdle; + obj->serial.rxstate = kUART_RxIdle; + + /* Zero the handle. */ + memset(&(obj->serial.uart_transfer_handle), 0, sizeof(obj->serial.uart_transfer_handle)); } void serial_free(serial_t *obj) { - UART_Deinit(uart_addrs[obj->index]); - serial_irq_ids[obj->index] = 0; + UART_Deinit(uart_addrs[obj->serial.index]); + serial_irq_ids[obj->serial.index] = 0; } void serial_baud(serial_t *obj, int baudrate) { - UART_SetBaudRate(uart_addrs[obj->index], (uint32_t)baudrate, CLOCK_GetFreq(uart_clocks[obj->index])); + UART_SetBaudRate(uart_addrs[obj->serial.index], (uint32_t)baudrate, CLOCK_GetFreq(uart_clocks[obj->serial.index])); } void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { - UART_Type *base = uart_addrs[obj->index]; + UART_Type *base = uart_addrs[obj->serial.index]; uint8_t temp; /* Set bit count and parity mode. */ temp = base->C1 & ~(UART_C1_PE_MASK | UART_C1_PT_MASK | UART_C1_M_MASK); @@ -163,10 +178,11 @@ void uart4_irq() uint32_t status_flags = UART4->S1; uart_irq((status_flags & UART_S1_TDRE_MASK), (status_flags & UART_S1_RDRF_MASK), 4); } + void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { irq_handler = handler; - serial_irq_ids[obj->index] = id; + serial_irq_ids[obj->serial.index] = id; } void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) @@ -174,7 +190,7 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) IRQn_Type uart_irqs[] = UART_RX_TX_IRQS; uint32_t vector = 0; - switch (obj->index) { + switch (obj->serial.index) { case 0: vector = (uint32_t)&uart0_irq; break; @@ -197,42 +213,42 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) if (enable) { switch (irq) { case RxIrq: - UART_EnableInterrupts(uart_addrs[obj->index], kUART_RxDataRegFullInterruptEnable); + UART_EnableInterrupts(uart_addrs[obj->serial.index], kUART_RxDataRegFullInterruptEnable); break; case TxIrq: - UART_EnableInterrupts(uart_addrs[obj->index], kUART_TxDataRegEmptyInterruptEnable); + UART_EnableInterrupts(uart_addrs[obj->serial.index], kUART_TxDataRegEmptyInterruptEnable); break; default: break; } - NVIC_SetVector(uart_irqs[obj->index], vector); - NVIC_EnableIRQ(uart_irqs[obj->index]); + NVIC_SetVector(uart_irqs[obj->serial.index], vector); + NVIC_EnableIRQ(uart_irqs[obj->serial.index]); } else { // disable int all_disabled = 0; SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq); switch (irq) { case RxIrq: - UART_DisableInterrupts(uart_addrs[obj->index], kUART_RxDataRegFullInterruptEnable); + UART_DisableInterrupts(uart_addrs[obj->serial.index], kUART_RxDataRegFullInterruptEnable); break; case TxIrq: - UART_DisableInterrupts(uart_addrs[obj->index], kUART_TxDataRegEmptyInterruptEnable); + UART_DisableInterrupts(uart_addrs[obj->serial.index], kUART_TxDataRegEmptyInterruptEnable); break; default: break; } switch (other_irq) { case RxIrq: - all_disabled = ((UART_GetEnabledInterrupts(uart_addrs[obj->index]) & kUART_RxDataRegFullInterruptEnable) == 0); + all_disabled = ((UART_GetEnabledInterrupts(uart_addrs[obj->serial.index]) & kUART_RxDataRegFullInterruptEnable) == 0); break; case TxIrq: - all_disabled = ((UART_GetEnabledInterrupts(uart_addrs[obj->index]) & kUART_TxDataRegEmptyInterruptEnable) == 0); + all_disabled = ((UART_GetEnabledInterrupts(uart_addrs[obj->serial.index]) & kUART_TxDataRegEmptyInterruptEnable) == 0); break; default: break; } if (all_disabled) - NVIC_DisableIRQ(uart_irqs[obj->index]); + NVIC_DisableIRQ(uart_irqs[obj->serial.index]); } } @@ -240,7 +256,7 @@ int serial_getc(serial_t *obj) { while (!serial_readable(obj)); uint8_t data; - data = UART_ReadByte(uart_addrs[obj->index]); + data = UART_ReadByte(uart_addrs[obj->serial.index]); return data; } @@ -248,22 +264,22 @@ int serial_getc(serial_t *obj) void serial_putc(serial_t *obj, int c) { while (!serial_writable(obj)); - UART_WriteByte(uart_addrs[obj->index], (uint8_t)c); + UART_WriteByte(uart_addrs[obj->serial.index], (uint8_t)c); } int serial_readable(serial_t *obj) { - uint32_t status_flags = UART_GetStatusFlags(uart_addrs[obj->index]); + uint32_t status_flags = UART_GetStatusFlags(uart_addrs[obj->serial.index]); if (status_flags & kUART_RxOverrunFlag) - UART_ClearStatusFlags(uart_addrs[obj->index], kUART_RxOverrunFlag); + UART_ClearStatusFlags(uart_addrs[obj->serial.index], kUART_RxOverrunFlag); return (status_flags & kUART_RxDataRegFullFlag); } int serial_writable(serial_t *obj) { - uint32_t status_flags = UART_GetStatusFlags(uart_addrs[obj->index]); + uint32_t status_flags = UART_GetStatusFlags(uart_addrs[obj->serial.index]); if (status_flags & kUART_RxOverrunFlag) - UART_ClearStatusFlags(uart_addrs[obj->index], kUART_RxOverrunFlag); + UART_ClearStatusFlags(uart_addrs[obj->serial.index], kUART_RxOverrunFlag); return (status_flags & kUART_TxDataRegEmptyFlag); } @@ -278,14 +294,36 @@ void serial_pinout_tx(PinName tx) void serial_break_set(serial_t *obj) { - uart_addrs[obj->index]->C2 |= UART_C2_SBK_MASK; + uart_addrs[obj->serial.index]->C2 |= UART_C2_SBK_MASK; } void serial_break_clear(serial_t *obj) { - uart_addrs[obj->index]->C2 &= ~UART_C2_SBK_MASK; + uart_addrs[obj->serial.index]->C2 &= ~UART_C2_SBK_MASK; +} + +const PinMap *serial_tx_pinmap() +{ + return PinMap_UART_TX; +} + +const PinMap *serial_rx_pinmap() +{ + return PinMap_UART_RX; +} + +const PinMap *serial_cts_pinmap() +{ + return PinMap_UART_CTS; +} + +const PinMap *serial_rts_pinmap() +{ + return PinMap_UART_RTS; } +#if DEVICE_SERIAL_FC + /* * Only hardware flow control is implemented in this API. */ @@ -294,24 +332,24 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi switch(type) { case FlowControlRTS: pinmap_pinout(rxflow, PinMap_UART_RTS); - uart_addrs[obj->index]->MODEM &= ~UART_MODEM_TXCTSE_MASK; - uart_addrs[obj->index]->MODEM |= UART_MODEM_RXRTSE_MASK; + uart_addrs[obj->serial.index]->MODEM &= ~UART_MODEM_TXCTSE_MASK; + uart_addrs[obj->serial.index]->MODEM |= UART_MODEM_RXRTSE_MASK; break; case FlowControlCTS: pinmap_pinout(txflow, PinMap_UART_CTS); - uart_addrs[obj->index]->MODEM &= ~UART_MODEM_RXRTSE_MASK; - uart_addrs[obj->index]->MODEM |= UART_MODEM_TXCTSE_MASK; + uart_addrs[obj->serial.index]->MODEM &= ~UART_MODEM_RXRTSE_MASK; + uart_addrs[obj->serial.index]->MODEM |= UART_MODEM_TXCTSE_MASK; break; case FlowControlRTSCTS: pinmap_pinout(rxflow, PinMap_UART_RTS); pinmap_pinout(txflow, PinMap_UART_CTS); - uart_addrs[obj->index]->MODEM |= UART_MODEM_TXCTSE_MASK | UART_MODEM_RXRTSE_MASK; + uart_addrs[obj->serial.index]->MODEM |= UART_MODEM_TXCTSE_MASK | UART_MODEM_RXRTSE_MASK; break; case FlowControlNone: - uart_addrs[obj->index]->MODEM &= ~(UART_MODEM_TXCTSE_MASK | UART_MODEM_RXRTSE_MASK); + uart_addrs[obj->serial.index]->MODEM &= ~(UART_MODEM_TXCTSE_MASK | UART_MODEM_RXRTSE_MASK); break; default: @@ -319,24 +357,404 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi } } -const PinMap *serial_tx_pinmap() +#endif + +static void serial_send_asynch(serial_t *obj) { - return PinMap_UART_TX; + uart_transfer_t sendXfer; + + /*Setup send transfer*/ + sendXfer.data = obj->tx_buff.buffer; + sendXfer.dataSize = obj->tx_buff.length; + + if (obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_ALLOCATED || + obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) { + UART_SendEDMA(uart_addrs[obj->serial.index], &obj->serial.uart_dma_handle, &sendXfer); + } else { + UART_TransferSendNonBlocking(uart_addrs[obj->serial.index], &obj->serial.uart_transfer_handle, &sendXfer); + } } -const PinMap *serial_rx_pinmap() +static void serial_receive_asynch(serial_t *obj) { - return PinMap_UART_RX; + uart_transfer_t receiveXfer; + + /*Setup send transfer*/ + receiveXfer.data = obj->rx_buff.buffer; + receiveXfer.dataSize = obj->rx_buff.length; + + if (obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_ALLOCATED || + obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) { + UART_ReceiveEDMA(uart_addrs[obj->serial.index], &obj->serial.uart_dma_handle, &receiveXfer); + } else { + UART_TransferReceiveNonBlocking(uart_addrs[obj->serial.index], &obj->serial.uart_transfer_handle, &receiveXfer, NULL); + } } -const PinMap *serial_cts_pinmap() +static bool serial_allocate_dma(serial_t *obj, uint32_t handler) { - return PinMap_UART_CTS; + dma_request_source_t dma_rx_requests[] = UART_DMA_RX_REQUEST_NUMBERS; + dma_request_source_t dma_tx_requests[] = UART_DMA_TX_REQUEST_NUMBERS; + edma_config_t userConfig; + + /* Allocate the UART RX DMA channel */ + obj->serial.uartDmaRx.dmaChannel = dma_channel_allocate(dma_rx_requests[obj->serial.index]); + if (obj->serial.uartDmaRx.dmaChannel == DMA_ERROR_OUT_OF_CHANNELS) { + return false; + } + + /* Allocate the UART TX DMA channel */ + obj->serial.uartDmaTx.dmaChannel = dma_channel_allocate(dma_tx_requests[obj->serial.index]); + if (obj->serial.uartDmaTx.dmaChannel == DMA_ERROR_OUT_OF_CHANNELS) { + dma_channel_free(obj->serial.uartDmaRx.dmaChannel); + return false; + } + + /* EDMA init*/ + /* + * userConfig.enableRoundRobinArbitration = false; + * userConfig.enableHaltOnError = true; + * userConfig.enableContinuousLinkMode = false; + * userConfig.enableDebugMode = false; + */ + EDMA_GetDefaultConfig(&userConfig); + + EDMA_Init(DMA0, &userConfig); + + memset(&(obj->serial.uartDmaTx.handle), 0, sizeof(obj->serial.uartDmaTx.handle)); + memset(&(obj->serial.uartDmaRx.handle), 0, sizeof(obj->serial.uartDmaRx.handle)); + + EDMA_CreateHandle(&(obj->serial.uartDmaRx.handle), DMA0, obj->serial.uartDmaRx.dmaChannel); + EDMA_CreateHandle(&(obj->serial.uartDmaTx.handle), DMA0, obj->serial.uartDmaTx.dmaChannel); + + UART_TransferCreateHandleEDMA(uart_addrs[obj->serial.index], &obj->serial.uart_dma_handle, (uart_edma_transfer_callback_t)handler, + NULL, &obj->serial.uartDmaTx.handle, &obj->serial.uartDmaRx.handle); + + return true; } -const PinMap *serial_rts_pinmap() +void serial_enable_dma(serial_t *obj, uint32_t handler, DMAUsage state) { - return PinMap_UART_RTS; + dma_init(); + + if (state == DMA_USAGE_ALWAYS && obj->serial.uartDmaRx.dmaUsageState != DMA_USAGE_ALLOCATED) { + /* Try to allocate channels */ + if (serial_allocate_dma(obj, handler)) { + obj->serial.uartDmaRx.dmaUsageState = DMA_USAGE_ALLOCATED; + } else { + obj->serial.uartDmaRx.dmaUsageState = state; + } + } else if (state == DMA_USAGE_OPPORTUNISTIC) { + if (obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_ALLOCATED) { + /* Channels have already been allocated previously by an ALWAYS state, so after this transfer, we will release them */ + obj->serial.uartDmaRx.dmaUsageState = DMA_USAGE_TEMPORARY_ALLOCATED; + } else { + /* Try to allocate channels */ + if (serial_allocate_dma(obj, handler)) { + obj->serial.uartDmaRx.dmaUsageState = DMA_USAGE_TEMPORARY_ALLOCATED; + } else { + obj->serial.uartDmaRx.dmaUsageState = state; + } + } + } else if (state == DMA_USAGE_NEVER) { + /* If channels are allocated, get rid of them */ + if (obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_ALLOCATED) { + dma_channel_free(obj->serial.uartDmaRx.dmaChannel); + dma_channel_free(obj->serial.uartDmaRx.dmaChannel); + } + obj->serial.uartDmaRx.dmaUsageState = DMA_USAGE_NEVER; + } +} + +void serial_enable_event(serial_t *obj, int event, uint8_t enable) +{ + // Keep track of the requested events. + if (enable) { + obj->serial.events |= event; + } else { + obj->serial.events &= ~event; + } +} + +static void serial_tx_buffer_set(serial_t *obj, void *tx, int tx_length, uint8_t width) { + (void)width; + + // Exit if a transmit is already on-going + if (serial_tx_active(obj)) { + return; + } + + obj->tx_buff.buffer = tx; + obj->tx_buff.length = tx_length; + obj->tx_buff.pos = 0; +} + +int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint) +{ + // Check that a buffer has indeed been set up + MBED_ASSERT(tx != (void*)0); + + if (tx_length == 0) return 0; + + if (serial_tx_active(obj)) { + return 0; + } + + // Set up buffer + serial_tx_buffer_set(obj, (void *)tx, tx_length, tx_width); + + // Set up events + serial_enable_event(obj, SERIAL_EVENT_TX_ALL, false); + serial_enable_event(obj, event, true); + + /* If using DMA, allocate channels only if they have not already been allocated */ + if (hint != DMA_USAGE_NEVER) { + /* User requested to transfer using DMA */ + serial_enable_dma(obj, handler, hint); + + /* Check if DMA setup was successful */ + if (obj->serial.uartDmaRx.dmaUsageState != DMA_USAGE_ALLOCATED && obj->serial.uartDmaRx.dmaUsageState != DMA_USAGE_TEMPORARY_ALLOCATED) { + /* Set up an interrupt transfer as DMA is unavailable */ + if (obj->serial.uart_transfer_handle.callback == 0) { + UART_TransferCreateHandle(uart_addrs[obj->serial.index], &obj->serial.uart_transfer_handle, (uart_transfer_callback_t)handler, NULL); + } + } + } else { + /* User requested to transfer using interrupts */ + /* Disable the DMA */ + serial_enable_dma(obj, handler, hint); + + /* Set up the interrupt transfer */ + if (obj->serial.uart_transfer_handle.callback == 0) { + UART_TransferCreateHandle(uart_addrs[obj->serial.index], &obj->serial.uart_transfer_handle, (uart_transfer_callback_t)handler, NULL); + } + } + + obj->serial.txstate = kUART_TxBusy; + + /* Start the transfer */ + serial_send_asynch(obj); + + /* Can't enter deep sleep as long as UART transmit is active */ + sleep_manager_lock_deep_sleep(); + + return 0; +} + +void serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t width) +{ + // We only support byte buffers for now + MBED_ASSERT(width == 8); + + if (serial_rx_active(obj)) return; + + obj->rx_buff.buffer = rx; + obj->rx_buff.length = rx_length; + obj->rx_buff.pos = 0; + + return; +} + +/* Character match is currently not supported */ +void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint) +{ + // Check that a buffer has indeed been set up + MBED_ASSERT(rx != (void*)0); + if (rx_length == 0) return; + + if (serial_rx_active(obj)) { + return; + } + + // Set up buffer + serial_rx_buffer_set(obj,(void*) rx, rx_length, rx_width); + + // Set up events + serial_enable_event(obj, SERIAL_EVENT_RX_ALL, false); + serial_enable_event(obj, event, true); + + //obj->char_match = char_match; + + /* If using DMA, allocate channels only if they have not already been allocated */ + if (hint != DMA_USAGE_NEVER) { + /* User requested to transfer using DMA */ + serial_enable_dma(obj, handler, hint); + + /* Check if DMA setup was successful */ + if (obj->serial.uartDmaRx.dmaUsageState != DMA_USAGE_ALLOCATED && obj->serial.uartDmaRx.dmaUsageState != DMA_USAGE_TEMPORARY_ALLOCATED) { + /* Set up an interrupt transfer as DMA is unavailable */ + if (obj->serial.uart_transfer_handle.callback == 0) { + UART_TransferCreateHandle(uart_addrs[obj->serial.index], &obj->serial.uart_transfer_handle, (uart_transfer_callback_t)handler, NULL); + } + } + + } else { + /* User requested to transfer using interrupts */ + /* Disable the DMA */ + serial_enable_dma(obj, handler, hint); + + /* Set up the interrupt transfer */ + if (obj->serial.uart_transfer_handle.callback == 0) { + UART_TransferCreateHandle(uart_addrs[obj->serial.index], &obj->serial.uart_transfer_handle, (uart_transfer_callback_t)handler, NULL); + } + } + + obj->serial.rxstate = kUART_RxBusy; + + /* Start the transfer */ + serial_receive_asynch(obj); + + /* Can't enter deep sleep as long as UART transfer is active */ + sleep_manager_lock_deep_sleep(); +} + +uint8_t serial_tx_active(serial_t *obj) +{ + if (obj->serial.txstate == kUART_TxIdle) { + return 0; + } + + return 1; +} + +uint8_t serial_rx_active(serial_t *obj) +{ + if (obj->serial.rxstate == kUART_RxIdle) { + return 0; + } + + return 1; +} + +int serial_irq_handler_asynch(serial_t *obj) +{ + int status = 0; + //uint8_t *buf = (uint8_t*)obj->rx_buff.buffer; + uint32_t status_flags = UART_GetStatusFlags(uart_addrs[obj->serial.index]); + + /* Determine whether the current scenario is DMA or IRQ, and act accordingly */ + if (obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_ALLOCATED || obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) { + /* DMA implementation */ + if ((obj->serial.txstate != kUART_TxIdle) && (obj->serial.uart_dma_handle.txState == kUART_TxIdle)) { + obj->serial.txstate = kUART_TxIdle; + status |= SERIAL_EVENT_TX_COMPLETE; + /* Transmit is complete, re-enable entry to deep sleep mode */ + sleep_manager_unlock_deep_sleep(); + } + + if ((obj->serial.rxstate != kUART_RxIdle) && (obj->serial.uart_dma_handle.rxState == kUART_RxIdle)) { + obj->serial.rxstate = kUART_RxIdle; + status |= SERIAL_EVENT_RX_COMPLETE; + /* Receive is complete, re-enable entry to deep sleep mode */ + sleep_manager_unlock_deep_sleep(); + } + + /* Release the dma channels if they were opportunistically allocated */ + if (obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) { + /* Ensure both TX and RX channels are idle before freeing them */ + if ((obj->serial.uart_dma_handle.txState == kUART_TxIdle) && (obj->serial.uart_dma_handle.rxState == kUART_RxIdle)) { + dma_channel_free(obj->serial.uartDmaRx.dmaChannel); + dma_channel_free(obj->serial.uartDmaTx.dmaChannel); + obj->serial.uartDmaRx.dmaUsageState = DMA_USAGE_OPPORTUNISTIC; + } + } + } else { + /* Interrupt implementation */ + if ((obj->serial.txstate != kUART_TxIdle) && (obj->serial.uart_transfer_handle.txState == kUART_TxIdle)) { + obj->serial.txstate = kUART_TxIdle; + status |= SERIAL_EVENT_TX_COMPLETE; + /* Transmit is complete, re-enable entry to deep sleep mode */ + sleep_manager_unlock_deep_sleep(); + } + + if ((obj->serial.rxstate != kUART_RxIdle) && (obj->serial.uart_transfer_handle.rxState == kUART_RxIdle)) { + obj->serial.rxstate = kUART_RxIdle; + status |= SERIAL_EVENT_RX_COMPLETE; + /* Receive is complete, re-enable entry to deep sleep mode */ + sleep_manager_unlock_deep_sleep(); + } + } +#if 0 + if (obj->char_match != SERIAL_RESERVED_CHAR_MATCH){ + /* Check for character match event */ + if (buf[obj->rx_buff.length - 1] == obj->char_match) { + status |= SERIAL_EVENT_RX_CHARACTER_MATCH; + } + } +#endif + + if (status_flags & kUART_RxOverrunFlag) { + UART_ClearStatusFlags(uart_addrs[obj->serial.index], kUART_RxOverrunFlag); + status |= SERIAL_EVENT_RX_OVERRUN_ERROR; + } + + if (status_flags & kUART_FramingErrorFlag) { + UART_ClearStatusFlags(uart_addrs[obj->serial.index], kUART_FramingErrorFlag); + status |= SERIAL_EVENT_RX_FRAMING_ERROR; + } + + if (status_flags & kUART_ParityErrorFlag) { + UART_ClearStatusFlags(uart_addrs[obj->serial.index], kUART_ParityErrorFlag); + status |= SERIAL_EVENT_RX_PARITY_ERROR; + } + + return status & obj->serial.events; +} + +void serial_tx_abort_asynch(serial_t *obj) +{ + // If we're not currently transferring, then there's nothing to do here + if (serial_tx_active(obj) == 0) { + return; + } + + if (obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_ALLOCATED || obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) { + UART_TransferAbortSendEDMA(uart_addrs[obj->serial.index], &obj->serial.uart_dma_handle); + /* Release the dma channels if they were opportunistically allocated */ + if (obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) { + /* Ensure both TX and RX channels are idle before freeing them */ + if ((obj->serial.uart_dma_handle.txState == kUART_TxIdle) && (obj->serial.uart_dma_handle.rxState == kUART_RxIdle)) { + dma_channel_free(obj->serial.uartDmaRx.dmaChannel); + dma_channel_free(obj->serial.uartDmaTx.dmaChannel); + obj->serial.uartDmaRx.dmaUsageState = DMA_USAGE_OPPORTUNISTIC; + } + } + } else { + UART_TransferAbortSend(uart_addrs[obj->serial.index], &obj->serial.uart_transfer_handle); + } + + obj->serial.txstate = kUART_TxIdle; + + /* Re-enable entry to deep sleep mode */ + sleep_manager_unlock_deep_sleep(); +} + +void serial_rx_abort_asynch(serial_t *obj) +{ + // If we're not currently transferring, then there's nothing to do here + if (serial_rx_active(obj) == 0) { + return; + } + + if (obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_ALLOCATED || obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) { + UART_TransferAbortReceiveEDMA(uart_addrs[obj->serial.index], &obj->serial.uart_dma_handle); + /* Release the dma channels if they were opportunistically allocated */ + if (obj->serial.uartDmaRx.dmaUsageState == DMA_USAGE_TEMPORARY_ALLOCATED) { + /* Ensure both TX and RX channels are idle before freeing them */ + if ((obj->serial.uart_dma_handle.txState == kUART_TxIdle) && (obj->serial.uart_dma_handle.rxState == kUART_RxIdle)) { + dma_channel_free(obj->serial.uartDmaRx.dmaChannel); + dma_channel_free(obj->serial.uartDmaTx.dmaChannel); + obj->serial.uartDmaRx.dmaUsageState = DMA_USAGE_OPPORTUNISTIC; + } + } + } else { + UART_TransferAbortReceive(uart_addrs[obj->serial.index], &obj->serial.uart_transfer_handle); + } + + obj->serial.rxstate = kUART_RxIdle; + + /* Re-enable entry to deep sleep mode */ + sleep_manager_unlock_deep_sleep(); } static int serial_is_enabled(uint32_t uart_index) diff --git a/targets/targets.json b/targets/targets.json index fbf927a9131..6c4470c6004 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -1813,6 +1813,7 @@ "PWMOUT", "SERIAL", "SERIAL_FC", + "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", From aff57777da9073cdb7dce9dab1a8a337177220a7 Mon Sep 17 00:00:00 2001 From: int_szyk Date: Tue, 10 Sep 2019 14:46:49 +0200 Subject: [PATCH 066/227] Coverity changes in USBDevice.cpp --- drivers/source/usb/USBDevice.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/source/usb/USBDevice.cpp b/drivers/source/usb/USBDevice.cpp index b8cc8dc607e..945deb69ecf 100644 --- a/drivers/source/usb/USBDevice.cpp +++ b/drivers/source/usb/USBDevice.cpp @@ -1272,6 +1272,7 @@ USBDevice::USBDevice(USBPhy *phy, uint16_t vendor_id, uint16_t product_id, uint1 _current_alternate = 0; _locked = 0; _post_process = NULL; + _max_packet_size_ep0 = 0; /* Set initial device state */ _device.state = Powered; From d904c3e1ee64c3b283afadb6dd5ea911f2da5363 Mon Sep 17 00:00:00 2001 From: jh228 <42536868+jh228@users.noreply.github.com> Date: Mon, 19 Aug 2019 09:52:44 +0900 Subject: [PATCH 067/227] Update gcc.py for preprocessing in linker script To fix https://github.com/ARMmbed/mbed-os/issues/11214, we need this update. :-) --- tools/toolchains/gcc.py | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/toolchains/gcc.py b/tools/toolchains/gcc.py index 29651e6737b..13a8ac744ea 100644 --- a/tools/toolchains/gcc.py +++ b/tools/toolchains/gcc.py @@ -248,6 +248,7 @@ def link(self, output, objects, libraries, lib_dirs, mem_map): preproc_output = join(dirname(output), ".link_script.ld") cmd = ( self.preproc + [mem_map] + self.ld[1:] + ["-o", preproc_output] + self.get_compile_options(self.get_symbols(), []) ) self.notify.cc_verbose("Preproc: %s" % ' '.join(cmd)) self.default_cmd(cmd) From 20461fec1947433c0020339849c4d179db8a7c1c Mon Sep 17 00:00:00 2001 From: jh228 <42536868+jh228@users.noreply.github.com> Date: Mon, 19 Aug 2019 15:09:04 +0900 Subject: [PATCH 068/227] Update gcc.py --- tools/toolchains/gcc.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/toolchains/gcc.py b/tools/toolchains/gcc.py index 13a8ac744ea..24568d7c528 100644 --- a/tools/toolchains/gcc.py +++ b/tools/toolchains/gcc.py @@ -247,7 +247,7 @@ def link(self, output, objects, libraries, lib_dirs, mem_map): if mem_map: preproc_output = join(dirname(output), ".link_script.ld") cmd = ( - self.preproc + [mem_map] + self.ld[1:] + ["-o", preproc_output] + self.preproc + [mem_map] + self.ld[1:] + ["-o", preproc_output] + self.get_compile_options(self.get_symbols(), []) ) self.notify.cc_verbose("Preproc: %s" % ' '.join(cmd)) From 08fe757f14072a7fd29b7727873c0968af9e3a3f Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Fri, 23 Aug 2019 16:57:04 +0200 Subject: [PATCH 069/227] STM32H743 files move --- .../TARGET_STM32H7/{TARGET_STM32H743xI => }/PeripheralNames.h | 0 .../{ => TARGET_STM32H743xI}/device/system_stm32h7xx.c | 0 .../TARGET_STM32H7/{TARGET_STM32H743xI => }/us_ticker_data.h | 0 3 files changed, 0 insertions(+), 0 deletions(-) rename targets/TARGET_STM/TARGET_STM32H7/{TARGET_STM32H743xI => }/PeripheralNames.h (100%) rename targets/TARGET_STM/TARGET_STM32H7/{ => TARGET_STM32H743xI}/device/system_stm32h7xx.c (100%) rename targets/TARGET_STM/TARGET_STM32H7/{TARGET_STM32H743xI => }/us_ticker_data.h (100%) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32H7/PeripheralNames.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/PeripheralNames.h rename to targets/TARGET_STM/TARGET_STM32H7/PeripheralNames.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/system_stm32h7xx.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/device/system_stm32h7xx.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/device/system_stm32h7xx.c rename to targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/device/system_stm32h7xx.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/us_ticker_data.h b/targets/TARGET_STM/TARGET_STM32H7/us_ticker_data.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/us_ticker_data.h rename to targets/TARGET_STM/TARGET_STM32H7/us_ticker_data.h From 46b310304af8d271d12af33714e25e83d668a52f Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Fri, 23 Aug 2019 17:00:59 +0200 Subject: [PATCH 070/227] STM32H747xI introduction --- .../TARGET_STM32H747xI/cmsis_nvic.h | 45 + .../TARGET_STM32H747xI/device/stm32h747xx.h | 30092 ++++++++++++++++ .../TARGET_STM32H747xI/flash_data.h | 67 + targets/TARGET_STM/mbed_rtx.h | 6 +- 4 files changed, 30209 insertions(+), 1 deletion(-) create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/cmsis_nvic.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/device/stm32h747xx.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/flash_data.h diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/cmsis_nvic.h new file mode 100644 index 00000000000..394411b70bb --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/cmsis_nvic.h @@ -0,0 +1,45 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 150 vectors = 600 bytes from 0x40 to 0x297 +// Total: 166 vectors = 664 bytes (0x298) to be reserved in RAM +#define NVIC_NUM_VECTORS 166 + +#ifdef CORE_CM7 +#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of DTCM RAM +#else +#define NVIC_RAM_VECTOR_ADDRESS 0x10000000 // Vectors positioned at start of D2 RAM (CM4) +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/device/stm32h747xx.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/device/stm32h747xx.h new file mode 100644 index 00000000000..280314f64cb --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/device/stm32h747xx.h @@ -0,0 +1,30092 @@ +/** + ****************************************************************************** + * @file stm32h747xx.h + * @author MCD Application Team + * @brief CMSIS STM32H747xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32h747xx + * @{ + */ + +#ifndef STM32H747xx_H +#define STM32H747xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32H7XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M Processor Exceptions Numbers *****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */ + PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1 and ADC2 global Interrupts */ + FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */ + FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */ + FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */ + FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + FDCAN_CAL_IRQn = 63, /*!< FDCAN Calibration unit Interrupt */ + CM7_SEV_IRQn = 64, /*!< CM7 Send event interrupt for CM4 */ + CM4_SEV_IRQn = 65, /*!< CM4 Send event interrupt for CM7 */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + RNG_IRQn = 80, /*!< RNG global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + UART7_IRQn = 82, /*!< UART7 global interrupt */ + UART8_IRQn = 83, /*!< UART8 global interrupt */ + SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ + SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ + SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ + SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ + LTDC_IRQn = 88, /*!< LTDC global Interrupt */ + LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ + DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */ + SAI2_IRQn = 91, /*!< SAI2 global Interrupt */ + QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */ + LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */ + CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */ + I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */ + I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */ + SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */ + OTG_FS_EP1_OUT_IRQn = 98, /*!< USB OTG HS2 global interrupt */ + OTG_FS_EP1_IN_IRQn = 99, /*!< USB OTG HS2 End Point 1 Out global interrupt */ + OTG_FS_WKUP_IRQn = 100, /*!< USB OTG HS2 End Point 1 In global interrupt */ + OTG_FS_IRQn = 101, /*!< USB OTG HS2 Wakeup through EXTI interrupt */ + DMAMUX1_OVR_IRQn = 102, /*! + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< Reserved, 0x028 */ + uint32_t RESERVED2; /*!< Reserved, 0x02C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x044 */ + uint32_t RESERVED4; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ +} ADC_TypeDef; + + +typedef struct +{ +__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ +uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ +__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ +__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */ +__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */ + +} ADC_Common_TypeDef; + +/** + * @brief VREFBUF + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */ + __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */ + __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */ + __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */ + __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */ + __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */ + __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */ + __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */ + __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */ + __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */ + __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */ + __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */ +} FDCAN_GlobalTypeDef; + +/** + * @brief TTFD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */ + __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */ + __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */ + __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */ + __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */ + __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */ + __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */ + __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */ + __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */ + __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */ + __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */ + __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */ + __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */ + __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */ + __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */ + __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */ + __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */ + __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */ + __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */ +} TTCAN_TypeDef; + +/** + * @brief FD Controller Area Network + */ + +typedef struct +{ + __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */ + __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */ + __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */ + __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */ + __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */ + __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */ +} FDCAN_ClockCalibrationUnit_TypeDef; + + +/** + * @brief Consumer Electronics Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +}CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ +} DFSDM_Channel_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t RESERVED4[11]; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register, Address offset: 0x34 */ + __IO uint32_t APB3FZ2; /*!< Debug MCU APB3FZ2 freeze register, Address offset: 0x38 */ + __IO uint32_t APB1LFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x3C */ + __IO uint32_t APB1LFZ2; /*!< Debug MCU APB1LFZ2 freeze register, Address offset: 0x40 */ + __IO uint32_t APB1HFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x44 */ + __IO uint32_t APB1HFZ2; /*!< Debug MCU APB1LFZ2 freeze register, Address offset: 0x48 */ + __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register, Address offset: 0x4C */ + __IO uint32_t APB2FZ2; /*!< Debug MCU APB2FZ2 freeze register, Address offset: 0x50 */ + __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register, Address offset: 0x54 */ + __IO uint32_t APB4FZ2; /*!< Debug MCU APB4FZ2 freeze register, Address offset: 0x58 */ + +}DBGMCU_TypeDef; +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */ + __IO uint32_t CM1AR; /*!< DMA channel x memory 1 address register */ +} BDMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} BDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */ +}DMAMUX_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< DMA Channel Status Register */ + __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */ +}DMAMUX_ChannelStatus_TypeDef; + +typedef struct +{ + __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */ +}DMAMUX_RequestGen_TypeDef; + +typedef struct +{ + __IO uint32_t RGSR; /*!< DMA Request Generator Status Register */ + __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register */ +}DMAMUX_RequestGenStatus_TypeDef; + +/** + * @brief MDMA Controller + */ +typedef struct +{ + __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x00 */ +}MDMA_TypeDef; + +typedef struct +{ + __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */ + __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */ + __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */ + __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */ + __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */ + __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */ + __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */ + __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */ + __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */ + __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */ + __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */ + uint32_t RESERVED0; /*!< Reserved, 0x68 */ + __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */ + __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */ +}MDMA_Channel_TypeDef; + +/** + * @brief DMA2D Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ +} DMA2D_TypeDef; + +/** + * @brief DSI Controller + */ + +typedef struct +{ + __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */ + __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */ + __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */ + __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */ + __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */ + __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */ + __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */ + uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */ + __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */ + __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */ + __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */ + __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */ + __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */ + __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */ + __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */ + __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */ + __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */ + __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */ + __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */ + __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */ + __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */ + __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */ + __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */ + __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */ + __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */ + __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */ + __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */ + __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */ + __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */ + __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */ + __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */ + __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */ + __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */ + __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */ + __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */ + __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */ + __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */ + __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */ + __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */ + uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */ + __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */ + uint32_t RESERVED3[8]; /*!< Reserved, 0xE0 - 0xFF */ + __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */ + uint32_t RESERVED4[2]; /*!< Reserved, 0x104 - 0x10B */ + __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */ + __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */ + uint32_t RESERVED5; /*!< Reserved, 0x114 */ + __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */ + uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */ + __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */ + __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */ + __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */ + __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */ + __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */ + __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */ + __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */ + __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */ + __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */ + __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */ + __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */ + uint32_t RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F */ + __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */ + uint32_t RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF */ + __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */ + __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */ + __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */ + __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */ + __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */ + uint32_t RESERVED9; /*!< Reserved, 0x414 */ + __IO uint32_t WPCR[5]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-0x42B */ + uint32_t RESERVED10; /*!< Reserved, 0x42C */ + __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */ +} DSI_TypeDef; + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACECR; + __IO uint32_t MACPFR; + __IO uint32_t MACWTR; + __IO uint32_t MACHT0R; + __IO uint32_t MACHT1R; + uint32_t RESERVED1[14]; + __IO uint32_t MACVTR; + uint32_t RESERVED2; + __IO uint32_t MACVHTR; + uint32_t RESERVED3; + __IO uint32_t MACVIR; + __IO uint32_t MACIVIR; + uint32_t RESERVED4[2]; + __IO uint32_t MACTFCR; + uint32_t RESERVED5[7]; + __IO uint32_t MACRFCR; + uint32_t RESERVED6[7]; + __IO uint32_t MACISR; + __IO uint32_t MACIER; + __IO uint32_t MACRXTXSR; + uint32_t RESERVED7; + __IO uint32_t MACPCSR; + __IO uint32_t MACRWKPFR; + uint32_t RESERVED8[2]; + __IO uint32_t MACLCSR; + __IO uint32_t MACLTCR; + __IO uint32_t MACLETR; + __IO uint32_t MAC1USTCR; + uint32_t RESERVED9[12]; + __IO uint32_t MACVR; + __IO uint32_t MACDR; + uint32_t RESERVED10; + __IO uint32_t MACHWF0R; + __IO uint32_t MACHWF1R; + __IO uint32_t MACHWF2R; + uint32_t RESERVED11[54]; + __IO uint32_t MACMDIOAR; + __IO uint32_t MACMDIODR; + uint32_t RESERVED12[2]; + __IO uint32_t MACARPAR; + uint32_t RESERVED13[59]; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; + uint32_t RESERVED14[248]; + __IO uint32_t MMCCR; + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; + uint32_t RESERVED15[14]; + __IO uint32_t MMCTSCGPR; + __IO uint32_t MMCTMCGPR; + int32_t RESERVED16[5]; + __IO uint32_t MMCTPCGR; + uint32_t RESERVED17[10]; + __IO uint32_t MMCRCRCEPR; + __IO uint32_t MMCRAEPR; + uint32_t RESERVED18[10]; + __IO uint32_t MMCRUPGR; + uint32_t RESERVED19[9]; + __IO uint32_t MMCTLPIMSTR; + __IO uint32_t MMCTLPITCR; + __IO uint32_t MMCRLPIMSTR; + __IO uint32_t MMCRLPITCR; + uint32_t RESERVED20[65]; + __IO uint32_t MACL3L4C0R; + __IO uint32_t MACL4A0R; + uint32_t RESERVED21[2]; + __IO uint32_t MACL3A0R0R; + __IO uint32_t MACL3A1R0R; + __IO uint32_t MACL3A2R0R; + __IO uint32_t MACL3A3R0R; + uint32_t RESERVED22[4]; + __IO uint32_t MACL3L4C1R; + __IO uint32_t MACL4A1R; + uint32_t RESERVED23[2]; + __IO uint32_t MACL3A0R1R; + __IO uint32_t MACL3A1R1R; + __IO uint32_t MACL3A2R1R; + __IO uint32_t MACL3A3R1R; + uint32_t RESERVED24[108]; + __IO uint32_t MACTSCR; + __IO uint32_t MACSSIR; + __IO uint32_t MACSTSR; + __IO uint32_t MACSTNR; + __IO uint32_t MACSTSUR; + __IO uint32_t MACSTNUR; + __IO uint32_t MACTSAR; + uint32_t RESERVED25; + __IO uint32_t MACTSSR; + uint32_t RESERVED26[3]; + __IO uint32_t MACTTSSNR; + __IO uint32_t MACTTSSSR; + uint32_t RESERVED27[2]; + __IO uint32_t MACACR; + uint32_t RESERVED28; + __IO uint32_t MACATSNR; + __IO uint32_t MACATSSR; + __IO uint32_t MACTSIACR; + __IO uint32_t MACTSEACR; + __IO uint32_t MACTSICNR; + __IO uint32_t MACTSECNR; + uint32_t RESERVED29[4]; + __IO uint32_t MACPPSCR; + uint32_t RESERVED30[3]; + __IO uint32_t MACPPSTTSR; + __IO uint32_t MACPPSTTNR; + __IO uint32_t MACPPSIR; + __IO uint32_t MACPPSWR; + uint32_t RESERVED31[12]; + __IO uint32_t MACPOCR; + __IO uint32_t MACSPI0R; + __IO uint32_t MACSPI1R; + __IO uint32_t MACSPI2R; + __IO uint32_t MACLMIR; + uint32_t RESERVED32[11]; + __IO uint32_t MTLOMR; + uint32_t RESERVED33[7]; + __IO uint32_t MTLISR; + uint32_t RESERVED34[55]; + __IO uint32_t MTLTQOMR; + __IO uint32_t MTLTQUR; + __IO uint32_t MTLTQDR; + uint32_t RESERVED35[8]; + __IO uint32_t MTLQICSR; + __IO uint32_t MTLRQOMR; + __IO uint32_t MTLRQMPOCR; + __IO uint32_t MTLRQDR; + uint32_t RESERVED36[177]; + __IO uint32_t DMAMR; + __IO uint32_t DMASBMR; + __IO uint32_t DMAISR; + __IO uint32_t DMADSR; + uint32_t RESERVED37[60]; + __IO uint32_t DMACCR; + __IO uint32_t DMACTCR; + __IO uint32_t DMACRCR; + uint32_t RESERVED38[2]; + __IO uint32_t DMACTDLAR; + uint32_t RESERVED39; + __IO uint32_t DMACRDLAR; + __IO uint32_t DMACTDTPR; + uint32_t RESERVED40; + __IO uint32_t DMACRDTPR; + __IO uint32_t DMACTDRLR; + __IO uint32_t DMACRDRLR; + __IO uint32_t DMACIER; + __IO uint32_t DMACRIWTR; +__IO uint32_t DMACSFCSR; + uint32_t RESERVED41; + __IO uint32_t DMACCATDR; + uint32_t RESERVED42; + __IO uint32_t DMACCARDR; + uint32_t RESERVED43; + __IO uint32_t DMACCATBR; + uint32_t RESERVED44; + __IO uint32_t DMACCARBR; + __IO uint32_t DMACSR; +uint32_t RESERVED45[2]; +__IO uint32_t DMACMFCR; +}ETH_TypeDef; +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ +__IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */ +__IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */ +__IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */ +__IO uint32_t D3PMR1; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */ +__IO uint32_t D3PCR1L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L) Address offset: 0x10 */ +__IO uint32_t D3PCR1H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H) Address offset: 0x14 */ +uint32_t RESERVED1[2]; /*!< Reserved, 0x18 to 0x1C */ +__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */ +__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */ +__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */ +__IO uint32_t D3PMR2; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */ +__IO uint32_t D3PCR2L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L) Address offset: 0x30 */ +__IO uint32_t D3PCR2H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */ +uint32_t RESERVED2[2]; /*!< Reserved, 0x38 to 0x3C */ +__IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */ +__IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */ +__IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */ +__IO uint32_t D3PMR3; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */ +__IO uint32_t D3PCR3L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */ +__IO uint32_t D3PCR3H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */ +uint32_t RESERVED3[10]; /*!< Reserved, 0x58 to 0x7C */ +__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x80 */ +__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x84 */ +__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x88 */ +uint32_t RESERVED4; /*!< Reserved, 0x8C */ +__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x90 */ +__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x94 */ +__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x98 */ +uint32_t RESERVED5; /*!< Reserved, 0x9C */ +__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0xA0 */ +__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0xA4 */ +__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */ +uint32_t RESERVED6[5]; /*!< Reserved, 0xAC to 0xBC */ +__IO uint32_t C2IMR1; /*!< EXTI Interrupt mask register, Address offset: 0xC0 */ +__IO uint32_t C2EMR1; /*!< EXTI Event mask register, Address offset: 0xC4 */ +__IO uint32_t C2PR1; /*!< EXTI Pending register, Address offset: 0xC8 */ +uint32_t RESERVED7; /*!< Reserved, 0xCC */ +__IO uint32_t C2IMR2; /*!< EXTI Interrupt mask register, Address offset: 0xD0 */ +__IO uint32_t C2EMR2; /*!< EXTI Event mask register, Address offset: 0xD4 */ +__IO uint32_t C2PR2; /*!< EXTI Pending register, Address offset: 0xD8 */ +uint32_t RESERVED8; /*!< Reserved, 0xDC */ +__IO uint32_t C2IMR3; /*!< EXTI Interrupt mask register, Address offset: 0xE0 */ +__IO uint32_t C2EMR3; /*!< EXTI Event mask register, Address offset: 0xE4 */ +__IO uint32_t C2PR3; /*!< EXTI Pending register, Address offset: 0xE8 */ + +}EXTI_TypeDef; + +typedef struct +{ +__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ +__IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */ +__IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x08 */ +uint32_t RESERVED1; /*!< Reserved, 0x0C */ +__IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */ +__IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */ +__IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x18 */ +uint32_t RESERVED2; /*!< Reserved, 0x1C */ +__IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ +__IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */ +__IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0x28 */ +}EXTI_Core_TypeDef; + + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR1; /*!< Flash Key Register for bank1, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< Flash Option Key Register, Address offset: 0x08 */ + __IO uint32_t CR1; /*!< Flash Control Register for bank1, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< Flash Status Register for bank1, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< Flash Control Register for bank1, Address offset: 0x14 */ + __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x18 */ + __IO uint32_t OPTSR_CUR; /*!< Flash Option Status Current Register, Address offset: 0x1C */ + __IO uint32_t OPTSR_PRG; /*!< Flash Option Status to Program Register, Address offset: 0x20 */ + __IO uint32_t OPTCCR; /*!< Flash Option Clear Control Register, Address offset: 0x24 */ + __IO uint32_t PRAR_CUR1; /*!< Flash Current Protection Address Register for bank1, Address offset: 0x28 */ + __IO uint32_t PRAR_PRG1; /*!< Flash Protection Address to Program Register for bank1, Address offset: 0x2C */ + __IO uint32_t SCAR_CUR1; /*!< Flash Current Secure Address Register for bank1, Address offset: 0x30 */ + __IO uint32_t SCAR_PRG1; /*!< Flash Secure Address to Program Register for bank1, Address offset: 0x34 */ + __IO uint32_t WPSN_CUR1; /*!< Flash Current Write Protection Register on bank1, Address offset: 0x38 */ + __IO uint32_t WPSN_PRG1; /*!< Flash Write Protection to Program Register on bank1, Address offset: 0x3C */ + __IO uint32_t BOOT7_CUR; /*!< Flash Current Boot Address for Pelican Core Register, Address offset: 0x40 */ + __IO uint32_t BOOT7_PRG; /*!< Flash Boot Address to Program for Pelican Core Register, Address offset: 0x44 */ + __IO uint32_t BOOT4_CUR; /*!< Flash Current Boot Address for M4 Core Register, Address offset: 0x48 */ + __IO uint32_t BOOT4_PRG; /*!< Flash Boot Address to Program for M4 Core Register, Address offset: 0x4C */ + __IO uint32_t CRCCR1; /*!< Flash CRC Control register For Bank1 Register , Address offset: 0x50 */ + __IO uint32_t CRCSADD1; /*!< Flash CRC Start Address Register for Bank1 , Address offset: 0x54 */ + __IO uint32_t CRCEADD1; /*!< Flash CRC End Address Register for Bank1 , Address offset: 0x58 */ + __IO uint32_t CRCDATA; /*!< Flash CRC Data Register for Bank1 , Address offset: 0x5C */ + __IO uint32_t ECC_FA1; /*!< Flash ECC Fail Address For Bank1 Register , Address offset: 0x60 */ + uint32_t RESERVED1[40]; /*!< Reserved, 0x64 to 0x100 */ + __IO uint32_t KEYR2; /*!< Flash Key Register for bank2, Address offset: 0x104 */ + uint32_t RESERVED2; /*!< Reserved, 0x108 */ + __IO uint32_t CR2; /*!< Flash Control Register for bank2, Address offset: 0x10C */ + __IO uint32_t SR2; /*!< Flash Status Register for bank2, Address offset: 0x110 */ + __IO uint32_t CCR2; /*!< Flash Status Register for bank2, Address offset: 0x114 */ + uint32_t RESERVED3[4]; /*!< Reserved, 0x118 to 0x124 */ + __IO uint32_t PRAR_CUR2; /*!< Flash Current Protection Address Register for bank2, Address offset: 0x128 */ + __IO uint32_t PRAR_PRG2; /*!< Flash Protection Address to Program Register for bank2, Address offset: 0x12C */ + __IO uint32_t SCAR_CUR2; /*!< Flash Current Secure Address Register for bank2, Address offset: 0x130 */ + __IO uint32_t SCAR_PRG2; /*!< Flash Secure Address Register for bank2, Address offset: 0x134 */ + __IO uint32_t WPSN_CUR2; /*!< Flash Current Write Protection Register on bank2, Address offset: 0x138 */ + __IO uint32_t WPSN_PRG2; /*!< Flash Write Protection to Program Register on bank2, Address offset: 0x13C */ + uint32_t RESERVED4[4]; /*!< Reserved, 0x140 to 0x14C */ + __IO uint32_t CRCCR2; /*!< Flash CRC Control register For Bank2 Register , Address offset: 0x150 */ + __IO uint32_t CRCSADD2; /*!< Flash CRC Start Address Register for Bank2 , Address offset: 0x154 */ + __IO uint32_t CRCEADD2; /*!< Flash CRC End Address Register for Bank2 , Address offset: 0x158 */ + __IO uint32_t CRCDATA2; /*!< Flash CRC Data Register for Bank2 , Address offset: 0x15C */ + __IO uint32_t ECC_FA2; /*!< Flash ECC Fail Address For Bank2 Register , Address offset: 0x160 */ +} FLASH_TypeDef; + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ + __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ + __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ + __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ + uint32_t RESERVED0; /*!< Reserved, 0x70 */ + __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ +} FMC_Bank2_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ + uint32_t RESERVED; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief Flexible Memory Controller Bank5 and 6 + */ + + +typedef struct +{ + __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ + __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ + __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ + __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ + __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ +} FMC_Bank5_6_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t HSOTR; /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x00 */ + __IO uint32_t PMCR; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t CFGR; /*!< SYSCFG configuration registers, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t CCCSR; /*!< SYSCFG compensation cell control/status register, Address offset: 0x20 */ + __IO uint32_t CCVR; /*!< SYSCFG compensation cell value register, Address offset: 0x24 */ + __IO uint32_t CCCR; /*!< SYSCFG compensation cell code register, Address offset: 0x28 */ + __IO uint32_t PWRCR; /*!< PWR control register, Address offset: 0x2C */ + uint32_t RESERVED3[61]; /*!< Reserved, 0x30-0x120 */ + __IO uint32_t PKGR; /*!< SYSCFG package register, Address offset: 0x124 */ + uint32_t RESERVED4[118]; /*!< Reserved, 0x128-0x2FC */ + __IO uint32_t UR0; /*!< SYSCFG user register 0, Address offset: 0x300 */ + __IO uint32_t UR1; /*!< SYSCFG user register 1, Address offset: 0x304 */ + __IO uint32_t UR2; /*!< SYSCFG user register 2, Address offset: 0x308 */ + __IO uint32_t UR3; /*!< SYSCFG user register 3, Address offset: 0x30C */ + __IO uint32_t UR4; /*!< SYSCFG user register 4, Address offset: 0x310 */ + __IO uint32_t UR5; /*!< SYSCFG user register 5, Address offset: 0x314 */ + __IO uint32_t UR6; /*!< SYSCFG user register 6, Address offset: 0x318 */ + __IO uint32_t UR7; /*!< SYSCFG user register 7, Address offset: 0x31C */ + __IO uint32_t UR8; /*!< SYSCFG user register 8, Address offset: 0x320 */ + __IO uint32_t UR9; /*!< SYSCFG user register 9, Address offset: 0x324 */ + __IO uint32_t UR10; /*!< SYSCFG user register 10, Address offset: 0x328 */ + __IO uint32_t UR11; /*!< SYSCFG user register 11, Address offset: 0x32C */ + __IO uint32_t UR12; /*!< SYSCFG user register 12, Address offset: 0x330 */ + __IO uint32_t UR13; /*!< SYSCFG user register 13, Address offset: 0x334 */ + __IO uint32_t UR14; /*!< SYSCFG user register 14, Address offset: 0x338 */ + __IO uint32_t UR15; /*!< SYSCFG user register 15, Address offset: 0x33C */ + __IO uint32_t UR16; /*!< SYSCFG user register 16, Address offset: 0x340 */ + __IO uint32_t UR17; /*!< SYSCFG user register 17, Address offset: 0x344 */ + +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ + uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ + uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ + uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */ + +} JPEG_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CSR1; /*!< PWR power control status register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */ + __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x0C */ + __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */ + __IO uint32_t CPU2CR; /*!< PWR CPU2 control register, Address offset: 0x14 */ + __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t WKUPCR; /*!< PWR wakeup clear register, Address offset: 0x20 */ + __IO uint32_t WKUPFR; /*!< PWR wakeup flag register, Address offset: 0x24 */ + __IO uint32_t WKUPEPR; /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t HSICFGR; /*!< HSI Clock Calibration Register, Address offset: 0x04 */ + __IO uint32_t CRRCR; /*!< Clock Recovery RC Register, Address offset: 0x08 */ + __IO uint32_t CSICFGR; /*!< CSI Clock Calibration Register, Address offset: 0x0C */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t D1CFGR; /*!< RCC Domain 1 configuration register, Address offset: 0x18 */ + __IO uint32_t D2CFGR; /*!< RCC Domain 2 configuration register, Address offset: 0x1C */ + __IO uint32_t D3CFGR; /*!< RCC Domain 3 configuration register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t PLLCKSELR; /*!< RCC PLLs Clock Source Selection Register, Address offset: 0x28 */ + __IO uint32_t PLLCFGR; /*!< RCC PLLs Configuration Register, Address offset: 0x2C */ + __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register, Address offset: 0x30 */ + __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register, Address offset: 0x34 */ + __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register, Address offset: 0x38 */ + __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register, Address offset: 0x3C */ + __IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register, Address offset: 0x40 */ + __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register, Address offset: 0x44 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */ + __IO uint32_t D1CCIPR; /*!< RCC Domain 1 Kernel Clock Configuration Register Address offset: 0x4C */ + __IO uint32_t D2CCIP1R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x50 */ + __IO uint32_t D2CCIP2R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x54 */ + __IO uint32_t D3CCIPR; /*!< RCC Domain 3 Kernel Clock Configuration Register Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t CIER; /*!< RCC Clock Source Interrupt Enable Register Address offset: 0x60 */ + __IO uint32_t CIFR; /*!< RCC Clock Source Interrupt Flag Register Address offset: 0x64 */ + __IO uint32_t CICR; /*!< RCC Clock Source Interrupt Clear Register Address offset: 0x68 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x6C */ + __IO uint32_t BDCR; /*!< RCC Vswitch Backup Domain Control Register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x78 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x7C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x80 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x84 */ + __IO uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x88 */ + __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x8C */ + __IO uint32_t APB1LRSTR; /*!< RCC APB1 peripheral reset Low Word register, Address offset: 0x90 */ + __IO uint32_t APB1HRSTR; /*!< RCC APB1 peripheral reset High Word register, Address offset: 0x94 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x98 */ + __IO uint32_t APB4RSTR; /*!< RCC APB4 peripheral reset register, Address offset: 0x9C */ + __IO uint32_t GCR; /*!< RCC RCC Global Control Register, Address offset: 0xA0 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0xA4 */ + __IO uint32_t D3AMR; /*!< RCC Domain 3 Autonomous Mode Register, Address offset: 0xA8 */ + uint32_t RESERVED11[9]; /*!< Reserved, 0xAC-0xCC Address offset: 0xAC */ + __IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0xD0 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0xD4 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0xD8 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0xDC */ + __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0xE0 */ + __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0xE4 */ + __IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0xE8 */ + __IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0xEC */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0xF0 */ + __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0xF4 */ + uint32_t RESERVED12; /*!< Reserved, Address offset: 0xF8 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0xFC */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x100 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x104 */ + __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x108 */ + __IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x10C */ + __IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x110 */ + __IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x114 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x118 */ + __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x11C */ + uint32_t RESERVED13[4]; /*!< Reserved, 0x120-0x12C Address offset: 0x120 */ + +} RCC_TypeDef; + +typedef struct +{ + __IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0x00 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x04 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x08 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x0C */ + __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0x10 */ + __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0x14 */ + __IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0x18 */ + __IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0x1C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0x20 */ + __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0x24 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0x3C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x40 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x44 */ + __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x48 */ + __IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x4C */ + __IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x50 */ + __IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x54 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x58 */ + __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x5C */ + uint32_t RESERVED10[4]; /*!< Reserved, 0x60-0x6C Address offset: 0x60 */ + +} RCC_Core_TypeDef; + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ + __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ + __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ + __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ + __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ + __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ + __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ + __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ + __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ + __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ + __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ + __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ + __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ +} RTC_TypeDef; + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief SPDIF-RX Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ + __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ + __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ + __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ + __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1A */ +} SPDIFRX_TypeDef; + + +/** + * @brief Secure digital input/output Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */ + __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */ + uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ + uint32_t RESERVED2[222]; /*!< Reserved, 0x84-0x3F8 */ + __IO uint32_t IPVR; /*!< SDMMC data FIFO register, Address offset: 0x3FC */ +} SDMMC_TypeDef; + + +/** + * @brief Delay Block DLYB + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief HW Semaphore HSEM + */ + +typedef struct +{ + __IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-7Ch */ + __IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-FCh */ + __IO uint32_t C1IER; /*!< HSEM Interrupt 0 enable register , Address offset: 100h */ + __IO uint32_t C1ICR; /*!< HSEM Interrupt 0 clear register , Address offset: 104h */ + __IO uint32_t C1ISR; /*!< HSEM Interrupt 0 Status register , Address offset: 108h */ + __IO uint32_t C1MISR; /*!< HSEM Interrupt 0 Masked Status register , Address offset: 10Ch */ + __IO uint32_t C2IER; /*!< HSEM Interrupt 1 enable register , Address offset: 110h */ + __IO uint32_t C2ICR; /*!< HSEM Interrupt 1 clear register , Address offset: 114h */ + __IO uint32_t C2ISR; /*!< HSEM Interrupt 1 Status register , Address offset: 118h */ + __IO uint32_t C2MISR; /*!< HSEM Interrupt 1 Masked Status register , Address offset: 11Ch */ + uint32_t Reserved[8]; /* Reserved Address offset: 120h-13Ch*/ + __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */ + __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */ + +} HSEM_TypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< HSEM interrupt enable register , Address offset: 0h */ + __IO uint32_t ICR; /*!< HSEM interrupt clear register , Address offset: 4h */ + __IO uint32_t ISR; /*!< HSEM interrupt status register , Address offset: 8h */ + __IO uint32_t MISR; /*!< HSEM masked interrupt status register , Address offset: Ch */ +} HSEM_Common_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI/I2S Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI/I2S Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t TXDR; /*!< SPI/I2S Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S Receive data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ + __IO uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */ + +} SPI_TypeDef; +/** + * @brief QUAD Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ + __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ + __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ + __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ + __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ + __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ +} QUADSPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint32_t RESERVED1; /*!< Reserved, 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */ +} TIM_TypeDef; + +/** + * @brief LPTIMIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + uint32_t RESERVED1; /*!< Reserved, 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register, Address offset: 0x24 */ +} LPTIM_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */ + __IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */ + __IO uint32_t OR; /*!< Comparator option register, Address offset: 0x08 */ +} COMPOPT_TypeDef; + +typedef struct +{ + __IO uint32_t CFGR; /*!< Comparator configuration register , Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CFGR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ +} COMP_Common_TypeDef; +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Single Wire Protocol Master Interface SPWMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */ + __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */ + uint32_t RESERVED1; /*!< Reserved, 0x08 */ + __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */ + __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */ + __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */ + __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */ + __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */ + __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */ +} SWPMI_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @brief RAM_ECC_Specific_Registers + */ +typedef struct +{ + __IO uint32_t CR; /*!< RAMECC monitor configuration register */ + __IO uint32_t SR; /*!< RAMECC monitor status register */ + __IO uint32_t FAR; /*!< RAMECC monitor failing address register */ + __IO uint32_t FDRL; /*!< RAMECC monitor failing data low register */ + __IO uint32_t FDRH; /*!< RAMECC monitor failing data high register */ + __IO uint32_t FECR; /*!< RAMECC monitor failing ECC error code register */ +} RAMECC_MonitorTypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< RAMECC interrupt enable register */ +} RAMECC_TypeDef; +/** + * @} + */ + + + +/** + * @brief High resolution Timer (HRTIM) + */ +/* HRTIM master registers definition */ +typedef struct +{ + __IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */ + __IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */ + __IO uint32_t MICR; /*!< HRTIM Master Timer interupt clear register, Address offset: 0x08 */ + __IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */ + __IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */ + __IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */ + __IO uint32_t MREP; /*!< HRTIM Master Timer repetition register, Address offset: 0x18 */ + __IO uint32_t MCMP1R; /*!< HRTIM Master Timer compare 1 register, Address offset: 0x1C */ + uint32_t RESERVED0; /*!< Reserved, 0x20 */ + __IO uint32_t MCMP2R; /*!< HRTIM Master Timer compare 2 register, Address offset: 0x24 */ + __IO uint32_t MCMP3R; /*!< HRTIM Master Timer compare 3 register, Address offset: 0x28 */ + __IO uint32_t MCMP4R; /*!< HRTIM Master Timer compare 4 register, Address offset: 0x2C */ + uint32_t RESERVED1[20]; /*!< Reserved, 0x30..0x7C */ +}HRTIM_Master_TypeDef; + +/* HRTIM Timer A to E registers definition */ +typedef struct +{ + __IO uint32_t TIMxCR; /*!< HRTIM Timerx control register, Address offset: 0x00 */ + __IO uint32_t TIMxISR; /*!< HRTIM Timerx interrupt status register, Address offset: 0x04 */ + __IO uint32_t TIMxICR; /*!< HRTIM Timerx interrupt clear register, Address offset: 0x08 */ + __IO uint32_t TIMxDIER; /*!< HRTIM Timerx DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t CNTxR; /*!< HRTIM Timerx counter register, Address offset: 0x10 */ + __IO uint32_t PERxR; /*!< HRTIM Timerx period register, Address offset: 0x14 */ + __IO uint32_t REPxR; /*!< HRTIM Timerx repetition register, Address offset: 0x18 */ + __IO uint32_t CMP1xR; /*!< HRTIM Timerx compare 1 register, Address offset: 0x1C */ + __IO uint32_t CMP1CxR; /*!< HRTIM Timerx compare 1 compound register, Address offset: 0x20 */ + __IO uint32_t CMP2xR; /*!< HRTIM Timerx compare 2 register, Address offset: 0x24 */ + __IO uint32_t CMP3xR; /*!< HRTIM Timerx compare 3 register, Address offset: 0x28 */ + __IO uint32_t CMP4xR; /*!< HRTIM Timerx compare 4 register, Address offset: 0x2C */ + __IO uint32_t CPT1xR; /*!< HRTIM Timerx capture 1 register, Address offset: 0x30 */ + __IO uint32_t CPT2xR; /*!< HRTIM Timerx capture 2 register, Address offset: 0x34 */ + __IO uint32_t DTxR; /*!< HRTIM Timerx dead time register, Address offset: 0x38 */ + __IO uint32_t SETx1R; /*!< HRTIM Timerx output 1 set register, Address offset: 0x3C */ + __IO uint32_t RSTx1R; /*!< HRTIM Timerx output 1 reset register, Address offset: 0x40 */ + __IO uint32_t SETx2R; /*!< HRTIM Timerx output 2 set register, Address offset: 0x44 */ + __IO uint32_t RSTx2R; /*!< HRTIM Timerx output 2 reset register, Address offset: 0x48 */ + __IO uint32_t EEFxR1; /*!< HRTIM Timerx external event filtering 1 register, Address offset: 0x4C */ + __IO uint32_t EEFxR2; /*!< HRTIM Timerx external event filtering 2 register, Address offset: 0x50 */ + __IO uint32_t RSTxR; /*!< HRTIM Timerx Reset register, Address offset: 0x54 */ + __IO uint32_t CHPxR; /*!< HRTIM Timerx Chopper register, Address offset: 0x58 */ + __IO uint32_t CPT1xCR; /*!< HRTIM Timerx Capture 1 register, Address offset: 0x5C */ + __IO uint32_t CPT2xCR; /*!< HRTIM Timerx Capture 2 register, Address offset: 0x60 */ + __IO uint32_t OUTxR; /*!< HRTIM Timerx Output register, Address offset: 0x64 */ + __IO uint32_t FLTxR; /*!< HRTIM Timerx Fault register, Address offset: 0x68 */ + uint32_t RESERVED0[5]; /*!< Reserved, 0x6C..0x7C */ +}HRTIM_Timerx_TypeDef; + +/* HRTIM common register definition */ +typedef struct +{ + __IO uint32_t CR1; /*!< HRTIM control register1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< HRTIM control register2, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< HRTIM interrupt status register, Address offset: 0x08 */ + __IO uint32_t ICR; /*!< HRTIM interrupt clear register, Address offset: 0x0C */ + __IO uint32_t IER; /*!< HRTIM interrupt enable register, Address offset: 0x10 */ + __IO uint32_t OENR; /*!< HRTIM Output enable register, Address offset: 0x14 */ + __IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */ + __IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */ + __IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */ + __IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */ + __IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */ + __IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */ + __IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */ + __IO uint32_t EECR2; /*!< HRTIM Timer external event control register2, Address offset: 0x34 */ + __IO uint32_t EECR3; /*!< HRTIM Timer external event control register3, Address offset: 0x38 */ + __IO uint32_t ADC1R; /*!< HRTIM ADC Trigger 1 register, Address offset: 0x3C */ + __IO uint32_t ADC2R; /*!< HRTIM ADC Trigger 2 register, Address offset: 0x40 */ + __IO uint32_t ADC3R; /*!< HRTIM ADC Trigger 3 register, Address offset: 0x44 */ + __IO uint32_t ADC4R; /*!< HRTIM ADC Trigger 4 register, Address offset: 0x48 */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x4C */ + __IO uint32_t FLTINR1; /*!< HRTIM Fault input register1, Address offset: 0x50 */ + __IO uint32_t FLTINR2; /*!< HRTIM Fault input register2, Address offset: 0x54 */ + __IO uint32_t BDMUPR; /*!< HRTIM Burst DMA Master Timer update register, Address offset: 0x58 */ + __IO uint32_t BDTAUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x5C */ + __IO uint32_t BDTBUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x60 */ + __IO uint32_t BDTCUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x64 */ + __IO uint32_t BDTDUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x68 */ + __IO uint32_t BDTEUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x6C */ + __IO uint32_t BDMADR; /*!< HRTIM Burst DMA Master Data register, Address offset: 0x70 */ +}HRTIM_Common_TypeDef; + +/* HRTIM register definition */ +typedef struct { + HRTIM_Master_TypeDef sMasterRegs; + HRTIM_Timerx_TypeDef sTimerxRegs[5]; + uint32_t RESERVED0[32]; + HRTIM_Common_TypeDef sCommonRegs; +}HRTIM_TypeDef; +/** + * @brief RNG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @brief MDIOS + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t WRFR; + __IO uint32_t CWRFR; + __IO uint32_t RDFR; + __IO uint32_t CRDFR; + __IO uint32_t SR; + __IO uint32_t CLRFR; + uint32_t RESERVED[57]; + __IO uint32_t DINR0; + __IO uint32_t DINR1; + __IO uint32_t DINR2; + __IO uint32_t DINR3; + __IO uint32_t DINR4; + __IO uint32_t DINR5; + __IO uint32_t DINR6; + __IO uint32_t DINR7; + __IO uint32_t DINR8; + __IO uint32_t DINR9; + __IO uint32_t DINR10; + __IO uint32_t DINR11; + __IO uint32_t DINR12; + __IO uint32_t DINR13; + __IO uint32_t DINR14; + __IO uint32_t DINR15; + __IO uint32_t DINR16; + __IO uint32_t DINR17; + __IO uint32_t DINR18; + __IO uint32_t DINR19; + __IO uint32_t DINR20; + __IO uint32_t DINR21; + __IO uint32_t DINR22; + __IO uint32_t DINR23; + __IO uint32_t DINR24; + __IO uint32_t DINR25; + __IO uint32_t DINR26; + __IO uint32_t DINR27; + __IO uint32_t DINR28; + __IO uint32_t DINR29; + __IO uint32_t DINR30; + __IO uint32_t DINR31; + __IO uint32_t DOUTR0; + __IO uint32_t DOUTR1; + __IO uint32_t DOUTR2; + __IO uint32_t DOUTR3; + __IO uint32_t DOUTR4; + __IO uint32_t DOUTR5; + __IO uint32_t DOUTR6; + __IO uint32_t DOUTR7; + __IO uint32_t DOUTR8; + __IO uint32_t DOUTR9; + __IO uint32_t DOUTR10; + __IO uint32_t DOUTR11; + __IO uint32_t DOUTR12; + __IO uint32_t DOUTR13; + __IO uint32_t DOUTR14; + __IO uint32_t DOUTR15; + __IO uint32_t DOUTR16; + __IO uint32_t DOUTR17; + __IO uint32_t DOUTR18; + __IO uint32_t DOUTR19; + __IO uint32_t DOUTR20; + __IO uint32_t DOUTR21; + __IO uint32_t DOUTR22; + __IO uint32_t DOUTR23; + __IO uint32_t DOUTR24; + __IO uint32_t DOUTR25; + __IO uint32_t DOUTR26; + __IO uint32_t DOUTR27; + __IO uint32_t DOUTR28; + __IO uint32_t DOUTR29; + __IO uint32_t DOUTR30; + __IO uint32_t DOUTR31; +} MDIOS_TypeDef; + + +/** + * @brief USB_OTG_Core_Registers + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ + __IO uint32_t CID; /*!< User ID Register 03Ch */ + __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/ + __IO uint32_t GHWCFG1; /* User HW config1 044h*/ + __IO uint32_t GHWCFG2; /* User HW config2 048h*/ + __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ + uint32_t Reserved6; /*!< Reserved 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */ + uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ +} USB_OTG_GlobalTypeDef; + + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ + __IO uint32_t DCTL; /*!< dev Control Register 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved9; /*!< Reserved 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ + uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ +} USB_OTG_OUTEndpointTypeDef; + + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ + uint32_t Reserved[2]; /*!< Reserved */ +} USB_OTG_HostChannelTypeDef; +/** + * @} + */ + + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define D1_ITCMRAM_BASE (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM */ +#define D1_ITCMICP_BASE (0x00100000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM */ +#define D1_DTCMRAM_BASE (0x20000000UL) /*!< Base address of : 128KB system data RAM accessible over DTCM */ +#define D1_AXIFLASH_BASE (0x08000000UL) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */ +#define D1_AXIICP_BASE (0x1FF00000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI */ +#define D1_AXISRAM_BASE (0x24000000UL) /*!< Base address of : (up to 512KB) system data RAM accessible over over AXI */ + +#define D2_AXISRAM_BASE (0x10000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI */ +#define D2_AHBSRAM_BASE (0x30000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI->AHB Bridge */ + +#define D3_BKPSRAM_BASE (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge */ +#define D3_SRAM_BASE (0x38000000UL) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge */ + +#define PERIPH_BASE (0x40000000UL) /*!< Base address of : AHB/APB Peripherals */ +#define QSPI_BASE (0x90000000UL) /*!< Base address of : QSPI memories accessible over AXI */ + +#define FLASH_BANK1_BASE (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI */ +#define FLASH_BANK2_BASE (0x08100000UL) /*!< Base address of : (up to 1 MB) Flash Bank2 accessible over AXI */ +#define FLASH_END (0x081FFFFFUL) /*!< FLASH end address */ + +/* Legacy define */ +#define FLASH_BASE FLASH_BANK1_BASE + +/*!< Device electronic signature memory map */ +#define UID_BASE (0x1FF1E800UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x1FF1E880UL) /*!< FLASH Size register base address */ + + +/*!< Peripheral memory map */ +#define D2_APB1PERIPH_BASE PERIPH_BASE +#define D2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL) + +#define D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000UL) +#define D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000UL) + +#define D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000UL) +#define D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000UL) + +/*!< Legacy Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL) + + +/*!< D1_AHB1PERIPH peripherals */ + +#define MDMA_BASE (D1_AHB1PERIPH_BASE + 0x0000UL) +#define DMA2D_BASE (D1_AHB1PERIPH_BASE + 0x1000UL) +#define JPGDEC_BASE (D1_AHB1PERIPH_BASE + 0x3000UL) +#define FLASH_R_BASE (D1_AHB1PERIPH_BASE + 0x2000UL) +#define FMC_R_BASE (D1_AHB1PERIPH_BASE + 0x4000UL) +#define QSPI_R_BASE (D1_AHB1PERIPH_BASE + 0x5000UL) +#define DLYB_QSPI_BASE (D1_AHB1PERIPH_BASE + 0x6000UL) +#define SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x7000UL) +#define DLYB_SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x8000UL) +#define RAMECC1_BASE (D1_AHB1PERIPH_BASE + 0x9000UL) + +/*!< D2_AHB1PERIPH peripherals */ + +#define DMA1_BASE (D2_AHB1PERIPH_BASE + 0x0000UL) +#define DMA2_BASE (D2_AHB1PERIPH_BASE + 0x0400UL) +#define DMAMUX1_BASE (D2_AHB1PERIPH_BASE + 0x0800UL) +#define ADC1_BASE (D2_AHB1PERIPH_BASE + 0x2000UL) +#define ADC2_BASE (D2_AHB1PERIPH_BASE + 0x2100UL) +#define ADC12_COMMON_BASE (D2_AHB1PERIPH_BASE + 0x2300UL) +#define ART_BASE (D2_AHB1PERIPH_BASE + 0x4400UL) +#define ETH_BASE (D2_AHB1PERIPH_BASE + 0x8000UL) +#define ETH_MAC_BASE (ETH_BASE) + +/*!< USB registers base address */ +#define USB1_OTG_HS_PERIPH_BASE (0x40040000UL) +#define USB2_OTG_FS_PERIPH_BASE (0x40080000UL) +#define USB_OTG_GLOBAL_BASE (0x000UL) +#define USB_OTG_DEVICE_BASE (0x800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0xB00UL) +#define USB_OTG_EP_REG_SIZE (0x20UL) +#define USB_OTG_HOST_BASE (0x400UL) +#define USB_OTG_HOST_PORT_BASE (0x440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x20UL) +#define USB_OTG_PCGCCTL_BASE (0xE00UL) +#define USB_OTG_FIFO_BASE (0x1000UL) +#define USB_OTG_FIFO_SIZE (0x1000UL) + +/*!< D2_AHB2PERIPH peripherals */ + +#define DCMI_BASE (D2_AHB2PERIPH_BASE + 0x0000UL) +#define RNG_BASE (D2_AHB2PERIPH_BASE + 0x1800UL) +#define SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2400UL) +#define DLYB_SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2800UL) +#define RAMECC2_BASE (D2_AHB2PERIPH_BASE + 0x3000UL) + +/*!< D3_AHB1PERIPH peripherals */ +#define GPIOA_BASE (D3_AHB1PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (D3_AHB1PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (D3_AHB1PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (D3_AHB1PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (D3_AHB1PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (D3_AHB1PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (D3_AHB1PERIPH_BASE + 0x1800UL) +#define GPIOH_BASE (D3_AHB1PERIPH_BASE + 0x1C00UL) +#define GPIOI_BASE (D3_AHB1PERIPH_BASE + 0x2000UL) +#define GPIOJ_BASE (D3_AHB1PERIPH_BASE + 0x2400UL) +#define GPIOK_BASE (D3_AHB1PERIPH_BASE + 0x2800UL) +#define RCC_BASE (D3_AHB1PERIPH_BASE + 0x4400UL) +#define RCC_C1_BASE (RCC_BASE + 0x130UL) +#define RCC_C2_BASE (RCC_BASE + 0x190UL) +#define PWR_BASE (D3_AHB1PERIPH_BASE + 0x4800UL) +#define CRC_BASE (D3_AHB1PERIPH_BASE + 0x4C00UL) +#define BDMA_BASE (D3_AHB1PERIPH_BASE + 0x5400UL) +#define DMAMUX2_BASE (D3_AHB1PERIPH_BASE + 0x5800UL) +#define ADC3_BASE (D3_AHB1PERIPH_BASE + 0x6000UL) +#define ADC3_COMMON_BASE (D3_AHB1PERIPH_BASE + 0x6300UL) +#define HSEM_BASE (D3_AHB1PERIPH_BASE + 0x6400UL) +#define RAMECC3_BASE (D3_AHB1PERIPH_BASE + 0x7000UL) + +/*!< D1_APB1PERIPH peripherals */ +#define LTDC_BASE (D1_APB1PERIPH_BASE + 0x1000UL) +#define LTDC_Layer1_BASE (LTDC_BASE + 0x84UL) +#define LTDC_Layer2_BASE (LTDC_BASE + 0x104UL) +#define DSI_BASE (D1_APB1PERIPH_BASE) +#define WWDG1_BASE (D1_APB1PERIPH_BASE + 0x3000UL) + +/*!< D2_APB1PERIPH peripherals */ +#define TIM2_BASE (D2_APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (D2_APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (D2_APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (D2_APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (D2_APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (D2_APB1PERIPH_BASE + 0x1400UL) +#define TIM12_BASE (D2_APB1PERIPH_BASE + 0x1800UL) +#define TIM13_BASE (D2_APB1PERIPH_BASE + 0x1C00UL) +#define TIM14_BASE (D2_APB1PERIPH_BASE + 0x2000UL) +#define LPTIM1_BASE (D2_APB1PERIPH_BASE + 0x2400UL) + +#define WWDG2_BASE (D2_APB1PERIPH_BASE + 0x2C00UL) + +#define SPI2_BASE (D2_APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (D2_APB1PERIPH_BASE + 0x3C00UL) +#define SPDIFRX_BASE (D2_APB1PERIPH_BASE + 0x4000UL) +#define USART2_BASE (D2_APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (D2_APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (D2_APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (D2_APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (D2_APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (D2_APB1PERIPH_BASE + 0x5800UL) +#define I2C3_BASE (D2_APB1PERIPH_BASE + 0x5C00UL) +#define CEC_BASE (D2_APB1PERIPH_BASE + 0x6C00UL) +#define DAC1_BASE (D2_APB1PERIPH_BASE + 0x7400UL) +#define UART7_BASE (D2_APB1PERIPH_BASE + 0x7800UL) +#define UART8_BASE (D2_APB1PERIPH_BASE + 0x7C00UL) +#define CRS_BASE (D2_APB1PERIPH_BASE + 0x8400UL) +#define SWPMI1_BASE (D2_APB1PERIPH_BASE + 0x8800UL) +#define OPAMP_BASE (D2_APB1PERIPH_BASE + 0x9000UL) +#define OPAMP1_BASE (D2_APB1PERIPH_BASE + 0x9000UL) +#define OPAMP2_BASE (D2_APB1PERIPH_BASE + 0x9010UL) +#define MDIOS_BASE (D2_APB1PERIPH_BASE + 0x9400UL) +#define FDCAN1_BASE (D2_APB1PERIPH_BASE + 0xA000UL) +#define FDCAN2_BASE (D2_APB1PERIPH_BASE + 0xA400UL) +#define FDCAN_CCU_BASE (D2_APB1PERIPH_BASE + 0xA800UL) +#define SRAMCAN_BASE (D2_APB1PERIPH_BASE + 0xAC00UL) + +/*!< D2_APB2PERIPH peripherals */ + +#define TIM1_BASE (D2_APB2PERIPH_BASE + 0x0000UL) +#define TIM8_BASE (D2_APB2PERIPH_BASE + 0x0400UL) +#define USART1_BASE (D2_APB2PERIPH_BASE + 0x1000UL) +#define USART6_BASE (D2_APB2PERIPH_BASE + 0x1400UL) +#define SPI1_BASE (D2_APB2PERIPH_BASE + 0x3000UL) +#define SPI4_BASE (D2_APB2PERIPH_BASE + 0x3400UL) +#define TIM15_BASE (D2_APB2PERIPH_BASE + 0x4000UL) +#define TIM16_BASE (D2_APB2PERIPH_BASE + 0x4400UL) +#define TIM17_BASE (D2_APB2PERIPH_BASE + 0x4800UL) +#define SPI5_BASE (D2_APB2PERIPH_BASE + 0x5000UL) +#define SAI1_BASE (D2_APB2PERIPH_BASE + 0x5800UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL) +#define SAI2_BASE (D2_APB2PERIPH_BASE + 0x5C00UL) +#define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL) +#define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL) +#define SAI3_BASE (D2_APB2PERIPH_BASE + 0x6000UL) +#define SAI3_Block_A_BASE (SAI3_BASE + 0x004UL) +#define SAI3_Block_B_BASE (SAI3_BASE + 0x024UL) +#define DFSDM1_BASE (D2_APB2PERIPH_BASE + 0x7000UL) +#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL) +#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL) +#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL) +#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL) +#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL) +#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL) +#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL) +#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL) +#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL) +#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL) +#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL) +#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL) +#define HRTIM1_BASE (D2_APB2PERIPH_BASE + 0x7400UL) +#define HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x00000080UL) +#define HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x00000100UL) +#define HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x00000180UL) +#define HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x00000200UL) +#define HRTIM1_TIME_BASE (HRTIM1_BASE + 0x00000280UL) +#define HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x00000380UL) + + +/*!< D3_APB1PERIPH peripherals */ +#define EXTI_BASE (D3_APB1PERIPH_BASE + 0x0000UL) +#define EXTI_D1_BASE (EXTI_BASE + 0x0080UL) +#define EXTI_D2_BASE (EXTI_BASE + 0x00C0UL) +#define SYSCFG_BASE (D3_APB1PERIPH_BASE + 0x0400UL) +#define LPUART1_BASE (D3_APB1PERIPH_BASE + 0x0C00UL) +#define SPI6_BASE (D3_APB1PERIPH_BASE + 0x1400UL) +#define I2C4_BASE (D3_APB1PERIPH_BASE + 0x1C00UL) +#define LPTIM2_BASE (D3_APB1PERIPH_BASE + 0x2400UL) +#define LPTIM3_BASE (D3_APB1PERIPH_BASE + 0x2800UL) +#define LPTIM4_BASE (D3_APB1PERIPH_BASE + 0x2C00UL) +#define LPTIM5_BASE (D3_APB1PERIPH_BASE + 0x3000UL) +#define COMP12_BASE (D3_APB1PERIPH_BASE + 0x3800UL) +#define COMP1_BASE (COMP12_BASE + 0x0CUL) +#define COMP2_BASE (COMP12_BASE + 0x10UL) +#define VREFBUF_BASE (D3_APB1PERIPH_BASE + 0x3C00UL) +#define RTC_BASE (D3_APB1PERIPH_BASE + 0x4000UL) +#define IWDG1_BASE (D3_APB1PERIPH_BASE + 0x4800UL) + +#define IWDG2_BASE (D3_APB1PERIPH_BASE + 0x4C00UL) + +#define SAI4_BASE (D3_APB1PERIPH_BASE + 0x5400UL) +#define SAI4_Block_A_BASE (SAI4_BASE + 0x004UL) +#define SAI4_Block_B_BASE (SAI4_BASE + 0x024UL) + + + + +#define BDMA_Channel0_BASE (BDMA_BASE + 0x0008UL) +#define BDMA_Channel1_BASE (BDMA_BASE + 0x001CUL) +#define BDMA_Channel2_BASE (BDMA_BASE + 0x0030UL) +#define BDMA_Channel3_BASE (BDMA_BASE + 0x0044UL) +#define BDMA_Channel4_BASE (BDMA_BASE + 0x0058UL) +#define BDMA_Channel5_BASE (BDMA_BASE + 0x006CUL) +#define BDMA_Channel6_BASE (BDMA_BASE + 0x0080UL) +#define BDMA_Channel7_BASE (BDMA_BASE + 0x0094UL) + +#define DMAMUX2_Channel0_BASE (DMAMUX2_BASE) +#define DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004UL) +#define DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008UL) +#define DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000CUL) +#define DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010UL) +#define DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014UL) +#define DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018UL) +#define DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001CUL) + +#define DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100UL) +#define DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104UL) +#define DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108UL) +#define DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010CUL) +#define DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110UL) +#define DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114UL) +#define DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118UL) +#define DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011CUL) + +#define DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080UL) +#define DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140UL) + +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL) + +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL) + +#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE) +#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL) +#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL) +#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL) +#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL) +#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL) +#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL) +#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL) +#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL) +#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL) +#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL) +#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL) +#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL) +#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL) +#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL) +#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL) + +#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL) +#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL) +#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL) +#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL) +#define DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110UL) +#define DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114UL) +#define DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118UL) +#define DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011CUL) + +#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL) +#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL) + +/*!< FMC Banks registers base address */ +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) +#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060UL) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) +#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0x5C001000UL) + +#define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040UL) +#define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080UL) +#define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0UL) +#define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100UL) +#define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140UL) +#define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180UL) +#define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0UL) +#define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200UL) +#define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240UL) +#define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280UL) +#define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0UL) +#define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300UL) +#define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340UL) +#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL) +#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL) +#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL) + +#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL) +#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL) +#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL) +#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL) +#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL) + +#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL) +#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL) +#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL) +#define RAMECC2_Monitor4_BASE (RAMECC2_BASE + 0x80UL) +#define RAMECC2_Monitor5_BASE (RAMECC2_BASE + 0xA0UL) + +#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL) +#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL) + + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE) + +#define WWDG2 ((WWDG_TypeDef *) WWDG2_BASE) +#define IWDG2 ((IWDG_TypeDef *) IWDG2_BASE) + +#define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define SPI5 ((SPI_TypeDef *) SPI5_BASE) +#define SPI6 ((SPI_TypeDef *) SPI6_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define UART7 ((USART_TypeDef *) UART7_BASE) +#define UART8 ((USART_TypeDef *) UART8_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define I2C4 ((I2C_TypeDef *) I2C4_BASE) +#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE) +#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE) +#define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE) +#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) +#define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE) +#define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE) +#define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE) + +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define COMP12 ((COMPOPT_TypeDef *) COMP12_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE) +#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) +#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) +#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) + + +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE) +#define EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE) +#define SDMMC ((SDMMC_TypeDef *) SDMMC_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE) +#define HRTIM1_TIMA ((HRTIM_TIM_TypeDef *) HRTIM1_TIMA_BASE) +#define HRTIM1_TIMB ((HRTIM_TIM_TypeDef *) HRTIM1_TIMB_BASE) +#define HRTIM1_TIMC ((HRTIM_TIM_TypeDef *) HRTIM1_TIMC_BASE) +#define HRTIM1_TIMD ((HRTIM_TIM_TypeDef *) HRTIM1_TIMD_BASE) +#define HRTIM1_TIME ((HRTIM_TIM_TypeDef *) HRTIM1_TIME_BASE) +#define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define SAI2 ((SAI_TypeDef *) SAI2_BASE) +#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE) +#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE) +#define SAI3 ((SAI_TypeDef *) SAI3_BASE) +#define SAI3_Block_A ((SAI_Block_TypeDef *)SAI3_Block_A_BASE) +#define SAI3_Block_B ((SAI_Block_TypeDef *)SAI3_Block_B_BASE) +#define SAI4 ((SAI_TypeDef *) SAI4_BASE) +#define SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE) +#define SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE) + +#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) +#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE) +#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE) +#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE) +#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE) +#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE) +#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE) +#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE) +#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE) +#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE) +#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE) +#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE) +#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE) +#define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE) +#define DCMI ((DCMI_TypeDef *) DCMI_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define RCC_C1 ((RCC_Core_TypeDef *) RCC_C1_BASE) +#define RCC_C2 ((RCC_Core_TypeDef *) RCC_C2_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) +#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) +#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) + +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE) +#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE) + +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE) +#define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE) + +#define BDMA ((BDMA_TypeDef *) BDMA_BASE) +#define BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE) +#define BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE) +#define BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE) +#define BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE) +#define BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE) +#define BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE) +#define BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE) +#define BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE) + +#define RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE) +#define RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE) +#define RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE) +#define RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE) +#define RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE) +#define RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE) + +#define RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE) +#define RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE) +#define RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE) +#define RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE) +#define RAMECC2_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE) +#define RAMECC2_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE) + +#define RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE) +#define RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE) +#define RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE) + +#define DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE) +#define DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE) +#define DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE) +#define DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE) +#define DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE) +#define DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE) +#define DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE) +#define DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE) +#define DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE) + + +#define DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE) +#define DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE) +#define DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE) +#define DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE) +#define DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE) +#define DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE) +#define DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE) +#define DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE) + +#define DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE) +#define DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE) + +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) + +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) + + +#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE) +#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE) +#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE) +#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE) +#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE) +#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE) +#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE) +#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE) +#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE) +#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE) +#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE) +#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE) +#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE) +#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE) +#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE) +#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE) +#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE) + +#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE) +#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE) +#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE) +#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE) +#define DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE) +#define DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE) +#define DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE) +#define DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE) + +#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE) +#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) + + +#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE) +#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) +#define FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) + + +#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) +#define DLYB_QUADSPI ((DLYB_TypeDef *) DLYB_QSPI_BASE) +#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) +#define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +#define JPEG ((JPEG_TypeDef *) JPGDEC_BASE) +#define HSEM ((HSEM_TypeDef *) HSEM_BASE) +#if defined(CORE_CM4) +#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x110UL)) +#else /* CORE_CM7 */ +#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL)) +#endif /* CORE_CM4 */ + +#define LTDC ((LTDC_TypeDef *)LTDC_BASE) +#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) +#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) +#define DSI ((DSI_TypeDef *)DSI_BASE) + +#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) + +#define ETH ((ETH_TypeDef *)ETH_BASE) +#define MDMA ((MDMA_TypeDef *)MDMA_BASE) +#define MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE) +#define MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE) +#define MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE) +#define MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE) +#define MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE) +#define MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE) +#define MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE) +#define MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE) +#define MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE) +#define MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE) +#define MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE) +#define MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE) +#define MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE) +#define MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE) +#define MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE) +#define MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE) + + +#define USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE) +#define USB2_OTG_FS ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE) + +/* Legacy defines */ +#define USB_OTG_HS USB1_OTG_HS +#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE +#define USB_OTG_FS USB2_OTG_FS +#define USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************************* ADC VERSION ********************************/ +#define ADC_VER_V5_X +/******************** Bit definition for ADC_ISR register ********************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ + +/******************** Bit definition for ADC_IER register ********************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */ +#define ADC_CR_BOOST_Pos (8U) +#define ADC_CR_BOOST_Msk (0x3UL << ADC_CR_BOOST_Pos) /*!< 0x00000300 */ +#define ADC_CR_BOOST ADC_CR_BOOST_Msk /*!< ADC Boost Mode configuration */ +#define ADC_CR_BOOST_0 (0x1UL << ADC_CR_BOOST_Pos) /*!< 0x00000100 */ +#define ADC_CR_BOOST_1 (0x2UL << ADC_CR_BOOST_Pos) /*!< 0x00000200 */ +#define ADC_CR_ADCALLIN_Pos (16U) +#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */ +#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */ +#define ADC_CR_LINCALRDYW1_Pos (22U) +#define ADC_CR_LINCALRDYW1_Msk (0x1UL << ADC_CR_LINCALRDYW1_Pos) /*!< 0x00400000 */ +#define ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk /*!< ADC Linearity calibration ready Word 1 */ +#define ADC_CR_LINCALRDYW2_Pos (23U) +#define ADC_CR_LINCALRDYW2_Msk (0x1UL << ADC_CR_LINCALRDYW2_Pos) /*!< 0x00800000 */ +#define ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk /*!< ADC Linearity calibration ready Word 2 */ +#define ADC_CR_LINCALRDYW3_Pos (24U) +#define ADC_CR_LINCALRDYW3_Msk (0x1UL << ADC_CR_LINCALRDYW3_Pos) /*!< 0x01000000 */ +#define ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk /*!< ADC Linearity calibration ready Word 3 */ +#define ADC_CR_LINCALRDYW4_Pos (25U) +#define ADC_CR_LINCALRDYW4_Msk (0x1UL << ADC_CR_LINCALRDYW4_Pos) /*!< 0x02000000 */ +#define ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk /*!< ADC Linearity calibration ready Word 4 */ +#define ADC_CR_LINCALRDYW5_Pos (26U) +#define ADC_CR_LINCALRDYW5_Msk (0x1UL << ADC_CR_LINCALRDYW5_Pos) /*!< 0x04000000 */ +#define ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk /*!< ADC Linearity calibration ready Word 5 */ +#define ADC_CR_LINCALRDYW6_Pos (27U) +#define ADC_CR_LINCALRDYW6_Msk (0x1UL << ADC_CR_LINCALRDYW6_Pos) /*!< 0x08000000 */ +#define ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk /*!< ADC Linearity calibration ready Word 6 */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC Differential Mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */ + +/******************** Bit definition for ADC_CFGR register ********************/ +#define ADC_CFGR_DMNGT_Pos (0U) +#define ADC_CFGR_DMNGT_Msk (0x3UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk /*!< ADC Data Management configuration */ +#define ADC_CFGR_DMNGT_0 (0x1UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMNGT_1 (0x2UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR_RES_Pos (2U) +#define ADC_CFGR_RES_Msk (0x7UL << ADC_CFGR_RES_Pos) /*!< 0x0000001C */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC Data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_2 (0x4UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC_CFGR_EXTSEL_0 (0x01UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x02UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x04UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x08UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC overrun mode */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC Delayed conversion mode */ + +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC JSQR Queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC Automatic injected group conversion */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC Injected queue disable */ + +/******************** Bit definition for ADC_CFGR2 register ********************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ + +#define ADC_CFGR2_RSHIFT1_Pos (11U) +#define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */ +#define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */ +#define ADC_CFGR2_RSHIFT2_Pos (12U) +#define ADC_CFGR2_RSHIFT2_Msk (0x1UL << ADC_CFGR2_RSHIFT2_Pos) /*!< 0x00001000 */ +#define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift data after Offset 2 correction */ +#define ADC_CFGR2_RSHIFT3_Pos (13U) +#define ADC_CFGR2_RSHIFT3_Msk (0x1UL << ADC_CFGR2_RSHIFT3_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift data after Offset 3 correction */ +#define ADC_CFGR2_RSHIFT4_Pos (14U) +#define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */ + +#define ADC_CFGR2_OVSR_Pos (16U) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_LSHIFT_Pos (28U) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_SMPR1 register ********************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_SMPR2 register ********************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27U) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register ********************/ +#define ADC_PCSEL_PCSEL_Pos (0U) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ +#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/ +#define ADC_LTR_LT_Pos (0U) +#define ADC_LTR_LT_Msk (0x3FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x03FFFFFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */ + +/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/ +#define ADC_HTR_HT_Pos (0U) +#define ADC_HTR_HT_Msk (0x3FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x03FFFFFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */ + +/******************** Bit definition for ADC_SQR1 register ********************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ********************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ********************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ********************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ + +/******************** Bit definition for ADC_JSQR register ********************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ********************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ +#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */ +#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */ +#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */ +#define ADC_OFR1_OFFSET1_24 (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSET1_25 (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_SSATE_Pos (31U) +#define ADC_OFR1_SSATE_Msk (0x1UL << ADC_OFR1_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk /*!< ADC Signed saturation Enable */ + +/******************** Bit definition for ADC_OFR2 register ********************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ +#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */ +#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */ +#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */ +#define ADC_OFR2_OFFSET2_24 (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSET2_25 (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_SSATE_Pos (31U) +#define ADC_OFR2_SSATE_Msk (0x1UL << ADC_OFR2_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk /*!< ADC Signed saturation Enable */ + +/******************** Bit definition for ADC_OFR3 register ********************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ +#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */ +#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */ +#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */ +#define ADC_OFR3_OFFSET3_24 (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSET3_25 (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_SSATE_Pos (31U) +#define ADC_OFR3_SSATE_Msk (0x1UL << ADC_OFR3_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk /*!< ADC Signed saturation Enable */ + +/******************** Bit definition for ADC_OFR4 register ********************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ +#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */ +#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */ +#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */ +#define ADC_OFR4_OFFSET4_24 (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSET4_25 (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_SSATE_Pos (31U) +#define ADC_OFR4_SSATE_Msk (0x1UL << ADC_OFR4_SSATE_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk /*!< ADC Signed saturation Enable */ + +/******************** Bit definition for ADC_JDR1 register ********************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ********************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_AWD3CR register ********************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_DIFSEL register ********************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ********************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_CALFACT_S_7 (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT_CALFACT_D_7 (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT_CALFACT_D_8 (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_CALFACT_D_9 (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT_CALFACT_D_10 (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_CALFACT2 register ********************/ +#define ADC_CALFACT2_LINCALFACT_Pos (0U) +#define ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */ +#define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk /*!< ADC Linearity calibration factors */ +#define ADC_CALFACT2_LINCALFACT_0 (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT2_LINCALFACT_1 (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT2_LINCALFACT_2 (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT2_LINCALFACT_3 (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT2_LINCALFACT_4 (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT2_LINCALFACT_5 (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT2_LINCALFACT_6 (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT2_LINCALFACT_7 (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT2_LINCALFACT_8 (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT2_LINCALFACT_9 (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT2_LINCALFACT_10 (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT2_LINCALFACT_11 (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT2_LINCALFACT_12 (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT2_LINCALFACT_13 (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT2_LINCALFACT_14 (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT2_LINCALFACT_15 (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */ +#define ADC_CALFACT2_LINCALFACT_16 (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT2_LINCALFACT_17 (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT2_LINCALFACT_18 (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT2_LINCALFACT_19 (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT2_LINCALFACT_20 (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT2_LINCALFACT_21 (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT2_LINCALFACT_22 (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT2_LINCALFACT_23 (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT2_LINCALFACT_24 (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT2_LINCALFACT_25 (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT2_LINCALFACT_26 (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */ +#define ADC_CALFACT2_LINCALFACT_27 (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */ +#define ADC_CALFACT2_LINCALFACT_28 (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */ +#define ADC_CALFACT2_LINCALFACT_29 (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register ********************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ + +/******************** Bit definition for ADC_CCR register ********************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + + +#define ADC_CCR_DAMDF_Pos (14U) +#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode Data format */ +#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC clock mode */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************** Bit definition for ADC_CDR2 register ******************/ +#define ADC_CDR2_RDATA_ALT_Pos (0U) +#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */ + +/******************************************************************************/ +/* */ +/* VREFBUF */ +/* */ +/******************************************************************************/ +/******************* Bit definition for VREFBUF_CSR register ****************/ +#define VREFBUF_CSR_ENVR_Pos (0U) +#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */ +#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1) /* 1 MB */ +#define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */ +#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */ + + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32H747xx_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/flash_data.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/flash_data.h new file mode 100644 index 00000000000..71d8fc8683d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/flash_data.h @@ -0,0 +1,67 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_FLASH_DATA_H +#define MBED_FLASH_DATA_H + +#include "device.h" +#include + +#if DEVICE_FLASH + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ + +/* Flash size */ +#ifndef FLASH_SIZE +#define FLASH_SIZE (uint32_t) 0x200000 // 2Mb +#endif + +#define ADDR_FLASH_SECTOR_0_BANK1 ((uint32_t)0x08000000) /* Base @ of Sector 0, Bank1, 128 Kbyte */ +#define ADDR_FLASH_SECTOR_1_BANK1 ((uint32_t)0x08020000) /* Base @ of Sector 1, Bank1, 128 Kbyte */ +#define ADDR_FLASH_SECTOR_2_BANK1 ((uint32_t)0x08040000) /* Base @ of Sector 2, Bank1, 128 Kbyte */ +#define ADDR_FLASH_SECTOR_3_BANK1 ((uint32_t)0x08060000) /* Base @ of Sector 3, Bank1, 128 Kbyte */ +#define ADDR_FLASH_SECTOR_4_BANK1 ((uint32_t)0x08080000) /* Base @ of Sector 4, Bank1, 128 Kbyte */ +#define ADDR_FLASH_SECTOR_5_BANK1 ((uint32_t)0x080A0000) /* Base @ of Sector 5, Bank1, 128 Kbyte */ +#define ADDR_FLASH_SECTOR_6_BANK1 ((uint32_t)0x080C0000) /* Base @ of Sector 6, Bank1, 128 Kbyte */ +#define ADDR_FLASH_SECTOR_7_BANK1 ((uint32_t)0x080E0000) /* Base @ of Sector 7, Bank1, 128 Kbyte */ + +#define ADDR_FLASH_SECTOR_0_BANK2 ((uint32_t)0x08100000) /* Base @ of Sector 0, Bank2, 128 Kbyte */ +#define ADDR_FLASH_SECTOR_1_BANK2 ((uint32_t)0x08120000) /* Base @ of Sector 1, Bank2, 128 Kbyte */ +#define ADDR_FLASH_SECTOR_2_BANK2 ((uint32_t)0x08140000) /* Base @ of Sector 2, Bank2, 128 Kbyte */ +#define ADDR_FLASH_SECTOR_3_BANK2 ((uint32_t)0x08160000) /* Base @ of Sector 3, Bank2, 128 Kbyte */ +#define ADDR_FLASH_SECTOR_4_BANK2 ((uint32_t)0x08180000) /* Base @ of Sector 4, Bank2, 128 Kbyte */ +#define ADDR_FLASH_SECTOR_5_BANK2 ((uint32_t)0x081A0000) /* Base @ of Sector 5, Bank2, 128 Kbyte */ +#define ADDR_FLASH_SECTOR_6_BANK2 ((uint32_t)0x081C0000) /* Base @ of Sector 6, Bank2, 128 Kbyte */ +#define ADDR_FLASH_SECTOR_7_BANK2 ((uint32_t)0x081E0000) /* Base @ of Sector 7, Bank2, 128 Kbyte */ + +#endif // DEVICE_FLASH + +#endif diff --git a/targets/TARGET_STM/mbed_rtx.h b/targets/TARGET_STM/mbed_rtx.h index fa9f97b55ce..66838fbdddd 100644 --- a/targets/TARGET_STM/mbed_rtx.h +++ b/targets/TARGET_STM/mbed_rtx.h @@ -36,6 +36,9 @@ #define INITIAL_SP (0x20018000UL) #endif /* toolchains */ +#elif (defined(TARGET_STM32H747xI) && defined(CORE_CM4)) +#define INITIAL_SP (0x10008000UL) + #elif (defined(TARGET_STM32F051R8) ||\ defined(TARGET_STM32F100RB) ||\ defined(TARGET_STM32L031K6) ||\ @@ -97,7 +100,8 @@ defined(TARGET_STM32F446VE) ||\ defined(TARGET_STM32F446ZE) ||\ defined(TARGET_STM32H743xI) ||\ - defined(TARGET_STM32H753xI)) + defined(TARGET_STM32H753xI) ||\ + defined(TARGET_STM32H747xI)) #define INITIAL_SP (0x20020000UL) #elif (defined(TARGET_STM32F429ZI) ||\ From 2008be1c0d4605755862d7a0f133c0ece9dd8f0d Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Fri, 30 Aug 2019 14:26:36 +0200 Subject: [PATCH 071/227] DISCO_H747I single core M7 introduction --- .../TARGET_DISCO_H747I/PeripheralPins.c | 563 +++++++++ .../TARGET_DISCO_H747I/PinNames.h | 471 ++++++++ .../TARGET_DISCO_H747I/system_clock.c | 207 ++++ .../TARGET_DISCO_H747I/system_stm32h7xx.c | 368 ++++++ .../TOOLCHAIN_ARM_STD/startup_stm32h747xx.S | 574 ++++++++++ .../TOOLCHAIN_ARM_STD/stm32h747xI.sct | 66 ++ .../TOOLCHAIN_GCC_ARM/STM32H747xI.ld | 169 +++ .../TOOLCHAIN_GCC_ARM/startup_stm32h747xx.S | 771 +++++++++++++ .../TOOLCHAIN_IAR/startup_stm32h747xx.S | 1009 +++++++++++++++++ .../TOOLCHAIN_IAR/stm32h747xI.icf | 35 + targets/targets.json | 43 + 11 files changed, 4276 insertions(+) create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PeripheralPins.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PinNames.h create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/system_clock.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/system_stm32h7xx.c create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_ARM_STD/startup_stm32h747xx.S create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_ARM_STD/stm32h747xI.sct create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI.ld create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_GCC_ARM/startup_stm32h747xx.S create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_IAR/startup_stm32h747xx.S create mode 100644 targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_IAR/stm32h747xI.icf diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PeripheralPins.c new file mode 100644 index 00000000000..0c48c8908e3 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PeripheralPins.c @@ -0,0 +1,563 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2018, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + * + * Automatically generated from STM32H747XIHx.xml + */ + +#include "PeripheralPins.h" +#include "mbed_toolchain.h" + +//============================================================================== +// Notes +// +// - The pins mentioned Px_y_ALTz are alternative possibilities which use other +// HW peripheral instances. You can use them the same way as any other "normal" +// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board +// pinout image on mbed.org. +// +// - The pins which are connected to other components present on the board have +// the comment "Connected to xxx". The pin function may not work properly in this +// case. These pins may not be displayed on the board pinout image on mbed.org. +// Please read the board reference manual and schematic for more information. +// +// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented +// See https://os.mbed.com/teams/ST/wiki/STDIO for more information. +// +//============================================================================== + + +//*** ADC *** + +MBED_WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_INP16 // Connected to PMOD\#1- USART2_CTS_NSS + {PA_0_ALT0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INN1 // Connected to ARD_A2 + {PA_0_ALT1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_INP0 // Connected to ARD_A2 + {PA_0_ALT2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INN1 // Connected to ARD_A2 + {PA_0_ALT3, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_INP0 // Connected to ARD_A2 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_INN16 // Connected to ETH_REF_CLK + {PA_1_ALT0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_INP17 // Connected to ETH_REF_CLK + {PA_1_ALT1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INP1 // Connected to ARD_A3 + {PA_1_ALT2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INP1 // Connected to ARD_A3 + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14 // Connected to ETH_MDIO + {PA_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14 // Connected to ETH_MDIO + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15 // Connected to ULPI_D0 + {PA_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15 // Connected to ULPI_D0 + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18 + {PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INN18 // Connected to ULPI_CK + {PA_5_ALT0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19 // Connected to ULPI_CK + {PA_5_ALT1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INN18 // Connected to ULPI_CK + {PA_5_ALT2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19 // Connected to ULPI_CK + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3 + {PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3 + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INN3 // Connected to ETH_CRS_DV + {PA_7_ALT0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7 // Connected to ETH_CRS_DV + {PA_7_ALT1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INN3 // Connected to ETH_CRS_DV + {PA_7_ALT2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7 // Connected to ETH_CRS_DV + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INN5 // Connected to ULPI_D1 + {PB_0_ALT0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9 // Connected to ULPI_D1 + {PB_0_ALT1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INN5 // Connected to ULPI_D1 + {PB_0_ALT2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9 // Connected to ULPI_D1 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5 // Connected to ULPI_D2 + {PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5 // Connected to ULPI_D2 + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10 // Connected to ULPI_STP + {PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10 // Connected to ULPI_STP + {PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_INP10 // Connected to ULPI_STP + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INN10 // Connected to ETH_MDC/SAI4_D1 + {PC_1_ALT0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11 // Connected to ETH_MDC/SAI4_D1 + {PC_1_ALT1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INN10 // Connected to ETH_MDC/SAI4_D1 + {PC_1_ALT2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11 // Connected to ETH_MDC/SAI4_D1 + {PC_1_ALT3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_INN10 // Connected to ETH_MDC/SAI4_D1 + {PC_1_ALT4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_INP11 // Connected to ETH_MDC/SAI4_D1 +// {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INN11 // Connected to PMOD\#3 +// {PC_2_ALT0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_INP12 // Connected to PMOD\#3 +// {PC_2_ALT1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INN11 // Connected to PMOD\#3 +// {PC_2_ALT2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_INP12 // Connected to PMOD\#3 +// {PC_2_ALT3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_INN11 // Connected to PMOD\#3 +// {PC_2_ALT4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_INP12 // Connected to PMOD\#3 + {PC_2, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_INN1 // Connected to ARD_A4 +// {PC_2_ALT6, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_INP0 // Connected to ARD_A4 +// {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_INN12 // Connected to PMOD\#2 +// {PC_3_ALT0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_INP13 // Connected to PMOD\#2 +// {PC_3_ALT1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_INN12 // Connected to PMOD\#2 +// {PC_3_ALT2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_INP13 // Connected to PMOD\#2 + {PC_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_INP1 // Connected to ARD_A5 + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INP4 // Connected to ETH_RXD0 + {PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INP4 // Connected to ETH_RXD0 + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INN4 // Connected to ETH_RXD1 + {PC_5_ALT0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_INP8 // Connected to ETH_RXD1 + {PC_5_ALT1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INN4 // Connected to ETH_RXD1 + {PC_5_ALT2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_INP8 // Connected to ETH_RXD1 + {PF_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_INP5 // Connected to FMC_A3 + {PF_4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_INN5 // Connected to FMC_A4 + {PF_4_ALT0, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC3_INP9 // Connected to FMC_A4 + {PF_5, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_INP4 // Connected to FMC_A5 + {PF_6, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_INN4 // Connected to QSPI_BK1_IO3 + {PF_6_ALT0, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_INP8 // Connected to QSPI_BK1_IO3 + {PF_7, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_INP3 // Connected to QSPI_BK1_IO2 + {PF_8, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_INN3 // Connected to PMOD\#14/ARD_D3 + {PF_8_ALT0, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_INP7 // Connected to PMOD\#14/ARD_D3 + {PF_9, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_INP2 // Connected to QSPI_BK1_IO1 + {PF_10, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_INN2 // Connected to ARD_A1 + {PF_10_ALT0, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_INP6 // Connected to ARD_A1 + {PF_11, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_INP2 // Connected to FMC_SDRAS + {PF_12, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_INN2 // Connected to FMC_A6 + {PF_12_ALT0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_INP6 // Connected to FMC_A6 + {PF_13, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_INP2 // Connected to FMC_A7 + {PF_14, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_INN2 // Connected to FMC_A8 + {PF_14_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_INP6 // Connected to FMC_A8 + {PH_2, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_INP13 // Connected to QSPI_BK2_IO0 + {PH_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_INN13 // Connected to QSPI_BK2_IO1 + {PH_3_ALT0, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC3_INP14 // Connected to QSPI_BK2_IO1 + {PH_4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC3_INN14 // Connected to ULPI_NXT + {PH_4_ALT0, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC3_INP15 // Connected to ULPI_NXT + {PH_5, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC3_INN15 // Connected to FMC_SDNWE + {PH_5_ALT0, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC3_INP16 // Connected to FMC_SDNWE + {NC, NC, 0} +}; + +// !!! SECTION TO BE CHECKED WITH DEVICE REFERENCE MANUAL +MBED_WEAK const PinMap PinMap_ADC_Internal[] = { + {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, + {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, + {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, + {NC, NC, 0} +}; + +//*** DAC *** + +MBED_WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 // Connected to ULPI_CK + {NC, NC, 0} +}; + +//*** I2C *** + +MBED_WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_7_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to PMOD\#19_DFSDM-DATA7 + {PB_9_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, // Connected to PMOD\#19_DFSDM-DATA7 + {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to ULPI_D4 + {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to SDIO1_D1 + {PD_13, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to FMC_A0 + {PF_15, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, // Connected to FMC_A9 + {PH_5, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to FMC_SDNWE + {PH_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to FMC_D16 + {PH_12, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, // Connected to FMC_D20 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to CEC_CK/MCO1 + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to HDMI_CEC + {PB_6_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, // Connected to HDMI_CEC + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to PMOD\#20_DFSDM-CK7 + {PB_8_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, // Connected to PMOD\#20_DFSDM-CK7 + {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to ULPI_D3 + {PD_12, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to FMC_A1 + {PF_14, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, // Connected to FMC_A8 + {PH_4, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to ULPI_NXT + {PH_7, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to FMC_SDCKE1 + {PH_11, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, // Connected to FMC_D19 + {NC, NC, 0} +}; + +//*** PWM *** + +// TIM cannot be used because already used by the us_ticker +// You have to comment all PWM using TIM_MST defined in hal_tick.h file +// or update python script (check TIM_MST_LIST) and re-run it +MBED_WEAK const PinMap PinMap_PWM[] = { + {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to PMOD\#1- USART2_CTS_NSS + {PA_0_ALT0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 // Connected to PMOD\#1- USART2_CTS_NSS + {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to ETH_REF_CLK + {PA_1_ALT0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 // Connected to ETH_REF_CLK + {PA_1_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N // Connected to ETH_REF_CLK + {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to ETH_MDIO + {PA_2_ALT0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // Connected to ETH_MDIO + {PA_2_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 // Connected to ETH_MDIO + {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // Connected to ULPI_D0 + {PA_3_ALT0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 // Connected to ULPI_D0 + {PA_3_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 // Connected to ULPI_D0 + {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to ULPI_CK + {PA_5_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N // Connected to ULPI_CK + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT0, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to ETH_CRS_DV + {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to ETH_CRS_DV + {PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N // Connected to ETH_CRS_DV + {PA_7_ALT2, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 // Connected to ETH_CRS_DV + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // Connected to CEC_CK/MCO1 +// {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // Connected to STDIO_UART_TX +// {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // Connected to STDIO_UART_RX + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // Connected to PMOD\#1 + {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to ULPI_D1 + {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 // Connected to ULPI_D1 + {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to ULPI_D1 + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N // Connected to ULPI_D2 + {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 // Connected to ULPI_D2 + {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N // Connected to ULPI_D2 + {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to ULPI_D7 + {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 // Connected to HDMI_CEC + {PB_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N // Connected to HDMI_CEC + {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 // Connected to PMOD\#20_DFSDM-CK7 + {PB_8_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 // Connected to PMOD\#20_DFSDM-CK7 + {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 // Connected to PMOD\#19_DFSDM-DATA7 + {PB_9_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 // Connected to PMOD\#19_DFSDM-DATA7 + {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to ULPI_D3 + {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // Connected to ULPI_D4 + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to ULPI_D6 + {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to PMOD\#9 + {PB_14_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to PMOD\#9 + {PB_14_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 // Connected to PMOD\#9 + {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N // Connected to PMOD\#8 + {PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N // Connected to PMOD\#8 + {PB_15_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 // Connected to PMOD\#8 + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to PMOD\#17_DFSDM_DATA3 + {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 // Connected to PMOD\#17_DFSDM_DATA3 + {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 // Connected to SDIO1_D0 + {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 // Connected to SDIO1_D0 + {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 // Connected to SDIO1_D1 + {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 // Connected to SDIO1_D1 + {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 // Connected to FMC_D0 + {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 // Connected to FMC_D1 + {PE_4, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N // Connected to SAI1_FS_A + {PE_5, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 // Connected to SAI1_SCK_A + {PE_6, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 // Connected to SAI1_SD_A + {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to FMC_D5 + {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // Connected to FMC_D6 + {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to FMC_D7 + {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // Connected to FMC_D8 + {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N // Connected to FMC_D9 + {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // Connected to FMC_D10 + {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // Connected to FMC_D11 + {PF_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 // Connected to QSPI_BK1_IO3 + {PF_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 // Connected to QSPI_BK1_IO2 + {PF_8, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 // Connected to PMOD\#14/ARD_D3 + {PF_8_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N // Connected to PMOD\#14/ARD_D3 + {PF_9, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 // Connected to QSPI_BK1_IO1 + {PF_9_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N // Connected to QSPI_BK1_IO1 + {PH_6, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 // Connected to FMC_SDNE1 + {PH_9, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 // Connected to FMC_D17 + {PH_10, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 // Connected to FMC_D18 + {PH_11, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 // Connected to FMC_D19 + {PH_12, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // Connected to FMC_D20 + {PH_13, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N // Connected to FMC_D21 + {PH_14, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to FMC_D22 + {PH_15, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N // Connected to FMC_D23 + {PI_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 // Connected to FMC_D24 + {PI_2, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 // Connected to FMC_D26 + {PI_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 // Connected to FMC_NBL3 + {PI_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 // Connected to FMC_D28 + {PI_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 // Connected to FMC_D29 + {PJ_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 // Connected to ARD_D9 + {PJ_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to ARD_D6 + {PJ_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N // Connected to ARD_D1 + {PJ_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 // Connected to ARD_D1 + {PJ_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // Connected to ARD_D0 + {PJ_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N // Connected to ARD_D0 + {PJ_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to ARD_D11 + {PJ_10_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 // Connected to ARD_D11 + {PJ_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // Connected to ARD_D12 + {PJ_11_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to ARD_D12 + {PK_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to ARD_D13 + {PK_0_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 // Connected to ARD_D13 + {PK_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // Connected to ARD_D10 + {PK_1_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N // Connected to ARD_D10 + {NC, NC, 0} +}; + +//*** SERIAL *** + +MBED_WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to PMOD\#1- USART2_CTS_NSS + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to ETH_MDIO + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_TX + {PA_9_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, // Connected to STDIO_UART_TX + {PA_12, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, // Connected to SPI2_SCK + {PA_15, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_4, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to HDMI_CEC + {PB_6_ALT0, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, // Connected to HDMI_CEC + {PB_6_ALT1, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART)}, // Connected to HDMI_CEC + {PB_9, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to PMOD\#19_DFSDM-DATA7 + {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to ULPI_D3 + {PB_13, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, // Connected to ULPI_D6 + {PB_14, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, // Connected to PMOD\#9 + {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to SDIO1_D2 + {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to SDIO1_D2 + {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // Connected to SDIO1_CK + {PD_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to FMC_D3 + {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_TX + {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to FMC_D13 + {PE_1, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, // Connected to FMC_NBL1 + {PE_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, // Connected to FMC_D5 + {PF_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, // Connected to QSPI_BK1_IO2 + {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, // Connected to QSPI_BK2_IO3 + {PH_13, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to FMC_D21 + {PJ_8, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, // Connected to ARD_D1 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to ETH_REF_CLK + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to ULPI_D0 + {PA_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, // Connected to CEC_CK/MCO1 + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_RX + {PA_10_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, // Connected to STDIO_UART_RX + {PA_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, // Connected to PMOD\#1 + {PB_3, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, // Connected to ULPI_D7 + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_7_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART)}, + {PB_8, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to PMOD\#20_DFSDM-CK7 + {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to ULPI_D4 + {PB_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, // Connected to ULPI_D5 + {PB_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, // Connected to PMOD\#8 + {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, // Connected to PMOD\#17_DFSDM_DATA3 + {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to SDIO1_D3 + {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to SDIO1_D3 + {PD_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to FMC_D2 + {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // Connected to SDIO1_CMD + {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_RX + {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to FMC_D14 + {PE_0, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, // Connected to FMC_NBL0 + {PE_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, // Connected to FMC_D4 + {PF_6, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, // Connected to QSPI_BK1_IO3 + {PG_9, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, // Connected to QSPI_BK2_IO2 + {PH_14, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to FMC_D22 + {PI_9, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to FMC_D30 + {PJ_9, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, // Connected to ARD_D0 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to ETH_REF_CLK + {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to SPI2_SCK + {PA_12_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, // Connected to SPI2_SCK + {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to PMOD\#9 + {PB_14_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to PMOD\#9 + {PC_8, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // Connected to SDIO1_D0 + {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to PMOD\#4- USART2_RTS + {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_15, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, // Connected to FMC_D1 + {PE_9, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, // Connected to FMC_D6 + {PF_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, // Connected to PMOD\#14/ARD_D3 + {PG_8, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, // Connected to FMC_SDCLK + {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, // Connected to ETH_TXD1 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to PMOD\#1- USART2_CTS_NSS + {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to PMOD\#1 + {PA_11_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, // Connected to PMOD\#1 + {PB_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to ULPI_D1 + {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to ULPI_D6 + {PB_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to PMOD\#8 + {PC_9, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // Connected to SDIO1_D1 + {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to PMOD\#18_DFSDM_CKOUT + {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to QSPI_BK1_IO0 + {PD_14, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, // Connected to FMC_D0 + {PE_10, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, // Connected to FMC_D7 + {PF_9, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, // Connected to QSPI_BK1_IO1 + {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, // Connected to ETH_TXD0 + {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, // Connected to FMC_SDCAS + {NC, NC, 0} +}; + +//*** SPI *** + +MBED_WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to ETH_CRS_DV + {PA_7_ALT0, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, // Connected to ETH_CRS_DV + {PB_2, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI3)}, // Connected to QSPI_CLK + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to ULPI_D7 + {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI3)}, // Connected to ULPI_D7 + {PB_5_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, // Connected to ULPI_D7 + {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to PMOD\#8 + {PC_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to ETH_MDC/SAI4_D1 + {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to PMOD\#2 + {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to SDIO1_CK +// {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI3)}, // Connected to STDIO_UART_RX + {PD_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to SPDIF_RX0 + {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to SAI1_SD_A + {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to FMC_D11 + {PF_9, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // Connected to QSPI_BK1_IO1 + {PF_11, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // Connected to FMC_SDRAS + {PG_14, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, // Connected to QSPI_BK2_IO3 + {PI_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to FMC_D27 + {PJ_10, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // Connected to ARD_D11 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_6_ALT0, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PB_4_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to PMOD\#9 + {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to PMOD\#3 + {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to SDIO1_D3 + {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to SAI1_SCK_A + {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to FMC_D10 + {PF_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // Connected to PMOD\#14/ARD_D3 + {PG_9, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to QSPI_BK2_IO2 + {PG_12, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, // Connected to ETH_TXD1 + {PH_7, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // Connected to FMC_SDCKE1 + {PI_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to FMC_D26 + {PJ_11, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // Connected to ARD_D12 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to ULPI_CK + {PA_5_ALT0, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, // Connected to ULPI_CK +// {PA_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to STDIO_UART_TX + {PA_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to SPI2_SCK + {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PB_3_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to ULPI_D3 + {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to ULPI_D6 + {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to SDIO1_D2 + {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to PMOD\#18_DFSDM_CKOUT + {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to ETH_nINT + {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to FMC_D9 + {PF_7, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // Connected to QSPI_BK1_IO2 + {PG_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to ETH_TX_EN + {PG_13, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, // Connected to ETH_TXD0 + {PH_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // Connected to FMC_SDNE1 + {PI_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to FMC_D25 + {PK_0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // Connected to ARD_D13 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PA_4_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PA_11, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to PMOD\#1 + {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PA_15_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI6)}, + {PB_4, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI2)}, + {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to PMOD\#19_DFSDM-DATA7 + {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to ULPI_D5 + {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to SAI1_FS_A + {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to FMC_D8 + {PF_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // Connected to QSPI_BK1_IO3 + {PG_8, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, // Connected to FMC_SDCLK + {PG_10, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PH_5, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // Connected to FMC_SDNWE + {PI_0, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to FMC_D24 + {PK_1, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // Connected to ARD_D10 + {NC, NC, 0} +}; + +//*** CAN *** + +MBED_WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, // Connected to PMOD\#1 + {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, // Connected to ULPI_D7 + {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, // Connected to PMOD\#20_DFSDM-CK7 + {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, // Connected to ULPI_D5 + {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, // Connected to FMC_D2 + {PH_14, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, // Connected to FMC_D22 + {PI_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, // Connected to FMC_D30 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, // Connected to SPI2_SCK + {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, // Connected to HDMI_CEC + {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, // Connected to PMOD\#19_DFSDM-DATA7 + {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, // Connected to ULPI_D6 + {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, // Connected to FMC_D3 + {PH_13, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, // Connected to FMC_D21 + {NC, NC, 0} +}; + +//*** QUADSPI *** + +MBED_WEAK const PinMap PinMap_QSPI_DATA0[] = { + {PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 // Connected to SDIO1_D1 + {PD_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 // Connected to QSPI_BK1_IO0 + {PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 // Connected to PMOD\#14/ARD_D3 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_DATA1[] = { + {PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 // Connected to SDIO1_D2 + {PD_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 + {PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 // Connected to QSPI_BK1_IO1 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_DATA2[] = { + {PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 // Connected to ETH_nINT + {PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 // Connected to QSPI_BK1_IO2 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_DATA3[] = { + {PA_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 // Connected to ETH_REF_CLK + {PD_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 + {PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 // Connected to QSPI_BK1_IO3 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = { + {PB_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_CLK // Connected to QSPI_CLK + {PF_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_CLK // Connected to ARD_A1 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = { + {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS // Connected to HDMI_CEC + {PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_NCS // Connected to ULPI_D3 + {PG_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS // Connected to QSPI_BK1_NCS + {NC, NC, 0} +}; diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PinNames.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PinNames.h new file mode 100644 index 00000000000..289e6e1d316 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PinNames.h @@ -0,0 +1,471 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2018, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + * + * Automatically generated from STM32H747XIHx.xml + */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ALT0 = 0x100, + ALT1 = 0x200, + ALT2 = 0x300, + ALT3 = 0x400, + ALT4 = 0x500 +} ALTx; + +typedef enum { + PA_0 = 0x00, + PA_0_ALT0 = PA_0 | ALT0, + PA_0_ALT1 = PA_0 | ALT1, + PA_0_ALT2 = PA_0 | ALT2, + PA_0_ALT3 = PA_0 | ALT3, + PA_1 = 0x01, + PA_1_ALT0 = PA_1 | ALT0, + PA_1_ALT1 = PA_1 | ALT1, + PA_1_ALT2 = PA_1 | ALT2, + PA_2 = 0x02, + PA_2_ALT0 = PA_2 | ALT0, + PA_2_ALT1 = PA_2 | ALT1, + PA_3 = 0x03, + PA_3_ALT0 = PA_3 | ALT0, + PA_3_ALT1 = PA_3 | ALT1, + PA_4 = 0x04, + PA_4_ALT0 = PA_4 | ALT0, + PA_4_ALT1 = PA_4 | ALT1, + PA_5 = 0x05, + PA_5_ALT0 = PA_5 | ALT0, + PA_5_ALT1 = PA_5 | ALT1, + PA_5_ALT2 = PA_5 | ALT2, + PA_6 = 0x06, + PA_6_ALT0 = PA_6 | ALT0, + PA_7 = 0x07, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, + PA_7_ALT2 = PA_7 | ALT2, + PA_8 = 0x08, + PA_9 = 0x09, + PA_9_ALT0 = PA_9 | ALT0, + PA_10 = 0x0A, + PA_10_ALT0 = PA_10 | ALT0, + PA_11 = 0x0B, + PA_11_ALT0 = PA_11 | ALT0, + PA_12 = 0x0C, + PA_12_ALT0 = PA_12 | ALT0, + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + PA_15_ALT0 = PA_15 | ALT0, + PA_15_ALT1 = PA_15 | ALT1, + + PB_0 = 0x10, + PB_0_ALT0 = PB_0 | ALT0, + PB_0_ALT1 = PB_0 | ALT1, + PB_0_ALT2 = PB_0 | ALT2, + PB_1 = 0x11, + PB_1_ALT0 = PB_1 | ALT0, + PB_1_ALT1 = PB_1 | ALT1, + PB_2 = 0x12, + PB_3 = 0x13, + PB_3_ALT0 = PB_3 | ALT0, + PB_3_ALT1 = PB_3 | ALT1, + PB_4 = 0x14, + PB_4_ALT0 = PB_4 | ALT0, + PB_4_ALT1 = PB_4 | ALT1, + PB_5 = 0x15, + PB_5_ALT0 = PB_5 | ALT0, + PB_5_ALT1 = PB_5 | ALT1, + PB_6 = 0x16, + PB_6_ALT0 = PB_6 | ALT0, + PB_6_ALT1 = PB_6 | ALT1, + PB_7 = 0x17, + PB_7_ALT0 = PB_7 | ALT0, + PB_8 = 0x18, + PB_8_ALT0 = PB_8 | ALT0, + PB_9 = 0x19, + PB_9_ALT0 = PB_9 | ALT0, + PB_10 = 0x1A, + PB_11 = 0x1B, + PB_12 = 0x1C, + PB_13 = 0x1D, + PB_14 = 0x1E, + PB_14_ALT0 = PB_14 | ALT0, + PB_14_ALT1 = PB_14 | ALT1, + PB_15 = 0x1F, + PB_15_ALT0 = PB_15 | ALT0, + PB_15_ALT1 = PB_15 | ALT1, + + PC_0 = 0x20, + PC_0_ALT0 = PC_0 | ALT0, + PC_0_ALT1 = PC_0 | ALT1, + PC_1 = 0x21, + PC_1_ALT0 = PC_1 | ALT0, + PC_1_ALT1 = PC_1 | ALT1, + PC_1_ALT2 = PC_1 | ALT2, + PC_1_ALT3 = PC_1 | ALT3, + PC_1_ALT4 = PC_1 | ALT4, + PC_2 = 0x22, + PC_2_ALT0 = PC_2 | ALT0, + PC_3 = 0x23, + PC_4 = 0x24, + PC_4_ALT0 = PC_4 | ALT0, + PC_5 = 0x25, + PC_5_ALT0 = PC_5 | ALT0, + PC_5_ALT1 = PC_5 | ALT1, + PC_5_ALT2 = PC_5 | ALT2, + PC_6 = 0x26, + PC_6_ALT0 = PC_6 | ALT0, + PC_7 = 0x27, + PC_7_ALT0 = PC_7 | ALT0, + PC_8 = 0x28, + PC_8_ALT0 = PC_8 | ALT0, + PC_9 = 0x29, + PC_9_ALT0 = PC_9 | ALT0, + PC_10 = 0x2A, + PC_10_ALT0 = PC_10 | ALT0, + PC_11 = 0x2B, + PC_11_ALT0 = PC_11 | ALT0, + PC_12 = 0x2C, + PC_13 = 0x2D, + PC_14 = 0x2E, + PC_15 = 0x2F, + + PD_0 = 0x30, + PD_1 = 0x31, + PD_2 = 0x32, + PD_3 = 0x33, + PD_4 = 0x34, + PD_5 = 0x35, + PD_6 = 0x36, + PD_7 = 0x37, + PD_8 = 0x38, + PD_9 = 0x39, + PD_10 = 0x3A, + PD_11 = 0x3B, + PD_12 = 0x3C, + PD_13 = 0x3D, + PD_14 = 0x3E, + PD_15 = 0x3F, + + PE_0 = 0x40, + PE_1 = 0x41, + PE_2 = 0x42, + PE_3 = 0x43, + PE_4 = 0x44, + PE_5 = 0x45, + PE_6 = 0x46, + PE_7 = 0x47, + PE_8 = 0x48, + PE_9 = 0x49, + PE_10 = 0x4A, + PE_11 = 0x4B, + PE_12 = 0x4C, + PE_13 = 0x4D, + PE_14 = 0x4E, + PE_15 = 0x4F, + + PF_0 = 0x50, + PF_1 = 0x51, + PF_2 = 0x52, + PF_3 = 0x53, + PF_4 = 0x54, + PF_4_ALT0 = PF_4 | ALT0, + PF_5 = 0x55, + PF_6 = 0x56, + PF_6_ALT0 = PF_6 | ALT0, + PF_7 = 0x57, + PF_8 = 0x58, + PF_8_ALT0 = PF_8 | ALT0, + PF_9 = 0x59, + PF_9_ALT0 = PF_9 | ALT0, + PF_10 = 0x5A, + PF_10_ALT0 = PF_10 | ALT0, + PF_11 = 0x5B, + PF_12 = 0x5C, + PF_12_ALT0 = PF_12 | ALT0, + PF_13 = 0x5D, + PF_14 = 0x5E, + PF_14_ALT0 = PF_14 | ALT0, + PF_15 = 0x5F, + + PG_0 = 0x60, + PG_1 = 0x61, + PG_2 = 0x62, + PG_3 = 0x63, + PG_4 = 0x64, + PG_5 = 0x65, + PG_6 = 0x66, + PG_7 = 0x67, + PG_8 = 0x68, + PG_9 = 0x69, + PG_10 = 0x6A, + PG_11 = 0x6B, + PG_12 = 0x6C, + PG_13 = 0x6D, + PG_14 = 0x6E, + PG_15 = 0x6F, + + PH_0 = 0x70, + PH_1 = 0x71, + PH_2 = 0x72, + PH_3 = 0x73, + PH_3_ALT0 = PH_3 | ALT0, + PH_4 = 0x74, + PH_4_ALT0 = PH_4 | ALT0, + PH_5 = 0x75, + PH_5_ALT0 = PH_5 | ALT0, + PH_6 = 0x76, + PH_7 = 0x77, + PH_8 = 0x78, + PH_9 = 0x79, + PH_10 = 0x7A, + PH_11 = 0x7B, + PH_12 = 0x7C, + PH_13 = 0x7D, + PH_14 = 0x7E, + PH_15 = 0x7F, + + PI_0 = 0x80, + PI_1 = 0x81, + PI_2 = 0x82, + PI_3 = 0x83, + PI_4 = 0x84, + PI_5 = 0x85, + PI_6 = 0x86, + PI_7 = 0x87, + PI_8 = 0x88, + PI_9 = 0x89, + PI_10 = 0x8A, + PI_11 = 0x8B, + PI_12 = 0x8C, + PI_13 = 0x8D, + PI_14 = 0x8E, + PI_15 = 0x8F, + + PJ_0 = 0x90, + PJ_1 = 0x91, + PJ_2 = 0x92, + PJ_3 = 0x93, + PJ_4 = 0x94, + PJ_5 = 0x95, + PJ_6 = 0x96, + PJ_7 = 0x97, + PJ_8 = 0x98, + PJ_8_ALT0 = PJ_8 | ALT0, + PJ_9 = 0x99, + PJ_9_ALT0 = PJ_9 | ALT0, + PJ_10 = 0x9A, + PJ_10_ALT0 = PJ_10 | ALT0, + PJ_11 = 0x9B, + PJ_11_ALT0 = PJ_11 | ALT0, + PJ_12 = 0x9C, + PJ_13 = 0x9D, + PJ_14 = 0x9E, + PJ_15 = 0x9F, + + PK_0 = 0xA0, + PK_0_ALT0 = PK_0 | ALT0, + PK_1 = 0xA1, + PK_1_ALT0 = PK_1 | ALT0, + PK_2 = 0xA2, + PK_3 = 0xA3, + + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + ADC_VBAT = 0xF2, + + // Arduino connector namings + A0 = PF_7, + A1 = PF_10, + A2 = PA_0, + A3 = PA_1, + A4 = PC_2, + A5 = PC_3, + D0 = PJ_9, + D1 = PJ_8, + D2 = PJ_3, + D3 = PF_8, + D4 = PJ_4, + D5 = PA_6, + D6 = PJ_7, + D7 = PJ_0, + D8 = PJ_5, + D9 = PJ_6, + D10 = PK_1, + D11 = PJ_10, + D12 = PJ_11, + D13 = PK_3, + D14 = PD_13, + D15 = PD_12, + + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_9, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_10, +#endif + + // Generic signals namings + LED1 = PI_12, // Green + LED2 = PI_13, // Orange + LED3 = PI_14, // Red + LED4 = PI_15, // Blue + + // Standardized button names + USER_BUTTON = PC_13, + BUTTON1 = USER_BUTTON, + + SERIAL_TX = STDIO_UART_TX, // Virtual Com Port + SERIAL_RX = STDIO_UART_RX, // Virtual Com Port + USBTX = STDIO_UART_TX, // Virtual Com Port + USBRX = STDIO_UART_RX, // Virtual Com Port + I2C_SCL = D15, + I2C_SDA = D14, + SPI_MOSI = D11, + SPI_MISO = D12, + SPI_SCK = D13, + SPI_CS = D10, + PWM_OUT = D9, + + /**** USB pins ****/ + USB_OTG_FS_DM = PA_11, + USB_OTG_FS_DP = PA_12, + USB_OTG_FS_ID = PA_10, + USB_OTG_FS_SOF = PA_8, + USB_OTG_FS_VBUS = PA_9, + USB_OTG_HS_DM = PB_14, + USB_OTG_HS_DP = PB_15, + USB_OTG_HS_ID = PB_12, + USB_OTG_HS_SOF = PA_4, + USB_OTG_HS_ULPI_CK = PA_5, + USB_OTG_HS_ULPI_D0 = PA_3, + USB_OTG_HS_ULPI_D1 = PB_0, + USB_OTG_HS_ULPI_D2 = PB_1, + USB_OTG_HS_ULPI_D3 = PB_10, + USB_OTG_HS_ULPI_D4 = PB_11, + USB_OTG_HS_ULPI_D5 = PB_12, + USB_OTG_HS_ULPI_D6 = PB_13, + USB_OTG_HS_ULPI_D7 = PB_5, + USB_OTG_HS_ULPI_DIR = PI_11, + USB_OTG_HS_ULPI_DIR_ALT0 = PC_2, + USB_OTG_HS_ULPI_NXT = PC_3, + USB_OTG_HS_ULPI_NXT_ALT0 = PH_4, + USB_OTG_HS_ULPI_STP = PC_0, + USB_OTG_HS_VBUS = PB_13, + + /**** ETHERNET pins ****/ + ETH_COL = PH_3, + ETH_COL_ALT0 = PA_3, + ETH_CRS = PH_2, + ETH_CRS_ALT0 = PA_0, + ETH_CRS_DV = PA_7, + ETH_MDC = PC_1, + ETH_MDIO = PA_2, + ETH_PPS_OUT = PB_5, + ETH_PPS_OUT_ALT0 = PG_8, + ETH_REF_CLK = PA_1, + ETH_RXD0 = PC_4, + ETH_RXD1 = PC_5, + ETH_RXD2 = PH_6, + ETH_RXD2_ALT0 = PB_0, + ETH_RXD3 = PB_1, + ETH_RXD3_ALT0 = PH_7, + ETH_RX_CLK = PA_1, + ETH_RX_DV = PA_7, + ETH_RX_ER = PI_10, + ETH_RX_ER_ALT0 = PB_10, + ETH_TXD0 = PG_13, + ETH_TXD0_ALT0 = PB_12, + ETH_TXD1 = PG_12, + ETH_TXD1_ALT0 = PG_14, + ETH_TXD1_ALT1 = PB_13, + ETH_TXD2 = PC_2, + ETH_TXD3 = PE_2, + ETH_TXD3_ALT0 = PB_8, + ETH_TX_CLK = PC_3, + ETH_TX_EN = PG_11, + ETH_TX_EN_ALT0 = PB_11, + + /**** OSCILLATOR pins ****/ + RCC_OSC32_IN = PC_14, + RCC_OSC32_OUT = PC_15, + RCC_OSC_IN = PH_0, + RCC_OSC_OUT = PH_1, + + /**** DEBUG pins ****/ + DEBUG_JTCK_SWCLK = PA_14, + DEBUG_JTDI = PA_15, + DEBUG_JTDO_SWO = PB_3, + DEBUG_JTMS_SWDIO = PA_13, + DEBUG_JTRST = PB_4, + DEBUG_TRACECLK = PE_2, + DEBUG_TRACED0 = PE_3, + DEBUG_TRACED0_ALT0 = PG_13, + DEBUG_TRACED0_ALT1 = PC_1, + DEBUG_TRACED1 = PE_4, + DEBUG_TRACED1_ALT0 = PG_14, + DEBUG_TRACED1_ALT1 = PC_8, + DEBUG_TRACED2 = PE_5, + DEBUG_TRACED2_ALT0 = PD_2, + DEBUG_TRACED3 = PC_12, + DEBUG_TRACED3_ALT0 = PE_6, + DEBUG_TRGIN = PJ_7, + DEBUG_TRGIO = PC_7, + DEBUG_TRGOUT = PJ_12, + PWR_PVD_IN = PB_7, + PWR_WKUP0 = PA_0, + PWR_WKUP1 = PA_2, + PWR_WKUP2 = PC_13, + PWR_WKUP3 = PI_8, + PWR_WKUP4 = PI_11, + PWR_WKUP5 = PC_1, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/system_clock.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/system_clock.c new file mode 100644 index 00000000000..34bc15cedfa --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/system_clock.c @@ -0,0 +1,207 @@ +/* mbed Microcontroller Library +* Copyright (c) 2006-2017 ARM Limited +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*/ + +/** + * This file configures the system clock as follows: + *-------------------------------------------------------------------- + * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) + * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) + * | 3- USE_PLL_HSI (internal 64 MHz clock) + *-------------------------------------------------------------------- + * SYSCLK(MHz) | 400 + * AHBCLK (MHz) | 200 + * APB1CLK (MHz) | 100 + * APB2CLK (MHz) | 100 + * APB3CLK (MHz) | 100 + * APB4CLK (MHz) | 100 + * USB capable (48 MHz) | YES + *-------------------------------------------------------------------- +**/ + +#include "stm32h7xx.h" +#include "nvic_addr.h" +#include "mbed_error.h" + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + +// clock source is selected with CLOCK_SOURCE in json config +#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO) +#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) +#define USE_PLL_HSI 0x2 // Use HSI internal clock + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +uint8_t SetSysClock_PLL_HSE(uint8_t bypass); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +uint8_t SetSysClock_PLL_HSI(void); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ + +void SetSysClock(void) +{ + +#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) + /* 1- Try to start with HSE and external clock (MCO from STLink PCB part) */ + if (SetSysClock_PLL_HSE(1) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) + /* 2- If fail try to start with HSE and external xtal */ + if (SetSysClock_PLL_HSE(0) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSI) + /* 3- If fail start with HSI clock */ + if (SetSysClock_PLL_HSI() == 0) +#endif + { + error("SetSysClock failed\n"); + } + } + } +} + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSE(uint8_t bypass) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + HAL_PWREx_ConfigSupply(PWR_DIRECT_SMPS_SUPPLY); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + if (bypass) { + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; + } else { + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + } + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 5; // 5 MHz + RCC_OscInitStruct.PLL.PLLN = 192; // 960 MHz + RCC_OscInitStruct.PLL.PLLP = 2; // PLLCLK = SYSCLK = 480 MHz + RCC_OscInitStruct.PLL.PLLQ = 116; // PLL1Q used for FDCAN = 10 MHz + RCC_OscInitStruct.PLL.PLLR = 2; + RCC_OscInitStruct.PLL.PLLFRACN = 0; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + /* Select PLL as system clock source and configure bus clocks dividers */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | + RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | + RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_D3PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; + RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; + RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { + return 0; // FAIL + } + + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_USB; + PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + return 0; // FAIL + } + + __HAL_RCC_CSI_ENABLE() ; + + __HAL_RCC_SYSCFG_CLK_ENABLE() ; + + HAL_EnableCompensationCell(); + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +/******************************************************************************/ +/* PLL (clocked by HSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSI(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + /*!< Supply configuration update enable */ + HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); + /* The voltage scaling allows optimizing the power consumption when the device is + clocked below the maximum system frequency, to update the voltage scaling value + regarding system frequency refer to product datasheet. */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + // Enable HSI oscillator and activate PLL with HSI as source + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_CSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.CSIState = RCC_CSI_OFF; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = 8; + RCC_OscInitStruct.PLL.PLLN = 100; + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLR = 2; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + /* Select PLL as system clock source and configure bus clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | \ + RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; + RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + return 0; // FAIL + } + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/system_stm32h7xx.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/system_stm32h7xx.c new file mode 100644 index 00000000000..e5b799374df --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/system_stm32h7xx.c @@ -0,0 +1,368 @@ +/** + ****************************************************************************** + * @file system_stm32h7xx_dualcore_boot_cm4_cm7.c + * @author MCD Application Team + * @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File. + * This provides system initialization template function is case of + * an application using a dual core STM32H7 device where + * Cortex-M7 and Cortex-M4 boot are enabled at the FLASH option bytes + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32h7xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32h7xx_system + * @{ + */ + +/** @addtogroup STM32H7xx_System_Private_Includes + * @{ + */ + +#include "stm32h7xx.h" +#include + +#if !defined (HSE_VALUE) +#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (CSI_VALUE) + #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* CSI_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 64000000; + uint32_t SystemD2Clock = 64000000; + const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting and vector table location + * configuration. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ + #endif + + /*SEVONPEND enabled so that an interrupt coming from the CPU(n) interrupt signal is + detectable by the CPU after a WFI/WFE instruction.*/ + SCB->SCR |= SCB_SCR_SEVONPEND_Pos; + +#ifdef CORE_CM7 + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= RCC_CR_HSION; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */ + RCC->CR &= 0xEAF6ED7FU; + + /* Reset D1CFGR register */ + RCC->D1CFGR = 0x00000000; + + /* Reset D2CFGR register */ + RCC->D2CFGR = 0x00000000; + + /* Reset D3CFGR register */ + RCC->D3CFGR = 0x00000000; + + /* Reset PLLCKSELR register */ + RCC->PLLCKSELR = 0x00000000; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x00000000; + /* Reset PLL1DIVR register */ + RCC->PLL1DIVR = 0x00000000; + /* Reset PLL1FRACR register */ + RCC->PLL1FRACR = 0x00000000; + + /* Reset PLL2DIVR register */ + RCC->PLL2DIVR = 0x00000000; + + /* Reset PLL2FRACR register */ + + RCC->PLL2FRACR = 0x00000000; + /* Reset PLL3DIVR register */ + RCC->PLL3DIVR = 0x00000000; + + /* Reset PLL3FRACR register */ + RCC->PLL3FRACR = 0x00000000; + + /* Reset HSEBYP bit */ + RCC->CR &= 0xFFFBFFFFU; + + /* Disable all interrupts */ + RCC->CIER = 0x00000000; + + /* Enable CortexM7 HSEM EXTI line (line 78)*/ + EXTI_D2->EMR3 |= 0x4000UL; + + + if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) + { + /* if stm32h7 revY*/ + /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ + *((__IO uint32_t*)0x51008108) = 0x000000001U; + } + +#endif /* CORE_CM7*/ + +#ifdef CORE_CM4 + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = D2_AHBSRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif + +#else +#ifdef CORE_CM7 + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM */ +#else + SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif + +#else +#error Please #define CORE_CM4 or CORE_CM7 +#endif +#endif + +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock , it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*) + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*), + * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. + * + * (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value + * 64 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp; + float_t fracn1, pllvco; + + /* Get SYSCLK source -------------------------------------------------------*/ + + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ + SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); + + break; + + case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ + SystemCoreClock = CSI_VALUE; + break; + + case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + + case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ; + pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos); + fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3)); + + if (pllm != 0U) + { + switch (pllsource) + { + case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */ + + hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ; + pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + + break; + + case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */ + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + + case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */ + pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + + default: + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + } + pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; + SystemCoreClock = (uint32_t)(float_t)(pllvco/(float_t)pllp); + } + else + { + SystemCoreClock = 0U; + } + break; + + default: + SystemCoreClock = CSI_VALUE; + break; + } + + /* Compute SystemClock frequency --------------------------------------------------*/ + tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]; + + /* SystemCoreClock frequency : CM7 CPU frequency */ + SystemCoreClock >>= tmp; + + /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */ + SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); + +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_ARM_STD/startup_stm32h747xx.S b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_ARM_STD/startup_stm32h747xx.S new file mode 100644 index 00000000000..317b969fbd5 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_ARM_STD/startup_stm32h747xx.S @@ -0,0 +1,574 @@ +;******************** (C) COPYRIGHT 2019 STMicroelectronics ******************** +;* File Name : startup_stm32h747xx.s +;* @author MCD Application Team +;* Description : STM32H7xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2019 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** + +__initial_sp EQU 0x20020000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog interrupt ( wwdg1_it, wwdg2_it) + DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt + DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt + DCD CM7_SEV_IRQHandler ; CM7 Send event interrupt for CM4 + DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD RNG_IRQHandler ; Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD SAI2_IRQHandler ; SAI2 + DCD QUADSPI_IRQHandler ; QUADSPI + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD SPDIF_RX_IRQHandler ; SPDIF_RX + DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out + DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt + DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts + DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt + DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt + DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt + DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt + DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt + DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt + DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt + DCD SAI3_IRQHandler ; SAI3 global Interrupt + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TIM15_IRQHandler ; TIM15 global Interrupt + DCD TIM16_IRQHandler ; TIM16 global Interrupt + DCD TIM17_IRQHandler ; TIM17 global Interrupt + DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt + DCD MDIOS_IRQHandler ; MDIOS global Interrupt + DCD JPEG_IRQHandler ; JPEG global Interrupt + DCD MDMA_IRQHandler ; MDMA global Interrupt + DCD DSI_IRQHandler ; DSI global Interrupt + DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt + DCD HSEM1_IRQHandler ; HSEM1 global Interrupt + DCD HSEM2_IRQHandler ; HSEM2 global Interrupt + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt + DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt + DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt + DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt + DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt + DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt + DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt + DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt + DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt + DCD COMP1_IRQHandler ; COMP1 global Interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt + DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt + DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt + DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) + DCD CRS_IRQHandler ; Clock Recovery Global Interrupt + DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt + DCD SAI4_IRQHandler ; SAI4 global interrupt + DCD 0 ; Reserved + DCD HOLD_CORE_IRQHandler ; Hold core interrupt + DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_AVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT FDCAN1_IT0_IRQHandler [WEAK] + EXPORT FDCAN2_IT0_IRQHandler [WEAK] + EXPORT FDCAN1_IT1_IRQHandler [WEAK] + EXPORT FDCAN2_IT1_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT FDCAN_CAL_IRQHandler [WEAK] + EXPORT CM7_SEV_IRQHandler [WEAK] + EXPORT CM4_SEV_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT SPDIF_RX_IRQHandler [WEAK] + EXPORT OTG_FS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_FS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMAMUX1_OVR_IRQHandler [WEAK] + EXPORT HRTIM1_Master_IRQHandler [WEAK] + EXPORT HRTIM1_TIMA_IRQHandler [WEAK] + EXPORT HRTIM1_TIMB_IRQHandler [WEAK] + EXPORT HRTIM1_TIMC_IRQHandler [WEAK] + EXPORT HRTIM1_TIMD_IRQHandler [WEAK] + EXPORT HRTIM1_TIME_IRQHandler [WEAK] + EXPORT HRTIM1_FLT_IRQHandler [WEAK] + EXPORT DFSDM1_FLT0_IRQHandler [WEAK] + EXPORT DFSDM1_FLT1_IRQHandler [WEAK] + EXPORT DFSDM1_FLT2_IRQHandler [WEAK] + EXPORT DFSDM1_FLT3_IRQHandler [WEAK] + EXPORT SAI3_IRQHandler [WEAK] + EXPORT SWPMI1_IRQHandler [WEAK] + EXPORT TIM15_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT MDIOS_WKUP_IRQHandler [WEAK] + EXPORT MDIOS_IRQHandler [WEAK] + EXPORT JPEG_IRQHandler [WEAK] + EXPORT MDMA_IRQHandler [WEAK] + EXPORT DSI_IRQHandler [WEAK] + EXPORT SDMMC2_IRQHandler [WEAK] + EXPORT HSEM1_IRQHandler [WEAK] + EXPORT HSEM2_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT DMAMUX2_OVR_IRQHandler [WEAK] + EXPORT BDMA_Channel0_IRQHandler [WEAK] + EXPORT BDMA_Channel1_IRQHandler [WEAK] + EXPORT BDMA_Channel2_IRQHandler [WEAK] + EXPORT BDMA_Channel3_IRQHandler [WEAK] + EXPORT BDMA_Channel4_IRQHandler [WEAK] + EXPORT BDMA_Channel5_IRQHandler [WEAK] + EXPORT BDMA_Channel6_IRQHandler [WEAK] + EXPORT BDMA_Channel7_IRQHandler [WEAK] + EXPORT COMP1_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT LPTIM3_IRQHandler [WEAK] + EXPORT LPTIM4_IRQHandler [WEAK] + EXPORT LPTIM5_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT WWDG_RST_IRQHandler [WEAK] + EXPORT CRS_IRQHandler [WEAK] + EXPORT ECC_IRQHandler [WEAK] + EXPORT SAI4_IRQHandler [WEAK] + EXPORT HOLD_CORE_IRQHandler [WEAK] + EXPORT WAKEUP_PIN_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_AVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +FDCAN1_IT0_IRQHandler +FDCAN2_IT0_IRQHandler +FDCAN1_IT1_IRQHandler +FDCAN2_IT1_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +FDCAN_CAL_IRQHandler +CM7_SEV_IRQHandler +CM4_SEV_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler +SAI2_IRQHandler +QUADSPI_IRQHandler +LPTIM1_IRQHandler +CEC_IRQHandler +I2C4_EV_IRQHandler +I2C4_ER_IRQHandler +SPDIF_RX_IRQHandler +OTG_FS_EP1_OUT_IRQHandler +OTG_FS_EP1_IN_IRQHandler +OTG_FS_WKUP_IRQHandler +OTG_FS_IRQHandler +DMAMUX1_OVR_IRQHandler +HRTIM1_Master_IRQHandler +HRTIM1_TIMA_IRQHandler +HRTIM1_TIMB_IRQHandler +HRTIM1_TIMC_IRQHandler +HRTIM1_TIMD_IRQHandler +HRTIM1_TIME_IRQHandler +HRTIM1_FLT_IRQHandler +DFSDM1_FLT0_IRQHandler +DFSDM1_FLT1_IRQHandler +DFSDM1_FLT2_IRQHandler +DFSDM1_FLT3_IRQHandler +SAI3_IRQHandler +SWPMI1_IRQHandler +TIM15_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +MDIOS_WKUP_IRQHandler +MDIOS_IRQHandler +JPEG_IRQHandler +MDMA_IRQHandler +DSI_IRQHandler +SDMMC2_IRQHandler +HSEM1_IRQHandler +HSEM2_IRQHandler +ADC3_IRQHandler +DMAMUX2_OVR_IRQHandler +BDMA_Channel0_IRQHandler +BDMA_Channel1_IRQHandler +BDMA_Channel2_IRQHandler +BDMA_Channel3_IRQHandler +BDMA_Channel4_IRQHandler +BDMA_Channel5_IRQHandler +BDMA_Channel6_IRQHandler +BDMA_Channel7_IRQHandler +COMP1_IRQHandler +LPTIM2_IRQHandler +LPTIM3_IRQHandler +LPTIM4_IRQHandler +LPTIM5_IRQHandler +LPUART1_IRQHandler +WWDG_RST_IRQHandler +CRS_IRQHandler +ECC_IRQHandler +SAI4_IRQHandler +HOLD_CORE_IRQHandler +WAKEUP_PIN_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_ARM_STD/stm32h747xI.sct b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_ARM_STD/stm32h747xI.sct new file mode 100644 index 00000000000..34101205f07 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_ARM_STD/stm32h747xI.sct @@ -0,0 +1,66 @@ +#! armcc -E +; Scatter-Loading Description File +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2016, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x08000000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0x200000 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +#define Stack_Size MBED_BOOT_STACK_SIZE + +#define MBED_RAM_START 0x20000000 +#define MBED_RAM_SIZE 0x20000 +#define MBED_VECTTABLE_RAM_START (MBED_RAM_START) +#define MBED_VECTTABLE_RAM_SIZE 0x298 +#define MBED_RAM0_START (MBED_VECTTABLE_RAM_START + MBED_VECTTABLE_RAM_SIZE) +#define MBED_RAM0_SIZE (MBED_RAM_SIZE - MBED_VECTTABLE_RAM_SIZE) + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 (MBED_RAM0_START) (MBED_RAM0_SIZE-Stack_Size) { ; RW data + .ANY (+RW +ZI) + } + + ARM_LIB_STACK (MBED_RAM0_START+MBED_RAM0_SIZE) EMPTY -Stack_Size { ; stack + } +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI.ld b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI.ld new file mode 100644 index 00000000000..307d8c07b4b --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI.ld @@ -0,0 +1,169 @@ +/* Linker script to configure memory regions. */ + +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x08000000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 2048K +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +STACK_SIZE = MBED_BOOT_STACK_SIZE; + +MEMORY +{ + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + RAM (rwx) : ORIGIN = 0x20000298, LENGTH = 128K - 0x298 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(8); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(8); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(8); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(8); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM + + .bss : + { + . = ALIGN(8); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(8); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + end = __end__; + *(.heap*) + . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_GCC_ARM/startup_stm32h747xx.S b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_GCC_ARM/startup_stm32h747xx.S new file mode 100644 index 00000000000..ceee064d186 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_GCC_ARM/startup_stm32h747xx.S @@ -0,0 +1,771 @@ +/** + ****************************************************************************** + * @file startup_stm32h747xx.s + * @author MCD Application Team + * @brief STM32H747xx Devices vector table for GCC based toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m7 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + // Calling the crt0 'cold-start' entry point. There __libc_init_array is called + // and when existing hardware_init_hook() and software_init_hook() before + // starting main(). software_init_hook() is available and has to be called due + // to initializsation when using rtos. + bl _start + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */ + .word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */ + .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */ + .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */ + .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */ + .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word 0 /* Reserved */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FMC_IRQHandler /* FMC */ + .word SDMMC1_IRQHandler /* SDMMC1 */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt */ + .word CM7_SEV_IRQHandler /* CM7 Send event interrupt for CM4 */ + .word CM4_SEV_IRQHandler /* CM4 Send event interrupt for CM7 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word 0 /* Reserved */ + .word RNG_IRQHandler /* Rng */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word SAI1_IRQHandler /* SAI1 */ + .word LTDC_IRQHandler /* LTDC */ + .word LTDC_ER_IRQHandler /* LTDC error */ + .word DMA2D_IRQHandler /* DMA2D */ + .word SAI2_IRQHandler /* SAI2 */ + .word QUADSPI_IRQHandler /* QUADSPI */ + .word LPTIM1_IRQHandler /* LPTIM1 */ + .word CEC_IRQHandler /* HDMI_CEC */ + .word I2C4_EV_IRQHandler /* I2C4 Event */ + .word I2C4_ER_IRQHandler /* I2C4 Error */ + .word SPDIF_RX_IRQHandler /* SPDIF_RX */ + .word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */ + .word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */ + .word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */ + .word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */ + .word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */ + .word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */ + .word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */ + .word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */ + .word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */ + .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */ + .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */ + .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */ + .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */ + .word SAI3_IRQHandler /* SAI3 global Interrupt */ + .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */ + .word TIM15_IRQHandler /* TIM15 global Interrupt */ + .word TIM16_IRQHandler /* TIM16 global Interrupt */ + .word TIM17_IRQHandler /* TIM17 global Interrupt */ + .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */ + .word MDIOS_IRQHandler /* MDIOS global Interrupt */ + .word JPEG_IRQHandler /* JPEG global Interrupt */ + .word MDMA_IRQHandler /* MDMA global Interrupt */ + .word DSI_IRQHandler /* DSI global Interrupt */ + .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */ + .word HSEM1_IRQHandler /* HSEM1 global Interrupt */ + .word HSEM2_IRQHandler /* HSEM1 global Interrupt */ + .word ADC3_IRQHandler /* ADC3 global Interrupt */ + .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */ + .word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */ + .word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */ + .word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */ + .word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */ + .word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */ + .word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */ + .word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */ + .word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */ + .word COMP1_IRQHandler /* COMP1 global Interrupt */ + .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */ + .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */ + .word LPTIM4_IRQHandler /* LP TIM4 global interrupt */ + .word LPTIM5_IRQHandler /* LP TIM5 global interrupt */ + .word LPUART1_IRQHandler /* LP UART1 interrupt */ + .word WWDG_RST_IRQHandler /* Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) */ + .word CRS_IRQHandler /* Clock Recovery Global Interrupt */ + .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */ + .word SAI4_IRQHandler /* SAI4 global interrupt */ + .word 0 /* Reserved */ + .word HOLD_CORE_IRQHandler /* Hold core interrupt */ + .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_AVD_IRQHandler + .thumb_set PVD_AVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak FDCAN1_IT0_IRQHandler + .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler + + .weak FDCAN2_IT0_IRQHandler + .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler + + .weak FDCAN1_IT1_IRQHandler + .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler + + .weak FDCAN2_IT1_IRQHandler + .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak FDCAN_CAL_IRQHandler + .thumb_set FDCAN_CAL_IRQHandler,Default_Handler + + .weak CM7_SEV_IRQHandler + .thumb_set CM7_SEV_IRQHandler,Default_Handler + + .weak CM4_SEV_IRQHandler + .thumb_set CM4_SEV_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak LTDC_IRQHandler + .thumb_set LTDC_IRQHandler,Default_Handler + + .weak LTDC_ER_IRQHandler + .thumb_set LTDC_ER_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + + .weak SAI2_IRQHandler + .thumb_set SAI2_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak I2C4_EV_IRQHandler + .thumb_set I2C4_EV_IRQHandler,Default_Handler + + .weak I2C4_ER_IRQHandler + .thumb_set I2C4_ER_IRQHandler,Default_Handler + + .weak SPDIF_RX_IRQHandler + .thumb_set SPDIF_RX_IRQHandler,Default_Handler + + .weak OTG_FS_EP1_OUT_IRQHandler + .thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_FS_EP1_IN_IRQHandler + .thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMAMUX1_OVR_IRQHandler + .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler + + .weak HRTIM1_Master_IRQHandler + .thumb_set HRTIM1_Master_IRQHandler,Default_Handler + + .weak HRTIM1_TIMA_IRQHandler + .thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler + + .weak HRTIM1_TIMB_IRQHandler + .thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler + + .weak HRTIM1_TIMC_IRQHandler + .thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler + + .weak HRTIM1_TIMD_IRQHandler + .thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler + + .weak HRTIM1_TIME_IRQHandler + .thumb_set HRTIM1_TIME_IRQHandler,Default_Handler + + .weak HRTIM1_FLT_IRQHandler + .thumb_set HRTIM1_FLT_IRQHandler,Default_Handler + + .weak DFSDM1_FLT0_IRQHandler + .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler + + .weak DFSDM1_FLT1_IRQHandler + .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler + + .weak DFSDM1_FLT2_IRQHandler + .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler + + .weak DFSDM1_FLT3_IRQHandler + .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler + + .weak SAI3_IRQHandler + .thumb_set SAI3_IRQHandler,Default_Handler + + .weak SWPMI1_IRQHandler + .thumb_set SWPMI1_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak MDIOS_WKUP_IRQHandler + .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler + + .weak MDIOS_IRQHandler + .thumb_set MDIOS_IRQHandler,Default_Handler + + .weak JPEG_IRQHandler + .thumb_set JPEG_IRQHandler,Default_Handler + + .weak MDMA_IRQHandler + .thumb_set MDMA_IRQHandler,Default_Handler + + .weak DSI_IRQHandler + .thumb_set DSI_IRQHandler,Default_Handler + + .weak SDMMC2_IRQHandler + .thumb_set SDMMC2_IRQHandler,Default_Handler + + .weak HSEM1_IRQHandler + .thumb_set HSEM1_IRQHandler,Default_Handler + + .weak HSEM2_IRQHandler + .thumb_set HSEM2_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak DMAMUX2_OVR_IRQHandler + .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler + + .weak BDMA_Channel0_IRQHandler + .thumb_set BDMA_Channel0_IRQHandler,Default_Handler + + .weak BDMA_Channel1_IRQHandler + .thumb_set BDMA_Channel1_IRQHandler,Default_Handler + + .weak BDMA_Channel2_IRQHandler + .thumb_set BDMA_Channel2_IRQHandler,Default_Handler + + .weak BDMA_Channel3_IRQHandler + .thumb_set BDMA_Channel3_IRQHandler,Default_Handler + + .weak BDMA_Channel4_IRQHandler + .thumb_set BDMA_Channel4_IRQHandler,Default_Handler + + .weak BDMA_Channel5_IRQHandler + .thumb_set BDMA_Channel5_IRQHandler,Default_Handler + + .weak BDMA_Channel6_IRQHandler + .thumb_set BDMA_Channel6_IRQHandler,Default_Handler + + .weak BDMA_Channel7_IRQHandler + .thumb_set BDMA_Channel7_IRQHandler,Default_Handler + + .weak COMP1_IRQHandler + .thumb_set COMP1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak LPTIM3_IRQHandler + .thumb_set LPTIM3_IRQHandler,Default_Handler + + .weak LPTIM4_IRQHandler + .thumb_set LPTIM4_IRQHandler,Default_Handler + + .weak LPTIM5_IRQHandler + .thumb_set LPTIM5_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak WWDG_RST_IRQHandler + .thumb_set WWDG_RST_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler + + .weak ECC_IRQHandler + .thumb_set ECC_IRQHandler,Default_Handler + + .weak SAI4_IRQHandler + .thumb_set SAI4_IRQHandler,Default_Handler + + .weak HOLD_CORE_IRQHandler + .thumb_set HOLD_CORE_IRQHandler,Default_Handler + + .weak WAKEUP_PIN_IRQHandler + .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_IAR/startup_stm32h747xx.S b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_IAR/startup_stm32h747xx.S new file mode 100644 index 00000000000..1d9887a66ac --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_IAR/startup_stm32h747xx.S @@ -0,0 +1,1009 @@ +;/******************** (C) COPYRIGHT 2019 STMicroelectronics ******************** +;* File Name : startup_stm32h747xx.s +;* Author : MCD Application Team +;* Description : STM32H747xx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +;* @attention +;* +;*

© Copyright (c) 2019 STMicroelectronics. +;* All rights reserved.

+;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) + DCD PVD_AVD_IRQHandler ; PVD/AVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 + DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0 + DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0 + DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1 + DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1 + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt + DCD CM7_SEV_IRQHandler ; CM7 Send event interrupt for CM4 + DCD CM4_SEV_IRQHandler ; CM4 Send event interrupt for CM7 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD RNG_IRQHandler ; Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD SAI2_IRQHandler ; SAI2 + DCD QUADSPI_IRQHandler ; QUADSPI + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD SPDIF_RX_IRQHandler ; SPDIF_RX + DCD OTG_FS_EP1_OUT_IRQHandler ; USB OTG FS End Point 1 Out + DCD OTG_FS_EP1_IN_IRQHandler ; USB OTG FS End Point 1 In + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt + DCD HRTIM1_Master_IRQHandler ; HRTIM Master Timer global Interrupts + DCD HRTIM1_TIMA_IRQHandler ; HRTIM Timer A global Interrupt + DCD HRTIM1_TIMB_IRQHandler ; HRTIM Timer B global Interrupt + DCD HRTIM1_TIMC_IRQHandler ; HRTIM Timer C global Interrupt + DCD HRTIM1_TIMD_IRQHandler ; HRTIM Timer D global Interrupt + DCD HRTIM1_TIME_IRQHandler ; HRTIM Timer E global Interrupt + DCD HRTIM1_FLT_IRQHandler ; HRTIM Fault global Interrupt + DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt + DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt + DCD SAI3_IRQHandler ; SAI3 global Interrupt + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TIM15_IRQHandler ; TIM15 global Interrupt + DCD TIM16_IRQHandler ; TIM16 global Interrupt + DCD TIM17_IRQHandler ; TIM17 global Interrupt + DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt + DCD MDIOS_IRQHandler ; MDIOS global Interrupt + DCD JPEG_IRQHandler ; JPEG global Interrupt + DCD MDMA_IRQHandler ; MDMA global Interrupt + DCD DSI_IRQHandler ; DSI global Interrupt + DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt + DCD HSEM1_IRQHandler ; HSEM1 global Interrupt + DCD HSEM2_IRQHandler ; HSEM2 global Interrupt + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt + DCD BDMA_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt + DCD BDMA_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt + DCD BDMA_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt + DCD BDMA_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt + DCD BDMA_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt + DCD BDMA_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt + DCD BDMA_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt + DCD BDMA_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt + DCD COMP1_IRQHandler ; COMP1 global Interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt + DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt + DCD LPTIM4_IRQHandler ; LP TIM4 global interrupt + DCD LPTIM5_IRQHandler ; LP TIM5 global interrupt + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD WWDG_RST_IRQHandler ; Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) + DCD CRS_IRQHandler ; Clock Recovery Global Interrupt + DCD ECC_IRQHandler ; ECC diagnostic Global Interrupt + DCD SAI4_IRQHandler ; SAI4 global interrupt + DCD 0 ; Reserved + DCD HOLD_CORE_IRQHandler ; Hold core interrupt + DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_AVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_AVD_IRQHandler + B PVD_AVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK FDCAN1_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT0_IRQHandler + B FDCAN1_IT0_IRQHandler + + PUBWEAK FDCAN2_IT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT0_IRQHandler + B FDCAN2_IT0_IRQHandler + + PUBWEAK FDCAN1_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN1_IT1_IRQHandler + B FDCAN1_IT1_IRQHandler + + PUBWEAK FDCAN2_IT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN2_IT1_IRQHandler + B FDCAN2_IT1_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_IRQHandler + B TIM1_BRK_IRQHandler + + PUBWEAK TIM1_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_IRQHandler + B TIM1_UP_IRQHandler + + PUBWEAK TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_IRQHandler + B TIM1_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK SDMMC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC1_IRQHandler + B SDMMC1_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK ETH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_IRQHandler + B ETH_IRQHandler + + PUBWEAK ETH_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_WKUP_IRQHandler + B ETH_WKUP_IRQHandler + + PUBWEAK FDCAN_CAL_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FDCAN_CAL_IRQHandler + B FDCAN_CAL_IRQHandler + + PUBWEAK CM7_SEV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CM7_SEV_IRQHandler + B CM7_SEV_IRQHandler + + PUBWEAK CM4_SEV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CM4_SEV_IRQHandler + B CM4_SEV_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_OUT_IRQHandler + B OTG_HS_EP1_OUT_IRQHandler + + PUBWEAK OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_IN_IRQHandler + B OTG_HS_EP1_IN_IRQHandler + + PUBWEAK OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_WKUP_IRQHandler + B OTG_HS_WKUP_IRQHandler + + PUBWEAK OTG_HS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_IRQHandler + B OTG_HS_IRQHandler + + PUBWEAK DCMI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DCMI_IRQHandler + B DCMI_IRQHandler + + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_IRQHandler + B RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK UART7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART7_IRQHandler + B UART7_IRQHandler + + PUBWEAK UART8_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART8_IRQHandler + B UART8_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + PUBWEAK SPI6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI6_IRQHandler + B SPI6_IRQHandler + + PUBWEAK SAI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_IRQHandler + B SAI1_IRQHandler + + PUBWEAK LTDC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_IRQHandler + B LTDC_IRQHandler + + PUBWEAK LTDC_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LTDC_ER_IRQHandler + B LTDC_ER_IRQHandler + + PUBWEAK DMA2D_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler + + PUBWEAK SAI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI2_IRQHandler + B SAI2_IRQHandler + + PUBWEAK QUADSPI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +QUADSPI_IRQHandler + B QUADSPI_IRQHandler + + PUBWEAK LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + + PUBWEAK CEC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_IRQHandler + B CEC_IRQHandler + + PUBWEAK I2C4_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_EV_IRQHandler + B I2C4_EV_IRQHandler + + PUBWEAK I2C4_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_ER_IRQHandler + B I2C4_ER_IRQHandler + + PUBWEAK SPDIF_RX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPDIF_RX_IRQHandler + B SPDIF_RX_IRQHandler + + PUBWEAK OTG_FS_EP1_OUT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_EP1_OUT_IRQHandler + B OTG_FS_EP1_OUT_IRQHandler + + PUBWEAK OTG_FS_EP1_IN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_EP1_IN_IRQHandler + B OTG_FS_EP1_IN_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMAMUX1_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX1_OVR_IRQHandler + B DMAMUX1_OVR_IRQHandler + + PUBWEAK HRTIM1_Master_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_Master_IRQHandler + B HRTIM1_Master_IRQHandler + + PUBWEAK HRTIM1_TIMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMA_IRQHandler + B HRTIM1_TIMA_IRQHandler + + PUBWEAK HRTIM1_TIMB_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMB_IRQHandler + B HRTIM1_TIMB_IRQHandler + + PUBWEAK HRTIM1_TIMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMC_IRQHandler + B HRTIM1_TIMC_IRQHandler + + PUBWEAK HRTIM1_TIMD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIMD_IRQHandler + B HRTIM1_TIMD_IRQHandler + + PUBWEAK HRTIM1_TIME_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_TIME_IRQHandler + B HRTIM1_TIME_IRQHandler + + PUBWEAK HRTIM1_FLT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HRTIM1_FLT_IRQHandler + B HRTIM1_FLT_IRQHandler + + PUBWEAK DFSDM1_FLT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT0_IRQHandler + B DFSDM1_FLT0_IRQHandler + + PUBWEAK DFSDM1_FLT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT1_IRQHandler + B DFSDM1_FLT1_IRQHandler + + PUBWEAK DFSDM1_FLT2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT2_IRQHandler + B DFSDM1_FLT2_IRQHandler + + PUBWEAK DFSDM1_FLT3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT3_IRQHandler + B DFSDM1_FLT3_IRQHandler + + PUBWEAK SAI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI3_IRQHandler + B SAI3_IRQHandler + + PUBWEAK SWPMI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SWPMI1_IRQHandler + B SWPMI1_IRQHandler + + PUBWEAK TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM15_IRQHandler + B TIM15_IRQHandler + + PUBWEAK TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler + B TIM16_IRQHandler + + PUBWEAK TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler + B TIM17_IRQHandler + + PUBWEAK MDIOS_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_WKUP_IRQHandler + B MDIOS_WKUP_IRQHandler + + PUBWEAK MDIOS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDIOS_IRQHandler + B MDIOS_IRQHandler + + PUBWEAK JPEG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +JPEG_IRQHandler + B JPEG_IRQHandler + + PUBWEAK MDMA_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +MDMA_IRQHandler + B MDMA_IRQHandler + + PUBWEAK DSI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DSI_IRQHandler + B DSI_IRQHandler + + PUBWEAK SDMMC2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC2_IRQHandler + B SDMMC2_IRQHandler + + PUBWEAK HSEM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HSEM1_IRQHandler + B HSEM1_IRQHandler + + PUBWEAK HSEM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HSEM2_IRQHandler + B HSEM2_IRQHandler + + PUBWEAK ADC3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC3_IRQHandler + B ADC3_IRQHandler + + PUBWEAK DMAMUX2_OVR_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMAMUX2_OVR_IRQHandler + B DMAMUX2_OVR_IRQHandler + + PUBWEAK BDMA_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel0_IRQHandler + B BDMA_Channel0_IRQHandler + + PUBWEAK BDMA_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel1_IRQHandler + B BDMA_Channel1_IRQHandler + + PUBWEAK BDMA_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel2_IRQHandler + B BDMA_Channel2_IRQHandler + + PUBWEAK BDMA_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel3_IRQHandler + B BDMA_Channel3_IRQHandler + + PUBWEAK BDMA_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel4_IRQHandler + B BDMA_Channel4_IRQHandler + + PUBWEAK BDMA_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel5_IRQHandler + B BDMA_Channel5_IRQHandler + + PUBWEAK BDMA_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel6_IRQHandler + B BDMA_Channel6_IRQHandler + + PUBWEAK BDMA_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +BDMA_Channel7_IRQHandler + B BDMA_Channel7_IRQHandler + + PUBWEAK COMP1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP1_IRQHandler + B COMP1_IRQHandler + + PUBWEAK LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler + B LPTIM2_IRQHandler + + PUBWEAK LPTIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM3_IRQHandler + B LPTIM3_IRQHandler + + PUBWEAK LPTIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM4_IRQHandler + B LPTIM4_IRQHandler + + PUBWEAK LPTIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM5_IRQHandler + B LPTIM5_IRQHandler + + PUBWEAK LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler + B LPUART1_IRQHandler + + PUBWEAK WWDG_RST_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_RST_IRQHandler + B WWDG_RST_IRQHandler + + PUBWEAK CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRS_IRQHandler + B CRS_IRQHandler + + PUBWEAK ECC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ECC_IRQHandler + B ECC_IRQHandler + + PUBWEAK SAI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI4_IRQHandler + B SAI4_IRQHandler + + PUBWEAK HOLD_CORE_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +HOLD_CORE_IRQHandler + B HOLD_CORE_IRQHandler + + PUBWEAK WAKEUP_PIN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WAKEUP_PIN_IRQHandler + B WAKEUP_PIN_IRQHandler + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_IAR/stm32h747xI.icf b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_IAR/stm32h747xI.icf new file mode 100644 index 00000000000..e9fda2ece7a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_IAR/stm32h747xI.icf @@ -0,0 +1,35 @@ +// 2MB FLASH (0x200000) +if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; } +if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x200000; } +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { define symbol MBED_BOOT_STACK_SIZE = 0x400; } + +define symbol __intvec_start__ = MBED_APP_START; +define symbol __region_ROM_start__ = MBED_APP_START; +define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; + +// 128KB DTCM RAM (0x20000) +// Vector table dynamic copy: 166 vectors = 664 bytes (0x298) reserved +define symbol __NVIC_start__ = 0x20000000; +define symbol __NVIC_end__ = 0x20000297; +define symbol __region_RAM_start__ = 0x20000298; // Aligned on 8 bytes +define symbol __region_RAM_end__ = 0x20000000 + 0x20000 - 1; + +// Memory regions +define memory mem with size = 4G; +define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]; +define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__]; + +// Stack and Heap +define symbol __size_cstack__ = MBED_BOOT_STACK_SIZE; +define symbol __size_heap__ = 0x10000; // 64KB +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block STACKHEAP with fixed order { block HEAP, block CSTACK }; + +initialize by copy with packing = zeros { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, block STACKHEAP }; diff --git a/targets/targets.json b/targets/targets.json index 6c4470c6004..e772f089c2a 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -3323,6 +3323,49 @@ "device_name": "STM32H743ZI", "bootloader_supported": true }, + "DISCO_H747I": { + "inherits": ["FAMILY_STM32"], + "core": "Cortex-M7FD", + "extra_labels_add": [ + "STM32H7", + "STM32H747xI", + "DISCO_H747I_CM7" + ], + "config": { + "clock_source": { + "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", + "value": "USE_PLL_HSE_EXTC", + "macro_name": "CLOCK_SOURCE" + }, + "lpticker_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer", + "value": 1 + } + }, + "macros_add": [ + "STM32H747xx", + "CORE_CM7", + "EXTRA_IDLE_STACK_REQUIRED", + "MBED_TICKLESS" + ], + "overrides": { "lpticker_delay_ticks": 0 }, + "supported_form_factors": ["ARDUINO"], + "detect_code": ["0814"], + "device_has_add": [ + "ANALOGOUT", + "CAN", + "CRC", + "TRNG", + "FLASH", + "MPU" + ], + "release_versions": ["2", "5"], + "device_name": "STM32H747ZI", + "bootloader_supported": true + }, + "DISCO_H747I_CM7": { + "inherits": ["DISCO_H747I"] + }, "UHURU_RAVEN": { "inherits": ["FAMILY_STM32"], "core": "Cortex-M7FD", From 39e890d3300e75d5c2b6d4e0f50a998b43b6ff50 Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Mon, 2 Sep 2019 11:08:04 +0200 Subject: [PATCH 072/227] Remove "STM32H747ZI" device_name, as not supported yet by MBED --- targets/targets.json | 1 - 1 file changed, 1 deletion(-) diff --git a/targets/targets.json b/targets/targets.json index e772f089c2a..78c077d659d 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -3360,7 +3360,6 @@ "MPU" ], "release_versions": ["2", "5"], - "device_name": "STM32H747ZI", "bootloader_supported": true }, "DISCO_H747I_CM7": { From 74a24ea88d6d861b21f5c0c0fd6ef996cdebe574 Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Tue, 10 Sep 2019 10:55:30 +0200 Subject: [PATCH 073/227] STM32H747 license update --- .../TARGET_DISCO_H747I/PeripheralPins.c | 2 +- .../TARGET_DISCO_H747I/PinNames.h | 2 +- .../TARGET_DISCO_H747I/system_clock.c | 27 ++++++------ .../TOOLCHAIN_ARM_STD/stm32h747xI.sct | 39 +++++----------- .../TOOLCHAIN_GCC_ARM/STM32H747xI.ld | 13 ++++++ .../TOOLCHAIN_IAR/stm32h747xI.icf | 13 ++++++ .../TARGET_STM32H747xI/cmsis_nvic.h | 43 ++++++------------ .../TARGET_STM32H747xI/flash_data.h | 44 +++++++------------ 8 files changed, 82 insertions(+), 101 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PeripheralPins.c index 0c48c8908e3..f6f63a0147d 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PeripheralPins.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2018, STMicroelectronics + * Copyright (c) 2019, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PinNames.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PinNames.h index 289e6e1d316..5131b93f648 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PinNames.h @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2018, STMicroelectronics + * Copyright (c) 2019, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/system_clock.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/system_clock.c index 34bc15cedfa..b8d296e884e 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/system_clock.c @@ -1,17 +1,16 @@ -/* mbed Microcontroller Library -* Copyright (c) 2006-2017 ARM Limited -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. +/* + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** */ /** diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_ARM_STD/stm32h747xI.sct b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_ARM_STD/stm32h747xI.sct index 34101205f07..a68f4cf7eec 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_ARM_STD/stm32h747xI.sct +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_ARM_STD/stm32h747xI.sct @@ -1,32 +1,17 @@ #! armcc -E ; Scatter-Loading Description File -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; Copyright (c) 2016, STMicroelectronics -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, -; this list of conditions and the following disclaimer. -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; 3. Neither the name of STMicroelectronics nor the names of its contributors -; may be used to endorse or promote products derived from this software -; without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2019 STMicroelectronics. +;* All rights reserved. +;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;****************************************************************************** #if !defined(MBED_APP_START) #define MBED_APP_START 0x08000000 diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI.ld b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI.ld index 307d8c07b4b..9a4969bec9c 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI.ld +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI.ld @@ -1,4 +1,17 @@ /* Linker script to configure memory regions. */ +/******************************************************************************* + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ #if !defined(MBED_APP_START) #define MBED_APP_START 0x08000000 diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_IAR/stm32h747xI.icf b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_IAR/stm32h747xI.icf index e9fda2ece7a..3408ed389f9 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_IAR/stm32h747xI.icf +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_IAR/stm32h747xI.icf @@ -1,3 +1,16 @@ +//****************************************************************************** +//* @attention +//* +//* Copyright (c) 2019 STMicroelectronics. +//* All rights reserved. +//* +//* This software component is licensed by ST under BSD 3-Clause license, +//* the "License"; You may not use this file except in compliance with the +//* License. You may obtain a copy of the License at: +//* opensource.org/licenses/BSD-3-Clause +//* +//****************************************************************************** + // 2MB FLASH (0x200000) if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; } if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x200000; } diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/cmsis_nvic.h index 394411b70bb..9787af110e7 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/cmsis_nvic.h @@ -1,32 +1,17 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2016, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ +/* + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ #ifndef MBED_CMSIS_NVIC_H #define MBED_CMSIS_NVIC_H diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/flash_data.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/flash_data.h index 71d8fc8683d..85303ecd962 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/flash_data.h +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/flash_data.h @@ -1,32 +1,18 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2016, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ +/* + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + #ifndef MBED_FLASH_DATA_H #define MBED_FLASH_DATA_H From 85919ba59615393928ad095f0d422f30f94325b4 Mon Sep 17 00:00:00 2001 From: Tymoteusz Bloch Date: Wed, 4 Sep 2019 13:59:36 +0200 Subject: [PATCH 074/227] Fixed msc9220_emac link_out memory management. --- .../TARGET_ARM_SSG/COMPONENT_SMSC9220/smsc9220_emac.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/features/netsocket/emac-drivers/TARGET_ARM_SSG/COMPONENT_SMSC9220/smsc9220_emac.cpp b/features/netsocket/emac-drivers/TARGET_ARM_SSG/COMPONENT_SMSC9220/smsc9220_emac.cpp index 167024e11a3..caf80bfdd41 100644 --- a/features/netsocket/emac-drivers/TARGET_ARM_SSG/COMPONENT_SMSC9220/smsc9220_emac.cpp +++ b/features/netsocket/emac-drivers/TARGET_ARM_SSG/COMPONENT_SMSC9220/smsc9220_emac.cpp @@ -168,6 +168,7 @@ bool SMSC9220_EMAC::link_out(emac_mem_buf_t *buf) true, (const char*)_memory_manager->get_ptr(buf), _memory_manager->get_len(buf)); + _memory_manager->free(buf); if (error != SMSC9220_ERROR_NONE) { _TXLockMutex.unlock(); return false; From 5cce3afc1bf78a7b87b93e1243a8bee82360af0e Mon Sep 17 00:00:00 2001 From: Tymoteusz Bloch Date: Fri, 30 Aug 2019 15:31:39 +0200 Subject: [PATCH 075/227] DNS cache synchronous fix - Non zero TTL test server change --- TESTS/netsocket/dns/main.cpp | 1 + TESTS/netsocket/dns/synchronous_dns_cache.cpp | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/TESTS/netsocket/dns/main.cpp b/TESTS/netsocket/dns/main.cpp index ae2e3f5b820..f97c4815e52 100644 --- a/TESTS/netsocket/dns/main.cpp +++ b/TESTS/netsocket/dns/main.cpp @@ -187,6 +187,7 @@ Case cases[] = { Case("ASYNCHRONOUS_DNS", ASYNCHRONOUS_DNS), Case("ASYNCHRONOUS_DNS_SIMULTANEOUS", ASYNCHRONOUS_DNS_SIMULTANEOUS), Case("ASYNCHRONOUS_DNS_SIMULTANEOUS_CACHE", ASYNCHRONOUS_DNS_SIMULTANEOUS_CACHE), + Case("SYNCHRONOUS_DNS_CACHE", SYNCHRONOUS_DNS_CACHE), #ifndef MBED_CONF_CELLULAR_OFFLOAD_DNS_QUERIES Case("ASYNCHRONOUS_DNS_CACHE", ASYNCHRONOUS_DNS_CACHE), #endif diff --git a/TESTS/netsocket/dns/synchronous_dns_cache.cpp b/TESTS/netsocket/dns/synchronous_dns_cache.cpp index bd876cc41c0..0b36b630bdd 100644 --- a/TESTS/netsocket/dns/synchronous_dns_cache.cpp +++ b/TESTS/netsocket/dns/synchronous_dns_cache.cpp @@ -40,7 +40,7 @@ void SYNCHRONOUS_DNS_CACHE() for (unsigned int i = 0; i < 5; i++) { SocketAddress address; int started_us = ticker_us; - nsapi_error_t err = get_interface()->gethostbyname(dns_test_hosts_second[0], &address); + nsapi_error_t err = get_interface()->gethostbyname(dns_test_hosts[0], &address); int delay_ms = (ticker_us - started_us) / 1000; @@ -49,6 +49,6 @@ void SYNCHRONOUS_DNS_CACHE() TEST_ASSERT_TRUE(i == 0 || delay_ms <= delay_first); printf("DNS: query \"%s\" => \"%s\", time %i ms\n", - dns_test_hosts_second[0], address.get_ip_address(), delay_ms); + dns_test_hosts[0], address.get_ip_address(), delay_ms); } } From 60a98b91d0a537a7a2eff82139c8aa0b1483b668 Mon Sep 17 00:00:00 2001 From: Matthew Macovsky Date: Mon, 9 Sep 2019 19:13:43 +0100 Subject: [PATCH 076/227] Add catch-all rule to makefile template --- tools/export/makefile/Makefile.tmpl | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tools/export/makefile/Makefile.tmpl b/tools/export/makefile/Makefile.tmpl index 6dca2f531b9..c62aa95f6b5 100644 --- a/tools/export/makefile/Makefile.tmpl +++ b/tools/export/makefile/Makefile.tmpl @@ -163,4 +163,10 @@ endif # Dependencies ############################################################################### +# Catch-all + +%: ; + +# Catch-all +############################################################################### From 8205a15342cdd6ea5293cd58127f62b498649e58 Mon Sep 17 00:00:00 2001 From: Qinghao Shi Date: Wed, 11 Sep 2019 19:01:48 +0100 Subject: [PATCH 077/227] TEST: update compare log file name --- tools/test/examples/examples.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/test/examples/examples.json b/tools/test/examples/examples.json index b2e1d1dd5c6..3d9bbf24b50 100644 --- a/tools/test/examples/examples.json +++ b/tools/test/examples/examples.json @@ -360,7 +360,7 @@ "export": true, "test" : true, "baud_rate": 9600, - "compare_log": ["mbed-os-example-mbed-crypto/tests/mbed-crypto.log"], + "compare_log": ["mbed-os-example-mbed-crypto/tests/getting-started.log"], "auto-update" : true }, { From 462103feb5d0f303d5fefb8b77c9545392ba6372 Mon Sep 17 00:00:00 2001 From: Hugues Kamba Date: Tue, 10 Sep 2019 11:00:43 +0100 Subject: [PATCH 078/227] Fix Coverity issues Issues fixed are related to: * Non-static class member initialization in constructors * Unused function return value * Always false statements --- drivers/source/FlashIAP.cpp | 2 +- drivers/source/Ticker.cpp | 4 ++-- platform/ATCmdParser.h | 2 +- platform/source/ATCmdParser.cpp | 2 +- platform/source/SysTimer.cpp | 2 ++ platform/source/mbed_retarget.cpp | 1 + 6 files changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/source/FlashIAP.cpp b/drivers/source/FlashIAP.cpp index 71565b80b0f..60d48344cac 100644 --- a/drivers/source/FlashIAP.cpp +++ b/drivers/source/FlashIAP.cpp @@ -46,7 +46,7 @@ static inline bool is_aligned(uint32_t number, uint32_t alignment) } } -FlashIAP::FlashIAP() +FlashIAP::FlashIAP() : _page_buf(nullptr) { } diff --git a/drivers/source/Ticker.cpp b/drivers/source/Ticker.cpp index fada56cf646..12a2d2ea60a 100644 --- a/drivers/source/Ticker.cpp +++ b/drivers/source/Ticker.cpp @@ -24,12 +24,12 @@ namespace mbed { -Ticker::Ticker() : TimerEvent(), _function(0), _lock_deepsleep(true) +Ticker::Ticker() : TimerEvent(), _delay(0), _function(0), _lock_deepsleep(true) { } // When low power ticker is in use, then do not disable deep sleep. -Ticker::Ticker(const ticker_data_t *data) : TimerEvent(data), _function(0), _lock_deepsleep(!data->interface->runs_in_deep_sleep) +Ticker::Ticker(const ticker_data_t *data) : TimerEvent(data), _delay(0), _function(0), _lock_deepsleep(!data->interface->runs_in_deep_sleep) { } diff --git a/platform/ATCmdParser.h b/platform/ATCmdParser.h index 36ffd8752bb..d9a6e985437 100644 --- a/platform/ATCmdParser.h +++ b/platform/ATCmdParser.h @@ -92,7 +92,7 @@ class ATCmdParser : private NonCopyable { */ ATCmdParser(FileHandle *fh, const char *output_delimiter = "\r", int buffer_size = 256, int timeout = 8000, bool debug = false) - : _fh(fh), _buffer_size(buffer_size), _oob_cb_count(0), _in_prev(0), _oobs(NULL) + : _fh(fh), _buffer_size(buffer_size), _oob_cb_count(0), _in_prev(0), _aborted(false), _oobs(NULL) { _buffer = new char[buffer_size]; set_timeout(timeout); diff --git a/platform/source/ATCmdParser.cpp b/platform/source/ATCmdParser.cpp index 7a54f55fbad..6f01a3ea790 100644 --- a/platform/source/ATCmdParser.cpp +++ b/platform/source/ATCmdParser.cpp @@ -397,7 +397,7 @@ void ATCmdParser::abort() bool ATCmdParser::process_oob() { int pre_count = _oob_cb_count; - recv(NULL); + static_cast(recv(NULL)); return _oob_cb_count != pre_count; } diff --git a/platform/source/SysTimer.cpp b/platform/source/SysTimer.cpp index 7ed90f423a6..0803849e25d 100644 --- a/platform/source/SysTimer.cpp +++ b/platform/source/SysTimer.cpp @@ -57,6 +57,7 @@ SysTimer::SysTimer() : _unacknowledged_ticks(0), _wake_time_set(false), _wake_time_passed(false), + _wake_early(false), _ticking(false), _deep_sleep_locked(false) { @@ -70,6 +71,7 @@ SysTimer::SysTimer(const ticker_data_t *data) : _unacknowledged_ticks(0), _wake_time_set(false), _wake_time_passed(false), + _wake_early(false), _ticking(false), _deep_sleep_locked(false) { diff --git a/platform/source/mbed_retarget.cpp b/platform/source/mbed_retarget.cpp index b55902a4e2b..6679d872193 100644 --- a/platform/source/mbed_retarget.cpp +++ b/platform/source/mbed_retarget.cpp @@ -826,6 +826,7 @@ int _lseek(FILEHANDLE fh, int offset, int whence) off_t off = lseek(fh, offset, whence); // Assuming INT_MAX = LONG_MAX, so we don't care about prototype difference if (off > INT_MAX) { + // Be cautious in case off_t is 64-bit errno = EOVERFLOW; return -1; } From a846eb3c3c538cfe205fe0851b98a881a8529a2d Mon Sep 17 00:00:00 2001 From: Mirela Chirica Date: Thu, 12 Sep 2019 12:55:33 +0300 Subject: [PATCH 079/227] Cellular: Stack type based on assigned IP addresses versions --- UNITTESTS/stubs/CellularUtil_stub.cpp | 4 +-- .../framework/AT/AT_CellularStack.cpp | 34 ++++++++++++++----- .../cellular/framework/AT/AT_CellularStack.h | 2 +- .../framework/common/CellularUtil.cpp | 14 ++++++-- .../cellular/framework/common/CellularUtil.h | 3 +- 5 files changed, 41 insertions(+), 16 deletions(-) diff --git a/UNITTESTS/stubs/CellularUtil_stub.cpp b/UNITTESTS/stubs/CellularUtil_stub.cpp index 1ed70b7cfde..757fd2bbb8e 100644 --- a/UNITTESTS/stubs/CellularUtil_stub.cpp +++ b/UNITTESTS/stubs/CellularUtil_stub.cpp @@ -51,9 +51,9 @@ uint16_t char_str_to_hex(const char *str, uint16_t len, char *buf, bool omit_lea return CellularUtil_stub::uint16_value; } -void convert_ipv6(char *ip) +nsapi_version_t convert_ipv6(char *ip) { - + return NSAPI_UNSPEC; } char *find_dot_number(char *str, int dot_number) diff --git a/features/cellular/framework/AT/AT_CellularStack.cpp b/features/cellular/framework/AT/AT_CellularStack.cpp index a8aba5b578d..dc0f5732c28 100644 --- a/features/cellular/framework/AT/AT_CellularStack.cpp +++ b/features/cellular/framework/AT/AT_CellularStack.cpp @@ -59,27 +59,43 @@ const char *AT_CellularStack::get_ip_address() { _at.lock(); + bool ipv4 = false, ipv6 = false; + _at.cmd_start_stop("+CGPADDR", "=", "%d", _cid); _at.resp_start("+CGPADDR:"); - int len = -1; if (_at.info_resp()) { _at.skip_param(); - len = _at.read_string(_ip, PDP_IPV6_SIZE); - - if (len != -1 && _stack_type != IPV4_STACK) { - // in case stack type is not IPV4 only, try to look also for IPV6 address - (void)_at.read_string(_ip, PDP_IPV6_SIZE); + if (_at.read_string(_ip, PDP_IPV6_SIZE) != -1) { + convert_ipv6(_ip); + SocketAddress address; + address.set_ip_address(_ip); + + ipv4 = (address.get_ip_version() == NSAPI_IPv4); + ipv6 = (address.get_ip_version() == NSAPI_IPv6); + + // Try to look for second address ONLY if modem has support for dual stack(can handle both IPv4 and IPv6 simultaneously). + // Otherwise assumption is that second address is not reliable, even if network provides one. + if ((get_property(PROPERTY_IPV4V6_PDP_TYPE) && (_at.read_string(_ip, PDP_IPV6_SIZE) != -1))) { + convert_ipv6(_ip); + address.set_ip_address(_ip); + ipv6 = (address.get_ip_version() == NSAPI_IPv6); + } } } _at.resp_stop(); _at.unlock(); - // we have at least IPV4 address - convert_ipv6(_ip); + if (ipv4 && ipv6) { + _stack_type = IPV4V6_STACK; + } else if (ipv4) { + _stack_type = IPV4_STACK; + } else if (ipv6) { + _stack_type = IPV6_STACK; + } - return len != -1 ? _ip : NULL; + return (ipv4 || ipv6) ? _ip : NULL; } nsapi_error_t AT_CellularStack::socket_stack_init() diff --git a/features/cellular/framework/AT/AT_CellularStack.h b/features/cellular/framework/AT/AT_CellularStack.h index afa28f90c6b..058eb7125ed 100644 --- a/features/cellular/framework/AT/AT_CellularStack.h +++ b/features/cellular/framework/AT/AT_CellularStack.h @@ -204,7 +204,7 @@ class AT_CellularStack : public NetworkStack, public AT_CellularBase { // PDP context id int _cid; - // stack type from PDP context + // stack type - initialised as PDP type and set accordingly after CGPADDR checked nsapi_ip_stack_t _stack_type; private: diff --git a/features/cellular/framework/common/CellularUtil.cpp b/features/cellular/framework/common/CellularUtil.cpp index 8c7bf7a9d39..33c5956899d 100644 --- a/features/cellular/framework/common/CellularUtil.cpp +++ b/features/cellular/framework/common/CellularUtil.cpp @@ -28,10 +28,10 @@ using namespace mbed; namespace mbed_cellular_util { -void convert_ipv6(char *ip) +nsapi_version_t convert_ipv6(char *ip) { if (!ip) { - return; + return NSAPI_UNSPEC; } int len = strlen(ip); @@ -49,7 +49,11 @@ void convert_ipv6(char *ip) // more that 3 periods mean that it was ipv6 but in format of a1.a2.a3.a4.a5.a6.a7.a8.a9.a10.a11.a12.a13.a14.a15.a16 // we need to convert it to hexadecimal format separated with colons - if (pos > 3) { + if (pos == 3) { + + return NSAPI_IPv4; + + } else if (pos > 3) { pos = 0; int ip_pos = 0; char b; @@ -74,7 +78,11 @@ void convert_ipv6(char *ip) ip[pos] = '\0'; } } + + return NSAPI_IPv6; } + + return NSAPI_UNSPEC; } // For example "32.1.13.184.0.0.205.48.0.0.0.0.0.0.0.0" diff --git a/features/cellular/framework/common/CellularUtil.h b/features/cellular/framework/common/CellularUtil.h index cfd7b50e0df..cfe0c86cbaf 100644 --- a/features/cellular/framework/common/CellularUtil.h +++ b/features/cellular/framework/common/CellularUtil.h @@ -48,8 +48,9 @@ static const char hex_values[] = "0123456789ABCDEF"; * where ax are in decimal format. In this case, function converts decimals to hex with separated with colons. * * @param ip IP address that can be IPv4 or IPv6 in different formats from AT command +CGPADDR. Converted result uses same buffer. + * @return IP version of the address or NSAPI_UNSPEC if param ip empty or if IPv4 or IPv6 version could not be concluded. */ -void convert_ipv6(char *ip); +nsapi_version_t convert_ipv6(char *ip); /** Separates IP addresses from the given 'orig' string. 'orig' may contain zero, one or two IP addresses in various formats. * See AT command +CGPIAF from 3GPP TS 27.007 for details. Does also needed conversions for IPv6 addresses. From 4078b6f398a9a64023fb61e23fb07c2aa432d4f8 Mon Sep 17 00:00:00 2001 From: Mirela Chirica Date: Thu, 5 Sep 2019 14:03:01 +0300 Subject: [PATCH 080/227] Cellular: IP stack property redefined --- features/cellular/framework/AT/AT_CellularBase.h | 2 +- features/cellular/framework/AT/AT_CellularContext.cpp | 7 ++++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/features/cellular/framework/AT/AT_CellularBase.h b/features/cellular/framework/AT/AT_CellularBase.h index e50008a75df..c4448142a7b 100644 --- a/features/cellular/framework/AT/AT_CellularBase.h +++ b/features/cellular/framework/AT/AT_CellularBase.h @@ -60,7 +60,7 @@ class AT_CellularBase { PROPERTY_AT_CSDH, // 0 = not supported, 1 = supported. Show text mode AT command PROPERTY_IPV4_PDP_TYPE, // 0 = not supported, 1 = supported. Does modem support IPV4? PROPERTY_IPV6_PDP_TYPE, // 0 = not supported, 1 = supported. Does modem support IPV6? - PROPERTY_IPV4V6_PDP_TYPE, // 0 = not supported, 1 = supported. Does modem support dual stack IPV4V6? + PROPERTY_IPV4V6_PDP_TYPE, // 0 = not supported, 1 = supported. Does modem support IPV4 and IPV6 simultaneously? PROPERTY_NON_IP_PDP_TYPE, // 0 = not supported, 1 = supported. Does modem support Non-IP? PROPERTY_AT_CGEREP, // 0 = not supported, 1 = supported. Does modem support AT command AT+CGEREP. diff --git a/features/cellular/framework/AT/AT_CellularContext.cpp b/features/cellular/framework/AT/AT_CellularContext.cpp index 7bfd6e666f6..d18918ec8f3 100644 --- a/features/cellular/framework/AT/AT_CellularContext.cpp +++ b/features/cellular/framework/AT/AT_CellularContext.cpp @@ -369,8 +369,9 @@ bool AT_CellularContext::get_context() // APN matched -> Check PDP type pdp_type_t pdp_type = string_to_pdp_type(pdp_type_from_context); - // Accept exact matching PDP context type - if (get_property(pdp_type_t_to_cellular_property(pdp_type))) { + // Accept exact matching PDP context type or dual PDP context for modems that support both IPv4 and IPv6 stacks + if (get_property(pdp_type_t_to_cellular_property(pdp_type)) || + ((pdp_type == IPV4V6_PDP_TYPE && (get_property(PROPERTY_IPV4_PDP_TYPE) && get_property(PROPERTY_IPV6_PDP_TYPE))) && !_nonip_req)) { _pdp_type = pdp_type; _cid = cid; } @@ -403,7 +404,7 @@ bool AT_CellularContext::set_new_context(int cid) if (_nonip_req && _cp_in_use && get_property(PROPERTY_NON_IP_PDP_TYPE)) { strncpy(pdp_type_str, "Non-IP", sizeof(pdp_type_str)); pdp_type = NON_IP_PDP_TYPE; - } else if (get_property(PROPERTY_IPV4V6_PDP_TYPE)) { + } else if (get_property(PROPERTY_IPV4V6_PDP_TYPE) || (get_property(PROPERTY_IPV4_PDP_TYPE) && get_property(PROPERTY_IPV6_PDP_TYPE))) { strncpy(pdp_type_str, "IPV4V6", sizeof(pdp_type_str)); pdp_type = IPV4V6_PDP_TYPE; } else if (get_property(PROPERTY_IPV6_PDP_TYPE)) { From 1b43450607572d4916c4fbccd7ae6a1d43463e5f Mon Sep 17 00:00:00 2001 From: Mirela Chirica Date: Thu, 5 Sep 2019 14:08:35 +0300 Subject: [PATCH 081/227] Cellular: Check IP version of send to address --- .../framework/AT/AT_CellularStack.cpp | 26 ++++++++++++++++--- .../cellular/framework/AT/AT_CellularStack.h | 8 ++++++ .../BG96/QUECTEL_BG96_CellularStack.cpp | 10 +++++-- 3 files changed, 38 insertions(+), 6 deletions(-) diff --git a/features/cellular/framework/AT/AT_CellularStack.cpp b/features/cellular/framework/AT/AT_CellularStack.cpp index dc0f5732c28..621431eabe0 100644 --- a/features/cellular/framework/AT/AT_CellularStack.cpp +++ b/features/cellular/framework/AT/AT_CellularStack.cpp @@ -23,7 +23,7 @@ using namespace mbed_cellular_util; using namespace mbed; -AT_CellularStack::AT_CellularStack(ATHandler &at, int cid, nsapi_ip_stack_t stack_type) : AT_CellularBase(at), _socket(NULL), _socket_count(0), _cid(cid), _stack_type(stack_type) +AT_CellularStack::AT_CellularStack(ATHandler &at, int cid, nsapi_ip_stack_t stack_type) : AT_CellularBase(at), _socket(NULL), _socket_count(0), _cid(cid), _stack_type(stack_type), _ip_ver_sendto(NSAPI_UNSPEC) { memset(_ip, 0, PDP_IPV6_SIZE); } @@ -272,6 +272,13 @@ nsapi_size_or_error_t AT_CellularStack::socket_sendto(nsapi_socket_t handle, con nsapi_size_or_error_t ret_val = NSAPI_ERROR_OK; if (socket->id == -1) { + + /* Check that stack type supports sendto address type*/ + if (!is_addr_stack_compatible(addr)) { + return NSAPI_ERROR_PARAMETER; + } + + _ip_ver_sendto = addr.get_ip_version(); _at.lock(); ret_val = create_socket_impl(socket); @@ -283,9 +290,9 @@ nsapi_size_or_error_t AT_CellularStack::socket_sendto(nsapi_socket_t handle, con } } - /* Check parameters */ - if (addr.get_ip_version() == NSAPI_UNSPEC) { - return NSAPI_ERROR_DEVICE_ERROR; + /* Check parameters - sendto address is valid and stack type supports sending to that address type*/ + if (!is_addr_stack_compatible(addr)) { + return NSAPI_ERROR_PARAMETER; } _at.lock(); @@ -393,3 +400,14 @@ AT_CellularStack::CellularSocket *AT_CellularStack::find_socket(int sock_id) } return sock; } + +bool AT_CellularStack::is_addr_stack_compatible(const SocketAddress &addr) +{ + if ((addr.get_ip_version() == NSAPI_UNSPEC) || + (addr.get_ip_version() == NSAPI_IPv4 && _stack_type == IPV6_STACK) || + (addr.get_ip_version() == NSAPI_IPv6 && _stack_type == IPV4_STACK)) { + return false; + } + return true; +} + diff --git a/features/cellular/framework/AT/AT_CellularStack.h b/features/cellular/framework/AT/AT_CellularStack.h index 058eb7125ed..5015aeee48b 100644 --- a/features/cellular/framework/AT/AT_CellularStack.h +++ b/features/cellular/framework/AT/AT_CellularStack.h @@ -192,6 +192,11 @@ class AT_CellularStack : public NetworkStack, public AT_CellularBase { */ int find_socket_index(nsapi_socket_t handle); + /** + * Checks if send to address is valid and if current stack type supports sending to that address type + */ + bool is_addr_stack_compatible(const SocketAddress &addr); + // socket container CellularSocket **_socket; @@ -207,6 +212,9 @@ class AT_CellularStack : public NetworkStack, public AT_CellularBase { // stack type - initialised as PDP type and set accordingly after CGPADDR checked nsapi_ip_stack_t _stack_type; + // IP version of send to address + nsapi_version_t _ip_ver_sendto; + private: int get_socket_index_by_port(uint16_t port); diff --git a/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularStack.cpp b/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularStack.cpp index c65fd50edd0..bcaa9a2b456 100644 --- a/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularStack.cpp +++ b/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularStack.cpp @@ -212,7 +212,7 @@ nsapi_error_t QUECTEL_BG96_CellularStack::create_socket_impl(CellularSocket *soc if (socket->proto == NSAPI_UDP && !socket->connected) { _at.at_cmd_discard("+QIOPEN", "=", "%d%d%s%s%d%d%d", _cid, request_connect_id, "UDP SERVICE", - (_stack_type == IPV4_STACK) ? "127.0.0.1" : "0:0:0:0:0:0:0:1", + (_ip_ver_sendto == NSAPI_IPv4) ? "127.0.0.1" : "0:0:0:0:0:0:0:1", remote_port, socket->localAddress.get_port(), 0); handle_open_socket_response(modem_connect_id, err); @@ -225,7 +225,7 @@ nsapi_error_t QUECTEL_BG96_CellularStack::create_socket_impl(CellularSocket *soc socket_close_impl(modem_connect_id); _at.at_cmd_discard("+QIOPEN", "=", "%d%d%s%s%d%d%d", _cid, request_connect_id, "UDP SERVICE", - (_stack_type == IPV4_STACK) ? "127.0.0.1" : "0:0:0:0:0:0:0:1", + (_ip_ver_sendto == NSAPI_IPv4) ? "127.0.0.1" : "0:0:0:0:0:0:0:1", remote_port, socket->localAddress.get_port(), 0); handle_open_socket_response(modem_connect_id, err); @@ -273,6 +273,12 @@ nsapi_size_or_error_t QUECTEL_BG96_CellularStack::socket_sendto_impl(CellularSoc return NSAPI_ERROR_PARAMETER; } + if (_ip_ver_sendto != address.get_ip_version()) { + _ip_ver_sendto = address.get_ip_version(); + socket_close_impl(socket->id); + create_socket_impl(socket); + } + int sent_len = 0; int sent_len_before = 0; int sent_len_after = 0; From 2cc2d690bec330b675dc82ef45a1e7049a86c0fd Mon Sep 17 00:00:00 2001 From: Mirela Chirica Date: Thu, 5 Sep 2019 10:34:46 +0300 Subject: [PATCH 082/227] Cellular: Enable IPv6 stack property for BG96 --- .../cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96.cpp b/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96.cpp index 6136863526b..b8222044f7b 100644 --- a/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96.cpp +++ b/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96.cpp @@ -57,7 +57,7 @@ static const intptr_t cellular_properties[AT_CellularBase::PROPERTY_MAX] = { 1, // AT_CMGF 1, // AT_CSDH 1, // PROPERTY_IPV4_STACK - 0, // PROPERTY_IPV6_STACK + 1, // PROPERTY_IPV6_STACK 0, // PROPERTY_IPV4V6_STACK 1, // PROPERTY_NON_IP_PDP_TYPE 1, // PROPERTY_AT_CGEREP From 7dc92567f97961bfb11e6af1d9801d5d6b791a96 Mon Sep 17 00:00:00 2001 From: Kostiantyn Tkachov Date: Thu, 12 Sep 2019 01:30:54 +0200 Subject: [PATCH 083/227] Updated mbedTLS CRYPTO target to be more flexibly configured for supported boards --- .../TARGET_MXCRYPTO_01}/sha1_alt.h | 0 .../TARGET_MXCRYPTO_01}/sha256_alt.h | 0 .../TARGET_MXCRYPTO_01}/sha512_alt.h | 0 .../TARGET_MXCRYPTO_02}/sha1_alt.h | 0 .../TARGET_MXCRYPTO_02}/sha256_alt.h | 0 .../TARGET_MXCRYPTO_02}/sha512_alt.h | 0 .../{TARGET_PSOC6 => TARGET_MXCRYPTO}/aes_alt.c | 8 +++++--- .../{TARGET_PSOC6 => TARGET_MXCRYPTO}/aes_alt.h | 0 .../crypto_common.c | 2 +- .../crypto_common.h | 0 .../{TARGET_PSOC6 => TARGET_MXCRYPTO}/ecdsa_alt.c | 0 .../{TARGET_PSOC6 => TARGET_MXCRYPTO}/ecp_alt.c | 10 ++++++++++ .../{TARGET_PSOC6 => TARGET_MXCRYPTO}/ecp_alt.h | 0 .../ecp_curves_alt.c | 0 .../mbedtls_device.h | 0 .../{TARGET_PSOC6 => TARGET_MXCRYPTO}/sha1_alt.c | 4 ++-- .../{TARGET_PSOC6 => TARGET_MXCRYPTO}/sha256_alt.c | 4 ++-- .../{TARGET_PSOC6 => TARGET_MXCRYPTO}/sha512_alt.c | 4 ++-- targets/targets.json | 13 +++++++++---- 19 files changed, 31 insertions(+), 14 deletions(-) rename features/mbedtls/targets/TARGET_Cypress/{TARGET_PSOC6/TARGET_PSOC6_01 => TARGET_MXCRYPTO/TARGET_MXCRYPTO_01}/sha1_alt.h (100%) rename features/mbedtls/targets/TARGET_Cypress/{TARGET_PSOC6/TARGET_PSOC6_01 => TARGET_MXCRYPTO/TARGET_MXCRYPTO_01}/sha256_alt.h (100%) rename features/mbedtls/targets/TARGET_Cypress/{TARGET_PSOC6/TARGET_PSOC6_01 => TARGET_MXCRYPTO/TARGET_MXCRYPTO_01}/sha512_alt.h (100%) rename features/mbedtls/targets/TARGET_Cypress/{TARGET_PSOC6/TARGET_PSOC6_02 => TARGET_MXCRYPTO/TARGET_MXCRYPTO_02}/sha1_alt.h (100%) rename features/mbedtls/targets/TARGET_Cypress/{TARGET_PSOC6/TARGET_PSOC6_02 => TARGET_MXCRYPTO/TARGET_MXCRYPTO_02}/sha256_alt.h (100%) rename features/mbedtls/targets/TARGET_Cypress/{TARGET_PSOC6/TARGET_PSOC6_02 => TARGET_MXCRYPTO/TARGET_MXCRYPTO_02}/sha512_alt.h (100%) rename features/mbedtls/targets/TARGET_Cypress/{TARGET_PSOC6 => TARGET_MXCRYPTO}/aes_alt.c (99%) rename features/mbedtls/targets/TARGET_Cypress/{TARGET_PSOC6 => TARGET_MXCRYPTO}/aes_alt.h (100%) rename features/mbedtls/targets/TARGET_Cypress/{TARGET_PSOC6 => TARGET_MXCRYPTO}/crypto_common.c (98%) rename features/mbedtls/targets/TARGET_Cypress/{TARGET_PSOC6 => TARGET_MXCRYPTO}/crypto_common.h (100%) rename features/mbedtls/targets/TARGET_Cypress/{TARGET_PSOC6 => TARGET_MXCRYPTO}/ecdsa_alt.c (100%) rename features/mbedtls/targets/TARGET_Cypress/{TARGET_PSOC6 => TARGET_MXCRYPTO}/ecp_alt.c (99%) rename features/mbedtls/targets/TARGET_Cypress/{TARGET_PSOC6 => TARGET_MXCRYPTO}/ecp_alt.h (100%) rename features/mbedtls/targets/TARGET_Cypress/{TARGET_PSOC6 => TARGET_MXCRYPTO}/ecp_curves_alt.c (100%) rename features/mbedtls/targets/TARGET_Cypress/{TARGET_PSOC6 => TARGET_MXCRYPTO}/mbedtls_device.h (100%) rename features/mbedtls/targets/TARGET_Cypress/{TARGET_PSOC6 => TARGET_MXCRYPTO}/sha1_alt.c (100%) rename features/mbedtls/targets/TARGET_Cypress/{TARGET_PSOC6 => TARGET_MXCRYPTO}/sha256_alt.c (100%) rename features/mbedtls/targets/TARGET_Cypress/{TARGET_PSOC6 => TARGET_MXCRYPTO}/sha512_alt.c (100%) diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_01/sha1_alt.h b/features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/TARGET_MXCRYPTO_01/sha1_alt.h similarity index 100% rename from features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_01/sha1_alt.h rename to features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/TARGET_MXCRYPTO_01/sha1_alt.h diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_01/sha256_alt.h b/features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/TARGET_MXCRYPTO_01/sha256_alt.h similarity index 100% rename from features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_01/sha256_alt.h rename to features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/TARGET_MXCRYPTO_01/sha256_alt.h diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_01/sha512_alt.h b/features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/TARGET_MXCRYPTO_01/sha512_alt.h similarity index 100% rename from features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_01/sha512_alt.h rename to features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/TARGET_MXCRYPTO_01/sha512_alt.h diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_02/sha1_alt.h b/features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/TARGET_MXCRYPTO_02/sha1_alt.h similarity index 100% rename from features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_02/sha1_alt.h rename to features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/TARGET_MXCRYPTO_02/sha1_alt.h diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_02/sha256_alt.h b/features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/TARGET_MXCRYPTO_02/sha256_alt.h similarity index 100% rename from features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_02/sha256_alt.h rename to features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/TARGET_MXCRYPTO_02/sha256_alt.h diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_02/sha512_alt.h b/features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/TARGET_MXCRYPTO_02/sha512_alt.h similarity index 100% rename from features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_PSOC6_02/sha512_alt.h rename to features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/TARGET_MXCRYPTO_02/sha512_alt.h diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/aes_alt.c b/features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/aes_alt.c similarity index 99% rename from features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/aes_alt.c rename to features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/aes_alt.c index d234d22aa0b..aacad6e48cb 100644 --- a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/aes_alt.c +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/aes_alt.c @@ -44,14 +44,14 @@ #include "mbedtls/platform.h" #include "mbedtls/platform_util.h" +#if defined(MBEDTLS_AES_ALT) + /* Parameter validation macros based on platform_util.h */ #define AES_VALIDATE_RET( cond ) \ MBEDTLS_INTERNAL_VALIDATE_RET( cond, MBEDTLS_ERR_AES_BAD_INPUT_DATA ) #define AES_VALIDATE( cond ) \ MBEDTLS_INTERNAL_VALIDATE( cond ) -#if defined(MBEDTLS_AES_ALT) - #include "crypto_common.h" #include "cy_crypto_core.h" @@ -107,7 +107,9 @@ static int aes_set_keys( mbedtls_aes_context *ctx, const unsigned char *key, cy_en_crypto_aes_key_length_t key_length; cy_en_crypto_status_t status; - AES_VALIDATE( ctx != NULL ); + AES_VALIDATE_RET( ctx != NULL ); + AES_VALIDATE_RET( key != NULL ); + switch( keybits ) { diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/aes_alt.h b/features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/aes_alt.h similarity index 100% rename from features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/aes_alt.h rename to features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/aes_alt.h diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/crypto_common.c b/features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/crypto_common.c similarity index 98% rename from features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/crypto_common.c rename to features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/crypto_common.c index 4f7cc3becc0..292cd7c4688 100644 --- a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/crypto_common.c +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/crypto_common.c @@ -168,5 +168,5 @@ void cy_hw_sha_clone( void *ctxDst, const void *ctxSrc, uint32_t ctxSize, CY_CRYPTO_CHECK_PARAM( shaBuffersDst != NULL ); Cy_Crypto_Core_MemCpy(((cy_hw_crypto_t *)ctxSrc)->base, ctxDst, ctxSrc, (uint16_t)ctxSize); - Cy_Crypto_Core_Sha_Init(((cy_hw_crypto_t *)ctxSrc)->base, hashStateDst, hashStateDst->mode, shaBuffersDst); + Cy_Crypto_Core_Sha_Init(((cy_hw_crypto_t *)ctxSrc)->base, hashStateDst, (cy_en_crypto_sha_mode_t)hashStateDst->mode, shaBuffersDst); } diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/crypto_common.h b/features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/crypto_common.h similarity index 100% rename from features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/crypto_common.h rename to features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/crypto_common.h diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecdsa_alt.c b/features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/ecdsa_alt.c similarity index 100% rename from features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecdsa_alt.c rename to features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/ecdsa_alt.c diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecp_alt.c b/features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/ecp_alt.c similarity index 99% rename from features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecp_alt.c rename to features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/ecp_alt.c index 811363adb78..715cf983286 100644 --- a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecp_alt.c +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/ecp_alt.c @@ -2669,21 +2669,31 @@ cy_en_crypto_ecc_curve_id_t cy_get_dp_idx(mbedtls_ecp_group_id gid) switch( gid ) { + #if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) case MBEDTLS_ECP_DP_SECP192R1: dp_idx = CY_CRYPTO_ECC_ECP_SECP192R1; break; + #endif /* defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) */ + #if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) case MBEDTLS_ECP_DP_SECP224R1: dp_idx = CY_CRYPTO_ECC_ECP_SECP224R1; break; + #endif /* defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) */ + #if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) case MBEDTLS_ECP_DP_SECP256R1: dp_idx = CY_CRYPTO_ECC_ECP_SECP256R1; break; + #endif /* defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) */ + #if defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) case MBEDTLS_ECP_DP_SECP384R1: dp_idx = CY_CRYPTO_ECC_ECP_SECP384R1; break; + #endif /* defined(MBEDTLS_ECP_DP_SECP384R1_ENABLED) */ + #if defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) case MBEDTLS_ECP_DP_SECP521R1: dp_idx = CY_CRYPTO_ECC_ECP_SECP521R1; break; + #endif /* defined(MBEDTLS_ECP_DP_SECP521R1_ENABLED) */ default: dp_idx = CY_CRYPTO_ECC_ECP_NONE; diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecp_alt.h b/features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/ecp_alt.h similarity index 100% rename from features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecp_alt.h rename to features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/ecp_alt.h diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecp_curves_alt.c b/features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/ecp_curves_alt.c similarity index 100% rename from features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/ecp_curves_alt.c rename to features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/ecp_curves_alt.c diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/mbedtls_device.h b/features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/mbedtls_device.h similarity index 100% rename from features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/mbedtls_device.h rename to features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/mbedtls_device.h diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha1_alt.c b/features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/sha1_alt.c similarity index 100% rename from features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha1_alt.c rename to features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/sha1_alt.c index 7fb5b7404bb..cdc4811a916 100644 --- a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha1_alt.c +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/sha1_alt.c @@ -39,13 +39,13 @@ #include +#if defined(MBEDTLS_SHA1_ALT) + /* Parameter validation macros based on platform_util.h */ #define SHA1_VALIDATE_RET(cond) \ MBEDTLS_INTERNAL_VALIDATE_RET( cond, MBEDTLS_ERR_SHA1_BAD_INPUT_DATA ) #define SHA1_VALIDATE(cond) MBEDTLS_INTERNAL_VALIDATE( cond ) -#if defined(MBEDTLS_SHA1_ALT) - void mbedtls_sha1_init( mbedtls_sha1_context *ctx ) { SHA1_VALIDATE( ctx != NULL ); diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha256_alt.c b/features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/sha256_alt.c similarity index 100% rename from features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha256_alt.c rename to features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/sha256_alt.c index f3c27ecd7ad..cd11a257bc9 100644 --- a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha256_alt.c +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/sha256_alt.c @@ -38,13 +38,13 @@ #include +#if defined(MBEDTLS_SHA256_ALT) + /* Parameter validation macros based on platform_util.h */ #define SHA256_VALIDATE_RET(cond) \ MBEDTLS_INTERNAL_VALIDATE_RET( cond, MBEDTLS_ERR_SHA256_BAD_INPUT_DATA ) #define SHA256_VALIDATE(cond) MBEDTLS_INTERNAL_VALIDATE( cond ) -#if defined(MBEDTLS_SHA256_ALT) - void mbedtls_sha256_init( mbedtls_sha256_context *ctx ) { SHA256_VALIDATE( ctx != NULL ); diff --git a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha512_alt.c b/features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/sha512_alt.c similarity index 100% rename from features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha512_alt.c rename to features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/sha512_alt.c index 74de3b9c8ba..f3dae2cb12e 100644 --- a/features/mbedtls/targets/TARGET_Cypress/TARGET_PSOC6/sha512_alt.c +++ b/features/mbedtls/targets/TARGET_Cypress/TARGET_MXCRYPTO/sha512_alt.c @@ -38,13 +38,13 @@ #include +#if defined(MBEDTLS_SHA512_ALT) + /* Parameter validation macros based on platform_util.h */ #define SHA512_VALIDATE_RET(cond) \ MBEDTLS_INTERNAL_VALIDATE_RET( cond, MBEDTLS_ERR_SHA512_BAD_INPUT_DATA ) #define SHA512_VALIDATE(cond) MBEDTLS_INTERNAL_VALIDATE( cond ) -#if defined(MBEDTLS_SHA512_ALT) - void mbedtls_sha512_init( mbedtls_sha512_context *ctx ) { SHA512_VALIDATE( ctx != NULL ); diff --git a/targets/targets.json b/targets/targets.json index 78c077d659d..ae26b8da767 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -8870,7 +8870,7 @@ "WATCHDOG" ], "release_versions": ["5"], - "extra_labels": ["Cypress", "PSOC6"], + "extra_labels": ["Cypress", "PSOC6", "MXCRYPTO"], "components_add": ["SOFTFP", "RTX"], "public": false, "overrides" : { @@ -8895,6 +8895,7 @@ "device_has_remove": ["ANALOGOUT"], "extra_labels_add": [ "PSOC6_02", + "MXCRYPTO_02", "CM0P_SLEEP", "WHD", "4343W", @@ -8913,6 +8914,7 @@ "device_has_remove": ["ANALOGOUT"], "extra_labels_add": [ "PSOC6_02", + "MXCRYPTO_02", "CM0P_SLEEP", "WHD", "43012", @@ -8931,6 +8933,7 @@ "supported_form_factors": ["ARDUINO"], "extra_labels_add": [ "PSOC6_01", + "MXCRYPTO_01", "CM0P_SLEEP", "WHD", "4343W", @@ -8972,6 +8975,7 @@ "supported_form_factors": ["ARDUINO"], "extra_labels_add": [ "PSOC6_01", + "MXCRYPTO_01", "CM0P_SLEEP" ], "macros_add": ["CY8C6347BZI_BLD53"], @@ -8987,7 +8991,7 @@ "components_remove": ["QSPIF"], "device_has_remove": ["QSPI"], "supported_form_factors": ["ARDUINO"], - "extra_labels_add": ["PSOC6_01"], + "extra_labels_add": ["PSOC6_01", "MXCRYPTO_01"], "macros_add": ["CYB06447BZI_D54", "PSOC6_DYNSRM_DISABLE=1", "CY_CFG_SYSCLK_WCO_ENABLED=1", @@ -9004,6 +9008,7 @@ "features": ["BLE"], "extra_labels_add": [ "PSOC6_01", + "MXCRYPTO_01", "CM0P_SLEEP", "WHD", "43012", @@ -9023,7 +9028,7 @@ "inherits": ["MCU_PSOC6_M0"], "supported_form_factors": ["ARDUINO"], "extra_labels_add": ["PSOC6_FUTURE", "CY8C63XX", "FUTURE_SEQUANA"], - "extra_labels_remove": ["PSOC6"], + "extra_labels_remove": ["PSOC6", "MXCRYPTO"], "device_has_remove": ["TRNG", "CRC", "I2CSLAVE", "USBDEVICE", "QSPI", "WATCHDOG"], "macros_add": ["CY8C6347BZI_BLD53"], "macros_remove": ["MBEDTLS_CONFIG_HW_SUPPORT"], @@ -9057,7 +9062,7 @@ "supported_form_factors": ["ARDUINO"], "components_remove": ["QSPIF"], "extra_labels_add": ["PSOC6_FUTURE", "CY8C63XX", "CORDIO"], - "extra_labels_remove": ["PSOC6"], + "extra_labels_remove": ["PSOC6", "MXCRYPTO"], "device_has_remove": ["TRNG", "CRC", "I2CSLAVE", "USBDEVICE", "QSPI", "WATCHDOG"], "macros_add": ["CY8C6347BZI_BLD53"], "macros_remove": ["MBEDTLS_CONFIG_HW_SUPPORT"], From 13b9035f76c434ecc95c033e00fd1caf2f725868 Mon Sep 17 00:00:00 2001 From: Hugues Kamba Date: Thu, 12 Sep 2019 13:20:47 +0100 Subject: [PATCH 084/227] Suppress Coverity warnings --- platform/source/mbed_retarget.cpp | 3 ++- rtos/source/TARGET_CORTEX/rtx4/cmsis_os1.c | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/platform/source/mbed_retarget.cpp b/platform/source/mbed_retarget.cpp index 6679d872193..61adeeb0f90 100644 --- a/platform/source/mbed_retarget.cpp +++ b/platform/source/mbed_retarget.cpp @@ -443,7 +443,7 @@ std::FILE *fdopen(FileHandle *fh, const char *mode) { // First reserve the integer file descriptor int fd = bind_to_fd(fh); - if (!fd) { + if (fd < 0) { return NULL; } // Then bind that to the C stream. If successful, C library @@ -825,6 +825,7 @@ int _lseek(FILEHANDLE fh, int offset, int whence) off_t off = lseek(fh, offset, whence); // Assuming INT_MAX = LONG_MAX, so we don't care about prototype difference + // coverity[result_independent_of_operands] if (off > INT_MAX) { // Be cautious in case off_t is 64-bit errno = EOVERFLOW; diff --git a/rtos/source/TARGET_CORTEX/rtx4/cmsis_os1.c b/rtos/source/TARGET_CORTEX/rtx4/cmsis_os1.c index a68eb0a1d8b..ce0ca3f7bed 100644 --- a/rtos/source/TARGET_CORTEX/rtx4/cmsis_os1.c +++ b/rtos/source/TARGET_CORTEX/rtx4/cmsis_os1.c @@ -267,6 +267,7 @@ osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id) { } ptr->mp_id = osMemoryPoolNew (queue_def->queue_sz, queue_def->item_sz, &queue_def->mp_attr); + // coverity[suspicious_sizeof] ptr->mq_id = osMessageQueueNew(queue_def->queue_sz, sizeof(void *), &queue_def->mq_attr); if ((ptr->mp_id == NULL) || (ptr->mq_id == NULL)) { if (ptr->mp_id != NULL) { From c4bc75661b27fe08a122b362b7c7202b6e991799 Mon Sep 17 00:00:00 2001 From: Darryl Green Date: Thu, 12 Sep 2019 16:04:44 +0100 Subject: [PATCH 085/227] Remove Mbed Crypto source files before importing --- features/mbedtls/mbed-crypto/importer/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/features/mbedtls/mbed-crypto/importer/Makefile b/features/mbedtls/mbed-crypto/importer/Makefile index a92e7036610..cd58e4c3aef 100644 --- a/features/mbedtls/mbed-crypto/importer/Makefile +++ b/features/mbedtls/mbed-crypto/importer/Makefile @@ -90,6 +90,7 @@ rsync: # Copying Mbed Crypto into Mbed OS... rm -rf $(TARGET_SRV_IMPL) rm -rf $(TARGET_SPE) + rm -rf $(TARGET_SRC) mkdir -p $(TARGET_SRV_IMPL) mkdir -p $(TARGET_SPE) From c9f7798df525be7a820e5d7c0085817927c40178 Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Wed, 11 Sep 2019 17:52:08 +0200 Subject: [PATCH 086/227] STM32WB ADC : Consecutive VBAT values reading was not possible Add Stop after read --- targets/TARGET_STM/TARGET_STM32WB/analogin_device.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/targets/TARGET_STM/TARGET_STM32WB/analogin_device.c b/targets/TARGET_STM/TARGET_STM32WB/analogin_device.c index 4e1769889de..e200ed3a603 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/analogin_device.c +++ b/targets/TARGET_STM/TARGET_STM32WB/analogin_device.c @@ -194,6 +194,11 @@ uint16_t adc_read(analogin_t *obj) if (HAL_ADC_PollForConversion(&obj->handle, 10) == HAL_OK) { adcValue = (uint16_t)HAL_ADC_GetValue(&obj->handle); } + + if (HAL_ADC_Stop(&obj->handle) != HAL_OK) { + debug("HAL_ADC_Stop failed\r\n"); + } + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE((&obj->handle)->Instance), LL_ADC_PATH_INTERNAL_NONE); return adcValue; } From 0ec45a50eab622357d4b24fdb4d16361cac0bf4c Mon Sep 17 00:00:00 2001 From: Hugues Kamba Date: Wed, 11 Sep 2019 15:44:07 +0100 Subject: [PATCH 087/227] Minimal-printf: Remove file printing in README and update tables --- platform/source/minimal-printf/README.md | 39 +++++++++++------------- 1 file changed, 18 insertions(+), 21 deletions(-) diff --git a/platform/source/minimal-printf/README.md b/platform/source/minimal-printf/README.md index cddfcbfcb46..7c287e78a34 100644 --- a/platform/source/minimal-printf/README.md +++ b/platform/source/minimal-printf/README.md @@ -118,30 +118,27 @@ https://github.com/ARMmbed/mbed-os-example-blinky-baremetal application compiled Blinky application size on K64F/GCC_ARM -| | File stream | Floating point | 64 bit integers | Flash | RAM | -| - | - | - | - | - | - | -| mbed-printf | | | | 17,168 | 5,880 | -| mbed-printf | | | X | 17,308 | 5,880 | -| mbed-printf | | X | X | 20,044 | 5,880 | -| mbed-printf | X | X | X | 22,560 | 5,880 | -| std printf | X | X | X | 35,244 | 5,864 | +| | Floating point | 64 bit integers | Flash | RAM | +| - | - | - | - | - | +| mbed-printf | | | 19,660 | 5,368 | +| mbed-printf | | X | 19,804 | 5,368 | +| mbed-printf | X | X | 22,548 | 5,368 | +| std printf | X | X | 35,292 | 5,864 | Blinky application size on K64F/ARMC6 -| | File stream | Floating point | 64 bit integers | Flash | RAM | -| - | - | - | - | - | - | -| mbed-printf | | | | 19,496 | xxxxx | -| mbed-printf | | | X | 19,644 | xxxxx | -| mbed-printf | | X | X | 22,468 | xxxxx | -| mbed-printf | X | X | X | 23,060 | xxxxx | -| std printf | X | X | X | 25,393 | xxxxx | +| | Floating point | 64 bit integers | Flash | RAM | +| - | - | - | - | - | +| mbed-printf | | | 18,764 | xxxxx | +| mbed-printf | | X | 18,764 | xxxxx | +| mbed-printf | X | X | 18,764 | xxxxx | +| std printf | X | X | 25,403 | xxxxx | Blinky application size on K64F/IAR -| | File stream | Floating point | 64 bit integers | Flash | RAM | -| - | - | - | - | - | - | -| mbed-printf | | | | 13,007 | 1,413 | -| mbed-printf | | | X | 13,147 | 1,413 | -| mbed-printf | | X | X | 14,955 | 1,413 | -| mbed-printf | X | X | X | 21,757 | 1,929 | -| std printf | X | X | X | 17,991 | 1,281 | +| | Floating point | 64 bit integers | Flash | RAM | +| - | - | - | - | - | +| mbed-printf | | | 19,623 | 1,737 | +| mbed-printf | | X | 19,763 | 1,737 | +| mbed-printf | X | X | 21,571 | 1,737 | +| std printf | X | X | 18,059 | 1,281 | From 82cc1801d3dde8a98293e622b31f710c3dc140df Mon Sep 17 00:00:00 2001 From: Marcin Tomczyk Date: Mon, 9 Sep 2019 11:12:51 +0200 Subject: [PATCH 088/227] Add missing documentation about tls testing --- TESTS/netsocket/README.md | 80 +++++++++++++++++++++++++++++++++++- TESTS/netsocket/tls/cert.h | 48 ++++++++++++++++++++++ TESTS/netsocket/tls/main.cpp | 30 +------------- 3 files changed, 127 insertions(+), 31 deletions(-) create mode 100644 TESTS/netsocket/tls/cert.h diff --git a/TESTS/netsocket/README.md b/TESTS/netsocket/README.md index d26b2228901..6200e61dea3 100644 --- a/TESTS/netsocket/README.md +++ b/TESTS/netsocket/README.md @@ -51,7 +51,7 @@ echo.mbedcloudtesting.com has IPv6 address 2a05:d018:21f:3800:8584:60f8:bc9f:e61 - Echo protocol, [RFC 862](https://tools.ietf.org/html/rfc862) is enabled on both TCP and UDP on port 7. Port 2007 for TLS - Discard protocol, [RFC 863](https://tools.ietf.org/html/rfc863) is enabled in both TCP and UDP on port 9. Port 2009 for TLS. -- Character generator protocol, [RFC 864](https://tools.ietf.org/html/rfc864) is enabled in both TCP and UDP on port 19. Output pattern should follow the proposed example pattern in RFC. +- Character generator protocol, [RFC 864](https://tools.ietf.org/html/rfc864) is enabled in both TCP and UDP on port 19. Port 2019 for TLS. Output pattern should follow the proposed example pattern in RFC. - Daytime protocol, [RFC 867](https://tools.ietf.org/html/rfc867) in both TCP and UDP on port 13. Port 2013 for TLS. - Time protocol, [RFC 868](https://tools.ietf.org/html/rfc868) in both TCP and UDP on port 37. @@ -80,6 +80,82 @@ daytime stream tcp6 nowait root internal time stream tcp6 nowait root internal ``` +Below is an example of how to install these services in TLS version into a Debian/Ubuntu based Linux distribution using Stunnel4 Daemon: + +```.sh +$ sudo apt install stunnel4 +$ nano /etc/stunnel/stunnel.conf +``` + +Enable following services from /etc/inetd.conf: + +``` +; ************************************************************************** +; * Service definitions (remove all services for inetd mode) * +; ************************************************************************** + +[echo] +accept = :::2007 +connect = 7 +cert = /etc/letsencrypt/live//fullchain.pem +key = /etc/letsencrypt/live//privkey.pem + +[discard] +accept = :::2009 +connect = 9 +cert = /etc/letsencrypt/live//fullchain.pem +key = /etc/letsencrypt/live//privkey.pem + +[daytime] +accept = :::2013 +connect = 13 +cert =/etc/letsencrypt/live//fullchain.pem +key = /etc/letsencrypt/live//privkey.pem + +[chargen] +accept = :::2019 +connect = 19 +cert = /etc/letsencrypt/live//fullchain.pem +key = /etc/letsencrypt/live//privkey.pem + +``` + +Get, update and install certificate files by certbot (Provided by Let's Encrypt ). + +- Install lighthttpd server. + +```.sh +$ sudo apt-get install lighttpd +$ sudo rm -rf /var/www/html/* +$ sudo echo "

Empty

" > /var/www/html/index.html +$ sudo echo "" >> /var/www/html/index.html +$ sudo chown www-data:www-data /var/www/html/index.html +$ sudo systemctl restart lighttpd.service +``` + +- Install and setup certbot. + +```.sh +$ sudo apt-get update +$ sudo apt-get install software-properties-common +$ sudo add-apt-repository ppa:certbot/certbot +$ sudo apt-get update +$ sudo apt-get install certbot +$ sudo certbot certonly +$ sudo certbot certonly --webroot -w /var/www/html -d +``` + +- Set test server to renew certificate before expiry. + +```.sh +$ sudo echo "SHELL=/bin/sh" > /etc/cron.d/certbot +$ sudo echo "PATH=/usr/local/sbin:/usr/local/bin:/sbin:/bin:/usr/sbin:/usr/bin" > /etc/cron.d/certbot +$ sudo echo "0 */12 * * * root test -x /usr/bin/certbot -a \! -d /run/systemd/system && perl -e 'sleep int(rand(43200))' && certbot -q renew" > /etc/cron.d/certbot +``` + +Where: + is test server url. + **Testing the connectivity** You can connect to the test server with an NMAP tool like this: @@ -1918,4 +1994,4 @@ Subset for driver test ### For socket layer driver (AT-driven, external IP stack): -All Socket, UDPSocket, TCPSocket and TLSSocket testcases. \ No newline at end of file +All Socket, UDPSocket, TCPSocket and TLSSocket testcases. diff --git a/TESTS/netsocket/tls/cert.h b/TESTS/netsocket/tls/cert.h new file mode 100644 index 00000000000..3bbaf5ca7e1 --- /dev/null +++ b/TESTS/netsocket/tls/cert.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2019, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "tls_tests.h" + +const char *tls_global::cert = \ + "-----BEGIN CERTIFICATE-----\n" + "MIIEkjCCA3qgAwIBAgIQCgFBQgAAAVOFc2oLheynCDANBgkqhkiG9w0BAQsFADA/\n" + "MSQwIgYDVQQKExtEaWdpdGFsIFNpZ25hdHVyZSBUcnVzdCBDby4xFzAVBgNVBAMT\n" + "DkRTVCBSb290IENBIFgzMB4XDTE2MDMxNzE2NDA0NloXDTIxMDMxNzE2NDA0Nlow\n" + "SjELMAkGA1UEBhMCVVMxFjAUBgNVBAoTDUxldCdzIEVuY3J5cHQxIzAhBgNVBAMT\n" + "GkxldCdzIEVuY3J5cHQgQXV0aG9yaXR5IFgzMIIBIjANBgkqhkiG9w0BAQEFAAOC\n" + "AQ8AMIIBCgKCAQEAnNMM8FrlLke3cl03g7NoYzDq1zUmGSXhvb418XCSL7e4S0EF\n" + "q6meNQhY7LEqxGiHC6PjdeTm86dicbp5gWAf15Gan/PQeGdxyGkOlZHP/uaZ6WA8\n" + "SMx+yk13EiSdRxta67nsHjcAHJyse6cF6s5K671B5TaYucv9bTyWaN8jKkKQDIZ0\n" + "Z8h/pZq4UmEUEz9l6YKHy9v6Dlb2honzhT+Xhq+w3Brvaw2VFn3EK6BlspkENnWA\n" + "a6xK8xuQSXgvopZPKiAlKQTGdMDQMc2PMTiVFrqoM7hD8bEfwzB/onkxEz0tNvjj\n" + "/PIzark5McWvxI0NHWQWM6r6hCm21AvA2H3DkwIDAQABo4IBfTCCAXkwEgYDVR0T\n" + "AQH/BAgwBgEB/wIBADAOBgNVHQ8BAf8EBAMCAYYwfwYIKwYBBQUHAQEEczBxMDIG\n" + "CCsGAQUFBzABhiZodHRwOi8vaXNyZy50cnVzdGlkLm9jc3AuaWRlbnRydXN0LmNv\n" + "bTA7BggrBgEFBQcwAoYvaHR0cDovL2FwcHMuaWRlbnRydXN0LmNvbS9yb290cy9k\n" + "c3Ryb290Y2F4My5wN2MwHwYDVR0jBBgwFoAUxKexpHsscfrb4UuQdf/EFWCFiRAw\n" + "VAYDVR0gBE0wSzAIBgZngQwBAgEwPwYLKwYBBAGC3xMBAQEwMDAuBggrBgEFBQcC\n" + "ARYiaHR0cDovL2Nwcy5yb290LXgxLmxldHNlbmNyeXB0Lm9yZzA8BgNVHR8ENTAz\n" + "MDGgL6AthitodHRwOi8vY3JsLmlkZW50cnVzdC5jb20vRFNUUk9PVENBWDNDUkwu\n" + "Y3JsMB0GA1UdDgQWBBSoSmpjBH3duubRObemRWXv86jsoTANBgkqhkiG9w0BAQsF\n" + "AAOCAQEA3TPXEfNjWDjdGBX7CVW+dla5cEilaUcne8IkCJLxWh9KEik3JHRRHGJo\n" + "uM2VcGfl96S8TihRzZvoroed6ti6WqEBmtzw3Wodatg+VyOeph4EYpr/1wXKtx8/\n" + "wApIvJSwtmVi4MFU5aMqrSDE6ea73Mj2tcMyo5jMd6jmeWUHK8so/joWUoHOUgwu\n" + "X4Po1QYz+3dszkDqMp4fklxBwXRsW10KXzPMTZ+sOPAveyxindmjkW8lGy+QsRlG\n" + "PfZ+G6Z6h7mjem0Y+iWlkYcV4PIWL1iwBi8saCbGS5jN2p8M+X+Q7UNKEkROb3N6\n" + "KOqkqm57TH2H3eDJAkSnh6/DNFu0Qg==\n" + "-----END CERTIFICATE-----\n"; + diff --git a/TESTS/netsocket/tls/main.cpp b/TESTS/netsocket/tls/main.cpp index 2a8fb9033a8..bd1fff47755 100644 --- a/TESTS/netsocket/tls/main.cpp +++ b/TESTS/netsocket/tls/main.cpp @@ -27,6 +27,7 @@ #include "utest.h" #include "utest/utest_stack_trace.h" #include "tls_tests.h" +#include "cert.h" #ifndef ECHO_SERVER_ADDR #error [NOT_SUPPORTED] Requires parameters for echo server @@ -47,35 +48,6 @@ mbed_stats_socket_t tls_stats[MBED_CONF_NSAPI_SOCKET_STATS_MAX_COUNT]; char tls_global::rx_buffer[RX_BUFF_SIZE]; char tls_global::tx_buffer[TX_BUFF_SIZE]; -const char *tls_global::cert = \ - "-----BEGIN CERTIFICATE-----\n" - "MIIEkjCCA3qgAwIBAgIQCgFBQgAAAVOFc2oLheynCDANBgkqhkiG9w0BAQsFADA/\n" - "MSQwIgYDVQQKExtEaWdpdGFsIFNpZ25hdHVyZSBUcnVzdCBDby4xFzAVBgNVBAMT\n" - "DkRTVCBSb290IENBIFgzMB4XDTE2MDMxNzE2NDA0NloXDTIxMDMxNzE2NDA0Nlow\n" - "SjELMAkGA1UEBhMCVVMxFjAUBgNVBAoTDUxldCdzIEVuY3J5cHQxIzAhBgNVBAMT\n" - "GkxldCdzIEVuY3J5cHQgQXV0aG9yaXR5IFgzMIIBIjANBgkqhkiG9w0BAQEFAAOC\n" - "AQ8AMIIBCgKCAQEAnNMM8FrlLke3cl03g7NoYzDq1zUmGSXhvb418XCSL7e4S0EF\n" - "q6meNQhY7LEqxGiHC6PjdeTm86dicbp5gWAf15Gan/PQeGdxyGkOlZHP/uaZ6WA8\n" - "SMx+yk13EiSdRxta67nsHjcAHJyse6cF6s5K671B5TaYucv9bTyWaN8jKkKQDIZ0\n" - "Z8h/pZq4UmEUEz9l6YKHy9v6Dlb2honzhT+Xhq+w3Brvaw2VFn3EK6BlspkENnWA\n" - "a6xK8xuQSXgvopZPKiAlKQTGdMDQMc2PMTiVFrqoM7hD8bEfwzB/onkxEz0tNvjj\n" - "/PIzark5McWvxI0NHWQWM6r6hCm21AvA2H3DkwIDAQABo4IBfTCCAXkwEgYDVR0T\n" - "AQH/BAgwBgEB/wIBADAOBgNVHQ8BAf8EBAMCAYYwfwYIKwYBBQUHAQEEczBxMDIG\n" - "CCsGAQUFBzABhiZodHRwOi8vaXNyZy50cnVzdGlkLm9jc3AuaWRlbnRydXN0LmNv\n" - "bTA7BggrBgEFBQcwAoYvaHR0cDovL2FwcHMuaWRlbnRydXN0LmNvbS9yb290cy9k\n" - "c3Ryb290Y2F4My5wN2MwHwYDVR0jBBgwFoAUxKexpHsscfrb4UuQdf/EFWCFiRAw\n" - "VAYDVR0gBE0wSzAIBgZngQwBAgEwPwYLKwYBBAGC3xMBAQEwMDAuBggrBgEFBQcC\n" - "ARYiaHR0cDovL2Nwcy5yb290LXgxLmxldHNlbmNyeXB0Lm9yZzA8BgNVHR8ENTAz\n" - "MDGgL6AthitodHRwOi8vY3JsLmlkZW50cnVzdC5jb20vRFNUUk9PVENBWDNDUkwu\n" - "Y3JsMB0GA1UdDgQWBBSoSmpjBH3duubRObemRWXv86jsoTANBgkqhkiG9w0BAQsF\n" - "AAOCAQEA3TPXEfNjWDjdGBX7CVW+dla5cEilaUcne8IkCJLxWh9KEik3JHRRHGJo\n" - "uM2VcGfl96S8TihRzZvoroed6ti6WqEBmtzw3Wodatg+VyOeph4EYpr/1wXKtx8/\n" - "wApIvJSwtmVi4MFU5aMqrSDE6ea73Mj2tcMyo5jMd6jmeWUHK8so/joWUoHOUgwu\n" - "X4Po1QYz+3dszkDqMp4fklxBwXRsW10KXzPMTZ+sOPAveyxindmjkW8lGy+QsRlG\n" - "PfZ+G6Z6h7mjem0Y+iWlkYcV4PIWL1iwBi8saCbGS5jN2p8M+X+Q7UNKEkROb3N6\n" - "KOqkqm57TH2H3eDJAkSnh6/DNFu0Qg==\n" - "-----END CERTIFICATE-----\n"; - void drop_bad_packets(TLSSocket &sock, int orig_timeout) { nsapi_error_t err; From a26835d9acc60cfb6b83ffe8d7a21fbbcfa1c478 Mon Sep 17 00:00:00 2001 From: Amanda Butler Date: Tue, 10 Sep 2019 15:20:55 -0500 Subject: [PATCH 089/227] Edit README.md Edit document. --- TESTS/netsocket/README.md | 1356 ++++++++++++++++++------------------- 1 file changed, 643 insertions(+), 713 deletions(-) diff --git a/TESTS/netsocket/README.md b/TESTS/netsocket/README.md index 6200e61dea3..0cf9eb35c17 100644 --- a/TESTS/netsocket/README.md +++ b/TESTS/netsocket/README.md @@ -5,7 +5,6 @@ This is a test plan for the Mbed OS Socket API. This describes all test cases an **NOTE:** Because testing is a moving target, this test plan might define more test cases than Mbed OS implements. Refer to [test case priorities](#test-case-priorities) for a list of test cases that the target must pass to be compliant with the Mbed OS socket API. - Target API ---------- @@ -17,13 +16,13 @@ The target for this plan is to test: - [TLSSocket](https://github.com/ARMmbed/mbed-os/blob/master/features/netsocket/TLSSocket.h). - [DNS](https://github.com/ARMmbed/mbed-os/blob/master/features/netsocket/DNS.h). -Please see the [Network Socket Documentation](https://os.mbed.com/docs/mbed-os/latest/apis/network-socket.html) for reference. +Please see the [Network Socket documentation](https://os.mbed.com/docs/mbed-os/latest/apis/network-socket.html) for reference. Tools to use ---------------- - Mbed OS. -- Standard Mbed OS development tools as described in the [Arm Mbed tools overview](https://os.mbed.com/docs/latest/tools/index.html). +- Standard Mbed OS development tools as described in the [Mbed OS tools overview](https://os.mbed.com/docs/latest/tools/index.html). - Test server. These test cases themselves do not require any special tooling, other than the test server described in "Test environment" chapter. @@ -37,7 +36,7 @@ The test environment consist of DUTs, network connection and the test server. Ar ### Public test server -Address: `echo.mbedcloudtesting.com'. +Address: `echo.mbedcloudtesting.com`. Both IPv4 and IPv6 addresses are available from a public DNS service: @@ -51,7 +50,7 @@ echo.mbedcloudtesting.com has IPv6 address 2a05:d018:21f:3800:8584:60f8:bc9f:e61 - Echo protocol, [RFC 862](https://tools.ietf.org/html/rfc862) is enabled on both TCP and UDP on port 7. Port 2007 for TLS - Discard protocol, [RFC 863](https://tools.ietf.org/html/rfc863) is enabled in both TCP and UDP on port 9. Port 2009 for TLS. -- Character generator protocol, [RFC 864](https://tools.ietf.org/html/rfc864) is enabled in both TCP and UDP on port 19. Port 2019 for TLS. Output pattern should follow the proposed example pattern in RFC. +- Character generator protocol, [RFC 864](https://tools.ietf.org/html/rfc864) is enabled in both TCP and UDP on port 19. Port 2019 for TLS. The output pattern follows the proposed example pattern in RFC. - Daytime protocol, [RFC 867](https://tools.ietf.org/html/rfc867) in both TCP and UDP on port 13. Port 2013 for TLS. - Time protocol, [RFC 868](https://tools.ietf.org/html/rfc868) in both TCP and UDP on port 37. @@ -122,43 +121,42 @@ key = /etc/letsencrypt/live//privkey.pem Get, update and install certificate files by certbot (Provided by Let's Encrypt ). -- Install lighthttpd server. - -```.sh -$ sudo apt-get install lighttpd -$ sudo rm -rf /var/www/html/* -$ sudo echo "

Empty

" > /var/www/html/index.html -$ sudo echo "" >> /var/www/html/index.html -$ sudo chown www-data:www-data /var/www/html/index.html -$ sudo systemctl restart lighttpd.service -``` - -- Install and setup certbot. - -```.sh -$ sudo apt-get update -$ sudo apt-get install software-properties-common -$ sudo add-apt-repository ppa:certbot/certbot -$ sudo apt-get update -$ sudo apt-get install certbot -$ sudo certbot certonly -$ sudo certbot certonly --webroot -w /var/www/html -d -``` - +- Install lighthttpd server: + + ```.sh + $ sudo apt-get install lighttpd + $ sudo rm -rf /var/www/html/* + $ sudo echo "

Empty

" > /var/www/html/index.html + $ sudo echo "" >> /var/www/html/index.html + $ sudo chown www-data:www-data /var/www/html/index.html + $ sudo systemctl restart lighttpd.service + ``` + +- Install and set up certbot: + + ```.sh + $ sudo apt-get update + $ sudo apt-get install software-properties-common + $ sudo add-apt-repository ppa:certbot/certbot + $ sudo apt-get update + $ sudo apt-get install certbot + $ sudo certbot certonly + $ sudo certbot certonly --webroot -w /var/www/html -d + ``` + - Set test server to renew certificate before expiry. + + ```.sh + $ sudo echo "SHELL=/bin/sh" > /etc/cron.d/certbot + $ sudo echo "PATH=/usr/local/sbin:/usr/local/bin:/sbin:/bin:/usr/sbin:/usr/bin" > /etc/cron.d/certbot + $ sudo echo "0 */12 * * * root test -x /usr/bin/certbot -a \! -d /run/systemd/system && perl -e 'sleep int(rand(43200))' && certbot -q renew" > /etc/cron.d/certbot + ``` -```.sh -$ sudo echo "SHELL=/bin/sh" > /etc/cron.d/certbot -$ sudo echo "PATH=/usr/local/sbin:/usr/local/bin:/sbin:/bin:/usr/sbin:/usr/bin" > /etc/cron.d/certbot -$ sudo echo "0 */12 * * * root test -x /usr/bin/certbot -a \! -d /run/systemd/system && perl -e 'sleep int(rand(43200))' && certbot -q renew" > /etc/cron.d/certbot -``` - -Where: - is test server url. +Where is the test server URL. **Testing the connectivity** -You can connect to the test server with an NMAP tool like this: +You can connect to the test server with an NMAP tool: ```.sh $ nmap -sT -p7,9,13,37,2007,2009,2013 echo.mbedcloudtesting.com @@ -202,7 +200,7 @@ Nmap done: 1 IP address (1 host up) scanned in 1.78 seconds ![Ethernet](eth_environment.png) -The Ethernet test environment consists of devices, an ethernet switch and an optional firewall that allows connecting to the Echo server. +The Ethernet test environment consists of devices, an Ethernet switch and an optional firewall that allows connecting to the Echo server. ### Wi-Fi test environment @@ -299,7 +297,7 @@ Please refer to the following table for priorities of test cases. Priorities are Building test binaries -------------------------- -For testing the board and driver, test against the Mbed OS master branch to get the most recent, up-to-date test cases and drivers. +To test the board and driver, test against the Mbed OS master branch to get the most recent, up-to-date test cases and drivers. To create a build environment: @@ -404,9 +402,10 @@ Wi-Fi tests require some more configuration, so for Wi-Fi purposes, the `mbed_ap } } ``` + Please, see `mbed-os/tools/test_configs` folder for examples. -Now build test binaries: +Now build the test binaries: ```.sh mbed test --compile -t -m -n mbed-os-tests-network-*,mbed-os-tests-netsocket* @@ -415,7 +414,7 @@ mbed test --compile -t -m -n mbed-os-tests-network-*,mbed-o Running tests ------------- -When device is connected to network, or in case of wireless device near the access point. +Run this when the device is connected to network, or if the wireless device is near the access point: ```.sh mbed test -n mbed-os-tests-network-*,mbed-os-tests-netsocket* @@ -424,156 +423,144 @@ mbed test -n mbed-os-tests-network-*,mbed-os-tests-netsocket* Test cases for Socket class --------------------------- -These test are equal for UDPSocket and TCPSocket but are described here because of identical API and behaviour. Socket class is abstract so it cannot be instantiated, therefore these test cases are implemented using both TCPSocket and UDPSocket. Some of these tests are also implemented for TLSSocket class. In such case certificate has to be set for the Socket before calling `open()`, unless specified otherwise in the test's +These tests are the same as those for UDPSocket and TCPSocket. The Socket class is abstract, so it cannot be instantiated; therefore, these test cases are implemented using both TCPSocket and UDPSocket. Some of these tests are also implemented for the TLSSocket class. In such case, the certificate has to be set for the Socket before calling `open()`, unless specified otherwise in the test's description. ### SOCKET_OPEN_DESTRUCT **Description:** -Call `Socket::open()` and then destruct the socket. +Call `Socket::open()`, and then destruct the socket. **Preconditions:** -1. Network interface and stack are initialized. -2. Network connection is up. +1. Network interface and stack are initialized. +1. Network connection is up. **Test steps:** -1. Create an object by calling `new Socket()`. -2. Call `Socket::open(stack)`. -3. Delete the object. -4. Repeat 100 times. +1. Create an object by calling `new Socket()`. +1. Call `Socket::open(stack)`. +1. Delete the object. +1. Repeat 100 times. **Expected result:** -`Socket::open()` should always return `NSAPI_ERROR_OK`. - - +`Socket::open()` always returns `NSAPI_ERROR_OK`. ### SOCKET_OPEN_LIMIT **Description:** - Call `Socket::open()` until it runs out of memory or other internal limit -in the stack is reached. + Call `Socket::open()` until it runs out of memory or another internal limit in the stack is reached. **Preconditions:** -1. Network interface and stack are initialized. -2. Network connection is up. +1. Network interface and stack are initialized. +1. Network connection is up. **Test steps:** -1. Create a object by calling `new Socket()`. -2. Call `Socket::open(stack)`. -3. Repeat until `NSAPI_ERROR_NO_MEMORY` or `NSAPI_ERROR_NO_SOCKET` error code is returned. -4. Call "delete" for all previously allocated sockets. -5. Repeat. +1. Create an object by calling `new Socket()`. +1. Call `Socket::open(stack)`. +1. Repeat until `NSAPI_ERROR_NO_MEMORY` or `NSAPI_ERROR_NO_SOCKET` error code is returned. +1. Call "delete" for all previously allocated sockets. +1. Repeat. **Expected result:** -Should be able to reserve at least 4 sockets. After freeing all sockets, should be able to reserve same number of sockets. - - +It can reserve at least four sockets. After freeing all sockets, it can reserve the same number of sockets. ### SOCKET_OPEN_TWICE **Description:** -Call `Socket::open()` twice +Call `Socket::open()` twice. **Preconditions:** -1. Network interface and stack are initialized. -2. Network connection is up. +1. Network interface and stack are initialized. +1. Network connection is up. **Test steps:** -1. Create a object by calling `new Socket()`. -2. Call `Socket::open(stack)`. -3. Call `Socket::open(stack)`. -4. Delete the socket. +1. Create an object by calling `new Socket()`. +1. Call `Socket::open(stack)`. +1. Call `Socket::open(stack)`. +1. Delete the socket. **Expected result:** -`Socket::open()` should first return `NSAPI_ERROR_OK` and second call `NSAPI_ERROR_PARAMETER`. - - +`Socket::open()` first returns `NSAPI_ERROR_OK` and then calls `NSAPI_ERROR_PARAMETER`. ### SOCKET_OPEN_CLOSE_REPEAT **Description:** -Call `Socket::open()` followed by `Socket::close()` and then again `Socket::open()`. Should allow you to reuse the same object. +Call `Socket::open()` followed by `Socket::close()` and then again `Socket::open()`. This allows you to reuse the same object. **Preconditions:** -1. Network interface and stack are initialized. -2. Network connection is up. +1. Network interface and stack are initialized. +1. Network connection is up. **Test steps:** -1. Create a object by calling `new Socket()`. -2. Call `Socket::open(stack)`. -3. Call `Socket::close(stack)`. -4. Call `Socket::open(stack)`. -5. Call `Socket::close(stack)`. -6. Delete the socket. +1. Create an object by calling `new Socket()`. +1. Call `Socket::open(stack)`. +1. Call `Socket::close(stack)`. +1. Call `Socket::open(stack)`. +1. Call `Socket::close(stack)`. +1. Delete the socket. **Expected result:** -All `Socket::open()` and `Socket::close()` calls should return `NSAPI_ERROR_OK`. - +All `Socket::open()` and `Socket::close()` calls return `NSAPI_ERROR_OK`. ### SOCKET_BIND_PORT **Description:** -Call `Socket::bind(port)'. +Call `Socket::bind(port)`. **Preconditions:** -1. Network interface and stack are initialized. -2. Network connection is up. +1. Network interface and stack are initialized. +1. Network connection is up. **Test steps:** -1. Create a object by calling `new Socket()`. -2. Call `Socket::open(stack)`. -3. Call `Socket::bind();`. -4. Destroy socket. +1. Create an object by calling `new Socket()`. +1. Call `Socket::open(stack)`. +1. Call `Socket::bind();`. +1. Destroy the socket. **Expected result:** All calls return `NSAPI_ERROR_OK`. - - ### SOCKET_BIND_PORT_FAIL **Description:** -Call `Socket::bind(port)` on port number that is already used +Call `Socket::bind(port)` on a port number that is already used. **Preconditions:** -1. Network interface and stack are initialized. -2. Network connection is up. +1. Network interface and stack are initialized. +1. Network connection is up. **Test steps:** -1. Create a object by calling `new Socket()`. -2. Call `Socket::open(stack)`. -3. Call `Socket::bind();`. -4. Repeat 1-3 for a new socket. -5. Destroy both sockets. +1. Create an object by calling `new Socket()`. +1. Call `Socket::open(stack)`. +1. Call `Socket::bind();`. +1. Repeat steps 1-3 for a new socket. +1. Destroy both sockets. **Expected result:** -Second `Socket::bind()` should return `NSAPI_ERROR_PARAMETER`. - - +The second `Socket::bind()` returns `NSAPI_ERROR_PARAMETER`. ### SOCKET_BIND_ADDRESS_PORT @@ -583,23 +570,21 @@ Call `Socket::bind(addr, port)`. **Preconditions:** -1. Network interface and stack are initialized. -2. Network connection is up. +1. Network interface and stack are initialized. +1. Network connection is up. **Test steps:** -1. Create a object by calling `new Socket()`. -2. Call `Socket::open(stack)`. -3. Get address by calling `NetworkInterface::get_ip_address()`. -4. Call `Socket::bind(address, );`. -5. Destroy socket. +1. Create an object by calling `new Socket()`. +1. Call `Socket::open(stack)`. +1. Get address by calling `NetworkInterface::get_ip_address()`. +1. Call `Socket::bind(address, );`. +1. Destroy the socket. **Expected result:** All calls return `NSAPI_ERROR_OK`. - - ### SOCKET_BIND_ADDRESS_NULL **Description:** @@ -608,178 +593,164 @@ Call `Socket::bind(NULL, port)`. **Preconditions:** -1. Network interface and stack are initialized. -2. Network connection is up. +1. Network interface and stack are initialized. +1. Network connection is up. **Test steps:** -1. Create a object by calling `new Socket()`. -2. Call `Socket::open(stack)`. -3. Call `Socket::bind(NULL, );`. -4. Destroy socket. +1. Create an object by calling `new Socket()`. +1. Call `Socket::open(stack)`. +1. Call `Socket::bind(NULL, );`. +1. Destroy the socket. **Expected result:** -`Socket::bind()` should return `NSAPI_ERROR_OK'. - - +`Socket::bind()` returns `NSAPI_ERROR_OK`. ### SOCKET_BIND_ADDRESS_INVALID **Description:** -Call `Socket::bind(address, port)` with and address that is not assigned -to us. +Call `Socket::bind(address, port)` with an address not assigned to you. **Preconditions:** -1. Network interface and stack are initialized. -2. Network connection is up. +1. Network interface and stack are initialized. +1. Network connection is up. **Test steps:** -1. Create a object by calling `new Socket()`. -2. Call `Socket::open(stack)`. -3. Check whether device is IPv4 or IPv6 connected. - 1. For IPv4: Call `Socket::bind("190.2.3.4", );`. - 2. For IPv6: Call `Socket::bind("fe80::ff01", );`. - -4. Destroy socket. +1. Create an object by calling `new Socket()`. +1. Call `Socket::open(stack)`. +1. Check whether the device is IPv4 or IPv6 connected. + 1. For IPv4: Call `Socket::bind("190.2.3.4", );`. + 1. For IPv6: Call `Socket::bind("fe80::ff01", );`. +1. Destroy the socket. **Expected result:** -`Socket::bind()` should return `NSAPI_ERROR_PARAMETER'. - - +`Socket::bind()` returns `NSAPI_ERROR_PARAMETER`. ### SOCKET_BIND_ADDRESS_WRONG_TYPE **Description:** -Call `Socket::bind(SocketAddress)` with and address that is not wrong type for the connection. +Call `Socket::bind(SocketAddress)` with an address that is not the wrong type for the connection. **Preconditions:** -1. Network interface and stack are initialized. -2. Network connection is up. +1. Network interface and stack are initialized. +1. Network connection is up. **Test steps:** -1. Create a object by calling `new Socket()`. -2. Call `Socket::open(stack)`. -3. Check whether device is IPv4 or IPv6 connected. - 1. For IPv4: Create `SocketAddress("fe80::ff01", );`. - 2. For IPv6: Create `SocketAddress("190.2.3.4", );`. - -4. Call `Socket::bind(address);`. -5. Destroy socket. +1. Create a object by calling `new Socket()`. +1. Call `Socket::open(stack)`. +1. Check whether the device is IPv4 or IPv6 connected: + - For IPv4: Create `SocketAddress("fe80::ff01", );`. + - For IPv6: Create `SocketAddress("190.2.3.4", );`. +1. Call `Socket::bind(address);`. +1. Destroy the socket. **Expected result:** -`Socket::bind()` should return `NSAPI_ERROR_PARAMETER'. - - +`Socket::bind()` returns `NSAPI_ERROR_PARAMETER`. ### SOCKET_BIND_ADDRESS **Description:** -Call `Socket::bind(SocketAddress)'. +Call `Socket::bind(SocketAddress)`. **Preconditions:** -1. Network interface and stack are initialized. -2. Network connection is up. +1. Network interface and stack are initialized. +1. Network connection is up. **Test steps:** -1. Create a object by calling `new Socket()`. -2. Call `Socket::open(stack)`. -3. Get address by calling NetworkInterface::get_ip_address(); -4. Create a SocketAddress object using this address and any non-used. - port number. -5. Call `Socket::bind(address);`. -6. Destroy socket. +1. Create an object by calling `new Socket()`. +1. Call `Socket::open(stack)`. +1. Get address by calling `NetworkInterface::get_ip_address();`. +1. Create a SocketAddress object using this address and any unused port number. +1. Call `Socket::bind(address);`. +1. Destroy the socket. **Expected result:** -All calls return `NSAPI_ERROR_OK'. - - +All calls return `NSAPI_ERROR_OK`. ### SOCKET_BIND_UNOPENED **Description:** -Call `Socket::bind()` on socket that has not been opened. +Call `Socket::bind()` on a socket that has not been opened. **Preconditions:** -1. Network interface and stack are initialized. -2. Network connection is up. +1. Network interface and stack are initialized. +1. Network connection is up. **Test steps:** -1. Create a object by calling `new Socket()`. -2. Call `Socket::bind();`. -3. Destroy socket. +1. Create an object by calling `new Socket()`. +1. Call `Socket::bind();`. +1. Destroy the socket. **Expected result:** -NSAPI_ERROR_NO_SOCKET - - +`NSAPI_ERROR_NO_SOCKET` Test cases for UDPSocket class ------------------------------ ### UDPSOCKET_OPEN_DESTRUCT -**Description:** Run SOCKET_OPEN_DESTRUCT for UDPSocket. +**Description:** Run `SOCKET_OPEN_DESTRUCT` for UDPSocket. ### UDPSOCKET_OPEN_LIMIT -**Description:** Run SOCKET_OPEN_LIMIT for UDPSocket. +**Description:** Run `SOCKET_OPEN_LIMIT` for UDPSocket. ### UDPSOCKET_OPEN_TWICE -**Description:** Run SOCKET_OPEN_TWICE for UDPSocket. +**Description:** Run `SOCKET_OPEN_TWICE` for UDPSocket. ### UDPSOCKET_OPEN_CLOSE_REPEAT -**Description:** Run SOCKET_OPEN_CLOSE_REPEAT for UDPSocket. +**Description:** Run `SOCKET_OPEN_CLOSE_REPEAT` for UDPSocket. ### UDPSOCKET_BIND_PORT -**Description:** Run SOCKET_BIND_PORT for UDPSocket. +**Description:** Run `SOCKET_BIND_PORT` for UDPSocket. ### UDPSOCKET_BIND_PORT_FAIL -**Description:** Run SOCKET_BIND_PORT_FAIL for UDPSocket. +**Description:** Run `SOCKET_BIND_PORT_FAIL` for UDPSocket. ### UDPSOCKET_BIND_ADDRESS_PORT -**Description:** Run SOCKET_BIND_ADDRESS_PORT for UDPSocket. +**Description:** Run `SOCKET_BIND_ADDRESS_PORT` for UDPSocket. ### UDPSOCKET_BIND_ADDRESS_NULL -**Description:** Run SOCKET_BIND_ADDRESS_NULL for UDPSocket. +**Description:** Run `SOCKET_BIND_ADDRESS_NULL` for UDPSocket. ### UDPSOCKET_BIND_ADDRESS_INVALID -**Description:** Run SOCKET_BIND_ADDRESS_INVALID for UDPSocket. +**Description:** Run `SOCKET_BIND_ADDRESS_INVALID` for UDPSocket. ### UDPSOCKET_BIND_WRONG_TYPE -**Description:** Run SOCKET_BIND_WRONG_TYPE for UDPSocket. +**Description:** Run `SOCKET_BIND_WRONG_TYPE` for UDPSocket. ### UDPSOCKET_BIND_ADDRESS -**Description:** Run SOCKET_BIND_ADDRESS for UDPSocket. +**Description:** Run `SOCKET_BIND_ADDRESS` for UDPSocket. ### UDPSOCKET_BIND_UNOPENED -**Description:** Run SOCKET_BIND_UNOPENED for UDPSocket. +**Description:** Run `SOCKET_BIND_UNOPENED` for UDPSocket. ### UDPSOCKET_SENDTO_INVALID @@ -789,27 +760,25 @@ Call `UDPSocket::sendto()` with invalid parameters. **Preconditions:** -1. Network interface and stack are initialized. -2. Network connection is up. -3. UDPSocket is open. +1. Network interface and stack are initialized. +1. Network connection is up. +1. UDPSocket is open. **Test steps:** -1. Call `UDPSocket:sendto( NULL, 9, NULL, 0);`. -2. Call `UDPSocket:sendto( "", 9, NULL, 0);`. -3. Call `UDPSocket:sendto( "", 0, NULL, 0);`. -4. Call `UDPSocket:sendto("echo.mbedcloudtesting.com", 9,NULL, 0);`. -5. Call `UDPSocket:sendto("echo.mbedcloudtesting.com", 9, "hello", 5);`. -6. Destroy the socket. +1. Call `UDPSocket:sendto( NULL, 9, NULL, 0);`. +1. Call `UDPSocket:sendto( "", 9, NULL, 0);`. +1. Call `UDPSocket:sendto( "", 0, NULL, 0);`. +1. Call `UDPSocket:sendto("echo.mbedcloudtesting.com", 9,NULL, 0);`. +1. Call `UDPSocket:sendto("echo.mbedcloudtesting.com", 9, "hello", 5);`. +1. Destroy the socket. **Expected result:** -All sendto() calls should return some error code except: - -- step 4 should return 0 -- step 5 should return 5 - +All `sendto()` calls return an error code except: +- Step 4 returns 0. +- Step 5 returns 5. ### UDPSOCKET_SENDTO_REPEAT @@ -819,87 +788,80 @@ Repeatedly send small packets. **Preconditions:** -1. Network interface and stack are initialized. -2. Network connection is up. -3. UDPSocket is open. +1. Network interface and stack are initialized. +1. Network connection is up. +1. UDPSocket is open. **Test steps:** -1. Call `UDPSocket:sendto("echo.mbedcloudtesting.com", 9, "hello", 5);`. -2. Repeat 100 times. -3. Fail if `NSAPI_ERROR_NO_MEMORY` is returned two times in a row,. - Wait 1 second before retry -4. Destroy the socket. +1. Call `UDPSocket:sendto("echo.mbedcloudtesting.com", 9, "hello", 5);`. +1. Repeat 100 times. +1. Fail if `NSAPI_ERROR_NO_MEMORY` is returned two times in a row. +1. Wait 1 second before retrying. +1. Destroy the socket. **Expected result:** -All sendto() calls should return 5. - - +All `sendto()` calls return 5. ### UDPSOCKET_ECHOTEST **Description:** -Repeatedly send packets to echo server and read incoming packets back. -Verify working of different packet sizes. +Repeatedly send packets to echo server and read incoming packets back. Verify different packet sizes work. **Preconditions:** -1. Network interface and stack are initialized. -2. Network connection is up. -3. UDPSocket is open. +1. Network interface and stack are initialized. +1. Network connection is up. +1. UDPSocket is open. **Test steps:** -1. Call `UDPSocket:sendto("echo.mbedcloudtesting.com", 7, , );`. -2. Wait for incomming packet. If timeout happens, retry. - sending&receiving, max 3 times. -3. Verify incomming content was the same that was sent. -4. Repeat 1200 times. -5. Destroy the socket. +1. Call `UDPSocket:sendto("echo.mbedcloudtesting.com", 7, , );`. +1. Wait for incoming packet. + - If timeout happens, retry sending and receiving a maximum of three times. +1. Verify incoming content is the same as the sent content. +1. Repeat 1,200 times. +1. Destroy the socket. **Expected result:** -At least one sendto() call of every size should return the packet size. -Errors returned from recvfrom() calls are tolerated. -Calculate packet loss rate, maximum tolerated packet loss rate is 30%. - - +- At least one `sendto()` call of every size returns the packet size. +- Errors returned from `recvfrom()` calls are tolerated. +- Calculate packet loss rate. The maximum tolerated packet loss rate is 30%. ### UDPSOCKET_ECHOTEST_NONBLOCK **Description:** -Repeatedly send packets to echo server and read incoming packets back. -Verify working of different packet sizes. Use socket in non-blocking -mode +Repeatedly send packets to echo server and read incoming packets back. Verify different packet sizes work. Use Socket in nonblocking +mode. **Preconditions:** -1. Network interface and stack are initialized. -2. Network connection is up. -3. UDPSocket is open. +1. Network interface and stack are initialized. +1. Network connection is up. +1. UDPSocket is open. **Test steps:** -1. Call `UDPSocket::set_blocking(false)`. -2. Register event handler with `UDPSocket::sigio()`. -3. Create another thread that constantly waits signal from sigio() handler, when received try `UDPSocket::recvfrom()`. -4. Call `UDPSocket:sendto("echo.mbedcloudtesting.com", 7, , );`. -5. Wait for incomming packet for one second. If nothing received retry, - max 3 times. -6. Verify incomming content was the same that was sent. -7. Repeat 1200 times. -8. Destroy the socket. +1. Call `UDPSocket::set_blocking(false)`. +1. Register event handler with `UDPSocket::sigio()`. +1. Create another thread that constantly waits for a signal from the `sigio()` handler. +1. When it's received, try `UDPSocket::recvfrom()`. +1. Call `UDPSocket:sendto("echo.mbedcloudtesting.com", 7, , );`. +1. Wait for an incoming packet for one second. + - If nothing is received, retry a maximum of three times. +1. Verify incoming content is the same as sent content. +1. Repeat 1,200 times. +1. Destroy the socket. **Expected result:** -At least one sendto() call of every size should return the packet size. -Errors returned from recvfrom() calls are tolerated. -Calculate packet loss rate, maximum tolerated packet loss rate is 30%. - - +- At least one `sendto()` call of every size returns the packet size. +- Errors returned from `recvfrom()` calls are tolerated. +- Calculate packet loss rate. The maximum tolerated packet loss rate is 30%. ### UDPSOCKET_RECV_TIMEOUT @@ -909,30 +871,26 @@ Test whether timeouts are obeyed in UDPSockets. **Preconditions:** -1. Network interface and stack are initialized. -2. Network connection is up. +1. Network interface and stack are initialized. +1. Network connection is up. **Test steps:** -1. Call `UDPSocket::set_timeout(100)`. -2. Call `UDPSocket::sendto("echo.mbedcloudtesting.com", 7, , 100);`. -3. Repeat 5 times. - 1. Record a time in millisecond precission. - 2. Call `UDPSocket::recvfrom()`. - 3. Record a time in millisecond precission. - -4. Repeat testcase 10 times. +1. Call `UDPSocket::set_timeout(100)`. +1. Call `UDPSocket::sendto("echo.mbedcloudtesting.com", 7, , 100);`. +1. Repeat five times. + 1. Record a time with millisecond precision. + 1. Call `UDPSocket::recvfrom()`. + 1. Record a time with millisecond precision. +1. Repeat the test case 10 times. **Expected result:** -Each `sendto()` calls should return 100. +Each `sendto()` call returns 100. -Within each loop, one `recvfrom()` may return the received packet size -(100). Other calls should return `NSAPI_ERROR_WOULD_BLOCK`. - -When `NSAPI_ERROR_WOULD_BLOCK` is received, check that time consumed is -more that 100 milliseconds but less than 200 milliseconds. +Within each loop, one `recvfrom()` may return the received packet size (100). Other calls return `NSAPI_ERROR_WOULD_BLOCK`. +When `NSAPI_ERROR_WOULD_BLOCK` is received, check that time consumed is more that 100 milliseconds but less than 200 milliseconds. ### UDPSOCKET_SENDTO_TIMEOUT @@ -942,76 +900,74 @@ Test whether timeouts are obeyed in UDPSockets. **Preconditions:** -1. Network interface and stack are initialized. -2. Network connection is up. +1. Network interface and stack are initialized. +1. Network connection is up. **Test steps:** -1. Record time. -2. Call `UDPSocket::sendto("echo.mbedcloudtesting.com", 9, , 100);`. -3. Record time. -4. Call `UDPSocket::set_timeout(1000)`. -5. Call `UDPSocket::sendto("echo.mbedcloudtesting.com", 9, , 100);`. -6. Record time. +1. Record time. +1. Call `UDPSocket::sendto("echo.mbedcloudtesting.com", 9, , 100);`. +1. Record time. +1. Call `UDPSocket::set_timeout(1000)`. +1. Call `UDPSocket::sendto("echo.mbedcloudtesting.com", 9, , 100);`. +1. Record time. **Expected result:** -Each sendto() call should return 100. - -All sendto() calls should return faster than 100 milliseconds because -UDP sending should not block that long. +Each `sendto()` call returns 100. +All `sendto()` calls return faster than 100 milliseconds because UDP sending does not block that long. Test cases for TCPSocket class ------------------------------ ### TCPSOCKET_OPEN_DESTRUCT -**Description:** Run SOCKET_OPEN_DESTRUCT for TCPSocket. +**Description:** Run `SOCKET_OPEN_DESTRUCT` for TCPSocket. ### TCPSOCKET_OPEN_LIMIT -**Description:** Run SOCKET_OPEN_LIMIT for TCPSocket. +**Description:** Run `SOCKET_OPEN_LIMIT` for TCPSocket. ### TCPSOCKET_OPEN_TWICE -**Description:** Run SOCKET_OPEN_TWICE for TCPSocket. +**Description:** Run `SOCKET_OPEN_TWICE` for TCPSocket. ### TCPSOCKET_OPEN_CLOSE_REPEAT -**Description:** Run SOCKET_OPEN_CLOSE_REPEAT for TCPSocket. +**Description:** Run `SOCKET_OPEN_CLOSE_REPEAT` for TCPSocket. ### TCPSOCKET_BIND_PORT -**Description:** Run SOCKET_BIND_PORT for TCPSocket. +**Description:** Run `SOCKET_BIND_PORT` for TCPSocket. ### TCPSOCKET_BIND_PORT_FAIL -**Description:** Run SOCKET_BIND_PORT_FAIL for TCPSocket. +**Description:** Run `SOCKET_BIND_PORT_FAIL` for TCPSocket. ### TCPSOCKET_BIND_ADDRESS_PORT -**Description:** Run SOCKET_BIND_ADDRESS_PORT for TCPSocket. +**Description:** Run `SOCKET_BIND_ADDRESS_PORT` for TCPSocket. ### TCPSOCKET_BIND_ADDRESS_NULL -**Description:** Run SOCKET_BIND_ADDRESS_NULL for TCPSocket. +**Description:** Run `SOCKET_BIND_ADDRESS_NULL` for TCPSocket. ### TCPSOCKET_BIND_ADDRESS_INVALID -**Description:** Run SOCKET_BIND_ADDRESS_INVALID for TCPSocket. +**Description:** Run `SOCKET_BIND_ADDRESS_INVALID` for TCPSocket. ### TCPSOCKET_BIND_WRONG_TYPE -**Description:** Run SOCKET_BIND_WRONG_TYPE for TCPSocket. +**Description:** Run `SOCKET_BIND_WRONG_TYPE` for TCPSocket. ### TCPSOCKET_BIND_ADDRESS -**Description:** Run SOCKET_BIND_ADDRESS for TCPSocket. +**Description:** Run `SOCKET_BIND_ADDRESS` for TCPSocket. ### TCPSOCKET_BIND_UNOPENED -**Description:** Run SOCKET_BIND_UNOPENED for TCPSocket. +**Description:** Run `SOCKET_BIND_UNOPENED` for TCPSocket. ### TCPSOCKET_CONNECT_INVALID @@ -1021,24 +977,21 @@ Call `TCPSocket::connect()` with invalid parameters. **Preconditions:** -1. Network interface and stack are initialized. -2. Network connection is up. -3. TCPSocket is open. +1. Network interface and stack are initialized. +1. Network connection is up. +1. TCPSocket is open. **Test steps:** -1. Call `TCPSocket:connect( NULL, 9);`. -2. Call `TCPSocket:connect( "", 9);`. -3. Call `TCPSocket:connect( "", 0);`. -4. Call `TCPSocket:connect( "echo.mbedcloudtesting.com", 9);`. -5. Destroy the socket. +1. Call `TCPSocket:connect( NULL, 9);`. +1. Call `TCPSocket:connect( "", 9);`. +1. Call `TCPSocket:connect( "", 0);`. +1. Call `TCPSocket:connect( "echo.mbedcloudtesting.com", 9);`. +1. Destroy the socket. **Expected result:** -All connect() calls should return some error code except the number 4 -should return `NSAPI_ERROR_OK`. - - +All `connect()` calls return an error code except the number 4, which returns `NSAPI_ERROR_OK`. ### TCPSOCKET_SEND_REPEAT @@ -1048,92 +1001,83 @@ Repeatedly send small packets. **Preconditions:** -1. Network interface and stack are initialized. -2. Network connection is up. -3. TCPSocket is open. +1. Network interface and stack are initialized. +1. Network connection is up. +1. TCPSocket is open. **Test steps:** -1. Call `TCPSocket::connect("echo.mbedcloudtesting.com", 9);`. -2. Call `TCPSocket::send("hello", 5);`. -3. Repeat 100 times. -4. Destroy the socket. +1. Call `TCPSocket::connect("echo.mbedcloudtesting.com", 9);`. +1. Call `TCPSocket::send("hello", 5);`. +1. Repeat 100 times. +1. Destroy the socket. **Expected result:** -`TCPSocket::connect()` should return `NSAPI_ERROR_OK'. - -All send() calls should return 5. - +`TCPSocket::connect()` returns `NSAPI_ERROR_OK`. +All `send()` calls return 5. ### TCPSOCKET_ECHOTEST **Description:** -Repeatedly send packets to echo server and read incoming packets back. -Verify working of different packet sizes. +Repeatedly send packets to echo server and read incoming packets back. Verify different packet sizes work. **Preconditions:** -1. Network interface and stack are initialized. -2. Network connection is up. -3. TCPSocket is open. +1. Network interface and stack are initialized. +1. Network connection is up. +1. TCPSocket is open. **Test steps:** -1. Call `TCPSocket::connect("echo.mbedcloudtesting.com", 7);`. -2. Call `TCPSocket::send(, );`. - 1. If less than was returned, size = sent bytes. - -3. Call `TCPSocket::recv(buffer, );`. -4. Verify incomming content was the same that was sent. -5. Repeat 1200 times. -6. Destroy the socket. +1. Call `TCPSocket::connect("echo.mbedcloudtesting.com", 7);`. +1. Call `TCPSocket::send(, );`. + 1. If less than was returned, size = sent bytes. +1. Call `TCPSocket::recv(buffer, );`. +1. Verify incoming content is the same as sent content. +1. Repeat 1,200 times. +1. Destroy the socket. **Expected result:** -All send() calls should return the packet size or less. All recv() calls -should return the same sized packet that was send with same content. - -NOTE: This is stream so recv() might return less data than what was -requested. In this case you need to keep calling recv() until all data -that you have sent is returned. +All `send()` calls return the packet size or less. All `recv()` calls return the same sized packet that was sent with same content. +NOTE: This is stream, so `recv()` might return less data than requested. Keep calling `recv()` until all data you have sent is returned. ### TCPSOCKET_ECHOTEST_NONBLOCK **Description:** -Repeatedly send packets to echo server and read incoming packets back. -Verify working of different packet sizes. Use socket in non-blocking -mode +Repeatedly send packets to echo server and read incoming packets back. Verify different packet sizes work. Use Socket in nonblocking +mode. **Preconditions:** -1. Network interface and stack are initialized. -2. Network connection is up. -3. TCPSocket is open. +1. Network interface and stack are initialized. +1. Network connection is up. +1. TCPSocket is open. **Test steps:** -1. Call `TCPSocket::connect("echo.mbedcloudtesting.com", 7);`. -2. Call `TCPSocket::set_blocking(false)`. -3. Register event handler with `TCPSocket::sigio()`. -4. Create another thread that constantly waits signal from `sigio()` handler, when received try `TCPSocket::recv(buf+index, - index)`, where index is the amount of data already received. -5. Call `TCPSocket:send(, );`. - 1. If less than was returned, try immeadiately sending remaining bytes. - 2. If `NSAPI_ERROR_WOULD_BLOCK` is returned, wait for sigio() call to happen. - -6. Wait for incomming packet for one second. -7. Verify incomming content was the same that was sent, set index for receiving thread to zero. -8. Repeat 1200 times. -9. Destroy the socket. +1. Call `TCPSocket::connect("echo.mbedcloudtesting.com", 7);`. +1. Call `TCPSocket::set_blocking(false)`. +1. Register event handler with `TCPSocket::sigio()`. +1. Create another thread that constantly waits for a signal from `sigio()` handler. +1. When it's received, try `TCPSocket::recv(buf+index, - index)`, where index is the amount of data already received. +1. Call `TCPSocket:send(, );`. + 1. If less than is returned, try immediately sending the remaining bytes. + 1. If `NSAPI_ERROR_WOULD_BLOCK` is returned, wait for `sigio()` call to happen. +1. Wait for incoming packet for one second. +1. Verify incoming content is the same as sent content. +1. Set index for receiving thread to zero. +1. Repeat 1,200 times. +1. Destroy the socket. **Expected result:** -All send() calls should return the packet size or less. All recv() calls -should return `NSAPI_ERROR_WOULD_BLOCK` or packet size that is equal or +All `send()` calls return the packet size or less. All `recv()` calls return `NSAPI_ERROR_WOULD_BLOCK` or a packet size equal to or less than what has been sent. ### TCPSOCKET_RECV_TIMEOUT @@ -1144,527 +1088,513 @@ Test whether timeouts are obeyed in TCPSockets. **Preconditions:** -1. Network interface and stack are initialized. -2. Network connection is up. -3. TCPSocket is open. +1. Network interface and stack are initialized. +1. Network connection is up. +1. TCPSocket is open. **Test steps:** -1. Call `TCPSocket::connect("echo.mbedcloudtesting.com", 7);`. -2. Call `TCPSocket::set_timeout(100);`. -3. Call `TCPSocket::send(;, 100);`. -4. Repeat 5 times. - 1. Record a time in millisecond precission. - 2. Call `TCPSocket::recv()`. - 3. Record a time in millisecond precission. - -5. Repeat testcase 10 times. +1. Call `TCPSocket::connect("echo.mbedcloudtesting.com", 7);`. +1. Call `TCPSocket::set_timeout(100);`. +1. Call `TCPSocket::send(;, 100);`. +1. Repeat 5 times. + 1. Record a time with millisecond precision. + 1. Call `TCPSocket::recv()`. + 1. Record a time with millisecond precision. +1. Repeat the test case 10 times. **Expected result:** -Each send() call should return 100. - -Within each loop, one recv() may return the received packet size (100). -Other calls should return `NSAPI_ERROR_WOULD_BLOCK`. +Each `send()` call returns 100. -When `NSAPI_ERROR_WOULD_BLOCK` is received, check that time consumed is -more that 100 milliseconds but less than 200 milliseconds. +Within each loop, one `recv()` may return the received packet size (100). Other calls return `NSAPI_ERROR_WOULD_BLOCK`. +When `NSAPI_ERROR_WOULD_BLOCK` is received, check the time consumed is more that 100 milliseconds but less than 200 milliseconds. ### TCPSOCKET_SEND_TIMEOUT **Description:** -Repeatedly send small packets in a given time limit +Repeatedly send small packets in a given time limit. **Preconditions:** -1. Network interface and stack are initialized. -2. Network connection is up. -3. TCPSocket is open. +1. Network interface and stack are initialized. +1. Network connection is up. +1. TCPSocket is open. **Test steps:** -1. Call `TCPSocket:connect("echo.mbedcloudtesting.com", 9);`. -3. Call `TCPSocket:set_blocking(false);`. -3. Call `TCPSocket:send("hello", 5);`. -4. Repeat 10 times. -5. Destroy the socket. +1. Call `TCPSocket:connect("echo.mbedcloudtesting.com", 9);`. +1. Call `TCPSocket:set_blocking(false);`. +1. Call `TCPSocket:send("hello", 5);`. +1. Repeat 10 times. +1. Destroy the socket. **Expected result:** -`TCPSocket::connect()` should return `NSAPI_ERROR_OK'. - -All send() calls should return in less than 800 milliseconds +`TCPSocket::connect()` return `NSAPI_ERROR_OK`. +All `send()` calls return in less than 800 milliseconds. ### TCPSOCKET_ENDPOINT_CLOSE **Description:** -Test whether we tolerate endpoint closing the connection. +Test whether you tolerate an endpoint closing the connection. **Preconditions:** -1. Network interface and stack are initialized. -2. Network connection is up. -3. TCPSocket is open. +1. Network interface and stack are initialized. +1. Network connection is up. +1. TCPSocket is open. **Test steps:** -1. Call `TCPSocket::connect("echo.mbedcloudtesting.com", 13);`. -2. Call `TCPSocket::recv(, 30);`. -3. Repeat until recv() returns 0. -4. Call `TCPSocket::close();`. -5. Delete socket. +1. Call `TCPSocket::connect("echo.mbedcloudtesting.com", 13);`. +1. Call `TCPSocket::recv(, 30);`. +1. Repeat until `recv()` returns 0. +1. Call `TCPSocket::close();`. +1. Delete the socket. **Expected result:** -Connect should return `NSAPI_ERROR_OK`. -First recv() should return more that zero. Something between 10 and 30 bytes (datetime string) +Connect returns `NSAPI_ERROR_OK`. -Second recv() should return zero because endpoint closed the connection. -close() should return `NSAPI_ERROR_OK'. +The first `recv()` returns more that zero. Something between 10 and 30 bytes (datetime string). + +The second `recv()` returns zero because the endpoint closed the connection. `close()` returns `NSAPI_ERROR_OK`. ### TCPSOCKET_SETSOCKOPT_KEEPALIVE_VALID **Description:** -Test we are able to request setting valid TCP keepalive values +Test you can request setting valid TCP keepalive values. **Preconditions:** -1. Network interface and stack are initialized. -2. Network connection is up. +1. Network interface and stack are initialized. +1. Network connection is up. **Test steps:** -1. Call `TCPSocket::setsockopt(keepalive, [0,1 or 7200]);`. -2. Call `TCPSocket::connect("echo.mbedcloudtesting.com", 9);`. -3. Call `TCPSocket::getsockopt(keepalive);`. +1. Call `TCPSocket::setsockopt(keepalive, [0,1 or 7200]);`. +1. Call `TCPSocket::connect("echo.mbedcloudtesting.com", 9);`. +1. Call `TCPSocket::getsockopt(keepalive);`. **Postconditions:** -1. Call `TCPSocket::close();`. -2. Delete socket. +1. Call `TCPSocket::close();`. +1. Delete the socket. **Expected result:** -`TCPSocket::getsockopt(keepalive)` returns same value as was set with `TCPSocket::setsockopt()` or `NSAPI_ERROR_UNSUPPORTED'. +`TCPSocket::getsockopt(keepalive)` returns the same value as that set with `TCPSocket::setsockopt()` or `NSAPI_ERROR_UNSUPPORTED`. Test cases for TLSSocket class ------------------------------ ### TLSSOCKET_OPEN_DESTRUCT -**Description:** Run SOCKET_OPEN_DESTRUCT for TLSSocket. +**Description:** Run `SOCKET_OPEN_DESTRUCT` for TLSSocket. ### TLSSOCKET_OPEN_LIMIT -**Description:** Run SOCKET_OPEN_LIMIT for TLSSocket. +**Description:** Run `SOCKET_OPEN_LIMIT` for TLSSocket. ### TLSSOCKET_OPEN_TWICE -**Description:** Run SOCKET_OPEN_TWICE for TLSSocket. +**Description:** Run `SOCKET_OPEN_TWICE` for TLSSocket. ### TLSSOCKET_CONNECT_INVALID -**Description:** Run SOCKET_CONNECT_INVALID for TLSSocket. +**Description:** Run `SOCKET_CONNECT_INVALID` for TLSSocket. ### TLSSOCKET_HANDSHAKE_INVALID **Description:** -Execute TLS handshake by calling `TLSSocket::connect()` - server must not match to the certificate used by to os.mbed.com +Execute the TLS handshake by calling `TLSSocket::connect()`. The server must not match the certificate used by os.mbed.com. **Preconditions:** -1. Network interface and stack are initialized. -2. Network connection is up. +1. Network interface and stack are initialized. +1. Network connection is up. **Test steps:** -1. Create TLSSocket. -2. Call `TLSSocket::open()`. -3. Call `TLSSocket::connect("os.mbed.com", 2009)`. -4. Call `TLSSocket::close()`. +1. Create TLSSocket. +1. Call `TLSSocket::open()`. +1. Call `TLSSocket::connect("os.mbed.com", 2009)`. +1. Call `TLSSocket::close()`. **Expected result:** -TLSSocket::connect must return an error +`TLSSocket::connect` must return an error. ### TLSSOCKET_SEND_CLOSED **Description:** -Make a HTTP request to a closed socket. +Make an HTTP request to a closed socket. **Preconditions:** -1. Network interface and stack are initialized. -2. Network connection is up. +1. Network interface and stack are initialized. +1. Network connection is up. **Test steps:** -1. Create TLSSocket. -2. Call `TLSSocket::open()`. -3. Call `TLSSocket::connect("echo.mbedcloudtesting.com", 2007)`. -4. Call `TLSSocket::close()`. -5. Call `TLSSocket::send("12345", 5)`. +1. Create TLSSocket. +1. Call `TLSSocket::open()`. +1. Call `TLSSocket::connect("echo.mbedcloudtesting.com", 2007)`. +1. Call `TLSSocket::close()`. +1. Call `TLSSocket::send("12345", 5)`. **Expected result:** -TLSSocket::send must return an error +`TLSSocket::send` must return an error. ### TLSSOCKET_SEND_REPEAT -**Description:** Run SOCKET_SEND_REPEAT for TLSSOCKET by using port number 2009. +**Description:** Run `SOCKET_SEND_REPEATÂ` for TLSSOCKET by using port number 2009. ### TLSSOCKET_SEND_TIMEOUT -**Description:** Run SOCKET_SEND_TIMEOUT for TLSSOCKET by using port number 2009. +**Description:** Run `SOCKET_SEND_TIMEOUTÂ` for TLSSOCKET by using port number 2009. ### TLSSOCKET_SEND_UNCONNECTED **Description:** -Make a HTTP request to an unconnected socket. +Make an HTTP request to an unconnected socket. **Preconditions:** -1. Network interface and stack are initialized. -2. Network connection is up. +1. Network interface and stack are initialized. +1. Network connection is up. **Test steps:** -1. Create TLSSocket. -2. Call `TLSSocket::open()`. -3. Call `TLSSocket::send("12345", 5)`. -4. Call `TLSSocket::connect("echo.mbedcloudtesting.com", 2007)`. +1. Create TLSSocket. +1. Call `TLSSocket::open()`. +1. Call `TLSSocket::send("12345", 5)`. +1. Call `TLSSocket::connect("echo.mbedcloudtesting.com", 2007)`. **Expected result:** -TLSSocket::send must return an error +`TLSSocket::send` must return an error. ### TLSSOCKET_ECHOTEST -**Description:** Run SOCKET_ECHOTEST for TLSSOCKET by using port number 2007. +**Description:** Run `SOCKET_ECHOTESTÂ` for TLSSOCKET by using port number 2007. ### TLSSOCKET_ECHOTEST_NONBLOCK -**Description:** Run SOCKET_ECHOTEST_NONBLOCK for TLSSOCKET by using port number 2007. +**Description:** Run `SOCKET_ECHOTEST_NONBLOCKÂ` for TLSSOCKET by using port number 2007. ### TLSSOCKET_ENDPOINT_CLOSE -**Description:** Run SOCKET_ENDPOINT_CLOSE for TLSSOCKET by using port number 2013. +**Description:** Run `SOCKET_ENDPOINT_CLOSE` for TLSSOCKET by using port number 2013. ### TLSSOCKET_NO_CERT **Description:** -Verify that TLS Socket fails to connect without certificate. +Verify TLS Socket fails to connect without a certificate. **Preconditions:** -1. Network interface and stack are initialized. -2. Network connection is up. +1. Network interface and stack are initialized. +1. Network connection is up. **Test steps:** -1. Create TLSSocket, without adding a default certificate. -2. Call `TLSSocket::open()`. -3. Call `TLSSocket::connect("echo.mbedcloudtesting.com", 2009)`. +1. Create TLSSocket, without adding a default certificate. +1. Call `TLSSocket::open()`. +1. Call `TLSSocket::connect("echo.mbedcloudtesting.com", 2009)`. **Expected result:** -TLSSocket::connect must return an error if the certificate is not present. +`TLSSocket::connect` must return an error if the certificate is not present. ### TLSSOCKET_RECV_TIMEOUT **Description:** -Run TCPSOCKET_RECV_TIMEOUT for TLSSOCKET by using port number 2007. +Run `TCPSOCKET_RECV_TIMEOUTÂ` for TLSSOCKET by using port number 2007. ### TLSSOCKET_SIMULTANEOUS_TEST **Description:** -Simultaneously send packets to echo server on two opened sockets and read incoming packets back. Verify working of two TLS sockets open and operate simultaneously. +Simultaneously send packets to echo server on two opened sockets and read incoming packets back. Verify TLS sockets open and operate simultaneously. **Preconditions:** -1. Network interface and stack are initialized. -2. Network connection is up. -3. TLSSockets are open and one additional thread has been created. -4. Both threads get their own socket instance. +1. Network interface and stack are initialized. +1. Network connection is up. +1. TLSSockets are open and one additional thread has been created. +1. Both threads get their own socket instance. **Test steps:** -1. On main thread: - 1. Call `TLSSocket::connect("echo.mbedcloudtesting.com", 2007);`. - 2. Call `TLSSocket::send(, );`. - 1. If less than was returned, size = sent bytes. - - 3. `Call TLSSocket::recv(buffer, );`. - 4. Verify incomming content was the same that was sent. - 5. Repeat 100 times. - -2. Simultaneously with the earlier step do on the additional thread: - 1. Call `TLSSocket::connect("echo.mbedcloudtesting.com", 2007);`. - 2. Call `TLSSocket::send(, );'. - 1. If less than was returned, size = sent bytes. - - 3. Call `TLSSocket::recv(buffer, );`. - 4. Verify incomming content was the same that was sent. - 5. Repeat 100 times. - -3. Wait for end additional thread. -4. Close and destroy the sockets. +1. (Simultaneously with step 2), on the main thread: + 1. Call `TLSSocket::connect("echo.mbedcloudtesting.com", 2007);`. + 1. Call `TLSSocket::send(, );`. + - If less than is returned, size = sent bytes. + 1. Call `TLSSocket::recv(buffer, );`. + 1. Verify incoming content is the same as sent content. + 1. Repeat 100 times. +1. (Simultaneously with step 1), on the additional thread: + 1. Call `TLSSocket::connect("echo.mbedcloudtesting.com", 2007);`. + 1. Call `TLSSocket::send(, );'. + - If less than is returned, size = sent bytes. + 1. Call `TLSSocket::recv(buffer, );`. + 1. Verify incoming content is the same as sent content. + 1. Repeat 100 times. +1. Wait for the additional thread to end. +1. Close and destroy the sockets. **Expected result:** -All send() calls should return the packet size or less. All recv() calls on main thread should return the same sized packet that was send with same content. All recv() calls on additional thread should return the valid daytime string .  +All `send()` calls return the packet size or less. All `recv()` calls on the main thread return the same sized packet that was sent with the same content. All `recv()` calls on the additional thread return the valid daytime string. Performance tests ----------------- - ### UDPSOCKET_ECHOTEST_BURST **Description:** -Send burst of packets to echo server and read incoming packets back. +Send a burst of packets to the echo server and read incoming packets back. **Preconditions:** -1. Network interface and stack are initialized. -2. Network connection is up. -3. UDPSocket is open. +1. Network interface and stack are initialized. +1. Network connection is up. +1. UDPSocket is open. **Test steps:** -1. Call `UDPSocket:sendto("echo.mbedcloudtesting.com", 7, , 100);`. -2. Call `UDPSocket:sendto("echo.mbedcloudtesting.com", 7, , 200);`. -3. Call `UDPSocket:sendto("echo.mbedcloudtesting.com", 7, , 300);`. -4. Call `UDPSocket:sendto("echo.mbedcloudtesting.com", 7, , 120);`. -5. Call `UDPSocket:sendto("echo.mbedcloudtesting.com", 7, , 500);`. -6. Wait for incomming packets for five second. -7. Verify incomming content was the same that was sent. Allow packet reordering. -8. Repeat 100 times. -9. Destroy the socket. +1. Call `UDPSocket:sendto("echo.mbedcloudtesting.com", 7, , 100);`. +1. Call `UDPSocket:sendto("echo.mbedcloudtesting.com", 7, , 200);`. +1. Call `UDPSocket:sendto("echo.mbedcloudtesting.com", 7, , 300);`. +1. Call `UDPSocket:sendto("echo.mbedcloudtesting.com", 7, , 120);`. +1. Call `UDPSocket:sendto("echo.mbedcloudtesting.com", 7, , 500);`. +1. Wait for incoming packets for five seconds. +1. Verify incoming content is the same as sent content. +1. Allow packet reordering. +1. Repeat 100 times. +1. Destroy the socket. **Expected result:** -All sendto() calls should return the packet size. +All `sendto()` calls return the packet size. -All recvfrom() calls should return the same sized packet that was send with same content. Allow packet reordering. +All `recvfrom()` calls return the same sized packet that was sent with same content. Allow packet reordering. -Calculate packet loss rate, maximum tolerated packet loss rate is 30%. - -Calculate number of succesfull rounds, it should be higher than 70. +Calculate packet loss rate. The maximum tolerated packet loss rate is 30%. +The number of succesful rounds is higher than 70. ### UDPSOCKET_ECHOTEST_BURST_NONBLOCK **Description:** -Send burst of packets to echo server and read incoming packets back. Use socket in non-blocking mode. +Send a burst of packets to the echo server and read incoming packets back. Use Socket in nonblocking mode. **Preconditions:** -1. Network interface and stack are initialized. -2. Network connection is up. -3. UDPSocket is open. +1. Network interface and stack are initialized. +1. Network connection is up. +1. UDPSocket is open. **Test steps:** -1. Call `UDPSocket::set_blocking(false)`. -2. Register event handler with `UDPSocket::sigio()`. -3. Create another thread that constantly waits signal from sigio() handler, when received try `UDPSocket::recvfrom()`. -4. Call `UDPSocket:sendto("echo.mbedcloudtesting.com", 7, , 100);`. -5. Call `UDPSocket:sendto("echo.mbedcloudtesting.com", 7, , 200);`. -6. Call `UDPSocket:sendto("echo.mbedcloudtesting.com", 7, , 300);`. -7. Call `UDPSocket:sendto("echo.mbedcloudtesting.com", 7, , 120);`. -8. Call `UDPSocket:sendto("echo.mbedcloudtesting.com", 7, , 500);`. -9. Wait for incomming packets for five second. -10. Verify incomming content was the same that was sent. Allow packet reordering. -11. Repeat 100 times. -12. Destroy the socket. +1. Call `UDPSocket::set_blocking(false)`. +1. Register event handler with `UDPSocket::sigio()`. +1. Create another thread that constantly waits signal from sigio() handler. +1. When received, try `UDPSocket::recvfrom()`. +1. Call `UDPSocket:sendto("echo.mbedcloudtesting.com", 7, , 100);`. +1. Call `UDPSocket:sendto("echo.mbedcloudtesting.com", 7, , 200);`. +1. Call `UDPSocket:sendto("echo.mbedcloudtesting.com", 7, , 300);`. +1. Call `UDPSocket:sendto("echo.mbedcloudtesting.com", 7, , 120);`. +1. Call `UDPSocket:sendto("echo.mbedcloudtesting.com", 7, , 500);`. +1. Wait for incoming packets for five seconds. +1. Verify incoming content is the same as sent content. +1. Allow packet reordering. +1. Repeat 100 times. +1. Destroy the socket. **Expected result:** -All sendto() calls should return the packet size. - -All recvfrom() calls should return the same sized packet that was send with same content. Allow packet reordering. - -Calculate packet loss rate, maximum tolerated packet loss rate is 30%. +All `sendto()` calls return the packet size. -Calculate number of succesfull rounds, it should be higher than 70. +All `recvfrom()` calls return the same sized packet that was sent with the same content. Allow packet reordering. +Calculate packet loss rate. The maximum tolerated packet loss rate is 30%. +The number of succesful rounds is higher than 70. ### TCPSOCKET_ECHOTEST_BURST **Description:** -Send burst of packets to echo server and read incoming packets back. +Send a burst of packets to the echo server and read incoming packets back. **Preconditions:** -1. Network interface and stack are initialized. -2. Network connection is up. -3. TCPSocket is open. +1. Network interface and stack are initialized. +1. Network connection is up. +1. TCPSocket is open. **Test steps:** -1. Call `TCPSocket::connect("echo.mbedcloudtesting.com", 7);`. -2. Call `TCPSocket::send(, 100);`. -3. Call `TCPSocket::send(, 200);`. -4. Call `TCPSocket::send(, 300);`. -5. Call `TCPSocket::send(, 120);`. -6. Call `TCPSocket::send(, 500);`. -7. Call `TCPSocket::recv(buf, 1220)`. -8. Verify incomming content was the same that was sent. -9. Repeat 100 times. -10. Destroy the socket. +1. Call `TCPSocket::connect("echo.mbedcloudtesting.com", 7);`. +1. Call `TCPSocket::send(, 100);`. +1. Call `TCPSocket::send(, 200);`. +1. Call `TCPSocket::send(, 300);`. +1. Call `TCPSocket::send(, 120);`. +1. Call `TCPSocket::send(, 500);`. +1. Call `TCPSocket::recv(buf, 1220)`. +1. Verify incoming content is the same as sent content. +1. Repeat 100 times. +1. Destroy the socket. **Expected result:** -All send() calls should return the packet size. +All `send()` calls return the packet size. -NOTE: This is stream so recv() might return less data than what was requested. In this case you need to keep calling recv() with remaining size until all data that you have sent is returned. - -Consecutive calls to recv() should return all the data that has been send. Total amount of returned must match 1220. +NOTE: This is stream, so `recv()` might return less data than requested. Keep calling `recv()` with the remaining size until all data you have sent is returned. +Consecutive calls to `recv()` return all the data that has been sent. The total amount of returned data must match 1220. ### TCPSOCKET_ECHOTEST_BURST_NONBLOCK **Description:** -Send burst of packets to echo server and read incoming packets back. Use socket in non-blocking mode. +Send a burst of packets to the echo server and read incoming packets back. Use Socket in nonblocking mode. **Preconditions:** -1. Network interface and stack are initialized. -2. Network connection is up. -3. TCPSocket is open. +1. Network interface and stack are initialized. +1. Network connection is up. +1. TCPSocket is open. **Test steps:** -1. Register event handler with `TCPSocket::sigio()`. -2. Call `TCPSocket::connect("echo.mbedcloudtesting.com", 7);`. -3. Call `TCPSocket::set_blocking(false)`. -4. Create another thread that constantly waits signal from sigio() handler, when received try `TCPSocket::recv()`. -5. For randomly generated packets, sized 100, 200, 300, 120 and 500 do - 1. Call `TCPSocket::send(packet, size);`. - 2. If less than size is sent, repeat with remaining. - 3. If `NSAPI_ERROR_WOULD_BLOCK` returned, wait for next sigio(). - -6. Wait for incomming packets for five second. -7. Verify incomming content was the same that was sent. Allow recv() to return smaller piezes. -8. Repeat 100 times. -9. Destroy the socket. +1. Register event handler with `TCPSocket::sigio()`. +1. Call `TCPSocket::connect("echo.mbedcloudtesting.com", 7);`. +1. Call `TCPSocket::set_blocking(false)`. +1. Create another thread that constantly waits for a signal from `sigio()` handler. +1. When it's received, try `TCPSocket::recv()`. +1. For randomly generated packets sized 100, 200, 300, 120 and 500: + 1. Call `TCPSocket::send(packet, size);`. + 1. If less than size is sent, repeat with remaining. + 1. If `NSAPI_ERROR_WOULD_BLOCK` returned, wait for next `sigio()`. +1. Wait for incoming packets for five seconds. +1. Verify incoming content is the same as sent content. +1. Allow `recv()` to return smaller pieces. +1. Repeat 100 times. +1. Destroy the socket. **Expected result:** -All send() calls should return `NSAPI_ERROR_WOULD_BLOCK` or size which is equal or less than requested. +All `send()` calls return `NSAPI_ERROR_WOULD_BLOCK` or a size less than or equal to what has been requested. -All recv() calls should return value that is less or equal to what have been sent. With consecutive calls, size should match. - -When recv() returns `NSAPI_ERROR_WOULD_BLOCK` wait for next sigio() event. No other error codes allowed. +All `recv()` calls return a value less than or equal to what has been sent. With consecutive calls, the sizes should match. +When `recv()` returns `NSAPI_ERROR_WOULD_BLOCK`, wait for the next `sigio()` event. No other error codes are allowed. ### TCPSOCKET_RECV_100K **Description:** -Download 100kB of data +Download 100kB of data. **Preconditions:** -1. Network interface and stack are initialized. -2. Network connection is up. -3. TCPSocket is open. +1. Network interface and stack are initialized. +1. Network connection is up. +1. TCPSocket is open. **Test steps:** -1. Call `TCPSocket::connect("echo.mbedcloudtesting.com", 19);`. -2. Call `TCPSocket::recv(buffer, 100);`. -3. Verify input according to known pattern. -4. Loop until 100kB of data received. -5. Close socket. +1. Call `TCPSocket::connect("echo.mbedcloudtesting.com", 19);`. +1. Call `TCPSocket::recv(buffer, 100);`. +1. Verify input according to a known pattern. +1. Loop until 100kB of data received. +1. Close socket. **Expected result:** -Each recv() call should return equal or less than 100 bytes of data. No -errors should be returned. +Each `recv()` call returns 100 bytes of data or fewer. No errors are returned. -Measure time taken for receiving, report speed +Measure time taken for receiving and report speed. ### TCPSOCKET_RECV_100K_NONBLOCK **Description:** -Download 100kB of data +Download 100kB of data. **Preconditions:** -1. Network interface and stack are initialized. -2. Network connection is up. -3. TCPSocket is open. +1. Network interface and stack are initialized. +1. Network connection is up. +1. TCPSocket is open. **Test steps:** -1. Call `TCPSocket::connect("echo.mbedcloudtesting.com", 19);`. -2. Call `TCPSocket::set_blocking(false)`. -3. Create another thread that constantly waits signal from sigio() handler, when received try `TCPSocket::recv()`. - 1. Call `TCPSocket::recv(buffer, 100);`. - 2. Verify input according to known pattern. - -4. Wait until 100kB of data received. -5. Close socket. +1. Call `TCPSocket::connect("echo.mbedcloudtesting.com", 19);`. +1. Call `TCPSocket::set_blocking(false)`. +1. Create another thread that constantly waits for a signal from `sigio()` handler. +1. When it's received, try `TCPSocket::recv()`. + 1. Call `TCPSocket::recv(buffer, 100);`. + 1. Verify input according to a known pattern. +1. Wait until 100kB of data received. +1. Close socket. **Expected result:** -Each recv() call should return equal or less than 100 bytes of data or `NSAPI_ERROR_WOULD_BLOCK` in which case thread should wait for another sigio(). No errors should be returned. +Each `recv()` call returns 100 bytes of data or less or `NSAPI_ERROR_WOULD_BLOCK`, in which case thread waits for another `sigio()`. No errors are returned. -Measure time taken for receiving, report speed. +Measure time taken for receiving and report speed. ### TCPSOCKET_THREAD_PER_SOCKET_SAFETY **Description:** -Run two threads which both exercise the underlying stack and driver through a dedicated socket. +Run two threads that both exercise the underlying stack and driver through a dedicated socket. **Preconditions:** -1. Network interface and stack are initialized. -2. Network connection is up. -3. 2 TCPSockets are open and one additional thread has been created. -4. Both threads get their own socket instance. +1. Network interface and stack are initialized. +1. Network connection is up. +1. Two TCPSockets are open, and one additional thread has been created. +1. Both threads get their own socket instance. **Test steps:** -1. Call `TCPSocket::connect("echo.mbedcloudtesting.com", 7)` in both threads - in the main thread executing the test case and on the additional one. -2. On main thread - 1. For randomly generated packets, sized 1001, 901, 801,...,101,1 do - 1. Call `TCPSocket::send(packet, size);`. - 2. Verify incoming content was the same that was sent. - Allow recv() to return smaller pieces. - -3. Simultaneously with the earlier step do on the additional thread - 1. For randomly generated packets, sized 10 do - 1. Call `TCPSocket::send(packet, size);`. - 2. Verify incomming content was the same that was sent. - Allow recv() to return smaller piezes. - 3. Stop the thread if inconsistensies were found and report it to main thread. - -4. Kill the additional thread. -5. Close and destroy the sockets. +1. Call `TCPSocket::connect("echo.mbedcloudtesting.com", 7)` in both threads - in the main thread executing the test case and on the additional one. + - (Simultaneously with the next step) on the main thread: + 1. For randomly generated packets, sized 1001, 901, 801,...,101,1 do + 1. Call `TCPSocket::send(packet, size);`. + 1. Verify incoming content was the same that was sent. + 1. Allow `recv()` to return smaller pieces. + - (Simultaneously with the earlier step) on the additional thread: + 1. For randomly generated packets, sized 10: + 1. Call `TCPSocket::send(packet, size);`. + 1. Verify incoming content is the same as sent content. + 1. Allow `recv()` to return smaller pieces. + 1. Stop the thread if inconsistencies are found, and report it to main thread. +1. Kill the additional thread. +1. Close and destroy the sockets. **Expected result:** -Echo server returns data to both threads and received data matches to send data. The additional thread isn't stopped prematurely. +The echo server returns data to both threads and received data matches to send data. The additional thread isn't stopped prematurely. Test cases for DNS class --------------------------- @@ -1677,13 +1607,13 @@ Verify the basic functionality of asynchronous DNS. Call `NetworkInterface::geth **Preconditions:** -1. Network interface is initialized. -2. Network connection is up. +1. Network interface is initialized. +1. Network connection is up. **Test steps:** -1. Call `gethostbyname_async()` with a valid host name and a callback. -2. Verify that callback is called with correct parameters. +1. Call `gethostbyname_async()` with a valid host name and a callback. +1. Verify the callback is called with correct parameters. **Expected result:** @@ -1693,201 +1623,201 @@ Callback is called with `NSAPI_ERROR_OK` and IP address. **Description:** -Verify that simultaneous asynchronous DNS queries work correctly. Call `NetworkInterface::gethostbyname_async()` in a row 6 times with a different host names. Wait for all requests to complete, and verify the result. Cache should not contain host names used in asynchronous request. +Verify simultaneous asynchronous DNS queries work correctly. Call `NetworkInterface::gethostbyname_async()` 6 times with different host names. Wait for all requests to complete, and verify the result. The cache does not contain host names used in asynchronous request. **Preconditions:** -1. Network interface is initialized. -2. Network connection is up. +1. Network interface is initialized. +1. Network connection is up. **Test steps:** -1. Call `gethostbyname_async()` in a row 6 times with a different host names. Host names shall not be found from cache. -2. Verify that last `gethostbyname_async()` operation is rejected because there is room only for 5 simultaneous operations. -3. Verify that callback is called with correct parameters 5 times. +1. Call `gethostbyname_async()` 6 times with different host names. Host names are not found from the cache. +1. Verify the last `gethostbyname_async()` operation is rejected because there is room only for five simultaneous operations. +1. Verify the callback is called with correct parameters five times. **Expected result:** -Sixth `gethostbyname_async()` is rejected. Callback is called with `NSAPI_ERROR_OK` and IP address 5 times. +The sixth `gethostbyname_async()` is rejected. Callback is called with `NSAPI_ERROR_OK` and IP address five times. ### ASYNCHRONOUS_DNS_SIMULTANEOUS_CACHE **Description:** -Verify that the caching of DNS results works correctly with simultaneous asynchronous DNS queries. Call `NetworkInterface::gethostbyname_async()` in a row 6 times with a different host names. Wait for all requests to complete and verify result. Cache shall contain at least one host name used in asynchronous request. You can achieve this, for example, by running test "Asynchronous DNS simultaneous" before this test and using same host names in this run. +Verify the caching of DNS results works correctly with simultaneous asynchronous DNS queries. Call `NetworkInterface::gethostbyname_async()` six times with different host names. Wait for all requests to complete, and verify the result. The cache contains at least one host name used in asynchronous request. You can achieve this, for example, by running the "Asynchronous DNS simultaneous" test before this test and using the same host names in this run. **Preconditions:** -1. Network interface is initialized. -2. Network connection is up. +1. Network interface is initialized. +1. Network connection is up. **Test steps:** -1. Call `gethostbyname_async()` in a row 6 times with a different host names. At least one host name shall be found from cache. -2. Verify that callback is called with correct parameters 6 times. +1. Call `gethostbyname_async()` six times with different host names. At least one host name is found from cache. +1. Verify that callback is called with correct parameters six times. **Expected result:** -Callback is called with `NSAPI_ERROR_OK` and IP address 6 times. +Callback is called with `NSAPI_ERROR_OK` and IP address six times. ### ASYNCHRONOUS_DNS_CACHE **Description:** -Verify that the caching of DNS results works correctly. Call `NetworkInterface::gethostbyname_async()` 5 times with the same host name and verify result after each request. For first request, cache shall not contain the host name. Verify that first request completes slower than the requests made after it (where the response is found from cache). +Verify the caching of DNS results works correctly. Call `NetworkInterface::gethostbyname_async()` five times with the same host name and verify the result after each request. For the first request, the cache does not contain the host name. Verify the first request completes more slowly than the requests made after it (where the response is found from cache). **Preconditions:** -1. Network interface is initialized. -2. Network connection is up. +1. Network interface is initialized. +1. Network connection is up. **Test steps:** -1. Call `gethostbyname_async()` with a host name. For first request, host name shall not be found from cache. -2. Verify that callback is called with correct parameters. -3. Repeat the sequence 4 times using the same host name. -4. For each request, calculate how long time it takes for DNS query to complete. +1. Call `gethostbyname_async()` with a host name. For the first request, the host name is not found from cache. +1. Verify the callback is called with correct parameters. +1. Repeat the sequence four times using the same host name. +1. For each request, calculate how long it takes for the DNS query to complete. **Expected result:** -Callback is called with `NSAPI_ERROR_OK` and IP address 5 times. First request shall complete before the requests made after it (where the response is found from cache). +The callback is called with `NSAPI_ERROR_OK` and IP address five times. The first request is complete before the requests made after it (where the response is found from cache). ### ASYNCHRONOUS_DNS_NON_ASYNC_AND_ASYNC **Description:** -Verify synchronous (in other words, blocking) DNS queries and asynchronous (in other words, non-blocking) queries work at the same time. Call `NetworkInterface::gethostbyname_async()`. Right after that, make 6 synchronous `NetworkInterface::gethostbyname()` calls with different host names. +Verify synchronous (in other words, blocking) DNS queries and asynchronous (in other words, nonblocking) queries work at the same time. Call `NetworkInterface::gethostbyname_async()`. Right after that, make six synchronous `NetworkInterface::gethostbyname()` calls with different host names. **Preconditions:** -1. Network interface is initialized. -2. Network connection is up. +1. Network interface is initialized. +1. Network connection is up. **Test steps:** -1. Call `gethostbyname_async()` with a host name. Host name shall not be found from cache. -2. Call `gethostbyname()` 6 times with a different host names (none of the names shall be same as in step 1). -3. Verify that each `gethostbyname()` returns success. -4. Verify that the asynchronous callback is called with correct parameters. +1. Call `gethostbyname_async()` with a host name. The host name is not found from cache. +1. Call `gethostbyname()` six times with different host names (none of the names are the same as that in step 1). +1. Verify each `gethostbyname()` returns success. +1. Verify the asynchronous callback is called with correct parameters. **Expected result:** -All operations shall return `NSAPI_ERROR_OK` and IP address. +All operations return `NSAPI_ERROR_OK` and IP address. ### ASYNCHRONOUS_DNS_CANCEL **Description:** -Verify that asynchronous DNS query cancel works correctly. Call `NetworkInterface::gethostbyname_async()` in a row 6 times with a different host names. Cache shall contain 3 host names used in requests. This can be achieved e.g. by running test "Asynchronous DNS synchronous and asynchronous" before this test and using same host names in this run. For each request that was given an unique ID, call cancel. Verify that callback is not called for canceled requests. +Verify the asynchronous DNS query cancel works correctly. Call `NetworkInterface::gethostbyname_async()` six times with different host names. The cache contains three host names used in requests. You can achieve this, for example, by running the "Asynchronous DNS synchronous and asynchronous" test before this test and using the same host names in this run. For each request that was given an unique ID, call cancel. Verify the callback is not called for canceled requests. **Preconditions:** -1. Network interface is initialized. -2. Network connection is up. +1. Network interface is initialized. +1. Network connection is up. **Test steps:** -1. Call `gethostbyname_async()` in a row 6 times with a different host names. Cache shall contain in maximum 3 host names used in requests. -2. Call `gethostbyname_async_cancel()` for each request that was given an unique ID. -3. Verify that for canceled requests, callback is not called. -4. Verify that for other requests, callback is called. +1. Call `gethostbyname_async()` six times with different host names. The cache contains a maximum of three host names used in requests. +1. Call `gethostbyname_async_cancel()` for each request that was given an unique ID. +1. Verify that for canceled requests, callback is not called. +1. Verify that for other requests, callback is called. **Expected result:** -Callback shall be called only for requests that were not canceled. +Callback is called only for requests that were not canceled. ### ASYNCHRONOUS_DNS_EXTERNAL_EVENT_QUEUE **Description:** -Verify that providing an external event queue works correctly. Define a thread and an event queue running on it. Define a DNS call in callback function that uses the event queue (call_in_callback_cb_t). Enable external event queue. Call `NetworkInterface::gethostbyname_async()` in a row 6 times with a different host names. +Verify that providing an external event queue works correctly. Define a thread and an event queue running on it. Define a DNS call in callback function that uses the event queue (call_in_callback_cb_t). Enable external event queue. Call `NetworkInterface::gethostbyname_async()` six times with different host names. **Preconditions:** -1. Network interface is initialized. -2. Network connection is up. +1. Network interface is initialized. +1. Network connection is up. **Test steps:** -1. Define a thread and an event queue running on it. -2. Define a DNS call in callback function that uses the event queue (call_in_callback_cb_t). -3. Start thread and event queue. -4. Set DNS callback function using the `nsapi_dns_call_in_set()` call. -5. Call `gethostbyname_async()` in a row 6 times with a different host names. Host names shall not be found from cache. -6. Verify that last `gethostbyname_async()` operation is rejected since there is room only for 5 simultaneous operations. -7. Verify that callback is called with correct parameters 5 times. -8. Restore default DNS callback function using the `nsapi_dns_call_in_set()` call. +1. Define a thread and an event queue running on it. +1. Define a DNS call in a callback function that uses the event queue (call_in_callback_cb_t). +1. Start thread and event queue. +1. Set DNS callback function using the `nsapi_dns_call_in_set()` call. +1. Call `gethostbyname_async()` six times with different host names. The host names are not found from cache. +1. Verify the last `gethostbyname_async()` operation is rejected because there is room only for five simultaneous operations. +1. Verify the callback is called with correct parameters five times. +1. Restore the default DNS callback function using the `nsapi_dns_call_in_set()` call. **Expected result:** -Sixth `gethostbyname_async()` is rejected. Callback is called with `NSAPI_ERROR_OK` and IP address 5 times. +The sixth `gethostbyname_async()` is rejected. Callback is called with `NSAPI_ERROR_OK` and IP address five times. ### ASYNCHRONOUS_DNS_INVALID_HOST **Description:** -Verify that DNS failure error is provided for invalid hosts. Call `NetworkInterface::gethostbyname_async()` in a row 6 times with a different host names. First, third and fifth host name shall be invalid. +Verify the DNS failure error is provided for invalid hosts. Call `NetworkInterface::gethostbyname_async()` six times with different host names. The first, third and fifth host names are invalid. **Preconditions:** -1. Network interface is initialized. -2. Network connection is up. +1. Network interface is initialized. +1. Network connection is up. **Test steps:** -1. Call `gethostbyname_async()` in a row 6 times with a different host names. Host names shall not be found from cache. First, third and fifth host name shall be invalid. -2. Verify that last `gethostbyname_async()` operation is rejected since there is room only for 5 simultaneous operations. -3. Verify that callback is called with correct parameters 5 times. +1. Call `gethostbyname_async()` six times with different host names. Host names are not found from cache. The first, third and fifth host names are invalid. +1. Verify the last `gethostbyname_async()` operation is rejected because there is room only for five simultaneous operations. +1. Verify the callback is called with correct parameters five times. **Expected result:** -Sixth `gethostbyname_async()` is rejected. Callback is called with `NSAPI_ERROR_DNS_FAILURE` for first, third and fifth host name. Callback is called with `NSAPI_ERROR_OK` and IP address for second and fourth host name. +The sixth `gethostbyname_async()` is rejected. Callback is called with `NSAPI_ERROR_DNS_FAILURE` for the first, third and fifth host names. Callback is called with `NSAPI_ERROR_OK` and IP address for the second and fourth host names. ### ASYNCHRONOUS_DNS_TIMEOUTS **Description:** -Test DNS timeouts using an external event queue that is modified to timeout the events faster that standard event queue. In this test event queue shall not delay events, instead it handles those immediately. Call `NetworkInterface::gethostbyname_async()` in a row 6 times with a different host names. All or some of the request shall timeout and timeout return value is returned. +Test DNS timeouts using an external event queue that is modified to time out the events faster than the standard event queue. In this test, the event queue does not delay events; instead, it handles those immediately. Call `NetworkInterface::gethostbyname_async()` six times with different host names. All or some of the request time out, and the timeout return value is returned. **Preconditions:** -1. Network interface is initialized. -2. Network connection is up. +1. Network interface is initialized. +1. Network connection is up. **Test steps:** -1. Define a thread and an event queue running on it. -2. Define a DNS call in callback function that uses the event queue (call_in_callback_cb_t). Callback function shall not delay callbacks; instead it shall handle those immediately. -3. Start thread and event queue. -4. Set DNS callback function using the `nsapi_dns_call_in_set()` call. -5. Call `gethostbyname_async()` in a row 6 times with a different host names. Host names shall not be found from cache. -6. Verify that last `gethostbyname_async()` operation is rejected since there is room only for 5 simultaneous operations. -7. Verify that callback is called with correct parameters 5 times. +1. Define a thread and an event queue running on it. +1. Define a DNS call in callback function that uses the event queue (call_in_callback_cb_t). The callback function does not delay callbacks; instead it handles those immediately. +1. Start thread and event queue. +1. Set DNS callback function using the `nsapi_dns_call_in_set()` call. +1. Call `gethostbyname_async()` six times with a different host names. Host names are not found from cache. +1. Verify the last `gethostbyname_async()` operation is rejected because there is room only for five simultaneous operations. +1. Verify the callback is called with correct parameters five times. **Expected result:** -Sixth `gethostbyname_async()` is rejected. At least for one operation, callback is called with `NSAPI_ERROR_TIMEOUT` value. +The sixth `gethostbyname_async()` is rejected. At least for one operation, the callback is called with the `NSAPI_ERROR_TIMEOUT` value. ### ASYNCHRONOUS_DNS_SIMULTANEOUS_REPEAT **Description:** -Verify that simultaneous asynchronous DNS queries work correctly when repeated in sequence. Call `NetworkInterface::gethostbyname_async()` in a row 5 times with a different host names. Wait for all requests to complete and verify result. Repeat the procedure 100 times. +Verify the simultaneous asynchronous DNS queries work correctly when repeated in sequence. Call `NetworkInterface::gethostbyname_async()` five times with different host names. Wait for all requests to complete, and verify the result. Repeat the procedure 100 times. **Preconditions:** -1. Network interface is initialized. -2. Network connection is up. +1. Network interface is initialized. +1. Network connection is up. **Test steps:** -1. Call `gethostbyname_async()` in a row 5 times with a different host names, providing a callback to be called when the operation completes. -2. Verify that callback is called with correct parameters 5 times for the first operation. -3. Repeat 100 times steps 1 to 2. +1. Call `gethostbyname_async()` five times with different host names, providing a callback to be called when the operation completes. +1. Verify the callback is called with correct parameters five times for the first operation. +1. Repeat steps 1-2 100 times. **Expected result:** -Callback, registered for `gethostbyname_async()`, is called with `NSAPI_ERROR_OK` and an IP address 5 times for every one of a hundred repetitions of the test. +A callback, registered for `gethostbyname_async()`, is called with `NSAPI_ERROR_OK` and an IP address five times for every one of 100 repetitions of the test. ### SYNCHRONOUS_DNS @@ -1897,13 +1827,13 @@ Verify the basic functionality of synchronous DNS. Call `NetworkInterface::getho **Preconditions:** -1. Network interface is initialized. -2. Network connection is up. +1. Network interface is initialized. +1. Network connection is up. **Test steps:** -1. Call `gethostbyname()` with a valid host name. -2. Verify the address was resolved and the return value was valid. +1. Call `gethostbyname()` with a valid host name. +1. Verify the address was resolved and the return value was valid. **Expected result:** @@ -1913,17 +1843,17 @@ Return value is `NSAPI_ERROR_OK` and IP address is obtained from the function ca **Description:** -Verify the basic functionality of synchronous DNS. Call `NetworkInterface::gethostbyname()` with a list of 6 host names, and verify the result. +Verify the basic functionality of synchronous DNS. Call `NetworkInterface::gethostbyname()` with a list of six host names, and verify the result. **Preconditions:** -1. Network interface is initialized. -2. Network connection is up. +1. Network interface is initialized. +1. Network connection is up. **Test steps:** -1. Call `gethostbyname()` with a list of 6 host names. -2. Verify that each of the addresses was resolved and the return value was valid. +1. Call `gethostbyname()` with a list of six host names. +1. Verify each of the addresses was resolved and the return value was valid. **Expected result:** @@ -1933,65 +1863,65 @@ Return value is `NSAPI_ERROR_OK` and IP addresses are obtained from the function **Description:** -Verify that the caching of DNS results works correctly. Call `NetworkInterface::gethostbyname()` 5 times with the same host name, and verify the result after each request. For first request, cache shall not contain the host name. Verify that first request completes before the requests made after it (where the response is found from cache). +Verify the caching of DNS results works correctly. Call `NetworkInterface::gethostbyname()` five times with the same host name, and verify the result after each request. For the first request, the cache does not contain the host name. Verify the first request completes before the requests made after it (where the response is found from cache). **Preconditions:** -1. Network interface is initialized. -2. Network connection is up. +1. Network interface is initialized. +1. Network connection is up. **Test steps:** -1. Call `gethostbyname()` with a host name. For the first request, host name should not be found in cache and an error should be returned. -2. Verify that address was resolved and the return value was valid. -3. Repeat the sequence 4 times using the same host name. -4. For each request, calculate how long time it takes for DNS query to complete. +1. Call `gethostbyname()` with a host name. For the first request, the host name is not found in cache, and an error is returned. +1. Verify the address was resolved and the return value was valid. +1. Repeat the sequence four times using the same host name. +1. For each request, calculate how long it takes the DNS query to complete. **Expected result:** -Return value is `NSAPI_ERROR_OK` and IP address is obtained from the function call 5 times. First request shall complete before the requests made after it (where the response is found from cache). +The return value is `NSAPI_ERROR_OK`, and the IP address is obtained from the function call five times. The first request completes before the requests made after it (where the response is found from cache). ### SYNCHRONOUS_DNS_INVALID_HOST **Description:** -Verify that DNS failure error is provided for invalid hosts. Call `NetworkInterface::gethostbyname()` in a row 6 times with different host names. First, third and fifth of the host names used in this test shall be invalid (for example by adding an incorrect suffic, like so: "google.com_invalid"). +Verify the DNS failure error is provided for invalid hosts. Call `NetworkInterface::gethostbyname()` six times with different host names. The first, third and fifth host names are invalid (for example by adding an incorrect suffix, such as "google.com_invalid"). **Preconditions:** -1. Network interface is initialized. -2. Network connection is up. +1. Network interface is initialized. +1. Network connection is up. **Test steps:** -1. Call `gethostbyname()` in a row 6 times with a different host names. Host names shall not be found from cache. First, third and fifth host name shall be invalid. -2. Verify that return value was valid and for valid hostnames the address was resolved 6 times. +1. Call `gethostbyname()` six times with different host names. Host names are not found from cache. The first, third and fifth host names are invalid. +1. Verify the return value was valid and for valid hostnames the address was resolved six times. **Expected result:** -Return value is `NSAPI_ERROR_DNS_FAILURE` for first, third and fifth host name, which were invalidated at the beginning of the test. Return value is `NSAPI_ERROR_OK` and IP address is obtained for second and fourth host name, which were valid. +The return value is `NSAPI_ERROR_DNS_FAILURE` for the first, third and fifth host names, which were invalidated at the beginning of the test. The return value is `NSAPI_ERROR_OK`, and the IP address is obtained for the second and fourth host names, which were valid. Subset for driver test ---------------------- ### For physical layer driver (emac, PPP): -- TCPSOCKET_ECHOTEST -- TCPSOCKET_ECHOTEST_BURST -- TCPSOCKET_ECHOTEST_BURST_NONBLOCK -- TCPSOCKET_ECHOTEST_NONBLOCK -- TCPSOCKET_RECV_100K -- TCPSOCKET_RECV_100K_NONBLOCK -- TCPSOCKET_RECV_TIMEOUT -- TCPSOCKET_SEND_REPEAT -- UDPSOCKET_BIND_SENDTO -- UDPSOCKET_ECHOTEST -- UDPSOCKET_ECHOTEST_NONBLOCK -- UDPSOCKET_RECV_TIMEOUT -- UDPSOCKET_SENDTO_INVALID -- UDPSOCKET_SENDTO_REPEAT -- UDPSOCKET_SENDTO_TIMEOUT +- TCPSOCKET_ECHOTEST. +- TCPSOCKET_ECHOTEST_BURST. +- TCPSOCKET_ECHOTEST_BURST_NONBLOCK. +- TCPSOCKET_ECHOTEST_NONBLOCK. +- TCPSOCKET_RECV_100K. +- TCPSOCKET_RECV_100K_NONBLOCK. +- TCPSOCKET_RECV_TIMEOUT. +- TCPSOCKET_SEND_REPEAT. +- UDPSOCKET_BIND_SENDTO. +- UDPSOCKET_ECHOTEST. +- UDPSOCKET_ECHOTEST_NONBLOCK. +- UDPSOCKET_RECV_TIMEOUT. +- UDPSOCKET_SENDTO_INVALID. +- UDPSOCKET_SENDTO_REPEAT. +- UDPSOCKET_SENDTO_TIMEOUT. ### For socket layer driver (AT-driven, external IP stack): -All Socket, UDPSocket, TCPSocket and TLSSocket testcases. +All Socket, UDPSocket, TCPSocket and TLSSocket test cases. From 227db159faf637a46aa754f7510b67efeb3b3a00 Mon Sep 17 00:00:00 2001 From: Marcin Tomczyk Date: Wed, 11 Sep 2019 07:59:24 +0200 Subject: [PATCH 090/227] Add missing documentation about tls testing - review comments fixes --- TESTS/netsocket/README.md | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/TESTS/netsocket/README.md b/TESTS/netsocket/README.md index 0cf9eb35c17..8cab4dd5134 100644 --- a/TESTS/netsocket/README.md +++ b/TESTS/netsocket/README.md @@ -487,17 +487,17 @@ Call `Socket::open()` twice. 1. Create an object by calling `new Socket()`. 1. Call `Socket::open(stack)`. 1. Call `Socket::open(stack)`. -1. Delete the socket. +1. Destroy the socket. **Expected result:** -`Socket::open()` first returns `NSAPI_ERROR_OK` and then calls `NSAPI_ERROR_PARAMETER`. +`Socket::open()` first call (socket was not opened) returns `NSAPI_ERROR_OK` and nexts calls (socet was opened by previous call Socket::open()) return `NSAPI_ERROR_PARAMETER`. ### SOCKET_OPEN_CLOSE_REPEAT **Description:** -Call `Socket::open()` followed by `Socket::close()` and then again `Socket::open()`. This allows you to reuse the same object. +Call `Socket::open()` followed by `Socket::close()` and then again `Socket::open()`. Should allows you to reuse the same object. **Preconditions:** @@ -511,7 +511,7 @@ Call `Socket::open()` followed by `Socket::close()` and then again `Socket::open 1. Call `Socket::close(stack)`. 1. Call `Socket::open(stack)`. 1. Call `Socket::close(stack)`. -1. Delete the socket. +1. Destroy the socket. **Expected result:** @@ -1155,13 +1155,13 @@ Test whether you tolerate an endpoint closing the connection. 1. Call `TCPSocket::recv(, 30);`. 1. Repeat until `recv()` returns 0. 1. Call `TCPSocket::close();`. -1. Delete the socket. +1. Destroy the socket. **Expected result:** Connect returns `NSAPI_ERROR_OK`. -The first `recv()` returns more that zero. Something between 10 and 30 bytes (datetime string). +The first `recv()` returns datetime string length (It is between 10 and 30 bytes). The second `recv()` returns zero because the endpoint closed the connection. `close()` returns `NSAPI_ERROR_OK`. @@ -1185,7 +1185,7 @@ Test you can request setting valid TCP keepalive values. **Postconditions:** 1. Call `TCPSocket::close();`. -1. Delete the socket. +1. Destroy the socket. **Expected result:** @@ -1257,11 +1257,11 @@ Make an HTTP request to a closed socket. ### TLSSOCKET_SEND_REPEAT -**Description:** Run `SOCKET_SEND_REPEATÂ` for TLSSOCKET by using port number 2009. +**Description:** Run `SOCKET_SEND_REPEAT` for TLSSOCKET by using port number 2009. ### TLSSOCKET_SEND_TIMEOUT -**Description:** Run `SOCKET_SEND_TIMEOUTÂ` for TLSSOCKET by using port number 2009. +**Description:** Run `SOCKET_SEND_TIMEOUT` for TLSSOCKET by using port number 2009. ### TLSSOCKET_SEND_UNCONNECTED @@ -1287,11 +1287,11 @@ Make an HTTP request to an unconnected socket. ### TLSSOCKET_ECHOTEST -**Description:** Run `SOCKET_ECHOTESTÂ` for TLSSOCKET by using port number 2007. +**Description:** Run `SOCKET_ECHOTEST` for TLSSOCKET by using port number 2007. ### TLSSOCKET_ECHOTEST_NONBLOCK -**Description:** Run `SOCKET_ECHOTEST_NONBLOCKÂ` for TLSSOCKET by using port number 2007. +**Description:** Run `SOCKET_ECHOTEST_NONBLOCK` for TLSSOCKET by using port number 2007. ### TLSSOCKET_ENDPOINT_CLOSE @@ -1322,7 +1322,7 @@ Verify TLS Socket fails to connect without a certificate. **Description:** -Run `TCPSOCKET_RECV_TIMEOUTÂ` for TLSSOCKET by using port number 2007. +Run `TCPSOCKET_RECV_TIMEOUT` for TLSSOCKET by using port number 2007. ### TLSSOCKET_SIMULTANEOUS_TEST From d6e2edc8d5af26d068eea643459d9b2bbabdb200 Mon Sep 17 00:00:00 2001 From: int_szyk Date: Wed, 11 Sep 2019 08:33:49 +0200 Subject: [PATCH 091/227] Coverity changes in USBMSD.cpp --- drivers/source/usb/USBMSD.cpp | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/source/usb/USBMSD.cpp b/drivers/source/usb/USBMSD.cpp index dfde0f75a24..1071eec7d87 100644 --- a/drivers/source/usb/USBMSD.cpp +++ b/drivers/source/usb/USBMSD.cpp @@ -66,7 +66,8 @@ enum Status { USBMSD::USBMSD(BlockDevice *bd, bool connect_blocking, uint16_t vendor_id, uint16_t product_id, uint16_t product_release) : USBDevice(get_usb_phy(), vendor_id, product_id, product_release), - _initialized(false), _media_removed(false), _in_task(&_queue), _out_task(&_queue), _reset_task(&_queue), _control_task(&_queue), _configure_task(&_queue), _bd(bd) + _initialized(false), _media_removed(false), _in_task(&_queue), _out_task(&_queue), _reset_task(&_queue), _control_task(&_queue), _configure_task(&_queue), _bd(bd), + _addr(0), _length(0), _mem_ok(false), _block_size(0), _memory_size(0), _block_count(0), _out_ready(false), _in_ready(false), _bulk_out_size(0) { _init(); if (connect_blocking) { @@ -78,7 +79,8 @@ USBMSD::USBMSD(BlockDevice *bd, bool connect_blocking, uint16_t vendor_id, uint1 USBMSD::USBMSD(USBPhy *phy, BlockDevice *bd, uint16_t vendor_id, uint16_t product_id, uint16_t product_release) : USBDevice(phy, vendor_id, product_id, product_release), - _initialized(false), _media_removed(false), _in_task(&_queue), _out_task(&_queue), _reset_task(&_queue), _control_task(&_queue), _configure_task(&_queue), _bd(bd) + _initialized(false), _media_removed(false), _in_task(&_queue), _out_task(&_queue), _reset_task(&_queue), _control_task(&_queue), _configure_task(&_queue), _bd(bd), + _addr(0), _length(0), _mem_ok(false), _block_size(0), _memory_size(0), _block_count(0), _out_ready(false), _in_ready(false), _bulk_out_size(0) { _init(); } From 7411db1deb10d6ca35c32f2e14fb8ffe32ab5638 Mon Sep 17 00:00:00 2001 From: int_szyk Date: Tue, 17 Sep 2019 12:01:32 +0200 Subject: [PATCH 092/227] Change the LSI_VALUE according to documentation --- targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_conf.h | 2 +- targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_rcc.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_conf.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_conf.h index 3bfc9a065b5..03fffc19f2b 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_conf.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_conf.h @@ -114,7 +114,7 @@ extern "C" { * @brief Internal Low Speed oscillator (LSI) value. */ #if !defined (LSI_VALUE) -#define LSI_VALUE 32000U /*!< LSI Typical Value in Hz */ +#define LSI_VALUE 40000U /*!< LSI Typical Value in Hz */ #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature. */ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_rcc.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_rcc.h index f03a74a1aa4..3e63d9c128e 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_rcc.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_rcc.h @@ -120,7 +120,7 @@ typedef struct #endif /* LSE_VALUE */ #if !defined (LSI_VALUE) -#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ +#define LSI_VALUE 40000U /*!< Value of the LSI oscillator in Hz */ #endif /* LSI_VALUE */ /** * @} From 19cb034b13cdee318bf4fcbcd83565e7355d1a81 Mon Sep 17 00:00:00 2001 From: Martin Kojtal Date: Tue, 17 Sep 2019 13:21:22 +0100 Subject: [PATCH 093/227] iar export: fix invalid optmization flag - remove from misc The exported project uses project file to set optimization, we can provide this via misc options. It was recently changed to Ol and this was not handled in our scripts. --- tools/export/iar/__init__.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/export/iar/__init__.py b/tools/export/iar/__init__.py index 02b82b0087b..5090b5eba5e 100644 --- a/tools/export/iar/__init__.py +++ b/tools/export/iar/__init__.py @@ -121,7 +121,7 @@ def generate(self): template = ["--vla", "--no_static_destruction"] # Flag invalid if set in template # Optimizations are also set in template - invalid_flag = lambda x: x in template or re.match("-O(\d|time|n|hz?)", x) + invalid_flag = lambda x: x in template or re.match("-O(\d|time|n|l|hz?)", x) flags['c_flags'] = [flag for flag in c_flags if not invalid_flag(flag)] try: From c5c026173735d562ec814be4589baf9a70670eb3 Mon Sep 17 00:00:00 2001 From: Kimmo Vaisanen Date: Tue, 17 Sep 2019 15:52:14 +0300 Subject: [PATCH 094/227] Cellular: Fix stop tag for Quectel M26 send command Possible responses for send command are SEND OK, SEND FAIL or ERROR so normal OK response check does not work properly. --- .../framework/targets/QUECTEL/M26/QUECTEL_M26_CellularStack.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/features/cellular/framework/targets/QUECTEL/M26/QUECTEL_M26_CellularStack.cpp b/features/cellular/framework/targets/QUECTEL/M26/QUECTEL_M26_CellularStack.cpp index 0c09c537e66..d02118b321f 100644 --- a/features/cellular/framework/targets/QUECTEL/M26/QUECTEL_M26_CellularStack.cpp +++ b/features/cellular/framework/targets/QUECTEL/M26/QUECTEL_M26_CellularStack.cpp @@ -439,6 +439,7 @@ nsapi_size_or_error_t QUECTEL_M26_CellularStack::socket_sendto_impl(CellularSock _at.resp_start(">"); _at.write_bytes((uint8_t *)data, sent_len); _at.resp_start(); + _at.set_stop_tag("\r\n"); _at.resp_stop(); if (_at.get_last_error() != NSAPI_ERROR_OK) { From 31528016b50d497b7129569726d6665d4f9a856b Mon Sep 17 00:00:00 2001 From: Ari Parkkila Date: Mon, 16 Sep 2019 02:59:23 -0700 Subject: [PATCH 095/227] Cellular: Add flow control (IFC) in BG96 AT driver --- .../framework/AT/athandler/athandlertest.cpp | 2 +- features/cellular/framework/AT/ATHandler.cpp | 8 +++++++- .../targets/QUECTEL/BG96/QUECTEL_BG96.cpp | 20 ++++++++++++------- 3 files changed, 21 insertions(+), 9 deletions(-) diff --git a/UNITTESTS/features/cellular/framework/AT/athandler/athandlertest.cpp b/UNITTESTS/features/cellular/framework/AT/athandler/athandlertest.cpp index d168c6a4889..44a86e5e942 100644 --- a/UNITTESTS/features/cellular/framework/AT/athandler/athandlertest.cpp +++ b/UNITTESTS/features/cellular/framework/AT/athandler/athandlertest.cpp @@ -1368,7 +1368,7 @@ TEST_F(TestATHandler, test_ATHandler_sync) EXPECT_EQ(false, at.sync(100)); fh1.size_value = 8; - char table[] = "OK\r\n\0"; + char table[] = "+CMEE: 1\r\nOK\r\n\0"; filehandle_stub_table = table; at.flush(); diff --git a/features/cellular/framework/AT/ATHandler.cpp b/features/cellular/framework/AT/ATHandler.cpp index 1fab9d5e22e..295967691be 100644 --- a/features/cellular/framework/AT/ATHandler.cpp +++ b/features/cellular/framework/AT/ATHandler.cpp @@ -1574,7 +1574,13 @@ bool ATHandler::sync(int timeout_ms) // especially a common response like OK could be response to previous request. clear_error(); _start_time = rtos::Kernel::get_ms_count(); - at_cmd_discard("+CMEE", "?"); + cmd_start("AT+CMEE?"); + cmd_stop(); + resp_start(); + set_stop_tag("+CMEE:"); + consume_to_stop_tag(); + set_stop_tag(OK); + consume_to_stop_tag(); if (!_last_err) { _at_timeout = timeout; unlock(); diff --git a/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96.cpp b/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96.cpp index b8222044f7b..fe31a3920f4 100644 --- a/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96.cpp +++ b/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96.cpp @@ -102,16 +102,22 @@ nsapi_error_t QUECTEL_BG96::soft_power_on() if (_pwr.is_connected()) { tr_info("QUECTEL_BG96::soft_power_on"); // check if modem was powered on already - if (wake_up()) { - return NSAPI_ERROR_OK; - } - if (!wake_up(true)) { - tr_error("Modem not responding"); - soft_power_off(); - return NSAPI_ERROR_DEVICE_ERROR; + if (!wake_up()) { + if (!wake_up(true)) { + tr_error("Modem not responding"); + soft_power_off(); + return NSAPI_ERROR_DEVICE_ERROR; + } } } +#if defined (MBED_CONF_QUECTEL_BG96_RTS) && defined(MBED_CONF_QUECTEL_BG96_CTS) + if (_at->at_cmd_discard("+IFC", "=", "%d%d", 2, 2) != NSAPI_ERROR_OK) { + tr_warn("Set flow control failed"); + return NSAPI_ERROR_DEVICE_ERROR; + } +#endif + return NSAPI_ERROR_OK; } From 9f947e34c00493f7599453fe91221ef6132d01dd Mon Sep 17 00:00:00 2001 From: Michal Paszta Date: Thu, 12 Sep 2019 15:59:12 +0200 Subject: [PATCH 096/227] Fix compilation warnings from GCC --- TESTS/netsocket/dns/synchronous_dns_cache.cpp | 1 + TESTS/netsocket/tcp/tcpsocket_echotest.cpp | 2 +- TESTS/netsocket/tcp/tcpsocket_recv_100k.cpp | 2 +- TESTS/netsocket/tls/tlssocket_echotest.cpp | 2 +- TESTS/netsocket/udp/udpsocket_echotest.cpp | 4 ++-- TESTS/network/emac/main.cpp | 9 +-------- .../network/interface/networkinterface_status.cpp | 2 +- TESTS/network/l3ip/main.cpp | 4 ---- .../multihoming/multihoming_asynchronous_dns.cpp | 2 +- .../multihoming/multihoming_synchronous_dns.cpp | 2 +- .../multihoming/multihoming_udpsocket_echotest.cpp | 6 +++--- TESTS/network/wifi/main.cpp | 14 ++------------ 12 files changed, 15 insertions(+), 35 deletions(-) diff --git a/TESTS/netsocket/dns/synchronous_dns_cache.cpp b/TESTS/netsocket/dns/synchronous_dns_cache.cpp index 0b36b630bdd..61f3fc68874 100644 --- a/TESTS/netsocket/dns/synchronous_dns_cache.cpp +++ b/TESTS/netsocket/dns/synchronous_dns_cache.cpp @@ -41,6 +41,7 @@ void SYNCHRONOUS_DNS_CACHE() SocketAddress address; int started_us = ticker_us; nsapi_error_t err = get_interface()->gethostbyname(dns_test_hosts[0], &address); + TEST_ASSERT_TRUE(err == NSAPI_ERROR_OK); int delay_ms = (ticker_us - started_us) / 1000; diff --git a/TESTS/netsocket/tcp/tcpsocket_echotest.cpp b/TESTS/netsocket/tcp/tcpsocket_echotest.cpp index 9ec5636a40c..b72284da35f 100644 --- a/TESTS/netsocket/tcp/tcpsocket_echotest.cpp +++ b/TESTS/netsocket/tcp/tcpsocket_echotest.cpp @@ -67,7 +67,7 @@ void TCPSOCKET_ECHOTEST() int recvd; int sent; - for (int s_idx = 0; s_idx < sizeof(pkt_sizes) / sizeof(*pkt_sizes); s_idx++) { + for (unsigned int s_idx = 0; s_idx < sizeof(pkt_sizes) / sizeof(*pkt_sizes); s_idx++) { int pkt_s = pkt_sizes[s_idx]; fill_tx_buffer_ascii(tcp_global::tx_buffer, BUFF_SIZE); sent = sock.send(tcp_global::tx_buffer, pkt_s); diff --git a/TESTS/netsocket/tcp/tcpsocket_recv_100k.cpp b/TESTS/netsocket/tcp/tcpsocket_recv_100k.cpp index a31e9296f0e..473c5ad23c4 100644 --- a/TESTS/netsocket/tcp/tcpsocket_recv_100k.cpp +++ b/TESTS/netsocket/tcp/tcpsocket_recv_100k.cpp @@ -146,7 +146,7 @@ void rcv_n_chk_against_rfc864_pattern_nonblock(TCPSocket &sock) int rd = sock.recv(buff, buff_size); TEST_ASSERT(rd > 0 || rd == NSAPI_ERROR_WOULD_BLOCK); if (rd > 0) { - if (rd > buff_size) { + if ((unsigned int) rd > buff_size) { TEST_FAIL_MESSAGE("sock.recv returned more than requested."); } check_RFC_864_pattern(buff, rd, recvd_size); diff --git a/TESTS/netsocket/tls/tlssocket_echotest.cpp b/TESTS/netsocket/tls/tlssocket_echotest.cpp index 72b299a3e62..5d9faa857e0 100644 --- a/TESTS/netsocket/tls/tlssocket_echotest.cpp +++ b/TESTS/netsocket/tls/tlssocket_echotest.cpp @@ -70,7 +70,7 @@ void TLSSOCKET_ECHOTEST() int recvd; int sent; - for (int s_idx = 0; s_idx < sizeof(pkt_sizes) / sizeof(*pkt_sizes); s_idx++) { + for (unsigned int s_idx = 0; s_idx < sizeof(pkt_sizes) / sizeof(*pkt_sizes); s_idx++) { int pkt_s = pkt_sizes[s_idx]; fill_tx_buffer_ascii(tls_global::tx_buffer, BUFF_SIZE); diff --git a/TESTS/netsocket/udp/udpsocket_echotest.cpp b/TESTS/netsocket/udp/udpsocket_echotest.cpp index c30094949c9..f085250ae6d 100755 --- a/TESTS/netsocket/udp/udpsocket_echotest.cpp +++ b/TESTS/netsocket/udp/udpsocket_echotest.cpp @@ -68,7 +68,7 @@ void UDPSOCKET_ECHOTEST() int sent; int packets_sent = 0; int packets_recv = 0; - for (int s_idx = 0; s_idx < sizeof(pkt_sizes) / sizeof(*pkt_sizes); ++s_idx) { + for (unsigned int s_idx = 0; s_idx < sizeof(pkt_sizes) / sizeof(*pkt_sizes); ++s_idx) { int pkt_s = pkt_sizes[s_idx]; fill_tx_buffer_ascii(tx_buffer, BUFF_SIZE); @@ -127,7 +127,7 @@ void UDPSOCKET_ECHOTEST_NONBLOCK() int sent; int packets_sent = 0; int packets_recv = 0; - for (int s_idx = 0; s_idx < sizeof(pkt_sizes) / sizeof(*pkt_sizes); ++s_idx) { + for (unsigned int s_idx = 0; s_idx < sizeof(pkt_sizes) / sizeof(*pkt_sizes); ++s_idx) { int pkt_s = pkt_sizes[s_idx]; int packets_sent_prev = packets_sent; for (int retry_cnt = 0; retry_cnt <= RETRIES; retry_cnt++) { diff --git a/TESTS/network/emac/main.cpp b/TESTS/network/emac/main.cpp index 593d944fda5..c1b2f68fa4c 100644 --- a/TESTS/network/emac/main.cpp +++ b/TESTS/network/emac/main.cpp @@ -83,14 +83,7 @@ int main() return !Harness::run(specification); } -#endif // (MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE == WIFI) && \ -!defined(TARGET_UBLOX_EVK_ODIN_W2) && \ -!defined(TARGET_REALTEK_RTL8195AM) && \ -!defined(TARGET_MTB_ADV_WISE_1530) && \ -!defined(TARGET_MTB_USI_WM_BN_BM_22) && \ -!defined(TARGET_MTB_MXCHIP_EMW3166) && \ -!defined(TARGET_MTB_UBLOX_ODIN_W2) && \ -!defined(TARGET_UNO_91H) +#endif // (MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE == WIFI) && !defined(TARGET_* #endif // MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE != ETHERNET && MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE != WIFI #endif // !defined(MBED_CONF_APP_ECHO_SERVER) || !defined(MBED_CONF_APP_ECHO_SERVER_TRACE) || !defined(MBED_CONF_APP_WIFI_SCAN) diff --git a/TESTS/network/interface/networkinterface_status.cpp b/TESTS/network/interface/networkinterface_status.cpp index f4ebe5d9ad1..e59796a31cd 100644 --- a/TESTS/network/interface/networkinterface_status.cpp +++ b/TESTS/network/interface/networkinterface_status.cpp @@ -132,7 +132,7 @@ void NETWORKINTERFACE_STATUS_NONBLOCK() status = wait_status_callback(); TEST_ASSERT_EQUAL(NSAPI_STATUS_DISCONNECTED, status); - wait(1); // In cellular there might still come disconnected messages from the network which are sent to callback. + ThisThread::sleep_for(1); // In cellular there might still come disconnected messages from the network which are sent to callback. // This would cause this test to fail as next connect is already ongoing. So wait here a while until (hopefully) // all messages also from the network have arrived. } diff --git a/TESTS/network/l3ip/main.cpp b/TESTS/network/l3ip/main.cpp index 98c04512a47..abca2b7e3fa 100644 --- a/TESTS/network/l3ip/main.cpp +++ b/TESTS/network/l3ip/main.cpp @@ -25,10 +25,6 @@ using namespace utest::v1; -namespace { -NetworkInterface *l3interface; -} - void L3IP_START() { printf("MBED: L3IP_START\n"); diff --git a/TESTS/network/multihoming/multihoming_asynchronous_dns.cpp b/TESTS/network/multihoming/multihoming_asynchronous_dns.cpp index a6f8bb5aa52..cd1f561c45a 100644 --- a/TESTS/network/multihoming/multihoming_asynchronous_dns.cpp +++ b/TESTS/network/multihoming/multihoming_asynchronous_dns.cpp @@ -61,7 +61,7 @@ void MULTIHOMING_ASYNCHRONOUS_DNS() continue; } - for (unsigned int j = 0; j < interface_num; j++) { + for (int j = 0; j < interface_num; j++) { nsapi_error_t err = interface->gethostbyname_async(dns_test_hosts[i], mbed::Callback(hostbyname_cb, (void *) &data), NSAPI_UNSPEC, interface_name[j]); diff --git a/TESTS/network/multihoming/multihoming_synchronous_dns.cpp b/TESTS/network/multihoming/multihoming_synchronous_dns.cpp index df71eae3268..cff77034f65 100644 --- a/TESTS/network/multihoming/multihoming_synchronous_dns.cpp +++ b/TESTS/network/multihoming/multihoming_synchronous_dns.cpp @@ -51,7 +51,7 @@ void MULTIHOMING_SYNCHRONOUS_DNS() continue; } - for (unsigned int j = 0; j < interface_num; j++) { + for (int j = 0; j < interface_num; j++) { nsapi_error_t err = interface->gethostbyname(dns_test_hosts[i], &address, NSAPI_UNSPEC, interface_name[j]); printf("DNS: query interface_name %s %d \n", interface_name[j], j); diff --git a/TESTS/network/multihoming/multihoming_udpsocket_echotest.cpp b/TESTS/network/multihoming/multihoming_udpsocket_echotest.cpp index b237281f424..347066c51b5 100644 --- a/TESTS/network/multihoming/multihoming_udpsocket_echotest.cpp +++ b/TESTS/network/multihoming/multihoming_udpsocket_echotest.cpp @@ -66,7 +66,7 @@ void MULTIHOMING_UDPSOCKET_ECHOTEST() UDPSocket sock; TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock.open(interface)); - for (unsigned int j = 0; j < interface_num; j++) { + for (int j = 0; j < interface_num; j++) { int recvd; int sent; int s_idx = 0; @@ -113,7 +113,7 @@ void udpsocket_echotest_nonblock_receiver(void *receive_bytes) for (int retry_cnt = 0; retry_cnt <= RETRIES; retry_cnt++) { recvd = sock.recvfrom(NULL, rx_buffer, expt2recv); if (recvd == NSAPI_ERROR_WOULD_BLOCK) { - wait_ms(WAIT2RECV_TIMEOUT); + ThisThread::sleep_for(WAIT2RECV_TIMEOUT); --retry_cnt; continue; } else if (recvd == expt2recv) { @@ -144,7 +144,7 @@ void MULTIHOMING_UDPSOCKET_ECHOTEST_NONBLOCK() TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, sock.open(interface)); sock.set_blocking(false); sock.sigio(callback(_sigio_handler, ThisThread::get_id())); - for (unsigned int j = 0; j < interface_num; j++) { + for (int j = 0; j < interface_num; j++) { int s_idx = 0; int packets_sent = 0; int packets_recv = 0; diff --git a/TESTS/network/wifi/main.cpp b/TESTS/network/wifi/main.cpp index 73859eb1631..651c9a66101 100644 --- a/TESTS/network/wifi/main.cpp +++ b/TESTS/network/wifi/main.cpp @@ -94,18 +94,8 @@ int main() { return !Harness::run(specification); } -#endif // defined(MBED_CONF_APP_WIFI_UNSECURE_SSID) && \ -!defined(MBED_CONF_APP_AP_MAC_UNSECURE) || \ -!defined(MBED_CONF_APP_MAX_SCAN_SIZE) || \ -!defined(MBED_CONF_APP_WIFI_CH_UNSECURE) || \ -!defined(MBED_CONF_APP_WIFI_UNSECURE_SSID) +#endif // defined(MBED_CONF_APP_WIFI_UNSECURE_SSID) && !defined(MBED_CONF_APP_* -#endif // defined(MBED_CONF_APP_WIFI_SECURE_SSID) && \ -(!defined(MBED_CONF_APP_AP_MAC_SECURE) || \ -!defined(MBED_CONF_APP_MAX_SCAN_SIZE) || \ -!defined(MBED_CONF_APP_WIFI_CH_SECURE) || \ -!defined(MBED_CONF_APP_WIFI_PASSWORD) || \ -!defined(MBED_CONF_APP_WIFI_SECURE_SSID) || \ -!defined MBED_CONF_APP_WIFI_SECURE_PROTOCOL) +#endif // defined(MBED_CONF_APP_WIFI_SECURE_SSID) && (!defined(MBED_CONF_APP_* #endif //!defined(MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE) || MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE != WIFI From 73133a19f5670a61460ac8cbbd2344687fcd2467 Mon Sep 17 00:00:00 2001 From: Hugues Kamba Date: Thu, 12 Sep 2019 09:00:19 +0100 Subject: [PATCH 097/227] Prevent unreachable statements and correct variable sizes. --- drivers/USBAudio.h | 4 ++-- rtos/source/Semaphore.cpp | 3 ++- rtos/source/TARGET_CORTEX/mbed_rtos_rtx.c | 1 - rtos/source/TARGET_CORTEX/mbed_rtx_handlers.c | 3 --- 4 files changed, 4 insertions(+), 7 deletions(-) diff --git a/drivers/USBAudio.h b/drivers/USBAudio.h index 6072afdf0a9..58a84cd69db 100644 --- a/drivers/USBAudio.h +++ b/drivers/USBAudio.h @@ -373,8 +373,8 @@ class USBAudio: protected USBDevice { usb_ep_t _episo_in; // tx endpoint // channel config in the configuration descriptor: master, left, right - uint8_t _channel_config_rx; - uint8_t _channel_config_tx; + uint16_t _channel_config_rx; + uint16_t _channel_config_tx; // configuration descriptor uint8_t _config_descriptor[183]; diff --git a/rtos/source/Semaphore.cpp b/rtos/source/Semaphore.cpp index 86d5db6d979..bcedd99bdc1 100644 --- a/rtos/source/Semaphore.cpp +++ b/rtos/source/Semaphore.cpp @@ -212,8 +212,9 @@ osStatus Semaphore::release(void) return osErrorResource; } } while (!core_util_atomic_cas_s32(&_count, &old_count, old_count + 1)); -#endif + return osOK; +#endif // MBED_CONF_RTOS_PRESENT } Semaphore::~Semaphore() diff --git a/rtos/source/TARGET_CORTEX/mbed_rtos_rtx.c b/rtos/source/TARGET_CORTEX/mbed_rtos_rtx.c index 39f02787c77..5792a7bdc10 100644 --- a/rtos/source/TARGET_CORTEX/mbed_rtos_rtx.c +++ b/rtos/source/TARGET_CORTEX/mbed_rtos_rtx.c @@ -115,5 +115,4 @@ MBED_NORETURN void mbed_rtos_start() osKernelStart(); MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_INITIALIZATION_FAILED), "Failed to start RTOS"); - while (1); // Code should never get here } diff --git a/rtos/source/TARGET_CORTEX/mbed_rtx_handlers.c b/rtos/source/TARGET_CORTEX/mbed_rtx_handlers.c index b5e46f812e8..cbc48e08f50 100644 --- a/rtos/source/TARGET_CORTEX/mbed_rtx_handlers.c +++ b/rtos/source/TARGET_CORTEX/mbed_rtx_handlers.c @@ -80,9 +80,6 @@ __NO_RETURN uint32_t osRtxErrorNotify(uint32_t code, void *object_id) MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_KERNEL, MBED_ERROR_CODE_UNKNOWN), "CMSIS-RTOS error: Unknown", code); break; } - - /* That shouldn't be reached */ - for (;;) {} } #if defined(MBED_TRAP_ERRORS_ENABLED) && MBED_TRAP_ERRORS_ENABLED From 3d23962faf203b2b243337daa1df30965a24123f Mon Sep 17 00:00:00 2001 From: Mark Edgeworth Date: Wed, 11 Sep 2019 11:22:56 +0100 Subject: [PATCH 098/227] IOTBTOOL-349: Correct handling of spaces in project name. This fixes an issue where a space in the name of a project would cause a link failure --- tools/toolchains/mbed_toolchain.py | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/tools/toolchains/mbed_toolchain.py b/tools/toolchains/mbed_toolchain.py index 7352338831f..e607b2b9f3f 100755 --- a/tools/toolchains/mbed_toolchain.py +++ b/tools/toolchains/mbed_toolchain.py @@ -733,13 +733,17 @@ def link_program(self, r, tmp_path, name): new_path = join(tmp_path, head) mkdir(new_path) + # The output file names are derived from the project name, but this can have spaces in it which + # messes-up later processing. Replace any spaces in the derived names with '_' + tail = tail.replace(" ", "_") + # Absolute path of the final linked file if self.config.has_regions: - elf = join(tmp_path, name + '_application.elf') - mapfile = join(tmp_path, name + '_application.map') + elf = join(tmp_path, tail + '_application.elf') + mapfile = join(tmp_path, tail + '_application.map') else: - elf = join(tmp_path, name + '.elf') - mapfile = join(tmp_path, name + '.map') + elf = join(tmp_path, tail + '.elf') + mapfile = join(tmp_path, tail + '.map') objects = sorted(set(r.get_file_paths(FileType.OBJECT))) config_file = ([self.config.app_config_location] @@ -768,21 +772,21 @@ def link_program(self, r, tmp_path, name): if exists(old_mapfile): remove(old_mapfile) rename(mapfile, old_mapfile) - self.progress("link", name) + self.progress("link", tail) self.link(elf, objects, libraries, lib_dirs, linker_script) if self.config.has_regions: - filename = "{}_application.{}".format(name, ext) + filename = "{}_application.{}".format(tail, ext) else: - filename = "{}.{}".format(name, ext) + filename = "{}.{}".format(tail, ext) full_path = join(tmp_path, filename) if ext != 'elf': if full_path and self.need_update(full_path, [elf]): - self.progress("elf2bin", name) + self.progress("elf2bin", tail) self.binary(r, elf, full_path) if self.config.has_regions: full_path, updatable = self._do_region_merge( - name, full_path, ext + tail, full_path, ext ) else: updatable = None @@ -794,7 +798,7 @@ def link_program(self, r, tmp_path, name): self._get_toolchain_labels() ) if post_build_hook: - self.progress("post-build", name) + self.progress("post-build", tail) post_build_hook(self, r, elf, full_path) # Initialize memap and process map file. This doesn't generate output. self.mem_stats(mapfile) From bb5857b92ceef06e8fa0871d316d2db6008b5fd0 Mon Sep 17 00:00:00 2001 From: Mark Edgeworth Date: Wed, 11 Sep 2019 12:18:50 +0100 Subject: [PATCH 099/227] Update tools/toolchains/mbed_toolchain.py Co-Authored-By: Graham Hammond --- tools/toolchains/mbed_toolchain.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/toolchains/mbed_toolchain.py b/tools/toolchains/mbed_toolchain.py index e607b2b9f3f..216dddf1372 100755 --- a/tools/toolchains/mbed_toolchain.py +++ b/tools/toolchains/mbed_toolchain.py @@ -739,7 +739,7 @@ def link_program(self, r, tmp_path, name): # Absolute path of the final linked file if self.config.has_regions: - elf = join(tmp_path, tail + '_application.elf') + elf = join(new_path, tail + '_application.elf') mapfile = join(tmp_path, tail + '_application.map') else: elf = join(tmp_path, tail + '.elf') From ed5dc1cdd5fbb8b55ebaae56590522838c065d9a Mon Sep 17 00:00:00 2001 From: Mark Edgeworth Date: Wed, 11 Sep 2019 12:27:46 +0100 Subject: [PATCH 100/227] Review changes --- tools/toolchains/mbed_toolchain.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tools/toolchains/mbed_toolchain.py b/tools/toolchains/mbed_toolchain.py index 216dddf1372..ce4516b227d 100755 --- a/tools/toolchains/mbed_toolchain.py +++ b/tools/toolchains/mbed_toolchain.py @@ -740,10 +740,10 @@ def link_program(self, r, tmp_path, name): # Absolute path of the final linked file if self.config.has_regions: elf = join(new_path, tail + '_application.elf') - mapfile = join(tmp_path, tail + '_application.map') + mapfile = join(new_path, tail + '_application.map') else: - elf = join(tmp_path, tail + '.elf') - mapfile = join(tmp_path, tail + '.map') + elf = join(new_path, tail + '.elf') + mapfile = join(new_path, tail + '.map') objects = sorted(set(r.get_file_paths(FileType.OBJECT))) config_file = ([self.config.app_config_location] @@ -779,7 +779,7 @@ def link_program(self, r, tmp_path, name): filename = "{}_application.{}".format(tail, ext) else: filename = "{}.{}".format(tail, ext) - full_path = join(tmp_path, filename) + full_path = join(new_path, filename) if ext != 'elf': if full_path and self.need_update(full_path, [elf]): self.progress("elf2bin", tail) From 2bf62bf4c5872e0d1bd8c1198842c4201ed56c9d Mon Sep 17 00:00:00 2001 From: Kimmo Vaisanen Date: Fri, 13 Sep 2019 15:01:11 +0300 Subject: [PATCH 101/227] Cellular: Fix get_interface_name to not include leading zero Multihoming documentation about interface name: "Two character name string is concatenated with 8 bit value containing index which is incremented on each netif addition" Cellular uses context id as index and to follow LWIP (LWIP::Interface::get_interface_name), index does not include leading zeros. --- .../at_cellularcontexttest.cpp | 29 ++++++++++++++++++- .../framework/AT/AT_CellularContext.cpp | 2 +- 2 files changed, 29 insertions(+), 2 deletions(-) diff --git a/UNITTESTS/features/cellular/framework/AT/at_cellularcontext/at_cellularcontexttest.cpp b/UNITTESTS/features/cellular/framework/AT/at_cellularcontext/at_cellularcontexttest.cpp index 451c3a571cc..00ee09e1e04 100644 --- a/UNITTESTS/features/cellular/framework/AT/at_cellularcontext/at_cellularcontexttest.cpp +++ b/UNITTESTS/features/cellular/framework/AT/at_cellularcontext/at_cellularcontexttest.cpp @@ -178,6 +178,18 @@ class def_AT_CTX : public AT_CellularContext { int _op; }; +class AT_CTX_cid: public AT_CellularContext { +public: + AT_CTX_cid(ATHandler &at, CellularDevice *device, const char *apn = MBED_CONF_NSAPI_DEFAULT_CELLULAR_APN) : + AT_CellularContext(at, device, apn) {} + virtual ~AT_CTX_cid() {} + + void set_cid(int cid) + { + _cid = cid; + } +}; + static int network_cb_count; static void network_cb(nsapi_event_t ev, intptr_t intptr) { @@ -250,6 +262,22 @@ TEST_F(TestAT_CellularContext, get_ip_address) EXPECT_TRUE(ip != NULL); } +TEST_F(TestAT_CellularContext, get_interface_name) +{ + EventQueue que; + FileHandle_stub fh1; + ATHandler at(&fh1, que, 0, ","); + AT_CellularDevice dev(&fh1); + AT_CTX_cid ctx(at, &dev); + + char ifn[5]; + EXPECT_TRUE(NULL == ctx.get_interface_name(ifn)); + + ctx.set_cid(1); + EXPECT_STREQ("ce1", ctx.get_interface_name(ifn)); + EXPECT_STREQ("ce1", ifn); +} + TEST_F(TestAT_CellularContext, attach) { EventQueue que; @@ -746,5 +774,4 @@ TEST_F(TestAT_CellularContext, get_timeout_for_operation) ctx1._op = -1; EXPECT_EQ(1800 * 1000, ctx1.do_op()); - } diff --git a/features/cellular/framework/AT/AT_CellularContext.cpp b/features/cellular/framework/AT/AT_CellularContext.cpp index d18918ec8f3..2d782a5c85a 100644 --- a/features/cellular/framework/AT/AT_CellularContext.cpp +++ b/features/cellular/framework/AT/AT_CellularContext.cpp @@ -244,7 +244,7 @@ char *AT_CellularContext::get_interface_name(char *interface_name) return NULL; } MBED_ASSERT(interface_name); - sprintf(interface_name, "ce%02d", _cid); + sprintf(interface_name, "ce%d", _cid); return interface_name; } From 3bf1979d7480caea1e6fbb02f87c30b747dbeafd Mon Sep 17 00:00:00 2001 From: Hugues Kamba Date: Wed, 11 Sep 2019 09:44:19 +0100 Subject: [PATCH 102/227] minimal-printf: Add capability to run floating point tests manually --- TESTS/mbed_platform/minimal-printf/compliance/README.md | 2 +- .../minimal-printf/compliance/test_config.json | 7 +++++++ 2 files changed, 8 insertions(+), 1 deletion(-) create mode 100644 TESTS/mbed_platform/minimal-printf/compliance/test_config.json diff --git a/TESTS/mbed_platform/minimal-printf/compliance/README.md b/TESTS/mbed_platform/minimal-printf/compliance/README.md index ee63ed63fdc..420f1251b35 100644 --- a/TESTS/mbed_platform/minimal-printf/compliance/README.md +++ b/TESTS/mbed_platform/minimal-printf/compliance/README.md @@ -6,6 +6,6 @@ This document describes how to run minimal-printf tests. You can use the following command to run tests: -`mbed test -m K64F -t GCC_ARM -n *printf* -v -c` +`mbed test -m K64F -t GCC_ARM -n *printf* -v -c --app-config TESTS/mbed_platform/minimal-printf/compliance/test_config.json` Do not use --profile minimal-printf so minimal-printf is not compared with itself. diff --git a/TESTS/mbed_platform/minimal-printf/compliance/test_config.json b/TESTS/mbed_platform/minimal-printf/compliance/test_config.json new file mode 100644 index 00000000000..084d441e0d0 --- /dev/null +++ b/TESTS/mbed_platform/minimal-printf/compliance/test_config.json @@ -0,0 +1,7 @@ +{ + "target_overrides": { + "*": { + "platform.minimal-printf-enable-floating-point": true + } + } +} From 1bed555921bded3d4fabf29e683a88e5bca06bc8 Mon Sep 17 00:00:00 2001 From: James Wang Date: Tue, 27 Aug 2019 19:50:01 +0800 Subject: [PATCH 103/227] set NRF52832 static_memory_defines true static_memory_defines controls the macro MBED_RAM_START AND MBED_RAM_SIZE when nrf52832 to use softdevice, it need MBED_RAM_START to set the true application ram start --- targets/targets.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/targets.json b/targets/targets.json index ae26b8da767..cca13e33b53 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -7332,7 +7332,7 @@ "MCU_NRF52832": { "inherits": ["Target"], "core": "Cortex-M4F", - "static_memory_defines": false, + "static_memory_defines": true, "macros": [ "BOARD_PCA10040", "NRF52", From 318f686ffc144ad140f40d13d121c615fa3d103c Mon Sep 17 00:00:00 2001 From: James Wang Date: Fri, 20 Sep 2019 11:34:35 +0800 Subject: [PATCH 104/227] remove NRF52840, NRF52832 static_memory_defines set static_memory_defines controls the macro MBED_RAM_START AND MBED_RAM_SIZE when nrf52840 to use softdevice, it need MBED_RAM_START to set the true application ram start default static_memory_defines is true, so just remove NRF52840 and NRF52832's set --- targets/targets.json | 2 -- 1 file changed, 2 deletions(-) diff --git a/targets/targets.json b/targets/targets.json index cca13e33b53..d818a664c79 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -7332,7 +7332,6 @@ "MCU_NRF52832": { "inherits": ["Target"], "core": "Cortex-M4F", - "static_memory_defines": true, "macros": [ "BOARD_PCA10040", "NRF52", @@ -7634,7 +7633,6 @@ "inherits": ["Target"], "components_add": ["QSPIF"], "core": "Cortex-M4F", - "static_memory_defines": false, "macros": [ "BOARD_PCA10056", "NRF52840_XXAA", From 95f04e104a3cf6a89740e1fdcf66c7543a6b43e2 Mon Sep 17 00:00:00 2001 From: Olli-Pekka Puolitaival Date: Mon, 16 Sep 2019 13:29:21 +0300 Subject: [PATCH 105/227] Make able to define build jobs amount when building examples --- tools/test/examples/examples.py | 10 ++++++++-- tools/test/examples/examples_lib.py | 4 ++-- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/tools/test/examples/examples.py b/tools/test/examples/examples.py index 59746336309..f8f7e69b50e 100644 --- a/tools/test/examples/examples.py +++ b/tools/test/examples/examples.py @@ -77,6 +77,13 @@ def main(): help=("build profile file"), metavar="profile") + compile_cmd.add_argument("-j", "--jobs", + dest='jobs', + metavar="NUMBER", + type=int, + default=0, + help="Number of concurrent jobs. Default: 0/auto (based on host machine's number of CPUs)") + compile_cmd.add_argument("-v", "--verbose", action="store_true", dest="verbose", @@ -136,8 +143,7 @@ def do_deploy(_, config, examples): def do_compile(args, config, examples): """Do the compile step""" - results = {} - results = lib.compile_repos(config, args.toolchains, args.mcu, args.profile, args.verbose, examples) + results = lib.compile_repos(config, args.toolchains, args.mcu, args.profile, args.verbose, examples, args.jobs) lib.print_summary(results) failures = lib.get_num_failures(results) print("Number of failures = %d" % failures) diff --git a/tools/test/examples/examples_lib.py b/tools/test/examples/examples_lib.py index df54d9a8e3c..4d57cdc1d8a 100644 --- a/tools/test/examples/examples_lib.py +++ b/tools/test/examples/examples_lib.py @@ -349,7 +349,7 @@ def status(message): return results -def compile_repos(config, toolchains, targets, profile, verbose, examples): +def compile_repos(config, toolchains, targets, profile, verbose, examples, jobs=0): """Compiles combinations of example programs, targets and compile chains. The results are returned in a [key: value] dictionary format: @@ -398,7 +398,7 @@ def compile_repos(config, toolchains, targets, profile, verbose, examples): valid_choices(example['toolchains'], toolchains), example['features']): - build_command = ["mbed-cli", "compile", "-t", toolchain, "-m", target] + (['-vv'] if verbose else []) + build_command = ["mbed-cli", "compile", "-t", toolchain, "-m", target, "-j", str(jobs)] + (['-vv'] if verbose else []) if profile: build_command.append("--profile") build_command.append(profile) From f95187599fc1c91d7147ba4f60a4d069c347108a Mon Sep 17 00:00:00 2001 From: Olli-Pekka Puolitaival Date: Tue, 17 Sep 2019 15:26:06 +0300 Subject: [PATCH 106/227] Fix documentation --- tools/test/examples/examples_lib.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/tools/test/examples/examples_lib.py b/tools/test/examples/examples_lib.py index 4d57cdc1d8a..c97183afb4f 100644 --- a/tools/test/examples/examples_lib.py +++ b/tools/test/examples/examples_lib.py @@ -367,7 +367,11 @@ def compile_repos(config, toolchains, targets, profile, verbose, examples, jobs= Args: config - the json object imported from the file. toolchains - List of toolchains to compile for. - results - results of the compilation stage. + targets - list of target names + profile - build profile path or name if in default place + verbose - enabling verbose + examples - List of examples to be build + jobs - Number of compile jobs """ results = {} From 02da070162e29e8b0d1f2a54997b3a396d3da4c1 Mon Sep 17 00:00:00 2001 From: Kyle Kearney Date: Mon, 16 Sep 2019 11:04:45 -0700 Subject: [PATCH 107/227] Fix incorrect integer division in analogout_read Replace with multiplication by the floating point reciprocal, to produce a floating point result while being more efficient than floating point division. Addresses the issue raised by kjbracey-arm in https://github.com/ARMmbed/mbed-os/pull/11324#pullrequestreview-282433989 --- targets/TARGET_Cypress/TARGET_PSOC6/cy_analogout_api.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/cy_analogout_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/cy_analogout_api.c index 44a48e987c2..b455fa57bc9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/cy_analogout_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/cy_analogout_api.c @@ -51,7 +51,7 @@ void analogout_write_u16(dac_t *obj, uint16_t value) float analogout_read(dac_t *obj) { - return analogout_read_u16(obj) / UINT16_MAX; + return analogout_read_u16(obj) * (1.0f / UINT16_MAX); } uint16_t analogout_read_u16(dac_t *obj) From 0a54b6900eba1017075059d0a8bde761112821d1 Mon Sep 17 00:00:00 2001 From: Kyle Kearney Date: Mon, 16 Sep 2019 12:08:05 -0700 Subject: [PATCH 108/227] Update to latest HAL - Add const and static qualifiers in places where they are applicable but missing - Remove headers for drivers that aren't implemented yet - Misc minor bugfixes --- .../psoc6csp/hal/include/cyhal_comp.h | 158 ---------------- .../psoc6csp/hal/include/cyhal_dma.h | 162 ---------------- .../psoc6csp/hal/include/cyhal_i2s.h | 176 ------------------ .../hal/include/cyhal_implementation.h | 45 ----- .../psoc6csp/hal/include/cyhal_opamp.h | 88 --------- .../psoc6csp/hal/include/cyhal_pdmpcm.h | 173 ----------------- .../psoc6csp/hal/include/cyhal_scb_common.h | 4 +- .../psoc6csp/hal/include/cyhal_utils.h | 2 +- .../TARGET_PSOC6/psoc6csp/hal/src/cyhal_adc.c | 2 +- .../psoc6csp/hal/src/cyhal_crypto_common.c | 2 +- .../TARGET_PSOC6/psoc6csp/hal/src/cyhal_dac.c | 38 ++-- .../psoc6csp/hal/src/cyhal_hwmgr.c | 1 + .../TARGET_PSOC6/psoc6csp/hal/src/cyhal_i2c.c | 2 + .../TARGET_PSOC6/psoc6csp/hal/src/cyhal_pwm.c | 4 +- .../psoc6csp/hal/src/cyhal_qspi.c | 4 +- .../psoc6csp/hal/src/cyhal_scb_common.c | 4 +- .../psoc6csp/hal/src/cyhal_sdhc.c | 28 ++- .../TARGET_PSOC6/psoc6csp/hal/src/cyhal_spi.c | 8 +- .../psoc6csp/hal/src/cyhal_timer.c | 8 +- .../psoc6csp/hal/src/cyhal_uart.c | 2 +- .../psoc6csp/hal/src/cyhal_udb_sdio.c | 6 +- .../psoc6csp/hal/src/cyhal_usb_dev.c | 10 +- 22 files changed, 61 insertions(+), 866 deletions(-) delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_comp.h delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dma.h delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_i2s.h delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_implementation.h delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_opamp.h delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pdmpcm.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_comp.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_comp.h deleted file mode 100644 index b2e3269beb9..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_comp.h +++ /dev/null @@ -1,158 +0,0 @@ -/***************************************************************************//** -* \file cyhal_comp.h -* -* Provides a high level interface for interacting with the Cypress Comparator. -* This interface abstracts out the chip specific details. -* If any chip specific functionality is necessary, or performance is critical, -* the low level functions can be used directly. -* -******************************************************************************** -* \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -/** -* \addtogroup group_hal_comp COMP (Comparator) -* \ingroup group_hal -* \{ -* High level interface for interacting with the Cypress Comparator. -* -* \defgroup group_hal_comp_macros Macros -* \defgroup group_hal_comp_functions Functions -* \defgroup group_hal_comp_data_structures Data Structures -* \defgroup group_hal_comp_enums Enumerated Types -*/ - -#pragma once - -#include -#include -#include "cy_result.h" -#include "cyhal_hw_types.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/** -* \addtogroup group_hal_comp_enums -* \{ -*/ - -/** Comparator interrupt triggers */ -typedef enum { - CYHAL_COMP_IRQ_NONE, //!< Interrupts disabled - CYHAL_COMP_IRQ_RISE, //!< Rising edge - CYHAL_COMP_IRQ_FALL, //!< Falling edge -} cyhal_comp_irq_event_t; - -/** Comparator power options */ -typedef enum { - CYHAL_COMP_POWER_OFF, //!< Block is turned off - CYHAL_COMP_POWER_LOW, //!< Block runs in low power/speed mode - CYHAL_COMP_POWER_MEDIUM, //!< Block runs in medium power/speed mode - CYHAL_COMP_POWER_HIGH, //!< Block runs in high power/speed mode -} cyhal_comp_power_t; - -/** Comparator output modes */ -typedef enum { - CYHAL_COMP_OUTPUT_PULSE, //!< Pulse output - CYHAL_COMP_OUTPUT_DIRECT, //!< Level output directly - CYHAL_COMP_OUTPUT_SYNC, //!< Level output after synchronous edge detection -} cyhal_comp_output_t; - -/** \} group_hal_comp_enums */ - - -/** -* \addtogroup group_hal_comp_data_structures -* \{ -*/ - -/** Configuration options for the comparator */ -typedef struct -{ - cyhal_comp_power_t power; //!< Power mode to operate in (0=off, 1=low, 2=medium, 3=high) - cyhal_comp_output_t output; //!< Output configuration (0=pulse, 1=direct, 2=sync) - bool hysteresis; //!< Should this use hysteresis - bool deepsleep; //!< Does this need to operate in deepsleep -} cyhal_comp_config_t; - -/** Handler for comparator interrupts */ -typedef void (*cyhal_comp_irq_handler_t)(void *handler_arg, cyhal_comp_irq_event_t event); - -/** \} group_hal_comp_data_structures */ - - -/** -* \addtogroup group_hal_comp_functions -* \{ -*/ - -/** Initialize the comparator peripheral. - * - * @param[out] obj The comparator object - * @param[in] vinp The vplus pin - * @param[in] vinm The vminus pin - * @param[in] vout The vout pin - * @return The status of the init request - */ -cy_rslt_t cyhal_comp_init(cyhal_comp_t *obj, cyhal_gpio_t vinp, cyhal_gpio_t vinm, cyhal_gpio_t vout); - -/** Release the comparator peripheral. - * - * @param[in,out] obj The comparator object - */ -void cyhal_comp_free(cyhal_comp_t *obj); - -/** Reconfigure the comparator object - * - * @param[in,out] obj The comparator object - * @param[in] cfg Configuration to apply to the comparator - * @return The status of the power request - */ -cy_rslt_t cyhal_comp_configure(cyhal_comp_t *obj, const cyhal_comp_config_t cfg); - -/** Gets the result of the comparator object - * - * @param[in] obj The comparator object - * @return The comparator output state - */ -bool cyhal_comp_output(cyhal_comp_t *obj); - -/** Register/clear an interrupt handler for the comparator toggle IRQ event - * - * @param[in] obj The comparator object - * @param[in] handler The function to call when the specified event happens - * @param[in] handler_arg Generic argument that will be provided to the handler when called - */ -void cyhal_comp_register_irq(cyhal_comp_t *obj, cyhal_comp_irq_handler_t handler, void *handler_arg); - -/** Enable or Disable the comparator IRQ - * - * @param[in] obj The comparator object - * @param[in] event The comparator IRQ event - * @param[in] enable True to turn on interrupts, False to turn off - */ -void cyhal_cyhal_comp_irq_enable(cyhal_comp_t *obj, cyhal_comp_irq_event_t event, bool enable); - -/** \} group_hal_comp_functions */ - -#if defined(__cplusplus) -} -#endif - -/** \} group_hal_comp */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dma.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dma.h deleted file mode 100644 index 0043a545bdf..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dma.h +++ /dev/null @@ -1,162 +0,0 @@ -/***************************************************************************//** -* \file cyhal_dma.h -* -* \brief -* Provides a high level interface for interacting with the Cypress DMA. -* This interface abstracts out the chip specific details. If any chip specific -* functionality is necessary, or performance is critical the low level functions -* can be used directly. -* -******************************************************************************** -* \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -/** -* \addtogroup group_hal_dma DMA (Direct Memory Access) -* \ingroup group_hal -* \{ -* High level interface for interacting with the Cypress DMA. -* -* \defgroup group_hal_dma_macros Macros -* \defgroup group_hal_dma_functions Functions -* \defgroup group_hal_dma_data_structures Data Structures -* \defgroup group_hal_dma_enums Enumerated Types -*/ - -#pragma once - -#include -#include -#include "cy_result.h" -#include "cyhal_hw_types.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/** -* \addtogroup group_hal_dma_enums -* \{ -*/ - -/** Direction for DMA transfers */ -typedef enum -{ - CYHAL_DMA_DIRECTION_MEM2MEM, //!< Memory to memory - CYHAL_DMA_DIRECTION_MEM2PERIPH, //!< Memory to peripheral - CYHAL_DMA_DIRECTION_PERIPH2MEM, //!< Peripheral to memory -} cyhal_dma_direction_t; - -/** DMA interrupt triggers */ -typedef enum { - /** TODO: Fill in */ - CYHAL_DMA_TBD, -} cyhal_dma_irq_event_t; - -/** \} group_hal_dma_enums */ - - -/** -* \addtogroup group_hal_dma_data_structures -* \{ -*/ - -/** Initial configuration of a DMA channel */ -typedef struct -{ - uint32_t src_addr; //!< source address - int8_t src_increment; //!< source address auto increment amount - uint32_t dst_addr; //!< destination address - int8_t dst_increment; //!< destination address auto increment amount - uint32_t length; //!< length of data to be transferred - uint8_t beat_size; //!< beat size to be set (8, 16, 32) - //cyhal_source_t trigger_source; //!< Source signal for initiating the DMA transfer -} cyhal_dma_cfg_t; - -/** Handler for DMA interrupts */ -typedef void (*cyhal_dma_irq_handler_t)(void *handler_arg, cyhal_dma_irq_event_t event); - -/** \} group_hal_dma_data_structures */ - - -/** -* \addtogroup group_hal_dma_functions -* \{ -*/ - -/** Initialize the DMA peripheral - * - * @param[out] obj The DMA object to initialize - * @param[in] priority The priority of this DMA operation relative to others - * @param[in] direction The direction memory is copied - * @return The status of the init request - */ -cy_rslt_t cyhal_dma_init(cyhal_dma_t *obj, uint8_t priority, cyhal_dma_direction_t direction); - -/** Release the DMA object - * - * @param[in,out] obj The DMA object - */ -void cyhal_dma_free(cyhal_dma_t *obj); - -/** Setup a DMA descriptor for specified resource - * - * @param[in] obj The DMA object - * @param[in] cfg Configuration prameters for the transfer - * @return The status of the setup_transfer request - */ -cy_rslt_t cyhal_dma_setup_transfer(cyhal_dma_t *obj, const cyhal_dma_cfg_t *cfg); - -/** Start DMA transfer - * - * Kick starts transfer in DMA channel with specified channel id - * @param[in] obj The DMA object - * @return The status of the start_transfer request - */ -cy_rslt_t cyhal_dma_start_transfer(cyhal_dma_t *obj); - -/** DMA channel busy check - * - * To check whether DMA channel is busy with a job or not - * @param[in] obj The DMA object - * @return Is the DMA object being used - */ -bool cyhal_dma_busy(cyhal_dma_t *obj); - -/** The DMA interrupt handler registration - * - * @param[in] obj The DMA object - * @param[in] handler The callback handler which will be invoked when the interrupt fires - * @param[in] handler_arg Generic argument that will be provided to the handler when called - */ -void cyhal_dma_register_irq(cyhal_dma_t *obj, cyhal_dma_irq_handler_t handler, void *handler_arg); - -/** Configure DMA interrupt enablement. - * - * @param[in] obj The DMA object - * @param[in] event The DMA IRQ type - * @param[in] enable True to turn on interrupts, False to turn off - */ -void cyhal_dma_irq_enable(cyhal_dma_t *obj, cyhal_dma_irq_event_t event, bool enable); - -/** \} group_hal_dma_functions */ - -#if defined(__cplusplus) -} -#endif - -/** \} group_hal_dma */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_i2s.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_i2s.h deleted file mode 100644 index 3ee37e8f25a..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_i2s.h +++ /dev/null @@ -1,176 +0,0 @@ -/***************************************************************************//** -* \file cyhal_i2s.h -* -* \brief -* Provides a high level interface for interacting with the Cypress I2S. -* This interface abstracts out the chip specific details. If any chip specific -* functionality is necessary, or performance is critical the low level functions -* can be used directly. -* -******************************************************************************** -* \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -/** -* \addtogroup group_hal_i2s I2S (Inter-IC Sound) -* \ingroup group_hal -* \{ -* High level interface for interacting with the Cypress I2S. -* -* \defgroup group_hal_i2s_macros Macros -* \defgroup group_hal_i2s_functions Functions -* \defgroup group_hal_i2s_data_structures Data Structures -* \defgroup group_hal_i2s_enums Enumerated Types -*/ - -#pragma once - -#include -#include -#include "cy_result.h" -#include "cyhal_hw_types.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/** -* \addtogroup group_hal_i2s_enums -* \{ -*/ - -/** I2S interrupt triggers */ -typedef enum { - /** TODO: Fill in */ - CYHAL_I2S_TBD, -} cyhal_i2s_irq_t; - -/** \} group_hal_i2s_enums */ - - -/** -* \addtogroup group_hal_i2s_data_structures -* \{ -*/ - -/** Handler for SPI interrupts */ -typedef void (*cyhal_i2s_irq_handler_t)(void *handler_arg, cyhal_i2s_irq_t event); - -/** \} group_hal_i2s_data_structures */ - - -/** -* \addtogroup group_hal_i2s_functions -* \{ -*/ - -/** Initialize the I2S peripheral. It sets the default parameters for I2S - * peripheral, and configures its specifieds pins. - * - * @param[out] obj The I2S object - * @param[in] tx_sck The transmit clock pin - * @param[in] tx_ws The transmit word select pin - * @param[in] tx_sdo The data out pin - * @param[in] rx_sck The receive clock pin - * @param[in] rx_ws The receive word select pin - * @param[in] rx_sdi The data in pin - * @return The status of the init request - */ -cy_rslt_t cyhal_i2s_init(cyhal_i2s_t *obj, cyhal_gpio_t tx_sck, cyhal_gpio_t tx_ws, cyhal_gpio_t tx_sdo, cyhal_gpio_t rx_sck, cyhal_gpio_t rx_ws, cyhal_gpio_t rx_sdi); - -/** Deinitialize the i2s object - * - * @param[in,out] obj The i2s object - */ -void cyhal_i2s_free(cyhal_i2s_t *obj); - -/** Configure the I2S frequency - * - * @param[in] obj The I2S object - * @param[in] hz Frequency in Hz - * @return The status of the frequency request - */ -cy_rslt_t cyhal_i2s_frequency(cyhal_i2s_t *obj, int hz); - -/** Configure I2S as slave or master. - * @param[in] obj The I2S object - * @param[in] is_slave Enable hardware as a slave (true) or master (false) - * @return The status of the mode request - */ -cy_rslt_t cyhal_i2s_mode(cyhal_i2s_t *obj, int is_slave); - -/** Blocking reading data - * - * @param[in] obj The I2S object - * @param[out] data The buffer for receiving - * @param[in,out] length in - Number of bytes to read, out - number of bytes read - * @return The status of the read request - */ -cy_rslt_t cyhal_i2s_read(cyhal_i2s_t *obj, uint8_t *data, size_t *length); - -/** Blocking sending data - * - * @param[in] obj The I2S object - * @param[in] data The buffer for sending - * @param[in] length Number of bytes to write - * @param[in] stop Stop to be generated after the transfer is done - * @return The status of the write request - */ -cy_rslt_t cyhal_i2s_write(cyhal_i2s_t *obj, const uint8_t *data, size_t length, bool stop); - -/** Start I2S asynchronous transfer - * - * @param[in] obj The I2S object - * @param[in] tx The transmit buffer - * @param[in,out] tx_length in - The number of bytes to transmit, out - The number of bytes actually transmitted - * @param[out] rx The receive buffer - * @param[in,out] rx_length in - The number of bytes to receive, out - The number of bytes actually received - * @return The status of the transfer_async request - */ -cy_rslt_t cyhal_i2s_transfer_async(cyhal_i2s_t *obj, const void *tx, size_t *tx_length, void *rx, size_t *rx_length); - -/** Abort I2S asynchronous transfer - * - * This function does not perform any check - that should happen in upper layers. - * @param[in] obj The I2S object - * @return The status of the abort_async request - */ -cy_rslt_t cyhal_i2s_abort_async(cyhal_i2s_t *obj); - -/** The I2S interrupt handler registration - * - * @param[in] obj The I2S object - * @param[in] handler The callback handler which will be invoked when the interrupt fires - * @param[in] handler_arg Generic argument that will be provided to the handler when called - */ -void cyhal_i2s_register_irq(cyhal_i2s_t *obj, cyhal_i2s_irq_handler_t handler, void *handler_arg); - -/** Configure I2S interrupt. This function is used for word-approach - * - * @param[in] obj The I2S object - * @param[in] event The I2S IRQ type - * @param[in] enable True to turn on interrupts, False to turn off - */ -void cyhal_i2s_irq_enable(cyhal_i2s_t *obj, cyhal_i2s_irq_t event, bool enable); - -/** \} group_hal_i2s_functions */ - -#if defined(__cplusplus) -} -#endif - -/** \} group_hal_i2s */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_implementation.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_implementation.h deleted file mode 100644 index 556ce1ca7c6..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_implementation.h +++ /dev/null @@ -1,45 +0,0 @@ -/***************************************************************************//** -* \file cyhal_implementation.h -* -* \brief -* Provides references for the PSoC 6 specific implementation of the HAL drivers. -* This includes references to implementation specific header files and any -* supporting data types. This file should not be used directly. It should only -* be referenced by HAL drivers to pull in the implementation specific code. -* -******************************************************************************** -* \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -/** -* \addtogroup group_hal_psoc6 PSoC 6 HAL Implementation -* \{ -* PSoC 6 specific implementation of the HAL drivers -* \} group_hal_psoc6 -*/ - -#pragma once - -#include "cy_pdl.h" -#include "cyhal.h" -#include "cyhal_hw_types.h" -#include "cyhal_crc_impl.h" -#include "cyhal_gpio_impl.h" -#include "cyhal_scb_common.h" -#include "cyhal_utils.h" -#include "cyhal_system_impl.h" -#include "cyhal_trng_impl.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_opamp.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_opamp.h deleted file mode 100644 index 7b55ea5f8ea..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_opamp.h +++ /dev/null @@ -1,88 +0,0 @@ -/***************************************************************************//** -* \file cyhal_opamp.h -* -* \brief -* Provides a high level interface for interacting with the Cypress OpAmp. -* This interface abstracts out the chip specific details. If any chip specific -* functionality is necessary, or performance is critical the low level functions -* can be used directly. -* -******************************************************************************** -* \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -/** -* \addtogroup group_hal_opamp OPAMP (Operational Amplifier) -* \ingroup group_hal -* \{ -* High level interface for interacting with the Cypress OpAmp. -* -* \defgroup group_hal_opamp_macros Macros -* \defgroup group_hal_opamp_functions Functions -* \defgroup group_hal_opamp_data_structures Data Structures -* \defgroup group_hal_opamp_enums Enumerated Types -*/ - -#pragma once - -#include -#include -#include "cy_result.h" -#include "cyhal_hw_types.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/** -* \addtogroup group_hal_opamp_functions -* \{ -*/ - -/** Initialize the opamp peripheral. - * If vinp is NULL, it will initialize in follower mode. - * - * @param[out] obj The opamp object - * @param[in] vinp The vplus pin - * @param[in] vinm The vminus pin - * @param[in] vout The vout pin - * @return The status of the init request - */ -cy_rslt_t cyhal_opamp_init(cyhal_opamp_t *obj, cyhal_gpio_t vinp, cyhal_gpio_t vinm, cyhal_gpio_t vout); - -/** Release the opamp peripheral. - * - * @param[in,out] obj The opamp object - */ -void cyhal_opamp_free(cyhal_opamp_t *obj); - -/** Reconfigure the opamp object - * - * @param[in,out] obj The opamp object - * @param[in] power Power mode to operate in (0=off, 1=low, 2=medium, 3=high) - * @param[in] deepsleep Does this need to operate in deepsleep - * @return The status of the power request - */ -cy_rslt_t cyhal_opamp_power(cyhal_opamp_t *obj, uint8_t power, bool deepsleep); - -/** \} group_hal_opamp_functions */ - -#if defined(__cplusplus) -} -#endif - -/** \} group_hal_opamp */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pdmpcm.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pdmpcm.h deleted file mode 100644 index d4805f8855e..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pdmpcm.h +++ /dev/null @@ -1,173 +0,0 @@ -/***************************************************************************//** -* \file cyhal_pdmpcm.h -* -* \brief -* Provides a high level interface for interacting with the Cypress PDM/PCM. -* This interface abstracts out the chip specific details. If any chip specific -* functionality is necessary, or performance is critical the low level functions -* can be used directly. -* -******************************************************************************** -* \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -/** -* \addtogroup group_hal_pdmpcm PDM/PCM (PDM-PCM Converter) -* \ingroup group_hal -* \{ -* High level interface for interacting with the Cypress PDM/PCM. -* -* \defgroup group_hal_pdmpcm_macros Macros -* \defgroup group_hal_pdmpcm_functions Functions -* \defgroup group_hal_pdmpcm_data_structures Data Structures -* \defgroup group_hal_pdmpcm_enums Enumerated Types -*/ - -#pragma once - -#include -#include -#include "cy_result.h" -#include "cyhal_hw_types.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/** -* \addtogroup group_hal_pdmpcm_enums -* \{ -*/ - -/** PDM/PCM interrupt triggers */ -typedef enum { - /** TODO: Fill in */ - CY_PDM_PCM_TBD, -} cyhal_pdm_pcm_irq_event_t; - -/** \} group_hal_pdmpcm_enums */ - -/** -* \addtogroup group_hal_pdmpcm_data_structures -* \{ -*/ - -/** Describes the current configuration of a PDM/PCM */ -typedef struct -{ - /** TODO: define */ - void * cfg; -} cyhal_pdm_pcm_cfg_t; - -/** Handler for PDM/PCM interrupts */ -typedef void (*cyhal_pdm_pcm_irq_handler_t)(void *handler_arg, cyhal_pdm_pcm_irq_event_t event); - -/** \} group_hal_pdmpcm_data_structures */ - - -/** -* \addtogroup group_hal_pdmpcm_functions -* \{ -*/ - -/** Initialize the PDM/PCM peripheral - * - * Configures the pins used by PDM/PCM converter, sets a default format and frequency, and enables the peripheral - * @param[out] obj The PDM/PCM object to initialize - * @param[in] in The pin to use for PDM input - * @param[in] clk The pin to use for PDM clock output - * @return The status of the init request - */ -cy_rslt_t cyhal_pdm_pcm_init(cyhal_pdm_pcm_t *obj, cyhal_gpio_t in, cyhal_gpio_t clk); - -/** Release a PDM/PCM object - * - * Return the peripheral, pins and clock owned by the PDM/PCM object to their reset state - * @param[in,out] obj The PDM/PCM object to deinitialize - */ -void cyhal_pdm_pcm_free(cyhal_pdm_pcm_t *obj); - -/** Updates the configuration of the PDM/PCM object - * - * @param[inout] obj The PDM/PCM object to configure - * @param[in] cfg The configuration of the PDM/PCM - * @return The status of the format request - */ -cy_rslt_t cyhal_pdm_pcm_config(cyhal_pdm_pcm_t *obj, const cyhal_pdm_pcm_cfg_t *cfg); - -/** Clears the FIFO - * - * @param[in] obj The PDM/PCM peripheral to use for sending - * @return The status of the clear request - */ -cy_rslt_t cyhal_pdm_pcm_clear(cyhal_pdm_pcm_t *obj); - -/** Reads a block out of the FIFO - * - * @param[in] obj The PDM/PCM peripheral to use for sending - * @param[out] data Pointer to the byte-array of data to read from the device - * @param[in,out] length Number of bytes to read, updated with the number actually read - * @return The status of the read request - */ -cy_rslt_t cyhal_pdm_pcm_read(cyhal_pdm_pcm_t *obj, uint8_t *data, uint32_t *length); - -/** Begin the PDM/PCM transfer - * - * @param[in] obj The PDM/PCM object that holds the transfer information - * @param[out] data The receive buffer - * @param[in,out] length Number of bytes to read, updated with the number actually read - * @return The status of the read_async request - */ -cy_rslt_t cyhal_pdm_pcm_read_async(cyhal_pdm_pcm_t *obj, void *data, size_t length); - -/** Checks if the specified PDM/PCM peripheral is in use - * - * @param[in] obj The PDM/PCM peripheral to check - * @return Indication of whether the PDM/PCM is still transmitting - */ -bool cyhal_pdm_pcm_is_busy(cyhal_pdm_pcm_t *obj); - -/** Abort an PDM/PCM transfer - * - * @param[in] obj The PDM/PCM peripheral to stop - * @return The status of the abort_async request - */ -cy_rslt_t cyhal_pdm_pcm_abort_async(cyhal_pdm_pcm_t *obj); - -/** The PDM/PCM interrupt handler registration - * - * @param[in] obj The PDM/PCM object - * @param[in] handler The callback handler which will be invoked when the interrupt fires - * @param[in] handler_arg Generic argument that will be provided to the handler when called - */ -void cyhal_pdm_pcm_register_irq(cyhal_pdm_pcm_t *obj, cyhal_pdm_pcm_irq_handler_t handler, void *handler_arg); - -/** Configure PDM/PCM interrupt enablement. - * - * @param[in] obj The PDM/PCM object - * @param[in] event The PDM/PCM IRQ type - * @param[in] enable True to turn on interrupts, False to turn off - */ -void cyhal_pdm_pcm_irq_enable(cyhal_pdm_pcm_t *obj, cyhal_pdm_pcm_irq_event_t event, bool enable); - -/** \} group_hal_pdmpcm_functions */ - -#if defined(__cplusplus) -} -#endif - -/** \} group_hal_pdmpcm */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_scb_common.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_scb_common.h index 6fcd9e73547..27c8e1a561f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_scb_common.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_scb_common.h @@ -51,9 +51,9 @@ extern "C" { */ /** The start address of the SCB blocks */ -extern CySCB_Type* CYHAL_SCB_BASE_ADDRESSES[CY_IP_MXSCB_INSTANCES]; +extern CySCB_Type* const CYHAL_SCB_BASE_ADDRESSES[CY_IP_MXSCB_INSTANCES]; /** The interrupt number of the SCB blocks. */ -extern IRQn_Type CYHAL_SCB_IRQ_N[CY_IP_MXSCB_INSTANCES]; +extern const IRQn_Type CYHAL_SCB_IRQ_N[CY_IP_MXSCB_INSTANCES]; /** The configuration structs for the resource in use on each SCB block (e.g. cyhal_i2c_t) */ extern void *cyhal_scb_config_structs[CY_IP_MXSCB_INSTANCES]; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_utils.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_utils.h index ab9f9b6532b..2bebb64e133 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_utils.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_utils.h @@ -79,7 +79,7 @@ extern "C" { */ static inline uint32_t cyhal_divider_value(uint32_t frequency, uint32_t frac_bits) { - return ((cy_PeriClkFreqHz * (1 << frac_bits)) + (frequency / 2)) / frequency - 1; + return ((Cy_SysClk_ClkPeriGetFrequency() * (1 << frac_bits)) + (frequency / 2)) / frequency - 1; } /** Converts the provided gpio pin to a resource instance object diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_adc.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_adc.c index 7311cabf118..4072f59864d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_adc.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_adc.c @@ -237,7 +237,7 @@ cy_rslt_t cyhal_adc_init(cyhal_adc_t *obj, cyhal_gpio_t pin, const cyhal_clock_d { if(obj->dedicated_clock) { - uint32_t div = cy_PeriClkFreqHz / DESIRED_DIVIDER; + uint32_t div = Cy_SysClk_ClkPeriGetFrequency() / DESIRED_DIVIDER; if (0 == div || CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphSetDivider(obj->clock.div_type, obj->clock.div_num, div - 1) || CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphEnableDivider(obj->clock.div_type, obj->clock.div_num)) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_crypto_common.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_crypto_common.c index da73153d068..2397ba0d8b3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_crypto_common.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_crypto_common.c @@ -33,7 +33,7 @@ extern "C" { #endif -static CRYPTO_Type* CYHAL_CRYPTO_BASE_ADDRESSES[CYHAL_CRYPTO_INST_COUNT] = +static CRYPTO_Type* const CYHAL_CRYPTO_BASE_ADDRESSES[CYHAL_CRYPTO_INST_COUNT] = { #ifdef CRYPTO CRYPTO, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_dac.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_dac.c index 72178689eb8..f0805d15eec 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_dac.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_dac.c @@ -56,25 +56,25 @@ static CTDAC_Type *const cyhal_ctdac_base[] = { #endif }; -const cy_stc_ctdac_config_t CYHAL_CTDAC_DEFAULT_CONFIG = - { - .refSource = CY_CTDAC_REFSOURCE_VDDA, - .formatMode = CY_CTDAC_FORMAT_UNSIGNED, - .updateMode = CY_CTDAC_UPDATE_DIRECT_WRITE, - .deglitchMode = CY_CTDAC_DEGLITCHMODE_UNBUFFERED, - .outputMode = CY_CTDAC_OUTPUT_VALUE, - .outputBuffer = CY_CTDAC_OUTPUT_UNBUFFERED, - .deepSleep = CY_CTDAC_DEEPSLEEP_DISABLE, - .deglitchCycles = 0, - .value = 0, - .nextValue = 0, - .enableInterrupt = true, - .configClock = false, - // The following values are simply placeholders because configClock is false - .dividerType = CY_SYSCLK_DIV_8_BIT, - .dividerNum = 0, - .dividerIntValue = 0, - .dividerFracValue = 0, +static const cy_stc_ctdac_config_t CYHAL_CTDAC_DEFAULT_CONFIG = +{ + .refSource = CY_CTDAC_REFSOURCE_VDDA, + .formatMode = CY_CTDAC_FORMAT_UNSIGNED, + .updateMode = CY_CTDAC_UPDATE_DIRECT_WRITE, + .deglitchMode = CY_CTDAC_DEGLITCHMODE_UNBUFFERED, + .outputMode = CY_CTDAC_OUTPUT_VALUE, + .outputBuffer = CY_CTDAC_OUTPUT_UNBUFFERED, + .deepSleep = CY_CTDAC_DEEPSLEEP_DISABLE, + .deglitchCycles = 0, + .value = 0, + .nextValue = 0, + .enableInterrupt = true, + .configClock = false, + // The following values are simply placeholders because configClock is false + .dividerType = CY_SYSCLK_DIV_8_BIT, + .dividerNum = 0, + .dividerIntValue = 0, + .dividerFracValue = 0, }; /******************************************************************************* diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_hwmgr.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_hwmgr.c index 237f043e813..1d66606cbab 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_hwmgr.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_hwmgr.c @@ -624,6 +624,7 @@ void cyhal_hwmgr_free(const cyhal_resource_inst_t* obj) uint32_t state = cyhal_system_critical_section_enter(); cy_rslt_t rslt = cyhal_clear_bit(cyhal_used, obj->type, obj->block_num, obj->channel_num); CY_ASSERT(CY_RSLT_SUCCESS == rslt); + (void)rslt; //Avoid warning about unused variable in Release builds cyhal_system_critical_section_exit(state); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_i2c.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_i2c.c index 4b979bb47bd..3d9d26e311c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_i2c.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_i2c.c @@ -82,6 +82,8 @@ static void cyhal_i2c_irq_handler(void) if (obj->async) { + /* This code is part of cyhal_i2c_master_transfer_async() API functionality */ + /* cyhal_i2c_master_transfer_async() API uses this interrupt handler for RX Transfer */ if (0 == (Cy_SCB_I2C_MasterGetStatus(obj->base, &obj->context) & CY_SCB_I2C_MASTER_BUSY)) { if (obj->tx_config.bufferSize) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_pwm.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_pwm.c index 1deba28727e..844ea2239df 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_pwm.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_pwm.c @@ -90,7 +90,7 @@ cy_rslt_t cyhal_pwm_init(cyhal_pwm_t *obj, cyhal_gpio_t pin, const cyhal_clock_d en_clk_dst_t pclk = (en_clk_dst_t)(CYHAL_TCPWM_DATA[obj->resource.block_num].clock_dst + obj->resource.channel_num); if (NULL != clk) { - obj->clock_hz = cy_PeriClkFreqHz / (1 + Cy_SysClk_PeriphGetDivider(clk->div_type, clk->div_num)); + obj->clock_hz = Cy_SysClk_ClkPeriGetFrequency() / (1 + Cy_SysClk_PeriphGetDivider(clk->div_type, clk->div_num)); if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphAssignDivider(pclk, clk->div_type, clk->div_num)) result = CYHAL_PWM_RSLT_FAILED_CLOCK_INIT; } @@ -105,7 +105,7 @@ cy_rslt_t cyhal_pwm_init(cyhal_pwm_t *obj, cyhal_gpio_t pin, const cyhal_clock_d result = CYHAL_PWM_RSLT_FAILED_CLOCK_INIT; else { - obj->clock_hz = cy_PeriClkFreqHz / div; + obj->clock_hz = Cy_SysClk_ClkPeriGetFrequency() / div; } } } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_qspi.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_qspi.c index 238bf1a3e2f..2842e623470 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_qspi.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_qspi.c @@ -83,7 +83,7 @@ static const cy_stc_smif_config_t default_qspi_config = }; /* List of available QSPI instances */ -SMIF_Type *smif_base_addresses[CY_IP_MXSMIF_INSTANCES] = +static SMIF_Type *const smif_base_addresses[CY_IP_MXSMIF_INSTANCES] = { #ifdef SMIF0 SMIF0, @@ -91,7 +91,7 @@ SMIF_Type *smif_base_addresses[CY_IP_MXSMIF_INSTANCES] = }; /* List of available QSPI interrupt sources */ -IRQn_Type CYHAL_QSPI_IRQ_N[CY_IP_MXSMIF_INSTANCES] = +static const IRQn_Type CYHAL_QSPI_IRQ_N[CY_IP_MXSMIF_INSTANCES] = { #ifdef SMIF0 smif_interrupt_IRQn, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_scb_common.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_scb_common.c index 20448a187dc..2b640f5e650 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_scb_common.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_scb_common.c @@ -31,7 +31,7 @@ extern "C" { #endif -CySCB_Type* CYHAL_SCB_BASE_ADDRESSES[CY_IP_MXSCB_INSTANCES] = +CySCB_Type* const CYHAL_SCB_BASE_ADDRESSES[CY_IP_MXSCB_INSTANCES] = { #ifdef SCB0 SCB0, @@ -83,7 +83,7 @@ CySCB_Type* CYHAL_SCB_BASE_ADDRESSES[CY_IP_MXSCB_INSTANCES] = #endif }; -IRQn_Type CYHAL_SCB_IRQ_N[CY_IP_MXSCB_INSTANCES] = +const IRQn_Type CYHAL_SCB_IRQ_N[CY_IP_MXSCB_INSTANCES] = { #ifdef SCB0 scb_0_interrupt_IRQn, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_sdhc.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_sdhc.c index b3bc8c5ad97..da2f6108f35 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_sdhc.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_sdhc.c @@ -157,7 +157,7 @@ static SDHC_Type * const CYHAL_SDHC_BASE_ADDRESSES[CY_IP_MXSDHC_INSTANCES] = }; /* List of available SDHC HF clocks */ -static uint8_t const CYHAL_SDHC_HF_CLOCKS[CY_IP_MXSDHC_INSTANCES] = +static const uint8_t CYHAL_SDHC_HF_CLOCKS[CY_IP_MXSDHC_INSTANCES] = { #ifdef SDHC0 4, @@ -170,7 +170,7 @@ static uint8_t const CYHAL_SDHC_HF_CLOCKS[CY_IP_MXSDHC_INSTANCES] = /* List of available SDHC interrupt sources */ -static IRQn_Type const CYHAL_SDHC_IRQ_N[CY_IP_MXSDHC_INSTANCES] = +static const IRQn_Type CYHAL_SDHC_IRQ_N[CY_IP_MXSDHC_INSTANCES] = { #ifdef SDHC0 sdhc_0_interrupt_general_IRQn, @@ -208,7 +208,7 @@ static void *cyhal_sd_config_structs[CY_IP_MXSDHC_INSTANCES]; /* Structure to map SDHC events on SDHC interrupts */ -const uint32_t eventMap[SDHC_EVENTS_NUM][SDHC_EVENTS_MAP_NUM] = +static const uint32_t eventMap[SDHC_EVENTS_NUM][SDHC_EVENTS_MAP_NUM] = { { (uint32_t)CYHAL_SDHC_CMD_COMPLETE, (uint32_t)CY_SD_HOST_CMD_COMPLETE}, { (uint32_t)CYHAL_SDHC_XFER_COMPLETE, (uint32_t)CY_SD_HOST_XFER_COMPLETE }, @@ -1089,16 +1089,13 @@ void cyhal_sdhc_enable_event(cyhal_sdhc_t *obj, cyhal_sdhc_event_t event, uint8_ /* Enable specific interrupt */ if((uint32_t) event < (uint32_t) CYHAL_SDHC_ALL_INTERRUPTS) { - obj->irq_cause |= event; - uint32_t event_count = SDHC_EVENTS_NUM; - uint8_t i; - - for (i = 0; i < event_count; i++) + for (uint8_t i = 0; i < SDHC_EVENTS_NUM; i++) { const uint32_t *map_entry = eventMap[i]; - if ((map_entry[SDHC_EVENT] & obj->irq_cause) != 0) + if ((map_entry[SDHC_EVENT] & (uint32_t) event) != 0) { - interruptMask |= map_entry[SDHC_ISR]; + interruptMask |= map_entry[SDHC_ISR]; + obj->irq_cause |= map_entry[SDHC_ISR]; } } } @@ -1114,16 +1111,13 @@ void cyhal_sdhc_enable_event(cyhal_sdhc_t *obj, cyhal_sdhc_event_t event, uint8_ { if((uint32_t) event < (uint32_t) CYHAL_SDHC_ALL_INTERRUPTS) { - obj->irq_cause &= ~event; - uint32_t event_count = SDHC_EVENTS_NUM; - uint8_t i; - - for (i = 0; i < event_count; i++) + for (uint8_t i = 0; i < SDHC_EVENTS_NUM; i++) { const uint32_t *map_entry = eventMap[i]; - if ((map_entry[SDHC_EVENT] & obj->irq_cause) != 0) + if ((map_entry[SDHC_EVENT] & (uint32_t) event) != 0) { - interruptMask &= ~map_entry[SDHC_ISR]; + interruptMask &= ~map_entry[SDHC_ISR]; + obj->irq_cause &= ~map_entry[SDHC_ISR]; } } } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_spi.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_spi.c index 8c878880052..949ef276226 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_spi.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_spi.c @@ -500,17 +500,17 @@ static cy_rslt_t cyhal_int_spi_frequency(cyhal_spi_t *obj, uint32_t hz, uint8_t for (oversample_value = SPI_OVERSAMPLE_MIN; oversample_value <= SPI_OVERSAMPLE_MAX; oversample_value++) { oversampled_freq = hz * oversample_value; - if ((hz * oversample_value > cy_PeriClkFreqHz) && (SPI_OVERSAMPLE_MIN == oversample_value)) + if ((hz * oversample_value > Cy_SysClk_ClkPeriGetFrequency()) && (SPI_OVERSAMPLE_MIN == oversample_value)) { return CYHAL_SPI_RSLT_CLOCK_ERROR; } - else if (hz * oversample_value > cy_PeriClkFreqHz) + else if (hz * oversample_value > Cy_SysClk_ClkPeriGetFrequency()) { continue; } divider_value = cyhal_divider_value(hz * oversample_value, 0); - divided_freq = cy_PeriClkFreqHz /(divider_value + 1); + divided_freq = Cy_SysClk_ClkPeriGetFrequency() /(divider_value + 1); diff = max(oversampled_freq, divided_freq) - min(oversampled_freq, divided_freq); if (diff < last_diff) @@ -534,7 +534,7 @@ static cy_rslt_t cyhal_int_spi_frequency(cyhal_spi_t *obj, uint32_t hz, uint8_t float desired_period_us = 1 / (float)hz * 1e6; uint32_t required_frequency = (uint32_t)(3e6 / (0.5f * desired_period_us - 36.66f / 1e3)); - if (required_frequency > cy_PeriClkFreqHz) + if (required_frequency > Cy_SysClk_ClkPeriGetFrequency()) { return CYHAL_SPI_RSLT_CLOCK_ERROR; } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_timer.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_timer.c index a41baf40972..1491d45890d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_timer.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_timer.c @@ -35,7 +35,7 @@ extern "C" { #endif -const cy_stc_tcpwm_counter_config_t default_config = +static const cy_stc_tcpwm_counter_config_t default_config = { .period = 32768, .clockPrescaler = CY_TCPWM_COUNTER_PRESCALER_DIVBY_1, @@ -102,7 +102,7 @@ cy_rslt_t cyhal_timer_init(cyhal_timer_t *obj, cyhal_gpio_t pin, const cyhal_clo { obj->clock = *clk; obj->dedicated_clock = false; - obj->clock_hz = cy_PeriClkFreqHz / (1 + Cy_SysClk_PeriphGetDivider(obj->clock.div_type, obj->clock.div_num)); + obj->clock_hz = Cy_SysClk_ClkPeriGetFrequency() / (1 + Cy_SysClk_PeriphGetDivider(obj->clock.div_type, obj->clock.div_num)); if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphAssignDivider(pclk, clk->div_type, clk->div_num)) { result = CYHAL_TIMER_RSLT_ERR_CLOCK_INIT; @@ -215,7 +215,7 @@ cy_rslt_t cyhal_timer_set_frequency(cyhal_timer_t *obj, uint32_t hz) if(CY_RSLT_SUCCESS == result) { - uint32_t div = cy_PeriClkFreqHz / hz; + uint32_t div = Cy_SysClk_ClkPeriGetFrequency() / hz; if (0 == div || CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphSetDivider(obj->clock.div_type, obj->clock.div_num, div - 1) || CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphEnableDivider(obj->clock.div_type, obj->clock.div_num)) @@ -224,7 +224,7 @@ cy_rslt_t cyhal_timer_set_frequency(cyhal_timer_t *obj, uint32_t hz) } else { - obj->clock_hz = cy_PeriClkFreqHz / div; + obj->clock_hz = Cy_SysClk_ClkPeriGetFrequency() / div; } } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_uart.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_uart.c index 9bddcaec454..519c4f9ee33 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_uart.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_uart.c @@ -346,7 +346,7 @@ void cyhal_uart_free(cyhal_uart_t *obj) static uint32_t cyhal_uart_actual_baud(uint32_t divider, uint32_t oversample) { - return cy_PeriClkFreqHz / ((divider + 1) * oversample); + return Cy_SysClk_ClkPeriGetFrequency() / ((divider + 1) * oversample); } static uint32_t cyhal_uart_baud_perdif(uint32_t desired_baud, uint32_t actual_baud) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_udb_sdio.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_udb_sdio.c index 4263a7b56ba..f199cd1a834 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_udb_sdio.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_udb_sdio.c @@ -74,7 +74,7 @@ static bool op_pending = false; /******************************************************************************* * (Internal) Configuration structures for SDIO pins *******************************************************************************/ -const cy_stc_gpio_pin_config_t pin_cmd_config = +static const cy_stc_gpio_pin_config_t pin_cmd_config = { .outVal = 1, .driveMode = CY_GPIO_DM_STRONG, @@ -91,7 +91,7 @@ const cy_stc_gpio_pin_config_t pin_cmd_config = .vohSel = 0UL, }; -const cy_stc_gpio_pin_config_t pin_data_config = +static const cy_stc_gpio_pin_config_t pin_data_config = { .outVal = 1, .driveMode = CY_GPIO_DM_STRONG, @@ -108,7 +108,7 @@ const cy_stc_gpio_pin_config_t pin_data_config = .vohSel = 0UL, }; -const cy_stc_gpio_pin_config_t pin_clk_config = +static const cy_stc_gpio_pin_config_t pin_clk_config = { .outVal = 1, .driveMode = CY_GPIO_DM_STRONG_IN_OFF, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_usb_dev.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_usb_dev.c index 7a94f948021..884bec75c76 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_usb_dev.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_usb_dev.c @@ -92,7 +92,7 @@ static USBFS_Type* const CYHAL_USB_DEV_BASE_ADDRESSES[CY_IP_MXUSBFS_INSTANCES] = #endif }; -static IRQn_Type CYHAL_USBDEV_IRQ_N[CY_IP_MXUSBFS_INSTANCES] = +static const IRQn_Type CYHAL_USBDEV_IRQ_N[CY_IP_MXUSBFS_INSTANCES] = { #ifdef USBFS0 usb_interrupt_lo_IRQn, @@ -115,7 +115,7 @@ static void cyhal_usb_0_dev_ep0_setup_callback(USBFS_Type *base, struct cy_stc_u static void cyhal_usb_0_dev_ep0_in_callback(USBFS_Type *base, struct cy_stc_usbfs_dev_drv_context *drvContext); static void cyhal_usb_0_dev_ep0_out_callback(USBFS_Type *base, struct cy_stc_usbfs_dev_drv_context *drvContext); static cyhal_usb_dev_event_callback_t cyhal_usb_dev_event_callback_table[CY_IP_MXUSBFS_INSTANCES][CYHAL_USB_DEV_EVENT_NUM]; -static cy_cb_usbfs_dev_drv_callback_t cyhal_usb_dev_drv_event_cb_table[CY_IP_MXUSBFS_INSTANCES][CYHAL_USB_DEV_EVENT_NUM] = +static const cy_cb_usbfs_dev_drv_callback_t cyhal_usb_dev_drv_event_cb_table[CY_IP_MXUSBFS_INSTANCES][CYHAL_USB_DEV_EVENT_NUM] = { /* USBFS0 */ { @@ -128,7 +128,7 @@ static cy_cb_usbfs_dev_drv_callback_t cyhal_usb_dev_drv_event_cb_table[CY_IP_MXU static void cyhal_usb_0_dev_sof_callback(USBFS_Type *base, struct cy_stc_usbfs_dev_drv_context *drvContext); static cyhal_usb_dev_sof_callback_t cyhal_usb_dev_sof_user_callback[CY_IP_MXUSBFS_INSTANCES]; -static cy_cb_usbfs_dev_drv_callback_t cyhal_usb_dev_drv_sof_cb_table[CY_IP_MXUSBFS_INSTANCES]= +static const cy_cb_usbfs_dev_drv_callback_t cyhal_usb_dev_drv_sof_cb_table[CY_IP_MXUSBFS_INSTANCES]= { /* USBFS0 */ &cyhal_usb_0_dev_sof_callback, @@ -136,7 +136,7 @@ static cy_cb_usbfs_dev_drv_callback_t cyhal_usb_dev_drv_sof_cb_table[CY_IP_MXUSB static void cyhal_usb_0_dev_ep_callback(USBFS_Type *base, uint32_t ep_addr, uint32_t errorType, cy_stc_usbfs_dev_drv_context_t *drvContext); static cyhal_usb_dev_endpoint_callback_t cyhal_usb_dev_ep_handler_table[CY_IP_MXUSBFS_INSTANCES][CYHAL_USB_DEV_EP_EVENT_NUM]; -static cy_cb_usbfs_dev_drv_ep_callback_t cyhal_usb_dev_drv_ep_cb_table[CY_IP_MXUSBFS_INSTANCES] = +static const cy_cb_usbfs_dev_drv_ep_callback_t cyhal_usb_dev_drv_ep_cb_table[CY_IP_MXUSBFS_INSTANCES] = { /* USBFS0 */ &cyhal_usb_0_dev_ep_callback, @@ -388,7 +388,7 @@ static cy_rslt_t cyhal_usb_dev_peri_clock_setup(cyhal_usb_dev_t *obj, const cyha if (CY_RSLT_SUCCESS == result) { /* Get divider to provide 100kHz clock or less */ - uint32_t div_value = (cy_PeriClkFreqHz / CYHAL_USB_DEV_BUS_RESET_CLOCK_HZ) - 1U; + uint32_t div_value = (Cy_SysClk_ClkPeriGetFrequency() / CYHAL_USB_DEV_BUS_RESET_CLOCK_HZ) - 1U; (void) Cy_SysClk_PeriphDisableDivider(obj->clock.div_type, obj->clock.div_num); status = Cy_SysClk_PeriphSetDivider(obj->clock.div_type, obj->clock.div_num, div_value); From 3acb1e49f837cfa80752bbaaff841789533da443 Mon Sep 17 00:00:00 2001 From: Kyle Kearney Date: Tue, 17 Sep 2019 10:40:50 -0700 Subject: [PATCH 109/227] Reorganize resource and rtos abstraction files - Move resource and rtos abstractions into their own folders - Remove files for abstractions that are not implemented --- .../TARGET_PSOC6/psoc6csp/README.md | 24 ---- .../psoc6csp/abstraction/include/cyabs_chip.h | 30 ----- .../psoc6csp/abstraction/include/cyabs_fs.h | 116 ------------------ .../{ => resource}/include/cyabs_resource.h | 0 .../{ => resource}/source/cyabs_resource.c | 0 .../include/COMPONENT_RTX/cyabs_rtos_impl.h | 0 .../{ => rtos}/include/cyabs_rtos.h | 0 .../source/COMPONENT_RTX/cyabs_rtos_rtxv5.c | 0 8 files changed, 170 deletions(-) delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/README.md delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/include/cyabs_chip.h delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/include/cyabs_fs.h rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/{ => resource}/include/cyabs_resource.h (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/{ => resource}/source/cyabs_resource.c (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/{ => rtos}/include/COMPONENT_RTX/cyabs_rtos_impl.h (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/{ => rtos}/include/cyabs_rtos.h (100%) rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/{ => rtos}/source/COMPONENT_RTX/cyabs_rtos_rtxv5.c (100%) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/README.md b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/README.md deleted file mode 100644 index a7ac9afd74e..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/README.md +++ /dev/null @@ -1,24 +0,0 @@ -# PSoC 6 CSP - -## Overview - -TBD: high-level overview - -## Features - -TBD: list of the functionality included - -## API Reference Manual - -The PSoC 6 Chip Support Package provides a set of APIs to configure, initialize and use the PSoC 6 MCU resources. - -See the [PSoC 6 CSP API Reference Manual][api] for the complete list of the provided interfaces. - -## More information -* [PSoC 6 CSP API Reference Manual][api] -* [Cypress Semiconductor](http://www.cypress.com) - -[api]: modules.html - ---- -© Cypress Semiconductor Corporation, 2019. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/include/cyabs_chip.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/include/cyabs_chip.h deleted file mode 100644 index fb3b77277df..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/include/cyabs_chip.h +++ /dev/null @@ -1,30 +0,0 @@ -/***************************************************************************//** -* \file cyabs_chip.h -* -* \brief -* Basic abstraction layer for dealing with chips containing a Cypress MCU. This -* API provides convenience methods for initializing and manipulating different -* hardware peripherals. Depending on the specific chip being used, not all -* features may be supported. -* -******************************************************************************** -* \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#pragma once - -#include "cyhal.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/include/cyabs_fs.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/include/cyabs_fs.h deleted file mode 100644 index 9c19358721c..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/include/cyabs_fs.h +++ /dev/null @@ -1,116 +0,0 @@ -/***************************************************************************//** -* \file cyabs_fs.h -* -* \brief -* Basic file system abstraction layer. This API provides convenience methods -* for reading and writing values. -* -******************************************************************************** -* \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -/** -* \addtogroup group_abstraction_fs File system abstraction -* \ingroup group_abstraction -* \{ -* Basic file system abstraction layer. This API provides convenience methods -* for reading and writing values. -* -* \defgroup group_abstraction_fs_macros Macros -* \defgroup group_abstraction_fs_data_structures Data Structures -* \defgroup group_abstraction_fs_functions Functions -*/ - -#pragma once - -#include -#include -#include "cy_result.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/** -* \addtogroup group_abstraction_fs_macros -* \{ -*/ - -#define CY_O_RDONLY (1 << 0) /**< TODO */ -#define CY_O_WRONLY (1 << 1) /**< TODO */ -#define CY_O_RDWR (1 << 2) /**< TODO */ -#define CY_O_APPEND (1 << 3) /**< TODO */ -#define CY_O_CREAT (1 << 4) /**< TODO */ - -/** \} group_abstraction_fs_macros */ - -/** -* \addtogroup group_abstraction_fs_data_structures -* \{ -*/ - -typedef uint32_t cy_handle_t; /**< Resource handle */ - -/** \} group_abstraction_fs_data_structures */ - - -/** -* \addtogroup group_abstraction_fs_functions -* \{ -*/ - -/** - * \brief open or create a file and return a handle - * \param path the path name of the file to open - * \param oflag the mode to use when opening the file - * \param handle pointer to location re receive handle - * \returns CY_RSLT_SUCCESS if successful, otherwise error code - */ -cy_rslt_t cy_fs_open(const char *path, uint32_t oflag, cy_handle_t *handle) ; - -/** - * \brief close an open file - * \param handle a file handle to an open file - * \returns CY_RSLT_SUCCESS if successful, otherwise error code - */ - cy_rslt_t cy_fs_close(cy_handle_t handle) ; - -/** - * \brief read data from a file - * \param handle a file handle open for reading or read/write - * \param buf the buffer for the read data - * \param nbyte the size of the buffer in bytes, the number of bytes read on return - * \returns CY_RSLT_SUCCESS if successful, otherwise error code - */ -cy_rslt_t cy_fs_read(cy_handle_t handle, void *buf, size_t *nbyte) ; - -/** - * \brief write data to a file - * \param handle a file handle open for writing or read/write - * \param buf the buffer for the data to write - * \param nbyte the size of the buffer in bytes, the number of bytes written on return - * \returns CY_RSLT_SUCCESS if successful, otherwise error code - */ -cy_rslt_t cy_fs_write(cy_handle_t handle, const void *buf, size_t *nbyte) ; - -/** \} group_abstraction_fs_functions */ - -#if defined(__cplusplus) -} -#endif - -/** \} group_abstraction_fs */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/include/cyabs_resource.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/resource/include/cyabs_resource.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/include/cyabs_resource.h rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/resource/include/cyabs_resource.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/source/cyabs_resource.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/resource/source/cyabs_resource.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/source/cyabs_resource.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/resource/source/cyabs_resource.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/include/COMPONENT_RTX/cyabs_rtos_impl.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/rtos/include/COMPONENT_RTX/cyabs_rtos_impl.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/include/COMPONENT_RTX/cyabs_rtos_impl.h rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/rtos/include/COMPONENT_RTX/cyabs_rtos_impl.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/include/cyabs_rtos.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/rtos/include/cyabs_rtos.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/include/cyabs_rtos.h rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/rtos/include/cyabs_rtos.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/source/COMPONENT_RTX/cyabs_rtos_rtxv5.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/rtos/source/COMPONENT_RTX/cyabs_rtos_rtxv5.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/source/COMPONENT_RTX/cyabs_rtos_rtxv5.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/rtos/source/COMPONENT_RTX/cyabs_rtos_rtxv5.c From 2b277e88270f8c2bf02a95f9a8d07bf377c3dc10 Mon Sep 17 00:00:00 2001 From: Kyle Kearney Date: Tue, 17 Sep 2019 17:00:17 -0700 Subject: [PATCH 110/227] Improve psoc6csp doxygen comments --- .../resource/include/cyabs_resource.h | 59 ++----- .../abstraction/rtos/include/cyabs_rtos.h | 159 +++++++++--------- .../psoc6csp/core_lib/include/cy_result.h | 94 ++++++----- .../TARGET_PSOC6/psoc6csp/hal/include/cyhal.h | 9 +- .../psoc6csp/hal/include/cyhal_adc.h | 10 -- .../psoc6csp/hal/include/cyhal_crc.h | 29 +--- .../psoc6csp/hal/include/cyhal_dac.h | 19 --- .../psoc6csp/hal/include/cyhal_flash.h | 33 +--- .../psoc6csp/hal/include/cyhal_gpio.h | 36 ---- .../psoc6csp/hal/include/cyhal_hw_resources.h | 31 +--- .../psoc6csp/hal/include/cyhal_hw_types.h | 111 ++++++------ .../psoc6csp/hal/include/cyhal_hwmgr.h | 19 --- .../psoc6csp/hal/include/cyhal_i2c.h | 62 +++---- .../psoc6csp/hal/include/cyhal_interconnect.h | 20 --- .../psoc6csp/hal/include/cyhal_lptimer.h | 28 --- .../psoc6csp/hal/include/cyhal_modules.h | 14 +- .../psoc6csp/hal/include/cyhal_pin_package.h | 34 +--- .../psoc6csp/hal/include/cyhal_pwm.h | 36 ---- .../psoc6csp/hal/include/cyhal_qspi.h | 37 +--- .../psoc6csp/hal/include/cyhal_rtc.h | 30 +--- .../psoc6csp/hal/include/cyhal_scb_common.h | 24 +-- .../psoc6csp/hal/include/cyhal_sdhc.h | 46 +---- .../psoc6csp/hal/include/cyhal_sdio.h | 38 +---- .../psoc6csp/hal/include/cyhal_spi.h | 16 +- .../psoc6csp/hal/include/cyhal_system.h | 20 --- .../psoc6csp/hal/include/cyhal_tcpwm_common.h | 33 +--- .../psoc6csp/hal/include/cyhal_timer.h | 38 +---- .../psoc6csp/hal/include/cyhal_trng.h | 12 -- .../psoc6csp/hal/include/cyhal_uart.h | 38 +---- .../psoc6csp/hal/include/cyhal_usb_dev.h | 73 ++++---- .../psoc6csp/hal/include/cyhal_utils.h | 67 ++++---- .../psoc6csp/hal/include/cyhal_wdt.h | 22 +-- .../TARGET_PSOC6/psoc6csp/hal/src/cyhal_wdt.c | 6 +- 33 files changed, 340 insertions(+), 963 deletions(-) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/resource/include/cyabs_resource.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/resource/include/cyabs_resource.h index 1b89b1403a5..dde2a0dcd76 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/resource/include/cyabs_resource.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/resource/include/cyabs_resource.h @@ -22,18 +22,6 @@ * limitations under the License. *******************************************************************************/ -/** -* \addtogroup group_abstraction_resource Resource abstraction -* \ingroup group_abstraction -* \{ -* Basic abstraction layer for dealing with resources. -* -* \defgroup group_abstraction_resource_macros Macros -* \defgroup group_abstraction_resource_enums Enums -* \defgroup group_abstraction_resource_data_structures Data Structures -* \defgroup group_abstraction_resource_functions Functions -*/ - #pragma once #include @@ -44,10 +32,12 @@ extern "C" { #endif -/** -* \addtogroup group_abstraction_resource_macros -* \{ -*/ +/** + * \addtogroup group_abstraction_resource Resource Abstraction + * \{ + * + * Basic abstraction layer for dealing with resources. + */ /** Error code for when the specified resource operation is not valid. */ #define CY_RSLT_RSC_ERROR_UNSUPPORTED (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_RESOURCE, 0)) @@ -62,13 +52,6 @@ extern "C" { /** Error code for when the specified resource can not be read. */ #define CY_RSLT_RSC_ERROR_READ (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_RESOURCE, 5)) -/** \} group_abstraction_resource_macros */ - - -/** -* \addtogroup group_abstraction_resource_enums -* \{ -*/ /** Different types of memory that the resources can be stored in. */ typedef enum { @@ -77,15 +60,7 @@ typedef enum CY_RESOURCE_IN_EXTERNAL_STORAGE /**< resource location in external storage */ } cy_resource_location_t; -/** \} group_abstraction_resource_enums */ - - -/** -* \addtogroup group_abstraction_resource_data_structures -* \{ -*/ - -/** Filesystem handle */ +/** Filesystem handle */ typedef struct { unsigned long offset; /**< Offset to the start of the resource */ @@ -99,19 +74,12 @@ typedef struct unsigned long size; /**< resource size */ union { - cy_filesystem_resource_handle_t fs; /** < filesystem resource handle */ - const uint8_t* mem_data; /** < memory resource handle */ - void* external_storage_context; /** < external storage context */ - } val; + cy_filesystem_resource_handle_t fs; /**< handle for resource in filesystem */ + const uint8_t* mem_data; /**< handle for resource in internal memory */ + void* external_storage_context; /**< handle for resource in external storage */ + } val; /**< low-level handle (type varies depending on resource storage location) */ } cy_resource_handle_t; -/** \} group_abstraction_resource_data_structures */ - -/** -* \addtogroup group_abstraction_resource_functions -* \{ -*/ - /** * \brief return the block size for the resource * \param handle handle to a resource @@ -147,7 +115,8 @@ cy_rslt_t cy_resource_get_block_count(const cy_resource_handle_t *handle, uint32 cy_rslt_t cy_resource_read(const cy_resource_handle_t *handle, uint32_t blockno, uint8_t **buffer, uint32_t *size); /** - * \brief optimized version of read for resources stored in memory (\see CY_RESOURCE_IN_MEMORY) + * \brief optimized version of read for resources stored in memory + * \see CY_RESOURCE_IN_MEMORY * \param handle the handle to the resource * \param buffer pointer to receive buffer address from resource. This does NOT need to be freed. * \param size location to receive the size of the block read @@ -155,8 +124,6 @@ cy_rslt_t cy_resource_read(const cy_resource_handle_t *handle, uint32_t blockno, */ cy_rslt_t cy_resource_readonly_memory(const cy_resource_handle_t *handle, const uint8_t **buffer, uint32_t *size); -/** \} group_abstraction_resource_functions */ - #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/rtos/include/cyabs_rtos.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/rtos/include/cyabs_rtos.h index 8fad10a6032..ec15a39b4fa 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/rtos/include/cyabs_rtos.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/rtos/include/cyabs_rtos.h @@ -33,50 +33,14 @@ #include #include -/* - * Note, cyabs_rtos_impl.h above is included and is the implementation of some basic - * types for the abstraction layer. The types expected to be defined are. - * - * cy_thread_t : typedef from underlying RTOS thread type - * cy_thread_arg_t : typedef from the RTOS type that is passed to the - * entry function of a thread. - * cy_mutex_t : typedef from the underlying RTOS mutex type - * cy_event_t : typedef from the underlying RTOS event type - * cy_queue_t : typedef from the underlying RTOS queue type - * cy_timer_callback_arg_t : typedef from the RTOS type that is passed - * : to the timer callback function - * cy_timer_t : typedef from the underlying RTOS timer type - * cy_time_t : count of time in milliseconds - * cy_rtos_error_t : typedef from the underlying RTOS error type - * - * The enum cy_thread_priority_t needs to have the following priority values defined - * and mapped to RTOS specific values: - * CY_RTOS_PRIORITY_MIN - * CY_RTOS_PRIORITY_LOW - * CY_RTOS_PRIORITY_BELOWNORMAL - * CY_RTOS_PRIORITY_NORMAL - * CY_RTOS_PRIORITY_ABOVENORMAL - * CY_RTOS_PRIORITY_HIGH - * CY_RTOS_PRIORITY_REALTIME - * CY_RTOS_PRIORITY_MAX - * - * Finally, the following macros need to be defined for memory allocations: - * CY_RTOS_MIN_STACK_SIZE - * CY_RTOS_ALIGNMENT - * CY_RTOS_ALIGNMENT_MASK - */ - - /** -* \addtogroup group_abstraction_rtos RTOS abstraction -* \ingroup group_abstraction -* \{ -* Basic abstraction layer for dealing with RTOSes. -* -* \defgroup group_abstraction_rtos_macros Macros -* \defgroup group_abstraction_rtos_enums Enums -* \defgroup group_abstraction_rtos_data_structures Data Structures -* \defgroup group_abstraction_rtos_functions Functions +* \defgroup group_abstraction_rtos_common Common +* \defgroup group_abstraction_rtos_mutex Mutex +* \defgroup group_abstraction_rtos_queue Queue +* \defgroup group_abstraction_rtos_semaphore Semaphore +* \defgroup group_abstraction_rtos_threads Threading +* \defgroup group_abstraction_rtos_time Time +* \defgroup group_abstraction_rtos_timer Timer */ #ifdef __cplusplus @@ -86,10 +50,10 @@ extern "C" /*********************************************** CONSTANTS **********************************************/ -/** -* \addtogroup group_abstraction_rtos_macros -* \{ -*/ +/** + * \ingroup group_abstraction_rtos_common + * \{ + */ /** Used with RTOS calls that require a timeout. This implies the call will never timeout. */ #define CY_RTOS_NEVER_TIMEOUT ( (uint32_t)0xffffffffUL ) @@ -100,31 +64,35 @@ extern "C" // underlying errors to these. If the errors are special cases, the the error CY_RTOS_GENERAL_ERROR can be // returns and cy_rtos_last_error() used to retrieve the RTOS specific error message. // -/** Requested operationd did not complete in the specified time */ +/** Requested operation did not complete in the specified time */ #define CY_RTOS_TIMEOUT CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 0) /** The RTOS could not allocate memory for the specified operation */ #define CY_RTOS_NO_MEMORY CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 1) /** An error occured in the RTOS */ #define CY_RTOS_GENERAL_ERROR CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 2) +/** A bad argument was passed into the APIs */ +#define CY_RTOS_BAD_PARAM CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 5) + +/** \} group_abstraction_rtos_common */ + +/** + * \ingroup group_abstraction_rtos_queue + * \{ + */ + /** The Queue is already full and can't accept any more items at this time */ #define CY_RTOS_QUEUE_FULL CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 3) /** The Queue is empty and has nothing to remove */ #define CY_RTOS_QUEUE_EMPTY CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 4) -/** A bad argument was passed into the APIs */ -#define CY_RTOS_BAD_PARAM CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 5) - -/** \} group_abstraction_rtos_macros */ +/** \} group_abstraction_rtos_queue */ /*********************************************** TYPES **********************************************/ -/** -* \addtogroup group_abstraction_rtos_enums -* \{ -*/ - /** * The state a thread can be in + * + * \ingroup group_abstraction_rtos_threads */ typedef enum cy_thread_state { @@ -138,6 +106,8 @@ typedef enum cy_thread_state /** * The type of timer + * + * \ingroup group_abstraction_rtos_timer */ typedef enum cy_timer_trigger_type { @@ -147,34 +117,22 @@ typedef enum cy_timer_trigger_type cy_timer_type_once = CY_TIMER_TYPE_ONCE, /**< \deprecated replaced by CY_TIMER_TYPE_ONCE */ } cy_timer_trigger_type_t ; -/** \} group_abstraction_rtos_enums */ - - -/** -* \addtogroup group_abstraction_rtos_data_structures -* \{ -*/ - /** * The type of a function that is the entry point for a thread * * @param[in] arg the argument passed from the thread create call to the entry function + * + * \ingroup group_abstraction_rtos_threads */ typedef void (*cy_thread_entry_fn_t)(cy_thread_arg_t arg) ; /** - * The callback function to be called by a timeer + * The callback function to be called by a timer + * + * \ingroup group_abstraction_rtos_timer */ typedef void (*cy_timer_callback_t)(cy_timer_callback_arg_t arg); -/** \} group_abstraction_rtos_data_structures */ - - -/** -* \addtogroup group_abstraction_rtos_functions -* \{ -*/ - /** * Return the last error from the RTOS. * @@ -185,11 +143,18 @@ typedef void (*cy_timer_callback_t)(cy_timer_callback_arg_t arg); * from the last RTOS abstraction layer that returned CY_RTOS_GENERAL_ERROR. * * @return RTOS specific error code. + * + * \ingroup group_abstraction_rtos_common */ extern cy_rtos_error_t cy_rtos_last_error(); /*********************************************** Threads **********************************************/ +/* + * + * \ingroup group_abstraction_rtos_threads + * \{ + */ /** Create a thread with specific thread argument. * @@ -281,8 +246,15 @@ extern cy_rslt_t cy_rtos_get_thread_state(cy_thread_t *thread, cy_thread_state_t */ extern cy_rslt_t cy_rtos_join_thread(cy_thread_t *thread); +/** \} group_abstraction_rtos_threads */ + /*********************************************** Mutexes **********************************************/ +/** + * \ingroup group_abstraction_rtos_mutex + * \{ + */ + /** Create a mutex. * * This is basically a binary mutex which can be used to synchronize between threads @@ -334,8 +306,15 @@ extern cy_rslt_t cy_rtos_set_mutex(cy_mutex_t *mutex); */ extern cy_rslt_t cy_rtos_deinit_mutex(cy_mutex_t *mutex); +/** \} group_abstraction_rtos_mutex */ + /*********************************************** Semaphores **********************************************/ +/** + * \ingroup group_abstraction_rtos_semaphore + * \{ + */ + /** * Create a semaphore * @@ -388,8 +367,15 @@ extern cy_rslt_t cy_rtos_set_semaphore(cy_semaphore_t *semaphore, bool in_isr); */ extern cy_rslt_t cy_rtos_deinit_semaphore(cy_semaphore_t *semaphore); +/** \} group_abstraction_rtos_semaphore */ + /*********************************************** Events **********************************************/ +/** + * \ingroup group_abstraction_rtos_event + * \{ + */ + /** Create an event. * * This is an event which can be used to signal a set of threads @@ -467,8 +453,15 @@ extern cy_rslt_t cy_rtos_waitbits_event(cy_event_t *event, uint32_t *bits, bool */ extern cy_rslt_t cy_rtos_deinit_event(cy_event_t *event); +/** \} group_abstraction_rtos_event */ + /*********************************************** Queues **********************************************/ +/** + * \ingroup group_abstraction_rtos_queue + * \{ + */ + /** Create a queue. * * This is a queue of data where entries are placed on the back of the queue @@ -561,8 +554,15 @@ extern cy_rslt_t cy_rtos_reset_queue(cy_queue_t *queue); */ extern cy_rslt_t cy_rtos_deinit_queue(cy_queue_t *queue); +/** \} group_abstraction_rtos_queue */ + /*********************************************** Timers **********************************************/ +/** + * \ingroup group_abstraction_rtos_timer + * \{ + */ + /** Create a new timer. * * This function intializes a timer object. @note The timer is @@ -617,8 +617,15 @@ extern cy_rslt_t cy_rtos_is_running_timer(cy_timer_t *timer, bool *state); */ extern cy_rslt_t cy_rtos_deinit_timer(cy_timer_t *timer); +/** \} group_abstraction_rtos_timer */ + /*********************************************** Time **********************************************/ +/** + * \ingroup group_abstraction_rtos_time + * \{ + */ + /** Gets time in milliseconds since RTOS start. * * @note Since this is only 32 bits, it will roll over every 49 days, 17 hours, 2 mins, 47.296 seconds @@ -642,9 +649,7 @@ extern cy_rslt_t cy_rtos_get_time(cy_time_t *tval); */ extern cy_rslt_t cy_rtos_delay_milliseconds(cy_time_t num_ms); -/** \} group_abstraction_rtos_functions */ - -/** @} */ +/** \} group_abstraction_rtos_timer */ #ifdef __cplusplus } /* extern "C" */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/core_lib/include/cy_result.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/core_lib/include/cy_result.h index d80830b9073..fc05bd7401a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/core_lib/include/cy_result.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/core_lib/include/cy_result.h @@ -32,7 +32,9 @@ * information about whether something succeeded or details about any issues * that were detected. * -* \defgroup group_result_macros Macros +* \defgroup group_result_fields Fields +* \defgroup group_result_modules Modules +* \defgroup group_result_severity Severity */ #pragma once @@ -43,11 +45,13 @@ extern "C" { #endif -/** -* \addtogroup group_result_macros -* \{ -*/ +/** Provides the result of an operation as a structured bitfield */ +typedef uint32_t cy_rslt_t; + +/** Result value indicating success */ +#define CY_RSLT_SUCCESS ((cy_rslt_t)0x00000000U) +/** \cond INTERNAL */ /** Mask for the bit at position "x" */ #define CY_BIT_MASK(x) ((1U << (x)) - 1U) @@ -71,14 +75,13 @@ extern "C" { /** Mask for the result type */ #define CY_RSLT_TYPE_MASK CY_BIT_MASK(CY_RSLT_TYPE_WIDTH) -/** Informational-only result status */ -#define CY_RSLT_TYPE_INFO (0U) -/** Warning result */ -#define CY_RSLT_TYPE_WARNING (1U) -/** Error result */ -#define CY_RSLT_TYPE_ERROR (2U) -/** Fatal error result */ -#define CY_RSLT_TYPE_FATAL (3U) +/** \endcond */ + +/** +* \addtogroup group_result_fields +* \{ +* Utlity macros for constructing result values and extracting individual fields from existing results. +*/ /** Get the value of the result code field */ #define CY_RSLT_GET_CODE(x) (((x) >> CY_RSLT_CODE_POSITION) & CY_RSLT_CODE_MASK) @@ -87,45 +90,60 @@ extern "C" { /** Get the value of the module identifier field */ #define CY_RSLT_GET_MODULE(x) (((x) >> CY_RSLT_MODULE_POSITION) & CY_RSLT_MODULE_MASK) +/** Create a result value from the specified type, module, and result code */ +#define CY_RSLT_CREATE(type, module, code) \ + ((((module) & CY_RSLT_MODULE_MASK) << CY_RSLT_MODULE_POSITION) | \ + (((code) & CY_RSLT_CODE_MASK) << CY_RSLT_CODE_POSITION) | \ + (((type) & CY_RSLT_TYPE_MASK) << CY_RSLT_TYPE_POSITION)) + +/** \} group_result_fields */ +/** +* \addtogroup group_result_severity +* \{ +*/ + +/** Informational-only result */ +#define CY_RSLT_TYPE_INFO (0U) +/** Warning result */ +#define CY_RSLT_TYPE_WARNING (1U) +/** Error result */ +#define CY_RSLT_TYPE_ERROR (2U) +/** Fatal error result */ +#define CY_RSLT_TYPE_FATAL (3U) + +/** \} group_result_severity */ + +/** +* \addtogroup group_result_modules +* \{ +* Defines codes to identify the module from which an error originated. +* For some large libraries, a range of module codes is defined here; +* see the library documentation for values corresonding to individual modules. +*/ /**** DRIVER Module codes: 0x0000 - 0x00FF ****/ -/** Base identifier for peripheral driver library */ +/** Base identifier for peripheral driver library modules (0x0000 - 0x007F) */ #define CY_RSLT_MODULE_DRIVERS_PDL_BASE (0x0000U) -/** Base identifier for peripheral driver library */ +/** Base identifier for wireless host driver library modules (0x0080 - 0x00FF) */ #define CY_RSLT_MODULE_DRIVERS_WHD_BASE (0x0080U) -/**** ABSTRACTION Module codes: 0x0100 - 0x01FF ****/ -/** Base identifier for chip support modules */ +/** Base identifier for HAL modules (0x0100 - 0x017F) */ #define CY_RSLT_MODULE_ABSTRACTION_HAL_BASE (0x0100U) -/** Base identifier for board support modules */ +/** Module identifier for board support package */ #define CY_RSLT_MODULE_ABSTRACTION_BSP (0x0180U) -/** Base identifier for file system modules */ +/** Module identifier for file system abstraction */ #define CY_RSLT_MODULE_ABSTRACTION_FS (0x0181U) -/** Base identifier for resource abstraction modules */ +/** Module identifier for resource abstraction */ #define CY_RSLT_MODULE_ABSTRACTION_RESOURCE (0x0182U) -/** Base identifier for rtos abstraction modules */ +/** Module identifier for rtos abstraction */ #define CY_RSLT_MODULE_ABSTRACTION_OS (0x0183U) -/** Base identifier for environment abstraction modules */ +/** Base identifier for environment abstraction modules (0x0184 - 0x01FF) */ #define CY_RSLT_MODULE_ABSTRACTION_ENV (0x0184U) -/** Middleware Module codes: 0x0200 - 0x02FF */ +/** Base identifier for Middleware module codes (0x0200 - 0x02FF) */ #define CY_RSLT_MODULE_MIDDLEWARE_BASE (0x0200U) - - -/** Provides the result of an operation as a structured bitfield */ -typedef uint32_t cy_rslt_t; - -/** Result value indicating success */ -#define CY_RSLT_SUCCESS ((cy_rslt_t)0x00000000U) - -/** Create a result value from the specified type, module, and result code */ -#define CY_RSLT_CREATE(type, module, code) \ - ((((module) & CY_RSLT_MODULE_MASK) << CY_RSLT_MODULE_POSITION) | \ - (((code) & CY_RSLT_CODE_MASK) << CY_RSLT_CODE_POSITION) | \ - (((type) & CY_RSLT_TYPE_MASK) << CY_RSLT_TYPE_POSITION)) - -/** \} group_result_macros */ +/** \} group_result_modules */ #ifdef __cplusplus } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal.h index 29891e4a9cd..41b68c6f54d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal.h @@ -35,11 +35,7 @@ *******************************************************************************/ /** -* \addtogroup group_hal -* \{ -* TODO: high-level HAL description -* update hal/include/cyhal.h to change this text -* \} group_hal +* \defgroup group_hal HAL Drivers */ #pragma once @@ -68,6 +64,3 @@ #include "cyhal_uart.h" #include "cyhal_usb_dev.h" #include "cyhal_wdt.h" - -/** \} group_hal */ - diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_adc.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_adc.h index ea60e0d7216..78b836c590c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_adc.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_adc.h @@ -31,11 +31,8 @@ * \{ * High level interface for interacting with the Cypress ADC. * -* \defgroup group_hal_adc_macros Macros * \defgroup group_hal_adc_functions ADC Functions * \defgroup group_hal_adc_channel_functions ADC Channel Functions -* \defgroup group_hal_adc_data_structures Data Structures -* \defgroup group_hal_adc_enums Enumerated Types */ #pragma once @@ -50,11 +47,6 @@ extern "C" { #endif -/** -* \addtogroup group_hal_adc_macros -* \{ -*/ - /** Maximum value that the ADC can return */ #define CYHAL_ADC_MAX_VALUE 0xFFFF @@ -67,8 +59,6 @@ extern "C" { /** No channels available */ #define CYHAL_ADC_RSLT_NO_CHANNELS (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_ADC, 3)) -/** \} group_hal_adc_macros */ - /** * \addtogroup group_hal_adc_functions diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crc.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crc.h index b42549ef4df..f464fa0da95 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crc.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crc.h @@ -31,10 +31,6 @@ * \{ * High level interface for interacting with the Cypress CRC. * -* \defgroup group_hal_crc_macros Macros -* \defgroup group_hal_crc_functions Functions -* \defgroup group_hal_crc_data_structures Data Structures -* \defgroup group_hal_crc_enums Enumerated Types */ #pragma once @@ -49,23 +45,10 @@ extern "C" { #endif -/** -* \addtogroup group_hal_crc_macros -* \{ -*/ - /** Invalid argument */ #define CYHAL_CRC_RSLT_ERR_BAD_ARGUMENT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_CRC, 0)) -/** \} group_hal_crc_macros */ - - -/** -* \addtogroup group_hal_crc_data_structures -* \{ -*/ - -/** CRC algorithm parameters */ +/** @brief CRC algorithm parameters */ typedef struct { uint32_t width; //!< Bit width of the CRC @@ -82,14 +65,6 @@ typedef struct bool remReverse; //!< If 1, the remainder is reversed. If 0, it is not. } crc_algorithm_t; -/** \} group_hal_crc_data_structures */ - - -/** -* \addtogroup group_hal_crc_functions -* \{ -*/ - /** Initialize the CRC generator. This function reserves the CRYPTO block for CRC calculations. * * @param[out] obj The CRC generator object @@ -131,8 +106,6 @@ cy_rslt_t cyhal_crc_compute(const cyhal_crc_t *obj, const uint8_t *data, size_t */ cy_rslt_t cyhal_crc_finish(const cyhal_crc_t *obj, uint32_t *crc); -/** \} group_hal_crc_functions */ - #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dac.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dac.h index 900944823bc..494142e1de1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dac.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dac.h @@ -31,10 +31,6 @@ * \{ * High level interface for interacting with the Cypress DAC. * -* \defgroup group_hal_dac_macros Macros -* \defgroup group_hal_dac_functions Functions -* \defgroup group_hal_dac_data_structures Data Structures -* \defgroup group_hal_dac_enums Enumerated Types */ #pragma once @@ -49,24 +45,11 @@ extern "C" { #endif -/** -* \addtogroup group_hal_dac_macros -* \{ -*/ - /** Bad argument */ #define CYHAL_DAC_RSLT_BAD_ARGUMENT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_DAC, 0)) /** Failed to initialize DAC */ #define CYHAL_DAC_RSLT_FAILED_INIT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_DAC, 1)) -/** \} group_hal_adc_macros */ - - -/** -* \addtogroup group_hal_dac_functions -* \{ -*/ - /** Initialize the DAC peripheral * * Configures the pin used by dac. @@ -102,8 +85,6 @@ void cyhal_dac_write(const cyhal_dac_t *obj, uint16_t value); */ uint16_t cyhal_dac_read(cyhal_dac_t *obj); -/** \} group_hal_dac_functions */ - #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_flash.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_flash.h index a1875d5fd4e..9eefbed5148 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_flash.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_flash.h @@ -30,11 +30,6 @@ * \ingroup group_hal * \{ * Flash HAL high-level description -* -* \defgroup group_hal_flash_macros Macros -* \defgroup group_hal_flash_functions Functions -* \defgroup group_hal_flash_data_structures Data Structures -* \defgroup group_hal_flash_enums Enumerated Types */ @@ -50,22 +45,10 @@ extern "C" { #endif -/** -* \addtogroup group_hal_flash_macros -* \{ -*/ - /** Invalid argument */ #define CYHAL_FLASH_RSLT_ERR_ADDRESS (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_FLASH, 0)) -/** \} group_hal_flash_macros */ - -/** -* \addtogroup group_hal_flash_data_structures -* \{ -*/ - -/** Information about a single block of flash memory */ +/** @brief Information about a single block of flash memory */ typedef struct { uint32_t start_address; //!< Start address of the memory @@ -75,25 +58,17 @@ typedef struct uint8_t erase_value; //!< The flash erase value } cyhal_flash_block_info_t; -/** Information about all of the blocks of flash memory */ +/** @brief Information about all of the blocks of flash memory */ typedef struct { uint8_t block_count; //!< The number of distinct flash blocks const cyhal_flash_block_info_t *blocks; //!< Array of the distinct flash blocks } cyhal_flash_info_t; -/** \} group_hal_flash_data_structures */ - - /******************************************************************************* * Functions *******************************************************************************/ -/** -* \addtogroup group_hal_flash_functions -* \{ -*/ - /** Initialize the flash_t object for access to flash through the HAL * * @param[out] obj The flash object @@ -215,10 +190,6 @@ cy_rslt_t cyhal_flash_start_program(cyhal_flash_t *obj, uint32_t address, const */ bool cyhal_flash_is_operation_complete(cyhal_flash_t *obj); -/** \} group_hal_flash_functions */ - -/** \} group_hal_flash_functions */ - #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_gpio.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_gpio.h index c19b8cabd2d..1aed43162cc 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_gpio.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_gpio.h @@ -30,11 +30,6 @@ * \ingroup group_hal * \{ * High level interface for interacting with the Cypress GPIO. -* -* \defgroup group_hal_gpio_macros Macros -* \defgroup group_hal_gpio_functions Functions -* \defgroup group_hal_gpio_data_structures Data Structures -* \defgroup group_hal_gpio_enums Enumerated Types */ #pragma once @@ -52,22 +47,9 @@ extern "C" { * Defines *******************************************************************************/ -/** -* \addtogroup group_hal_gpio_macros -* \{ -*/ - /** Integer representation of no connect pin (required to exist in all BSPs) */ #define CYHAL_NC_PIN_VALUE ((cyhal_gpio_t)0xFFFFFFFF) -/** \} group_hal_gpio_macros */ - - -/** -* \addtogroup group_hal_gpio_enums -* \{ -*/ - /******************************************************************************* * Enumerations *******************************************************************************/ @@ -99,25 +81,9 @@ typedef enum { CYHAL_GPIO_DRIVE_PULLUPDOWN, /**< Pull-up and pull-down resistors */ } cyhal_gpio_drive_mode_t; -/** \} group_hal_gpio_enums */ - - -/** -* \addtogroup group_hal_gpio_data_structures -* \{ -*/ - /** GPIO callback function type */ typedef void (*cyhal_gpio_event_callback_t)(void *callback_arg, cyhal_gpio_event_t event); -/** \} group_hal_gpio_data_structures */ - - -/** -* \addtogroup group_hal_gpio_functions -* \{ -*/ - /******************************************************************************* * Functions *******************************************************************************/ @@ -186,8 +152,6 @@ void cyhal_gpio_register_callback(cyhal_gpio_t pin, cyhal_gpio_event_callback_t */ void cyhal_gpio_enable_event(cyhal_gpio_t pin, cyhal_gpio_event_t event, uint8_t intrPriority, bool enable); -/** \} group_hal_gpio_functions */ - /******************************************************************************* * Backward compatibility macro. The following code is DEPRECATED and must * not be used in new projects diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hw_resources.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hw_resources.h index a4f1c0ccbc2..f5da12987ff 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hw_resources.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hw_resources.h @@ -23,15 +23,9 @@ *******************************************************************************/ /** -* \addtogroup group_hal_hw_resources PSoC 6 Hardware Resources +* \addtogroup group_hal_psoc6_hw_types * \ingroup group_hal_psoc6 * \{ -* Struct definitions for configuration resources in the PDL. -* -* \defgroup group_hal_hw_resources_macros Macros -* \defgroup group_hal_hw_resources_functions Functions -* \defgroup group_hal_hw_resources_data_structures Data Structures -* \defgroup group_hal_hw_resources_enums Enumerated Types */ #pragma once @@ -40,11 +34,6 @@ extern "C" { #endif -/** -* \addtogroup group_hal_hw_resources_enums -* \{ -*/ - /* NOTE: Any changes made to this enum must also be made to the hardware manager resource tracking */ /** Resource types that the hardware manager supports */ typedef enum @@ -74,15 +63,9 @@ typedef enum CYHAL_RSC_INVALID, /*!< Placeholder for invalid type */ } cyhal_resource_t; -/** \} group_hal_hw_resources_enums */ - - -/** -* \addtogroup group_hal_hw_resources_data_structures -* \{ -*/ - -/** Represents a particular instance of a resource on the chip */ +/** + * @brief Represents a particular instance of a resource on the chip + */ typedef struct { cyhal_resource_t type; //!< The resource block type @@ -91,12 +74,10 @@ typedef struct * The channel number, if the resource type defines multiple channels * per block instance. Otherwise, 0 */ uint8_t channel_num; -} cyhal_resource_inst_t; - -/** \} group_hal_hw_resources_data_structures */ +} cyhal_resource_inst_t; #if defined(__cplusplus) } #endif /* __cplusplus */ -/** \} group_hal_hw_resources */ +/** \} group_hal_psoc6_hw_types */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hw_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hw_types.h index da78744306f..5548ffc6b86 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hw_types.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hw_types.h @@ -23,13 +23,11 @@ *******************************************************************************/ /** -* \addtogroup group_hal_hw_types PSoC 6 Hardware Types +* \addtogroup group_hal_psoc6_hw_types Implementation-defined types * \ingroup group_hal_psoc6 * \{ -* Struct definitions for configuration resources in the PDL. -* -* \defgroup group_hal_hw_types_macros Macros -* \defgroup group_hal_hw_types_data_structures Data Structures +* Aliases for types which are part of the public HAL interface but whose representations are +* need to vary per HAL implementation */ #pragma once @@ -47,16 +45,16 @@ extern "C" { #endif -/** -* \addtogroup group_hal_hw_types_macros -* \{ -*/ -/** Default priority for interrupts */ #ifndef CYHAL_ISR_PRIORITY_DEFAULT +/** Default priority for interrupts */ #define CYHAL_ISR_PRIORITY_DEFAULT (7) #endif +/** +* \cond INTERNAL +*/ + #define CYHAL_CRC_IMPL_HEADER "cyhal_crc_impl.h" //!< Implementation specific header for CRC #define CYHAL_GPIO_IMPL_HEADER "cyhal_gpio_impl.h" //!< Implementation specific header for GPIO #define CYHAL_PWM_IMPL_HEADER "cyhal_pwm_impl.h" //!< Implementation specific header for PWM @@ -64,33 +62,50 @@ extern "C" { #define CYHAL_TIMER_IMPL_HEADER "cyhal_timer_impl.h" //!< Implementation specific header for Timer #define CYHAL_TRNG_IMPL_HEADER "cyhal_trng_impl.h" //!< Implementation specific header for TRNG -/** \} group_hal_hw_types_macros */ +/** \endcond */ /** -* \addtogroup group_hal_hw_types_data_structures -* \{ */ - typedef uint32_t cyhal_source_t; //!< Routable signal source typedef uint32_t cyhal_dest_t; //!< Routable signal destination +/** Callbacks for Sleep and Deepsleep APIs */ +#define cyhal_system_callback_t cy_stc_syspm_callback_t + /** Available clock divider types */ typedef cy_en_divider_types_t cyhal_clock_divider_types_t; -/** Clock divider object */ +/** Divider for CM4, CM0 and Peri clock. Supports values between [1, 256] */ +typedef uint16_t cyhal_system_divider_t; + +/** Enum for clock type to configure. HFCLKs are configured using different APIs and does not using this enum */ +typedef enum +{ + CYHAL_SYSTEM_CLOCK_CM4, + CYHAL_SYSTEM_CLOCK_CM0, + CYHAL_SYSTEM_CLOCK_PERI, +} cyhal_system_clock_t; + +/** @brief Clock divider object */ typedef struct { cyhal_clock_divider_types_t div_type; uint8_t div_num; } cyhal_clock_divider_t; -/** Event callback data object */ +/** @brief Event callback data object */ typedef struct { cy_israddress callback; void* callback_arg; } cyhal_event_callback_data_t; +/** +* \addtogroup group_hal_psoc6_hw_types_handle Instance Handles +* \{ +* Structs which retain data which needs to persist across HAL API calls. From the perspective of the +* generic HAL interface, these are opaque; the contents are specific to this implementation. +*/ -/** ADC object */ +/** @brief ADC object */ typedef struct { #ifdef CY_IP_MXS40PASS_SAR SAR_Type* base; @@ -105,7 +120,7 @@ typedef struct { #endif } cyhal_adc_t; -/** ADC channel object */ +/** @brief ADC channel object */ typedef struct { #ifdef CY_IP_MXS40PASS_SAR cyhal_adc_t* adc; @@ -116,7 +131,7 @@ typedef struct { #endif } cyhal_adc_channel_t; -/** Comparator object */ +/** @brief Comparator object */ typedef struct { #if defined(CY_IP_MXLPCOMP_INSTANCES) || defined(PASS_NR_CTBS) /* TODO: define */ @@ -126,7 +141,7 @@ typedef struct { #endif } cyhal_comp_t; -/** CRC object */ +/** @brief CRC object */ typedef struct { #if defined(CY_IP_MXCRYPTO_INSTANCES) || defined(CPUSS_CRYPTO_PRESENT) CRYPTO_Type* base; @@ -135,7 +150,7 @@ typedef struct { #endif } cyhal_crc_t; -/** DAC object */ +/** @brief DAC object */ typedef struct { #ifdef CY_IP_MXS40PASS_CTDAC CTDAC_Type* base; @@ -146,7 +161,7 @@ typedef struct { #endif } cyhal_dac_t; -/** DMA object */ +/** @brief DMA object */ typedef struct { #if defined(CY_IP_M4CPUSS_DMAC_INSTANCES) || defined(CY_IP_M4CPUSS_DMA_INSTANCES) cyhal_resource_inst_t resource; @@ -155,12 +170,12 @@ typedef struct { #endif } cyhal_dma_t; -/** Flash object */ +/** @brief Flash object */ typedef struct { void *empty; } cyhal_flash_t; -/** I2C object */ +/** @brief I2C object */ typedef struct { #ifdef CY_IP_MXSCB CySCB_Type* base; @@ -184,7 +199,7 @@ typedef struct { #endif } cyhal_i2c_t; -/** I2S object */ +/** @brief I2S object */ typedef struct { #ifdef CY_IP_MXAUDIOSS_INSTANCES /* TODO: define */ @@ -194,7 +209,7 @@ typedef struct { #endif } cyhal_i2s_t; -/** LPTIMER object */ +/** @brief LPTIMER object */ typedef struct { #ifdef CY_IP_MXS40SRSS_MCWDT_INSTANCES MCWDT_STRUCT_Type *base; @@ -205,7 +220,7 @@ typedef struct { #endif } cyhal_lptimer_t; -/** OpAmp object */ +/** @brief OpAmp object */ typedef struct { #ifdef PASS_NR_CTBS /* TODO: define */ @@ -215,7 +230,7 @@ typedef struct { #endif } cyhal_opamp_t; -/** PDM-PCM object */ +/** @brief PDM-PCM object */ typedef struct { #ifdef CY_IP_MXAUDIOSS_INSTANCES /* TODO: define */ @@ -225,7 +240,7 @@ typedef struct { #endif } cyhal_pdm_pcm_t; -/** PWM object */ +/** @brief PWM object */ typedef struct { #ifdef CY_IP_MXTCPWM TCPWM_Type* base; @@ -240,7 +255,7 @@ typedef struct { #endif } cyhal_pwm_t; -/** SMIF object */ +/** @brief SMIF object */ typedef struct { #ifdef CY_IP_MXSMIF SMIF_Type* base; @@ -260,7 +275,7 @@ typedef struct { #endif /* ifdef CY_IP_MXSMIF */ } cyhal_qspi_t; -/** RNG object */ +/** @brief RNG object */ typedef struct { #if defined(CY_IP_MXCRYPTO_INSTANCES) || defined(CPUSS_CRYPTO_PRESENT) CRYPTO_Type* base; @@ -268,12 +283,12 @@ typedef struct { #endif } cyhal_trng_t; -/** RTC object */ +/** @brief RTC object */ typedef struct { uint8_t placeholder; } cyhal_rtc_t; -/** SDHC object */ +/** @brief SDHC object */ typedef struct { #ifdef CY_IP_MXSDHC SDHC_Type* base; @@ -298,7 +313,7 @@ typedef struct { #endif } cyhal_sdhc_t; -/** SDIO object */ +/** @brief SDIO object */ typedef struct { #if defined(CY_IP_MXSDHC) SDHC_Type* base; @@ -346,7 +361,7 @@ typedef struct { #endif /* defined(CY_IP_MXSDHC) */ } cyhal_sdio_t; -/** SPI object */ +/** @brief SPI object */ typedef struct { #ifdef CY_IP_MXSCB CySCB_Type* base; @@ -377,21 +392,7 @@ typedef struct { #endif } cyhal_spi_t; -/** Callbacks for Sleep and Deepsleep APIs */ -#define cyhal_system_callback_t cy_stc_syspm_callback_t - -/** Enum for clock type to configure. HFCLKs are configured using different APIs and does not using this enum */ -typedef enum -{ - CYHAL_SYSTEM_CLOCK_CM4, - CYHAL_SYSTEM_CLOCK_CM0, - CYHAL_SYSTEM_CLOCK_PERI, -} cyhal_system_clock_t; - -/** Divider for CM4, CM0 and Peri clock. Supports values between [1, 256] */ -typedef uint16_t cyhal_system_divider_t; - -/** Timer object */ +/** @brief Timer object */ typedef struct { #ifdef CY_IP_MXTCPWM TCPWM_Type* base; @@ -409,7 +410,7 @@ typedef struct { #endif } cyhal_timer_t; -/** UART object */ +/** @brief UART object */ typedef struct { #ifdef CY_IP_MXSCB CySCB_Type* base; @@ -433,7 +434,7 @@ typedef struct { #endif } cyhal_uart_t; -/** USB Device object */ +/** @brief USB Device object */ typedef struct { #ifdef CY_IP_MXUSBFS USBFS_Type* base; @@ -451,15 +452,15 @@ typedef struct { #endif } cyhal_usb_dev_t; -/** WDT object */ +/** @brief WDT object */ typedef struct { uint8_t placeholder; } cyhal_wdt_t; -/** \} group_hal_hw_types_data_structures */ +/** \} group_hal_psoc6_hw_types_handles */ #if defined(__cplusplus) } #endif /* __cplusplus */ -/** \} group_hal_hw_types */ +/** \} group_hal_psoc6_hw_types */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hwmgr.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hwmgr.h index b7c48eb7c85..35f076cf78f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hwmgr.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hwmgr.h @@ -29,10 +29,6 @@ * \ingroup group_hal * \{ * High level interface for interacting with the Cypress Hardware Manager. -* -* \defgroup group_hal_hwmgr_macros Macros -* \defgroup group_hal_hwmgr_functions Functions -* \defgroup group_hal_hwmgr_data_structures Data Structures */ #pragma once @@ -47,11 +43,6 @@ extern "C" { #endif -/** -* \addtogroup group_hal_hwmgr_macros -* \{ -*/ - /** The requested resource type is invalid */ #define CYHAL_HWMGR_RSLT_ERR_INVALID (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_CHIP_HWMGR, 0)) /** The requested resource is already in use */ @@ -62,14 +53,6 @@ extern "C" { /** Attempt to free a resource that was not used */ #define CYHAL_HWMGR_RSLT_WARN_UNUSED (CY_RSLT_CREATE(CY_RSLT_TYPE_WARNING, CYHAL_RSLT_MODULE_CHIP_HWMGR, 50)) -/** \} group_hal_hwmgr_macros */ - - -/** -* \addtogroup group_hal_hwmgr_functions -* \{ -*/ - /** Initializes the hardware manager to keep track of what resources are being used. * * @return The status of the init request @@ -119,8 +102,6 @@ cy_rslt_t cyhal_hwmgr_allocate_clock(cyhal_clock_divider_t* obj, cyhal_clock_div */ void cyhal_hwmgr_free_clock(cyhal_clock_divider_t* obj); -/** \} group_hal_hwmgr_functions */ - #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_i2c.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_i2c.h index 5b8dfbfd39f..35e9cc32469 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_i2c.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_i2c.h @@ -30,11 +30,9 @@ * \ingroup group_hal * \{ * High level interface for interacting with the Cypress I2C. -* -* \defgroup group_hal_i2c_macros Macros -* \defgroup group_hal_i2c_functions Functions -* \defgroup group_hal_i2c_data_structures Data Structures -* \defgroup group_hal_i2c_enums Enumerated Types +* +* \defgroup group_hal_i2c_master Master +* \defgroup group_hal_i2c_slave Slave */ #pragma once @@ -49,11 +47,6 @@ extern "C" { #endif -/** -* \addtogroup group_hal_i2c_macros -* \{ -*/ - /** The requested resource type is invalid */ #define CYHAL_I2C_RSLT_ERR_INVALID_PIN (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_I2C, 0)) /** Can not reach desired data rate */ @@ -61,14 +54,6 @@ extern "C" { /** Address size is not correct, should be 1 or two */ #define CYHAL_I2C_RSLT_ERR_INVALID_ADDRESS_SIZE (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_I2C, 2)) -/** \} group_hal_i2c_macros */ - - -/** -* \addtogroup group_hal_i2c_enums -* \{ -*/ - /** Enum to enable/disable/report interrupt cause flags. */ typedef enum { @@ -86,18 +71,10 @@ typedef enum CYHAL_I2C_MASTER_ERR_EVENT = 1 << 20, /* Indicates the I2C hardware has detected an error. */ } cyhal_i2c_event_t; -/** \} group_hal_i2c_enums */ - - -/** -* \addtogroup group_hal_i2c_data_structures -* \{ -*/ - /** Handler for I2C events */ typedef void (*cyhal_i2c_event_callback_t)(void *callback_arg, cyhal_i2c_event_t event); -/** Initial I2C configuration */ +/** @brief Initial I2C configuration */ typedef struct { bool is_slave; /* I2C mode, is the device a master or slave */ @@ -105,14 +82,6 @@ typedef struct uint32_t frequencyhal_hz; /* Frequency that the I2C bus runs at */ } cyhal_i2c_cfg_t; -/** \} group_hal_i2c_data_structures */ - - -/** -* \addtogroup group_hal_i2c_functions -* \{ -*/ - /** Initialize the I2C peripheral, and configures its specifieds pins. By default * it is setup as a Master running at 400kHz. This can be changed by calling * cyhal_i2c_configure(). @@ -141,6 +110,11 @@ void cyhal_i2c_free(cyhal_i2c_t *obj); */ cy_rslt_t cyhal_i2c_configure(cyhal_i2c_t *obj, const cyhal_i2c_cfg_t *cfg); +/** +* \addtogroup group_hal_i2c_master +* \{ +*/ + /** * I2C master write * @@ -169,6 +143,13 @@ cy_rslt_t cyhal_i2c_master_write(cyhal_i2c_t *obj, uint16_t dev_addr, const uint */ cy_rslt_t cyhal_i2c_master_read(cyhal_i2c_t *obj, uint16_t dev_addr, uint8_t *data, uint16_t size, uint32_t timeout, bool send_stop); +/** \} group_hal_i2c_master */ + +/** +* \addtogroup group_hal_i2c_slave +* \{ +*/ + /** * I2C slave config write buffer * The user needs to setup a new buffer every time (i.e. call slave_send and slave_recv every time the buffer has been used up) @@ -193,6 +174,13 @@ cy_rslt_t cyhal_i2c_slave_config_write_buff(cyhal_i2c_t *obj, const uint8_t *dat */ cy_rslt_t cyhal_i2c_slave_config_read_buff(cyhal_i2c_t *obj, uint8_t *data, uint16_t size); +/** \} group_hal_i2c_slave */ + +/** +* \addtogroup group_hal_i2c_master +* \{ +*/ + /** Perform an i2c write using a block of data stored at the specified memory location * * @param[in] obj The I2C object @@ -231,6 +219,8 @@ cy_rslt_t cyhal_i2c_master_mem_read(cyhal_i2c_t *obj, uint16_t address, uint16_t */ cy_rslt_t cyhal_i2c_master_transfer_async(cyhal_i2c_t *obj, uint16_t address, const void *tx, size_t tx_size, void *rx, size_t rx_size); +/** \} group_hal_i2c_master */ + /** Abort asynchronous transfer * * This function does not perform any check - that should happen in upper layers. @@ -256,8 +246,6 @@ void cyhal_i2c_register_callback(cyhal_i2c_t *obj, cyhal_i2c_event_callback_t ca */ void cyhal_i2c_enable_event(cyhal_i2c_t *obj, cyhal_i2c_event_t event, uint8_t intrPriority, bool enable); -/** \} group_hal_i2c_functions */ - /******************************************************************************* * Backward compatibility macro. The following code is DEPRECATED and must * not be used in new projects diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_interconnect.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_interconnect.h index 1875c015608..390633cb5b1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_interconnect.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_interconnect.h @@ -30,11 +30,6 @@ * \ingroup group_hal * \{ * High level interface for interacting with the Cypress digital routing. -* -* \defgroup group_hal_interconnect_macros Macros -* \defgroup group_hal_interconnect_functions Functions -* \defgroup group_hal_interconnect_data_structures Data Structures -* \defgroup group_hal_interconnect_enums Enumerated Types */ #pragma once @@ -49,11 +44,6 @@ extern "C" { #endif -/** -* \addtogroup group_hal_interconnect_macros -* \{ -*/ - /** No connection is available */ #define CYHAL_CONNECT_RSLT_NO_CONNECTION (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_INTERCONNECT, 0)) /** The connections source and destination are already connected */ @@ -64,14 +54,6 @@ extern "C" { /** Indicates that a mux output does not continue to another mux */ #define CYHAL_INTERCONNECT_MUX_NOT_CONTINUATION 0xFF -/** \} group_hal_interconnect_macros */ - - -/** -* \addtogroup group_hal_interconnect_functions -* \{ -*/ - /** Connect a pin to a peripheral terminal. This will route a direct connect from the pin to the peripheral. * Any previous direct connection from the pin will be overriden. * @param[in] pin_connection Details about the pin and its target connection @@ -95,8 +77,6 @@ cy_rslt_t cyhal_disconnect_pin(cyhal_gpio_t pin); */ cy_rslt_t cyhal_connect_trigger(cyhal_source_t source, cyhal_dest_t dest); -/** \} group_hal_interconnect_functions */ - #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_lptimer.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_lptimer.h index b38cee8c132..5f77945d292 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_lptimer.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_lptimer.h @@ -30,11 +30,6 @@ * \ingroup group_hal * \{ * High level interface for interacting with the Cypress LPTIMER. -* -* \defgroup group_hal_lptimer_macros Macros -* \defgroup group_hal_lptimer_functions Functions -* \defgroup group_hal_lptimer_data_structures Data Structures -* \defgroup group_hal_lptimer_enums Enumerated Types */ #pragma once @@ -48,35 +43,14 @@ extern "C" { #endif -/** -* \addtogroup group_hal_lptimer_enums -* \{ -*/ - /** LPTIMER interrupt triggers */ typedef enum { CYHAL_LPTIMER_COMPARE_MATCH, } cyhal_lptimer_event_t; -/** \} group_hal_lptimer_enums */ - - -/** -* \addtogroup group_hal_lptimer_data_structures -* \{ -*/ - /** Handler for LPTIMER interrupts */ typedef void (*cyhal_lptimer_event_callback_t)(void *callback_arg, cyhal_lptimer_event_t event); -/** \} group_hal_lptimer_data_structures */ - - -/** -* \addtogroup group_hal_lptimer_functions -* \{ -*/ - /** Initialize the LPTIMER * * Initialize or re-initialize the LPTIMER. This resets all the @@ -168,8 +142,6 @@ void cyhal_lptimer_enable_event(cyhal_lptimer_t *obj, cyhal_lptimer_event_t even */ void cyhal_lptimer_irq_trigger(cyhal_lptimer_t *obj); -/** \} group_hal_lptimer_functions */ - #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_modules.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_modules.h index f7855517489..d53cf526e97 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_modules.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_modules.h @@ -24,12 +24,8 @@ *******************************************************************************/ /** -* \addtogroup group_hal_modules Driver Modules * \ingroup group_hal * \{ -* Enum definition for all HAL resource modules. -* -* \defgroup group_hal_modules_enums Enumerated Types */ #pragma once @@ -40,12 +36,6 @@ extern "C" { #endif - -/** -* \addtogroup group_hal_modules_enums -* \{ -*/ - /** Enum to in indicate which module an errors occurred in. */ enum cyhal_rslt_module_chip { @@ -76,10 +66,8 @@ enum cyhal_rslt_module_chip CYHAL_RSLT_MODULE_WDT, //!< An error occurred in WDT module }; -/** \} group_hal_modules_enums */ - #if defined(__cplusplus) } #endif /* __cplusplus */ -/** \} group_hal_modules */ +/** \} group_hal */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pin_package.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pin_package.h index 6957d909482..1063a599d49 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pin_package.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pin_package.h @@ -23,15 +23,10 @@ *******************************************************************************/ /** -* \addtogroup group_hal_pin_package PSoC 6 Pin Packages +* \addtogroup group_hal_psoc6_pin_package Pins * \ingroup group_hal_psoc6 * \{ * Definitions for the pinout for each supported device -* -* \defgroup group_hal_pin_package_macros Macros -* \defgroup group_hal_pin_package_functions Functions -* \defgroup group_hal_pin_package_data_structures Data Structures -* \defgroup group_hal_pin_package_enums Enumerated Types */ #pragma once @@ -42,11 +37,6 @@ extern "C" { #endif /* __cplusplus */ -/** -* \addtogroup group_hal_pin_package_enums -* \{ -*/ - /** Port names */ typedef enum { CYHAL_PORT_0 = 0x0, @@ -67,25 +57,19 @@ typedef enum { CYHAL_PORT_15 = 0xF, } cyhal_port_t; -/** \} group_hal_pin_package_enums */ - - -/** -* \addtogroup group_hal_pin_package_data_structures -* \{ -*/ - -/** GPIO pin configuration object */ +/** Bitfield representing the configuration of a GPIO (hsiom selection and mode). + * Use the CY_GPIO_CFG_GET_MODE and CY_GPIO_CFG_GET_HSIOM to extract the + * individual field values. + */ typedef uint16_t cyhal_gpio_mapping_cfg_t; // 8bit hsiom, 8bit mode -/** \} group_hal_pin_package_data_structures */ - +/** Extract the GPIO mode setting from a cyhal_gpio_mapping_cfg_t */ +#define CY_GPIO_CFG_GET_MODE(x) ((uint8_t)((x) & 0xFF)) +/** Extract the HSIOM selection from a cyhal_gpio_mapping_cfg_t */ +#define CY_GPIO_CFG_GET_HSIOM(x) ((en_hsiom_sel_t)(((x) >> 8) & 0xFF)) /** \cond INTERNAL */ - #define CY_GPIO_CFG_CREATE(hsiom, mode) ((cyhal_gpio_mapping_cfg_t)(((hsiom) << 8) + (mode))) -#define CY_GPIO_CFG_GET_MODE(x) ((uint8_t)((x) & 0xFF)) -#define CY_GPIO_CFG_GET_HSIOM(x) ((en_hsiom_sel_t)(((x) >> 8) & 0xFF)) #define CYHAL_PIN_OUT_FUNCTION(hsiom) CY_GPIO_CFG_CREATE(hsiom, CY_GPIO_DM_STRONG_IN_OFF) #define CYHAL_PIN_OUT_BUF_FUNCTION(hsiom) CY_GPIO_CFG_CREATE(hsiom, CY_GPIO_DM_STRONG) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pwm.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pwm.h index 4ea56fb1558..b7cf1e09a05 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pwm.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pwm.h @@ -30,11 +30,6 @@ * \ingroup group_hal * \{ * High level interface for interacting with the Cypress PWM. -* -* \defgroup group_hal_pwm_macros Macros -* \defgroup group_hal_pwm_functions Functions -* \defgroup group_hal_pwm_data_structures Data Structures -* \defgroup group_hal_pwm_enums Enumerated Types */ #pragma once @@ -48,11 +43,6 @@ extern "C" { #endif -/** -* \addtogroup group_hal_pwm_macros -* \{ -*/ - /** Bad argument */ #define CYHAL_PWM_RSLT_BAD_ARGUMENT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_PWM, 0)) /** Failed to initialize PWM clock */ @@ -60,14 +50,6 @@ extern "C" { /** Failed to initialize PWM */ #define CYHAL_PWM_RSLT_FAILED_INIT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_PWM, 2)) -/** \} group_hal_pwm_macros */ - - -/** -* \addtogroup group_hal_pwm_enums -* \{ -*/ - /** PWM interrupt triggers */ typedef enum { CYHAL_PWM_IRQ_NONE = 0, @@ -76,25 +58,9 @@ typedef enum { CYHAL_PWM_IRQ_ALL = (1 << 2) - 1, } cyhal_pwm_event_t; -/** \} group_hal_pwm_enums */ - - -/** -* \addtogroup group_hal_pwm_data_structures -* \{ -*/ - /** Handler for PWM interrupts */ typedef void(*cyhal_pwm_event_callback_t)(void *callback_arg, cyhal_pwm_event_t event); -/** \} group_hal_pwm_data_structures */ - - -/** -* \addtogroup group_hal_pwm_functions -* \{ -*/ - /** Initialize the PWM out peripheral and configure the pin * * @param[out] obj The PWM object to initialize @@ -159,8 +125,6 @@ void cyhal_pwm_register_callback(cyhal_pwm_t *obj, cyhal_pwm_event_callback_t ca */ void cyhal_pwm_enable_event(cyhal_pwm_t *obj, cyhal_pwm_event_t event, uint8_t intrPriority, bool enable); -/** \} group_hal_pwm_functions */ - #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_qspi.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_qspi.h index d99c8732586..b3ba4d91233 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_qspi.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_qspi.h @@ -30,11 +30,6 @@ * \ingroup group_hal * \{ * High level interface for interacting with the Cypress Quad-SPI. -* -* \defgroup group_hal_qspi_macros Macros -* \defgroup group_hal_qspi_functions Functions -* \defgroup group_hal_qspi_data_structures Data Structures -* \defgroup group_hal_qspi_enums Enumerated Types */ #pragma once @@ -49,11 +44,6 @@ extern "C" { #endif -/** -* \addtogroup group_hal_qspi_enums -* \{ -*/ - /** QSPI Bus width * * Some parts of commands provide variable bus width @@ -80,27 +70,12 @@ typedef enum { CYHAL_QSPI_IRQ_RECEIVE_DONE = 1 << 1, /**< Async receive done. >*/ } cyhal_qspi_event_t; -/** \} group_hal_qspi_enums */ - -/** -* \addtogroup group_hal_qspi_macros -* \{ -*/ - #define CYHAL_QSPI_RSLT_ERR_BUS_WIDTH (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 0)) /**< Bus width Error. >*/ #define CYHAL_QSPI_RSLT_ERR_PIN (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 1)) /**< Pin related Error. >*/ #define CYHAL_QSPI_RSLT_ERR_DATA_SEL (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 2)) /**< Data select Error. >*/ #define CYHAL_QSPI_RSLT_ERR_INSTANCE (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 3)) /**< QSPI instance related Error. >*/ -/** \} group_hal_qspi_macros */ - - -/** -* \addtogroup group_hal_qspi_data_structures -* \{ -*/ - -/** QSPI command settings */ +/** @brief QSPI command settings */ typedef struct cyhal_qspi_command { struct { cyhal_qspi_bus_width_t bus_width; /**< Bus width for the instruction >*/ @@ -128,14 +103,6 @@ typedef struct cyhal_qspi_command { /** Handler for QSPI callbacks */ typedef void (*cyhal_qspi_event_callback_t)(void *callback_arg, cyhal_qspi_event_t event); -/** \} group_hal_qspi_data_structures */ - - -/** -* \addtogroup group_hal_qspi_functions -* \{ -*/ - /** Initialize QSPI peripheral. * * It should initialize QSPI pins (io0-io7, sclk and ssel), set frequency, clock polarity and phase mode. @@ -256,8 +223,6 @@ void cyhal_qspi_register_callback(cyhal_qspi_t *obj, cyhal_qspi_event_callback_t */ void cyhal_qspi_enable_event(cyhal_qspi_t *obj, cyhal_qspi_event_t event, uint8_t intrPriority, bool enable); -/** \} group_hal_qspi_functions */ - #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_rtc.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_rtc.h index 18e4fc5f3d2..e49fe882219 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_rtc.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_rtc.h @@ -30,11 +30,6 @@ * \ingroup group_hal * \{ * High level interface for interacting with the Cypress RTC. -* -* \defgroup group_hal_rtc_macros Macros -* \defgroup group_hal_rtc_functions Functions -* \defgroup group_hal_rtc_data_structures Data Structures -* \defgroup group_hal_rtc_enums Enumerated Types */ #pragma once @@ -53,25 +48,12 @@ extern "C" { #endif -/** -* \addtogroup group_hal_rtc_enums -* \{ -*/ - /** RTC interrupt triggers */ typedef enum { CYHAL_RTC_ALARM, } cyhal_rtc_event_t; -/** \} group_hal_rtc_enums */ - - -/** -* \addtogroup group_hal_rtc_data_structures -* \{ -*/ - -/** Defines which fields should be active for the alarm. */ +/** @brief Defines which fields should be active for the alarm. */ typedef struct { uint8_t en_sec : 1; /** !< Enable match of seconds */ @@ -85,14 +67,6 @@ typedef struct /** Handler for RTC events */ typedef void (*cyhal_rtc_event_callback_t)(void *callback_arg, cyhal_rtc_event_t event); -/** \} group_hal_rtc_data_structures */ - - -/** -* \addtogroup group_hal_rtc_functions -* \{ -*/ - /** Initialize the RTC peripheral * * Powerup the RTC in preparation for access. This function must be called @@ -167,8 +141,6 @@ void cyhal_rtc_register_callback(cyhal_rtc_t *obj, cyhal_rtc_event_callback_t ca */ void cyhal_rtc_enable_event(cyhal_rtc_t *obj, cyhal_rtc_event_t event, uint8_t intrPriority, bool enable); -/** \} group_hal_rtc_functions */ - #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_scb_common.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_scb_common.h index 27c8e1a561f..e1a00765c52 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_scb_common.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_scb_common.h @@ -23,16 +23,10 @@ *******************************************************************************/ /** - * \addtogroup group_hal_scb_common PSoC 6 SCB Common Functionality + * \addtogroup group_hal_psoc6_scb_common SCB Common Functionality * \ingroup group_hal_psoc6 * \{ * Code shared between the SCB resources (UART, I2C, and SPI). - * - * \defgroup group_hal_scb_common_macros Macros - * \defgroup group_hal_scb_common_constants Constants - * \defgroup group_hal_scb_common_functions Functions - * \defgroup group_hal_scb_common_data_structures Data Structures - * \defgroup group_hal_scb_common_enums Enumerated Types */ #pragma once @@ -45,11 +39,6 @@ extern "C" { #endif -/** - * \addtogroup group_hal_scb_common_constants - * \{ - */ - /** The start address of the SCB blocks */ extern CySCB_Type* const CYHAL_SCB_BASE_ADDRESSES[CY_IP_MXSCB_INSTANCES]; /** The interrupt number of the SCB blocks. */ @@ -58,13 +47,6 @@ extern const IRQn_Type CYHAL_SCB_IRQ_N[CY_IP_MXSCB_INSTANCES]; /** The configuration structs for the resource in use on each SCB block (e.g. cyhal_i2c_t) */ extern void *cyhal_scb_config_structs[CY_IP_MXSCB_INSTANCES]; -/** \} group_hal_scb_common_constants */ - - -/** - * \addtogroup group_hal_scb_common_functions - * \{ - */ /** Get the SCB block corresponding to an IRQn. * @@ -84,10 +66,8 @@ __STATIC_INLINE void *cyhal_scb_get_irq_obj(void) return cyhal_scb_config_structs[block]; } -/** \} group_hal_scb_common_functions */ - #if defined(__cplusplus) } #endif -/** \} group_hal_scb_common */ \ No newline at end of file +/** \} group_hal_psoc6_scb_common */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_sdhc.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_sdhc.h index 51d1a3b5b21..6cd2fc9eb82 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_sdhc.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_sdhc.h @@ -30,11 +30,6 @@ * \ingroup group_hal * \{ * High level interface for interacting with the Cypress SDHC. -* -* \defgroup group_hal_sdhc_macros Macros -* \defgroup group_hal_sdhc_functions Functions -* \defgroup group_hal_sdhc_data_structures Data Structures -* \defgroup group_hal_sdhc_enums Enumerated Types */ #pragma once @@ -48,21 +43,8 @@ extern "C" { #endif -/** -* \addtogroup group_hal_sdhc_macros -* \{ -*/ - #define CYHAL_SDHC_RSLT_ERR_PIN (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDHC, 0)) /**< Pin related Error. >*/ -/** \} group_hal_sdhc_macros */ - - -/** -* \addtogroup group_hal_sdhc_enums -* \{ -*/ - /** Card types */ typedef enum { @@ -95,28 +77,12 @@ typedef enum { CYHAL_SDHC_ALL_INTERRUPTS = 0xFFFF, //!> Is used to enable/disable all interrupts } cyhal_sdhc_event_t; -/** \} group_hal_sdhc_enums */ - - -/** -* \addtogroup group_hal_sdhc_macros -* \{ -*/ - #define CYHAL_SDHC_RSLT_ERR_PIN (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDHC, 0)) /**< Pin related Error. >*/ -/** \} group_hal_sdhc_macros */ - - -/** -* \addtogroup group_hal_sdhc_data_structures -* \{ -*/ - /** Handler for SDHC interrupts */ typedef void (*cyhal_sdhc_event_callback_t)(void *callback_arg, cyhal_sdhc_event_t event); -/** Defines configuration options for the SDHC block */ +/** @brief Defines configuration options for the SDHC block */ typedef struct { bool enableLedControl; //!< Drive one IO to indicate when the card is being accessed @@ -125,14 +91,6 @@ typedef struct uint8_t busWidth; //!< The desired bus width } cyhal_sdhc_config_t; -/** \} group_hal_sdhc_data_structures */ - - -/** -* \addtogroup group_hal_sdhc_functions -* \{ -*/ - /** Initialize the SDHC peripheral * * @param[out] obj The SDHC object @@ -261,8 +219,6 @@ void cyhal_sdhc_register_callback(cyhal_sdhc_t *obj, cyhal_sdhc_event_callback_t */ void cyhal_sdhc_enable_event(cyhal_sdhc_t *obj, cyhal_sdhc_event_t event, uint8_t intrPriority, bool enable); -/** \} group_hal_sdhc_functions */ - #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_sdio.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_sdio.h index 21ae340a184..d5e396eca88 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_sdio.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_sdio.h @@ -31,10 +31,6 @@ * \{ * High level interface for interacting with the Cypress SDIO interface. * -* \defgroup group_hal_sdio_macros Macros -* \defgroup group_hal_sdio_functions Functions -* \defgroup group_hal_sdio_data_structures Data Structures -* \defgroup group_hal_sdio_enums Enumerated Types */ #pragma once @@ -48,11 +44,10 @@ extern "C" { #endif - /** -* \addtogroup group_hal_sdio_macros -* \{ -*/ + * \addtogroup group_hal_sdio_errors Error Codes + * \{ + */ #define CYHAL_SDIO_RET_NO_ERRORS (0x00) /**< No error*/ #define CYHAL_SDIO_RET_NO_SP_ERRORS (0x01) /**< Non-specific error code*/ @@ -96,12 +91,7 @@ extern "C" { CYHAL_RSLT_MODULE_SDIO, \ CYHAL_SDIO_CANCELED) -/** \} group_hal_sdio_macros */ - -/** -* \addtogroup group_hal_sdio_enums -* \{ -*/ +/** \} group_hal_sdio_errors */ /** Commands that can be issued */ typedef enum @@ -149,15 +139,7 @@ typedef enum { CYHAL_SDIO_ALL_INTERRUPTS = 0x0E1FF, //!> Is used to enable/disable all interrupts events } cyhal_sdio_event_t; -/** \} group_hal_sdio_enums */ - - -/** -* \addtogroup group_hal_sdio_data_structures -* \{ -*/ - -/** SDIO controller initial configuration */ +/** @brief SDIO controller initial configuration */ typedef struct { uint32_t frequencyhal_hz; //!< Clock frequency, in hertz @@ -167,14 +149,6 @@ typedef struct /** Callback for SDIO events */ typedef void (*cyhal_sdio_event_callback_t)(void *callback_arg, cyhal_sdio_event_t event); -/** \} group_hal_sdio_data_structures */ - - -/** -* \addtogroup group_hal_sdio_functions -* \{ -*/ - /** Initialize the SDIO peripheral * * @param[out] obj The SDIO object @@ -270,8 +244,6 @@ void cyhal_sdio_register_callback(cyhal_sdio_t *obj, cyhal_sdio_event_callback_t */ void cyhal_sdio_enable_event(cyhal_sdio_t *obj, cyhal_sdio_event_t event, uint8_t intrPriority, bool enable); -/** \} group_hal_sdio_functions */ - /******************************************************************************* * Backward compatibility macro. The following code is DEPRECATED and must * not be used in new projects diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_spi.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_spi.h index d242c050e40..ca6f24a08ba 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_spi.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_spi.h @@ -30,11 +30,6 @@ * \ingroup group_hal * \{ * High level interface for interacting with the Cypress SPI. -* -* \defgroup group_hal_spi_macros Macros -* \defgroup group_hal_spi_functions Functions -* \defgroup group_hal_spi_data_structures Data Structures -* \defgroup group_hal_spi_enums Enumerated Types */ #pragma once @@ -50,11 +45,6 @@ extern "C" { #endif -/** -* \addtogroup group_hal_spi_macros -* \{ -*/ - /** Bad argument */ #define CYHAL_SPI_RSLT_BAD_ARGUMENT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 0)) /** Failed to initialize SPI clock */ @@ -70,8 +60,6 @@ extern "C" { /** The requested resource type is invalid */ #define CYHAL_SPI_RSLT_ERR_INVALID_PIN (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 7)) -/** \} group_hal_spi_macros */ - /** Compatibility define for cyhal_spi_set_frequency. */ #define cyhal_spi_frequency cyhal_spi_set_frequency @@ -109,7 +97,7 @@ typedef enum CYHAL_SPI_MODE_11_LSB, } cyhal_spi_mode_t; -/** Initial SPI configuration. */ +/** @brief Initial SPI configuration. */ typedef struct { cyhal_spi_mode_t mode; //!< The operating mode @@ -251,8 +239,6 @@ void cyhal_spi_enable_event(cyhal_spi_t *obj, cyhal_spi_event_t event, uint8_t i typedef cyhal_spi_event_t cyhal_spi_irq_event_t; /** \endcond */ -/** \} group_hal_spi_functions */ - #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_system.h index d30ff720253..d5f994a0190 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_system.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_system.h @@ -31,11 +31,6 @@ * \{ * High level interface for interacting with the Cypress power management * and system clock configuration. -* -* \defgroup group_hal_system_macros Macros -* \defgroup group_hal_system_functions Functions -* \defgroup group_hal_system_data_structures Data Structures -* \defgroup group_hal_system_enums Enumerated Types */ #pragma once @@ -50,11 +45,6 @@ extern "C" { #endif -/** -* \addtogroup group_hal_system_macros -* \{ -*/ - /** An error occurred in System module */ #define CYHAL_SYSTEM_RSLT_ERROR (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SYSTEM , 0)) /** An error occurred in System module */ @@ -66,14 +56,6 @@ extern "C" { /** An error occurred in System module */ #define CYHAL_SYSTEM_RSLT_NO_VALID_DIVIDER (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SYSTEM , 4)) -/** \} group_hal_system_macros */ - - -/** -* \addtogroup group_hal_system_functions -* \{ -*/ - /** Enter a critical section * * Disables interrupts and returns a value indicating whether the interrupts were previously @@ -156,8 +138,6 @@ cy_rslt_t cyhal_system_clock_set_frequency(uint8_t clock, uint32_t frequency_hz) */ cy_rslt_t cyhal_system_clock_set_divider(cyhal_system_clock_t clock, cyhal_system_divider_t divider); -/** \} group_hal_system_functions */ - #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_tcpwm_common.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_tcpwm_common.h index 6371f80fe43..faa9d44ddbf 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_tcpwm_common.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_tcpwm_common.h @@ -23,16 +23,10 @@ *******************************************************************************/ /** - * \addtogroup group_hal_tcpwm_common PSoC 6 TCPWM Common Functionality + * \addtogroup group_hal_psoc6_tcpwm_common TCPWM Common Functionality * \ingroup group_hal_psoc6 * \{ * Code shared between the Cypress Timer / Counter and PWM. - * - * \defgroup group_hal_tcpwm_common_macros Macros - * \defgroup group_hal_tcpwm_common_constants Constants - * \defgroup group_hal_tcpwm_common_functions Functions - * \defgroup group_hal_tcpwm_common_data_structures Data Structures - * \defgroup group_hal_tcpwm_common_enums Enumerated Types */ #pragma once @@ -41,11 +35,6 @@ #include #include "cyhal_hw_types.h" -/** - * \addtogroup group_hal_tcpwm_common_data_structures - * \{ - */ - /** Handler for TCPWM interrupts */ typedef void(*cyhal_tcpwm_event_callback_t)(void *callback_arg, int event); @@ -59,25 +48,9 @@ typedef struct { uint8_t isr_offset; //!< TCPWM base IRQn (channel 0 IRQn) } cyhal_tcpwm_data_t; -/** \} group_hal_tcpwm_common_data_structures */ - - -/** - * \addtogroup group_hal_tcpwm_common_constants - * \{ - */ - /** Contains data about all of the TCPWMs */ extern const cyhal_tcpwm_data_t CYHAL_TCPWM_DATA[CY_IP_MXTCPWM_INSTANCES]; -/** \} group_hal_tcpwm_common_constants */ - - -/** - * \addtogroup group_hal_tcpwm_common_functions - * \{ - */ - /** Initialize a timer/counter or PWM object's callback data. * * @param[in] resource The timer/counter or PWM resource @@ -103,6 +76,4 @@ void cyhal_tcpwm_register_callback(cyhal_resource_inst_t *resource, cy_israddres */ void cyhal_tcpwm_enable_event(TCPWM_Type *type, cyhal_resource_inst_t *resource, uint32_t event, uint8_t intrPriority, bool enable); -/** \} group_hal_tcpwm_common_functions */ - -/** \} group_hal_tcpwm_common */ \ No newline at end of file +/** \} group_hal_psoc6_tcpwm_common */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_timer.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_timer.h index 6b1197769ce..5dcb30921ca 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_timer.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_timer.h @@ -30,11 +30,6 @@ * \ingroup group_hal * \{ * High level interface for interacting with the Cypress Timer. -* -* \defgroup group_hal_timer_macros Macros -* \defgroup group_hal_timer_functions Functions -* \defgroup group_hal_timer_data_structures Data Structures -* \defgroup group_hal_timer_enums Enumerated Types */ #pragma once @@ -49,11 +44,6 @@ extern "C" { #endif -/** -* \addtogroup group_hal_timer_enums -* \{ -*/ - /** Timer directions */ typedef enum { @@ -70,15 +60,7 @@ typedef enum { CYHAL_TIMER_IRQ_ALL = (1 << 2) - 1, } cyhal_timer_event_t; -/** \} group_hal_timer_enums */ - - -/** -* \addtogroup group_hal_timer_data_structures -* \{ -*/ - -/** Describes the current configuration of a timer/counter */ +/** @brief Describes the current configuration of a timer/counter */ typedef struct { /** @@ -97,14 +79,6 @@ typedef struct /** Handler for timer events */ typedef void(*cyhal_timer_event_callback_t)(void *callback_arg, cyhal_timer_event_t event); -/** \} group_hal_timer_data_structures */ - - -/** -* \addtogroup group_hal_timer_macros -* \{ -*/ - /** Bad argument. eg: null pointer */ #define CYHAL_TIMER_RSLT_ERR_BAD_ARGUMENT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_TIMER, 0)) /** Failed to initialize Timer clock */ @@ -117,14 +91,6 @@ typedef void(*cyhal_timer_event_callback_t)(void *callback_arg, cyhal_timer_even /** Default timer frequency, used when an existing clock divider is not provided to init */ #define CYHAL_TIMER_DEFAULT_FREQ (1000000u) -/** \} group_hal_timer_macros */ - - -/** -* \addtogroup group_hal_timer_functions -* \{ -*/ - /** Initialize the timer/counter peripheral and configure the pin. * * @param[out] obj The timer/counter object to initialize @@ -189,8 +155,6 @@ void cyhal_timer_register_callback(cyhal_timer_t *obj, cyhal_timer_event_callbac */ void cyhal_timer_enable_event(cyhal_timer_t *obj, cyhal_timer_event_t event, uint8_t intrPriority, bool enable); -/** \} group_hal_timer_functions */ - #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_trng.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_trng.h index fe2ca19539c..aafbb18b164 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_trng.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_trng.h @@ -30,11 +30,6 @@ * \ingroup group_hal * \{ * High level interface for interacting with the Cypress TRNG. -* -* \defgroup group_hal_trng_macros Macros -* \defgroup group_hal_trng_functions Functions -* \defgroup group_hal_trng_data_structures Data Structures -* \defgroup group_hal_trng_enums Enumerated Types */ #pragma once @@ -56,11 +51,6 @@ extern "C" { */ #define CYHAL_TRNG_RSLT_ERR_HW (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_TRNG, 1)) -/** -* \addtogroup group_hal_trng_functions -* \{ -*/ - /** Initialize the random number generator. * * @param[out] obj The random number generator object @@ -81,8 +71,6 @@ void cyhal_trng_free(cyhal_trng_t *obj); */ uint32_t cyhal_trng_generate(const cyhal_trng_t *obj); -/** \} group_hal_trng_functions */ - #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_uart.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_uart.h index 29cb37b7daa..4cd3f897ded 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_uart.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_uart.h @@ -30,11 +30,6 @@ * \ingroup group_hal * \{ * High level interface for interacting with the Cypress UART. -* -* \defgroup group_hal_uart_macros Macros -* \defgroup group_hal_uart_functions Functions -* \defgroup group_hal_uart_data_structures Data Structures -* \defgroup group_hal_uart_enums Enumerated Types */ #pragma once @@ -49,11 +44,6 @@ extern "C" { #endif -/** -* \addtogroup group_hal_uart_macros -* \{ -*/ - /** The requested resource type is invalid */ #define CYHAL_UART_RSLT_ERR_INVALID_PIN (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_UART, 0)) /** Failed to configure power management callback */ @@ -66,13 +56,6 @@ extern "C" { #define CYHAL_UART_DEFAULT_BAUD 115200 /** The maximum allowable difference between baud requested and actual baud **/ #define CYHAL_UART_MAX_BAUD_PERCENT_DIFFERENCE 10 -/** \} group_hal_uart_macros */ - - -/** -* \addtogroup group_hal_uart_enums -* \{ -*/ /** UART Parity */ typedef enum @@ -96,15 +79,7 @@ typedef enum CYHAL_UART_IRQ_TX_EMPTY = 1 << 8, //!< The tx hardware buffer is empty } cyhal_uart_event_t; -/** \} group_hal_uart_enums */ - - -/** -* \addtogroup group_hal_uart_data_structures -* \{ -*/ - -/** Initial UART configuration */ +/** @brief Initial UART configuration */ typedef struct { uint32_t data_bits; //!< The number of start bits @@ -117,14 +92,6 @@ typedef struct /** UART callback function type */ typedef void (*cyhal_uart_event_callback_t)(void *callback_arg, cyhal_uart_event_t event); -/** \} group_hal_uart_data_structures */ - - -/** -* \addtogroup group_hal_uart_functions -* \{ -*/ - /** Initialize the uart peripheral. It sets the default parameters for uart * peripheral, and configures its specifieds pins. * @@ -305,9 +272,6 @@ void cyhal_uart_register_callback(cyhal_uart_t *obj, cyhal_uart_event_callback_t */ void cyhal_uart_enable_event(cyhal_uart_t *obj, cyhal_uart_event_t event, uint8_t intrPriority, bool enable); -/** \} group_hal_uart_functions */ - - #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_usb_dev.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_usb_dev.h index d84d01aebfe..839f106d65d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_usb_dev.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_usb_dev.h @@ -30,11 +30,7 @@ * \ingroup group_hal * \{ * High level interface for interacting with the Cypress USB Device. -* -* \defgroup group_hal_usb_dev_macros Macros -* \defgroup group_hal_usb_dev_functions Functions -* \defgroup group_hal_usb_dev_data_structures Data Structures -* \defgroup group_hal_usb_dev_enums Enumerated Types +* */ #pragma once @@ -49,11 +45,6 @@ extern "C" { #endif -/** -* \addtogroup group_hal_usb_dev_macros -* \{ -*/ - /** The usb error */ #define CYHAL_USB_DEV_RSLT_ERR (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_USB, 0)) @@ -63,6 +54,11 @@ extern "C" { /** The configuration of USB clock failed */ #define CYHAL_USB_DEV_RSLT_ERR_CLK_CFG (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_USB, 2)) +/** + * \addtogroup group_hal_usb_dev_endpoint Endpoint + * \{ + * APIs relating to endpoint management + */ /** Returns true if endpoint direction is IN */ #define CYHAL_USB_DEV_IS_IN_EP(endpoint) (0U != (0x80U & (uint32_t) (endpoint))) @@ -72,14 +68,6 @@ extern "C" { /** Returns endpoint index (type uint32_t) */ #define CYHAL_USB_DEV_GET_EP_IDX(endpoint) (CYHAL_USB_DEV_GET_EP_NUM(endpoint) - 1U) -/** \} group_hal_usb_dev_macros */ - - -/** -* \addtogroup group_hal_usb_dev_enums -* \{ -*/ - /** USB Device Endpoints types */ typedef enum { @@ -89,6 +77,8 @@ typedef enum CYHAL_USB_DEV_EP_TYPE_INT = 3 } cyhal_usb_dev_ep_type_t; +/** \} group_hal_usb_dev_endpoint */ + /** Service Callback Events */ typedef enum { @@ -98,21 +88,21 @@ typedef enum CYHAL_USB_DEV_EVENT_EP0_OUT, /**< Callback hooked to endpoint 0 OUT packet interrupt */ } cyhal_usb_dev_event_t; -/** \} group_hal_usb_dev_enums */ - - -/** -* \addtogroup group_hal_usb_dev_data_structures -* \{ -*/ - -/** USB endpoint address (it consists from endpoint number and direction) */ +/** + * USB endpoint address (consists from endpoint number and direction) + * + * \ingroup group_hal_usb_dev_endpoint + */ typedef uint8_t cyhal_usb_dev_ep_t; /** Callback handler for USB Device interrupt */ typedef void (*cyhal_usb_dev_irq_callback_t)(void); -/** Callback handler for the transfer completion event for data endpoints (not applicable for endpoint 0)*/ +/** + * Callback handler for the transfer completion event for data endpoints (not applicable for endpoint 0) + * + * \ingroup group_hal_usb_dev_endpoint + */ typedef void (* cyhal_usb_dev_endpoint_callback_t)(cyhal_usb_dev_ep_t endpoint); /** Callback handler for the events for USB Device */ @@ -121,14 +111,6 @@ typedef void (*cyhal_usb_dev_event_callback_t)(void); /** Callback handler for the events for USB Device */ typedef void (*cyhal_usb_dev_sof_callback_t)(uint32_t frame_number); -/** \} group_hal_usb_dev_data_structures */ - - -/** -* \addtogroup group_hal_usb_dev_functions -* \{ -*/ - /** * Initialize this USBPhy instance. * @@ -208,6 +190,12 @@ typedef void (*cyhal_usb_dev_sof_callback_t)(uint32_t frame_number); */ void cyhal_usb_dev_set_address(cyhal_usb_dev_t *obj, uint8_t address); +/** + * \addtogroup group_hal_usb_dev_ep0 EP0 + * \{ + * APIs relating specifically to management of endpoint zero + */ + /** * Get wMaxPacketSize of endpoint 0. * The endpoint 0 has dedicated buffer. @@ -266,6 +254,13 @@ uint32_t cyhal_usb_dev_ep0_get_max_packet(cyhal_usb_dev_t *obj); */ void cyhal_usb_dev_ep0_stall(cyhal_usb_dev_t *obj); +/** \} group_hal_usb_dev_ep0 */ + +/** + * \addtogroup group_hal_usb_dev_endpoint + * \{ + */ + /** * Configure an endpoint. * @@ -385,6 +380,8 @@ cy_rslt_t cyhal_usb_dev_endpoint_add(cyhal_usb_dev_t *obj, bool alloc, bool enab */ cy_rslt_t cyhal_usb_dev_endpoint_abort(cyhal_usb_dev_t *obj, cyhal_usb_dev_ep_t endpoint); +/** \} group_hal_usb_dev_endpoint */ + /** The USB Device callback handler registration * * @param[in,out] obj The usb device object @@ -415,6 +412,8 @@ void cyhal_usb_dev_process_irq(cyhal_usb_dev_t *obj); * @param[in,out] obj The usb device object * @param[in] endpoint Endpoint to registers handler * @param[in] callback The callback handler which will be invoked when the endpoint comp + * + * \ingroup group_hal_usb_dev_endpoint */ void cyhal_usb_dev_register_endpoint_callback(cyhal_usb_dev_t *obj, cyhal_usb_dev_ep_t endpoint, cyhal_usb_dev_endpoint_callback_t callback); @@ -435,8 +434,6 @@ void cyhal_usb_dev_register_event_callback(cyhal_usb_dev_t *obj, cyhal_usb_dev_e */ void cyhal_usb_dev_register_sof_callback( cyhal_usb_dev_t *obj, cyhal_usb_dev_sof_callback_t callback); -/** \} group_hal_usb_dev_functions */ - #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_utils.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_utils.h index 2bebb64e133..3f457af2fd4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_utils.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_utils.h @@ -23,15 +23,8 @@ *******************************************************************************/ /** -* \addtogroup group_hal_utils PSoC 6 Utility Functions -* \ingroup group_hal_psoc6 +* \addtogroup group_hal_psoc6 PSoC 6 Implementation * \{ -* Utility functions for working with the PSoC 6 HAL implementation. -* -* \defgroup group_hal_utils_macros Macros -* \defgroup group_hal_utils_functions Functions -* \defgroup group_hal_utils_data_structures Data Structures -* \defgroup group_hal_utils_enums Enumerated Types */ #pragma once @@ -43,17 +36,25 @@ extern "C" { #endif + +/** + * \addtogroup group_hal_psoc6_interrupts Interrupts + * \{ + */ +#define CYHAL_IRQN_OFFSET 16 /**< Offset for implementation-defined ISR type numbers (IRQ0 = 16) */ +#define CYHAL_GET_CURRENT_IRQN() ((IRQn_Type) (__get_IPSR() - CYHAL_IRQN_OFFSET)) /**< Macro to get the IRQn of the current ISR */ + +/** \} group_hal_psoc6_interrupts */ + + /** -* \addtogroup group_hal_utils_macros +* \addtogroup group_hal_psoc6_pin_package * \{ */ #define CYHAL_GET_PIN(pin) ((uint8_t)(pin & 0xFFFFUL)) /**< Macro to extract the pin number */ #define CYHAL_GET_PORT(pin) ((uint8_t)((uint32_t)(pin >> 16) & 0xFFUL)) /**< Macro to extract the port number */ -#define CYHAL_IRQN_OFFSET 16 /**< Offset for implementation-defined ISR type numbers (IRQ0 = 16) */ -#define CYHAL_GET_CURRENT_IRQN() ((IRQn_Type) (__get_IPSR() - CYHAL_IRQN_OFFSET)) /**< Macro to get the IRQn of the current ISR */ - /** Looks up the resource block that connects to the specified pins from the provided resource pin mapping table. * This is a convinience utility for cyhal_utils_get_resource() if the mappings is an array of known size. * @@ -63,25 +64,6 @@ extern "C" { */ #define CY_UTILS_GET_RESOURCE(pin, mappings) cyhal_utils_get_resource(pin, mappings, sizeof(mappings)/sizeof(cyhal_resource_pin_mapping_t)) -/** \} group_hal_utils_macros */ - - -/** -* \addtogroup group_hal_utils_functions -* \{ -*/ - -/** Calculate the peri clock divider value that need to be set to reach frequency closest to the input frequency - * - * @param[in] frequency The desired frequency - * @param[in] frac_bits The number of fractional bits that the divider has - * @return The calculate divider value to set, NOTE a divider value of x divide the frequency by (x+1) - */ -static inline uint32_t cyhal_divider_value(uint32_t frequency, uint32_t frac_bits) -{ - return ((Cy_SysClk_ClkPeriGetFrequency() * (1 << frac_bits)) + (frequency / 2)) / frequency - 1; -} - /** Converts the provided gpio pin to a resource instance object * * @param[in] pin The pin to get a resource object for @@ -108,10 +90,29 @@ const cyhal_resource_pin_mapping_t *cyhal_utils_get_resource(cyhal_gpio_t pin, c */ void cyhal_utils_disconnect_and_free(cyhal_gpio_t pin); -/** \} group_hal_utils_functions */ +/** \} group_hal_psoc6_pin_package */ + +/** +* \addtogroup group_hal_psoc6_clocks Clocks +* \{ +*/ + +/** Calculate the peri clock divider value that need to be set to reach frequency closest to the input frequency + * + * @param[in] frequency The desired frequency + * @param[in] frac_bits The number of fractional bits that the divider has + * @return The calculate divider value to set, NOTE a divider value of x divide the frequency by (x+1) + */ +static inline uint32_t cyhal_divider_value(uint32_t frequency, uint32_t frac_bits) +{ + return ((Cy_SysClk_ClkPeriGetFrequency() * (1 << frac_bits)) + (frequency / 2)) / frequency - 1; +} + +/** \} group_hal_psoc6_clocks */ #if defined(__cplusplus) } #endif -/** \} group_hal_utils */ +/** \} group_hal_psoc6_utils */ +/** \} group_hal_psoc6 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_wdt.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_wdt.h index 53bb6677ab3..ea82d395505 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_wdt.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_wdt.h @@ -30,11 +30,6 @@ * \ingroup group_hal * \{ * High level interface for interacting with the Cypress WDT. -* -* \defgroup group_hal_wdt_macros Macros -* \defgroup group_hal_wdt_functions Functions -* \defgroup group_hal_wdt_data_structures Data Structures -* \defgroup group_hal_wdt_enums Enumerated Types */ #pragma once @@ -46,24 +41,11 @@ extern "C" { #endif -/** -* \addtogroup group_hal_wdt_macros -* \{ -*/ - /** WDT timeout out of range */ #define CY_RSLT_WDT_INVALID_TIMEOUT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_WDT, 0)) /** WDT already initialized */ #define CY_RSLT_WDT_ALREADY_INITIALIZED (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_WDT, 1)) -/** \} group_hal_wdt_macros */ - - -/** -* \addtogroup group_hal_wdt_functions -* \{ -*/ - /** Initialize and start the WDT * * Initialize or re-initialize the WDT. @@ -130,8 +112,6 @@ uint32_t cyhal_wdt_get_timeout_ms(cyhal_wdt_t *obj); */ uint32_t cyhal_wdt_get_max_timeout_ms(void); -/** \} group_hal_wdt_functions */ - #if defined(__cplusplus) } #endif @@ -140,4 +120,4 @@ uint32_t cyhal_wdt_get_max_timeout_ms(void); #include CYHAL_WDT_IMPL_HEADER #endif /* CYHAL_WDT_IMPL_HEADER */ -/** \} group_hal_wdt */ \ No newline at end of file +/** \} group_hal_wdt */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_wdt.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_wdt.c index a372e90c177..731122736a2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_wdt.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_wdt.c @@ -27,8 +27,8 @@ *******************************************************************************/ /** -* \addtogroup group_hal_psoc6_wdt PSoC 6 WDT (Watchdog Timer) -* \ingroup group_hal_psoc6 +* \addtogroup group_hal_psoc6_wdt (WDT) Watchdog Timer +* \ingroup group_hal_psoc6 * \{ * The PSoC 6 WDT is only capable of supporting certain timeout ranges below its maximum timeout of 6000ms. * As a result, any unsupported timeouts given to the HAL WDT are rounded up to the nearest supported value. @@ -80,7 +80,7 @@ * 4 * * -* \} group_hal_psoc6 +* \} group_hal_psoc6_wdt */ #include From 1c1dfe1dd8eba3ce35d290dba003c5516d39e858 Mon Sep 17 00:00:00 2001 From: Hugues Kamba Date: Thu, 19 Sep 2019 10:52:02 +0100 Subject: [PATCH 111/227] Correct force inline syntax for IAR compiler Unlinke other compilers supported, the IAR compiler requires the pre-processor extension to force inline a method to be placed before the keyword `template` if the method is declared with one. --- drivers/Ticker.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/Ticker.h b/drivers/Ticker.h index 362f74c4bd3..daa5148927f 100644 --- a/drivers/Ticker.h +++ b/drivers/Ticker.h @@ -83,8 +83,12 @@ class Ticker : public TimerEvent, private NonCopyable { * @param func pointer to the function to be called * @param t the time between calls in seconds */ - template - MBED_FORCEINLINE void attach(F &&func, float t) +#if defined(__ICCARM__) + MBED_FORCEINLINE template +#else + template MBED_FORCEINLINE +#endif + void attach(F &&func, float t) { attach_us(std::forward(func), t * 1000000.0f); } From 7272fe06130bd7d4773024db2b496ed167fd17c5 Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Thu, 19 Sep 2019 13:04:13 +0200 Subject: [PATCH 112/227] STM32H7: LSI clock selection when LSE is not available --- targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_rcc.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_rcc.h b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_rcc.h index 2a2877f292a..93f86f96059 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_rcc.h +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_rcc.h @@ -430,6 +430,9 @@ typedef struct /** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source * @{ */ +/* MBED */ +#define RCC_RTCCLKSOURCE_NO_CLK (0x00000000U) +/* MBED */ #define RCC_RTCCLKSOURCE_LSE (0x00000100U) #define RCC_RTCCLKSOURCE_LSI (0x00000200U) #define RCC_RTCCLKSOURCE_HSE_DIV2 (0x00002300U) From b3a14b5eade5f29bca7f822efd85b3dddc71e153 Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Thu, 19 Sep 2019 13:06:11 +0200 Subject: [PATCH 113/227] STM32WB : LSI clock selection when LSE is not available --- targets/TARGET_STM/TARGET_STM32WB/device/stm32_hal_legacy.h | 3 +-- targets/TARGET_STM/lp_ticker.c | 4 ++++ targets/TARGET_STM/mbed_overrides.c | 4 ++++ targets/TARGET_STM/rtc_api.c | 4 ++++ 4 files changed, 13 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32WB/device/stm32_hal_legacy.h b/targets/TARGET_STM/TARGET_STM32WB/device/stm32_hal_legacy.h index 3feee96cd25..f4b904bc395 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/device/stm32_hal_legacy.h +++ b/targets/TARGET_STM/TARGET_STM32WB/device/stm32_hal_legacy.h @@ -2929,9 +2929,8 @@ #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 -#if defined(STM32L4) +#if defined(STM32L4) || defined(STM32WB) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE -#elif defined(STM32WB) || defined(STM32G0) #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK #endif diff --git a/targets/TARGET_STM/lp_ticker.c b/targets/TARGET_STM/lp_ticker.c index 87dbbd51ddb..1cd5c1e05fd 100644 --- a/targets/TARGET_STM/lp_ticker.c +++ b/targets/TARGET_STM/lp_ticker.c @@ -113,7 +113,11 @@ void lp_ticker_init(void) #else /* MBED_CONF_TARGET_LSE_AVAILABLE */ /* Enable LSI clock */ +#if TARGET_STM32WB + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI1; +#else RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI; +#endif RCC_OscInitStruct.LSIState = RCC_LSI_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; diff --git a/targets/TARGET_STM/mbed_overrides.c b/targets/TARGET_STM/mbed_overrides.c index 8092cfe5c31..e74d4960d4e 100644 --- a/targets/TARGET_STM/mbed_overrides.c +++ b/targets/TARGET_STM/mbed_overrides.c @@ -61,7 +61,11 @@ void mbed_sdk_init() RCC_OscInitTypeDef RCC_OscInitStruct = {0}; if (__HAL_RCC_GET_RTC_SOURCE() != RCC_RTCCLKSOURCE_NO_CLK) { +#if TARGET_STM32WB + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI1; +#else RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI; +#endif RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; RCC_OscInitStruct.LSIState = RCC_LSI_ON; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { diff --git a/targets/TARGET_STM/rtc_api.c b/targets/TARGET_STM/rtc_api.c index e28a311b842..e100520671c 100644 --- a/targets/TARGET_STM/rtc_api.c +++ b/targets/TARGET_STM/rtc_api.c @@ -74,7 +74,11 @@ void rtc_init(void) error("PeriphClkInitStruct RTC failed with LSE\n"); } #else /* MBED_CONF_TARGET_LSE_AVAILABLE */ +#if TARGET_STM32WB + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI1; +#else RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI; +#endif RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; RCC_OscInitStruct.LSIState = RCC_LSI_ON; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { From 2d967dacbf7daf5f3ae858af8987acbe36a970d0 Mon Sep 17 00:00:00 2001 From: Mirela Chirica Date: Thu, 19 Sep 2019 16:19:31 +0300 Subject: [PATCH 114/227] Cellular: Enable IPV6 for WISE_1570 --- .../framework/targets/QUECTEL/BC95/QUECTEL_BC95.cpp | 2 +- .../QUECTEL/BC95/QUECTEL_BC95_CellularStack.cpp | 10 ++++++++-- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/features/cellular/framework/targets/QUECTEL/BC95/QUECTEL_BC95.cpp b/features/cellular/framework/targets/QUECTEL/BC95/QUECTEL_BC95.cpp index a47e765b073..24c53470abb 100644 --- a/features/cellular/framework/targets/QUECTEL/BC95/QUECTEL_BC95.cpp +++ b/features/cellular/framework/targets/QUECTEL/BC95/QUECTEL_BC95.cpp @@ -40,7 +40,7 @@ static const intptr_t cellular_properties[AT_CellularBase::PROPERTY_MAX] = { 1, // AT_CMGF 1, // AT_CSDH 1, // PROPERTY_IPV4_STACK - 0, // PROPERTY_IPV6_STACK + 1, // PROPERTY_IPV6_STACK 0, // PROPERTY_IPV4V6_STACK 0, // PROPERTY_NON_IP_PDP_TYPE 0, // PROPERTY_AT_CGEREP diff --git a/features/cellular/framework/targets/QUECTEL/BC95/QUECTEL_BC95_CellularStack.cpp b/features/cellular/framework/targets/QUECTEL/BC95/QUECTEL_BC95_CellularStack.cpp index 7c09ec3dca1..03c39342b63 100644 --- a/features/cellular/framework/targets/QUECTEL/BC95/QUECTEL_BC95_CellularStack.cpp +++ b/features/cellular/framework/targets/QUECTEL/BC95/QUECTEL_BC95_CellularStack.cpp @@ -142,9 +142,9 @@ nsapi_error_t QUECTEL_BC95_CellularStack::create_socket_impl(CellularSocket *soc bool socketOpenWorking = false; if (socket->proto == NSAPI_UDP) { - _at.cmd_start_stop("+NSOCR", "=DGRAM,", "%d%d%d", 17, socket->localAddress.get_port(), 1); + _at.cmd_start_stop("+NSOCR", "=DGRAM,", "%d%d%d%s", 17, socket->localAddress.get_port(), 1, ((_ip_ver_sendto == NSAPI_IPv4) ? "AF_INET" : "AF_INET6")); } else if (socket->proto == NSAPI_TCP) { - _at.cmd_start_stop("+NSOCR", "=STREAM,", "%d%d%d", 6, socket->localAddress.get_port(), 1); + _at.cmd_start_stop("+NSOCR", "=STREAM,", "%d%d%d%s", 6, socket->localAddress.get_port(), 1, ((_ip_ver_sendto == NSAPI_IPv4) ? "AF_INET" : "AF_INET6")); } else { return NSAPI_ERROR_PARAMETER; } @@ -173,6 +173,12 @@ nsapi_size_or_error_t QUECTEL_BC95_CellularStack::socket_sendto_impl(CellularSoc // open already. MBED_ASSERT(socket->id != -1); + if (_ip_ver_sendto != address.get_ip_version()) { + _ip_ver_sendto = address.get_ip_version(); + socket_close_impl(socket->id); + create_socket_impl(socket); + } + int sent_len = 0; if (size > PACKET_SIZE_MAX) { From f5f6caa3b0c08f6755e851c8eec92e11b9230d0b Mon Sep 17 00:00:00 2001 From: Leszek Rusinowicz Date: Tue, 3 Sep 2019 13:02:06 +0200 Subject: [PATCH 115/227] FUTURE_SEQUANA: InterruptIn implementation bug fix Fixed HAL API implementation for InterruptIn: - Interrupt was not enabled by default after configuration as it should be. - Interrupt-to-object linking was not handled properly. --- .../TARGET_PSOC6_FUTURE/gpio_irq_api.c | 20 +++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/gpio_irq_api.c b/targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/gpio_irq_api.c index 8ed9bc6b8e8..d4fe527cc18 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/gpio_irq_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6_FUTURE/gpio_irq_api.c @@ -202,12 +202,17 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 MBED_ASSERT("Invalid pin ID!"); return (-1); } - obj->handler = (uint32_t) handler; + obj->handler = (uint32_t)handler; obj->id_arg = id; - return gpio_irq_setup_channel(obj); + irq_objects[obj->port_id][obj->pin] = obj; + if (gpio_irq_setup_channel(obj) != 0) { + irq_objects[obj->port_id][obj->pin] = NULL; + return (-1); + } } else { return (-1); } + return 0; } void gpio_irq_free(gpio_irq_t *obj) @@ -218,6 +223,7 @@ void gpio_irq_free(gpio_irq_t *obj) irq_port_usage[obj->port_id].pin_mask &= ~(1 << obj->pin); if (irq_port_usage[obj->port_id].pin_mask == 0) { gpio_irq_release_channel(irq_port_usage[obj->port_id].irqn, obj->port_id); + irq_objects[obj->port_id][obj->pin] = NULL; return; } NVIC_EnableIRQ(irq_port_usage[obj->port_id].irqn); @@ -230,26 +236,30 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) if (obj->mode == IRQ_FALL) { obj->mode += IRQ_RISE; Cy_GPIO_SetInterruptEdge(obj->port, obj->pin, CY_GPIO_INTR_BOTH); - } else { + } else if (obj->mode == IRQ_NONE) { obj->mode = IRQ_RISE; Cy_GPIO_SetInterruptEdge(obj->port, obj->pin, CY_GPIO_INTR_RISING); + gpio_irq_enable(obj); } } else if (event == IRQ_FALL) { if (obj->mode == IRQ_RISE) { obj->mode += IRQ_FALL; Cy_GPIO_SetInterruptEdge(obj->port, obj->pin, CY_GPIO_INTR_BOTH); - } else { + } else if (obj->mode == IRQ_NONE) { obj->mode = IRQ_FALL; Cy_GPIO_SetInterruptEdge(obj->port, obj->pin, CY_GPIO_INTR_FALLING); + gpio_irq_enable(obj); } } else { obj->mode = IRQ_NONE; + gpio_irq_disable(obj); Cy_GPIO_SetInterruptEdge(obj->port, obj->pin, CY_GPIO_INTR_DISABLE); } } else if (obj->mode != IRQ_NONE) { if (event == IRQ_RISE) { if (obj->mode == IRQ_RISE) { obj->mode = IRQ_NONE; + gpio_irq_disable(obj); Cy_GPIO_SetInterruptEdge(obj->port, obj->pin, CY_GPIO_INTR_DISABLE); } else { obj->mode = IRQ_FALL; @@ -258,6 +268,7 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) } else if (event == IRQ_FALL) { if (obj->mode == IRQ_FALL) { obj->mode = IRQ_NONE; + gpio_irq_disable(obj); Cy_GPIO_SetInterruptEdge(obj->port, obj->pin, CY_GPIO_INTR_DISABLE); } else { obj->mode = IRQ_RISE; @@ -266,6 +277,7 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) } else { obj->mode = IRQ_NONE; Cy_GPIO_SetInterruptEdge(obj->port, obj->pin, CY_GPIO_INTR_DISABLE); + gpio_irq_disable(obj); } } } From 76171e54e711ea6a5d1f8a2413461367706b612f Mon Sep 17 00:00:00 2001 From: Kimmo Vaisanen Date: Fri, 20 Sep 2019 09:24:50 +0300 Subject: [PATCH 116/227] Cellular: Handle SEND FAIL and ERROR response QISEND command can respond either SEND OK, SEND FAIL or ERROR. If response is not SEND OK, sent bytes should not be checked but error should be reported. --- .../targets/QUECTEL/BG96/QUECTEL_BG96_CellularStack.cpp | 9 +++++++-- .../targets/QUECTEL/M26/QUECTEL_M26_CellularStack.cpp | 7 +++++++ 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularStack.cpp b/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularStack.cpp index bcaa9a2b456..ee9652e4f64 100644 --- a/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularStack.cpp +++ b/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96_CellularStack.cpp @@ -300,12 +300,17 @@ nsapi_size_or_error_t QUECTEL_BG96_CellularStack::socket_sendto_impl(CellularSoc _at.write_bytes((uint8_t *)data, size); _at.resp_start(); _at.set_stop_tag("\r\n"); + // Possible responses are SEND OK, SEND FAIL or ERROR. + char response[16]; + response[0] = '\0'; + _at.read_string(response, sizeof(response)); _at.resp_stop(); + if (strcmp(response, "SEND OK") != 0) { + return NSAPI_ERROR_DEVICE_ERROR; + } // Get the sent count after sending - nsapi_size_or_error_t err = _at.at_cmd_int("+QISEND", "=", sent_len_after, "%d%d", socket->id, 0); - if (err == NSAPI_ERROR_OK) { sent_len = sent_len_after - sent_len_before; return sent_len; diff --git a/features/cellular/framework/targets/QUECTEL/M26/QUECTEL_M26_CellularStack.cpp b/features/cellular/framework/targets/QUECTEL/M26/QUECTEL_M26_CellularStack.cpp index d02118b321f..36241c81c1c 100644 --- a/features/cellular/framework/targets/QUECTEL/M26/QUECTEL_M26_CellularStack.cpp +++ b/features/cellular/framework/targets/QUECTEL/M26/QUECTEL_M26_CellularStack.cpp @@ -440,7 +440,14 @@ nsapi_size_or_error_t QUECTEL_M26_CellularStack::socket_sendto_impl(CellularSock _at.write_bytes((uint8_t *)data, sent_len); _at.resp_start(); _at.set_stop_tag("\r\n"); + // Possible responses are SEND OK, SEND FAIL or ERROR. + char response[16]; + response[0] = '\0'; + _at.read_string(response, sizeof(response)); _at.resp_stop(); + if (strcmp(response, "SEND OK") != 0) { + return NSAPI_ERROR_DEVICE_ERROR; + } if (_at.get_last_error() != NSAPI_ERROR_OK) { tr_error("QUECTEL_M26_CellularStack:%s:%u:[NSAPI_ERROR_DEVICE_ERROR]", __FUNCTION__, __LINE__); From b8d30a426e7a193c1b47072e16e728facc1c62cc Mon Sep 17 00:00:00 2001 From: Hugues Kamba Date: Mon, 16 Sep 2019 19:12:12 +0100 Subject: [PATCH 117/227] Fix Coverity issue: Initialize FlashIAP non-static member in constructor --- drivers/FlashIAP.h | 6 ++++-- drivers/source/FlashIAP.cpp | 10 ---------- platform/NonCopyable.h | 4 ++-- 3 files changed, 6 insertions(+), 14 deletions(-) diff --git a/drivers/FlashIAP.h b/drivers/FlashIAP.h index 5ac0a8986cf..8797a34f1c1 100644 --- a/drivers/FlashIAP.h +++ b/drivers/FlashIAP.h @@ -63,8 +63,10 @@ namespace mbed { */ class FlashIAP : private NonCopyable { public: - FlashIAP(); - ~FlashIAP(); + constexpr FlashIAP() : _flash(), _page_buf(nullptr) + { + + } /** Initialize a flash IAP device * diff --git a/drivers/source/FlashIAP.cpp b/drivers/source/FlashIAP.cpp index 60d48344cac..a452ad51c4f 100644 --- a/drivers/source/FlashIAP.cpp +++ b/drivers/source/FlashIAP.cpp @@ -46,16 +46,6 @@ static inline bool is_aligned(uint32_t number, uint32_t alignment) } } -FlashIAP::FlashIAP() : _page_buf(nullptr) -{ - -} - -FlashIAP::~FlashIAP() -{ - -} - int FlashIAP::init() { int ret = 0; diff --git a/platform/NonCopyable.h b/platform/NonCopyable.h index 487aaffbd8d..144ca025b23 100644 --- a/platform/NonCopyable.h +++ b/platform/NonCopyable.h @@ -172,11 +172,11 @@ class NonCopyable { /** * Disallow construction of NonCopyable objects from outside of its hierarchy. */ - NonCopyable() { } + NonCopyable() = default; /** * Disallow destruction of NonCopyable objects from outside of its hierarchy. */ - ~NonCopyable() { } + ~NonCopyable() = default; #if (!defined(MBED_DEBUG) && (MBED_CONF_PLATFORM_FORCE_NON_COPYABLE_ERROR == 0)) /** From 6eb8fc5942e81235d1d531c0f9979e227f548f37 Mon Sep 17 00:00:00 2001 From: Kimmo Vaisanen Date: Thu, 12 Sep 2019 15:14:36 +0300 Subject: [PATCH 118/227] Unittests for CellularList --- .../framework/common/list/listtest.cpp | 90 +++++++++++++++++++ .../framework/common/list/unittest.cmake | 19 ++++ 2 files changed, 109 insertions(+) create mode 100644 UNITTESTS/features/cellular/framework/common/list/listtest.cpp create mode 100644 UNITTESTS/features/cellular/framework/common/list/unittest.cmake diff --git a/UNITTESTS/features/cellular/framework/common/list/listtest.cpp b/UNITTESTS/features/cellular/framework/common/list/listtest.cpp new file mode 100644 index 00000000000..98872a9a9c7 --- /dev/null +++ b/UNITTESTS/features/cellular/framework/common/list/listtest.cpp @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2018, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gtest/gtest.h" +#include "CellularList.h" + +using namespace mbed; + +// AStyle ignored as the definition is not clear due to preprocessor usage +// *INDENT-OFF* +class Testlist : public testing::Test { +protected: + + void SetUp() + { + } + + void TearDown() + { + } +}; +// *INDENT-ON* + +struct entry_t { + int i; + entry_t *next; +}; + +TEST_F(Testlist, test_list_int) +{ + CellularList list; + EXPECT_TRUE(NULL == list.get_head()); + + entry_t *first = list.add_new(); + first->i = 1; + EXPECT_TRUE(NULL != first); + + entry_t *second = list.add_new(); + first->i = 2; + EXPECT_TRUE(NULL != second); + + entry_t *third = list.add_new(); + first->i = 3; + EXPECT_TRUE(NULL != third); + + EXPECT_EQ(3, list.get_head()->i); + + list.delete_last(); // Deletes first + EXPECT_EQ(3, list.get_head()->i); + + list.delete_all(); + EXPECT_TRUE(NULL == list.get_head()); +} + +TEST_F(Testlist, delete_last_until_empty) +{ + CellularList list; + list.add_new(); + list.add_new(); + list.delete_last(); + list.delete_last(); + EXPECT_TRUE(NULL == list.get_head()); +} + +TEST_F(Testlist, empty_list_delete_last) +{ + CellularList list; + list.delete_last(); + EXPECT_TRUE(NULL == list.get_head()); +} + +TEST_F(Testlist, empty_list_delete_all) +{ + CellularList list; + list.delete_all(); + EXPECT_TRUE(NULL == list.get_head()); +} diff --git a/UNITTESTS/features/cellular/framework/common/list/unittest.cmake b/UNITTESTS/features/cellular/framework/common/list/unittest.cmake new file mode 100644 index 00000000000..d81bc507881 --- /dev/null +++ b/UNITTESTS/features/cellular/framework/common/list/unittest.cmake @@ -0,0 +1,19 @@ + +#################### +# UNIT TESTS +#################### + +# Add test specific include paths +set(unittest-includes ${unittest-includes} + features/cellular/framework/common/util + ../features/cellular/framework/common +) + +# Source files +set(unittest-sources +) + +# Test files +set(unittest-test-sources + features/cellular/framework/common/list/listtest.cpp +) From a6eed00d5b3cba53be8ac6657efdead4bbef7926 Mon Sep 17 00:00:00 2001 From: Kimmo Vaisanen Date: Fri, 13 Sep 2019 08:45:04 +0300 Subject: [PATCH 119/227] Add UT for CellularUtil::hex_to_char and ::hex_str_to_char_str Also added checks for pointer validity. --- .../framework/common/util/utiltest.cpp | 41 +++++++++++++++++++ .../framework/common/CellularUtil.cpp | 20 +++++---- 2 files changed, 53 insertions(+), 8 deletions(-) diff --git a/UNITTESTS/features/cellular/framework/common/util/utiltest.cpp b/UNITTESTS/features/cellular/framework/common/util/utiltest.cpp index a52a9dd4877..1efe3e7b7e2 100644 --- a/UNITTESTS/features/cellular/framework/common/util/utiltest.cpp +++ b/UNITTESTS/features/cellular/framework/common/util/utiltest.cpp @@ -53,6 +53,47 @@ TEST_F(Testutil, test_util_binary_str_to_uint) EXPECT_TRUE(0 == binary_str_to_uint(binary_str, 0)); } +TEST_F(Testutil, hex_to_char) +{ + char output; + + // 0 + hex_to_char("00", output); + EXPECT_EQ((char)0x00, output); + + // <128 + hex_to_char("10", output); + EXPECT_EQ((char)0x10, output); + + // =128 + hex_to_char("80", output); + EXPECT_EQ((char)0x80, output); + + // >128 + hex_to_char("FF", output); + EXPECT_EQ((char)0xFF, output); + + // Null -> output is not modified + hex_to_char(NULL, output); + EXPECT_EQ((char)0xFF, output); +} + +TEST_F(Testutil, hex_str_to_char_str) +{ + char input[] = "0165AABBCC"; + char output[32]; + EXPECT_EQ(5, hex_str_to_char_str(input, strlen(input), output)); + EXPECT_EQ((char)0x01, output[0]); + EXPECT_EQ((char)0x65, output[1]); + EXPECT_EQ((char)0xAA, output[2]); + EXPECT_EQ((char)0xBB, output[3]); + EXPECT_EQ((char)0xCC, output[4]); + + // NULL params + EXPECT_EQ(0, hex_str_to_char_str(NULL, 2, output)); + EXPECT_EQ(0, hex_str_to_char_str(input, strlen(input), NULL)); +} + TEST_F(Testutil, test_util_uint_to_binary_string) { char str[33]; diff --git a/features/cellular/framework/common/CellularUtil.cpp b/features/cellular/framework/common/CellularUtil.cpp index 33c5956899d..0ad61544ee3 100644 --- a/features/cellular/framework/common/CellularUtil.cpp +++ b/features/cellular/framework/common/CellularUtil.cpp @@ -278,11 +278,13 @@ int hex_str_to_int(const char *hex_string, int hex_string_length) int hex_str_to_char_str(const char *str, uint16_t len, char *buf) { int strcount = 0; - for (int i = 0; i + 1 < len; i += 2) { - char tmp; - hex_to_char(str + i, tmp); - buf[strcount] = tmp; - strcount++; + if (str && buf) { + for (int i = 0; i + 1 < len; i += 2) { + char tmp; + hex_to_char(str + i, tmp); + buf[strcount] = tmp; + strcount++; + } } return strcount; @@ -290,9 +292,11 @@ int hex_str_to_char_str(const char *str, uint16_t len, char *buf) void hex_to_char(const char *hex, char &buf) { - int upper = hex_str_to_int(hex, 1); - int lower = hex_str_to_int(hex + 1, 1); - buf = ((upper << 4) & 0xF0) | (lower & 0x0F); + if (hex) { + int upper = hex_str_to_int(hex, 1); + int lower = hex_str_to_int(hex + 1, 1); + buf = ((upper << 4) & 0xF0) | (lower & 0x0F); + } } void uint_to_binary_str(uint32_t num, char *str, int str_size, int bit_cnt) From 3c5958035a95005a5ac05e577762cde9f4d012ae Mon Sep 17 00:00:00 2001 From: Kimmo Vaisanen Date: Fri, 13 Sep 2019 12:28:29 +0300 Subject: [PATCH 120/227] Improve UT for cellular properties --- .../at_cellularbase/at_cellularbasetest.cpp | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/UNITTESTS/features/cellular/framework/AT/at_cellularbase/at_cellularbasetest.cpp b/UNITTESTS/features/cellular/framework/AT/at_cellularbase/at_cellularbasetest.cpp index e531fa07623..82229d0ad2d 100644 --- a/UNITTESTS/features/cellular/framework/AT/at_cellularbase/at_cellularbasetest.cpp +++ b/UNITTESTS/features/cellular/framework/AT/at_cellularbase/at_cellularbasetest.cpp @@ -53,6 +53,11 @@ class my_base : public AT_CellularBase { { return get_property(PROPERTY_AT_CGDATA); } + + void reset_property_array() + { + _property_array = NULL; + } }; // AStyle ignored as the definition is not clear due to preprocessor usage @@ -137,3 +142,18 @@ TEST_F(TestAT_CellularBase, test_AT_CellularBase_is_supported) EXPECT_EQ(true, my_at.check_supported()); EXPECT_EQ(false, my_at.check_not_supported()); } + +TEST_F(TestAT_CellularBase, test_invalid_params) +{ + EventQueue eq; + FileHandle_stub fh; + ATHandler ah(&fh, eq, 0, ","); + my_base my_at(ah); + + my_at.reset_property_array(); // as array is a static variable, it might have been set in previous tests + + my_at.set_cellular_properties(NULL); + + // Property array not set + EXPECT_EQ(0, my_at.get_property(AT_CellularBase::PROPERTY_IPV4_PDP_TYPE)); +} From b41c638ac53a8f252d6e4fded6c98a6b712c064f Mon Sep 17 00:00:00 2001 From: Kimmo Vaisanen Date: Mon, 16 Sep 2019 13:56:34 +0300 Subject: [PATCH 121/227] Add possibility to test URC handlers --- UNITTESTS/stubs/ATHandler_stub.cpp | 6 ++++++ UNITTESTS/stubs/ATHandler_stub.h | 7 +++++++ 2 files changed, 13 insertions(+) diff --git a/UNITTESTS/stubs/ATHandler_stub.cpp b/UNITTESTS/stubs/ATHandler_stub.cpp index f614cf87884..d03c7a48566 100644 --- a/UNITTESTS/stubs/ATHandler_stub.cpp +++ b/UNITTESTS/stubs/ATHandler_stub.cpp @@ -54,6 +54,8 @@ int ATHandler_stub::int_valid_count_table[kRead_int_table_size]; int ATHandler_stub::int_count = kRead_int_table_size; bool ATHandler_stub::process_oob_urc = false; +std::vector ATHandler_stub::urc_handlers; + int ATHandler_stub::read_string_index = kRead_string_table_size; const char *ATHandler_stub::read_string_table[kRead_string_table_size]; int ATHandler_stub::resp_stop_success_count = kResp_stop_count_default; @@ -111,6 +113,7 @@ bool ATHandler::get_debug() const ATHandler::~ATHandler() { + ATHandler_stub::urc_handlers.clear(); } void ATHandler::inc_ref_count() @@ -149,6 +152,9 @@ void ATHandler::set_urc_handler(const char *urc, mbed::Callback cb) return; } + ATHandler_stub::urc_handler handler = { .urc = urc, .cb = cb }; + ATHandler_stub::urc_handlers.push_back(handler); + if (ATHandler_stub::call_immediately) { cb(); } diff --git a/UNITTESTS/stubs/ATHandler_stub.h b/UNITTESTS/stubs/ATHandler_stub.h index df3e14b3a46..9521d0976e2 100644 --- a/UNITTESTS/stubs/ATHandler_stub.h +++ b/UNITTESTS/stubs/ATHandler_stub.h @@ -22,6 +22,7 @@ #include "ATHandler.h" #include "FileHandle_stub.h" #include "Callback.h" +#include "vector" #ifndef __AT_HANDLER_STUB_H__ #define __AT_HANDLER_STUB_H__ @@ -61,6 +62,12 @@ extern int int_count; extern int resp_stop_success_count; extern bool process_oob_urc; +struct urc_handler { + const char *urc; + mbed::Callback cb; +}; +extern std::vector urc_handlers; + extern bool get_debug_flag; bool is_get_debug_run(); void get_debug_clear(); From 89ca070e8240b5926a73ace7b809fbc07e181c42 Mon Sep 17 00:00:00 2001 From: Kimmo Vaisanen Date: Mon, 16 Sep 2019 13:56:50 +0300 Subject: [PATCH 122/227] Add UT for CEREG URC handler --- .../at_cellularnetworktest.cpp | 83 +++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/UNITTESTS/features/cellular/framework/AT/at_cellularnetwork/at_cellularnetworktest.cpp b/UNITTESTS/features/cellular/framework/AT/at_cellularnetwork/at_cellularnetworktest.cpp index 54c1f55d8a0..4fdc9106561 100644 --- a/UNITTESTS/features/cellular/framework/AT/at_cellularnetwork/at_cellularnetworktest.cpp +++ b/UNITTESTS/features/cellular/framework/AT/at_cellularnetwork/at_cellularnetworktest.cpp @@ -85,6 +85,89 @@ TEST_F(TestAT_CellularNetwork, Create) delete cn; } +int expected_rat = 0; +int expected_status = 0; +int expected_cellid = 0; + +void status_cb_urc(nsapi_event_t ev, intptr_t ptr) +{ + const cell_callback_data_t *data = (const cell_callback_data_t *)ptr; + switch (ev) { + case CellularRadioAccessTechnologyChanged: + EXPECT_EQ(NSAPI_ERROR_OK, data->error); + EXPECT_EQ(expected_rat, data->status_data); + break; + case CellularRegistrationStatusChanged: + EXPECT_EQ(NSAPI_ERROR_OK, data->error); + EXPECT_EQ(expected_status, data->status_data); + break; + case CellularCellIDChanged: + EXPECT_EQ(NSAPI_ERROR_OK, data->error); + EXPECT_EQ(expected_cellid, data->status_data); + break; + default: + if (ev == NSAPI_EVENT_CONNECTION_STATUS_CHANGE) { + EXPECT_EQ(NSAPI_STATUS_DISCONNECTED, (int)ptr); + } else { + FAIL(); + } + } +} + +TEST_F(TestAT_CellularNetwork, test_urc_creg) +{ + EventQueue que; + FileHandle_stub fh1; + ATHandler at(&fh1, que, 0, ","); + + AT_CellularNetwork cn(at); + cn.attach(status_cb_urc); + + EXPECT_STREQ("+CEREG:", ATHandler_stub::urc_handlers[0].urc); + EXPECT_STREQ("+CREG:", ATHandler_stub::urc_handlers[1].urc); + + // Connected to home network + expected_rat = CellularNetwork::RAT_NB1; + expected_status = CellularNetwork::RegisteredHomeNetwork; + expected_cellid = 305463233; + + ATHandler_stub::int_count = 4; + ATHandler_stub::int_valid_count_table[3] = 1; // [1] STAT, Registered to home network + ATHandler_stub::int_valid_count_table[2] = 9; // [4] ACT, NB-IoT + ATHandler_stub::int_valid_count_table[1] = 1; // [5] cause_type, skipped + ATHandler_stub::int_valid_count_table[0] = 1; // [6] reject_cause, skipped + + ATHandler_stub::read_string_index = 4; + ATHandler_stub::read_string_table[3] = "00C3"; // [2] LAC, 195 + ATHandler_stub::read_string_table[2] = "1234FFC1"; // [3] ci, 305463233 + ATHandler_stub::read_string_table[1] = "00100100"; // [7] active time + ATHandler_stub::read_string_table[0] = "01000111"; // [8] periodic-tau + + ATHandler_stub::urc_handlers[0].cb(); + + // Disconnected + expected_rat = CellularNetwork::RAT_NB1; + expected_status = CellularNetwork::NotRegistered; + expected_cellid = 0; + + ATHandler_stub::int_count = 4; + ATHandler_stub::int_valid_count_table[3] = 0; // [1] STAT, Not reqistered + ATHandler_stub::int_valid_count_table[2] = 9; // [4] ACT, NB-IoT + ATHandler_stub::int_valid_count_table[1] = 1; // [5] cause_type, skipped + ATHandler_stub::int_valid_count_table[0] = 1; // [6] reject_cause, skipped + + ATHandler_stub::read_string_index = 4; + ATHandler_stub::read_string_table[3] = "0000"; // [2] LAC, 0000 + ATHandler_stub::read_string_table[2] = "00000000"; // [3] ci, 000000000 + ATHandler_stub::read_string_table[1] = "00100100"; // [7] active time + ATHandler_stub::read_string_table[0] = "01000111"; // [8] periodic-tau + + ATHandler_stub::urc_handlers[0].cb(); + ATHandler_stub::read_string_index = kRead_string_table_size; + ATHandler_stub::read_string_value = NULL; + ATHandler_stub::ssize_value = 0; +} + TEST_F(TestAT_CellularNetwork, test_AT_CellularNetwork_set_registration) { EventQueue que; From 5ae3b078d4a140980b897cd2119edcd0bfab5d85 Mon Sep 17 00:00:00 2001 From: Kimmo Vaisanen Date: Mon, 16 Sep 2019 15:49:42 +0300 Subject: [PATCH 123/227] Add UT for AT_CellularNetwork::is_active_context --- .../at_cellularnetworktest.cpp | 40 +++++++++++++++++++ .../cellular/framework/API/CellularNetwork.h | 4 +- 2 files changed, 42 insertions(+), 2 deletions(-) diff --git a/UNITTESTS/features/cellular/framework/AT/at_cellularnetwork/at_cellularnetworktest.cpp b/UNITTESTS/features/cellular/framework/AT/at_cellularnetwork/at_cellularnetworktest.cpp index 4fdc9106561..f6dd1baf63b 100644 --- a/UNITTESTS/features/cellular/framework/AT/at_cellularnetwork/at_cellularnetworktest.cpp +++ b/UNITTESTS/features/cellular/framework/AT/at_cellularnetwork/at_cellularnetworktest.cpp @@ -767,3 +767,43 @@ TEST_F(TestAT_CellularNetwork, test_AT_CellularNetwork_set_packet_domain_event_r EXPECT_TRUE(NSAPI_ERROR_DEVICE_ERROR == cn.set_packet_domain_event_reporting(true)); EXPECT_TRUE(NSAPI_ERROR_DEVICE_ERROR == cn.set_packet_domain_event_reporting(false)); } + +TEST_F(TestAT_CellularNetwork, test_AT_CellularNetwork_is_active_context) +{ + EventQueue que; + FileHandle_stub fh1; + ATHandler at(&fh1, que, 0, ","); + + AT_CellularNetwork cn(at); + + // No contexts + int active_contexts = -1; + EXPECT_FALSE(cn.is_active_context(&active_contexts)); + EXPECT_EQ(0, active_contexts); + + // Active contexts + ATHandler_stub::resp_info_true_counter = 2; + ATHandler_stub::int_count = 4; + ATHandler_stub::int_valid_count_table[3] = 0; // ctx 0 + ATHandler_stub::int_valid_count_table[2] = 0; // ctx 0 inactive + ATHandler_stub::int_valid_count_table[1] = 1; // ctx 1 + ATHandler_stub::int_valid_count_table[0] = 1; // ctx 1 active + + EXPECT_TRUE(cn.is_active_context(&active_contexts)); + EXPECT_EQ(1, active_contexts); + + ATHandler_stub::resp_info_true_counter = 2; + ATHandler_stub::int_count = 4; + EXPECT_FALSE(cn.is_active_context(&active_contexts, 0)); + EXPECT_EQ(1, active_contexts); + + ATHandler_stub::resp_info_true_counter = 2; + ATHandler_stub::int_count = 4; + EXPECT_TRUE(cn.is_active_context(&active_contexts, 1)); + EXPECT_EQ(1, active_contexts); + + ATHandler_stub::resp_info_true_counter = 2; + ATHandler_stub::int_count = 4; + EXPECT_TRUE(cn.is_active_context(NULL, 1)); + EXPECT_EQ(1, active_contexts); +} diff --git a/features/cellular/framework/API/CellularNetwork.h b/features/cellular/framework/API/CellularNetwork.h index 357d8a0f23d..947340746f6 100644 --- a/features/cellular/framework/API/CellularNetwork.h +++ b/features/cellular/framework/API/CellularNetwork.h @@ -338,8 +338,8 @@ class CellularNetwork { /** Check if there is any PDP context active. If cid is given, then check is done only for that cid. * - * @param number_of_active_contexts If given then in return contains the number of active contexts - * @param cid If given then active contexts are checked only against this cid + * @param number_of_active_contexts If given then in return contains the number of all active contexts + * @param cid If given then check if the context with this cid is active * * @return true if any (or the given cid) context is active, false otherwise or in case of error */ From 6ac9379093812ca7fe08dac46d49625fc6a264b7 Mon Sep 17 00:00:00 2001 From: Kimmo Vaisanen Date: Mon, 16 Sep 2019 16:00:02 +0300 Subject: [PATCH 124/227] Fix CellularDevice::shutdown UT As shutdown was overridden in test class, original shutdown() method was not called at all. --- UNITTESTS/target_h/myCellularDevice.h | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/UNITTESTS/target_h/myCellularDevice.h b/UNITTESTS/target_h/myCellularDevice.h index ff99be062cd..f69b7dcafd8 100644 --- a/UNITTESTS/target_h/myCellularDevice.h +++ b/UNITTESTS/target_h/myCellularDevice.h @@ -35,7 +35,7 @@ class FileHandle; class myCellularDevice : public CellularDevice { public: myCellularDevice(FileHandle *fh) : CellularDevice(fh), _context_list(0), _network(0) {} - ~myCellularDevice() + virtual ~myCellularDevice() { delete _context_list; delete _network; @@ -125,11 +125,6 @@ class myCellularDevice : public CellularDevice { return NSAPI_ERROR_OK; } - virtual nsapi_error_t shutdown() - { - return NSAPI_ERROR_OK; - } - virtual nsapi_error_t is_ready() { return NSAPI_ERROR_OK; From 9da19e2877ecef0af0d718e230a0420b81c6071a Mon Sep 17 00:00:00 2001 From: Kimmo Vaisanen Date: Tue, 17 Sep 2019 09:05:48 +0300 Subject: [PATCH 125/227] UT for CellularDevice get/set timeouts methods --- .../cellulardevice/cellulardevicetest.cpp | 32 +++++++++++++++++++ UNITTESTS/stubs/CellularStateMachine_stub.cpp | 14 +++++++- UNITTESTS/stubs/CellularStateMachine_stub.h | 2 ++ UNITTESTS/target_h/myCellularDevice.h | 19 +++++++++++ 4 files changed, 66 insertions(+), 1 deletion(-) diff --git a/UNITTESTS/features/cellular/framework/device/cellulardevice/cellulardevicetest.cpp b/UNITTESTS/features/cellular/framework/device/cellulardevice/cellulardevicetest.cpp index cb1c18f87ec..4fc3e0f6c8c 100644 --- a/UNITTESTS/features/cellular/framework/device/cellulardevice/cellulardevicetest.cpp +++ b/UNITTESTS/features/cellular/framework/device/cellulardevice/cellulardevicetest.cpp @@ -240,3 +240,35 @@ TEST_F(TestCellularDevice, test_shutdown) delete dev; } + +TEST_F(TestCellularDevice, test_timeout_array) +{ + FileHandle_stub fh1; + myCellularDevice *dev = new myCellularDevice(&fh1); + EXPECT_TRUE(dev); + + CellularStateMachine_stub::nsapi_error_value = NSAPI_ERROR_OK; + + // Max size + uint16_t set_timeouts[CELLULAR_RETRY_ARRAY_SIZE + 1]; + for (int i = 0; i < CELLULAR_RETRY_ARRAY_SIZE; i++) { + set_timeouts[i] = i + 100; + } + dev->set_retry_timeout_array(set_timeouts, CELLULAR_RETRY_ARRAY_SIZE); + + uint16_t verify_timeouts[CELLULAR_RETRY_ARRAY_SIZE + 1]; + for (int i = 0; i < CELLULAR_RETRY_ARRAY_SIZE; i++) { + verify_timeouts[i] = i + 100; + } + dev->verify_timeout_array(verify_timeouts, CELLULAR_RETRY_ARRAY_SIZE); + + // Empty + dev->set_retry_timeout_array(NULL, 0); + dev->verify_timeout_array(NULL, 0); + + // Oversize (returns only CELLULAR_RETRY_ARRAY_SIZE) + dev->set_retry_timeout_array(set_timeouts, CELLULAR_RETRY_ARRAY_SIZE + 1); + dev->verify_timeout_array(verify_timeouts, CELLULAR_RETRY_ARRAY_SIZE); + + delete dev; +} diff --git a/UNITTESTS/stubs/CellularStateMachine_stub.cpp b/UNITTESTS/stubs/CellularStateMachine_stub.cpp index 974120ad1e2..c38dd5d1093 100644 --- a/UNITTESTS/stubs/CellularStateMachine_stub.cpp +++ b/UNITTESTS/stubs/CellularStateMachine_stub.cpp @@ -24,10 +24,12 @@ nsapi_error_t CellularStateMachine_stub::nsapi_error_value = NSAPI_ERROR_OK; CellularStubState CellularStateMachine_stub::get_current_target_state = STATE_INIT; CellularStubState CellularStateMachine_stub::get_current_current_state = STATE_INIT; bool CellularStateMachine_stub::bool_value = false; +std::vector CellularStateMachine_stub::timeouts; CellularStateMachine::CellularStateMachine(CellularDevice &device, events::EventQueue &queue, CellularNetwork &nw) : _cellularDevice(device), _network(nw), _queue(queue) { + CellularStateMachine_stub::timeouts.clear(); } CellularStateMachine::~CellularStateMachine() @@ -77,11 +79,21 @@ void CellularStateMachine::cellular_event_changed(nsapi_event_t ev, intptr_t ptr void CellularStateMachine::get_retry_timeout_array(uint16_t *timeout, int &array_len) const { - + const int array_size = CellularStateMachine_stub::timeouts.size(); + for (int i = 0; i < array_size; i++) { + timeout[i] = CellularStateMachine_stub::timeouts[i]; + } + array_len = array_size; } void CellularStateMachine::set_retry_timeout_array(const uint16_t timeout[], int array_len) { + CellularStateMachine_stub::timeouts.clear(); + + const int real_size = array_len > CELLULAR_RETRY_ARRAY_SIZE ? CELLULAR_RETRY_ARRAY_SIZE : array_len; + for (int i = 0; i < real_size; i++) { + CellularStateMachine_stub::timeouts.push_back(timeout[i]); + } } void CellularStateMachine::set_timeout(int timeout) diff --git a/UNITTESTS/stubs/CellularStateMachine_stub.h b/UNITTESTS/stubs/CellularStateMachine_stub.h index a42e944df8c..7910e467da5 100644 --- a/UNITTESTS/stubs/CellularStateMachine_stub.h +++ b/UNITTESTS/stubs/CellularStateMachine_stub.h @@ -18,6 +18,7 @@ #define CELLULARSTATEMACHINE_STUB_H_ #include "CellularStateMachine.h" +#include enum CellularStubState { STATE_INIT = 0, @@ -35,6 +36,7 @@ extern nsapi_error_t nsapi_error_value; extern CellularStubState get_current_target_state; extern CellularStubState get_current_current_state; extern bool bool_value; +extern std::vector timeouts; } diff --git a/UNITTESTS/target_h/myCellularDevice.h b/UNITTESTS/target_h/myCellularDevice.h index f69b7dcafd8..6752c0d2007 100644 --- a/UNITTESTS/target_h/myCellularDevice.h +++ b/UNITTESTS/target_h/myCellularDevice.h @@ -22,6 +22,7 @@ #include "FileHandle_stub.h" #include "ATHandler_stub.h" #include "AT_CellularContext.h" +#include "gtest/gtest.h" using namespace events; @@ -175,6 +176,24 @@ class myCellularDevice : public CellularDevice { { return NSAPI_ERROR_OK; } + + void verify_timeout_array(const uint16_t timeout[], int array_len) + { + if (array_len > CELLULAR_RETRY_ARRAY_SIZE) { + FAIL(); + } + uint16_t get_timeouts[CELLULAR_RETRY_ARRAY_SIZE]; + int get_timeouts_len = 0; + + get_retry_timeout_array(get_timeouts, get_timeouts_len); + + EXPECT_EQ(array_len, get_timeouts_len); + + for (int i = 0; i < array_len; i++) { + EXPECT_EQ(timeout[i], get_timeouts[i]); + } + } + AT_CellularNetwork *_network; AT_CellularContext *_context_list; }; From 5861f1a855d693f05100772e9f102baf37249f50 Mon Sep 17 00:00:00 2001 From: Hugues Kamba Date: Thu, 12 Sep 2019 15:57:32 +0100 Subject: [PATCH 126/227] Remove `statement is unreachable` warning in MbedCRC.h The code removed appears unnecessary given that the switch case below also handles the case where the polynomial is `POLY_32BIT_REV_ANSI` --- drivers/MbedCRC.h | 29 +++++++++++++---------------- 1 file changed, 13 insertions(+), 16 deletions(-) diff --git a/drivers/MbedCRC.h b/drivers/MbedCRC.h index e4a388d5616..86d1ddd374c 100644 --- a/drivers/MbedCRC.h +++ b/drivers/MbedCRC.h @@ -514,22 +514,19 @@ class MbedCRC { MBED_STATIC_ASSERT(width <= 32, "Max 32-bit CRC supported"); #if DEVICE_CRC - if (POLY_32BIT_REV_ANSI == polynomial) { - _crc_table = (uint32_t *)Table_CRC_32bit_Rev_ANSI; - _mode = TABLE; - return; - } - crc_mbed_config_t config; - config.polynomial = polynomial; - config.width = width; - config.initial_xor = _initial_value; - config.final_xor = _final_xor; - config.reflect_in = _reflect_data; - config.reflect_out = _reflect_remainder; - - if (hal_crc_is_supported(&config)) { - _mode = HARDWARE; - return; + if (POLY_32BIT_REV_ANSI != polynomial) { + crc_mbed_config_t config; + config.polynomial = polynomial; + config.width = width; + config.initial_xor = _initial_value; + config.final_xor = _final_xor; + config.reflect_in = _reflect_data; + config.reflect_out = _reflect_remainder; + + if (hal_crc_is_supported(&config)) { + _mode = HARDWARE; + return; + } } #endif From d4fe163804f698395afcc19ff42e9cb752366d69 Mon Sep 17 00:00:00 2001 From: Hugues Kamba Date: Wed, 25 Sep 2019 12:20:50 +0100 Subject: [PATCH 127/227] Fix ARMC6 linker error for the bare metal profile The ARMC6 compiler inadvertently introduces the `_scanf_mbtowc` symbol to the build. The commit provides a weak definition of the symbol to satisfy the linker whenever the symbol is included. This affects ARM Compiler 6 version 6.12 and earlier. The compiler error was previously observed when the MICROLIB library is used with the uARM toolchain. However, the weak definition was put in `mbed-os/rtos` which is not included when the bare metal profile is used. --- platform/source/mbed_retarget.cpp | 18 ++++++++++++++++++ .../TOOLCHAIN_ARM_MICRO/mbed_boot_arm_micro.c | 18 ------------------ 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/platform/source/mbed_retarget.cpp b/platform/source/mbed_retarget.cpp index 61adeeb0f90..c4428544d95 100644 --- a/platform/source/mbed_retarget.cpp +++ b/platform/source/mbed_retarget.cpp @@ -1735,3 +1735,21 @@ MBED_WEAK const ticker_info_t *lp_ticker_get_info() }; return &info; } + + +// The below resolves the linker error generated by a bug in Arm Compiler 6 +// The compiler inadvertently introduces the +// _scanf_mbtowc symbol to the build. The code below provides a weak reference +// for the missing symbol. +// Arm Compiler 6 version 6.12 and earlier versions are affected. +typedef int ScanfReadRec; +extern "C" MBED_WEAK long int _scanf_mbtowc( + int ignored, + FILE *p, + ScanfReadRec *sr, + int *charmap, + int exact +) +{ + return 0; +} diff --git a/rtos/source/TARGET_CORTEX/TOOLCHAIN_ARM_MICRO/mbed_boot_arm_micro.c b/rtos/source/TARGET_CORTEX/TOOLCHAIN_ARM_MICRO/mbed_boot_arm_micro.c index 6a94ff87f65..c2ce8ddb198 100644 --- a/rtos/source/TARGET_CORTEX/TOOLCHAIN_ARM_MICRO/mbed_boot_arm_micro.c +++ b/rtos/source/TARGET_CORTEX/TOOLCHAIN_ARM_MICRO/mbed_boot_arm_micro.c @@ -68,21 +68,3 @@ MBED_WEAK void __aeabi_assert(const char *expr, const char *file, int line) { mbed_assert_internal(expr, file, line); } - -// The below resolves the linker error generated by a bug in Arm Compiler 6 -// When building with MicroLib, the compiler inadvertently introduces the -// _scanf_mbtowc symbol to the build. The code below provides a weak reference -// for the missing symbol. -// Arm Compiler 6 version 6.12 and earlier versions are affected. -#include -typedef int ScanfReadRec; -MBED_WEAK long int _scanf_mbtowc( - int ignored, - FILE *p, - ScanfReadRec *sr, - int *charmap, - int exact -) -{ - return 0; -} From 8bed19a9d2b34dc0229e5e0bb90c6b32ecf0a3e0 Mon Sep 17 00:00:00 2001 From: Volodymyr Medvid Date: Thu, 19 Sep 2019 10:40:44 +0100 Subject: [PATCH 128/227] PSOC6: update to PDL 1.3.1.1474 --- .../TARGET_PSOC6/psoc6pdl/RELEASE.md | 27 +- .../devices/include/cy8c6245w_s3d72.h | 1193 +++++++++++++++++ .../devices/include/cy_device_headers.h | 10 +- .../devices/include/cyb06445lqi_s3d42.h | 1193 +++++++++++++++++ .../devices/include/cyb06447bzi_bld53.h | 4 +- .../devices/include/cyb06447bzi_bld54.h | 4 +- .../devices/include/cyb06447bzi_d54.h | 2 +- ...{cyb0644abzi_d44.h => cyb0644abzi_s2d44.h} | 26 +- .../psoc6pdl/drivers/include/cy_prot.h | 7 +- .../psoc6pdl/drivers/include/cy_sysclk.h | 172 +-- .../psoc6pdl/drivers/include/cy_sysint.h | 14 +- .../drivers/include/cy_usbfs_dev_drv.h | 23 +- .../drivers/include/cy_usbfs_dev_drv_pvt.h | 2 +- .../drivers/include/cy_usbfs_dev_drv_reg.h | 2 +- .../psoc6pdl/drivers/source/cy_prot.c | 2 +- .../psoc6pdl/drivers/source/cy_sysclk.c | 2 +- .../psoc6pdl/drivers/source/cy_sysint.c | 2 +- .../drivers/source/cy_usbfs_dev_drv.c | 8 +- .../drivers/source/cy_usbfs_dev_drv_io.c | 4 +- .../drivers/source/cy_usbfs_dev_drv_io_dma.c | 2 +- .../connectivity_wifi-1.0.cypersonality | 6 +- .../Connectivity/43012/hobto/ipblocks.cydata | Bin 531 -> 531 bytes .../43438/CYW43438KUBG/base/view.xml | 16 + .../Connectivity/43438/CYW43438KUBG/info.xml | 6 + .../43438/CYW43438KUBG/studio/presentation | 2 + .../43438/CYW43438KUBG/studio/view.xml | 23 + .../Connectivity/43438/hobto/ipblocks.cydata | Bin 531 -> 531 bytes .../udd/devices/Connectivity/43438/info.xml | 5 + .../Connectivity/43438/studio/view.xml | 1 + .../Connectivity/4343W/hobto/ipblocks.cydata | Bin 531 -> 531 bytes .../studio/connectivity/43xxx_bt_v1.cydata | Bin 275 -> 275 bytes .../studio/connectivity/43xxx_coex_v1.cydata | Bin 275 -> 275 bytes .../studio/connectivity/43xxx_wifi_v1.cydata | Bin 275 -> 275 bytes .../MXS40/PSoC6A2M/CYB0644ABZI-D44/info.xml | 6 - .../base/view.xml | 4 +- .../MXS40/PSoC6A2M/CYB0644ABZI-S2D44/info.xml | 6 + .../CYB0644ABZI-S2D44/studio/presentation | 2 + .../studio/view.xml | 6 +- .../MXS40/PSoC6A2M/hobto/amuxbus.cydata | Bin 2779 -> 2779 bytes .../MXS40/PSoC6A2M/hobto/clocks.cydata | Bin 1511 -> 1511 bytes .../devices/MXS40/PSoC6A2M/hobto/dsi.cydata | Bin 275 -> 275 bytes .../MXS40/PSoC6A2M/hobto/interrupts.cydata | Bin 2543 -> 2543 bytes .../MXS40/PSoC6A2M/hobto/ipblocks.cydata | Bin 16443 -> 16443 bytes .../devices/MXS40/PSoC6A2M/hobto/pins.cydata | Bin 16443 -> 16443 bytes .../MXS40/PSoC6A2M/hobto/triggers.cydata | Bin 16443 -> 16443 bytes .../PSoC6A512K/CY8C6245W-S3D72/base/view.xml | 16 + .../MXS40/PSoC6A512K/CY8C6245W-S3D72/info.xml | 6 + .../CY8C6245W-S3D72}/studio/presentation | 0 .../CY8C6245W-S3D72/studio/view.xml | 60 + .../CYB06445LQI-S3D42/base/view.xml | 16 + .../PSoC6A512K/CYB06445LQI-S3D42/info.xml | 6 + .../CYB06445LQI-S3D42/studio/presentation | 2 + .../CYB06445LQI-S3D42/studio/view.xml | 60 + .../MXS40/PSoC6A512K/hobto/amuxbus.cydata | Bin 1671 -> 1671 bytes .../MXS40/PSoC6A512K/hobto/clocks.cydata | Bin 1167 -> 1167 bytes .../devices/MXS40/PSoC6A512K/hobto/dsi.cydata | Bin 275 -> 275 bytes .../MXS40/PSoC6A512K/hobto/interrupts.cydata | Bin 2169 -> 2169 bytes .../MXS40/PSoC6A512K/hobto/ipblocks.cydata | Bin 16443 -> 16443 bytes .../MXS40/PSoC6A512K/hobto/pins.cydata | Bin 16443 -> 16443 bytes .../MXS40/PSoC6A512K/hobto/triggers.cydata | Bin 16443 -> 16443 bytes .../CYB06447BZI-BLD53/base/view.xml | 2 +- .../CYB06447BZI-BLD53/studio/view.xml | 2 +- .../CYB06447BZI-BLD54/base/view.xml | 2 +- .../CYB06447BZI-BLD54/studio/view.xml | 2 +- .../PSoC6ABLE2/CYB06447BZI-D54/base/view.xml | 2 +- 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.../udd/devices/MXS40/studio/features.mk | 28 +- .../TARGET_PSOC6/psoc6pdl/udd/version.dat | 2 +- .../TARGET_PSOC6/psoc6pdl/udd/version.xml | 2 +- .../TARGET_PSOC6/psoc6pdl/version.xml | 2 +- 113 files changed, 2824 insertions(+), 170 deletions(-) create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245w_s3d72.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06445lqi_s3d42.h rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/{cyb0644abzi_d44.h => cyb0644abzi_s2d44.h} (99%) create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43438/CYW43438KUBG/base/view.xml create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43438/CYW43438KUBG/info.xml create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43438/CYW43438KUBG/studio/presentation create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43438/CYW43438KUBG/studio/view.xml create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43438/info.xml create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43438/studio/view.xml delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-D44/info.xml rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/{CYB0644ABZI-D44 => CYB0644ABZI-S2D44}/base/view.xml (81%) create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/info.xml create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/studio/presentation rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/{CYB0644ABZI-D44 => CYB0644ABZI-S2D44}/studio/view.xml (94%) create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/base/view.xml create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/info.xml rename targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/{PSoC6A2M/CYB0644ABZI-D44 => PSoC6A512K/CY8C6245W-S3D72}/studio/presentation (100%) create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/studio/view.xml create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CYB06445LQI-S3D42/base/view.xml create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CYB06445LQI-S3D42/info.xml create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CYB06445LQI-S3D42/studio/presentation create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CYB06445LQI-S3D42/studio/view.xml diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/RELEASE.md b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/RELEASE.md index ca7d720c447..96b63774056 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/RELEASE.md +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/RELEASE.md @@ -1,31 +1,16 @@ -# PSoC 6 Peripheral Driver Library v1.3.0 +# PSoC 6 Peripheral Driver Library v1.3.1 Please refer to the [README.md](./README.md) and the [PDL API Reference Manual](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/index.html) for a complete description of the Peripheral Driver Library. ### New Features -New Drivers -* [CAN FD 1.0](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__canfd.html) - Updated Drivers -* [DMAC 1.10](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__dmac.html) -* [SD Host 1.30](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__sd_host.html) -* [SMIF 1.40](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__smif.html) -* [Startup 2.60](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__system__config.html) -* [SysPm 4.30](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__syspm.html) -* [USBFS 2.10](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__usbfs__dev__drv.html) +* [SysInt 1.30](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__sysInt.html) +* [USBFS 2.20](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__usbfs__dev__drv.html) Drivers with patch version updates -* [Crypto 2.30.1](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__crypto.html) -* [CTB 1.10.1](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__ctb.html) -* [eFuse 1.10.1](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__efuse.html) -* [Flash 3.30.1](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__flash.html) -* [PDM_PCM 2.20.1](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__pdm_pcm.html) -* [RTC 2.20.1](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__rtc.html) -* [SAR 1.20.1](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__sar.html) -* [SCB 2.30.1](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__scb.html) -* [SysClk 1.40.1](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__sysclk.html) -* [SysLib 2.40.1](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__syslib.html) -* [TCPWM 1.10.1](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__tcpwm.html) +* [Prot 1.30.1](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__prot.html) +* [SysClk 1.40.2](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__sysclk.html) + ### Known Issues None diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245w_s3d72.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245w_s3d72.h new file mode 100644 index 00000000000..45cc953c17d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245w_s3d72.h @@ -0,0 +1,1193 @@ +/***************************************************************************//** +* \file cy8c6245w_s3d72.h +* +* \brief +* CY8C6245W-S3D72 device header +* +* \note +* Generator version: 1.5.0.1292 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CY8C6245W_S3D72_H_ +#define _CY8C6245W_S3D72_H_ + +/** +* \addtogroup group_device CY8C6245W-S3D72 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6245W-S3D72 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CY8C6245W-S3D72 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CY8C6245W-S3D72 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CY8C6245W-S3D72 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00040000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u + +#include "psoc6_03_config.h" +#include "gpio_psoc6_03_100_tqfp.h" + +#define CY_DEVICE_PSOC6A512K +#define CY_SILICON_ID 0xE70E1105UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/** \} CY8C6245W-S3D72 */ + +#endif /* _CY8C6245W_S3D72_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy_device_headers.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy_device_headers.h index 1c08507114e..4a0d2bdfb5d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy_device_headers.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy_device_headers.h @@ -5,7 +5,7 @@ * Common header file to be included by the drivers. * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.5.0.1292 * ******************************************************************************** * \copyright @@ -182,8 +182,8 @@ #include "cy8c6248fni_d43.h" #elif defined (CY8C624ALQI_D42) #include "cy8c624alqi_d42.h" -#elif defined (CYB0644ABZI_D44) - #include "cyb0644abzi_d44.h" +#elif defined (CYB0644ABZI_S2D44) + #include "cyb0644abzi_s2d44.h" #elif defined (CY8C624ABZI_S2D44A0) #include "cy8c624abzi_s2d44a0.h" #elif defined (CY8C624ABZI_S2D44) @@ -220,6 +220,8 @@ #include "cy8c6245azi_s3d42.h" #elif defined (CY8C6245LQI_S3D42) #include "cy8c6245lqi_s3d42.h" +#elif defined (CYB06445LQI_S3D42) + #include "cyb06445lqi_s3d42.h" #elif defined (CY8C6245FNI_S3D41) #include "cy8c6245fni_s3d41.h" #elif defined (CY8C6245AZI_S3D12) @@ -232,6 +234,8 @@ #include "cy8c6245azi_s3d02.h" #elif defined (CY8C6245LQI_S3D02) #include "cy8c6245lqi_s3d02.h" +#elif defined (CY8C6245W_S3D72) + #include "cy8c6245w_s3d72.h" #else #include "cy_device_common.h" #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06445lqi_s3d42.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06445lqi_s3d42.h new file mode 100644 index 00000000000..8b23c5c8b2b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06445lqi_s3d42.h @@ -0,0 +1,1193 @@ +/***************************************************************************//** +* \file cyb06445lqi_s3d42.h +* +* \brief +* CYB06445LQI-S3D42 device header +* +* \note +* Generator version: 1.5.0.1292 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CYB06445LQI_S3D42_H_ +#define _CYB06445LQI_S3D42_H_ + +/** +* \addtogroup group_device CYB06445LQI-S3D42 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CYB06445LQI-S3D42 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CYB06445LQI-S3D42 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CYB06445LQI-S3D42 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CYB06445LQI-S3D42 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00040000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00080000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 7u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 1u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u + +#include "psoc6_03_config.h" +#include "gpio_psoc6_03_68_qfn.h" + +#define CY_DEVICE_PSOC6A512K +#define CY_SILICON_ID 0xE70D1105UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/** \} CYB06445LQI-S3D42 */ + +#endif /* _CYB06445LQI_S3D42_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_bld53.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_bld53.h index 8e912aa0f9a..acd153aae2f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_bld53.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_bld53.h @@ -5,7 +5,7 @@ * CYB06447BZI-BLD53 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.5.0.1292 * ******************************************************************************** * \copyright @@ -458,7 +458,7 @@ typedef enum { #define CY_SRAM_BASE 0x08000000UL #define CY_SRAM_SIZE 0x00048000UL #define CY_FLASH_BASE 0x10000000UL -#define CY_FLASH_SIZE 0x00100000UL +#define CY_FLASH_SIZE 0x000D0000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL #define CY_XIP_BASE 0x18000000UL diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_bld54.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_bld54.h index a4cd2e9d9d3..96163e55f63 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_bld54.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_bld54.h @@ -5,7 +5,7 @@ * CYB06447BZI-BLD54 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.5.0.1292 * ******************************************************************************** * \copyright @@ -458,7 +458,7 @@ typedef enum { #define CY_SRAM_BASE 0x08000000UL #define CY_SRAM_SIZE 0x00048000UL #define CY_FLASH_BASE 0x10000000UL -#define CY_FLASH_SIZE 0x00100000UL +#define CY_FLASH_SIZE 0x000D0000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL #define CY_XIP_BASE 0x18000000UL diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_d54.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_d54.h index 92d90a89b9c..ecc81689f5a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_d54.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb06447bzi_d54.h @@ -5,7 +5,7 @@ * CYB06447BZI-D54 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.5.0.1292 * ******************************************************************************** * \copyright diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb0644abzi_d44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb0644abzi_s2d44.h similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb0644abzi_d44.h rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb0644abzi_s2d44.h index 47894aae801..e5a3c7c1c1f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb0644abzi_d44.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb0644abzi_s2d44.h @@ -1,11 +1,11 @@ /***************************************************************************//** -* \file cyb0644abzi_d44.h +* \file cyb0644abzi_s2d44.h * * \brief -* CYB0644ABZI-D44 device header +* CYB0644ABZI-S2D44 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.5.0.1292 * ******************************************************************************** * \copyright @@ -25,11 +25,11 @@ * limitations under the License. *******************************************************************************/ -#ifndef _CYB0644ABZI_D44_H_ -#define _CYB0644ABZI_D44_H_ +#ifndef _CYB0644ABZI_S2D44_H_ +#define _CYB0644ABZI_S2D44_H_ /** -* \addtogroup group_device CYB0644ABZI-D44 +* \addtogroup group_device CYB0644ABZI-S2D44 * \{ */ @@ -54,7 +54,7 @@ typedef enum { SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ SysTick_IRQn = -1, /*!< -1 System Tick Timer */ - /* CYB0644ABZI-D44 User Interrupt Numbers */ + /* CYB0644ABZI-S2D44 User Interrupt Numbers */ NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ @@ -63,7 +63,7 @@ typedef enum { NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ - /* CYB0644ABZI-D44 Internal SW Interrupt Numbers */ + /* CYB0644ABZI-S2D44 Internal SW Interrupt Numbers */ Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ @@ -85,7 +85,7 @@ typedef enum { DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ SysTick_IRQn = -1, /*!< -1 System Tick Timer */ - /* CYB0644ABZI-D44 Peripheral Interrupt Numbers */ + /* CYB0644ABZI-S2D44 Peripheral Interrupt Numbers */ ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ @@ -264,7 +264,7 @@ typedef enum { (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) -/* CYB0644ABZI-D44 interrupts that can be routed to the CM0+ NVIC */ +/* CYB0644ABZI-S2D44 interrupts that can be routed to the CM0+ NVIC */ typedef enum { ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ @@ -485,7 +485,7 @@ typedef enum { #define CY_SRAM_BASE 0x08000000UL #define CY_SRAM_SIZE 0x00100000UL #define CY_FLASH_BASE 0x10000000UL -#define CY_FLASH_SIZE 0x00200000UL +#define CY_FLASH_SIZE 0x001D0000UL #define CY_EM_EEPROM_BASE 0x14000000UL #define CY_EM_EEPROM_SIZE 0x00008000UL #define CY_XIP_BASE 0x18000000UL @@ -1321,9 +1321,9 @@ typedef enum { #define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ #define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ -/** \} CYB0644ABZI-D44 */ +/** \} CYB0644ABZI-S2D44 */ -#endif /* _CYB0644ABZI_D44_H_ */ +#endif /* _CYB0644ABZI_S2D44_H_ */ /* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_prot.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_prot.h index 8842e1a735c..c51985c4211 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_prot.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_prot.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_prot.h -* \version 1.30 +* \version 1.30.1 * * \brief * Provides an API declaration of the Protection Unit driver @@ -390,6 +390,11 @@ * * * +* +* +* +* +* * * * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysclk.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysclk.h index 0b14e8c7b01..7b80ad6739d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysclk.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysclk.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_sysclk.h -* \version 1.40.1 +* \version 1.40.2 * * Provides an API declaration of the sysclk driver. * @@ -104,6 +104,11 @@ *
VersionChangesReason for Change
1.30.1Snippet updated.Old snippet outdated.
1.30Defect in \ref Cy_Prot_GetPpuProgStruct() function due to faulty defines is fixed.Defect fixing.
* * +* +* +* +* +* * * * @@ -446,15 +451,7 @@ * an external 32.768 kHz square wave is brought in directly through the * SRSS_WCO_OUT_PIN pin. * -* Some devices support a built-in clock supervisor (CSV) in the WCO. The clock -* supervisor detects if the WCO has been lost; that is, the WCO is no longer -* producing clock pulses. The CSV does this by checking to ensure there is at -* least one WCO clock pulse within a certain time window. The ILO or PILO can be -* the supervising clock. Firmware can configure the CSV to trigger a fault, -* a reset, or both after specified cycles of the supervising clock. -* * \defgroup group_sysclk_wco_funcs Functions -* \defgroup group_sysclk_wco_structs Data Structures * \defgroup group_sysclk_wco_enums Enumerated Types * \} * \defgroup group_sysclk_clk_hf High-Frequency Clocks @@ -484,14 +481,7 @@ * * ![](sysclk_hf_dist.png) * -* Some devices support a clock supervisor (CSV) for each root clock. These -* can detect frequency loss, or monitor that the clock frequency stays within -* a specified range. The possible supervising clocks are IMO, ECO, or ALTHF. -* Loss detection and frequency monitoring can be enabled or disabled independently. -* Each has its own programmable action that occurs on detection of an error. -* * \defgroup group_sysclk_clk_hf_funcs Functions -* \defgroup group_sysclk_clk_hf_structs Data Structures * \defgroup group_sysclk_clk_hf_enums Enumerated Types * \} * \defgroup group_sysclk_clk_fast Fast Clock @@ -665,6 +655,7 @@ extern "C" { /** \} group_sysclk_macros */ + /** * \addtogroup group_sysclk_returns * \{ @@ -742,6 +733,7 @@ __STATIC_INLINE void Cy_SysClk_EcoDisable(void) SRSS_CLK_ECO_CONFIG &= ~SRSS_CLK_ECO_CONFIG_ECO_EN_Msk; } + /******************************************************************************* * Function Name: Cy_SysClk_EcoGetStatus ****************************************************************************//** @@ -826,6 +818,7 @@ typedef enum CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT = 3U /**< Output FLL/PLL output regardless of lock status. This can be dangerous if used to clock clkHf, because FLL/PLL output may be unstable */ } cy_en_fll_pll_output_mode_t; + /** FLL current-controlled oscillator (CCO) frequency ranges. * See register CLK_FLL_CONFIG4, bits CCO_RANGE. */ @@ -839,6 +832,7 @@ typedef enum } cy_en_fll_cco_ranges_t; /** \} group_sysclk_fll_enums */ + /** * \addtogroup group_sysclk_fll_structs * \{ @@ -892,6 +886,7 @@ __STATIC_INLINE bool Cy_SysClk_FllIsEnabled(void) return (_FLD2BOOL(SRSS_CLK_FLL_CONFIG_FLL_ENABLE, SRSS_CLK_FLL_CONFIG)); } + /******************************************************************************* * Function Name: Cy_SysClk_FllLocked ****************************************************************************//** @@ -1037,6 +1032,7 @@ __STATIC_INLINE bool Cy_SysClk_PllLocked(uint32_t clkPath) return (_FLD2BOOL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS_CLK_PLL_STATUS[clkPath])); } + /******************************************************************************* * Function Name: Cy_SysClk_PllLostLock ****************************************************************************//** @@ -1064,6 +1060,7 @@ __STATIC_INLINE bool Cy_SysClk_PllLostLock(uint32_t clkPath) return (retVal); } + /******************************************************************************* * Function Name: Cy_SysClk_PllDisable ****************************************************************************//** @@ -1139,6 +1136,7 @@ __STATIC_INLINE void Cy_SysClk_IloEnable(void) SRSS_CLK_ILO_CONFIG |= SRSS_CLK_ILO_CONFIG_ENABLE_Msk; } + /******************************************************************************* * Function Name: Cy_SysClk_IloDisable ****************************************************************************//** @@ -1168,6 +1166,7 @@ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_IloDisable(void) return (retVal); } + /******************************************************************************* * Function Name: Cy_SysClk_IloHibernateOn ****************************************************************************//** @@ -1226,6 +1225,7 @@ __STATIC_INLINE void Cy_SysClk_PiloEnable(void) SRSS_CLK_PILO_CONFIG_PILO_CLK_EN_Msk; } + /******************************************************************************* * Function Name: Cy_SysClk_PiloDisable ****************************************************************************//** @@ -1245,6 +1245,7 @@ __STATIC_INLINE void Cy_SysClk_PiloDisable(void) SRSS_CLK_PILO_CONFIG_PILO_CLK_EN_Msk); } + /******************************************************************************* * Function Name: Cy_SysClk_PiloSetTrim ****************************************************************************//** @@ -1261,6 +1262,7 @@ __STATIC_INLINE void Cy_SysClk_PiloSetTrim(uint32_t trimVal) CY_REG32_CLR_SET(SRSS_CLK_PILO_CONFIG, SRSS_CLK_PILO_CONFIG_PILO_FFREQ, trimVal); } + /******************************************************************************* * Function Name: Cy_SysClk_PiloGetTrim ****************************************************************************//** @@ -1405,59 +1407,44 @@ typedef enum CY_SYSCLK_WCO_NOT_BYPASSED = 0U, /**< WCO is not bypassed crystal is used */ CY_SYSCLK_WCO_BYPASSED = 1U /**< WCO is bypassed external clock must be supplied on XTAL pin */ } cy_en_wco_bypass_modes_t; +/** \} group_sysclk_wco_enums */ -/** WCO CSV supervisor clock selections */ +/** \cond BWC */ typedef enum { - CY_SYSCLK_WCO_CSV_SUPERVISOR_ILO, /**< WCO CSV supervisor clock source is the ILO */ - CY_SYSCLK_WCO_CSV_SUPERVISOR_ALTLF, /**< WCO CSV supervisor clock source is the alternate low-frequency clock (ALTLF) */ - CY_SYSCLK_WCO_CSV_SUPERVISOR_PILO /**< WCO CSV supervisor clock source is the PILO */ + CY_SYSCLK_WCO_CSV_SUPERVISOR_ILO, + CY_SYSCLK_WCO_CSV_SUPERVISOR_ALTLF, + CY_SYSCLK_WCO_CSV_SUPERVISOR_PILO } cy_en_wco_csv_supervisor_clock_t; -/** -* Clock supervisor clock loss window. There must be one clock of the supervised -* clock within this many clocks of the supervising clock. -* See registers CLK_CSV_HF_CTL and CLK_CSV_WCO_CTL, bitfield CSV_LOSS_WINDOW. -*/ typedef enum { - CY_SYSCLK_CSV_LOSS_4_CYCLES = 0U, /**< 1 clock must be seen within 4 cycles of the supervising clock */ - CY_SYSCLK_CSV_LOSS_8_CYCLES = 1U, /**< 1 clock must be seen within 8 cycles of the supervising clock */ - CY_SYSCLK_CSV_LOSS_16_CYCLES = 2U, /**< 1 clock must be seen within 16 cycles of the supervising clock */ - CY_SYSCLK_CSV_LOSS_32_CYCLES = 3U, /**< 1 clock must be seen within 32 cycles of the supervising clock */ - CY_SYSCLK_CSV_LOSS_64_CYCLES = 4U, /**< 1 clock must be seen within 64 cycles of the supervising clock */ - CY_SYSCLK_CSV_LOSS_128_CYCLES = 5U, /**< 1 clock must be seen within 128 cycles of the supervising clock */ - CY_SYSCLK_CSV_LOSS_256_CYCLES = 6U, /**< 1 clock must be seen within 256 cycles of the supervising clock */ - CY_SYSCLK_CSV_LOSS_512_CYCLES = 7U /**< 1 clock must be seen within 512 cycles of the supervising clock */ + CY_SYSCLK_CSV_LOSS_4_CYCLES = 0U, + CY_SYSCLK_CSV_LOSS_8_CYCLES = 1U, + CY_SYSCLK_CSV_LOSS_16_CYCLES = 2U, + CY_SYSCLK_CSV_LOSS_32_CYCLES = 3U, + CY_SYSCLK_CSV_LOSS_64_CYCLES = 4U, + CY_SYSCLK_CSV_LOSS_128_CYCLES = 5U, + CY_SYSCLK_CSV_LOSS_256_CYCLES = 6U, + CY_SYSCLK_CSV_LOSS_512_CYCLES = 7U } cy_en_csv_loss_window_t; -/** -* Clock supervisor error actions. See register CLK_CSV_HF_CTL[CSV_FREQ_ACTION and CSV_LOSS_ACTION]. -*/ typedef enum { - CY_SYSCLK_CSV_ERROR_IGNORE = 0U, /**< Ignore the error reported by the clock supervisor */ - CY_SYSCLK_CSV_ERROR_FAULT = 1U, /**< Trigger a fault when an error is reported by the clock supervisor */ - CY_SYSCLK_CSV_ERROR_RESET = 2U, /**< Trigger a reset when an error is reported by the clock supervisor */ - CY_SYSCLK_CSV_ERROR_FAULT_RESET = 3U /**< Trigger a fault then reset when an error is reported by the supervisor */ + CY_SYSCLK_CSV_ERROR_IGNORE = 0U, + CY_SYSCLK_CSV_ERROR_FAULT = 1U, + CY_SYSCLK_CSV_ERROR_RESET = 2U, + CY_SYSCLK_CSV_ERROR_FAULT_RESET = 3U } cy_en_csv_error_actions_t; -/** \} group_sysclk_wco_enums */ -/** -* \addtogroup group_sysclk_wco_structs -* \{ -*/ -/** -* This structure is used to configure the clock supervisor for the WCO. -*/ typedef struct { - cy_en_wco_csv_supervisor_clock_t supervisorClock; /**< supervisor clock selection */ - bool enableLossDetection; /**< 1= enabled, 0= disabled. Note that if loss detection is enabled, writes to other register bits are ignored */ - cy_en_csv_loss_window_t lossWindow; /**< \ref cy_en_csv_loss_window_t */ - cy_en_csv_error_actions_t lossAction; /**< \ref cy_en_csv_error_actions_t */ + cy_en_wco_csv_supervisor_clock_t supervisorClock; + bool enableLossDetection; + cy_en_csv_loss_window_t lossWindow; + cy_en_csv_error_actions_t lossAction; } cy_stc_wco_csv_config_t; -/** \} group_sysclk_wco_structs */ +/** \endcond */ /** * \addtogroup group_sysclk_wco_funcs @@ -1508,6 +1495,7 @@ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_WcoEnable(uint32_t timeoutus) return (retVal); } + /******************************************************************************* * Function Name: Cy_SysClk_WcoOkay ****************************************************************************//** @@ -1527,6 +1515,7 @@ __STATIC_INLINE bool Cy_SysClk_WcoOkay(void) return (_FLD2BOOL(BACKUP_STATUS_WCO_OK, BACKUP_STATUS)); } + /******************************************************************************* * Function Name: Cy_SysClk_WcoDisable ****************************************************************************//** @@ -1542,6 +1531,7 @@ __STATIC_INLINE void Cy_SysClk_WcoDisable(void) BACKUP_CTL &= (uint32_t)~BACKUP_CTL_WCO_EN_Msk; } + /******************************************************************************* * Function Name: Cy_SysClk_WcoBypass ****************************************************************************//** @@ -1819,38 +1809,29 @@ typedef enum CY_SYSCLK_CLKHF_DIVIDE_BY_4 = 2U, /**< divide clkHf by 4 */ CY_SYSCLK_CLKHF_DIVIDE_BY_8 = 3U /**< divide clkHf by 8 */ } cy_en_clkhf_dividers_t; +/** \} group_sysclk_clk_hf_enums */ -/** -* clkHf clock supervisor input sources. See register CLK_CSV_HF_CTL[CSV_MUX]. -*/ +/** \cond BWC */ typedef enum { - CY_SYSCLK_CLKHF_CSV_SUPERVISOR_IMO = 0U, /**< Supervising clock is the IMO */ - CY_SYSCLK_CLKHF_CSV_SUPERVISOR_EXT = 1U, /**< Supervising clock is the external clock */ - CY_SYSCLK_CLKHF_CSV_SUPERVISOR_ALTHF = 2U /**< Supervising clock is clk_althf */ + CY_SYSCLK_CLKHF_CSV_SUPERVISOR_IMO = 0U, + CY_SYSCLK_CLKHF_CSV_SUPERVISOR_EXT = 1U, + CY_SYSCLK_CLKHF_CSV_SUPERVISOR_ALTHF = 2U } cy_en_clkhf_csv_supervisor_clock_t; -/** \} group_sysclk_clk_hf_enums */ -/** -* \addtogroup group_sysclk_clk_hf_structs -* \{SupervisingWindow -*/ -/** -* This structure is used to configure the clock supervisor for clkHf. -*/ typedef struct { - cy_en_clkhf_csv_supervisor_clock_t supervisorClock; /**< \ref cy_en_clkhf_csv_supervisor_clock_t */ - uint16_t supervisingWindow; /**< Number of supervising clock cycles */ - bool enableFrequencyFaultDetection; /**< 1= enabled, 0= disabled */ - uint16_t frequencyLowerLimit; /**< Lowest frequency in kHz that supervised clock can go */ - uint16_t frequencyUpperLimit; /**< Highest frequency in kHz that supervised clock can go */ - cy_en_csv_error_actions_t frequencyAction; /**< \ref cy_en_csv_error_actions_t */ - bool enableLossDetection; /**< 1= enabled, 0= disabled */ - cy_en_csv_loss_window_t lossWindow; /**< \ref cy_en_csv_loss_window_t */ - cy_en_csv_error_actions_t lossAction; /**< \ref cy_en_csv_error_actions_t */ + cy_en_clkhf_csv_supervisor_clock_t supervisorClock; + uint16_t supervisingWindow; + bool enableFrequencyFaultDetection; + uint16_t frequencyLowerLimit; + uint16_t frequencyUpperLimit; + cy_en_csv_error_actions_t frequencyAction; + bool enableLossDetection; + cy_en_csv_loss_window_t lossWindow; + cy_en_csv_error_actions_t lossAction; } cy_stc_clkhf_csv_config_t; -/** \} group_sysclk_clk_hf_structs */ +/** \endcond */ /** \cond INTERNAL */ extern uint32_t altHfFreq; /* Internal storage for BLE ECO frequency user setting */ @@ -1880,7 +1861,7 @@ __STATIC_INLINE cy_en_clkhf_dividers_t Cy_SysClk_ClkHfGetDivider(uint32_t clkHf) * \return \ref cy_en_sysclk_status_t * * \funcusage -* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfEnable +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPathSetSource * *******************************************************************************/ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfEnable(uint32_t clkHf) @@ -1894,6 +1875,7 @@ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfEnable(uint32_t clkHf) return (retVal); } + /******************************************************************************* * Function Name: Cy_SysClk_ClkHfDisable ****************************************************************************//** @@ -1922,6 +1904,7 @@ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfDisable(uint32_t clkHf) return (retVal); } + /******************************************************************************* * Function Name: Cy_SysClk_ClkHfSetSource ****************************************************************************//** @@ -1961,6 +1944,7 @@ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfSetSource(uint32_t clkHf, c return (retVal); } + /******************************************************************************* * Function Name: Cy_SysClk_ClkHfGetSource ****************************************************************************//** @@ -1981,6 +1965,7 @@ __STATIC_INLINE cy_en_clkhf_in_sources_t Cy_SysClk_ClkHfGetSource(uint32_t clkHf return ((cy_en_clkhf_in_sources_t)(_FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS_CLK_ROOT_SELECT[clkHf]))); } + /******************************************************************************* * Function Name: Cy_SysClk_ClkHfSetDivider ****************************************************************************//** @@ -2022,6 +2007,7 @@ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfSetDivider(uint32_t clkHf, return (retVal); } + /******************************************************************************* * Function Name: Cy_SysClk_ClkHfGetDivider ****************************************************************************//** @@ -2077,6 +2063,7 @@ __STATIC_INLINE uint32_t Cy_SysClk_ClkFastGetFrequency(void) return (CY_SYSLIB_DIV_ROUND(locFreq, locDiv)); } + /******************************************************************************* * Function Name: Cy_SysClk_ClkFastSetDivider ****************************************************************************//** @@ -2107,6 +2094,7 @@ __STATIC_INLINE void Cy_SysClk_ClkFastSetDivider(uint8_t divider) CY_REG32_CLR_SET(CPUSS_CM4_CLOCK_CTL, CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, divider); } + /******************************************************************************* * Function Name: Cy_SysClk_ClkFastGetDivider ****************************************************************************//** @@ -2160,6 +2148,7 @@ __STATIC_INLINE uint32_t Cy_SysClk_ClkPeriGetFrequency(void) return (CY_SYSLIB_DIV_ROUND(locFreq, locDiv)); } + /******************************************************************************* * Function Name: Cy_SysClk_ClkPeriSetDivider ****************************************************************************//** @@ -2183,6 +2172,7 @@ __STATIC_INLINE void Cy_SysClk_ClkPeriSetDivider(uint8_t divider) CY_REG32_CLR_SET(CPUSS_CM0_CLOCK_CTL, CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, divider); } + /******************************************************************************* * Function Name: Cy_SysClk_ClkPeriGetDivider ****************************************************************************//** @@ -2220,6 +2210,7 @@ typedef enum } cy_en_divider_types_t; /** \} group_sysclk_clk_peripheral_enums */ + /** * \addtogroup group_sysclk_clk_peripheral_funcs * \{ @@ -2328,6 +2319,7 @@ __STATIC_INLINE uint32_t Cy_SysClk_PeriphGetDivider(cy_en_divider_types_t divide return (retVal); } + /******************************************************************************* * Function Name: Cy_SysClk_PeriphSetFracDivider ****************************************************************************//** @@ -2390,6 +2382,7 @@ __STATIC_INLINE cy_en_sysclk_status_t return (retVal); } + /******************************************************************************* * Function Name: Cy_SysClk_PeriphGetFracDivider ****************************************************************************//** @@ -2430,6 +2423,7 @@ __STATIC_INLINE void Cy_SysClk_PeriphGetFracDivider(cy_en_divider_types_t divide } } + /******************************************************************************* * Function Name: Cy_SysClk_PeriphAssignDivider ****************************************************************************//** @@ -2468,6 +2462,7 @@ __STATIC_INLINE cy_en_sysclk_status_t return (retVal); } + /******************************************************************************* * Function Name: Cy_SysClk_PeriphGetAssignedDivider ****************************************************************************//** @@ -2489,6 +2484,7 @@ __STATIC_INLINE uint32_t Cy_SysClk_PeriphGetAssignedDivider(en_clk_dst_t ipBlock return (PERI_CLOCK_CTL[ipBlock] & (CY_PERI_CLOCK_CTL_DIV_SEL_Msk | CY_PERI_CLOCK_CTL_TYPE_SEL_Msk)); } + /******************************************************************************* * Function Name: Cy_SysClk_PeriphEnableDivider ****************************************************************************//** @@ -2531,6 +2527,7 @@ __STATIC_INLINE cy_en_sysclk_status_t return (retVal); } + /******************************************************************************* * Function Name: Cy_SysClk_PeriphDisableDivider ****************************************************************************//** @@ -2566,6 +2563,7 @@ __STATIC_INLINE cy_en_sysclk_status_t return (retVal); } + /******************************************************************************* * Function Name: Cy_SysClk_PeriphEnablePhaseAlignDivider ****************************************************************************//** @@ -2621,6 +2619,7 @@ __STATIC_INLINE cy_en_sysclk_status_t return (retVal); } + /******************************************************************************* * Function Name: Cy_SysClk_PeriphGetDividerEnabled ****************************************************************************//** @@ -2726,6 +2725,7 @@ __STATIC_INLINE void Cy_SysClk_ClkSlowSetDivider(uint8_t divider) CY_REG32_CLR_SET(CPUSS_CM0_CLOCK_CTL, CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV, divider); } + /******************************************************************************* * Function Name: Cy_SysClk_ClkSlowGetDivider ****************************************************************************//** @@ -2773,6 +2773,7 @@ typedef enum __STATIC_INLINE void Cy_SysClk_ClkLfSetSource(cy_en_clklf_in_sources_t source); __STATIC_INLINE cy_en_clklf_in_sources_t Cy_SysClk_ClkLfGetSource(void); + /******************************************************************************* * Function Name: Cy_SysClk_ClkLfSetSource ****************************************************************************//** @@ -2793,6 +2794,7 @@ __STATIC_INLINE void Cy_SysClk_ClkLfSetSource(cy_en_clklf_in_sources_t source) CY_REG32_CLR_SET(SRSS_CLK_SELECT, SRSS_CLK_SELECT_LFCLK_SEL, source); } + /******************************************************************************* * Function Name: Cy_SysClk_ClkLfGetSource ****************************************************************************//** @@ -2871,6 +2873,7 @@ __STATIC_INLINE void Cy_SysClk_ClkTimerSetSource(cy_en_clktimer_in_sources_t sou CY_REG32_CLR_SET(SRSS_CLK_TIMER_CTL, CY_SRSS_CLK_TIMER_CTL_TIMER, source); } + /******************************************************************************* * Function Name: Cy_SysClk_ClkTimerGetSource ****************************************************************************//** @@ -2889,6 +2892,7 @@ __STATIC_INLINE cy_en_clktimer_in_sources_t Cy_SysClk_ClkTimerGetSource(void) return ((cy_en_clktimer_in_sources_t)(SRSS_CLK_TIMER_CTL & CY_SRSS_CLK_TIMER_CTL_TIMER_Msk)); } + /******************************************************************************* * Function Name: Cy_SysClk_ClkTimerSetDivider ****************************************************************************//** @@ -2910,6 +2914,7 @@ __STATIC_INLINE void Cy_SysClk_ClkTimerSetDivider(uint8_t divider) CY_REG32_CLR_SET(SRSS_CLK_TIMER_CTL, SRSS_CLK_TIMER_CTL_TIMER_DIV, divider); } + /******************************************************************************* * Function Name: Cy_SysClk_ClkTimerGetDivider ****************************************************************************//** @@ -2927,6 +2932,7 @@ __STATIC_INLINE uint8_t Cy_SysClk_ClkTimerGetDivider(void) return ((uint8_t)_FLD2VAL(SRSS_CLK_TIMER_CTL_TIMER_DIV, SRSS_CLK_TIMER_CTL)); } + /******************************************************************************* * Function Name: Cy_SysClk_ClkTimerEnable ****************************************************************************//** @@ -2943,6 +2949,7 @@ __STATIC_INLINE void Cy_SysClk_ClkTimerEnable(void) SRSS_CLK_TIMER_CTL |= SRSS_CLK_TIMER_CTL_ENABLE_Msk; } + /******************************************************************************* * Function Name: Cy_SysClk_ClkTimerDisable ****************************************************************************//** @@ -2992,6 +2999,7 @@ typedef enum CY_SYSCLK_PUMP_IN_CLKPATH15 /**< Pump clock input is clock path 15 */ } cy_en_clkpump_in_sources_t; + /** * Pump clock (clk_pump) divide options. See CLK_SELECT register, PUMP_DIV bits. * Used with functions \ref Cy_SysClk_ClkPumpSetDivider, and @@ -3026,6 +3034,7 @@ __STATIC_INLINE cy_en_clkpump_divide_t Cy_SysClk_ClkPumpGetDivider(void); __STATIC_INLINE void Cy_SysClk_ClkPumpEnable(void); __STATIC_INLINE void Cy_SysClk_ClkPumpDisable(void); + /******************************************************************************* * Function Name: Cy_SysClk_ClkPumpSetSource ****************************************************************************//** @@ -3048,6 +3057,7 @@ __STATIC_INLINE void Cy_SysClk_ClkPumpSetSource(cy_en_clkpump_in_sources_t sourc CY_REG32_CLR_SET(SRSS_CLK_SELECT, SRSS_CLK_SELECT_PUMP_SEL, source); } + /******************************************************************************* * Function Name: Cy_SysClk_ClkPumpGetSource ****************************************************************************//** @@ -3065,6 +3075,7 @@ __STATIC_INLINE cy_en_clkpump_in_sources_t Cy_SysClk_ClkPumpGetSource(void) return ((cy_en_clkpump_in_sources_t)_FLD2VAL(SRSS_CLK_SELECT_PUMP_SEL, SRSS_CLK_SELECT)); } + /******************************************************************************* * Function Name: Cy_SysClk_ClkPumpSetDivider ****************************************************************************//** @@ -3086,6 +3097,7 @@ __STATIC_INLINE void Cy_SysClk_ClkPumpSetDivider(cy_en_clkpump_divide_t divider) CY_REG32_CLR_SET(SRSS_CLK_SELECT, SRSS_CLK_SELECT_PUMP_DIV, divider); } + /******************************************************************************* * Function Name: Cy_SysClk_ClkPumpGetDivider ****************************************************************************//** @@ -3103,6 +3115,7 @@ __STATIC_INLINE cy_en_clkpump_divide_t Cy_SysClk_ClkPumpGetDivider(void) return ((cy_en_clkpump_divide_t)_FLD2VAL(SRSS_CLK_SELECT_PUMP_DIV, SRSS_CLK_SELECT)); } + /******************************************************************************* * Function Name: Cy_SysClk_ClkPumpEnable ****************************************************************************//** @@ -3119,6 +3132,7 @@ __STATIC_INLINE void Cy_SysClk_ClkPumpEnable(void) SRSS_CLK_SELECT |= SRSS_CLK_SELECT_PUMP_ENABLE_Msk; } + /******************************************************************************* * Function Name: Cy_SysClk_ClkPumpDisable ****************************************************************************//** @@ -3155,6 +3169,7 @@ typedef enum } cy_en_clkbak_in_sources_t; /** \} group_sysclk_clk_bak_enums */ + /** * \addtogroup group_sysclk_clk_bak_funcs * \{ @@ -3185,6 +3200,7 @@ __STATIC_INLINE void Cy_SysClk_ClkBakSetSource(cy_en_clkbak_in_sources_t source) CY_REG32_CLR_SET(BACKUP_CTL, BACKUP_CTL_CLK_SEL, source); } + /******************************************************************************* * Function Name: Cy_SysClk_ClkBakGetSource ****************************************************************************//** diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysint.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysint.h index 00ed0eb8233..1a526c264a6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysint.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysint.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_sysint.h -* \version 1.20 +* \version 1.30 * * \brief * Provides an API declaration of the SysInt driver @@ -170,6 +170,11 @@ *
VersionChangesReason for Change
1.40.2Update documentation based on collateral review feedback.User experience enhancement.
1.40.1Fix compiler warning.
* * +* +* +* +* +* * * * @@ -360,6 +365,7 @@ typedef struct { ((nmiNum) == CY_SYSINT_NMI2) || \ ((nmiNum) == CY_SYSINT_NMI3) || \ ((nmiNum) == CY_SYSINT_NMI4)) + #define CY_SYSINT_IS_PC_0 (0UL == _FLD2VAL(PROT_MPU_MS_CTL_PC, PROT_MPU_MS_CTL(0U))) /** \endcond */ @@ -420,8 +426,8 @@ cy_israddress Cy_SysInt_GetVector(IRQn_Type IRQn); * Interrupt source. This parameter can either be of type cy_en_intr_t or IRQn_Type * based on the selected core. * +* \note CM0+ may call this function only at PC=0, CM4 may set its NMI handler at any PC. * \note The CM0+ NMI is used for performing system calls that execute out of ROM. -* Hence modification of the NMI source is strongly discouraged for this core. * * \funcusage * \snippet sysint/snippet/main.c snippet_Cy_SysInt_SetNmiSource @@ -434,6 +440,10 @@ __STATIC_INLINE void Cy_SysInt_SetNmiSource(cy_en_sysint_nmi_t nmiNum, cy_en_int #endif { CY_ASSERT_L3(CY_SYSINT_IS_NMI_NUM_VALID(nmiNum)); + +#if (CY_CPU_CORTEX_M0P) + CY_ASSERT_L1(CY_SYSINT_IS_PC_0); +#endif if (CY_CPUSS_V1) { diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_usbfs_dev_drv.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_usbfs_dev_drv.h index 840a07a75d2..ef485ccf9dd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_usbfs_dev_drv.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_usbfs_dev_drv.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_usbfs_dev_drv.h -* \version 2.10 +* \version 2.20 * * Provides API declarations of the USBFS driver. * @@ -640,6 +640,22 @@ *
VersionChangesReason for Change
1.30The Cy_SysInt_SetNmiSource is updated with Protection Context check for CM0+.User experience enhancement.
1.20.1The Vector Table section is extended with a code snippet.Documentation enhancement.
* * +* +* +* +* +* +* +* +* +* * * @@ -647,8 +663,9 @@ * continues communication through the endpoint after the host retried * the OUT transaction (the retried transaction has the same toggle bit * as the previous had). -* +* * +* * * - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/features/cellular/xsl_script.sh b/features/cellular/xsl_script.sh deleted file mode 100755 index d5320b42b83..00000000000 --- a/features/cellular/xsl_script.sh +++ /dev/null @@ -1,35 +0,0 @@ -#!/bin/bash - -# Copyright (c) 2015 ARM Limited. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 -# Licensed under the Apache License, Version 2.0 (the License); you may -# not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# * http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an AS IS BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -echo -echo "Creating report" -echo - -echo ' - -' >> lcov/index.xml - -for f in lcov/results/*.xml -do -name=${f##*/} -echo ''>> lcov/index.xml -done - -echo '' >> lcov/index.xml - -echo -echo "Report created to lcov/index.xml (outputs html)" -echo \ No newline at end of file From 5c80e2244bcf1483a590b71149a2ade45375077a Mon Sep 17 00:00:00 2001 From: Cruz Monrreal II Date: Fri, 11 Oct 2019 16:06:01 -0500 Subject: [PATCH 214/227] Fixed Travis CI issue where jobs were/are getting stalled while fetching packages. Something on Travis CI's side has changed such that invoking the 'wait' command within a script attempts to wait on some other jobs in addition to those spawned within the CI job. Workaround is to explicitly collect the PIDs for processes spawned within the script and only wait on those. --- tools/test/travis-ci/functions.sh | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/tools/test/travis-ci/functions.sh b/tools/test/travis-ci/functions.sh index c3b3ff053a0..7da9d76dacd 100644 --- a/tools/test/travis-ci/functions.sh +++ b/tools/test/travis-ci/functions.sh @@ -93,6 +93,9 @@ _fetch_deps() { local pkg="${1}" local dep_list="${2}" + local pid_list="" + + local PID; info "Fetching '${pkg}' archives" @@ -103,9 +106,17 @@ _fetch_deps() || die "Download failed ('${dep}')" \ && info "Fetched ${deps_url}/${dep}.deb" & + PID=$! + pid_list="${pid_list} ${PID}" + done <<< "${dep_list}" - wait + # Ignoring shellcheck warning, since we need to allow parameter expansion to + # turn the list string into parametesr. + # shellcheck disable=SC2086 + wait ${pid_list} + + info "Fetch completed." } From 2eb2dcf9238ccd778b5545164c6cc16c0b0aae37 Mon Sep 17 00:00:00 2001 From: Michal Paszta Date: Tue, 8 Oct 2019 11:00:43 +0300 Subject: [PATCH 215/227] Fix memory leak on NetworkInterface destruction We dynamically allocate memory in every add_event_listener(), but we do not free it on NetworkInterface destruction. --- features/netsocket/NetworkInterface.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/features/netsocket/NetworkInterface.cpp b/features/netsocket/NetworkInterface.cpp index 48d463b5908..fc307c458b9 100644 --- a/features/netsocket/NetworkInterface.cpp +++ b/features/netsocket/NetworkInterface.cpp @@ -144,6 +144,7 @@ NetworkInterface::~NetworkInterface() ns_list_foreach_safe(iface_eventlist_entry_t, entry, event_list) { if (entry->iface == this) { ns_list_remove(event_list, entry); + delete entry; } } } From 2d9a2db39e29520a60a3642fc4c7f6c0c9d6e1ea Mon Sep 17 00:00:00 2001 From: Dominika Maziec Date: Fri, 27 Sep 2019 12:42:41 +0200 Subject: [PATCH 216/227] unitests update for tcp and udp --- .../features/netsocket/SocketAddress/test_SocketAddress.cpp | 6 +++++- UNITTESTS/features/netsocket/TCPSocket/test_TCPSocket.cpp | 2 ++ UNITTESTS/features/netsocket/UDPSocket/test_UDPSocket.cpp | 3 +++ 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/UNITTESTS/features/netsocket/SocketAddress/test_SocketAddress.cpp b/UNITTESTS/features/netsocket/SocketAddress/test_SocketAddress.cpp index d9abf4f656f..553606cf625 100644 --- a/UNITTESTS/features/netsocket/SocketAddress/test_SocketAddress.cpp +++ b/UNITTESTS/features/netsocket/SocketAddress/test_SocketAddress.cpp @@ -162,5 +162,9 @@ TEST_F(TestSocketAddress, bool_operator_ip6_true) EXPECT_TRUE(addr ? true : false); } - +TEST_F(TestSocketAddress, bool_operator_ip6_false) +{ + SocketAddress addr("0:0:0:0:0:0:0:0",80); + EXPECT_FALSE(addr ? true : false); +} diff --git a/UNITTESTS/features/netsocket/TCPSocket/test_TCPSocket.cpp b/UNITTESTS/features/netsocket/TCPSocket/test_TCPSocket.cpp index 40fcf6e1959..24e672370ea 100644 --- a/UNITTESTS/features/netsocket/TCPSocket/test_TCPSocket.cpp +++ b/UNITTESTS/features/netsocket/TCPSocket/test_TCPSocket.cpp @@ -77,6 +77,8 @@ TEST_F(TestTCPSocket, connect) stack.return_value = NSAPI_ERROR_OK; const SocketAddress a("127.0.0.1", 1024); EXPECT_EQ(socket->connect(a), NSAPI_ERROR_OK); + EXPECT_EQ(socket->setsockopt(NSAPI_SOCKET,NSAPI_BIND_TO_DEVICE, "12345", 5), NSAPI_ERROR_UNSUPPORTED); + EXPECT_EQ(socket->connect("127.0.0.1", 1024), NSAPI_ERROR_OK); } TEST_F(TestTCPSocket, connect_no_open) diff --git a/UNITTESTS/features/netsocket/UDPSocket/test_UDPSocket.cpp b/UNITTESTS/features/netsocket/UDPSocket/test_UDPSocket.cpp index f746d010fc0..900abf13a53 100644 --- a/UNITTESTS/features/netsocket/UDPSocket/test_UDPSocket.cpp +++ b/UNITTESTS/features/netsocket/UDPSocket/test_UDPSocket.cpp @@ -74,6 +74,9 @@ TEST_F(TestUDPSocket, sendto_addr_port) stack.return_value = NSAPI_ERROR_OK; EXPECT_EQ(socket->sendto("127.0.0.1", 0, 0, 0), 0); + + EXPECT_EQ(socket->setsockopt(NSAPI_SOCKET,NSAPI_BIND_TO_DEVICE,"12324",5), NSAPI_ERROR_UNSUPPORTED); + EXPECT_EQ(socket->sendto("127.0.0.1", 0, 0, 0), 0); } TEST_F(TestUDPSocket, connect) From 1655c37f4c7396fdfcca0a01148b377c5b504587 Mon Sep 17 00:00:00 2001 From: Michal Paszta Date: Wed, 2 Oct 2019 15:48:59 +0200 Subject: [PATCH 217/227] Improve coverage For the following classes: * DTLSSocket * NetworkInterface * TLSSocketWrapper --- .../netsocket/DTLSSocket/test_DTLSSocket.cpp | 6 +++ .../test_NetworkInterface.cpp | 12 ++++-- .../test_TLSSocketWrapper.cpp | 41 +++++++++++++++++++ 3 files changed, 56 insertions(+), 3 deletions(-) diff --git a/UNITTESTS/features/netsocket/DTLSSocket/test_DTLSSocket.cpp b/UNITTESTS/features/netsocket/DTLSSocket/test_DTLSSocket.cpp index cc4bdc2aecd..f00c5055246 100644 --- a/UNITTESTS/features/netsocket/DTLSSocket/test_DTLSSocket.cpp +++ b/UNITTESTS/features/netsocket/DTLSSocket/test_DTLSSocket.cpp @@ -54,6 +54,12 @@ TEST_F(TestDTLSSocket, constructor) EXPECT_TRUE(socket); } +TEST_F(TestDTLSSocket, connect_no_socket) +{ + EXPECT_TRUE(socket); + EXPECT_EQ(socket->connect("127.0.0.1", 1024), NSAPI_ERROR_NO_SOCKET); +} + /* connect */ TEST_F(TestDTLSSocket, connect) diff --git a/UNITTESTS/features/netsocket/NetworkInterface/test_NetworkInterface.cpp b/UNITTESTS/features/netsocket/NetworkInterface/test_NetworkInterface.cpp index 5dc2575b308..dec2c52cb5f 100644 --- a/UNITTESTS/features/netsocket/NetworkInterface/test_NetworkInterface.cpp +++ b/UNITTESTS/features/netsocket/NetworkInterface/test_NetworkInterface.cpp @@ -64,6 +64,7 @@ class TestNetworkInterface : public testing::Test { TEST_F(TestNetworkInterface, constructor) { EXPECT_TRUE(iface); + iface->set_as_default(); //Empty function. Just trigger it, so it doesn't obscure coverage reports. } // get_default_instance is tested along with the implementations of NetworkInterface. @@ -92,6 +93,12 @@ TEST_F(TestNetworkInterface, get_gateway) EXPECT_EQ(iface->get_gateway(), n); } +TEST_F(TestNetworkInterface, get_interface_name) +{ + char *n = 0; + EXPECT_EQ(iface->get_interface_name(n), n); +} + TEST_F(TestNetworkInterface, set_network) { EXPECT_EQ(iface->set_network("127.0.0.1", "255.255.0.0", "127.0.0.1"), NSAPI_ERROR_UNSUPPORTED); @@ -168,7 +175,7 @@ TEST_F(TestNetworkInterface, add_event_listener) TEST_F(TestNetworkInterface, remove_event_listener) { - // Add two callback and check that both are called + // Add two callbacks and check that both are called callback_is_called = false; second_callback_called = false; iface->add_event_listener(my_iface_callback); @@ -215,7 +222,6 @@ TEST_F(TestNetworkInterface, correct_event_listener_per_interface) EXPECT_EQ(second_callback_called, true); iface->remove_event_listener(my_iface_callback); - iface2->remove_event_listener(my_iface_callback2); - + // Do not call iface2->remove_event_listener, so the destructor can take care of this. delete iface2; } diff --git a/UNITTESTS/features/netsocket/TLSSocketWrapper/test_TLSSocketWrapper.cpp b/UNITTESTS/features/netsocket/TLSSocketWrapper/test_TLSSocketWrapper.cpp index 1d62f948d16..1de1e86bac0 100644 --- a/UNITTESTS/features/netsocket/TLSSocketWrapper/test_TLSSocketWrapper.cpp +++ b/UNITTESTS/features/netsocket/TLSSocketWrapper/test_TLSSocketWrapper.cpp @@ -105,6 +105,20 @@ TEST_F(TestTLSSocketWrapper, constructor_hostname) delete wrapper2; } +TEST_F(TestTLSSocketWrapper, no_socket) +{ + TLSSocketWrapper *wrapperTmp = new TLSSocketWrapper(NULL); + const SocketAddress a("127.0.0.1", 1024); + EXPECT_EQ(wrapperTmp->connect(a), NSAPI_ERROR_NO_SOCKET); + EXPECT_EQ(wrapperTmp->bind(a), NSAPI_ERROR_NO_SOCKET); + EXPECT_EQ(wrapperTmp->setsockopt(0, 0, 0, 0), NSAPI_ERROR_NO_SOCKET); + EXPECT_EQ(wrapperTmp->getsockopt(0, 0, 0, 0), NSAPI_ERROR_NO_SOCKET); + EXPECT_EQ(wrapperTmp->send(dataBuf, dataSize), NSAPI_ERROR_NO_SOCKET); + EXPECT_EQ(wrapperTmp->recv(dataBuf, dataSize), NSAPI_ERROR_NO_SOCKET); + EXPECT_EQ(wrapperTmp->close(), NSAPI_ERROR_NO_SOCKET); + delete wrapperTmp; +} + /* connect */ TEST_F(TestTLSSocketWrapper, connect) @@ -194,6 +208,11 @@ TEST_F(TestTLSSocketWrapper, connect_handshake_fail_ssl_handshake_in_progress) mbedtls_stub.retArray[2] = MBEDTLS_ERR_SSL_WANT_READ; // mbedtls_ssl_handshake error const SocketAddress a("127.0.0.1", 1024); EXPECT_EQ(wrapper->connect(a), NSAPI_ERROR_IN_PROGRESS); + + // Check that send will fail in this situation. + mbedtls_stub.retArray[3] = MBEDTLS_ERR_SSL_WANT_READ; // mbedtls_ssl_handshake error + eventFlagsStubNextRetval.push_back(osFlagsError); // Break the wait loop + EXPECT_EQ(wrapper->send(dataBuf, dataSize), NSAPI_ERROR_WOULD_BLOCK); } TEST_F(TestTLSSocketWrapper, connect_handshake_fail_ssl_get_verify_result) @@ -243,6 +262,17 @@ TEST_F(TestTLSSocketWrapper, send_error_would_block) EXPECT_EQ(wrapper->send(dataBuf, dataSize), NSAPI_ERROR_WOULD_BLOCK); } +TEST_F(TestTLSSocketWrapper, send_device_error) +{ + transport->open((NetworkStack *)&stack); + mbedtls_stub.useCounter = true; + mbedtls_stub.retArray[3] = MBEDTLS_ERR_SSL_FATAL_ALERT_MESSAGE; // mbedtls_ssl_write + eventFlagsStubNextRetval.push_back(osFlagsError); // Break the wait loop + const SocketAddress a("127.0.0.1", 1024); + EXPECT_EQ(wrapper->connect(a), NSAPI_ERROR_OK); + EXPECT_EQ(wrapper->send(dataBuf, dataSize), NSAPI_ERROR_DEVICE_ERROR); +} + TEST_F(TestTLSSocketWrapper, send_to) { transport->open((NetworkStack *)&stack); @@ -294,6 +324,17 @@ TEST_F(TestTLSSocketWrapper, recv_would_block) EXPECT_EQ(wrapper->recv(dataBuf, dataSize), NSAPI_ERROR_WOULD_BLOCK); } +TEST_F(TestTLSSocketWrapper, recv_device_error) +{ + transport->open((NetworkStack *)&stack); + mbedtls_stub.useCounter = true; + mbedtls_stub.retArray[3] = MBEDTLS_ERR_SSL_FATAL_ALERT_MESSAGE; // mbedtls_ssl_write + const SocketAddress a("127.0.0.1", 1024); + EXPECT_EQ(wrapper->connect(a), NSAPI_ERROR_OK); + eventFlagsStubNextRetval.push_back(osFlagsError); // Break the wait loop + EXPECT_EQ(wrapper->recv(dataBuf, dataSize), NSAPI_ERROR_DEVICE_ERROR); +} + TEST_F(TestTLSSocketWrapper, recv_from_no_socket) { SocketAddress a("127.0.0.1", 1024); From 2e222d9bfc4be57be546da9ef5ee469e7e84be30 Mon Sep 17 00:00:00 2001 From: Michal Paszta Date: Wed, 2 Oct 2019 15:50:49 +0200 Subject: [PATCH 218/227] test for InternetSocket::close blocking Close should not take place in case there is someone reading or writing to the socket. --- .../InternetSocket/test_InternetSocket.cpp | 21 +++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/UNITTESTS/features/netsocket/InternetSocket/test_InternetSocket.cpp b/UNITTESTS/features/netsocket/InternetSocket/test_InternetSocket.cpp index 8a757ce9252..c06f6b587c7 100644 --- a/UNITTESTS/features/netsocket/InternetSocket/test_InternetSocket.cpp +++ b/UNITTESTS/features/netsocket/InternetSocket/test_InternetSocket.cpp @@ -18,6 +18,9 @@ #include "gtest/gtest.h" #include "features/netsocket/InternetSocket.h" #include "NetworkStack_stub.h" +#include +#include +#include extern std::list eventFlagsStubNextRetval; @@ -155,10 +158,19 @@ TEST_F(TestInternetSocket, close_during_read) { stack.return_value = NSAPI_ERROR_OK; socket->open((NetworkStack *)&stack); - // when c++11 is available use something like the code below to test the blocking behavior - // socket->add_reader(); - // std::async(c[](){std::this_thread::sleep_for(1ms); socket->rem_reader()}); + // Simulate the blocking behavior by adding a reader. + socket->add_reader(); + // The reader will be removed after we attempt to close the socket. + auto delay = std::chrono::milliseconds(2); + auto fut = std::async(std::launch::async, [&](){std::this_thread::sleep_for(delay); socket->rem_reader();}); + + // close() will block until the other thread calls rem_reader() + auto start = std::chrono::system_clock::now(); EXPECT_EQ(socket->close(), NSAPI_ERROR_OK); + auto end = std::chrono::system_clock::now(); + + auto diff = end - start; + EXPECT_LE(delay, end - start); } TEST_F(TestInternetSocket, modify_multicast_group) @@ -166,9 +178,6 @@ TEST_F(TestInternetSocket, modify_multicast_group) SocketAddress a("127.0.0.1", 1024); stack.return_value = NSAPI_ERROR_OK; socket->open((NetworkStack *)&stack); - // when c++11 is available use something like the code below to test the blocking behavior - // socket->add_reader(); - // std::async(c[](){std::this_thread::sleep_for(1ms); socket->rem_reader()}); EXPECT_EQ(socket->join_multicast_group(a), NSAPI_ERROR_UNSUPPORTED); EXPECT_EQ(socket->leave_multicast_group(a), NSAPI_ERROR_UNSUPPORTED); } From 40c037fc72d1c99f6cfff0aa79aacbf768a3d9c4 Mon Sep 17 00:00:00 2001 From: Michal Paszta Date: Wed, 2 Oct 2019 16:27:05 +0200 Subject: [PATCH 219/227] Astyle fixes --- .../netsocket/InternetSocket/test_InternetSocket.cpp | 5 ++++- .../features/netsocket/SocketAddress/test_SocketAddress.cpp | 2 +- UNITTESTS/features/netsocket/TCPSocket/test_TCPSocket.cpp | 2 +- UNITTESTS/features/netsocket/UDPSocket/test_UDPSocket.cpp | 2 +- 4 files changed, 7 insertions(+), 4 deletions(-) diff --git a/UNITTESTS/features/netsocket/InternetSocket/test_InternetSocket.cpp b/UNITTESTS/features/netsocket/InternetSocket/test_InternetSocket.cpp index c06f6b587c7..f176818dd15 100644 --- a/UNITTESTS/features/netsocket/InternetSocket/test_InternetSocket.cpp +++ b/UNITTESTS/features/netsocket/InternetSocket/test_InternetSocket.cpp @@ -162,7 +162,10 @@ TEST_F(TestInternetSocket, close_during_read) socket->add_reader(); // The reader will be removed after we attempt to close the socket. auto delay = std::chrono::milliseconds(2); - auto fut = std::async(std::launch::async, [&](){std::this_thread::sleep_for(delay); socket->rem_reader();}); + auto fut = std::async(std::launch::async, [&]() { + std::this_thread::sleep_for(delay); + socket->rem_reader(); + }); // close() will block until the other thread calls rem_reader() auto start = std::chrono::system_clock::now(); diff --git a/UNITTESTS/features/netsocket/SocketAddress/test_SocketAddress.cpp b/UNITTESTS/features/netsocket/SocketAddress/test_SocketAddress.cpp index 553606cf625..cc3588a7e6f 100644 --- a/UNITTESTS/features/netsocket/SocketAddress/test_SocketAddress.cpp +++ b/UNITTESTS/features/netsocket/SocketAddress/test_SocketAddress.cpp @@ -164,7 +164,7 @@ TEST_F(TestSocketAddress, bool_operator_ip6_true) TEST_F(TestSocketAddress, bool_operator_ip6_false) { - SocketAddress addr("0:0:0:0:0:0:0:0",80); + SocketAddress addr("0:0:0:0:0:0:0:0", 80); EXPECT_FALSE(addr ? true : false); } diff --git a/UNITTESTS/features/netsocket/TCPSocket/test_TCPSocket.cpp b/UNITTESTS/features/netsocket/TCPSocket/test_TCPSocket.cpp index 24e672370ea..be38eb1d57d 100644 --- a/UNITTESTS/features/netsocket/TCPSocket/test_TCPSocket.cpp +++ b/UNITTESTS/features/netsocket/TCPSocket/test_TCPSocket.cpp @@ -77,7 +77,7 @@ TEST_F(TestTCPSocket, connect) stack.return_value = NSAPI_ERROR_OK; const SocketAddress a("127.0.0.1", 1024); EXPECT_EQ(socket->connect(a), NSAPI_ERROR_OK); - EXPECT_EQ(socket->setsockopt(NSAPI_SOCKET,NSAPI_BIND_TO_DEVICE, "12345", 5), NSAPI_ERROR_UNSUPPORTED); + EXPECT_EQ(socket->setsockopt(NSAPI_SOCKET, NSAPI_BIND_TO_DEVICE, "12345", 5), NSAPI_ERROR_UNSUPPORTED); EXPECT_EQ(socket->connect("127.0.0.1", 1024), NSAPI_ERROR_OK); } diff --git a/UNITTESTS/features/netsocket/UDPSocket/test_UDPSocket.cpp b/UNITTESTS/features/netsocket/UDPSocket/test_UDPSocket.cpp index 900abf13a53..b7f560c6e29 100644 --- a/UNITTESTS/features/netsocket/UDPSocket/test_UDPSocket.cpp +++ b/UNITTESTS/features/netsocket/UDPSocket/test_UDPSocket.cpp @@ -75,7 +75,7 @@ TEST_F(TestUDPSocket, sendto_addr_port) stack.return_value = NSAPI_ERROR_OK; EXPECT_EQ(socket->sendto("127.0.0.1", 0, 0, 0), 0); - EXPECT_EQ(socket->setsockopt(NSAPI_SOCKET,NSAPI_BIND_TO_DEVICE,"12324",5), NSAPI_ERROR_UNSUPPORTED); + EXPECT_EQ(socket->setsockopt(NSAPI_SOCKET, NSAPI_BIND_TO_DEVICE, "12324", 5), NSAPI_ERROR_UNSUPPORTED); EXPECT_EQ(socket->sendto("127.0.0.1", 0, 0, 0), 0); } From 48c445f3587246cb3fb86f63b28fede4a77d6741 Mon Sep 17 00:00:00 2001 From: Jarkko Paso Date: Mon, 7 Oct 2019 16:08:51 +0300 Subject: [PATCH 220/227] S2-LP: sync with development repository --- .../stm-s2lp-rf-driver/source/NanostackRfPhys2lp.cpp | 4 +++- components/802.15.4_RF/stm-s2lp-rf-driver/source/s2lpReg.h | 4 ++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/components/802.15.4_RF/stm-s2lp-rf-driver/source/NanostackRfPhys2lp.cpp b/components/802.15.4_RF/stm-s2lp-rf-driver/source/NanostackRfPhys2lp.cpp index 82641efb407..a32dbfacac3 100644 --- a/components/802.15.4_RF/stm-s2lp-rf-driver/source/NanostackRfPhys2lp.cpp +++ b/components/802.15.4_RF/stm-s2lp-rf-driver/source/NanostackRfPhys2lp.cpp @@ -550,10 +550,11 @@ static void rf_init_registers(void) rf_write_register_field(PCKTCTRL3, PCKT_FORMAT_FIELD, PCKT_FORMAT_802_15_4); rf_write_register_field(MOD2, MOD_TYPE_FIELD, MOD_2FSK); rf_write_register(PCKT_FLT_OPTIONS, 0); - rf_write_register_field(PCKTCTRL1, PCKT_CRCMODE_FIELD, PCKT_CRCMODE_0X1021); + rf_write_register_field(PCKTCTRL1, PCKT_CRCMODE_FIELD, PCKT_CRCMODE_0x04C11DB7); rf_write_register_field(PCKTCTRL1, PCKT_TXSOURCE_FIELD, PCKT_TXSOURCE_NORMAL); rf_write_register_field(PCKTCTRL1, PCKT_WHITENING_FIELD, PCKT_WHITENING_ENABLED); rf_write_register_field(PCKTCTRL2, PCKT_FIXVARLEN_FIELD, PCKT_VARIABLE_LEN); + rf_write_register_field(PCKTCTRL2, PCKT_FCS_TYPE_FIELD, PCKT_FCS_TYPE_4_OCTET); rf_write_register_field(PCKTCTRL3, PCKT_RXMODE_FIELD, PCKT_RXMODE_NORMAL); rf_write_register_field(PCKTCTRL3, PCKT_BYTE_SWAP_FIELD, PCKT_BYTE_SWAP_LSB); rf_write_register(PCKTCTRL5, PCKT_PREAMBLE_LEN); @@ -999,6 +1000,7 @@ static void rf_receive(uint8_t rx_channel) rf_poll_state_change(S2LP_STATE_READY); rf_flush_rx_fifo(); if (rf_update_config == true) { + rf_channel_multiplier = 1; rf_update_config = false; rf_set_channel_configuration_registers(); } diff --git a/components/802.15.4_RF/stm-s2lp-rf-driver/source/s2lpReg.h b/components/802.15.4_RF/stm-s2lp-rf-driver/source/s2lpReg.h index 734109c4ae6..48dc513e549 100644 --- a/components/802.15.4_RF/stm-s2lp-rf-driver/source/s2lpReg.h +++ b/components/802.15.4_RF/stm-s2lp-rf-driver/source/s2lpReg.h @@ -249,10 +249,14 @@ extern "C" { // PCKTCTRL2 #define PCKT_FIXVARLEN_FIELD 0x01 #define PCKT_VARIABLE_LEN (1 << 0) +#define PCKT_FCS_TYPE_FIELD 0x20 +#define PCKT_FCS_TYPE_4_OCTET (0 << 5) +#define PCKT_FCS_TYPE_2_OCTET (1 << 5) // PCKTCTRL1 #define PCKT_CRCMODE_FIELD 0xE0 #define PCKT_CRCMODE_0X1021 (3 << 5) +#define PCKT_CRCMODE_0x04C11DB7 (5 << 5) #define PCKT_TXSOURCE_FIELD 0x0C #define PCKT_TXSOURCE_NORMAL (0 << 2) #define PCKT_WHITENING_FIELD 0x10 From 65def89e942b6b151213280c6b11b63cde2a002d Mon Sep 17 00:00:00 2001 From: Kyle Kearney Date: Thu, 3 Oct 2019 15:55:57 -0700 Subject: [PATCH 221/227] Make devicekey remainder test more meaningful As of 722628be0250fbd09248d92e3e2720775ec0f84b, the "remainder" configuration also uses the default location near the end of flash. Which makes the two tests nearly identical with the exception that the "last two sectors" test correctly handles parts with a low (possibly 1:1) erase size to program size ratio. Therefore, change the "remainder" test to instead be a "default" test that uses the tdb_internal_address/size values, so that it a.) tests something meaningfully different and b.) tests using the custom TDB address/size values if they are provided. c.) functions correctly on devices where the default sector-based size computation does not work (e.g. because of the low erase size to program size ratio) and therefore a custom location and size has been specified. The is_conf_tdb_internal variable is unused and therefore removed. --- .../direct_access_devicekey_test/main.cpp | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/features/storage/TESTS/kvstore/direct_access_devicekey_test/main.cpp b/features/storage/TESTS/kvstore/direct_access_devicekey_test/main.cpp index cf6a60f9f81..6ec412eacd8 100644 --- a/features/storage/TESTS/kvstore/direct_access_devicekey_test/main.cpp +++ b/features/storage/TESTS/kvstore/direct_access_devicekey_test/main.cpp @@ -50,7 +50,7 @@ static inline uint32_t align_down(uint64_t val, uint64_t size) return (((val) / size)) * size; } -int get_virtual_TDBStore_position(uint32_t conf_start_address, uint32_t conf_size, bool is_conf_tdb_internal, +int get_virtual_TDBStore_position(uint32_t conf_start_address, uint32_t conf_size, uint32_t *tdb_start_address, uint32_t *tdb_end_address) { uint32_t bd_final_size = conf_size; @@ -117,14 +117,14 @@ int get_virtual_TDBStore_position(uint32_t conf_start_address, uint32_t conf_si } -void test_direct_access_to_devicekey_tdb_flashiap_remainder() +void test_direct_access_to_devicekey_tdb_flashiap_default() { - utest_printf("Test Direct Access To DeviceKey Test Entire FlashIAP Remainder\n"); + utest_printf("Test Direct Access To DeviceKey Test Entire FlashIAP Default Address\n"); uint32_t flash_bd_start_address; uint32_t flash_bd_end_address; - int err = get_virtual_TDBStore_position(0, 0, true, &flash_bd_start_address, &flash_bd_end_address); + int err = get_virtual_TDBStore_position(MBED_CONF_STORAGE_TDB_INTERNAL_INTERNAL_BASE_ADDRESS, MBED_CONF_STORAGE_TDB_INTERNAL_INTERNAL_SIZE, &flash_bd_start_address, &flash_bd_end_address); TEST_SKIP_UNLESS_MESSAGE(err != -2, "Test skipped. Not enough available space on Internal FlashIAP"); TEST_ASSERT_EQUAL(0, err); uint32_t flash_bd_size = flash_bd_end_address - flash_bd_start_address; @@ -177,7 +177,7 @@ void test_direct_access_to_devicekey_tdb_last_two_sectors() uint32_t flash_bd_start_address; uint32_t flash_bd_end_address; - int err = get_virtual_TDBStore_position(0, 0, false, &flash_bd_start_address, &flash_bd_end_address); + int err = get_virtual_TDBStore_position(0, 0, &flash_bd_start_address, &flash_bd_end_address); TEST_SKIP_UNLESS_MESSAGE(err != -2, "Test skipped. Not enough available space on Internal FlashIAP"); TEST_ASSERT_EQUAL(0, err); @@ -258,7 +258,6 @@ void test_direct_access_to_device_inject_root() // Now use Direct Access To DeviceKey to retrieve it uint32_t internal_start_address; uint32_t internal_rbp_size; - bool is_conf_tdb_internal = false; if (strcmp(STR(MBED_CONF_STORAGE_STORAGE_TYPE), "FILESYSTEM") == 0) { internal_start_address = MBED_CONF_STORAGE_FILESYSTEM_INTERNAL_BASE_ADDRESS; internal_rbp_size = MBED_CONF_STORAGE_FILESYSTEM_RBP_INTERNAL_SIZE; @@ -268,7 +267,6 @@ void test_direct_access_to_device_inject_root() } else if (strcmp(STR(MBED_CONF_STORAGE_STORAGE_TYPE), "TDB_INTERNAL") == 0) { internal_start_address = MBED_CONF_STORAGE_TDB_INTERNAL_INTERNAL_BASE_ADDRESS; internal_rbp_size = MBED_CONF_STORAGE_TDB_INTERNAL_INTERNAL_SIZE; - is_conf_tdb_internal = true; } else if (strcmp(STR(MBED_CONF_STORAGE_STORAGE_TYPE), "default") == 0) { #if COMPONENT_QSPIF || COMPONENT_SPIF || COMPONENT_DATAFLASH internal_start_address = MBED_CONF_STORAGE_TDB_EXTERNAL_INTERNAL_BASE_ADDRESS; @@ -279,7 +277,6 @@ void test_direct_access_to_device_inject_root() #elif COMPONENT_FLASHIAP internal_start_address = MBED_CONF_STORAGE_TDB_INTERNAL_INTERNAL_BASE_ADDRESS; internal_rbp_size = MBED_CONF_STORAGE_TDB_INTERNAL_INTERNAL_SIZE; - is_conf_tdb_internal = true; #else TEST_SKIP_UNLESS_MESSAGE(false, "Test skipped. No KVStore Internal"); #endif @@ -289,7 +286,7 @@ void test_direct_access_to_device_inject_root() uint32_t tdb_st_add = 0; uint32_t tdb_end_add = 0; - ret = get_virtual_TDBStore_position(internal_start_address, internal_rbp_size, is_conf_tdb_internal, &tdb_st_add, &tdb_end_add); + ret = get_virtual_TDBStore_position(internal_start_address, internal_rbp_size, &tdb_st_add, &tdb_end_add); TEST_SKIP_UNLESS_MESSAGE(ret != -2, "Test skipped. Not enough available space on Internal FlashIAP"); TEST_ASSERT_EQUAL(0, ret); @@ -329,7 +326,7 @@ utest::v1::status_t greentea_failure_handler(const Case *const source, const fai } Case cases[] = { - Case("Testing direct access to devicekey with tdb over flashiap remainder", test_direct_access_to_devicekey_tdb_flashiap_remainder, greentea_failure_handler), + Case("Testing direct access to devicekey with tdb over flashiap default placement", test_direct_access_to_devicekey_tdb_flashiap_default, greentea_failure_handler), Case("Testing direct access to devicekey with tdb over last two sectors", test_direct_access_to_devicekey_tdb_last_two_sectors, greentea_failure_handler), Case("Testing direct access to injected devicekey ", test_direct_access_to_device_inject_root, greentea_failure_handler), }; From 58c541fe80eb854a1a36a4aa080d3d0f0f0a7b8f Mon Sep 17 00:00:00 2001 From: adbridge Date: Wed, 16 Oct 2019 11:58:38 +0100 Subject: [PATCH 222/227] Update Mbed version block --- platform/mbed_version.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/platform/mbed_version.h b/platform/mbed_version.h index 854e9deb74b..c1773417cb4 100644 --- a/platform/mbed_version.h +++ b/platform/mbed_version.h @@ -45,7 +45,7 @@ * * @note 99 is default value for development version (master branch) */ -#define MBED_PATCH_VERSION 0 +#define MBED_PATCH_VERSION 1 #define MBED_ENCODE_VERSION(major, minor, patch) ((major)*10000 + (minor)*100 + (patch)) From a8c0491173129822b1ae3a2d45f5613e87d6cb28 Mon Sep 17 00:00:00 2001 From: Jarkko Paso Date: Mon, 7 Oct 2019 13:00:49 +0300 Subject: [PATCH 223/227] Merge commit '3e6cb31659a56d343c7b8fe37645f195eb87ffcf' * commit '3e6cb31659a56d343c7b8fe37645f195eb87ffcf': Squashed 'features/nanostack/sal-stack-nanostack/' changes from c473148..0824752 --- .../nanostack/dhcp_service_api.h | 10 ++ .../sal-stack-nanostack/nanostack/sw_mac.h | 8 + .../nanostack/ws_bbr_api.h | 22 +++ .../source/6LoWPAN/MAC/mac_helper.c | 14 +- .../source/6LoWPAN/MAC/mac_helper.h | 2 +- .../source/6LoWPAN/ws/ws_bbr_api.c | 15 ++ .../source/6LoWPAN/ws/ws_bootstrap.c | 18 +- .../source/6LoWPAN/ws/ws_common.c | 9 + .../source/6LoWPAN/ws/ws_config.h | 8 + .../source/6LoWPAN/ws/ws_pae_auth.c | 4 +- .../source/6LoWPAN/ws/ws_pae_controller.c | 87 +++++++++- .../source/6LoWPAN/ws/ws_pae_controller.h | 41 +++++ .../source/6LoWPAN/ws/ws_pae_lib.c | 14 +- .../source/6LoWPAN/ws/ws_pae_supp.c | 9 +- .../source/Common_Protocols/icmpv6.c | 7 +- .../source/Common_Protocols/udp.c | 7 +- .../DHCPv6_client/dhcpv6_client_service.c | 23 ++- .../source/MAC/IEEE802_15_4/mac_defines.h | 18 +- .../source/MAC/IEEE802_15_4/mac_mcps_sap.c | 112 +++++++++--- .../source/MAC/IEEE802_15_4/mac_mcps_sap.h | 2 + .../source/MAC/IEEE802_15_4/mac_mlme.c | 59 +++---- .../source/MAC/IEEE802_15_4/mac_mlme.h | 5 - .../source/MAC/IEEE802_15_4/mac_pd_sap.c | 16 +- .../MAC/IEEE802_15_4/mac_security_mib.c | 153 +++++++++++++++- .../MAC/IEEE802_15_4/mac_security_mib.h | 27 ++- .../source/MAC/IEEE802_15_4/sw_mac.c | 9 + .../source/RPL/rpl_control.c | 37 +++- .../source/RPL/rpl_control.h | 5 + .../source/RPL/rpl_downward.c | 26 ++- .../source/RPL/rpl_policy.c | 47 ++++- .../source/RPL/rpl_policy.h | 11 ++ .../source/RPL/rpl_structures.h | 1 + .../source/RPL/rpl_upward.c | 28 ++- .../source/Security/kmp/kmp_api.c | 5 + .../source/Security/kmp/kmp_api.h | 10 ++ .../eap_tls_sec_prot/auth_eap_tls_sec_prot.c | 28 ++- .../eap_tls_sec_prot/eap_tls_sec_prot_lib.c | 17 ++ .../eap_tls_sec_prot/eap_tls_sec_prot_lib.h | 13 ++ .../eap_tls_sec_prot/supp_eap_tls_sec_prot.c | 23 ++- .../fwh_sec_prot/auth_fwh_sec_prot.c | 9 +- .../fwh_sec_prot/supp_fwh_sec_prot.c | 5 + .../gkh_sec_prot/auth_gkh_sec_prot.c | 10 +- .../gkh_sec_prot/supp_gkh_sec_prot.c | 12 +- .../Security/protocols/sec_prot_certs.c | 49 ++++++ .../Security/protocols/sec_prot_certs.h | 42 +++++ .../source/Security/protocols/sec_prot_lib.c | 15 +- .../source/Security/protocols/sec_prot_lib.h | 9 + .../protocols/tls_sec_prot/tls_sec_prot.c | 32 +++- .../protocols/tls_sec_prot/tls_sec_prot.h | 8 +- .../protocols/tls_sec_prot/tls_sec_prot_lib.c | 164 ++++++++++++++++-- .../source/libDHCPv6/dhcp_service_api.c | 18 ++ .../source/libDHCPv6/libDHCPv6.c | 11 ++ .../source/libDHCPv6/libDHCPv6.h | 1 + .../source/libNET/src/ns_net.c | 12 ++ 54 files changed, 1167 insertions(+), 180 deletions(-) diff --git a/features/nanostack/sal-stack-nanostack/nanostack/dhcp_service_api.h b/features/nanostack/sal-stack-nanostack/nanostack/dhcp_service_api.h index 27315a55406..e4759a59515 100644 --- a/features/nanostack/sal-stack-nanostack/nanostack/dhcp_service_api.h +++ b/features/nanostack/sal-stack-nanostack/nanostack/dhcp_service_api.h @@ -217,6 +217,16 @@ void dhcp_service_update_server_address(uint32_t msg_tr_id, uint8_t *server_addr */ void dhcp_service_req_remove(uint32_t msg_tr_id); +/** + * \brief Stops transactions for a messages (retransmissions). + * + * Clears off sending retransmissions for a particular message transaction by finding it via its message class pointer. + * + * \param msg_class_ptr The message class pointer. + * + */ +void dhcp_service_req_remove_all(void *msg_class_ptr); + /** * \brief Timer tick function for retransmissions. * diff --git a/features/nanostack/sal-stack-nanostack/nanostack/sw_mac.h b/features/nanostack/sal-stack-nanostack/nanostack/sw_mac.h index 6bdfc7eeb7d..e4a018fc4e9 100644 --- a/features/nanostack/sal-stack-nanostack/nanostack/sw_mac.h +++ b/features/nanostack/sal-stack-nanostack/nanostack/sw_mac.h @@ -97,6 +97,14 @@ extern int ns_sw_mac_phy_statistics_start(struct mac_api_s *mac_api, struct phy_ */ extern uint32_t ns_sw_mac_read_current_timestamp(struct mac_api_s *mac_api); +/** + * @brief Enable or disable Frame counter per security key. SW MAC must be create before enable this feature! + * @param mac_api MAC instance. + * @param enable_feature True will allocate frame counter table for devices / key False will clear mode and free counter table. + * @return 0 on success, -1 on fail. + */ +extern int8_t ns_sw_mac_enable_frame_counter_per_key(struct mac_api_s *mac_api, bool enable_feature); + #ifdef __cplusplus } #endif diff --git a/features/nanostack/sal-stack-nanostack/nanostack/ws_bbr_api.h b/features/nanostack/sal-stack-nanostack/nanostack/ws_bbr_api.h index dbfb20b25ad..a4d4d460e8f 100644 --- a/features/nanostack/sal-stack-nanostack/nanostack/ws_bbr_api.h +++ b/features/nanostack/sal-stack-nanostack/nanostack/ws_bbr_api.h @@ -140,4 +140,26 @@ int ws_bbr_node_access_revoke_start(int8_t interface_id); */ int ws_bbr_eapol_node_limit_set(int8_t interface_id, uint16_t limit); +/** + * Extended certificate validation + */ +#define BBR_CRT_EXT_VALID_NONE 0x00 /**< Do not make extended validations */ +#define BBR_CRT_EXT_VALID_WISUN 0x01 /**< Validate Wi-SUN specific fields */ + +/** + * Sets extended certificate validation setting + * + * Sets extended certificate validation setting on border router. Function can be used + * to set which fields on client certificate are validated. + * + * \param interface_id Network interface ID + * \param validation Extended Certificate validation setting + * BBR_CRT_EXT_VALID_NONE Do not make extended validations + * BBR_CRT_EXT_VALID_WISUN Validate Wi-SUN specific fields + * + * \return 0 Validation setting was set + * \return <0 Setting set failed + */ +int ws_bbr_ext_certificate_validation_set(int8_t interface_id, uint8_t validation); + #endif /* WS_BBR_API_H_ */ diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/MAC/mac_helper.c b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/MAC/mac_helper.c index 177113f46e3..f6bc6626f6a 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/MAC/mac_helper.c +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/MAC/mac_helper.c @@ -349,12 +349,12 @@ int8_t mac_helper_security_default_recv_key_set(protocol_interface_info_entry_t return 0; } -int8_t mac_helper_security_auto_request_key_index_set(protocol_interface_info_entry_t *interface, uint8_t id) +int8_t mac_helper_security_auto_request_key_index_set(protocol_interface_info_entry_t *interface, uint8_t key_attibute_index, uint8_t id) { if (id == 0) { return -1; } - + interface->mac_parameters->mac_default_key_attribute_id = key_attibute_index; mac_helper_pib_8bit_set(interface, macAutoRequestKeyIndex, id); return 0; } @@ -442,13 +442,11 @@ void mac_helper_security_key_swap_next_to_default(protocol_interface_info_entry_ interface->mac_parameters->mac_prev_key_index = interface->mac_parameters->mac_default_key_index; interface->mac_parameters->mac_prev_key_attribute_id = interface->mac_parameters->mac_default_key_attribute_id; - interface->mac_parameters->mac_default_key_index = interface->mac_parameters->mac_next_key_index; - interface->mac_parameters->mac_default_key_attribute_id = interface->mac_parameters->mac_next_key_attribute_id; + mac_helper_security_auto_request_key_index_set(interface, interface->mac_parameters->mac_next_key_attribute_id, interface->mac_parameters->mac_next_key_index); + interface->mac_parameters->mac_next_key_index = 0; interface->mac_parameters->mac_next_key_attribute_id = prev_attribute; - mac_helper_pib_8bit_set(interface, macAutoRequestKeyIndex, interface->mac_parameters->mac_default_key_index); - } void mac_helper_security_key_clean(protocol_interface_info_entry_t *interface) @@ -841,7 +839,7 @@ int8_t mac_helper_link_frame_counter_read(int8_t interface_id, uint32_t *seq_ptr } mlme_get_t get_req; get_req.attr = macFrameCounter; - get_req.attr_index = 0; + get_req.attr_index = cur->mac_parameters->mac_default_key_attribute_id; cur->mac_api->mlme_req(cur->mac_api, MLME_GET, &get_req); *seq_ptr = cur->mac_parameters->security_frame_counter; @@ -858,7 +856,7 @@ int8_t mac_helper_link_frame_counter_set(int8_t interface_id, uint32_t seq_ptr) } mlme_set_t set_req; set_req.attr = macFrameCounter; - set_req.attr_index = 0; + set_req.attr_index = cur->mac_parameters->mac_default_key_attribute_id; set_req.value_pointer = &seq_ptr; set_req.value_size = 4; cur->mac_api->mlme_req(cur->mac_api, MLME_SET, &set_req); diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/MAC/mac_helper.h b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/MAC/mac_helper.h index 025df0313b1..3cee0175395 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/MAC/mac_helper.h +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/MAC/mac_helper.h @@ -69,7 +69,7 @@ int8_t mac_helper_security_default_key_set(struct protocol_interface_info_entry int8_t mac_helper_security_default_recv_key_set(struct protocol_interface_info_entry *interface, const uint8_t *key, uint8_t id, uint8_t keyid_mode); -int8_t mac_helper_security_auto_request_key_index_set(struct protocol_interface_info_entry *interface, uint8_t id); +int8_t mac_helper_security_auto_request_key_index_set(struct protocol_interface_info_entry *interface, uint8_t key_attibute_index, uint8_t id); int8_t mac_helper_security_next_key_set(struct protocol_interface_info_entry *interface, uint8_t *key, uint8_t id, uint8_t keyid_mode); diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bbr_api.c b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bbr_api.c index 317ab8ac785..f01c07b110f 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bbr_api.c +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bbr_api.c @@ -636,3 +636,18 @@ int ws_bbr_eapol_node_limit_set(int8_t interface_id, uint16_t limit) return -1; #endif } + +int ws_bbr_ext_certificate_validation_set(int8_t interface_id, uint8_t validation) +{ + (void) interface_id; +#ifdef HAVE_WS_BORDER_ROUTER + bool enabled = false; + if (validation & BBR_CRT_EXT_VALID_WISUN) { + enabled = true; + } + return ws_pae_controller_ext_certificate_validation_set(interface_id, enabled); +#else + (void) validation; + return -1; +#endif +} diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap.c b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap.c index 8483b7de8e7..cc651f10339 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap.c +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_bootstrap.c @@ -1371,7 +1371,7 @@ static void ws_bootstrap_neighbor_table_clean(struct protocol_interface_info_ent //Read current timestamp uint32_t time_from_last_unicast_shedule = ws_time_from_last_unicast_traffic(current_time_stamp, ws_neighbor); - if (time_from_last_unicast_shedule > WS_NEIGHBOR_TEMPORARY_LINK_MIN_TIMEOUT || !ws_neighbor->unicast_data_rx) { + if (time_from_last_unicast_shedule > WS_NEIGHBOR_TEMPORARY_LINK_MIN_TIMEOUT) { //Accept only Enough Old Device if (!neighbor_entry_ptr) { //Accept first compare @@ -1581,6 +1581,10 @@ int ws_bootstrap_init(int8_t interface_id, net_6lowpan_mode_e bootstrap_mode) return -2; } + if (ns_sw_mac_enable_frame_counter_per_key(cur->mac_api, true)) { + return -1; + } + if (!etx_storage_list_allocate(cur->id, buffer.device_decription_table_size)) { return -1; } @@ -1940,6 +1944,9 @@ static void ws_dhcp_client_global_adress_cb(int8_t interface, uint8_t dhcp_addr[ if (cur) { rpl_control_register_address(cur, prefix); } + } else { + //Delete dhcpv6 client + dhcp_client_global_address_delete(interface, dhcp_addr, prefix); } } @@ -2055,6 +2062,9 @@ static void ws_bootstrap_rpl_activate(protocol_interface_info_entry_t *cur) // If i am router I Do this rpl_control_force_leaf(protocol_6lowpan_rpl_domain, leaf); rpl_control_request_parent_link_confirmation(true); + rpl_control_set_dio_multicast_min_config_advertisment_count(WS_MIN_DIO_MULTICAST_CONFIG_ADVERTISMENT_COUNT); + rpl_control_set_dao_retry_count(WS_MAX_DAO_RETRIES); + rpl_control_set_initial_dao_ack_wait(WS_MAX_DAO_INITIAL_TIMEOUT); cur->ws_info->rpl_state = 0xff; // Set invalid state and learn from event } @@ -2107,7 +2117,9 @@ static void ws_bootstrap_start_discovery(protocol_interface_info_entry_t *cur) ws_bootstrap_neighbor_list_clean(cur); // Clear RPL information - rpl_control_remove_domain_from_interface(cur); + rpl_control_free_domain_instances_from_interface(cur); + // Clear EAPOL relay address + ws_eapol_relay_delete(cur); // Clear ip stack from old information ws_bootstrap_ip_stack_reset(cur); @@ -2169,7 +2181,7 @@ static void ws_bootstrap_nw_key_clear(protocol_interface_info_entry_t *cur, uint static void ws_bootstrap_nw_key_index_set(protocol_interface_info_entry_t *cur, uint8_t index) { // Set send key - mac_helper_security_auto_request_key_index_set(cur, index + 1); + mac_helper_security_auto_request_key_index_set(cur, index, index + 1); } static void ws_bootstrap_nw_frame_counter_set(protocol_interface_info_entry_t *cur, uint32_t counter) diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_common.c b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_common.c index e9a8e025c11..cb2970ec1b4 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_common.c +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_common.c @@ -31,6 +31,8 @@ #include "Service_Libs/etx/etx.h" #include "Service_Libs/mac_neighbor_table/mac_neighbor_table.h" #include "Service_Libs/blacklist/blacklist.h" +#include "RPL/rpl_protocol.h" +#include "RPL/rpl_control.h" #include "ws_management_api.h" #include "mac_api.h" @@ -404,6 +406,13 @@ bool ws_common_allow_child_registration(protocol_interface_info_entry_t *interfa return true; } + //Verify that we have Selected Parent + if (interface->bootsrap_mode != ARM_NWK_BOOTSRAP_MODE_6LoWPAN_BORDER_ROUTER && !rpl_control_parent_candidate_list_size(interface, true)) { + tr_info("Do not accept new ARO child: no selected parent"); + return false; + } + + ns_list_foreach_safe(mac_neighbor_table_entry_t, cur, &mac_neighbor_info(interface)->neighbour_list) { if (ipv6_neighbour_has_registered_by_eui64(&interface->ipv6_neighbour_cache, cur->mac64)) { diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_config.h b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_config.h index 0d63c67c6b9..ee05b7fb44e 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_config.h +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_config.h @@ -133,4 +133,12 @@ extern uint8_t DEVICE_MIN_SENS; #define FRAME_COUNTER_INCREMENT 1000 // How much frame counter is incremented on start up #define FRAME_COUNTER_STORE_THRESHOLD 800 // How much frame counter must increment before it is stored + +/* + * RPL Configuration parameters + */ +#define WS_MAX_DAO_RETRIES 3 // With 40s, 80s, 160s, 320s, 640s +#define WS_MAX_DAO_INITIAL_TIMEOUT 400 // With 40s initial value exponentially increasing +#define WS_MIN_DIO_MULTICAST_CONFIG_ADVERTISMENT_COUNT 10 // Define 10 multicast advertisment when learn config or learn config update + #endif /* WS_CONFIG_H_ */ diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_auth.c b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_auth.c index 8e20e856fb1..e4ec775a398 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_auth.c +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_auth.c @@ -919,12 +919,12 @@ static void ws_pae_auth_next_kmp_trigger(pae_auth_t *pae_auth, supp_entry_t *sup kmp_api_t *api = ws_pae_lib_kmp_list_type_get(&supp_entry->kmp_list, next_type); if (api != NULL) { + /* For other types than GTK, only one ongoing negotiation at the same time, + for GTK there can be previous terminating and the new one for next key index */ if (next_type != IEEE_802_11_GKH) { tr_info("KMP already ongoing; ignored, eui-64: %s", trace_array(supp_entry->addr.eui_64, 8)); return; } - // Delete KMP - ws_pae_lib_kmp_list_delete(&supp_entry->kmp_list, api); } } diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_controller.c b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_controller.c index 086ec063936..11e2c455cb3 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_controller.c +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_controller.c @@ -100,6 +100,7 @@ typedef struct { typedef struct { uint16_t node_limit; /**< Max number of stored supplicants */ bool node_limit_set : 1; /**< Node limit set */ + bool ext_cert_valid_enabled : 1; /**< Extended certificate validation enabled */ } pae_controller_config_t; static pae_controller_t *ws_pae_controller_get(protocol_interface_info_entry_t *interface_ptr); @@ -126,7 +127,8 @@ static NS_LIST_DEFINE(pae_controller_list, pae_controller_t, link); pae_controller_config_t pae_controller_config = { .node_limit = 0, - .node_limit_set = false + .node_limit_set = false, + .ext_cert_valid_enabled = false }; #if !defined(HAVE_PAE_SUPP) && !defined(HAVE_PAE_AUTH) @@ -482,9 +484,12 @@ static void ws_pae_controller_nw_key_index_check_and_set(protocol_interface_info controller->gtk_index = index; uint32_t frame_counter = ws_pae_controller_frame_counter_get(&controller->stored_frame_counter, index, controller->nw_key[index].hash); - controller->nw_frame_counter_set(interface_ptr, frame_counter); + if (frame_counter) { + controller->nw_frame_counter_set(interface_ptr, frame_counter); + } tr_info("NW frame counter set: %"PRIu32"", frame_counter); ws_pae_controller_frame_counter_write(controller, index, controller->nw_key[index].hash, frame_counter); + } // Do not update PAN version for initial key index set @@ -511,9 +516,12 @@ static void ws_pae_controller_active_nw_key_set(protocol_interface_info_entry_t // If index has changed and the key for the index is fresh get frame counter if (controller->gtk_index != index && controller->nw_key[index].fresh) { uint32_t frame_counter = ws_pae_controller_frame_counter_get(&controller->stored_frame_counter, index, controller->nw_key[index].hash); - controller->nw_frame_counter_set(cur, frame_counter); + if (frame_counter) { + controller->nw_frame_counter_set(cur, frame_counter); + } tr_info("NW frame counter set: %"PRIu32"", frame_counter); ws_pae_controller_frame_counter_write(controller, index, controller->nw_key[index].hash, frame_counter); + } controller->gtk_index = index; @@ -586,6 +594,7 @@ static void ws_pae_controller_data_init(pae_controller_t *controller) sec_prot_keys_gtks_init(&controller->gtks); sec_prot_keys_gtks_init(&controller->next_gtks); sec_prot_certs_init(&controller->certs); + sec_prot_certs_ext_certificate_validation_set(&controller->certs, pae_controller_config.ext_cert_valid_enabled); ws_pae_timers_settings_init(&controller->timer_settings); } @@ -695,6 +704,9 @@ int8_t ws_pae_controller_stop(protocol_interface_info_entry_t *interface_ptr) // Stores frame counter ws_pae_controller_frame_counter_store(controller); + // Removes network keys from PAE controller and MAC + ws_pae_controller_nw_keys_remove(interface_ptr); + // If PAE has been initialized, deletes it if (controller->pae_delete) { controller->pae_delete(interface_ptr); @@ -764,6 +776,46 @@ int8_t ws_pae_controller_certificate_chain_set(const arm_certificate_chain_entry } } } + + // Updates the length of own certificates + entry->certs.own_cert_chain_len = sec_prot_certs_cert_chain_entry_len_get(&entry->certs.own_cert_chain); + } + + return 0; +} + +int8_t ws_pae_controller_own_certificate_add(const arm_certificate_entry_s *cert) +{ + if (!cert) { + return -1; + } + + int8_t ret = -1; + + ns_list_foreach(pae_controller_t, entry, &pae_controller_list) { + for (uint8_t i = 0; i < SEC_PROT_CERT_CHAIN_DEPTH; i++) { + if (entry->certs.own_cert_chain.cert[i] == NULL) { + sec_prot_certs_cert_set(&entry->certs.own_cert_chain, i, (uint8_t *) cert->cert, cert->cert_len); + // Set private key if set for the certificate that is added + if (cert->key && cert->key_len > 0) { + sec_prot_certs_priv_key_set(&entry->certs.own_cert_chain, (uint8_t *) cert->key, cert->key_len); + } + ret = 0; + break; + } + } + // Updates the length of own certificates + entry->certs.own_cert_chain_len = sec_prot_certs_cert_chain_entry_len_get(&entry->certs.own_cert_chain); + } + + return ret; +} + +int8_t ws_pae_controller_own_certificates_remove(void) +{ + ns_list_foreach(pae_controller_t, entry, &pae_controller_list) { + sec_prot_certs_chain_entry_init(&entry->certs.own_cert_chain); + entry->certs.own_cert_chain_len = 0; } return 0; @@ -816,6 +868,15 @@ int8_t ws_pae_controller_trusted_certificate_remove(const arm_certificate_entry_ return ret; } +int8_t ws_pae_controller_trusted_certificates_remove(void) +{ + ns_list_foreach(pae_controller_t, entry, &pae_controller_list) { + sec_prot_certs_chain_list_delete(&entry->certs.trusted_cert_chain_list); + } + + return 0; +} + int8_t ws_pae_controller_certificate_revocation_list_add(const arm_cert_revocation_list_entry_s *crl) { if (!crl) { @@ -1051,6 +1112,26 @@ int8_t ws_pae_controller_node_limit_set(int8_t interface_id, uint16_t limit) #endif } +int8_t ws_pae_controller_ext_certificate_validation_set(int8_t interface_id, bool enabled) +{ +#ifdef HAVE_PAE_AUTH + pae_controller_config.ext_cert_valid_enabled = enabled; + + pae_controller_t *controller = ws_pae_controller_get_or_create(interface_id); + if (!controller) { + return -1; + } + + sec_prot_certs_ext_certificate_validation_set(&controller->certs, enabled); + + return 0; +#else + (void) interface_id; + (void) enabled; + return -1; +#endif +} + void ws_pae_controller_forced_gc(bool full_gc) { /* Purge only when on critical limit since node limit should handle limiting diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_controller.h b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_controller.h index b34a61ae374..717ca112585 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_controller.h +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_controller.h @@ -158,6 +158,26 @@ int8_t ws_pae_controller_timing_adjust(uint8_t timing); */ int8_t ws_pae_controller_certificate_chain_set(const arm_certificate_chain_entry_s *chain); +/** + * ws_pae_controller_own_certificate_add add own certificate to certificate chain + * + * \param cert own certificate + * + * \return < 0 failure + * \return >= 0 success + * + */ +int8_t ws_pae_controller_own_certificate_add(const arm_certificate_entry_s *cert); + +/** + * ws_pae_controller_own_certificates_remove removes own certificates + * + * \return < 0 failure + * \return >= 0 success + * + */ +int8_t ws_pae_controller_own_certificates_remove(void); + /** * ws_pae_controller_trusted_certificate_add add trusted certificate * @@ -180,6 +200,15 @@ int8_t ws_pae_controller_trusted_certificate_add(const arm_certificate_entry_s * */ int8_t ws_pae_controller_trusted_certificate_remove(const arm_certificate_entry_s *cert); +/** + * ws_pae_controller_trusted_certificates_remove removes trusted certificates + * + * \return < 0 failure + * \return >= 0 success + * + */ +int8_t ws_pae_controller_trusted_certificates_remove(void); + /** * ws_pae_controller_certificate_revocation_list_add add certification revocation list * @@ -338,6 +367,18 @@ int8_t ws_pae_controller_node_access_revoke_start(int8_t interface_id); */ int8_t ws_pae_controller_node_limit_set(int8_t interface_id, uint16_t limit); +/** + * ws_pae_controller_ext_certificate_validation_set enable or disable extended certificate validation + * + * \param interface_ptr interface + * \param enabled true to enable extended validation, false to disable + * + * \return < 0 failure + * \return >= 0 success + * + */ +int8_t ws_pae_controller_ext_certificate_validation_set(int8_t interface_id, bool enabled); + /** * ws_pae_controller_active_key_update update active key (test interface) * diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_lib.c b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_lib.c index d01917d955a..d27c63b0550 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_lib.c +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_lib.c @@ -76,13 +76,21 @@ int8_t ws_pae_lib_kmp_list_delete(kmp_list_t *kmp_list, kmp_api_t *kmp) kmp_api_t *ws_pae_lib_kmp_list_type_get(kmp_list_t *kmp_list, kmp_type_e type) { + kmp_api_t *kmp = NULL; + ns_list_foreach(kmp_entry_t, cur, kmp_list) { + // If kmp type matches if (kmp_api_type_get(cur->kmp) == type) { - return cur->kmp; + /* If receiving of messages has not been disabled for the kmp (kmp is not + in terminating phase) prioritizes that kmp */ + if (!kmp_api_receive_disable(cur->kmp)) { + return cur->kmp; + } + // Otherwise returns any kmp that matches + kmp = cur->kmp; } } - - return 0; + return kmp; } void ws_pae_lib_kmp_list_free(kmp_list_t *kmp_list) diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_supp.c b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_supp.c index ae7abe7a0d5..6d22e3e9a87 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_supp.c +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/ws/ws_pae_supp.c @@ -588,6 +588,7 @@ int8_t ws_pae_supp_init(protocol_interface_info_entry_t *interface_ptr, const se pae_supp->timer_running = false; pae_supp->new_br_eui_64_set = false; pae_supp->new_br_eui_64_fresh = false; + pae_supp->entry_address_active = false; ws_pae_lib_supp_init(&pae_supp->entry); @@ -1010,7 +1011,13 @@ static kmp_api_t *ws_pae_supp_kmp_incoming_ind(kmp_service_t *service, kmp_type_ // Check if ongoing kmp_api_t *kmp = ws_pae_lib_kmp_list_type_get(&pae_supp->entry.kmp_list, type); - if (kmp) { + /* If kmp receiving is enabled or it is not GKH, routes message to existing KMP. + + For GKH creates an instance to handle message. If message is not valid (e.g. repeated + message counter), GKH ignores message and waits for timeout. All further messages + are routed to that instance. If valid message arrives, GKH instance handles the + message, replies to authenticator and terminates. */ + if (kmp && (!kmp_api_receive_disable(kmp) || type != IEEE_802_11_GKH)) { return kmp; } diff --git a/features/nanostack/sal-stack-nanostack/source/Common_Protocols/icmpv6.c b/features/nanostack/sal-stack-nanostack/source/Common_Protocols/icmpv6.c index a1cb4042e8d..d842055a9f0 100644 --- a/features/nanostack/sal-stack-nanostack/source/Common_Protocols/icmpv6.c +++ b/features/nanostack/sal-stack-nanostack/source/Common_Protocols/icmpv6.c @@ -1388,6 +1388,9 @@ static void icmpv6_aro_cb(buffer_t *buf, uint8_t status) ll_address[8] ^= 2; } rpl_control_address_register_done(buf->interface, ll_address, status); + if (status != SOCKET_TX_DONE) { + ws_common_aro_failure(buf->interface, ll_address); + } } buffer_t *icmpv6_build_ns(protocol_interface_info_entry_t *cur, const uint8_t target_addr[16], const uint8_t *prompting_src_addr, bool unicast, bool unspecified_source, const aro_t *aro) @@ -1603,8 +1606,6 @@ buffer_t *icmpv6_build_na(protocol_interface_info_entry_t *cur, bool solicited, uint8_t *ptr; uint8_t flags; - tr_debug("Build NA"); - /* Check if ARO response and status == success, then sending can be omitted with flag */ if (aro && cur->ipv6_neighbour_cache.omit_na_aro_success && aro->status == ARO_SUCCESS) { tr_debug("Omit NA ARO success"); @@ -1712,6 +1713,8 @@ buffer_t *icmpv6_build_na(protocol_interface_info_entry_t *cur, bool solicited, buf->info = (buffer_info_t)(B_DIR_DOWN | B_FROM_ICMP | B_TO_ICMP); buf->interface = cur; + tr_debug("Build NA"); + return (buf); } diff --git a/features/nanostack/sal-stack-nanostack/source/Common_Protocols/udp.c b/features/nanostack/sal-stack-nanostack/source/Common_Protocols/udp.c index a232e6762c6..0159f450d1b 100644 --- a/features/nanostack/sal-stack-nanostack/source/Common_Protocols/udp.c +++ b/features/nanostack/sal-stack-nanostack/source/Common_Protocols/udp.c @@ -146,12 +146,7 @@ buffer_t *udp_up(buffer_t *buf) if (buf->dst_sa.port == UDP_PORT_ECHO && buf->src_sa.port != UDP_PORT_ECHO) { protocol_interface_info_entry_t *cur; - tr_debug("UDP echo msg [%"PRIi16"]: %s%s", - buffer_data_length(buf), - trace_array( - buffer_data_pointer(buf), - (buffer_data_length(buf) > 64 ? 64 : buffer_data_length(buf))), - (buffer_data_length(buf) > 64 ? "..." : "")); + tr_debug("UDP echo msg from %s", trace_ipv6(buf->src_sa.address)); cur = buf->interface; diff --git a/features/nanostack/sal-stack-nanostack/source/DHCPv6_client/dhcpv6_client_service.c b/features/nanostack/sal-stack-nanostack/source/DHCPv6_client/dhcpv6_client_service.c index ed5ffede381..af57e49c5c6 100644 --- a/features/nanostack/sal-stack-nanostack/source/DHCPv6_client/dhcpv6_client_service.c +++ b/features/nanostack/sal-stack-nanostack/source/DHCPv6_client/dhcpv6_client_service.c @@ -111,7 +111,7 @@ void dhcp_client_delete(int8_t interface) if (srv_data_ptr != NULL) { tr_debug("Free DHCPv6 Client\n"); memcpy(temporary_address, srv_data_ptr->iaNontemporalAddress.addressPrefix, 16); - dhcp_service_req_remove(srv_data_ptr->transActionId);// remove all pending retransmissions + dhcp_service_req_remove_all(srv_data_ptr);// remove all pending retransmissions libdhcvp6_nontemporalAddress_server_data_free(srv_data_ptr); addr_delete(cur, temporary_address); @@ -144,13 +144,18 @@ int dhcp_solicit_resp_cb(uint16_t instance_id, void *ptr, uint8_t msg_name, uin dhcpv6_client_server_data_t *srv_data_ptr = NULL; (void)instance_id; - srv_data_ptr = ptr; + //Validate that started TR ID class is still at list + srv_data_ptr = libdhcpv6_nonTemporal_validate_class_pointer(ptr); + if (srv_data_ptr == NULL) { tr_error("server data not found"); goto error_exit; } + //Clear Active Transaction state + srv_data_ptr->transActionId = 0; + // Validate message if (msg_name != DHCPV6_REPLY_TYPE) { tr_error("invalid response"); @@ -158,7 +163,7 @@ int dhcp_solicit_resp_cb(uint16_t instance_id, void *ptr, uint8_t msg_name, uin } if (libdhcpv6_reply_message_option_validate(&clientId, &serverId, &dhcp_ia_non_temporal_params, msg_ptr, msg_len) != 0) { - tr_error("Sol Not include all Options"); + tr_error("Reply Not include all Options"); goto error_exit; } @@ -330,7 +335,7 @@ int dhcp_client_server_address_update(int8_t interface, uint8_t *prefix, uint8_t } memcpy(srv_data_ptr->server_address, server_address, 16); - if (!srv_data_ptr->iaNonTemporalStructValid) { + if (srv_data_ptr->transActionId) { dhcp_service_update_server_address(srv_data_ptr->transActionId, server_address); } return 0; @@ -357,7 +362,7 @@ void dhcp_client_global_address_delete(int8_t interface, uint8_t *dhcp_addr, uin return; } - dhcp_service_req_remove(srv_data_ptr->transActionId);// remove all pending retransmissions + dhcp_service_req_remove_all(srv_data_ptr);// remove all pending retransmissions if (dhcp_client.one_instance_interface) { addr_deprecate(cur, srv_data_ptr->iaNontemporalAddress.addressPrefix); } else { @@ -384,7 +389,7 @@ void dhcpv6_renew(protocol_interface_info_entry_t *interface, if_address_entry_t return; } if (reason == ADDR_CALLBACK_INVALIDATED) { - dhcp_service_req_remove(srv_data_ptr->transActionId);//stop retransmissions of renew + dhcp_service_req_remove_all(srv_data_ptr);// remove all pending retransmissions libdhcvp6_nontemporalAddress_server_data_free(srv_data_ptr); tr_warn("Dhcp address lost"); return; @@ -394,6 +399,12 @@ void dhcpv6_renew(protocol_interface_info_entry_t *interface, if_address_entry_t return; } + if (srv_data_ptr->transActionId) { + //Do not trig new Renew process + tr_warn("Do not trig new pending renew request"); + return; + } + payload_len = libdhcpv6_address_request_message_len(srv_data_ptr->clientLinkIdType, srv_data_ptr->serverLinkType, 0, !dhcp_client.no_address_hint); payload_ptr = ns_dyn_mem_temporary_alloc(payload_len); if (payload_ptr == NULL) { diff --git a/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_defines.h b/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_defines.h index 25a18844a4d..119c2c2efa7 100644 --- a/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_defines.h +++ b/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_defines.h @@ -148,24 +148,19 @@ typedef struct mac_mcps_data_conf_fail_s { typedef struct protocol_interface_rf_mac_setup { int8_t mac_interface_id; - bool macUpState; + bool macUpState: 1; bool shortAdressValid: 1; //Define Dynamic src address to mac16 when it is true bool beaconSrcAddressModeLong: 1; //This force beacon src to mac64 otherwise shortAdressValid will define type + bool secFrameCounterPerKey: 1; bool mac_extension_enabled: 1; bool mac_ack_tx_active: 1; bool mac_frame_pending: 1; - uint16_t mac_short_address; - uint16_t pan_id; - uint8_t mac64[8]; - uint16_t coord_short_address; - uint8_t coord_long_address[8]; /* MAC Capability Information */ bool macCapRxOnIdle: 1; bool macCapCordinator: 1; bool macCapAssocationPermit: 1; bool macCapBatteryPowered: 1; bool macCapSecrutityCapability: 1; - bool macProminousMode: 1; bool macGTSPermit: 1; bool mac_security_enabled: 1; @@ -173,7 +168,6 @@ typedef struct protocol_interface_rf_mac_setup { bool mac_security_bypass_unknow_device: 1; /* Load balancing need this feature */ bool macAcceptAnyBeacon: 1; - /* TX process Flag */ bool macTxProcessActive: 1; bool macTxRequestAck: 1; @@ -188,6 +182,12 @@ typedef struct protocol_interface_rf_mac_setup { bool scan_active: 1; bool rf_csma_extension_supported: 1; bool ack_tx_possible: 1; + uint16_t mac_short_address; + uint16_t pan_id; + uint8_t mac64[8]; + uint16_t coord_short_address; + uint8_t coord_long_address[8]; + /* CSMA Params */ unsigned macMinBE: 4; unsigned macMaxBE: 4; @@ -200,7 +200,6 @@ typedef struct protocol_interface_rf_mac_setup { uint8_t scan_duration; //Needed??? mac_scan_type_t scan_type; - uint8_t mac_channel; //uint8_t cca_failure; @@ -253,6 +252,7 @@ typedef struct protocol_interface_rf_mac_setup { struct mlme_device_descriptor_s *device_description_table; uint8_t device_description_table_size; struct mlme_key_descriptor_s *key_description_table; + void *key_device_frame_counter_list_buffer; uint8_t key_description_table_size; uint8_t key_lookup_list_size; uint8_t key_usage_list_size; diff --git a/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mcps_sap.c b/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mcps_sap.c index 687325955a7..74c30b16b31 100644 --- a/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mcps_sap.c +++ b/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mcps_sap.c @@ -90,6 +90,14 @@ uint32_t mac_mcps_sap_get_phy_timestamp(protocol_interface_rf_mac_setup_s *rf_ma return timestamp; } +static bool mac_data_counter_too_small(uint32_t current_counter, uint32_t packet_counter) +{ + if ((current_counter - packet_counter) >= 2) { + return true; + } + return false; +} + static bool mac_data_request_confirmation_finnish(protocol_interface_rf_mac_setup_s *rf_mac_setup, mac_pre_build_frame_t *buffer) { if (!buffer->asynch_request) { @@ -583,10 +591,14 @@ static uint8_t mac_data_interface_decrypt_packet(mac_pre_parsed_frame_t *b, mlme return MLME_UNAVAILABLE_KEY; } - if (b->neigh_info && neighbour_validation.frameCounter < b->neigh_info->FrameCounter) { - tr_debug("MLME_COUNTER_ERROR"); - return MLME_COUNTER_ERROR; + if (b->neigh_info) { + uint32_t min_accepted_frame_counter = mac_mib_key_device_frame_counter_get(key_description, b->neigh_info, device_descriptor_handle); + if (neighbour_validation.frameCounter < min_accepted_frame_counter) { + tr_debug("MLME_COUNTER_ERROR"); + return MLME_COUNTER_ERROR; + } } + } key = key_description->Key; @@ -620,10 +632,15 @@ static uint8_t mac_data_interface_decrypt_packet(mac_pre_parsed_frame_t *b, mlme //Update key device and key description tables if (!security_by_pass) { - b->neigh_info->FrameCounter = neighbour_validation.frameCounter + 1; + + mac_sec_mib_key_device_frame_counter_set(key_description, b->neigh_info, neighbour_validation.frameCounter + 1, device_descriptor_handle); + if (!key_device_description) { - // Black list old used keys by this device - mac_sec_mib_device_description_blacklist(rf_mac_setup, device_descriptor_handle); + if (!rf_mac_setup->secFrameCounterPerKey) { + // Black list old used keys by this device + mac_sec_mib_device_description_blacklist(rf_mac_setup, device_descriptor_handle); + } + key_device_description = mac_sec_mib_key_device_description_list_update(key_description); if (key_device_description) { tr_debug("Set new device user %u for key", device_descriptor_handle); @@ -1199,6 +1216,7 @@ mac_pre_build_frame_t *mcps_sap_prebuild_frame_buffer_get(uint16_t payload_size) return NULL; } memset(buffer, 0, sizeof(mac_pre_build_frame_t)); + buffer->aux_header.frameCounter = 0xffffffff; if (payload_size) { //Mac interlnal payload allocate buffer->mac_payload = ns_dyn_mem_temporary_alloc(payload_size); @@ -1229,7 +1247,7 @@ void mcps_sap_prebuild_frame_buffer_free(mac_pre_build_frame_t *buffer) } -static bool mac_frame_security_parameters_init(ccm_globals_t *ccm_ptr, protocol_interface_rf_mac_setup_s *rf_ptr, mac_pre_build_frame_t *buffer) +static mlme_key_descriptor_t *mac_frame_security_key_get(protocol_interface_rf_mac_setup_s *rf_ptr, mac_pre_build_frame_t *buffer) { /* Encrypt the packet payload if AES encyption bit is set */ mlme_security_t key_source; @@ -1237,13 +1255,13 @@ static bool mac_frame_security_parameters_init(ccm_globals_t *ccm_ptr, protocol_ key_source.KeyIndex = buffer->aux_header.KeyIndex; key_source.SecurityLevel = buffer->aux_header.securityLevel; memcpy(key_source.Keysource, buffer->aux_header.Keysource, 8); - mlme_key_descriptor_t *key_description = mac_sec_key_description_get(rf_ptr, &key_source, buffer->fcf_dsn.DstAddrMode, buffer->DstAddr, buffer->DstPANId); + return mac_sec_key_description_get(rf_ptr, &key_source, buffer->fcf_dsn.DstAddrMode, buffer->DstAddr, buffer->DstPANId); +} - if (!key_description) { - buffer->status = MLME_UNAVAILABLE_KEY; - return false; - } +static bool mac_frame_security_parameters_init(ccm_globals_t *ccm_ptr, protocol_interface_rf_mac_setup_s *rf_ptr, mac_pre_build_frame_t *buffer, mlme_key_descriptor_t *key_description) +{ + /* Encrypt the packet payload if AES encyption bit is set */ mlme_device_descriptor_t *device_description; uint8_t *nonce_ext_64_ptr; @@ -1298,6 +1316,7 @@ static void mac_common_data_confirmation_handle(protocol_interface_rf_mac_setup_ timer_mac_stop(rf_mac_setup); if (m_event == MAC_CCA_FAIL) { sw_mac_stats_update(rf_mac_setup, STAT_MAC_TX_CCA_FAIL, 0); + tr_debug("MAC CCA fail"); /* CCA fail */ //rf_mac_setup->cca_failure++; buf->status = MLME_BUSY_CHAN; @@ -1305,7 +1324,7 @@ static void mac_common_data_confirmation_handle(protocol_interface_rf_mac_setup_ sw_mac_stats_update(rf_mac_setup, STAT_MAC_TX_COUNT, buf->mac_payload_length); if (m_event == MAC_TX_FAIL) { sw_mac_stats_update(rf_mac_setup, STAT_MAC_TX_FAIL, 0); - tr_error("MAC tx fail"); + tr_debug("MAC tx fail"); buf->status = MLME_TX_NO_ACK; } else if (m_event == MAC_TX_DONE) { if (mac_is_ack_request_set(buf) == false) { @@ -1517,16 +1536,31 @@ static int8_t mcps_generic_packet_build(protocol_interface_rf_mac_setup_s *rf_pt mac_header_information_elements_preparation(buffer); mcps_generic_sequence_number_allocate(rf_ptr, buffer); - + mlme_key_descriptor_t *key_desc; if (buffer->fcf_dsn.securityEnabled) { + bool increment_framecounter = false; //Remember to update security counter here! - buffer->aux_header.frameCounter = mac_mlme_framecounter_get(rf_ptr); - if (!mac_frame_security_parameters_init(&ccm_ptr, rf_ptr, buffer)) { + key_desc = mac_frame_security_key_get(rf_ptr, buffer); + if (!key_desc) { + buffer->status = MLME_UNAVAILABLE_KEY; return -2; } - //Increment security counter - mac_mlme_framecounter_increment(rf_ptr); + //GET Counter + uint32_t new_frameCounter = mac_sec_mib_key_outgoing_frame_counter_get(rf_ptr, key_desc); + // If buffer frame counter is set, this is FHSS channel retry, update frame counter only if something was sent after failure + if ((buffer->aux_header.frameCounter == 0xffffffff) || buffer->asynch_request || mac_data_counter_too_small(new_frameCounter, buffer->aux_header.frameCounter)) { + buffer->aux_header.frameCounter = new_frameCounter; + increment_framecounter = true; + } + + if (!mac_frame_security_parameters_init(&ccm_ptr, rf_ptr, buffer, key_desc)) { + return -2; + } + //Increment security counter + if (increment_framecounter) { + mac_sec_mib_key_outgoing_frame_counter_increment(rf_ptr, key_desc); + } } //Calculate Payload length here with IE extension @@ -1559,7 +1593,9 @@ static int8_t mcps_generic_packet_build(protocol_interface_rf_mac_setup_s *rf_pt tr_debug("Too Long %u, %u pa %u header %u mic %u", frame_length, mac_payload_length, buffer->mac_header_length_with_security, buffer->security_mic_len, dev_driver->phy_MTU); buffer->status = MLME_FRAME_TOO_LONG; //decrement security counter - mac_mlme_framecounter_decrement(rf_ptr); + if (buffer->fcf_dsn.securityEnabled) { + mac_sec_mib_key_outgoing_frame_counter_decrement(rf_ptr, key_desc); + } return -1; } @@ -1673,19 +1709,24 @@ int8_t mcps_generic_ack_build(protocol_interface_rf_mac_setup_s *rf_ptr, bool in ccm_globals_t ccm_ptr; mac_pre_build_frame_t *buffer = &rf_ptr->enhanced_ack_buffer; - + mlme_key_descriptor_t *key_desc; if (buffer->fcf_dsn.securityEnabled) { //Remember to update security counter here! + key_desc = mac_frame_security_key_get(rf_ptr, buffer); + if (!key_desc) { + buffer->status = MLME_UNAVAILABLE_KEY; + return -2; + } if (init_build) { - buffer->aux_header.frameCounter = mac_mlme_framecounter_get(rf_ptr); + buffer->aux_header.frameCounter = mac_sec_mib_key_outgoing_frame_counter_get(rf_ptr, key_desc); } - if (!mac_frame_security_parameters_init(&ccm_ptr, rf_ptr, buffer)) { + if (!mac_frame_security_parameters_init(&ccm_ptr, rf_ptr, buffer, key_desc)) { return -2; } if (init_build) { //Increment security counter - mac_mlme_framecounter_increment(rf_ptr); + mac_sec_mib_key_outgoing_frame_counter_increment(rf_ptr, key_desc); } } @@ -1709,7 +1750,7 @@ int8_t mcps_generic_ack_build(protocol_interface_rf_mac_setup_s *rf_ptr, bool in if (buffer->fcf_dsn.securityEnabled) { //decrement security counter - mac_mlme_framecounter_decrement(rf_ptr); + mac_sec_mib_key_outgoing_frame_counter_decrement(rf_ptr, key_desc); ccm_free(&ccm_ptr); } return -1; @@ -1770,7 +1811,14 @@ static int8_t mcps_generic_packet_rebuild(protocol_interface_rf_mac_setup_s *rf_ } if (buffer->fcf_dsn.securityEnabled) { - if (!mac_frame_security_parameters_init(&ccm_ptr, rf_ptr, buffer)) { + + mlme_key_descriptor_t *key_desc = mac_frame_security_key_get(rf_ptr, buffer); + if (!key_desc) { + buffer->status = MLME_UNAVAILABLE_KEY; + return -2; + } + + if (!mac_frame_security_parameters_init(&ccm_ptr, rf_ptr, buffer, key_desc)) { return -2; } } @@ -2318,3 +2366,17 @@ int mcps_packet_ingress_rate_limit_by_memory(uint8_t free_heap_percentage) return -1; } + +void mcps_pending_packet_counter_update_check(protocol_interface_rf_mac_setup_s *rf_mac_setup, mac_pre_build_frame_t *buffer) +{ + if (buffer->fcf_dsn.securityEnabled) { + mlme_key_descriptor_t *key_desc = mac_frame_security_key_get(rf_mac_setup, buffer); + if (key_desc) { + uint32_t current_counter = mac_sec_mib_key_outgoing_frame_counter_get(rf_mac_setup, key_desc); + if (mac_data_counter_too_small(current_counter, buffer->aux_header.frameCounter)) { + buffer->aux_header.frameCounter = current_counter; + mac_sec_mib_key_outgoing_frame_counter_increment(rf_mac_setup, key_desc); + } + } + } +} diff --git a/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mcps_sap.h b/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mcps_sap.h index 90a0cbf7383..de61fe8b91b 100644 --- a/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mcps_sap.h +++ b/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mcps_sap.h @@ -140,4 +140,6 @@ int mcps_packet_ingress_rate_limit_by_memory(uint8_t free_heap_percentage); uint32_t mac_mcps_sap_get_phy_timestamp(struct protocol_interface_rf_mac_setup *rf_mac_setup); +void mcps_pending_packet_counter_update_check(struct protocol_interface_rf_mac_setup *rf_mac_setup, mac_pre_build_frame_t *buffer); + #endif /* MAC_IEEE802_15_4_MAC_MCPS_SAP_H_ */ diff --git a/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mlme.c b/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mlme.c index 70dc179df58..d0925f97f88 100644 --- a/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mlme.c +++ b/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mlme.c @@ -606,15 +606,21 @@ static int8_t mac_mlme_8bit_set(protocol_interface_rf_mac_setup_s *rf_mac_setup, return 0; } -static int8_t mac_mlme_32bit_set(protocol_interface_rf_mac_setup_s *rf_mac_setup, mlme_attr_t attribute, uint32_t value) +static int8_t mac_mlme_32bit_set(protocol_interface_rf_mac_setup_s *rf_mac_setup, mlme_attr_t attribute, uint8_t index, uint32_t value) { - (void)rf_mac_setup; - (void) value; + switch (attribute) { case macFrameCounter: - platform_enter_critical(); - rf_mac_setup->security_frame_counter = value; - platform_exit_critical(); + if (rf_mac_setup->secFrameCounterPerKey) { + mlme_key_descriptor_t *key_desc = mac_sec_key_description_get_by_attribute(rf_mac_setup, index); + if (!key_desc) { + return -1; + } + mac_sec_mib_key_outgoing_frame_counter_set(rf_mac_setup, key_desc, value); + } else { + mac_sec_mib_key_outgoing_frame_counter_set(rf_mac_setup, NULL, value); + } + break; default: @@ -718,7 +724,7 @@ static int8_t mac_mlme_handle_set_values(protocol_interface_rf_mac_setup_s *rf_m return mac_mlme_16bit_set(rf_mac_setup, set_req->attr, *pu16); } else if (set_req->value_size == 4) { const uint32_t *pu32 = set_req->value_pointer; - return mac_mlme_32bit_set(rf_mac_setup, set_req->attr, *pu32); + return mac_mlme_32bit_set(rf_mac_setup, set_req->attr, set_req->attr_index, *pu32); } return -1; } @@ -787,30 +793,6 @@ int8_t mac_mlme_set_req(protocol_interface_rf_mac_setup_s *rf_mac_setup, const m } } -uint32_t mac_mlme_framecounter_get(struct protocol_interface_rf_mac_setup *rf_mac_setup) -{ - uint32_t value; - platform_enter_critical(); - value = rf_mac_setup->security_frame_counter; - platform_exit_critical(); - return value; -} - -void mac_mlme_framecounter_increment(struct protocol_interface_rf_mac_setup *rf_mac_setup) -{ - platform_enter_critical(); - rf_mac_setup->security_frame_counter++; - platform_exit_critical(); -} - -void mac_mlme_framecounter_decrement(struct protocol_interface_rf_mac_setup *rf_mac_setup) -{ - platform_enter_critical(); - rf_mac_setup->security_frame_counter--; - platform_exit_critical(); -} - - int8_t mac_mlme_get_req(struct protocol_interface_rf_mac_setup *rf_mac_setup, mlme_get_conf_t *get_req) { if (!get_req || !rf_mac_setup) { @@ -833,9 +815,16 @@ int8_t mac_mlme_get_req(struct protocol_interface_rf_mac_setup *rf_mac_setup, ml break; case macFrameCounter: - platform_enter_critical(); - get_req->value_pointer = &rf_mac_setup->security_frame_counter; - platform_exit_critical(); + if (rf_mac_setup->secFrameCounterPerKey) { + mlme_key_descriptor_t *key_desc = mac_sec_key_description_get_by_attribute(rf_mac_setup, get_req->attr_index); + if (!key_desc) { + return -1; + } + get_req->value_pointer = &key_desc->KeyFrameCounter; + } else { + get_req->value_pointer = &rf_mac_setup->security_frame_counter; + } + get_req->value_size = 4; break; @@ -1344,8 +1333,6 @@ int mac_mlme_beacon_notify(protocol_interface_rf_mac_setup_s *rf_mac_setup, mlme mac->mlme_ind_cb(mac, MLME_BEACON_NOTIFY, data); } - tr_debug("Beacon Notify: %s", trace_array(data->beacon_data, data->beacon_data_length)); - if (rf_mac_setup->mac_mlme_scan_resp) { mlme_scan_conf_t *conf = rf_mac_setup->mac_mlme_scan_resp; update_beacon = add_or_update_beacon(conf, data, rf_mac_setup->fhss_api); diff --git a/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mlme.h b/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mlme.h index 76e0c0c3f5a..fb251c80009 100644 --- a/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mlme.h +++ b/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_mlme.h @@ -65,11 +65,6 @@ int8_t mac_mlme_get_req(struct protocol_interface_rf_mac_setup *rf_mac_setup, st void mac_extended_mac_set(struct protocol_interface_rf_mac_setup *rf_mac_setup, const uint8_t *mac64); -uint32_t mac_mlme_framecounter_get(struct protocol_interface_rf_mac_setup *rf_mac_setup); - -void mac_mlme_framecounter_increment(struct protocol_interface_rf_mac_setup *rf_mac_setup); -void mac_mlme_framecounter_decrement(struct protocol_interface_rf_mac_setup *rf_mac_setup); - /** * MLME Poll Request * diff --git a/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_pd_sap.c b/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_pd_sap.c index d938de1a43a..1e0a09865f8 100644 --- a/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_pd_sap.c +++ b/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_pd_sap.c @@ -387,14 +387,6 @@ static void mac_sap_no_ack_cb(protocol_interface_rf_mac_setup_s *rf_ptr) } } -static bool mac_data_counter_too_small(uint32_t current_counter, uint32_t packet_counter) -{ - if ((current_counter - packet_counter) >= 2) { - return true; - } - return false; -} - static bool mac_data_asynch_channel_switch(protocol_interface_rf_mac_setup_s *rf_ptr, mac_pre_build_frame_t *active_buf) { @@ -420,13 +412,7 @@ static void mac_data_ack_tx_finish(protocol_interface_rf_mac_setup_s *rf_ptr) } if (rf_ptr->active_pd_data_request) { - if (rf_ptr->active_pd_data_request->fcf_dsn.securityEnabled) { - uint32_t current_counter = mac_mlme_framecounter_get(rf_ptr); - if (mac_data_counter_too_small(current_counter, rf_ptr->active_pd_data_request->aux_header.frameCounter)) { - rf_ptr->active_pd_data_request->aux_header.frameCounter = current_counter; - mac_mlme_framecounter_increment(rf_ptr); - } - } + mcps_pending_packet_counter_update_check(rf_ptr, rf_ptr->active_pd_data_request); //GEN TX failure mac_sap_cca_fail_cb(rf_ptr); } diff --git a/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_security_mib.c b/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_security_mib.c index e009d042561..b023c32cdf8 100644 --- a/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_security_mib.c +++ b/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_security_mib.c @@ -19,6 +19,7 @@ #include "ns_types.h" #include "ns_trace.h" #include "nsdynmemLIB.h" +#include "platform/arm_hal_interrupt.h" #include "mac_api.h" #include "sw_mac.h" #include "mac_common_defines.h" @@ -78,6 +79,42 @@ static mlme_key_id_lookup_descriptor_t *mac_sec_mib_key_lookup_table_allocate(ui return table_ptr; } +static int mac_sec_mib_frame_counter_key_buffer_allocate(protocol_interface_rf_mac_setup_s *rf_mac_setup, uint16_t list_size, uint16_t device_count) +{ + rf_mac_setup->key_device_frame_counter_list_buffer = ns_dyn_mem_alloc(sizeof(uint32_t) * list_size * device_count); + if (!rf_mac_setup->key_device_frame_counter_list_buffer) { + return -1; + } + memset(rf_mac_setup->key_device_frame_counter_list_buffer, 0, (sizeof(uint32_t) * list_size * device_count)); + rf_mac_setup->secFrameCounterPerKey = true; + mlme_key_descriptor_t *key_descriptor_list = rf_mac_setup->key_description_table; + uint32_t *frame_counter_pointer = rf_mac_setup->key_device_frame_counter_list_buffer; + for (uint8_t i = 0; i < rf_mac_setup->key_description_table_size; i++) { + key_descriptor_list->KeyDeviceFrameCouterList = frame_counter_pointer; + key_descriptor_list->KeyFrameCounterPerKey = true; + key_descriptor_list->KeyFrameCounter = 0; + //Update Pointers + key_descriptor_list++; + frame_counter_pointer += device_count; + } + + return 0; +} + +static void mac_sec_mib_frame_counter_key_buffer_free(protocol_interface_rf_mac_setup_s *rf_mac_setup) +{ + mlme_key_descriptor_t *key_descriptor_list = rf_mac_setup->key_description_table; + for (uint8_t i = 0; i < rf_mac_setup->key_description_table_size; i++) { + key_descriptor_list->KeyDeviceFrameCouterList = NULL; + key_descriptor_list->KeyFrameCounterPerKey = false; + //Update Pointers + key_descriptor_list++; + } + ns_dyn_mem_free(rf_mac_setup->key_device_frame_counter_list_buffer); + rf_mac_setup->key_device_frame_counter_list_buffer = NULL; + rf_mac_setup->secFrameCounterPerKey = false; +} + static mlme_device_descriptor_t *mac_sec_mib_device_description_get_by_mac16(protocol_interface_rf_mac_setup_s *rf_mac_setup, uint16_t mac16) { @@ -134,6 +171,11 @@ static void mac_sec_mib_key_device_description_remove_from_list(mlme_key_descrip if (removed_entry) { key_descpription_table->KeyDeviceListEntries--; + //Clear Also frame counter per key if it its enabled + if (key_descpription_table->KeyFrameCounterPerKey) { + //SET frame counter to 0 + mac_sec_mib_key_device_frame_counter_set(key_descpription_table, NULL, 0, device_descriptor_handle); + } } } @@ -234,7 +276,6 @@ int8_t mac_sec_mib_device_description_set(uint8_t atribute_index, mlme_device_de //validate index to list size if (!rf_mac_setup || !device_descriptor || atribute_index >= rf_mac_setup->device_description_table_size) { - tr_debug("Too many Devices"); return -1; } @@ -302,6 +343,17 @@ int8_t mac_sec_mib_key_description_set(uint8_t atribute_index, mlme_key_descript memcpy(key_ptr->KeyUsageList, key_descriptor->KeyUsageList, sizeof(mlme_key_usage_descriptor_t) * key_ptr->KeyUsageListEntries); } + if (key_ptr->KeyFrameCounterPerKey) { + key_ptr->KeyFrameCounter = 0; + if (key_ptr->KeyDeviceListEntries == 0) { + //Clear all frame counters from old possible user's + uint32_t *counter_ptr = key_ptr->KeyDeviceFrameCouterList; + for (int i = 0; i < rf_mac_setup->device_description_table_size; i++) { + *counter_ptr++ = 0; + } + } + } + return 0; } @@ -414,6 +466,17 @@ mlme_key_descriptor_t *mac_sec_key_description_get(protocol_interface_rf_mac_set return NULL; } +mlme_key_descriptor_t *mac_sec_key_description_get_by_attribute(protocol_interface_rf_mac_setup_s *rf_mac_setup, uint8_t atribute_index) +{ + //validate index to list size + if (atribute_index >= rf_mac_setup->key_description_table_size) { + return NULL; + } + + + return rf_mac_setup->key_description_table + atribute_index; +} + int8_t mac_sec_mib_init(protocol_interface_rf_mac_setup_s *rf_mac_setup, mac_description_storage_size_t *storage_sizes) { @@ -434,16 +497,102 @@ int8_t mac_sec_mib_init(protocol_interface_rf_mac_setup_s *rf_mac_setup, mac_des return 0; } + +int8_t mac_sec_mib_frame_counter_per_key_set(protocol_interface_rf_mac_setup_s *rf_mac_setup, bool enabled) +{ + if (enabled) { + if (rf_mac_setup->key_device_frame_counter_list_buffer) { + return 0; + } + return mac_sec_mib_frame_counter_key_buffer_allocate(rf_mac_setup, rf_mac_setup->key_description_table_size, rf_mac_setup->device_description_table_size); + } + + //Clear Key Descriptors + + //Free current list + mac_sec_mib_frame_counter_key_buffer_free(rf_mac_setup); + return 0; +} + + void mac_sec_mib_deinit(protocol_interface_rf_mac_setup_s *rf_mac_setup) { if (!rf_mac_setup) { return; } + mac_sec_mib_frame_counter_key_buffer_free(rf_mac_setup); mac_sec_mib_device_description_table_deinit(rf_mac_setup); mac_sec_mib_key_description_table_deinit(rf_mac_setup); } +uint32_t mac_sec_mib_key_outgoing_frame_counter_get(protocol_interface_rf_mac_setup_s *rf_mac_setup, mlme_key_descriptor_t *key_descpription) +{ + uint32_t value; + platform_enter_critical(); + if (key_descpription && key_descpription->KeyFrameCounterPerKey) { + value = key_descpription->KeyFrameCounter; + } else { + value = rf_mac_setup->security_frame_counter; + } + platform_exit_critical(); + return value; +} + +void mac_sec_mib_key_outgoing_frame_counter_set(protocol_interface_rf_mac_setup_s *rf_mac_setup, mlme_key_descriptor_t *key_descpription, uint32_t value) +{ + platform_enter_critical(); + if (key_descpription && key_descpription->KeyFrameCounterPerKey) { + key_descpription->KeyFrameCounter = value; + } else { + rf_mac_setup->security_frame_counter = value; + } + platform_exit_critical(); +} + +void mac_sec_mib_key_outgoing_frame_counter_increment(struct protocol_interface_rf_mac_setup *rf_mac_setup, mlme_key_descriptor_t *key_descpription) +{ + platform_enter_critical(); + if (key_descpription && key_descpription->KeyFrameCounterPerKey) { + key_descpription->KeyFrameCounter++; + } else { + rf_mac_setup->security_frame_counter++; + } + platform_exit_critical(); +} + +void mac_sec_mib_key_outgoing_frame_counter_decrement(struct protocol_interface_rf_mac_setup *rf_mac_setup, mlme_key_descriptor_t *key_descpription) +{ + platform_enter_critical(); + if (key_descpription && key_descpription->KeyFrameCounterPerKey) { + key_descpription->KeyFrameCounter--; + } else { + rf_mac_setup->security_frame_counter--; + } + platform_exit_critical(); +} + + +void mac_sec_mib_key_device_frame_counter_set(mlme_key_descriptor_t *key_descpription_table, mlme_device_descriptor_t *device_info, uint32_t frame_counter, uint8_t attribute_index) +{ + if (key_descpription_table->KeyFrameCounterPerKey) { + uint32_t *counter_ptr = key_descpription_table->KeyDeviceFrameCouterList + attribute_index; + *counter_ptr = frame_counter; + } else { + device_info->FrameCounter = frame_counter; + } +} + +uint32_t mac_mib_key_device_frame_counter_get(mlme_key_descriptor_t *key_descpription_table, mlme_device_descriptor_t *device_info, uint8_t attribute_index) +{ + if (key_descpription_table->KeyFrameCounterPerKey) { + uint32_t *counter_ptr = key_descpription_table->KeyDeviceFrameCouterList + attribute_index; + return *counter_ptr; + } + return device_info->FrameCounter; +} + + //allocate new entry and update entries size mlme_key_device_descriptor_t *mac_sec_mib_key_device_description_list_update(mlme_key_descriptor_t *key_descpription_table) { @@ -477,7 +626,6 @@ mlme_key_device_descriptor_t *mac_sec_mib_key_device_description_discover_from_l void mac_sec_mib_device_description_blacklist(protocol_interface_rf_mac_setup_s *rf_mac_setup, uint8_t device_handle) { - if (!rf_mac_setup) { return; } @@ -485,7 +633,6 @@ void mac_sec_mib_device_description_blacklist(protocol_interface_rf_mac_setup_s for (uint8_t i = 0; i < rf_mac_setup->key_description_table_size; i++) { descriptor = mac_sec_mib_key_device_description_discover_from_list(&rf_mac_setup->key_description_table[i], device_handle); if (descriptor) { - tr_debug("Black listed device %u", device_handle); descriptor->Blacklisted = true; } diff --git a/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_security_mib.h b/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_security_mib.h index 05be16d572e..9ca75cd5b85 100644 --- a/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_security_mib.h +++ b/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/mac_security_mib.h @@ -25,21 +25,26 @@ struct mac_description_storage_size_s; typedef struct mlme_key_descriptor_s { mlme_key_id_lookup_descriptor_t *KeyIdLookupList; - uint8_t KeyIdLookupListEntries; mlme_key_device_descriptor_t *KeyDeviceList; + mlme_key_usage_descriptor_t *KeyUsageList; + uint32_t *KeyDeviceFrameCouterList; + uint32_t KeyFrameCounter; + uint8_t Key[16]; uint8_t KeyDeviceListSize; uint8_t KeyDeviceListEntries; - mlme_key_usage_descriptor_t *KeyUsageList; + uint8_t KeyIdLookupListEntries; uint8_t KeyUsageListEntries; uint8_t KeyUsageListSize; - uint8_t Key[16]; - bool unique_key_descriptor; + bool unique_key_descriptor: 1; + bool KeyFrameCounterPerKey: 1; } mlme_key_descriptor_t; int8_t mac_sec_mib_init(struct protocol_interface_rf_mac_setup *rf_mac_setup, struct mac_description_storage_size_s *storage_sizes); void mac_sec_mib_deinit(struct protocol_interface_rf_mac_setup *rf_mac_setup); +int8_t mac_sec_mib_frame_counter_per_key_set(struct protocol_interface_rf_mac_setup *rf_mac_setup, bool enabled); + int8_t mac_sec_mib_device_description_set(uint8_t atribute_index, mlme_device_descriptor_t *device_descriptor, struct protocol_interface_rf_mac_setup *rf_mac_setup); int8_t mac_sec_mib_key_description_set(uint8_t atribute_index, mlme_key_descriptor_entry_t *key_descriptor, struct protocol_interface_rf_mac_setup *rf_mac_setup); @@ -52,10 +57,24 @@ uint8_t mac_mib_device_descption_attribute_get_by_descriptor(struct protocol_int mlme_key_descriptor_t *mac_sec_key_description_get(struct protocol_interface_rf_mac_setup *rf_mac_setup, mlme_security_t *key_source, uint8_t address_mode, uint8_t *address_ptr, uint16_t pan_id); +mlme_key_descriptor_t *mac_sec_key_description_get_by_attribute(struct protocol_interface_rf_mac_setup *rf_mac_setup, uint8_t atribute_index); + mlme_key_device_descriptor_t *mac_sec_mib_key_device_description_list_update(mlme_key_descriptor_t *key_descpription_table); mlme_key_device_descriptor_t *mac_sec_mib_key_device_description_discover_from_list(mlme_key_descriptor_t *key_descpription_table, uint8_t device_descriptor_handle); void mac_sec_mib_device_description_blacklist(struct protocol_interface_rf_mac_setup *rf_mac_setup, uint8_t device_handle); +void mac_sec_mib_key_device_frame_counter_set(mlme_key_descriptor_t *key_descpription_table, mlme_device_descriptor_t *device_info, uint32_t frame_counter, uint8_t attribute_index); + +uint32_t mac_mib_key_device_frame_counter_get(mlme_key_descriptor_t *key_descpription_table, mlme_device_descriptor_t *device_info, uint8_t attribute_index); + +uint32_t mac_sec_mib_key_outgoing_frame_counter_get(struct protocol_interface_rf_mac_setup *rf_mac_setup, mlme_key_descriptor_t *key_descpription); + +void mac_sec_mib_key_outgoing_frame_counter_set(struct protocol_interface_rf_mac_setup *rf_mac_setup, mlme_key_descriptor_t *key_descpription, uint32_t value); + +void mac_sec_mib_key_outgoing_frame_counter_increment(struct protocol_interface_rf_mac_setup *rf_mac_setup, mlme_key_descriptor_t *key_descpription); + +void mac_sec_mib_key_outgoing_frame_counter_decrement(struct protocol_interface_rf_mac_setup *rf_mac_setup, mlme_key_descriptor_t *key_descpription); + #endif /* MAC_SECURITY_MIB_H_ */ diff --git a/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/sw_mac.c b/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/sw_mac.c index 7c40766f930..ca52231bac2 100644 --- a/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/sw_mac.c +++ b/features/nanostack/sal-stack-nanostack/source/MAC/IEEE802_15_4/sw_mac.c @@ -25,6 +25,7 @@ #include "MAC/IEEE802_15_4/mac_defines.h" #include "MAC/IEEE802_15_4/mac_mcps_sap.h" #include "MAC/IEEE802_15_4/mac_pd_sap.h" +#include "MAC/IEEE802_15_4/mac_security_mib.h" #include "MAC/rf_driver_storage.h" #include "MAC/virtual_rf/virtual_rf_defines.h" #include "mac_fhss_callbacks.h" @@ -123,6 +124,14 @@ mac_api_t *ns_sw_mac_create(int8_t rf_driver_id, mac_description_storage_size_t return this; } +int8_t ns_sw_mac_enable_frame_counter_per_key(struct mac_api_s *mac_api_s, bool enable_feature) +{ + if (!mac_api_s || mac_api_s != mac_store.mac_api) { + return -1; + } + return mac_sec_mib_frame_counter_per_key_set(mac_store.setup, enable_feature); +} + int8_t ns_sw_mac_virtual_client_register(mac_api_t *api, int8_t virtual_driver_id) { if (!api || api != mac_store.mac_api) { diff --git a/features/nanostack/sal-stack-nanostack/source/RPL/rpl_control.c b/features/nanostack/sal-stack-nanostack/source/RPL/rpl_control.c index f176350b9e7..c6854e3f4e0 100644 --- a/features/nanostack/sal-stack-nanostack/source/RPL/rpl_control.c +++ b/features/nanostack/sal-stack-nanostack/source/RPL/rpl_control.c @@ -176,6 +176,21 @@ void rpl_control_request_parent_link_confirmation(bool requested) rpl_policy_set_parent_confirmation_request(requested); } +void rpl_control_set_dio_multicast_min_config_advertisment_count(uint8_t min_count) +{ + rpl_policy_set_dio_multicast_config_advertisment_min_count(min_count); +} + +void rpl_control_set_dao_retry_count(uint8_t count) +{ + rpl_policy_set_dao_retry_count(count); +} + +void rpl_control_set_initial_dao_ack_wait(uint16_t timeout_in_ms) +{ + rpl_policy_set_initial_dao_ack_wait(timeout_in_ms); +} + /* Send address registration to either specified address, or to non-registered address */ void rpl_control_register_address(protocol_interface_info_entry_t *interface, const uint8_t addr[16]) { @@ -340,16 +355,24 @@ void rpl_control_delete_domain(rpl_domain_t *domain) rpl_free(domain, sizeof * domain); } -static void rpl_control_remove_interface_from_domain(protocol_interface_info_entry_t *cur, rpl_domain_t *domain) +static void rpl_control_remove_interface_from_domain(protocol_interface_info_entry_t *cur, rpl_domain_t *domain, bool free_instances) { ns_list_foreach(rpl_instance_t, instance, &domain->instances) { rpl_instance_remove_interface(instance, cur->id); } + ns_list_foreach(if_address_entry_t, addr, &cur->ip_addresses) { if (!addr_is_ipv6_link_local(addr->address)) { rpl_control_unpublish_address(domain, addr->address); } } + + if (free_instances) { + ns_list_foreach_safe(rpl_instance_t, instance, &domain->instances) { + rpl_delete_instance(instance); + } + } + if (domain->non_storing_downstream_interface == cur->id) { domain->non_storing_downstream_interface = -1; } @@ -374,7 +397,16 @@ void rpl_control_set_domain_on_interface(protocol_interface_info_entry_t *cur, r void rpl_control_remove_domain_from_interface(protocol_interface_info_entry_t *cur) { if (cur->rpl_domain) { - rpl_control_remove_interface_from_domain(cur, cur->rpl_domain); + rpl_control_remove_interface_from_domain(cur, cur->rpl_domain, false); + addr_delete_group(cur, ADDR_LINK_LOCAL_ALL_RPL_NODES); + cur->rpl_domain = NULL; + } +} + +void rpl_control_free_domain_instances_from_interface(protocol_interface_info_entry_t *cur) +{ + if (cur->rpl_domain) { + rpl_control_remove_interface_from_domain(cur, cur->rpl_domain, true); addr_delete_group(cur, ADDR_LINK_LOCAL_ALL_RPL_NODES); cur->rpl_domain = NULL; } @@ -1368,6 +1400,7 @@ void rpl_control_transmit_dis(rpl_domain_t *domain, protocol_interface_info_entr buffer_data_end_set(buf, ptr); rpl_control_transmit(domain, cur, ICMPV6_CODE_RPL_DIS, buf, dst); + tr_info("Transmit DIS"); } #ifdef HAVE_RPL_DAO_HANDLING diff --git a/features/nanostack/sal-stack-nanostack/source/RPL/rpl_control.h b/features/nanostack/sal-stack-nanostack/source/RPL/rpl_control.h index c9c1d7f176f..17290fddc0b 100644 --- a/features/nanostack/sal-stack-nanostack/source/RPL/rpl_control.h +++ b/features/nanostack/sal-stack-nanostack/source/RPL/rpl_control.h @@ -145,6 +145,7 @@ rpl_domain_t *rpl_control_create_domain(void); void rpl_control_delete_domain(rpl_domain_t *domain); void rpl_control_set_domain_on_interface(struct protocol_interface_info_entry *cur, rpl_domain_t *domain, bool downstream); void rpl_control_remove_domain_from_interface(struct protocol_interface_info_entry *cur); +void rpl_control_free_domain_instances_from_interface(struct protocol_interface_info_entry *cur); void rpl_control_set_callback(rpl_domain_t *domain, rpl_domain_callback_t callback, rpl_prefix_callback_t prefix_learn_cb, rpl_new_parent_callback_t new_parent_add, void *cb_handle); /* Target publishing */ @@ -156,6 +157,9 @@ uint16_t rpl_control_parent_candidate_list_size(struct protocol_interface_info_e void rpl_control_neighbor_delete(struct protocol_interface_info_entry *interface, const uint8_t ll_addr[16]); /* Parent link confirmation API extension */ void rpl_control_request_parent_link_confirmation(bool requested); +void rpl_control_set_dio_multicast_min_config_advertisment_count(uint8_t min_count); +void rpl_control_set_dao_retry_count(uint8_t count); +void rpl_control_set_initial_dao_ack_wait(uint16_t timeout_in_ms); void rpl_control_register_address(struct protocol_interface_info_entry *interface, const uint8_t addr[16]); void rpl_control_address_register_done(struct protocol_interface_info_entry *interface, const uint8_t ll_addr[16], uint8_t status); @@ -178,6 +182,7 @@ uint16_t rpl_control_current_rank(const struct rpl_instance *instance); #define rpl_control_fast_timer(ticks) ((void) 0) #define rpl_control_slow_timer(seconds) ((void) 0) #define rpl_control_remove_domain_from_interface(cur) ((void) 0) +#define rpl_control_free_domain_instances_from_interface(cur) ((void) 0) #define rpl_control_register_address(interface, addr) ((void) 0) #define rpl_control_address_register_done(interface, ll_addr, status) ((void) 0) diff --git a/features/nanostack/sal-stack-nanostack/source/RPL/rpl_downward.c b/features/nanostack/sal-stack-nanostack/source/RPL/rpl_downward.c index ad9cde193c7..188f144a45a 100644 --- a/features/nanostack/sal-stack-nanostack/source/RPL/rpl_downward.c +++ b/features/nanostack/sal-stack-nanostack/source/RPL/rpl_downward.c @@ -712,6 +712,21 @@ void rpl_instance_send_dao_update(rpl_instance_t *instance) return; } + if (rpl_policy_dao_retry_count() > 0 && instance->dao_attempt >= rpl_policy_dao_retry_count()) { + // Check if recovery logic is started + // after half the retries are done we remove the primary parent + tr_info("DAO remove primary parent"); + rpl_neighbour_t *neighbour = ns_list_get_first(&instance->candidate_neighbours); + if (neighbour) { + rpl_delete_neighbour(instance, neighbour); + } + // Set parameters to restart + instance->dao_in_transit = false; + instance->dao_attempt = 0; + instance->dao_retry_timer = 0; + instance->delay_dao_timer = 0; + return; + } /* Which parent this DAO will be for if storing */ rpl_neighbour_t *parent = NULL; @@ -847,6 +862,15 @@ void rpl_instance_send_dao_update(rpl_instance_t *instance) cur = NULL; } + if (instance->dao_attempt > 0) { + // Start informing problem in routing. This will cause us to select secondary routes when sending the DAO + tr_info("DAO reachability problem"); + protocol_interface_info_entry_t *interface = protocol_stack_interface_info_get_by_rpl_domain(instance->domain, -1); + if (interface) { + ipv6_neighbour_reachability_problem(dst, interface->id); + } + } + bool need_ack = rpl_control_transmit_dao(instance->domain, cur, instance, instance->id, instance->dao_sequence, dodag->id, opts, ptr - opts, dst); ns_dyn_mem_free(opts); @@ -1859,7 +1883,7 @@ void rpl_instance_address_registration_done(protocol_interface_info_entry_t *int if (status == SOCKET_TX_DONE) { /* State_timer is 1/10 s. Set renewal to 75-85% of lifetime */ if_address_entry_t *address = rpl_interface_addr_get(interface, dao_target->prefix); - if (address) { + if (address && address->source != ADDR_SOURCE_DHCP) { address->state_timer = (address->preferred_lifetime * randLIB_get_random_in_range(75, 85) / 10); } neighbour->confirmed = true; diff --git a/features/nanostack/sal-stack-nanostack/source/RPL/rpl_policy.c b/features/nanostack/sal-stack-nanostack/source/RPL/rpl_policy.c index 30488983339..ec581c8bb42 100644 --- a/features/nanostack/sal-stack-nanostack/source/RPL/rpl_policy.c +++ b/features/nanostack/sal-stack-nanostack/source/RPL/rpl_policy.c @@ -35,6 +35,11 @@ #define TRACE_GROUP "RPLy" static bool rpl_policy_parent_confirmation_req = false; +static int8_t rpl_policy_dao_retry_count_conf = 0; +static int16_t rpl_policy_dao_initial_timeout_conf = 20; // Default is 2 seconds 100ms ticks +static uint16_t rpl_policy_dio_validity_period_hysteresis = 0x0180; //Fixed Point 1.5 +static uint8_t rpl_policy_multicast_config_min_advertisment_count = 0; + /* TODO - application API to control when to join new instances / DODAGs * @@ -105,6 +110,11 @@ bool rpl_policy_request_dao_acks(const rpl_domain_t *domain, uint8_t mop) return true; } +void rpl_policy_set_initial_dao_ack_wait(uint16_t timeout_in_ms) +{ + rpl_policy_dao_initial_timeout_conf = timeout_in_ms; +} + uint16_t rpl_policy_initial_dao_ack_wait(const rpl_domain_t *domain, uint8_t mop) { (void)mop; @@ -120,7 +130,18 @@ uint16_t rpl_policy_initial_dao_ack_wait(const rpl_domain_t *domain, uint8_t mop } } - return 20; /* *100ms ticks = 2s */ + return rpl_policy_dao_initial_timeout_conf; +} + + +void rpl_policy_set_dao_retry_count(uint8_t count) +{ + rpl_policy_dao_retry_count_conf = count; +} + +int8_t rpl_policy_dao_retry_count() +{ + return rpl_policy_dao_retry_count_conf; } /* Given the next-hop address from a source routing header, which interface, @@ -192,6 +213,20 @@ uint16_t rpl_policy_etx_hysteresis(rpl_domain_t *domain) return 0x0080; /* 8.8 fixed-point, so 0.5 */ } +uint16_t rpl_policy_dio_validity_period(rpl_domain_t *domain) +{ + (void)domain; + + return rpl_policy_dio_validity_period_hysteresis; /* Fixed Point */ +} + +void rpl_policy_set_dio_validity_period(rpl_domain_t *domain, uint16_t fixed_point) +{ + (void)domain; + + rpl_policy_dio_validity_period_hysteresis = fixed_point; /* Fixed Point */ +} + uint16_t rpl_policy_etx_change_parent_selection_delay(rpl_domain_t *domain) { (void)domain; @@ -331,6 +366,16 @@ bool rpl_policy_parent_confirmation_requested(void) return rpl_policy_parent_confirmation_req; } +uint8_t rpl_policy_dio_multicast_config_advertisment_min_count(void) +{ + return rpl_policy_multicast_config_min_advertisment_count; +} + +void rpl_policy_set_dio_multicast_config_advertisment_min_count(uint8_t min_count) +{ + rpl_policy_multicast_config_min_advertisment_count = min_count; +} + #ifdef RPL_STRUCTURES_H_ #error "rpl_structures.h should not be included by rpl_policy.c" diff --git a/features/nanostack/sal-stack-nanostack/source/RPL/rpl_policy.h b/features/nanostack/sal-stack-nanostack/source/RPL/rpl_policy.h index dc1094e5cd5..c51adc81cd1 100644 --- a/features/nanostack/sal-stack-nanostack/source/RPL/rpl_policy.h +++ b/features/nanostack/sal-stack-nanostack/source/RPL/rpl_policy.h @@ -27,11 +27,20 @@ bool rpl_policy_join_config(rpl_domain_t *domain, const rpl_dodag_conf_t *conf, bool rpl_policy_request_dao_acks(const rpl_domain_t *domain, uint8_t mop); uint16_t rpl_policy_initial_dao_ack_wait(const rpl_domain_t *domain, uint8_t mop); +void rpl_policy_set_initial_dao_ack_wait(uint16_t timeout_in_ms); + +void rpl_policy_set_dao_retry_count(uint8_t count); +int8_t rpl_policy_dao_retry_count(); + int8_t rpl_policy_srh_next_hop_interface(rpl_domain_t *domain, int8_t if_id, const uint8_t *next_hop); uint16_t rpl_policy_modify_downward_cost_to_root_neighbour(rpl_domain_t *domain, int8_t if_id, const uint8_t *next_hop, uint16_t cost); uint16_t rpl_policy_parent_selection_period(rpl_domain_t *domain); uint16_t rpl_policy_etx_hysteresis(rpl_domain_t *domain); +//Return Fixed point multiple which base 1.0 is 0x0100 +uint16_t rpl_policy_dio_validity_period(rpl_domain_t *domain); +//Fixed point must 1.0 is 0x0100 +void rpl_policy_set_dio_validity_period(rpl_domain_t *domain, uint16_t fixed_point); uint16_t rpl_policy_etx_change_parent_selection_delay(rpl_domain_t *domain); uint16_t rpl_policy_dio_parent_selection_delay(rpl_domain_t *domain); @@ -56,5 +65,7 @@ uint16_t rpl_policy_mrhof_parent_switch_threshold(const rpl_domain_t *domain); uint16_t rpl_policy_mrhof_max_rank_stretch_for_extra_parents(const rpl_domain_t *domain); bool rpl_policy_parent_confirmation_requested(void); void rpl_policy_set_parent_confirmation_request(bool confirmation_requested); +uint8_t rpl_policy_dio_multicast_config_advertisment_min_count(void); +void rpl_policy_set_dio_multicast_config_advertisment_min_count(uint8_t min_count); #endif /* RPL_POLICY_H_ */ diff --git a/features/nanostack/sal-stack-nanostack/source/RPL/rpl_structures.h b/features/nanostack/sal-stack-nanostack/source/RPL/rpl_structures.h index 107ff9b6eb9..1d4dcc0c377 100644 --- a/features/nanostack/sal-stack-nanostack/source/RPL/rpl_structures.h +++ b/features/nanostack/sal-stack-nanostack/source/RPL/rpl_structures.h @@ -90,6 +90,7 @@ struct rpl_dodag { bool leaf: 1; /* We are a leaf in this DODAG (by policy) */ bool have_config: 1; /* We have the config */ bool used: 1; /* We have ever been a member of this DODAG? */ + uint8_t new_config_advertisment_count; /* We have advertiment new config at multicasti DIO */ NS_LIST_HEAD(rpl_dodag_version_t, link) versions; /* List of DODAG versions (newest first) */ prefix_list_t prefixes; /* Prefixes advertised in DIO PIOs */ rpl_dio_route_list_t routes; /* Routes advertised in DIO RIOs*/ diff --git a/features/nanostack/sal-stack-nanostack/source/RPL/rpl_upward.c b/features/nanostack/sal-stack-nanostack/source/RPL/rpl_upward.c index cdee6bec908..4bd186d3699 100644 --- a/features/nanostack/sal-stack-nanostack/source/RPL/rpl_upward.c +++ b/features/nanostack/sal-stack-nanostack/source/RPL/rpl_upward.c @@ -635,6 +635,7 @@ rpl_dodag_t *rpl_create_dodag(rpl_instance_t *instance, const uint8_t *dodagid, dodag->have_config = false; dodag->used = false; dodag->g_mop_prf = g_mop_prf; + dodag->new_config_advertisment_count = 0; // Default timer parameters and trickle start should never normally // be used - we would set the parameters from the DODAG Config and start // as we join a version. But initialising here catches odd cases where @@ -728,6 +729,7 @@ bool rpl_dodag_update_config(rpl_dodag_t *dodag, const rpl_dodag_conf_t *conf, c /* They've changed the timing parameters for our currently-in-use trickle timer! */ tr_warn("Trickle parameters changed"); trickle_start(&dodag->instance->dio_timer, &dodag->dio_timer_params); + dodag->new_config_advertisment_count = 0; } dodag->instance->of = rpl_objective_lookup(conf->objective_code_point); /* We could be a leaf of an unknown OCP. Still need an OF to choose parents */ @@ -1355,6 +1357,11 @@ static void trace_info_print(const char *fmt, ...) va_end(ap); } +static uint32_t rpl_dio_imax_time_calculate(uint16_t Imax, uint16_t fixed_point) +{ + return (((uint32_t)Imax * fixed_point) / 0x0100); +} + void rpl_instance_run_parent_selection(rpl_instance_t *instance) { @@ -1438,6 +1445,15 @@ void rpl_instance_run_parent_selection(rpl_instance_t *instance) if (preferred_parent) { // Always stop repair if we find a parent rpl_instance_set_local_repair(instance, false); + //Validate time from last DIO + + uint32_t time_between_parent = protocol_core_monotonic_time - preferred_parent->dio_timestamp; + uint32_t accepted_time = rpl_dio_imax_time_calculate(instance->current_dodag_version->dodag->dio_timer_params.Imax, rpl_policy_dio_validity_period(instance->domain)); + + if (accepted_time < time_between_parent) { + rpl_control_transmit_dis(instance->domain, NULL, RPL_SOLINFO_PRED_INSTANCEID, instance->id, NULL, 0, preferred_parent->ll_address); + } + } else if (original_preferred) { // Only start repair if we just lost a parent rpl_instance_set_local_repair(instance, true); @@ -1533,7 +1549,15 @@ void rpl_instance_dio_trigger(rpl_instance_t *instance, protocol_interface_info_ } // Always send config in unicasts (as required), never in multicasts (optional) - rpl_dodag_conf_t *conf = addr ? &dodag->config : NULL; + rpl_dodag_conf_t *conf; + if (addr) { + conf = &dodag->config; + } else if (dodag->new_config_advertisment_count < rpl_policy_dio_multicast_config_advertisment_min_count()) { + conf = &dodag->config; + dodag->new_config_advertisment_count++; + } else { + conf = NULL; + } rpl_control_transmit_dio(instance->domain, cur, instance->id, dodag_version->number, rank, dodag->g_mop_prf, instance->dtsn, dodag, dodag->id, conf, addr); @@ -1921,7 +1945,7 @@ bool rpl_upward_accept_prefix_update(const rpl_dodag_t *dodag_info, const rpl_ne //Calculate Time between from last dio from parent and this neighbour //neighbour dio_timestamp >= pref_parent's, because it's a newly-received message uint32_t time_between_parent = neighbour->dio_timestamp - pref_parent->dio_timestamp; - uint32_t accepted_time = (uint32_t)dodag_info->dio_timer_params.Imax * 2; + uint32_t accepted_time = rpl_dio_imax_time_calculate(dodag_info->dio_timer_params.Imax, 0x0200); //Accept prefix Update If Time from last DIO is more than 2 x Max if (accepted_time < time_between_parent) { return true; diff --git a/features/nanostack/sal-stack-nanostack/source/Security/kmp/kmp_api.c b/features/nanostack/sal-stack-nanostack/source/Security/kmp/kmp_api.c index 35d541f1565..3ca8bc2e6a4 100644 --- a/features/nanostack/sal-stack-nanostack/source/Security/kmp/kmp_api.c +++ b/features/nanostack/sal-stack-nanostack/source/Security/kmp/kmp_api.c @@ -314,6 +314,11 @@ kmp_type_e kmp_api_type_get(kmp_api_t *kmp) return kmp->type; } +bool kmp_api_receive_disable(kmp_api_t *kmp) +{ + return kmp->receive_disable; +} + kmp_type_e kmp_api_type_from_id_get(uint8_t kmp_id) { switch (kmp_id) { diff --git a/features/nanostack/sal-stack-nanostack/source/Security/kmp/kmp_api.h b/features/nanostack/sal-stack-nanostack/source/Security/kmp/kmp_api.h index cb19ec168db..c690aa9ec91 100644 --- a/features/nanostack/sal-stack-nanostack/source/Security/kmp/kmp_api.h +++ b/features/nanostack/sal-stack-nanostack/source/Security/kmp/kmp_api.h @@ -152,6 +152,16 @@ void kmp_api_delete(kmp_api_t *kmp); */ kmp_type_e kmp_api_type_get(kmp_api_t *kmp); +/** + * kmp_api_type_get get receive disabled status + * + * \param kmp instance + * + * \return true/false true when receiving has been disabled + * + */ +bool kmp_api_receive_disable(kmp_api_t *kmp); + /** * kmp_api_type_from_id_get get KMP type from KMP id * diff --git a/features/nanostack/sal-stack-nanostack/source/Security/protocols/eap_tls_sec_prot/auth_eap_tls_sec_prot.c b/features/nanostack/sal-stack-nanostack/source/Security/protocols/eap_tls_sec_prot/auth_eap_tls_sec_prot.c index 3e1c1c7fb67..40a5c2eccda 100644 --- a/features/nanostack/sal-stack-nanostack/source/Security/protocols/eap_tls_sec_prot/auth_eap_tls_sec_prot.c +++ b/features/nanostack/sal-stack-nanostack/source/Security/protocols/eap_tls_sec_prot/auth_eap_tls_sec_prot.c @@ -98,7 +98,7 @@ static int8_t auth_eap_tls_sec_prot_message_handle(sec_prot_t *prot); static int8_t auth_eap_tls_sec_prot_message_send(sec_prot_t *prot, uint8_t eap_code, uint8_t eap_type, uint8_t tls_state); static void auth_eap_tls_sec_prot_timer_timeout(sec_prot_t *prot, uint16_t ticks); -static void auth_eap_tls_sec_prot_init_tls(sec_prot_t *prot); +static int8_t auth_eap_tls_sec_prot_init_tls(sec_prot_t *prot); static void auth_eap_tls_sec_prot_delete_tls(sec_prot_t *prot); static void auth_eap_tls_sec_prot_seq_id_update(sec_prot_t *prot); @@ -348,16 +348,16 @@ static int8_t auth_eap_tls_sec_prot_tls_send(sec_prot_t *tls_prot, void *pdu, ui return 0; } -static void auth_eap_tls_sec_prot_init_tls(sec_prot_t *prot) +static int8_t auth_eap_tls_sec_prot_init_tls(sec_prot_t *prot) { eap_tls_sec_prot_int_t *data = eap_tls_sec_prot_get(prot); if (data->tls_prot) { - return; + return 0; } data->tls_prot = prot->type_get(prot, SEC_PROT_TYPE_TLS); if (!data->tls_prot) { - return; + return -1; } data->tls_prot->header_size = TLS_HEAD_LEN; @@ -369,6 +369,8 @@ static void auth_eap_tls_sec_prot_init_tls(sec_prot_t *prot) data->tls_prot->send = auth_eap_tls_sec_prot_tls_send; data->tls_ongoing = true; + + return 0; } static void auth_eap_tls_sec_prot_delete_tls(sec_prot_t *prot) @@ -388,14 +390,17 @@ static void auth_eap_tls_sec_prot_state_machine(sec_prot_t *prot) // EAP-TLS authenticator state machine switch (sec_prot_state_get(&data->common)) { case EAP_TLS_STATE_INIT: + tr_info("EAP-TLS init"); sec_prot_state_set(prot, &data->common, EAP_TLS_STATE_CREATE_REQ); + prot->timer_start(prot); break; // Wait KMP-CREATE.request case EAP_TLS_STATE_CREATE_REQ: tr_info("EAP-TLS start, eui-64: %s", trace_array(sec_prot_remote_eui_64_addr_get(prot), 8)); - prot->timer_start(prot); + // Set default timeout for the total maximum length of the negotiation + sec_prot_default_timeout_set(&data->common); // KMP-CREATE.confirm prot->create_conf(prot, SEC_RESULT_OK); @@ -469,8 +474,11 @@ static void auth_eap_tls_sec_prot_state_machine(sec_prot_t *prot) // All fragments received for a message if (result == EAP_TLS_MSG_RECEIVE_DONE) { - auth_eap_tls_sec_prot_init_tls(prot); - + // Initialize TLS protocol + if (auth_eap_tls_sec_prot_init_tls(prot) < 0) { + tr_error("TLS init failed"); + return; + } if (data->tls_ongoing) { // Call TLS data->tls_prot->receive(data->tls_prot, data->tls_recv.data, data->tls_recv.total_len); @@ -538,12 +546,14 @@ static void auth_eap_tls_sec_prot_state_machine(sec_prot_t *prot) sec_prot_state_set(prot, &data->common, EAP_TLS_STATE_FINISHED); break; - case EAP_TLS_STATE_FINISHED: + case EAP_TLS_STATE_FINISHED: { + uint8_t *remote_eui_64 = sec_prot_remote_eui_64_addr_get(prot); + tr_info("EAP-TLS finished, eui-64: %s", remote_eui_64 ? trace_array(sec_prot_remote_eui_64_addr_get(prot), 8) : "not set"); auth_eap_tls_sec_prot_delete_tls(prot); prot->timer_stop(prot); prot->finished(prot); break; - + } default: break; } diff --git a/features/nanostack/sal-stack-nanostack/source/Security/protocols/eap_tls_sec_prot/eap_tls_sec_prot_lib.c b/features/nanostack/sal-stack-nanostack/source/Security/protocols/eap_tls_sec_prot/eap_tls_sec_prot_lib.c index b3d4e870085..40e4b9ea0a8 100644 --- a/features/nanostack/sal-stack-nanostack/source/Security/protocols/eap_tls_sec_prot/eap_tls_sec_prot_lib.c +++ b/features/nanostack/sal-stack-nanostack/source/Security/protocols/eap_tls_sec_prot/eap_tls_sec_prot_lib.c @@ -59,6 +59,23 @@ int8_t eap_tls_sec_prot_lib_message_allocate(tls_data_t *data, uint8_t head_len, return 0; } +int8_t eap_tls_sec_prot_lib_message_realloc(tls_data_t *data, uint8_t head_len, uint16_t new_len) +{ + tls_data_t new_tls_send; + + eap_tls_sec_prot_lib_message_init(&new_tls_send); + if (eap_tls_sec_prot_lib_message_allocate(&new_tls_send, head_len, new_len) < 0) { + return -1; + } + memcpy(new_tls_send.data + head_len, data->data + head_len, data->handled_len); + new_tls_send.handled_len = data->handled_len; + eap_tls_sec_prot_lib_message_free(data); + + *data = new_tls_send; + + return 0; +} + void eap_tls_sec_prot_lib_message_free(tls_data_t *data) { ns_dyn_mem_free(data->data); diff --git a/features/nanostack/sal-stack-nanostack/source/Security/protocols/eap_tls_sec_prot/eap_tls_sec_prot_lib.h b/features/nanostack/sal-stack-nanostack/source/Security/protocols/eap_tls_sec_prot/eap_tls_sec_prot_lib.h index 0de960bb054..285e617d643 100644 --- a/features/nanostack/sal-stack-nanostack/source/Security/protocols/eap_tls_sec_prot/eap_tls_sec_prot_lib.h +++ b/features/nanostack/sal-stack-nanostack/source/Security/protocols/eap_tls_sec_prot/eap_tls_sec_prot_lib.h @@ -72,6 +72,19 @@ extern const uint8_t eap_msg_trace[4][10]; */ int8_t eap_tls_sec_prot_lib_message_allocate(tls_data_t *data, uint8_t head_len, uint16_t len); +/** + * eap_tls_sec_prot_lib_message_realloc allocates larger message buffer and copies existing data to it + * + * \param data data buffer which length is increased + * \param head_len header length + * \param new_len new length for the buffer + * + * \return < 0 failure + * \return >= 0 success + * + */ +int8_t eap_tls_sec_prot_lib_message_realloc(tls_data_t *data, uint8_t head_len, uint16_t new_len); + /** * eap_tls_sec_prot_lib_message_free free message buffer * diff --git a/features/nanostack/sal-stack-nanostack/source/Security/protocols/eap_tls_sec_prot/supp_eap_tls_sec_prot.c b/features/nanostack/sal-stack-nanostack/source/Security/protocols/eap_tls_sec_prot/supp_eap_tls_sec_prot.c index dadbdc17d33..8d73f22f38d 100644 --- a/features/nanostack/sal-stack-nanostack/source/Security/protocols/eap_tls_sec_prot/supp_eap_tls_sec_prot.c +++ b/features/nanostack/sal-stack-nanostack/source/Security/protocols/eap_tls_sec_prot/supp_eap_tls_sec_prot.c @@ -90,7 +90,7 @@ static int8_t supp_eap_tls_sec_prot_message_handle(sec_prot_t *prot); static int8_t supp_eap_tls_sec_prot_message_send(sec_prot_t *prot, uint8_t eap_code, uint8_t eap_type, uint8_t tls_state); static void supp_eap_tls_sec_prot_timer_timeout(sec_prot_t *prot, uint16_t ticks); -static void supp_eap_tls_sec_prot_init_tls(sec_prot_t *prot); +static int8_t supp_eap_tls_sec_prot_init_tls(sec_prot_t *prot); static void supp_eap_tls_sec_prot_delete_tls(sec_prot_t *prot); static void supp_eap_tls_sec_prot_seq_id_update(sec_prot_t *prot); @@ -360,16 +360,16 @@ static int8_t supp_eap_tls_sec_prot_tls_send(sec_prot_t *tls_prot, void *pdu, ui return 0; } -static void supp_eap_tls_sec_prot_init_tls(sec_prot_t *prot) +static int8_t supp_eap_tls_sec_prot_init_tls(sec_prot_t *prot) { eap_tls_sec_prot_int_t *data = eap_tls_sec_prot_get(prot); if (data->tls_prot) { - return; + return 0; } data->tls_prot = prot->type_get(prot, SEC_PROT_TYPE_TLS); if (!data->tls_prot) { - return; + return -1; } data->tls_prot->header_size = TLS_HEAD_LEN; @@ -381,6 +381,8 @@ static void supp_eap_tls_sec_prot_init_tls(sec_prot_t *prot) data->tls_prot->send = supp_eap_tls_sec_prot_tls_send; data->tls_ongoing = true; + + return 0; } static void supp_eap_tls_sec_prot_delete_tls(sec_prot_t *prot) @@ -400,7 +402,9 @@ static void supp_eap_tls_sec_prot_state_machine(sec_prot_t *prot) // EAP-TLS supplicant state machine switch (sec_prot_state_get(&data->common)) { case EAP_TLS_STATE_INIT: + tr_info("EAP-TLS init"); sec_prot_state_set(prot, &data->common, EAP_TLS_STATE_REQUEST_ID); + prot->timer_start(prot); break; // Wait EAP request, Identity (starts handshake on supplicant) @@ -411,13 +415,14 @@ static void supp_eap_tls_sec_prot_state_machine(sec_prot_t *prot) return; } + // Set default timeout for the total maximum length of the negotiation + sec_prot_default_timeout_set(&data->common); + // Store sequence ID supp_eap_tls_sec_prot_seq_id_update(prot); tr_info("EAP-TLS start"); - prot->timer_start(prot); - // Send KMP-CREATE.indication prot->create_ind(prot); sec_prot_state_set(prot, &data->common, EAP_TLS_STATE_CREATE_RESP); @@ -459,7 +464,10 @@ static void supp_eap_tls_sec_prot_state_machine(sec_prot_t *prot) data->common.ticks = retry_timeout; // Initialize TLS protocol - supp_eap_tls_sec_prot_init_tls(prot); + if (supp_eap_tls_sec_prot_init_tls(prot) < 0) { + tr_error("TLS init failed"); + return; + } // Request TLS to start (send client hello) data->tls_prot->create_req(data->tls_prot, prot->sec_keys); break; @@ -523,6 +531,7 @@ static void supp_eap_tls_sec_prot_state_machine(sec_prot_t *prot) break; case EAP_TLS_STATE_FINISHED: + tr_info("EAP-TLS finished"); supp_eap_tls_sec_prot_delete_tls(prot); prot->timer_stop(prot); prot->finished(prot); diff --git a/features/nanostack/sal-stack-nanostack/source/Security/protocols/fwh_sec_prot/auth_fwh_sec_prot.c b/features/nanostack/sal-stack-nanostack/source/Security/protocols/fwh_sec_prot/auth_fwh_sec_prot.c index ed91c306d60..5c0a48393d1 100644 --- a/features/nanostack/sal-stack-nanostack/source/Security/protocols/fwh_sec_prot/auth_fwh_sec_prot.c +++ b/features/nanostack/sal-stack-nanostack/source/Security/protocols/fwh_sec_prot/auth_fwh_sec_prot.c @@ -341,6 +341,7 @@ static void auth_fwh_sec_prot_state_machine(sec_prot_t *prot) // 4WH authenticator state machine switch (sec_prot_state_get(&data->common)) { case FWH_STATE_INIT: + tr_info("4WH: init"); prot->timer_start(prot); sec_prot_state_set(prot, &data->common, FWH_STATE_CREATE_REQ); break; @@ -349,6 +350,9 @@ static void auth_fwh_sec_prot_state_machine(sec_prot_t *prot) case FWH_STATE_CREATE_REQ: tr_info("4WH: start, eui-64: %s", trace_array(sec_prot_remote_eui_64_addr_get(prot), 8)); + // Set default timeout for the total maximum length of the negotiation + sec_prot_default_timeout_set(&data->common); + uint8_t *pmk = sec_prot_keys_pmk_get(prot->sec_keys); if (!pmk) { // If PMK is not set fails prot->create_conf(prot, SEC_RESULT_ERROR); @@ -429,10 +433,13 @@ static void auth_fwh_sec_prot_state_machine(sec_prot_t *prot) sec_prot_state_set(prot, &data->common, FWH_STATE_FINISHED); break; - case FWH_STATE_FINISHED: + case FWH_STATE_FINISHED: { + uint8_t *remote_eui_64 = sec_prot_remote_eui_64_addr_get(prot); + tr_info("4WH: finished, eui-64: %s", remote_eui_64 ? trace_array(sec_prot_remote_eui_64_addr_get(prot), 8) : "not set"); prot->timer_stop(prot); prot->finished(prot); break; + } default: break; diff --git a/features/nanostack/sal-stack-nanostack/source/Security/protocols/fwh_sec_prot/supp_fwh_sec_prot.c b/features/nanostack/sal-stack-nanostack/source/Security/protocols/fwh_sec_prot/supp_fwh_sec_prot.c index 7faa7e7f433..ee44df03cfe 100644 --- a/features/nanostack/sal-stack-nanostack/source/Security/protocols/fwh_sec_prot/supp_fwh_sec_prot.c +++ b/features/nanostack/sal-stack-nanostack/source/Security/protocols/fwh_sec_prot/supp_fwh_sec_prot.c @@ -310,6 +310,7 @@ static void supp_fwh_sec_prot_state_machine(sec_prot_t *prot) // 4WH supplicant state machine switch (sec_prot_state_get(&data->common)) { case FWH_STATE_INIT: + tr_info("4WH: init"); prot->timer_start(prot); sec_prot_state_set(prot, &data->common, FWH_STATE_MESSAGE_1); break; @@ -325,6 +326,9 @@ static void supp_fwh_sec_prot_state_machine(sec_prot_t *prot) return; } + // Set default timeout for the total maximum length of the negotiation + sec_prot_default_timeout_set(&data->common); + tr_info("4WH: start"); // Store authenticator nonce for check when 4WH Message 3 is received @@ -467,6 +471,7 @@ static void supp_fwh_sec_prot_state_machine(sec_prot_t *prot) break; case FWH_STATE_FINISHED: + tr_info("4WH: finished"); prot->timer_stop(prot); prot->finished(prot); break; diff --git a/features/nanostack/sal-stack-nanostack/source/Security/protocols/gkh_sec_prot/auth_gkh_sec_prot.c b/features/nanostack/sal-stack-nanostack/source/Security/protocols/gkh_sec_prot/auth_gkh_sec_prot.c index ac95f917830..50a9691b33b 100644 --- a/features/nanostack/sal-stack-nanostack/source/Security/protocols/gkh_sec_prot/auth_gkh_sec_prot.c +++ b/features/nanostack/sal-stack-nanostack/source/Security/protocols/gkh_sec_prot/auth_gkh_sec_prot.c @@ -293,14 +293,17 @@ static void auth_gkh_sec_prot_state_machine(sec_prot_t *prot) // GKH authenticator state machine switch (sec_prot_state_get(&data->common)) { case GKH_STATE_INIT: + tr_info("GKH init"); sec_prot_state_set(prot, &data->common, GKH_STATE_CREATE_REQ); + prot->timer_start(prot); break; // Wait KMP-CREATE.request case GKH_STATE_CREATE_REQ: tr_info("GKH start, eui-64: %s", trace_array(sec_prot_remote_eui_64_addr_get(prot), 8)); - prot->timer_start(prot); + // Set default timeout for the total maximum length of the negotiation + sec_prot_default_timeout_set(&data->common); // KMP-CREATE.confirm prot->create_conf(prot, SEC_RESULT_OK); @@ -340,10 +343,13 @@ static void auth_gkh_sec_prot_state_machine(sec_prot_t *prot) sec_prot_state_set(prot, &data->common, GKH_STATE_FINISHED); break; - case GKH_STATE_FINISHED: + case GKH_STATE_FINISHED: { + uint8_t *remote_eui_64 = sec_prot_remote_eui_64_addr_get(prot); + tr_info("GKH finished, eui-64: %s", remote_eui_64 ? trace_array(sec_prot_remote_eui_64_addr_get(prot), 8) : "not set"); prot->timer_stop(prot); prot->finished(prot); break; + } default: break; diff --git a/features/nanostack/sal-stack-nanostack/source/Security/protocols/gkh_sec_prot/supp_gkh_sec_prot.c b/features/nanostack/sal-stack-nanostack/source/Security/protocols/gkh_sec_prot/supp_gkh_sec_prot.c index 15b8dcce2ce..ccd2890ec99 100644 --- a/features/nanostack/sal-stack-nanostack/source/Security/protocols/gkh_sec_prot/supp_gkh_sec_prot.c +++ b/features/nanostack/sal-stack-nanostack/source/Security/protocols/gkh_sec_prot/supp_gkh_sec_prot.c @@ -230,7 +230,9 @@ static void supp_gkh_sec_prot_state_machine(sec_prot_t *prot) // GKH supplicant state machine switch (sec_prot_state_get(&data->common)) { case GKH_STATE_INIT: + tr_info("GKH init"); sec_prot_state_set(prot, &data->common, GKH_STATE_MESSAGE_1); + prot->timer_start(prot); break; // Wait GKH message 1 (starts handshake on supplicant) @@ -243,11 +245,12 @@ static void supp_gkh_sec_prot_state_machine(sec_prot_t *prot) return; } - supp_gkh_sec_prot_security_replay_counter_update(prot); + // Set default timeout for the total maximum length of the negotiation + sec_prot_default_timeout_set(&data->common); - tr_debug("GKH start"); + supp_gkh_sec_prot_security_replay_counter_update(prot); - prot->timer_start(prot); + tr_info("GKH start"); // Send KMP-CREATE.indication prot->create_ind(prot); @@ -267,7 +270,7 @@ static void supp_gkh_sec_prot_state_machine(sec_prot_t *prot) break; case GKH_STATE_FINISH: - tr_debug("GKH finish"); + tr_info("GKH finish"); // KMP-FINISHED.indication, prot->finished_ind(prot, sec_prot_result_get(&data->common), prot->sec_keys); @@ -275,6 +278,7 @@ static void supp_gkh_sec_prot_state_machine(sec_prot_t *prot) break; case GKH_STATE_FINISHED: + tr_info("GKH finished"); prot->timer_stop(prot); prot->finished(prot); break; diff --git a/features/nanostack/sal-stack-nanostack/source/Security/protocols/sec_prot_certs.c b/features/nanostack/sal-stack-nanostack/source/Security/protocols/sec_prot_certs.c index cc779a1149f..dc76a22ba94 100644 --- a/features/nanostack/sal-stack-nanostack/source/Security/protocols/sec_prot_certs.c +++ b/features/nanostack/sal-stack-nanostack/source/Security/protocols/sec_prot_certs.c @@ -32,6 +32,10 @@ #define TRACE_GROUP "spce" +// Length for PEM coded certificate's begin and end certificate text strings +#define SEC_PROT_CERT_PEM_HEADER_FOOTER_LEN 52 +#define SEC_PROT_CERT_PEM_HEADER_STR "-----BEGIN CERTIFICATE-----" + int8_t sec_prot_certs_init(sec_prot_certs_t *certs) { if (!certs) { @@ -41,6 +45,8 @@ int8_t sec_prot_certs_init(sec_prot_certs_t *certs) sec_prot_certs_chain_entry_init(&certs->own_cert_chain); ns_list_init(&certs->trusted_cert_chain_list); ns_list_init(&certs->cert_revocat_lists); + certs->own_cert_chain_len = 0; + certs->ext_cert_valid_enabled = false; return 0; } @@ -56,6 +62,27 @@ void sec_prot_certs_delete(sec_prot_certs_t *certs) sec_prot_certs_revocat_lists_delete(&certs->cert_revocat_lists); } +int8_t sec_prot_certs_ext_certificate_validation_set(sec_prot_certs_t *certs, bool enabled) +{ + if (!certs) { + return -1; + } + + certs->ext_cert_valid_enabled = enabled; + + return 0; +} + +bool sec_prot_certs_ext_certificate_validation_get(const sec_prot_certs_t *certs) +{ + return certs->ext_cert_valid_enabled; +} + +uint16_t sec_prot_certs_own_cert_chain_len_get(const sec_prot_certs_t *certs) +{ + return certs->own_cert_chain_len; +} + cert_chain_entry_t *sec_prot_certs_chain_entry_create(void) { cert_chain_entry_t *entry = ns_dyn_mem_alloc(sizeof(cert_chain_entry_t)); @@ -98,6 +125,28 @@ uint8_t *sec_prot_certs_cert_get(const cert_chain_entry_t *entry, uint8_t index, return entry->cert[index]; } +uint16_t sec_prot_certs_cert_chain_entry_len_get(const cert_chain_entry_t *entry) +{ + uint16_t chain_length = 0; + for (uint8_t index = 0; index < SEC_PROT_CERT_CHAIN_DEPTH; index++) { + if (entry->cert[index]) { + uint16_t cert_length = entry->cert_len[index]; + // Checks if certificate is in PEM base64 format + if (cert_length > SEC_PROT_CERT_PEM_HEADER_FOOTER_LEN && + entry->cert[index][cert_length - 1] == '\0' && + strstr((const char *)entry->cert[index], SEC_PROT_CERT_PEM_HEADER_STR) != NULL) { + cert_length -= SEC_PROT_CERT_PEM_HEADER_FOOTER_LEN; + /* 4 base64 chars encode 3 bytes (ignores line endings and possible paddings in the + calculation i.e they are counted to length) */ + chain_length += (cert_length / 4) * 3; + } else { + chain_length += cert_length; + } + } + } + return chain_length; +} + int8_t sec_prot_certs_priv_key_set(cert_chain_entry_t *entry, uint8_t *key, uint8_t key_len) { if (!entry) { diff --git a/features/nanostack/sal-stack-nanostack/source/Security/protocols/sec_prot_certs.h b/features/nanostack/sal-stack-nanostack/source/Security/protocols/sec_prot_certs.h index 3c2ce3d1a94..e9a25ece847 100644 --- a/features/nanostack/sal-stack-nanostack/source/Security/protocols/sec_prot_certs.h +++ b/features/nanostack/sal-stack-nanostack/source/Security/protocols/sec_prot_certs.h @@ -58,6 +58,8 @@ typedef struct { cert_chain_entry_t own_cert_chain; /**< Own certificate chain */ cert_chain_list_t trusted_cert_chain_list; /**< Trusted certificate chain lists */ cert_revocat_lists_t cert_revocat_lists; /**< Certificate Revocation Lists */ + uint16_t own_cert_chain_len; /**< Own certificate chain certificates length */ + bool ext_cert_valid_enabled : 1; /**< Extended certificate validation enabled */ } sec_prot_certs_t; /** @@ -78,6 +80,37 @@ int8_t sec_prot_certs_init(sec_prot_certs_t *certs); */ void sec_prot_certs_delete(sec_prot_certs_t *certs); +/** + * sec_prot_certs_ext_certificate_validation_set enable or disable extended certificate validation + * + * \param certs certificate information + * \param enabled true to enable extended validation, false to disable + * + * \return < 0 failure + * \return >= 0 success + * + */ +int8_t sec_prot_certs_ext_certificate_validation_set(sec_prot_certs_t *certs, bool enabled); + +/** + * sec_prot_certs_ext_certificate_validation_get get extended certificate validation setting + * + * \param certs certificate information + * + * \return true/false enabled or not + * + */ +bool sec_prot_certs_ext_certificate_validation_get(const sec_prot_certs_t *certs); + +/** + * sec_prot_certs_own_cert_chain_len_get get length of own certificate chain + * + * \param certs certificate information + * + * \return length of all the certificates in the own certificate chain + */ +uint16_t sec_prot_certs_own_cert_chain_len_get(const sec_prot_certs_t *certs); + /** * sec_prot_certs_chain_entry_create allocate memory for certificate chain entry * @@ -123,6 +156,15 @@ int8_t sec_prot_certs_cert_set(cert_chain_entry_t *entry, uint8_t index, uint8_t */ uint8_t *sec_prot_certs_cert_get(const cert_chain_entry_t *entry, uint8_t index, uint16_t *cert_len); +/** + * sec_prot_certs_cert_chain_entry_len_get get length of certificate chain on cert chain entry + * + * \param entry certificate chain entry + * + * \return total length of all the certificates in the entry + */ +uint16_t sec_prot_certs_cert_chain_entry_len_get(const cert_chain_entry_t *entry); + /** * sec_prot_certs_priv_key_set set certificate (chain) private key * diff --git a/features/nanostack/sal-stack-nanostack/source/Security/protocols/sec_prot_lib.c b/features/nanostack/sal-stack-nanostack/source/Security/protocols/sec_prot_lib.c index 470d854639b..29268529d32 100644 --- a/features/nanostack/sal-stack-nanostack/source/Security/protocols/sec_prot_lib.c +++ b/features/nanostack/sal-stack-nanostack/source/Security/protocols/sec_prot_lib.c @@ -48,7 +48,7 @@ void sec_prot_init(sec_prot_common_t *data) { data->state = SEC_STATE_INIT; data->result = SEC_RESULT_OK; - data->ticks = SEC_TOTAL_TIMEOUT; + data->ticks = SEC_INIT_TIMEOUT; data->trickle_running = false; } @@ -73,10 +73,14 @@ void sec_prot_timer_timeout_handle(sec_prot_t *prot, sec_prot_common_t *data, co if (data->ticks > ticks) { data->ticks -= ticks; } else { - tr_debug("prot timeout"); + tr_debug("prot timeout, state: %i", data->state); data->ticks = 0; sec_prot_result_set(data, SEC_RESULT_TIMEOUT); - sec_prot_state_set(prot, data, SEC_STATE_FINISH); + if (data->state == SEC_STATE_INIT) { + sec_prot_state_set(prot, data, SEC_STATE_FINISHED); + } else { + sec_prot_state_set(prot, data, SEC_STATE_FINISH); + } } } @@ -167,6 +171,11 @@ bool sec_prot_result_ok_check(sec_prot_common_t *data) return false; } +void sec_prot_default_timeout_set(sec_prot_common_t *data) +{ + data->ticks = SEC_TOTAL_TIMEOUT; +} + void sec_prot_lib_nonce_generate(uint8_t *nonce) { // Use randlib diff --git a/features/nanostack/sal-stack-nanostack/source/Security/protocols/sec_prot_lib.h b/features/nanostack/sal-stack-nanostack/source/Security/protocols/sec_prot_lib.h index 4786e49cd4d..1ade05bd44e 100644 --- a/features/nanostack/sal-stack-nanostack/source/Security/protocols/sec_prot_lib.h +++ b/features/nanostack/sal-stack-nanostack/source/Security/protocols/sec_prot_lib.h @@ -32,6 +32,7 @@ #define FWH_NONCE_LENGTH 32 #define EUI64_LEN 8 #define SEC_TOTAL_TIMEOUT 30 * 60 * 10 // 30 minutes +#define SEC_INIT_TIMEOUT 60 * 10 // 60 seconds #define SEC_FINISHED_TIMEOUT 5 * 10 // 5 seconds @@ -295,4 +296,12 @@ bool sec_prot_result_timeout_check(sec_prot_common_t *data); */ bool sec_prot_result_ok_check(sec_prot_common_t *data); +/** + * sec_prot_default_timeout_set sets default timeout for protocol + * + * \param data common data + * + */ +void sec_prot_default_timeout_set(sec_prot_common_t *data); + #endif /* SEC_PROT_LIB_H_ */ diff --git a/features/nanostack/sal-stack-nanostack/source/Security/protocols/tls_sec_prot/tls_sec_prot.c b/features/nanostack/sal-stack-nanostack/source/Security/protocols/tls_sec_prot/tls_sec_prot.c index 7d443073c61..beff5f5bae7 100644 --- a/features/nanostack/sal-stack-nanostack/source/Security/protocols/tls_sec_prot/tls_sec_prot.c +++ b/features/nanostack/sal-stack-nanostack/source/Security/protocols/tls_sec_prot/tls_sec_prot.c @@ -104,6 +104,8 @@ static bool tls_sec_prot_queue_check(sec_prot_t *prot); static bool tls_sec_prot_queue_process(sec_prot_t *prot); static void tls_sec_prot_queue_remove(sec_prot_t *prot); +static uint16_t tls_sec_prot_send_buffer_size_get(sec_prot_t *prot); + #define tls_sec_prot_get(prot) (tls_sec_prot_int_t *) &prot->data static NS_LIST_DEFINE(tls_sec_prot_queue, tls_sec_prot_queue_t, link); @@ -292,15 +294,17 @@ static void client_tls_sec_prot_state_machine(sec_prot_t *prot) switch (sec_prot_state_get(&data->common)) { case TLS_STATE_INIT: + tr_debug("TLS: init"); sec_prot_state_set(prot, &data->common, TLS_STATE_CREATE_REQ); + prot->timer_start(prot); + // Set default timeout for the total maximum length of the negotiation + sec_prot_default_timeout_set(&data->common); break; // Wait KMP-CREATE.request case TLS_STATE_CREATE_REQ: tr_debug("TLS: start"); - prot->timer_start(prot); - prot->create_conf(prot, SEC_RESULT_OK); sec_prot_state_set(prot, &data->common, TLS_STATE_CONFIGURE); @@ -383,15 +387,17 @@ static void server_tls_sec_prot_state_machine(sec_prot_t *prot) switch (sec_prot_state_get(&data->common)) { case TLS_STATE_INIT: + tr_debug("TLS: init"); sec_prot_state_set(prot, &data->common, TLS_STATE_CLIENT_HELLO); + prot->timer_start(prot); + // Set default timeout for the total maximum length of the negotiation + sec_prot_default_timeout_set(&data->common); break; // Wait EAP request, Identity (starts handshake on supplicant) case TLS_STATE_CLIENT_HELLO: - tr_debug("TLS: start, eui-64: %s", trace_array(sec_prot_remote_eui_64_addr_get(prot), 8)); - prot->timer_start(prot); client_hello = true; sec_prot_state_set(prot, &data->common, TLS_STATE_CREATE_RESP); @@ -494,12 +500,23 @@ static int16_t tls_sec_prot_tls_send(void *handle, const void *buf, size_t len) tls_sec_prot_int_t *data = tls_sec_prot_get(prot); if (!data->tls_send.data) { - eap_tls_sec_prot_lib_message_allocate(&data->tls_send, prot->header_size, TLS_SEC_PROT_BUFFER_SIZE); + uint16_t buffer_len = tls_sec_prot_send_buffer_size_get(prot); + eap_tls_sec_prot_lib_message_allocate(&data->tls_send, prot->header_size, buffer_len); } if (!data->tls_send.data) { return -1; } + /* If send buffer is too small for the TLS payload, re-allocates */ + uint16_t new_len = prot->header_size + data->tls_send.handled_len + len; + if (new_len > data->tls_send.total_len) { + tr_error("TLS send buffer size too small: %i < %i, allocating new: %i", data->tls_send.total_len, new_len, data->tls_send.total_len + TLS_SEC_PROT_SEND_BUFFER_SIZE_INCREMENT); + if (eap_tls_sec_prot_lib_message_realloc(&data->tls_send, prot->header_size, + data->tls_send.total_len + TLS_SEC_PROT_SEND_BUFFER_SIZE_INCREMENT) < 0) { + return -1; + } + } + memcpy(data->tls_send.data + prot->header_size + data->tls_send.handled_len, buf, len); data->tls_send.handled_len += len; @@ -685,4 +702,9 @@ static void tls_sec_prot_queue_remove(sec_prot_t *prot) } } +static uint16_t tls_sec_prot_send_buffer_size_get(sec_prot_t *prot) +{ + return TLS_SEC_PROT_SEND_BUFFER_SIZE + sec_prot_certs_own_cert_chain_len_get(prot->sec_keys->certs); +} + #endif /* HAVE_WS */ diff --git a/features/nanostack/sal-stack-nanostack/source/Security/protocols/tls_sec_prot/tls_sec_prot.h b/features/nanostack/sal-stack-nanostack/source/Security/protocols/tls_sec_prot/tls_sec_prot.h index 5ed9621ea76..129648e1cc1 100644 --- a/features/nanostack/sal-stack-nanostack/source/Security/protocols/tls_sec_prot/tls_sec_prot.h +++ b/features/nanostack/sal-stack-nanostack/source/Security/protocols/tls_sec_prot/tls_sec_prot.h @@ -23,7 +23,13 @@ * */ -#define TLS_SEC_PROT_BUFFER_SIZE 1200 // Send buffer size (maximum size for a TLS data for a flight) +/* TLS send buffer size not including certificates. This should include e.g. on + * server: server hello, server key exchange, certificate request and server + * hello done. */ +#define TLS_SEC_PROT_SEND_BUFFER_SIZE 500 + +/* TLS send buffer size increment if it is detected that buffer is too small */ +#define TLS_SEC_PROT_SEND_BUFFER_SIZE_INCREMENT 1000 /** * client_tls_sec_prot_register register client TLS protocol to KMP service diff --git a/features/nanostack/sal-stack-nanostack/source/Security/protocols/tls_sec_prot/tls_sec_prot_lib.c b/features/nanostack/sal-stack-nanostack/source/Security/protocols/tls_sec_prot/tls_sec_prot_lib.c index 6b631e20f51..03e2f5cf723 100644 --- a/features/nanostack/sal-stack-nanostack/source/Security/protocols/tls_sec_prot/tls_sec_prot_lib.c +++ b/features/nanostack/sal-stack-nanostack/source/Security/protocols/tls_sec_prot/tls_sec_prot_lib.c @@ -49,6 +49,7 @@ #include "mbedtls/ctr_drbg.h" #include "mbedtls/ssl_ciphersuites.h" #include "mbedtls/debug.h" +#include "mbedtls/oid.h" #include "mbedtls/ssl_internal.h" @@ -57,7 +58,9 @@ #define TLS_HANDSHAKE_TIMEOUT_MIN 25000 #define TLS_HANDSHAKE_TIMEOUT_MAX 201000 -//#define TLS_SEC_PROT_LIB_TLS_DEBUG // Enable mbed TLS debug traces +//#define TLS_SEC_PROT_LIB_TLS_DEBUG // Enable mbed TLS debug traces + +typedef int tls_sec_prot_lib_crt_verify_cb(tls_security_t *sec, mbedtls_x509_crt *crt, uint32_t *flags); struct tls_security_s { mbedtls_ssl_config conf; /**< mbed TLS SSL configuration */ @@ -71,6 +74,8 @@ struct tls_security_s { mbedtls_x509_crt owncert; /**< Own certificate(s) */ mbedtls_pk_context pkey; /**< Private key for own certificate */ void *handle; /**< Handle provided in callbacks (defined by library user) */ + bool ext_cert_valid : 1; /**< Extended certificate validation enabled */ + tls_sec_prot_lib_crt_verify_cb *crt_verify; /**< Verify function for client/server certificate */ tls_sec_prot_lib_send *send; /**< Send callback */ tls_sec_prot_lib_receive *receive; /**< Receive callback */ tls_sec_prot_lib_export_keys *export_keys; /**< Export keys callback */ @@ -88,20 +93,39 @@ static int tls_sec_prot_lib_ssl_export_keys(void *p_expkey, const unsigned char size_t ivlen, const unsigned char client_random[32], const unsigned char server_random[32], mbedtls_tls_prf_types tls_prf_type); + +static int tls_sec_prot_lib_x509_crt_verify(void *ctx, mbedtls_x509_crt *crt, int certificate_depth, uint32_t *flags); +static int8_t tls_sec_prot_lib_subject_alternative_name_validate(mbedtls_x509_crt *crt); +static int8_t tls_sec_prot_lib_extended_key_usage_validate(mbedtls_x509_crt *crt); +#ifdef HAVE_PAE_AUTH +static int tls_sec_prot_lib_x509_crt_idevid_ldevid_verify(tls_security_t *sec, mbedtls_x509_crt *crt, uint32_t *flags); +#endif +#ifdef HAVE_PAE_SUPP +static int tls_sec_prot_lib_x509_crt_server_verify(tls_security_t *sec, mbedtls_x509_crt *crt, uint32_t *flags); +#endif #ifdef TLS_SEC_PROT_LIB_TLS_DEBUG static void tls_sec_prot_lib_debug(void *ctx, int level, const char *file, int line, const char *string); #endif - #ifdef MBEDTLS_PLATFORM_MEMORY // Disable for now //#define TLS_SEC_PROT_LIB_USE_MBEDTLS_PLATFORM_MEMORY #endif - #ifdef TLS_SEC_PROT_LIB_USE_MBEDTLS_PLATFORM_MEMORY static void *tls_sec_prot_lib_mem_calloc(size_t count, size_t size); static void tls_sec_prot_lib_mem_free(void *ptr); #endif +#if defined(HAVE_PAE_AUTH) && defined(HAVE_PAE_SUPP) +#define is_server_is_set (is_server == true) +#define is_server_is_not_set (is_server == false) +#elif defined(HAVE_PAE_AUTH) +#define is_server_is_set true +#define is_server_is_not_set false +#elif defined(HAVE_PAE_SUPP) +#define is_server_is_set false +#define is_server_is_not_set true +#endif + int8_t tls_sec_prot_lib_init(tls_security_t *sec) { const char *pers = "ws_tls"; @@ -110,7 +134,6 @@ int8_t tls_sec_prot_lib_init(tls_security_t *sec) mbedtls_platform_set_calloc_free(tls_sec_prot_lib_mem_calloc, tls_sec_prot_lib_mem_free); #endif - mbedtls_ssl_init(&sec->ssl); mbedtls_ssl_config_init(&sec->conf); mbedtls_ctr_drbg_init(&sec->ctr_drbg); @@ -269,21 +292,37 @@ static int tls_sec_prot_lib_configure_certificates(tls_security_t *sec, const se // Certificate verify required on both client and server mbedtls_ssl_conf_authmode(&sec->conf, MBEDTLS_SSL_VERIFY_REQUIRED); + // Get extended certificate validation setting + sec->ext_cert_valid = sec_prot_certs_ext_certificate_validation_get(certs); + return 0; } int8_t tls_sec_prot_lib_connect(tls_security_t *sec, bool is_server, const sec_prot_certs_t *certs) { +#if !defined(HAVE_PAE_SUPP) || !defined(HAVE_PAE_AUTH) + (void) is_server; +#endif + if (!sec) { return -1; } - int endpoint = MBEDTLS_SSL_IS_CLIENT; - if (is_server) { - endpoint = MBEDTLS_SSL_IS_SERVER; +#ifdef HAVE_PAE_SUPP + if (is_server_is_not_set) { + sec->crt_verify = tls_sec_prot_lib_x509_crt_server_verify; } +#endif +#ifdef HAVE_PAE_AUTH + if (is_server_is_set) { + sec->crt_verify = tls_sec_prot_lib_x509_crt_idevid_ldevid_verify; + } +#endif - if ((mbedtls_ssl_config_defaults(&sec->conf, endpoint, MBEDTLS_SSL_TRANSPORT_STREAM, 0)) != 0) { + + if ((mbedtls_ssl_config_defaults(&sec->conf, + is_server_is_set ? MBEDTLS_SSL_IS_SERVER : MBEDTLS_SSL_IS_CLIENT, + MBEDTLS_SSL_TRANSPORT_STREAM, 0)) != 0) { tr_error("config defaults fail"); return -1; } @@ -331,8 +370,11 @@ int8_t tls_sec_prot_lib_connect(tls_security_t *sec, bool is_server, const sec_p mbedtls_ssl_conf_min_version(&sec->conf, MBEDTLS_SSL_MAJOR_VERSION_3, MBEDTLS_SSL_MAJOR_VERSION_3); mbedtls_ssl_conf_max_version(&sec->conf, MBEDTLS_SSL_MAJOR_VERSION_3, MBEDTLS_SSL_MAJOR_VERSION_3); + // Set certificate verify callback + mbedtls_ssl_set_verify(&sec->ssl, tls_sec_prot_lib_x509_crt_verify, sec); + #ifdef MBEDTLS_ECP_RESTARTABLE - if (endpoint == MBEDTLS_SSL_IS_SERVER) { + if (is_server_is_set) { // Temporary to enable non blocking ECC */ sec->ssl.handshake->ecrs_enabled = 1; } @@ -433,6 +475,109 @@ static int tls_sec_prot_lib_ssl_export_keys(void *p_expkey, const unsigned char return 0; } +static int tls_sec_prot_lib_x509_crt_verify(void *ctx, mbedtls_x509_crt *crt, int certificate_depth, uint32_t *flags) +{ + tls_security_t *sec = (tls_security_t *) ctx; + + /* MD/PK forced by configuration flags and dynamic settings but traced also here + to prevent invalid configurations/certificates */ + if (crt->sig_md != MBEDTLS_MD_SHA256) { + tr_error("Invalid signature md algorithm"); + } + if (crt->sig_pk != MBEDTLS_PK_ECDSA) { + tr_error("Invalid signature pk algorithm"); + } + + // Verify client/server certificate of the chain + if (certificate_depth == 0) { + return sec->crt_verify(sec, crt, flags); + } + + // No further checks for intermediate and root certificates at the moment + return 0; +} + +static int8_t tls_sec_prot_lib_subject_alternative_name_validate(mbedtls_x509_crt *crt) +{ + mbedtls_asn1_sequence *seq = &crt->subject_alt_names; + int8_t result = -1; + while (seq) { + mbedtls_x509_subject_alternative_name san; + int ret_value = mbedtls_x509_parse_subject_alt_name((mbedtls_x509_buf *)&seq->buf, &san); + if (ret_value == 0 && san.type == MBEDTLS_X509_SAN_OTHER_NAME) { + // id-on-hardwareModuleName must be present (1.3.6.1.5.5.7.8.4) + if (MBEDTLS_OID_CMP(MBEDTLS_OID_ON_HW_MODULE_NAME, &san.san.other_name.value.hardware_module_name.oid)) { + // Traces hardwareModuleName (1.3.6.1.4.1..) + char buffer[30]; + ret_value = mbedtls_oid_get_numeric_string(buffer, sizeof(buffer), &san.san.other_name.value.hardware_module_name.oid); + if (ret_value != MBEDTLS_ERR_OID_BUF_TOO_SMALL) { + tr_info("id-on-hardwareModuleName %s", buffer); + } + // Traces serial number as hex string + mbedtls_x509_buf *val = &san.san.other_name.value.hardware_module_name.val; + if (val->p) { + tr_info("id-on-hardwareModuleName hwSerialNum %s", trace_array(val->p, val->len)); + } + result = 0; + } + } else { + tr_debug("Ignored subject alt name: %i", san.type); + } + seq = seq->next; + } + return result; +} + +static int8_t tls_sec_prot_lib_extended_key_usage_validate(mbedtls_x509_crt *crt) +{ +#if defined(MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE) + // Extended key usage must be present + if (mbedtls_x509_crt_check_extended_key_usage(crt, MBEDTLS_OID_WISUN_FAN, sizeof(MBEDTLS_OID_WISUN_FAN) - 1) != 0) { + tr_error("invalid extended key usage"); + return -1; // FAIL + } +#endif + return 0; +} + +#ifdef HAVE_PAE_AUTH +static int tls_sec_prot_lib_x509_crt_idevid_ldevid_verify(tls_security_t *sec, mbedtls_x509_crt *crt, uint32_t *flags) +{ + // For both IDevID and LDevId both subject alternative name or extended key usage must be valid + if (tls_sec_prot_lib_subject_alternative_name_validate(crt) < 0 || + tls_sec_prot_lib_extended_key_usage_validate(crt) < 0) { + tr_error("invalid cert"); + if (sec->ext_cert_valid) { + *flags |= MBEDTLS_X509_BADCERT_OTHER; + return MBEDTLS_ERR_X509_CERT_VERIFY_FAILED; + } + } + return 0; +} +#endif + +#ifdef HAVE_PAE_SUPP +static int tls_sec_prot_lib_x509_crt_server_verify(tls_security_t *sec, mbedtls_x509_crt *crt, uint32_t *flags) +{ + int8_t sane_res = tls_sec_prot_lib_subject_alternative_name_validate(crt); + int8_t ext_key_res = tls_sec_prot_lib_extended_key_usage_validate(crt); + + // If either subject alternative name or extended key usage is present + if (sane_res >= 0 || ext_key_res >= 0) { + // Then both subject alternative name and extended key usage must be valid + if (sane_res < 0 || ext_key_res < 0) { + tr_error("invalid cert"); + if (sec->ext_cert_valid) { + *flags |= MBEDTLS_X509_BADCERT_OTHER; + return MBEDTLS_ERR_X509_CERT_VERIFY_FAILED; + } + } + } + + return 0; +} +#endif + static int tls_sec_lib_entropy_poll(void *ctx, unsigned char *output, size_t len, size_t *olen) { (void)ctx; @@ -518,4 +663,3 @@ uint16_t tls_sec_prot_lib_size(void) } #endif /* WS_MBEDTLS_SECURITY_ENABLED */ #endif /* HAVE_WS */ - diff --git a/features/nanostack/sal-stack-nanostack/source/libDHCPv6/dhcp_service_api.c b/features/nanostack/sal-stack-nanostack/source/libDHCPv6/dhcp_service_api.c index 5eb41644855..8e321a9468f 100644 --- a/features/nanostack/sal-stack-nanostack/source/libDHCPv6/dhcp_service_api.c +++ b/features/nanostack/sal-stack-nanostack/source/libDHCPv6/dhcp_service_api.c @@ -679,6 +679,7 @@ void dhcp_service_delete(uint16_t instance) int dhcp_service_send_resp(uint32_t msg_tr_id, uint8_t options, uint8_t *msg_ptr, uint16_t msg_len) { + tr_debug("Send DHCPv6 response"); msg_tr_t *msg_tr_ptr; server_instance_t *srv_instance; msg_tr_ptr = dhcp_tr_find(msg_tr_id); @@ -706,6 +707,7 @@ int dhcp_service_send_resp(uint32_t msg_tr_id, uint8_t options, uint8_t *msg_ptr } uint32_t dhcp_service_send_req(uint16_t instance_id, uint8_t options, void *ptr, const uint8_t addr[static 16], uint8_t *msg_ptr, uint16_t msg_len, dhcp_service_receive_resp_cb *receive_resp_cb) { + tr_debug("Send DHCPv6 request"); msg_tr_t *msg_tr_ptr; server_instance_t *srv_ptr; srv_ptr = dhcp_service_client_find(instance_id); @@ -767,6 +769,17 @@ void dhcp_service_req_remove(uint32_t msg_tr_id) return; } +void dhcp_service_req_remove_all(void *msg_class_ptr) +{ + if (dhcp_service) { + ns_list_foreach_safe(msg_tr_t, cur_ptr, &dhcp_service->tr_list) { + if (cur_ptr->client_obj_ptr == msg_class_ptr) { + dhcp_tr_delete(cur_ptr); + } + } + } +} + void dhcp_service_send_message(msg_tr_t *msg_tr_ptr) { int8_t retval; @@ -930,4 +943,9 @@ bool dhcp_service_timer_tick(uint16_t ticks) return false; } +void dhcp_service_req_remove_all(void *msg_class_ptr) +{ + (void)msg_class_ptr; +} + #endif diff --git a/features/nanostack/sal-stack-nanostack/source/libDHCPv6/libDHCPv6.c b/features/nanostack/sal-stack-nanostack/source/libDHCPv6/libDHCPv6.c index 5b7b3ffb8be..86fa88345cf 100644 --- a/features/nanostack/sal-stack-nanostack/source/libDHCPv6/libDHCPv6.c +++ b/features/nanostack/sal-stack-nanostack/source/libDHCPv6/libDHCPv6.c @@ -217,6 +217,17 @@ dhcpv6_client_server_data_t *libdhcpv6_nonTemporal_entry_get_by_prefix(int8_t in return NULL; } +dhcpv6_client_server_data_t *libdhcpv6_nonTemporal_validate_class_pointer(void *class_ptr) +{ + ns_list_foreach(dhcpv6_client_server_data_t, cur, &dhcpv6_client_nonTemporal_list) { + if (cur == class_ptr) { + return cur; + } + } + return NULL; +} + + uint16_t libdhcpv6_duid_option_size(uint16_t linkType) { uint16_t length = 8; // Type & Length header part *2 diff --git a/features/nanostack/sal-stack-nanostack/source/libDHCPv6/libDHCPv6.h b/features/nanostack/sal-stack-nanostack/source/libDHCPv6/libDHCPv6.h index 7cbf1cdd7e2..e3cb6128263 100644 --- a/features/nanostack/sal-stack-nanostack/source/libDHCPv6/libDHCPv6.h +++ b/features/nanostack/sal-stack-nanostack/source/libDHCPv6/libDHCPv6.h @@ -235,6 +235,7 @@ dhcpv6_client_server_data_t *libdhcpv6_nonTemporal_entry_get_by_iaid(uint32_t ia dhcpv6_client_server_data_t *libdhcpv6_nonTemporal_entry_get_by_transactionId(uint32_t txId); dhcpv6_client_server_data_t *libdhcpv6_nonTemporal_entry_get_by_prefix(int8_t interfaceId, uint8_t *prefix); dhcpv6_client_server_data_t *libdhcpv6_nonTemporal_entry_get_by_instance(uint8_t instanceId); +dhcpv6_client_server_data_t *libdhcpv6_nonTemporal_validate_class_pointer(void *class_ptr); uint8_t libdhcpv6_nonTemporal_entry_get_unique_instance_id(void); diff --git a/features/nanostack/sal-stack-nanostack/source/libNET/src/ns_net.c b/features/nanostack/sal-stack-nanostack/source/libNET/src/ns_net.c index da7e31b98e5..5ee8a60dc66 100644 --- a/features/nanostack/sal-stack-nanostack/source/libNET/src/ns_net.c +++ b/features/nanostack/sal-stack-nanostack/source/libNET/src/ns_net.c @@ -988,18 +988,30 @@ int8_t arm_network_trusted_certificate_remove(const arm_certificate_entry_s *cer int8_t arm_network_trusted_certificates_remove(void) { +#ifdef HAVE_WS + return ws_pae_controller_trusted_certificates_remove(); +#else return -1; +#endif } int8_t arm_network_own_certificate_add(const arm_certificate_entry_s *cert) { +#ifdef HAVE_WS + return ws_pae_controller_own_certificate_add(cert); +#else (void) cert; return -1; +#endif } extern int8_t arm_network_own_certificates_remove(void) { +#ifdef HAVE_WS + return ws_pae_controller_own_certificates_remove(); +#else return -1; +#endif } int8_t arm_network_certificate_revocation_list_add(const arm_cert_revocation_list_entry_s *crl) From 9051e21f39f3d0a80acf893981bb2242afda2bda Mon Sep 17 00:00:00 2001 From: Jarkko Paso Date: Mon, 7 Oct 2019 13:08:20 +0300 Subject: [PATCH 224/227] Merge commit 'ffb05c770964013a9f1ee9fb89d25e9fd09e886d' * commit 'ffb05c770964013a9f1ee9fb89d25e9fd09e886d': Squashed 'features/nanostack/coap-service/' changes from e9edb1b..b919a33 --- .../coap-service/test/coap-service/unittest/makefile_defines.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/features/nanostack/coap-service/test/coap-service/unittest/makefile_defines.txt b/features/nanostack/coap-service/test/coap-service/unittest/makefile_defines.txt index 9b6e5a0a500..dc1f53eb308 100755 --- a/features/nanostack/coap-service/test/coap-service/unittest/makefile_defines.txt +++ b/features/nanostack/coap-service/test/coap-service/unittest/makefile_defines.txt @@ -33,6 +33,7 @@ INCLUDE_DIRS =\ ../../../../../event-loop/source/ \ ../../../../../mbedtls/include/ \ ../../../../../mbedtls/include/mbedtls/ \ + ../../../../../mbedtls/crypto/include/ \ /usr/include\ $(CPPUTEST_HOME)/include\ From 070269295f8755c650ed31f99efc03b53b89e6c2 Mon Sep 17 00:00:00 2001 From: adbridge Date: Wed, 16 Oct 2019 12:10:38 +0100 Subject: [PATCH 225/227] Add OKDO platform Manually ported from PR11407 --- .../TARGET_OKDO_ODIN_W2/PinNames.h | 236 ++++++++++++++++++ targets/targets.json | 6 + 2 files changed, 242 insertions(+) create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_OKDO_ODIN_W2/PinNames.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_OKDO_ODIN_W2/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_OKDO_ODIN_W2/PinNames.h new file mode 100644 index 00000000000..acb231a0d91 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_OKDO_ODIN_W2/PinNames.h @@ -0,0 +1,236 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PA_0 = 0x00, PA_1 = 0x01, PA_2 = 0x02, PA_3 = 0x03, + PA_4 = 0x04, PA_5 = 0x05, PA_6 = 0x06, PA_7 = 0x07, + PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, PA_11 = 0x0B, + PA_12 = 0x0C, PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, + + PB_0 = 0x10, PB_1 = 0x11, PB_2 = 0x12, PB_3 = 0x13, + PB_4 = 0x14, PB_5 = 0x15, PB_6 = 0x16, PB_7 = 0x17, + PB_8 = 0x18, PB_9 = 0x19, PB_10 = 0x1A, PB_11 = 0x1B, + PB_12 = 0x1C, PB_13 = 0x1D, PB_14 = 0x1E, PB_15 = 0x1F, + + PC_0 = 0x20, PC_1 = 0x21, PC_2 = 0x22, PC_3 = 0x23, + PC_4 = 0x24, PC_5 = 0x25, PC_6 = 0x26, PC_7 = 0x27, + PC_8 = 0x28, PC_9 = 0x29, PC_10 = 0x2A, PC_11 = 0x2B, + PC_12 = 0x2C, PC_13 = 0x2D, PC_14 = 0x2E, PC_15 = 0x2F, + + PD_0 = 0x30, PD_1 = 0x31, PD_2 = 0x32, PD_3 = 0x33, + PD_4 = 0x34, PD_5 = 0x35, PD_6 = 0x36, PD_7 = 0x37, + PD_8 = 0x38, PD_9 = 0x39, PD_10 = 0x3A, PD_11 = 0x3B, + PD_12 = 0x3C, PD_13 = 0x3D, PD_14 = 0x3E, PD_15 = 0x3F, + + PE_0 = 0x40, PE_1 = 0x41, PE_2 = 0x42, PE_3 = 0x43, + PE_4 = 0x44, PE_5 = 0x45, PE_6 = 0x46, PE_7 = 0x47, + PE_8 = 0x48, PE_9 = 0x49, PE_10 = 0x4A, PE_11 = 0x4B, + PE_12 = 0x4C, PE_13 = 0x4D, PE_14 = 0x4E, PE_15 = 0x4F, + + PF_0 = 0x50, PF_1 = 0x51, PF_2 = 0x52, PF_3 = 0x53, + PF_4 = 0x54, PF_5 = 0x55, PF_6 = 0x56, PF_7 = 0x57, + PF_8 = 0x58, PF_9 = 0x59, PF_10 = 0x5A, PF_11 = 0x5B, + PF_12 = 0x5C, PF_13 = 0x5D, PF_14 = 0x5E, PF_15 = 0x5F, + + PG_0 = 0x60, PG_1 = 0x61, PG_2 = 0x62, PG_3 = 0x63, + PG_4 = 0x64, PG_5 = 0x65, PG_6 = 0x66, PG_7 = 0x67, + PG_8 = 0x68, PG_9 = 0x69, PG_10 = 0x6A, PG_11 = 0x6B, + PG_12 = 0x6C, PG_13 = 0x6D, PG_14 = 0x6E, PG_15 = 0x6F, + + PH_0 = 0x70, PH_1 = 0x71, PH_2 = 0x72, PH_3 = 0x73, + PH_4 = 0x74, PH_5 = 0x75, PH_6 = 0x76, PH_7 = 0x77, + PH_8 = 0x78, PH_9 = 0x79, PH_10 = 0x7A, PH_11 = 0x7B, + PH_12 = 0x7C, PH_13 = 0x7D, PH_14 = 0x7E, PH_15 = 0x7F, + + // Not connected + NC = (int)0xFFFFFFFF, + + // Module Pins + // PortA + P_A1 = NC, + P_A2 = NC, + P_A3 = NC, + P_A4 = NC, + P_A5 = PC_2, + P_A6 = PF_2, + P_A7 = PE_0, + P_A8 = PB_6, + P_A9 = PB_8, + P_A10 = PA_11, + P_A11 = PA_9, + P_A12 = PA_12, + P_A13 = PA_10, + P_A14 = PD_9, + P_A15 = PD_8, + P_A16 = PD_11, + P_A17 = PD_12, + P_A18 = PA_3, + // PortB + P_B1 = NC, + P_B2 = NC, + P_B3 = NC, + P_B4 = NC, + P_B5 = NC, + P_B6 = NC, + P_B7 = NC, + P_B8 = NC, + // PortC + P_C1 = NC, + P_C2 = NC, + P_C3 = NC, + P_C4 = NC, + P_C5 = PG_4, + P_C6 = PE_13, + P_C7 = NC, + P_C8 = PE_12, + P_C9 = NC, + P_C10 = PE_14, + P_C11 = PE_11, + P_C12 = PE_9, + P_C13 = PF_6, + P_C14 = PC_1, + P_C15 = PA_2, + P_C16 = PF_7, + P_C17 = PF_1, + P_C18 = PF_0, + // PortD + P_D1 = PB_12, + P_D2 = PB_13, + P_D3 = PB_11, + P_D4 = PA_7, + P_D5 = PC_4, + P_D6 = PC_5, + P_D7 = NC, + P_D8 = PA_1, + // TestPads + P_TP5 = PB_4, + P_TP7 = PA_13, + P_TP8 = PA_15, + P_TP9 = PA_14, + P_TP10 = PB_3, + //P_TP11, // BOOT0 + + // Mbed pins + LED_RED = PE_0, + LED_GREEN = PB_6, + LED_BLUE = PB_8, + + LED1 = LED_RED, + LED2 = LED_GREEN, + LED3 = LED_BLUE, + + SW1 = PF_2, + + // Standardized button names + BUTTON1 = SW1, + + I2C_SDA = PF_0, + I2C_SCL = PF_1, + + SPI0_MOSI = PE_14, + SPI0_MISO = PE_13, + SPI0_SCK = PE_12, + SPI0_CS = PE_11, //CS for SPI Flash on MCB + SPI1_CS = PE_9, //CS for LCD on MTB + SPI2_CS = PG_4, //CS for SD card on MTB + + SPI_MOSI = SPI0_MOSI, + SPI_MISO = SPI0_MISO, + SPI_SCK = SPI0_SCK, + SPI_CS = SPI0_CS, + + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#elif MBED_CONF_TARGET_USB_TX + STDIO_UART_TX = MBED_CONF_TARGET_USB_TX, +#else + STDIO_UART_TX = PA_9, +#endif + +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#elif MBED_CONF_TARGET_USB_RX + STDIO_UART_TX = MBED_CONF_TARGET_USB_RX, +#else + STDIO_UART_RX = PA_10, +#endif + + // DAPLink + USBRX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + SWDIO = PA_15, + SWCLK = PA_14, + NTRST = PB_4, + + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + ADC_VBAT = 0xF2, + + //Right side (top view) + GND = NC, + GP10 = NC, + RTS = NC, + CTS = NC, + GP7 = P_C12, //LCD CS on MTB + GP6 = P_A12, //LCD Reset on MTB + GP5 = P_A10, //LCD A0 on MTB + GP4 = P_A17, + TX2 = NC, + RX2 = NC, + SDA2 = NC, + SCL2 = NC, + MOSI2 = NC, + MISO2 = NC, + SCK2 = NC, + GP3 = P_A16, + GP2 = P_C5, //CS for SD Card on MTB + PWM2 = LED_GREEN, + PWM1 = LED_BLUE, + PWM0 = LED_RED, + +} PinName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/targets.json b/targets/targets.json index 3bf1370fdd2..2f25f7aa4bf 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -4875,6 +4875,12 @@ "overrides": {"lse_available": 0}, "release_versions": ["5"] }, + "OKDO_ODIN_W2": { + "inherits": ["MODULE_UBLOX_ODIN_W2"], + "device_has_add": [], + "overrides": {"lse_available": 0}, + "release_versions": ["5"] + }, "UBLOX_C030": { "inherits": ["FAMILY_STM32"], "supported_form_factors": ["ARDUINO"], From 455bb9ec68baa608c1121c1e2dc23d68fd79a58e Mon Sep 17 00:00:00 2001 From: adbridge Date: Wed, 16 Oct 2019 12:31:35 +0100 Subject: [PATCH 226/227] "Update secure binaries for LPC55S69_S (ARMC6)" --- .../prebuilt/crypto_access_control.bin | Bin 163520 -> 163520 bytes .../TARGET_M33_NS/prebuilt/spm_client.bin | Bin 163520 -> 163520 bytes .../TARGET_M33_NS/prebuilt/spm_server.bin | Bin 163520 -> 163520 bytes .../TARGET_M33_NS/prebuilt/spm_smoke.bin | Bin 163520 -> 163520 bytes .../TARGET_M33_NS/prebuilt/tfm.bin | Bin 163520 -> 163520 bytes 5 files changed, 0 insertions(+), 0 deletions(-) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/prebuilt/crypto_access_control.bin b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/prebuilt/crypto_access_control.bin index 06ab9e46edf453abc62d3ba0b670182b2807f4b4..a9e95e63a32a01708a20ac1966c901e776657db7 100644 GIT binary patch delta 19348 zcmZ|13tZGi_dh;o*=4!PA|N0jyIf@PlAxKWnG5OynR(A!7N#b6Nh~eR4DgbgmHK?D z!OGOEM9qXYLQ+CAyFBJ2WIoze)C|ckA5#2$_Wpa%F7|z%{?C73ufu#kGiT16nK^UL znKSd@s5|(mJGgo&=`3DiMbZk|MdzdhjVYp+BjAWvY4eh-bq34#*hXt|HB@SQUi%$U znyn;oKhbn4CTKBjmDUA~q50C8pf5DPG)S)p$I&xVU2qc3ww(>`O>|kJ&@yV0Dnirg z3EQ5~Y#lAPePcLHlrHV-s&hCy)}-Z>2@CvGlC8E_O-kaqqwy z^KxcZn>8(S5(DJJ-sl>m@4ew_sU^f1AipQY#|;fx>1eoGZV8s1_0j`z570QNA#PLT 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z4L)J18Hvya$fNOp{A&u0s@?7(>YJR=hr;{XNEhkfM;EUPP7W(lk7%<-_tBpViJr7L zqmSuam*{TOqbJe$kh9U<-X5PEojm>=MNcwjAXPGu`13u=ZZffG2+~lWz4l}M@=%H_4{QEw3f8qR-Woet3GbevyODE cH@&F*+91k*Q(idIo*wT= Date: Wed, 16 Oct 2019 13:00:44 +0100 Subject: [PATCH 227/227] "Update secure binaries for ARM_MUSCA_A1_S (ARMC6)" --- .../prebuilt/crypto_access_control.bin | Bin 521888 -> 521888 bytes .../prebuilt/spm_client.bin | Bin 521888 -> 521888 bytes .../prebuilt/spm_server.bin | Bin 521888 -> 521888 bytes .../TARGET_MUSCA_A1_NS/prebuilt/spm_smoke.bin | Bin 521888 -> 521888 bytes .../TARGET_MUSCA_A1_NS/prebuilt/tfm.bin | Bin 521888 -> 521888 bytes 5 files changed, 0 insertions(+), 0 deletions(-) diff --git a/targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/TARGET_MUSCA_A1_NS/prebuilt/crypto_access_control.bin b/targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/TARGET_MUSCA_A1_NS/prebuilt/crypto_access_control.bin index 82d4d2c8ab827212c546dc305086dca1ba4a4724..0206d254489ea7194e67492a33984ec95e0e29ff 100644 GIT binary patch delta 20648 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VersionChangesReason for Change
2.20Fix configuration register value restoring in resume routine after +* Deep Sleep. +* Fix issue that USB Device stops working in DMA modes after wake up +* from Deep Sleep. +*
The LPM requests are ignored after wake up from Deep Sleep and the +* host starts sending SOFs.Updated \ref Cy_USBFS_Dev_Drv_Resume function to restore LPM control +* register after exit Deep Sleep. +*
2.10Returns the data toggle bit into the previous state after detecting * that the host is retrying an OUT transaction.
2.0The list of changes to support the MBED-OS USB Device stack is provided below: * - Changed the processing of the control transfers. @@ -744,7 +761,7 @@ extern "C" { #define CY_USBFS_VERSION_MAJOR (2) /** USBFS Driver minor version */ -#define CY_USBFS_VERSION_MINOR (10) +#define CY_USBFS_VERSION_MINOR (20) /** USBFS Driver identifier */ #define CY_USBFS_ID CY_PDL_DRV_ID(0x3BU) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_usbfs_dev_drv_pvt.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_usbfs_dev_drv_pvt.h index ab7fd88b6aa..ad42bfc2772 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_usbfs_dev_drv_pvt.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_usbfs_dev_drv_pvt.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_usbfs_dev_drv_pvt.h -* \version 2.10 +* \version 2.20 * * Provides API declarations of the USBFS driver. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_usbfs_dev_drv_reg.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_usbfs_dev_drv_reg.h index 1f07ed7b756..3f87d10b22a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_usbfs_dev_drv_reg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_usbfs_dev_drv_reg.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_usbfs_dev_drv_reg.h -* \version 2.10 +* \version 2.20 * * Provides register access API implementation of the USBFS driver. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_prot.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_prot.c index 2e4051b7909..4731fa74024 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_prot.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_prot.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_prot.c -* \version 1.30 +* \version 1.30.1 * * \brief * Provides an API implementation of the Protection Unit driver diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sysclk.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sysclk.c index 9ac04d8c48a..6d49d85fc7a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sysclk.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sysclk.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_sysclk.c -* \version 1.40.1 +* \version 1.40.2 * * Provides an API implementation of the sysclk driver. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sysint.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sysint.c index af8b9987e25..834b111affc 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sysint.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sysint.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_sysint.c -* \version 1.20 +* \version 1.30 * * \brief * Provides an API implementation of the SysInt driver. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_usbfs_dev_drv.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_usbfs_dev_drv.c index 3d51a74904b..7bec02a2b66 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_usbfs_dev_drv.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_usbfs_dev_drv.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_usbfs_dev_drv.c -* \version 2.10 +* \version 2.20 * * Provides general API implementation of the USBFS driver. * @@ -1273,6 +1273,8 @@ void Cy_USBFS_Dev_Drv_Suspend(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t * *******************************************************************************/ void Cy_USBFS_Dev_Drv_Resume(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t *context) { + uint32_t lpmCtl; + /* Enables the clock to mxusbfs IP */ USBFS_DEV_USB_CLK_EN(base) = CY_USBFS_DEV_DRV_WRITE_ODD(USBFS_USBDEV_USB_CLK_EN_CSR_CLK_EN_Msk); @@ -1285,6 +1287,10 @@ void Cy_USBFS_Dev_Drv_Resume(USBFS_Type *base, cy_stc_usbfs_dev_drv_context_t *c /* Restores the data endpoints configuration */ RestoreDeviceConfiguration(base, context); + /* Cypress ID# 337915: Restore response to LPM packets */ + lpmCtl = USBFS_DEV_LPM_LPM_CTL(base); + USBFS_DEV_LPM_LPM_CTL(base) = lpmCtl; + /* Releases PHY from suspend mode */ USBFS_DEV_LPM_POWER_CTL(base) &= ~USBFS_USBLPM_POWER_CTL_SUSPEND_Msk; (void) USBFS_DEV_LPM_POWER_CTL(base); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_usbfs_dev_drv_io.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_usbfs_dev_drv_io.c index 1cbd0066cb8..9e73999444f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_usbfs_dev_drv_io.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_usbfs_dev_drv_io.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_usbfs_dev_drv_io.c -* \version 2.10 +* \version 2.20 * * Provides data transfer API implementation of the USBFS driver. * @@ -139,6 +139,8 @@ void Cy_USBFS_Dev_Drv_ConfigDevice(USBFS_Type *base, cy_stc_usbfs_dev_drv_contex /* The configuration completes: Generates a rising edge for the USBDEV_ARB_CFG.CFG_CMP bit */ USBFS_DEV_ARB_CFG(base) = _VAL2FLD(USBFS_USBDEV_ARB_CFG_DMA_CFG, context->mode) | autoMemMask; + /* Read the register to ensure that the write is flushed out to the hardware */ + (void) USBFS_DEV_ARB_CFG(base); USBFS_DEV_ARB_CFG(base) |= USBFS_USBDEV_ARB_CFG_CFG_CMP_Msk; (void) USBFS_DEV_ARB_CFG(base); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_usbfs_dev_drv_io_dma.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_usbfs_dev_drv_io_dma.c index 35c887d4a4d..d264894730f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_usbfs_dev_drv_io_dma.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_usbfs_dev_drv_io_dma.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_usbfs_dev_drv_io_dma.c -* \version 2.10 +* \version 2.20 * * Provides data transfer API implementation of the USBFS driver. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/connectivity_wifi-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/connectivity_wifi-1.0.cypersonality index fd92874cd5c..e7c3c534176 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/connectivity_wifi-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/connectivity_wifi-1.0.cypersonality @@ -157,9 +157,9 @@ + default="`${toHex($idx == 0 ? (minKeepFilt ? 0x0806 : 0x800) : + $idx == 1 ? (minKeepFilt ? 0x888e : 0x800) : + 0x800)}`" visible="`${config$idx && (filter$idx_type eq CY_PF_PORT_ETHER_TYPE_FILTER)}`" editable="`${config$idx_editable}`" desc="Enter a 16-bit ether type value. Example: 0x800 for IP, 0x806 for ARP." /> + + 0x00000000 + 0x000 + 0 + 0 + CortexM3 + Cypress + 0 + 524288 + 63-WLBGA + 63 + 2400 + 4800 + The CYW43438KUBG device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43438/CYW43438KUBG/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43438/CYW43438KUBG/info.xml new file mode 100644 index 00000000000..bade276acc7 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43438/CYW43438KUBG/info.xml @@ -0,0 +1,6 @@ + + + CYW43438KUBG + The CYW43438KUBG devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43438/CYW43438KUBG/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43438/CYW43438KUBG/studio/presentation new file mode 100644 index 00000000000..5ec34f1652b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43438/CYW43438KUBG/studio/presentation @@ -0,0 +1,2 @@ +Connectivity +43438 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43438/CYW43438KUBG/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43438/CYW43438KUBG/studio/view.xml new file mode 100644 index 00000000000..c50aafc2e4a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43438/CYW43438KUBG/studio/view.xml @@ -0,0 +1,23 @@ + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43438/hobto/ipblocks.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43438/hobto/ipblocks.cydata index 716e5a570d7a659fdd59863951b18c54b0e23243..4a1e4211a638503885cc1ef9af53dc082a42f000 100644 GIT binary patch delta 14 WcmbQtGMQz9IJ3mmPaCCvG6Dc2$OSzB delta 14 VcmbQtGMQz9ICI-(fsIl>837{{1m^$% diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43438/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43438/info.xml new file mode 100644 index 00000000000..a66973f979d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43438/info.xml @@ -0,0 +1,5 @@ + + + 43438 + The 43438 devices + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43438/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43438/studio/view.xml new file mode 100644 index 00000000000..cdc66e3e2db --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43438/studio/view.xml @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343W/hobto/ipblocks.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343W/hobto/ipblocks.cydata index 414edc5adfe4741c0208dfd457cd2cac59510601..dc13b6a85dbea0b5c436f663963678f1ff91af9c 100644 GIT binary patch delta 14 WcmbQtGMQz9IJ3mmPaCCvG6Dc2$OSzB delta 14 VcmbQtGMQz9ICI-(fsIl>837{{1m^$% diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/studio/connectivity/43xxx_bt_v1.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/studio/connectivity/43xxx_bt_v1.cydata index 9f3f145e62190c7f32ff7fc9c51086a77e8ed16e..bb290d891c73ddfe4caefcb80a9ee27d068036b4 100644 GIT binary patch delta 13 VcmbQtG?{6FIJ4B$PZOnn0stNh1sVVV delta 13 UcmbQtG?{6FICIlxfr(N-0Ue11z5oCK diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/studio/connectivity/43xxx_coex_v1.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/studio/connectivity/43xxx_coex_v1.cydata index e794ee03daab228d9b8cc2544b1ebf83a1693e74..05cf58d18fdd6c5ce427b5a124aabb1d7d9e7b7d 100644 GIT binary patch delta 13 VcmbQtG?{6FIJ4B$PZOnn0stNh1sVVV delta 13 UcmbQtG?{6FICIlxfr(N-0Ue11z5oCK diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/studio/connectivity/43xxx_wifi_v1.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/studio/connectivity/43xxx_wifi_v1.cydata index 4121b5925dbbf15fd6d04a2ce14291b8c713493a..20b3f5c92ff1eb7bcb478615959edd0ce3e193c2 100644 GIT binary patch delta 13 VcmbQtG?{6FIJ4B$PZOnn0stNh1sVVV delta 13 UcmbQtG?{6FICIlxfr(N-0Ue11z5oCK diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-D44/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-D44/info.xml deleted file mode 100644 index 2ab891b2cbe..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-D44/info.xml +++ /dev/null @@ -1,6 +0,0 @@ - - - CYB0644ABZI-D44 - The CYB0644ABZI-D44 devices - true - \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-D44/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/base/view.xml similarity index 81% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-D44/base/view.xml rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/base/view.xml index 9d1e14301b9..9e4a8b3ad5a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-D44/base/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/base/view.xml @@ -6,11 +6,11 @@ 1 CortexM0p,CortexM4 Cypress - 2097152 + 1900544 1048576 124-BGA 124 1700 3600 - The CYB0644ABZI-D44 device. + The CYB0644ABZI-S2D44 device. \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/info.xml new file mode 100644 index 00000000000..91435aa73d1 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/info.xml @@ -0,0 +1,6 @@ + + + CYB0644ABZI-S2D44 + The CYB0644ABZI-S2D44 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/studio/presentation new file mode 100644 index 00000000000..6a8bdde3e3d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 64 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-D44/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/studio/view.xml similarity index 94% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-D44/studio/view.xml rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/studio/view.xml index 7bb0648dbbe..1940a0f73d6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-D44/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/studio/view.xml @@ -1,14 +1,14 @@ - + - + - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/hobto/amuxbus.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/hobto/amuxbus.cydata index 1969b056d76bbf12dd4c959823f8c0b82fc5a0b7..c2b08046cda1ee6049a42bd2baf52eea24f4e003 100644 GIT binary patch delta 14 WcmcaDdRugYIJ3mmPaCBUasdD=Nd>?F delta 14 VcmcaDdRugYICI-(fsIlJxd1Db1!@2Q diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/hobto/clocks.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/hobto/clocks.cydata index 5d58568447f1e16069d5bcc0a1ceb3d42381d98f..3849b150f16ef323edc25613a78ab76fd83f5125 100644 GIT binary patch delta 14 WcmaFP{hWJ(IJ3mmPaCDqvH}1sqy@_W delta 14 VcmaFP{hWJ(ICI-(fsImUSph5X1$6)b diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/hobto/dsi.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/hobto/dsi.cydata index 1144c17e5c28b46884f7afccda532cebb6e01580..d5a7718bb7fd30b756e78635cca3cd17e802ff5f 100644 GIT binary patch delta 13 VcmbQtG?{6FIJ3mmPZOnn0stNV1sDJT delta 13 UcmbQtG?{6FICI-(fr(N-0Ue + + 0xE70E + 0x105 + 1 + 1 + CortexM0p,CortexM4 + Cypress + 524288 + 262144 + 100-TQFP + 100 + 1700 + 3600 + The CY8C6245W-S3D72 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/info.xml new file mode 100644 index 00000000000..1204849e13d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/info.xml @@ -0,0 +1,6 @@ + + + CY8C6245W-S3D72 + The CY8C6245W-S3D72 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-D44/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/studio/presentation similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-D44/studio/presentation rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/studio/presentation diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/studio/view.xml new file mode 100644 index 00000000000..2729e899146 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/studio/view.xml @@ -0,0 +1,60 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CYB06445LQI-S3D42/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CYB06445LQI-S3D42/base/view.xml new file mode 100644 index 00000000000..667ceb310db --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CYB06445LQI-S3D42/base/view.xml @@ -0,0 +1,16 @@ + + + 0xE70D + 0x105 + 1 + 1 + CortexM0p,CortexM4 + Cypress + 524288 + 262144 + 68-QFN + 68 + 1700 + 3600 + The CYB06445LQI-S3D42 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CYB06445LQI-S3D42/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CYB06445LQI-S3D42/info.xml new file mode 100644 index 00000000000..d9684d8c4de --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CYB06445LQI-S3D42/info.xml @@ -0,0 +1,6 @@ + + + CYB06445LQI-S3D42 + The CYB06445LQI-S3D42 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CYB06445LQI-S3D42/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CYB06445LQI-S3D42/studio/presentation new file mode 100644 index 00000000000..6a8bdde3e3d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CYB06445LQI-S3D42/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 64 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CYB06445LQI-S3D42/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CYB06445LQI-S3D42/studio/view.xml new file mode 100644 index 00000000000..3a4e2ece26b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CYB06445LQI-S3D42/studio/view.xml @@ -0,0 +1,60 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/hobto/amuxbus.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/hobto/amuxbus.cydata index d66bc3817d3b702fc1a0fd5bd979a7ff72f112b3..972a771b9887af49337e70c2ce4749222731fab1 100644 GIT binary patch delta 14 VcmZqYZRedJ&MYzY(?+RWHUJ`31h4=A delta 14 VcmZqYZRedJ&fKy&MYzY(?+RM762mC1iky&fK1 CortexM0p,CortexM4 Cypress - 1048576 + 851968 294912 116-BGA-BLE 116 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD53/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD53/studio/view.xml index 79127663aca..21d084ff40b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD53/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD53/studio/view.xml @@ -8,7 +8,7 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD54/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD54/base/view.xml index 5986ad24862..a1f9392ce83 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD54/base/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD54/base/view.xml @@ -6,7 +6,7 @@ 1 CortexM0p,CortexM4 Cypress - 1048576 + 851968 294912 124-BGA-SIP 124 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD54/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD54/studio/view.xml index 32a87b718eb..4b289cf509e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD54/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD54/studio/view.xml @@ -8,7 +8,7 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-D54/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-D54/base/view.xml index 4f18e77b864..884495df5b4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-D54/base/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-D54/base/view.xml @@ -6,7 +6,7 @@ 1 CortexM0p,CortexM4 Cypress - 1048576 + 851968 294912 124-BGA 124 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-D54/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-D54/studio/view.xml index d4b3c4f7fbe..f0451972da3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-D54/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-D54/studio/view.xml @@ -8,7 +8,7 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/hobto/amuxbus.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/hobto/amuxbus.cydata index dacfb41ed13b6d1ac2ccf9d9cff171b2fd592394..d7b8d5103112a611cdddaaa9f1cf14d5a6791309 100644 GIT binary patch delta 14 Vcmdlfwo`0^IJ3mmPaCD=xdA7t1l<4t delta 14 Vcmdlfwo`0^ICI-(fsIn~+yEx_1cv|s diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/hobto/clocks.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/hobto/clocks.cydata index 120e2c637e7dfa64cfef6bda8795d357a5acc8e7..149b4663f992d40fbf519dff9f0990b07465329c 100644 GIT binary patch delta 14 Wcmey#{gZowIJ3mmPaCD~vjPAvoCW~^ delta 14 Vcmey#{gZowICI-(fsIo4SphBR1*-r6 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/hobto/dsi.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/hobto/dsi.cydata index 580a8fa32a10cf81282cf65619e535c43b0f891d..7a8fab992c60a33d74e19b4c86c1b603991a86aa 100644 GIT binary patch delta 14 WcmbPfG1Fp#IJ3mmPaCEFO9KEYY6Z~% delta 14 VcmbPfG1Fp#ICI-(fsIoCr2#0m1$zJh diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/hobto/interrupts.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/hobto/interrupts.cydata index b3009214e8891339970f906b98f0dc1dc0756ec9..a0d21bfc664d38ab44f5d618969558e1f4a3aa2b 100644 GIT binary patch delta 14 WcmdlgxK(h1IJ3mmPaCCXa{vG*zXe19 delta 14 VcmdlgxK(h1ICI-(fsInLIRGaM1nvL; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/hobto/ipblocks.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/hobto/ipblocks.cydata index 8dd500408779ad64fe222f5fb88fa552b3c82ab1..059dc04d00a5dd6f14cd39fc4f52bb1ca81923a3 100644 GIT binary patch delta 16 Xcmdnpz_`1Cae_Fr#MDn4r4$_iHPZ#| delta 16 Xcmdnpz_`1Cae_E=+h&1{Qi=`$H6I0- diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/hobto/pins.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/hobto/pins.cydata index ce7bbbc49b5a55bf9dc4ce6d9d27804fca0e5c79..d9d8457191de043af46c3a8725dbd46b2e6c1b7b 100644 GIT binary patch delta 16 XcmaFd!1TC*X@WSj#MDn4r92w|I|K%( delta 16 XcmaFd!1TC*X@WR&+h&1{Ql1R}I#32u diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/hobto/triggers.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/hobto/triggers.cydata index 16fbc2da8671706588e606cc9ff516ca4dbe1f4b..2e47f64a85d0c41601e296d01ef59d78e9769ce1 100644 GIT binary patch delta 16 Xcmdnpz_`1Cae_Fr#MDn4r4$_iHPZ#| delta 16 Xcmdnpz_`1Cae_E=+h&1{Qi=`$H6I0- diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/studio/modules/module_43-SMT.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/studio/modules/module_43-SMT.cydata index 4fba5b69165abbca63610dc6526293b8c0676765..ca27bc7ddd8e987af908eadf6ae41135c9c6a084 100644 GIT binary patch delta 14 VcmaFO^O|RZIJ4B$PaCBI*#Im%1zZ3C delta 14 VcmaFO^O|RZICIlxfsImuYyc}=1poj5 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/m4cpuss_v1-dw0.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/m4cpuss_v1-dw0.cydata index d45dd5e2d900dc72837f9b5f255d1be333b97f12..51d97af74e6c8a8fffa51123018854ee4d19a332 100644 GIT binary patch delta 14 WcmbQtGMQz9IJ4B$PaCCvG6Dc2)&)NR delta 14 VcmbQtGMQz9ICIlxfsIl>837{r1mgez diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/m4cpuss_v1-dw1.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/m4cpuss_v1-dw1.cydata index 2d58780962cdb81741cd63c0dd5f32ba4fb7dd90..a820a30f696eae074ae8c06186d0030221618bcc 100644 GIT binary patch delta 14 WcmbQtGMQz9IJ4B$PaCCvG6Dc2)&)NR delta 14 VcmbQtGMQz9ICIlxfsIl>837{r1mgez diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/m4cpuss_v1.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/m4cpuss_v1.cydata index ff8a295016161f2a56e352b282d199961541b07c..56e0d87fc76e302fa554797ee7962044ab640a08 100644 GIT binary patch delta 14 VcmZ3^yPS7|IJ4B$PaCCr*#ITu1rh)N delta 14 VcmZ3^yPS7|ICIlxfsInVYyc$%1hxPG diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/m4cpuss_ver2_v1-dmac.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/m4cpuss_ver2_v1-dmac.cydata index 39f91fc0993eae70e71530a650876d4e37053dc0..9fed15246174aa2dbc95e08de1587370a097a496 100644 GIT binary patch delta 14 WcmbQtGMQz9IJ4B$PaCCvG6Dc2)&)NR delta 14 VcmbQtGMQz9ICIlxfsIl>837{r1mgez diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/m4cpuss_ver2_v1-dw0.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/m4cpuss_ver2_v1-dw0.cydata index ea890ce468ec80acb02a29db5636ee2628e18872..8351b31aa4762765a46e7684f5b47833f60daaca 100644 GIT binary patch delta 14 WcmbQtGMQz9IJ4B$PaCCvG6Dc2)&)NR delta 14 VcmbQtGMQz9ICIlxfsIl>837{r1mgez diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/m4cpuss_ver2_v1-dw1.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/m4cpuss_ver2_v1-dw1.cydata index c0e1be55d46407fc78be4597be35e0e7e6fbcbb1..ab7d5dbaefe41b2888598a931863346bd2fd2882 100644 GIT binary patch delta 14 WcmbQtGMQz9IJ4B$PaCCvG6Dc2)&)NR delta 14 VcmbQtGMQz9ICIlxfsIl>837{r1mgez diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/m4cpuss_ver2_v1.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/m4cpuss_ver2_v1.cydata index 7ff3ec57263d36bd6729ea96af189c89d44576a5..da9447e2c99def8c10509406654231440e90f310 100644 GIT binary patch delta 14 VcmbQwH=l2UIJ4B$PaCCJ*#RUR1bqMi delta 14 VcmbQwH=l2UICIlxfsInE>;NM^1R($b diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxaudioss_v1.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxaudioss_v1.cydata index 0f80931581a6242fbcef4bedb24df3777510f437..bb405a277583e0c4cd3da660b2567d7851f3121b 100644 GIT binary patch delta 14 VcmdnYwV7*zIJ4B$PaCBqSpg;L1g`)9 delta 14 VcmdnYwV7*zICIlxfsIm837{r1mgez diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxcsdv2_v1.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxcsdv2_v1.cydata index 7450d1a297ddcb0175588460e7010656bff3a6ee..d191fa106f155bc4fef84f8a7b741ae8b13ce00c 100644 GIT binary patch delta 14 Vcmey*_n&WqIJ4B$PaCCD*#Rz`1)Tr@ delta 14 Vcmey*_n&WqICIlxfsInB>;Nsk1wjA+ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxefuse_v1.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxefuse_v1.cydata index 9c7f22ab1a2ddf8289595ce955e6b475883f630e..24968ac70f6afcbe571353cc2af4f5b77248d1d3 100644 GIT binary patch delta 13 VcmbQtG?{6FIJ4B$PZOnn0stNh1sVVV delta 13 UcmbQtG?{6FICIlxfr(N-0Ue11z5oCK diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxlcd_v1.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxlcd_v1.cydata index 31b263aba2eb6e6f3fe00c716517ebb2ec77f389..fede36b62d806d3cc9829cef0f7cdb01f6d1495e 100644 GIT binary patch delta 14 WcmZ3_xt?=^IJ4B$PaCDCvH$=kVFe%n delta 14 VcmZ3_xt?=^ICIlxfsImASpX%21jGOU diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxlcd_ver2_v1.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxlcd_ver2_v1.cydata index ec995c82565df08a283f43c390ee4da4ee83813b..83da1259b4fc1f6cb175795355856fc4e08d0215 100644 GIT binary patch delta 14 Wcmcc3d7E>BIJ4B$PaCBUvH$=pF$JUm delta 14 Vcmcc3d7E>BICIlxfsIlJSpX_i1xNq@ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxlpcomp_s40.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxlpcomp_s40.cydata index ada859eebe8efad326f4939a5c4d71cbcdfacfac..3e4e10c111bc57fc0e8acdbe3bb208fbb570d1e5 100644 GIT binary patch delta 14 WcmX@feUf{EIJ4B$PaCDyvjPAqY6Wuu delta 14 VcmX@feUf{EICIlxfsIn@Spg`F1s4DS diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxperi_v1.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxperi_v1.cydata index de8546bff8e4ab5a6230a6a6f18edf01d1e9e8d0..64dfe0006edd63b2d66322bde8b294775694e3a2 100644 GIT binary patch delta 14 Vcmcb~ag$?$IJ4B$PaCD|SpX^F1snhX delta 14 Vcmcb~ag$?$ICIlxfsIo3EC4A31i%0Q diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxperi_ver2_v1.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxperi_ver2_v1.cydata index dcb6853c8aef754e1702d99a539555873a6efed5..480fe8bcced048b123d4acf3b0d4e9e8c33dd857 100644 GIT binary patch delta 14 Vcmey#@sneMIJ4B$PaCD;SpY3z1$+Pi delta 14 Vcmey#@sneMICIlxfsIn}EC4Kn1t0(b diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxprofile_v1.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxprofile_v1.cydata index 216e69b61c61bdb9ce6f431f3d7de3be1d574f45..7559ecc90036d2055dc7d0eb8e28b75a315a6fd0 100644 GIT binary patch delta 14 WcmbQtGMQz9IJ4B$PaCCvG6Dc2)&)NR delta 14 VcmbQtGMQz9ICIlxfsIl>837{r1mgez diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxs40ioss_v1-port.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxs40ioss_v1-port.cydata index be738ff04148af95e2244d7ee1d2ae74421a8928..c720b9ef0c361cd1b6bbac4de88016fe90efde27 100644 GIT binary patch delta 14 WcmbQJFi~NGIJ4B$PaCDa^8)}TOa*@c delta 14 VcmbQJFi~NGICIlxfsIn%`2i(v1tS0e diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxs40ioss_v1.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxs40ioss_v1.cydata index 36405c931c219bf75865a4ed4efe5d8523476b9e..fa54cc0cd5db2e35371a18c5a161518c25bb1c3d 100644 GIT binary patch delta 14 Wcmcc0dzE*BIJ4B$PaCCnvjG4q>jj(u delta 14 Vcmcc0dzE*BICIlxfsInT*#IgH1wa4* diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxs40ioss_v2-port.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxs40ioss_v2-port.cydata index 74431715b428ad9a3a0829b9569648438d1217f8..21a33bb364e7633d3b94822c9e738a3880ad24ac 100644 GIT binary patch delta 14 WcmbQKFjHZIIJ4B$PaCEF^8)}UECrVU delta 14 VcmbQKFjHZIICIlxfsIoC`2i+Q1v>x$ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxs40ioss_v2.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxs40ioss_v2.cydata index 7a1691fe4b044f8a9258eabf48a9cecaa9cd7b82..9ef6d1f207998ac30acb547036e680ba9549f966 100644 GIT binary patch delta 14 Vcmdnbx1Vo;NXd1c3km diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxs40pass_v1-ctbm.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxs40pass_v1-ctbm.cydata index 2e20dc0911e830c819c08c4bed5bf752c12aaecb..c7afe436d425035ca56421b40354164022de21b5 100644 GIT binary patch delta 14 VcmeAa?G&9L&MY;NM^1cd+q diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxs40srss_v1.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxs40srss_v1.cydata index d88aa1322fcd2f875dd362df893667311a4b944f..7da156f27145ae4f6110790542b9ff21942cdf99 100644 GIT binary patch delta 14 Wcmew;_)&0zIJ4B$PaCDKa{vG?T?P68 delta 14 Vcmew;_)&0zICIlxfsInvIRGtx1)cx^ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxscb_v1.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxscb_v1.cydata index 6abaa107d1f8b361aed3aa6be151a6d8c89087b0..e294cb15cd1ae8a5ed32e7d156d727073ac7bedc 100644 GIT binary patch delta 14 WcmbQtGMQz9IJ4B$PaCCvG6Dc2)&)NR delta 14 VcmbQtGMQz9ICIlxfsIl>837{r1mgez diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxsdhc_v1.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxsdhc_v1.cydata index 20876383ef9c51bb15bb74f32e1fe8ac27b84d8d..5d475fb7e299d9497091ced17c1fabe5debed522 100644 GIT binary patch delta 14 WcmbQtGMQz9IJ4B$PaCCvG6Dc2)&)NR delta 14 VcmbQtGMQz9ICIlxfsIl>837{r1mgez diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxsmif_v1.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxsmif_v1.cydata index 45d16d19ff2592d234d7b076a60a65d9c57cbeb8..a5d96d7314662d5f672354518b1a3043305d5917 100644 GIT binary patch delta 14 WcmbQtGMQz9IJ4B$PaCCvG6Dc2)&)NR delta 14 VcmbQtGMQz9ICIlxfsIl>837{r1mgez diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxtcpwm_v1.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxtcpwm_v1.cydata index ec339cb97bab93226093d7d7a7c02f5f7ebc5ab2..fdb56445bd09da9934e4ab29f0c08466b464740c 100644 GIT binary patch delta 14 WcmZ3@yP9``IJ4B$PaCBsvH<`lQw1IX delta 14 VcmZ3@yP9``ICIlxfsIlV*#ISV1i}CS diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxttcanfd_s40s_v1.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxttcanfd_s40s_v1.cydata index ca34023950caef655ea3a7884d2bc5580ba09a80..eb43d1eda8229c8fff2a027fbc2f7e3a3d9c8d72 100644 GIT binary patch delta 14 VcmZ3@v6^FoIJ4B$PaCBKSpX#21d;#% delta 14 VcmZ3@v6^FoICIlxfsImvEC3_>1U3Kw diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxudb_v1.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxudb_v1.cydata index c66eb4e074c3385fe52785765a11353756976d40..6c167c0ce206e08917c3929a2ae2cbad02eb5668 100644 GIT binary patch delta 14 WcmbQtGMQz9IJ4B$PaCCvG6Dc2)&)NR delta 14 VcmbQtGMQz9ICIlxfsIl>837{r1mgez diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxusbfs_v1.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxusbfs_v1.cydata index 1d834983272d36f9479fb9c327f8b507c9a148ca..a2f0f02b6dc5b0ab3180510a66708367ce7e5a1b 100644 GIT binary patch delta 14 WcmbQtGMQz9IJ4B$PaCCvG6Dc2)&)NR delta 14 VcmbQtGMQz9ICIlxfsIl>837{r1mgez diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/features.mk b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/features.mk index 49b2150f6f1..1763c9f4ae7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/features.mk +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/features.mk @@ -2,26 +2,28 @@ # list of the MPNs that have that capability or feature. # Major device capabilities. -CY_DEVICES_WITH_M0P=CY8C6246BZI-D04 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6247FDI-D52 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6247WI-D54 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CY8C6347LQI-BLD52 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CYB0644ABZI-D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 +CY_DEVICES_WITH_M0P=CY8C6246BZI-D04 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6247FDI-D52 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6247WI-D54 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CY8C6347LQI-BLD52 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CYB0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245W-S3D72 CY_DEVICES_WITH_BLE=CY8C6336BZI-BLF03 CY8C6316BZI-BLF03 CY8C6316BZI-BLF53 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6337BZI-BLF13 CY8C6336BZI-BLF04 CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CY8C6336LQI-BLF02 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 CY_DEVICES_WITH_UDBS=CY8C6116BZI-F54 CY8C6136BZI-F34 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6316BZI-BLF53 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C6247FDI-D32 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6247FDI-D52 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6316BZI-BLF54 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CY8C6347LQI-BLD52 -CY_DEVICES_WITH_FS_USB=CY8C6036BZI-F04 CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6246BZI-D04 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C637BZI-MD76 CY8C6137FDI-F02 CY8C6117FDI-F02 CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6336BZI-BLF04 CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CYB06447BZI-BLD54 CYB06447BZI-D54 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CYB0644ABZI-D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 -CY_DEVICES_WITH_CAPSENSE=CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6316BZI-BLF53 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6247FDI-D32 CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6337BZI-BLF13 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CYB0644ABZI-D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 -CY_DEVICES_WITH_CRYPTO=CY8C6116BZI-F54 CY8C6137BZI-F54 CY8C6247BZI-D44 CY8C6247BZI-D54 CY8C6316BZI-BLF53 CY8C6347BZI-BLD43 CY8C6347BZI-BLD53 CY8C6347FMI-BLD43 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6347BZI-BUD43 CY8C6347BZI-BUD53 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6316BZI-BLF54 CY8C6347BZI-BLD44 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD43 CY8C6137WI-F54 CY8C6247WI-D54 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CYB0644ABZI-D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CY8C6245FNI-S3D41 +CY_DEVICES_WITH_FS_USB=CY8C6036BZI-F04 CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6246BZI-D04 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C637BZI-MD76 CY8C6137FDI-F02 CY8C6117FDI-F02 CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6336BZI-BLF04 CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CYB06447BZI-BLD54 CYB06447BZI-D54 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CYB0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245W-S3D72 +CY_DEVICES_WITH_CAPSENSE=CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6316BZI-BLF53 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6247FDI-D32 CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6337BZI-BLF13 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CYB0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245W-S3D72 +CY_DEVICES_WITH_CRYPTO=CY8C6116BZI-F54 CY8C6137BZI-F54 CY8C6247BZI-D44 CY8C6247BZI-D54 CY8C6316BZI-BLF53 CY8C6347BZI-BLD43 CY8C6347BZI-BLD53 CY8C6347FMI-BLD43 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6347BZI-BUD43 CY8C6347BZI-BUD53 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6316BZI-BLF54 CY8C6347BZI-BLD44 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD43 CY8C6137WI-F54 CY8C6247WI-D54 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CYB0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245W-S3D72 # Different classifications of devices. CY_DEVICES_WITH_DIE_PSOC6ABLE2=CY8C6036BZI-F04 CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6246BZI-D04 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6336BZI-BLF03 CY8C6316BZI-BLF03 CY8C6316BZI-BLF53 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6137FDI-F02 CY8C6117FDI-F02 CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6337BZI-BLF13 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6336BZI-BLF04 CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CY8C6336LQI-BLF02 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 -CY_DEVICES_WITH_DIE_PSOC6A2M=CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CYB0644ABZI-D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 -CY_DEVICES_WITH_DIE_PSOC6A512K=CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 +CY_DEVICES_WITH_DIE_PSOC6A2M=CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CYB0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 +CY_DEVICES_WITH_DIE_PSOC6A512K=CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245W-S3D72 -CY_DEVICES_WITH_FLASH_KB_512=CY8C6036BZI-F04 CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6246BZI-D04 CY8C6336BZI-BLF03 CY8C6316BZI-BLF03 CY8C6316BZI-BLF53 CY8C6336BZI-BLD13 CY8C6336BZI-BUD13 CY8C6136FDI-F42 CY8C6136FTI-F42 CY8C6336BZI-BLF04 CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6336LQI-BLF02 CY8C6336LQI-BLF42 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 -CY_DEVICES_WITH_FLASH_KB_1024=CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6137FDI-F02 CY8C6117FDI-F02 CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6337BZI-BLF13 CY8C6247FDI-D52 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CY8C6347LQI-BLD52 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 -CY_DEVICES_WITH_FLASH_KB_2048=CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C624ALQI-D42 CYB0644ABZI-D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 +CY_DEVICES_WITH_FLASH_KB_512=CY8C6036BZI-F04 CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6246BZI-D04 CY8C6336BZI-BLF03 CY8C6316BZI-BLF03 CY8C6316BZI-BLF53 CY8C6336BZI-BLD13 CY8C6336BZI-BUD13 CY8C6136FDI-F42 CY8C6136FTI-F42 CY8C6336BZI-BLF04 CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6336LQI-BLF02 CY8C6336LQI-BLF42 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245W-S3D72 +CY_DEVICES_WITH_FLASH_KB_1024=CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6137FDI-F02 CY8C6117FDI-F02 CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6337BZI-BLF13 CY8C6247FDI-D52 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CY8C6347LQI-BLD52 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 +CY_DEVICES_WITH_FLASH_KB_832=CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 +CY_DEVICES_WITH_FLASH_KB_2048=CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C624ALQI-D42 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 +CY_DEVICES_WITH_FLASH_KB_1856=CYB0644ABZI-S2D44 -CY_DEVICES_WITH_MAX_SPEED_MHZ_150=CY8C6036BZI-F04 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6246BZI-D04 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6336BZI-BLF03 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6137FDI-F02 CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6337BZI-BLF13 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6336BZI-BLF04 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6247WI-D54 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CY8C6336LQI-BLF02 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CYB0644ABZI-D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 +CY_DEVICES_WITH_MAX_SPEED_MHZ_150=CY8C6036BZI-F04 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6246BZI-D04 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6336BZI-BLF03 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6137FDI-F02 CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6337BZI-BLF13 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6336BZI-BLF04 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6247WI-D54 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CY8C6336LQI-BLF02 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CYB0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245W-S3D72 CY_DEVICES_WITH_MAX_SPEED_MHZ_50=CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6117BZI-F34 CY8C6316BZI-BLF03 CY8C6316BZI-BLF53 CY8C6117FDI-F02 CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6117WI-F34 -CY_DEVICES_WITH_PACKAGE_124-BGA=CY8C6036BZI-F04 CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6246BZI-D04 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C637BZI-MD76 CY8C6247BZI-AUD54 CY8C6247BFI-D54 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CYB06447BZI-D54 CY8C624ABZI-D44 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C6248BZI-D44 CYB0644ABZI-D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C6248BZI-S2D44 +CY_DEVICES_WITH_PACKAGE_124-BGA=CY8C6036BZI-F04 CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6246BZI-D04 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C637BZI-MD76 CY8C6247BZI-AUD54 CY8C6247BFI-D54 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CYB06447BZI-D54 CY8C624ABZI-D44 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C6248BZI-D44 CYB0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C6248BZI-S2D44 CY_DEVICES_WITH_PACKAGE_116-BGA-BLE=CY8C6336BZI-BLF03 CY8C6316BZI-BLF03 CY8C6316BZI-BLF53 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C637BZI-BLD74 CY8C68237BZ-BLE CY8C6337BZI-BLF13 CYB06447BZI-BLD53 CY_DEVICES_WITH_PACKAGE_104-M-CSP-BLE=CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637FMI-BLD73 CY8C68237FM-BLE CY_DEVICES_WITH_PACKAGE_80-WLCSP=CY8C6137FDI-F02 CY8C6117FDI-F02 CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 @@ -32,7 +34,7 @@ CY_DEVICES_WITH_PACKAGE_104-M-CSP-BLE-USB=CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY CY_DEVICES_WITH_PACKAGE_68-QFN-BLE=CY8C6336LQI-BLF02 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 CY_DEVICES_WITH_PACKAGE_128-TQFP=CY8C624AAZI-D44 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248AZI-D44 CY8C624AAZI-S2D44 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248AZI-S2D44 CY_DEVICES_WITH_PACKAGE_100-WLCSP=CY8C624AFNI-D43 CY8C6248FNI-D43 CY8C624AFNI-S2D43 CY8C6248FNI-S2D43 -CY_DEVICES_WITH_PACKAGE_68-QFN=CY8C624ALQI-D42 CY8C6245LQI-S3D72 CY8C6245LQI-S3D62 CY8C6245LQI-S3D42 CY8C6245LQI-S3D12 CY8C6245LQI-S3D02 -CY_DEVICES_WITH_PACKAGE_100-TQFP=CY8C6245AZI-S3D72 CY8C6245AZI-S3D62 CY8C6245AZI-S3D42 CY8C6245AZI-S3D12 CY8C6245AZI-S3D02 +CY_DEVICES_WITH_PACKAGE_68-QFN=CY8C624ALQI-D42 CY8C6245LQI-S3D72 CY8C6245LQI-S3D62 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245LQI-S3D12 CY8C6245LQI-S3D02 +CY_DEVICES_WITH_PACKAGE_100-TQFP=CY8C6245AZI-S3D72 CY8C6245AZI-S3D62 CY8C6245AZI-S3D42 CY8C6245AZI-S3D12 CY8C6245AZI-S3D02 CY8C6245W-S3D72 CY_DEVICES_WITH_PACKAGE_49-WLCSP=CY8C6245FNI-S3D71 CY8C6245FNI-S3D41 CY8C6245FNI-S3D11 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/version.dat b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/version.dat index c968d500615..dee60c3d868 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/version.dat +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/version.dat @@ -1 +1 @@ -1.1.2.59 +1.1.2.62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/version.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/version.xml index 6520a853e56..5298029c68f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/version.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/version.xml @@ -1 +1 @@ -1.1.2.59 +1.1.2.62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/version.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/version.xml index a50a525320d..cef1ad789e3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/version.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/version.xml @@ -1 +1 @@ -1.3.0.1362 +1.3.1.1474 From 0cb250ca043a06c736527bb581317a9f5be68ab3 Mon Sep 17 00:00:00 2001 From: Volodymyr Medvid Date: Tue, 24 Sep 2019 17:43:23 +0300 Subject: [PATCH 129/227] PSOC6: update to PDL 1.3.1.1499 --- .../TARGET_PSOC6/psoc6pdl/RELEASE.md | 5 ++++- .../psoc6pdl/drivers/include/cy_canfd.h | 7 ++++++- .../psoc6pdl/drivers/include/cy_device.h | 6 +++--- .../psoc6pdl/drivers/include/cy_flash.h | 14 ++++++++++---- .../psoc6pdl/drivers/include/cy_sysint.h | 2 +- .../psoc6pdl/drivers/include/cy_syspm.h | 18 ++++++++++++++++-- .../psoc6pdl/drivers/source/cy_canfd.c | 7 ++++--- .../psoc6pdl/drivers/source/cy_device.c | 2 +- .../psoc6pdl/drivers/source/cy_flash.c | 2 +- .../psoc6pdl/drivers/source/cy_syspm.c | 16 ++++++++-------- .../TARGET_PSOC6/psoc6pdl/version.xml | 2 +- 11 files changed, 55 insertions(+), 26 deletions(-) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/RELEASE.md b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/RELEASE.md index 96b63774056..2eb1fec50ef 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/RELEASE.md +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/RELEASE.md @@ -4,10 +4,13 @@ Please refer to the [README.md](./README.md) and the [PDL API Reference Manual]( ### New Features Updated Drivers -* [SysInt 1.30](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__sysInt.html) +* [SysInt 1.30](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__sysint.html) +* [SysPm 4.40](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__syspm.html) * [USBFS 2.20](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__usbfs__dev__drv.html) Drivers with patch version updates +* [CAN FD 1.0.1](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__canfd.html) +* [Flash 3.30.2](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__flash.html) * [Prot 1.30.1](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__prot.html) * [SysClk 1.40.2](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__sysclk.html) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_canfd.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_canfd.h index 73eb7ed8590..09dd4119d6d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_canfd.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_canfd.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_canfd.h -* \version 1.0 +* \version 1.0.1 * * This file provides constants and parameter values for * the CAN FD driver. @@ -217,6 +217,11 @@ * * * +* +* +* +* +* * * * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_device.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_device.h index 8aa1b930968..1f2060bf82a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_device.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_device.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_device.h -* \version 2.0 +* \version 2.10 * * This file specifies the structure for core and peripheral block HW base * addresses, versions, and parameters. @@ -381,9 +381,9 @@ void Cy_PDL_Init(const cy_stc_device_t * device); #define SFLASH_CPUSS_TRIM_ROM_CTL_ULP (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_ROM_CTL_ULP) #define SFLASH_CPUSS_TRIM_RAM_CTL_ULP (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_RAM_CTL_ULP) #define SFLASH_CPUSS_TRIM_ROM_CTL_HALF_LP (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_ROM_CTL_HALF_LP) -#define SFLASH_CPUSS_TRIM_ROM_CTL_HALF_LP (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_ROM_CTL_HALF_LP) -#define SFLASH_CPUSS_TRIM_RAM_CTL_HALF_ULP (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_RAM_CTL_HALF_ULP) +#define SFLASH_CPUSS_TRIM_RAM_CTL_HALF_LP (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_RAM_CTL_HALF_LP) #define SFLASH_CPUSS_TRIM_ROM_CTL_HALF_ULP (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_ROM_CTL_HALF_ULP) +#define SFLASH_CPUSS_TRIM_RAM_CTL_HALF_ULP (((SFLASH_V1_Type *) SFLASH)->CPUSS_TRIM_RAM_CTL_HALF_ULP) #define SFLASH_CSD0_ADC_VREF0_TRIM (((SFLASH_V1_Type *) SFLASH)->CSDV2_CSD0_ADC_VREF0) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_flash.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_flash.h index d55c64826dc..ad3c50820e9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_flash.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_flash.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_flash.h -* \version 3.30.1 +* \version 3.30.2 * * Provides the API declarations of the Flash driver. * @@ -52,12 +52,13 @@ * interrupt instead of a reset. * * A Read while Write violation occurs when a flash Read operation is initiated -* in the same or neighboring flash sector where the flash Write, Erase, or +* in the same or neighboring (neighboring restriction is applicable just for the +* CY8C6xx6, CY8C6xx7 devices) flash sector where the flash Write, Erase, or * Program operation is working. This violation may cause a HardFault exception. * To avoid the Read while Write violation, the user must carefully split the * Read and Write operation on flash sectors which are not neighboring, -* considering both cores in the multi-processor device. The flash is divided -* into four equal sectors. You may edit the linker script to place the code +* considering both cores in the multi-processor device. If the flash is divided +* into four equal sectors, you may edit the linker script to place the code * into neighboring sectors. For example, use sectors number 0 and 1 for code * and sectors 2 and 3 for data storage. * @@ -255,6 +256,11 @@ *
VersionChangesReason for Change
1.0.1Updated description of the \ref Cy_CANFD_Init() and \ref Cy_CANFD_DeInit() functionsDocumentation update and clarification
1.0Initial version
* * +* +* +* +* +* * * * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysint.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysint.h index 1a526c264a6..ba6977eae74 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysint.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysint.h @@ -270,7 +270,7 @@ extern cy_israddress __ramVectors[]; /**< Relocated vector table in SRAM */ #define CY_SYSINT_DRV_VERSION_MAJOR 1 /** Driver minor version */ -#define CY_SYSINT_DRV_VERSION_MINOR 20 +#define CY_SYSINT_DRV_VERSION_MINOR 30 /** SysInt driver ID */ #define CY_SYSINT_ID CY_PDL_DRV_ID (0x15U) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syspm.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syspm.h index ceb514f62d0..a762587bf2f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syspm.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syspm.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_syspm.h -* \version 4.30 +* \version 4.40 * * Provides the function definitions for the power management API. * @@ -724,6 +724,20 @@ *
VersionChangesReason for Change
3.30.2Updated documentation to limit devices with the neighboring restriction.User experience enhancement.
3.30.1Used the CY_RAMFUNC_BEGIN and CY_RAMFUNC_END macros that allocate the function in RAM instead of using the CY_SECTION(".cy_ramfunc") macros.Removed the code duplication.
* * +* +* +* +* +* * * * * +* +* +* +* +* * * * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/system_psoc6_cm4.c index a5408385ee6..0a18f50a4d4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/system_psoc6_cm4.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/system_psoc6_cm4.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6_cm4.c -* \version 2.50 +* \version 2.60 * * The device system-source file. * From 7dd86e8f481c9c1022c77ab637123b1b7963b129 Mon Sep 17 00:00:00 2001 From: Kyle Kearney Date: Thu, 19 Sep 2019 12:05:25 -0700 Subject: [PATCH 180/227] Clean up BSP hardware configuration - Improve block naming - Remove unneeded items --- .../GeneratedSource/cycfg_clocks.c | 15 + .../GeneratedSource/cycfg_clocks.h | 6 + .../GeneratedSource/cycfg_peripherals.c | 44 +++ .../GeneratedSource/cycfg_peripherals.h | 13 + .../GeneratedSource/cycfg_pins.c | 87 +++++ .../GeneratedSource/cycfg_pins.h | 84 +++++ .../GeneratedSource/cycfg_qspi_memslot.c | 44 +-- .../GeneratedSource/cycfg_qspi_memslot.h | 26 +- .../GeneratedSource/cycfg_system.c | 2 +- .../cyreservedresources.list | 30 +- .../COMPONENT_BSP_DESIGN_MODUS/design.modus | 82 ++++- .../cyreservedresources.list | 24 +- .../COMPONENT_BSP_DESIGN_MODUS/design.modus | 4 +- .../GeneratedSource/cycfg.c | 1 - .../GeneratedSource/cycfg.h | 1 - .../GeneratedSource/cycfg_clocks.c | 23 +- .../GeneratedSource/cycfg_clocks.h | 14 +- .../GeneratedSource/cycfg_dmas.c | 230 ------------ .../GeneratedSource/cycfg_dmas.h | 87 ----- .../GeneratedSource/cycfg_peripherals.h | 1 - .../GeneratedSource/cycfg_pins.c | 28 +- .../GeneratedSource/cycfg_pins.h | 58 +-- .../GeneratedSource/cycfg_qspi_memslot.c | 44 +-- .../GeneratedSource/cycfg_qspi_memslot.h | 26 +- .../cyreservedresources.list | 48 +-- .../COMPONENT_BSP_DESIGN_MODUS/design.modus | 130 +------ .../GeneratedSource/cycfg_clocks.c | 15 + .../GeneratedSource/cycfg_clocks.h | 6 + .../GeneratedSource/cycfg_peripherals.c | 44 +++ .../GeneratedSource/cycfg_peripherals.h | 13 + .../GeneratedSource/cycfg_pins.c | 58 +++ .../GeneratedSource/cycfg_pins.h | 56 +++ .../GeneratedSource/cycfg_qspi_memslot.c | 44 +-- .../GeneratedSource/cycfg_qspi_memslot.h | 26 +- .../GeneratedSource/cycfg_system.c | 2 +- .../cyreservedresources.list | 16 +- .../design.cycapsense | 333 +++++++++++++++++- .../COMPONENT_BSP_DESIGN_MODUS/design.modus | 71 +++- .../GeneratedSource/cycfg_clocks.c | 27 +- .../GeneratedSource/cycfg_clocks.h | 19 +- .../GeneratedSource/cycfg_peripherals.c | 95 +++-- .../GeneratedSource/cycfg_peripherals.h | 27 +- .../GeneratedSource/cycfg_pins.c | 283 ++++++++++----- .../GeneratedSource/cycfg_pins.h | 324 +++++++++++++---- .../GeneratedSource/cycfg_routing.h | 2 - .../GeneratedSource/cycfg_system.c | 62 +++- .../GeneratedSource/cycfg_system.h | 19 + .../cyreservedresources.list | 18 +- .../COMPONENT_BSP_DESIGN_MODUS/design.cyqspi | 63 ++++ .../COMPONENT_BSP_DESIGN_MODUS/design.modus | 154 ++------ .../GeneratedSource/cycfg.c | 1 - .../GeneratedSource/cycfg.h | 1 - .../GeneratedSource/cycfg_clocks.c | 31 +- .../GeneratedSource/cycfg_clocks.h | 22 +- .../GeneratedSource/cycfg_dmas.c | 230 ------------ .../GeneratedSource/cycfg_dmas.h | 87 ----- .../GeneratedSource/cycfg_peripherals.h | 3 +- .../GeneratedSource/cycfg_qspi_memslot.c | 44 +-- .../GeneratedSource/cycfg_qspi_memslot.h | 26 +- .../cyreservedresources.list | 44 +-- .../COMPONENT_BSP_DESIGN_MODUS/design.modus | 136 +------ 61 files changed, 1954 insertions(+), 1600 deletions(-) delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.c delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.c delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c index 33ad3de755e..473bd8a7e58 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c @@ -24,6 +24,14 @@ #include "cycfg_clocks.h" +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_UART_CLK_DIV_obj = + { + .type = CYHAL_RSC_CLOCK, + .block_num = CYBSP_UART_CLK_DIV_HW, + .channel_num = CYBSP_UART_CLK_DIV_NUM, + }; +#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj = { @@ -52,6 +60,13 @@ void init_cycfg_clocks(void) { + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 719U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_UART_CLK_DIV_obj); +#endif //defined (CY_USING_HAL) + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 1U); Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 1U, 77U); Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 1U); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h index 2ba0f1937b7..9b8200af2e9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h @@ -35,6 +35,9 @@ extern "C" { #endif +#define CYBSP_UART_CLK_DIV_ENABLED 1U +#define CYBSP_UART_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT +#define CYBSP_UART_CLK_DIV_NUM 0U #define CYBSP_BT_UART_CLK_DIV_ENABLED 1U #define CYBSP_BT_UART_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT #define CYBSP_BT_UART_CLK_DIV_NUM 1U @@ -45,6 +48,9 @@ extern "C" { #define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT #define CYBSP_CSD_COMM_CLK_DIV_NUM 1U +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_UART_CLK_DIV_obj; +#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj; #endif //defined (CY_USING_HAL) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c index c26f522b065..1300f6a4047 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c @@ -24,6 +24,20 @@ #include "cycfg_peripherals.h" +#define CYBSP_USBUART_INTR_LVL_SEL (CY_USBFS_DEV_DRV_SET_SOF_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_BUS_RESET_LVL(0x2U) | \ + CY_USBFS_DEV_DRV_SET_EP0_LVL(0x2U) | \ + CY_USBFS_DEV_DRV_SET_LPM_LVL(0x0U) | \ + CY_USBFS_DEV_DRV_SET_ARB_EP_LVL(0x0U) | \ + CY_USBFS_DEV_DRV_SET_EP1_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP2_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP3_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP4_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP5_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP6_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP7_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP8_LVL(0x1U)) + cy_stc_csd_context_t cy_csd_0_context = { .lockKey = CY_CSD_NONE_KEY, @@ -136,6 +150,31 @@ const cy_stc_rtc_config_t CYBSP_RTC_config = .channel_num = 0U, }; #endif //defined (CY_USING_HAL) +const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config = +{ + .mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU, + .epAccess = CY_USBFS_DEV_DRV_USE_8_BITS_DR, + .epBuffer = NULL, + .epBufferSize = 0U, + .dmaConfig[0] = NULL, + .dmaConfig[1] = NULL, + .dmaConfig[2] = NULL, + .dmaConfig[3] = NULL, + .dmaConfig[4] = NULL, + .dmaConfig[5] = NULL, + .dmaConfig[6] = NULL, + .dmaConfig[7] = NULL, + .enableLpm = false, + .intrLevelSel = CYBSP_USBUART_INTR_LVL_SEL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_USBUART_obj = + { + .type = CYHAL_RSC_USB, + .block_num = 0U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) void init_cycfg_peripherals(void) @@ -163,4 +202,9 @@ void init_cycfg_peripherals(void) #if defined (CY_USING_HAL) cyhal_hwmgr_reserve(&CYBSP_RTC_obj); #endif //defined (CY_USING_HAL) + + Cy_SysClk_PeriphAssignDivider(PCLK_USB_CLOCK_DEV_BRS, CY_SYSCLK_DIV_16_BIT, 0U); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_USBUART_obj); +#endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h index deff2270e58..08b0a43fedb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h @@ -37,6 +37,7 @@ #include "cycfg_qspi_memslot.h" #include "cy_mcwdt.h" #include "cy_rtc.h" +#include "cy_usbfs_dev_drv.h" #if defined(__cplusplus) extern "C" { @@ -113,6 +114,14 @@ extern "C" { #define CYBSP_RTC_100_YEAR_OFFSET (8U) #define CYBSP_RTC_10_YEAR_OFFSET (4U) #define CYBSP_RTC_YEAR_OFFSET (0U) +#define CYBSP_USBUART_ENABLED 1U +#define CYBSP_USBUART_ACTIVE_ENDPOINTS_MASK 0U +#define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 512U +#define CYBSP_USBUART_ENDPOINTS_ACCESS_TYPE 0U +#define CYBSP_USBUART_HW USBFS0 +#define CYBSP_USBUART_HI_IRQ usb_interrupt_hi_IRQn +#define CYBSP_USBUART_MED_IRQ usb_interrupt_med_IRQn +#define CYBSP_USBUART_LO_IRQ usb_interrupt_lo_IRQn extern cy_stc_csd_context_t cy_csd_0_context; extern const cy_stc_scb_uart_config_t CYBSP_BT_UART_config; @@ -135,6 +144,10 @@ extern const cy_stc_rtc_config_t CYBSP_RTC_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_RTC_obj; #endif //defined (CY_USING_HAL) +extern const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_USBUART_obj; +#endif //defined (CY_USING_HAL) void init_cycfg_peripherals(void); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c index 14f111d2a72..2d6e9e041af 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c @@ -216,6 +216,54 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_SPI_CLOCK_config = .channel_num = CYBSP_QSPI_SPI_CLOCK_PIN, }; #endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_USB_DP_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_USB_DP_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_USB_DP_PORT_NUM, + .channel_num = CYBSP_USB_DP_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_USB_DM_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_USB_DM_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_USB_DM_PORT_NUM, + .channel_num = CYBSP_USB_DM_PIN, + }; +#endif //defined (CY_USING_HAL) const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config = { .outVal = 1, @@ -408,6 +456,30 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config = .channel_num = CYBSP_BT_HOST_WAKE_PIN, }; #endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_WIFI_HOST_WAKE_HSIOM, + .intEdge = CY_GPIO_INTR_RISING, + .intMask = 1UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_WIFI_HOST_WAKE_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_WIFI_HOST_WAKE_PORT_NUM, + .channel_num = CYBSP_WIFI_HOST_WAKE_PIN, + }; +#endif //defined (CY_USING_HAL) const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config = { .outVal = 1, @@ -812,6 +884,16 @@ void init_cycfg_pins(void) cyhal_hwmgr_reserve(&CYBSP_QSPI_SPI_CLOCK_obj); #endif //defined (CY_USING_HAL) + Cy_GPIO_Pin_Init(CYBSP_USB_DP_PORT, CYBSP_USB_DP_PIN, &CYBSP_USB_DP_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_USB_DP_obj); +#endif //defined (CY_USING_HAL) + + Cy_GPIO_Pin_Init(CYBSP_USB_DM_PORT, CYBSP_USB_DM_PIN, &CYBSP_USB_DM_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_USB_DM_obj); +#endif //defined (CY_USING_HAL) + #if defined (CY_USING_HAL) cyhal_hwmgr_reserve(&CYBSP_CSD_RX_obj); #endif //defined (CY_USING_HAL) @@ -851,6 +933,11 @@ void init_cycfg_pins(void) cyhal_hwmgr_reserve(&CYBSP_BT_HOST_WAKE_obj); #endif //defined (CY_USING_HAL) + Cy_GPIO_Pin_Init(CYBSP_WIFI_HOST_WAKE_PORT, CYBSP_WIFI_HOST_WAKE_PIN, &CYBSP_WIFI_HOST_WAKE_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_WIFI_HOST_WAKE_obj); +#endif //defined (CY_USING_HAL) + Cy_GPIO_Pin_Init(CYBSP_EZI2C_SCL_PORT, CYBSP_EZI2C_SCL_PIN, &CYBSP_EZI2C_SCL_config); #if defined (CY_USING_HAL) cyhal_hwmgr_reserve(&CYBSP_EZI2C_SCL_obj); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h index 4975b85b7ed..608ed5c6ff8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h @@ -228,6 +228,54 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_QSPI_SPI_CLOCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG #endif //defined (CY_USING_HAL) +#define CYBSP_USB_DP_ENABLED 1U +#define CYBSP_USB_DP_PORT GPIO_PRT14 +#define CYBSP_USB_DP_PORT_NUM 14U +#define CYBSP_USB_DP_PIN 0U +#define CYBSP_USB_DP_NUM 0U +#define CYBSP_USB_DP_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_USB_DP_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_14_pin_0_HSIOM + #define ioss_0_port_14_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_USB_DP_HSIOM ioss_0_port_14_pin_0_HSIOM +#define CYBSP_USB_DP_IRQ ioss_interrupts_gpio_14_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_USB_DP_HAL_PORT_PIN P14_0 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_USB_DP_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_USB_DP_HAL_DIR CYHAL_GPIO_DIR_INPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_USB_DP_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG +#endif //defined (CY_USING_HAL) +#define CYBSP_USB_DM_ENABLED 1U +#define CYBSP_USB_DM_PORT GPIO_PRT14 +#define CYBSP_USB_DM_PORT_NUM 14U +#define CYBSP_USB_DM_PIN 1U +#define CYBSP_USB_DM_NUM 1U +#define CYBSP_USB_DM_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_USB_DM_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_14_pin_1_HSIOM + #define ioss_0_port_14_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_USB_DM_HSIOM ioss_0_port_14_pin_1_HSIOM +#define CYBSP_USB_DM_IRQ ioss_interrupts_gpio_14_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_USB_DM_HAL_PORT_PIN P14_1 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_USB_DM_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_USB_DM_HAL_DIR CYHAL_GPIO_DIR_INPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_USB_DM_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG +#endif //defined (CY_USING_HAL) #define CYBSP_CSD_RX_ENABLED 1U #define CYBSP_CSD_RX_PORT GPIO_PRT1 #define CYBSP_CSD_RX_PORT_NUM 1U @@ -420,6 +468,30 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_BT_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG #endif //defined (CY_USING_HAL) +#define CYBSP_WIFI_HOST_WAKE_ENABLED 1U +#define CYBSP_WIFI_HOST_WAKE_PORT GPIO_PRT4 +#define CYBSP_WIFI_HOST_WAKE_PORT_NUM 4U +#define CYBSP_WIFI_HOST_WAKE_PIN 1U +#define CYBSP_WIFI_HOST_WAKE_NUM 1U +#define CYBSP_WIFI_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_WIFI_HOST_WAKE_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_4_pin_1_HSIOM + #define ioss_0_port_4_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_WIFI_HOST_WAKE_HSIOM ioss_0_port_4_pin_1_HSIOM +#define CYBSP_WIFI_HOST_WAKE_IRQ ioss_interrupts_gpio_4_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_WIFI_HOST_WAKE_HAL_PORT_PIN P4_1 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WIFI_HOST_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_RISE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WIFI_HOST_WAKE_HAL_DIR CYHAL_GPIO_DIR_INPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WIFI_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG +#endif //defined (CY_USING_HAL) #define CYBSP_EZI2C_SCL_ENABLED 1U #define CYBSP_EZI2C_SCL_PORT GPIO_PRT6 #define CYBSP_EZI2C_SCL_PORT_NUM 6U @@ -813,6 +885,14 @@ extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SPI_CLOCK_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_QSPI_SPI_CLOCK_obj; #endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_USB_DP_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_USB_DM_obj; +#endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_CSD_RX_obj; @@ -845,6 +925,10 @@ extern const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj; #endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_WIFI_HOST_WAKE_obj; +#endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c index c4e5bcf916f..14d433859db 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c @@ -24,7 +24,7 @@ #include "cycfg_qspi_memslot.h" -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0xECU, @@ -42,7 +42,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd = .dataWidth = CY_SMIF_WIDTH_QUAD }; -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x06U, @@ -60,7 +60,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x04U, @@ -78,7 +78,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0xDCU, @@ -96,7 +96,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x60U, @@ -114,7 +114,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x34U, @@ -132,7 +132,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd = .dataWidth = CY_SMIF_WIDTH_QUAD }; -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x35U, @@ -150,7 +150,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x05U, @@ -168,7 +168,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x01U, @@ -186,34 +186,34 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 = +const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0 = { /* Specifies the number of address bytes used by the memory slave device. */ .numOfAddrBytes = 0x04U, /* The size of the memory. */ .memSize = 0x04000000U, /* Specifies the Read command. */ - .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readCmd, + .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readCmd, /* Specifies the Write Enable command. */ - .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd, + .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd, /* Specifies the Write Disable command. */ - .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd, + .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd, /* Specifies the Erase command. */ - .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd, + .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd, /* Specifies the sector size of each erase. */ .eraseSize = 0x00040000U, /* Specifies the Chip Erase command. */ - .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd, + .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd, /* Specifies the Program command. */ - .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_programCmd, + .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_programCmd, /* Specifies the page size for programming. */ .programSize = 0x00000200U, /* Specifies the command to read the QE-containing status register. */ - .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd, + .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd, /* Specifies the command to read the WIP-containing status register. */ - .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd, + .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd, /* Specifies the command to write into the QE-containing status register. */ - .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd, + .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd, /* The mask for the status register. */ .stsRegBusyMask = 0x01U, /* The mask for the status register. */ @@ -226,7 +226,7 @@ const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 = .programTime = 1300U }; -const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 = +const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0 = { /* Determines the slot number where the memory device is placed. */ .slaveSelect = CY_SMIF_SLAVE_SELECT_0, @@ -244,11 +244,11 @@ const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 = Valid when the memory mapped mode is enabled. */ .dualQuadSlots = 0, /* The configuration of the device. */ - .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 + .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0 }; const cy_stc_smif_mem_config_t* const smifMemConfigs[] = { - &S25FL512SX4byteaddr_SlaveSlot_0 + &S25FL512S_4byteaddr_SlaveSlot_0 }; const cy_stc_smif_block_config_t smifBlockConfig = diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h index 32f9b49b2e6..0ee62b1d559 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h @@ -28,19 +28,19 @@ #define CY_SMIF_DEVICE_NUM 1 -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd; - -extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0; - -extern const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd; + +extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0; + +extern const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0; extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM]; extern const cy_stc_smif_block_config_t smifBlockConfig; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c index a8562c420e8..2a317110713 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c @@ -73,7 +73,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = .refDiv = 20U, .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4, .enableOutputDiv = true, - .lockTolerance = 10U, + .lockTolerance = 4U, .igain = 9U, .pgain = 5U, .settlingCount = 8U, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list index a79663451dd..8453a4470f1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list @@ -1,34 +1,6 @@ -[Device="CY8C624ABZI-D44"] +[Device=CY8C624ABZI-D44] [Blocks] -# User IO -# CYBSP_USER_LED1 -ioss[0].port[11].pin[1] -# CYBSP_USER_LED2 -ioss[0].port[1].pin[5] -# CYBSP_USER_LED3 -ioss[0].port[1].pin[1] -# CYBSP_USER_LED4 -ioss[0].port[0].pin[5] -# CYBSP_USER_LED5 -ioss[0].port[7].pin[3] -# CYBSP_USER_BTN1 -ioss[0].port[0].pin[4] -# CYBSP_USER_BTN2 -ioss[0].port[1].pin[4] - -# Debug -# CYBSP_DEBUG_UART -scb[5] -# CYBSP_DEBUG_UART_RX -ioss[0].port[5].pin[0] -# CYBSP_DEBUG_UART_TX -ioss[0].port[5].pin[1] -# CYBSP_DEBUG_UART_RTS -ioss[0].port[5].pin[2] -# CYBSP_DEBUG_UART_CTS -ioss[0].port[5].pin[3] - # WIFI # CYBSP_WIFI_SDIO sdhc[0] diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.modus index 602d095a873..b2964f1eaf6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.modus +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.modus @@ -1,5 +1,5 @@ - + @@ -124,6 +124,26 @@ + + + + + + + + + + + + + + + + + + + + @@ -204,6 +224,16 @@ + + + + + + + + + + @@ -354,6 +384,11 @@ + + + + + @@ -467,7 +502,7 @@ - + @@ -525,7 +560,6 @@ - @@ -565,6 +599,27 @@ + + + + + + + + + + + + + + + + + + + + + @@ -639,6 +694,18 @@ + + + + + + + + + + + + @@ -655,6 +722,10 @@ + + + + @@ -700,9 +771,6 @@ - - - - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list index a80bc9b2557..28210ff4663 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list @@ -1,24 +1,4 @@ -[Device="CY8C6347BZI-BLD53"] +[Device=CY8C6347BZI-BLD53] [Blocks] -# User IO -# CYBSP_USER_LED1 -ioss[0].port[1].pin[5] -# CYBSP_USER_LED2 -ioss[0].port[13].pin[7] -# CYBSP_USER_LED3 -ioss[0].port[0].pin[3] -# CYBSP_USER_LED4 -ioss[0].port[1].pin[1] -# CYBSP_USER_LED5 -ioss[0].port[11].pin[1] -# CYBSP_USER_BTN1 -ioss[0].port[0].pin[4] - -# Debug -# CYBSP_DEBUG_UART -scb[5] -# CYBSP_DEBUG_UART_RX -ioss[0].port[5].pin[0] -# CYBSP_DEBUG_UART_TX -ioss[0].port[5].pin[1] +# Nothing needs to be reserved for this device diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.modus index 29698a4c275..5b9ac8b1ab6 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.modus +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.modus @@ -560,8 +560,6 @@ - - - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c index cda6d4025b1..cb430a41643 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c @@ -28,7 +28,6 @@ void init_cycfg_all(void) { init_cycfg_system(); init_cycfg_clocks(); - init_cycfg_dmas(); init_cycfg_routing(); init_cycfg_peripherals(); init_cycfg_pins(); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h index 3585cf91ba1..9abc7f0f4ab 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h @@ -32,7 +32,6 @@ extern "C" { #include "cycfg_notices.h" #include "cycfg_system.h" #include "cycfg_clocks.h" -#include "cycfg_dmas.h" #include "cycfg_routing.h" #include "cycfg_peripherals.h" #include "cycfg_pins.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c index 151484a1da7..2a4822d1d43 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c @@ -32,14 +32,6 @@ .channel_num = CYBSP_USB_CLK_DIV_NUM, }; #endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SDIO_DIV_obj = - { - .type = CYHAL_RSC_CLOCK, - .block_num = CYBSP_SDIO_DIV_HW, - .channel_num = CYBSP_SDIO_DIV_NUM, - }; -#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj = { @@ -57,11 +49,11 @@ }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t peri_0_div_8_4_obj = + const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj = { .type = CYHAL_RSC_CLOCK, - .block_num = peri_0_div_8_4_HW, - .channel_num = peri_0_div_8_4_NUM, + .block_num = CYBSP_BT_UART_CLK_DIV_HW, + .channel_num = CYBSP_BT_UART_CLK_DIV_NUM, }; #endif //defined (CY_USING_HAL) @@ -75,13 +67,6 @@ void init_cycfg_clocks(void) cyhal_hwmgr_reserve(&CYBSP_USB_CLK_DIV_obj); #endif //defined (CY_USING_HAL) - Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U); - Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U); - Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SDIO_DIV_obj); -#endif //defined (CY_USING_HAL) - Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U); Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 7U); Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U); @@ -100,6 +85,6 @@ void init_cycfg_clocks(void) Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 4U, 108U); Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 4U); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&peri_0_div_8_4_obj); + cyhal_hwmgr_reserve(&CYBSP_BT_UART_CLK_DIV_obj); #endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h index 516b0c3730d..ab4a3aeaa87 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h @@ -38,25 +38,19 @@ extern "C" { #define CYBSP_USB_CLK_DIV_ENABLED 1U #define CYBSP_USB_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT #define CYBSP_USB_CLK_DIV_NUM 0U -#define CYBSP_SDIO_DIV_ENABLED 1U -#define CYBSP_SDIO_DIV_HW CY_SYSCLK_DIV_8_BIT -#define CYBSP_SDIO_DIV_NUM 0U #define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U #define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT #define CYBSP_CSD_COMM_CLK_DIV_NUM 1U #define CYBSP_CSD_CLK_DIV_ENABLED 1U #define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT #define CYBSP_CSD_CLK_DIV_NUM 3U -#define peri_0_div_8_4_ENABLED 1U -#define peri_0_div_8_4_HW CY_SYSCLK_DIV_8_BIT -#define peri_0_div_8_4_NUM 4U +#define CYBSP_BT_UART_CLK_DIV_ENABLED 1U +#define CYBSP_BT_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT +#define CYBSP_BT_UART_CLK_DIV_NUM 4U #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj; #endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_SDIO_DIV_obj; -#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj; #endif //defined (CY_USING_HAL) @@ -64,7 +58,7 @@ extern "C" { extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t peri_0_div_8_4_obj; + extern const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj; #endif //defined (CY_USING_HAL) void init_cycfg_clocks(void); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.c deleted file mode 100644 index 8d869195513..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.c +++ /dev/null @@ -1,230 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_dmas.c -* -* Description: -* DMA configuration -* This file was automatically generated and should not be modified. -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#include "cycfg_dmas.h" - -const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_0_Descriptor_0_config = -{ - .retrigger = CY_DMA_RETRIG_IM, - .interruptType = CY_DMA_1ELEMENT, - .triggerOutType = CY_DMA_1ELEMENT, - .channelState = CY_DMA_CHANNEL_DISABLED, - .triggerInType = CY_DMA_1ELEMENT, - .dataSize = CY_DMA_BYTE, - .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .descriptorType = CY_DMA_1D_TRANSFER, - .srcAddress = NULL, - .dstAddress = NULL, - .srcXincrement = 0, - .dstXincrement = 1, - .xCount = 6, - .srcYincrement = 0, - .dstYincrement = 0, - .yCount = 1, - .nextDescriptor = NULL, -}; -cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_0_Descriptor_0 = -{ - .ctl = 0UL, - .src = 0UL, - .dst = 0UL, - .xCtl = 0UL, - .yCtl = 0UL, - .nextPtr = 0UL, -}; -const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_0_channelConfig = -{ - .descriptor = &cpuss_0_dw0_0_chan_0_Descriptor_0, - .preemptable = true, - .priority = 1, - .enable = false, - .bufferable = false, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t cpuss_0_dw0_0_chan_0_obj = - { - .type = CYHAL_RSC_DMA, - .block_num = 0U, - .channel_num = cpuss_0_dw0_0_chan_0_CHANNEL, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_1_Descriptor_0_config = -{ - .retrigger = CY_DMA_RETRIG_16CYC, - .interruptType = CY_DMA_1ELEMENT, - .triggerOutType = CY_DMA_1ELEMENT, - .channelState = CY_DMA_CHANNEL_DISABLED, - .triggerInType = CY_DMA_1ELEMENT, - .dataSize = CY_DMA_BYTE, - .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .descriptorType = CY_DMA_1D_TRANSFER, - .srcAddress = NULL, - .dstAddress = NULL, - .srcXincrement = 1, - .dstXincrement = 0, - .xCount = 5, - .srcYincrement = 0, - .dstYincrement = 0, - .yCount = 1, - .nextDescriptor = NULL, -}; -cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_1_Descriptor_0 = -{ - .ctl = 0UL, - .src = 0UL, - .dst = 0UL, - .xCtl = 0UL, - .yCtl = 0UL, - .nextPtr = 0UL, -}; -const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_1_channelConfig = -{ - .descriptor = &cpuss_0_dw0_0_chan_1_Descriptor_0, - .preemptable = true, - .priority = 1, - .enable = false, - .bufferable = false, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t cpuss_0_dw0_0_chan_1_obj = - { - .type = CYHAL_RSC_DMA, - .block_num = 0U, - .channel_num = cpuss_0_dw0_0_chan_1_CHANNEL, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_1_Descriptor_0_config = -{ - .retrigger = CY_DMA_RETRIG_4CYC, - .interruptType = CY_DMA_DESCR, - .triggerOutType = CY_DMA_1ELEMENT, - .channelState = CY_DMA_CHANNEL_DISABLED, - .triggerInType = CY_DMA_X_LOOP, - .dataSize = CY_DMA_HALFWORD, - .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .descriptorType = CY_DMA_2D_TRANSFER, - .srcAddress = NULL, - .dstAddress = NULL, - .srcXincrement = 2, - .dstXincrement = 0, - .xCount = 10, - .srcYincrement = 10, - .dstYincrement = 0, - .yCount = 2, - .nextDescriptor = NULL, -}; -cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_1_Descriptor_0 = -{ - .ctl = 0UL, - .src = 0UL, - .dst = 0UL, - .xCtl = 0UL, - .yCtl = 0UL, - .nextPtr = 0UL, -}; -const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_1_channelConfig = -{ - .descriptor = &cpuss_0_dw1_0_chan_1_Descriptor_0, - .preemptable = false, - .priority = 0, - .enable = false, - .bufferable = false, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t cpuss_0_dw1_0_chan_1_obj = - { - .type = CYHAL_RSC_DMA, - .block_num = 1U, - .channel_num = cpuss_0_dw1_0_chan_1_CHANNEL, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_3_Descriptor_0_config = -{ - .retrigger = CY_DMA_RETRIG_IM, - .interruptType = CY_DMA_DESCR, - .triggerOutType = CY_DMA_1ELEMENT, - .channelState = CY_DMA_CHANNEL_DISABLED, - .triggerInType = CY_DMA_X_LOOP, - .dataSize = CY_DMA_HALFWORD, - .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .descriptorType = CY_DMA_2D_TRANSFER, - .srcAddress = NULL, - .dstAddress = NULL, - .srcXincrement = 0, - .dstXincrement = 2, - .xCount = 10, - .srcYincrement = 0, - .dstYincrement = 10, - .yCount = 2, - .nextDescriptor = NULL, -}; -cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_3_Descriptor_0 = -{ - .ctl = 0UL, - .src = 0UL, - .dst = 0UL, - .xCtl = 0UL, - .yCtl = 0UL, - .nextPtr = 0UL, -}; -const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_3_channelConfig = -{ - .descriptor = &cpuss_0_dw1_0_chan_3_Descriptor_0, - .preemptable = false, - .priority = 0, - .enable = false, - .bufferable = false, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t cpuss_0_dw1_0_chan_3_obj = - { - .type = CYHAL_RSC_DMA, - .block_num = 1U, - .channel_num = cpuss_0_dw1_0_chan_3_CHANNEL, - }; -#endif //defined (CY_USING_HAL) - - -void init_cycfg_dmas(void) -{ -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&cpuss_0_dw0_0_chan_0_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&cpuss_0_dw0_0_chan_1_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&cpuss_0_dw1_0_chan_1_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&cpuss_0_dw1_0_chan_3_obj); -#endif //defined (CY_USING_HAL) -} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.h deleted file mode 100644 index d6c0d6587db..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.h +++ /dev/null @@ -1,87 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_dmas.h -* -* Description: -* DMA configuration -* This file was automatically generated and should not be modified. -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#if !defined(CYCFG_DMAS_H) -#define CYCFG_DMAS_H - -#include "cycfg_notices.h" -#include "cy_dma.h" -#if defined (CY_USING_HAL) - #include "cyhal_hwmgr.h" -#endif //defined (CY_USING_HAL) - -#if defined(__cplusplus) -extern "C" { -#endif - -#define cpuss_0_dw0_0_chan_0_ENABLED 1U -#define cpuss_0_dw0_0_chan_0_HW DW0 -#define cpuss_0_dw0_0_chan_0_CHANNEL 0U -#define cpuss_0_dw0_0_chan_0_IRQ cpuss_interrupts_dw0_0_IRQn -#define cpuss_0_dw0_0_chan_1_ENABLED 1U -#define cpuss_0_dw0_0_chan_1_HW DW0 -#define cpuss_0_dw0_0_chan_1_CHANNEL 1U -#define cpuss_0_dw0_0_chan_1_IRQ cpuss_interrupts_dw0_1_IRQn -#define cpuss_0_dw1_0_chan_1_ENABLED 1U -#define cpuss_0_dw1_0_chan_1_HW DW1 -#define cpuss_0_dw1_0_chan_1_CHANNEL 1U -#define cpuss_0_dw1_0_chan_1_IRQ cpuss_interrupts_dw1_1_IRQn -#define cpuss_0_dw1_0_chan_3_ENABLED 1U -#define cpuss_0_dw1_0_chan_3_HW DW1 -#define cpuss_0_dw1_0_chan_3_CHANNEL 3U -#define cpuss_0_dw1_0_chan_3_IRQ cpuss_interrupts_dw1_3_IRQn - -extern const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_0_Descriptor_0_config; -extern cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_0_Descriptor_0; -extern const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_0_channelConfig; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t cpuss_0_dw0_0_chan_0_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_1_Descriptor_0_config; -extern cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_1_Descriptor_0; -extern const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_1_channelConfig; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t cpuss_0_dw0_0_chan_1_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_1_Descriptor_0_config; -extern cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_1_Descriptor_0; -extern const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_1_channelConfig; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t cpuss_0_dw1_0_chan_1_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_3_Descriptor_0_config; -extern cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_3_Descriptor_0; -extern const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_3_channelConfig; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t cpuss_0_dw1_0_chan_3_obj; -#endif //defined (CY_USING_HAL) - -void init_cycfg_dmas(void); - -#if defined(__cplusplus) -} -#endif - - -#endif /* CYCFG_DMAS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h index 106b3ad7a05..3d5385559e5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h @@ -118,7 +118,6 @@ extern "C" { #define CYBSP_USBUART_ACTIVE_ENDPOINTS_MASK 0U #define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 512U #define CYBSP_USBUART_ENDPOINTS_ACCESS_TYPE 0U -#define CYBSP_USBUART_USB_CORE 4U #define CYBSP_USBUART_HW USBFS0 #define CYBSP_USBUART_HI_IRQ usb_interrupt_hi_IRQn #define CYBSP_USBUART_MED_IRQ usb_interrupt_med_IRQn diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c index ca1cca68968..7daee6bb073 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c @@ -216,11 +216,11 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config = .channel_num = CYBSP_QSPI_SCK_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_0_config = +const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = ioss_0_port_14_pin_0_HSIOM, + .hsiom = CYBSP_USB_DP_HSIOM, .intEdge = CY_GPIO_INTR_DISABLE, .intMask = 0UL, .vtrip = CY_GPIO_VTRIP_CMOS, @@ -233,18 +233,18 @@ const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_0_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t ioss_0_port_14_pin_0_obj = + const cyhal_resource_inst_t CYBSP_USB_DP_obj = { .type = CYHAL_RSC_GPIO, - .block_num = ioss_0_port_14_pin_0_PORT_NUM, - .channel_num = ioss_0_port_14_pin_0_PIN, + .block_num = CYBSP_USB_DP_PORT_NUM, + .channel_num = CYBSP_USB_DP_PIN, }; #endif //defined (CY_USING_HAL) -const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_1_config = +const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config = { .outVal = 1, .driveMode = CY_GPIO_DM_ANALOG, - .hsiom = ioss_0_port_14_pin_1_HSIOM, + .hsiom = CYBSP_USB_DM_HSIOM, .intEdge = CY_GPIO_INTR_DISABLE, .intMask = 0UL, .vtrip = CY_GPIO_VTRIP_CMOS, @@ -257,11 +257,11 @@ const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_1_config = .vohSel = 0UL, }; #if defined (CY_USING_HAL) - const cyhal_resource_inst_t ioss_0_port_14_pin_1_obj = + const cyhal_resource_inst_t CYBSP_USB_DM_obj = { .type = CYHAL_RSC_GPIO, - .block_num = ioss_0_port_14_pin_1_PORT_NUM, - .channel_num = ioss_0_port_14_pin_1_PIN, + .block_num = CYBSP_USB_DM_PORT_NUM, + .channel_num = CYBSP_USB_DM_PIN, }; #endif //defined (CY_USING_HAL) const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = @@ -884,14 +884,14 @@ void init_cycfg_pins(void) cyhal_hwmgr_reserve(&CYBSP_QSPI_SCK_obj); #endif //defined (CY_USING_HAL) - Cy_GPIO_Pin_Init(ioss_0_port_14_pin_0_PORT, ioss_0_port_14_pin_0_PIN, &ioss_0_port_14_pin_0_config); + Cy_GPIO_Pin_Init(CYBSP_USB_DP_PORT, CYBSP_USB_DP_PIN, &CYBSP_USB_DP_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&ioss_0_port_14_pin_0_obj); + cyhal_hwmgr_reserve(&CYBSP_USB_DP_obj); #endif //defined (CY_USING_HAL) - Cy_GPIO_Pin_Init(ioss_0_port_14_pin_1_PORT, ioss_0_port_14_pin_1_PIN, &ioss_0_port_14_pin_1_config); + Cy_GPIO_Pin_Init(CYBSP_USB_DM_PORT, CYBSP_USB_DM_PIN, &CYBSP_USB_DM_config); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&ioss_0_port_14_pin_1_obj); + cyhal_hwmgr_reserve(&CYBSP_USB_DM_obj); #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h index 9bf6916e7ba..95f624c7a54 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h @@ -228,51 +228,53 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_QSPI_SCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG #endif //defined (CY_USING_HAL) -#define ioss_0_port_14_pin_0_ENABLED 1U -#define ioss_0_port_14_pin_0_PORT GPIO_PRT14 -#define ioss_0_port_14_pin_0_PORT_NUM 14U -#define ioss_0_port_14_pin_0_PIN 0U -#define ioss_0_port_14_pin_0_NUM 0U -#define ioss_0_port_14_pin_0_DRIVEMODE CY_GPIO_DM_ANALOG -#define ioss_0_port_14_pin_0_INIT_DRIVESTATE 1 +#define CYBSP_USB_DP_ENABLED 1U +#define CYBSP_USB_DP_PORT GPIO_PRT14 +#define CYBSP_USB_DP_PORT_NUM 14U +#define CYBSP_USB_DP_PIN 0U +#define CYBSP_USB_DP_NUM 0U +#define CYBSP_USB_DP_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_USB_DP_INIT_DRIVESTATE 1 #ifndef ioss_0_port_14_pin_0_HSIOM #define ioss_0_port_14_pin_0_HSIOM HSIOM_SEL_GPIO #endif -#define ioss_0_port_14_pin_0_IRQ ioss_interrupts_gpio_14_IRQn +#define CYBSP_USB_DP_HSIOM ioss_0_port_14_pin_0_HSIOM +#define CYBSP_USB_DP_IRQ ioss_interrupts_gpio_14_IRQn #if defined (CY_USING_HAL) - #define ioss_0_port_14_pin_0_HAL_PORT_PIN P14_0 + #define CYBSP_USB_DP_HAL_PORT_PIN P14_0 #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define ioss_0_port_14_pin_0_HAL_IRQ CYHAL_GPIO_IRQ_NONE + #define CYBSP_USB_DP_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define ioss_0_port_14_pin_0_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_USB_DP_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define ioss_0_port_14_pin_0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG + #define CYBSP_USB_DP_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG #endif //defined (CY_USING_HAL) -#define ioss_0_port_14_pin_1_ENABLED 1U -#define ioss_0_port_14_pin_1_PORT GPIO_PRT14 -#define ioss_0_port_14_pin_1_PORT_NUM 14U -#define ioss_0_port_14_pin_1_PIN 1U -#define ioss_0_port_14_pin_1_NUM 1U -#define ioss_0_port_14_pin_1_DRIVEMODE CY_GPIO_DM_ANALOG -#define ioss_0_port_14_pin_1_INIT_DRIVESTATE 1 +#define CYBSP_USB_DM_ENABLED 1U +#define CYBSP_USB_DM_PORT GPIO_PRT14 +#define CYBSP_USB_DM_PORT_NUM 14U +#define CYBSP_USB_DM_PIN 1U +#define CYBSP_USB_DM_NUM 1U +#define CYBSP_USB_DM_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_USB_DM_INIT_DRIVESTATE 1 #ifndef ioss_0_port_14_pin_1_HSIOM #define ioss_0_port_14_pin_1_HSIOM HSIOM_SEL_GPIO #endif -#define ioss_0_port_14_pin_1_IRQ ioss_interrupts_gpio_14_IRQn +#define CYBSP_USB_DM_HSIOM ioss_0_port_14_pin_1_HSIOM +#define CYBSP_USB_DM_IRQ ioss_interrupts_gpio_14_IRQn #if defined (CY_USING_HAL) - #define ioss_0_port_14_pin_1_HAL_PORT_PIN P14_1 + #define CYBSP_USB_DM_HAL_PORT_PIN P14_1 #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define ioss_0_port_14_pin_1_HAL_IRQ CYHAL_GPIO_IRQ_NONE + #define CYBSP_USB_DM_HAL_IRQ CYHAL_GPIO_IRQ_NONE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define ioss_0_port_14_pin_1_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_USB_DM_HAL_DIR CYHAL_GPIO_DIR_INPUT #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - #define ioss_0_port_14_pin_1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG + #define CYBSP_USB_DM_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG #endif //defined (CY_USING_HAL) #define CYBSP_CSD_TX_ENABLED 1U #define CYBSP_CSD_TX_PORT GPIO_PRT1 @@ -883,13 +885,13 @@ extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj; #endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_0_config; +extern const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config; #if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t ioss_0_port_14_pin_0_obj; + extern const cyhal_resource_inst_t CYBSP_USB_DP_obj; #endif //defined (CY_USING_HAL) -extern const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_1_config; +extern const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config; #if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t ioss_0_port_14_pin_1_obj; + extern const cyhal_resource_inst_t CYBSP_USB_DM_obj; #endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config; #if defined (CY_USING_HAL) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c index c4e5bcf916f..14d433859db 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c @@ -24,7 +24,7 @@ #include "cycfg_qspi_memslot.h" -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0xECU, @@ -42,7 +42,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd = .dataWidth = CY_SMIF_WIDTH_QUAD }; -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x06U, @@ -60,7 +60,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x04U, @@ -78,7 +78,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0xDCU, @@ -96,7 +96,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x60U, @@ -114,7 +114,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x34U, @@ -132,7 +132,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd = .dataWidth = CY_SMIF_WIDTH_QUAD }; -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x35U, @@ -150,7 +150,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x05U, @@ -168,7 +168,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x01U, @@ -186,34 +186,34 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 = +const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0 = { /* Specifies the number of address bytes used by the memory slave device. */ .numOfAddrBytes = 0x04U, /* The size of the memory. */ .memSize = 0x04000000U, /* Specifies the Read command. */ - .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readCmd, + .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readCmd, /* Specifies the Write Enable command. */ - .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd, + .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd, /* Specifies the Write Disable command. */ - .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd, + .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd, /* Specifies the Erase command. */ - .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd, + .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd, /* Specifies the sector size of each erase. */ .eraseSize = 0x00040000U, /* Specifies the Chip Erase command. */ - .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd, + .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd, /* Specifies the Program command. */ - .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_programCmd, + .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_programCmd, /* Specifies the page size for programming. */ .programSize = 0x00000200U, /* Specifies the command to read the QE-containing status register. */ - .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd, + .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd, /* Specifies the command to read the WIP-containing status register. */ - .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd, + .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd, /* Specifies the command to write into the QE-containing status register. */ - .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd, + .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd, /* The mask for the status register. */ .stsRegBusyMask = 0x01U, /* The mask for the status register. */ @@ -226,7 +226,7 @@ const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 = .programTime = 1300U }; -const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 = +const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0 = { /* Determines the slot number where the memory device is placed. */ .slaveSelect = CY_SMIF_SLAVE_SELECT_0, @@ -244,11 +244,11 @@ const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 = Valid when the memory mapped mode is enabled. */ .dualQuadSlots = 0, /* The configuration of the device. */ - .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 + .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0 }; const cy_stc_smif_mem_config_t* const smifMemConfigs[] = { - &S25FL512SX4byteaddr_SlaveSlot_0 + &S25FL512S_4byteaddr_SlaveSlot_0 }; const cy_stc_smif_block_config_t smifBlockConfig = diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h index 32f9b49b2e6..0ee62b1d559 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h @@ -28,19 +28,19 @@ #define CY_SMIF_DEVICE_NUM 1 -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd; - -extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0; - -extern const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd; + +extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0; + +extern const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0; extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM]; extern const cy_stc_smif_block_config_t smifBlockConfig; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list index c58ceb548d5..79a5f7bedc4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list @@ -1,31 +1,14 @@ -[Device="CY8C6247BZI-D54"] +[Device=CY8C6247BZI-D54] [Blocks] -# User IO -# CYBSP_USER_LED1 -ioss[0].port[1].pin[5] -# CYBSP_USER_LED2 -ioss[0].port[13].pin[7] -# CYBSP_USER_LED3 -ioss[0].port[0].pin[3] -# CYBSP_USER_LED4 -ioss[0].port[1].pin[1] -# CYBSP_USER_LED5 -ioss[0].port[11].pin[1] -# CYBSP_USER_BTN1 -ioss[0].port[0].pin[4] - -# Debug -# CYBSP_DEBUG_UART -scb[5] -# CYBSP_DEBUG_UART_RX -ioss[0].port[5].pin[0] -# CYBSP_DEBUG_UART_TX -ioss[0].port[5].pin[1] - # WIFI # CYBSP_WIFI_SDIO udb[0] +peri[0].div_8[0] +cpuss[0].dw0[0].chan[0] +cpuss[0].dw0[0].chan[1] +cpuss[0].dw1[0].chan[1] +cpuss[0].dw1[0].chan[3] # CYBSP_WIFI_SDIO_D0 ioss[0].port[2].pin[0] # CYBSP_WIFI_SDIO_D1 @@ -39,4 +22,21 @@ ioss[0].port[2].pin[4] # CYBSP_WIFI_SDIO_CLK ioss[0].port[2].pin[5] # CYBSP_WIFI_WL_REG_ON -ioss[0].port[2].pin[6] \ No newline at end of file +ioss[0].port[2].pin[6] + +[RoutingResources] +# CYBSP_WIFI_SDIO +cpuss[0].dw0_tr_in[0] +cpuss[0].dw0_tr_in[1] +cpuss[0].dw1_tr_in[1] +cpuss[0].dw1_tr_in[3] + +udb[0].tr_udb[0] +udb[0].tr_udb[1] +udb[0].tr_udb[3] +udb[0].tr_udb[7] + +tr_group[0].input[43] +tr_group[0].input[44] +tr_group[0].input[47] +tr_group[0].input[48] diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.modus index 089526cce09..ac79c2d9f75 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.modus +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.modus @@ -8,114 +8,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -232,7 +124,7 @@ - + @@ -242,7 +134,7 @@ - + @@ -497,11 +389,6 @@ - - - - - @@ -512,7 +399,7 @@ - + @@ -673,7 +560,6 @@ - @@ -713,12 +599,10 @@ - - - + - + @@ -887,8 +771,6 @@ - - - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c index 3639c4da05d..06429f5183b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c @@ -24,6 +24,14 @@ #include "cycfg_clocks.h" +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj = + { + .type = CYHAL_RSC_CLOCK, + .block_num = CYBSP_USB_CLK_DIV_HW, + .channel_num = CYBSP_USB_CLK_DIV_NUM, + }; +#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = { @@ -52,6 +60,13 @@ void init_cycfg_clocks(void) { + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 499U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_USB_CLK_DIV_obj); +#endif //defined (CY_USING_HAL) + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U); Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 255U); Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h index 30aec8b8b40..eb49bf1b7cd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h @@ -35,6 +35,9 @@ extern "C" { #endif +#define CYBSP_USB_CLK_DIV_ENABLED 1U +#define CYBSP_USB_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT +#define CYBSP_USB_CLK_DIV_NUM 0U #define CYBSP_CSD_CLK_DIV_ENABLED 1U #define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT #define CYBSP_CSD_CLK_DIV_NUM 0U @@ -45,6 +48,9 @@ extern "C" { #define CYBSP_BT_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT #define CYBSP_BT_UART_CLK_DIV_NUM 3U +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj; +#endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj; #endif //defined (CY_USING_HAL) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c index 022f8d72083..edb443da8a6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c @@ -24,6 +24,20 @@ #include "cycfg_peripherals.h" +#define CYBSP_USBUART_INTR_LVL_SEL (CY_USBFS_DEV_DRV_SET_SOF_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_BUS_RESET_LVL(0x2U) | \ + CY_USBFS_DEV_DRV_SET_EP0_LVL(0x2U) | \ + CY_USBFS_DEV_DRV_SET_LPM_LVL(0x0U) | \ + CY_USBFS_DEV_DRV_SET_ARB_EP_LVL(0x0U) | \ + CY_USBFS_DEV_DRV_SET_EP1_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP2_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP3_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP4_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP5_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP6_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP7_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP8_LVL(0x1U)) + cy_stc_csd_context_t cy_csd_0_context = { .lockKey = CY_CSD_NONE_KEY, @@ -136,6 +150,31 @@ const cy_stc_rtc_config_t CYBSP_RTC_config = .channel_num = 0U, }; #endif //defined (CY_USING_HAL) +const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config = +{ + .mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU, + .epAccess = CY_USBFS_DEV_DRV_USE_8_BITS_DR, + .epBuffer = NULL, + .epBufferSize = 0U, + .dmaConfig[0] = NULL, + .dmaConfig[1] = NULL, + .dmaConfig[2] = NULL, + .dmaConfig[3] = NULL, + .dmaConfig[4] = NULL, + .dmaConfig[5] = NULL, + .dmaConfig[6] = NULL, + .dmaConfig[7] = NULL, + .enableLpm = false, + .intrLevelSel = CYBSP_USBUART_INTR_LVL_SEL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_USBUART_obj = + { + .type = CYHAL_RSC_USB, + .block_num = 0U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) void init_cycfg_peripherals(void) @@ -163,4 +202,9 @@ void init_cycfg_peripherals(void) #if defined (CY_USING_HAL) cyhal_hwmgr_reserve(&CYBSP_RTC_obj); #endif //defined (CY_USING_HAL) + + Cy_SysClk_PeriphAssignDivider(PCLK_USB_CLOCK_DEV_BRS, CY_SYSCLK_DIV_16_BIT, 0U); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_USBUART_obj); +#endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h index 2749cb0f4b6..0df379d5692 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h @@ -37,6 +37,7 @@ #include "cycfg_qspi_memslot.h" #include "cy_mcwdt.h" #include "cy_rtc.h" +#include "cy_usbfs_dev_drv.h" #if defined(__cplusplus) extern "C" { @@ -113,6 +114,14 @@ extern "C" { #define CYBSP_RTC_100_YEAR_OFFSET (8U) #define CYBSP_RTC_10_YEAR_OFFSET (4U) #define CYBSP_RTC_YEAR_OFFSET (0U) +#define CYBSP_USBUART_ENABLED 1U +#define CYBSP_USBUART_ACTIVE_ENDPOINTS_MASK 0U +#define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 512U +#define CYBSP_USBUART_ENDPOINTS_ACCESS_TYPE 0U +#define CYBSP_USBUART_HW USBFS0 +#define CYBSP_USBUART_HI_IRQ usb_interrupt_hi_IRQn +#define CYBSP_USBUART_MED_IRQ usb_interrupt_med_IRQn +#define CYBSP_USBUART_LO_IRQ usb_interrupt_lo_IRQn extern cy_stc_csd_context_t cy_csd_0_context; extern const cy_stc_scb_uart_config_t CYBSP_BT_UART_config; @@ -135,6 +144,10 @@ extern const cy_stc_rtc_config_t CYBSP_RTC_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_RTC_obj; #endif //defined (CY_USING_HAL) +extern const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_USBUART_obj; +#endif //defined (CY_USING_HAL) void init_cycfg_peripherals(void); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c index 54a6937a3e6..d7a628353bb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c @@ -240,6 +240,54 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config = .channel_num = CYBSP_QSPI_SCK_PIN, }; #endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_USB_DP_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_USB_DP_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_USB_DP_PORT_NUM, + .channel_num = CYBSP_USB_DP_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_USB_DM_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_USB_DM_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_USB_DM_PORT_NUM, + .channel_num = CYBSP_USB_DM_PIN, + }; +#endif //defined (CY_USING_HAL) const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config = { .outVal = 1, @@ -841,6 +889,16 @@ void init_cycfg_pins(void) cyhal_hwmgr_reserve(&CYBSP_QSPI_SCK_obj); #endif //defined (CY_USING_HAL) + Cy_GPIO_Pin_Init(CYBSP_USB_DP_PORT, CYBSP_USB_DP_PIN, &CYBSP_USB_DP_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_USB_DP_obj); +#endif //defined (CY_USING_HAL) + + Cy_GPIO_Pin_Init(CYBSP_USB_DM_PORT, CYBSP_USB_DM_PIN, &CYBSP_USB_DM_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_USB_DM_obj); +#endif //defined (CY_USING_HAL) + #if defined (CY_USING_HAL) cyhal_hwmgr_reserve(&CYBSP_CSD_TX_obj); #endif //defined (CY_USING_HAL) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h index b04921c52fd..76eaef0b401 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h @@ -252,6 +252,54 @@ extern "C" { #if defined (CY_USING_HAL) #define CYBSP_QSPI_SCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG #endif //defined (CY_USING_HAL) +#define CYBSP_USB_DP_ENABLED 1U +#define CYBSP_USB_DP_PORT GPIO_PRT14 +#define CYBSP_USB_DP_PORT_NUM 14U +#define CYBSP_USB_DP_PIN 0U +#define CYBSP_USB_DP_NUM 0U +#define CYBSP_USB_DP_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_USB_DP_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_14_pin_0_HSIOM + #define ioss_0_port_14_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_USB_DP_HSIOM ioss_0_port_14_pin_0_HSIOM +#define CYBSP_USB_DP_IRQ ioss_interrupts_gpio_14_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_USB_DP_HAL_PORT_PIN P14_0 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_USB_DP_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_USB_DP_HAL_DIR CYHAL_GPIO_DIR_INPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_USB_DP_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG +#endif //defined (CY_USING_HAL) +#define CYBSP_USB_DM_ENABLED 1U +#define CYBSP_USB_DM_PORT GPIO_PRT14 +#define CYBSP_USB_DM_PORT_NUM 14U +#define CYBSP_USB_DM_PIN 1U +#define CYBSP_USB_DM_NUM 1U +#define CYBSP_USB_DM_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_USB_DM_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_14_pin_1_HSIOM + #define ioss_0_port_14_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_USB_DM_HSIOM ioss_0_port_14_pin_1_HSIOM +#define CYBSP_USB_DM_IRQ ioss_interrupts_gpio_14_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_USB_DM_HAL_PORT_PIN P14_1 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_USB_DM_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_USB_DM_HAL_DIR CYHAL_GPIO_DIR_INPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_USB_DM_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG +#endif //defined (CY_USING_HAL) #define CYBSP_CSD_TX_ENABLED 1U #define CYBSP_CSD_TX_PORT GPIO_PRT1 #define CYBSP_CSD_TX_PORT_NUM 1U @@ -841,6 +889,14 @@ extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj; #endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_USB_DP_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_USB_DM_obj; +#endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config; #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_CSD_TX_obj; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c index c4e5bcf916f..14d433859db 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c @@ -24,7 +24,7 @@ #include "cycfg_qspi_memslot.h" -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0xECU, @@ -42,7 +42,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd = .dataWidth = CY_SMIF_WIDTH_QUAD }; -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x06U, @@ -60,7 +60,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x04U, @@ -78,7 +78,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0xDCU, @@ -96,7 +96,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x60U, @@ -114,7 +114,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x34U, @@ -132,7 +132,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd = .dataWidth = CY_SMIF_WIDTH_QUAD }; -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x35U, @@ -150,7 +150,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x05U, @@ -168,7 +168,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x01U, @@ -186,34 +186,34 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 = +const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0 = { /* Specifies the number of address bytes used by the memory slave device. */ .numOfAddrBytes = 0x04U, /* The size of the memory. */ .memSize = 0x04000000U, /* Specifies the Read command. */ - .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readCmd, + .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readCmd, /* Specifies the Write Enable command. */ - .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd, + .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd, /* Specifies the Write Disable command. */ - .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd, + .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd, /* Specifies the Erase command. */ - .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd, + .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd, /* Specifies the sector size of each erase. */ .eraseSize = 0x00040000U, /* Specifies the Chip Erase command. */ - .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd, + .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd, /* Specifies the Program command. */ - .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_programCmd, + .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_programCmd, /* Specifies the page size for programming. */ .programSize = 0x00000200U, /* Specifies the command to read the QE-containing status register. */ - .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd, + .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd, /* Specifies the command to read the WIP-containing status register. */ - .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd, + .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd, /* Specifies the command to write into the QE-containing status register. */ - .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd, + .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd, /* The mask for the status register. */ .stsRegBusyMask = 0x01U, /* The mask for the status register. */ @@ -226,7 +226,7 @@ const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 = .programTime = 1300U }; -const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 = +const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0 = { /* Determines the slot number where the memory device is placed. */ .slaveSelect = CY_SMIF_SLAVE_SELECT_0, @@ -244,11 +244,11 @@ const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 = Valid when the memory mapped mode is enabled. */ .dualQuadSlots = 0, /* The configuration of the device. */ - .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 + .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0 }; const cy_stc_smif_mem_config_t* const smifMemConfigs[] = { - &S25FL512SX4byteaddr_SlaveSlot_0 + &S25FL512S_4byteaddr_SlaveSlot_0 }; const cy_stc_smif_block_config_t smifBlockConfig = diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h index 32f9b49b2e6..0ee62b1d559 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h @@ -28,19 +28,19 @@ #define CY_SMIF_DEVICE_NUM 1 -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd; - -extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0; - -extern const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd; + +extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0; + +extern const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0; extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM]; extern const cy_stc_smif_block_config_t smifBlockConfig; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c index 89e36dce129..d2306adee24 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c @@ -76,7 +76,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = .refDiv = 20U, .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4, .enableOutputDiv = true, - .lockTolerance = 10U, + .lockTolerance = 4U, .igain = 9U, .pgain = 5U, .settlingCount = 8U, diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list index 779bac9b78d..8453a4470f1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list @@ -1,20 +1,6 @@ -[Device="CY8C624ABZI-D44"] +[Device=CY8C624ABZI-D44] [Blocks] -# User IO -# CYBSP_USER_LED1 -ioss[0].port[13].pin[7] -# CYBSP_USER_BTN1 -ioss[0].port[0].pin[4] - -# Debug -# CYBSP_DEBUG_UART -scb[5] -# CYBSP_DEBUG_UART_RX -ioss[0].port[5].pin[0] -# CYBSP_DEBUG_UART_TX -ioss[0].port[5].pin[1] - # WIFI # CYBSP_WIFI_SDIO sdhc[0] diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense index 239c647ba50..43d6108110e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense @@ -74,5 +74,336 @@ - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus index 586b4c9934f..7212a7127ae 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus @@ -1,5 +1,5 @@ - + @@ -134,6 +134,26 @@ + + + + + + + + + + + + + + + + + + + + @@ -364,6 +384,11 @@ + + + + + @@ -474,7 +499,7 @@ - + @@ -531,7 +556,6 @@ - @@ -571,6 +595,27 @@ + + + + + + + + + + + + + + + + + + + + + @@ -645,6 +690,18 @@ + + + + + + + + + + + + @@ -661,6 +718,10 @@ + + + + @@ -706,8 +767,6 @@ - - - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c index 54dbf991f99..36da6ec41b1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c @@ -24,18 +24,37 @@ #include "cycfg_clocks.h" +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj = + { + .type = CYHAL_RSC_CLOCK, + .block_num = CYBSP_USB_CLK_DIV_HW, + .channel_num = CYBSP_USB_CLK_DIV_NUM, + }; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_I2C_CLK_DIV_obj = + { + .type = CYHAL_RSC_CLOCK, + .block_num = CYBSP_I2C_CLK_DIV_HW, + .channel_num = CYBSP_I2C_CLK_DIV_NUM, + }; +#endif //defined (CY_USING_HAL) + void init_cycfg_clocks(void) { Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U); Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 499U); Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U); - - Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U); - Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 35U); - Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_USB_CLK_DIV_obj); +#endif //defined (CY_USING_HAL) Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U); Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 3U); Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_I2C_CLK_DIV_obj); +#endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h index aef4c18422f..aee335b7032 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h @@ -27,21 +27,28 @@ #include "cycfg_notices.h" #include "cy_sysclk.h" +#if defined (CY_USING_HAL) + #include "cyhal_hwmgr.h" +#endif //defined (CY_USING_HAL) #if defined(__cplusplus) extern "C" { #endif -#define peri_0_div_16_0_ENABLED 1U -#define peri_0_div_16_0_HW CY_SYSCLK_DIV_16_BIT -#define peri_0_div_16_0_NUM 0U -#define CYBSP_DEBUG_UART_CLK_DIV_ENABLED 1U -#define CYBSP_DEBUG_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT -#define CYBSP_DEBUG_UART_CLK_DIV_NUM 0U +#define CYBSP_USB_CLK_DIV_ENABLED 1U +#define CYBSP_USB_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT +#define CYBSP_USB_CLK_DIV_NUM 0U #define CYBSP_I2C_CLK_DIV_ENABLED 1U #define CYBSP_I2C_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT #define CYBSP_I2C_CLK_DIV_NUM 1U +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_I2C_CLK_DIV_obj; +#endif //defined (CY_USING_HAL) + void init_cycfg_clocks(void); #if defined(__cplusplus) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c index 3fce96da0b7..3b6a06b6ef9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c @@ -24,6 +24,20 @@ #include "cycfg_peripherals.h" +#define CYBSP_USBUART_INTR_LVL_SEL (CY_USBFS_DEV_DRV_SET_SOF_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_BUS_RESET_LVL(0x2U) | \ + CY_USBFS_DEV_DRV_SET_EP0_LVL(0x2U) | \ + CY_USBFS_DEV_DRV_SET_LPM_LVL(0x0U) | \ + CY_USBFS_DEV_DRV_SET_ARB_EP_LVL(0x0U) | \ + CY_USBFS_DEV_DRV_SET_EP1_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP2_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP3_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP4_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP5_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP6_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP7_LVL(0x1U) | \ + CY_USBFS_DEV_DRV_SET_EP8_LVL(0x1U)) + const cy_stc_scb_ezi2c_config_t CYBSP_I2C_config = { .numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS, @@ -32,34 +46,14 @@ const cy_stc_scb_ezi2c_config_t CYBSP_I2C_config = .subAddressSize = CY_SCB_EZI2C_SUB_ADDR8_BITS, .enableWakeFromSleep = false, }; -const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config = -{ - .uartMode = CY_SCB_UART_STANDARD, - .enableMutliProcessorMode = false, - .smartCardRetryOnNack = false, - .irdaInvertRx = false, - .irdaEnableLowPowerReceiver = false, - .oversample = 12, - .enableMsbFirst = false, - .dataWidth = 8UL, - .parity = CY_SCB_UART_PARITY_NONE, - .stopBits = CY_SCB_UART_STOP_BITS_1, - .enableInputFilter = false, - .breakWidth = 11UL, - .dropOnFrameError = false, - .dropOnParityError = false, - .receiverAddress = 0x0UL, - .receiverAddressMask = 0x0UL, - .acceptAddrInFifo = false, - .enableCts = false, - .ctsPolarity = CY_SCB_UART_ACTIVE_LOW, - .rtsRxFifoLevel = 0UL, - .rtsPolarity = CY_SCB_UART_ACTIVE_LOW, - .rxFifoTriggerLevel = 63UL, - .rxFifoIntEnableMask = 0UL, - .txFifoTriggerLevel = 63UL, - .txFifoIntEnableMask = 0UL, -}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_I2C_obj = + { + .type = CYHAL_RSC_SCB, + .block_num = 3U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) const cy_stc_smif_config_t CYBSP_QSPI_config = { .mode = (uint32_t)CY_SMIF_NORMAL, @@ -67,11 +61,54 @@ const cy_stc_smif_config_t CYBSP_QSPI_config = .rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK, .blockEvent = (uint32_t)CY_SMIF_BUS_ERROR, }; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_QSPI_obj = + { + .type = CYHAL_RSC_SMIF, + .block_num = 0U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config = +{ + .mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU, + .epAccess = CY_USBFS_DEV_DRV_USE_8_BITS_DR, + .epBuffer = NULL, + .epBufferSize = 0U, + .dmaConfig[0] = NULL, + .dmaConfig[1] = NULL, + .dmaConfig[2] = NULL, + .dmaConfig[3] = NULL, + .dmaConfig[4] = NULL, + .dmaConfig[5] = NULL, + .dmaConfig[6] = NULL, + .dmaConfig[7] = NULL, + .enableLpm = false, + .intrLevelSel = CYBSP_USBUART_INTR_LVL_SEL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_USBUART_obj = + { + .type = CYHAL_RSC_USB, + .block_num = 0U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) void init_cycfg_peripherals(void) { Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_I2C_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_QSPI_obj); +#endif //defined (CY_USING_HAL) - Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U); + Cy_SysClk_PeriphAssignDivider(PCLK_USB_CLOCK_DEV_BRS, CY_SYSCLK_DIV_16_BIT, 0U); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_USBUART_obj); +#endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h index 871b62dc66e..7680b5fe23c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h @@ -28,9 +28,12 @@ #include "cycfg_notices.h" #include "cy_scb_ezi2c.h" #include "cy_sysclk.h" -#include "cy_scb_uart.h" +#if defined (CY_USING_HAL) + #include "cyhal_hwmgr.h" +#endif //defined (CY_USING_HAL) #include "cy_smif.h" #include "cycfg_qspi_memslot.h" +#include "cy_usbfs_dev_drv.h" #if defined(__cplusplus) extern "C" { @@ -39,9 +42,6 @@ extern "C" { #define CYBSP_I2C_ENABLED 1U #define CYBSP_I2C_HW SCB3 #define CYBSP_I2C_IRQ scb_3_interrupt_IRQn -#define CYBSP_DEBUG_UART_ENABLED 1U -#define CYBSP_DEBUG_UART_HW SCB5 -#define CYBSP_DEBUG_UART_IRQ scb_5_interrupt_IRQn #define CYBSP_QSPI_ENABLED 1U #define CYBSP_QSPI_HW SMIF0 #define CYBSP_QSPI_IRQ smif_interrupt_IRQn @@ -60,10 +60,27 @@ extern "C" { #define CYBSP_QSPI_SS2 (0UL) #define CYBSP_QSPI_SS3 (0UL) #define CYBSP_QSPI_DESELECT_DELAY 7 +#define CYBSP_USBUART_ENABLED 1U +#define CYBSP_USBUART_ACTIVE_ENDPOINTS_MASK 0U +#define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 512U +#define CYBSP_USBUART_ENDPOINTS_ACCESS_TYPE 0U +#define CYBSP_USBUART_HW USBFS0 +#define CYBSP_USBUART_HI_IRQ usb_interrupt_hi_IRQn +#define CYBSP_USBUART_MED_IRQ usb_interrupt_med_IRQn +#define CYBSP_USBUART_LO_IRQ usb_interrupt_lo_IRQn extern const cy_stc_scb_ezi2c_config_t CYBSP_I2C_config; -extern const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_I2C_obj; +#endif //defined (CY_USING_HAL) extern const cy_stc_smif_config_t CYBSP_QSPI_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_QSPI_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_USBUART_obj; +#endif //defined (CY_USING_HAL) void init_cycfg_peripherals(void); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c index 18d8b8518ec..9a0642174bc 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c @@ -40,6 +40,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = .vrefSel = 0UL, .vohSel = 0UL, }; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_WCO_IN_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_WCO_IN_PORT_NUM, + .channel_num = CYBSP_WCO_IN_PIN, + }; +#endif //defined (CY_USING_HAL) const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = { .outVal = 1, @@ -56,22 +64,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = .vrefSel = 0UL, .vohSel = 0UL, }; -const cy_stc_gpio_pin_config_t CYBSP_SW2_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_PULLUP, - .hsiom = CYBSP_SW2_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_WCO_OUT_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_WCO_OUT_PORT_NUM, + .channel_num = CYBSP_WCO_OUT_PIN, + }; +#endif //defined (CY_USING_HAL) const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config = { .outVal = 1, @@ -88,6 +88,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config = .vrefSel = 0UL, .vohSel = 0UL, }; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_QSPI_SS_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_QSPI_SS_PORT_NUM, + .channel_num = CYBSP_QSPI_SS_PIN, + }; +#endif //defined (CY_USING_HAL) const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config = { .outVal = 1, @@ -104,6 +112,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config = .vrefSel = 0UL, .vohSel = 0UL, }; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_QSPI_D3_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_QSPI_D3_PORT_NUM, + .channel_num = CYBSP_QSPI_D3_PIN, + }; +#endif //defined (CY_USING_HAL) const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config = { .outVal = 1, @@ -120,6 +136,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config = .vrefSel = 0UL, .vohSel = 0UL, }; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_QSPI_D2_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_QSPI_D2_PORT_NUM, + .channel_num = CYBSP_QSPI_D2_PIN, + }; +#endif //defined (CY_USING_HAL) const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config = { .outVal = 1, @@ -136,6 +160,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config = .vrefSel = 0UL, .vohSel = 0UL, }; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_QSPI_D1_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_QSPI_D1_PORT_NUM, + .channel_num = CYBSP_QSPI_D1_PIN, + }; +#endif //defined (CY_USING_HAL) const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config = { .outVal = 1, @@ -152,6 +184,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config = .vrefSel = 0UL, .vohSel = 0UL, }; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_QSPI_D0_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_QSPI_D0_PORT_NUM, + .channel_num = CYBSP_QSPI_D0_PIN, + }; +#endif //defined (CY_USING_HAL) const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config = { .outVal = 1, @@ -168,6 +208,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config = .vrefSel = 0UL, .vohSel = 0UL, }; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_QSPI_SCK_PORT_NUM, + .channel_num = CYBSP_QSPI_SCK_PIN, + }; +#endif //defined (CY_USING_HAL) const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config = { .outVal = 1, @@ -184,6 +232,14 @@ const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config = .vrefSel = 0UL, .vohSel = 0UL, }; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_ECO_IN_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_ECO_IN_PORT_NUM, + .channel_num = CYBSP_ECO_IN_PIN, + }; +#endif //defined (CY_USING_HAL) const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config = { .outVal = 1, @@ -200,22 +256,14 @@ const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config = .vrefSel = 0UL, .vohSel = 0UL, }; -const cy_stc_gpio_pin_config_t CYBSP_LED3_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_LED3_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_ECO_OUT_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_ECO_OUT_PORT_NUM, + .channel_num = CYBSP_ECO_OUT_PIN, + }; +#endif //defined (CY_USING_HAL) const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config = { .outVal = 1, @@ -232,6 +280,14 @@ const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config = .vrefSel = 0UL, .vohSel = 0UL, }; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_USB_DP_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_USB_DP_PORT_NUM, + .channel_num = CYBSP_USB_DP_PIN, + }; +#endif //defined (CY_USING_HAL) const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config = { .outVal = 1, @@ -248,54 +304,14 @@ const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config = .vrefSel = 0UL, .vohSel = 0UL, }; -const cy_stc_gpio_pin_config_t CYBSP_LED4_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = CYBSP_LED4_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -const cy_stc_gpio_pin_config_t ioss_0_port_5_pin_0_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_HIGHZ, - .hsiom = ioss_0_port_5_pin_0_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; -const cy_stc_gpio_pin_config_t ioss_0_port_5_pin_1_config = -{ - .outVal = 1, - .driveMode = CY_GPIO_DM_STRONG_IN_OFF, - .hsiom = ioss_0_port_5_pin_1_HSIOM, - .intEdge = CY_GPIO_INTR_DISABLE, - .intMask = 0UL, - .vtrip = CY_GPIO_VTRIP_CMOS, - .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_1_2, - .vregEn = 0UL, - .ibufMode = 0UL, - .vtripSel = 0UL, - .vrefSel = 0UL, - .vohSel = 0UL, -}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_USB_DM_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_USB_DM_PORT_NUM, + .channel_num = CYBSP_USB_DM_PIN, + }; +#endif //defined (CY_USING_HAL) const cy_stc_gpio_pin_config_t CYBSP_I2C_SCL_config = { .outVal = 1, @@ -312,6 +328,14 @@ const cy_stc_gpio_pin_config_t CYBSP_I2C_SCL_config = .vrefSel = 0UL, .vohSel = 0UL, }; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_I2C_SCL_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_I2C_SCL_PORT_NUM, + .channel_num = CYBSP_I2C_SCL_PIN, + }; +#endif //defined (CY_USING_HAL) const cy_stc_gpio_pin_config_t CYBSP_I2C_SDA_config = { .outVal = 1, @@ -328,6 +352,14 @@ const cy_stc_gpio_pin_config_t CYBSP_I2C_SDA_config = .vrefSel = 0UL, .vohSel = 0UL, }; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_I2C_SDA_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_I2C_SDA_PORT_NUM, + .channel_num = CYBSP_I2C_SDA_PIN, + }; +#endif //defined (CY_USING_HAL) const cy_stc_gpio_pin_config_t CYBSP_SWO_config = { .outVal = 1, @@ -337,13 +369,21 @@ const cy_stc_gpio_pin_config_t CYBSP_SWO_config = .intMask = 0UL, .vtrip = CY_GPIO_VTRIP_CMOS, .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_FULL, + .driveSel = CY_GPIO_DRIVE_1_2, .vregEn = 0UL, .ibufMode = 0UL, .vtripSel = 0UL, .vrefSel = 0UL, .vohSel = 0UL, }; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_SWO_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_SWO_PORT_NUM, + .channel_num = CYBSP_SWO_PIN, + }; +#endif //defined (CY_USING_HAL) const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = { .outVal = 1, @@ -353,13 +393,21 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = .intMask = 0UL, .vtrip = CY_GPIO_VTRIP_CMOS, .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_FULL, + .driveSel = CY_GPIO_DRIVE_1_2, .vregEn = 0UL, .ibufMode = 0UL, .vtripSel = 0UL, .vrefSel = 0UL, .vohSel = 0UL, }; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_SWDIO_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_SWDIO_PORT_NUM, + .channel_num = CYBSP_SWDIO_PIN, + }; +#endif //defined (CY_USING_HAL) const cy_stc_gpio_pin_config_t CYBSP_SWCLK_config = { .outVal = 1, @@ -369,58 +417,107 @@ const cy_stc_gpio_pin_config_t CYBSP_SWCLK_config = .intMask = 0UL, .vtrip = CY_GPIO_VTRIP_CMOS, .slewRate = CY_GPIO_SLEW_FAST, - .driveSel = CY_GPIO_DRIVE_FULL, + .driveSel = CY_GPIO_DRIVE_1_2, .vregEn = 0UL, .ibufMode = 0UL, .vtripSel = 0UL, .vrefSel = 0UL, .vohSel = 0UL, }; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_SWCLK_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_SWCLK_PORT_NUM, + .channel_num = CYBSP_SWCLK_PIN, + }; +#endif //defined (CY_USING_HAL) void init_cycfg_pins(void) { Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj); +#endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config); - - Cy_GPIO_Pin_Init(CYBSP_SW2_PORT, CYBSP_SW2_PIN, &CYBSP_SW2_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj); +#endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_QSPI_SS_PORT, CYBSP_QSPI_SS_PIN, &CYBSP_QSPI_SS_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_QSPI_SS_obj); +#endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_QSPI_D3_PORT, CYBSP_QSPI_D3_PIN, &CYBSP_QSPI_D3_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_QSPI_D3_obj); +#endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_QSPI_D2_PORT, CYBSP_QSPI_D2_PIN, &CYBSP_QSPI_D2_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_QSPI_D2_obj); +#endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_QSPI_D1_PORT, CYBSP_QSPI_D1_PIN, &CYBSP_QSPI_D1_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_QSPI_D1_obj); +#endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_QSPI_D0_PORT, CYBSP_QSPI_D0_PIN, &CYBSP_QSPI_D0_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_QSPI_D0_obj); +#endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_QSPI_SCK_PORT, CYBSP_QSPI_SCK_PIN, &CYBSP_QSPI_SCK_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_QSPI_SCK_obj); +#endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_ECO_IN_PORT, CYBSP_ECO_IN_PIN, &CYBSP_ECO_IN_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_ECO_IN_obj); +#endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_ECO_OUT_PORT, CYBSP_ECO_OUT_PIN, &CYBSP_ECO_OUT_config); - - Cy_GPIO_Pin_Init(CYBSP_LED3_PORT, CYBSP_LED3_PIN, &CYBSP_LED3_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_ECO_OUT_obj); +#endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_USB_DP_PORT, CYBSP_USB_DP_PIN, &CYBSP_USB_DP_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_USB_DP_obj); +#endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_USB_DM_PORT, CYBSP_USB_DM_PIN, &CYBSP_USB_DM_config); - - Cy_GPIO_Pin_Init(CYBSP_LED4_PORT, CYBSP_LED4_PIN, &CYBSP_LED4_config); - - Cy_GPIO_Pin_Init(ioss_0_port_5_pin_0_PORT, ioss_0_port_5_pin_0_PIN, &ioss_0_port_5_pin_0_config); - - Cy_GPIO_Pin_Init(ioss_0_port_5_pin_1_PORT, ioss_0_port_5_pin_1_PIN, &ioss_0_port_5_pin_1_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_USB_DM_obj); +#endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_I2C_SCL_PORT, CYBSP_I2C_SCL_PIN, &CYBSP_I2C_SCL_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_I2C_SCL_obj); +#endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_I2C_SDA_PORT, CYBSP_I2C_SDA_PIN, &CYBSP_I2C_SDA_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_I2C_SDA_obj); +#endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_SWO_obj); +#endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj); +#endif //defined (CY_USING_HAL) Cy_GPIO_Pin_Init(CYBSP_SWCLK_PORT, CYBSP_SWCLK_PIN, &CYBSP_SWCLK_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_SWCLK_obj); +#endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h index d6937cc557f..3dff95f9a70 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h @@ -27,6 +27,9 @@ #include "cycfg_notices.h" #include "cy_gpio.h" +#if defined (CY_USING_HAL) + #include "cyhal_hwmgr.h" +#endif //defined (CY_USING_HAL) #include "cycfg_routing.h" #if defined(__cplusplus) @@ -45,6 +48,18 @@ extern "C" { #endif #define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM #define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_WCO_IN_HAL_PORT_PIN P0_0 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG +#endif //defined (CY_USING_HAL) #define CYBSP_WCO_OUT_ENABLED 1U #define CYBSP_WCO_OUT_PORT GPIO_PRT0 #define CYBSP_WCO_OUT_PORT_NUM 0U @@ -57,18 +72,18 @@ extern "C" { #endif #define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM #define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn -#define CYBSP_SW2_ENABLED 1U -#define CYBSP_SW2_PORT GPIO_PRT0 -#define CYBSP_SW2_PORT_NUM 0U -#define CYBSP_SW2_PIN 4U -#define CYBSP_SW2_NUM 4U -#define CYBSP_SW2_DRIVEMODE CY_GPIO_DM_PULLUP -#define CYBSP_SW2_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_0_pin_4_HSIOM - #define ioss_0_port_0_pin_4_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_SW2_HSIOM ioss_0_port_0_pin_4_HSIOM -#define CYBSP_SW2_IRQ ioss_interrupts_gpio_0_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_WCO_OUT_HAL_PORT_PIN P0_1 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG +#endif //defined (CY_USING_HAL) #define CYBSP_QSPI_SS_ENABLED 1U #define CYBSP_QSPI_SS_PORT GPIO_PRT11 #define CYBSP_QSPI_SS_PORT_NUM 11U @@ -81,6 +96,18 @@ extern "C" { #endif #define CYBSP_QSPI_SS_HSIOM ioss_0_port_11_pin_2_HSIOM #define CYBSP_QSPI_SS_IRQ ioss_interrupts_gpio_11_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_SS_HAL_PORT_PIN P11_2 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_SS_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_SS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_SS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG +#endif //defined (CY_USING_HAL) #define CYBSP_QSPI_D3_ENABLED 1U #define CYBSP_QSPI_D3_PORT GPIO_PRT11 #define CYBSP_QSPI_D3_PORT_NUM 11U @@ -93,6 +120,18 @@ extern "C" { #endif #define CYBSP_QSPI_D3_HSIOM ioss_0_port_11_pin_3_HSIOM #define CYBSP_QSPI_D3_IRQ ioss_interrupts_gpio_11_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D3_HAL_PORT_PIN P11_3 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D3_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D3_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG +#endif //defined (CY_USING_HAL) #define CYBSP_QSPI_D2_ENABLED 1U #define CYBSP_QSPI_D2_PORT GPIO_PRT11 #define CYBSP_QSPI_D2_PORT_NUM 11U @@ -105,6 +144,18 @@ extern "C" { #endif #define CYBSP_QSPI_D2_HSIOM ioss_0_port_11_pin_4_HSIOM #define CYBSP_QSPI_D2_IRQ ioss_interrupts_gpio_11_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D2_HAL_PORT_PIN P11_4 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D2_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D2_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG +#endif //defined (CY_USING_HAL) #define CYBSP_QSPI_D1_ENABLED 1U #define CYBSP_QSPI_D1_PORT GPIO_PRT11 #define CYBSP_QSPI_D1_PORT_NUM 11U @@ -117,6 +168,18 @@ extern "C" { #endif #define CYBSP_QSPI_D1_HSIOM ioss_0_port_11_pin_5_HSIOM #define CYBSP_QSPI_D1_IRQ ioss_interrupts_gpio_11_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D1_HAL_PORT_PIN P11_5 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D1_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D1_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG +#endif //defined (CY_USING_HAL) #define CYBSP_QSPI_D0_ENABLED 1U #define CYBSP_QSPI_D0_PORT GPIO_PRT11 #define CYBSP_QSPI_D0_PORT_NUM 11U @@ -129,6 +192,18 @@ extern "C" { #endif #define CYBSP_QSPI_D0_HSIOM ioss_0_port_11_pin_6_HSIOM #define CYBSP_QSPI_D0_IRQ ioss_interrupts_gpio_11_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D0_HAL_PORT_PIN P11_6 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D0_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D0_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_D0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG +#endif //defined (CY_USING_HAL) #define CYBSP_QSPI_SCK_ENABLED 1U #define CYBSP_QSPI_SCK_PORT GPIO_PRT11 #define CYBSP_QSPI_SCK_PORT_NUM 11U @@ -141,6 +216,18 @@ extern "C" { #endif #define CYBSP_QSPI_SCK_HSIOM ioss_0_port_11_pin_7_HSIOM #define CYBSP_QSPI_SCK_IRQ ioss_interrupts_gpio_11_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_SCK_HAL_PORT_PIN P11_7 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_SCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_SCK_HAL_DIR CYHAL_GPIO_DIR_OUTPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_QSPI_SCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG +#endif //defined (CY_USING_HAL) #define CYBSP_ECO_IN_ENABLED 1U #define CYBSP_ECO_IN_PORT GPIO_PRT12 #define CYBSP_ECO_IN_PORT_NUM 12U @@ -153,6 +240,18 @@ extern "C" { #endif #define CYBSP_ECO_IN_HSIOM ioss_0_port_12_pin_6_HSIOM #define CYBSP_ECO_IN_IRQ ioss_interrupts_gpio_12_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_ECO_IN_HAL_PORT_PIN P12_6 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_ECO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_ECO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_ECO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG +#endif //defined (CY_USING_HAL) #define CYBSP_ECO_OUT_ENABLED 1U #define CYBSP_ECO_OUT_PORT GPIO_PRT12 #define CYBSP_ECO_OUT_PORT_NUM 12U @@ -165,18 +264,18 @@ extern "C" { #endif #define CYBSP_ECO_OUT_HSIOM ioss_0_port_12_pin_7_HSIOM #define CYBSP_ECO_OUT_IRQ ioss_interrupts_gpio_12_IRQn -#define CYBSP_LED3_ENABLED 1U -#define CYBSP_LED3_PORT GPIO_PRT13 -#define CYBSP_LED3_PORT_NUM 13U -#define CYBSP_LED3_PIN 7U -#define CYBSP_LED3_NUM 7U -#define CYBSP_LED3_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_LED3_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_13_pin_7_HSIOM - #define ioss_0_port_13_pin_7_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_LED3_HSIOM ioss_0_port_13_pin_7_HSIOM -#define CYBSP_LED3_IRQ ioss_interrupts_gpio_13_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_ECO_OUT_HAL_PORT_PIN P12_7 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_ECO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_ECO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_ECO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG +#endif //defined (CY_USING_HAL) #define CYBSP_USB_DP_ENABLED 1U #define CYBSP_USB_DP_PORT GPIO_PRT14 #define CYBSP_USB_DP_PORT_NUM 14U @@ -189,6 +288,18 @@ extern "C" { #endif #define CYBSP_USB_DP_HSIOM ioss_0_port_14_pin_0_HSIOM #define CYBSP_USB_DP_IRQ ioss_interrupts_gpio_14_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_USB_DP_HAL_PORT_PIN P14_0 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_USB_DP_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_USB_DP_HAL_DIR CYHAL_GPIO_DIR_INPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_USB_DP_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG +#endif //defined (CY_USING_HAL) #define CYBSP_USB_DM_ENABLED 1U #define CYBSP_USB_DM_PORT GPIO_PRT14 #define CYBSP_USB_DM_PORT_NUM 14U @@ -201,40 +312,18 @@ extern "C" { #endif #define CYBSP_USB_DM_HSIOM ioss_0_port_14_pin_1_HSIOM #define CYBSP_USB_DM_IRQ ioss_interrupts_gpio_14_IRQn -#define CYBSP_LED4_ENABLED 1U -#define CYBSP_LED4_PORT GPIO_PRT1 -#define CYBSP_LED4_PORT_NUM 1U -#define CYBSP_LED4_PIN 5U -#define CYBSP_LED4_NUM 5U -#define CYBSP_LED4_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define CYBSP_LED4_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_1_pin_5_HSIOM - #define ioss_0_port_1_pin_5_HSIOM HSIOM_SEL_GPIO -#endif -#define CYBSP_LED4_HSIOM ioss_0_port_1_pin_5_HSIOM -#define CYBSP_LED4_IRQ ioss_interrupts_gpio_1_IRQn -#define ioss_0_port_5_pin_0_ENABLED 1U -#define ioss_0_port_5_pin_0_PORT GPIO_PRT5 -#define ioss_0_port_5_pin_0_PORT_NUM 5U -#define ioss_0_port_5_pin_0_PIN 0U -#define ioss_0_port_5_pin_0_NUM 0U -#define ioss_0_port_5_pin_0_DRIVEMODE CY_GPIO_DM_HIGHZ -#define ioss_0_port_5_pin_0_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_5_pin_0_HSIOM - #define ioss_0_port_5_pin_0_HSIOM HSIOM_SEL_GPIO -#endif -#define ioss_0_port_5_pin_0_IRQ ioss_interrupts_gpio_5_IRQn -#define ioss_0_port_5_pin_1_ENABLED 1U -#define ioss_0_port_5_pin_1_PORT GPIO_PRT5 -#define ioss_0_port_5_pin_1_PORT_NUM 5U -#define ioss_0_port_5_pin_1_PIN 1U -#define ioss_0_port_5_pin_1_NUM 1U -#define ioss_0_port_5_pin_1_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF -#define ioss_0_port_5_pin_1_INIT_DRIVESTATE 1 -#ifndef ioss_0_port_5_pin_1_HSIOM - #define ioss_0_port_5_pin_1_HSIOM HSIOM_SEL_GPIO -#endif -#define ioss_0_port_5_pin_1_IRQ ioss_interrupts_gpio_5_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_USB_DM_HAL_PORT_PIN P14_1 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_USB_DM_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_USB_DM_HAL_DIR CYHAL_GPIO_DIR_INPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_USB_DM_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG +#endif //defined (CY_USING_HAL) #define CYBSP_I2C_SCL_ENABLED 1U #define CYBSP_I2C_SCL_PORT GPIO_PRT6 #define CYBSP_I2C_SCL_PORT_NUM 6U @@ -247,6 +336,18 @@ extern "C" { #endif #define CYBSP_I2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM #define CYBSP_I2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_I2C_SCL_HAL_PORT_PIN P6_0 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_I2C_SCL_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_I2C_SCL_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_I2C_SCL_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW +#endif //defined (CY_USING_HAL) #define CYBSP_I2C_SDA_ENABLED 1U #define CYBSP_I2C_SDA_PORT GPIO_PRT6 #define CYBSP_I2C_SDA_PORT_NUM 6U @@ -259,8 +360,21 @@ extern "C" { #endif #define CYBSP_I2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM #define CYBSP_I2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_I2C_SDA_HAL_PORT_PIN P6_1 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_I2C_SDA_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_I2C_SDA_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_I2C_SDA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW +#endif //defined (CY_USING_HAL) #define CYBSP_SWO_ENABLED 1U #define CYBSP_SWO_PORT GPIO_PRT6 +#define CYBSP_SWO_PORT_NUM 6U #define CYBSP_SWO_PIN 4U #define CYBSP_SWO_NUM 4U #define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF @@ -270,8 +384,21 @@ extern "C" { #endif #define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM #define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_SWO_HAL_PORT_PIN P6_4 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG +#endif //defined (CY_USING_HAL) #define CYBSP_SWDIO_ENABLED 1U #define CYBSP_SWDIO_PORT GPIO_PRT6 +#define CYBSP_SWDIO_PORT_NUM 6U #define CYBSP_SWDIO_PIN 6U #define CYBSP_SWDIO_NUM 6U #define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP @@ -281,8 +408,21 @@ extern "C" { #endif #define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM #define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_SWDIO_HAL_PORT_PIN P6_6 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP +#endif //defined (CY_USING_HAL) #define CYBSP_SWCLK_ENABLED 1U #define CYBSP_SWCLK_PORT GPIO_PRT6 +#define CYBSP_SWCLK_PORT_NUM 6U #define CYBSP_SWCLK_PIN 7U #define CYBSP_SWCLK_NUM 7U #define CYBSP_SWCLK_DRIVEMODE CY_GPIO_DM_PULLDOWN @@ -292,29 +432,87 @@ extern "C" { #endif #define CYBSP_SWCLK_HSIOM ioss_0_port_6_pin_7_HSIOM #define CYBSP_SWCLK_IRQ ioss_interrupts_gpio_6_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_SWCLK_HAL_PORT_PIN P6_7 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWCLK_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWCLK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWCLK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN +#endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_WCO_IN_obj; +#endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config; -extern const cy_stc_gpio_pin_config_t CYBSP_SW2_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj; +#endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_QSPI_SS_obj; +#endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_QSPI_D3_obj; +#endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_QSPI_D2_obj; +#endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_QSPI_D1_obj; +#endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_QSPI_D0_obj; +#endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj; +#endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_ECO_IN_obj; +#endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config; -extern const cy_stc_gpio_pin_config_t CYBSP_LED3_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_ECO_OUT_obj; +#endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_USB_DP_obj; +#endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config; -extern const cy_stc_gpio_pin_config_t CYBSP_LED4_config; -extern const cy_stc_gpio_pin_config_t ioss_0_port_5_pin_0_config; -extern const cy_stc_gpio_pin_config_t ioss_0_port_5_pin_1_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_USB_DM_obj; +#endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_I2C_SCL_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_I2C_SCL_obj; +#endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_I2C_SDA_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_I2C_SDA_obj; +#endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_SWO_obj; +#endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_SWDIO_obj; +#endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_SWCLK_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_SWCLK_obj; +#endif //defined (CY_USING_HAL) void init_cycfg_pins(void); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h index eff29bf6931..4a642230557 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h @@ -40,8 +40,6 @@ void init_cycfg_routing(void); #define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1 #define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0 #define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK -#define ioss_0_port_5_pin_0_HSIOM P5_0_SCB5_UART_RX -#define ioss_0_port_5_pin_1_HSIOM P5_1_SCB5_UART_TX #define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL #define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA #define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c index b6c01928d46..663193f6abd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c @@ -71,13 +71,53 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = .refDiv = 20U, .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4, .enableOutputDiv = true, - .lockTolerance = 10U, + .lockTolerance = 4U, .igain = 9U, .pgain = 5U, .settlingCount = 8U, .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT, .cco_Freq = 355U, }; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = + { + .type = CYHAL_RSC_CLKPATH, + .block_num = 0U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = + { + .type = CYHAL_RSC_CLKPATH, + .block_num = 1U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = + { + .type = CYHAL_RSC_CLKPATH, + .block_num = 2U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj = + { + .type = CYHAL_RSC_CLKPATH, + .block_num = 3U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj = + { + .type = CYHAL_RSC_CLKPATH, + .block_num = 4U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = { .feedbackDiv = 30, @@ -501,4 +541,24 @@ void init_cycfg_system(void) /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */ SystemCoreClockUpdate(); + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj); +#endif //defined (CY_USING_HAL) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h index 4bdd873358f..f3da5da0731 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h @@ -27,6 +27,9 @@ #include "cycfg_notices.h" #include "cy_sysclk.h" +#if defined (CY_USING_HAL) + #include "cyhal_hwmgr.h" +#endif //defined (CY_USING_HAL) #include "cy_gpio.h" #include "cy_syspm.h" @@ -75,6 +78,22 @@ extern "C" { #define CY_CFG_PWR_VDDIO0_MV 3300 #define CY_CFG_PWR_VDDIO1_MV 3300 +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj; +#endif //defined (CY_USING_HAL) + void init_cycfg_system(void); #if defined(__cplusplus) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list index 982f685fc41..866126ae961 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list @@ -1,18 +1,4 @@ -[Device="CYB06447BZI-D54"] +[Device=CYB06447BZI-D54] [Blocks] -# User IO -# CYBSP_USER_LED1 -ioss[0].port[13].pin[7] -# CYBSP_USER_LED2 -ioss[0].port[1].pin[5] -# CYBSP_USER_BTN1 -ioss[0].port[0].pin[4] - -# Debug -# CYBSP_DEBUG_UART -scb[5] -# CYBSP_DEBUG_UART_RX -ioss[0].port[5].pin[0] -# CYBSP_DEBUG_UART_TX -ioss[0].port[5].pin[1] +# Nothing needs to be reserved for this board diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi new file mode 100644 index 00000000000..a4c24aff9c4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi @@ -0,0 +1,63 @@ + + + + PSoC 6.xml + + + 0 + S25FL128S + true + None + 0x18000000 + 0x1000000 + 0x18FFFFFF + true + false + QUAD_SPI_DATA_0_3 + S25FL128S + true + + + 1 + Not used + false + None + 0x18010000 + 0x10000 + 0x1801FFFF + false + false + SPI_MOSI_MISO_DATA_0_1 + default_memory.xml + false + + + 2 + Not used + false + None + 0x18020000 + 0x10000 + 0x1802FFFF + false + false + SPI_MOSI_MISO_DATA_0_1 + default_memory.xml + false + + + 3 + Not used + false + None + 0x18030000 + 0x10000 + 0x1803FFFF + false + false + SPI_MOSI_MISO_DATA_0_1 + default_memory.xml + false + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/design.modus index ad8992850d9..460fe57995e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/design.modus +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/design.modus @@ -28,16 +28,6 @@ - - - - - - - - - - @@ -118,16 +108,6 @@ - - - - - - - - - - @@ -148,36 +128,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -228,16 +178,11 @@ - + - - - - - @@ -252,51 +197,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -334,7 +234,7 @@ - + @@ -375,7 +275,6 @@ - @@ -390,6 +289,27 @@ + + + + + + + + + + + + + + + + + + + + + @@ -412,14 +332,6 @@ - - - - - - - - @@ -453,8 +365,16 @@ - - + + + + + + + + + + @@ -468,11 +388,13 @@ + + + + - - - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c index cda6d4025b1..cb430a41643 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c @@ -28,7 +28,6 @@ void init_cycfg_all(void) { init_cycfg_system(); init_cycfg_clocks(); - init_cycfg_dmas(); init_cycfg_routing(); init_cycfg_peripherals(); init_cycfg_pins(); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h index 3585cf91ba1..9abc7f0f4ab 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h @@ -32,7 +32,6 @@ extern "C" { #include "cycfg_notices.h" #include "cycfg_system.h" #include "cycfg_clocks.h" -#include "cycfg_dmas.h" #include "cycfg_routing.h" #include "cycfg_peripherals.h" #include "cycfg_pins.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c index 54d1df91cbd..6a19f39283b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c @@ -25,19 +25,11 @@ #include "cycfg_clocks.h" #if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_USB_UART_CLK_DIV_obj = + const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj = { .type = CYHAL_RSC_CLOCK, - .block_num = CYBSP_USB_UART_CLK_DIV_HW, - .channel_num = CYBSP_USB_UART_CLK_DIV_NUM, - }; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t CYBSP_SDIO_CLK_DIV_obj = - { - .type = CYHAL_RSC_CLOCK, - .block_num = CYBSP_SDIO_CLK_DIV_HW, - .channel_num = CYBSP_SDIO_CLK_DIV_NUM, + .block_num = CYBSP_USB_CLK_DIV_HW, + .channel_num = CYBSP_USB_CLK_DIV_NUM, }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) @@ -49,11 +41,11 @@ }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - const cyhal_resource_inst_t peri_0_div_8_3_obj = + const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj = { .type = CYHAL_RSC_CLOCK, - .block_num = peri_0_div_8_3_HW, - .channel_num = peri_0_div_8_3_NUM, + .block_num = CYBSP_BT_UART_CLK_DIV_HW, + .channel_num = CYBSP_BT_UART_CLK_DIV_NUM, }; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) @@ -88,14 +80,7 @@ void init_cycfg_clocks(void) Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 999U); Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_USB_UART_CLK_DIV_obj); -#endif //defined (CY_USING_HAL) - - Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U); - Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U); - Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U); -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&CYBSP_SDIO_CLK_DIV_obj); + cyhal_hwmgr_reserve(&CYBSP_USB_CLK_DIV_obj); #endif //defined (CY_USING_HAL) Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U); @@ -109,7 +94,7 @@ void init_cycfg_clocks(void) Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 108U); Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U); #if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&peri_0_div_8_3_obj); + cyhal_hwmgr_reserve(&CYBSP_BT_UART_CLK_DIV_obj); #endif //defined (CY_USING_HAL) Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 4U); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h index c1e5915eb07..3c26bd3bb74 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h @@ -35,18 +35,15 @@ extern "C" { #endif -#define CYBSP_USB_UART_CLK_DIV_ENABLED 1U -#define CYBSP_USB_UART_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT -#define CYBSP_USB_UART_CLK_DIV_NUM 0U -#define CYBSP_SDIO_CLK_DIV_ENABLED 1U -#define CYBSP_SDIO_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT -#define CYBSP_SDIO_CLK_DIV_NUM 0U +#define CYBSP_USB_CLK_DIV_ENABLED 1U +#define CYBSP_USB_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT +#define CYBSP_USB_CLK_DIV_NUM 0U #define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U #define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT #define CYBSP_CSD_COMM_CLK_DIV_NUM 1U -#define peri_0_div_8_3_ENABLED 1U -#define peri_0_div_8_3_HW CY_SYSCLK_DIV_8_BIT -#define peri_0_div_8_3_NUM 3U +#define CYBSP_BT_UART_CLK_DIV_ENABLED 1U +#define CYBSP_BT_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT +#define CYBSP_BT_UART_CLK_DIV_NUM 3U #define CYBSP_CSD_CLK_DIV_ENABLED 1U #define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT #define CYBSP_CSD_CLK_DIV_NUM 4U @@ -58,16 +55,13 @@ extern "C" { #define CYBSP_WL_UART_CLK_DIV_NUM 6U #if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_USB_UART_CLK_DIV_obj; -#endif //defined (CY_USING_HAL) -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t CYBSP_SDIO_CLK_DIV_obj; + extern const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t peri_0_div_8_3_obj; + extern const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj; #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.c deleted file mode 100644 index 8d869195513..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.c +++ /dev/null @@ -1,230 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_dmas.c -* -* Description: -* DMA configuration -* This file was automatically generated and should not be modified. -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#include "cycfg_dmas.h" - -const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_0_Descriptor_0_config = -{ - .retrigger = CY_DMA_RETRIG_IM, - .interruptType = CY_DMA_1ELEMENT, - .triggerOutType = CY_DMA_1ELEMENT, - .channelState = CY_DMA_CHANNEL_DISABLED, - .triggerInType = CY_DMA_1ELEMENT, - .dataSize = CY_DMA_BYTE, - .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .descriptorType = CY_DMA_1D_TRANSFER, - .srcAddress = NULL, - .dstAddress = NULL, - .srcXincrement = 0, - .dstXincrement = 1, - .xCount = 6, - .srcYincrement = 0, - .dstYincrement = 0, - .yCount = 1, - .nextDescriptor = NULL, -}; -cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_0_Descriptor_0 = -{ - .ctl = 0UL, - .src = 0UL, - .dst = 0UL, - .xCtl = 0UL, - .yCtl = 0UL, - .nextPtr = 0UL, -}; -const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_0_channelConfig = -{ - .descriptor = &cpuss_0_dw0_0_chan_0_Descriptor_0, - .preemptable = true, - .priority = 1, - .enable = false, - .bufferable = false, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t cpuss_0_dw0_0_chan_0_obj = - { - .type = CYHAL_RSC_DMA, - .block_num = 0U, - .channel_num = cpuss_0_dw0_0_chan_0_CHANNEL, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_1_Descriptor_0_config = -{ - .retrigger = CY_DMA_RETRIG_16CYC, - .interruptType = CY_DMA_1ELEMENT, - .triggerOutType = CY_DMA_1ELEMENT, - .channelState = CY_DMA_CHANNEL_DISABLED, - .triggerInType = CY_DMA_1ELEMENT, - .dataSize = CY_DMA_BYTE, - .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .descriptorType = CY_DMA_1D_TRANSFER, - .srcAddress = NULL, - .dstAddress = NULL, - .srcXincrement = 1, - .dstXincrement = 0, - .xCount = 5, - .srcYincrement = 0, - .dstYincrement = 0, - .yCount = 1, - .nextDescriptor = NULL, -}; -cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_1_Descriptor_0 = -{ - .ctl = 0UL, - .src = 0UL, - .dst = 0UL, - .xCtl = 0UL, - .yCtl = 0UL, - .nextPtr = 0UL, -}; -const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_1_channelConfig = -{ - .descriptor = &cpuss_0_dw0_0_chan_1_Descriptor_0, - .preemptable = true, - .priority = 1, - .enable = false, - .bufferable = false, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t cpuss_0_dw0_0_chan_1_obj = - { - .type = CYHAL_RSC_DMA, - .block_num = 0U, - .channel_num = cpuss_0_dw0_0_chan_1_CHANNEL, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_1_Descriptor_0_config = -{ - .retrigger = CY_DMA_RETRIG_4CYC, - .interruptType = CY_DMA_DESCR, - .triggerOutType = CY_DMA_1ELEMENT, - .channelState = CY_DMA_CHANNEL_DISABLED, - .triggerInType = CY_DMA_X_LOOP, - .dataSize = CY_DMA_HALFWORD, - .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .descriptorType = CY_DMA_2D_TRANSFER, - .srcAddress = NULL, - .dstAddress = NULL, - .srcXincrement = 2, - .dstXincrement = 0, - .xCount = 10, - .srcYincrement = 10, - .dstYincrement = 0, - .yCount = 2, - .nextDescriptor = NULL, -}; -cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_1_Descriptor_0 = -{ - .ctl = 0UL, - .src = 0UL, - .dst = 0UL, - .xCtl = 0UL, - .yCtl = 0UL, - .nextPtr = 0UL, -}; -const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_1_channelConfig = -{ - .descriptor = &cpuss_0_dw1_0_chan_1_Descriptor_0, - .preemptable = false, - .priority = 0, - .enable = false, - .bufferable = false, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t cpuss_0_dw1_0_chan_1_obj = - { - .type = CYHAL_RSC_DMA, - .block_num = 1U, - .channel_num = cpuss_0_dw1_0_chan_1_CHANNEL, - }; -#endif //defined (CY_USING_HAL) -const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_3_Descriptor_0_config = -{ - .retrigger = CY_DMA_RETRIG_IM, - .interruptType = CY_DMA_DESCR, - .triggerOutType = CY_DMA_1ELEMENT, - .channelState = CY_DMA_CHANNEL_DISABLED, - .triggerInType = CY_DMA_X_LOOP, - .dataSize = CY_DMA_HALFWORD, - .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, - .descriptorType = CY_DMA_2D_TRANSFER, - .srcAddress = NULL, - .dstAddress = NULL, - .srcXincrement = 0, - .dstXincrement = 2, - .xCount = 10, - .srcYincrement = 0, - .dstYincrement = 10, - .yCount = 2, - .nextDescriptor = NULL, -}; -cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_3_Descriptor_0 = -{ - .ctl = 0UL, - .src = 0UL, - .dst = 0UL, - .xCtl = 0UL, - .yCtl = 0UL, - .nextPtr = 0UL, -}; -const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_3_channelConfig = -{ - .descriptor = &cpuss_0_dw1_0_chan_3_Descriptor_0, - .preemptable = false, - .priority = 0, - .enable = false, - .bufferable = false, -}; -#if defined (CY_USING_HAL) - const cyhal_resource_inst_t cpuss_0_dw1_0_chan_3_obj = - { - .type = CYHAL_RSC_DMA, - .block_num = 1U, - .channel_num = cpuss_0_dw1_0_chan_3_CHANNEL, - }; -#endif //defined (CY_USING_HAL) - - -void init_cycfg_dmas(void) -{ -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&cpuss_0_dw0_0_chan_0_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&cpuss_0_dw0_0_chan_1_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&cpuss_0_dw1_0_chan_1_obj); -#endif //defined (CY_USING_HAL) - -#if defined (CY_USING_HAL) - cyhal_hwmgr_reserve(&cpuss_0_dw1_0_chan_3_obj); -#endif //defined (CY_USING_HAL) -} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.h deleted file mode 100644 index d6c0d6587db..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.h +++ /dev/null @@ -1,87 +0,0 @@ -/******************************************************************************* -* File Name: cycfg_dmas.h -* -* Description: -* DMA configuration -* This file was automatically generated and should not be modified. -* -******************************************************************************** -* Copyright 2017-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -********************************************************************************/ - -#if !defined(CYCFG_DMAS_H) -#define CYCFG_DMAS_H - -#include "cycfg_notices.h" -#include "cy_dma.h" -#if defined (CY_USING_HAL) - #include "cyhal_hwmgr.h" -#endif //defined (CY_USING_HAL) - -#if defined(__cplusplus) -extern "C" { -#endif - -#define cpuss_0_dw0_0_chan_0_ENABLED 1U -#define cpuss_0_dw0_0_chan_0_HW DW0 -#define cpuss_0_dw0_0_chan_0_CHANNEL 0U -#define cpuss_0_dw0_0_chan_0_IRQ cpuss_interrupts_dw0_0_IRQn -#define cpuss_0_dw0_0_chan_1_ENABLED 1U -#define cpuss_0_dw0_0_chan_1_HW DW0 -#define cpuss_0_dw0_0_chan_1_CHANNEL 1U -#define cpuss_0_dw0_0_chan_1_IRQ cpuss_interrupts_dw0_1_IRQn -#define cpuss_0_dw1_0_chan_1_ENABLED 1U -#define cpuss_0_dw1_0_chan_1_HW DW1 -#define cpuss_0_dw1_0_chan_1_CHANNEL 1U -#define cpuss_0_dw1_0_chan_1_IRQ cpuss_interrupts_dw1_1_IRQn -#define cpuss_0_dw1_0_chan_3_ENABLED 1U -#define cpuss_0_dw1_0_chan_3_HW DW1 -#define cpuss_0_dw1_0_chan_3_CHANNEL 3U -#define cpuss_0_dw1_0_chan_3_IRQ cpuss_interrupts_dw1_3_IRQn - -extern const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_0_Descriptor_0_config; -extern cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_0_Descriptor_0; -extern const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_0_channelConfig; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t cpuss_0_dw0_0_chan_0_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_1_Descriptor_0_config; -extern cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_1_Descriptor_0; -extern const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_1_channelConfig; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t cpuss_0_dw0_0_chan_1_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_1_Descriptor_0_config; -extern cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_1_Descriptor_0; -extern const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_1_channelConfig; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t cpuss_0_dw1_0_chan_1_obj; -#endif //defined (CY_USING_HAL) -extern const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_3_Descriptor_0_config; -extern cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_3_Descriptor_0; -extern const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_3_channelConfig; -#if defined (CY_USING_HAL) - extern const cyhal_resource_inst_t cpuss_0_dw1_0_chan_3_obj; -#endif //defined (CY_USING_HAL) - -void init_cycfg_dmas(void); - -#if defined(__cplusplus) -} -#endif - - -#endif /* CYCFG_DMAS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h index d02d6fc9044..201696099e3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h @@ -123,9 +123,8 @@ extern "C" { #define CYBSP_RTC_YEAR_OFFSET (0U) #define CYBSP_USBUART_ENABLED 1U #define CYBSP_USBUART_ACTIVE_ENDPOINTS_MASK 7U -#define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 140U +#define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 512U #define CYBSP_USBUART_ENDPOINTS_ACCESS_TYPE 0U -#define CYBSP_USBUART_USB_CORE 4U #define CYBSP_USBUART_HW USBFS0 #define CYBSP_USBUART_HI_IRQ usb_interrupt_hi_IRQn #define CYBSP_USBUART_MED_IRQ usb_interrupt_med_IRQn diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c index c4e5bcf916f..14d433859db 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c @@ -24,7 +24,7 @@ #include "cycfg_qspi_memslot.h" -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0xECU, @@ -42,7 +42,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd = .dataWidth = CY_SMIF_WIDTH_QUAD }; -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x06U, @@ -60,7 +60,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x04U, @@ -78,7 +78,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0xDCU, @@ -96,7 +96,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x60U, @@ -114,7 +114,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x34U, @@ -132,7 +132,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd = .dataWidth = CY_SMIF_WIDTH_QUAD }; -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x35U, @@ -150,7 +150,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x05U, @@ -168,7 +168,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd = +const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd = { /* The 8-bit command. 1 x I/O read command. */ .command = 0x01U, @@ -186,34 +186,34 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd = .dataWidth = CY_SMIF_WIDTH_SINGLE }; -const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 = +const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0 = { /* Specifies the number of address bytes used by the memory slave device. */ .numOfAddrBytes = 0x04U, /* The size of the memory. */ .memSize = 0x04000000U, /* Specifies the Read command. */ - .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readCmd, + .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readCmd, /* Specifies the Write Enable command. */ - .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd, + .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd, /* Specifies the Write Disable command. */ - .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd, + .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd, /* Specifies the Erase command. */ - .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd, + .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd, /* Specifies the sector size of each erase. */ .eraseSize = 0x00040000U, /* Specifies the Chip Erase command. */ - .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd, + .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd, /* Specifies the Program command. */ - .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_programCmd, + .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_programCmd, /* Specifies the page size for programming. */ .programSize = 0x00000200U, /* Specifies the command to read the QE-containing status register. */ - .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd, + .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd, /* Specifies the command to read the WIP-containing status register. */ - .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd, + .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd, /* Specifies the command to write into the QE-containing status register. */ - .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd, + .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd, /* The mask for the status register. */ .stsRegBusyMask = 0x01U, /* The mask for the status register. */ @@ -226,7 +226,7 @@ const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 = .programTime = 1300U }; -const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 = +const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0 = { /* Determines the slot number where the memory device is placed. */ .slaveSelect = CY_SMIF_SLAVE_SELECT_0, @@ -244,11 +244,11 @@ const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 = Valid when the memory mapped mode is enabled. */ .dualQuadSlots = 0, /* The configuration of the device. */ - .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 + .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0 }; const cy_stc_smif_mem_config_t* const smifMemConfigs[] = { - &S25FL512SX4byteaddr_SlaveSlot_0 + &S25FL512S_4byteaddr_SlaveSlot_0 }; const cy_stc_smif_block_config_t smifBlockConfig = diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h index 32f9b49b2e6..0ee62b1d559 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h @@ -28,19 +28,19 @@ #define CY_SMIF_DEVICE_NUM 1 -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd; -extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd; - -extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0; - -extern const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd; + +extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0; + +extern const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0; extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM]; extern const cy_stc_smif_block_config_t smifBlockConfig; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list index a055be07d22..a8490a965d3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list @@ -1,27 +1,14 @@ -[Device="CY8C6247BZI-D54"] +[Device=CY8C6247BZI-D54] [Blocks] -# User IO -# CYBSP_USER_LED1 -ioss[0].port[0].pin[3] -# CYBSP_USER_LED2 -ioss[0].port[1].pin[1] -# CYBSP_USER_LED3 -ioss[0].port[10].pin[6] -# CYBSP_USER_BTN1 -ioss[0].port[0].pin[4] - -# Debug -# CYBSP_DEBUG_UART -scb[6] -# CYBSP_DEBUG_UART_RX -ioss[0].port[13].pin[0] -# CYBSP_DEBUG_UART_TX -ioss[0].port[13].pin[1] - # WIFI # CYBSP_WIFI_SDIO udb[0] +peri[0].div_8[0] +cpuss[0].dw0[0].chan[0] +cpuss[0].dw0[0].chan[1] +cpuss[0].dw1[0].chan[1] +cpuss[0].dw1[0].chan[3] # CYBSP_WIFI_SDIO_D0 ioss[0].port[2].pin[0] # CYBSP_WIFI_SDIO_D1 @@ -35,4 +22,21 @@ ioss[0].port[2].pin[4] # CYBSP_WIFI_SDIO_CLK ioss[0].port[2].pin[5] # CYBSP_WIFI_WL_REG_ON -ioss[0].port[2].pin[6] \ No newline at end of file +ioss[0].port[2].pin[6] + +[RoutingResources] +# CYBSP_WIFI_SDIO +cpuss[0].dw0_tr_in[0] +cpuss[0].dw0_tr_in[1] +cpuss[0].dw1_tr_in[1] +cpuss[0].dw1_tr_in[3] + +udb[0].tr_udb[0] +udb[0].tr_udb[1] +udb[0].tr_udb[3] +udb[0].tr_udb[7] + +tr_group[0].input[43] +tr_group[0].input[44] +tr_group[0].input[47] +tr_group[0].input[48] \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.modus index 6bc99333172..6ded06e1212 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.modus +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.modus @@ -8,114 +8,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -762,22 +654,17 @@ - + - - - - - - + @@ -1041,7 +928,6 @@ - @@ -1081,12 +967,10 @@ - - - + - + @@ -1246,6 +1130,14 @@ + + + + + + + + @@ -1303,8 +1195,6 @@ - - - + From 2eab0fbee400fdc4d5398ef769ff8f12b5b33349 Mon Sep 17 00:00:00 2001 From: Ari Parkkila Date: Wed, 25 Sep 2019 00:04:44 -0700 Subject: [PATCH 181/227] Cellular: Fix resolving of DNS server IPv4/6 address --- .../framework/common/util/utiltest.cpp | 52 ++++++++----------- UNITTESTS/stubs/CellularUtil_stub.cpp | 16 +++--- .../framework/AT/AT_CellularContext.cpp | 23 ++------ .../framework/common/CellularUtil.cpp | 11 +--- 4 files changed, 39 insertions(+), 63 deletions(-) diff --git a/UNITTESTS/features/cellular/framework/common/util/utiltest.cpp b/UNITTESTS/features/cellular/framework/common/util/utiltest.cpp index 1efe3e7b7e2..23ff20f8265 100644 --- a/UNITTESTS/features/cellular/framework/common/util/utiltest.cpp +++ b/UNITTESTS/features/cellular/framework/common/util/utiltest.cpp @@ -184,60 +184,54 @@ TEST_F(Testutil, separate_ip_addresses) char ip[64] = {0}; char subnet[64] = {0}; - strncpy(s, "32.1.20.187.1.112.139.245.251.136.232.110.123.51.230.138.0.1.2.3.4.5.6.7.8.9.10.11.12.13.14.15\0", 95); + // IP address representations formats are for IPv6 or IPv4 address, with and without mask, in dotted or colon (IPv6 only) notation + + // IPv6 with a mask in dotted notation + strncpy(s, "32.1.20.187.1.112.139.245.251.136.232.110.123.51.230.138.0.1.2.3.4.5.6.7.8.9.10.11.12.13.14.15\0", + sizeof("32.1.20.187.1.112.139.245.251.136.232.110.123.51.230.138.0.1.2.3.4.5.6.7.8.9.10.11.12.13.14.15\0")); separate_ip_addresses(NULL, ip, sizeof(ip), subnet, sizeof(subnet)); separate_ip_addresses(s, ip, sizeof(ip), subnet, sizeof(subnet)); EXPECT_STREQ("2001:14BB:170:8BF5:FB88:E86E:7B33:E68A", ip); EXPECT_STREQ("001:203:405:607:809:A0B:C0D:E0F", subnet); - strncpy(s, "32:1:20:187:1:112:139:245:251:136:232:110:123:51:230:138 0:1:2:3:4:5:6:7:8:9:10:11:12:13:14:15\0", 95); + // IPv6 with mask in colon notation + strncpy(s, "32:1:20:187:1:112:139:1245 0:1:2:3:4:5:6:7\0", sizeof("32:1:20:187:1:112:139:1245 0:1:2:3:4:5:6:7\0")); separate_ip_addresses(s, ip, sizeof(ip), subnet, sizeof(subnet)); - EXPECT_STREQ("32:1:20:187:1:112:139:245:251:136:232:110:123:51:230:138", ip); - EXPECT_STREQ("0:1:2:3:4:5:6:7:8:9:10:11:12:13:14:15", subnet); + EXPECT_STREQ("32:1:20:187:1:112:139:1245", ip); + EXPECT_STREQ("0:1:2:3:4:5:6:7", subnet); ip[0] = '\0'; subnet[0] = '\0'; - strncpy(s, "1.2.3.4\0", 8); + // IPv6 without mask in dotted notation + strncpy(s, "0.2.3.4.5.6.7.8.90.100.11.12.13.14.15.16\0", sizeof("0.2.3.4.5.6.7.8.90.100.11.12.13.14.15.16\0")); separate_ip_addresses(s, ip, sizeof(ip), subnet, sizeof(subnet)); - EXPECT_STREQ("1.2.3.4", ip); + EXPECT_STREQ("002:304:506:708:5A64:B0C:D0E:F10", ip); EXPECT_STREQ("", subnet); ip[0] = '\0'; subnet[0] = '\0'; - strncpy(s, "1.2.3.4.5.6.7.8\0", 16); - separate_ip_addresses(s, ip, sizeof(ip), subnet, sizeof(subnet)); - EXPECT_STREQ("1.2.3.4", ip); - EXPECT_STREQ("5.6.7.8", subnet); - - ip[0] = '\0'; - subnet[0] = '\0'; - strncpy(s, "1.2.3.4.5.6.7.8.9.10.11.12.13.14.15.16\0", 39); + // IPv6 without mask in colon notation + strncpy(s, "0032:1:20:187:0:112:139:245f\0", sizeof("0032:1:20:187:0:112:139:245f\0")); separate_ip_addresses(s, ip, sizeof(ip), subnet, sizeof(subnet)); - EXPECT_STREQ("102:304:506:708:90A:B0C:D0E:F10", ip); + EXPECT_STREQ("0032:1:20:187:0:112:139:245f", ip); EXPECT_STREQ("", subnet); ip[0] = '\0'; subnet[0] = '\0'; - strncpy(s, "32:1:20:187:1:112:139:245:251:136:232:110:123:51:230:138\0", 57); + // IPv4 with mask + strncpy(s, "100.0.3.40.255.6.7.80\0", sizeof("100.0.3.40.255.6.7.80\0")); separate_ip_addresses(s, ip, sizeof(ip), subnet, sizeof(subnet)); - EXPECT_STREQ("32:1:20:187:1:112:139:245:251:136:232:110:123:51:230:138", ip); - EXPECT_STREQ("", subnet); + EXPECT_STREQ("100.0.3.40", ip); + EXPECT_STREQ("255.6.7.80", subnet); ip[0] = '\0'; subnet[0] = '\0'; - strncpy(s, "1.2.3.4 32:1:20:187:1:112:139:245:251:136:232:110:123:51:230:138\0", 65); + // IPv4 without mask + strncpy(s, "1.255.3.0\0", sizeof("1.255.3.0\0")); separate_ip_addresses(s, ip, sizeof(ip), subnet, sizeof(subnet)); - EXPECT_STREQ("1.2.3.4", ip); - EXPECT_STREQ("32:1:20:187:1:112:139:245:251:136:232:110:123:51:230:138", subnet); - - ip[0] = '\0'; - subnet[0] = '\0'; - strncpy(s, "1.2.3.4 5.6.7.8.9.10.11.12.13.14.15.16.17.18.19.20\0", 51); - separate_ip_addresses(s, ip, sizeof(ip), subnet, sizeof(subnet)); - EXPECT_STREQ("1.2.3.4", ip); - EXPECT_STREQ("506:708:90A:B0C:D0E:F10:1112:1314", subnet); - EXPECT_STREQ("1.2.3.4 5.6.7.8.9.10.11.12.13.14.15.16.17.18.19.20", s); + EXPECT_STREQ("1.255.3.0", ip); + EXPECT_STREQ("", subnet); } TEST_F(Testutil, get_dynamic_ip_port) diff --git a/UNITTESTS/stubs/CellularUtil_stub.cpp b/UNITTESTS/stubs/CellularUtil_stub.cpp index 757fd2bbb8e..d54469a6590 100644 --- a/UNITTESTS/stubs/CellularUtil_stub.cpp +++ b/UNITTESTS/stubs/CellularUtil_stub.cpp @@ -69,9 +69,11 @@ void separate_ip4like_addresses(char *orig, char *ip, size_t ip_size, char *ip2, strlen(CellularUtil_stub::char_table[CellularUtil_stub::table_idx])); ip[strlen(CellularUtil_stub::char_table[CellularUtil_stub::table_idx])] = '\0'; CellularUtil_stub::table_idx--; - memcpy(ip2, CellularUtil_stub::char_table[CellularUtil_stub::table_idx], - strlen(CellularUtil_stub::char_table[CellularUtil_stub::table_idx])); - ip2[strlen(CellularUtil_stub::char_table[CellularUtil_stub::table_idx])] = '\0'; + if (ip2) { + memcpy(ip2, CellularUtil_stub::char_table[CellularUtil_stub::table_idx], + strlen(CellularUtil_stub::char_table[CellularUtil_stub::table_idx])); + ip2[strlen(CellularUtil_stub::char_table[CellularUtil_stub::table_idx])] = '\0'; + } } } @@ -83,9 +85,11 @@ void separate_ip_addresses(char *orig, char *ip, size_t ip_size, char *ip2, size strlen(CellularUtil_stub::char_table[CellularUtil_stub::table_idx])); ip[strlen(CellularUtil_stub::char_table[CellularUtil_stub::table_idx])] = '\0'; CellularUtil_stub::table_idx--; - memcpy(ip2, CellularUtil_stub::char_table[CellularUtil_stub::table_idx], - strlen(CellularUtil_stub::char_table[CellularUtil_stub::table_idx])); - ip2[strlen(CellularUtil_stub::char_table[CellularUtil_stub::table_idx])] = '\0'; + if (ip2) { + memcpy(ip2, CellularUtil_stub::char_table[CellularUtil_stub::table_idx], + strlen(CellularUtil_stub::char_table[CellularUtil_stub::table_idx])); + ip2[strlen(CellularUtil_stub::char_table[CellularUtil_stub::table_idx])] = '\0'; + } } } diff --git a/features/cellular/framework/AT/AT_CellularContext.cpp b/features/cellular/framework/AT/AT_CellularContext.cpp index e0e192e8fbe..d29b058a0ed 100644 --- a/features/cellular/framework/AT/AT_CellularContext.cpp +++ b/features/cellular/framework/AT/AT_CellularContext.cpp @@ -816,9 +816,7 @@ nsapi_error_t AT_CellularContext::get_rate_control( nsapi_error_t AT_CellularContext::get_pdpcontext_params(pdpContextList_t ¶ms_list) { const int ipv6_subnet_size = 128; - const int max_ipv6_size = 64; char *ipv6_and_subnetmask = new char[ipv6_subnet_size]; - char *temp = new char[max_ipv6_size]; _at.lock(); @@ -834,38 +832,28 @@ nsapi_error_t AT_CellularContext::get_pdpcontext_params(pdpContextList_t ¶ms // rest are optional params ipv6_and_subnetmask[0] = '\0'; - temp[0] = '\0'; _at.read_string(ipv6_and_subnetmask, ipv6_subnet_size); separate_ip_addresses(ipv6_and_subnetmask, params->local_addr, sizeof(params->local_addr), params->local_subnet_mask, sizeof(params->local_subnet_mask)); ipv6_and_subnetmask[0] = '\0'; _at.read_string(ipv6_and_subnetmask, ipv6_subnet_size); - separate_ip_addresses(ipv6_and_subnetmask, params->gateway_addr, sizeof(params->gateway_addr), temp, max_ipv6_size); - prefer_ipv6(params->gateway_addr, sizeof(params->gateway_addr), temp, max_ipv6_size); + separate_ip_addresses(ipv6_and_subnetmask, params->gateway_addr, sizeof(params->gateway_addr), NULL, 0); ipv6_and_subnetmask[0] = '\0'; - temp[0] = '\0'; _at.read_string(ipv6_and_subnetmask, ipv6_subnet_size); - separate_ip_addresses(ipv6_and_subnetmask, params->dns_primary_addr, sizeof(params->dns_primary_addr), temp, max_ipv6_size); - prefer_ipv6(params->dns_primary_addr, sizeof(params->dns_primary_addr), temp, max_ipv6_size); + separate_ip_addresses(ipv6_and_subnetmask, params->dns_primary_addr, sizeof(params->dns_primary_addr), NULL, 0); ipv6_and_subnetmask[0] = '\0'; - temp[0] = '\0'; _at.read_string(ipv6_and_subnetmask, ipv6_subnet_size); - separate_ip_addresses(ipv6_and_subnetmask, params->dns_secondary_addr, sizeof(params->dns_secondary_addr), temp, max_ipv6_size); - prefer_ipv6(params->dns_secondary_addr, sizeof(params->dns_secondary_addr), temp, max_ipv6_size); + separate_ip_addresses(ipv6_and_subnetmask, params->dns_secondary_addr, sizeof(params->dns_secondary_addr), NULL, 0); ipv6_and_subnetmask[0] = '\0'; - temp[0] = '\0'; _at.read_string(ipv6_and_subnetmask, ipv6_subnet_size); - separate_ip_addresses(ipv6_and_subnetmask, params->p_cscf_prim_addr, sizeof(params->p_cscf_prim_addr), temp, max_ipv6_size); - prefer_ipv6(params->p_cscf_prim_addr, sizeof(params->p_cscf_prim_addr), temp, max_ipv6_size); + separate_ip_addresses(ipv6_and_subnetmask, params->p_cscf_prim_addr, sizeof(params->p_cscf_prim_addr), NULL, 0); ipv6_and_subnetmask[0] = '\0'; - temp[0] = '\0'; _at.read_string(ipv6_and_subnetmask, ipv6_subnet_size); - separate_ip_addresses(ipv6_and_subnetmask, params->p_cscf_sec_addr, sizeof(params->p_cscf_sec_addr), temp, max_ipv6_size); - prefer_ipv6(params->p_cscf_sec_addr, sizeof(params->p_cscf_sec_addr), temp, max_ipv6_size); + separate_ip_addresses(ipv6_and_subnetmask, params->p_cscf_sec_addr, sizeof(params->p_cscf_sec_addr), NULL, 0); params->im_signalling_flag = _at.read_int(); params->lipa_indication = _at.read_int(); @@ -877,7 +865,6 @@ nsapi_error_t AT_CellularContext::get_pdpcontext_params(pdpContextList_t ¶ms } _at.resp_stop(); - delete [] temp; delete [] ipv6_and_subnetmask; return _at.unlock_return_error(); diff --git a/features/cellular/framework/common/CellularUtil.cpp b/features/cellular/framework/common/CellularUtil.cpp index 1128955e0e6..7157ecb6a58 100644 --- a/features/cellular/framework/common/CellularUtil.cpp +++ b/features/cellular/framework/common/CellularUtil.cpp @@ -205,16 +205,7 @@ void separate_ip_addresses(char *orig, char *ip, size_t ip_size, char *ip2, size } } } else { - temp = strstr(orig, " "); - // found space as separator and it wasn't in beginning --> contains 2 ip addresses - if (temp && temp != orig) { - separate_ip4like_addresses(temp++, ip2, ip2_size, NULL, 0); - orig[temp - orig - 1] = '\0'; - separate_ip4like_addresses(orig, ip, ip_size, NULL, 0); - orig[temp - orig - 1] = ' '; // put space back to keep orig as original - } else { - separate_ip4like_addresses(orig, ip, ip_size, ip2, ip2_size); - } + separate_ip4like_addresses(orig, ip, ip_size, ip2, ip2_size); } } From 9145b72433ee82f5aae03a6fd16af53213ec3f80 Mon Sep 17 00:00:00 2001 From: Ben Cooke Date: Thu, 29 Aug 2019 11:46:36 -0500 Subject: [PATCH 182/227] Add MTS_DRAGONFLY_F413RH platform to mbed-os --- .../blockdevice/COMPONENT_SPIF/mbed_lib.json | 6 + .../ONBOARD_TELIT_HE910.cpp | 70 +++++ .../ONBOARD_TELIT_HE910.h | 36 +++ .../PeripheralNames.h | 90 ++++++ .../PeripheralPins.c | 289 ++++++++++++++++++ .../TARGET_MTS_DRAGONFLY_F413RH/PinNames.h | 217 +++++++++++++ .../onboard_modem_api.c | 65 ++++ .../system_clock.c | 239 +++++++++++++++ targets/targets.json | 61 ++++ tools/arm_pack_manager/index.json | 25 +- 10 files changed, 1096 insertions(+), 2 deletions(-) create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_MTS_DRAGONFLY_F413RH/ONBOARD_TELIT_HE910.cpp create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_MTS_DRAGONFLY_F413RH/ONBOARD_TELIT_HE910.h create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_MTS_DRAGONFLY_F413RH/PeripheralNames.h create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_MTS_DRAGONFLY_F413RH/PeripheralPins.c create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_MTS_DRAGONFLY_F413RH/PinNames.h create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_MTS_DRAGONFLY_F413RH/onboard_modem_api.c create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_MTS_DRAGONFLY_F413RH/system_clock.c diff --git a/components/storage/blockdevice/COMPONENT_SPIF/mbed_lib.json b/components/storage/blockdevice/COMPONENT_SPIF/mbed_lib.json index b0b4d7b5984..1d0fddaeb94 100644 --- a/components/storage/blockdevice/COMPONENT_SPIF/mbed_lib.json +++ b/components/storage/blockdevice/COMPONENT_SPIF/mbed_lib.json @@ -73,6 +73,12 @@ "SPI_MISO": "SPI3_MISO", "SPI_CLK": "SPI3_SCK", "SPI_CS": "SPI_CS1" + }, + "MTS_DRAGONFLY_F413RH": { + "SPI_MOSI": "SPI3_MOSI", + "SPI_MISO": "SPI3_MISO", + "SPI_CLK": "SPI3_SCK", + "SPI_CS": "SPI_CS1" } } } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_MTS_DRAGONFLY_F413RH/ONBOARD_TELIT_HE910.cpp b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_MTS_DRAGONFLY_F413RH/ONBOARD_TELIT_HE910.cpp new file mode 100644 index 00000000000..8b1bd8979e7 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_MTS_DRAGONFLY_F413RH/ONBOARD_TELIT_HE910.cpp @@ -0,0 +1,70 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if MBED_CONF_NSAPI_PRESENT + +#include "cellular/onboard_modem_api.h" +#include "UARTSerial.h" +#include "ONBOARD_TELIT_HE910.h" +#include "ThisThread.h" +#include "CellularLog.h" + +using namespace mbed; + +ONBOARD_TELIT_HE910::ONBOARD_TELIT_HE910(FileHandle *fh) : TELIT_HE910(fh) +{ +} + +nsapi_error_t ONBOARD_TELIT_HE910::hard_power_on() +{ + ::onboard_modem_init(); + return NSAPI_ERROR_OK; +} + +nsapi_error_t ONBOARD_TELIT_HE910::hard_power_off() +{ + ::onboard_modem_deinit(); + return NSAPI_ERROR_OK; +} + +nsapi_error_t ONBOARD_TELIT_HE910::soft_power_on() +{ + ::onboard_modem_power_up(); + // From Telit_xE910 Global form factor App note: It is mandatory to avoid sending data to the serial ports during the first 200ms of the module start-up. + rtos::ThisThread::sleep_for(200); + return NSAPI_ERROR_OK; +} + +nsapi_error_t ONBOARD_TELIT_HE910::soft_power_off() +{ + ::onboard_modem_power_down(); + return NSAPI_ERROR_OK; +} + +CellularDevice *CellularDevice::get_target_default_instance() +{ + static UARTSerial serial(MDMTXD, MDMRXD, 115200); +#if DEVICE_SERIAL_FC + if (MDMRTS != NC && MDMCTS != NC) { + tr_debug("Modem flow control: RTS %d CTS %d", MDMRTS, MDMCTS); + serial.set_flow_control(SerialBase::RTSCTS, MDMRTS, MDMCTS); + } +#endif + static ONBOARD_TELIT_HE910 device(&serial); + return &device; +} + +#endif // MBED_CONF_NSAPI_PRESENT diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_MTS_DRAGONFLY_F413RH/ONBOARD_TELIT_HE910.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_MTS_DRAGONFLY_F413RH/ONBOARD_TELIT_HE910.h new file mode 100644 index 00000000000..9e08961411a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_MTS_DRAGONFLY_F413RH/ONBOARD_TELIT_HE910.h @@ -0,0 +1,36 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ONBOARD_TELIT_HE910_ +#define ONBOARD_TELIT_HE910_ + +#include "TELIT_HE910.h" + +namespace mbed { + +class ONBOARD_TELIT_HE910 : public TELIT_HE910 { +public: + ONBOARD_TELIT_HE910(FileHandle *fh); + + virtual nsapi_error_t hard_power_on(); + virtual nsapi_error_t hard_power_off(); + virtual nsapi_error_t soft_power_on(); + virtual nsapi_error_t soft_power_off(); +}; + +} // namespace mbed + +#endif // ONBOARD_TELIT_HE910_ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_MTS_DRAGONFLY_F413RH/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_MTS_DRAGONFLY_F413RH/PeripheralNames.h new file mode 100644 index 00000000000..3493e2cd25e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_MTS_DRAGONFLY_F413RH/PeripheralNames.h @@ -0,0 +1,90 @@ +/* mbed Microcontroller Library + * Copyright (c) 2016 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC_1 = (int)ADC1_BASE +} ADCName; + +typedef enum { + DAC_1 = (int)DAC_BASE +} DACName; + +typedef enum { + UART_1 = (int)USART1_BASE, + UART_2 = (int)USART2_BASE, + UART_3 = (int)USART3_BASE, + UART_4 = (int)UART4_BASE, + UART_5 = (int)UART5_BASE, + UART_6 = (int)USART6_BASE, + UART_7 = (int)UART7_BASE, + UART_8 = (int)UART8_BASE, + UART_9 = (int)UART9_BASE, + UART_10 = (int)UART10_BASE +} UARTName; + +typedef enum { + SPI_1 = (int)SPI1_BASE, + SPI_2 = (int)SPI2_BASE, + SPI_3 = (int)SPI3_BASE, + SPI_4 = (int)SPI4_BASE, + SPI_5 = (int)SPI5_BASE +} SPIName; + +typedef enum { + I2C_1 = (int)I2C1_BASE, + I2C_2 = (int)I2C2_BASE, + I2C_3 = (int)I2C3_BASE, + FMPI2C_1 = (int)FMPI2C1_BASE +} I2CName; + +typedef enum { + PWM_1 = (int)TIM1_BASE, + PWM_2 = (int)TIM2_BASE, + PWM_3 = (int)TIM3_BASE, + PWM_4 = (int)TIM4_BASE, + PWM_5 = (int)TIM5_BASE, + PWM_8 = (int)TIM8_BASE, + PWM_9 = (int)TIM9_BASE, + PWM_10 = (int)TIM10_BASE, + PWM_11 = (int)TIM11_BASE, + PWM_12 = (int)TIM12_BASE, + PWM_13 = (int)TIM13_BASE, + PWM_14 = (int)TIM14_BASE +} PWMName; + +typedef enum { + CAN_1 = (int)CAN1_BASE, + CAN_2 = (int)CAN2_BASE, + CAN_3 = (int)CAN3_BASE +} CANName; + +typedef enum { + QSPI_1 = (int)QSPI_R_BASE, +} QSPIName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_MTS_DRAGONFLY_F413RH/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_MTS_DRAGONFLY_F413RH/PeripheralPins.c new file mode 100644 index 00000000000..39ec61bace4 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_MTS_DRAGONFLY_F413RH/PeripheralPins.c @@ -0,0 +1,289 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2018, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "PeripheralPins.h" +#include "mbed_toolchain.h" + +//============================================================================== +// Notes +// +// - The pins mentioned Px_y_ALTz are alternative possibilities which use other +// HW peripheral instances. You can use them the same way as any other "normal" +// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board +// pinout image on mbed.org. +// +// - The pins which are connected to other components present on the board have +// the comment "Connected to xxx". The pin function may not work properly in this +// case. These pins may not be displayed on the board pinout image on mbed.org. +// Please read the board reference manual and schematic for more information. +// +// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented +// See https://os.mbed.com/teams/ST/wiki/STDIO for more information. +// +//============================================================================== + + +//*** ADC *** + +MBED_WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_ADC_Internal[] = { + {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, + {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, + {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, + {NC, NC, 0} +}; + +//*** DAC *** + +MBED_WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC_OUT1 + {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC_OUT2 + {NC, NC, 0} +}; + +//*** I2C *** + +MBED_WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)}, + {PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_15, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)}, + {NC, NC, 0} +}; + +//*** PWM *** +// TIM5 cannot be used because already used by the us_ticker +MBED_WEAK const PinMap PinMap_PWM[] = { + {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {NC, NC, 0} +}; + +//*** SERIAL *** + +MBED_WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PA_12, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART4)}, + {PA_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_4, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_9, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART5)}, + {PB_13, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART5)}, + {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART4)}, + {PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART5)}, + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_8, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART5)}, + {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {NC, NC, 0} +}; + +//*** SPI *** + +MBED_WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_1, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PB_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)}, + {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI4)}, + {PA_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)}, + {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_7, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_11, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PB_1, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI5)}, + {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {NC, NC, 0} +}; + +//*** CAN *** + +MBED_WEAK const PinMap PinMap_CAN_RD[] = { + {PA_8, CAN_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_CAN3)}, + {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PB_3, CAN_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_CAN3)}, + {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_CAN1)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PA_15, CAN_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_CAN3)}, + {PB_4, CAN_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF11_CAN3)}, + {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_CAN1)}, + {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, + {NC, NC, 0} +}; + +//*** QUADSPI *** + +MBED_WEAK const PinMap PinMap_QSPI_DATA0[] = { + {PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO0 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_DATA1[] = { + {PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO1 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_DATA2[] = { + {PC_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_DATA3[] = { + {PA_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = { + {PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_CLK + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = { + {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS + {NC, NC, 0} +}; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_MTS_DRAGONFLY_F413RH/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_MTS_DRAGONFLY_F413RH/PinNames.h new file mode 100644 index 00000000000..5bd280463d7 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_MTS_DRAGONFLY_F413RH/PinNames.h @@ -0,0 +1,217 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + // Not connected + NC = -1, + + PA_0 = 0x00, + PA_1 = 0x01, + PA_2 = 0x02, + PA_3 = 0x03, + PA_4 = 0x04, + PA_5 = 0x05, + PA_6 = 0x06, + PA_7 = 0x07, + PA_8 = 0x08, + PA_9 = 0x09, + PA_10 = 0x0A, + PA_11 = 0x0B, + PA_12 = 0x0C, + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + + PB_0 = 0x10, + PB_1 = 0x11, + PB_2 = 0x12, + PB_3 = 0x13, + PB_4 = 0x14, + PB_5 = 0x15, + PB_6 = 0x16, + PB_7 = 0x17, + PB_8 = 0x18, + PB_9 = 0x19, + PB_10 = 0x1A, + PB_12 = 0x1C, + PB_13 = 0x1D, + PB_14 = 0x1E, + PB_15 = 0x1F, + + PC_0 = 0x20, + PC_1 = 0x21, + PC_2 = 0x22, + PC_3 = 0x23, + PC_4 = 0x24, + PC_5 = 0x25, + PC_6 = 0x26, + PC_7 = 0x27, + PC_8 = 0x28, + PC_9 = 0x29, + PC_10 = 0x2A, + PC_11 = 0x2B, + PC_12 = 0x2C, + PC_13 = 0x2D, + PC_14 = 0x2E, + PC_15 = 0x2F, + + PD_2 = 0x32, + + PH_0 = 0x70, + PH_1 = 0x71, + + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + ADC_VBAT = 0xF2, + + // Arduino connector namings + A0 = PC_2, + A1 = PC_0, + A2 = PC_4, + A3 = PB_0, + A4 = PC_1, + A5 = PC_9, + D0 = PA_3, + D1 = PA_2, + D2 = PB_15, + D3 = PA_0, + D4 = PA_7, + D5 = PA_9, + D6 = PA_1, + D7 = PA_8, + D8 = PB_1, + D9 = PB_13, + D10 = PC_8, + D11 = PB_5, + D12 = PA_6, + D13 = PA_5, + D14 = PB_9, + D15 = PB_8, + + // Generic signals namings + LED1 = D3, + LED2 = D3, + LED3 = D3, + LED4 = D3, + LED_RED = LED1, + BUTTON1 = NC, + SERIAL_TX = D1, + SERIAL_RX = D0, + SERIAL_RTS = D3, + SERIAL_CTS = D6, + SERIAL_DCD = D4, + SERIAL_DSR = D5, + SERIAL_DTR = D7, + SERIAL_RI = D8, + USBTX = PB_6, + USBRX = PB_7, +// STDIO for console print + STDIO_UART_TX = USBTX, + STDIO_UART_RX = USBRX, + RADIO_TX = PC_6, + RADIO_RX = PC_7, + RADIO_RTS = PB_10, + RADIO_CTS = PB_12, + RADIO_DCD = NC, + RADIO_DSR = NC, + RADIO_DTR = NC, + RADIO_RI = NC, + MDMPWRON = PC_13, // 3G_ONOFF DragonFly Design Guide, Page No. 16 + MDMTXD = RADIO_TX, // Transmit Data + MDMRXD = RADIO_RX, // Receive Data + MDMRTS = RADIO_RTS, // Request to Send + MDMCTS = RADIO_CTS, // Clear to Send + MDMDCD = RADIO_DCD, // Data Carrier Detect + MDMDSR = RADIO_DSR, // Data Set Ready + MDMDTR = RADIO_DTR, // Data Terminal Ready + MDMRI = RADIO_RI, // Ring Indicator + + WAKEUP = D3, + + // I2C1 and I2C3 are available on Arduino pins + I2C1_SCL = D15, + I2C1_SDA = D14, + I2C3_SCL = D7, + I2C3_SDA = A5, + + // legacy definitions + I2C_SCL = I2C1_SCL, + I2C_SDA = I2C1_SDA, + + // SPI1 and SPI2 are available on Arduino pins + SPI1_MOSI = D11, + SPI1_MISO = D12, + SPI1_SCK = D13, + SPI2_MOSI = D2, + SPI2_MISO = A0, + SPI2_SCK = D9, + + // SPI3 connects to flash part + SPI3_MOSI = PC_12, + SPI3_MISO = PC_11, + SPI3_SCK = PC_10, + + // legacy definitions + SPI_MOSI = SPI3_MOSI, + SPI_MISO = SPI3_MISO, + SPI_SCK = SPI3_SCK, + SPI_CS1 = PA_4, + SPI_CS2 = PB_14, + + /**** USB pins ****/ + USB_OTG_FS_DM = PA_11, + USB_OTG_FS_DP = PA_12, + USB_OTG_FS_ID = PA_10, + USB_OTG_FS_SOF = PA_8, + USB_OTG_FS_VBUS = PA_9 + +} PinName; + +#define ACTIVE_HIGH_POLARITY 1 +#define ACTIVE_LOW_POLARITY 0 + +#define MDM_PIN_POLARITY ACTIVE_HIGH_POLARITY + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_MTS_DRAGONFLY_F413RH/onboard_modem_api.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_MTS_DRAGONFLY_F413RH/onboard_modem_api.c new file mode 100644 index 00000000000..82e623e28eb --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_MTS_DRAGONFLY_F413RH/onboard_modem_api.c @@ -0,0 +1,65 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if MBED_CONF_NSAPI_PRESENT + +#include "cellular/onboard_modem_api.h" +#include "gpio_api.h" +#include "platform/mbed_wait_api.h" +#include "PinNames.h" + +#if MODEM_ON_BOARD + +static void press_power_button(int time_ms) +{ + gpio_t gpio; + + gpio_init_out_ex(&gpio, MDMPWRON, 1); + gpio_write(&gpio, 0); + wait_ms(time_ms); + gpio_write(&gpio, 1); +} + +void onboard_modem_init() +{ + //does nothing at the moment, TODO: MultiTech to add hardware initialization stuff if needed +} + +void onboard_modem_deinit() +{ + //does nothing at the moment, TODO: MultiTech to add hardware de-initialization stuff if needed +} +void onboard_modem_power_up() +{ + /* keep the power line low for 200 milisecond */ + press_power_button(200); + /* give modem a little time to respond */ + wait_ms(100); +} + +void onboard_modem_power_down() +{ + gpio_t gpio; + + gpio_init_out_ex(&gpio, MDMPWRON, 0); + /* keep the power line low for more than 10 seconds. + * If 3G_ON_OFF pin is kept low for more than a second, a controlled disconnect and shutdown takes + * place, Due to the network disconnect, shut-off can take up to 30 seconds. However, we wait for 10 + * seconds only */ + wait_ms(10 * 1000); +} +#endif //MODEM_ON_BOARD +#endif //MBED_CONF_NSAPI_PRESENT diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_MTS_DRAGONFLY_F413RH/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_MTS_DRAGONFLY_F413RH/system_clock.c new file mode 100644 index 00000000000..e7cc6eed4e5 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_MTS_DRAGONFLY_F413RH/system_clock.c @@ -0,0 +1,239 @@ +/* mbed Microcontroller Library +* Copyright (c) 2006-2017 ARM Limited +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*/ + +/** + * This file configures the system clock as follows: + *----------------------------------------------------------------------------- + * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI + * | (external 8 MHz clock) | (internal 16 MHz) + * | 2- PLL_HSE_XTAL | + * | (external 8 MHz xtal) | + *----------------------------------------------------------------------------- + * SYSCLK(MHz) | 100 | 100 + *----------------------------------------------------------------------------- + * AHBCLK (MHz) | 100 | 100 + *----------------------------------------------------------------------------- + * APB1CLK (MHz) | 50 | 50 + *----------------------------------------------------------------------------- + * APB2CLK (MHz) | 100 | 100 + *----------------------------------------------------------------------------- + * USB capable (48 MHz precise clock) | NO | NO + *----------------------------------------------------------------------------- +**/ + +#include "stm32f4xx.h" +#include "mbed_debug.h" +#include "nvic_addr.h" + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#ifndef VECT_TAB_OFFSET +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#endif + + +/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ +#define USE_PLL_HSE_EXTC (0) /* Use external clock */ +#define USE_PLL_HSE_XTAL (1) /* Use external xtal */ + +#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) +uint8_t SetSysClock_PLL_HSE(uint8_t bypass); +#endif + +uint8_t SetSysClock_PLL_HSI(void); + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting, vector table location and External memory + * configuration. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ +#endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ +#endif + +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +void SetSysClock(void) +{ + /* 1- Try to start with HSE and external clock */ +#if USE_PLL_HSE_EXTC != 0 + if (SetSysClock_PLL_HSE(1) == 0) +#endif + { + /* 2- If fail try to start with HSE and external xtal */ +#if USE_PLL_HSE_XTAL != 0 + if (SetSysClock_PLL_HSE(0) == 0) +#endif + { + /* 3- If fail start with HSI clock */ + if (SetSysClock_PLL_HSI() == 0) { + while(1) { + // [TODO] Put something here to tell the user that a problem occured... + } + } + } + } + + /* Output clock on MCO2 pin(PC9) for debugging purpose */ + //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 100 MHz / 4 = 25 MHz +} + +#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSE(uint8_t bypass) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + /* The voltage scaling allows optimizing the power consumption when the device is + clocked below the maximum system frequency, to update the voltage scaling value + regarding system frequency refer to product datasheet. */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); + + /* Enable HSE oscillator and activate PLL with HSE as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + if (bypass == 0) { + RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */ + } else { + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */ + } + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + //RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8) + //RCC_OscInitStruct.PLL.PLLN = 400; // VCO output clock = 400 MHz (1 MHz * 400) + RCC_OscInitStruct.PLL.PLLM = 13; // VCO input clock = 2 MHz (8 MHz / 4) + RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 400 MHz (2 MHz * 200) + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4) + RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { + return 0; // FAIL + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + + //if (bypass == 0) + // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal + //else + // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock + + return 1; // OK +} +#endif + +/******************************************************************************/ +/* PLL (clocked by HSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSI(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + /* The voltage scaling allows optimizing the power consumption when the device is + clocked below the maximum system frequency, to update the voltage scaling value + regarding system frequency refer to product datasheet. */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); + + /* Enable HSI oscillator and activate PLL with HSI as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + //RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16) + //RCC_OscInitStruct.PLL.PLLN = 400; // VCO output clock = 400 MHz (1 MHz * 400) + RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8) + RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200) + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4) + RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { + return 0; // FAIL + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz + + return 1; // OK +} + diff --git a/targets/targets.json b/targets/targets.json index 928101029ff..dc258bb9f64 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -4551,6 +4551,67 @@ "device_name": "STM32F411RE", "bootloader_supported": true }, + "MTS_DRAGONFLY_F413RH": { + "inherits": ["FAMILY_STM32"], + "core": "Cortex-M4F", + "extra_labels_add": [ + "STM32F4", + "STM32F413xx", + "STM32F413ZH", + "STM32F413xH" + ], + "config": { + "modem_is_on_board": { + "help": "Value: Tells the build system that the modem is on-board as oppose to a plug-in shield/module.", + "value": 1, + "macro_name": "MODEM_ON_BOARD" + }, + "modem_data_connection_type": { + "help": "Value: Defines how an on-board modem is wired up to the MCU, e.g., data connection can be a UART or USB and so forth.", + "value": 1, + "macro_name": "MODEM_ON_BOARD_UART" + }, + "lpticker_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer", + "value": 1 + }, + "clock_source": { + "help": "USE_PLL_HSE_XTAL | USE_PLL_HSI", + "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI", + "macro_name": "CLOCK_SOURCE" + }, + "hse_value": { + "help": "HSE via 26MHz xtal", + "value": "26000000", + "macro_name": "HSE_VALUE" + } + }, + "overrides": { "lpticker_delay_ticks": 4, "tickless-from-us-ticker": true, "lse_available": 0}, + "detect_code": ["0316"], + "macros_add": [ + "MBED_TICKLESS", + "USBSTM_HAL_UNSUPPORTED" + ], + "device_has_add": [ + "ANALOGOUT", + "CAN", + "SERIAL_ASYNCH", + "TRNG", + "FLASH", + "MPU" + ], + "device_has_remove": [ + "SERIAL_FC" + ], + "components_add": ["FLASHIAP", "SPIF"], + "bootloader_supported": true, + "release_versions": ["2", "5"], + "device_name": "STM32F413RHTx", + "mbed_rom_start" : "0x08000000", + "mbed_rom_size" : "0x180000", + "mbed_ram_start" : "0x200001D8", + "mbed_ram_size" : "0x50000" + }, "MTS_DRAGONFLY_L471QG": { "inherits": ["FAMILY_STM32"], "supported_form_factors": ["ARDUINO"], diff --git a/tools/arm_pack_manager/index.json b/tools/arm_pack_manager/index.json index dfd29fe2e92..ab49324b74a 100644 --- a/tools/arm_pack_manager/index.json +++ b/tools/arm_pack_manager/index.json @@ -366558,8 +366558,29 @@ "mpu": "Present", "units": 1 } - }, - "sectors": null, + }, + "sectors": [ + [ + 134217728, + 16384 + ], + [ + 134283264, + 65536 + ], + [ + 134348800, + 131072 + ], + [ + 536836096, + 528 + ], + [ + 536854528, + 4 + ] + ], "sub_family": "STM32F413", "vendor": "STMicroelectronics:13" }, From 0039cfb7435adb6d65744baba1e48de847671f7d Mon Sep 17 00:00:00 2001 From: Michal Paszta Date: Mon, 30 Sep 2019 18:35:03 +0300 Subject: [PATCH 183/227] Increase timeout in DNS_TIMEOUTS test for ESP8266 The test floods the device with UDP requests (it skips the 100 ms delay to simulate instant timeout). ESP8266 starts responding with "busy p..." message. It needs more time to process the data and recover for subsequent tests. --- TESTS/netsocket/dns/asynchronous_dns_timeouts.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/TESTS/netsocket/dns/asynchronous_dns_timeouts.cpp b/TESTS/netsocket/dns/asynchronous_dns_timeouts.cpp index a22fb2fcf92..a37f86a24de 100644 --- a/TESTS/netsocket/dns/asynchronous_dns_timeouts.cpp +++ b/TESTS/netsocket/dns/asynchronous_dns_timeouts.cpp @@ -74,7 +74,7 @@ void ASYNCHRONOUS_DNS_TIMEOUTS() TEST_ASSERT(result_exp_timeout > 0); // Give event queue time to finalise before destructors - ThisThread::sleep_for(2000); + ThisThread::sleep_for(12000); nsapi_dns_call_in_set(0); } From 39e17a111f898b12ae365ce1ed5532f39263b0c5 Mon Sep 17 00:00:00 2001 From: Michal Paszta Date: Mon, 30 Sep 2019 18:38:34 +0300 Subject: [PATCH 184/227] Increase the timeout for DNS tests as their number increased --- TESTS/netsocket/dns/dns_tests.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/TESTS/netsocket/dns/dns_tests.h b/TESTS/netsocket/dns/dns_tests.h index aaec1cd4584..026acbe9303 100644 --- a/TESTS/netsocket/dns/dns_tests.h +++ b/TESTS/netsocket/dns/dns_tests.h @@ -69,7 +69,7 @@ namespace dns_global { #ifdef MBED_GREENTEA_TEST_DNSSOCKET_TIMEOUT_S static const int TESTS_TIMEOUT = MBED_GREENTEA_TEST_DNSSOCKET_TIMEOUT_S; #else -static const int TESTS_TIMEOUT = 10 * 60; +static const int TESTS_TIMEOUT = 14 * 60; #endif } From d8b88dc5dd6e545a0fb87f0639aeebddd7d1f7dd Mon Sep 17 00:00:00 2001 From: Filip Jagodzinski Date: Tue, 1 Oct 2019 14:39:28 +0200 Subject: [PATCH 185/227] Tests: USB: Move control endpoint buffers to heap This fixes the stack overflow error during the basic USB tests. Update the ctrl_buf member of the USBTester and USBEndpointTester test classes to be allocated on the heap. This saves 2 KB of a main stack. --- TESTS/usb_device/basic/USBEndpointTester.cpp | 6 +++++- TESTS/usb_device/basic/USBEndpointTester.h | 5 +++-- TESTS/usb_device/basic/USBTester.cpp | 7 +++++-- TESTS/usb_device/basic/USBTester.h | 5 +++-- 4 files changed, 16 insertions(+), 7 deletions(-) diff --git a/TESTS/usb_device/basic/USBEndpointTester.cpp b/TESTS/usb_device/basic/USBEndpointTester.cpp index 476e407acbc..0b95dff2121 100644 --- a/TESTS/usb_device/basic/USBEndpointTester.cpp +++ b/TESTS/usb_device/basic/USBEndpointTester.cpp @@ -40,6 +40,8 @@ #define VENDOR_TEST_RW_RESTART 11 #define VENDOR_TEST_ABORT_BUFF_CHECK 12 +#define CTRL_BUF_SIZE (2048) + #define EVENT_READY (1 << 0) #define TEST_SIZE_EP_BULK_MAX (64) @@ -170,6 +172,7 @@ USBEndpointTester::USBEndpointTester(USBPhy *phy, uint16_t vendor_id, uint16_t p queue = mbed::mbed_highprio_event_queue(); configuration_desc(0); + ctrl_buf = new uint8_t[CTRL_BUF_SIZE]; init(); USBDevice::connect(); flags.wait_any(EVENT_READY, osWaitForever, false); @@ -183,6 +186,7 @@ USBEndpointTester::~USBEndpointTester() } } deinit(); + delete[] ctrl_buf; } const char *USBEndpointTester::get_desc_string(const uint8_t *desc) @@ -225,7 +229,7 @@ void USBEndpointTester::callback_request(const setup_packet_t *setup) case VENDOR_TEST_CTRL_IN: result = Send; data = ctrl_buf; - size = setup->wValue < sizeof(ctrl_buf) ? setup->wValue : sizeof(ctrl_buf); + size = setup->wValue < CTRL_BUF_SIZE ? setup->wValue : CTRL_BUF_SIZE; break; case VENDOR_TEST_CTRL_OUT: result = Receive; diff --git a/TESTS/usb_device/basic/USBEndpointTester.h b/TESTS/usb_device/basic/USBEndpointTester.h index be099c1484d..b6037f60a7a 100644 --- a/TESTS/usb_device/basic/USBEndpointTester.h +++ b/TESTS/usb_device/basic/USBEndpointTester.h @@ -23,12 +23,13 @@ #include "USBDevice_Types.h" #include "EventQueue.h" #include "EventFlags.h" +#include "platform/NonCopyable.h" #include "USBDevice.h" #define NUM_ENDPOINTS 6 // Not including CTRL OUT/IN -class USBEndpointTester: public USBDevice { +class USBEndpointTester: public USBDevice, private mbed::NonCopyable { public: USBEndpointTester(USBPhy *phy, uint16_t vendor_id, uint16_t product_id, uint16_t product_release, @@ -80,7 +81,7 @@ class USBEndpointTester: public USBDevice { protected: events::EventQueue *queue; rtos::EventFlags flags; - uint8_t ctrl_buf[2048]; + uint8_t *ctrl_buf; bool _abort_transfer_test; usb_ep_t _endpoints[NUM_ENDPOINTS]; diff --git a/TESTS/usb_device/basic/USBTester.cpp b/TESTS/usb_device/basic/USBTester.cpp index eba6d79714a..6907a859c1f 100644 --- a/TESTS/usb_device/basic/USBTester.cpp +++ b/TESTS/usb_device/basic/USBTester.cpp @@ -37,6 +37,8 @@ #define MAX_EP_SIZE 64 #define MIN_EP_SIZE 8 +#define CTRL_BUF_SIZE (2048) + #define EVENT_READY (1 << 0) @@ -57,7 +59,7 @@ USBTester::USBTester(USBPhy *phy, uint16_t vendor_id, uint16_t product_id, uint1 queue = mbed::mbed_highprio_event_queue(); configuration_desc(0); - + ctrl_buf = new uint8_t[CTRL_BUF_SIZE]; init(); USBDevice::connect(); flags.wait_any(EVENT_READY, osWaitForever, false); @@ -67,6 +69,7 @@ USBTester::USBTester(USBPhy *phy, uint16_t vendor_id, uint16_t product_id, uint1 USBTester::~USBTester() { deinit(); + delete[] ctrl_buf; } @@ -138,7 +141,7 @@ void USBTester::callback_request(const setup_packet_t *setup) case VENDOR_TEST_CTRL_IN: result = Send; data = ctrl_buf; - size = setup->wValue < sizeof(ctrl_buf) ? setup->wValue : sizeof(ctrl_buf); + size = setup->wValue < CTRL_BUF_SIZE ? setup->wValue : CTRL_BUF_SIZE; break; case VENDOR_TEST_CTRL_OUT: result = Receive; diff --git a/TESTS/usb_device/basic/USBTester.h b/TESTS/usb_device/basic/USBTester.h index 01045501e7e..76258004d99 100644 --- a/TESTS/usb_device/basic/USBTester.h +++ b/TESTS/usb_device/basic/USBTester.h @@ -23,10 +23,11 @@ #include "USBDevice_Types.h" #include "EventQueue.h" #include "EventFlags.h" +#include "platform/NonCopyable.h" #include "USBDevice.h" -class USBTester: public USBDevice { +class USBTester: public USBDevice, private mbed::NonCopyable { public: /* @@ -138,7 +139,7 @@ class USBTester: public USBDevice { virtual void epbulk_out_callback(); virtual void epint_out_callback(); virtual void callback_reset(); - uint8_t ctrl_buf[2048]; + uint8_t *ctrl_buf; }; From e2d6d26ab5a8f256942f519ccdd4f15f88871352 Mon Sep 17 00:00:00 2001 From: Juhani Puurula Date: Thu, 3 Oct 2019 12:12:43 +0300 Subject: [PATCH 186/227] Change imgtool lib import to relative import --- tools/psa/tfm/bin_utils/imgtool.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tools/psa/tfm/bin_utils/imgtool.py b/tools/psa/tfm/bin_utils/imgtool.py index b984ce21708..0440f88fd74 100644 --- a/tools/psa/tfm/bin_utils/imgtool.py +++ b/tools/psa/tfm/bin_utils/imgtool.py @@ -19,9 +19,9 @@ import os import re import argparse -from imgtool_lib import keys -from imgtool_lib import image -from imgtool_lib import version +from .imgtool_lib import keys +from .imgtool_lib import image +from .imgtool_lib import version import sys def find_load_address(args): From 5b9741094ff2db26f39da248b791b55d92e97a54 Mon Sep 17 00:00:00 2001 From: Ari Parkkila Date: Thu, 3 Oct 2019 01:12:14 -0700 Subject: [PATCH 187/227] Cellular: Fix CellularStateMachine to not loop on power state --- features/cellular/framework/device/CellularStateMachine.cpp | 4 ---- 1 file changed, 4 deletions(-) diff --git a/features/cellular/framework/device/CellularStateMachine.cpp b/features/cellular/framework/device/CellularStateMachine.cpp index ca1c09b18a8..9e32292073a 100644 --- a/features/cellular/framework/device/CellularStateMachine.cpp +++ b/features/cellular/framework/device/CellularStateMachine.cpp @@ -371,10 +371,6 @@ void CellularStateMachine::state_device_ready() _status = 0; enter_to_state(STATE_SIM_PIN); } - } else { - _status = 0; - _is_retry = true; - enter_to_state(STATE_INIT); } } if (_cb_data.error != NSAPI_ERROR_OK) { From d12a051068581a5363644c4ce06da39cd7a6dae0 Mon Sep 17 00:00:00 2001 From: mudassar-ublox Date: Thu, 3 Oct 2019 12:22:17 +0500 Subject: [PATCH 188/227] setting timeout before send command --- .../framework/targets/UBLOX/AT/UBLOX_AT_CellularStack.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/features/cellular/framework/targets/UBLOX/AT/UBLOX_AT_CellularStack.cpp b/features/cellular/framework/targets/UBLOX/AT/UBLOX_AT_CellularStack.cpp index 819eef3df86..4a432e290ab 100644 --- a/features/cellular/framework/targets/UBLOX/AT/UBLOX_AT_CellularStack.cpp +++ b/features/cellular/framework/targets/UBLOX/AT/UBLOX_AT_CellularStack.cpp @@ -447,13 +447,14 @@ nsapi_error_t UBLOX_AT_CellularStack::gethostbyname(const char *host, SocketAddr if (address->set_ip_address(host)) { err = NSAPI_ERROR_OK; } else { - // This interrogation can sometimes take longer than the usual 8 seconds - _at.cmd_start_stop("+UDNSRN", "=0,", "%s", host); #ifdef TARGET_UBLOX_C030_R41XM _at.set_at_timeout(70000); #else _at.set_at_timeout(120000); #endif + // This interrogation can sometimes take longer than the usual 8 seconds + _at.cmd_start_stop("+UDNSRN", "=0,", "%s", host); + _at.resp_start("+UDNSRN:"); if (_at.info_resp()) { _at.read_string(ipAddress, sizeof(ipAddress)); From d41802fb7591aeb30370a7085d2fdd50dbf02043 Mon Sep 17 00:00:00 2001 From: Kyle Kearney Date: Wed, 18 Sep 2019 17:02:27 -0700 Subject: [PATCH 189/227] Simplicy QSPIF target overrides for PSoC6 All current PSoC 6 targets support the same QSPI frequency and minimum program size. So specify a single entry rather than duplicating for each device. --- .../blockdevice/COMPONENT_QSPIF/mbed_lib.json | 18 +----------------- 1 file changed, 1 insertion(+), 17 deletions(-) diff --git a/components/storage/blockdevice/COMPONENT_QSPIF/mbed_lib.json b/components/storage/blockdevice/COMPONENT_QSPIF/mbed_lib.json index b99c24707a7..1f2bc1c3204 100644 --- a/components/storage/blockdevice/COMPONENT_QSPIF/mbed_lib.json +++ b/components/storage/blockdevice/COMPONENT_QSPIF/mbed_lib.json @@ -39,23 +39,7 @@ "QSPI_MIN_READ_SIZE": "4", "QSPI_MIN_PROG_SIZE": "4" }, - "CY8CKIT_062S2_43012": { - "QSPI_FREQ": "50000000", - "QSPI_MIN_PROG_SIZE": "512" - }, - "CY8CPROTO_062_4343W": { - "QSPI_FREQ": "50000000", - "QSPI_MIN_PROG_SIZE": "512" - }, - "CY8CKIT_062_WIFI_BT": { - "QSPI_FREQ": "50000000", - "QSPI_MIN_PROG_SIZE": "512" - }, - "CY8CKIT_062_BLE": { - "QSPI_FREQ": "50000000", - "QSPI_MIN_PROG_SIZE": "512" - }, - "CYW943012P6EVB_01": { + "MCU_PSOC6": { "QSPI_FREQ": "50000000", "QSPI_MIN_PROG_SIZE": "512" } From d111aff98b949a9e7d2aa1d1928dcae885d02041 Mon Sep 17 00:00:00 2001 From: Chun-Chieh Li Date: Tue, 11 Jun 2019 17:21:28 +0800 Subject: [PATCH 190/227] Support Nuvoton's NUMAKER_M252KG target --- .../TARGET_M251/PeripheralNames.h | 127 + .../TARGET_M251/PeripheralPins.c | 294 ++ .../TARGET_M251/PeripheralPins.h | 68 + targets/TARGET_NUVOTON/TARGET_M251/PinNames.h | 136 + .../TARGET_NUVOTON/TARGET_M251/PortNames.h | 38 + .../TARGET_NUVOTON/TARGET_M251/analogin_api.c | 121 + .../TARGET_M251/analogout_api.c | 183 ++ .../TARGET_M251/crypto/crypto-misc.cpp | 274 ++ .../TARGET_M251/crypto/crypto-misc.h | 104 + targets/TARGET_NUVOTON/TARGET_M251/device.h | 26 + .../TARGET_NUVOTON/TARGET_M251/device/M251.h | 647 ++++ .../TARGET_M251/device/Reg/NuMicro.h | 15 + .../TARGET_M251/device/Reg/acmp_reg.h | 234 ++ .../TARGET_M251/device/Reg/bpwm_reg.h | 1742 +++++++++++ .../TARGET_M251/device/Reg/clk_reg.h | 1133 +++++++ .../TARGET_M251/device/Reg/crc_reg.h | 148 + .../TARGET_M251/device/Reg/crypto_reg.h | 450 +++ .../TARGET_M251/device/Reg/dac_reg.h | 203 ++ .../TARGET_M251/device/Reg/eadc_reg.h | 837 ++++++ .../TARGET_M251/device/Reg/ebi_reg.h | 286 ++ .../TARGET_M251/device/Reg/fmc_reg.h | 434 +++ .../TARGET_M251/device/Reg/gpio_reg.h | 927 ++++++ .../TARGET_M251/device/Reg/i2c_reg.h | 706 +++++ .../TARGET_M251/device/Reg/opa_reg.h | 136 + .../TARGET_M251/device/Reg/pdma_reg.h | 722 +++++ .../TARGET_M251/device/Reg/psio_reg.h | 1450 +++++++++ .../TARGET_M251/device/Reg/pwm_reg.h | 2657 +++++++++++++++++ .../TARGET_M251/device/Reg/qspi_reg.h | 591 ++++ .../TARGET_M251/device/Reg/rtc_reg.h | 775 +++++ .../TARGET_M251/device/Reg/sc_reg.h | 973 ++++++ .../TARGET_M251/device/Reg/spi_reg.h | 838 ++++++ .../TARGET_M251/device/Reg/sys_reg.h | 2442 +++++++++++++++ .../TARGET_M251/device/Reg/timer_reg.h | 673 +++++ .../TARGET_M251/device/Reg/uart_reg.h | 1292 ++++++++ .../TARGET_M251/device/Reg/ui2c_reg.h | 576 ++++ .../TARGET_M251/device/Reg/usbd_reg.h | 650 ++++ .../TARGET_M251/device/Reg/uspi_reg.h | 676 +++++ .../TARGET_M251/device/Reg/uuart_reg.h | 675 +++++ .../TARGET_M251/device/Reg/wdt_reg.h | 169 ++ .../TARGET_M251/device/Reg/wwdt_reg.h | 146 + .../device/StdDriver/inc/m251_acmp.h | 414 +++ .../device/StdDriver/inc/m251_bpwm.h | 376 +++ .../device/StdDriver/inc/m251_clk.h | 627 ++++ .../device/StdDriver/inc/m251_crc.h | 109 + .../device/StdDriver/inc/m251_crypto.h | 188 ++ .../device/StdDriver/inc/m251_dac.h | 249 ++ .../device/StdDriver/inc/m251_eadc.h | 723 +++++ .../device/StdDriver/inc/m251_ebi.h | 350 +++ .../device/StdDriver/inc/m251_fmc.h | 697 +++++ .../device/StdDriver/inc/m251_gpio.h | 473 +++ .../device/StdDriver/inc/m251_i2c.h | 488 +++ .../device/StdDriver/inc/m251_opa.h | 201 ++ .../device/StdDriver/inc/m251_pdma.h | 353 +++ .../device/StdDriver/inc/m251_psio.h | 1190 ++++++++ .../device/StdDriver/inc/m251_pwm.h | 515 ++++ .../device/StdDriver/inc/m251_qspi.h | 389 +++ .../device/StdDriver/inc/m251_rtc.h | 377 +++ .../device/StdDriver/inc/m251_sc.h | 383 +++ .../device/StdDriver/inc/m251_scuart.h | 266 ++ .../device/StdDriver/inc/m251_spi.h | 595 ++++ .../device/StdDriver/inc/m251_sys.h | 1231 ++++++++ .../device/StdDriver/inc/m251_timer.h | 529 ++++ .../device/StdDriver/inc/m251_timer_pwm.h | 606 ++++ .../device/StdDriver/inc/m251_uart.h | 500 ++++ .../device/StdDriver/inc/m251_usbd.h | 700 +++++ .../device/StdDriver/inc/m251_usci_i2c.h | 331 ++ .../device/StdDriver/inc/m251_usci_spi.h | 410 +++ .../device/StdDriver/inc/m251_usci_uart.h | 490 +++ .../device/StdDriver/inc/m251_wdt.h | 222 ++ .../device/StdDriver/inc/m251_wwdt.h | 157 + .../device/StdDriver/src/m251_acmp.c | 73 + .../device/StdDriver/src/m251_bpwm.c | 748 +++++ .../device/StdDriver/src/m251_clk.c | 1185 ++++++++ .../device/StdDriver/src/m251_crc.c | 97 + .../device/StdDriver/src/m251_crypto.c | 229 ++ .../device/StdDriver/src/m251_dac.c | 87 + .../device/StdDriver/src/m251_eadc.c | 152 + .../device/StdDriver/src/m251_ebi.c | 194 ++ .../device/StdDriver/src/m251_fmc.c | 520 ++++ .../device/StdDriver/src/m251_gpio.c | 163 + .../device/StdDriver/src/m251_i2c.c | 1594 ++++++++++ .../device/StdDriver/src/m251_pdma.c | 423 +++ .../device/StdDriver/src/m251_pwm.c | 1079 +++++++ .../device/StdDriver/src/m251_qspi.c | 812 +++++ .../device/StdDriver/src/m251_rtc.c | 893 ++++++ .../device/StdDriver/src/m251_sc.c | 463 +++ .../device/StdDriver/src/m251_scuart.c | 239 ++ .../device/StdDriver/src/m251_spi.c | 1141 +++++++ .../device/StdDriver/src/m251_sys.c | 221 ++ .../device/StdDriver/src/m251_timer.c | 413 +++ .../device/StdDriver/src/m251_timer_pwm.c | 159 + .../device/StdDriver/src/m251_uart.c | 659 ++++ .../device/StdDriver/src/m251_usbd.c | 784 +++++ .../device/StdDriver/src/m251_usci_i2c.c | 1688 +++++++++++ .../device/StdDriver/src/m251_usci_spi.c | 708 +++++ .../device/StdDriver/src/m251_usci_uart.c | 748 +++++ .../device/StdDriver/src/m251_wdt.c | 69 + .../device/StdDriver/src/m251_wwdt.c | 68 + .../device/TOOLCHAIN_ARMC6/M251.sct | 75 + .../device/TOOLCHAIN_GCC_ARM/M251.ld | 222 ++ .../TARGET_M251/device/TOOLCHAIN_IAR/M251.icf | 80 + .../TARGET_NUVOTON/TARGET_M251/device/cmsis.h | 35 + .../TARGET_M251/device/cmsis_nvic.h | 37 + .../TARGET_M251/device/startup_M251.c | 342 +++ .../TARGET_M251/device/system_M251.c | 154 + .../TARGET_M251/device/system_M251.h | 75 + targets/TARGET_NUVOTON/TARGET_M251/dma.h | 43 + targets/TARGET_NUVOTON/TARGET_M251/dma_api.c | 172 ++ .../TARGET_NUVOTON/TARGET_M251/flash_api.c | 115 + targets/TARGET_NUVOTON/TARGET_M251/gpio_api.c | 144 + .../TARGET_NUVOTON/TARGET_M251/gpio_irq_api.c | 256 ++ .../TARGET_NUVOTON/TARGET_M251/gpio_object.h | 61 + targets/TARGET_NUVOTON/TARGET_M251/i2c_api.c | 927 ++++++ .../TARGET_NUVOTON/TARGET_M251/lp_ticker.c | 224 ++ .../TARGET_M251/mbed_overrides.c | 90 + targets/TARGET_NUVOTON/TARGET_M251/objects.h | 130 + targets/TARGET_NUVOTON/TARGET_M251/pinmap.c | 84 + targets/TARGET_NUVOTON/TARGET_M251/port_api.c | 101 + .../TARGET_NUVOTON/TARGET_M251/pwmout_api.c | 201 ++ targets/TARGET_NUVOTON/TARGET_M251/rtc_api.c | 215 ++ .../TARGET_NUVOTON/TARGET_M251/serial_api.c | 1153 +++++++ targets/TARGET_NUVOTON/TARGET_M251/sleep.c | 59 + targets/TARGET_NUVOTON/TARGET_M251/spi_api.c | 843 ++++++ targets/TARGET_NUVOTON/TARGET_M251/trng_api.c | 90 + .../TARGET_NUVOTON/TARGET_M251/us_ticker.c | 180 ++ targets/targets.json | 75 + 126 files changed, 60505 insertions(+) create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/PeripheralNames.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/PeripheralPins.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/PeripheralPins.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/PinNames.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/PortNames.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/analogin_api.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/analogout_api.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/crypto/crypto-misc.cpp create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/crypto/crypto-misc.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/M251.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/Reg/NuMicro.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/Reg/acmp_reg.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/Reg/bpwm_reg.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/Reg/clk_reg.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/Reg/crc_reg.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/Reg/crypto_reg.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/Reg/dac_reg.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/Reg/eadc_reg.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/Reg/ebi_reg.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/Reg/fmc_reg.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/Reg/gpio_reg.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/Reg/i2c_reg.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/Reg/opa_reg.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/Reg/pdma_reg.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/Reg/psio_reg.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/Reg/pwm_reg.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/Reg/qspi_reg.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/Reg/rtc_reg.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/Reg/sc_reg.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/Reg/spi_reg.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/Reg/sys_reg.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/Reg/timer_reg.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/Reg/uart_reg.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/Reg/ui2c_reg.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/Reg/usbd_reg.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/Reg/uspi_reg.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/Reg/uuart_reg.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/Reg/wdt_reg.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/Reg/wwdt_reg.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_acmp.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_bpwm.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_clk.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_crc.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_crypto.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_dac.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_eadc.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_ebi.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_fmc.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_gpio.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_i2c.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_opa.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_pdma.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_psio.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_pwm.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_qspi.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_rtc.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_sc.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_scuart.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_spi.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_sys.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_timer.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_timer_pwm.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_uart.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_usbd.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_usci_i2c.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_usci_spi.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_usci_uart.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_wdt.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_wwdt.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_acmp.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_bpwm.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_clk.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_crc.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_crypto.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_dac.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_eadc.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_ebi.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_fmc.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_gpio.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_i2c.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_pdma.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_pwm.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_qspi.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_rtc.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_sc.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_scuart.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_spi.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_sys.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_timer.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_timer_pwm.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_uart.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_usbd.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_usci_i2c.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_usci_spi.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_usci_uart.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_wdt.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_wwdt.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/TOOLCHAIN_ARMC6/M251.sct create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/TOOLCHAIN_GCC_ARM/M251.ld create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/TOOLCHAIN_IAR/M251.icf create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/cmsis.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/cmsis_nvic.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/startup_M251.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/system_M251.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/device/system_M251.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/dma.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/dma_api.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/flash_api.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/gpio_api.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/gpio_irq_api.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/gpio_object.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/i2c_api.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/lp_ticker.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/mbed_overrides.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/objects.h create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/pinmap.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/port_api.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/pwmout_api.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/rtc_api.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/serial_api.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/sleep.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/spi_api.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/trng_api.c create mode 100644 targets/TARGET_NUVOTON/TARGET_M251/us_ticker.c diff --git a/targets/TARGET_NUVOTON/TARGET_M251/PeripheralNames.h b/targets/TARGET_NUVOTON/TARGET_M251/PeripheralNames.h new file mode 100644 index 00000000000..fc5bda40971 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/PeripheralNames.h @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2019, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* NOTE: Check all module base addresses (XXX_BASE in BSP) for free bit fields to define module name + * which encodes module base address and module index/subindex. */ +#define NU_MODSUBINDEX_Pos 0 +#define NU_MODSUBINDEX_Msk (0x1Ful << NU_MODSUBINDEX_Pos) +#define NU_MODINDEX_Pos 20 +#define NU_MODINDEX_Msk (0xFul << NU_MODINDEX_Pos) + +#define NU_MODNAME(MODBASE, INDEX, SUBINDEX) ((MODBASE) | ((INDEX) << NU_MODINDEX_Pos) | ((SUBINDEX) << NU_MODSUBINDEX_Pos)) +#define NU_MODBASE(MODNAME) ((MODNAME) & ~(NU_MODINDEX_Msk | NU_MODSUBINDEX_Msk)) +#define NU_MODINDEX(MODNAME) (((MODNAME) & NU_MODINDEX_Msk) >> NU_MODINDEX_Pos) +#define NU_MODSUBINDEX(MODNAME) (((MODNAME) & NU_MODSUBINDEX_Msk) >> NU_MODSUBINDEX_Pos) + +#if 0 +typedef enum { + GPIO_A = (int) NU_MODNAME(GPIOA_BASE, 0, 0), + GPIO_B = (int) NU_MODNAME(GPIOB_BASE, 1, 0), + GPIO_C = (int) NU_MODNAME(GPIOC_BASE, 2, 0), + GPIO_D = (int) NU_MODNAME(GPIOD_BASE, 3, 0), + GPIO_E = (int) NU_MODNAME(GPIOE_BASE, 4, 0), + GPIO_F = (int) NU_MODNAME(GPIOF_BASE, 5, 0) +} GPIOName; +#endif + +typedef enum { + ADC_0_0 = (int) NU_MODNAME(EADC_BASE, 0, 0), + ADC_0_1 = (int) NU_MODNAME(EADC_BASE, 0, 1), + ADC_0_2 = (int) NU_MODNAME(EADC_BASE, 0, 2), + ADC_0_3 = (int) NU_MODNAME(EADC_BASE, 0, 3), + ADC_0_4 = (int) NU_MODNAME(EADC_BASE, 0, 4), + ADC_0_5 = (int) NU_MODNAME(EADC_BASE, 0, 5), + ADC_0_6 = (int) NU_MODNAME(EADC_BASE, 0, 6), + ADC_0_7 = (int) NU_MODNAME(EADC_BASE, 0, 7), + ADC_0_8 = (int) NU_MODNAME(EADC_BASE, 0, 8), + ADC_0_9 = (int) NU_MODNAME(EADC_BASE, 0, 9), + ADC_0_10 = (int) NU_MODNAME(EADC_BASE, 0, 10), + ADC_0_11 = (int) NU_MODNAME(EADC_BASE, 0, 11), + ADC_0_12 = (int) NU_MODNAME(EADC_BASE, 0, 12), + ADC_0_13 = (int) NU_MODNAME(EADC_BASE, 0, 13), + ADC_0_14 = (int) NU_MODNAME(EADC_BASE, 0, 14), + ADC_0_15 = (int) NU_MODNAME(EADC_BASE, 0, 15) +} ADCName; + +typedef enum { + DAC_0_0 = (int) NU_MODNAME(DAC_BASE, 0, 0) +} DACName; + +typedef enum { + UART_0 = (int) NU_MODNAME(UART0_BASE, 0, 0), + UART_1 = (int) NU_MODNAME(UART1_BASE, 1, 0), + UART_2 = (int) NU_MODNAME(UART2_BASE, 2, 0), + + /* NOTE: board-specific */ + STDIO_UART = UART_0 +} UARTName; + +typedef enum { + SPI_0 = (int) NU_MODNAME(SPI0_BASE, 0, 0) +} SPIName; + +typedef enum { + I2C_0 = (int) NU_MODNAME(I2C0_BASE, 0, 0), + I2C_1 = (int) NU_MODNAME(I2C1_BASE, 1, 0) +} I2CName; + +typedef enum { + PWM_0_0 = (int) NU_MODNAME(PWM0_BASE, 0, 0), + PWM_0_1 = (int) NU_MODNAME(PWM0_BASE, 0, 1), + PWM_0_2 = (int) NU_MODNAME(PWM0_BASE, 0, 2), + PWM_0_3 = (int) NU_MODNAME(PWM0_BASE, 0, 3), + PWM_0_4 = (int) NU_MODNAME(PWM0_BASE, 0, 4), + PWM_0_5 = (int) NU_MODNAME(PWM0_BASE, 0, 5), + + PWM_1_0 = (int) NU_MODNAME(PWM1_BASE, 1, 0), + PWM_1_1 = (int) NU_MODNAME(PWM1_BASE, 1, 1), + PWM_1_2 = (int) NU_MODNAME(PWM1_BASE, 1, 2), + PWM_1_3 = (int) NU_MODNAME(PWM1_BASE, 1, 3), + PWM_1_4 = (int) NU_MODNAME(PWM1_BASE, 1, 4), + PWM_1_5 = (int) NU_MODNAME(PWM1_BASE, 1, 5) +} PWMName; + +typedef enum { + TIMER_0 = (int) NU_MODNAME(TIMER01_BASE, 0, 0), + TIMER_1 = (int) NU_MODNAME(TIMER01_BASE + 0x100UL, 1, 0), + TIMER_2 = (int) NU_MODNAME(TIMER23_BASE, 2, 0), + TIMER_3 = (int) NU_MODNAME(TIMER23_BASE + 0x100UL, 3, 0) +} TIMERName; + +typedef enum { + RTC_0 = (int) NU_MODNAME(RTC_BASE, 0, 0) +} RTCName; + +typedef enum { + DMA_0 = (int) NU_MODNAME(PDMA_BASE, 0, 0) +} DMAName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M251/PeripheralPins.c b/targets/TARGET_NUVOTON/TARGET_M251/PeripheralPins.c new file mode 100644 index 00000000000..b802efdaf69 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/PeripheralPins.c @@ -0,0 +1,294 @@ +/* + * Copyright (c) 2019, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralPins.h" + +//*** ADC *** + +const PinMap PinMap_ADC[] = { + {PB_0, ADC_0_0, SYS_GPB_MFPL_PB0MFP_EADC0_CH0}, + {PB_1, ADC_0_1, SYS_GPB_MFPL_PB1MFP_EADC0_CH1}, + {PB_2, ADC_0_2, SYS_GPB_MFPL_PB2MFP_EADC0_CH2}, + {PB_3, ADC_0_3, SYS_GPB_MFPL_PB3MFP_EADC0_CH3}, + {PB_4, ADC_0_4, SYS_GPB_MFPL_PB4MFP_EADC0_CH4}, + {PB_5, ADC_0_5, SYS_GPB_MFPL_PB5MFP_EADC0_CH5}, + {PB_6, ADC_0_6, SYS_GPB_MFPL_PB6MFP_EADC0_CH6}, + {PB_7, ADC_0_7, SYS_GPB_MFPL_PB7MFP_EADC0_CH7}, + {PB_8, ADC_0_8, SYS_GPB_MFPH_PB8MFP_EADC0_CH8}, + {PB_9, ADC_0_9, SYS_GPB_MFPH_PB9MFP_EADC0_CH9}, + {PB_10, ADC_0_10, SYS_GPB_MFPH_PB10MFP_EADC0_CH10}, + {PB_11, ADC_0_11, SYS_GPB_MFPH_PB11MFP_EADC0_CH11}, + {PB_12, ADC_0_12, SYS_GPB_MFPH_PB12MFP_EADC0_CH12}, + {PB_13, ADC_0_13, SYS_GPB_MFPH_PB13MFP_EADC0_CH13}, + {PB_14, ADC_0_14, SYS_GPB_MFPH_PB14MFP_EADC0_CH14}, + {PB_15, ADC_0_15, SYS_GPB_MFPH_PB15MFP_EADC0_CH15}, + + {NC, NC, 0} +}; + +//*** DAC *** + +const PinMap PinMap_DAC[] = { + {PB_12, DAC_0_0, SYS_GPB_MFPH_PB12MFP_DAC0_OUT}, + + {NC, NC, 0} +}; + +//*** I2C *** + +const PinMap PinMap_I2C_SDA[] = { + {PA_2, I2C_1, SYS_GPA_MFPL_PA2MFP_I2C1_SDA}, + {PA_4, I2C_0, SYS_GPA_MFPL_PA4MFP_I2C0_SDA}, + {PA_6, I2C_1, SYS_GPA_MFPL_PA6MFP_I2C1_SDA}, + {PA_13, I2C_1, SYS_GPA_MFPH_PA13MFP_I2C1_SDA}, + {PB_0, I2C_1, SYS_GPB_MFPL_PB0MFP_I2C1_SDA}, + {PB_2, I2C_1, SYS_GPB_MFPL_PB2MFP_I2C1_SDA}, + {PB_4, I2C_0, SYS_GPB_MFPL_PB4MFP_I2C0_SDA}, + {PB_10, I2C_1, SYS_GPB_MFPH_PB10MFP_I2C1_SDA}, + {PC_0, I2C_0, SYS_GPC_MFPL_PC0MFP_I2C0_SDA}, + {PC_4, I2C_1, SYS_GPC_MFPL_PC4MFP_I2C1_SDA}, + {PC_8, I2C_0, SYS_GPC_MFPH_PC8MFP_I2C0_SDA}, + {PC_11, I2C_0, SYS_GPC_MFPH_PC11MFP_I2C0_SDA}, + {PD_4, I2C_1, SYS_GPD_MFPL_PD4MFP_I2C1_SDA}, + {PD_6, I2C_0, SYS_GPD_MFPL_PD6MFP_I2C0_SDA}, + {PE_0, I2C_1, SYS_GPE_MFPL_PE0MFP_I2C1_SDA}, + {PF_1, I2C_1, SYS_GPF_MFPL_PF1MFP_I2C1_SDA}, + {PF_2, I2C_0, SYS_GPF_MFPL_PF2MFP_I2C0_SDA}, + + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PA_3, I2C_1, SYS_GPA_MFPL_PA3MFP_I2C1_SCL}, + {PA_5, I2C_0, SYS_GPA_MFPL_PA5MFP_I2C0_SCL}, + {PA_7, I2C_1, SYS_GPA_MFPL_PA7MFP_I2C1_SCL}, + {PA_12, I2C_1, SYS_GPA_MFPH_PA12MFP_I2C1_SCL}, + {PB_1, I2C_1, SYS_GPB_MFPL_PB1MFP_I2C1_SCL}, + {PB_3, I2C_1, SYS_GPB_MFPL_PB3MFP_I2C1_SCL}, + {PB_5, I2C_0, SYS_GPB_MFPL_PB5MFP_I2C0_SCL}, + {PB_11, I2C_1, SYS_GPB_MFPH_PB11MFP_I2C1_SCL}, + {PC_1, I2C_0, SYS_GPC_MFPL_PC1MFP_I2C0_SCL}, + {PC_5, I2C_1, SYS_GPC_MFPL_PC5MFP_I2C1_SCL}, + {PC_12, I2C_0, SYS_GPC_MFPH_PC12MFP_I2C0_SCL}, + {PD_5, I2C_1, SYS_GPD_MFPL_PD5MFP_I2C1_SCL}, + {PD_7, I2C_0, SYS_GPD_MFPL_PD7MFP_I2C0_SCL}, + {PE_1, I2C_1, SYS_GPE_MFPL_PE1MFP_I2C1_SCL}, + {PE_13, I2C_0, SYS_GPE_MFPH_PE13MFP_I2C0_SCL}, + {PF_0, I2C_1, SYS_GPF_MFPL_PF0MFP_I2C1_SCL}, + {PF_3, I2C_0, SYS_GPF_MFPL_PF3MFP_I2C0_SCL}, + + {NC, NC, 0} +}; + +//*** PWM *** + +const PinMap PinMap_PWM[] = { + {PA_0, PWM_0_5, SYS_GPA_MFPL_PA0MFP_PWM0_CH5}, + {PA_1, PWM_0_4, SYS_GPA_MFPL_PA1MFP_PWM0_CH4}, + {PA_2, PWM_0_3, SYS_GPA_MFPL_PA2MFP_PWM0_CH3}, + {PA_3, PWM_0_2, SYS_GPA_MFPL_PA3MFP_PWM0_CH2}, + {PA_4, PWM_0_1, SYS_GPA_MFPL_PA4MFP_PWM0_CH1}, + {PA_5, PWM_0_0, SYS_GPA_MFPL_PA5MFP_PWM0_CH0}, + {PA_6, PWM_1_5, SYS_GPA_MFPL_PA6MFP_PWM1_CH5}, + {PA_7, PWM_1_4, SYS_GPA_MFPL_PA7MFP_PWM1_CH4}, + {PB_0, PWM_0_5, SYS_GPB_MFPL_PB0MFP_PWM0_CH5}, + {NU_PINNAME_BIND(PB_0, PWM_0_5), PWM_0_5, SYS_GPB_MFPL_PB0MFP_PWM0_CH5}, + {PB_0, PWM_1_5, SYS_GPB_MFPL_PB0MFP_PWM1_CH5}, + {NU_PINNAME_BIND(PB_0, PWM_1_5), PWM_1_5, SYS_GPB_MFPL_PB0MFP_PWM1_CH5}, + {PB_1, PWM_0_4, SYS_GPB_MFPL_PB1MFP_PWM0_CH4}, + {NU_PINNAME_BIND(PB_1, PWM_0_4), PWM_0_4, SYS_GPB_MFPL_PB1MFP_PWM0_CH4}, + {PB_1, PWM_1_4, SYS_GPB_MFPL_PB1MFP_PWM1_CH4}, + {NU_PINNAME_BIND(PB_1, PWM_1_4), PWM_1_4, SYS_GPB_MFPL_PB1MFP_PWM1_CH4}, + {PB_2, PWM_0_3, SYS_GPB_MFPL_PB2MFP_PWM0_CH3}, + {PB_3, PWM_0_2, SYS_GPB_MFPL_PB3MFP_PWM0_CH2}, + {PB_4, PWM_0_1, SYS_GPB_MFPL_PB4MFP_PWM0_CH1}, + {PB_5, PWM_0_0, SYS_GPB_MFPL_PB5MFP_PWM0_CH0}, + {PB_6, PWM_1_5, SYS_GPB_MFPL_PB6MFP_PWM1_CH5}, + {PB_7, PWM_1_4, SYS_GPB_MFPL_PB7MFP_PWM1_CH4}, + {PB_12, PWM_1_3, SYS_GPB_MFPH_PB12MFP_PWM1_CH3}, + {PB_13, PWM_1_2, SYS_GPB_MFPH_PB13MFP_PWM1_CH2}, + {PB_14, PWM_1_1, SYS_GPB_MFPH_PB14MFP_PWM1_CH1}, + {PB_15, PWM_1_0, SYS_GPB_MFPH_PB15MFP_PWM1_CH0}, + {PC_0, PWM_1_5, SYS_GPC_MFPL_PC0MFP_PWM1_CH5}, + {PC_1, PWM_1_4, SYS_GPC_MFPL_PC1MFP_PWM1_CH4}, + {PC_2, PWM_1_3, SYS_GPC_MFPL_PC2MFP_PWM1_CH3}, + {PC_3, PWM_1_2, SYS_GPC_MFPL_PC3MFP_PWM1_CH2}, + {PC_4, PWM_1_1, SYS_GPC_MFPL_PC4MFP_PWM1_CH1}, + {PC_5, PWM_1_0, SYS_GPC_MFPL_PC5MFP_PWM1_CH0}, + {PC_6, PWM_1_3, SYS_GPC_MFPL_PC6MFP_PWM1_CH3}, + {PC_7, PWM_1_2, SYS_GPC_MFPL_PC7MFP_PWM1_CH2}, + {PC_8, PWM_1_1, SYS_GPC_MFPH_PC8MFP_PWM1_CH1}, + {PC_9, PWM_1_3, SYS_GPC_MFPH_PC9MFP_PWM1_CH3}, + {PC_10, PWM_1_2, SYS_GPC_MFPH_PC10MFP_PWM1_CH2}, + {PC_11, PWM_1_1, SYS_GPC_MFPH_PC11MFP_PWM1_CH1}, + {PC_12, PWM_1_0, SYS_GPC_MFPH_PC12MFP_PWM1_CH0}, + {PD_15, PWM_0_5, SYS_GPD_MFPH_PD15MFP_PWM0_CH5}, + {PE_2, PWM_0_5, SYS_GPE_MFPL_PE2MFP_PWM0_CH5}, + {PE_3, PWM_0_4, SYS_GPE_MFPL_PE3MFP_PWM0_CH4}, + {PE_4, PWM_0_3, SYS_GPE_MFPL_PE4MFP_PWM0_CH3}, + {PE_5, PWM_0_2, SYS_GPE_MFPL_PE5MFP_PWM0_CH2}, + {PE_6, PWM_0_1, SYS_GPE_MFPL_PE6MFP_PWM0_CH1}, + {PE_7, PWM_0_0, SYS_GPE_MFPL_PE7MFP_PWM0_CH0}, + {PE_8, PWM_0_0, SYS_GPE_MFPH_PE8MFP_PWM0_CH0}, + {PE_9, PWM_0_1, SYS_GPE_MFPH_PE9MFP_PWM0_CH1}, + {PE_10, PWM_0_2, SYS_GPE_MFPH_PE10MFP_PWM0_CH2}, + {PE_11, PWM_0_3, SYS_GPE_MFPH_PE11MFP_PWM0_CH3}, + {PE_12, PWM_0_4, SYS_GPE_MFPH_PE12MFP_PWM0_CH4}, + {PE_13, PWM_0_5, SYS_GPE_MFPH_PE13MFP_PWM0_CH5}, + {NU_PINNAME_BIND(PE_13, PWM_0_5), PWM_0_5, SYS_GPE_MFPH_PE13MFP_PWM0_CH5}, + {PE_13, PWM_1_0, SYS_GPE_MFPH_PE13MFP_PWM1_CH0}, + {NU_PINNAME_BIND(PE_13, PWM_1_0), PWM_1_0, SYS_GPE_MFPH_PE13MFP_PWM1_CH0}, + {PF_4, PWM_0_1, SYS_GPF_MFPL_PF4MFP_PWM0_CH1}, + {PF_5, PWM_0_0, SYS_GPF_MFPL_PF5MFP_PWM0_CH0}, + {PF_14, PWM_0_4, SYS_GPF_MFPH_PF14MFP_PWM0_CH4}, + + {NC, NC, 0} +}; + +//*** SERIAL *** + +const PinMap PinMap_UART_TX[] = { + {PA_1, UART_0, SYS_GPA_MFPL_PA1MFP_UART0_TXD}, + {PA_3, UART_1, SYS_GPA_MFPL_PA3MFP_UART1_TXD}, + {PA_5, UART_0, SYS_GPA_MFPL_PA5MFP_UART0_TXD}, + {PA_7, UART_0, SYS_GPA_MFPL_PA7MFP_UART0_TXD}, + {PA_9, UART_1, SYS_GPA_MFPH_PA9MFP_UART1_TXD}, + {PA_14, UART_0, SYS_GPA_MFPH_PA14MFP_UART0_TXD}, + {PB_1, UART_2, SYS_GPB_MFPL_PB1MFP_UART2_TXD}, + {PB_3, UART_1, SYS_GPB_MFPL_PB3MFP_UART1_TXD}, + {PB_5, UART_2, SYS_GPB_MFPL_PB5MFP_UART2_TXD}, + {PB_7, UART_1, SYS_GPB_MFPL_PB7MFP_UART1_TXD}, + {PB_9, UART_0, SYS_GPB_MFPH_PB9MFP_UART0_TXD}, + {PB_13, UART_0, SYS_GPB_MFPH_PB13MFP_UART0_TXD}, + {PC_1, UART_2, SYS_GPC_MFPL_PC1MFP_UART2_TXD}, + {PC_5, UART_2, SYS_GPC_MFPL_PC5MFP_UART2_TXD}, + {PC_12, UART_0, SYS_GPC_MFPH_PC12MFP_UART0_TXD}, + {PD_3, UART_0, SYS_GPD_MFPL_PD3MFP_UART0_TXD}, + {PD_7, UART_1, SYS_GPD_MFPL_PD7MFP_UART1_TXD}, + {PD_11, UART_1, SYS_GPD_MFPH_PD11MFP_UART1_TXD}, + {PE_8, UART_2, SYS_GPE_MFPH_PE8MFP_UART2_TXD}, + {PE_13, UART_1, SYS_GPE_MFPH_PE13MFP_UART1_TXD}, + {PE_14, UART_2, SYS_GPE_MFPH_PE14MFP_UART2_TXD}, + {PF_0, UART_0, SYS_GPF_MFPL_PF0MFP_UART0_TXD}, + {NU_PINNAME_BIND(PF_0, UART_0), UART_0, SYS_GPF_MFPL_PF0MFP_UART0_TXD}, + {PF_0, UART_1, SYS_GPF_MFPL_PF0MFP_UART1_TXD}, + {NU_PINNAME_BIND(PF_0, UART_1), UART_1, SYS_GPF_MFPL_PF0MFP_UART1_TXD}, + {PF_3, UART_0, SYS_GPF_MFPL_PF3MFP_UART0_TXD}, + {PF_4, UART_2, SYS_GPF_MFPL_PF4MFP_UART2_TXD}, + + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PA_0, UART_0, SYS_GPA_MFPL_PA0MFP_UART0_RXD}, + {PA_2, UART_1, SYS_GPA_MFPL_PA2MFP_UART1_RXD}, + {PA_4, UART_0, SYS_GPA_MFPL_PA4MFP_UART0_RXD}, + {PA_6, UART_0, SYS_GPA_MFPL_PA6MFP_UART0_RXD}, + {PA_8, UART_1, SYS_GPA_MFPH_PA8MFP_UART1_RXD}, + {PA_15, UART_0, SYS_GPA_MFPH_PA15MFP_UART0_RXD}, + {PB_0, UART_2, SYS_GPB_MFPL_PB0MFP_UART2_RXD}, + {PB_2, UART_1, SYS_GPB_MFPL_PB2MFP_UART1_RXD}, + {PB_4, UART_2, SYS_GPB_MFPL_PB4MFP_UART2_RXD}, + {PB_6, UART_1, SYS_GPB_MFPL_PB6MFP_UART1_RXD}, + {PB_8, UART_0, SYS_GPB_MFPH_PB8MFP_UART0_RXD}, + {PB_12, UART_0, SYS_GPB_MFPH_PB12MFP_UART0_RXD}, + {PC_0, UART_2, SYS_GPC_MFPL_PC0MFP_UART2_RXD}, + {PC_4, UART_2, SYS_GPC_MFPL_PC4MFP_UART2_RXD}, + {PC_8, UART_1, SYS_GPC_MFPH_PC8MFP_UART1_RXD}, + {PC_11, UART_0, SYS_GPC_MFPH_PC11MFP_UART0_RXD}, + {PD_2, UART_0, SYS_GPD_MFPL_PD2MFP_UART0_RXD}, + {PD_6, UART_1, SYS_GPD_MFPL_PD6MFP_UART1_RXD}, + {PD_10, UART_1, SYS_GPD_MFPH_PD10MFP_UART1_RXD}, + {PD_12, UART_2, SYS_GPD_MFPH_PD12MFP_UART2_RXD}, + {PE_9, UART_2, SYS_GPE_MFPH_PE9MFP_UART2_RXD}, + {PE_15, UART_2, SYS_GPE_MFPH_PE15MFP_UART2_RXD}, + {PF_1, UART_0, SYS_GPF_MFPL_PF1MFP_UART0_RXD}, + {NU_PINNAME_BIND(PF_1, UART_0), UART_0, SYS_GPF_MFPL_PF1MFP_UART0_RXD}, + {PF_1, UART_1, SYS_GPF_MFPL_PF1MFP_UART1_RXD}, + {NU_PINNAME_BIND(PF_1, UART_1), UART_1, SYS_GPF_MFPL_PF1MFP_UART1_RXD}, + {PF_2, UART_0, SYS_GPF_MFPL_PF2MFP_UART0_RXD}, + {PF_5, UART_2, SYS_GPF_MFPL_PF5MFP_UART2_RXD}, + + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RTS[] = { + {PA_0, UART_1, SYS_GPA_MFPL_PA0MFP_UART1_nRTS}, + {PA_4, UART_0, SYS_GPA_MFPL_PA4MFP_UART0_nRTS}, + {PB_8, UART_1, SYS_GPB_MFPH_PB8MFP_UART1_nRTS}, + {PB_10, UART_0, SYS_GPB_MFPH_PB10MFP_UART0_nRTS}, + {PB_14, UART_0, SYS_GPB_MFPH_PB14MFP_UART0_nRTS}, + {PC_3, UART_2, SYS_GPC_MFPL_PC3MFP_UART2_nRTS}, + {PC_6, UART_0, SYS_GPC_MFPL_PC6MFP_UART0_nRTS}, + {PD_8, UART_2, SYS_GPD_MFPH_PD8MFP_UART2_nRTS}, + {PE_12, UART_1, SYS_GPE_MFPH_PE12MFP_UART1_nRTS}, + {PF_4, UART_2, SYS_GPF_MFPL_PF4MFP_UART2_nRTS}, + + {NC, NC, 0} +}; + +const PinMap PinMap_UART_CTS[] = { + {PA_1, UART_1, SYS_GPA_MFPL_PA1MFP_UART1_nCTS}, + {PA_5, UART_0, SYS_GPA_MFPL_PA5MFP_UART0_nCTS}, + {PB_9, UART_1, SYS_GPB_MFPH_PB9MFP_UART1_nCTS}, + {PB_11, UART_0, SYS_GPB_MFPH_PB11MFP_UART0_nCTS}, + {PB_15, UART_0, SYS_GPB_MFPH_PB15MFP_UART0_nCTS}, + {PC_2, UART_2, SYS_GPC_MFPL_PC2MFP_UART2_nCTS}, + {PC_7, UART_0, SYS_GPC_MFPL_PC7MFP_UART0_nCTS}, + {PD_9, UART_2, SYS_GPD_MFPH_PD9MFP_UART2_nCTS}, + {PE_11, UART_1, SYS_GPE_MFPH_PE11MFP_UART1_nCTS}, + {PF_5, UART_2, SYS_GPF_MFPL_PF5MFP_UART2_nCTS}, + + {NC, NC, 0} +}; + +//*** SPI *** + +const PinMap PinMap_SPI_MOSI[] = { + {PA_0, SPI_0, SYS_GPA_MFPL_PA0MFP_SPI0_MOSI}, + {PB_12, SPI_0, SYS_GPB_MFPH_PB12MFP_SPI0_MOSI}, + {PD_0, SPI_0, SYS_GPD_MFPL_PD0MFP_SPI0_MOSI}, + {PF_6, SPI_0, SYS_GPF_MFPL_PF6MFP_SPI0_MOSI}, + + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PA_1, SPI_0, SYS_GPA_MFPL_PA1MFP_SPI0_MISO}, + {PB_13, SPI_0, SYS_GPB_MFPH_PB13MFP_SPI0_MISO}, + {PD_1, SPI_0, SYS_GPD_MFPL_PD1MFP_SPI0_MISO}, + {PF_7, SPI_0, SYS_GPF_MFPL_PF7MFP_SPI0_MISO}, + + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SCLK[] = { + {PA_2, SPI_0, SYS_GPA_MFPL_PA2MFP_SPI0_CLK}, + {PB_14, SPI_0, SYS_GPB_MFPH_PB14MFP_SPI0_CLK}, + {PD_2, SPI_0, SYS_GPD_MFPL_PD2MFP_SPI0_CLK}, + + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PA_3, SPI_0, SYS_GPA_MFPL_PA3MFP_SPI0_SS}, + {PB_15, SPI_0, SYS_GPB_MFPH_PB15MFP_SPI0_SS}, + {PD_3, SPI_0, SYS_GPD_MFPL_PD3MFP_SPI0_SS}, + + {NC, NC, 0} +}; diff --git a/targets/TARGET_NUVOTON/TARGET_M251/PeripheralPins.h b/targets/TARGET_NUVOTON/TARGET_M251/PeripheralPins.h new file mode 100644 index 00000000000..f26f1ccffd0 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/PeripheralPins.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2019, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +//*** GPIO *** + +extern const PinMap PinMap_GPIO[]; + +//*** ADC *** + +extern const PinMap PinMap_ADC[]; + +//*** DAC *** + +extern const PinMap PinMap_DAC[]; + +//*** I2C *** + +extern const PinMap PinMap_I2C_SDA[]; +extern const PinMap PinMap_I2C_SCL[]; + +//*** PWM *** + +extern const PinMap PinMap_PWM[]; + +//*** SERIAL *** + +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; +extern const PinMap PinMap_UART_RTS[]; +extern const PinMap PinMap_UART_CTS[]; + +//*** SPI *** + +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_SSEL[]; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M251/PinNames.h b/targets/TARGET_NUVOTON/TARGET_M251/PinNames.h new file mode 100644 index 00000000000..f7af3cf2d28 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/PinNames.h @@ -0,0 +1,136 @@ +/* + * Copyright (c) 2019, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NU_PININDEX_Pos 0 +#define NU_PININDEX_Msk (0xFFul << NU_PININDEX_Pos) +#define NU_PINPORT_Pos 8 +#define NU_PINPORT_Msk (0xFul << NU_PINPORT_Pos) +#define NU_PIN_MODINDEX_Pos 12 +#define NU_PIN_MODINDEX_Msk (0xFul << NU_PIN_MODINDEX_Pos) +#define NU_PIN_BIND_Pos 16 +#define NU_PIN_BIND_Msk (0x1ul << NU_PIN_BIND_Pos) + +#define NU_PININDEX(PINNAME) (((unsigned int)(PINNAME) & NU_PININDEX_Msk) >> NU_PININDEX_Pos) +#define NU_PINPORT(PINNAME) (((unsigned int)(PINNAME) & NU_PINPORT_Msk) >> NU_PINPORT_Pos) +#define NU_PIN_BIND(PINNAME) (((unsigned int)(PINNAME) & NU_PIN_BIND_Msk) >> NU_PIN_BIND_Pos) +#define NU_PIN_MODINDEX(PINNAME) (((unsigned int)(PINNAME) & NU_PIN_MODINDEX_Msk) >> NU_PIN_MODINDEX_Pos) +#define NU_PINNAME(PORT, PIN) ((((unsigned int) (PORT)) << (NU_PINPORT_Pos)) | (((unsigned int) (PIN)) << NU_PININDEX_Pos)) +#define NU_PINNAME_BIND(PINNAME, modname) ((PinName) NU_PINNAME_BIND_(NU_PINPORT(PINNAME), NU_PININDEX(PINNAME), modname)) +#define NU_PINNAME_BIND_(PORT, PIN, modname) ((((unsigned int)(PORT)) << NU_PINPORT_Pos) | (((unsigned int)(PIN)) << NU_PININDEX_Pos) | (NU_MODINDEX(modname) << NU_PIN_MODINDEX_Pos) | NU_PIN_BIND_Msk) + +#define NU_PORT_BASE(PORT) ((GPIO_T *)(((uint32_t) GPIOA_BASE) + 0x40 * PORT)) +#define NU_MFP_POS(pin) ((pin % 8) * 4) +#define NU_MFP_MSK(pin) (0xful << NU_MFP_POS(pin)) + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +typedef enum { + /* Input pull mode */ + PullNone = 0, + PullDown, + PullUp, + + /* I/O mode */ + InputOnly, + PushPullOutput, + OpenDrain, + QuasiBidirectional, + + /* Default input pull mode */ + PullDefault = PullUp +} PinMode; + +typedef enum { + /* Not connected */ + NC = (int)0xFFFFFFFF, + + /* Generic naming */ + PA_0 = NU_PINNAME(0, 0), PA_1, PA_2, PA_3, PA_4, PA_5, PA_6, PA_7, PA_8, PA_9, PA_10, PA_11, PA_12, PA_13, PA_14, PA_15, + PB_0 = NU_PINNAME(1, 0), PB_1, PB_2, PB_3, PB_4, PB_5, PB_6, PB_7, PB_8, PB_9, PB_10, PB_11, PB_12, PB_13, PB_14, PB_15, + PC_0 = NU_PINNAME(2, 0), PC_1, PC_2, PC_3, PC_4, PC_5, PC_6, PC_7, PC_8, PC_9, PC_10, PC_11, PC_12, PC_14 = PC_12 + 2, + PD_0 = NU_PINNAME(3, 0), PD_1, PD_2, PD_3, PD_4, PD_5, PD_6, PD_7, PD_8, PD_9, PD_10, PD_11, PD_12, PD_13, PD_15 = PD_13 + 2, + PE_0 = NU_PINNAME(4, 0), PE_1, PE_2, PE_3, PE_4, PE_5, PE_6, PE_7, PE_8, PE_9, PE_10, PE_11, PE_12, PE_13, PE_14, PE_15, + PF_0 = NU_PINNAME(5, 0), PF_1, PF_2, PF_3, PF_4, PF_5, PF_6, PF_7, PF_14 = PF_7 + 7, + + /* Arduino UNO naming */ + A0 = PB_7, + A1 = PB_6, + A2 = PB_5, + A3 = PB_4, + A4 = PB_0, + A5 = PB_1, + + D0 = PB_2, + D1 = PB_3, + D2 = PC_4, + D3 = PC_5, + D4 = PC_3, + D5 = PC_2, + D6 = PA_7, + D7 = PA_6, + D8 = PA_5, + D9 = PA_4, + D10 = PA_3, + D11 = PA_0, + D12 = PA_1, + D13 = PA_2, + D14 = PC_0, + D15 = PC_1, + + /* Other board-specific naming */ + + /* UART naming */ + USBTX = PB_13, + USBRX = PB_12, + STDIO_UART_TX = USBTX, + STDIO_UART_RX = USBRX, + SERIAL_TX = USBTX, + SERIAL_RX = USBRX, + + /* I2C naming */ + I2C_SCL = D15, + I2C_SDA = D14, + + /* LED naming */ + LED_RED = PB_14, + LED1 = LED_RED, + LED2 = LED1, // No real LED. Just for passing ATS. + LED3 = LED1, // No real LED. Just for passing ATS. + LED4 = LED1, // No real LED. Just for passing ATS. + + /* Button naming */ + +} PinName; + +#ifdef __cplusplus +} +#endif + +#endif // MBED_PINNAMES_H diff --git a/targets/TARGET_NUVOTON/TARGET_M251/PortNames.h b/targets/TARGET_NUVOTON/TARGET_M251/PortNames.h new file mode 100644 index 00000000000..26541dd0242 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/PortNames.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2019, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PortA = 0, + PortB = 1, + PortC = 2, + PortD = 3, + PortE = 4, + PortF = 5 +} PortName; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M251/analogin_api.c b/targets/TARGET_NUVOTON/TARGET_M251/analogin_api.c new file mode 100644 index 00000000000..087be9ab52c --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/analogin_api.c @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2019, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "analogin_api.h" + +#if DEVICE_ANALOGIN + +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralPins.h" +#include "nu_modutil.h" + +static uint32_t eadc_modinit_mask = 0; + +static const struct nu_modinit_s adc_modinit_tab[] = { + {ADC_0_0, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC_INT0_IRQn, NULL}, + {ADC_0_1, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC_INT0_IRQn, NULL}, + {ADC_0_2, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC_INT0_IRQn, NULL}, + {ADC_0_3, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC_INT0_IRQn, NULL}, + {ADC_0_4, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC_INT0_IRQn, NULL}, + {ADC_0_5, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC_INT0_IRQn, NULL}, + {ADC_0_6, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC_INT0_IRQn, NULL}, + {ADC_0_7, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC_INT0_IRQn, NULL}, + {ADC_0_8, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC_INT0_IRQn, NULL}, + {ADC_0_9, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC_INT0_IRQn, NULL}, + {ADC_0_10, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC_INT0_IRQn, NULL}, + {ADC_0_11, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC_INT0_IRQn, NULL}, + {ADC_0_12, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC_INT0_IRQn, NULL}, + {ADC_0_13, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC_INT0_IRQn, NULL}, + {ADC_0_14, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC_INT0_IRQn, NULL}, + {ADC_0_15, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC_INT0_IRQn, NULL}, +}; + +void analogin_init(analogin_t *obj, PinName pin) +{ + obj->adc = (ADCName) pinmap_peripheral(pin, PinMap_ADC); + MBED_ASSERT(obj->adc != (ADCName) NC); + + const struct nu_modinit_s *modinit = get_modinit(obj->adc, adc_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->adc); + + EADC_T *eadc_base = (EADC_T *) NU_MODBASE(obj->adc); + + // NOTE: All channels (identified by ADCName) share a ADC module. This reset will also affect other channels of the same ADC module. + if (! eadc_modinit_mask) { + // Reset this module if no channel enabled + SYS_ResetModule(modinit->rsetidx); + + // Select clock source + CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv); + + // Enable clock + CLK_EnableModuleClock(modinit->clkidx); + + /* Configure EADC_module to be ready to convert + * M251 doesn't support 'input mode' feature. Configure it to 0. */ + EADC_Open(eadc_base, 0); + } + + uint32_t chn = NU_MODSUBINDEX(obj->adc); + + // Wire pinout + pinmap_pinout(pin, PinMap_ADC); + + // Configure the sample module Nmod for analog input channel Nch and software trigger source + EADC_ConfigSampleModule(eadc_base, chn, EADC_SOFTWARE_TRIGGER, chn); + + /* Extend sampling time (in EADC clocks) + * + * Some targets like NUMAKER_M252KG may fail to pass CI Test Shield test + * without extending sampling time. + */ + EADC_SetExtendSampleTime(eadc_base, chn, 10); + + eadc_modinit_mask |= 1 << chn; +} + +uint16_t analogin_read_u16(analogin_t *obj) +{ + EADC_T *eadc_base = (EADC_T *) NU_MODBASE(obj->adc); + uint32_t chn = NU_MODSUBINDEX(obj->adc); + + EADC_START_CONV(eadc_base, 1 << chn); + while (EADC_GET_DATA_VALID_FLAG(eadc_base, 1 << chn) != ((uint32_t) (1 << chn))); + uint16_t conv_res_12 = EADC_GET_CONV_DATA(eadc_base, chn); + // Just 12 bits are effective. Convert to 16 bits. + // conv_res_12: 0000 b11b10b9b8 b7b6b5b4 b3b2b1b0 + // conv_res_16: b11b10b9b8 b7b6b5b4 b3b2b1b0 b11b10b9b8 + uint16_t conv_res_16 = (conv_res_12 << 4) | (conv_res_12 >> 8); + + return conv_res_16; +} + +float analogin_read(analogin_t *obj) +{ + uint16_t value = analogin_read_u16(obj); + return (float) value * (1.0f / (float) 0xFFFF); +} + +const PinMap *analogin_pinmap() +{ + return PinMap_ADC; +} + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M251/analogout_api.c b/targets/TARGET_NUVOTON/TARGET_M251/analogout_api.c new file mode 100644 index 00000000000..e80b020c336 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/analogout_api.c @@ -0,0 +1,183 @@ +/* + * Copyright (c) 2019, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "analogout_api.h" + +#if DEVICE_ANALOGOUT + +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralPins.h" +#include "nu_modutil.h" + +/* Maximum DAC modules */ +#define NU_DACMOD_MAXNUM 1 +/* Maximum DAC channels per module */ +#define NU_DACCHN_MAXNUM 1 + +static uint32_t dac_modinit_mask[NU_DACMOD_MAXNUM]; + +static const struct nu_modinit_s dac_modinit_tab[] = { + {DAC_0_0, DAC_MODULE, 0, 0, DAC_RST, DAC_IRQn, NULL}, +}; + +void analogout_init(dac_t *obj, PinName pin) +{ + obj->dac = (DACName) pinmap_peripheral(pin, PinMap_DAC); + MBED_ASSERT(obj->dac != (DACName) NC); + + const struct nu_modinit_s *modinit = get_modinit(obj->dac, dac_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == obj->dac); + + /* Module index */ + uint32_t modidx = NU_MODINDEX(obj->dac); + MBED_ASSERT(modidx < NU_DACMOD_MAXNUM); + + /* Module subindex (aka channel) */ + uint32_t chn = NU_MODSUBINDEX(obj->dac); + MBED_ASSERT(chn < NU_DACCHN_MAXNUM); + + DAC_T *dac_base = (DAC_T *) NU_MODBASE(obj->dac); + + /* Module-level setup from here */ + + if (! dac_modinit_mask[modidx]) { + /* Reset IP */ + SYS_ResetModule(modinit->rsetidx); + + /* Select IP clock source and clock divider */ + CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv); + + /* Enable IP clock */ + CLK_EnableModuleClock(modinit->clkidx); + + /* The conversion settling time is 6us when 12-bit input code transition from + * lowest code (0x000) to highest code (0xFFF). */ + DAC_SetDelayTime(dac_base, 6); + + /* Configure DAT data format to left-aligned + * Effective 12-bits are aligned to left of 16-bit DAC_DAT. */ + DAC_ENABLE_LEFT_ALIGN(dac_base); + } + + /* Channel-level setup from here: */ + + /* Set the software trigger, enable DAC event trigger mode and enable D/A converter */ + DAC_Open(dac_base, chn, DAC_SOFTWARE_TRIGGER); + + /* Wire pinout */ + pinmap_pinout(pin, PinMap_DAC); + + /* Mark channel allocated */ + dac_modinit_mask[modidx] |= 1 << chn; +} + +void analogout_free(dac_t *obj) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->dac, dac_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == obj->dac); + + /* Module index */ + uint32_t modidx = NU_MODINDEX(obj->dac); + MBED_ASSERT(modidx < NU_DACMOD_MAXNUM); + + /* Module subindex (aka channel) */ + uint32_t chn = NU_MODSUBINDEX(obj->dac); + MBED_ASSERT(chn < NU_DACCHN_MAXNUM); + + DAC_T *dac_base = (DAC_T *) NU_MODBASE(obj->dac); + + /* Channel-level windup from here */ + + /* Mark channel free */ + dac_modinit_mask[modidx] &= ~(1 << chn); + + /* Close channel */ + DAC_Close(dac_base, chn); + + /* Module-level windup from here: */ + + /* See analogout_init() for reason */ + if (! dac_modinit_mask[modidx]) { + /* Disable IP clock */ + CLK_DisableModuleClock(modinit->clkidx); + } +} + +void analogout_write(dac_t *obj, float value) +{ + if (value <= 0.0f) { + analogout_write_u16(obj, 0); + } else if (value >= 1.0f) { + analogout_write_u16(obj, 0xFFFF); + } else { + analogout_write_u16(obj, (uint16_t) (value * ((float) 0xFFFF))); + } +} + +void analogout_write_u16(dac_t *obj, uint16_t value) +{ + DAC_T *dac_base = (DAC_T *) NU_MODBASE(obj->dac); + uint32_t chn = NU_MODSUBINDEX(obj->dac); + + /* We should have configured DAC data format to left-aligned */ + MBED_ASSERT(dac_base->CTL & DAC_CTL_LALIGN_Msk); + DAC_WRITE_DATA(dac_base, chn, value); + + /* Clear the DAC conversion complete finish flag for safe */ + DAC_CLR_INT_FLAG(dac_base, chn); + + /* Start A/D conversion */ + DAC_START_CONV(dac_base); + + /* Wait for completed */ + while (DAC_IS_BUSY(dac_base, chn)); +} + +float analogout_read(dac_t *obj) +{ + uint32_t value = analogout_read_u16(obj); + return (float) value * (1.0f / (float) 0xFFFF); +} + +uint16_t analogout_read_u16(dac_t *obj) +{ + DAC_T *dac_base = (DAC_T *) NU_MODBASE(obj->dac); + uint32_t chn = NU_MODSUBINDEX(obj->dac); + + /* We should have configured DAC data format to left-aligned */ + MBED_ASSERT(dac_base->CTL & DAC_CTL_LALIGN_Msk); + uint16_t dat12_4 = DAC_READ_DATA(dac_base, chn); + /* Just 12 bits are effective. Convert to 16 bits. + * + * dat12_4 : b11b10b9b8 b7b6b5b4 b3b2b1b0 0000 + * dat16 : b11b10b9b8 b7b6b5b4 b3b2b1b0 b11b10b9b8 + */ + uint16_t dat16 = (dat12_4 & 0xFFF0) | (dat12_4 >> 12); + + return dat16; +} + +const PinMap *analogout_pinmap() +{ + return PinMap_DAC; +} + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M251/crypto/crypto-misc.cpp b/targets/TARGET_NUVOTON/TARGET_M251/crypto/crypto-misc.cpp new file mode 100644 index 00000000000..4da9836fa0c --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/crypto/crypto-misc.cpp @@ -0,0 +1,274 @@ +/* + * Copyright (c) 2019, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#include "cmsis.h" +#include "mbed_assert.h" +#include "mbed_atomic.h" +#include "mbed_critical.h" +#include "mbed_error.h" +#include +#include "nu_modutil.h" +#include "nu_bitutil.h" +#include "crypto-misc.h" +#include "platform/SingletonPtr.h" +#include "platform/PlatformMutex.h" + +#if DEVICE_TRNG || defined(MBEDTLS_CONFIG_HW_SUPPORT) + +/* Consideration for choosing proper synchronization mechanism + * + * 1. We choose mutex to synchronize access to crypto non-SHA AC. We can guarantee: + * (1) No deadlock + * We just lock mutex for a short sequence of operations rather than the whole lifetime + * of crypto context. + * (2) No priority inversion + * Mutex supports priority inheritance and it is enabled. + * 2. We choose atomic flag to synchronize access to crypto SHA AC. We can guarantee: + * (1) No deadlock + * With SHA AC not supporting context save & restore, we provide SHA S/W fallback when + * SHA AC is not available. + * (2) No biting CPU + * Same reason as above. + */ + +/* Mutex for crypto AES AC management */ +static SingletonPtr crypto_aes_mutex; + +/* Atomic flag for crypto SHA AC management */ +static core_util_atomic_flag crypto_sha_atomic_flag = CORE_UTIL_ATOMIC_FLAG_INIT; + + +/* Crypto (AES, DES, SHA, etc.) init counter. Crypto's keeps active as it is non-zero. */ +static uint16_t crypto_init_counter = 0U; + +/* Crypto done flags */ +#define CRYPTO_DONE_OK BIT0 /* Done with OK */ +#define CRYPTO_DONE_ERR BIT1 /* Done with error */ + +/* Track if PRNG H/W operation is done */ +static volatile uint16_t crypto_prng_done; +/* Track if AES H/W operation is done */ +static volatile uint16_t crypto_aes_done; + +static void crypto_submodule_prestart(volatile uint16_t *submodule_done); +static bool crypto_submodule_wait(volatile uint16_t *submodule_done); + +/* As crypto init counter changes from 0 to 1: + * + * 1. Enable crypto clock + * 2. Enable crypto interrupt + */ +void crypto_init(void) +{ + core_util_critical_section_enter(); + if (crypto_init_counter == USHRT_MAX) { + core_util_critical_section_exit(); + error("Crypto clock enable counter would overflow (> USHRT_MAX)"); + } + core_util_atomic_incr_u16(&crypto_init_counter, 1); + if (crypto_init_counter == 1) { + CLK_EnableModuleClock(CRPT_MODULE); + + NVIC_EnableIRQ(CRPT_IRQn); + } + core_util_critical_section_exit(); +} + +/* As crypto init counter changes from 1 to 0: + * + * 1. Disable crypto interrupt + * 2. Disable crypto clock + */ +void crypto_uninit(void) +{ + core_util_critical_section_enter(); + if (crypto_init_counter == 0) { + core_util_critical_section_exit(); + error("Crypto clock enable counter would underflow (< 0)"); + } + core_util_atomic_decr_u16(&crypto_init_counter, 1); + if (crypto_init_counter == 0) { + NVIC_DisableIRQ(CRPT_IRQn); + + CLK_DisableModuleClock(CRPT_MODULE); + } + core_util_critical_section_exit(); +} + +/* Implementation that should never be optimized out by the compiler */ +void crypto_zeroize(void *v, size_t n) +{ + volatile unsigned char *p = (volatile unsigned char*) v; + while (n--) { + *p++ = 0; + } +} + +/* Implementation that should never be optimized out by the compiler */ +void crypto_zeroize32(uint32_t *v, size_t n) +{ + volatile uint32_t *p = (volatile uint32_t*) v; + while (n--) { + *p++ = 0; + } +} + +void crypto_aes_acquire(void) +{ + /* Don't check return code of Mutex::lock(void) + * + * This function treats RTOS errors as fatal system errors, so it can only return osOK. + * Use of the return value is deprecated, as the return is expected to become void in + * the future. + */ + crypto_aes_mutex->lock(); +} + +void crypto_aes_release(void) +{ + crypto_aes_mutex->unlock(); +} + +bool crypto_sha_try_acquire(void) +{ + return !core_util_atomic_flag_test_and_set(&crypto_sha_atomic_flag); +} + +void crypto_sha_release(void) +{ + core_util_atomic_flag_clear(&crypto_sha_atomic_flag); +} + +void crypto_prng_prestart(void) +{ + crypto_submodule_prestart(&crypto_prng_done); +} + +bool crypto_prng_wait(void) +{ + return crypto_submodule_wait(&crypto_prng_done); +} + +void crypto_aes_prestart(void) +{ + crypto_submodule_prestart(&crypto_aes_done); +} + +bool crypto_aes_wait(void) +{ + return crypto_submodule_wait(&crypto_aes_done); +} + +bool crypto_dma_buff_compat(const void *buff, size_t buff_size, size_t size_aligned_to) +{ + uint32_t buff_ = (uint32_t) buff; + + return (((buff_ & 0x03) == 0) && /* Word-aligned buffer base address */ + ((buff_size & (size_aligned_to - 1)) == 0) && /* Crypto submodule dependent buffer size alignment */ + (((buff_ >> 28) == 0x2) && (buff_size <= (0x30000000 - buff_)))); /* 0x20000000-0x2FFFFFFF */ +} + +/* Overlap cases + * + * 1. in_buff in front of out_buff: + * + * in in_end + * | | + * |||||||||||||||| + * |||||||||||||||| + * | | + * out out_end + * + * 2. out_buff in front of in_buff: + * + * in in_end + * | | + * |||||||||||||||| + * |||||||||||||||| + * | | + * out out_end + */ +bool crypto_dma_buffs_overlap(const void *in_buff, size_t in_buff_size, const void *out_buff, size_t out_buff_size) +{ + uint32_t in = (uint32_t) in_buff; + uint32_t in_end = in + in_buff_size; + uint32_t out = (uint32_t) out_buff; + uint32_t out_end = out + out_buff_size; + + bool overlap = (in <= out && out < in_end) || (out <= in && in < out_end); + + return overlap; +} + +static void crypto_submodule_prestart(volatile uint16_t *submodule_done) +{ + *submodule_done = 0; + + /* Ensure memory accesses above are completed before DMA is started + * + * Replacing __DSB() with __DMB() is also OK in this case. + * + * Refer to "multi-master systems" section with DMA in: + * https://static.docs.arm.com/dai0321/a/DAI0321A_programming_guide_memory_barriers_for_m_profile.pdf + */ + __DSB(); +} + +static bool crypto_submodule_wait(volatile uint16_t *submodule_done) +{ + while (! *submodule_done); + + /* Ensure while loop above and subsequent code are not reordered */ + __DSB(); + + if ((*submodule_done & CRYPTO_DONE_OK)) { + /* Done with OK */ + return true; + } else if ((*submodule_done & CRYPTO_DONE_ERR)) { + /* Done with error */ + return false; + } + + return false; +} + +/* Crypto interrupt handler + * + * There's inconsistency in cryptography related naming, Crpt or Crypto. For example, + * cryptography IRQ handler could be CRPT_IRQHandler or CRYPTO_IRQHandler. To override + * default cryptography IRQ handler, see device/startup_{CHIP}.c for its correct name + * or call NVIC_SetVector() in crypto_init() regardless of its name. */ +extern "C" void CRPT_IRQHandler() +{ + uint32_t intsts; + + if ((intsts = PRNG_GET_INT_FLAG(CRYPTO_MODBASE())) != 0) { + /* Done with OK */ + crypto_prng_done |= CRYPTO_DONE_OK; + /* Clear interrupt flag */ + PRNG_CLR_INT_FLAG(CRYPTO_MODBASE()); + } else if ((intsts = AES_GET_INT_FLAG(CRYPTO_MODBASE())) != 0) { + /* Done with OK */ + crypto_aes_done |= CRYPTO_DONE_OK; + /* Clear interrupt flag */ + AES_CLR_INT_FLAG(CRYPTO_MODBASE()); + } +} + +#endif /* #if DEVICE_TRNG || defined(MBEDTLS_CONFIG_HW_SUPPORT) */ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/crypto/crypto-misc.h b/targets/TARGET_NUVOTON/TARGET_M251/crypto/crypto-misc.h new file mode 100644 index 00000000000..fa5a278d91f --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/crypto/crypto-misc.h @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2019, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_CRYPTO_MISC_H +#define MBED_CRYPTO_MISC_H + +#include + +#if DEVICE_TRNG || defined(MBEDTLS_CONFIG_HW_SUPPORT) + +#ifdef __cplusplus +extern "C" { +#endif + +/* Get Crypto module base */ +__STATIC_INLINE CRPT_T *CRYPTO_MODBASE(void) +{ + return CRPT; +} + +/* Init/Uninit crypto module */ +void crypto_init(void); +void crypto_uninit(void); + +/* Clear buffer to zero + * Implementation that should never be optimized out by the compiler */ +void crypto_zeroize(void *v, size_t n); +void crypto_zeroize32(uint32_t *v, size_t n); + +/* Acquire/release ownership of crypto sub-module + * + * \note "acquire" is blocking until ownership is acquired + * + * \note "acquire"/"release" must be paired. + * + * \note Recursive "acquire" is allowed because the underlying synchronization + * primitive mutex supports it. + */ +void crypto_aes_acquire(void); +void crypto_aes_release(void); + +/* Acquire/release ownership of crypto sub-module + * + * \return false if crytpo sub-module is held by another thread or + * another mbedtls context. + * true if successful + * + * \note Successful "try_acquire" and "release" must be paired. + */ +bool crypto_sha_try_acquire(void); +void crypto_sha_release(void); + +/* Flow control between crypto/xxx start and crypto/xxx ISR + * + * crypto_xxx_prestart/crypto_xxx_wait encapsulate control flow between crypto/xxx start and crypto/xxx ISR. + * + * crypto_xxx_prestart will also address synchronization issue with memory barrier instruction. + * + * On finish, return of crypto_xxx_wait indicates success or not: + * true if successful + * false if failed + * + * Example: Start AES H/W and wait for its finish + * crypto_aes_prestart(); + * AES_Start(); + * crypto_aes_wait(); + */ +void crypto_prng_prestart(void); +bool crypto_prng_wait(void); +void crypto_aes_prestart(void); +bool crypto_aes_wait(void); + + +/* Check if buffer can be used for crypto DMA. It has the following requirements: + * (1) Word-aligned buffer base address + * (2) Crypto submodule (AES, DES, SHA, etc.) dependent buffer size alignment. Must be 2 power. + * (3) Located in 0x20000000-0x2FFFFFFF region + */ +bool crypto_dma_buff_compat(const void *buff, size_t buff_size, size_t size_aligned_to); + +/* Check if input/output buffers are overlapped */ +bool crypto_dma_buffs_overlap(const void *in_buff, size_t in_buff_size, const void *out_buff, size_t out_buff_size); + +#ifdef __cplusplus +} +#endif + +#endif +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device.h b/targets/TARGET_NUVOTON/TARGET_M251/device.h new file mode 100644 index 00000000000..aea59466b54 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2019, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_ID_LENGTH 24 + +#include "objects.h" + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/M251.h b/targets/TARGET_NUVOTON/TARGET_M251/device/M251.h new file mode 100644 index 00000000000..42d7ec6c408 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/M251.h @@ -0,0 +1,647 @@ +/**************************************************************************//** + * @file M251.h + * @version V1.0 + * @brief Peripheral Access Layer Header File + * + * @note + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ + +/** + \mainpage NuMicro M251/M252 Series CMSIS BSP Driver Reference + * + * Introduction + * + * This user manual describes the usage of M251/M252 Series MCU device driver + * + * Disclaimer + * + * The Software is furnished "AS IS", without warranty as to performance or results, and + * the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all + * warranties, express, implied or otherwise, with regard to the Software, its use, or + * operation, including without limitation any and all warranties of merchantability, fitness + * for a particular purpose, and non-infringement of intellectual property rights. + * + * Important Notice + * + * Nuvoton Products are neither intended nor warranted for usage in systems or equipment, + * any malfunction or failure of which may cause loss of human life, bodily injury or severe + * property damage. Such applications are deemed, "Insecure Usage". + * + * Insecure usage includes, but is not limited to: equipment for surgical implementation, + * atomic energy control instruments, airplane or spaceship instruments, the control or + * operation of dynamic, brake or safety systems designed for vehicular use, traffic signal + * instruments, all types of safety devices, and other applications intended to support or + * sustain life. + * + * All Insecure Usage shall be made at customer's risk, and in the event that third parties + * lay claims to Nuvoton as a result of customer's Insecure Usage, customer shall indemnify + * the damages and liabilities thus incurred by Nuvoton. + * + * Please note that all data and specifications are subject to change without notice. All the + * trademarks of products and companies mentioned in this datasheet belong to their respective + * owners. + * + * Copyright Notice + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + */ + +#ifndef __M251_H__ +#define __M251_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************************/ +/* Processor and Core Peripherals */ +/******************************************************************************/ +/** @addtogroup CMSIS_Device CMSIS Definitions + Configuration of the Cortex-M23 Processor and Core Peripherals + @{ +*/ + +/* + * ========================================================================== + * ---------- Interrupt Number Definition ----------------------------------- + * ========================================================================== + */ + +/** + * @details Interrupt Number Definition. + */ +typedef enum IRQn +{ + /****** Cortex-M0 Processor Exceptions Numbers ***********************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ + + /****** ARMIKMCU Swift specific Interrupt Numbers ********************************************/ + BOD_IRQn = 0, /*!< Brown-Out Low Voltage Detected Interrupt */ + IRCTRIM_IRQn = 1, /*!< Watch Dog Timer Interrupt */ + PWRWU_IRQn = 2, /*!< EINT0, EINT2 and EINT4 Interrupt */ + RESERVE0 = 3, /*!< Reserve 0 */ + CLKFAIL_IRQn = 4, /*!< Clock fail dector Interrupt */ + RESERVE1 = 5, /*!< Reserve 1 */ + RTC_IRQn = 6, /*!< Real Time Clock Interrupt */ + TAMPER_IRQn = 7, /*!< Tamper detection Interrupt */ + WDT_IRQn = 8, /*!< Watch Dog Timer Interrupt */ + WWDT_IRQn = 9, /*!< Window Watch Dog Timer Interrupt */ + EINT0_IRQn = 10, /*!< External Input 0 Interrupt */ + EINT1_IRQn = 11, /*!< External Input 1 Interrupt */ + EINT2_IRQn = 12, /*!< External Input 2 Interrupt */ + EINT3_IRQn = 13, /*!< External Input 3 Interrupt */ + EINT4_IRQn = 14, /*!< External Input 4 Interrupt */ + EINT5_IRQn = 15, /*!< External Input 5 Interrupt */ + GPA_IRQn = 16, /*!< GPIO PORT A Interrupt */ + GPB_IRQn = 17, /*!< GPIO PORT B Interrupt */ + GPC_IRQn = 18, /*!< GPIO PORT C Interrupt */ + GPD_IRQn = 19, /*!< GPIO PORT D Interrupt */ + GPE_IRQn = 20, /*!< GPIO PORT E Interrupt */ + GPF_IRQn = 21, /*!< GPIO PORT F Interrupt */ + QSPI0_IRQn = 22, /*!< QSPI0 Interrupt */ + SPI0_IRQn = 23, /*!< SPI0 Interrupt */ + BRAKE0_IRQn = 24, /*!< PWM Brake0 Interrupt */ + PWM0_P0_IRQn = 25, /*!< PWM0 P0 Interrupt */ + PWM0_P1_IRQn = 26, /*!< PWM0 P1 Interrupt */ + PWM0_P2_IRQn = 27, /*!< PWM0 P2 Interrupt */ + BRAKE1_IRQn = 28, /*!< PWM Brake1 Interrupt */ + PWM1_P0_IRQn = 29, /*!< PWM1 P0 Interrupt */ + PWM1_P1_IRQn = 30, /*!< PWM1 P1 Interrupt */ + PWM1_P2_IRQn = 31, /*!< PWM1 P2 Interrupt */ + TMR0_IRQn = 32, /*!< TIMER0 Interrupt */ + TMR1_IRQn = 33, /*!< TIMER1 Interrupt */ + TMR2_IRQn = 34, /*!< TIMER2 Interrupt */ + TMR3_IRQn = 35, /*!< TIMER3 Interrupt */ + UART0_IRQn = 36, /*!< UART0 Interrupt */ + UART1_IRQn = 37, /*!< UART1 Interrupt */ + I2C0_IRQn = 38, /*!< I2C0 Interrupt */ + I2C1_IRQn = 39, /*!< I2C1 Interrupt */ + PDMA_IRQn = 40, /*!< Peripheral DMA Interrupt */ + DAC_IRQn = 41, /*!< DAC Interrupt */ + EADC_INT0_IRQn = 42, /*!< Enhance ADC Interrupt 0 */ + EADC_INT1_IRQn = 43, /*!< Enhance ADC Interrupt 1 */ + ACMP01_IRQn = 44, /*!< ACMP0 Interrupt */ + BPWM0_IRQn = 45, /*!< BPWM0 Interrupt */ + EADC_INT2_IRQn = 46, /*!< Enhance EADC Interrupt 2 */ + EADC_INT3_IRQn = 47, /*!< Enhance EADC Interrupt 3 */ + UART2_IRQn = 48, /*!< UART2 Interrupt */ + RESERVE2 = 49, /*!< Reserve 2 */ + USCI0_IRQn = 50, /*!< USCI0 Interrupt */ + RESERVE3 = 51, /*!< Reserve 3 */ + USCI1_IRQn = 52, /*!< USCI1 Interrupt */ + USBD_IRQn = 53, /*!< USB Device Interrupt */ + BPWM1_IRQn = 54, /*!< BPWM1 Interrupt */ + PSIO_IRQn = 55, /*!< PSIO Interrupt */ + RESERVE4 = 56, /*!< Reserve 4 */ + CRPT_IRQn = 57, /*!< Cryption Interrupt */ + SC0_IRQn = 58, /*!< Smart Card0 Interrupt */ + RESERVE5 = 59, /*!< Reserve 5 */ + USCI2_IRQn = 60, /*!< USCI2 Interrupt */ + RESERVE6 = 61, /*!< Reserve 6 */ + OPA_IRQn = 62, /*!< OPA Interrupt */ +} IRQn_Type; + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) +#pragma push +#pragma anon_unions +#elif defined (__ICCARM__) +#pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wc11-extensions" +#pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) +/* anonymous unions are enabled by default */ +#elif defined (__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined (__TASKING__) +#pragma warning 586 +#elif defined (__CSMC__) +/* anonymous unions are enabled by default */ +#else +#warning Not supported compiler type +#endif + +/* -------- Configuration of the Cortex-ARMv8MBL Processor and Core Peripherals ------- */ +#define __ARMv8MBL_REV 0x0000U /* Core revision r0p0 */ +#define __SAU_PRESENT 0U /* SAU present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define USE_ASSERT 0U /* Define to use Assert function or not */ + +/*@}*/ /* end of group CMSIS_Device */ + + +#include "core_cm23.h" /* Processor and core peripherals */ +#include "system_M251.h" /* System Header */ + +/** + * Initialize the system clock + * + * @param none + * @return none + * + * @brief Setup the micro controller system + * Initialize the PLL and update the SystemFrequency variable + */ +extern void SystemInit(void); + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +#include "acmp_reg.h" +#include "bpwm_reg.h" +#include "clk_reg.h" +#include "crc_reg.h" +#include "crypto_reg.h" +#include "dac_reg.h" +#include "eadc_reg.h" +#include "ebi_reg.h" +#include "fmc_reg.h" +#include "gpio_reg.h" +#include "i2c_reg.h" +#include "opa_reg.h" +#include "pdma_reg.h" +#include "psio_reg.h" +#include "pwm_reg.h" +#include "rtc_reg.h" +#include "sc_reg.h" +#include "qspi_reg.h" +#include "spi_reg.h" +#include "sys_reg.h" +#include "timer_reg.h" +#include "uart_reg.h" +#include "uuart_reg.h" +#include "ui2c_reg.h" +#include "uspi_reg.h" +#include "usbd_reg.h" +#include "wdt_reg.h" +#include "wwdt_reg.h" + +/**@}*/ /* end of REGISTER group */ + + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ + +/** @addtogroup PERIPHERAL_BASE Peripheral Memory Base + Memory Mapped Structure for Series Peripheral + @{ + */ + +/* Peripheral and SRAM base address */ +#define FLASH_BASE ((uint32_t)0x00000000UL) /*!< Flash Base Address */ +#define SRAM_BASE ((uint32_t)0x20000000UL) /*!< SRAM Base Address */ +#define PERIPH_BASE ((uint32_t)0x40000000UL) /*!< Peripheral Base Address */ + +/* Peripheral memory map */ +#define AHBPERIPH_BASE PERIPH_BASE /*!< AHB Base Address */ +#define APBPERIPH_BASE (PERIPH_BASE + 0x00040000UL) /*!< APB Base Address */ + +/*!< AHB peripherals */ +#define SYS_BASE (AHBPERIPH_BASE + 0x00000UL) +#define CLK_BASE (AHBPERIPH_BASE + 0x00200UL) +#define NMI_BASE (AHBPERIPH_BASE + 0x00300UL) +#define GPIO_BASE (AHBPERIPH_BASE + 0x04000UL) +#define GPIOA_BASE (AHBPERIPH_BASE + 0x04000UL) +#define GPIOB_BASE (AHBPERIPH_BASE + 0x04040UL) +#define GPIOC_BASE (AHBPERIPH_BASE + 0x04080UL) +#define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0UL) +#define GPIOE_BASE (AHBPERIPH_BASE + 0x04100UL) +#define GPIOF_BASE (AHBPERIPH_BASE + 0x04140UL) +#define GPIO_DBCTL_BASE (AHBPERIPH_BASE + 0x04440UL) +#define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04800UL) +#define PDMA_BASE (AHBPERIPH_BASE + 0x08000UL) +#define FMC_BASE (AHBPERIPH_BASE + 0x0C000UL) +#define EBI_BASE (AHBPERIPH_BASE + 0x10000UL) +#define CRC_BASE (AHBPERIPH_BASE + 0x31000UL) +#define CRPT_BASE (AHBPERIPH_BASE + 0x32000UL) + +/*!< APB0 peripherals */ +#define WDT_BASE (APBPERIPH_BASE + 0x00000UL) +#define WWDT_BASE (APBPERIPH_BASE + 0x00100UL) +#define OPA_BASE (APBPERIPH_BASE + 0x06000UL) +#define TIMER01_BASE (APBPERIPH_BASE + 0x10000UL) +#define PWM0_BASE (APBPERIPH_BASE + 0x18000UL) +#define BPWM0_BASE (APBPERIPH_BASE + 0x1A000UL) +#define QSPI0_BASE (APBPERIPH_BASE + 0x20000UL) +#define UART0_BASE (APBPERIPH_BASE + 0x30000UL) +#define UART2_BASE (APBPERIPH_BASE + 0x32000UL) +#define I2C0_BASE (APBPERIPH_BASE + 0x40000UL) +#define SC0_BASE (APBPERIPH_BASE + 0x50000UL) +#define USBD_BASE (APBPERIPH_BASE + 0x80000UL) +#define USCI0_BASE (APBPERIPH_BASE + 0x90000UL) +#define USCI2_BASE (APBPERIPH_BASE + 0x92000UL) + +/*!< APB1 peripherals */ +#define RTC_BASE (APBPERIPH_BASE + 0x01000UL) +#define EADC_BASE (APBPERIPH_BASE + 0x03000UL) +#define ACMP01_BASE (APBPERIPH_BASE + 0x05000UL) +#define DAC_BASE (APBPERIPH_BASE + 0x07000UL) +#define TIMER23_BASE (APBPERIPH_BASE + 0x11000UL) +#define PWM1_BASE (APBPERIPH_BASE + 0x19000UL) +#define BPWM1_BASE (APBPERIPH_BASE + 0x1B000UL) +#define SPI0_BASE (APBPERIPH_BASE + 0x21000UL) +#define UART1_BASE (APBPERIPH_BASE + 0x31000UL) +#define I2C1_BASE (APBPERIPH_BASE + 0x41000UL) +#define PSIO_BASE (APBPERIPH_BASE + 0x83000UL) +#define USCI1_BASE (APBPERIPH_BASE + 0x91000UL) + +/**@}*/ /* end of group PERIPHERAL_BASE */ + + +/******************************************************************************/ +/* Peripheral declaration */ +/******************************************************************************/ + +/** @addtogroup PERIPHERAL_DECLARATION Peripheral Pointer + The Declaration of Peripheral Pointer + @{ + */ + +/*!< AHB peripherals */ +#define SYS ((SYS_T *) SYS_BASE) +#define CLK ((CLK_T *) CLK_BASE) +#define PA ((GPIO_T *) GPIOA_BASE) +#define PB ((GPIO_T *) GPIOB_BASE) +#define PC ((GPIO_T *) GPIOC_BASE) +#define PD ((GPIO_T *) GPIOD_BASE) +#define PE ((GPIO_T *) GPIOE_BASE) +#define PF ((GPIO_T *) GPIOF_BASE) +#define GPIO ((GPIO_DBCTL_T *) GPIO_DBCTL_BASE) +#define PDMA ((PDMA_T *) PDMA_BASE) +#define FMC ((FMC_T *) FMC_BASE) +#define EBI ((EBI_T *) EBI_BASE) +#define CRC ((CRC_T *) CRC_BASE) +#define CRPT ((CRPT_T *) CRPT_BASE) + +/*!< APB0 peripherals */ +#define WDT ((WDT_T *) WDT_BASE) +#define WWDT ((WWDT_T *) WWDT_BASE) +#define OPA ((OPA_T *) OPA_BASE) +#define TIMER0 ((TIMER_T *) TIMER01_BASE) +#define TIMER1 ((TIMER_T *) (TIMER01_BASE + 0x100UL)) +#define PWM0 ((PWM_T *) PWM0_BASE) +#define BPWM0 ((BPWM_T *) BPWM0_BASE) +#define QSPI0 ((QSPI_T *) QSPI0_BASE) +#define UART0 ((UART_T *) UART0_BASE) +#define UART2 ((UART_T *) UART2_BASE) +#define I2C0 ((I2C_T *) I2C0_BASE) +#define SC0 ((SC_T *) SC0_BASE) +#define USBD ((USBD_T *) USBD_BASE) +#define UI2C0 ((UI2C_T *) USCI0_BASE) +#define USPI0 ((USPI_T *) USCI0_BASE) +#define UUART0 ((UUART_T *) USCI0_BASE) +#define UI2C2 ((UI2C_T *) USCI2_BASE) +#define USPI2 ((USPI_T *) USCI2_BASE) +#define UUART2 ((UUART_T *) USCI2_BASE) + +/*!< APB1 peripherals */ +#define RTC ((RTC_T *) RTC_BASE) +#define EADC ((EADC_T *) EADC_BASE) +#define ACMP01 ((ACMP_T *) ACMP01_BASE) +#define DAC ((DAC_T *) DAC_BASE) +#define TIMER2 ((TIMER_T *) TIMER23_BASE) +#define TIMER3 ((TIMER_T *) (TIMER23_BASE+ 0x100UL)) +#define PWM1 ((PWM_T *) PWM1_BASE) +#define BPWM1 ((BPWM_T *) BPWM1_BASE) +#define SPI0 ((SPI_T *) SPI0_BASE) +#define UART1 ((UART_T *) UART1_BASE) +#define I2C1 ((I2C_T *) I2C1_BASE) +#define PSIO ((PSIO_T *) PSIO_BASE) +#define UI2C1 ((UI2C_T *) USCI1_BASE) +#define USPI1 ((USPI_T *) USCI1_BASE) +#define UUART1 ((UUART_T *) USCI1_BASE) + +/**@}*/ /* end of group PERIPHERAL_DECLARATION */ + + +/* -------------------- End of section using anonymous unions ------------------- */ +#if defined (__CC_ARM) +#pragma pop +#elif defined (__ICCARM__) +/* leave anonymous unions enabled */ +#elif (__ARMCC_VERSION >= 6010050) +#pragma clang diagnostic pop +#elif defined (__GNUC__) +/* anonymous unions are enabled by default */ +#elif defined (__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined (__TASKING__) +#pragma warning restore +#elif defined (__CSMC__) +/* anonymous unions are enabled by default */ +#else +#warning Not supported compiler type +#endif + +#ifdef __cplusplus +} +#endif + + +/*=============================================================================*/ + +/** @addtogroup IO_ROUTINE I/O Routines + The Declaration of I/O Routines + @{ + */ + +typedef volatile unsigned char vu8; +typedef volatile unsigned long vu32; +typedef volatile unsigned short vu16; + +/** + * @brief Get a 8-bit unsigned value from specified address + * @param[in] addr Address to get 8-bit data from + * @return 8-bit unsigned value stored in specified address + */ +#define M8(addr) (*((vu8 *) (addr))) + +/** + * @brief Get a 16-bit unsigned value from specified address + * @param[in] addr Address to get 16-bit data from + * @return 16-bit unsigned value stored in specified address + * @note The input address must be 16-bit aligned + */ +#define M16(addr) (*((vu16 *) (addr))) + +/** + * @brief Get a 32-bit unsigned value from specified address + * @param[in] addr Address to get 32-bit data from + * @return 32-bit unsigned value stored in specified address + * @note The input address must be 32-bit aligned + */ +#define M32(addr) (*((vu32 *) (addr))) + +/** + * @brief Set a 32-bit unsigned value to specified I/O port + * @param[in] port Port address to set 32-bit data + * @param[in] value Value to write to I/O port + * @return None + * @note The output port must be 32-bit aligned + */ +#define outpw(port,value) (*((volatile unsigned int *)(port))=(value)) + +/** + * @brief Get a 32-bit unsigned value from specified I/O port + * @param[in] port Port address to get 32-bit data from + * @return 32-bit unsigned value stored in specified I/O port + * @note The input port must be 32-bit aligned + */ +#define inpw(port) ((*((volatile unsigned int *)(port)))) + +/** + * @brief Set a 16-bit unsigned value to specified I/O port + * @param[in] port Port address to set 16-bit data + * @param[in] value Value to write to I/O port + * @return None + * @note The output port must be 16-bit aligned + */ +#define outps(port,value) (*((volatile unsigned short *)(port))=(value)) + +/** + * @brief Get a 16-bit unsigned value from specified I/O port + * @param[in] port Port address to get 16-bit data from + * @return 16-bit unsigned value stored in specified I/O port + * @note The input port must be 16-bit aligned + */ +#define inps(port) ((*((volatile unsigned short *)(port)))) + +/** + * @brief Set a 8-bit unsigned value to specified I/O port + * @param[in] port Port address to set 8-bit data + * @param[in] value Value to write to I/O port + * @return None + */ +#define outpb(port,value) (*((volatile unsigned char *)(port))=(value)) + +/** + * @brief Get a 8-bit unsigned value from specified I/O port + * @param[in] port Port address to get 8-bit data from + * @return 8-bit unsigned value stored in specified I/O port + */ +#define inpb(port) ((*((volatile unsigned char *)(port)))) + +/** + * @brief Set a 32-bit unsigned value to specified I/O port + * @param[in] port Port address to set 32-bit data + * @param[in] value Value to write to I/O port + * @return None + * @note The output port must be 32-bit aligned + */ +#define outp32(port,value) (*((volatile unsigned int *)(port))=(value)) + +/** + * @brief Get a 32-bit unsigned value from specified I/O port + * @param[in] port Port address to get 32-bit data from + * @return 32-bit unsigned value stored in specified I/O port + * @note The input port must be 32-bit aligned + */ +#define inp32(port) ((*((volatile unsigned int *)(port)))) + +/** + * @brief Set a 16-bit unsigned value to specified I/O port + * @param[in] port Port address to set 16-bit data + * @param[in] value Value to write to I/O port + * @return None + * @note The output port must be 16-bit aligned + */ +#define outp16(port,value) (*((volatile unsigned short *)(port))=(value)) + +/** + * @brief Get a 16-bit unsigned value from specified I/O port + * @param[in] port Port address to get 16-bit data from + * @return 16-bit unsigned value stored in specified I/O port + * @note The input port must be 16-bit aligned + */ +#define inp16(port) ((*((volatile unsigned short *)(port)))) + +/** + * @brief Set a 8-bit unsigned value to specified I/O port + * @param[in] port Port address to set 8-bit data + * @param[in] value Value to write to I/O port + * @return None + */ +#define outp8(port,value) (*((volatile unsigned char *)(port))=(value)) + +/** + * @brief Get a 8-bit unsigned value from specified I/O port + * @param[in] port Port address to get 8-bit data from + * @return 8-bit unsigned value stored in specified I/O port + */ +#define inp8(port) ((*((volatile unsigned char *)(port)))) + +/*@}*/ /* end of group IO_ROUTINE */ + + +/******************************************************************************/ +/* Legacy Constants */ +/******************************************************************************/ + +/** @addtogroup Legacy_Constants Legacy Constants + Legacy Constants + @{ +*/ + +#define E_SUCCESS (0) + +#ifndef NULL + #define NULL (0) ///< NULL pointer +#endif + +#define TRUE (1UL) ///< Boolean true, define to use in API parameters or return value +#define FALSE (0UL) ///< Boolean false, define to use in API parameters or return value + +#define ENABLE (1UL) ///< Enable, define to use in API parameters +#define DISABLE (0UL) ///< Disable, define to use in API parameters + +/* Define one bit mask */ +#define BIT0 (0x00000001UL) ///< Bit 0 mask of an 32 bit integer +#define BIT1 (0x00000002UL) ///< Bit 1 mask of an 32 bit integer +#define BIT2 (0x00000004UL) ///< Bit 2 mask of an 32 bit integer +#define BIT3 (0x00000008UL) ///< Bit 3 mask of an 32 bit integer +#define BIT4 (0x00000010UL) ///< Bit 4 mask of an 32 bit integer +#define BIT5 (0x00000020UL) ///< Bit 5 mask of an 32 bit integer +#define BIT6 (0x00000040UL) ///< Bit 6 mask of an 32 bit integer +#define BIT7 (0x00000080UL) ///< Bit 7 mask of an 32 bit integer +#define BIT8 (0x00000100UL) ///< Bit 8 mask of an 32 bit integer +#define BIT9 (0x00000200UL) ///< Bit 9 mask of an 32 bit integer +#define BIT10 (0x00000400UL) ///< Bit 10 mask of an 32 bit integer +#define BIT11 (0x00000800UL) ///< Bit 11 mask of an 32 bit integer +#define BIT12 (0x00001000UL) ///< Bit 12 mask of an 32 bit integer +#define BIT13 (0x00002000UL) ///< Bit 13 mask of an 32 bit integer +#define BIT14 (0x00004000UL) ///< Bit 14 mask of an 32 bit integer +#define BIT15 (0x00008000UL) ///< Bit 15 mask of an 32 bit integer +#define BIT16 (0x00010000UL) ///< Bit 16 mask of an 32 bit integer +#define BIT17 (0x00020000UL) ///< Bit 17 mask of an 32 bit integer +#define BIT18 (0x00040000UL) ///< Bit 18 mask of an 32 bit integer +#define BIT19 (0x00080000UL) ///< Bit 19 mask of an 32 bit integer +#define BIT20 (0x00100000UL) ///< Bit 20 mask of an 32 bit integer +#define BIT21 (0x00200000UL) ///< Bit 21 mask of an 32 bit integer +#define BIT22 (0x00400000UL) ///< Bit 22 mask of an 32 bit integer +#define BIT23 (0x00800000UL) ///< Bit 23 mask of an 32 bit integer +#define BIT24 (0x01000000UL) ///< Bit 24 mask of an 32 bit integer +#define BIT25 (0x02000000UL) ///< Bit 25 mask of an 32 bit integer +#define BIT26 (0x04000000UL) ///< Bit 26 mask of an 32 bit integer +#define BIT27 (0x08000000UL) ///< Bit 27 mask of an 32 bit integer +#define BIT28 (0x10000000UL) ///< Bit 28 mask of an 32 bit integer +#define BIT29 (0x20000000UL) ///< Bit 29 mask of an 32 bit integer +#define BIT30 (0x40000000UL) ///< Bit 30 mask of an 32 bit integer +#define BIT31 (0x80000000UL) ///< Bit 31 mask of an 32 bit integer + +/* Byte Mask Definitions */ +#define BYTE0_Msk (0x000000FFUL) ///< Mask to get bit0~bit7 from a 32 bit integer +#define BYTE1_Msk (0x0000FF00UL) ///< Mask to get bit8~bit15 from a 32 bit integer +#define BYTE2_Msk (0x00FF0000UL) ///< Mask to get bit16~bit23 from a 32 bit integer +#define BYTE3_Msk (0xFF000000UL) ///< Mask to get bit24~bit31 from a 32 bit integer + +#define GET_BYTE0(u32Param) (((u32Param) & BYTE0_Msk) ) /*!< Extract Byte 0 (Bit 0~ 7) from parameter u32Param */ +#define GET_BYTE1(u32Param) (((u32Param) & BYTE1_Msk) >> 8) /*!< Extract Byte 1 (Bit 8~15) from parameter u32Param */ +#define GET_BYTE2(u32Param) (((u32Param) & BYTE2_Msk) >> 16) /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */ +#define GET_BYTE3(u32Param) (((u32Param) & BYTE3_Msk) >> 24) /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */ + +/*@}*/ /* end of group Legacy_Constants */ + + +/******************************************************************************/ +/* Peripheral header files */ +/******************************************************************************/ +#include "m251_bpwm.h" +#include "m251_sys.h" +#include "m251_clk.h" +#include "m251_uart.h" +#include "m251_opa.h" +#include "m251_acmp.h" +#include "m251_rtc.h" +#include "m251_fmc.h" +#include "m251_gpio.h" +#include "m251_i2c.h" +#include "m251_pdma.h" +#include "m251_pwm.h" +#include "m251_qspi.h" +#include "m251_spi.h" +#include "m251_timer.h" +#include "m251_timer_pwm.h" +#include "m251_usci_i2c.h" +#include "m251_usci_spi.h" +#include "m251_usci_uart.h" +#include "m251_usbd.h" +#include "m251_rtc.h" +#include "m251_crc.h" +#include "m251_wdt.h" +#include "m251_wwdt.h" +#include "m251_eadc.h" +#include "m251_dac.h" +#include "m251_crypto.h" +#include "m251_ebi.h" +#include "m251_psio.h" +#include "m251_sc.h" +#include "m251_scuart.h" + +#endif /* __M251_H__ */ + + +/* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. */ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/NuMicro.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/NuMicro.h new file mode 100644 index 00000000000..3bfe1658446 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/NuMicro.h @@ -0,0 +1,15 @@ +/**************************************************************************//** + * @file NuMicro.h + * @version V1.00 + * @brief NuMicro peripheral access layer header file. + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NUMICRO_H__ +#define __NUMICRO_H__ + +#include "M251.h" + +#endif /* __NUMICRO_H__ */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/acmp_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/acmp_reg.h new file mode 100644 index 00000000000..672695d3ee8 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/acmp_reg.h @@ -0,0 +1,234 @@ +/**************************************************************************//** + * @file acmp_reg.h + * @version V1.00 + * @brief ACMP register definition header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __ACMP_REG_H__ +#define __ACMP_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup ACMP Analog Comparator Controller (ACMP) + Memory Mapped Structure for ACMP Controller +@{ */ + +typedef struct +{ + + + /** + * @var ACMP_T::CTL + * Offset: 0x00~0x04 Analog Comparator 0/1 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ACMPEN |Comparator Enable Bit + * | | |0 = Comparator x Disabled. + * | | |1 = Comparator x Enabled. + * |[1] |ACMPIE |Comparator Interrupt Enable Bit + * | | |0 = Comparator x interrupt Disabled. + * | | |1 = Comparator x interrupt Enabled + * | | |If WKEN (ACMP_CTL0[16]) is set to 1, the wake-up interrupt function will be enabled as well. + * |[3] |ACMPOINV |Comparator Output Inverse + * | | |0 = Comparator x output inverse Disabled. + * | | |1 = Comparator x output inverse Enabled. + * |[5:4] |NEGSEL |Comparator Negative Input Selection + * | | |00 = ACMPx_N pin. + * | | |01 = Internal comparator reference voltage (CRV). + * | | |10 = Band-gap voltage. + * | | |11 = DAC output. + * |[7:6] |POSSEL |Comparator Positive Input Selection + * | | |00 = Input from ACMPx_P0. + * | | |01 = Input from ACMPx_P1. + * | | |10 = Input from ACMPx_P2. + * | | |11 = Input from ACMPx_P3. + * |[9:8] |INTPOL |Interrupt Condition Polarity Selection + * | | |ACMPIFx will be set to 1 when comparator output edge condition is detected. + * | | |00 = Rising edge or falling edge. + * | | |01 = Rising edge. + * | | |10 = Falling edge. + * | | |11 = Reserved. + * |[12] |OUTSEL |Comparator Output Select + * | | |0 = Comparator x output to ACMPx_O pin is unfiltered comparator output. + * | | |1 = Comparator x output to ACMPx_O pin is from filter output. + * |[15:13] |FILTSEL |Comparator Output Filter Count Selection + * | | |000 = Filter function is Disabled. + * | | |001 = ACMPx output is sampled 1 consecutive PCLK. + * | | |010 = ACMPx output is sampled 2 consecutive PCLKs. + * | | |011 = ACMPx output is sampled 4 consecutive PCLKs. + * | | |100 = ACMPx output is sampled 8 consecutive PCLKs. + * | | |101 = ACMPx output is sampled 16 consecutive PCLKs. + * | | |110 = ACMPx output is sampled 32 consecutive PCLKs. + * | | |111 = ACMPx output is sampled 64 consecutive PCLKs. + * |[16] |WKEN |Power-down Wake-up Enable Bit + * | | |0 = Wake-up function Disabled. + * | | |1 = Wake-up function Enabled. + * |[17] |WLATEN |Window Latch Mode Enable Bit + * | | |0 = Window Latch Mode Disabled. + * | | |1 = Window Latch Mode Enabled. + * |[18] |WCMPSEL |Window Compare Mode Selection + * | | |0 = Window Compare Mode Disabled. + * | | |1 = Window Compare Mode is Selected. + * |[25:24] |HYSSEL |Hysteresis Mode Selection + * | | |00 = Hysteresis is 0mV. + * | | |01 = Hysteresis is 10mV. + * | | |10 = Hysteresis is 20mV. + * | | |11 = Hysteresis is 30mV. + * |[29:28] |MODESEL |Propagation Delay Mode Selection + * | | |00 = Max propagation delay is 4.5uS, operation current is 1.2uA. + * | | |01 = Max propagation delay is 2uS, operation current is 3uA. + * | | |10 = Max propagation delay is 600nS, operation current is 10uA. + * | | |11 = Max propagation delay is 200nS, operation current is 75uA. + * @var ACMP_T::STATUS + * Offset: 0x08 Analog Comparator Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ACMPIF0 |Comparator 0 Interrupt Flag + * | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8]) is detected on comparator 0 output. + * | | |This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1. + * | | |Note: Write 1 to clear this bit to 0. + * |[1] |ACMPIF1 |Comparator 1 Interrupt Flag + * | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8]) is detected on comparator 1 output. + * | | |This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1. + * | | |Note: Write 1 to clear this bit to 0. + * |[4] |ACMPO0 |Comparator 0 Output + * | | |Synchronized to the PCLK to allow reading by software. + * | | |Cleared when the comparator 0 is disabled, i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0. + * |[5] |ACMPO1 |Comparator 1 Output + * | | |Synchronized to the PCLK to allow reading by software. + * | | |Cleared when the comparator 1 is disabled, i.e. ACMPEN (ACMP_CTL1[0]) is cleared to 0. + * |[8] |WKIF0 |Comparator 0 Power-down Wake-up Interrupt Flag + * | | |This bit will be set to 1 when ACMP0 wake-up interrupt event occurs. + * | | |0 = No power-down wake-up occurred. + * | | |1 = Power-down wake-up occurred. + * | | |Note: Write 1 to clear this bit to 0. + * |[9] |WKIF1 |Comparator 1 Power-down Wake-up Interrupt Flag + * | | |This bit will be set to 1 when ACMP1 wake-up interrupt event occurs. + * | | |0 = No power-down wake-up occurred. + * | | |1 = Power-down wake-up occurred. + * | | |Note: Write 1 to clear this bit to 0. + * |[12] |ACMPS0 |Comparator 0 Status + * | | |Synchronized to the PCLK to allow reading by software. + * | | |Cleared when the comparator 0 is disabled, i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0. + * |[13] |ACMPS1 |Comparator 1 Status + * | | |Synchronized to the PCLK to allow reading by software + * | | |Cleared when the comparator 1 is disabled, i.e. ACMPEN (ACMP_CTL1[0]) is cleared to 0. + * |[16] |ACMPWO |Comparator Window Output + * | | |This bit shows the output status of window compare mode + * | | |0 = The positive input voltage is outside the window. + * | | |1 = The positive input voltage is in the window. + * @var ACMP_T::VREF + * Offset: 0x0C Analog Comparator Reference Voltage Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |CRVCTL |Comparator Reference Voltage Setting + * | | |CRV = CRV source voltage * (1/6+CRVCTL/24). + * |[6] |CRVSSEL |CRV Source Voltage Selection + * | | |0 = AVDD is selected as CRV source voltage. + * | | |1 = The reference voltage defined by SYS_VREFCTL register is selected as CRV source voltage. + */ + __IO uint32_t CTL[2]; /*!< [0x0000~0x0004] Analog Comparator 0/1 Control Register */ + __IO uint32_t STATUS; /*!< [0x0008] Analog Comparator Status Register */ + __IO uint32_t VREF; /*!< [0x000c] Analog Comparator Reference Voltage Control Register */ + +} ACMP_T; + +/** + @addtogroup ACMP_CONST ACMP Bit Field Definition + Constant Definitions for ACMP Controller +@{ */ + +#define ACMP_CTL_ACMPEN_Pos (0) /*!< ACMP_T::CTL: ACMPEN Position */ +#define ACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos) /*!< ACMP_T::CTL: ACMPEN Mask */ + +#define ACMP_CTL_ACMPIE_Pos (1) /*!< ACMP_T::CTL: ACMPIE Position */ +#define ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos) /*!< ACMP_T::CTL: ACMPIE Mask */ + +#define ACMP_CTL_ACMPOINV_Pos (3) /*!< ACMP_T::CTL: ACMPOINV Position */ +#define ACMP_CTL_ACMPOINV_Msk (0x1ul << ACMP_CTL_ACMPOINV_Pos) /*!< ACMP_T::CTL: ACMPOINV Mask */ + +#define ACMP_CTL_NEGSEL_Pos (4) /*!< ACMP_T::CTL: NEGSEL Position */ +#define ACMP_CTL_NEGSEL_Msk (0x3ul << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_T::CTL: NEGSEL Mask */ + +#define ACMP_CTL_POSSEL_Pos (6) /*!< ACMP_T::CTL: POSSEL Position */ +#define ACMP_CTL_POSSEL_Msk (0x3ul << ACMP_CTL_POSSEL_Pos) /*!< ACMP_T::CTL: POSSEL Mask */ + +#define ACMP_CTL_INTPOL_Pos (8) /*!< ACMP_T::CTL: INTPOL Position */ +#define ACMP_CTL_INTPOL_Msk (0x3ul << ACMP_CTL_INTPOL_Pos) /*!< ACMP_T::CTL: INTPOL Mask */ + +#define ACMP_CTL_OUTSEL_Pos (12) /*!< ACMP_T::CTL: OUTSEL Position */ +#define ACMP_CTL_OUTSEL_Msk (0x1ul << ACMP_CTL_OUTSEL_Pos) /*!< ACMP_T::CTL: OUTSEL Mask */ + +#define ACMP_CTL_FILTSEL_Pos (13) /*!< ACMP_T::CTL: FILTSEL Position */ +#define ACMP_CTL_FILTSEL_Msk (0x7ul << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_T::CTL: FILTSEL Mask */ + +#define ACMP_CTL_WKEN_Pos (16) /*!< ACMP_T::CTL: WKEN Position */ +#define ACMP_CTL_WKEN_Msk (0x1ul << ACMP_CTL_WKEN_Pos) /*!< ACMP_T::CTL: WKEN Mask */ + +#define ACMP_CTL_WLATEN_Pos (17) /*!< ACMP_T::CTL: WLATEN Position */ +#define ACMP_CTL_WLATEN_Msk (0x1ul << ACMP_CTL_WLATEN_Pos) /*!< ACMP_T::CTL: WLATEN Mask */ + +#define ACMP_CTL_WCMPSEL_Pos (18) /*!< ACMP_T::CTL: WCMPSEL Position */ +#define ACMP_CTL_WCMPSEL_Msk (0x1ul << ACMP_CTL_WCMPSEL_Pos) /*!< ACMP_T::CTL: WCMPSEL Mask */ + +#define ACMP_CTL_HYSSEL_Pos (24) /*!< ACMP_T::CTL: HYSSEL Position */ +#define ACMP_CTL_HYSSEL_Msk (0x3ul << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_T::CTL: HYSSEL Mask */ + +#define ACMP_CTL_MODESEL_Pos (28) /*!< ACMP_T::CTL: MODESEL Position */ +#define ACMP_CTL_MODESEL_Msk (0x3ul << ACMP_CTL_MODESEL_Pos) /*!< ACMP_T::CTL: MODESEL Mask */ + +#define ACMP_STATUS_ACMPIF0_Pos (0) /*!< ACMP_T::STATUS: ACMPIF0 Position */ +#define ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos) /*!< ACMP_T::STATUS: ACMPIF0 Mask */ + +#define ACMP_STATUS_ACMPIF1_Pos (1) /*!< ACMP_T::STATUS: ACMPIF1 Position */ +#define ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos) /*!< ACMP_T::STATUS: ACMPIF1 Mask */ + +#define ACMP_STATUS_ACMPO0_Pos (4) /*!< ACMP_T::STATUS: ACMPO0 Position */ +#define ACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos) /*!< ACMP_T::STATUS: ACMPO0 Mask */ + +#define ACMP_STATUS_ACMPO1_Pos (5) /*!< ACMP_T::STATUS: ACMPO1 Position */ +#define ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos) /*!< ACMP_T::STATUS: ACMPO1 Mask */ + +#define ACMP_STATUS_WKIF0_Pos (8) /*!< ACMP_T::STATUS: WKIF0 Position */ +#define ACMP_STATUS_WKIF0_Msk (0x1ul << ACMP_STATUS_WKIF0_Pos) /*!< ACMP_T::STATUS: WKIF0 Mask */ + +#define ACMP_STATUS_WKIF1_Pos (9) /*!< ACMP_T::STATUS: WKIF1 Position */ +#define ACMP_STATUS_WKIF1_Msk (0x1ul << ACMP_STATUS_WKIF1_Pos) /*!< ACMP_T::STATUS: WKIF1 Mask */ + +#define ACMP_STATUS_ACMPS0_Pos (12) /*!< ACMP_T::STATUS: ACMPS0 Position */ +#define ACMP_STATUS_ACMPS0_Msk (0x1ul << ACMP_STATUS_ACMPS0_Pos) /*!< ACMP_T::STATUS: ACMPS0 Mask */ + +#define ACMP_STATUS_ACMPS1_Pos (13) /*!< ACMP_T::STATUS: ACMPS1 Position */ +#define ACMP_STATUS_ACMPS1_Msk (0x1ul << ACMP_STATUS_ACMPS1_Pos) /*!< ACMP_T::STATUS: ACMPS1 Mask */ + +#define ACMP_STATUS_ACMPWO_Pos (16) /*!< ACMP_T::STATUS: ACMPWO Position */ +#define ACMP_STATUS_ACMPWO_Msk (0x1ul << ACMP_STATUS_ACMPWO_Pos) /*!< ACMP_T::STATUS: ACMPWO Mask */ + +#define ACMP_VREF_CRVCTL_Pos (0) /*!< ACMP_T::VREF: CRVCTL Position */ +#define ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos) /*!< ACMP_T::VREF: CRVCTL Mask */ + +#define ACMP_VREF_CRVSSEL_Pos (6) /*!< ACMP_T::VREF: CRVSSEL Position */ +#define ACMP_VREF_CRVSSEL_Msk (0x1ul << ACMP_VREF_CRVSSEL_Pos) /*!< ACMP_T::VREF: CRVSSEL Mask */ + + +/**@}*/ /* ACMP_CONST */ +/**@}*/ /* end of ACMP register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __ACMP_REG_H__ */ \ No newline at end of file diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/bpwm_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/bpwm_reg.h new file mode 100644 index 00000000000..4a3411e8a00 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/bpwm_reg.h @@ -0,0 +1,1742 @@ +/**************************************************************************//** + * @file bpwm_reg.h + * @version V1.00 + * @brief BPWM register definition header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __BPWM_REG_H__ +#define __BPWM_REG_H__ + + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup BPWM Basic Pulse Width Modulation Controller (BPWM) + Memory Mapped Structure for BPWM Controller +@{ */ +typedef struct +{ + /** + * @var BCAPDAT_T::RCAPDAT + * Offset: 0x20C~0x238 BPWM Rising Capture Data Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RCAPDAT |BPWM Rising Capture Data (Read Only) + * | | |When rising capture condition happened, the BPWM counter value will be saved in this register. + * @var BCAPDAT_T::FCAPDAT + * Offset: 0x210 BPWM Falling Capture Data Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FCAPDAT |BPWM Falling Capture Data (Read Only) + * | | |When falling capture condition happened, the BPWM counter value will be saved in this register. + */ + __IO uint32_t RCAPDAT; /*!< [0x20C/0x214/0x21C/0x224/0x22C/0x234] BPWM Rising Capture Data Register 0~5 */ + __IO uint32_t FCAPDAT; /*!< [0x210/0x218/0x220/0x228/0x230/0x238] BPWM Falling Capture Data Register 0~5 */ +} BCAPDAT_T; + +typedef struct +{ + + + /** + * @var BPWM_T::CTL0 + * Offset: 0x00 BPWM Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CTRLD0 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[1] |CTRLD1 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[2] |CTRLD2 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[3] |CTRLD3 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[4] |CTRLD4 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[5] |CTRLD5 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[16] |IMMLDEN0 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[17] |IMMLDEN1 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[18] |IMMLDEN2 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[19] |IMMLDEN3 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[20] |IMMLDEN4 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[21] |IMMLDEN5 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect) + * | | |If counter halt is enabled, BPWM all counters will keep current value until exit ICE debug mode. + * | | |0 = ICE debug mode counter halt Disabled. + * | | |1 = ICE debug mode counter halt Enabled. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable (Write Protect) + * | | |0 = ICE debug mode acknowledgement effects BPWM output. + * | | |BPWM pin will be forced as tri-state while ICE debug mode acknowledged. + * | | |1 = ICE debug mode acknowledgement Disabled. + * | | |BPWM pin will keep output no matter ICE debug mode acknowledged or not. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * @var BPWM_T::CTL1 + * Offset: 0x04 BPWM Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CNTTYPE0 |BPWM Counter Behavior Type 0 + * | | |Each bit n controls corresponding BPWM channel n. + * | | |00 = Up counter type (supports in capture mode). + * | | |01 = Down count type (supports in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * @var BPWM_T::CLKSRC + * Offset: 0x10 BPWM Clock Source Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |ECLKSRC0 |BPWM_CH01 External Clock Source Select + * | | |000 = BPWMx_CLK, x denotes 0 or 1. + * | | |001 = TIMER0 overflow. + * | | |010 = TIMER1 overflow. + * | | |011 = TIMER2 overflow. + * | | |100 = TIMER3 overflow. + * | | |Others = Reserved. + * @var BPWM_T::CLKPSC + * Offset: 0x14 BPWM Clock Prescale Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CLKPSC |BPWM Counter Clock Prescale + * | | |The clock of BPWM counter is decided by clock prescaler + * | | |Each BPWM pair share one BPWM counter clock prescaler + * | | |The clock of BPWM counter is divided by (CLKPSC+ 1) + * @var BPWM_T::CNTEN + * Offset: 0x20 BPWM Counter Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTEN0 |BPWM Counter 0 Enable Bit + * | | |0 = BPWM Counter and clock prescaler stop running. + * | | |1 = BPWM Counter and clock prescaler start running. + * @var BPWM_T::CNTCLR + * Offset: 0x24 BPWM Clear Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTCLR0 |Clear BPWM Counter Control Bit 0 + * | | |It is automatically cleared by hardware. + * | | |0 = No effect. + * | | |1 = Clear 16-bit BPWM counter to 0000H. + * @var BPWM_T::PERIOD + * Offset: 0x30 BPWM Period Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PERIOD |BPWM Period Register + * | | |Up-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, and restarts from 0. + * | | |Down-Count mode: In this mode, BPWM counter counts from PERIOD to 0, and restarts from PERIOD. + * | | |BPWM period time = (PERIOD+1) * BPWM_CLK period. + * | | |Up-Down-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again. + * | | |BPWM period time = 2 * PERIOD * BPWM_CLK period. + * @var BPWM_T::CMPDAT[6] + * Offset: 0x50~0x64 BPWM Comparator Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMPDAT |BPWM Comparator Register + * | | |CMPDAT use to compare with CNTR to generate BPWM waveform, interrupt and trigger EADC. + * | | |In independent mode, CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point. + * @var BPWM_T::CNT + * Offset: 0x90 BPWM Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CNT |BPWM Data Register (Read Only) + * | | |User can monitor CNTR to know the current value in 16-bit period counter. + * |[16] |DIRF |BPWM Direction Indicator Flag (Read Only) + * | | |0 = Counter is Down count. + * | | |1 = Counter is UP count. + * @var BPWM_T::WGCTL0 + * Offset: 0xB0 BPWM Generation Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |ZPCTL0 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[3:2] |ZPCTL1 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[5:4] |ZPCTL2 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[7:6] |ZPCTL3 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[9:8] |ZPCTL4 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[11:10] |ZPCTL5 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[17:16] |PRDPCTL0 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * |[19:18] |PRDPCTL1 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * |[21:20] |PRDPCTL2 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * |[23:22] |PRDPCTL3 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * |[25:24] |PRDPCTL4 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * |[27:26] |PRDPCTL5 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * @var BPWM_T::WGCTL1 + * Offset: 0xB4 BPWM Generation Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CMPUCTL0 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[3:2] |CMPUCTL1 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[5:4] |CMPUCTL2 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[7:6] |CMPUCTL3 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[9:8] |CMPUCTL4 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[11:10] |CMPUCTL5 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[17:16] |CMPDCTL0 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * |[19:18] |CMPDCTL1 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * |[21:20] |CMPDCTL2 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * |[23:22] |CMPDCTL3 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * |[25:24] |CMPDCTL4 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * |[27:26] |CMPDCTL5 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * @var BPWM_T::MSKEN + * Offset: 0xB8 BPWM Mask Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKEN0 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * |[1] |MSKEN1 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * |[2] |MSKEN2 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * |[3] |MSKEN3 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * |[4] |MSKEN4 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * |[5] |MSKEN5 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * @var BPWM_T::MSK + * Offset: 0xBC BPWM Mask Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKDAT0 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * |[1] |MSKDAT1 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * |[2] |MSKDAT2 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * |[3] |MSKDAT3 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * |[4] |MSKDAT4 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * |[5] |MSKDAT5 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * @var BPWM_T::POLCTL + * Offset: 0xD4 BPWM Pin Polar Inverse Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PINV0 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * |[1] |PINV1 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * |[2] |PINV2 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * |[3] |PINV3 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * |[4] |PINV4 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * |[5] |PINV5 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * @var BPWM_T::POEN + * Offset: 0xD8 BPWM Output Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |POEN0 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * |[1] |POEN1 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * |[2] |POEN2 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * |[3] |POEN3 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * |[4] |POEN4 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * |[5] |POEN5 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * @var BPWM_T::INTEN + * Offset: 0xE0 BPWM Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIEN0 |BPWM Zero Point Interrupt 0 Enable Bit + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * |[8] |PIEN0 |BPWM Period Point Interrupt 0 Enable Bit + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note: When up-down counter type period point means center point. + * |[16] |CMPUIEN0 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[17] |CMPUIEN1 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[18] |CMPUIEN2 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[19] |CMPUIEN3 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[20] |CMPUIEN4 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[21] |CMPUIEN5 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[24] |CMPDIEN0 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * |[25] |CMPDIEN1 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * |[26] |CMPDIEN2 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * |[27] |CMPDIEN3 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * |[28] |CMPDIEN4 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * |[29] |CMPDIEN5 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * @var BPWM_T::INTSTS + * Offset: 0xE8 BPWM Interrupt Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIF0 |BPWM Zero Point Interrupt Flag 0 + * | | |This bit is set by hardware when BPWM_CH0 counter reaches 0, software can write 1 to clear this bit to 0. + * |[8] |PIF0 |BPWM Period Point Interrupt Flag 0 + * | | |This bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0, software can write 1 to clear this bit to 0. + * |[16] |CMPUIF0 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[17] |CMPUIF1 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[18] |CMPUIF2 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[19] |CMPUIF3 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[20] |CMPUIF4 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[21] |CMPUIF5 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[24] |CMPDIF0 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * |[25] |CMPDIF1 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * |[26] |CMPDIF2 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * |[27] |CMPDIF3 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * |[28] |CMPDIF4 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * |[29] |CMPDIF5 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * @var BPWM_T::EADCTS0 + * Offset: 0xF8 BPWM Trigger EADC Source Select Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |TRGSEL0 |BPWM_CH0 Trigger EADC Source Select + * | | |0000 = BPWM_CH0 zero point. + * | | |0001 = BPWM_CH0 period point. + * | | |0010 = BPWM_CH0 zero or period point. + * | | |0011 = BPWM_CH0 up-count CMPDAT point. + * | | |0100 = BPWM_CH0 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH1 up-count CMPDAT point. + * | | |1001 = BPWM_CH1 down-count CMPDAT point. + * | | |Others reserved + * |[7] |TRGEN0 |BPWM_CH0 Trigger EADC Enable Bit + * |[11:8] |TRGSEL1 |BPWM_CH1 Trigger EADC Source Select + * | | |0000 = BPWM_CH0 zero point. + * | | |0001 = BPWM_CH0 period point. + * | | |0010 = BPWM_CH0 zero or period point. + * | | |0011 = BPWM_CH0 up-count CMPDAT point. + * | | |0100 = BPWM_CH0 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH1 up-count CMPDAT point. + * | | |1001 = BPWM_CH1 down-count CMPDAT point. + * | | |Others reserved + * |[15] |TRGEN1 |BPWM_CH1 Trigger EADC Enable Bit + * |[19:16] |TRGSEL2 |BPWM_CH2 Trigger EADC Source Select + * | | |0000 = BPWM_CH2 zero point. + * | | |0001 = BPWM_CH2 period point. + * | | |0010 = BPWM_CH2 zero or period point. + * | | |0011 = BPWM_CH2 up-count CMPDAT point. + * | | |0100 = BPWM_CH2 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH3 up-count CMPDAT point. + * | | |1001 = BPWM_CH3 down-count CMPDAT point. + * | | |Others reserved + * |[23] |TRGEN2 |BPWM_CH2 Trigger EADC Enable Bit + * |[27:24] |TRGSEL3 |BPWM_CH3 Trigger EADC Source Select + * | | |0000 = BPWM_CH2 zero point. + * | | |0001 = BPWM_CH2 period point. + * | | |0010 = BPWM_CH2 zero or period point. + * | | |0011 = BPWM_CH2 up-count CMPDAT point. + * | | |0100 = BPWM_CH2 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH3 up-count CMPDAT point. + * | | |1001 = BPWM_CH3 down-count CMPDAT point. + * | | |Others reserved. + * |[31] |TRGEN3 |BPWM_CH3 Trigger EADC Enable Bit + * @var BPWM_T::EADCTS1 + * Offset: 0xFC BPWM Trigger EADC Source Select Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |TRGSEL4 |BPWM_CH4 Trigger EADC Source Select + * | | |0000 = BPWM_CH4 zero point. + * | | |0001 = BPWM_CH4 period point. + * | | |0010 = BPWM_CH4 zero or period point. + * | | |0011 = BPWM_CH4 up-count CMPDAT point. + * | | |0100 = BPWM_CH4 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH5 up-count CMPDAT point. + * | | |1001 = BPWM_CH5 down-count CMPDAT point. + * | | |Others reserved + * |[7] |TRGEN4 |BPWM_CH4 Trigger EADC Enable Bit + * |[11:8] |TRGSEL5 |BPWM_CH5 Trigger EADC Source Select + * | | |0000 = BPWM_CH4 zero point. + * | | |0001 = BPWM_CH4 period point. + * | | |0010 = BPWM_CH4 zero or period point. + * | | |0011 = BPWM_CH4 up-count CMPDAT point. + * | | |0100 = BPWM_CH4 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH5 up-count CMPDAT point. + * | | |1001 = BPWM_CH5 down-count CMPDAT point. + * | | |Others reserved + * |[15] |TRGEN5 |BPWM_CH5 Trigger EADC Enable Bit + * @var BPWM_T::SSCTL + * Offset: 0x110 BPWM Synchronous Start Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SSEN0 |BPWM Synchronous Start Function 0 Enable Bit + * | | |When synchronous start function is enabled, the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN). + * | | |0 = BPWM synchronous start function Disabled. + * | | |1 = BPWM synchronous start function Enabled. + * |[9:8] |SSRC |BPWM Synchronous Start Source Select + * | | |00 = Synchronous start source come from PWM0. + * | | |01 = Synchronous start source come from PWM1. + * | | |10 = Synchronous start source come from BPWM0. + * | | |11 = Synchronous start source come from BPWM1. + * @var BPWM_T::SSTRG + * Offset: 0x114 BPWM Synchronous Start Trigger Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTSEN |BPWM Counter Synchronous Start Enable Bit(Write Only) + * | | |BPMW counter synchronous enable function is used to make PWM or BPWM channels start counting at the same time. + * | | |Writing this bit to 1 will also set the counter enable bit if correlated BPWM channel counter synchronous start function is enabled. + * @var BPWM_T::STATUS + * Offset: 0x120 BPWM Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTMAX0 |Time-base Counter 0 Equal to 0xFFFF Latched Status + * | | |0 = The time-base counter never reached its maximum value 0xFFFF. + * | | |1 = The time-base counter reached its maximum value. Software can write 1 to clear this bit. + * |[16] |EADCTRG0 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = No EADC start of conversion trigger event has occurred. + * | | |1 = An EADC start of conversion trigger event has occurred. Software can write 1 to clear this bit. + * |[17] |EADCTRG1 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = No EADC start of conversion trigger event has occurred. + * | | |1 = An EADC start of conversion trigger event has occurred. Software can write 1 to clear this bit. + * |[18] |EADCTRG2 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = No EADC start of conversion trigger event has occurred. + * | | |1 = An EADC start of conversion trigger event has occurred. Software can write 1 to clear this bit. + * |[19] |EADCTRG3 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = No EADC start of conversion trigger event has occurred. + * | | |1 = An EADC start of conversion trigger event has occurred. Software can write 1 to clear this bit. + * |[20] |EADCTRG4 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = No EADC start of conversion trigger event has occurred. + * | | |1 = An EADC start of conversion trigger event has occurred. Software can write 1 to clear this bit. + * |[21] |EADCTRG5 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = No EADC start of conversion trigger event has occurred. + * | | |1 = An EADC start of conversion trigger event has occurred. Software can write 1 to clear this bit. + * @var BPWM_T::CAPINEN + * Offset: 0x200 BPWM Capture Input Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPINEN0 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * |[1] |CAPINEN1 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * |[2] |CAPINEN2 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * |[3] |CAPINEN3 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * |[4] |CAPINEN4 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * |[5] |CAPINEN5 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * @var BPWM_T::CAPCTL + * Offset: 0x204 BPWM Capture Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPEN0 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[1] |CAPEN1 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[2] |CAPEN2 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[3] |CAPEN3 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[4] |CAPEN4 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[5] |CAPEN5 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[8] |CAPINV0 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[9] |CAPINV1 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[10] |CAPINV2 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[11] |CAPINV3 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[12] |CAPINV4 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[13] |CAPINV5 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[16] |RCRLDEN0 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[17] |RCRLDEN1 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[18] |RCRLDEN2 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[19] |RCRLDEN3 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[20] |RCRLDEN4 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[21] |RCRLDEN5 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[24] |FCRLDEN0 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[25] |FCRLDEN1 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[26] |FCRLDEN2 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[27] |FCRLDEN3 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[28] |FCRLDEN4 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[29] |FCRLDEN5 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * @var BPWM_T::CAPSTS + * Offset: 0x208 BPWM Capture Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CRIFOV0 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[1] |CRIFOV1 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[2] |CRIFOV2 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[3] |CRIFOV3 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[4] |CRIFOV4 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[5] |CRIFOV5 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[8] |CFIFOV0 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * |[9] |CFIFOV1 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * |[10] |CFIFOV2 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * |[11] |CFIFOV3 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * |[12] |CFIFOV4 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * |[13] |CFIFOV5 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * @var BPWM_T::CAPIEN + * Offset: 0x250 BPWM Capture Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |CAPRIENn |BPWM Capture Rising Latch Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[13:8] |CAPFIENn |BPWM Capture Falling Latch Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * @var BPWM_T::CAPIF + * Offset: 0x254 BPWM Capture Interrupt Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPRIF0 |BPWM Capture Rising Latch Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note: This bit is cleared by writing 1 to it. + * |[1] |CAPRIF1 |BPWM Capture Rising Latch Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note: This bit is cleared by writing 1 to it. + * |[2] |CAPRIF2 |BPWM Capture Rising Latch Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note: This bit is cleared by writing 1 to it. + * |[3] |CAPRIF3 |BPWM Capture Rising Latch Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note: This bit is cleared by writing 1 to it. + * |[4] |CAPRIF4 |BPWM Capture Rising Latch Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note: This bit is cleared by writing 1 to it. + * |[5] |CAPRIF5 |BPWM Capture Rising Latch Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note: This bit is cleared by writing 1 to it. + * |[8] |CAPFIF0 |BPWM Capture Falling Latch Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note: This bit is cleared by writing 1 to it. + * |[9] |CAPFIF1 |BPWM Capture Falling Latch Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note: This bit is cleared by writing 1 to it. + * |[10] |CAPFIF2 |BPWM Capture Falling Latch Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note: This bit is cleared by writing 1 to it. + * |[11] |CAPFIF3 |BPWM Capture Falling Latch Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note: This bit is cleared by writing 1 to it. + * |[12] |CAPFIF4 |BPWM Capture Falling Latch Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note: This bit is cleared by writing 1 to it. + * |[13] |CAPFIF5 |BPWM Capture Falling Latch Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note: This bit is cleared by writing 1 to it. + * @var BPWM_T::PBUF + * Offset: 0x304 BPWM PERIOD Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PBUF |BPWM Period Buffer (Read Only) + * | | |Used as PERIOD active register. + * @var BPWM_T::CMPBUF[6] + * Offset: 0x31C~0x330 BPWM CMPDAT 0~5 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMPBUF |BPWM Comparator Buffer (Read Only) + * | | |Used as CMP active register. + */ + __IO uint32_t CTL0; /*!< [0x0000] BPWM Control Register 0 */ + __IO uint32_t CTL1; /*!< [0x0004] BPWM Control Register 1 */ + __I uint32_t RESERVE0[2]; + __IO uint32_t CLKSRC; /*!< [0x0010] BPWM Clock Source Register */ + __IO uint32_t CLKPSC; /*!< [0x0014] BPWM Clock Prescale Register */ + __I uint32_t RESERVE1[2]; + __IO uint32_t CNTEN; /*!< [0x0020] BPWM Counter Enable Register */ + __IO uint32_t CNTCLR; /*!< [0x0024] BPWM Clear Counter Register */ + __I uint32_t RESERVE2[2]; + __IO uint32_t PERIOD; /*!< [0x0030] BPWM Period Register */ + __I uint32_t RESERVE3[7]; + __IO uint32_t CMPDAT[6]; /*!< [0x0050 ~ 0x0064] BPWM Comparator Register 0 ~ 6 */ + __I uint32_t RESERVE4[10]; + __I uint32_t CNT; /*!< [0x0090] BPWM Counter Register */ + __I uint32_t RESERVE5[7]; + __IO uint32_t WGCTL0; /*!< [0x00b0] BPWM Generation Register 0 */ + __IO uint32_t WGCTL1; /*!< [0x00b4] BPWM Generation Register 1 */ + __IO uint32_t MSKEN; /*!< [0x00b8] BPWM Mask Enable Register */ + __IO uint32_t MSK; /*!< [0x00bc] BPWM Mask Data Register */ + __I uint32_t RESERVE6[5]; + __IO uint32_t POLCTL; /*!< [0x00d4] BPWM Pin Polar Inverse Register */ + __IO uint32_t POEN; /*!< [0x00d8] BPWM Output Enable Register */ + __I uint32_t RESERVE7[1]; + __IO uint32_t INTEN; /*!< [0x00e0] BPWM Interrupt Enable Register */ + __I uint32_t RESERVE8[1]; + __IO uint32_t INTSTS; /*!< [0x00e8] BPWM Interrupt Flag Register */ + __I uint32_t RESERVE9[3]; + __IO uint32_t EADCTS0; /*!< [0x00f8] BPWM Trigger EADC Source Select Register 0 */ + __IO uint32_t EADCTS1; /*!< [0x00fc] BPWM Trigger EADC Source Select Register 1 */ + __I uint32_t RESERVE10[4]; + __IO uint32_t SSCTL; /*!< [0x0110] BPWM Synchronous Start Control Register */ + __O uint32_t SSTRG; /*!< [0x0114] BPWM Synchronous Start Trigger Register */ + __I uint32_t RESERVE11[2]; + __IO uint32_t STATUS; /*!< [0x0120] BPWM Status Register */ + __I uint32_t RESERVE12[55]; + __IO uint32_t CAPINEN; /*!< [0x0200] BPWM Capture Input Enable Register */ + __IO uint32_t CAPCTL; /*!< [0x0204] BPWM Capture Control Register */ + __I uint32_t CAPSTS; /*!< [0x0208] BPWM Capture Status Register */ + BCAPDAT_T CAPDAT[6]; /*!< [0x020C ~ 0x0238] BPWM Rising and Falling Capture Data Register 0~5 */ + __I uint32_t RESERVE13[5]; + __IO uint32_t CAPIEN; /*!< [0x0250] BPWM Capture Interrupt Enable Register */ + __IO uint32_t CAPIF; /*!< [0x0254] BPWM Capture Interrupt Flag Register */ + __I uint32_t RESERVE14[43]; + __I uint32_t PBUF; /*!< [0x0304] BPWM PERIOD Buffer */ + __I uint32_t RESERVE15[5]; + __I uint32_t CMPBUF[6]; /*!< [0x031c ~ 0x0330] BPWM CMPDAT 0 ~ 5 Buffer */ + +} BPWM_T; + +/** + @addtogroup BPWM_CONST BPWM Bit Field Definition + Constant Definitions for BPWM Controller +@{ */ + +#define BPWM_CTL0_CTRLD0_Pos (0) /*!< BPWM_T::CTL0: CTRLD0 Position */ +#define BPWM_CTL0_CTRLD0_Msk (0x1ul << BPWM_CTL0_CTRLD0_Pos) /*!< BPWM_T::CTL0: CTRLD0 Mask */ + +#define BPWM_CTL0_CTRLD1_Pos (1) /*!< BPWM_T::CTL0: CTRLD1 Position */ +#define BPWM_CTL0_CTRLD1_Msk (0x1ul << BPWM_CTL0_CTRLD1_Pos) /*!< BPWM_T::CTL0: CTRLD1 Mask */ + +#define BPWM_CTL0_CTRLD2_Pos (2) /*!< BPWM_T::CTL0: CTRLD2 Position */ +#define BPWM_CTL0_CTRLD2_Msk (0x1ul << BPWM_CTL0_CTRLD2_Pos) /*!< BPWM_T::CTL0: CTRLD2 Mask */ + +#define BPWM_CTL0_CTRLD3_Pos (3) /*!< BPWM_T::CTL0: CTRLD3 Position */ +#define BPWM_CTL0_CTRLD3_Msk (0x1ul << BPWM_CTL0_CTRLD3_Pos) /*!< BPWM_T::CTL0: CTRLD3 Mask */ + +#define BPWM_CTL0_CTRLD4_Pos (4) /*!< BPWM_T::CTL0: CTRLD4 Position */ +#define BPWM_CTL0_CTRLD4_Msk (0x1ul << BPWM_CTL0_CTRLD4_Pos) /*!< BPWM_T::CTL0: CTRLD4 Mask */ + +#define BPWM_CTL0_CTRLD5_Pos (5) /*!< BPWM_T::CTL0: CTRLD5 Position */ +#define BPWM_CTL0_CTRLD5_Msk (0x1ul << BPWM_CTL0_CTRLD5_Pos) /*!< BPWM_T::CTL0: CTRLD5 Mask */ + +#define BPWM_CTL0_IMMLDEN0_Pos (16) /*!< BPWM_T::CTL0: IMMLDEN0 Position */ +#define BPWM_CTL0_IMMLDEN0_Msk (0x1ul << BPWM_CTL0_IMMLDEN0_Pos) /*!< BPWM_T::CTL0: IMMLDEN0 Mask */ + +#define BPWM_CTL0_IMMLDEN1_Pos (17) /*!< BPWM_T::CTL0: IMMLDEN1 Position */ +#define BPWM_CTL0_IMMLDEN1_Msk (0x1ul << BPWM_CTL0_IMMLDEN1_Pos) /*!< BPWM_T::CTL0: IMMLDEN1 Mask */ + +#define BPWM_CTL0_IMMLDEN2_Pos (18) /*!< BPWM_T::CTL0: IMMLDEN2 Position */ +#define BPWM_CTL0_IMMLDEN2_Msk (0x1ul << BPWM_CTL0_IMMLDEN2_Pos) /*!< BPWM_T::CTL0: IMMLDEN2 Mask */ + +#define BPWM_CTL0_IMMLDEN3_Pos (19) /*!< BPWM_T::CTL0: IMMLDEN3 Position */ +#define BPWM_CTL0_IMMLDEN3_Msk (0x1ul << BPWM_CTL0_IMMLDEN3_Pos) /*!< BPWM_T::CTL0: IMMLDEN3 Mask */ + +#define BPWM_CTL0_IMMLDEN4_Pos (20) /*!< BPWM_T::CTL0: IMMLDEN4 Position */ +#define BPWM_CTL0_IMMLDEN4_Msk (0x1ul << BPWM_CTL0_IMMLDEN4_Pos) /*!< BPWM_T::CTL0: IMMLDEN4 Mask */ + +#define BPWM_CTL0_IMMLDEN5_Pos (21) /*!< BPWM_T::CTL0: IMMLDEN5 Position */ +#define BPWM_CTL0_IMMLDEN5_Msk (0x1ul << BPWM_CTL0_IMMLDEN5_Pos) /*!< BPWM_T::CTL0: IMMLDEN5 Mask */ + +#define BPWM_CTL0_DBGHALT_Pos (30) /*!< BPWM_T::CTL0: DBGHALT Position */ +#define BPWM_CTL0_DBGHALT_Msk (0x1ul << BPWM_CTL0_DBGHALT_Pos) /*!< BPWM_T::CTL0: DBGHALT Mask */ + +#define BPWM_CTL0_DBGTRIOFF_Pos (31) /*!< BPWM_T::CTL0: DBGTRIOFF Position */ +#define BPWM_CTL0_DBGTRIOFF_Msk (0x1ul << BPWM_CTL0_DBGTRIOFF_Pos) /*!< BPWM_T::CTL0: DBGTRIOFF Mask */ + +#define BPWM_CTL1_CNTTYPE0_Pos (0) /*!< BPWM_T::CTL1: CNTTYPE0 Position */ +#define BPWM_CTL1_CNTTYPE0_Msk (0x3ul << BPWM_CTL1_CNTTYPE0_Pos) /*!< BPWM_T::CTL1: CNTTYPE0 Mask */ + +#define BPWM_CLKSRC_ECLKSRC0_Pos (0) /*!< BPWM_T::CLKSRC: ECLKSRC0 Position */ +#define BPWM_CLKSRC_ECLKSRC0_Msk (0x7ul << BPWM_CLKSRC_ECLKSRC0_Pos) /*!< BPWM_T::CLKSRC: ECLKSRC0 Mask */ + +#define BPWM_CLKPSC_CLKPSC_Pos (0) /*!< BPWM_T::CLKPSC: CLKPSC Position */ +#define BPWM_CLKPSC_CLKPSC_Msk (0xffful << BPWM_CLKPSC_CLKPSC_Pos) /*!< BPWM_T::CLKPSC: CLKPSC Mask */ + +#define BPWM_CNTEN_CNTEN0_Pos (0) /*!< BPWM_T::CNTEN: CNTEN0 Position */ +#define BPWM_CNTEN_CNTEN0_Msk (0x1ul << BPWM_CNTEN_CNTEN0_Pos) /*!< BPWM_T::CNTEN: CNTEN0 Mask */ + +#define BPWM_CNTCLR_CNTCLR0_Pos (0) /*!< BPWM_T::CNTCLR: CNTCLR0 Position */ +#define BPWM_CNTCLR_CNTCLR0_Msk (0x1ul << BPWM_CNTCLR_CNTCLR0_Pos) /*!< BPWM_T::CNTCLR: CNTCLR0 Mask */ + +#define BPWM_PERIOD_PERIOD_Pos (0) /*!< BPWM_T::PERIOD: PERIOD Position */ +#define BPWM_PERIOD_PERIOD_Msk (0xfffful << BPWM_PERIOD_PERIOD_Pos) /*!< BPWM_T::PERIOD: PERIOD Mask */ + +#define BPWM_CMPDAT_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT0: CMPDAT Position */ +#define BPWM_CMPDAT_CMPDAT_Msk (0xfffful << BPWM_CMPDAT_CMPDAT_Pos) /*!< BPWM_T::CMPDAT0: CMPDAT Mask */ + +#define BPWM_CNT_CNT_Pos (0) /*!< BPWM_T::CNT: CNT Position */ +#define BPWM_CNT_CNT_Msk (0xfffful << BPWM_CNT_CNT_Pos) /*!< BPWM_T::CNT: CNT Mask */ + +#define BPWM_CNT_DIRF_Pos (16) /*!< BPWM_T::CNT: DIRF Position */ +#define BPWM_CNT_DIRF_Msk (0x1ul << BPWM_CNT_DIRF_Pos) /*!< BPWM_T::CNT: DIRF Mask */ + +#define BPWM_WGCTL0_ZPCTL0_Pos (0) /*!< BPWM_T::WGCTL0: ZPCTL0 Position */ +#define BPWM_WGCTL0_ZPCTL0_Msk (0x3ul << BPWM_WGCTL0_ZPCTL0_Pos) /*!< BPWM_T::WGCTL0: ZPCTL0 Mask */ + +#define BPWM_WGCTL0_ZPCTL1_Pos (2) /*!< BPWM_T::WGCTL0: ZPCTL1 Position */ +#define BPWM_WGCTL0_ZPCTL1_Msk (0x3ul << BPWM_WGCTL0_ZPCTL1_Pos) /*!< BPWM_T::WGCTL0: ZPCTL1 Mask */ + +#define BPWM_WGCTL0_ZPCTL2_Pos (4) /*!< BPWM_T::WGCTL0: ZPCTL2 Position */ +#define BPWM_WGCTL0_ZPCTL2_Msk (0x3ul << BPWM_WGCTL0_ZPCTL2_Pos) /*!< BPWM_T::WGCTL0: ZPCTL2 Mask */ + +#define BPWM_WGCTL0_ZPCTL3_Pos (6) /*!< BPWM_T::WGCTL0: ZPCTL3 Position */ +#define BPWM_WGCTL0_ZPCTL3_Msk (0x3ul << BPWM_WGCTL0_ZPCTL3_Pos) /*!< BPWM_T::WGCTL0: ZPCTL3 Mask */ + +#define BPWM_WGCTL0_ZPCTL4_Pos (8) /*!< BPWM_T::WGCTL0: ZPCTL4 Position */ +#define BPWM_WGCTL0_ZPCTL4_Msk (0x3ul << BPWM_WGCTL0_ZPCTL4_Pos) /*!< BPWM_T::WGCTL0: ZPCTL4 Mask */ + +#define BPWM_WGCTL0_ZPCTL5_Pos (10) /*!< BPWM_T::WGCTL0: ZPCTL5 Position */ +#define BPWM_WGCTL0_ZPCTL5_Msk (0x3ul << BPWM_WGCTL0_ZPCTL5_Pos) /*!< BPWM_T::WGCTL0: ZPCTL5 Mask */ + +#define BPWM_WGCTL0_PRDPCTL0_Pos (16) /*!< BPWM_T::WGCTL0: PRDPCTL0 Position */ +#define BPWM_WGCTL0_PRDPCTL0_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL0_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL0 Mask */ + +#define BPWM_WGCTL0_PRDPCTL1_Pos (18) /*!< BPWM_T::WGCTL0: PRDPCTL1 Position */ +#define BPWM_WGCTL0_PRDPCTL1_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL1_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL1 Mask */ + +#define BPWM_WGCTL0_PRDPCTL2_Pos (20) /*!< BPWM_T::WGCTL0: PRDPCTL2 Position */ +#define BPWM_WGCTL0_PRDPCTL2_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL2_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL2 Mask */ + +#define BPWM_WGCTL0_PRDPCTL3_Pos (22) /*!< BPWM_T::WGCTL0: PRDPCTL3 Position */ +#define BPWM_WGCTL0_PRDPCTL3_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL3_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL3 Mask */ + +#define BPWM_WGCTL0_PRDPCTL4_Pos (24) /*!< BPWM_T::WGCTL0: PRDPCTL4 Position */ +#define BPWM_WGCTL0_PRDPCTL4_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL4_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL4 Mask */ + +#define BPWM_WGCTL0_PRDPCTL5_Pos (26) /*!< BPWM_T::WGCTL0: PRDPCTL5 Position */ +#define BPWM_WGCTL0_PRDPCTL5_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL5_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL5 Mask */ + +#define BPWM_WGCTL1_CMPUCTL0_Pos (0) /*!< BPWM_T::WGCTL1: CMPUCTL0 Position */ +#define BPWM_WGCTL1_CMPUCTL0_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL0_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL0 Mask */ + +#define BPWM_WGCTL1_CMPUCTL1_Pos (2) /*!< BPWM_T::WGCTL1: CMPUCTL1 Position */ +#define BPWM_WGCTL1_CMPUCTL1_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL1_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL1 Mask */ + +#define BPWM_WGCTL1_CMPUCTL2_Pos (4) /*!< BPWM_T::WGCTL1: CMPUCTL2 Position */ +#define BPWM_WGCTL1_CMPUCTL2_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL2_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL2 Mask */ + +#define BPWM_WGCTL1_CMPUCTL3_Pos (6) /*!< BPWM_T::WGCTL1: CMPUCTL3 Position */ +#define BPWM_WGCTL1_CMPUCTL3_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL3_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL3 Mask */ + +#define BPWM_WGCTL1_CMPUCTL4_Pos (8) /*!< BPWM_T::WGCTL1: CMPUCTL4 Position */ +#define BPWM_WGCTL1_CMPUCTL4_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL4_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL4 Mask */ + +#define BPWM_WGCTL1_CMPUCTL5_Pos (10) /*!< BPWM_T::WGCTL1: CMPUCTL5 Position */ +#define BPWM_WGCTL1_CMPUCTL5_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL5_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL5 Mask */ + +#define BPWM_WGCTL1_CMPDCTL0_Pos (16) /*!< BPWM_T::WGCTL1: CMPDCTL0 Position */ +#define BPWM_WGCTL1_CMPDCTL0_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL0_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL0 Mask */ + +#define BPWM_WGCTL1_CMPDCTL1_Pos (18) /*!< BPWM_T::WGCTL1: CMPDCTL1 Position */ +#define BPWM_WGCTL1_CMPDCTL1_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL1_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL1 Mask */ + +#define BPWM_WGCTL1_CMPDCTL2_Pos (20) /*!< BPWM_T::WGCTL1: CMPDCTL2 Position */ +#define BPWM_WGCTL1_CMPDCTL2_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL2_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL2 Mask */ + +#define BPWM_WGCTL1_CMPDCTL3_Pos (22) /*!< BPWM_T::WGCTL1: CMPDCTL3 Position */ +#define BPWM_WGCTL1_CMPDCTL3_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL3_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL3 Mask */ + +#define BPWM_WGCTL1_CMPDCTL4_Pos (24) /*!< BPWM_T::WGCTL1: CMPDCTL4 Position */ +#define BPWM_WGCTL1_CMPDCTL4_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL4_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL4 Mask */ + +#define BPWM_WGCTL1_CMPDCTL5_Pos (26) /*!< BPWM_T::WGCTL1: CMPDCTL5 Position */ +#define BPWM_WGCTL1_CMPDCTL5_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL5_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL5 Mask */ + +#define BPWM_MSKEN_MSKEN0_Pos (0) /*!< BPWM_T::MSKEN: MSKEN0 Position */ +#define BPWM_MSKEN_MSKEN0_Msk (0x1ul << BPWM_MSKEN_MSKEN0_Pos) /*!< BPWM_T::MSKEN: MSKEN0 Mask */ + +#define BPWM_MSKEN_MSKEN1_Pos (1) /*!< BPWM_T::MSKEN: MSKEN1 Position */ +#define BPWM_MSKEN_MSKEN1_Msk (0x1ul << BPWM_MSKEN_MSKEN1_Pos) /*!< BPWM_T::MSKEN: MSKEN1 Mask */ + +#define BPWM_MSKEN_MSKEN2_Pos (2) /*!< BPWM_T::MSKEN: MSKEN2 Position */ +#define BPWM_MSKEN_MSKEN2_Msk (0x1ul << BPWM_MSKEN_MSKEN2_Pos) /*!< BPWM_T::MSKEN: MSKEN2 Mask */ + +#define BPWM_MSKEN_MSKEN3_Pos (3) /*!< BPWM_T::MSKEN: MSKEN3 Position */ +#define BPWM_MSKEN_MSKEN3_Msk (0x1ul << BPWM_MSKEN_MSKEN3_Pos) /*!< BPWM_T::MSKEN: MSKEN3 Mask */ + +#define BPWM_MSKEN_MSKEN4_Pos (4) /*!< BPWM_T::MSKEN: MSKEN4 Position */ +#define BPWM_MSKEN_MSKEN4_Msk (0x1ul << BPWM_MSKEN_MSKEN4_Pos) /*!< BPWM_T::MSKEN: MSKEN4 Mask */ + +#define BPWM_MSKEN_MSKEN5_Pos (5) /*!< BPWM_T::MSKEN: MSKEN5 Position */ +#define BPWM_MSKEN_MSKEN5_Msk (0x1ul << BPWM_MSKEN_MSKEN5_Pos) /*!< BPWM_T::MSKEN: MSKEN5 Mask */ + +#define BPWM_MSK_MSKDAT0_Pos (0) /*!< BPWM_T::MSK: MSKDAT0 Position */ +#define BPWM_MSK_MSKDAT0_Msk (0x1ul << BPWM_MSK_MSKDAT0_Pos) /*!< BPWM_T::MSK: MSKDAT0 Mask */ + +#define BPWM_MSK_MSKDAT1_Pos (1) /*!< BPWM_T::MSK: MSKDAT1 Position */ +#define BPWM_MSK_MSKDAT1_Msk (0x1ul << BPWM_MSK_MSKDAT1_Pos) /*!< BPWM_T::MSK: MSKDAT1 Mask */ + +#define BPWM_MSK_MSKDAT2_Pos (2) /*!< BPWM_T::MSK: MSKDAT2 Position */ +#define BPWM_MSK_MSKDAT2_Msk (0x1ul << BPWM_MSK_MSKDAT2_Pos) /*!< BPWM_T::MSK: MSKDAT2 Mask */ + +#define BPWM_MSK_MSKDAT3_Pos (3) /*!< BPWM_T::MSK: MSKDAT3 Position */ +#define BPWM_MSK_MSKDAT3_Msk (0x1ul << BPWM_MSK_MSKDAT3_Pos) /*!< BPWM_T::MSK: MSKDAT3 Mask */ + +#define BPWM_MSK_MSKDAT4_Pos (4) /*!< BPWM_T::MSK: MSKDAT4 Position */ +#define BPWM_MSK_MSKDAT4_Msk (0x1ul << BPWM_MSK_MSKDAT4_Pos) /*!< BPWM_T::MSK: MSKDAT4 Mask */ + +#define BPWM_MSK_MSKDAT5_Pos (5) /*!< BPWM_T::MSK: MSKDAT5 Position */ +#define BPWM_MSK_MSKDAT5_Msk (0x1ul << BPWM_MSK_MSKDAT5_Pos) /*!< BPWM_T::MSK: MSKDAT5 Mask */ + +#define BPWM_POLCTL_PINV0_Pos (0) /*!< BPWM_T::POLCTL: PINV0 Position */ +#define BPWM_POLCTL_PINV0_Msk (0x1ul << BPWM_POLCTL_PINV0_Pos) /*!< BPWM_T::POLCTL: PINV0 Mask */ + +#define BPWM_POLCTL_PINV1_Pos (1) /*!< BPWM_T::POLCTL: PINV1 Position */ +#define BPWM_POLCTL_PINV1_Msk (0x1ul << BPWM_POLCTL_PINV1_Pos) /*!< BPWM_T::POLCTL: PINV1 Mask */ + +#define BPWM_POLCTL_PINV2_Pos (2) /*!< BPWM_T::POLCTL: PINV2 Position */ +#define BPWM_POLCTL_PINV2_Msk (0x1ul << BPWM_POLCTL_PINV2_Pos) /*!< BPWM_T::POLCTL: PINV2 Mask */ + +#define BPWM_POLCTL_PINV3_Pos (3) /*!< BPWM_T::POLCTL: PINV3 Position */ +#define BPWM_POLCTL_PINV3_Msk (0x1ul << BPWM_POLCTL_PINV3_Pos) /*!< BPWM_T::POLCTL: PINV3 Mask */ + +#define BPWM_POLCTL_PINV4_Pos (4) /*!< BPWM_T::POLCTL: PINV4 Position */ +#define BPWM_POLCTL_PINV4_Msk (0x1ul << BPWM_POLCTL_PINV4_Pos) /*!< BPWM_T::POLCTL: PINV4 Mask */ + +#define BPWM_POLCTL_PINV5_Pos (5) /*!< BPWM_T::POLCTL: PINV5 Position */ +#define BPWM_POLCTL_PINV5_Msk (0x1ul << BPWM_POLCTL_PINV5_Pos) /*!< BPWM_T::POLCTL: PINV5 Mask */ + +#define BPWM_POEN_POEN0_Pos (0) /*!< BPWM_T::POEN: POEN0 Position */ +#define BPWM_POEN_POEN0_Msk (0x1ul << BPWM_POEN_POEN0_Pos) /*!< BPWM_T::POEN: POEN0 Mask */ + +#define BPWM_POEN_POEN1_Pos (1) /*!< BPWM_T::POEN: POEN1 Position */ +#define BPWM_POEN_POEN1_Msk (0x1ul << BPWM_POEN_POEN1_Pos) /*!< BPWM_T::POEN: POEN1 Mask */ + +#define BPWM_POEN_POEN2_Pos (2) /*!< BPWM_T::POEN: POEN2 Position */ +#define BPWM_POEN_POEN2_Msk (0x1ul << BPWM_POEN_POEN2_Pos) /*!< BPWM_T::POEN: POEN2 Mask */ + +#define BPWM_POEN_POEN3_Pos (3) /*!< BPWM_T::POEN: POEN3 Position */ +#define BPWM_POEN_POEN3_Msk (0x1ul << BPWM_POEN_POEN3_Pos) /*!< BPWM_T::POEN: POEN3 Mask */ + +#define BPWM_POEN_POEN4_Pos (4) /*!< BPWM_T::POEN: POEN4 Position */ +#define BPWM_POEN_POEN4_Msk (0x1ul << BPWM_POEN_POEN4_Pos) /*!< BPWM_T::POEN: POEN4 Mask */ + +#define BPWM_POEN_POEN5_Pos (5) /*!< BPWM_T::POEN: POEN5 Position */ +#define BPWM_POEN_POEN5_Msk (0x1ul << BPWM_POEN_POEN5_Pos) /*!< BPWM_T::POEN: POEN5 Mask */ + +#define BPWM_INTEN_ZIEN0_Pos (0) /*!< BPWM_T::INTEN: ZIEN0 Position */ +#define BPWM_INTEN_ZIEN0_Msk (0x1ul << BPWM_INTEN_ZIEN0_Pos) /*!< BPWM_T::INTEN: ZIEN0 Mask */ + +#define BPWM_INTEN_PIEN0_Pos (8) /*!< BPWM_T::INTEN: PIEN0 Position */ +#define BPWM_INTEN_PIEN0_Msk (0x1ul << BPWM_INTEN_PIEN0_Pos) /*!< BPWM_T::INTEN: PIEN0 Mask */ + +#define BPWM_INTEN_CMPUIEN0_Pos (16) /*!< BPWM_T::INTEN: CMPUIEN0 Position */ +#define BPWM_INTEN_CMPUIEN0_Msk (0x1ul << BPWM_INTEN_CMPUIEN0_Pos) /*!< BPWM_T::INTEN: CMPUIEN0 Mask */ + +#define BPWM_INTEN_CMPUIEN1_Pos (17) /*!< BPWM_T::INTEN: CMPUIEN1 Position */ +#define BPWM_INTEN_CMPUIEN1_Msk (0x1ul << BPWM_INTEN_CMPUIEN1_Pos) /*!< BPWM_T::INTEN: CMPUIEN1 Mask */ + +#define BPWM_INTEN_CMPUIEN2_Pos (18) /*!< BPWM_T::INTEN: CMPUIEN2 Position */ +#define BPWM_INTEN_CMPUIEN2_Msk (0x1ul << BPWM_INTEN_CMPUIEN2_Pos) /*!< BPWM_T::INTEN: CMPUIEN2 Mask */ + +#define BPWM_INTEN_CMPUIEN3_Pos (19) /*!< BPWM_T::INTEN: CMPUIEN3 Position */ +#define BPWM_INTEN_CMPUIEN3_Msk (0x1ul << BPWM_INTEN_CMPUIEN3_Pos) /*!< BPWM_T::INTEN: CMPUIEN3 Mask */ + +#define BPWM_INTEN_CMPUIEN4_Pos (20) /*!< BPWM_T::INTEN: CMPUIEN4 Position */ +#define BPWM_INTEN_CMPUIEN4_Msk (0x1ul << BPWM_INTEN_CMPUIEN4_Pos) /*!< BPWM_T::INTEN: CMPUIEN4 Mask */ + +#define BPWM_INTEN_CMPUIEN5_Pos (21) /*!< BPWM_T::INTEN: CMPUIEN5 Position */ +#define BPWM_INTEN_CMPUIEN5_Msk (0x1ul << BPWM_INTEN_CMPUIEN5_Pos) /*!< BPWM_T::INTEN: CMPUIEN5 Mask */ + +#define BPWM_INTEN_CMPDIEN0_Pos (24) /*!< BPWM_T::INTEN: CMPDIEN0 Position */ +#define BPWM_INTEN_CMPDIEN0_Msk (0x1ul << BPWM_INTEN_CMPDIEN0_Pos) /*!< BPWM_T::INTEN: CMPDIEN0 Mask */ + +#define BPWM_INTEN_CMPDIEN1_Pos (25) /*!< BPWM_T::INTEN: CMPDIEN1 Position */ +#define BPWM_INTEN_CMPDIEN1_Msk (0x1ul << BPWM_INTEN_CMPDIEN1_Pos) /*!< BPWM_T::INTEN: CMPDIEN1 Mask */ + +#define BPWM_INTEN_CMPDIEN2_Pos (26) /*!< BPWM_T::INTEN: CMPDIEN2 Position */ +#define BPWM_INTEN_CMPDIEN2_Msk (0x1ul << BPWM_INTEN_CMPDIEN2_Pos) /*!< BPWM_T::INTEN: CMPDIEN2 Mask */ + +#define BPWM_INTEN_CMPDIEN3_Pos (27) /*!< BPWM_T::INTEN: CMPDIEN3 Position */ +#define BPWM_INTEN_CMPDIEN3_Msk (0x1ul << BPWM_INTEN_CMPDIEN3_Pos) /*!< BPWM_T::INTEN: CMPDIEN3 Mask */ + +#define BPWM_INTEN_CMPDIEN4_Pos (28) /*!< BPWM_T::INTEN: CMPDIEN4 Position */ +#define BPWM_INTEN_CMPDIEN4_Msk (0x1ul << BPWM_INTEN_CMPDIEN4_Pos) /*!< BPWM_T::INTEN: CMPDIEN4 Mask */ + +#define BPWM_INTEN_CMPDIEN5_Pos (29) /*!< BPWM_T::INTEN: CMPDIEN5 Position */ +#define BPWM_INTEN_CMPDIEN5_Msk (0x1ul << BPWM_INTEN_CMPDIEN5_Pos) /*!< BPWM_T::INTEN: CMPDIEN5 Mask */ + +#define BPWM_INTSTS_ZIF0_Pos (0) /*!< BPWM_T::INTSTS: ZIF0 Position */ +#define BPWM_INTSTS_ZIF0_Msk (0x1ul << BPWM_INTSTS_ZIF0_Pos) /*!< BPWM_T::INTSTS: ZIF0 Mask */ + +#define BPWM_INTSTS_PIF0_Pos (8) /*!< BPWM_T::INTSTS: PIF0 Position */ +#define BPWM_INTSTS_PIF0_Msk (0x1ul << BPWM_INTSTS_PIF0_Pos) /*!< BPWM_T::INTSTS: PIF0 Mask */ + +#define BPWM_INTSTS_CMPUIF0_Pos (16) /*!< BPWM_T::INTSTS: CMPUIF0 Position */ +#define BPWM_INTSTS_CMPUIF0_Msk (0x1ul << BPWM_INTSTS_CMPUIF0_Pos) /*!< BPWM_T::INTSTS: CMPUIF0 Mask */ + +#define BPWM_INTSTS_CMPUIF1_Pos (17) /*!< BPWM_T::INTSTS: CMPUIF1 Position */ +#define BPWM_INTSTS_CMPUIF1_Msk (0x1ul << BPWM_INTSTS_CMPUIF1_Pos) /*!< BPWM_T::INTSTS: CMPUIF1 Mask */ + +#define BPWM_INTSTS_CMPUIF2_Pos (18) /*!< BPWM_T::INTSTS: CMPUIF2 Position */ +#define BPWM_INTSTS_CMPUIF2_Msk (0x1ul << BPWM_INTSTS_CMPUIF2_Pos) /*!< BPWM_T::INTSTS: CMPUIF2 Mask */ + +#define BPWM_INTSTS_CMPUIF3_Pos (19) /*!< BPWM_T::INTSTS: CMPUIF3 Position */ +#define BPWM_INTSTS_CMPUIF3_Msk (0x1ul << BPWM_INTSTS_CMPUIF3_Pos) /*!< BPWM_T::INTSTS: CMPUIF3 Mask */ + +#define BPWM_INTSTS_CMPUIF4_Pos (20) /*!< BPWM_T::INTSTS: CMPUIF4 Position */ +#define BPWM_INTSTS_CMPUIF4_Msk (0x1ul << BPWM_INTSTS_CMPUIF4_Pos) /*!< BPWM_T::INTSTS: CMPUIF4 Mask */ + +#define BPWM_INTSTS_CMPUIF5_Pos (21) /*!< BPWM_T::INTSTS: CMPUIF5 Position */ +#define BPWM_INTSTS_CMPUIF5_Msk (0x1ul << BPWM_INTSTS_CMPUIF5_Pos) /*!< BPWM_T::INTSTS: CMPUIF5 Mask */ + +#define BPWM_INTSTS_CMPDIF0_Pos (24) /*!< BPWM_T::INTSTS: CMPDIF0 Position */ +#define BPWM_INTSTS_CMPDIF0_Msk (0x1ul << BPWM_INTSTS_CMPDIF0_Pos) /*!< BPWM_T::INTSTS: CMPDIF0 Mask */ + +#define BPWM_INTSTS_CMPDIF1_Pos (25) /*!< BPWM_T::INTSTS: CMPDIF1 Position */ +#define BPWM_INTSTS_CMPDIF1_Msk (0x1ul << BPWM_INTSTS_CMPDIF1_Pos) /*!< BPWM_T::INTSTS: CMPDIF1 Mask */ + +#define BPWM_INTSTS_CMPDIF2_Pos (26) /*!< BPWM_T::INTSTS: CMPDIF2 Position */ +#define BPWM_INTSTS_CMPDIF2_Msk (0x1ul << BPWM_INTSTS_CMPDIF2_Pos) /*!< BPWM_T::INTSTS: CMPDIF2 Mask */ + +#define BPWM_INTSTS_CMPDIF3_Pos (27) /*!< BPWM_T::INTSTS: CMPDIF3 Position */ +#define BPWM_INTSTS_CMPDIF3_Msk (0x1ul << BPWM_INTSTS_CMPDIF3_Pos) /*!< BPWM_T::INTSTS: CMPDIF3 Mask */ + +#define BPWM_INTSTS_CMPDIF4_Pos (28) /*!< BPWM_T::INTSTS: CMPDIF4 Position */ +#define BPWM_INTSTS_CMPDIF4_Msk (0x1ul << BPWM_INTSTS_CMPDIF4_Pos) /*!< BPWM_T::INTSTS: CMPDIF4 Mask */ + +#define BPWM_INTSTS_CMPDIF5_Pos (29) /*!< BPWM_T::INTSTS: CMPDIF5 Position */ +#define BPWM_INTSTS_CMPDIF5_Msk (0x1ul << BPWM_INTSTS_CMPDIF5_Pos) /*!< BPWM_T::INTSTS: CMPDIF5 Mask */ + +#define BPWM_EADCTS0_TRGSEL0_Pos (0) /*!< BPWM_T::EADCTS0: TRGSEL0 Position */ +#define BPWM_EADCTS0_TRGSEL0_Msk (0xful << BPWM_EADCTS0_TRGSEL0_Pos) /*!< BPWM_T::EADCTS0: TRGSEL0 Mask */ + +#define BPWM_EADCTS0_TRGEN0_Pos (7) /*!< BPWM_T::EADCTS0: TRGEN0 Position */ +#define BPWM_EADCTS0_TRGEN0_Msk (0x1ul << BPWM_EADCTS0_TRGEN0_Pos) /*!< BPWM_T::EADCTS0: TRGEN0 Mask */ + +#define BPWM_EADCTS0_TRGSEL1_Pos (8) /*!< BPWM_T::EADCTS0: TRGSEL1 Position */ +#define BPWM_EADCTS0_TRGSEL1_Msk (0xful << BPWM_EADCTS0_TRGSEL1_Pos) /*!< BPWM_T::EADCTS0: TRGSEL1 Mask */ + +#define BPWM_EADCTS0_TRGEN1_Pos (15) /*!< BPWM_T::EADCTS0: TRGEN1 Position */ +#define BPWM_EADCTS0_TRGEN1_Msk (0x1ul << BPWM_EADCTS0_TRGEN1_Pos) /*!< BPWM_T::EADCTS0: TRGEN1 Mask */ + +#define BPWM_EADCTS0_TRGSEL2_Pos (16) /*!< BPWM_T::EADCTS0: TRGSEL2 Position */ +#define BPWM_EADCTS0_TRGSEL2_Msk (0xful << BPWM_EADCTS0_TRGSEL2_Pos) /*!< BPWM_T::EADCTS0: TRGSEL2 Mask */ + +#define BPWM_EADCTS0_TRGEN2_Pos (23) /*!< BPWM_T::EADCTS0: TRGEN2 Position */ +#define BPWM_EADCTS0_TRGEN2_Msk (0x1ul << BPWM_EADCTS0_TRGEN2_Pos) /*!< BPWM_T::EADCTS0: TRGEN2 Mask */ + +#define BPWM_EADCTS0_TRGSEL3_Pos (24) /*!< BPWM_T::EADCTS0: TRGSEL3 Position */ +#define BPWM_EADCTS0_TRGSEL3_Msk (0xful << BPWM_EADCTS0_TRGSEL3_Pos) /*!< BPWM_T::EADCTS0: TRGSEL3 Mask */ + +#define BPWM_EADCTS0_TRGEN3_Pos (31) /*!< BPWM_T::EADCTS0: TRGEN3 Position */ +#define BPWM_EADCTS0_TRGEN3_Msk (0x1ul << BPWM_EADCTS0_TRGEN3_Pos) /*!< BPWM_T::EADCTS0: TRGEN3 Mask */ + +#define BPWM_EADCTS1_TRGSEL4_Pos (0) /*!< BPWM_T::EADCTS1: TRGSEL4 Position */ +#define BPWM_EADCTS1_TRGSEL4_Msk (0xful << BPWM_EADCTS1_TRGSEL4_Pos) /*!< BPWM_T::EADCTS1: TRGSEL4 Mask */ + +#define BPWM_EADCTS1_TRGEN4_Pos (7) /*!< BPWM_T::EADCTS1: TRGEN4 Position */ +#define BPWM_EADCTS1_TRGEN4_Msk (0x1ul << BPWM_EADCTS1_TRGEN4_Pos) /*!< BPWM_T::EADCTS1: TRGEN4 Mask */ + +#define BPWM_EADCTS1_TRGSEL5_Pos (8) /*!< BPWM_T::EADCTS1: TRGSEL5 Position */ +#define BPWM_EADCTS1_TRGSEL5_Msk (0xful << BPWM_EADCTS1_TRGSEL5_Pos) /*!< BPWM_T::EADCTS1: TRGSEL5 Mask */ + +#define BPWM_EADCTS1_TRGEN5_Pos (15) /*!< BPWM_T::EADCTS1: TRGEN5 Position */ +#define BPWM_EADCTS1_TRGEN5_Msk (0x1ul << BPWM_EADCTS1_TRGEN5_Pos) /*!< BPWM_T::EADCTS1: TRGEN5 Mask */ + +#define BPWM_SSCTL_SSEN0_Pos (0) /*!< BPWM_T::SSCTL: SSEN0 Position */ +#define BPWM_SSCTL_SSEN0_Msk (0x1ul << BPWM_SSCTL_SSEN0_Pos) /*!< BPWM_T::SSCTL: SSEN0 Mask */ + +#define BPWM_SSCTL_SSRC_Pos (8) /*!< BPWM_T::SSCTL: SSRC Position */ +#define BPWM_SSCTL_SSRC_Msk (0x3ul << BPWM_SSCTL_SSRC_Pos) /*!< BPWM_T::SSCTL: SSRC Mask */ + +#define BPWM_SSTRG_CNTSEN_Pos (0) /*!< BPWM_T::SSTRG: CNTSEN Position */ +#define BPWM_SSTRG_CNTSEN_Msk (0x1ul << BPWM_SSTRG_CNTSEN_Pos) /*!< BPWM_T::SSTRG: CNTSEN Mask */ + +#define BPWM_STATUS_CNTMAX0_Pos (0) /*!< BPWM_T::STATUS: CNTMAX0 Position */ +#define BPWM_STATUS_CNTMAX0_Msk (0x1ul << BPWM_STATUS_CNTMAX0_Pos) /*!< BPWM_T::STATUS: CNTMAX0 Mask */ + +#define BPWM_STATUS_EADCTRG0_Pos (16) /*!< BPWM_T::STATUS: EADCTRG0 Position */ +#define BPWM_STATUS_EADCTRG0_Msk (0x1ul << BPWM_STATUS_EADCTRG0_Pos) /*!< BPWM_T::STATUS: EADCTRG0 Mask */ + +#define BPWM_STATUS_EADCTRG1_Pos (17) /*!< BPWM_T::STATUS: EADCTRG1 Position */ +#define BPWM_STATUS_EADCTRG1_Msk (0x1ul << BPWM_STATUS_EADCTRG1_Pos) /*!< BPWM_T::STATUS: EADCTRG1 Mask */ + +#define BPWM_STATUS_EADCTRG2_Pos (18) /*!< BPWM_T::STATUS: EADCTRG2 Position */ +#define BPWM_STATUS_EADCTRG2_Msk (0x1ul << BPWM_STATUS_EADCTRG2_Pos) /*!< BPWM_T::STATUS: EADCTRG2 Mask */ + +#define BPWM_STATUS_EADCTRG3_Pos (19) /*!< BPWM_T::STATUS: EADCTRG3 Position */ +#define BPWM_STATUS_EADCTRG3_Msk (0x1ul << BPWM_STATUS_EADCTRG3_Pos) /*!< BPWM_T::STATUS: EADCTRG3 Mask */ + +#define BPWM_STATUS_EADCTRG4_Pos (20) /*!< BPWM_T::STATUS: EADCTRG4 Position */ +#define BPWM_STATUS_EADCTRG4_Msk (0x1ul << BPWM_STATUS_EADCTRG4_Pos) /*!< BPWM_T::STATUS: EADCTRG4 Mask */ + +#define BPWM_STATUS_EADCTRG5_Pos (21) /*!< BPWM_T::STATUS: EADCTRG5 Position */ +#define BPWM_STATUS_EADCTRG5_Msk (0x1ul << BPWM_STATUS_EADCTRG5_Pos) /*!< BPWM_T::STATUS: EADCTRG5 Mask */ + +#define BPWM_CAPINEN_CAPINEN0_Pos (0) /*!< BPWM_T::CAPINEN: CAPINEN0 Position */ +#define BPWM_CAPINEN_CAPINEN0_Msk (0x1ul << BPWM_CAPINEN_CAPINEN0_Pos) /*!< BPWM_T::CAPINEN: CAPINEN0 Mask */ + +#define BPWM_CAPINEN_CAPINEN1_Pos (1) /*!< BPWM_T::CAPINEN: CAPINEN1 Position */ +#define BPWM_CAPINEN_CAPINEN1_Msk (0x1ul << BPWM_CAPINEN_CAPINEN1_Pos) /*!< BPWM_T::CAPINEN: CAPINEN1 Mask */ + +#define BPWM_CAPINEN_CAPINEN2_Pos (2) /*!< BPWM_T::CAPINEN: CAPINEN2 Position */ +#define BPWM_CAPINEN_CAPINEN2_Msk (0x1ul << BPWM_CAPINEN_CAPINEN2_Pos) /*!< BPWM_T::CAPINEN: CAPINEN2 Mask */ + +#define BPWM_CAPINEN_CAPINEN3_Pos (3) /*!< BPWM_T::CAPINEN: CAPINEN3 Position */ +#define BPWM_CAPINEN_CAPINEN3_Msk (0x1ul << BPWM_CAPINEN_CAPINEN3_Pos) /*!< BPWM_T::CAPINEN: CAPINEN3 Mask */ + +#define BPWM_CAPINEN_CAPINEN4_Pos (4) /*!< BPWM_T::CAPINEN: CAPINEN4 Position */ +#define BPWM_CAPINEN_CAPINEN4_Msk (0x1ul << BPWM_CAPINEN_CAPINEN4_Pos) /*!< BPWM_T::CAPINEN: CAPINEN4 Mask */ + +#define BPWM_CAPINEN_CAPINEN5_Pos (5) /*!< BPWM_T::CAPINEN: CAPINEN5 Position */ +#define BPWM_CAPINEN_CAPINEN5_Msk (0x1ul << BPWM_CAPINEN_CAPINEN5_Pos) /*!< BPWM_T::CAPINEN: CAPINEN5 Mask */ + +#define BPWM_CAPCTL_CAPEN0_Pos (0) /*!< BPWM_T::CAPCTL: CAPEN0 Position */ +#define BPWM_CAPCTL_CAPEN0_Msk (0x1ul << BPWM_CAPCTL_CAPEN0_Pos) /*!< BPWM_T::CAPCTL: CAPEN0 Mask */ + +#define BPWM_CAPCTL_CAPEN1_Pos (1) /*!< BPWM_T::CAPCTL: CAPEN1 Position */ +#define BPWM_CAPCTL_CAPEN1_Msk (0x1ul << BPWM_CAPCTL_CAPEN1_Pos) /*!< BPWM_T::CAPCTL: CAPEN1 Mask */ + +#define BPWM_CAPCTL_CAPEN2_Pos (2) /*!< BPWM_T::CAPCTL: CAPEN2 Position */ +#define BPWM_CAPCTL_CAPEN2_Msk (0x1ul << BPWM_CAPCTL_CAPEN2_Pos) /*!< BPWM_T::CAPCTL: CAPEN2 Mask */ + +#define BPWM_CAPCTL_CAPEN3_Pos (3) /*!< BPWM_T::CAPCTL: CAPEN3 Position */ +#define BPWM_CAPCTL_CAPEN3_Msk (0x1ul << BPWM_CAPCTL_CAPEN3_Pos) /*!< BPWM_T::CAPCTL: CAPEN3 Mask */ + +#define BPWM_CAPCTL_CAPEN4_Pos (4) /*!< BPWM_T::CAPCTL: CAPEN4 Position */ +#define BPWM_CAPCTL_CAPEN4_Msk (0x1ul << BPWM_CAPCTL_CAPEN4_Pos) /*!< BPWM_T::CAPCTL: CAPEN4 Mask */ + +#define BPWM_CAPCTL_CAPEN5_Pos (5) /*!< BPWM_T::CAPCTL: CAPEN5 Position */ +#define BPWM_CAPCTL_CAPEN5_Msk (0x1ul << BPWM_CAPCTL_CAPEN5_Pos) /*!< BPWM_T::CAPCTL: CAPEN5 Mask */ + +#define BPWM_CAPCTL_CAPINV0_Pos (8) /*!< BPWM_T::CAPCTL: CAPINV0 Position */ +#define BPWM_CAPCTL_CAPINV0_Msk (0x1ul << BPWM_CAPCTL_CAPINV0_Pos) /*!< BPWM_T::CAPCTL: CAPINV0 Mask */ + +#define BPWM_CAPCTL_CAPINV1_Pos (9) /*!< BPWM_T::CAPCTL: CAPINV1 Position */ +#define BPWM_CAPCTL_CAPINV1_Msk (0x1ul << BPWM_CAPCTL_CAPINV1_Pos) /*!< BPWM_T::CAPCTL: CAPINV1 Mask */ + +#define BPWM_CAPCTL_CAPINV2_Pos (10) /*!< BPWM_T::CAPCTL: CAPINV2 Position */ +#define BPWM_CAPCTL_CAPINV2_Msk (0x1ul << BPWM_CAPCTL_CAPINV2_Pos) /*!< BPWM_T::CAPCTL: CAPINV2 Mask */ + +#define BPWM_CAPCTL_CAPINV3_Pos (11) /*!< BPWM_T::CAPCTL: CAPINV3 Position */ +#define BPWM_CAPCTL_CAPINV3_Msk (0x1ul << BPWM_CAPCTL_CAPINV3_Pos) /*!< BPWM_T::CAPCTL: CAPINV3 Mask */ + +#define BPWM_CAPCTL_CAPINV4_Pos (12) /*!< BPWM_T::CAPCTL: CAPINV4 Position */ +#define BPWM_CAPCTL_CAPINV4_Msk (0x1ul << BPWM_CAPCTL_CAPINV4_Pos) /*!< BPWM_T::CAPCTL: CAPINV4 Mask */ + +#define BPWM_CAPCTL_CAPINV5_Pos (13) /*!< BPWM_T::CAPCTL: CAPINV5 Position */ +#define BPWM_CAPCTL_CAPINV5_Msk (0x1ul << BPWM_CAPCTL_CAPINV5_Pos) /*!< BPWM_T::CAPCTL: CAPINV5 Mask */ + +#define BPWM_CAPCTL_RCRLDEN0_Pos (16) /*!< BPWM_T::CAPCTL: RCRLDEN0 Position */ +#define BPWM_CAPCTL_RCRLDEN0_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN0_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN0 Mask */ + +#define BPWM_CAPCTL_RCRLDEN1_Pos (17) /*!< BPWM_T::CAPCTL: RCRLDEN1 Position */ +#define BPWM_CAPCTL_RCRLDEN1_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN1_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN1 Mask */ + +#define BPWM_CAPCTL_RCRLDEN2_Pos (18) /*!< BPWM_T::CAPCTL: RCRLDEN2 Position */ +#define BPWM_CAPCTL_RCRLDEN2_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN2_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN2 Mask */ + +#define BPWM_CAPCTL_RCRLDEN3_Pos (19) /*!< BPWM_T::CAPCTL: RCRLDEN3 Position */ +#define BPWM_CAPCTL_RCRLDEN3_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN3_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN3 Mask */ + +#define BPWM_CAPCTL_RCRLDEN4_Pos (20) /*!< BPWM_T::CAPCTL: RCRLDEN4 Position */ +#define BPWM_CAPCTL_RCRLDEN4_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN4_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN4 Mask */ + +#define BPWM_CAPCTL_RCRLDEN5_Pos (21) /*!< BPWM_T::CAPCTL: RCRLDEN5 Position */ +#define BPWM_CAPCTL_RCRLDEN5_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN5_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN5 Mask */ + +#define BPWM_CAPCTL_FCRLDEN0_Pos (24) /*!< BPWM_T::CAPCTL: FCRLDEN0 Position */ +#define BPWM_CAPCTL_FCRLDEN0_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN0_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN0 Mask */ + +#define BPWM_CAPCTL_FCRLDEN1_Pos (25) /*!< BPWM_T::CAPCTL: FCRLDEN1 Position */ +#define BPWM_CAPCTL_FCRLDEN1_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN1_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN1 Mask */ + +#define BPWM_CAPCTL_FCRLDEN2_Pos (26) /*!< BPWM_T::CAPCTL: FCRLDEN2 Position */ +#define BPWM_CAPCTL_FCRLDEN2_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN2_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN2 Mask */ + +#define BPWM_CAPCTL_FCRLDEN3_Pos (27) /*!< BPWM_T::CAPCTL: FCRLDEN3 Position */ +#define BPWM_CAPCTL_FCRLDEN3_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN3_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN3 Mask */ + +#define BPWM_CAPCTL_FCRLDEN4_Pos (28) /*!< BPWM_T::CAPCTL: FCRLDEN4 Position */ +#define BPWM_CAPCTL_FCRLDEN4_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN4_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN4 Mask */ + +#define BPWM_CAPCTL_FCRLDEN5_Pos (29) /*!< BPWM_T::CAPCTL: FCRLDEN5 Position */ +#define BPWM_CAPCTL_FCRLDEN5_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN5_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN5 Mask */ + +#define BPWM_CAPSTS_CRIFOV0_Pos (0) /*!< BPWM_T::CAPSTS: CRIFOV0 Position */ +#define BPWM_CAPSTS_CRIFOV0_Msk (0x1ul << BPWM_CAPSTS_CRIFOV0_Pos) /*!< BPWM_T::CAPSTS: CRIFOV0 Mask */ + +#define BPWM_CAPSTS_CRIFOV1_Pos (1) /*!< BPWM_T::CAPSTS: CRIFOV1 Position */ +#define BPWM_CAPSTS_CRIFOV1_Msk (0x1ul << BPWM_CAPSTS_CRIFOV1_Pos) /*!< BPWM_T::CAPSTS: CRIFOV1 Mask */ + +#define BPWM_CAPSTS_CRIFOV2_Pos (2) /*!< BPWM_T::CAPSTS: CRIFOV2 Position */ +#define BPWM_CAPSTS_CRIFOV2_Msk (0x1ul << BPWM_CAPSTS_CRIFOV2_Pos) /*!< BPWM_T::CAPSTS: CRIFOV2 Mask */ + +#define BPWM_CAPSTS_CRIFOV3_Pos (3) /*!< BPWM_T::CAPSTS: CRIFOV3 Position */ +#define BPWM_CAPSTS_CRIFOV3_Msk (0x1ul << BPWM_CAPSTS_CRIFOV3_Pos) /*!< BPWM_T::CAPSTS: CRIFOV3 Mask */ + +#define BPWM_CAPSTS_CRIFOV4_Pos (4) /*!< BPWM_T::CAPSTS: CRIFOV4 Position */ +#define BPWM_CAPSTS_CRIFOV4_Msk (0x1ul << BPWM_CAPSTS_CRIFOV4_Pos) /*!< BPWM_T::CAPSTS: CRIFOV4 Mask */ + +#define BPWM_CAPSTS_CRIFOV5_Pos (5) /*!< BPWM_T::CAPSTS: CRIFOV5 Position */ +#define BPWM_CAPSTS_CRIFOV5_Msk (0x1ul << BPWM_CAPSTS_CRIFOV5_Pos) /*!< BPWM_T::CAPSTS: CRIFOV5 Mask */ + +#define BPWM_CAPSTS_CFIFOV0_Pos (8) /*!< BPWM_T::CAPSTS: CFIFOV0 Position */ +#define BPWM_CAPSTS_CFIFOV0_Msk (0x1ul << BPWM_CAPSTS_CFIFOV0_Pos) /*!< BPWM_T::CAPSTS: CFIFOV0 Mask */ + +#define BPWM_CAPSTS_CFIFOV1_Pos (9) /*!< BPWM_T::CAPSTS: CFIFOV1 Position */ +#define BPWM_CAPSTS_CFIFOV1_Msk (0x1ul << BPWM_CAPSTS_CFIFOV1_Pos) /*!< BPWM_T::CAPSTS: CFIFOV1 Mask */ + +#define BPWM_CAPSTS_CFIFOV2_Pos (10) /*!< BPWM_T::CAPSTS: CFIFOV2 Position */ +#define BPWM_CAPSTS_CFIFOV2_Msk (0x1ul << BPWM_CAPSTS_CFIFOV2_Pos) /*!< BPWM_T::CAPSTS: CFIFOV2 Mask */ + +#define BPWM_CAPSTS_CFIFOV3_Pos (11) /*!< BPWM_T::CAPSTS: CFIFOV3 Position */ +#define BPWM_CAPSTS_CFIFOV3_Msk (0x1ul << BPWM_CAPSTS_CFIFOV3_Pos) /*!< BPWM_T::CAPSTS: CFIFOV3 Mask */ + +#define BPWM_CAPSTS_CFIFOV4_Pos (12) /*!< BPWM_T::CAPSTS: CFIFOV4 Position */ +#define BPWM_CAPSTS_CFIFOV4_Msk (0x1ul << BPWM_CAPSTS_CFIFOV4_Pos) /*!< BPWM_T::CAPSTS: CFIFOV4 Mask */ + +#define BPWM_CAPSTS_CFIFOV5_Pos (13) /*!< BPWM_T::CAPSTS: CFIFOV5 Position */ +#define BPWM_CAPSTS_CFIFOV5_Msk (0x1ul << BPWM_CAPSTS_CFIFOV5_Pos) /*!< BPWM_T::CAPSTS: CFIFOV5 Mask */ + +#define BPWM_RCAPDAT_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT: RCAPDAT Position */ +#define BPWM_RCAPDAT_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT: RCAPDAT Mask */ + +#define BPWM_FCAPDAT_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT: FCAPDAT Position */ +#define BPWM_FCAPDAT_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT: FCAPDAT Mask */ + +#define BPWM_RCAPDAT0_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT0: RCAPDAT Position */ +#define BPWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT0_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT0: RCAPDAT Mask */ + +#define BPWM_FCAPDAT0_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT0: FCAPDAT Position */ +#define BPWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT0_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT0: FCAPDAT Mask */ + +#define BPWM_RCAPDAT1_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT1: RCAPDAT Position */ +#define BPWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT1_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT1: RCAPDAT Mask */ + +#define BPWM_FCAPDAT1_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT1: FCAPDAT Position */ +#define BPWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT1_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT1: FCAPDAT Mask */ + +#define BPWM_RCAPDAT2_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT2: RCAPDAT Position */ +#define BPWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT2_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT2: RCAPDAT Mask */ + +#define BPWM_FCAPDAT2_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT2: FCAPDAT Position */ +#define BPWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT2_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT2: FCAPDAT Mask */ + +#define BPWM_RCAPDAT3_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT3: RCAPDAT Position */ +#define BPWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT3_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT3: RCAPDAT Mask */ + +#define BPWM_FCAPDAT3_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT3: FCAPDAT Position */ +#define BPWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT3_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT3: FCAPDAT Mask */ + +#define BPWM_RCAPDAT4_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT4: RCAPDAT Position */ +#define BPWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT4_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT4: RCAPDAT Mask */ + +#define BPWM_FCAPDAT4_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT4: FCAPDAT Position */ +#define BPWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT4_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT4: FCAPDAT Mask */ + +#define BPWM_RCAPDAT5_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT5: RCAPDAT Position */ +#define BPWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT5_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT5: RCAPDAT Mask */ + +#define BPWM_FCAPDAT5_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT5: FCAPDAT Position */ +#define BPWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT5_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT5: FCAPDAT Mask */ + +#define BPWM_CAPIEN_CAPRIENn_Pos (0) /*!< BPWM_T::CAPIEN: CAPRIENn Position */ +#define BPWM_CAPIEN_CAPRIENn_Msk (0x3ful << BPWM_CAPIEN_CAPRIENn_Pos) /*!< BPWM_T::CAPIEN: CAPRIENn Mask */ + +#define BPWM_CAPIEN_CAPFIENn_Pos (8) /*!< BPWM_T::CAPIEN: CAPFIENn Position */ +#define BPWM_CAPIEN_CAPFIENn_Msk (0x3ful << BPWM_CAPIEN_CAPFIENn_Pos) /*!< BPWM_T::CAPIEN: CAPFIENn Mask */ + +#define BPWM_CAPIF_CAPRIF0_Pos (0) /*!< BPWM_T::CAPIF: CAPRIF0 Position */ +#define BPWM_CAPIF_CAPRIF0_Msk (0x1ul << BPWM_CAPIF_CAPRIF0_Pos) /*!< BPWM_T::CAPIF: CAPRIF0 Mask */ + +#define BPWM_CAPIF_CAPRIF1_Pos (1) /*!< BPWM_T::CAPIF: CAPRIF1 Position */ +#define BPWM_CAPIF_CAPRIF1_Msk (0x1ul << BPWM_CAPIF_CAPRIF1_Pos) /*!< BPWM_T::CAPIF: CAPRIF1 Mask */ + +#define BPWM_CAPIF_CAPRIF2_Pos (2) /*!< BPWM_T::CAPIF: CAPRIF2 Position */ +#define BPWM_CAPIF_CAPRIF2_Msk (0x1ul << BPWM_CAPIF_CAPRIF2_Pos) /*!< BPWM_T::CAPIF: CAPRIF2 Mask */ + +#define BPWM_CAPIF_CAPRIF3_Pos (3) /*!< BPWM_T::CAPIF: CAPRIF3 Position */ +#define BPWM_CAPIF_CAPRIF3_Msk (0x1ul << BPWM_CAPIF_CAPRIF3_Pos) /*!< BPWM_T::CAPIF: CAPRIF3 Mask */ + +#define BPWM_CAPIF_CAPRIF4_Pos (4) /*!< BPWM_T::CAPIF: CAPRIF4 Position */ +#define BPWM_CAPIF_CAPRIF4_Msk (0x1ul << BPWM_CAPIF_CAPRIF4_Pos) /*!< BPWM_T::CAPIF: CAPRIF4 Mask */ + +#define BPWM_CAPIF_CAPRIF5_Pos (5) /*!< BPWM_T::CAPIF: CAPRIF5 Position */ +#define BPWM_CAPIF_CAPRIF5_Msk (0x1ul << BPWM_CAPIF_CAPRIF5_Pos) /*!< BPWM_T::CAPIF: CAPRIF5 Mask */ + +#define BPWM_CAPIF_CAPFIF0_Pos (8) /*!< BPWM_T::CAPIF: CAPFIF0 Position */ +#define BPWM_CAPIF_CAPFIF0_Msk (0x1ul << BPWM_CAPIF_CAPFIF0_Pos) /*!< BPWM_T::CAPIF: CAPFIF0 Mask */ + +#define BPWM_CAPIF_CAPFIF1_Pos (9) /*!< BPWM_T::CAPIF: CAPFIF1 Position */ +#define BPWM_CAPIF_CAPFIF1_Msk (0x1ul << BPWM_CAPIF_CAPFIF1_Pos) /*!< BPWM_T::CAPIF: CAPFIF1 Mask */ + +#define BPWM_CAPIF_CAPFIF2_Pos (10) /*!< BPWM_T::CAPIF: CAPFIF2 Position */ +#define BPWM_CAPIF_CAPFIF2_Msk (0x1ul << BPWM_CAPIF_CAPFIF2_Pos) /*!< BPWM_T::CAPIF: CAPFIF2 Mask */ + +#define BPWM_CAPIF_CAPFIF3_Pos (11) /*!< BPWM_T::CAPIF: CAPFIF3 Position */ +#define BPWM_CAPIF_CAPFIF3_Msk (0x1ul << BPWM_CAPIF_CAPFIF3_Pos) /*!< BPWM_T::CAPIF: CAPFIF3 Mask */ + +#define BPWM_CAPIF_CAPFIF4_Pos (12) /*!< BPWM_T::CAPIF: CAPFIF4 Position */ +#define BPWM_CAPIF_CAPFIF4_Msk (0x1ul << BPWM_CAPIF_CAPFIF4_Pos) /*!< BPWM_T::CAPIF: CAPFIF4 Mask */ + +#define BPWM_CAPIF_CAPFIF5_Pos (13) /*!< BPWM_T::CAPIF: CAPFIF5 Position */ +#define BPWM_CAPIF_CAPFIF5_Msk (0x1ul << BPWM_CAPIF_CAPFIF5_Pos) /*!< BPWM_T::CAPIF: CAPFIF5 Mask */ + +#define BPWM_PBUF_PBUF_Pos (0) /*!< BPWM_T::PBUF: PBUF Position */ +#define BPWM_PBUF_PBUF_Msk (0xfffful << BPWM_PBUF_PBUF_Pos) /*!< BPWM_T::PBUF: PBUF Mask */ + +#define BPWM_CMPBUF_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF0: CMPBUF Position */ +#define BPWM_CMPBUF_CMPBUF_Msk (0xfffful << BPWM_CMPBUFn_CMPBUF_Pos) /*!< BPWM_T::CMPBUF0: CMPBUF Mask */ + +#define BPWM_CMPBUF0_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF0: CMPBUF Position */ +#define BPWM_CMPBUF0_CMPBUF_Msk (0xfffful << BPWM_CMPBUF0_CMPBUF_Pos) /*!< BPWM_T::CMPBUF0: CMPBUF Mask */ + +#define BPWM_CMPBUF1_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF1: CMPBUF Position */ +#define BPWM_CMPBUF1_CMPBUF_Msk (0xfffful << BPWM_CMPBUF1_CMPBUF_Pos) /*!< BPWM_T::CMPBUF1: CMPBUF Mask */ + +#define BPWM_CMPBUF2_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF2: CMPBUF Position */ +#define BPWM_CMPBUF2_CMPBUF_Msk (0xfffful << BPWM_CMPBUF2_CMPBUF_Pos) /*!< BPWM_T::CMPBUF2: CMPBUF Mask */ + +#define BPWM_CMPBUF3_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF3: CMPBUF Position */ +#define BPWM_CMPBUF3_CMPBUF_Msk (0xfffful << BPWM_CMPBUF3_CMPBUF_Pos) /*!< BPWM_T::CMPBUF3: CMPBUF Mask */ + +#define BPWM_CMPBUF4_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF4: CMPBUF Position */ +#define BPWM_CMPBUF4_CMPBUF_Msk (0xfffful << BPWM_CMPBUF4_CMPBUF_Pos) /*!< BPWM_T::CMPBUF4: CMPBUF Mask */ + +#define BPWM_CMPBUF5_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF5: CMPBUF Position */ +#define BPWM_CMPBUF5_CMPBUF_Msk (0xfffful << BPWM_CMPBUF5_CMPBUF_Pos) /*!< BPWM_T::CMPBUF5: CMPBUF Mask */ + +/**@}*/ /* BPWM_CONST */ +/**@}*/ /* end of BPWM register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __BPWM_REG_H__ */ \ No newline at end of file diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/clk_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/clk_reg.h new file mode 100644 index 00000000000..06a0251a7e4 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/clk_reg.h @@ -0,0 +1,1133 @@ +/**************************************************************************//** + * @file clk_reg.h + * @version V1.00 + * @brief CLK register definition header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __CLK_REG_H__ +#define __CLK_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup CLK System Clock Controller (CLK) + Memory Mapped Structure for CLK Controller +@{ */ + +typedef struct +{ + + + /** + * @var CLK_T::PWRCTL + * Offset: 0x00 System Power-down Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |HXTEN |HXT Enable Bit (Write Protect) + * | | |The bit default value is set by flash controller user configuration register CONFIG0 [26] + * | | |When the default clock source is from HXT, this bit is set to 1 automatically. + * | | |0 = 4~32 MHz external high speed crystal (HXT) Disabled. + * | | |1 = 4~32 MHz external high speed crystal (HXT) Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[1] |LXTEN |LXT Enable Bit (Write Protect) + * | | |0 = 32.768 kHz external low speed crystal (LXT) Disabled. + * | | |1 = 32.768 kHz external low speed crystal (LXT) Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[2] |HIRCEN |HIRC Enable Bit (Write Protect) + * | | |0 = 48MHz internal high speed RC oscillator (HIRC) Disabled. + * | | |1 = 48 MHz internal high speed RC oscillator (HIRC) Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[3] |LIRCEN |LIRC Enable Bit (Write Protect) + * | | |0 = 38.4 kHz internal low speed RC oscillator (LIRC) Disabled. + * | | |1 = 38.4 kHz internal low speed RC oscillator (LIRC) Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note : LIRC will also be forced on when 1 + * | | |Power down and ~(cfg0[3] & cfg0[4] & ~cfg0[31] & cfg0[30]) 2 + * | | |Not power down and ~(cfg0[3] & cfg0[4] & cfg0[31]) + * |[4] |PDWKDLY |Enable the Wake-up Delay Counter (Write Protect) + * | | |When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable. + * | | |The delayed clock cycle is 4096 clock cycles when chip works at 4~32 MHz external high speed crystal oscillator (HXT), HIRC and MIRC see HIRCSTBS and MIRCSTBS + * | | |0 = Clock cycles delay Disabled. + * | | |1 = Clock cycles delay Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[5] |PDWKIEN |Power-down Mode Wake-up Interrupt Enable Bit (Write Protect) + * | | |0 = Power-down mode wake-up interrupt Disabled. + * | | |1 = Power-down mode wake-up interrupt Enabled. + * | | |Note1: The interrupt will occur when both PDWKIF and PDWKIEN are high. + * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[6] |PDWKIF |Power-down Mode Wake-up Interrupt Status + * | | |Set by "Power-down wake-up event", it indicates that resume from Power-down mode. + * | | |The flag is set if any wake-up source is occurred. Refer Power Modes and Wake-up Sources chapter. + * | | |Note1: Write 1 to clear the bit to 0. + * | | |Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1. + * |[7] |PDEN |System Power-down Enable (Write Protect) + * | | |When this bit is set to 1, Power-down mode is enabled and chip Power-down behavior will depend on the PDWTCPU bit. + * | | |(a) If the PDWTCPU is 0, then the chip enters Power-down mode immediately after the PDEN bit set + * | | |(default) + * | | |(b) if the PDWTCPU is 1, then the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode. + * | | |When chip wakes up from Power-down mode, this bit is auto cleared + * | | |Users need to set this bit again for next Power-down. + * | | |In Power-down mode, HXT and the HIRC will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode. + * | | |In Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection + * | | |The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC. + * | | |0 = Chip operating normally or chip in idle mode because of WFI command. + * | | |1 = Chip enters Power-down mode instant or wait CPU sleep command WFI. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[19] |MIRCEN |MIRC Enable Bit (Write Protect) + * | | |0 = 4MHz internal high speed RC oscillator (MIRC) Disabled. + * | | |1 = 4 MHz internal high speed RC oscillator (MIRC) Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note: Will be forced on when CLKSEL0[2:0] = 0x101b. + * |[22:20] |HXTGAIN |HXT Gain Control Bit (Write Protect) + * | | |This is a protected register. Please refer to open lock sequence to program it. + * | | |Gain control is used to enlarge the gain of crystal to make sure crystal work normally + * | | |If gain control is enabled, crystal will consume more power than gain control off. + * | | |000 = HXT frequency 1~4 MHz. + * | | |001 = HXT frequency 4~8 MHz. + * | | |010 = HXT frequency 8~12 MHz. + * | | |011 = HXT frequency 12~16 MHz. + * | | |100 = HXT frequency 12~24 MHz. + * | | |101 = HXT frequency 16~32 Mhz. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note : reset by powr on reset + * @var CLK_T::AHBCLK + * Offset: 0x04 AHB Devices Clock Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |PDMACKEN |PDMA Controller Clock Enable Bit + * | | |0 = PDMA peripheral clock Disabled. + * | | |1 = PDMA peripheral clock Enabled. + * |[2] |ISPCKEN |Flash ISP Controller Clock Enable Bit + * | | |0 = Flash ISP peripheral clock Disabled. + * | | |1 = Flash ISP peripheral clock Enabled. + * |[3] |EBICKEN |EBI Controller Clock Enable Bit + * | | |0 = EBI peripheral clock Disabled. + * | | |1 = EBI peripheral clock Enabled. + * |[7] |CRCCKEN |CRC Generator Controller Clock Enable Bit + * | | |0 = CRC peripheral clock Disabled. + * | | |1 = CRC peripheral clock Enabled. + * |[12] |CRPTCKEN |Cryptographic Accelerator Clock Enable Bit + * | | |0 = Cryptographic Accelerator clock Disabled. + * | | |1 = Cryptographic Accelerator clock Enabled. + * |[15] |FMCIDLE |Flash Memory Controller Clock Enable Bit in IDLE Mode + * | | |0 = FMC clock Disabled when chip is under IDLE mode. + * | | |1 = FMC clock Enabled when chip is under IDLE mode. + * @var CLK_T::APBCLK0 + * Offset: 0x08 APB Devices Clock Enable Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WDTCKEN |Watchdog Timer Clock Enable Bit (Write Protect) + * | | |0 = Watchdog timer clock Disabled. + * | | |1 = Watchdog timer clock Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note : this bit is forced to 1 when cfg0[3] & cfg0[3] & cfg0[31] are all 1s + * |[1] |RTCCKEN |Real-time-clock APB Interface Clock Enable Bit + * | | |This bit is used to control the RTC APB clock only + * | | |The RTC peripheral clock source is selected from RTCSEL(CLK_CLKSEL3[8]) + * | | |It can be selected to 32.768 kHz external low speed crystal or 38.4 kHz internal low speed RC oscillator (LIRC). + * | | |0 = RTC clock Disabled. + * | | |1 = RTC clock Enabled. + * |[2] |TMR0CKEN |Timer0 Clock Enable Bit + * | | |0 = Timer0 clock Disabled. + * | | |1 = Timer0 clock Enabled. + * |[3] |TMR1CKEN |Timer1 Clock Enable Bit + * | | |0 = Timer1 clock Disabled. + * | | |1 = Timer1 clock Enabled. + * |[4] |TMR2CKEN |Timer2 Clock Enable Bit + * | | |0 = Timer2 clock Disabled. + * | | |1 = Timer2 clock Enabled. + * |[5] |TMR3CKEN |Timer3 Clock Enable Bit + * | | |0 = Timer3 clock Disabled. + * | | |1 = Timer3 clock Enabled. + * |[6] |CLKOCKEN |CLKO Clock Enable Bit + * | | |0 = CLKO clock Disabled. + * | | |1 = CLKO clock Enabled. + * |[7] |ACMP01CKEN|Analog Comparator 0/1 Clock Enable Bit + * | | |0 = Analog comparator 0/1 clock Disabled. + * | | |1 = Analog comparator 0/1 clock Enabled. + * |[8] |I2C0CKEN |I2C0 Clock Enable Bit + * | | |0 = I2C0 clock Disabled. + * | | |1 = I2C0 clock Enabled. + * |[9] |I2C1CKEN |I2C1 Clock Enable Bit + * | | |0 = I2C1 clock Disabled. + * | | |1 = I2C1 clock Enabled. + * |[12] |QSPI0CKEN |QSPI0 Clock Enable Bit + * | | |0 = QSPI0 clock Disabled. + * | | |1 = QSPI0 clock Enabled. + * |[13] |SPI0CKEN |SPI0 Clock Enable Bit + * | | |0 = SPI0 clock Disabled. + * | | |1 = SPI0 clock Enabled. + * |[16] |UART0CKEN |UART0 Clock Enable Bit + * | | |0 = UART0 clock Disabled. + * | | |1 = UART0 clock Enabled. + * |[17] |UART1CKEN |UART1 Clock Enable Bit + * | | |0 = UART1 clock Disabled. + * | | |1 = UART1 clock Enabled. + * |[18] |UART2CKEN |UART2 Clock Enable Bit + * | | |0 = UART2 clock Disabled. + * | | |1 = UART2 clock Enabled. + * |[27] |USBDCKEN |USB Device Clock Enable Bit + * | | |0 = USB Device clock Disabled. + * | | |1 = USB Device clock Enabled. + * |[28] |EADCCKEN |Enhanced Analog-digital-converter (EADC) Clock Enable Bit + * | | |0 = EADC clock Disabled. + * | | |1 = EADC clock Enabled. + * @var CLK_T::APBCLK1 + * Offset: 0x0C APB Devices Clock Enable Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SC0CKEN |SC0 Clock Enable Bit + * | | |0 = SC0 clock Disabled. + * | | |1 = SC0 clock Enabled. + * |[8] |USCI0CKEN |USCI0 Clock Enable Bit + * | | |0 = USCI0 clock Disabled. + * | | |1 = USCI0 clock Enabled. + * |[9] |USCI1CKEN |USCI1 Clock Enable Bit + * | | |0 = USCI1 clock Disabled. + * | | |1 = USCI1 clock Enabled. + * |[10] |USCI2CKEN |USCI2 Clock Enable Bit + * | | |0 = USCI1 clock Disabled. + * | | |1 = USCI1 clock Enabled. + * |[12] |DACCKEN |DAC Clock Enable Bit + * | | |0 = DAC clock Disabled. + * | | |1 = DAC clock Enabled. + * |[16] |PWM0CKEN |PWM0 Clock Enable Bit + * | | |0 = PWM0 clock Disabled. + * | | |1 = PWM0 clock Enabled. + * |[17] |PWM1CKEN |PWM1 Clock Enable Bit + * | | |0 = PWM1 clock Disabled. + * | | |1 = PWM1 clock Enabled. + * |[18] |BPWM0CKEN |BPWM0 Clock Enable Bit + * | | |0 = BPWM0 clock Disabled. + * | | |1 = BPWM0 clock Enabled. + * |[19] |BPWM1CKEN |BPWM1 Clock Enable Bit + * | | |0 = BPWM1 clock Disabled. + * | | |1 = BPWM1 clock Enabled. + * |[30] |OPACKEN |OP Amplifier (OPA) Clock Enable Bit + * | | |0 = OPA clock Disabled. + * | | |1 = OPA clock Enabled. + * |[31] |PSIOCKEN |PSIO Clock Enable Bit + * | | |0 = PSIO clock Disabled. + * | | |1 = PSIO clock Enabled. + * @var CLK_T::CLKSEL0 + * Offset: 0x10 Clock Source Select Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |HCLKSEL |HCLK Clock Source Selection (Write Protect) + * | | |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on. + * | | |The default value is reloaded from the value of CFOSC (CONFIG0[26]) in user configuration register of Flash controller by any reset + * | | |Therefore the default value is either 000b or 101b. + * | | |000 = Clock source from HXT. + * | | |001 = Clock source from LXT. + * | | |010 = Clock source from PLL. + * | | |011 = Clock source from LIRC. + * | | |101= Clock source from MIRC. + * | | |111= Clock source from HIRC. + * | | |Other = Reserved. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[5:3] |STCLKSEL |Cortex-M23 SysTick Clock Source Selection (Write Protect) + * | | |If SYST_CTRL[2]=0, SysTick uses listed clock source below. + * | | |000 = Clock source from HXT. + * | | |001 = Clock source from LXT. + * | | |010 = Clock source from HXT/2. + * | | |011 = Clock source from HCLK/2. + * | | |111 = Clock source from HIRC/2. + * | | |Note: if SysTick clock source is not from HCLK (i.e + * | | |SYST_CTRL[2] = 0), SysTick clock source must less than or equal to HCLK/2. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[8] |USBDSEL |USB Device Clock Source Selection (Write Protect) + * | | |These bits are protected bit + * | | |It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection + * | | |Refer to the register REGWRPROT at address GCR_BA+0x100. + * | | |0 = Clock source from HIRC. + * | | |1 = Clock source from PLL. divided + * @var CLK_T::CLKSEL1 + * Offset: 0x14 Clock Source Select Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |WDTSEL |Watchdog Timer Clock Source Selection (Write Protect) + * | | |00 = Reserved. + * | | |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |10 = Clock source from HCLK/2048. + * | | |11 = Clock source from 38.4 kHz internal low speed RC oscillator (LIRC). + * | | |Note: This bit is write protected.Refer to the SYS_REGLCTL register + * | | |Note: This bit is forced to 11 when CONFIG0[31], CONFIG0[4], CONFIG0[3] are all ones. + * |[3:2] |WWDTSEL |Window Watchdog Timer Clock Source Selection (Write Protect) + * | | |10 = Clock source from HCLK/2048. + * | | |11 = Clock source from 38.4 kHz internal low speed RC oscillator (LIRC). + * | | |Others = Reserved. + * |[6:4] |CLKOSEL |Clock Divider Clock Source Selection + * | | |000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from HCLK. + * | | |011 = Clock source from 48 MHz internal high speed RC oscillator (HIRC). + * | | |100 = Clock source from 38.4 kHz internal low speed RC oscillator (LIRC). + * | | |101 = Clock source from 4 MHz internal medium speed RC oscillator (MIRC). + * | | |110 = Clock source from PLL. + * | | |111 = Clock source from internal USB synchronous mode. + * |[10:8] |TMR0SEL |TIMER0 Clock Source Selection + * | | |000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK0. + * | | |011 = Clock source from external clock T0 pin. + * | | |101 = Clock source from 38.4 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 48 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[14:12] |TMR1SEL |TIMER1 Clock Source Selection + * | | |000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK0. + * | | |011 = Clock source from external clock T1 pin. + * | | |101 = Clock source from 38.4 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 48 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[18:16] |TMR2SEL |TIMER2 Clock Source Selection + * | | |000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK1. + * | | |011 = Clock source from external clock T2 pin. + * | | |101 = Clock source from 38.4 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 48 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[22:20] |TMR3SEL |TIMER3 Clock Source Selection + * | | |000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK1. + * | | |011 = Clock source from external clock T3 pin. + * | | |101 = Clock source from 38.4 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 48 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[26:24] |UART0SEL |UART0 Clock Source Selection + * | | |000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from PLL. + * | | |010 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |011 = Clock source from 48 MHz internal high speed RC oscillator (HIRC). + * | | |100= PCLK0-> default. + * | | |101= LIRC + * |[30:28] |UART1SEL |UART1 Clock Source Selection + * | | |000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from PLL. + * | | |010 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |011 = Clock source from 48 MHz internal high speed RC oscillator (HIRC). + * | | |100= PCLK1 -> default. + * | | |101= LIRC + * @var CLK_T::CLKSEL2 + * Offset: 0x18 Clock Source Select Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PWM0SEL |PWM0 Clock Source Selection + * | | |The peripheral clock source of PWM0 is defined by PWM0SEL. + * | | |0 = Clock source from PLL. + * | | |1 = Clock source from PCLK0. + * |[1] |PWM1SEL |PWM1 Clock Source Selection + * | | |The peripheral clock source of PWM1 is defined by PWM1SEL. + * | | |0 = Clock source from PLL. + * | | |1 = Clock source from PCLK1. + * |[3:2] |QSPI0SEL |QSPI0 Clock Source Selection + * | | |00 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK0. + * | | |11 = Clock source from 48 MHz internal high speed RC oscillator (HIRC). + * |[5:4] |SPI0SEL |SPI0 Clock Source Selection + * | | |00 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK1. + * | | |11 = Clock source from 48 MHz internal high speed RC oscillator (HIRC). + * |[8] |BPWM0SEL |BPWM0 Clock Source Selection + * | | |The peripheral clock source of BPWM0 is defined by BPWM0SEL. + * | | |0 = Clock source from PLL. + * | | |1 = Clock source from PCLK0. + * |[9] |BPWM1SEL |BPWM1 Clock Source Selection + * | | |The peripheral clock source of BPWM1 is defined by BPWM1SEL. + * | | |0 = Clock source from PLL. + * | | |1 = Clock source from PCLK1. + * |[30:28] |PSIOSEL |PSIO Clock Source Selection + * | | |000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK1. + * | | |011 = Clock source from PLL. + * | | |100 = Clock source from 38.4 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 48 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * @var CLK_T::CLKSEL3 + * Offset: 0x1C Clock Source Select Control Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |SC0SEL |SC0 Clock Source Selection + * | | |00 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK0. + * | | |11 = Clock source from 48 MHz internal high speed RC oscillator (HIRC). + * |[26:24] |UART2SEL |UART2 Clock Source Selection + * | | |000 = Clock source from 4~32 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from PLL. + * | | |010 = Reserved. + * | | |010 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |011 = Clock source from 48 MHz internal high speed RC oscillator (HIRC). + * | | |100= PCLK 0-> default. + * | | |101= LIRC + * @var CLK_T::CLKDIV0 + * Offset: 0x20 Clock Divider Number Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |HCLKDIV |HCLK Clock Divide Number From HCLK Clock Source + * | | |HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1). + * |[7:4] |USBDIV |USB Clock Divide Number From PLL Clock + * | | |USB clock frequency = (PLL frequency) / (USBDIV + 1). + * |[11:8] |UART0DIV |UART0 Clock Divide Number From UART0 Clock Source + * | | |UART0 clock frequency = (UART0 clock source frequency) / (UART0DIV + 1). + * |[15:12] |UART1DIV |UART1 Clock Divide Number From UART1 Clock Source + * | | |UART1 clock frequency = (UART1 clock source frequency) / (UART1DIV + 1). + * |[23:16] |EADCDIV |EADC Clock Divide Number From EADC Clock Source + * | | |EADC clock frequency = (EADC clock source frequency) / (EADCDIV + 1). + * @var CLK_T::CLKDIV1 + * Offset: 0x24 Clock Divider Number Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |SC0DIV |SC0 Clock Divide Number From SC0 Clock Source + * | | |SC0 clock frequency = (SC0 clock source frequency ) / (SC0DIV + 1). + * |[31:24] |PSIODIV |PSIO Clock Divide Number From PSIO Clock Source + * | | |PSIO clock frequency = (PSIO clock source frequency ) / (PSIODIV + 1). + * @var CLK_T::CLKDIV4 + * Offset: 0x30 Clock Divider Number Register 4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |UART2DIV |UART2 Clock Divide Number From UART2 Clock Source + * | | |UART2 clock frequency = (UART2 clock source frequency) / (UART2DIV + 1). + * @var CLK_T::PCLKDIV + * Offset: 0x34 APB Clock Divider Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |APB0DIV |APB0 Clock DIvider + * | | |APB0 clock can be divided from HCLK + * | | |000: PCLK0 = HCLK. + * | | |001: PCLK0 = 1/2 HCLK. + * | | |010: PCLK0 = 1/4 HCLK. + * | | |011: PCLK0 = 1/8 HCLK. + * | | |100: PCLK0 = 1/16 HCLK. + * | | |101: PCLK0 = 1/32 HCLK. + * | | |Others: Reserved. + * |[6:4] |APB1DIV |APB1 Clock DIvider + * | | |APB1 clock can be divided from HCLK + * | | |000: PCLK1 = HCLK. + * | | |001: PCLK1 = 1/2 HCLK. + * | | |010: PCLK1 = 1/4 HCLK. + * | | |011: PCLK1 = 1/8 HCLK. + * | | |100: PCLK1 = 1/16 HCLK. + * | | |101: PCLK1 = 1/32 HCLK. + * | | |Others: Reserved. + * @var CLK_T::PLLCTL + * Offset: 0x40 PLL Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |FBDIV |PLL Feedback Divider Control (Write Protect) + * | | |Refer to the formulas below the table. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[12:9] |INDIV |PLL Input Divider Control (Write Protect) + * | | |Refer to the formulas below the table. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[15:14] |OUTDIV |PLL Output Divider Control (Write Protect) + * | | |Refer to the formulas below the table. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[16] |PD |Power-down Mode (Write Protect) + * | | |If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too. + * | | |0 = PLL is in normal mode. + * | | |1 = PLL is in Power-down mode (default). + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[17] |BP |PLL Bypass Control (Write Protect) + * | | |0 = PLL is in normal mode (default). + * | | |1 = PLL clock output is same as PLL input clock FIN. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[18] |OE |PLL OE (FOUT Enable) Pin Control (Write Protect) + * | | |0 = PLL FOUT Enabled. + * | | |1 = PLL FOUT is fixed low. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[20:19] |PLLSRC |PLL Source Clock Selection (Write Protect) + * | | |00 = PLL source clock from 4~32 MHz external high-speed crystal oscillator (HXT). + * | | |01 = PLL source clock from 12 MHz internal high-speed oscillator (HIRC/4). + * | | |10 = PLL source clock from 4~32 MHz external high-speed crystal oscillator (HXT). + * | | |11 = PLL source clock from 4 MHz internal high-speed oscillator (MIRC). + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note: MIRC and HIRC have to be both on when source switch between them + * |[23] |STBSEL |PLL Stable Counter Selection (Write Protect) + * | | |0 = PLL stable time is 1200 PLL source clock (suitable for source clock is equal to or less than 12 MHz). + * | | |1 = PLL stable time is 2400 PLL source clock (suitable for source clock is larger than 12 MHz). + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[24] |PLL_CLF_EN|1: PLL Clock Filter On + * | | |0 : OFF + * @var CLK_T::STATUS + * Offset: 0x50 Clock Status Monitor Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |HXTSTB |HXT Clock Source Stable Flag (Read Only) + * | | |0 = 4~32 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled. + * | | |1 = 4~32 MHz external high speed crystal oscillator (HXT) clock is stable and enabled. + * |[1] |LXTSTB |LXT Clock Source Stable Flag (Read Only) + * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled. + * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled. + * |[2] |PLLSTB |Internal PLL Clock Source Stable Flag (Read Only) + * | | |0 = Internal PLL clock is not stable or disabled. + * | | |1 = Internal PLL clock is stable and enabled. + * |[3] |LIRCSTB |LIRC Clock Source Stable Flag (Read Only) + * | | |0 = 38.4 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled. + * | | |1 = 38.4 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled. + * |[4] |HIRCSTB |HIRC Clock Source Stable Flag (Read Only) + * | | |0 = 48 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled. + * | | |1 = 48 MHz internal high speed RC oscillator (HIRC) clock is stable and enabled. + * |[6] |MIRCSTB |MIRC Clock Source Stable Flag (Read Only) + * | | |0 = 4 MHz internal mid speed RC oscillator (MIRC) clock is not stable or disabled. + * | | |1 = 4 MHz internal mid speed RC oscillator (MIRC) clock is stable and enabled. + * |[7] |CLKSFAIL |Clock Switching Fail Flag (Read Only) + * | | |This bit is updated when software switches system clock source + * | | |If switch target clock is stable, this bit will be set to 0 + * | | |If switch target clock is not stable, this bit will be set to 1. + * | | |0 = Clock switching success. + * | | |1 = Clock switching failure. + * | | |Note: Write 1 to clear the bit to 0. + * @var CLK_T::CLKOCTL + * Offset: 0x60 Clock Output Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |FREQSEL |Clock Output Frequency Selection + * | | |The formula of output frequency is + * | | |Fout = Fin/2(N+1). + * | | |Fin is the input clock frequency. + * | | |Fout is the frequency of divider output clock. + * | | |N is the 4-bit value of FREQSEL[3:0]. + * |[4] |CLKOEN |Clock Output Enable Bit + * | | |0 = Clock Output function Disabled. + * | | |1 = Clock Output function Enabled. + * |[5] |DIV1EN |Clock Output Divide One Enable Bit + * | | |0 = Clock Output will output clock with source frequency divided by FREQSEL. + * | | |1 = Clock Output will output clock with source frequency. + * |[6] |CLK1HZEN |Clock Output 1Hz Enable Bit + * | | |0 = 1 Hz clock output for 32.768 kHz frequency compensation Disabled. + * | | |1 = 1 Hz clock output for 32.768 kHz frequency compensation Enabled. + * @var CLK_T::CLKDCTL + * Offset: 0x70 Clock Fail Detector Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4] |HXTFDEN |HXT Clock Fail Detector Enable Bit + * | | |0 = 4~32 MHz external high speed crystal oscillator (HXT) clock fail detector Disabled. + * | | |1 = 4~32 MHz external high speed crystal oscillator (HXT) clock fail detector Enabled. + * |[5] |HXTFIEN |HXT Clock Fail Interrupt Enable Bit + * | | |0 = 4~32 MHz external high speed crystal oscillator (HXT) clock fail interrupt Disabled. + * | | |1 = 4~32 MHz external high speed crystal oscillator (HXT) clock fail interrupt Enabled. + * |[12] |LXTFDEN |LXT Clock Fail Detector Enable Bit + * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Disabled. + * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Enabled. + * |[13] |LXTFIEN |LXT Clock Fail Interrupt Enable Bit + * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Disabled. + * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Enabled. + * |[16] |HXTFQDEN |HXT Clock Frequency Range Detector Enable Bit + * | | |0 = 4~32 MHz external high speed crystal oscillator (HXT) clock frequency range detector Disabled. + * | | |1 = 4~32 MHz external high speed crystal oscillator (HXT) clock frequency range detector Enabled. + * |[17] |HXTFQIEN |HXT Clock Frequency Range Detector Interrupt Enable Bit + * | | |0 = 4~32 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Disabled. + * | | |1 = 4~32 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Enabled. + * @var CLK_T::CLKDSTS + * Offset: 0x74 Clock Fail Detector Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |HXTFIF |HXT Clock Fail Interrupt Flag (Write Protect) + * | | |0 = 4~32 MHz external high speed crystal oscillator (HXT) clock is normal. + * | | |1 = 4~32 MHz external high speed crystal oscillator (HXT) clock stops. + * | | |Note: Write 1 to clear the bit to 0. + * |[1] |LXTFIF |LXT Clock Fail Interrupt Flag (Write Protect) + * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is normal. + * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) stops. + * | | |Note: Write 1 to clear the bit to 0. + * |[8] |HXTFQIF |HXT Clock Frequency Range Detector Interrupt Flag (Write Protect) + * | | |0 = 4~32 MHz external high speed crystal oscillator (HXT) clock frequency is normal. + * | | |1 = 4~32 MHz external high speed crystal oscillator (HXT) clock frequency is abnormal. + * | | |Note: Write 1 to clear the bit to 0. + * @var CLK_T::CDUPB + * Offset: 0x78 Clock Frequency Range Detector Upper Boundary Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |UPERBD |HXT Clock Frequency Range Detector Upper Boundary Value + * | | |The bits define the maximum value of frequency range detector window. + * | | |When HXT frequency higher than this maximum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1. + * @var CLK_T::CDLOWB + * Offset: 0x7C Clock Frequency Range Detector Lower Boundary Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |LOWERBD |HXT Clock Frequency Range Detector Lower Boundary Value + * | | |The bits define the minimum value of frequency range detector window. + * | | |When HXT frequency lower than this minimum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1. + * @var CLK_T::PMUCTL + * Offset: 0x90 Power Manager Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |PDMSEL |Power-down Mode Selection (Write Protect) + * | | |This is a protected register. Please refer to open lock sequence to program it. + * | | |These bits control chip power-down mode grade selection when CPU execute WFI/WFE instruction. + * | | |000 = Power-down mode is selected. (PD) + * | | |010 = fast wake up.(FWPD) + * | | |110 = Deep Power-down mode is selected (DPD). + * | | |others = Reserved. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[8] |WKTMREN |Wake-up Timer Enable (Write Protect) + * | | |This is a protected register. Please refer to open lock sequence to program it. + * | | |0 = Wake-up timer disable at DPD mode. + * | | |1 = Wake-up timer enabled at DPD mode. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[11:9] |WKTMRIS |Wake-up Timer Time-out Interval Select (Write Protect) + * | | |This is a protected register. Please refer to open lock sequence to program it. + * | | |These bits control wake-up timer time-out interval when chip at DPD mode. + * | | |000 = Time-out interval is 128 OSC32K clocks (~3.368 ms). + * | | |001 = Time-out interval is 256 OSC32K clocks (~6.736 ms). + * | | |010 = Time-out interval is 512 OSC32K clocks (~13.47 ms). + * | | |011 = Time-out interval is 1024 OSC32K clocks (~26.95 ms). + * | | |100 = Time-out interval is 4096 OSC32K clocks (~107.79 ms). + * | | |101 = Time-out interval is 8192 OSC32K clocks (~215.58 ms). + * | | |110 = Time-out interval is 16384 OSC32K clocks (~431.16 ms). + * | | |111 = Time-out interval is 32768 OSC32K clocks (~862.32 ms). + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[17:16] |WKPINEN0 |Wake-up Pin Enable 0(Write Protect) + * | | |This is a protected register. Please refer to open lock sequence to program it. + * | | |This is control register for GPC.0 to wake-up pin. + * | | |00 = Wake-up pin disable at Deep Power-down mode. + * | | |01 = Wake-up pin rising edge enabled at Deep Power-down mode. + * | | |10 = Wake-up pin falling edge enabled at Deep Power-down mode. + * | | |11 = Wake-up pin both edge enabled at Deep Power-down mode. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[22] |WKPINDBEN |Wake-up pin De-bounce Enable Bit (Write Protect) + * | | |The WKPINDBEN bit is used to enable the de-bounce function for wake-up pin. + * | | |If the input signal pulse width cannot be sampled by continuous eight de-bounce sample cycle, + * | | |the input signal transition is seen as the signal bounce and will not trigger the wakeup. + * | | |The de-bounce clock source is the 38 kHz internal low speed RC oscillator (LIRC). + * | | |0 = Deep power-down wake-up pin De-bounce function disable. + * | | |1 = Deep power-down wake-up pin De-bounce function enable. + * | | |The de-bounce function is valid only for edge triggered + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[23] |RTCWKEN |RTC Wake-up Enable (Write Protect) + * | | |This is a protected register. Please refer to open lock sequence to program it. + * | | |0 = RTC wake-up disable at Deep Power-down mode or Standby Power-down mode. + * | | |1 = RTC wake-up enabled at Deep Power-down mode or Standby Power-down mode. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[25:24] |WKPINEN1 |Wake-up Pin Enable 1(Write Protect) + * | | |This is a protected register. Please refer to open lock sequence to program it. + * | | |This is control register for GPB.0 to wake-up pin. + * | | |00 = Wake-up pin disable at Deep Power-down mode. + * | | |01 = Wake-up pin rising edge enabled at Deep Power-down mode. + * | | |10 = Wake-up pin falling edge enabled at Deep Power-down mode. + * | | |11 = Wake-up pin both edge enabled at Deep Power-down mode. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register + * |[27:26] |WKPINEN2 |Wake-up Pin Enable 2(Write Protect) + * | | |This is a protected register. Please refer to open lock sequence to program it. + * | | |This is control register for GPB.2 to wake-up pin. + * | | |00 = Wake-up pin disable at Deep Power-down mode. + * | | |01 = Wake-up pin rising edge enabled at Deep Power-down mode. + * | | |10 = Wake-up pin falling edge enabled at Deep Power-down mode. + * | | |11 = Wake-up pin both edge enabled at Deep Power-down mode. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[29:28] |WKPINEN3 |Wake-up Pin Enable 3(Write Protect) + * | | |This is a protected register. Please refer to open lock sequence to program it. + * | | |This is control register for GPB.12 to wake-up pin. + * | | |00 = Wake-up pin disable at Deep Power-down mode. + * | | |01 = Wake-up pin rising edge enabled at Deep Power-down mode. + * | | |10 = Wake-up pin falling edge enabled at Deep Power-down mode. + * | | |11 = Wake-up pin both edge enabled at Deep Power-down mode. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[31:30] |WKPINEN4 |Wake-up Pin Enable 4(Write Protect) + * | | |This is a protected register. Please refer to open lock sequence to program it. + * | | |This is control register for GPF.6 to wake-up pin. + * | | |00 = Wake-up pin disable at Deep Power-down mode. + * | | |01 = Wake-up pin rising edge enabled at Deep Power-down mode. + * | | |10 = Wake-up pin falling edge enabled at Deep Power-down mode. + * | | |11 = Wake-up pin both edge enabled at Deep Power-down mode. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var CLK_T::PMUSTS + * Offset: 0x94 Power Manager Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PINWK0 |Pin Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (GPC.0) + * | | |This flag is cleared when DPD mode is entered. + * |[1] |TMRWK |Timer Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) was requested by wakeup timer time-out + * | | |This flag is cleared when DPD mode is entered. + * |[2] |RTCWK |RTC Wake-up Flag (Read Only) + * | | |This flag indicates that wakeup of device from Deep Power-down mode (DPD) was requested with a RTC alarm, tick time or tamper happened + * | | |This flag is cleared when DPD mode is entered. + * |[3] |PINWK1 |Pin Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (GPB.0) + * | | |This flag is cleared when DPD mode is entered. + * |[4] |PINWK2 |Pin Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (GPB.2) + * | | |This flag is cleared when DPD mode is entered. + * |[5] |PINWK3 |Pin Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (GPB.12) + * | | |This flag is cleared when DPD mode is entered. + * |[6] |PINWK4 |Pin Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (GPF.6) + * | | |This flag is cleared when DPD mode is entered. + * |[12] |LVRWK |LVR Wake-up Flag (Read Only) + * | | |This flag indicates that wakeup of device from Deep Power-down mode was requested with a LVR happened + * | | |This flag is cleared when DPD mode is entered. + * |[31] |CLRWK |Clear Wake-up Flag + * | | |0 = No clear. + * | | |1= Clear all wake-up flag. + * @var CLK_T::HXTFSEL + * Offset: 0xB4 HXT Filter Select Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |HXTFSEL |HXT Filter Select (Write Protect) + * | | |0 = HXT frequency is > 12MHz. + * | | |1 = HXT frequency is <= 12MHz. + */ + __IO uint32_t PWRCTL; /*!< [0x0000] System Power-down Control Register */ + __IO uint32_t AHBCLK; /*!< [0x0004] AHB Devices Clock Enable Control Register */ + __IO uint32_t APBCLK0; /*!< [0x0008] APB Devices Clock Enable Control Register 0 */ + __IO uint32_t APBCLK1; /*!< [0x000c] APB Devices Clock Enable Control Register 1 */ + __IO uint32_t CLKSEL0; /*!< [0x0010] Clock Source Select Control Register 0 */ + __IO uint32_t CLKSEL1; /*!< [0x0014] Clock Source Select Control Register 1 */ + __IO uint32_t CLKSEL2; /*!< [0x0018] Clock Source Select Control Register 2 */ + __IO uint32_t CLKSEL3; /*!< [0x001c] Clock Source Select Control Register 3 */ + __IO uint32_t CLKDIV0; /*!< [0x0020] Clock Divider Number Register 0 */ + __IO uint32_t CLKDIV1; /*!< [0x0024] Clock Divider Number Register 1 */ + __I uint32_t RESERVE0[2]; + __IO uint32_t CLKDIV4; /*!< [0x0030] Clock Divider Number Register 4 */ + __IO uint32_t PCLKDIV; /*!< [0x0034] APB Clock Divider Register */ + __I uint32_t RESERVE1[2]; + __IO uint32_t PLLCTL; /*!< [0x0040] PLL Control Register */ + __I uint32_t RESERVE2[3]; + __I uint32_t STATUS; /*!< [0x0050] Clock Status Monitor Register */ + __I uint32_t RESERVE3[3]; + __IO uint32_t CLKOCTL; /*!< [0x0060] Clock Output Control Register */ + __I uint32_t RESERVE4[3]; + __IO uint32_t CLKDCTL; /*!< [0x0070] Clock Fail Detector Control Register */ + __IO uint32_t CLKDSTS; /*!< [0x0074] Clock Fail Detector Status Register */ + __IO uint32_t CDUPB; /*!< [0x0078] Clock Frequency Range Detector Upper Boundary Register */ + __IO uint32_t CDLOWB; /*!< [0x007c] Clock Frequency Range Detector Lower Boundary Register */ + __I uint32_t RESERVE5[4]; + __IO uint32_t PMUCTL; /*!< [0x0090] Power Manager Control Register */ + __IO uint32_t PMUSTS; /*!< [0x0094] Power Manager Status Register */ + __I uint32_t RESERVE6[7]; + __IO uint32_t HXTFSEL; /*!< [0x00b4] HXT Filter Select Control Register */ + +} CLK_T; + +/** + @addtogroup CLK_CONST CLK Bit Field Definition + Constant Definitions for CLK Controller +@{ */ + +#define CLK_PWRCTL_HXTEN_Pos (0) /*!< CLK_T::PWRCTL: HXTEN Position */ +#define CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos) /*!< CLK_T::PWRCTL: HXTEN Mask */ + +#define CLK_PWRCTL_LXTEN_Pos (1) /*!< CLK_T::PWRCTL: LXTEN Position */ +#define CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos) /*!< CLK_T::PWRCTL: LXTEN Mask */ + +#define CLK_PWRCTL_HIRCEN_Pos (2) /*!< CLK_T::PWRCTL: HIRCEN Position */ +#define CLK_PWRCTL_HIRCEN_Msk (0x1ul << CLK_PWRCTL_HIRCEN_Pos) /*!< CLK_T::PWRCTL: HIRCEN Mask */ + +#define CLK_PWRCTL_LIRCEN_Pos (3) /*!< CLK_T::PWRCTL: LIRCEN Position */ +#define CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos) /*!< CLK_T::PWRCTL: LIRCEN Mask */ + +#define CLK_PWRCTL_PDWKDLY_Pos (4) /*!< CLK_T::PWRCTL: PDWKDLY Position */ +#define CLK_PWRCTL_PDWKDLY_Msk (0x1ul << CLK_PWRCTL_PDWKDLY_Pos) /*!< CLK_T::PWRCTL: PDWKDLY Mask */ + +#define CLK_PWRCTL_PDWKIEN_Pos (5) /*!< CLK_T::PWRCTL: PDWKIEN Position */ +#define CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos) /*!< CLK_T::PWRCTL: PDWKIEN Mask */ + +#define CLK_PWRCTL_PDWKIF_Pos (6) /*!< CLK_T::PWRCTL: PDWKIF Position */ +#define CLK_PWRCTL_PDWKIF_Msk (0x1ul << CLK_PWRCTL_PDWKIF_Pos) /*!< CLK_T::PWRCTL: PDWKIF Mask */ + +#define CLK_PWRCTL_PDEN_Pos (7) /*!< CLK_T::PWRCTL: PDEN Position */ +#define CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos) /*!< CLK_T::PWRCTL: PDEN Mask */ + +#define CLK_PWRCTL_MIRCEN_Pos (19) /*!< CLK_T::PWRCTL: MIRCEN Position */ +#define CLK_PWRCTL_MIRCEN_Msk (0x1ul << CLK_PWRCTL_MIRCEN_Pos) /*!< CLK_T::PWRCTL: MIRCEN Mask */ + +#define CLK_PWRCTL_HXTGAIN_Pos (20) /*!< CLK_T::PWRCTL: HXTGAIN Position */ +#define CLK_PWRCTL_HXTGAIN_Msk (0x7ul << CLK_PWRCTL_HXTGAIN_Pos) /*!< CLK_T::PWRCTL: HXTGAIN Mask */ + +#define CLK_AHBCLK_PDMACKEN_Pos (1) /*!< CLK_T::AHBCLK: PDMACKEN Position */ +#define CLK_AHBCLK_PDMACKEN_Msk (0x1ul << CLK_AHBCLK_PDMACKEN_Pos) /*!< CLK_T::AHBCLK: PDMACKEN Mask */ + +#define CLK_AHBCLK_ISPCKEN_Pos (2) /*!< CLK_T::AHBCLK: ISPCKEN Position */ +#define CLK_AHBCLK_ISPCKEN_Msk (0x1ul << CLK_AHBCLK_ISPCKEN_Pos) /*!< CLK_T::AHBCLK: ISPCKEN Mask */ + +#define CLK_AHBCLK_EBICKEN_Pos (3) /*!< CLK_T::AHBCLK: EBICKEN Position */ +#define CLK_AHBCLK_EBICKEN_Msk (0x1ul << CLK_AHBCLK_EBICKEN_Pos) /*!< CLK_T::AHBCLK: EBICKEN Mask */ + +#define CLK_AHBCLK_CRCCKEN_Pos (7) /*!< CLK_T::AHBCLK: CRCCKEN Position */ +#define CLK_AHBCLK_CRCCKEN_Msk (0x1ul << CLK_AHBCLK_CRCCKEN_Pos) /*!< CLK_T::AHBCLK: CRCCKEN Mask */ + +#define CLK_AHBCLK_CRPTCKEN_Pos (12) /*!< CLK_T::AHBCLK: CRPTCKEN Position */ +#define CLK_AHBCLK_CRPTCKEN_Msk (0x1ul << CLK_AHBCLK_CRPTCKEN_Pos) /*!< CLK_T::AHBCLK: CRPTCKEN Mask */ + +#define CLK_AHBCLK_FMCIDLE_Pos (15) /*!< CLK_T::AHBCLK: FMCIDLE Position */ +#define CLK_AHBCLK_FMCIDLE_Msk (0x1ul << CLK_AHBCLK_FMCIDLE_Pos) /*!< CLK_T::AHBCLK: FMCIDLE Mask */ + +#define CLK_APBCLK0_WDTCKEN_Pos (0) /*!< CLK_T::APBCLK0: WDTCKEN Position */ +#define CLK_APBCLK0_WDTCKEN_Msk (0x1ul << CLK_APBCLK0_WDTCKEN_Pos) /*!< CLK_T::APBCLK0: WDTCKEN Mask */ + +#define CLK_APBCLK0_RTCCKEN_Pos (1) /*!< CLK_T::APBCLK0: RTCCKEN Position */ +#define CLK_APBCLK0_RTCCKEN_Msk (0x1ul << CLK_APBCLK0_RTCCKEN_Pos) /*!< CLK_T::APBCLK0: RTCCKEN Mask */ + +#define CLK_APBCLK0_TMR0CKEN_Pos (2) /*!< CLK_T::APBCLK0: TMR0CKEN Position */ +#define CLK_APBCLK0_TMR0CKEN_Msk (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos) /*!< CLK_T::APBCLK0: TMR0CKEN Mask */ + +#define CLK_APBCLK0_TMR1CKEN_Pos (3) /*!< CLK_T::APBCLK0: TMR1CKEN Position */ +#define CLK_APBCLK0_TMR1CKEN_Msk (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos) /*!< CLK_T::APBCLK0: TMR1CKEN Mask */ + +#define CLK_APBCLK0_TMR2CKEN_Pos (4) /*!< CLK_T::APBCLK0: TMR2CKEN Position */ +#define CLK_APBCLK0_TMR2CKEN_Msk (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos) /*!< CLK_T::APBCLK0: TMR2CKEN Mask */ + +#define CLK_APBCLK0_TMR3CKEN_Pos (5) /*!< CLK_T::APBCLK0: TMR3CKEN Position */ +#define CLK_APBCLK0_TMR3CKEN_Msk (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos) /*!< CLK_T::APBCLK0: TMR3CKEN Mask */ + +#define CLK_APBCLK0_CLKOCKEN_Pos (6) /*!< CLK_T::APBCLK0: CLKOCKEN Position */ +#define CLK_APBCLK0_CLKOCKEN_Msk (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos) /*!< CLK_T::APBCLK0: CLKOCKEN Mask */ + +#define CLK_APBCLK0_ACMP01CKEN_Pos (7) /*!< CLK_T::APBCLK0: ACMP01CKEN Position */ +#define CLK_APBCLK0_ACMP01CKEN_Msk (0x1ul << CLK_APBCLK0_ACMP01CKEN_Pos) /*!< CLK_T::APBCLK0: ACMP01CKEN Mask */ + +#define CLK_APBCLK0_I2C0CKEN_Pos (8) /*!< CLK_T::APBCLK0: I2C0CKEN Position */ +#define CLK_APBCLK0_I2C0CKEN_Msk (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos) /*!< CLK_T::APBCLK0: I2C0CKEN Mask */ + +#define CLK_APBCLK0_I2C1CKEN_Pos (9) /*!< CLK_T::APBCLK0: I2C1CKEN Position */ +#define CLK_APBCLK0_I2C1CKEN_Msk (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos) /*!< CLK_T::APBCLK0: I2C1CKEN Mask */ + +#define CLK_APBCLK0_QSPI0CKEN_Pos (12) /*!< CLK_T::APBCLK0: QSPI0CKEN Position */ +#define CLK_APBCLK0_QSPI0CKEN_Msk (0x1ul << CLK_APBCLK0_QSPI0CKEN_Pos) /*!< CLK_T::APBCLK0: QSPI0CKEN Mask */ + +#define CLK_APBCLK0_SPI0CKEN_Pos (13) /*!< CLK_T::APBCLK0: SPI0CKEN Position */ +#define CLK_APBCLK0_SPI0CKEN_Msk (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos) /*!< CLK_T::APBCLK0: SPI0CKEN Mask */ + +#define CLK_APBCLK0_UART0CKEN_Pos (16) /*!< CLK_T::APBCLK0: UART0CKEN Position */ +#define CLK_APBCLK0_UART0CKEN_Msk (0x1ul << CLK_APBCLK0_UART0CKEN_Pos) /*!< CLK_T::APBCLK0: UART0CKEN Mask */ + +#define CLK_APBCLK0_UART1CKEN_Pos (17) /*!< CLK_T::APBCLK0: UART1CKEN Position */ +#define CLK_APBCLK0_UART1CKEN_Msk (0x1ul << CLK_APBCLK0_UART1CKEN_Pos) /*!< CLK_T::APBCLK0: UART1CKEN Mask */ + +#define CLK_APBCLK0_UART2CKEN_Pos (18) /*!< CLK_T::APBCLK0: UART2CKEN Position */ +#define CLK_APBCLK0_UART2CKEN_Msk (0x1ul << CLK_APBCLK0_UART2CKEN_Pos) /*!< CLK_T::APBCLK0: UART2CKEN Mask */ + +#define CLK_APBCLK0_USBDCKEN_Pos (27) /*!< CLK_T::APBCLK0: USBDCKEN Position */ +#define CLK_APBCLK0_USBDCKEN_Msk (0x1ul << CLK_APBCLK0_USBDCKEN_Pos) /*!< CLK_T::APBCLK0: USBDCKEN Mask */ + +#define CLK_APBCLK0_EADCCKEN_Pos (28) /*!< CLK_T::APBCLK0: EADCCKEN Position */ +#define CLK_APBCLK0_EADCCKEN_Msk (0x1ul << CLK_APBCLK0_EADCCKEN_Pos) /*!< CLK_T::APBCLK0: EADCCKEN Mask */ + +#define CLK_APBCLK1_SC0CKEN_Pos (0) /*!< CLK_T::APBCLK1: SC0CKEN Position */ +#define CLK_APBCLK1_SC0CKEN_Msk (0x1ul << CLK_APBCLK1_SC0CKEN_Pos) /*!< CLK_T::APBCLK1: SC0CKEN Mask */ + +#define CLK_APBCLK1_USCI0CKEN_Pos (8) /*!< CLK_T::APBCLK1: USCI0CKEN Position */ +#define CLK_APBCLK1_USCI0CKEN_Msk (0x1ul << CLK_APBCLK1_USCI0CKEN_Pos) /*!< CLK_T::APBCLK1: USCI0CKEN Mask */ + +#define CLK_APBCLK1_USCI1CKEN_Pos (9) /*!< CLK_T::APBCLK1: USCI1CKEN Position */ +#define CLK_APBCLK1_USCI1CKEN_Msk (0x1ul << CLK_APBCLK1_USCI1CKEN_Pos) /*!< CLK_T::APBCLK1: USCI1CKEN Mask */ + +#define CLK_APBCLK1_USCI2CKEN_Pos (10) /*!< CLK_T::APBCLK1: USCI2CKEN Position */ +#define CLK_APBCLK1_USCI2CKEN_Msk (0x1ul << CLK_APBCLK1_USCI2CKEN_Pos) /*!< CLK_T::APBCLK1: USCI2CKEN Mask */ + +#define CLK_APBCLK1_DACCKEN_Pos (12) /*!< CLK_T::APBCLK1: DACCKEN Position */ +#define CLK_APBCLK1_DACCKEN_Msk (0x1ul << CLK_APBCLK1_DACCKEN_Pos) /*!< CLK_T::APBCLK1: DACCKEN Mask */ + +#define CLK_APBCLK1_PWM0CKEN_Pos (16) /*!< CLK_T::APBCLK1: PWM0CKEN Position */ +#define CLK_APBCLK1_PWM0CKEN_Msk (0x1ul << CLK_APBCLK1_PWM0CKEN_Pos) /*!< CLK_T::APBCLK1: PWM0CKEN Mask */ + +#define CLK_APBCLK1_PWM1CKEN_Pos (17) /*!< CLK_T::APBCLK1: PWM1CKEN Position */ +#define CLK_APBCLK1_PWM1CKEN_Msk (0x1ul << CLK_APBCLK1_PWM1CKEN_Pos) /*!< CLK_T::APBCLK1: PWM1CKEN Mask */ + +#define CLK_APBCLK1_BPWM0CKEN_Pos (18) /*!< CLK_T::APBCLK1: BPWM0CKEN Position */ +#define CLK_APBCLK1_BPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM0CKEN_Pos) /*!< CLK_T::APBCLK1: BPWM0CKEN Mask */ + +#define CLK_APBCLK1_BPWM1CKEN_Pos (19) /*!< CLK_T::APBCLK1: BPWM1CKEN Position */ +#define CLK_APBCLK1_BPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM1CKEN_Pos) /*!< CLK_T::APBCLK1: BPWM1CKEN Mask */ + +#define CLK_APBCLK1_OPACKEN_Pos (30) /*!< CLK_T::APBCLK1: OPACKEN Position */ +#define CLK_APBCLK1_OPACKEN_Msk (0x1ul << CLK_APBCLK1_OPACKEN_Pos) /*!< CLK_T::APBCLK1: OPACKEN Mask */ + +#define CLK_APBCLK1_PSIOCKEN_Pos (31) /*!< CLK_T::APBCLK1: PSIOCKEN Position */ +#define CLK_APBCLK1_PSIOCKEN_Msk (0x1ul << CLK_APBCLK1_PSIOCKEN_Pos) /*!< CLK_T::APBCLK1: PSIOCKEN Mask */ + +#define CLK_CLKSEL0_HCLKSEL_Pos (0) /*!< CLK_T::CLKSEL0: HCLKSEL Position */ +#define CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos) /*!< CLK_T::CLKSEL0: HCLKSEL Mask */ + +#define CLK_CLKSEL0_STCLKSEL_Pos (3) /*!< CLK_T::CLKSEL0: STCLKSEL Position */ +#define CLK_CLKSEL0_STCLKSEL_Msk (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos) /*!< CLK_T::CLKSEL0: STCLKSEL Mask */ + +#define CLK_CLKSEL0_USBDSEL_Pos (8) /*!< CLK_T::CLKSEL0: USBDSEL Position */ +#define CLK_CLKSEL0_USBDSEL_Msk (0x1ul << CLK_CLKSEL0_USBDSEL_Pos) /*!< CLK_T::CLKSEL0: USBDSEL Mask */ + +#define CLK_CLKSEL1_WDTSEL_Pos (0) /*!< CLK_T::CLKSEL1: WDTSEL Position */ +#define CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos) /*!< CLK_T::CLKSEL1: WDTSEL Mask */ + +#define CLK_CLKSEL1_WWDTSEL_Pos (2) /*!< CLK_T::CLKSEL1: WWDTSEL Position */ +#define CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos) /*!< CLK_T::CLKSEL1: WWDTSEL Mask */ + +#define CLK_CLKSEL1_CLKOSEL_Pos (4) /*!< CLK_T::CLKSEL1: CLKOSEL Position */ +#define CLK_CLKSEL1_CLKOSEL_Msk (0x7ul << CLK_CLKSEL1_CLKOSEL_Pos) /*!< CLK_T::CLKSEL1: CLKOSEL Mask */ + +#define CLK_CLKSEL1_TMR0SEL_Pos (8) /*!< CLK_T::CLKSEL1: TMR0SEL Position */ +#define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) /*!< CLK_T::CLKSEL1: TMR0SEL Mask */ + +#define CLK_CLKSEL1_TMR1SEL_Pos (12) /*!< CLK_T::CLKSEL1: TMR1SEL Position */ +#define CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos) /*!< CLK_T::CLKSEL1: TMR1SEL Mask */ + +#define CLK_CLKSEL1_TMR2SEL_Pos (16) /*!< CLK_T::CLKSEL1: TMR2SEL Position */ +#define CLK_CLKSEL1_TMR2SEL_Msk (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos) /*!< CLK_T::CLKSEL1: TMR2SEL Mask */ + +#define CLK_CLKSEL1_TMR3SEL_Pos (20) /*!< CLK_T::CLKSEL1: TMR3SEL Position */ +#define CLK_CLKSEL1_TMR3SEL_Msk (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos) /*!< CLK_T::CLKSEL1: TMR3SEL Mask */ + +#define CLK_CLKSEL1_UART0SEL_Pos (24) /*!< CLK_T::CLKSEL1: UART0SEL Position */ +#define CLK_CLKSEL1_UART0SEL_Msk (0x7ul << CLK_CLKSEL1_UART0SEL_Pos) /*!< CLK_T::CLKSEL1: UART0SEL Mask */ + +#define CLK_CLKSEL1_UART1SEL_Pos (28) /*!< CLK_T::CLKSEL1: UART1SEL Position */ +#define CLK_CLKSEL1_UART1SEL_Msk (0x7ul << CLK_CLKSEL1_UART1SEL_Pos) /*!< CLK_T::CLKSEL1: UART1SEL Mask */ + +#define CLK_CLKSEL2_PWM0SEL_Pos (0) /*!< CLK_T::CLKSEL2: PWM0SEL Position */ +#define CLK_CLKSEL2_PWM0SEL_Msk (0x1ul << CLK_CLKSEL2_PWM0SEL_Pos) /*!< CLK_T::CLKSEL2: PWM0SEL Mask */ + +#define CLK_CLKSEL2_PWM1SEL_Pos (1) /*!< CLK_T::CLKSEL2: PWM1SEL Position */ +#define CLK_CLKSEL2_PWM1SEL_Msk (0x1ul << CLK_CLKSEL2_PWM1SEL_Pos) /*!< CLK_T::CLKSEL2: PWM1SEL Mask */ + +#define CLK_CLKSEL2_QSPI0SEL_Pos (2) /*!< CLK_T::CLKSEL2: QSPI0SEL Position */ +#define CLK_CLKSEL2_QSPI0SEL_Msk (0x3ul << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< CLK_T::CLKSEL2: QSPI0SEL Mask */ + +#define CLK_CLKSEL2_SPI0SEL_Pos (4) /*!< CLK_T::CLKSEL2: SPI0SEL Position */ +#define CLK_CLKSEL2_SPI0SEL_Msk (0x3ul << CLK_CLKSEL2_SPI0SEL_Pos) /*!< CLK_T::CLKSEL2: SPI0SEL Mask */ + +#define CLK_CLKSEL2_BPWM0SEL_Pos (8) /*!< CLK_T::CLKSEL2: BPWM0SEL Position */ +#define CLK_CLKSEL2_BPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM0SEL_Pos) /*!< CLK_T::CLKSEL2: BPWM0SEL Mask */ + +#define CLK_CLKSEL2_BPWM1SEL_Pos (9) /*!< CLK_T::CLKSEL2: BPWM1SEL Position */ +#define CLK_CLKSEL2_BPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM1SEL_Pos) /*!< CLK_T::CLKSEL2: BPWM1SEL Mask */ + +#define CLK_CLKSEL2_PSIOSEL_Pos (28) /*!< CLK_T::CLKSEL2: PSIOSEL Position */ +#define CLK_CLKSEL2_PSIOSEL_Msk (0x7ul << CLK_CLKSEL2_PSIOSEL_Pos) /*!< CLK_T::CLKSEL2: PSIOSEL Mask */ + +#define CLK_CLKSEL3_SC0SEL_Pos (0) /*!< CLK_T::CLKSEL3: SC0SEL Position */ +#define CLK_CLKSEL3_SC0SEL_Msk (0x3ul << CLK_CLKSEL3_SC0SEL_Pos) /*!< CLK_T::CLKSEL3: SC0SEL Mask */ + +#define CLK_CLKSEL3_UART2SEL_Pos (24) /*!< CLK_T::CLKSEL3: UART2SEL Position */ +#define CLK_CLKSEL3_UART2SEL_Msk (0x7ul << CLK_CLKSEL3_UART2SEL_Pos) /*!< CLK_T::CLKSEL3: UART2SEL Mask */ + +#define CLK_CLKDIV0_HCLKDIV_Pos (0) /*!< CLK_T::CLKDIV0: HCLKDIV Position */ +#define CLK_CLKDIV0_HCLKDIV_Msk (0xful << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLK_T::CLKDIV0: HCLKDIV Mask */ + +#define CLK_CLKDIV0_USBDIV_Pos (4) /*!< CLK_T::CLKDIV0: USBDIV Position */ +#define CLK_CLKDIV0_USBDIV_Msk (0xful << CLK_CLKDIV0_USBDIV_Pos) /*!< CLK_T::CLKDIV0: USBDIV Mask */ + +#define CLK_CLKDIV0_UART0DIV_Pos (8) /*!< CLK_T::CLKDIV0: UART0DIV Position */ +#define CLK_CLKDIV0_UART0DIV_Msk (0xful << CLK_CLKDIV0_UART0DIV_Pos) /*!< CLK_T::CLKDIV0: UART0DIV Mask */ + +#define CLK_CLKDIV0_UART1DIV_Pos (12) /*!< CLK_T::CLKDIV0: UART1DIV Position */ +#define CLK_CLKDIV0_UART1DIV_Msk (0xful << CLK_CLKDIV0_UART1DIV_Pos) /*!< CLK_T::CLKDIV0: UART1DIV Mask */ + +#define CLK_CLKDIV0_EADCDIV_Pos (16) /*!< CLK_T::CLKDIV0: EADCDIV Position */ +#define CLK_CLKDIV0_EADCDIV_Msk (0xfful << CLK_CLKDIV0_EADCDIV_Pos) /*!< CLK_T::CLKDIV0: EADCDIV Mask */ + +#define CLK_CLKDIV1_SC0DIV_Pos (0) /*!< CLK_T::CLKDIV1: SC0DIV Position */ +#define CLK_CLKDIV1_SC0DIV_Msk (0xfful << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLK_T::CLKDIV1: SC0DIV Mask */ + +#define CLK_CLKDIV1_PSIODIV_Pos (24) /*!< CLK_T::CLKDIV1: PSIODIV Position */ +#define CLK_CLKDIV1_PSIODIV_Msk (0xfful << CLK_CLKDIV1_PSIODIV_Pos) /*!< CLK_T::CLKDIV1: PSIODIV Mask */ + +#define CLK_CLKDIV4_UART2DIV_Pos (0) /*!< CLK_T::CLKDIV4: UART2DIV Position */ +#define CLK_CLKDIV4_UART2DIV_Msk (0xful << CLK_CLKDIV4_UART2DIV_Pos) /*!< CLK_T::CLKDIV4: UART2DIV Mask */ + +#define CLK_PCLKDIV_APB0DIV_Pos (0) /*!< CLK_T::PCLKDIV: APB0DIV Position */ +#define CLK_PCLKDIV_APB0DIV_Msk (0x7ul << CLK_PCLKDIV_APB0DIV_Pos) /*!< CLK_T::PCLKDIV: APB0DIV Mask */ + +#define CLK_PCLKDIV_APB1DIV_Pos (4) /*!< CLK_T::PCLKDIV: APB1DIV Position */ +#define CLK_PCLKDIV_APB1DIV_Msk (0x7ul << CLK_PCLKDIV_APB1DIV_Pos) /*!< CLK_T::PCLKDIV: APB1DIV Mask */ + +#define CLK_PLLCTL_FBDIV_Pos (0) /*!< CLK_T::PLLCTL: FBDIV Position */ +#define CLK_PLLCTL_FBDIV_Msk (0x3ful << CLK_PLLCTL_FBDIV_Pos) /*!< CLK_T::PLLCTL: FBDIV Mask */ + +#define CLK_PLLCTL_INDIV_Pos (9) /*!< CLK_T::PLLCTL: INDIV Position */ +#define CLK_PLLCTL_INDIV_Msk (0xful << CLK_PLLCTL_INDIV_Pos) /*!< CLK_T::PLLCTL: INDIV Mask */ + +#define CLK_PLLCTL_OUTDIV_Pos (14) /*!< CLK_T::PLLCTL: OUTDIV Position */ +#define CLK_PLLCTL_OUTDIV_Msk (0x3ul << CLK_PLLCTL_OUTDIV_Pos) /*!< CLK_T::PLLCTL: OUTDIV Mask */ + +#define CLK_PLLCTL_PD_Pos (16) /*!< CLK_T::PLLCTL: PD Position */ +#define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos) /*!< CLK_T::PLLCTL: PD Mask */ + +#define CLK_PLLCTL_BP_Pos (17) /*!< CLK_T::PLLCTL: BP Position */ +#define CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos) /*!< CLK_T::PLLCTL: BP Mask */ + +#define CLK_PLLCTL_OE_Pos (18) /*!< CLK_T::PLLCTL: OE Position */ +#define CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos) /*!< CLK_T::PLLCTL: OE Mask */ + +#define CLK_PLLCTL_PLLSRC_Pos (19) /*!< CLK_T::PLLCTL: PLLSRC Position */ +#define CLK_PLLCTL_PLLSRC_Msk (0x3ul << CLK_PLLCTL_PLLSRC_Pos) /*!< CLK_T::PLLCTL: PLLSRC Mask */ + +#define CLK_PLLCTL_STBSEL_Pos (23) /*!< CLK_T::PLLCTL: STBSEL Position */ +#define CLK_PLLCTL_STBSEL_Msk (0x1ul << CLK_PLLCTL_STBSEL_Pos) /*!< CLK_T::PLLCTL: STBSEL Mask */ + +#define CLK_PLLCTL_PLL_CLF_EN_Pos (24) /*!< CLK_T::PLLCTL: PLL_CLF_EN Position */ +#define CLK_PLLCTL_PLL_CLF_EN_Msk (0x1ul << CLK_PLLCTL_PLL_CLF_EN_Pos) /*!< CLK_T::PLLCTL: PLL_CLF_EN Mask */ + +#define CLK_STATUS_HXTSTB_Pos (0) /*!< CLK_T::STATUS: HXTSTB Position */ +#define CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos) /*!< CLK_T::STATUS: HXTSTB Mask */ + +#define CLK_STATUS_LXTSTB_Pos (1) /*!< CLK_T::STATUS: LXTSTB Position */ +#define CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos) /*!< CLK_T::STATUS: LXTSTB Mask */ + +#define CLK_STATUS_PLLSTB_Pos (2) /*!< CLK_T::STATUS: PLLSTB Position */ +#define CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos) /*!< CLK_T::STATUS: PLLSTB Mask */ + +#define CLK_STATUS_LIRCSTB_Pos (3) /*!< CLK_T::STATUS: LIRCSTB Position */ +#define CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos) /*!< CLK_T::STATUS: LIRCSTB Mask */ + +#define CLK_STATUS_HIRCSTB_Pos (4) /*!< CLK_T::STATUS: HIRCSTB Position */ +#define CLK_STATUS_HIRCSTB_Msk (0x1ul << CLK_STATUS_HIRCSTB_Pos) /*!< CLK_T::STATUS: HIRCSTB Mask */ + +#define CLK_STATUS_MIRCSTB_Pos (6) /*!< CLK_T::STATUS: MIRCSTB Position */ +#define CLK_STATUS_MIRCSTB_Msk (0x1ul << CLK_STATUS_MIRCSTB_Pos) /*!< CLK_T::STATUS: MIRCSTB Mask */ + +#define CLK_STATUS_CLKSFAIL_Pos (7) /*!< CLK_T::STATUS: CLKSFAIL Position */ +#define CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos) /*!< CLK_T::STATUS: CLKSFAIL Mask */ + +#define CLK_CLKOCTL_FREQSEL_Pos (0) /*!< CLK_T::CLKOCTL: FREQSEL Position */ +#define CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos) /*!< CLK_T::CLKOCTL: FREQSEL Mask */ + +#define CLK_CLKOCTL_CLKOEN_Pos (4) /*!< CLK_T::CLKOCTL: CLKOEN Position */ +#define CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos) /*!< CLK_T::CLKOCTL: CLKOEN Mask */ + +#define CLK_CLKOCTL_DIV1EN_Pos (5) /*!< CLK_T::CLKOCTL: DIV1EN Position */ +#define CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos) /*!< CLK_T::CLKOCTL: DIV1EN Mask */ + +#define CLK_CLKOCTL_CLK1HZEN_Pos (6) /*!< CLK_T::CLKOCTL: CLK1HZEN Position */ +#define CLK_CLKOCTL_CLK1HZEN_Msk (0x1ul << CLK_CLKOCTL_CLK1HZEN_Pos) /*!< CLK_T::CLKOCTL: CLK1HZEN Mask */ + +#define CLK_CLKDCTL_HXTFDEN_Pos (4) /*!< CLK_T::CLKDCTL: HXTFDEN Position */ +#define CLK_CLKDCTL_HXTFDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFDEN Mask */ + +#define CLK_CLKDCTL_HXTFIEN_Pos (5) /*!< CLK_T::CLKDCTL: HXTFIEN Position */ +#define CLK_CLKDCTL_HXTFIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFIEN Mask */ + +#define CLK_CLKDCTL_LXTFDEN_Pos (12) /*!< CLK_T::CLKDCTL: LXTFDEN Position */ +#define CLK_CLKDCTL_LXTFDEN_Msk (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos) /*!< CLK_T::CLKDCTL: LXTFDEN Mask */ + +#define CLK_CLKDCTL_LXTFIEN_Pos (13) /*!< CLK_T::CLKDCTL: LXTFIEN Position */ +#define CLK_CLKDCTL_LXTFIEN_Msk (0x1ul << CLK_CLKDCTL_LXTFIEN_Pos) /*!< CLK_T::CLKDCTL: LXTFIEN Mask */ + +#define CLK_CLKDCTL_HXTFQDEN_Pos (16) /*!< CLK_T::CLKDCTL: HXTFQDEN Position */ +#define CLK_CLKDCTL_HXTFQDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQDEN Mask */ + +#define CLK_CLKDCTL_HXTFQIEN_Pos (17) /*!< CLK_T::CLKDCTL: HXTFQIEN Position */ +#define CLK_CLKDCTL_HXTFQIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQIEN Mask */ + +#define CLK_CLKDSTS_HXTFIF_Pos (0) /*!< CLK_T::CLKDSTS: HXTFIF Position */ +#define CLK_CLKDSTS_HXTFIF_Msk (0x1ul << CLK_CLKDSTS_HXTFIF_Pos) /*!< CLK_T::CLKDSTS: HXTFIF Mask */ + +#define CLK_CLKDSTS_LXTFIF_Pos (1) /*!< CLK_T::CLKDSTS: LXTFIF Position */ +#define CLK_CLKDSTS_LXTFIF_Msk (0x1ul << CLK_CLKDSTS_LXTFIF_Pos) /*!< CLK_T::CLKDSTS: LXTFIF Mask */ + +#define CLK_CLKDSTS_HXTFQIF_Pos (8) /*!< CLK_T::CLKDSTS: HXTFQIF Position */ +#define CLK_CLKDSTS_HXTFQIF_Msk (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos) /*!< CLK_T::CLKDSTS: HXTFQIF Mask */ + +#define CLK_CDUPB_UPERBD_Pos (0) /*!< CLK_T::CDUPB: UPERBD Position */ +#define CLK_CDUPB_UPERBD_Msk (0x3fful << CLK_CDUPB_UPERBD_Pos) /*!< CLK_T::CDUPB: UPERBD Mask */ + +#define CLK_CDLOWB_LOWERBD_Pos (0) /*!< CLK_T::CDLOWB: LOWERBD Position */ +#define CLK_CDLOWB_LOWERBD_Msk (0x3fful << CLK_CDLOWB_LOWERBD_Pos) /*!< CLK_T::CDLOWB: LOWERBD Mask */ + +#define CLK_PMUCTL_PDMSEL_Pos (0) /*!< CLK_T::PMUCTL: PDMSEL Position */ +#define CLK_PMUCTL_PDMSEL_Msk (0x7ul << CLK_PMUCTL_PDMSEL_Pos) /*!< CLK_T::PMUCTL: PDMSEL Mask */ + +#define CLK_PMUCTL_WKTMREN_Pos (8) /*!< CLK_T::PMUCTL: WKTMREN Position */ +#define CLK_PMUCTL_WKTMREN_Msk (0x1ul << CLK_PMUCTL_WKTMREN_Pos) /*!< CLK_T::PMUCTL: WKTMREN Mask */ + +#define CLK_PMUCTL_WKTMRIS_Pos (9) /*!< CLK_T::PMUCTL: WKTMRIS Position */ +#define CLK_PMUCTL_WKTMRIS_Msk (0x7ul << CLK_PMUCTL_WKTMRIS_Pos) /*!< CLK_T::PMUCTL: WKTMRIS Mask */ + +#define CLK_PMUCTL_WKPINEN0_Pos (16) /*!< CLK_T::PMUCTL: WKPINEN0 Position */ +#define CLK_PMUCTL_WKPINEN0_Msk (0x3ul << CLK_PMUCTL_WKPINEN0_Pos) /*!< CLK_T::PMUCTL: WKPINEN0 Mask */ + +#define CLK_PMUCTL_WKPINDBEN_Pos (22) /*!< CLK_T::PMUCTL: WKPINDBEN Position */ +#define CLK_PMUCTL_WKPINDBEN_Msk (0x1ul << CLK_PMUCTL_WKPINDBEN_Pos) /*!< CLK_T::PMUCTL: WKPINDBEN Mask */ + +#define CLK_PMUCTL_RTCWKEN_Pos (23) /*!< CLK_T::PMUCTL: RTCWKEN Position */ +#define CLK_PMUCTL_RTCWKEN_Msk (0x1ul << CLK_PMUCTL_RTCWKEN_Pos) /*!< CLK_T::PMUCTL: RTCWKEN Mask */ + +#define CLK_PMUCTL_WKPINEN1_Pos (24) /*!< CLK_T::PMUCTL: WKPINEN1 Position */ +#define CLK_PMUCTL_WKPINEN1_Msk (0x3ul << CLK_PMUCTL_WKPINEN1_Pos) /*!< CLK_T::PMUCTL: WKPINEN1 Mask */ + +#define CLK_PMUCTL_WKPINEN2_Pos (26) /*!< CLK_T::PMUCTL: WKPINEN2 Position */ +#define CLK_PMUCTL_WKPINEN2_Msk (0x3ul << CLK_PMUCTL_WKPINEN2_Pos) /*!< CLK_T::PMUCTL: WKPINEN2 Mask */ + +#define CLK_PMUCTL_WKPINEN3_Pos (28) /*!< CLK_T::PMUCTL: WKPINEN3 Position */ +#define CLK_PMUCTL_WKPINEN3_Msk (0x3ul << CLK_PMUCTL_WKPINEN3_Pos) /*!< CLK_T::PMUCTL: WKPINEN3 Mask */ + +#define CLK_PMUCTL_WKPINEN4_Pos (30) /*!< CLK_T::PMUCTL: WKPINEN4 Position */ +#define CLK_PMUCTL_WKPINEN4_Msk (0x3ul << CLK_PMUCTL_WKPINEN4_Pos) /*!< CLK_T::PMUCTL: WKPINEN4 Mask */ + +#define CLK_PMUSTS_PINWK0_Pos (0) /*!< CLK_T::PMUSTS: PINWK0 Position */ +#define CLK_PMUSTS_PINWK0_Msk (0x1ul << CLK_PMUSTS_PINWK0_Pos) /*!< CLK_T::PMUSTS: PINWK0 Mask */ + +#define CLK_PMUSTS_TMRWK_Pos (1) /*!< CLK_T::PMUSTS: TMRWK Position */ +#define CLK_PMUSTS_TMRWK_Msk (0x1ul << CLK_PMUSTS_TMRWK_Pos) /*!< CLK_T::PMUSTS: TMRWK Mask */ + +#define CLK_PMUSTS_RTCWK_Pos (2) /*!< CLK_T::PMUSTS: RTCWK Position */ +#define CLK_PMUSTS_RTCWK_Msk (0x1ul << CLK_PMUSTS_RTCWK_Pos) /*!< CLK_T::PMUSTS: RTCWK Mask */ + +#define CLK_PMUSTS_PINWK1_Pos (3) /*!< CLK_T::PMUSTS: PINWK1 Position */ +#define CLK_PMUSTS_PINWK1_Msk (0x1ul << CLK_PMUSTS_PINWK1_Pos) /*!< CLK_T::PMUSTS: PINWK1 Mask */ + +#define CLK_PMUSTS_PINWK2_Pos (4) /*!< CLK_T::PMUSTS: PINWK2 Position */ +#define CLK_PMUSTS_PINWK2_Msk (0x1ul << CLK_PMUSTS_PINWK2_Pos) /*!< CLK_T::PMUSTS: PINWK2 Mask */ + +#define CLK_PMUSTS_PINWK3_Pos (5) /*!< CLK_T::PMUSTS: PINWK3 Position */ +#define CLK_PMUSTS_PINWK3_Msk (0x1ul << CLK_PMUSTS_PINWK3_Pos) /*!< CLK_T::PMUSTS: PINWK3 Mask */ + +#define CLK_PMUSTS_PINWK4_Pos (6) /*!< CLK_T::PMUSTS: PINWK4 Position */ +#define CLK_PMUSTS_PINWK4_Msk (0x1ul << CLK_PMUSTS_PINWK4_Pos) /*!< CLK_T::PMUSTS: PINWK4 Mask */ + +#define CLK_PMUSTS_LVRWK_Pos (12) /*!< CLK_T::PMUSTS: LVRWK Position */ +#define CLK_PMUSTS_LVRWK_Msk (0x1ul << CLK_PMUSTS_LVRWK_Pos) /*!< CLK_T::PMUSTS: LVRWK Mask */ + +#define CLK_PMUSTS_CLRWK_Pos (31) /*!< CLK_T::PMUSTS: CLRWK Position */ +#define CLK_PMUSTS_CLRWK_Msk (0x1ul << CLK_PMUSTS_CLRWK_Pos) /*!< CLK_T::PMUSTS: CLRWK Mask */ + +#define CLK_HXTFSEL_HXTFSEL_Pos (0) /*!< CLK_T::HXTFSEL: HXTFSEL Position */ +#define CLK_HXTFSEL_HXTFSEL_Msk (0x1ul << CLK_HXTFSEL_HXTFSEL_Pos) /*!< CLK_T::HXTFSEL: HXTFSEL Mask */ + +/**@}*/ /* CLK_CONST */ +/**@}*/ /* end of CLK register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __CLK_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/crc_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/crc_reg.h new file mode 100644 index 00000000000..3b6ab0a9c5f --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/crc_reg.h @@ -0,0 +1,148 @@ +/**************************************************************************//** + * @file crc_reg.h + * @version V1.00 + * @brief CRC register definition header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __CRC_REG_H__ +#define __CRC_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup CRC Cyclic Redundancy Check Controller (CRC) + Memory Mapped Structure for CRC Controller +@{ */ + +typedef struct +{ + + + /** + * @var CRC_T::CTL + * Offset: 0x00 CRC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CRCEN |CRC Channel Enable Bit + * | | |0 = No effect. + * | | |1 = CRC operation Enabled. + * |[1] |CHKSINIT |Checksum Initialization + * | | |0 = No effect. + * | | |1 = Initial checksum value by auto reload CRC_SEED register value to CRC_CHECKSUM register value. + * | | |Note: This bit will be cleared automatically. + * |[24] |DATREV |Write Data Bit Order Reverse + * | | |This bit is used to enable the bit order reverse function per byte for write data value in CRC_DAT register. + * | | |0 = Bit order reversed for CRC write data in Disabled. + * | | |1 = Bit order reversed for CRC write data in Enabled (per byte). + * | | |Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB. + * |[25] |CHKSREV |Checksum Bit Order Reverse + * | | |This bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register. + * | | |0 = Bit order reverse for CRC checksum Disabled. + * | | |1 = Bit order reverse for CRC checksum Enabled. + * | | |Note: If the checksum result is 0xDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB. + * |[26] |DATFMT |Write Data 1's Complement + * | | |This bit is used to enable the 1's complement function for write data value in CRC_DAT register. + * | | |0 = 1's complement for CRC writes data in Disabled. + * | | |1 = 1's complement for CRC writes data in Enabled. + * |[27] |CHKSFMT |Checksum 1's Complement + * | | |This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register. + * | | |0 = 1's complement for CRC checksum Disabled. + * | | |1 = 1's complement for CRC checksum Enabled. + * |[29:28] |DATLEN |CPU Write Data Length + * | | |This field indicates the write data length. + * | | |00 = Data length is 8-bit mode. + * | | |01 = Data length is 16-bit mode. + * | | |1x = Data length is 32-bit mode. + * | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0] + * |[31:30] |CRCMODE |CRC Polynomial Mode + * | | |This field indicates the CRC operation polynomial mode. + * | | |00 = CRC-CCITT Polynomial mode. + * | | |01 = CRC-8 Polynomial mode. + * | | |10 = CRC-16 Polynomial mode. + * | | |11 = CRC-32 Polynomial mode. + * @var CRC_T::DAT + * Offset: 0x04 CRC Write Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |CRC Write Data Bits + * | | |User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation. + * | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]. + * @var CRC_T::SEED + * Offset: 0x08 CRC Seed Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEED |CRC Seed Value + * | | |This field indicates the CRC seed value. + * | | |Note: This field will be reloaded as checksum initial value (CRC_CHECKSUM register) after perform CHKSINIT (CRC_CTL[1]). + * @var CRC_T::CHECKSUM + * Offset: 0x0C CRC Checksum Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CHECKSUM |CRC Checksum Results + * | | |This field indicates the CRC checksum result. + */ + __IO uint32_t CTL; /*!< [0x0000] CRC Control Register */ + __IO uint32_t DAT; /*!< [0x0004] CRC Write Data Register */ + __IO uint32_t SEED; /*!< [0x0008] CRC Seed Register */ + __I uint32_t CHECKSUM; /*!< [0x000c] CRC Checksum Register */ +} CRC_T; + +/** + @addtogroup CRC_CONST CRC Bit Field Definition + Constant Definitions for CRC Controller +@{ */ + +#define CRC_CTL_CRCEN_Pos (0) /*!< CRC_T::CTL: CRCEN Position */ +#define CRC_CTL_CRCEN_Msk (0x1ul << CRC_CTL_CRCEN_Pos) /*!< CRC_T::CTL: CRCEN Mask */ + +#define CRC_CTL_CHKSINIT_Pos (1) /*!< CRC_T::CTL: CHKSINIT Position */ +#define CRC_CTL_CHKSINIT_Msk (0x1ul << CRC_CTL_CHKSINIT_Pos) /*!< CRC_T::CTL: CHKSINIT Mask */ + +#define CRC_CTL_DATREV_Pos (24) /*!< CRC_T::CTL: DATREV Position */ +#define CRC_CTL_DATREV_Msk (0x1ul << CRC_CTL_DATREV_Pos) /*!< CRC_T::CTL: DATREV Mask */ + +#define CRC_CTL_CHKSREV_Pos (25) /*!< CRC_T::CTL: CHKSREV Position */ +#define CRC_CTL_CHKSREV_Msk (0x1ul << CRC_CTL_CHKSREV_Pos) /*!< CRC_T::CTL: CHKSREV Mask */ + +#define CRC_CTL_DATFMT_Pos (26) /*!< CRC_T::CTL: DATFMT Position */ +#define CRC_CTL_DATFMT_Msk (0x1ul << CRC_CTL_DATFMT_Pos) /*!< CRC_T::CTL: DATFMT Mask */ + +#define CRC_CTL_CHKSFMT_Pos (27) /*!< CRC_T::CTL: CHKSFMT Position */ +#define CRC_CTL_CHKSFMT_Msk (0x1ul << CRC_CTL_CHKSFMT_Pos) /*!< CRC_T::CTL: CHKSFMT Mask */ + +#define CRC_CTL_DATLEN_Pos (28) /*!< CRC_T::CTL: DATLEN Position */ +#define CRC_CTL_DATLEN_Msk (0x3ul << CRC_CTL_DATLEN_Pos) /*!< CRC_T::CTL: DATLEN Mask */ + +#define CRC_CTL_CRCMODE_Pos (30) /*!< CRC_T::CTL: CRCMODE Position */ +#define CRC_CTL_CRCMODE_Msk (0x3ul << CRC_CTL_CRCMODE_Pos) /*!< CRC_T::CTL: CRCMODE Mask */ + +#define CRC_DAT_DATA_Pos (0) /*!< CRC_T::DAT: DATA Position */ +#define CRC_DAT_DATA_Msk (0xfffffffful << CRC_DAT_DATA_Pos) /*!< CRC_T::DAT: DATA Mask */ + +#define CRC_SEED_SEED_Pos (0) /*!< CRC_T::SEED: SEED Position */ +#define CRC_SEED_SEED_Msk (0xfffffffful << CRC_SEED_SEED_Pos) /*!< CRC_T::SEED: SEED Mask */ + +#define CRC_CHECKSUM_CHECKSUM_Pos (0) /*!< CRC_T::CHECKSUM: CHECKSUM Position */ +#define CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos) /*!< CRC_T::CHECKSUM: CHECKSUM Mask */ + +/**@}*/ /* CRC_CONST */ +/**@}*/ /* end of CRC register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __CRC_REG_H__ */ \ No newline at end of file diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/crypto_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/crypto_reg.h new file mode 100644 index 00000000000..cb934ec4a76 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/crypto_reg.h @@ -0,0 +1,450 @@ +/**************************************************************************//** + * @file crypto_reg.h + * @version V1.00 + * @brief CRYPTO register definition header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __CRYPTO_REG_H__ +#define __CRYPTO_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup CRPT Cryptographic Accelerator (CRPT) + Memory Mapped Structure for Cryptographic Accelerator +@{ */ + +typedef struct +{ + + + /** + * @var CRPT_T::INTEN + * Offset: 0x00 Crypto Interrupt Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |AESIEN |AES Interrupt Enable Bit + * | | |0 = AES interrupt Disabled. + * | | |1 = AES interrupt Enabled. + * | | |In DMA mode, an interrupt will be triggered when amount of data set in AES_DMA_CNT is fed into the AES engine. + * | | |In Non-DMA mode, an interrupt will be triggered when the AES engine finishes the operation. + * |[1] |AESEIEN |AES Error Flag Enable Bit + * | | |0 = AES error interrupt flag Disabled. + * | | |1 = AES error interrupt flag Enabled. + * |[16] |PRNGIEN |PRNG Interrupt Enable Bit + * | | |0 = PRNG interrupt Disabled. + * | | |1 = PRNG interrupt Enabled. + * @var CRPT_T::INTSTS + * Offset: 0x04 Crypto Interrupt Flag + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |AESIF |AES Finish Interrupt Flag + * | | |This bit is cleared by writing 1, and it has no effect by writing 0. + * | | |0 = No AES interrupt. + * | | |1 = AES encryption/decryption done interrupt. + * |[1] |AESEIF |AES Error Flag + * | | |This bit is cleared by writing 1, and it has no effect by writing 0. + * | | |0 = No AES error. + * | | |1 = AES encryption/decryption error interrupt. + * |[16] |PRNGIF |PRNG Finish Interrupt Flag + * | | |This bit is cleared by writing 1, and it has no effect by writing 0. + * | | |0 = No PRNG interrupt. + * | | |1 = PRNG key generation done interrupt. + * @var CRPT_T::PRNG_CTL + * Offset: 0x08 PRNG Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |Start PRNG Engine + * | | |0 = Stop PRNG engine. + * | | |1 = Generate new key and store the new key to register CRPT_PRNG_KEYx, which will be cleared when the new key is generated. + * |[1] |SEEDRLD |Reload New Seed for PRNG Engine + * | | |0 = Generating key based on the current seed. + * | | |1 = Reload new seed. + * |[3:2] |KEYSZ |PRNG Generate Key Size + * | | |00 = 64 bits. + * | | |01 = 128 bits. + * | | |10 = 192 bits. + * | | |11 = 256 bits. + * |[8] |BUSY |PRNG Busy (Read Only) + * | | |0 = PRNG engine is idle. + * | | |1 = Indicate that the PRNG engine is generating CRPT_PRNG_KEYx. + * @var CRPT_T::PRNG_SEED + * Offset: 0x0C Seed for PRNG + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEED |Seed for PRNG (Write Only) + * | | |The bits store the seed for PRNG engine. + * @var CRPT_T::PRNG_KEY[8] + * Offset: 0x10 ~ 0x2C PRNG Generated Key0 ~ Key7 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |Store PRNG Generated Key (Read Only) + * | | |The bits store the key that is generated by PRNG. + * @var CRPT_T::AES_FDBCK[4] + * Offset: 0x50 ~ 0x5C AES Engine Output Feedback Data After Cryptographic Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |AES Feedback Information + * | | |The feedback value is 128 bits in size. + * | | |The AES engine uses the data from CRPT_AES_FDBCKx as the data inputted to CRPT_AES_IVx for the next block in DMA cascade mode. + * | | |The AES engine outputs feedback information for IV in the next block's operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_AES_IVx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::AES_CTL + * Offset: 0x100 AES Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |AES Engine Start + * | | |0 = No effect. + * | | |1 = Start AES engine. BUSY flag will be set. + * | | |Note: This bit is always 0 when it's read back. + * |[1] |STOP |AES Engine Stop + * | | |0 = No effect. + * | | |1 = Stop AES engine. + * | | |Note: This bit is always 0 when it's read back. + * |[3:2] |KEYSZ |AES Key Size + * | | |This bit defines three different key size for AES operation. + * | | |2'b00 = 128 bits key. + * | | |2'b01 = 192 bits key. + * | | |2'b10 = 256 bits key. + * | | |2'b11 = Reserved. + * | | |If the AES accelerator is operating and the corresponding flag BUSY is 1, updating this register has no effect. + * |[5] |DMALAST |AES Last Block + * | | |In DMA mode, this bit must be set as beginning the last DMA cascade round. + * | | |In Non-DMA mode, this bit must be set when feeding in the last block of data in ECB, CBC, CTR, OFB, and CFB mode, and feeding in the (last-1) block of data at CBC-CS1, CBC-CS2, and CBC-CS3 mode. + * | | |This bit is always 0 when it's read back. Must be written again once START is triggered. + * |[6] |DMACSCAD |AES Engine DMA with Cascade Mode + * | | |0 = DMA cascade function Disabled. + * | | |1 = In DMA cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation. + * |[7] |DMAEN |AES Engine DMA Enable Bit + * | | |0 = AES DMA engine Disabled. + * | | |The AES engine operates in Non-DMA mode. The data need to be written in CRPT_AES_DATIN. + * | | |1 = AES_DMA engine Enabled. + * | | |The AES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic. + * |[15:8] |OPMODE |AES Engine Operation Modes + * | | |0x00 = ECB (Electronic Codebook Mode) 0x01 = CBC (Cipher Block Chaining Mode). + * | | |0x02 = CFB (Cipher Feedback Mode). + * | | |0x03 = OFB (Output Feedback Mode). + * | | |0x04 = CTR (Counter Mode). + * | | |0x10 = CBC-CS1 (CBC Ciphertext-Stealing 1 Mode). + * | | |0x11 = CBC-CS2 (CBC Ciphertext-Stealing 2 Mode). + * | | |0x12 = CBC-CS3 (CBC Ciphertext-Stealing 3 Mode). + * |[16] |ENCRYPTO |AES Encryption/Decryption + * | | |0 = AES engine executes decryption operation. + * | | |1 = AES engine executes encryption operation. + * |[22] |OUTSWAP |AES Engine Output Data Swap + * | | |0 = Keep the original order. + * | | |1 = The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * |[23] |INSWAP |AES Engine Input Data Swap + * | | |0 = Keep the original order. + * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * |[30:26] |KEYUNPRT |Unprotect Key + * | | |Writing 0 to CRPT_AES_CTL[31] and "10110" to CRPT_AES_CTL[30:26] is to unprotect the AES key. + * | | |The KEYUNPRT can be read and written + * | | |When it is written as the AES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT. + * |[31] |KEYPRT |Protect Key + * | | |Read as a flag to reflect KEYPRT. + * | | |0 = No effect. + * | | |1 = Protect the content of the AES key from reading + * | | |The return value for reading CRPT_AES_KEYx is not the content of the registers CRPT_AES_KEYx + * | | |Once it is set, it can be cleared by asserting KEYUNPRT + * | | |And the key content would be cleared as well. + * @var CRPT_T::AES_STS + * Offset: 0x104 AES Engine Flag + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |AES Engine Busy + * | | |0 = The AES engine is idle or finished. + * | | |1 = The AES engine is under processing. + * |[8] |INBUFEMPTY|AES Input Buffer Empty + * | | |0 = There are some data in input buffer waiting for the AES engine to process. + * | | |1 = AES input buffer is empty + * | | |Software needs to feed data to the AES engine + * | | |Otherwise, the AES engine will be pending to wait for input data. + * |[9] |INBUFFULL |AES Input Buffer Full Flag + * | | |0 = AES input buffer is not full. Software can feed the data into the AES engine. + * | | |1 = AES input buffer is full + * | | |Software cannot feed data to the AES engine + * | | |Otherwise, the flag INBUFERR will be set to 1. + * |[10] |INBUFERR |AES Input Buffer Error Flag + * | | |0 = No error. + * | | |1 = Error happens during feeding data to the AES engine. + * |[12] |CNTERR |CRPT_AES_CNT Setting Error + * | | |0 = No error in CRPT_AES_CNT setting. + * | | |1 = CRPT_AES_CNT is 0 if DMAEN (CRPT_AES_CTL[7]) is enabled. + * |[16] |OUTBUFEMPTY|AES Out Buffer Empty + * | | |0 = AES output buffer is not empty. There are some valid data kept in output buffer. + * | | |1 = AES output buffer is empty + * | | |Software cannot get data from CRPT_AES_DATOUT + * | | |Otherwise, the flag OUTBUFERR will be set to 1 since the output buffer is empty. + * |[17] |OUTBUFFULL|AES Out Buffer Full Flag + * | | |0 = AES output buffer is not full. + * | | |1 = AES output buffer is full, and software needs to get data from CRPT_AES_DATOUT + * | | |Otherwise, the AES engine will be pending since the output buffer is full. + * |[18] |OUTBUFERR |AES Out Buffer Error Flag + * | | |0 = No error. + * | | |1 = Error happens during getting the result from AES engine. + * |[20] |BUSERR |AES DMA Access Bus Error Flag + * | | |0 = No error. + * | | |1 = Bus error will stop DMA operation and AES engine. + * @var CRPT_T::AES_DATIN + * Offset: 0x108 AES Engine Data Input Port Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATIN |AES Engine Input Port + * | | |CPU feeds data to AES engine through this port by checking CRPT_AES_STS. Feed data as INBUFFULL is 0. + * @var CRPT_T::AES_DATOUT + * Offset: 0x10C AES Engine Data Output Port Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATOUT |AES Engine Output Port + * | | |CPU gets results from the AES engine through this port by checking CRPT_AES_STS + * | | |Get data as OUTBUFEMPTY is 0. + * @var CRPT_T::AES_KEY[8] + * Offset: 0x110 ~ 0x12C AES Key Word 0 ~ 7 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |CRPT_AESn_KEYx + * | | |The KEY keeps the security key for AES operation. + * | | |x = 0, 1..7. + * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key + * | | |{CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 128-bit security key for AES operation + * | | |{CRPT_AES_KEY5, CRPT_AES_KEY4, CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 192-bit security key for AES operation + * | | |{CRPT_AES_KEY7, CRPT_AES_KEY6, CRPT_AES_KEY5, CRPT_AES_KEY4, CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 256-bit security key for AES operation. + * @var CRPT_T::AES_IV[4] + * Offset: 0x130 ~ 0x13C AES Initial Vector Word 0 ~ 3 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |AES Initial Vectors + * | | |x = 0, 1..3. + * | | |Four initial vectors (CRPT_AES_IV0, CRPT_AES_IV1, CRPT_AES_IV2, and CRPT_AES_IV3) are for AES operating in CBC, CFB, and OFB mode + * | | |Four registers (CRPT_AES_IV0, CRPT_AES_IV1, CRPT_AES_IV2, and CRPT_AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode. + * @var CRPT_T::AES_SADDR + * Offset: 0x140 AES DMA Source Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |AES DMA Source Address + * | | |The AES accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO + * | | |The SADDR keeps the source address of the data buffer where the source text is stored + * | | |Based on the source address, the AES accelerator can read the plain text (encryption) / cipher text (descryption) from SRAM memory space and do AES operation + * | | |The start of source address should be located at word boundary + * | | |In other words, bit 1 and 0 of SADDR are ignored. + * | | |SADDR can be read and written + * | | |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of SADDR will be updated later on + * | | |Consequently, software can prepare the DMA source address for the next AES operation. + * | | |In DMA mode, software can update the next CRPT_AES_SADDR before triggering START. + * | | |The value of CRPT_AES_SADDR and CRPT_AES_DADDR can be the same. + * @var CRPT_T::AES_DADDR + * Offset: 0x144 AES DMA Destination Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DADDR |AES DMA Destination Address + * | | |The AES accelerator supports DMA function to transfer the cipher text between SRAM memory space and embedded FIFO + * | | |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored + * | | |Based on the destination address, the AES accelerator can write the cipher text (encryption) / plain text (decryption) back to SRAM memory space after the AES operation is finished + * | | |The start of destination address should be located at word boundary + * | | |In other words, bit 1 and 0 of DADDR are ignored. + * | | |DADDR can be read and written + * | | |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of DADDR will be updated later on + * | | |Consequently, software can prepare the destination address for the next AES operation. + * | | |In DMA mode, software can update the next CRPT_AES_DADDR before triggering START. + * | | |The value of CRPT_AES_SADDR and CRPT_AES_DADDR can be the same. + * @var CRPT_T::AES_CNT + * Offset: 0x148 AES Byte Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |AES Byte Count + * | | |The CRPT_AES_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode + * | | |The CRPT_AES_CNT is 32-bit and the maximum of byte count is 4G bytes. + * | | |CRPT_AESn_CNT can be read and written + * | | |Writing to CRPT_AES_CNT while the AES accelerator is operating doesn't affect the current AES operation + * | | |But the value of CRPT_AESn_CNT will be updated later on + * | | |Consequently, software can prepare the byte count of data for the next AES operation. + * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be more than 16 bytes + * | | |Operations that are qual or less than one block will output unexpected result. + * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AES_CNT must be set as byte count for the last block of data before feeding in the last block of data + * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AES_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data. + */ + __IO uint32_t INTEN; /*!< [0x0000] Crypto Interrupt Enable Control Register */ + __IO uint32_t INTSTS; /*!< [0x0004] Crypto Interrupt Flag */ + __IO uint32_t PRNG_CTL; /*!< [0x0008] PRNG Control Register */ + __O uint32_t PRNG_SEED; /*!< [0x000c] Seed for PRNG */ + __I uint32_t PRNG_KEY[8]; /*!< [0x0010 ~ 0x002c] PRNG Generated Key0 ~ 7 */ + __I uint32_t RESERVE0[8]; + __I uint32_t AES_FDBCK[4]; /*!< [0x0050 ~ 0x005c] AES Engine Output Feedback Data After Cryptographic Operation*/ + __I uint32_t RESERVE1[40]; + __IO uint32_t AES_CTL; /*!< [0x0100] AES Control Register */ + __I uint32_t AES_STS; /*!< [0x0104] AES Engine Flag */ + __IO uint32_t AES_DATIN; /*!< [0x0108] AES Engine Data Input Port Register */ + __I uint32_t AES_DATOUT; /*!< [0x010c] AES Engine Data Output Port Register */ + __IO uint32_t AES_KEY[8]; /*!< [0x0110 ~ 0x012c] AES Key Word 0 ~ 7 Register */ + __IO uint32_t AES_IV[4]; /*!< [0x0130 ~ 0x013c] AES Initial Vector Word 0 ~3 Register */ + __IO uint32_t AES_SADDR; /*!< [0x0140] AES DMA Source Address Register */ + __IO uint32_t AES_DADDR; /*!< [0x0144] AES DMA Destination Address Register */ + __IO uint32_t AES_CNT; /*!< [0x0148] AES Byte Count Register */ + +} CRPT_T; + +/** + @addtogroup CRPT_CONST CRYPTO Bit Field Definition + Constant Definitions for CRYPTO Controller +@{ */ + +#define CRPT_INTEN_AESIEN_Pos (0) /*!< CRPT_T::INTEN: AESIEN Position */ +#define CRPT_INTEN_AESIEN_Msk (0x1ul << CRPT_INTEN_AESIEN_Pos) /*!< CRPT_T::INTEN: AESIEN Mask */ + +#define CRPT_INTEN_AESEIEN_Pos (1) /*!< CRPT_T::INTEN: AESEIEN Position */ +#define CRPT_INTEN_AESEIEN_Msk (0x1ul << CRPT_INTEN_AESEIEN_Pos) /*!< CRPT_T::INTEN: AESEIEN Mask */ + +#define CRPT_INTEN_PRNGIEN_Pos (16) /*!< CRPT_T::INTEN: PRNGIEN Position */ +#define CRPT_INTEN_PRNGIEN_Msk (0x1ul << CRPT_INTEN_PRNGIEN_Pos) /*!< CRPT_T::INTEN: PRNGIEN Mask */ + +#define CRPT_INTSTS_AESIF_Pos (0) /*!< CRPT_T::INTSTS: AESIF Position */ +#define CRPT_INTSTS_AESIF_Msk (0x1ul << CRPT_INTSTS_AESIF_Pos) /*!< CRPT_T::INTSTS: AESIF Mask */ + +#define CRPT_INTSTS_AESEIF_Pos (1) /*!< CRPT_T::INTSTS: AESEIF Position */ +#define CRPT_INTSTS_AESEIF_Msk (0x1ul << CRPT_INTSTS_AESEIF_Pos) /*!< CRPT_T::INTSTS: AESEIF Mask */ + +#define CRPT_INTSTS_PRNGIF_Pos (16) /*!< CRPT_T::INTSTS: PRNGIF Position */ +#define CRPT_INTSTS_PRNGIF_Msk (0x1ul << CRPT_INTSTS_PRNGIF_Pos) /*!< CRPT_T::INTSTS: PRNGIF Mask */ + +#define CRPT_PRNG_CTL_START_Pos (0) /*!< CRPT_T::PRNG_CTL: START Position */ +#define CRPT_PRNG_CTL_START_Msk (0x1ul << CRPT_PRNG_CTL_START_Pos) /*!< CRPT_T::PRNG_CTL: START Mask */ + +#define CRPT_PRNG_CTL_SEEDRLD_Pos (1) /*!< CRPT_T::PRNG_CTL: SEEDRLD Position */ +#define CRPT_PRNG_CTL_SEEDRLD_Msk (0x1ul << CRPT_PRNG_CTL_SEEDRLD_Pos) /*!< CRPT_T::PRNG_CTL: SEEDRLD Mask */ + +#define CRPT_PRNG_CTL_KEYSZ_Pos (2) /*!< CRPT_T::PRNG_CTL: KEYSZ Position */ +#define CRPT_PRNG_CTL_KEYSZ_Msk (0x3ul << CRPT_PRNG_CTL_KEYSZ_Pos) /*!< CRPT_T::PRNG_CTL: KEYSZ Mask */ + +#define CRPT_PRNG_CTL_BUSY_Pos (8) /*!< CRPT_T::PRNG_CTL: BUSY Position */ +#define CRPT_PRNG_CTL_BUSY_Msk (0x1ul << CRPT_PRNG_CTL_BUSY_Pos) /*!< CRPT_T::PRNG_CTL: BUSY Mask */ + +#define CRPT_PRNG_SEED_SEED_Pos (0) /*!< CRPT_T::PRNG_SEED: SEED Position */ +#define CRPT_PRNG_SEED_SEED_Msk (0xfffffffful << CRPT_PRNG_SEED_SEED_Pos) /*!< CRPT_T::PRNG_SEED: SEED Mask */ + +#define CRPT_PRNG_KEYx_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY[8]: KEY Position */ +#define CRPT_PRNG_KEYx_KEY_Msk (0xfffffffful << CRPT_PRNG_KEYx_KEY_Pos) /*!< CRPT_T::PRNG_KEY:[8] KEY Mask */ + +#define CRPT_AES_FDBCKx_FDBCK_Pos (0) /*!< CRPT_T::AES_FDBCK[4]: FDBCK Position */ +#define CRPT_AES_FDBCKx_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCKx_FDBCK_Pos) /*!< CRPT_T::AES_FDBCK[4]: FDBCK Mask */ + +#define CRPT_AES_CTL_START_Pos (0) /*!< CRPT_T::AES_CTL: START Position */ +#define CRPT_AES_CTL_START_Msk (0x1ul << CRPT_AES_CTL_START_Pos) /*!< CRPT_T::AES_CTL: START Mask */ + +#define CRPT_AES_CTL_STOP_Pos (1) /*!< CRPT_T::AES_CTL: STOP Position */ +#define CRPT_AES_CTL_STOP_Msk (0x1ul << CRPT_AES_CTL_STOP_Pos) /*!< CRPT_T::AES_CTL: STOP Mask */ + +#define CRPT_AES_CTL_KEYSZ_Pos (2) /*!< CRPT_T::AES_CTL: KEYSZ Position */ +#define CRPT_AES_CTL_KEYSZ_Msk (0x3ul << CRPT_AES_CTL_KEYSZ_Pos) /*!< CRPT_T::AES_CTL: KEYSZ Mask */ + +#define CRPT_AES_CTL_DMALAST_Pos (5) /*!< CRPT_T::AES_CTL: DMALAST Position */ +#define CRPT_AES_CTL_DMALAST_Msk (0x1ul << CRPT_AES_CTL_DMALAST_Pos) /*!< CRPT_T::AES_CTL: DMALAST Mask */ + +#define CRPT_AES_CTL_DMACSCAD_Pos (6) /*!< CRPT_T::AES_CTL: DMACSCAD Position */ +#define CRPT_AES_CTL_DMACSCAD_Msk (0x1ul << CRPT_AES_CTL_DMACSCAD_Pos) /*!< CRPT_T::AES_CTL: DMACSCAD Mask */ + +#define CRPT_AES_CTL_DMAEN_Pos (7) /*!< CRPT_T::AES_CTL: DMAEN Position */ +#define CRPT_AES_CTL_DMAEN_Msk (0x1ul << CRPT_AES_CTL_DMAEN_Pos) /*!< CRPT_T::AES_CTL: DMAEN Mask */ + +#define CRPT_AES_CTL_OPMODE_Pos (8) /*!< CRPT_T::AES_CTL: OPMODE Position */ +#define CRPT_AES_CTL_OPMODE_Msk (0xfful << CRPT_AES_CTL_OPMODE_Pos) /*!< CRPT_T::AES_CTL: OPMODE Mask */ + +#define CRPT_AES_CTL_ENCRYPTO_Pos (16) /*!< CRPT_T::AES_CTL: ENCRYPTO Position */ +#define CRPT_AES_CTL_ENCRYPTO_Msk (0x1ul << CRPT_AES_CTL_ENCRYPTO_Pos) /*!< CRPT_T::AES_CTL: ENCRYPTO Mask */ + +#define CRPT_AES_CTL_OUTSWAP_Pos (22) /*!< CRPT_T::AES_CTL: OUTSWAP Position */ +#define CRPT_AES_CTL_OUTSWAP_Msk (0x1ul << CRPT_AES_CTL_OUTSWAP_Pos) /*!< CRPT_T::AES_CTL: OUTSWAP Mask */ + +#define CRPT_AES_CTL_INSWAP_Pos (23) /*!< CRPT_T::AES_CTL: INSWAP Position */ +#define CRPT_AES_CTL_INSWAP_Msk (0x1ul << CRPT_AES_CTL_INSWAP_Pos) /*!< CRPT_T::AES_CTL: INSWAP Mask */ + +#define CRPT_AES_CTL_KEYUNPRT_Pos (26) /*!< CRPT_T::AES_CTL: KEYUNPRT Position */ +#define CRPT_AES_CTL_KEYUNPRT_Msk (0x1ful << CRPT_AES_CTL_KEYUNPRT_Pos) /*!< CRPT_T::AES_CTL: KEYUNPRT Mask */ + +#define CRPT_AES_CTL_KEYPRT_Pos (31) /*!< CRPT_T::AES_CTL: KEYPRT Position */ +#define CRPT_AES_CTL_KEYPRT_Msk (0x1ul << CRPT_AES_CTL_KEYPRT_Pos) /*!< CRPT_T::AES_CTL: KEYPRT Mask */ + +#define CRPT_AES_STS_BUSY_Pos (0) /*!< CRPT_T::AES_STS: BUSY Position */ +#define CRPT_AES_STS_BUSY_Msk (0x1ul << CRPT_AES_STS_BUSY_Pos) /*!< CRPT_T::AES_STS: BUSY Mask */ + +#define CRPT_AES_STS_INBUFEMPTY_Pos (8) /*!< CRPT_T::AES_STS: INBUFEMPTY Position */ +#define CRPT_AES_STS_INBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_INBUFEMPTY_Pos) /*!< CRPT_T::AES_STS: INBUFEMPTY Mask */ + +#define CRPT_AES_STS_INBUFFULL_Pos (9) /*!< CRPT_T::AES_STS: INBUFFULL Position */ +#define CRPT_AES_STS_INBUFFULL_Msk (0x1ul << CRPT_AES_STS_INBUFFULL_Pos) /*!< CRPT_T::AES_STS: INBUFFULL Mask */ + +#define CRPT_AES_STS_INBUFERR_Pos (10) /*!< CRPT_T::AES_STS: INBUFERR Position */ +#define CRPT_AES_STS_INBUFERR_Msk (0x1ul << CRPT_AES_STS_INBUFERR_Pos) /*!< CRPT_T::AES_STS: INBUFERR Mask */ + +#define CRPT_AES_STS_CNTERR_Pos (12) /*!< CRPT_T::AES_STS: CNTERR Position */ +#define CRPT_AES_STS_CNTERR_Msk (0x1ul << CRPT_AES_STS_CNTERR_Pos) /*!< CRPT_T::AES_STS: CNTERR Mask */ + +#define CRPT_AES_STS_OUTBUFEMPTY_Pos (16) /*!< CRPT_T::AES_STS: OUTBUFEMPTY Position*/ +#define CRPT_AES_STS_OUTBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_OUTBUFEMPTY_Pos) /*!< CRPT_T::AES_STS: OUTBUFEMPTY Mask */ + +#define CRPT_AES_STS_OUTBUFFULL_Pos (17) /*!< CRPT_T::AES_STS: OUTBUFFULL Position */ +#define CRPT_AES_STS_OUTBUFFULL_Msk (0x1ul << CRPT_AES_STS_OUTBUFFULL_Pos) /*!< CRPT_T::AES_STS: OUTBUFFULL Mask */ + +#define CRPT_AES_STS_OUTBUFERR_Pos (18) /*!< CRPT_T::AES_STS: OUTBUFERR Position */ +#define CRPT_AES_STS_OUTBUFERR_Msk (0x1ul << CRPT_AES_STS_OUTBUFERR_Pos) /*!< CRPT_T::AES_STS: OUTBUFERR Mask */ + +#define CRPT_AES_STS_BUSERR_Pos (20) /*!< CRPT_T::AES_STS: BUSERR Position */ +#define CRPT_AES_STS_BUSERR_Msk (0x1ul << CRPT_AES_STS_BUSERR_Pos) /*!< CRPT_T::AES_STS: BUSERR Mask */ + +#define CRPT_AES_DATIN_DATIN_Pos (0) /*!< CRPT_T::AES_DATIN: DATIN Position */ +#define CRPT_AES_DATIN_DATIN_Msk (0xfffffffful << CRPT_AES_DATIN_DATIN_Pos) /*!< CRPT_T::AES_DATIN: DATIN Mask */ + +#define CRPT_AES_DATOUT_DATOUT_Pos (0) /*!< CRPT_T::AES_DATOUT: DATOUT Position */ +#define CRPT_AES_DATOUT_DATOUT_Msk (0xfffffffful << CRPT_AES_DATOUT_DATOUT_Pos) /*!< CRPT_T::AES_DATOUT: DATOUT Mask */ + +#define CRPT_AES_KEYx_KEY_Pos (0) /*!< CRPT_T::AES_KEY[8]: KEY Position */ +#define CRPT_AES_KEYx_KEY_Msk (0xfffffffful << CRPT_AES_KEYx_KEY_Pos) /*!< CRPT_T::AES_KEY[8]: KEY Mask */ + +#define CRPT_AES_IVx_IV_Pos (0) /*!< CRPT_T::AES_IV[4]: IV Position */ +#define CRPT_AES_IVx_IV_Msk (0xfffffffful << CRPT_AES_IVx_IV_Pos) /*!< CRPT_T::AES_IV[4]: IV Mask */ + +#define CRPT_AES_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES_SADDR: SADDR Position */ +#define CRPT_AES_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES_SADDR_SADDR_Pos) /*!< CRPT_T::AES_SADDR: SADDR Mask */ + +#define CRPT_AES_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES_DADDR: DADDR Position */ +#define CRPT_AES_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES_DADDR_DADDR_Pos) /*!< CRPT_T::AES_DADDR: DADDR Mask */ + +#define CRPT_AES_CNT_CNT_Pos (0) /*!< CRPT_T::AES_CNT: CNT Position */ +#define CRPT_AES_CNT_CNT_Msk (0xfffffffful << CRPT_AES_CNT_CNT_Pos) /*!< CRPT_T::AES_CNT: CNT Mask */ + +/**@}*/ /* CRPT_CONST CRYPTO */ +/**@}*/ /* end of CRYPTO register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + + +#endif /* __CRYPTO_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/dac_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/dac_reg.h new file mode 100644 index 00000000000..e3f21c9bdf8 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/dac_reg.h @@ -0,0 +1,203 @@ +/**************************************************************************//** + * @file dac_reg.h + * @version V1.00 + * @brief DAC register definition header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __DAC_REG_H__ +#define __DAC_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup DAC Digital to Analog Converter (DAC) + Memory Mapped Structure for DAC Controller +@{ */ + +typedef struct +{ + + + /** + * @var DAC_T::CTL + * Offset: 0x00 DAC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DACEN |DAC Enable Bit + * | | |0 = DAC is Disabled. + * | | |1 = DAC is Enabled. + * |[1] |DACIEN |DAC Interrupt Enable Bit + * | | |0 = Interrupt is Disabled. + * | | |1 = Interrupt is Enabled. + * |[2] |DMAEN |DMA Mode Enable Bit + * | | |0 = DMA mode Disabled. + * | | |1 = DMA mode Enabled. + * |[3] |DMAURIEN |DMA Under-run Interrupt Enable Bit + * | | |0 = DMA underrun interrupt Disabled. + * | | |1 = DMA underrun interrupt Enabled. + * |[4] |TRGEN |Trigger Mode Enable Bit + * | | |0 = DAC event trigger mode Disabled. + * | | |1 = DAC event trigger mode Enabled. + * |[7:5] |TRGSEL |Trigger Source Selection + * | | |000 = Software trigger. + * | | |001 = External pin DAC_ST trigger. + * | | |010 = Timer 0 trigger. + * | | |011 = Timer 1 trigger. + * | | |100 = Timer 2 trigger. + * | | |101 = Timer 3 trigger. + * | | |Others = reserved. + * |[8] |BYPASS |Bypass Buffer Mode + * | | |0 = Output voltage buffer Enabled. + * | | |1 = Output voltage buffer Disabled. + * |[10] |LALIGN |DAC Data Left-aligned Enabled Control + * | | |0 = Right alignment. + * | | |1 = Left alignment. + * |[13:12] |ETRGSEL |External Pin Trigger Selection + * | | |00 = Low level trigger. + * | | |01 = High level trigger. + * | | |10 = Falling edge trigger. + * | | |11 = Rising edge trigger. + * |[15:14] |BWSEL |DAC Data Bit-width Selection + * | | |00 = data is 12 bits. + * | | |01 = data is 8 bits. + * | | |Others = reserved. + * @var DAC_T::SWTRG + * Offset: 0x04 DAC Software Trigger Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SWTRG |Software Trigger + * | | |0 = Software trigger Disabled. + * | | |1 = Software trigger Enabled. + * | | |User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically; Reading this bit will always get 0. + * @var DAC_T::DAT + * Offset: 0x08 DAC Data Holding Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |DACDAT |DAC 12-bit Holding Data + * | | |The unused bits (DAC_DAT[3:0] in left-alignment mode and DAC_DAT[15:12] in right alignment mode) are ignored by DAC controller hardware. + * | | |12 bit left alignment: user has to load data into DAC_DAT[15:4] bits. + * | | |12 bit right alignment: user has to load data into DAC_DAT[11:0] bits. + * | | |DAC 8-bit Holding Data + * | | |The unused bits DAC_DAT[15:8] are ignored by DAC controller hardware. + * | | |Note: Conversion data and DAC output data is 12-bit + * @var DAC_T::DATOUT + * Offset: 0x0C DAC Data Output Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |DATOUT |DAC 12-bit Output Data + * | | |These bits are current digital data for DAC output conversion. + * | | |It is loaded from DAC_DAT register and user cannot write it directly. + * @var DAC_T::STATUS + * Offset: 0x10 DAC Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FINISH |DAC Conversion Complete Finish Flag + * | | |0 = DAC is in conversion state. + * | | |1 = DAC conversion finish. + * | | |This bit set to 1 when conversion time counter counts to SETTLET + * | | |It is cleared to 0 when DAC starts a new conversion + * | | |User writes 1 to clear this bit to 0. + * |[1] |DMAUDR |DMA Under Run Interrupt Flag + * | | |0 = No DMA under-run error condition occurred. + * | | |1 = DMA under-run error condition occurred. + * | | |User writes 1 to clear this bit. + * |[8] |BUSY |DAC Busy Flag (Read Only) + * | | |0 = DAC is ready for next conversion. + * | | |1 = DAC is busy in conversion. + * | | |This is read only bit. + * @var DAC_T::TCTL + * Offset: 0x14 DAC Timing Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |SETTLET |DAC Output Settling Time + * | | |User software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed. + * | | |For example, DAC controller clock speed is 50MHz and DAC conversion setting time is 1 us, SETTLET value must be greater than 0x32. + */ + __IO uint32_t CTL; /*!< [0x0000] DAC Control Register */ + __IO uint32_t SWTRG; /*!< [0x0004] DAC Software Trigger Control Register */ + __IO uint32_t DAT; /*!< [0x0008] DAC Data Holding Register */ + __I uint32_t DATOUT; /*!< [0x000c] DAC Data Output Register */ + __IO uint32_t STATUS; /*!< [0x0010] DAC Status Register */ + __IO uint32_t TCTL; /*!< [0x0014] DAC Timing Control Register */ + +} DAC_T; + +/** + @addtogroup DAC_CONST DAC Bit Field Definition + Constant Definitions for DAC Controller +@{ */ + +#define DAC_CTL_DACEN_Pos (0) /*!< DAC_T::CTL: DACEN Position */ +#define DAC_CTL_DACEN_Msk (0x1ul << DAC_CTL_DACEN_Pos) /*!< DAC_T::CTL: DACEN Mask */ + +#define DAC_CTL_DACIEN_Pos (1) /*!< DAC_T::CTL: DACIEN Position */ +#define DAC_CTL_DACIEN_Msk (0x1ul << DAC_CTL_DACIEN_Pos) /*!< DAC_T::CTL: DACIEN Mask */ + +#define DAC_CTL_DMAEN_Pos (2) /*!< DAC_T::CTL: DMAEN Position */ +#define DAC_CTL_DMAEN_Msk (0x1ul << DAC_CTL_DMAEN_Pos) /*!< DAC_T::CTL: DMAEN Mask */ + +#define DAC_CTL_DMAURIEN_Pos (3) /*!< DAC_T::CTL: DMAURIEN Position */ +#define DAC_CTL_DMAURIEN_Msk (0x1ul << DAC_CTL_DMAURIEN_Pos) /*!< DAC_T::CTL: DMAURIEN Mask */ + +#define DAC_CTL_TRGEN_Pos (4) /*!< DAC_T::CTL: TRGEN Position */ +#define DAC_CTL_TRGEN_Msk (0x1ul << DAC_CTL_TRGEN_Pos) /*!< DAC_T::CTL: TRGEN Mask */ + +#define DAC_CTL_TRGSEL_Pos (5) /*!< DAC_T::CTL: TRGSEL Position */ +#define DAC_CTL_TRGSEL_Msk (0x7ul << DAC_CTL_TRGSEL_Pos) /*!< DAC_T::CTL: TRGSEL Mask */ + +#define DAC_CTL_BYPASS_Pos (8) /*!< DAC_T::CTL: BYPASS Position */ +#define DAC_CTL_BYPASS_Msk (0x1ul << DAC_CTL_BYPASS_Pos) /*!< DAC_T::CTL: BYPASS Mask */ + +#define DAC_CTL_LALIGN_Pos (10) /*!< DAC_T::CTL: LALIGN Position */ +#define DAC_CTL_LALIGN_Msk (0x1ul << DAC_CTL_LALIGN_Pos) /*!< DAC_T::CTL: LALIGN Mask */ + +#define DAC_CTL_ETRGSEL_Pos (12) /*!< DAC_T::CTL: ETRGSEL Position */ +#define DAC_CTL_ETRGSEL_Msk (0x3ul << DAC_CTL_ETRGSEL_Pos) /*!< DAC_T::CTL: ETRGSEL Mask */ + +#define DAC_CTL_BWSEL_Pos (14) /*!< DAC_T::CTL: BWSEL Position */ +#define DAC_CTL_BWSEL_Msk (0x3ul << DAC_CTL_BWSEL_Pos) /*!< DAC_T::CTL: BWSEL Mask */ + +#define DAC_SWTRG_SWTRG_Pos (0) /*!< DAC_T::SWTRG: SWTRG Position */ +#define DAC_SWTRG_SWTRG_Msk (0x1ul << DAC_SWTRG_SWTRG_Pos) /*!< DAC_T::SWTRG: SWTRG Mask */ + +#define DAC_DAT_DACDAT_Pos (0) /*!< DAC_T::DAT: DACDAT Position */ +#define DAC_DAT_DACDAT_Msk (0xfffful << DAC_DAT_DACDAT_Pos) /*!< DAC_T::DAT: DACDAT Mask */ + +#define DAC_DATOUT_DATOUT_Pos (0) /*!< DAC_T::DATOUT: DATOUT Position */ +#define DAC_DATOUT_DATOUT_Msk (0xffful << DAC_DATOUT_DATOUT_Pos) /*!< DAC_T::DATOUT: DATOUT Mask */ + +#define DAC_STATUS_FINISH_Pos (0) /*!< DAC_T::STATUS: FINISH Position */ +#define DAC_STATUS_FINISH_Msk (0x1ul << DAC_STATUS_FINISH_Pos) /*!< DAC_T::STATUS: FINISH Mask */ + +#define DAC_STATUS_DMAUDR_Pos (1) /*!< DAC_T::STATUS: DMAUDR Position */ +#define DAC_STATUS_DMAUDR_Msk (0x1ul << DAC_STATUS_DMAUDR_Pos) /*!< DAC_T::STATUS: DMAUDR Mask */ + +#define DAC_STATUS_BUSY_Pos (8) /*!< DAC_T::STATUS: BUSY Position */ +#define DAC_STATUS_BUSY_Msk (0x1ul << DAC_STATUS_BUSY_Pos) /*!< DAC_T::STATUS: BUSY Mask */ + +#define DAC_TCTL_SETTLET_Pos (0) /*!< DAC_T::TCTL: SETTLET Position */ +#define DAC_TCTL_SETTLET_Msk (0x3fful << DAC_TCTL_SETTLET_Pos) /*!< DAC_T::TCTL: SETTLET Mask */ + +/**@}*/ /* DAC_CONST */ +/**@}*/ /* end of DAC register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __DAC_REG_H__ */ \ No newline at end of file diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/eadc_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/eadc_reg.h new file mode 100644 index 00000000000..d06cd6934bd --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/eadc_reg.h @@ -0,0 +1,837 @@ +/**************************************************************************//** + * @file eadc_reg.h + * @version V1.00 + * @brief EADC register definition header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EADC_REG_H__ +#define __EADC_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup EADC Enhanced Analog to Digital Converter (EADC) + Memory Mapped Structure for EADC Controller +@{ */ + +typedef struct +{ + + + /** + * @var EADC_T::DAT[19] + * Offset: 0x00~0x48 A/D Data Register 0~18 for Sample Module 0 ~ 18 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RESULT |A/D Conversion Result + * | | |This field contains 12 bits conversion result. + * |[16] |OV |Overrun Flag + * | | |If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1. + * | | |0 = Data in RESULT[11:0] is recent conversion result. + * | | |1 = Data in RESULT[11:0] is overwrite. + * | | |Note: It is cleared by hardware after EADC_DAT register is read. + * |[17] |VALID |Valid Flag + * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read. + * | | |0 = Data in RESULT[11:0] bits is not valid. + * | | |1 = Data in RESULT[11:0] bits is valid. + * @var EADC_T::CURDAT + * Offset: 0x4C EADC PDMA Current Transfer Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[18:0] |CURDAT |ADC PDMA Current Transfer Data (Read Only) + * | | |This register is a shadow register of EADC_DATn (n=0~18) for PDMA support. + * | | |This is a read only register. + * | | |NOTE: After PDMA read this register, the VAILD of the shadow EADC_DAT register will be automatically cleared. + * @var EADC_T::CTL + * Offset: 0x50 A/D Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADCEN |A/D Converter Enable Bit + * | | |0 = ADC Disabled. + * | | |1 = ADC Enabled. + * | | |Note: Before starting A/D conversion function, this bit should be set to 1 + * | | |Clear it to 0 to disable A/D converter analog circuit power consumption. + * |[1] |ADCRST |ADC A/D Converter Control Circuits Reset + * | | |0 = No effect. + * | | |1 = Cause ADC control circuits reset to initial state, but not change the ADC registers value. + * | | |Note: ADCRST bit remains 1 during ADC reset, when ADC reset end, the ADCRST bit is automatically cleared to 0. + * |[2] |ADCIEN0 |Specific Sample Module A/D ADINT0 Interrupt Enable Bit + * | | |The A/D converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module A/D conversion + * | | |If ADCIEN0 bit is set then conversion end interrupt request ADINT0 is generated. + * | | |0 = Specific sample module A/D ADINT0 interrupt function Disabled. + * | | |1 = Specific sample module A/D ADINT0 interrupt function Enabled. + * |[3] |ADCIEN1 |Specific Sample Module A/D ADINT1 Interrupt Enable Bit + * | | |The A/D converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module A/D conversion + * | | |If ADCIEN1 bit is set then conversion end interrupt request ADINT1 is generated. + * | | |0 = Specific sample module A/D ADINT1 interrupt function Disabled. + * | | |1 = Specific sample module A/D ADINT1 interrupt function Enabled. + * |[4] |ADCIEN2 |Specific Sample Module A/D ADINT2 Interrupt Enable Bit + * | | |The A/D converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module A/D conversion + * | | |If ADCIEN2 bit is set then conversion end interrupt request ADINT2 is generated. + * | | |0 = Specific sample module A/D ADINT2 interrupt function Disabled. + * | | |1 = Specific sample module A/D ADINT2 interrupt function Enabled. + * |[5] |ADCIEN3 |Specific Sample Module A/D ADINT3 Interrupt Enable Bit + * | | |The A/D converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module A/D conversion + * | | |If ADCIEN3 bit is set then conversion end interrupt request ADINT3 is generated. + * | | |0 = Specific sample module A/D ADINT3 interrupt function Disabled. + * | | |1 = Specific sample module A/D ADINT3 interrupt function Enabled. + * @var EADC_T::SWTRG + * Offset: 0x54 A/D Sample Module Software Start Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[18:0] |SWTRG |A/D Sample Module 0~18 Software Force to Start ADC Conversion + * | | |0 = No effect. + * | | |1 = Cause an ADC conversion when the priority is given to sample module. + * | | |Note: After writing this register to start ADC conversion, the EADC_PENDSTS register will show which sample module will conversion + * | | |If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it. + * @var EADC_T::PENDSTS + * Offset: 0x58 A/D Start of Conversion Pending Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[18:0] |STPF |A/D Sample Module 0~18 Start of Conversion Pending Flag + * | | |Read: + * | | |0 = There is no pending conversion for sample module. + * | | |1 = Sample module ADC start of conversion is pending. + * | | |Write: + * | | |1 = Clear pending flag and stop conversion for corresponding sample module. + * | | |Note1: This bit remains 1 during pending state, when the respective ADC conversion is end, the STPFn (n=0~18) bit is automatically cleared to 0. + * | | |Note2: After stopping current conversion, the corresponding EADC_DATn (n=0~18) keeps its original value + * @var EADC_T::OVSTS + * Offset: 0x5C A/D Sample Module Start of Conversion Overrun Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[18:0] |SPOVF |A/D SAMPLE0~18 Overrun Flag + * | | |0 = No sample module event overrun. + * | | |1 = Indicates a new sample module event is generated while an old one event is pending. + * | | |Note: This bit is cleared by writing 1 to it. + * @var EADC_T::SCTL[16] + * Offset: 0x80~0xBC A/D Sample Module 0 ~ 15 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |CHSEL |A/D Sample Module Channel Selection + * | | |00H = EADC_CH0. + * | | |01H = EADC_CH1. + * | | |02H = EADC_CH2. + * | | |03H = EADC_CH3. + * | | |04H = EADC_CH4. + * | | |05H = EADC_CH5. + * | | |06H = EADC_CH6. + * | | |07H = EADC_CH7. + * | | |08H = EADC_CH8. + * | | |09H = EADC_CH9. + * | | |0AH = EADC_CH10. + * | | |0BH = EADC_CH11. + * | | |0CH = EADC_CH12. + * | | |0DH = EADC_CH13. + * | | |0EH = EADC_CH14. + * | | |0FH = EADC_CH15. + * | | |Note: when internal ADC channel16, 17 or 18 is selected, EADC_CH15 is useless. + * |[4] |EXTREN |A/D External Trigger Rising Edge Enable Bit + * | | |0 = Rising edge Disabled when A/D selects EADC0_ST as trigger source. + * | | |1 = Rising edge Enabled when A/D selects EADC0_ST trigger source. + * |[5] |EXTFEN |A/D External Trigger Falling Edge Enable Bit + * | | |0 = Falling edge Disabled when A/D selects EADC0_ST as trigger source. + * | | |1 = Falling edge Enabled when A/D selects EADC0_ST as trigger source. + * |[7:6] |TRGDLYDIV |A/D Sample Module Start of Conversion Trigger Delay Clock Divider Selection + * | | |Trigger delay clock frequency: + * | | |00 = ADC_CLK/1. + * | | |01 = ADC_CLK/2. + * | | |10 = ADC_CLK/4. + * | | |11 = ADC_CLK/16. + * |[15:8] |TRGDLYCNT |A/D Sample Module Start of Conversion Trigger Delay Time + * | | |Trigger delay time = TRGDLYCNT x ADC_CLK x n (n=1,2,4,16 from TRGDLYDIV setting). + * | | |Note: If TRGDLYCNT is set to 1, Trigger delay time is actullay the same as TRGDLYCNT is set to 2 for hardware operation. + * |[20:16] |TRGSEL |A/D Sample Module Start of Conversion Trigger Source Selection + * | | |0H = Disable trigger. + * | | |1H = External trigger from EADC0_ST pin input. + * | | |2H = ADC ADINT0 interrupt EOC (End of conversion) pulse trigger. + * | | |3H = ADC ADINT1 interrupt EOC (End of conversion) pulse trigger. + * | | |4H = Timer0 overflow pulse trigger. + * | | |5H = Timer1 overflow pulse trigger. + * | | |6H = Timer2 overflow pulse trigger. + * | | |7H = Timer3 overflow pulse trigger. + * | | |8H = PWM0TG0. + * | | |9H = PWM0TG1. + * | | |AH = PWM0TG2. + * | | |BH = PWM0TG3. + * | | |CH = PWM0TG4. + * | | |DH = PWM0TG5. + * | | |EH = PWM1TG0. + * | | |FH = PWM1TG1. + * | | |10H = PWM1TG2. + * | | |11H = PWM1TG3. + * | | |12H = PWM1TG4. + * | | |13H = PWM1TG5. + * | | |14H =BPWM0TG. + * | | |15H =BPWM1TG. + * | | |other = Reserved. + * | | |NOTE: Refer PWM_EADCTS0, PWM_EADCTS1, BPWM_EADCTS0, BPWM_ EADCTS1 and TIMERn_CTL (n=0~3) to get more information for PWM, BPWM trigger and timer trigger. + * |[22] |INTPOS |Interrupt Flag Position Select + * | | |0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at A/D end of conversion. + * | | |1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at A/D start of conversion. + * |[31:24] |EXTSMPT |ADC Sampling Time Extend + * | | |When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, user can extend A/D sampling time after trigger source is coming to get enough sampling time + * | | |EXTSMPT can be set from 0~8'd251. + * @var EADC_T::SCTL0[3] + * Offset: 0xc0~0xC8 A/D Sample Module 16 ~ 18 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PDMAEN |PDMA Transfer Enable Bit + * | | |When ADC conversion is completed, the converted data is loaded into EADC_DATn (n: 16 ~ 18) register, user can enable this bit to generate a PDMA data transfer request. + * | | |0 = PDMA data transfer Disabled. + * | | |1 = PDMA data transfer Enabled. + * | | |Note: When set this bit field to 1, user must set ADCIENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt. + * |[31:24] |EXTSMPT |ADC Sampling Time Extend + * | | |When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, user can extend A/D sampling time after trigger source is coming to get enough sampling time + * | | |EXTSMPT can be set from 0~8'd251. + * @var EADC_T::INTSRC[4] + * Offset: 0xD0~0xDC ADC Interrupt 0~4 Source Enable Control Register. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SPLIE0 |Sample Module 0 Interrupt Enable Bit + * | | |0 = Sample Module 0 interrupt Disabled. + * | | |1 = Sample Module 0 interrupt Enabled. + * |[1] |SPLIE1 |Sample Module 1 Interrupt Enable Bit + * | | |0 = Sample Module 1 interrupt Disabled. + * | | |1 = Sample Module 1 interrupt Enabled. + * |[2] |SPLIE2 |Sample Module 2 Interrupt Enable Bit + * | | |0 = Sample Module 2 interrupt Disabled. + * | | |1 = Sample Module 2 interrupt Enabled. + * |[3] |SPLIE3 |Sample Module 3 Interrupt Enable Bit + * | | |0 = Sample Module 3 interrupt Disabled. + * | | |1 = Sample Module 3 interrupt Enabled. + * |[4] |SPLIE4 |Sample Module 4 Interrupt Enable Bit + * | | |0 = Sample Module 4 interrupt Disabled. + * | | |1 = Sample Module 4 interrupt Enabled. + * |[5] |SPLIE5 |Sample Module 5 Interrupt Enable Bit + * | | |0 = Sample Module 5 interrupt Disabled. + * | | |1 = Sample Module 5 interrupt Enabled. + * |[6] |SPLIE6 |Sample Module 6 Interrupt Enable Bit + * | | |0 = Sample Module 6 interrupt Disabled. + * | | |1 = Sample Module 6 interrupt Enabled. + * |[7] |SPLIE7 |Sample Module 7 Interrupt Enable Bit + * | | |0 = Sample Module 7 interrupt Disabled. + * | | |1 = Sample Module 7 interrupt Enabled. + * |[8] |SPLIE8 |Sample Module 8 Interrupt Enable Bit + * | | |0 = Sample Module 8 interrupt Disabled. + * | | |1 = Sample Module 8 interrupt Enabled. + * |[9] |SPLIE9 |Sample Module 9 Interrupt Enable Bit + * | | |0 = Sample Module 9 interrupt Disabled. + * | | |1 = Sample Module 9 interrupt Enabled. + * |[10] |SPLIE10 |Sample Module 10 Interrupt Enable Bit + * | | |0 = Sample Module 10 interrupt Disabled. + * | | |1 = Sample Module 10 interrupt Enabled. + * |[11] |SPLIE11 |Sample Module 11 Interrupt Enable Bit + * | | |0 = Sample Module 11 interrupt Disabled. + * | | |1 = Sample Module 11 interrupt Enabled. + * |[12] |SPLIE12 |Sample Module 12 Interrupt Enable Bit + * | | |0 = Sample Module 12 interrupt Disabled. + * | | |1 = Sample Module 12 interrupt Enabled. + * |[13] |SPLIE13 |Sample Module 13 Interrupt Enable Bit + * | | |0 = Sample Module 13 interrupt Disabled. + * | | |1 = Sample Module 13 interrupt Enabled. + * |[14] |SPLIE14 |Sample Module 14 Interrupt Enable Bit + * | | |0 = Sample Module 14 interrupt Disabled. + * | | |1 = Sample Module 14 interrupt Enabled. + * |[15] |SPLIE15 |Sample Module 15 Interrupt Enable Bit + * | | |0 = Sample Module 15 interrupt Disabled. + * | | |1 = Sample Module 15 interrupt Enabled. + * |[16] |SPLIE16 |Sample Module 16 Interrupt Enable Bit + * | | |0 = Sample Module 16 interrupt Disabled. + * | | |1 = Sample Module 16 interrupt Enabled. + * |[17] |SPLIE17 |Sample Module 17 Interrupt Enable Bit + * | | |0 = Sample Module 17 interrupt Disabled. + * | | |1 = Sample Module 17 interrupt Enabled. + * |[18] |SPLIE18 |Sample Module 18 Interrupt Enable Bit + * | | |0 = Sample Module 18 interrupt Disabled. + * | | |1 = Sample Module 18 interrupt Enabled. + * @var EADC_T::CMP[4] + * Offset: 0xE0~0xEC A/D Result Compare Register 0 ~ 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADCMPEN |A/D Result Compare Enable Bit + * | | |0 = Compare Disabled. + * | | |1 = Compare Enabled. + * | | |Set this bit to 1 to enable compare CMPDAT (EADC_CMPn[27:16], n=0~3) with specified sample module conversion result when converted data is loaded into EADC_DAT register. + * |[1] |ADCMPIE |A/D Result Compare Interrupt Enable Bit + * | | |0 = Compare function interrupt Disabled. + * | | |1 = Compare function interrupt Enabled. + * | | |If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated. + * |[2] |CMPCOND |Compare Condition + * | | |0= Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one. + * | | |1= Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one. + * | | |Note: When the internal counter reaches the value to (CMPMCNT (EADC_CMPn[11:8], n=0~3) +1), the ADCMPFn bit will be set. + * |[7:3] |CMPSPL |Compare Sample Module Selection + * | | |00000 = Sample Module 0 conversion result EADC_DAT0 is selected to be compared. + * | | |00001 = Sample Module 1 conversion result EADC_DAT1 is selected to be compared. + * | | |00010 = Sample Module 2 conversion result EADC_DAT2 is selected to be compared. + * | | |00011 = Sample Module 3 conversion result EADC_DAT3 is selected to be compared. + * | | |00100 = Sample Module 4 conversion result EADC_DAT4 is selected to be compared. + * | | |00101 = Sample Module 5 conversion result EADC_DAT5 is selected to be compared. + * | | |00110 = Sample Module 6 conversion result EADC_DAT6 is selected to be compared. + * | | |00111 = Sample Module 7 conversion result EADC_DAT7 is selected to be compared. + * | | |01000 = Sample Module 8 conversion result EADC_DAT8 is selected to be compared. + * | | |01001 = Sample Module 9 conversion result EADC_DAT9 is selected to be compared. + * | | |01010 = Sample Module 10 conversion result EADC_DAT10 is selected to be compared. + * | | |01011 = Sample Module 11 conversion result EADC_DAT11 is selected to be compared. + * | | |01100 = Sample Module 12 conversion result EADC_DAT12 is selected to be compared. + * | | |01101 = Sample Module 13 conversion result EADC_DAT13 is selected to be compared. + * | | |01110 = Sample Module 14 conversion result EADC_DAT14 is selected to be compared. + * | | |01111 = Sample Module 15 conversion result EADC_DAT15 is selected to be compared. + * | | |10000 = Sample Module 16 conversion result EADC_DAT16 is selected to be compared. + * | | |10001 = Sample Module 17 conversion result EADC_DAT17 is selected to be compared. + * | | |10010 = Sample Module 18 conversion result EADC_DAT18 is selected to be compared. + * |[11:8] |CMPMCNT |Compare Match Count + * | | |When the specified A/D sample module analog conversion result matches the compare condition defined by CMPCOND (EADC_CMPn[2], n=0~3), the internal match counter will increase 1 + * | | |If the compare result does not meet the compare condition, the internal compare match counter will reset to 0 + * | | |When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be set. + * |[15] |CMPWEN |Compare Window Mode Enable Bit + * | | |0 = ADCMPF0 (EADC_STATUS2[4]) will be set when EADC_CMP0 compared condition matched + * | | |ADCMPF2 (EADC_STATUS2[6]) will be set when EADC_CMP2 compared condition matched + * | | |1 = ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched + * | | |ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched. + * | | |Note: This bit is only present in EADC_CMP0 and EADC_CMP2 register. + * |[27:16] |CMPDAT |Comparison Data + * | | |The 12 bits data is used to compare with conversion result of specified sample module + * | | |User can use it to monitor the external analog input pin voltage transition without imposing a load on software. + * @var EADC_T::STATUS0 + * Offset: 0xF0 A/D Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |VALID |EADC_DAT0~15 Data Valid Flag + * | | |It is a mirror of VALID bit in sample module A/D result data register EADC_DATn. (n=0~15). + * |[31:16] |OV |EADC_DAT0~15 Overrun Flag + * | | |It is a mirror to OV bit in sample module A/D result data register EADC_DATn. (n=0~15). + * @var EADC_T::STATUS1 + * Offset: 0xF4 A/D Status Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |VALID |EADC_DAT16~18 Data Valid Flag + * | | |It is a mirror of VALID bit in sample module A/D result data register EADC_DATn. (n=16~18). + * |[18:16] |OV |EADC_DAT16~18 Overrun Flag + * | | |It is a mirror to OV bit in sample module A/D result data register EADC_DATn. (n=16~18). + * @var EADC_T::STATUS2 + * Offset: 0xF8 A/D Status Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADIF0 |A/D ADINT0 Interrupt Flag + * | | |0 = No ADINT0 interrupt pulse received. + * | | |1 = ADINT0 interrupt pulse has been received. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2:This bit indicates whether an A/D conversion of specific sample module has been completed + * |[1] |ADIF1 |A/D ADINT1 Interrupt Flag + * | | |0 = No ADINT1 interrupt pulse received. + * | | |1 = ADINT1 interrupt pulse has been received. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2:This bit indicates whether an A/D conversion of specific sample module has been completed + * |[2] |ADIF2 |A/D ADINT2 Interrupt Flag + * | | |0 = No ADINT2 interrupt pulse received. + * | | |1 = ADINT2 interrupt pulse has been received. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2:This bit indicates whether an A/D conversion of specific sample module has been completed + * |[3] |ADIF3 |A/D ADINT3 Interrupt Flag + * | | |0 = No ADINT3 interrupt pulse received. + * | | |1 = ADINT3 interrupt pulse has been received. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2:This bit indicates whether an A/D conversion of specific sample module has been completed + * |[4] |ADCMPF0 |ADC Compare 0 Flag + * | | |When the specific sample module A/D conversion result meets setting condition in EADC_CMP0 then this bit is set to 1. + * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP0 register setting. + * | | |1 = Conversion result in EADC_DAT meets EADC_CMP0 register setting. + * | | |Note: This bit is cleared by writing 1 to it. + * |[5] |ADCMPF1 |ADC Compare 1 Flag + * | | |When the specific sample module A/D conversion result meets setting condition in EADC_CMP1 then this bit is set to 1. + * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP1 register setting. + * | | |1 = Conversion result in EADC_DAT meets EADC_CMP1 register setting. + * | | |Note: This bit is cleared by writing 1 to it. + * |[6] |ADCMPF2 |ADC Compare 2 Flag + * | | |When the specific sample module A/D conversion result meets setting condition in EADC_CMP2 then this bit is set to 1. + * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP2 register setting. + * | | |1 = Conversion result in EADC_DAT meets EADC_CMP2 register setting. + * | | |Note: This bit is cleared by writing 1 to it. + * |[7] |ADCMPF3 |ADC Compare 3 Flag + * | | |When the specific sample module A/D conversion result meets setting condition in EADC_CMP3 then this bit is set to 1. + * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP3 register setting. + * | | |1 = Conversion result in EADC_DAT meets EADC_CMP3 register setting. + * | | |Note: This bit is cleared by writing 1 to it. + * |[8] |ADOVIF0 |A/D ADINT0 Interrupt Flag Overrun + * | | |0 = ADINT0 interrupt flag is not overwritten to 1. + * | | |1 = ADINT0 interrupt flag is overwritten to 1. + * | | |Note: This bit is cleared by writing 1 to it. + * |[9] |ADOVIF1 |A/D ADINT1 Interrupt Flag Overrun + * | | |0 = ADINT1 interrupt flag is not overwritten to 1. + * | | |1 = ADINT1 interrupt flag is overwritten to 1. + * | | |Note: This bit is cleared by writing 1 to it. + * |[10] |ADOVIF2 |A/D ADINT2 Interrupt Flag Overrun + * | | |0 = ADINT2 interrupt flag is not overwritten to 1. + * | | |1 = ADINT2 interrupt flag is overwritten to 1. + * | | |Note: This bit is cleared by writing 1 to it. + * |[11] |ADOVIF3 |A/D ADINT3 Interrupt Flag Overrun + * | | |0 = ADINT3 interrupt flag is not overwritten to 1. + * | | |1 = ADINT3 interrupt flag is overwritten to 1. + * | | |Note: This bit is cleared by writing 1 to it. + * |[12] |ADCMPO0 |ADC Compare 0 Output Status + * | | |The 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module + * | | |User can use it to monitor the external analog input pin voltage status. + * | | |0 = Conversion result in EADC_DAT less than CMPDAT0 setting. + * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT0 setting. + * |[13] |ADCMPO1 |ADC Compare 1 Output Status + * | | |The 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module + * | | |User can use it to monitor the external analog input pin voltage status. + * | | |0 = Conversion result in EADC_DAT less than CMPDAT1 setting. + * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT1 setting. + * |[14] |ADCMPO2 |ADC Compare 2 Output Status + * | | |The 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module + * | | |User can use it to monitor the external analog input pin voltage status. + * | | |0 = Conversion result in EADC_DAT less than CMPDAT2 setting. + * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT2 setting. + * |[15] |ADCMPO3 |ADC Compare 3 Output Status + * | | |The 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module + * | | |User can use it to monitor the external analog input pin voltage status. + * | | |0 = Conversion result in EADC_DAT less than CMPDAT3 setting. + * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT3 setting. + * |[20:16] |CHANNEL |Current Conversion Channel + * | | |This filed reflects ADC current conversion channel when BUSY=1. + * | | |It is read only. + * | | |00H = EADC_CH0. + * | | |01H = EADC_CH1. + * | | |02H = EADC_CH2. + * | | |03H = EADC_CH3. + * | | |04H = EADC_CH4. + * | | |05H = EADC_CH5. + * | | |06H = EADC_CH6. + * | | |07H = EADC_CH7. + * | | |08H = EADC_CH8. + * | | |09H = EADC_CH9. + * | | |0AH = EADC_CH10. + * | | |0BH = EADC_CH11. + * | | |0CH = EADC_CH12. + * | | |0DH = EADC_CH13. + * | | |0EH = EADC_CH14. + * | | |0FH = EADC_CH15. + * | | |10H = VBG. + * | | |11H = VTEMP. + * | | |12H = VBAT/4. + * | | |Note: These bit are read only. + * |[23] |BUSY |A/D Conveter Busy/Idle Status + * | | |0 = EADC is in idle state. + * | | |1 = EADC is busy for sample or conversion. + * | | |Note: This bit is read only + * | | |Once trigger source is coming, it must wait 2 ADC_CLK synchronization then the BUSY status will be high + * | | |This status will be high to low when the current conversion done. + * |[24] |ADOVIF |All A/D Interrupt Flag Overrun Bits Check + * | | |n=0~3. + * | | |0 = None of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1. + * | | |1 = Any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1. + * | | |Note: This bit will keep 1 when any ADOVIFn Flag is equal to 1. + * |[25] |STOVF |for All A/D Sample Module Start of Conversion Overrun Flags Check + * | | |n=0~18. + * | | |0 = None of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1. + * | | |1 = Any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1. + * | | |Note: This bit will keep 1 when any SPOVFn Flag is equal to 1. + * |[26] |AVALID |for All Sample Module A/D Result Data Register EADC_DAT Data Valid Flag Check + * | | |n=0~18. + * | | |0 = None of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1. + * | | |1 = Any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1. + * | | |Note: This bit will keep 1 when any VALIDn Flag is equal to 1. + * |[27] |AOV |for All Sample Module A/D Result Data Register Overrun Flags Check + * | | |n=0~18. + * | | |0 = None of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1. + * | | |1 = Any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1. + * | | |Note: This bit will keep 1 when any OVn Flag is equal to 1. + * @var EADC_T::STATUS3 + * Offset: 0xFC A/D Status Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |CURSPL |ADC Current Sample Module + * | | |This register show the current ADC is controlled by which sample module control logic modules. + * | | |If the ADC is Idle, this bit filed will set to 0x1F. + * | | |Note: This is a read only register. + * @var EADC_T::PWRCTL + * Offset: 0x110 ADC Power Management Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |READY |ADC Start-up Completely and Ready for Conversion (Read Only) + * | | |0 = Power-on sequence is still in progress. + * | | |1 = ADC is ready for conversion. + * |[5] |AUTOFF |Auto Off Mode + * | | |0 = Function of auto off disabled. + * | | |1 = Function of auto off enabled + * | | |When AUTOFF is set to 1, ADC will be power off automatically to save power + * |[19:8] |STUPT |ADC Start-up Time + * | | |Set this bit fields to adjust start-up time. The minimum start-up time of ADC is 10us. + * | | |ADC start-up time = (1/ADC_CLK) x STUPT. + * |[23:20] |AUTOPDTHT |Auto Power Down Threshold Time + * | | |Auto Power Down Threshold Time = (1/ADC_CLK) x AUTOPDTHT. + * | | |0111 = 8 ADC clock for power down threshold time. + * | | |1000 = 16 ADC clock for power down threshold time. + * | | |1001 = 32 ADC clock for power down threshold time. + * | | |1010 = 64 ADC clock for power down threshold time. + * | | |1011 = 128 ADC clock for power down threshold time. + * | | |1100 = 256 ADC clock for power down threshold time. + * | | |Others = 256 ADC clock for power down threshold time. + * @var EADC_T::PDMACTL + * Offset: 0x130 ADC PDMA Control Rgister + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[18:0] |PDMATEN |PDMA Transfer Enable Bit + * | | |When ADC conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, user can enable this bit to generate a PDMA data transfer request. + * | | |0 = PDMA data transfer Disabled. + * | | |1 = PDMA data transfer Enabled. + * | | |Note: When set this bit field to 1, user must set ADCIENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt. + * @var EADC_T::MCTL1[16] + * Offset: 0x140~0x17C A/D Sample Module 0~15 Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ALIGN |Alignment Selection + * | | |0 = The conversion result will be right aligned in data register. + * | | |1 = The conversion result will be left aligned in data register. + * |[1] |AVG |Average Mode Selection + * | | |0 = Conversion results will be stored in data register without averaging. + * | | |1 = Conversion results in data register will be averaged. + * | | |This bit needs to work with ACU (EADC_MnCTL1[7:4], n=0~15). + * |[7:4] |ACU |Number of Accumulated Conversion Results Selection + * | | |0H = 1 conversion result will be accumulated. + * | | |1H = 2 conversion result will be accumulated. + * | | |2H = 4 conversion result will be accumulated. + * | | |3H = 8 conversion result will be accumulated. + * | | |4H = 16 conversion result will be accumulated. + * | | |5H = 32 conversion result will be accumulated. + * | | |6H = 64 conversion result will be accumulated. + * | | |7H = 128 conversion result will be accumulated. + * | | |8H = 256 conversion result will be accumulated. + * @var EADC_T::OFFSETCAL + * Offset: 0x208 A/D Result Offset Cancellation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |OFFSETCANCEL|A/D Offset Cancellation Trim Bits + * | | |When CALEN(EADC_CTL[8]) is set to 1, the offset cancellation trim bits will compensate A/D result offset + * | | |When this bit is set to 0, the offset cancellation trim bits have no effect to A/D result. + * | | |Note:These 5 bits trim value wouln't latched into EADC_OFFSETCAL automatically when flash initalization + * | | |User must read DCR2 by ISP command first, then write the value to OFFSETCANCEL. + * | | |Note: OFFSETCANCEL is signed format + * | | |OFFSETCANCEL will sign extension to 12 bit by hardware to perform signed addition with ADC conversion result if CALEN is enabled. + */ + __I uint32_t DAT[19]; /*!< [0x0000~0x0048] A/D Data Register n for Sample Module n, n=0~18 */ + __I uint32_t CURDAT; /*!< [0x004c] EADC PDMA Current Transfer Data Register */ + __IO uint32_t CTL; /*!< [0x0050] A/D Control Register */ + __O uint32_t SWTRG; /*!< [0x0054] A/D Sample Module Software Start Register */ + __IO uint32_t PENDSTS; /*!< [0x0058] A/D Start of Conversion Pending Flag Register */ + __IO uint32_t OVSTS; /*!< [0x005c] A/D Sample Module Start of Conversion Overrun Flag Register */ + __I uint32_t RESERVE0[8]; + __IO uint32_t SCTL[16]; /*!< [0x0080~0x00bc] A/D Sample Module n Control Register n=0~15 */ + __IO uint32_t SCTL0[3]; /*!< [0x00c0~0x00c8] A/D Sample Module n Control Register n=16~18 */ + __I uint32_t RESERVE1[1]; + __IO uint32_t INTSRC[4]; /*!< [0x00d0~0x00dc] ADC Interrupt n Source Enable Control Register. n=0~3 */ + __IO uint32_t CMP[4]; /*!< [0x00e0~0x00ec] A/D Result Compare Register n, n=0~3 */ + __I uint32_t STATUS0; /*!< [0x00f0] A/D Status Register 0 */ + __I uint32_t STATUS1; /*!< [0x00f4] A/D Status Register 1 */ + __IO uint32_t STATUS2; /*!< [0x00f8] A/D Status Register 2 */ + __I uint32_t STATUS3; /*!< [0x00fc] A/D Status Register 3 */ + __I uint32_t RESERVE2[4]; + __IO uint32_t PWRCTL; /*!< [0x0110] ADC Power Management Control Register */ + __I uint32_t RESERVE3[7]; + __IO uint32_t PDMACTL; /*!< [0x0130] ADC PDMA Control Rgister */ + __I uint32_t RESERVE4[3]; + __IO uint32_t MCTL1[16]; /*!< [0x0140~0x017c] A/D Sample Module n Control Register 1, n=0~15 */ + __I uint32_t RESERVE5[34]; + __IO uint32_t OFFSETCAL; /*!< [0x0208] A/D Result Offset Cancellation Register */ + + +} EADC_T; + +/** + @addtogroup EADC_CONST EADC Bit Field Definition + Constant Definitions for EADC Controller +@{ */ + +#define EADC_DAT_RESULT_Pos (0) /*!< EADC_T::DATn: RESULT Position */ +#define EADC_DAT_RESULT_Msk (0xfffful << EADC_DAT_RESULT_Pos) /*!< EADC_T::DATn: RESULT Mask */ + +#define EADC_DAT_OV_Pos (16) /*!< EADC_T::DATn: OV Position */ +#define EADC_DAT_OV_Msk (0x1ul << EADC_DAT_OV_Pos) /*!< EADC_T::DATn: OV Mask */ + +#define EADC_DAT_VALID_Pos (17) /*!< EADC_T::DATn: VALID Position */ +#define EADC_DAT_VALID_Msk (0x1ul << EADC_DAT_VALID_Pos) /*!< EADC_T::DATn: VALID Mask */ + +#define EADC_CURDAT_CURDAT_Pos (0) /*!< EADC_T::CURDAT: CURDAT Position */ +#define EADC_CURDAT_CURDAT_Msk (0x3fffful << EADC_CURDAT_CURDAT_Pos) /*!< EADC_T::CURDAT: CURDAT Mask */ + +#define EADC_CTL_ADCEN_Pos (0) /*!< EADC_T::CTL: ADCEN Position */ +#define EADC_CTL_ADCEN_Msk (0x1ul << EADC_CTL_ADCEN_Pos) /*!< EADC_T::CTL: ADCEN Mask */ + +#define EADC_CTL_ADCRST_Pos (1) /*!< EADC_T::CTL: ADCRST Position */ +#define EADC_CTL_ADCRST_Msk (0x1ul << EADC_CTL_ADCRST_Pos) /*!< EADC_T::CTL: ADCRST Mask */ + +#define EADC_CTL_ADCIEN0_Pos (2) /*!< EADC_T::CTL: ADCIEN0 Position */ +#define EADC_CTL_ADCIEN0_Msk (0x1ul << EADC_CTL_ADCIEN0_Pos) /*!< EADC_T::CTL: ADCIEN0 Mask */ + +#define EADC_CTL_ADCIEN1_Pos (3) /*!< EADC_T::CTL: ADCIEN1 Position */ +#define EADC_CTL_ADCIEN1_Msk (0x1ul << EADC_CTL_ADCIEN1_Pos) /*!< EADC_T::CTL: ADCIEN1 Mask */ + +#define EADC_CTL_ADCIEN2_Pos (4) /*!< EADC_T::CTL: ADCIEN2 Position */ +#define EADC_CTL_ADCIEN2_Msk (0x1ul << EADC_CTL_ADCIEN2_Pos) /*!< EADC_T::CTL: ADCIEN2 Mask */ + +#define EADC_CTL_ADCIEN3_Pos (5) /*!< EADC_T::CTL: ADCIEN3 Position */ +#define EADC_CTL_ADCIEN3_Msk (0x1ul << EADC_CTL_ADCIEN3_Pos) /*!< EADC_T::CTL: ADCIEN3 Mask */ + +#define EADC_CTL_CALEN_Pos (8) /*!< EADC_T::CTL: CALEN Position */ +#define EADC_CTL_CALEN_Msk (0x1ul << EADC_CTL_CALEN_Pos) /*!< EADC_T::CTL: CALEN Mask */ + +#define EADC_SWTRG_SWTRG_Pos (0) /*!< EADC_T::SWTRG: SWTRG Position */ +#define EADC_SWTRG_SWTRG_Msk (0x7fffful << EADC_SWTRG_SWTRG_Pos) /*!< EADC_T::SWTRG: SWTRG Mask */ + +#define EADC_PENDSTS_STPF_Pos (0) /*!< EADC_T::PENDSTS: STPF Position */ +#define EADC_PENDSTS_STPF_Msk (0x7fffful << EADC_PENDSTS_STPF_Pos) /*!< EADC_T::PENDSTS: STPF Mask */ + +#define EADC_OVSTS_SPOVF_Pos (0) /*!< EADC_T::OVSTS: SPOVF Position */ +#define EADC_OVSTS_SPOVF_Msk (0x7fffful << EADC_OVSTS_SPOVF_Pos) /*!< EADC_T::OVSTS: SPOVF Mask */ + +#define EADC_SCTL_CHSEL_Pos (0) /*!< EADC_T::SCTLn: CHSEL Position */ +#define EADC_SCTL_CHSEL_Msk (0xful << EADC_SCTL_CHSEL_Pos) /*!< EADC_T::SCTLn: CHSEL Mask */ + +#define EADC_SCTL_EXTREN_Pos (4) /*!< EADC_T::SCTLn: EXTREN Position */ +#define EADC_SCTL_EXTREN_Msk (0x1ul << EADC_SCTL_EXTREN_Pos) /*!< EADC_T::SCTLn: EXTREN Mask */ + +#define EADC_SCTL_EXTFEN_Pos (5) /*!< EADC_T::SCTLn: EXTFEN Position */ +#define EADC_SCTL_EXTFEN_Msk (0x1ul << EADC_SCTL_EXTFEN_Pos) /*!< EADC_T::SCTLn: EXTFEN Mask */ + +#define EADC_SCTL_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTLn: TRGDLYDIV Position */ +#define EADC_SCTL_TRGDLYDIV_Msk (0x3ul << EADC_SCTL_TRGDLYDIV_Pos) /*!< EADC_T::SCTLn: TRGDLYDIV Mask */ + +#define EADC_SCTL_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTLn: TRGDLYCNT Position */ +#define EADC_SCTL_TRGDLYCNT_Msk (0xfful << EADC_SCTL_TRGDLYCNT_Pos) /*!< EADC_T::SCTLn: TRGDLYCNT Mask */ + +#define EADC_SCTL_TRGSEL_Pos (16) /*!< EADC_T::SCTLn: TRGSEL Position */ +#define EADC_SCTL_TRGSEL_Msk (0x1ful << EADC_SCTL_TRGSEL_Pos) /*!< EADC_T::SCTLn: TRGSEL Mask */ + +#define EADC_SCTL_INTPOS_Pos (22) /*!< EADC_T::SCTLn: INTPOS Position */ +#define EADC_SCTL_INTPOS_Msk (0x1ul << EADC_SCTL_INTPOS_Pos) /*!< EADC_T::SCTLn: INTPOS Mask */ + +#define EADC_SCTL_EXTSMPT_Pos (24) /*!< EADC_T::SCTLn: EXTSMPT Position */ +#define EADC_SCTL_EXTSMPT_Msk (0xfful << EADC_SCTL_EXTSMPT_Pos) /*!< EADC_T::SCTLn: EXTSMPT Mask */ + +#define EADC_SCTL0_EXTSMPT_Pos (24) /*!< EADC_T::SCTL0n: EXTSMPT Position */ +#define EADC_SCTL0_EXTSMPT_Msk (0xfful << EADC_SCTL0_EXTSMPT_Pos) /*!< EADC_T::SCTL0n: EXTSMPT Mask */ + +#define EADC_INTSRC_SPLIE0_Pos (0) /*!< EADC_T::INTSRCn: SPLIE0 Position */ +#define EADC_INTSRC_SPLIE0_Msk (0x1ul << EADC_INTSRC_SPLIE0_Pos) /*!< EADC_T::INTSRCn: SPLIE0 Mask */ + +#define EADC_INTSRC_SPLIE1_Pos (1) /*!< EADC_T::INTSRCn: SPLIE1 Position */ +#define EADC_INTSRC_SPLIE1_Msk (0x1ul << EADC_INTSRC_SPLIE1_Pos) /*!< EADC_T::INTSRCn: SPLIE1 Mask */ + +#define EADC_INTSRC_SPLIE2_Pos (2) /*!< EADC_T::INTSRCn: SPLIE2 Position */ +#define EADC_INTSRC_SPLIE2_Msk (0x1ul << EADC_INTSRC_SPLIE2_Pos) /*!< EADC_T::INTSRCn: SPLIE2 Mask */ + +#define EADC_INTSRC_SPLIE3_Pos (3) /*!< EADC_T::INTSRCn: SPLIE3 Position */ +#define EADC_INTSRC_SPLIE3_Msk (0x1ul << EADC_INTSRC_SPLIE3_Pos) /*!< EADC_T::INTSRCn: SPLIE3 Mask */ + +#define EADC_INTSRC_SPLIE4_Pos (4) /*!< EADC_T::INTSRCn: SPLIE4 Position */ +#define EADC_INTSRC_SPLIE4_Msk (0x1ul << EADC_INTSRC_SPLIE4_Pos) /*!< EADC_T::INTSRCn: SPLIE4 Mask */ + +#define EADC_INTSRC_SPLIE5_Pos (5) /*!< EADC_T::INTSRCn: SPLIE5 Position */ +#define EADC_INTSRC_SPLIE5_Msk (0x1ul << EADC_INTSRC_SPLIE5_Pos) /*!< EADC_T::INTSRCn: SPLIE5 Mask */ + +#define EADC_INTSRC_SPLIE6_Pos (6) /*!< EADC_T::INTSRCn: SPLIE6 Position */ +#define EADC_INTSRC_SPLIE6_Msk (0x1ul << EADC_INTSRC_SPLIE6_Pos) /*!< EADC_T::INTSRCn: SPLIE6 Mask */ + +#define EADC_INTSRC_SPLIE7_Pos (7) /*!< EADC_T::INTSRCn: SPLIE7 Position */ +#define EADC_INTSRC_SPLIE7_Msk (0x1ul << EADC_INTSRC_SPLIE7_Pos) /*!< EADC_T::INTSRCn: SPLIE7 Mask */ + +#define EADC_INTSRC_SPLIE8_Pos (8) /*!< EADC_T::INTSRCn: SPLIE8 Position */ +#define EADC_INTSRC_SPLIE8_Msk (0x1ul << EADC_INTSRC_SPLIE8_Pos) /*!< EADC_T::INTSRCn: SPLIE8 Mask */ + +#define EADC_INTSRC_SPLIE9_Pos (9) /*!< EADC_T::INTSRCn: SPLIE9 Position */ +#define EADC_INTSRC_SPLIE9_Msk (0x1ul << EADC_INTSRC_SPLIE9_Pos) /*!< EADC_T::INTSRCn: SPLIE9 Mask */ + +#define EADC_INTSRC_SPLIE10_Pos (10) /*!< EADC_T::INTSRCn: SPLIE10 Position */ +#define EADC_INTSRC_SPLIE10_Msk (0x1ul << EADC_INTSRC_SPLIE10_Pos) /*!< EADC_T::INTSRCn: SPLIE10 Mask */ + +#define EADC_INTSRC_SPLIE11_Pos (11) /*!< EADC_T::INTSRCn: SPLIE11 Position */ +#define EADC_INTSRC_SPLIE11_Msk (0x1ul << EADC_INTSRC_SPLIE11_Pos) /*!< EADC_T::INTSRCn: SPLIE11 Mask */ + +#define EADC_INTSRC_SPLIE12_Pos (12) /*!< EADC_T::INTSRCn: SPLIE12 Position */ +#define EADC_INTSRC_SPLIE12_Msk (0x1ul << EADC_INTSRC_SPLIE12_Pos) /*!< EADC_T::INTSRCn: SPLIE12 Mask */ + +#define EADC_INTSRC_SPLIE13_Pos (13) /*!< EADC_T::INTSRCn: SPLIE13 Position */ +#define EADC_INTSRC_SPLIE13_Msk (0x1ul << EADC_INTSRC_SPLIE13_Pos) /*!< EADC_T::INTSRCn: SPLIE13 Mask */ + +#define EADC_INTSRC_SPLIE14_Pos (14) /*!< EADC_T::INTSRCn: SPLIE14 Position */ +#define EADC_INTSRC_SPLIE14_Msk (0x1ul << EADC_INTSRC_SPLIE14_Pos) /*!< EADC_T::INTSRCn: SPLIE14 Mask */ + +#define EADC_INTSRC_SPLIE15_Pos (15) /*!< EADC_T::INTSRCn: SPLIE15 Position */ +#define EADC_INTSRC_SPLIE15_Msk (0x1ul << EADC_INTSRC_SPLIE15_Pos) /*!< EADC_T::INTSRCn: SPLIE15 Mask */ + +#define EADC_INTSRC_SPLIE16_Pos (16) /*!< EADC_T::INTSRCn: SPLIE16 Position */ +#define EADC_INTSRC_SPLIE16_Msk (0x1ul << EADC_INTSRC_SPLIE16_Pos) /*!< EADC_T::INTSRCn: SPLIE16 Mask */ + +#define EADC_INTSRC_SPLIE17_Pos (17) /*!< EADC_T::INTSRCn: SPLIE17 Position */ +#define EADC_INTSRC_SPLIE17_Msk (0x1ul << EADC_INTSRC_SPLIE17_Pos) /*!< EADC_T::INTSRCn: SPLIE17 Mask */ + +#define EADC_INTSRC_SPLIE18_Pos (18) /*!< EADC_T::INTSRCn: SPLIE18 Position */ +#define EADC_INTSRC_SPLIE18_Msk (0x1ul << EADC_INTSRC_SPLIE18_Pos) /*!< EADC_T::INTSRCn: SPLIE18 Mask */ + +#define EADC_CMP_ADCMPEN_Pos (0) /*!< EADC_T::CMPn: ADCMPEN Position */ +#define EADC_CMP_ADCMPEN_Msk (0x1ul << EADC_CMP_ADCMPEN_Pos) /*!< EADC_T::CMPn: ADCMPEN Mask */ + +#define EADC_CMP_ADCMPIE_Pos (1) /*!< EADC_T::CMPn: ADCMPIE Position */ +#define EADC_CMP_ADCMPIE_Msk (0x1ul << EADC_CMP_ADCMPIE_Pos) /*!< EADC_T::CMPn: ADCMPIE Mask */ + +#define EADC_CMP_CMPCOND_Pos (2) /*!< EADC_T::CMPn: CMPCOND Position */ +#define EADC_CMP_CMPCOND_Msk (0x1ul << EADC_CMP_CMPCOND_Pos) /*!< EADC_T::CMPn: CMPCOND Mask */ + +#define EADC_CMP_CMPSPL_Pos (3) /*!< EADC_T::CMPn: CMPSPL Position */ +#define EADC_CMP_CMPSPL_Msk (0x1ful << EADC_CMP_CMPSPL_Pos) /*!< EADC_T::CMPn: CMPSPL Mask */ + +#define EADC_CMP_CMPMCNT_Pos (8) /*!< EADC_T::CMPn: CMPMCNT Position */ +#define EADC_CMP_CMPMCNT_Msk (0xful << EADC_CMP_CMPMCNT_Pos) /*!< EADC_T::CMPn: CMPMCNT Mask */ + +#define EADC_CMP_CMPWEN_Pos (15) /*!< EADC_T::CMPn: CMPWEN Position */ +#define EADC_CMP_CMPWEN_Msk (0x1ul << EADC_CMP_CMPWEN_Pos) /*!< EADC_T::CMPn: CMPWEN Mask */ + +#define EADC_CMP_CMPDAT_Pos (16) /*!< EADC_T::CMPn: CMPDAT Position */ +#define EADC_CMP_CMPDAT_Msk (0xffful << EADC_CMP_CMPDAT_Pos) /*!< EADC_T::CMPn: CMPDAT Mask */ + +#define EADC_STATUS0_VALID_Pos (0) /*!< EADC_T::STATUS0: VALID Position */ +#define EADC_STATUS0_VALID_Msk (0xfffful << EADC_STATUS0_VALID_Pos) /*!< EADC_T::STATUS0: VALID Mask */ + +#define EADC_STATUS0_OV_Pos (16) /*!< EADC_T::STATUS0: OV Position */ +#define EADC_STATUS0_OV_Msk (0xfffful << EADC_STATUS0_OV_Pos) /*!< EADC_T::STATUS0: OV Mask */ + +#define EADC_STATUS1_VALID_Pos (0) /*!< EADC_T::STATUS1: VALID Position */ +#define EADC_STATUS1_VALID_Msk (0x7ul << EADC_STATUS1_VALID_Pos) /*!< EADC_T::STATUS1: VALID Mask */ + +#define EADC_STATUS1_OV_Pos (16) /*!< EADC_T::STATUS1: OV Position */ +#define EADC_STATUS1_OV_Msk (0x7ul << EADC_STATUS1_OV_Pos) /*!< EADC_T::STATUS1: OV Mask */ + +#define EADC_STATUS2_ADIF0_Pos (0) /*!< EADC_T::STATUS2: ADIF0 Position */ +#define EADC_STATUS2_ADIF0_Msk (0x1ul << EADC_STATUS2_ADIF0_Pos) /*!< EADC_T::STATUS2: ADIF0 Mask */ + +#define EADC_STATUS2_ADIF1_Pos (1) /*!< EADC_T::STATUS2: ADIF1 Position */ +#define EADC_STATUS2_ADIF1_Msk (0x1ul << EADC_STATUS2_ADIF1_Pos) /*!< EADC_T::STATUS2: ADIF1 Mask */ + +#define EADC_STATUS2_ADIF2_Pos (2) /*!< EADC_T::STATUS2: ADIF2 Position */ +#define EADC_STATUS2_ADIF2_Msk (0x1ul << EADC_STATUS2_ADIF2_Pos) /*!< EADC_T::STATUS2: ADIF2 Mask */ + +#define EADC_STATUS2_ADIF3_Pos (3) /*!< EADC_T::STATUS2: ADIF3 Position */ +#define EADC_STATUS2_ADIF3_Msk (0x1ul << EADC_STATUS2_ADIF3_Pos) /*!< EADC_T::STATUS2: ADIF3 Mask */ + +#define EADC_STATUS2_ADCMPF0_Pos (4) /*!< EADC_T::STATUS2: ADCMPF0 Position */ +#define EADC_STATUS2_ADCMPF0_Msk (0x1ul << EADC_STATUS2_ADCMPF0_Pos) /*!< EADC_T::STATUS2: ADCMPF0 Mask */ + +#define EADC_STATUS2_ADCMPF1_Pos (5) /*!< EADC_T::STATUS2: ADCMPF1 Position */ +#define EADC_STATUS2_ADCMPF1_Msk (0x1ul << EADC_STATUS2_ADCMPF1_Pos) /*!< EADC_T::STATUS2: ADCMPF1 Mask */ + +#define EADC_STATUS2_ADCMPF2_Pos (6) /*!< EADC_T::STATUS2: ADCMPF2 Position */ +#define EADC_STATUS2_ADCMPF2_Msk (0x1ul << EADC_STATUS2_ADCMPF2_Pos) /*!< EADC_T::STATUS2: ADCMPF2 Mask */ + +#define EADC_STATUS2_ADCMPF3_Pos (7) /*!< EADC_T::STATUS2: ADCMPF3 Position */ +#define EADC_STATUS2_ADCMPF3_Msk (0x1ul << EADC_STATUS2_ADCMPF3_Pos) /*!< EADC_T::STATUS2: ADCMPF3 Mask */ + +#define EADC_STATUS2_ADOVIF0_Pos (8) /*!< EADC_T::STATUS2: ADOVIF0 Position */ +#define EADC_STATUS2_ADOVIF0_Msk (0x1ul << EADC_STATUS2_ADOVIF0_Pos) /*!< EADC_T::STATUS2: ADOVIF0 Mask */ + +#define EADC_STATUS2_ADOVIF1_Pos (9) /*!< EADC_T::STATUS2: ADOVIF1 Position */ +#define EADC_STATUS2_ADOVIF1_Msk (0x1ul << EADC_STATUS2_ADOVIF1_Pos) /*!< EADC_T::STATUS2: ADOVIF1 Mask */ + +#define EADC_STATUS2_ADOVIF2_Pos (10) /*!< EADC_T::STATUS2: ADOVIF2 Position */ +#define EADC_STATUS2_ADOVIF2_Msk (0x1ul << EADC_STATUS2_ADOVIF2_Pos) /*!< EADC_T::STATUS2: ADOVIF2 Mask */ + +#define EADC_STATUS2_ADOVIF3_Pos (11) /*!< EADC_T::STATUS2: ADOVIF3 Position */ +#define EADC_STATUS2_ADOVIF3_Msk (0x1ul << EADC_STATUS2_ADOVIF3_Pos) /*!< EADC_T::STATUS2: ADOVIF3 Mask */ + +#define EADC_STATUS2_ADCMPO0_Pos (12) /*!< EADC_T::STATUS2: ADCMPO0 Position */ +#define EADC_STATUS2_ADCMPO0_Msk (0x1ul << EADC_STATUS2_ADCMPO0_Pos) /*!< EADC_T::STATUS2: ADCMPO0 Mask */ + +#define EADC_STATUS2_ADCMPO1_Pos (13) /*!< EADC_T::STATUS2: ADCMPO1 Position */ +#define EADC_STATUS2_ADCMPO1_Msk (0x1ul << EADC_STATUS2_ADCMPO1_Pos) /*!< EADC_T::STATUS2: ADCMPO1 Mask */ + +#define EADC_STATUS2_ADCMPO2_Pos (14) /*!< EADC_T::STATUS2: ADCMPO2 Position */ +#define EADC_STATUS2_ADCMPO2_Msk (0x1ul << EADC_STATUS2_ADCMPO2_Pos) /*!< EADC_T::STATUS2: ADCMPO2 Mask */ + +#define EADC_STATUS2_ADCMPO3_Pos (15) /*!< EADC_T::STATUS2: ADCMPO3 Position */ +#define EADC_STATUS2_ADCMPO3_Msk (0x1ul << EADC_STATUS2_ADCMPO3_Pos) /*!< EADC_T::STATUS2: ADCMPO3 Mask */ + +#define EADC_STATUS2_CHANNEL_Pos (16) /*!< EADC_T::STATUS2: CHANNEL Position */ +#define EADC_STATUS2_CHANNEL_Msk (0x1ful << EADC_STATUS2_CHANNEL_Pos) /*!< EADC_T::STATUS2: CHANNEL Mask */ + +#define EADC_STATUS2_BUSY_Pos (23) /*!< EADC_T::STATUS2: BUSY Position */ +#define EADC_STATUS2_BUSY_Msk (0x1ul << EADC_STATUS2_BUSY_Pos) /*!< EADC_T::STATUS2: BUSY Mask */ + +#define EADC_STATUS2_ADOVIF_Pos (24) /*!< EADC_T::STATUS2: ADOVIF Position */ +#define EADC_STATUS2_ADOVIF_Msk (0x1ul << EADC_STATUS2_ADOVIF_Pos) /*!< EADC_T::STATUS2: ADOVIF Mask */ + +#define EADC_STATUS2_STOVF_Pos (25) /*!< EADC_T::STATUS2: STOVF Position */ +#define EADC_STATUS2_STOVF_Msk (0x1ul << EADC_STATUS2_STOVF_Pos) /*!< EADC_T::STATUS2: STOVF Mask */ + +#define EADC_STATUS2_AVALID_Pos (26) /*!< EADC_T::STATUS2: AVALID Position */ +#define EADC_STATUS2_AVALID_Msk (0x1ul << EADC_STATUS2_AVALID_Pos) /*!< EADC_T::STATUS2: AVALID Mask */ + +#define EADC_STATUS2_AOV_Pos (27) /*!< EADC_T::STATUS2: AOV Position */ +#define EADC_STATUS2_AOV_Msk (0x1ul << EADC_STATUS2_AOV_Pos) /*!< EADC_T::STATUS2: AOV Mask */ + +#define EADC_STATUS3_CURSPL_Pos (0) /*!< EADC_T::STATUS3: CURSPL Position */ +#define EADC_STATUS3_CURSPL_Msk (0x1ful << EADC_STATUS3_CURSPL_Pos) /*!< EADC_T::STATUS3: CURSPL Mask */ + +#define EADC_MCTL1_ALIGN_Pos (0) /*!< EADC_T::MnCTL1: ALIGN Position */ +#define EADC_MCTL1_ALIGN_Msk (0x1ul << EADC_MCTL1_ALIGN_Pos) /*!< EADC_T::MnCTL1: ALIGN Mask */ + +#define EADC_MCTL1_AVG_Pos (1) /*!< EADC_T::MnCTL1: AVG Position */ +#define EADC_MCTL1_AVG_Msk (0x1ul << EADC_MCTL1_AVG_Pos) /*!< EADC_T::MnCTL1: AVG Mask */ + +#define EADC_MCTL1_ACU_Pos (4) /*!< EADC_T::MnCTL1: ACU Position */ +#define EADC_MCTL1_ACU_Msk (0xful << EADC_MCTL1_ACU_Pos) /*!< EADC_T::MnCTL1: ACU Mask */ + +#define EADC_PWRCTL_READY_Pos (0) /*!< EADC_T::PWRCTL: READY Position */ +#define EADC_PWRCTL_READY_Msk (0x1ul << EADC_PWRCTL_READY_Pos) /*!< EADC_T::PWRCTL: READY Mask */ + +#define EADC_PWRCTL_AUTOFF_Pos (5) /*!< EADC_T::PWRCTL: AUTOFF Position */ +#define EADC_PWRCTL_AUTOFF_Msk (0x1ul << EADC_PWRCTL_AUTOFF_Pos) /*!< EADC_T::PWRCTL: AUTOFF Mask */ + +#define EADC_PWRCTL_STUPT_Pos (8) /*!< EADC_T::PWRCTL: STUPT Position */ +#define EADC_PWRCTL_STUPT_Msk (0xffful << EADC_PWRCTL_STUPT_Pos) /*!< EADC_T::PWRCTL: STUPT Mask */ + +#define EADC_PWRCTL_AUTOPDTHT_Pos (20) /*!< EADC_T::PWRCTL: AUTOPDTHT Position */ +#define EADC_PWRCTL_AUTOPDTHT_Msk (0xful << EADC_PWRCTL_AUTOPDTHT_Pos) /*!< EADC_T::PWRCTL: AUTOPDTHT Mask */ + +#define EADC_PDMACTL_PDMATEN_Pos (0) /*!< EADC_T::PDMACTL: PDMATEN Position */ +#define EADC_PDMACTL_PDMATEN_Msk (0x7fffful << EADC_PDMACTL_PDMATEN_Pos) /*!< EADC_T::PDMACTL: PDMATEN Mask */ + +#define EADC_OFFSETCAL_OFFSETCANCEL_Pos (0) /*!< EADC_T::OFFSETCAL: OFFSETCANCEL Position*/ +#define EADC_OFFSETCAL_OFFSETCANCEL_Msk (0x1ful << EADC_OFFSETCAL_OFFSETCANCEL_Pos) /*!< EADC_T::OFFSETCAL: OFFSETCANCEL Mask */ + +/**@}*/ /* EADC_CONST */ +/**@}*/ /* end of EADC register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __EADC_REG_H__ */ \ No newline at end of file diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/ebi_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/ebi_reg.h new file mode 100644 index 00000000000..07ccca8b9f0 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/ebi_reg.h @@ -0,0 +1,286 @@ +/**************************************************************************//** + * @file ebi_reg.h + * @version V1.00 + * @brief EBI register definition header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EBI_REG_H__ +#define __EBI_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup EBI External Bus Interface Controller (EBI) + Memory Mapped Structure for EBI Controller +@{ */ + +typedef struct +{ + + + /** + * @var EBI_T::CTL0 + * Offset: 0x00 External Bus Interface Bank0 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |EN |EBI Enable Bit + * | | |This bit is the functional enable bit for EBI. + * | | |0 = EBI function Disabled. + * | | |1 = EBI function Enabled. + * |[1] |DW16 |EBI Data Width 16-bit Select + * | | |This bit defines if the EBI data width is 8-bit or 16-bit. + * | | |0 = EBI data width is 8-bit. + * | | |1 = EBI data width is 16-bit. + * |[2] |CSPOLINV |Chip Select Pin Polar Inverse + * | | |This bit defines the active level of EBI chip select pin (EBI_nCS). + * | | |0 = Chip select pin (EBI_nCS) is active low. + * | | |1 = Chip select pin (EBI_nCS) is active high. + * |[4] |CACCESS |Continuous Data Access Mode + * | | |When con tenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request. + * | | |0 = Continuous data access mode Disabled. + * | | |1 = Continuous data access mode Enabled. + * |[10:8] |MCLKDIV |External Output Clock Divider + * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow: + * | | |000 = HCLK/1. + * | | |001 = HCLK/2. + * | | |010 = HCLK/4. + * | | |011 = HCLK/8. + * | | |100 = HCLK/16. + * | | |101 = HCLK/32. + * | | |110 = HCLK/64. + * | | |111 = HCLK/128. + * |[18:16] |TALE |Extend Time of ALE + * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE. + * | | |tALE = (TALE+1)*EBI_MCLK. + * | | |Note: This field only available in EBI_CTL0 register + * |[24] |WBUFEN |EBI Write Buffer Enable Bit + * | | |0 = EBI write buffer Disabled. + * | | |1 = EBI write buffer Enabled. + * | | |Note: This bit only available in EBI_CTL0 register + * @var EBI_T::TCTL0 + * Offset: 0x04 External Bus Interface Bank0 Timing Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:3] |TACC |EBI Data Access Time + * | | |TACC defines data access time (tACC). + * | | |tACC = (TACC +1) * EBI_MCLK. + * |[10:8] |TAHD |EBI Data Access Hold Time + * | | |TAHD defines data access hold time (tAHD). + * | | |tAHD = (TAHD +1) * EBI_MCLK. + * |[15:12] |W2X |Idle Cycle After Write + * | | |This field defines the number of W2X idle cycle. + * | | |W2X idle cycle = (W2X * EBI_MCLK). + * | | |When write action is finished, W2X idle cycle is inserted and EBI_nCS return to idle state. + * |[22] |RAHDOFF |Access Hold Time Disable Control When Read + * | | |0 = Data Access Hold Time (tAHD) during EBI reading Enabled. + * | | |1 = Data Access Hold Time (tAHD) during EBI reading Disabled. + * |[23] |WAHDOFF |Access Hold Time Disable Control When Write + * | | |0 = Data Access Hold Time (tAHD) during EBI writing Enabled. + * | | |1 = Data Access Hold Time (tAHD) during EBI writing Disabled. + * |[27:24] |R2R |Idle Cycle Between Read-to-read + * | | |This field defines the number of R2R idle cycle. + * | | |R2R idle cycle = (R2R * EBI_MCLK). + * | | |When read action is finished and the next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state. + * @var EBI_T::CTL1 + * Offset: 0x10 External Bus Interface Bank1 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |EN |EBI Enable Bit + * | | |This bit is the functional enable bit for EBI. + * | | |0 = EBI function Disabled. + * | | |1 = EBI function Enabled. + * |[1] |DW16 |EBI Data Width 16-bit Select + * | | |This bit defines if the EBI data width is 8-bit or 16-bit. + * | | |0 = EBI data width is 8-bit. + * | | |1 = EBI data width is 16-bit. + * |[2] |CSPOLINV |Chip Select Pin Polar Inverse + * | | |This bit defines the active level of EBI chip select pin (EBI_nCS). + * | | |0 = Chip select pin (EBI_nCS) is active low. + * | | |1 = Chip select pin (EBI_nCS) is active high. + * |[4] |CACCESS |Continuous Data Access Mode + * | | |When con tenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request. + * | | |0 = Continuous data access mode Disabled. + * | | |1 = Continuous data access mode Enabled. + * |[10:8] |MCLKDIV |External Output Clock Divider + * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow: + * | | |000 = HCLK/1. + * | | |001 = HCLK/2. + * | | |010 = HCLK/4. + * | | |011 = HCLK/8. + * | | |100 = HCLK/16. + * | | |101 = HCLK/32. + * | | |110 = HCLK/64. + * | | |111 = HCLK/128. + * |[18:16] |TALE |Extend Time of ALE + * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE. + * | | |tALE = (TALE+1)*EBI_MCLK. + * | | |Note: This field only available in EBI_CTL0 register + * |[24] |WBUFEN |EBI Write Buffer Enable Bit + * | | |0 = EBI write buffer Disabled. + * | | |1 = EBI write buffer Enabled. + * | | |Note: This bit only available in EBI_CTL0 register + * @var EBI_T::TCTL1 + * Offset: 0x14 External Bus Interface Bank1 Timing Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:3] |TACC |EBI Data Access Time + * | | |TACC defines data access time (tACC). + * | | |tACC = (TACC +1) * EBI_MCLK. + * |[10:8] |TAHD |EBI Data Access Hold Time + * | | |TAHD defines data access hold time (tAHD). + * | | |tAHD = (TAHD +1) * EBI_MCLK. + * |[15:12] |W2X |Idle Cycle After Write + * | | |This field defines the number of W2X idle cycle. + * | | |W2X idle cycle = (W2X * EBI_MCLK). + * | | |When write action is finished, W2X idle cycle is inserted and EBI_nCS return to idle state. + * |[22] |RAHDOFF |Access Hold Time Disable Control When Read + * | | |0 = Data Access Hold Time (tAHD) during EBI reading Enabled. + * | | |1 = Data Access Hold Time (tAHD) during EBI reading Disabled. + * |[23] |WAHDOFF |Access Hold Time Disable Control When Write + * | | |0 = Data Access Hold Time (tAHD) during EBI writing Enabled. + * | | |1 = Data Access Hold Time (tAHD) during EBI writing Disabled. + * |[27:24] |R2R |Idle Cycle Between Read-to-read + * | | |This field defines the number of R2R idle cycle. + * | | |R2R idle cycle = (R2R * EBI_MCLK). + * | | |When read action is finished and the next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state. + * @var EBI_T::CTL2 + * Offset: 0x20 External Bus Interface Bank2 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |EN |EBI Enable Bit + * | | |This bit is the functional enable bit for EBI. + * | | |0 = EBI function Disabled. + * | | |1 = EBI function Enabled. + * |[1] |DW16 |EBI Data Width 16-bit Select + * | | |This bit defines if the EBI data width is 8-bit or 16-bit. + * | | |0 = EBI data width is 8-bit. + * | | |1 = EBI data width is 16-bit. + * |[2] |CSPOLINV |Chip Select Pin Polar Inverse + * | | |This bit defines the active level of EBI chip select pin (EBI_nCS). + * | | |0 = Chip select pin (EBI_nCS) is active low. + * | | |1 = Chip select pin (EBI_nCS) is active high. + * |[4] |CACCESS |Continuous Data Access Mode + * | | |When con tenuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request. + * | | |0 = Continuous data access mode Disabled. + * | | |1 = Continuous data access mode Enabled. + * |[10:8] |MCLKDIV |External Output Clock Divider + * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow: + * | | |000 = HCLK/1. + * | | |001 = HCLK/2. + * | | |010 = HCLK/4. + * | | |011 = HCLK/8. + * | | |100 = HCLK/16. + * | | |101 = HCLK/32. + * | | |110 = HCLK/64. + * | | |111 = HCLK/128. + * |[18:16] |TALE |Extend Time of ALE + * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE. + * | | |tALE = (TALE+1)*EBI_MCLK. + * | | |Note: This field only available in EBI_CTL0 register + * |[24] |WBUFEN |EBI Write Buffer Enable Bit + * | | |0 = EBI write buffer Disabled. + * | | |1 = EBI write buffer Enabled. + * | | |Note: This bit only available in EBI_CTL0 register + * @var EBI_T::TCTL2 + * Offset: 0x24 External Bus Interface Bank2 Timing Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:3] |TACC |EBI Data Access Time + * | | |TACC defines data access time (tACC). + * | | |tACC = (TACC +1) * EBI_MCLK. + * |[10:8] |TAHD |EBI Data Access Hold Time + * | | |TAHD defines data access hold time (tAHD). + * | | |tAHD = (TAHD +1) * EBI_MCLK. + * |[15:12] |W2X |Idle Cycle After Write + * | | |This field defines the number of W2X idle cycle. + * | | |W2X idle cycle = (W2X * EBI_MCLK). + * | | |When write action is finished, W2X idle cycle is inserted and EBI_nCS return to idle state. + * |[22] |RAHDOFF |Access Hold Time Disable Control When Read + * | | |0 = Data Access Hold Time (tAHD) during EBI reading Enabled. + * | | |1 = Data Access Hold Time (tAHD) during EBI reading Disabled. + * |[23] |WAHDOFF |Access Hold Time Disable Control When Write + * | | |0 = Data Access Hold Time (tAHD) during EBI writing Enabled. + * | | |1 = Data Access Hold Time (tAHD) during EBI writing Disabled. + * |[27:24] |R2R |Idle Cycle Between Read-to-read + * | | |This field defines the number of R2R idle cycle. + * | | |R2R idle cycle = (R2R * EBI_MCLK). + * | | |When read action is finished and the next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state. + */ + __IO uint32_t CTL0; /*!< [0x0000] External Bus Interface Bank0 Control Register */ + __IO uint32_t TCTL0; /*!< [0x0004] External Bus Interface Bank0 Timing Control Register */ + __I uint32_t RESERVE0[2]; + __IO uint32_t CTL1; /*!< [0x0010] External Bus Interface Bank1 Control Register */ + __IO uint32_t TCTL1; /*!< [0x0014] External Bus Interface Bank1 Timing Control Register */ + __I uint32_t RESERVE1[2]; + __IO uint32_t CTL2; /*!< [0x0020] External Bus Interface Bank2 Control Register */ + __IO uint32_t TCTL2; /*!< [0x0024] External Bus Interface Bank2 Timing Control Register */ + +} EBI_T; + +/** + @addtogroup EBI_CONST EBI Bit Field Definition + Constant Definitions for EBI Controller +@{ */ + +#define EBI_CTL_EN_Pos (0) /*!< EBI_T::CTL: EN Position */ +#define EBI_CTL_EN_Msk (0x1ul << EBI_CTL_EN_Pos) /*!< EBI_T::CTL: EN Mask */ + +#define EBI_CTL_DW16_Pos (1) /*!< EBI_T::CTL: DW16 Position */ +#define EBI_CTL_DW16_Msk (0x1ul << EBI_CTL_DW16_Pos) /*!< EBI_T::CTL: DW16 Mask */ + +#define EBI_CTL_CSPOLINV_Pos (2) /*!< EBI_T::CTL: CSPOLINV Position */ +#define EBI_CTL_CSPOLINV_Msk (0x1ul << EBI_CTL_CSPOLINV_Pos) /*!< EBI_T::CTL: CSPOLINV Mask */ + +#define EBI_CTL_CACCESS_Pos (4) /*!< EBI_T::CTL: CACCESS Position */ +#define EBI_CTL_CACCESS_Msk (0x1ul << EBI_CTL_CACCESS_Pos) /*!< EBI_T::CTL: CACCESS Mask */ + +#define EBI_CTL_MCLKDIV_Pos (8) /*!< EBI_T::CTL: MCLKDIV Position */ +#define EBI_CTL_MCLKDIV_Msk (0x7ul << EBI_CTL_MCLKDIV_Pos) /*!< EBI_T::CTL: MCLKDIV Mask */ + +#define EBI_CTL_TALE_Pos (16) /*!< EBI_T::CTL: TALE Position */ +#define EBI_CTL_TALE_Msk (0x7ul << EBI_CTL_TALE_Pos) /*!< EBI_T::CTL: TALE Mask */ + +#define EBI_CTL_WBUFEN_Pos (24) /*!< EBI_T::CTL: WBUFEN Position */ +#define EBI_CTL_WBUFEN_Msk (0x1ul << EBI_CTL_WBUFEN_Pos) /*!< EBI_T::CTL: WBUFEN Mask */ + +#define EBI_TCTL_TACC_Pos (3) /*!< EBI_T::TCTL: TACC Position */ +#define EBI_TCTL_TACC_Msk (0x1ful << EBI_TCTL_TACC_Pos) /*!< EBI_T::TCTL: TACC Mask */ + +#define EBI_TCTL_TAHD_Pos (8) /*!< EBI_T::TCTL: TAHD Position */ +#define EBI_TCTL_TAHD_Msk (0x7ul << EBI_TCTL_TAHD_Pos) /*!< EBI_T::TCTL: TAHD Mask */ + +#define EBI_TCTL_W2X_Pos (12) /*!< EBI_T::TCTL: W2X Position */ +#define EBI_TCTL_W2X_Msk (0xful << EBI_TCTL_W2X_Pos) /*!< EBI_T::TCTL: W2X Mask */ + +#define EBI_TCTL_RAHDOFF_Pos (22) /*!< EBI_T::TCTL: RAHDOFF Position */ +#define EBI_TCTL_RAHDOFF_Msk (0x1ul << EBI_TCTL_RAHDOFF_Pos) /*!< EBI_T::TCTL: RAHDOFF Mask */ + +#define EBI_TCTL_WAHDOFF_Pos (23) /*!< EBI_T::TCTL: WAHDOFF Position */ +#define EBI_TCTL_WAHDOFF_Msk (0x1ul << EBI_TCTL_WAHDOFF_Pos) /*!< EBI_T::TCTL: WAHDOFF Mask */ + +#define EBI_TCTL_R2R_Pos (24) /*!< EBI_T::TCTL: R2R Position */ +#define EBI_TCTL_R2R_Msk (0xful << EBI_TCTL_R2R_Pos) /*!< EBI_T::TCTL: R2R Mask */ + +/**@}*/ /* EBI_CONST */ +/**@}*/ /* end of EBI register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __EBI_REG_H__ */ \ No newline at end of file diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/fmc_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/fmc_reg.h new file mode 100644 index 00000000000..9c3448510ef --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/fmc_reg.h @@ -0,0 +1,434 @@ +/**************************************************************************//** + * @file fmc_reg.h + * @version V1.00 + * @brief FMC register definition header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __FMC_REG_H__ +#define __FMC_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup FMC Flash Memory Controller (FMC) + Memory Mapped Structure for FMC Controller +@{ */ + +typedef struct +{ + + + /** + * @var FMC_T::ISPCTL + * Offset: 0x00 ISP Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ISPEN |ISP Enable Bit (Write Protect) + * | | |ISP function enable bit. Set this bit to enable ISP function. + * | | |0 = ISP function Disabled. + * | | |1 = ISP function Enabled. + * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register. + * |[1] |BS |Boot Select (Write Protect) + * | | |Set/clear this bit to select next booting from LDROM/APROM, respectively + * | | |This bit also functions as chip booting status flag, which can be used to check where chip booted from + * | | |This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened + * | | |0 = Booting from APROM. + * | | |1 = Booting from LDROM. + * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register. + * |[3] |APUEN |APROM Update Enable Bit (Write Protect) + * | | |0 = APROM cannot be updated when the chip runs in APROM. + * | | |1 = APROM can be updated when the chip runs in APROM. + * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register. + * |[4] |CFGUEN |CONFIG Update Enable Bit (Write Protect) + * | | |0 = CONFIG cannot be updated. + * | | |1 = CONFIG can be updated. + * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register. + * |[5] |LDUEN |LDROM Update Enable Bit (Write Protect) + * | | |LDROM update enable bit. + * | | |0 = LDROM cannot be updated. + * | | |1 = LDROM can be updated. + * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register. + * |[6] |ISPFF |ISP Fail Flag (Write Protect) + * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: + * | | |This bit needs to be cleared by writing 1 to it. + * | | |(1) APROM writes to itself if APUEN is set to 0. + * | | |(2) LDROM writes to itself if LDUEN is set to 0. + * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0. + * | | |(4) Page Erase command at LOCK mode with ICE connection + * | | |(5) Erase or Program command at brown-out detected + * | | |(6) Destination address is illegal, such as over an available range. + * | | |(7) Invalid ISP commands + * | | |(8) ISP CMD in XOM region, except mass erase, page erase and chksum command + * | | |(9) The wrong setting of page erase ISP CMD in XOM + * | | |(10) Violate XOM setting one time protection + * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register. + * @var FMC_T::ISPADDR + * Offset: 0x04 ISP Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPADDR |ISP Address + * | | |For Checksum Calculation command, this field is the Flash starting address for checksum calculation, 512 bytes alignment is necessary for checksum calculation. + * @var FMC_T::ISPDAT + * Offset: 0x08 ISP Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPDAT |ISP Data + * | | |Write data to this register before ISP program operation. + * | | |Read data from this register after ISP read operation. + * | | |For Run Checksum Calculation command, ISPDAT is the memory size (byte) and 512 bytes alignment + * | | |For ISP Read Checksum command, ISPDAT is the checksum result + * | | |If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, (2) the memory range for checksum calculation is incorrect. + * @var FMC_T::ISPCMD + * Offset: 0x0C ISP CMD Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |CMD |ISP CMD + * | | |ISP command table is shown below: + * | | |0x00= FLASH Read. + * | | |0x04= Read Unique ID. + * | | |0x0B= Read Company ID. + * | | |0x0C= Read Device ID. + * | | |0x0D= Read Checksum. + * | | |0x21= FLASH 32-bit Program. + * | | |0x22= FLASH Page Erase. + * | | |0x27= FLASH Multi-Word Program. + * | | |0x28= Run Flash All-One Verification. + * | | |0x2D= Run Checksum Calculation. + * | | |0x2E= Vector Remap. + * | | |The other commands are invalid. + * @var FMC_T::ISPTRG + * Offset: 0x10 ISP Trigger Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ISPGO |ISP Start Trigger (Write Protect) + * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. + * | | |0 = ISP operation is finished. + * | | |1 = ISP is progressed. + * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register. + * @var FMC_T::FTCTL + * Offset: 0x18 Flash Access Time Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9] |CACHEINV |Flash Cache Invalidation (Write Protect) + * | | |Write 1 to start cache invalidation. The value will be change to 0 once the process finishes. + * | | |0 = Flash Cache Invalidation.(default) + * | | |1 = Flash Cache Invalidation. + * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register. + * @var FMC_T::ISPSTS + * Offset: 0x40 ISP Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ISPBUSY |ISP Busy Flag (Read Only) + * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. + * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]). + * | | |0 = ISP operation is finished. + * | | |1 = ISP is progressed. + * |[2:1] |CBS |Boot Selection of CONFIG (Read Only) + * | | |This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened. + * | | |00 = LDROM with IAP mode. + * | | |01 = LDROM without IAP mode. + * | | |10 = APROM with IAP mode. + * | | |11 = APROM without IAP mode. + * |[5] |PGFF |Flash Program with Fast Verification Flag (Read Only) + * | | |This bit is set if data is mismatched at ISP programming verification + * | | |This bit is clear by performing ISP Flash erase or ISP read CID operation + * | | |0 = Flash Program is success. + * | | |1 = Flash Program is fail. Program data is different with data in the Flash memory + * |[6] |ISPFF |ISP Fail Flag (Write Protect) + * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6] + * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: + * | | |(1) APROM writes to itself if APUEN is set to 0. + * | | |(2) LDROM writes to itself if LDUEN is set to 0. + * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0. + * | | |(4) Page Erase command at LOCK mode with ICE connection + * | | |(5) Erase or Program command at brown-out detected + * | | |(6) Destination address is illegal, such as over an available range. + * | | |(7) Invalid ISP commands + * | | |(8) ISP CMD in XOM region, except mass erase, page erase and chksum command + * | | |(9) The wrong setting of page erase ISP CMD in XOM + * | | |(10) Violate XOM setting one time protection + * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register. + * |[7] |ALLONE |Flash All-one Verification Flag + * | | |This bit is set by hardware if all of Flash bits are 1, and clear if Flash bits are not all 1 after "Run Flash All-One Verification" complete; this bit also can be clear by writing 1 + * | | |0 = Flash bits are not all 1 after "Run Flash All-One Verification" complete. + * | | |1 = All of Flash bits are 1 after "Run Flash All-One Verification" complete. + * |[29:9] |VECMAP |Vector Page Mapping Address (Read Only) + * | | |All access to 0x0000_0000~0x0000_01FF is remapped to the Flash memory or SRAM address {VECMAP[20:0], 9'h000} ~ {VECMAP[20:0], 9'h1FF}. + * | | |VECMAP [20:19] = 00 system vector address is mapped to Flash memory. + * | | |VECMAP [20:19] = 10 system vector address is mapped to SRAM memory. + * | | |VECMAP [18:12] should be 0. + * @var FMC_T::CYCCTL + * Offset: 0x4C Flash Access Cycle Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |CYCLE |Flash Access Cycle Control (Write Protect) + * | | |This register is updated automaticly by hardware while FCYCDIS (FMC_ISPSTS[4]) is 0, and updated by software while auto-tuning function disabled ( FADIS (FMC_CYCTL[8]) is 1) + * | | |0001 = CPU access with zero wait cycle ; Flash access cycle is 1;. + * | | |The HCLK working frequency range is <19MHz; Cache is disabled by hardware. + * | | |0010 = CPU access with one wait cycles if cache miss; Flash access cycle is 2;. + * | | | The optimized HCLK working frequency range is 18~33 MHz + * | | |0011 = CPU access with two wait cycles if cahce miss; Flash access cycle is 3;. + * | | | The optimized HCLK working frequency range is 33~50 MHz + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var FMC_T::MPDAT0 + * Offset: 0x80 ISP Data0 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPDAT0 |ISP Data 0 + * | | |This register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data + * @var FMC_T::MPDAT1 + * Offset: 0x84 ISP Data1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPDAT1 |ISP Data 1 + * | | |This register is the second 32-bit data for 64-bit/multi-word programming. + * @var FMC_T::MPDAT2 + * Offset: 0x88 ISP Data2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPDAT2 |ISP Data 2 + * | | |This register is the third 32-bit data for multi-word programming. + * @var FMC_T::MPDAT3 + * Offset: 0x8C ISP Data3 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPDAT3 |ISP Data 3 + * | | |This register is the fourth 32-bit data for multi-word programming. + * @var FMC_T::MPSTS + * Offset: 0xC0 ISP Multi-program Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MPBUSY |ISP Multi-word Program Busy Flag (Read Only) + * | | |Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished. + * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]). + * | | |0 = ISP Multi-Word program operation is finished. + * | | |1 = ISP Multi-Word program operation is progressed. + * |[1] |PPGO |ISP Multi-program Status (Read Only) + * | | |0 = ISP multi-word program operation is not active. + * | | |1 = ISP multi-word program operation is in progress. + * |[2] |ISPFF |ISP Fail Flag (Read Only) + * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6] + * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: + * | | |(1) APROM writes to itself if APUEN is set to 0. + * | | |(2) LDROM writes to itself if LDUEN is set to 0. + * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0. + * | | |(4) Page Erase command at LOCK mode with ICE connection + * | | |(5) Erase or Program command at brown-out detected + * | | |(6) Destination address is illegal, such as over an available range. + * | | |(7) Invalid ISP commands + * |[4] |D0 |ISP DATA 0 Flag (Read Only) + * | | |This bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to Flash complete. + * | | |0 = FMC_MPDAT0 register is empty, or program to Flash complete. + * | | |1 = FMC_MPDAT0 register has been written, and not program to Flash complete. + * |[5] |D1 |ISP DATA 1 Flag (Read Only) + * | | |This bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to Flash complete. + * | | |0 = FMC_MPDAT1 register is empty, or program to Flash complete. + * | | |1 = FMC_MPDAT1 register has been written, and not program to Flash complete. + * |[6] |D2 |ISP DATA 2 Flag (Read Only) + * | | |This bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to Flash complete. + * | | |0 = FMC_MPDAT2 register is empty, or program to Flash complete. + * | | |1 = FMC_MPDAT2 register has been written, and not program to Flash complete. + * |[7] |D3 |ISP DATA 3 Flag (Read Only) + * | | |This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to Flash complete. + * | | |0 = FMC_MPDAT3 register is empty, or program to Flash complete. + * | | |1 = FMC_MPDAT3 register has been written, and not program to Flash complete. + * @var FMC_T::MPADDR + * Offset: 0xC4 ISP Multi-program Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |MPADDR |ISP Multi-word Program Address + * | | |MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1. + * | | |MPADDR will keep the final ISP address when ISP multi-word program is complete. + * @var FMC_T::XOMR0STS0 + * Offset: 0xD0 XOM Region 0 Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |BASE |XOM Region 0 Base Address (Page-aligned) + * | | |BASE is the base address of XOM Region 0. + * @var FMC_T::XOMR0STS1 + * Offset: 0xD4 XOM Region 0 Status Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |SIZE |XOM Region 0 Size (Page-aligned) + * | | |SIZE is the page number of XOM Region 0. + * @var FMC_T::XOMSTS + * Offset: 0xE0 XOM Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |XOMR0ON |XOM Region 0 On + * | | |XOM Region 0 active status. + * | | |0 = No active. + * | | |1 = XOM region 0 is active. + * |[4] |XOMPEF |XOM Page Erase Function Fail + * | | |XOM page erase function status. If XOMPEF is set to 1, user needs to erase XOM region again. + * | | |0 = Sucess. + * | | |1 = Fail. + */ + __IO uint32_t ISPCTL; /*!< [0x0000] ISP Control Register */ + __IO uint32_t ISPADDR; /*!< [0x0004] ISP Address Register */ + __IO uint32_t ISPDAT; /*!< [0x0008] ISP Data Register */ + __IO uint32_t ISPCMD; /*!< [0x000c] ISP CMD Register */ + __IO uint32_t ISPTRG; /*!< [0x0010] ISP Trigger Control Register */ + __I uint32_t RESERVE0; + __IO uint32_t FTCTL; /*!< [0x0018] Flash Access Time Control Register */ + __I uint32_t RESERVE1[9]; + __IO uint32_t ISPSTS; /*!< [0x0040] ISP Status Register */ + __I uint32_t RESERVE2[2]; + __IO uint32_t CYCCTL; /*!< [0x004c] Flash Access Cycle Control Register */ + __I uint32_t RESERVE3[12]; + __IO uint32_t MPDAT0; /*!< [0x0080] ISP Data0 Register */ + __IO uint32_t MPDAT1; /*!< [0x0084] ISP Data1 Register */ + __IO uint32_t MPDAT2; /*!< [0x0088] ISP Data2 Register */ + __IO uint32_t MPDAT3; /*!< [0x008c] ISP Data3 Register */ + __I uint32_t RESERVE4[12]; + __I uint32_t MPSTS; /*!< [0x00c0] ISP Multi-program Status Register */ + __I uint32_t MPADDR; /*!< [0x00c4] ISP Multi-program Address Register */ + __I uint32_t RESERVE5[2]; + __I uint32_t XOMR0STS0; /*!< [0x00d0] XOM Region 0 Status Register 0 */ + __I uint32_t XOMR0STS1; /*!< [0x00d4] XOM Region 0 Status Register 1 */ + __I uint32_t RESERVE6[2]; + __I uint32_t XOMSTS; /*!< [0x00e0] XOM Status Register */ + +} FMC_T; + +/** + @addtogroup FMC_CONST FMC Bit Field Definition + Constant Definitions for FMC Controller +@{ */ + +#define FMC_ISPCTL_ISPEN_Pos (0) /*!< FMC_T::ISPCTL: ISPEN Position */ +#define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos) /*!< FMC_T::ISPCTL: ISPEN Mask */ + +#define FMC_ISPCTL_BS_Pos (1) /*!< FMC_T::ISPCTL: BS Position */ +#define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos) /*!< FMC_T::ISPCTL: BS Mask */ + +#define FMC_ISPCTL_APUEN_Pos (3) /*!< FMC_T::ISPCTL: APUEN Position */ +#define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos) /*!< FMC_T::ISPCTL: APUEN Mask */ + +#define FMC_ISPCTL_CFGUEN_Pos (4) /*!< FMC_T::ISPCTL: CFGUEN Position */ +#define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos) /*!< FMC_T::ISPCTL: CFGUEN Mask */ + +#define FMC_ISPCTL_LDUEN_Pos (5) /*!< FMC_T::ISPCTL: LDUEN Position */ +#define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos) /*!< FMC_T::ISPCTL: LDUEN Mask */ + +#define FMC_ISPCTL_ISPFF_Pos (6) /*!< FMC_T::ISPCTL: ISPFF Position */ +#define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos) /*!< FMC_T::ISPCTL: ISPFF Mask */ + +#define FMC_ISPADDR_ISPADDR_Pos (0) /*!< FMC_T::ISPADDR: ISPADDR Position */ +#define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos) /*!< FMC_T::ISPADDR: ISPADDR Mask */ + +#define FMC_ISPDAT_ISPDAT_Pos (0) /*!< FMC_T::ISPDAT: ISPDAT Position */ +#define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) /*!< FMC_T::ISPDAT: ISPDAT Mask */ + +#define FMC_ISPCMD_CMD_Pos (0) /*!< FMC_T::ISPCMD: CMD Position */ +#define FMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos) /*!< FMC_T::ISPCMD: CMD Mask */ + +#define FMC_ISPTRG_ISPGO_Pos (0) /*!< FMC_T::ISPTRG: ISPGO Position */ +#define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) /*!< FMC_T::ISPTRG: ISPGO Mask */ + +#define FMC_FTCTL_CACHEINV_Pos (9) /*!< FMC_T::FTCTL: CACHEINV Position */ +#define FMC_FTCTL_CACHEINV_Msk (0x1ul << FMC_FTCTL_CACHEINV_Pos) /*!< FMC_T::FTCTL: CACHEINV Mask */ + +#define FMC_ISPSTS_ISPBUSY_Pos (0) /*!< FMC_T::ISPSTS: ISPBUSY Position */ +#define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos) /*!< FMC_T::ISPSTS: ISPBUSY Mask */ + +#define FMC_ISPSTS_CBS_Pos (1) /*!< FMC_T::ISPSTS: CBS Position */ +#define FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos) /*!< FMC_T::ISPSTS: CBS Mask */ + +#define FMC_ISPSTS_PGFF_Pos (5) /*!< FMC_T::ISPSTS: PGFF Position */ +#define FMC_ISPSTS_PGFF_Msk (0x1ul << FMC_ISPSTS_PGFF_Pos) /*!< FMC_T::ISPSTS: PGFF Mask */ + +#define FMC_ISPSTS_ISPFF_Pos (6) /*!< FMC_T::ISPSTS: ISPFF Position */ +#define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos) /*!< FMC_T::ISPSTS: ISPFF Mask */ + +#define FMC_ISPSTS_ALLONE_Pos (7) /*!< FMC_T::ISPSTS: ALLONE Position */ +#define FMC_ISPSTS_ALLONE_Msk (0x1ul << FMC_ISPSTS_ALLONE_Pos) /*!< FMC_T::ISPSTS: ALLONE Mask */ + +#define FMC_ISPSTS_VECMAP_Pos (9) /*!< FMC_T::ISPSTS: VECMAP Position */ +#define FMC_ISPSTS_VECMAP_Msk (0x1ffffful << FMC_ISPSTS_VECMAP_Pos) /*!< FMC_T::ISPSTS: VECMAP Mask */ + +#define FMC_CYCCTL_CYCLE_Pos (0) /*!< FMC_T::CYCCTL: CYCLE Position */ +#define FMC_CYCCTL_CYCLE_Msk (0xful << FMC_CYCCTL_CYCLE_Pos) /*!< FMC_T::CYCCTL: CYCLE Mask */ + +#define FMC_MPDAT0_ISPDAT0_Pos (0) /*!< FMC_T::MPDAT0: ISPDAT0 Position */ +#define FMC_MPDAT0_ISPDAT0_Msk (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos) /*!< FMC_T::MPDAT0: ISPDAT0 Mask */ + +#define FMC_MPDAT1_ISPDAT1_Pos (0) /*!< FMC_T::MPDAT1: ISPDAT1 Position */ +#define FMC_MPDAT1_ISPDAT1_Msk (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos) /*!< FMC_T::MPDAT1: ISPDAT1 Mask */ + +#define FMC_MPDAT2_ISPDAT2_Pos (0) /*!< FMC_T::MPDAT2: ISPDAT2 Position */ +#define FMC_MPDAT2_ISPDAT2_Msk (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos) /*!< FMC_T::MPDAT2: ISPDAT2 Mask */ + +#define FMC_MPDAT3_ISPDAT3_Pos (0) /*!< FMC_T::MPDAT3: ISPDAT3 Position */ +#define FMC_MPDAT3_ISPDAT3_Msk (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos) /*!< FMC_T::MPDAT3: ISPDAT3 Mask */ + +#define FMC_MPSTS_MPBUSY_Pos (0) /*!< FMC_T::MPSTS: MPBUSY Position */ +#define FMC_MPSTS_MPBUSY_Msk (0x1ul << FMC_MPSTS_MPBUSY_Pos) /*!< FMC_T::MPSTS: MPBUSY Mask */ + +#define FMC_MPSTS_PPGO_Pos (1) /*!< FMC_T::MPSTS: PPGO Position */ +#define FMC_MPSTS_PPGO_Msk (0x1ul << FMC_MPSTS_PPGO_Pos) /*!< FMC_T::MPSTS: PPGO Mask */ + +#define FMC_MPSTS_ISPFF_Pos (2) /*!< FMC_T::MPSTS: ISPFF Position */ +#define FMC_MPSTS_ISPFF_Msk (0x1ul << FMC_MPSTS_ISPFF_Pos) /*!< FMC_T::MPSTS: ISPFF Mask */ + +#define FMC_MPSTS_D0_Pos (4) /*!< FMC_T::MPSTS: D0 Position */ +#define FMC_MPSTS_D0_Msk (0x1ul << FMC_MPSTS_D0_Pos) /*!< FMC_T::MPSTS: D0 Mask */ + +#define FMC_MPSTS_D1_Pos (5) /*!< FMC_T::MPSTS: D1 Position */ +#define FMC_MPSTS_D1_Msk (0x1ul << FMC_MPSTS_D1_Pos) /*!< FMC_T::MPSTS: D1 Mask */ + +#define FMC_MPSTS_D2_Pos (6) /*!< FMC_T::MPSTS: D2 Position */ +#define FMC_MPSTS_D2_Msk (0x1ul << FMC_MPSTS_D2_Pos) /*!< FMC_T::MPSTS: D2 Mask */ + +#define FMC_MPSTS_D3_Pos (7) /*!< FMC_T::MPSTS: D3 Position */ +#define FMC_MPSTS_D3_Msk (0x1ul << FMC_MPSTS_D3_Pos) /*!< FMC_T::MPSTS: D3 Mask */ + +#define FMC_MPADDR_MPADDR_Pos (0) /*!< FMC_T::MPADDR: MPADDR Position */ +#define FMC_MPADDR_MPADDR_Msk (0xfffffffful << FMC_MPADDR_MPADDR_Pos) /*!< FMC_T::MPADDR: MPADDR Mask */ + +#define FMC_XOMR0STS0_BASE_Pos (0) /*!< FMC_T::XOMR0STS0: BASE Position */ +#define FMC_XOMR0STS0_BASE_Msk (0xfffffful << FMC_XOMR0STS0_BASE_Pos) /*!< FMC_T::XOMR0STS0: BASE Mask */ + +#define FMC_XOMR0STS1_SIZE_Pos (0) /*!< FMC_T::XOMR0STS1: SIZE Position */ +#define FMC_XOMR0STS1_SIZE_Msk (0x1fful << FMC_XOMR0STS1_SIZE_Pos) /*!< FMC_T::XOMR0STS1: SIZE Mask */ + +#define FMC_XOMSTS_XOMR0ON_Pos (0) /*!< FMC_T::XOMSTS: XOMR0ON Position */ +#define FMC_XOMSTS_XOMR0ON_Msk (0x1ul << FMC_XOMSTS_XOMR0ON_Pos) /*!< FMC_T::XOMSTS: XOMR0ON Mask */ + +#define FMC_XOMSTS_XOMPEF_Pos (4) /*!< FMC_T::XOMSTS: XOMPEF Position */ +#define FMC_XOMSTS_XOMPEF_Msk (0x1ul << FMC_XOMSTS_XOMPEF_Pos) /*!< FMC_T::XOMSTS: XOMPEF Mask */ + +/**@}*/ /* FMC_CONST */ +/**@}*/ /* end of FMC register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __FMC_REG_H__ */ \ No newline at end of file diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/gpio_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/gpio_reg.h new file mode 100644 index 00000000000..eb25013b627 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/gpio_reg.h @@ -0,0 +1,927 @@ +/**************************************************************************//** + * @file gpio_reg.h + * @version V1.00 + * @brief GPIO register definition header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __GPIO_REG_H__ +#define __GPIO_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup GPIO General Purpose Input/Output Controller (GPIO) + Memory Mapped Structure for GPIO Controller +@{ */ + +typedef struct +{ + + + /** + * @var GPIO_T::MODE + * Offset: 0x00/0x40/0x80/0xC0/0x100/0x140 Port A-F I/O Mode Control + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2n+1:2n]|MODEn |Port A-F I/O Pin[n] Mode Control + * | | |Determine each I/O mode of Px.n pins. + * | | |00 = Px.n is in Input mode. + * | | |01 = Px.n is in Push-pull Output mode. + * | | |10 = Px.n is in Open-drain Output mode. + * | | |11 = Px.n is in Quasi-bidirectional mode. + * | | |Note1: The initial value of this field is defined by CIOINI (CONFIG0 [10]) + * | | |If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on + * | | |If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. + * | | |Note2: The PC.13/PC.15/PD.14/PF.8~15 pin is ignored. + * | | | + * @var GPIO_T::DINOFF + * Offset: 0x04/0x44/0x84/0xC4/0x104/0x144 Port A-F Digital Input Path Disable Control + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n+16] |DINOFFn |Port A-F Pin[n] Digital Input Path Disable Bit + * | | |Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled + * | | |If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. + * | | |0 = Px.n digital input path Enabled. + * | | |1 = Px.n digital input path Disabled (digital input tied to low). + * | | |Note: The PC.13/PC.15/PD.14/PF.8~15 pin is ignored. + * | | | + * @var GPIO_T::DOUT + * Offset: 0x08/0x48/0x88/0xC8/0x108/0x148 Port A-F Data Output Value + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |DOUTn |Port A-F Pin[n] Output Value + * | | |Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. + * | | |0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. + * | | |1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode. + * | | |Note: The PC.13/PC.15/PD.14/PF.8~15 pin is ignored. + * | | | + * @var GPIO_T::DATMSK + * Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C Port A-F Data Output Write Mask + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |DATMSKn |Port A-F Pin[n] Data Output Write Mask + * | | |These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit + * | | |When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected + * | | |If the write signal is masked, writing data to the protect bit is ignored. + * | | |0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. + * | | |1 = Corresponding DOUT (Px_DOUT[n]) bit protected. + * | | |Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. + * | | |Note2: The PC.13/PC.15/PD.14/PF.8~15 pin is ignored. + * | | | + * @var GPIO_T::PIN + * Offset: 0x10/0x50/0x90/0xD0/0x110/0x150 Port A-H Pin Value + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |PINn |Port A-F Pin[n] Pin Value + * | | |Each bit of the register reflects the actual status of the respective Px.n pin + * | | |If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. + * | | |Note: The PC.13/PC.15/PD.14/PF.8~15 pin is ignored. + * | | | + * @var GPIO_T::DBEN + * Offset: 0x14/0x54/0x94/0xD4/0x114/0x154 Port A-F De-Bounce Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |DBENn |Port A-F Pin[n] Input Signal De-bounce Enable Bit + * | | |The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit + * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt + * | | |The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]). + * | | |0 = Px.n de-bounce function Disabled. + * | | |1 = Px.n de-bounce function Enabled. + * | | |The de-bounce function is valid only for edge triggered interrupt + * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored. + * | | |Note: The PC.13/PC.15/PD.14/PF.8~15 pin is ignored. + * | | | + * @var GPIO_T::INTTYPE + * Offset: 0x18/0x58/0x98/0xD8/0x118/0x158 Port A-F Interrupt Trigger Type Control + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |TYPEn |Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control + * | | |TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger + * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce + * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. + * | | |0 = Edge trigger interrupt. + * | | |1 = Level trigger interrupt. + * | | |If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) + * | | |If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. + * | | |The de-bounce function is valid only for edge triggered interrupt + * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored. + * | | |Note: The PC.13/PC.15/PD.14/PF.8~15 pin is ignored. + * | | | + * @var GPIO_T::INTEN + * Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C Port A-F Interrupt Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |FLIENn |Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit + * | | |The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin + * | | |Set bit to 1 also enable the pin wake-up function. + * | | |When setting the FLIEN (Px_INTEN[n]) bit to 1 : + * | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. + * | | |If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. + * | | |0 = Px.n level low or high to low interrupt Disabled. + * | | |1 = Px.n level low or high to low interrupt Enabled. + * | | |Note: The PC.13/PC.15/PD.14/PF.8~15 pin is ignored. + * | | | + * |[n+16] |RHIENn |Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit + * | | |The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin + * | | |Set bit to 1 also enable the pin wake-up function. + * | | |When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : + * | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. + * | | |If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. + * | | |0 = Px.n level high or low to high interrupt Disabled. + * | | |1 = Px.n level high or low to high interrupt Enabled. + * | | |Note: The PC.13/PC.15/PD.14/PF.8~15 pin is ignored. + * | | | + * @var GPIO_T::INTSRC + * Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160 Port A-F Interrupt Source Flag + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |INTSRCn |Port A-F Pin[n] Interrupt Source Flag + * | | |Write Operation : + * | | |0 = No action. + * | | |1 = Clear the corresponding pending interrupt. + * | | |Read Operation : + * | | |0 = No interrupt at Px.n. + * | | |1 = Px.n generates an interrupt. + * | | |Note: The PC.13/PC.15/PD.14/PF.8~15 pin is ignored. + * | | | + * @var GPIO_T::SMTEN + * Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164 Port A-F Input Schmitt Trigger Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |SMTENn |Port A-F Pin[n] Input Schmitt Trigger Enable Bit + * | | |0 = Px.n input schmitt trigger function Disabled. + * | | |1 = Px.n input schmitt trigger function Enabled. + * | | |Note: The PC.13/PC.15/PD.14/PF.8~15 pin is ignored. + * | | | + * @var GPIO_T::SLEWCTL + * Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168 Port A-F High Slew Rate Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2n+1:2n]|HSRENn |Port A-F Pin[n] High Slew Rate Control + * | | |00 = Px.n output with normal slew rate mode. + * | | |01 = Px.n output with high slew rate mode. + * | | |10 = Reserved. + * | | |11 = Reserved. + * | | |Note1: The PC.13/PC.15/PD.14/PF.8~15 pin is ignored. + * | | |Note2: Please refer to the M251 Datasheet for detailed pin operation voltage + * | | | information about VDD, VDDIO and VBAT electrical characteristics. + * @var GPIO_T::PUSEL + * Offset: 0x30/0x70/0xB0/0xF0/0x130/0x170 Port A-F Pull-up and Pull-down Selection Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2n+1:2n]|PUSELn |Port A-F Pin[n] Pull-up and Pull-down Enable Register + * | | |Determine each I/O Pull-up/pull-down of Px.n pins. + * | | |00 = Px.n pull-up and pull-down disable. + * | | |01 = Px.n pull-up enable. + * | | |10 = Px.n pull-down enable. + * | | |11 = Px.n pull-up and pull-down disable. + * | | |Note1: + * | | |Basically, the pull-up control and pull-down control has following behavior limitation + * | | |The independent pull-up control register only valid when MODEn set as tri-state and open-drain mode + * | | |The independent pull-down control register only valid when MODEn set as tri-state mode + * | | |When both pull-up pull-down is set as 1 at tri-state mode, keep I/O in tri-state mode + * | | |Note2: The PC.13/PC.15/PD.14/PF.8~15 pin is ignored. + * | | | + */ + __IO uint32_t MODE; /*!< [0x00/0x40/0x80/0xc0/0x100/0x140] PA~PF I/O Mode Control */ + __IO uint32_t DINOFF; /*!< [0x04/0x44/0x84/0xc4/0x104/0x144] PA~PF Digital Input Path Disable Control */ + __IO uint32_t DOUT; /*!< [0x08/0x48/0x88/0xc8/0x108/0x148] PA~PF Data Output Value */ + __IO uint32_t DATMSK; /*!< [0x0c/0x4c/0x8c/0xcc/0x10c/0x14c] PA~PF Data Output Write Mask */ + __I uint32_t PIN; /*!< [0x10/0x50/0x90/0xd0/0x110/0x150] PA~PF Pin Value */ + __IO uint32_t DBEN; /*!< [0x14/0x54/0x94/0xd4/0x114/0x154] PA~PF De-bounce Enable Control Register */ + __IO uint32_t INTTYPE; /*!< [0x18/0x58/0x98/0xd8/0x118/0x158] PA~PF Interrupt Trigger Type Control */ + __IO uint32_t INTEN; /*!< [0x1c/0x5c/0x9c/0xdc/0x11c/0x15c] PA~PF Interrupt Enable Control Register */ + __IO uint32_t INTSRC; /*!< [0x20/0x60/0xa0/0xe0/0x120/0x160] PA~PF Interrupt Source Flag */ + __IO uint32_t SMTEN; /*!< [0x24/0x64/0xa4/0xe4/0x124/0x164] PA~PF Input Schmitt Trigger Enable Register*/ + __IO uint32_t SLEWCTL; /*!< [0x28/0x68/0xa8/0xe8/0x128/0x168] PA~PF High Slew Rate Control Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[1]; + /// @endcond //HIDDEN_SYMBOLS + __IO uint32_t PUSEL; /*!< [0x30/0x70/0xB0/0xF0/0x130/0x170] PA~PF Pull-up and Pull-down Selection Register*/ +} GPIO_T; + + +typedef struct +{ + + + + /** + * @var GPIO_DBCTL_T::DBCTL + * Offset: 0x440 Interrupt De-bounce Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |DBCLKSEL |De-bounce Sampling Cycle Selection + * | | |0000 = Sample interrupt input once per 1 clocks. + * | | |0001 = Sample interrupt input once per 2 clocks. + * | | |0010 = Sample interrupt input once per 4 clocks. + * | | |0011 = Sample interrupt input once per 8 clocks. + * | | |0100 = Sample interrupt input once per 16 clocks. + * | | |0101 = Sample interrupt input once per 32 clocks. + * | | |0110 = Sample interrupt input once per 64 clocks. + * | | |0111 = Sample interrupt input once per 128 clocks. + * | | |1000 = Sample interrupt input once per 256 clocks. + * | | |1001 = Sample interrupt input once per 2*256 clocks. + * | | |1010 = Sample interrupt input once per 4*256 clocks. + * | | |1011 = Sample interrupt input once per 8*256 clocks. + * | | |1100 = Sample interrupt input once per 16*256 clocks. + * | | |1101 = Sample interrupt input once per 32*256 clocks. + * | | |1110 = Sample interrupt input once per 64*256 clocks. + * | | |1111 = Sample interrupt input once per 128*256 clocks. + * |[4] |DBCLKSRC |De-bounce Counter Clock Source Selection + * | | |0 = De-bounce counter clock source is the HCLK. + * | | |1 = De-bounce counter clock source is the 38.4 kHz internal low speed RC oscillator (LIRC). + * |[21:16] |ICLKONx |Interrupt Clock on Mode + * | | |0 = Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1. + * | | |1 = All I/O pins edge detection circuit is always active after reset. + * | | |Note: It is recommended to disable this bit to save system power if no special application concern. + */ + + __IO uint32_t DBCTL; /*!< [0x0440] Interrupt De-bounce Control Register */ + +} GPIO_DBCTL_T; + +/** + @addtogroup GPIO_CONST GPIO Bit Field Definition + Constant Definitions for GPIO Controller +@{ */ + +#define GPIO_MODE_MODE0_Pos (0) /*!< GPIO_T::MODE: MODE0 Position */ +#define GPIO_MODE_MODE0_Msk (0x3ul << GPIO_MODE_MODE0_Pos) /*!< GPIO_T::MODE: MODE0 Mask */ + +#define GPIO_MODE_MODE1_Pos (2) /*!< GPIO_T::MODE: MODE1 Position */ +#define GPIO_MODE_MODE1_Msk (0x3ul << GPIO_MODE_MODE1_Pos) /*!< GPIO_T::MODE: MODE1 Mask */ + +#define GPIO_MODE_MODE2_Pos (4) /*!< GPIO_T::MODE: MODE2 Position */ +#define GPIO_MODE_MODE2_Msk (0x3ul << GPIO_MODE_MODE2_Pos) /*!< GPIO_T::MODE: MODE2 Mask */ + +#define GPIO_MODE_MODE3_Pos (6) /*!< GPIO_T::MODE: MODE3 Position */ +#define GPIO_MODE_MODE3_Msk (0x3ul << GPIO_MODE_MODE3_Pos) /*!< GPIO_T::MODE: MODE3 Mask */ + +#define GPIO_MODE_MODE4_Pos (8) /*!< GPIO_T::MODE: MODE4 Position */ +#define GPIO_MODE_MODE4_Msk (0x3ul << GPIO_MODE_MODE4_Pos) /*!< GPIO_T::MODE: MODE4 Mask */ + +#define GPIO_MODE_MODE5_Pos (10) /*!< GPIO_T::MODE: MODE5 Position */ +#define GPIO_MODE_MODE5_Msk (0x3ul << GPIO_MODE_MODE5_Pos) /*!< GPIO_T::MODE: MODE5 Mask */ + +#define GPIO_MODE_MODE6_Pos (12) /*!< GPIO_T::MODE: MODE6 Position */ +#define GPIO_MODE_MODE6_Msk (0x3ul << GPIO_MODE_MODE6_Pos) /*!< GPIO_T::MODE: MODE6 Mask */ + +#define GPIO_MODE_MODE7_Pos (14) /*!< GPIO_T::MODE: MODE7 Position */ +#define GPIO_MODE_MODE7_Msk (0x3ul << GPIO_MODE_MODE7_Pos) /*!< GPIO_T::MODE: MODE7 Mask */ + +#define GPIO_MODE_MODE8_Pos (16) /*!< GPIO_T::MODE: MODE8 Position */ +#define GPIO_MODE_MODE8_Msk (0x3ul << GPIO_MODE_MODE8_Pos) /*!< GPIO_T::MODE: MODE8 Mask */ + +#define GPIO_MODE_MODE9_Pos (18) /*!< GPIO_T::MODE: MODE9 Position */ +#define GPIO_MODE_MODE9_Msk (0x3ul << GPIO_MODE_MODE9_Pos) /*!< GPIO_T::MODE: MODE9 Mask */ + +#define GPIO_MODE_MODE10_Pos (20) /*!< GPIO_T::MODE: MODE10 Position */ +#define GPIO_MODE_MODE10_Msk (0x3ul << GPIO_MODE_MODE10_Pos) /*!< GPIO_T::MODE: MODE10 Mask */ + +#define GPIO_MODE_MODE11_Pos (22) /*!< GPIO_T::MODE: MODE11 Position */ +#define GPIO_MODE_MODE11_Msk (0x3ul << GPIO_MODE_MODE11_Pos) /*!< GPIO_T::MODE: MODE11 Mask */ + +#define GPIO_MODE_MODE12_Pos (24) /*!< GPIO_T::MODE: MODE12 Position */ +#define GPIO_MODE_MODE12_Msk (0x3ul << GPIO_MODE_MODE12_Pos) /*!< GPIO_T::MODE: MODE12 Mask */ + +#define GPIO_MODE_MODE13_Pos (26) /*!< GPIO_T::MODE: MODE13 Position */ +#define GPIO_MODE_MODE13_Msk (0x3ul << GPIO_MODE_MODE13_Pos) /*!< GPIO_T::MODE: MODE13 Mask */ + +#define GPIO_MODE_MODE14_Pos (28) /*!< GPIO_T::MODE: MODE14 Position */ +#define GPIO_MODE_MODE14_Msk (0x3ul << GPIO_MODE_MODE14_Pos) /*!< GPIO_T::MODE: MODE14 Mask */ + +#define GPIO_MODE_MODE15_Pos (30) /*!< GPIO_T::MODE: MODE15 Position */ +#define GPIO_MODE_MODE15_Msk (0x3ul << GPIO_MODE_MODE15_Pos) /*!< GPIO_T::MODE: MODE15 Mask */ + +#define GPIO_DINOFF_DINOFF0_Pos (16) /*!< GPIO_T::DINOFF: DINOFF0 Position */ +#define GPIO_DINOFF_DINOFF0_Msk (0x1ul << GPIO_DINOFF_DINOFF0_Pos) /*!< GPIO_T::DINOFF: DINOFF0 Mask */ + +#define GPIO_DINOFF_DINOFF1_Pos (17) /*!< GPIO_T::DINOFF: DINOFF1 Position */ +#define GPIO_DINOFF_DINOFF1_Msk (0x1ul << GPIO_DINOFF_DINOFF1_Pos) /*!< GPIO_T::DINOFF: DINOFF1 Mask */ + +#define GPIO_DINOFF_DINOFF2_Pos (18) /*!< GPIO_T::DINOFF: DINOFF2 Position */ +#define GPIO_DINOFF_DINOFF2_Msk (0x1ul << GPIO_DINOFF_DINOFF2_Pos) /*!< GPIO_T::DINOFF: DINOFF2 Mask */ + +#define GPIO_DINOFF_DINOFF3_Pos (19) /*!< GPIO_T::DINOFF: DINOFF3 Position */ +#define GPIO_DINOFF_DINOFF3_Msk (0x1ul << GPIO_DINOFF_DINOFF3_Pos) /*!< GPIO_T::DINOFF: DINOFF3 Mask */ + +#define GPIO_DINOFF_DINOFF4_Pos (20) /*!< GPIO_T::DINOFF: DINOFF4 Position */ +#define GPIO_DINOFF_DINOFF4_Msk (0x1ul << GPIO_DINOFF_DINOFF4_Pos) /*!< GPIO_T::DINOFF: DINOFF4 Mask */ + +#define GPIO_DINOFF_DINOFF5_Pos (21) /*!< GPIO_T::DINOFF: DINOFF5 Position */ +#define GPIO_DINOFF_DINOFF5_Msk (0x1ul << GPIO_DINOFF_DINOFF5_Pos) /*!< GPIO_T::DINOFF: DINOFF5 Mask */ + +#define GPIO_DINOFF_DINOFF6_Pos (22) /*!< GPIO_T::DINOFF: DINOFF6 Position */ +#define GPIO_DINOFF_DINOFF6_Msk (0x1ul << GPIO_DINOFF_DINOFF6_Pos) /*!< GPIO_T::DINOFF: DINOFF6 Mask */ + +#define GPIO_DINOFF_DINOFF7_Pos (23) /*!< GPIO_T::DINOFF: DINOFF7 Position */ +#define GPIO_DINOFF_DINOFF7_Msk (0x1ul << GPIO_DINOFF_DINOFF7_Pos) /*!< GPIO_T::DINOFF: DINOFF7 Mask */ + +#define GPIO_DINOFF_DINOFF8_Pos (24) /*!< GPIO_T::DINOFF: DINOFF8 Position */ +#define GPIO_DINOFF_DINOFF8_Msk (0x1ul << GPIO_DINOFF_DINOFF8_Pos) /*!< GPIO_T::DINOFF: DINOFF8 Mask */ + +#define GPIO_DINOFF_DINOFF9_Pos (25) /*!< GPIO_T::DINOFF: DINOFF9 Position */ +#define GPIO_DINOFF_DINOFF9_Msk (0x1ul << GPIO_DINOFF_DINOFF9_Pos) /*!< GPIO_T::DINOFF: DINOFF9 Mask */ + +#define GPIO_DINOFF_DINOFF10_Pos (26) /*!< GPIO_T::DINOFF: DINOFF10 Position */ +#define GPIO_DINOFF_DINOFF10_Msk (0x1ul << GPIO_DINOFF_DINOFF10_Pos) /*!< GPIO_T::DINOFF: DINOFF10 Mask */ + +#define GPIO_DINOFF_DINOFF11_Pos (27) /*!< GPIO_T::DINOFF: DINOFF11 Position */ +#define GPIO_DINOFF_DINOFF11_Msk (0x1ul << GPIO_DINOFF_DINOFF11_Pos) /*!< GPIO_T::DINOFF: DINOFF11 Mask */ + +#define GPIO_DINOFF_DINOFF12_Pos (28) /*!< GPIO_T::DINOFF: DINOFF12 Position */ +#define GPIO_DINOFF_DINOFF12_Msk (0x1ul << GPIO_DINOFF_DINOFF12_Pos) /*!< GPIO_T::DINOFF: DINOFF12 Mask */ + +#define GPIO_DINOFF_DINOFF13_Pos (29) /*!< GPIO_T::DINOFF: DINOFF13 Position */ +#define GPIO_DINOFF_DINOFF13_Msk (0x1ul << GPIO_DINOFF_DINOFF13_Pos) /*!< GPIO_T::DINOFF: DINOFF13 Mask */ + +#define GPIO_DINOFF_DINOFF14_Pos (30) /*!< GPIO_T::DINOFF: DINOFF14 Position */ +#define GPIO_DINOFF_DINOFF14_Msk (0x1ul << GPIO_DINOFF_DINOFF14_Pos) /*!< GPIO_T::DINOFF: DINOFF14 Mask */ + +#define GPIO_DINOFF_DINOFF15_Pos (31) /*!< GPIO_T::DINOFF: DINOFF15 Position */ +#define GPIO_DINOFF_DINOFF15_Msk (0x1ul << GPIO_DINOFF_DINOFF15_Pos) /*!< GPIO_T::DINOFF: DINOFF15 Mask */ + +#define GPIO_DOUT_DOUT0_Pos (0) /*!< GPIO_T::DOUT: DOUT0 Position */ +#define GPIO_DOUT_DOUT0_Msk (0x1ul << GPIO_DOUT_DOUT0_Pos) /*!< GPIO_T::DOUT: DOUT0 Mask */ + +#define GPIO_DOUT_DOUT1_Pos (1) /*!< GPIO_T::DOUT: DOUT1 Position */ +#define GPIO_DOUT_DOUT1_Msk (0x1ul << GPIO_DOUT_DOUT1_Pos) /*!< GPIO_T::DOUT: DOUT1 Mask */ + +#define GPIO_DOUT_DOUT2_Pos (2) /*!< GPIO_T::DOUT: DOUT2 Position */ +#define GPIO_DOUT_DOUT2_Msk (0x1ul << GPIO_DOUT_DOUT2_Pos) /*!< GPIO_T::DOUT: DOUT2 Mask */ + +#define GPIO_DOUT_DOUT3_Pos (3) /*!< GPIO_T::DOUT: DOUT3 Position */ +#define GPIO_DOUT_DOUT3_Msk (0x1ul << GPIO_DOUT_DOUT3_Pos) /*!< GPIO_T::DOUT: DOUT3 Mask */ + +#define GPIO_DOUT_DOUT4_Pos (4) /*!< GPIO_T::DOUT: DOUT4 Position */ +#define GPIO_DOUT_DOUT4_Msk (0x1ul << GPIO_DOUT_DOUT4_Pos) /*!< GPIO_T::DOUT: DOUT4 Mask */ + +#define GPIO_DOUT_DOUT5_Pos (5) /*!< GPIO_T::DOUT: DOUT5 Position */ +#define GPIO_DOUT_DOUT5_Msk (0x1ul << GPIO_DOUT_DOUT5_Pos) /*!< GPIO_T::DOUT: DOUT5 Mask */ + +#define GPIO_DOUT_DOUT6_Pos (6) /*!< GPIO_T::DOUT: DOUT6 Position */ +#define GPIO_DOUT_DOUT6_Msk (0x1ul << GPIO_DOUT_DOUT6_Pos) /*!< GPIO_T::DOUT: DOUT6 Mask */ + +#define GPIO_DOUT_DOUT7_Pos (7) /*!< GPIO_T::DOUT: DOUT7 Position */ +#define GPIO_DOUT_DOUT7_Msk (0x1ul << GPIO_DOUT_DOUT7_Pos) /*!< GPIO_T::DOUT: DOUT7 Mask */ + +#define GPIO_DOUT_DOUT8_Pos (8) /*!< GPIO_T::DOUT: DOUT8 Position */ +#define GPIO_DOUT_DOUT8_Msk (0x1ul << GPIO_DOUT_DOUT8_Pos) /*!< GPIO_T::DOUT: DOUT8 Mask */ + +#define GPIO_DOUT_DOUT9_Pos (9) /*!< GPIO_T::DOUT: DOUT9 Position */ +#define GPIO_DOUT_DOUT9_Msk (0x1ul << GPIO_DOUT_DOUT9_Pos) /*!< GPIO_T::DOUT: DOUT9 Mask */ + +#define GPIO_DOUT_DOUT10_Pos (10) /*!< GPIO_T::DOUT: DOUT10 Position */ +#define GPIO_DOUT_DOUT10_Msk (0x1ul << GPIO_DOUT_DOUT10_Pos) /*!< GPIO_T::DOUT: DOUT10 Mask */ + +#define GPIO_DOUT_DOUT11_Pos (11) /*!< GPIO_T::DOUT: DOUT11 Position */ +#define GPIO_DOUT_DOUT11_Msk (0x1ul << GPIO_DOUT_DOUT11_Pos) /*!< GPIO_T::DOUT: DOUT11 Mask */ + +#define GPIO_DOUT_DOUT12_Pos (12) /*!< GPIO_T::DOUT: DOUT12 Position */ +#define GPIO_DOUT_DOUT12_Msk (0x1ul << GPIO_DOUT_DOUT12_Pos) /*!< GPIO_T::DOUT: DOUT12 Mask */ + +#define GPIO_DOUT_DOUT13_Pos (13) /*!< GPIO_T::DOUT: DOUT13 Position */ +#define GPIO_DOUT_DOUT13_Msk (0x1ul << GPIO_DOUT_DOUT13_Pos) /*!< GPIO_T::DOUT: DOUT13 Mask */ + +#define GPIO_DOUT_DOUT14_Pos (14) /*!< GPIO_T::DOUT: DOUT14 Position */ +#define GPIO_DOUT_DOUT14_Msk (0x1ul << GPIO_DOUT_DOUT14_Pos) /*!< GPIO_T::DOUT: DOUT14 Mask */ + +#define GPIO_DOUT_DOUT15_Pos (15) /*!< GPIO_T::DOUT: DOUT15 Position */ +#define GPIO_DOUT_DOUT15_Msk (0x1ul << GPIO_DOUT_DOUT15_Pos) /*!< GPIO_T::DOUT: DOUT15 Mask */ + +#define GPIO_DATMSK_DATMSK0_Pos (0) /*!< GPIO_T::DATMSK: DATMSK0 Position */ +#define GPIO_DATMSK_DATMSK0_Msk (0x1ul << GPIO_DATMSK_DATMSK0_Pos) /*!< GPIO_T::DATMSK: DATMSK0 Mask */ + +#define GPIO_DATMSK_DATMSK1_Pos (1) /*!< GPIO_T::DATMSK: DATMSK1 Position */ +#define GPIO_DATMSK_DATMSK1_Msk (0x1ul << GPIO_DATMSK_DATMSK1_Pos) /*!< GPIO_T::DATMSK: DATMSK1 Mask */ + +#define GPIO_DATMSK_DATMSK2_Pos (2) /*!< GPIO_T::DATMSK: DATMSK2 Position */ +#define GPIO_DATMSK_DATMSK2_Msk (0x1ul << GPIO_DATMSK_DATMSK2_Pos) /*!< GPIO_T::DATMSK: DATMSK2 Mask */ + +#define GPIO_DATMSK_DATMSK3_Pos (3) /*!< GPIO_T::DATMSK: DATMSK3 Position */ +#define GPIO_DATMSK_DATMSK3_Msk (0x1ul << GPIO_DATMSK_DATMSK3_Pos) /*!< GPIO_T::DATMSK: DATMSK3 Mask */ + +#define GPIO_DATMSK_DATMSK4_Pos (4) /*!< GPIO_T::DATMSK: DATMSK4 Position */ +#define GPIO_DATMSK_DATMSK4_Msk (0x1ul << GPIO_DATMSK_DATMSK4_Pos) /*!< GPIO_T::DATMSK: DATMSK4 Mask */ + +#define GPIO_DATMSK_DATMSK5_Pos (5) /*!< GPIO_T::DATMSK: DATMSK5 Position */ +#define GPIO_DATMSK_DATMSK5_Msk (0x1ul << GPIO_DATMSK_DATMSK5_Pos) /*!< GPIO_T::DATMSK: DATMSK5 Mask */ + +#define GPIO_DATMSK_DATMSK6_Pos (6) /*!< GPIO_T::DATMSK: DATMSK6 Position */ +#define GPIO_DATMSK_DATMSK6_Msk (0x1ul << GPIO_DATMSK_DATMSK6_Pos) /*!< GPIO_T::DATMSK: DATMSK6 Mask */ + +#define GPIO_DATMSK_DATMSK7_Pos (7) /*!< GPIO_T::DATMSK: DATMSK7 Position */ +#define GPIO_DATMSK_DATMSK7_Msk (0x1ul << GPIO_DATMSK_DATMSK7_Pos) /*!< GPIO_T::DATMSK: DATMSK7 Mask */ + +#define GPIO_DATMSK_DATMSK8_Pos (8) /*!< GPIO_T::DATMSK: DATMSK8 Position */ +#define GPIO_DATMSK_DATMSK8_Msk (0x1ul << GPIO_DATMSK_DATMSK8_Pos) /*!< GPIO_T::DATMSK: DATMSK8 Mask */ + +#define GPIO_DATMSK_DATMSK9_Pos (9) /*!< GPIO_T::DATMSK: DATMSK9 Position */ +#define GPIO_DATMSK_DATMSK9_Msk (0x1ul << GPIO_DATMSK_DATMSK9_Pos) /*!< GPIO_T::DATMSK: DATMSK9 Mask */ + +#define GPIO_DATMSK_DATMSK10_Pos (10) /*!< GPIO_T::DATMSK: DATMSK10 Position */ +#define GPIO_DATMSK_DATMSK10_Msk (0x1ul << GPIO_DATMSK_DATMSK10_Pos) /*!< GPIO_T::DATMSK: DATMSK10 Mask */ + +#define GPIO_DATMSK_DATMSK11_Pos (11) /*!< GPIO_T::DATMSK: DATMSK11 Position */ +#define GPIO_DATMSK_DATMSK11_Msk (0x1ul << GPIO_DATMSK_DATMSK11_Pos) /*!< GPIO_T::DATMSK: DATMSK11 Mask */ + +#define GPIO_DATMSK_DATMSK12_Pos (12) /*!< GPIO_T::DATMSK: DATMSK12 Position */ +#define GPIO_DATMSK_DATMSK12_Msk (0x1ul << GPIO_DATMSK_DATMSK12_Pos) /*!< GPIO_T::DATMSK: DATMSK12 Mask */ + +#define GPIO_DATMSK_DATMSK13_Pos (13) /*!< GPIO_T::DATMSK: DATMSK13 Position */ +#define GPIO_DATMSK_DATMSK13_Msk (0x1ul << GPIO_DATMSK_DATMSK13_Pos) /*!< GPIO_T::DATMSK: DATMSK13 Mask */ + +#define GPIO_DATMSK_DATMSK14_Pos (14) /*!< GPIO_T::DATMSK: DATMSK14 Position */ +#define GPIO_DATMSK_DATMSK14_Msk (0x1ul << GPIO_DATMSK_DATMSK14_Pos) /*!< GPIO_T::DATMSK: DATMSK14 Mask */ + +#define GPIO_DATMSK_DATMSK15_Pos (15) /*!< GPIO_T::DATMSK: DATMSK15 Position */ +#define GPIO_DATMSK_DATMSK15_Msk (0x1ul << GPIO_DATMSK_DATMSK15_Pos) /*!< GPIO_T::DATMSK: DATMSK15 Mask */ + +#define GPIO_PIN_PIN0_Pos (0) /*!< GPIO_T::PIN: PIN0 Position */ +#define GPIO_PIN_PIN0_Msk (0x1ul << GPIO_PIN_PIN0_Pos) /*!< GPIO_T::PIN: PIN0 Mask */ + +#define GPIO_PIN_PIN1_Pos (1) /*!< GPIO_T::PIN: PIN1 Position */ +#define GPIO_PIN_PIN1_Msk (0x1ul << GPIO_PIN_PIN1_Pos) /*!< GPIO_T::PIN: PIN1 Mask */ + +#define GPIO_PIN_PIN2_Pos (2) /*!< GPIO_T::PIN: PIN2 Position */ +#define GPIO_PIN_PIN2_Msk (0x1ul << GPIO_PIN_PIN2_Pos) /*!< GPIO_T::PIN: PIN2 Mask */ + +#define GPIO_PIN_PIN3_Pos (3) /*!< GPIO_T::PIN: PIN3 Position */ +#define GPIO_PIN_PIN3_Msk (0x1ul << GPIO_PIN_PIN3_Pos) /*!< GPIO_T::PIN: PIN3 Mask */ + +#define GPIO_PIN_PIN4_Pos (4) /*!< GPIO_T::PIN: PIN4 Position */ +#define GPIO_PIN_PIN4_Msk (0x1ul << GPIO_PIN_PIN4_Pos) /*!< GPIO_T::PIN: PIN4 Mask */ + +#define GPIO_PIN_PIN5_Pos (5) /*!< GPIO_T::PIN: PIN5 Position */ +#define GPIO_PIN_PIN5_Msk (0x1ul << GPIO_PIN_PIN5_Pos) /*!< GPIO_T::PIN: PIN5 Mask */ + +#define GPIO_PIN_PIN6_Pos (6) /*!< GPIO_T::PIN: PIN6 Position */ +#define GPIO_PIN_PIN6_Msk (0x1ul << GPIO_PIN_PIN6_Pos) /*!< GPIO_T::PIN: PIN6 Mask */ + +#define GPIO_PIN_PIN7_Pos (7) /*!< GPIO_T::PIN: PIN7 Position */ +#define GPIO_PIN_PIN7_Msk (0x1ul << GPIO_PIN_PIN7_Pos) /*!< GPIO_T::PIN: PIN7 Mask */ + +#define GPIO_PIN_PIN8_Pos (8) /*!< GPIO_T::PIN: PIN8 Position */ +#define GPIO_PIN_PIN8_Msk (0x1ul << GPIO_PIN_PIN8_Pos) /*!< GPIO_T::PIN: PIN8 Mask */ + +#define GPIO_PIN_PIN9_Pos (9) /*!< GPIO_T::PIN: PIN9 Position */ +#define GPIO_PIN_PIN9_Msk (0x1ul << GPIO_PIN_PIN9_Pos) /*!< GPIO_T::PIN: PIN9 Mask */ + +#define GPIO_PIN_PIN10_Pos (10) /*!< GPIO_T::PIN: PIN10 Position */ +#define GPIO_PIN_PIN10_Msk (0x1ul << GPIO_PIN_PIN10_Pos) /*!< GPIO_T::PIN: PIN10 Mask */ + +#define GPIO_PIN_PIN11_Pos (11) /*!< GPIO_T::PIN: PIN11 Position */ +#define GPIO_PIN_PIN11_Msk (0x1ul << GPIO_PIN_PIN11_Pos) /*!< GPIO_T::PIN: PIN11 Mask */ + +#define GPIO_PIN_PIN12_Pos (12) /*!< GPIO_T::PIN: PIN12 Position */ +#define GPIO_PIN_PIN12_Msk (0x1ul << GPIO_PIN_PIN12_Pos) /*!< GPIO_T::PIN: PIN12 Mask */ + +#define GPIO_PIN_PIN13_Pos (13) /*!< GPIO_T::PIN: PIN13 Position */ +#define GPIO_PIN_PIN13_Msk (0x1ul << GPIO_PIN_PIN13_Pos) /*!< GPIO_T::PIN: PIN13 Mask */ + +#define GPIO_PIN_PIN14_Pos (14) /*!< GPIO_T::PIN: PIN14 Position */ +#define GPIO_PIN_PIN14_Msk (0x1ul << GPIO_PIN_PIN14_Pos) /*!< GPIO_T::PIN: PIN14 Mask */ + +#define GPIO_PIN_PIN15_Pos (15) /*!< GPIO_T::PIN: PIN15 Position */ +#define GPIO_PIN_PIN15_Msk (0x1ul << GPIO_PIN_PIN15_Pos) /*!< GPIO_T::PIN: PIN15 Mask */ + +#define GPIO_DBEN_DBEN0_Pos (0) /*!< GPIO_T::DBEN: DBEN0 Position */ +#define GPIO_DBEN_DBEN0_Msk (0x1ul << GPIO_DBEN_DBEN0_Pos) /*!< GPIO_T::DBEN: DBEN0 Mask */ + +#define GPIO_DBEN_DBEN1_Pos (1) /*!< GPIO_T::DBEN: DBEN1 Position */ +#define GPIO_DBEN_DBEN1_Msk (0x1ul << GPIO_DBEN_DBEN1_Pos) /*!< GPIO_T::DBEN: DBEN1 Mask */ + +#define GPIO_DBEN_DBEN2_Pos (2) /*!< GPIO_T::DBEN: DBEN2 Position */ +#define GPIO_DBEN_DBEN2_Msk (0x1ul << GPIO_DBEN_DBEN2_Pos) /*!< GPIO_T::DBEN: DBEN2 Mask */ + +#define GPIO_DBEN_DBEN3_Pos (3) /*!< GPIO_T::DBEN: DBEN3 Position */ +#define GPIO_DBEN_DBEN3_Msk (0x1ul << GPIO_DBEN_DBEN3_Pos) /*!< GPIO_T::DBEN: DBEN3 Mask */ + +#define GPIO_DBEN_DBEN4_Pos (4) /*!< GPIO_T::DBEN: DBEN4 Position */ +#define GPIO_DBEN_DBEN4_Msk (0x1ul << GPIO_DBEN_DBEN4_Pos) /*!< GPIO_T::DBEN: DBEN4 Mask */ + +#define GPIO_DBEN_DBEN5_Pos (5) /*!< GPIO_T::DBEN: DBEN5 Position */ +#define GPIO_DBEN_DBEN5_Msk (0x1ul << GPIO_DBEN_DBEN5_Pos) /*!< GPIO_T::DBEN: DBEN5 Mask */ + +#define GPIO_DBEN_DBEN6_Pos (6) /*!< GPIO_T::DBEN: DBEN6 Position */ +#define GPIO_DBEN_DBEN6_Msk (0x1ul << GPIO_DBEN_DBEN6_Pos) /*!< GPIO_T::DBEN: DBEN6 Mask */ + +#define GPIO_DBEN_DBEN7_Pos (7) /*!< GPIO_T::DBEN: DBEN7 Position */ +#define GPIO_DBEN_DBEN7_Msk (0x1ul << GPIO_DBEN_DBEN7_Pos) /*!< GPIO_T::DBEN: DBEN7 Mask */ + +#define GPIO_DBEN_DBEN8_Pos (8) /*!< GPIO_T::DBEN: DBEN8 Position */ +#define GPIO_DBEN_DBEN8_Msk (0x1ul << GPIO_DBEN_DBEN8_Pos) /*!< GPIO_T::DBEN: DBEN8 Mask */ + +#define GPIO_DBEN_DBEN9_Pos (9) /*!< GPIO_T::DBEN: DBEN9 Position */ +#define GPIO_DBEN_DBEN9_Msk (0x1ul << GPIO_DBEN_DBEN9_Pos) /*!< GPIO_T::DBEN: DBEN9 Mask */ + +#define GPIO_DBEN_DBEN10_Pos (10) /*!< GPIO_T::DBEN: DBEN10 Position */ +#define GPIO_DBEN_DBEN10_Msk (0x1ul << GPIO_DBEN_DBEN10_Pos) /*!< GPIO_T::DBEN: DBEN10 Mask */ + +#define GPIO_DBEN_DBEN11_Pos (11) /*!< GPIO_T::DBEN: DBEN11 Position */ +#define GPIO_DBEN_DBEN11_Msk (0x1ul << GPIO_DBEN_DBEN11_Pos) /*!< GPIO_T::DBEN: DBEN11 Mask */ + +#define GPIO_DBEN_DBEN12_Pos (12) /*!< GPIO_T::DBEN: DBEN12 Position */ +#define GPIO_DBEN_DBEN12_Msk (0x1ul << GPIO_DBEN_DBEN12_Pos) /*!< GPIO_T::DBEN: DBEN12 Mask */ + +#define GPIO_DBEN_DBEN13_Pos (13) /*!< GPIO_T::DBEN: DBEN13 Position */ +#define GPIO_DBEN_DBEN13_Msk (0x1ul << GPIO_DBEN_DBEN13_Pos) /*!< GPIO_T::DBEN: DBEN13 Mask */ + +#define GPIO_DBEN_DBEN14_Pos (14) /*!< GPIO_T::DBEN: DBEN14 Position */ +#define GPIO_DBEN_DBEN14_Msk (0x1ul << GPIO_DBEN_DBEN14_Pos) /*!< GPIO_T::DBEN: DBEN14 Mask */ + +#define GPIO_DBEN_DBEN15_Pos (15) /*!< GPIO_T::DBEN: DBEN15 Position */ +#define GPIO_DBEN_DBEN15_Msk (0x1ul << GPIO_DBEN_DBEN15_Pos) /*!< GPIO_T::DBEN: DBEN15 Mask */ + +#define GPIO_INTTYPE_TYPE0_Pos (0) /*!< GPIO_T::INTTYPE: TYPE0 Position */ +#define GPIO_INTTYPE_TYPE0_Msk (0x1ul << GPIO_INTTYPE_TYPE0_Pos) /*!< GPIO_T::INTTYPE: TYPE0 Mask */ + +#define GPIO_INTTYPE_TYPE1_Pos (1) /*!< GPIO_T::INTTYPE: TYPE1 Position */ +#define GPIO_INTTYPE_TYPE1_Msk (0x1ul << GPIO_INTTYPE_TYPE1_Pos) /*!< GPIO_T::INTTYPE: TYPE1 Mask */ + +#define GPIO_INTTYPE_TYPE2_Pos (2) /*!< GPIO_T::INTTYPE: TYPE2 Position */ +#define GPIO_INTTYPE_TYPE2_Msk (0x1ul << GPIO_INTTYPE_TYPE2_Pos) /*!< GPIO_T::INTTYPE: TYPE2 Mask */ + +#define GPIO_INTTYPE_TYPE3_Pos (3) /*!< GPIO_T::INTTYPE: TYPE3 Position */ +#define GPIO_INTTYPE_TYPE3_Msk (0x1ul << GPIO_INTTYPE_TYPE3_Pos) /*!< GPIO_T::INTTYPE: TYPE3 Mask */ + +#define GPIO_INTTYPE_TYPE4_Pos (4) /*!< GPIO_T::INTTYPE: TYPE4 Position */ +#define GPIO_INTTYPE_TYPE4_Msk (0x1ul << GPIO_INTTYPE_TYPE4_Pos) /*!< GPIO_T::INTTYPE: TYPE4 Mask */ + +#define GPIO_INTTYPE_TYPE5_Pos (5) /*!< GPIO_T::INTTYPE: TYPE5 Position */ +#define GPIO_INTTYPE_TYPE5_Msk (0x1ul << GPIO_INTTYPE_TYPE5_Pos) /*!< GPIO_T::INTTYPE: TYPE5 Mask */ + +#define GPIO_INTTYPE_TYPE6_Pos (6) /*!< GPIO_T::INTTYPE: TYPE6 Position */ +#define GPIO_INTTYPE_TYPE6_Msk (0x1ul << GPIO_INTTYPE_TYPE6_Pos) /*!< GPIO_T::INTTYPE: TYPE6 Mask */ + +#define GPIO_INTTYPE_TYPE7_Pos (7) /*!< GPIO_T::INTTYPE: TYPE7 Position */ +#define GPIO_INTTYPE_TYPE7_Msk (0x1ul << GPIO_INTTYPE_TYPE7_Pos) /*!< GPIO_T::INTTYPE: TYPE7 Mask */ + +#define GPIO_INTTYPE_TYPE8_Pos (8) /*!< GPIO_T::INTTYPE: TYPE8 Position */ +#define GPIO_INTTYPE_TYPE8_Msk (0x1ul << GPIO_INTTYPE_TYPE8_Pos) /*!< GPIO_T::INTTYPE: TYPE8 Mask */ + +#define GPIO_INTTYPE_TYPE9_Pos (9) /*!< GPIO_T::INTTYPE: TYPE9 Position */ +#define GPIO_INTTYPE_TYPE9_Msk (0x1ul << GPIO_INTTYPE_TYPE9_Pos) /*!< GPIO_T::INTTYPE: TYPE9 Mask */ + +#define GPIO_INTTYPE_TYPE10_Pos (10) /*!< GPIO_T::INTTYPE: TYPE10 Position */ +#define GPIO_INTTYPE_TYPE10_Msk (0x1ul << GPIO_INTTYPE_TYPE10_Pos) /*!< GPIO_T::INTTYPE: TYPE10 Mask */ + +#define GPIO_INTTYPE_TYPE11_Pos (11) /*!< GPIO_T::INTTYPE: TYPE11 Position */ +#define GPIO_INTTYPE_TYPE11_Msk (0x1ul << GPIO_INTTYPE_TYPE11_Pos) /*!< GPIO_T::INTTYPE: TYPE11 Mask */ + +#define GPIO_INTTYPE_TYPE12_Pos (12) /*!< GPIO_T::INTTYPE: TYPE12 Position */ +#define GPIO_INTTYPE_TYPE12_Msk (0x1ul << GPIO_INTTYPE_TYPE12_Pos) /*!< GPIO_T::INTTYPE: TYPE12 Mask */ + +#define GPIO_INTTYPE_TYPE13_Pos (13) /*!< GPIO_T::INTTYPE: TYPE13 Position */ +#define GPIO_INTTYPE_TYPE13_Msk (0x1ul << GPIO_INTTYPE_TYPE13_Pos) /*!< GPIO_T::INTTYPE: TYPE13 Mask */ + +#define GPIO_INTTYPE_TYPE14_Pos (14) /*!< GPIO_T::INTTYPE: TYPE14 Position */ +#define GPIO_INTTYPE_TYPE14_Msk (0x1ul << GPIO_INTTYPE_TYPE14_Pos) /*!< GPIO_T::INTTYPE: TYPE14 Mask */ + +#define GPIO_INTTYPE_TYPE15_Pos (15) /*!< GPIO_T::INTTYPE: TYPE15 Position */ +#define GPIO_INTTYPE_TYPE15_Msk (0x1ul << GPIO_INTTYPE_TYPE15_Pos) /*!< GPIO_T::INTTYPE: TYPE15 Mask */ + +#define GPIO_INTEN_FLIEN0_Pos (0) /*!< GPIO_T::INTEN: FLIEN0 Position */ +#define GPIO_INTEN_FLIEN0_Msk (0x1ul << GPIO_INTEN_FLIEN0_Pos) /*!< GPIO_T::INTEN: FLIEN0 Mask */ + +#define GPIO_INTEN_FLIEN1_Pos (1) /*!< GPIO_T::INTEN: FLIEN1 Position */ +#define GPIO_INTEN_FLIEN1_Msk (0x1ul << GPIO_INTEN_FLIEN1_Pos) /*!< GPIO_T::INTEN: FLIEN1 Mask */ + +#define GPIO_INTEN_FLIEN2_Pos (2) /*!< GPIO_T::INTEN: FLIEN2 Position */ +#define GPIO_INTEN_FLIEN2_Msk (0x1ul << GPIO_INTEN_FLIEN2_Pos) /*!< GPIO_T::INTEN: FLIEN2 Mask */ + +#define GPIO_INTEN_FLIEN3_Pos (3) /*!< GPIO_T::INTEN: FLIEN3 Position */ +#define GPIO_INTEN_FLIEN3_Msk (0x1ul << GPIO_INTEN_FLIEN3_Pos) /*!< GPIO_T::INTEN: FLIEN3 Mask */ + +#define GPIO_INTEN_FLIEN4_Pos (4) /*!< GPIO_T::INTEN: FLIEN4 Position */ +#define GPIO_INTEN_FLIEN4_Msk (0x1ul << GPIO_INTEN_FLIEN4_Pos) /*!< GPIO_T::INTEN: FLIEN4 Mask */ + +#define GPIO_INTEN_FLIEN5_Pos (5) /*!< GPIO_T::INTEN: FLIEN5 Position */ +#define GPIO_INTEN_FLIEN5_Msk (0x1ul << GPIO_INTEN_FLIEN5_Pos) /*!< GPIO_T::INTEN: FLIEN5 Mask */ + +#define GPIO_INTEN_FLIEN6_Pos (6) /*!< GPIO_T::INTEN: FLIEN6 Position */ +#define GPIO_INTEN_FLIEN6_Msk (0x1ul << GPIO_INTEN_FLIEN6_Pos) /*!< GPIO_T::INTEN: FLIEN6 Mask */ + +#define GPIO_INTEN_FLIEN7_Pos (7) /*!< GPIO_T::INTEN: FLIEN7 Position */ +#define GPIO_INTEN_FLIEN7_Msk (0x1ul << GPIO_INTEN_FLIEN7_Pos) /*!< GPIO_T::INTEN: FLIEN7 Mask */ + +#define GPIO_INTEN_FLIEN8_Pos (8) /*!< GPIO_T::INTEN: FLIEN8 Position */ +#define GPIO_INTEN_FLIEN8_Msk (0x1ul << GPIO_INTEN_FLIEN8_Pos) /*!< GPIO_T::INTEN: FLIEN8 Mask */ + +#define GPIO_INTEN_FLIEN9_Pos (9) /*!< GPIO_T::INTEN: FLIEN9 Position */ +#define GPIO_INTEN_FLIEN9_Msk (0x1ul << GPIO_INTEN_FLIEN9_Pos) /*!< GPIO_T::INTEN: FLIEN9 Mask */ + +#define GPIO_INTEN_FLIEN10_Pos (10) /*!< GPIO_T::INTEN: FLIEN10 Position */ +#define GPIO_INTEN_FLIEN10_Msk (0x1ul << GPIO_INTEN_FLIEN10_Pos) /*!< GPIO_T::INTEN: FLIEN10 Mask */ + +#define GPIO_INTEN_FLIEN11_Pos (11) /*!< GPIO_T::INTEN: FLIEN11 Position */ +#define GPIO_INTEN_FLIEN11_Msk (0x1ul << GPIO_INTEN_FLIEN11_Pos) /*!< GPIO_T::INTEN: FLIEN11 Mask */ + +#define GPIO_INTEN_FLIEN12_Pos (12) /*!< GPIO_T::INTEN: FLIEN12 Position */ +#define GPIO_INTEN_FLIEN12_Msk (0x1ul << GPIO_INTEN_FLIEN12_Pos) /*!< GPIO_T::INTEN: FLIEN12 Mask */ + +#define GPIO_INTEN_FLIEN13_Pos (13) /*!< GPIO_T::INTEN: FLIEN13 Position */ +#define GPIO_INTEN_FLIEN13_Msk (0x1ul << GPIO_INTEN_FLIEN13_Pos) /*!< GPIO_T::INTEN: FLIEN13 Mask */ + +#define GPIO_INTEN_FLIEN14_Pos (14) /*!< GPIO_T::INTEN: FLIEN14 Position */ +#define GPIO_INTEN_FLIEN14_Msk (0x1ul << GPIO_INTEN_FLIEN14_Pos) /*!< GPIO_T::INTEN: FLIEN14 Mask */ + +#define GPIO_INTEN_FLIEN15_Pos (15) /*!< GPIO_T::INTEN: FLIEN15 Position */ +#define GPIO_INTEN_FLIEN15_Msk (0x1ul << GPIO_INTEN_FLIEN15_Pos) /*!< GPIO_T::INTEN: FLIEN15 Mask */ + +#define GPIO_INTEN_RHIEN0_Pos (16) /*!< GPIO_T::INTEN: RHIEN0 Position */ +#define GPIO_INTEN_RHIEN0_Msk (0x1ul << GPIO_INTEN_RHIEN0_Pos) /*!< GPIO_T::INTEN: RHIEN0 Mask */ + +#define GPIO_INTEN_RHIEN1_Pos (17) /*!< GPIO_T::INTEN: RHIEN1 Position */ +#define GPIO_INTEN_RHIEN1_Msk (0x1ul << GPIO_INTEN_RHIEN1_Pos) /*!< GPIO_T::INTEN: RHIEN1 Mask */ + +#define GPIO_INTEN_RHIEN2_Pos (18) /*!< GPIO_T::INTEN: RHIEN2 Position */ +#define GPIO_INTEN_RHIEN2_Msk (0x1ul << GPIO_INTEN_RHIEN2_Pos) /*!< GPIO_T::INTEN: RHIEN2 Mask */ + +#define GPIO_INTEN_RHIEN3_Pos (19) /*!< GPIO_T::INTEN: RHIEN3 Position */ +#define GPIO_INTEN_RHIEN3_Msk (0x1ul << GPIO_INTEN_RHIEN3_Pos) /*!< GPIO_T::INTEN: RHIEN3 Mask */ + +#define GPIO_INTEN_RHIEN4_Pos (20) /*!< GPIO_T::INTEN: RHIEN4 Position */ +#define GPIO_INTEN_RHIEN4_Msk (0x1ul << GPIO_INTEN_RHIEN4_Pos) /*!< GPIO_T::INTEN: RHIEN4 Mask */ + +#define GPIO_INTEN_RHIEN5_Pos (21) /*!< GPIO_T::INTEN: RHIEN5 Position */ +#define GPIO_INTEN_RHIEN5_Msk (0x1ul << GPIO_INTEN_RHIEN5_Pos) /*!< GPIO_T::INTEN: RHIEN5 Mask */ + +#define GPIO_INTEN_RHIEN6_Pos (22) /*!< GPIO_T::INTEN: RHIEN6 Position */ +#define GPIO_INTEN_RHIEN6_Msk (0x1ul << GPIO_INTEN_RHIEN6_Pos) /*!< GPIO_T::INTEN: RHIEN6 Mask */ + +#define GPIO_INTEN_RHIEN7_Pos (23) /*!< GPIO_T::INTEN: RHIEN7 Position */ +#define GPIO_INTEN_RHIEN7_Msk (0x1ul << GPIO_INTEN_RHIEN7_Pos) /*!< GPIO_T::INTEN: RHIEN7 Mask */ + +#define GPIO_INTEN_RHIEN8_Pos (24) /*!< GPIO_T::INTEN: RHIEN8 Position */ +#define GPIO_INTEN_RHIEN8_Msk (0x1ul << GPIO_INTEN_RHIEN8_Pos) /*!< GPIO_T::INTEN: RHIEN8 Mask */ + +#define GPIO_INTEN_RHIEN9_Pos (25) /*!< GPIO_T::INTEN: RHIEN9 Position */ +#define GPIO_INTEN_RHIEN9_Msk (0x1ul << GPIO_INTEN_RHIEN9_Pos) /*!< GPIO_T::INTEN: RHIEN9 Mask */ + +#define GPIO_INTEN_RHIEN10_Pos (26) /*!< GPIO_T::INTEN: RHIEN10 Position */ +#define GPIO_INTEN_RHIEN10_Msk (0x1ul << GPIO_INTEN_RHIEN10_Pos) /*!< GPIO_T::INTEN: RHIEN10 Mask */ + +#define GPIO_INTEN_RHIEN11_Pos (27) /*!< GPIO_T::INTEN: RHIEN11 Position */ +#define GPIO_INTEN_RHIEN11_Msk (0x1ul << GPIO_INTEN_RHIEN11_Pos) /*!< GPIO_T::INTEN: RHIEN11 Mask */ + +#define GPIO_INTEN_RHIEN12_Pos (28) /*!< GPIO_T::INTEN: RHIEN12 Position */ +#define GPIO_INTEN_RHIEN12_Msk (0x1ul << GPIO_INTEN_RHIEN12_Pos) /*!< GPIO_T::INTEN: RHIEN12 Mask */ + +#define GPIO_INTEN_RHIEN13_Pos (29) /*!< GPIO_T::INTEN: RHIEN13 Position */ +#define GPIO_INTEN_RHIEN13_Msk (0x1ul << GPIO_INTEN_RHIEN13_Pos) /*!< GPIO_T::INTEN: RHIEN13 Mask */ + +#define GPIO_INTEN_RHIEN14_Pos (30) /*!< GPIO_T::INTEN: RHIEN14 Position */ +#define GPIO_INTEN_RHIEN14_Msk (0x1ul << GPIO_INTEN_RHIEN14_Pos) /*!< GPIO_T::INTEN: RHIEN14 Mask */ + +#define GPIO_INTEN_RHIEN15_Pos (31) /*!< GPIO_T::INTEN: RHIEN15 Position */ +#define GPIO_INTEN_RHIEN15_Msk (0x1ul << GPIO_INTEN_RHIEN15_Pos) /*!< GPIO_T::INTEN: RHIEN15 Mask */ + +#define GPIO_INTSRC_INTSRC0_Pos (0) /*!< GPIO_T::INTSRC: INTSRC0 Position */ +#define GPIO_INTSRC_INTSRC0_Msk (0x1ul << GPIO_INTSRC_INTSRC0_Pos) /*!< GPIO_T::INTSRC: INTSRC0 Mask */ + +#define GPIO_INTSRC_INTSRC1_Pos (1) /*!< GPIO_T::INTSRC: INTSRC1 Position */ +#define GPIO_INTSRC_INTSRC1_Msk (0x1ul << GPIO_INTSRC_INTSRC1_Pos) /*!< GPIO_T::INTSRC: INTSRC1 Mask */ + +#define GPIO_INTSRC_INTSRC2_Pos (2) /*!< GPIO_T::INTSRC: INTSRC2 Position */ +#define GPIO_INTSRC_INTSRC2_Msk (0x1ul << GPIO_INTSRC_INTSRC2_Pos) /*!< GPIO_T::INTSRC: INTSRC2 Mask */ + +#define GPIO_INTSRC_INTSRC3_Pos (3) /*!< GPIO_T::INTSRC: INTSRC3 Position */ +#define GPIO_INTSRC_INTSRC3_Msk (0x1ul << GPIO_INTSRC_INTSRC3_Pos) /*!< GPIO_T::INTSRC: INTSRC3 Mask */ + +#define GPIO_INTSRC_INTSRC4_Pos (4) /*!< GPIO_T::INTSRC: INTSRC4 Position */ +#define GPIO_INTSRC_INTSRC4_Msk (0x1ul << GPIO_INTSRC_INTSRC4_Pos) /*!< GPIO_T::INTSRC: INTSRC4 Mask */ + +#define GPIO_INTSRC_INTSRC5_Pos (5) /*!< GPIO_T::INTSRC: INTSRC5 Position */ +#define GPIO_INTSRC_INTSRC5_Msk (0x1ul << GPIO_INTSRC_INTSRC5_Pos) /*!< GPIO_T::INTSRC: INTSRC5 Mask */ + +#define GPIO_INTSRC_INTSRC6_Pos (6) /*!< GPIO_T::INTSRC: INTSRC6 Position */ +#define GPIO_INTSRC_INTSRC6_Msk (0x1ul << GPIO_INTSRC_INTSRC6_Pos) /*!< GPIO_T::INTSRC: INTSRC6 Mask */ + +#define GPIO_INTSRC_INTSRC7_Pos (7) /*!< GPIO_T::INTSRC: INTSRC7 Position */ +#define GPIO_INTSRC_INTSRC7_Msk (0x1ul << GPIO_INTSRC_INTSRC7_Pos) /*!< GPIO_T::INTSRC: INTSRC7 Mask */ + +#define GPIO_INTSRC_INTSRC8_Pos (8) /*!< GPIO_T::INTSRC: INTSRC8 Position */ +#define GPIO_INTSRC_INTSRC8_Msk (0x1ul << GPIO_INTSRC_INTSRC8_Pos) /*!< GPIO_T::INTSRC: INTSRC8 Mask */ + +#define GPIO_INTSRC_INTSRC9_Pos (9) /*!< GPIO_T::INTSRC: INTSRC9 Position */ +#define GPIO_INTSRC_INTSRC9_Msk (0x1ul << GPIO_INTSRC_INTSRC9_Pos) /*!< GPIO_T::INTSRC: INTSRC9 Mask */ + +#define GPIO_INTSRC_INTSRC10_Pos (10) /*!< GPIO_T::INTSRC: INTSRC10 Position */ +#define GPIO_INTSRC_INTSRC10_Msk (0x1ul << GPIO_INTSRC_INTSRC10_Pos) /*!< GPIO_T::INTSRC: INTSRC10 Mask */ + +#define GPIO_INTSRC_INTSRC11_Pos (11) /*!< GPIO_T::INTSRC: INTSRC11 Position */ +#define GPIO_INTSRC_INTSRC11_Msk (0x1ul << GPIO_INTSRC_INTSRC11_Pos) /*!< GPIO_T::INTSRC: INTSRC11 Mask */ + +#define GPIO_INTSRC_INTSRC12_Pos (12) /*!< GPIO_T::INTSRC: INTSRC12 Position */ +#define GPIO_INTSRC_INTSRC12_Msk (0x1ul << GPIO_INTSRC_INTSRC12_Pos) /*!< GPIO_T::INTSRC: INTSRC12 Mask */ + +#define GPIO_INTSRC_INTSRC13_Pos (13) /*!< GPIO_T::INTSRC: INTSRC13 Position */ +#define GPIO_INTSRC_INTSRC13_Msk (0x1ul << GPIO_INTSRC_INTSRC13_Pos) /*!< GPIO_T::INTSRC: INTSRC13 Mask */ + +#define GPIO_INTSRC_INTSRC14_Pos (14) /*!< GPIO_T::INTSRC: INTSRC14 Position */ +#define GPIO_INTSRC_INTSRC14_Msk (0x1ul << GPIO_INTSRC_INTSRC14_Pos) /*!< GPIO_T::INTSRC: INTSRC14 Mask */ + +#define GPIO_INTSRC_INTSRC15_Pos (15) /*!< GPIO_T::INTSRC: INTSRC15 Position */ +#define GPIO_INTSRC_INTSRC15_Msk (0x1ul << GPIO_INTSRC_INTSRC15_Pos) /*!< GPIO_T::INTSRC: INTSRC15 Mask */ + +#define GPIO_SMTEN_SMTEN0_Pos (0) /*!< GPIO_T::SMTEN: SMTEN0 Position */ +#define GPIO_SMTEN_SMTEN0_Msk (0x1ul << GPIO_SMTEN_SMTEN0_Pos) /*!< GPIO_T::SMTEN: SMTEN0 Mask */ + +#define GPIO_SMTEN_SMTEN1_Pos (1) /*!< GPIO_T::SMTEN: SMTEN1 Position */ +#define GPIO_SMTEN_SMTEN1_Msk (0x1ul << GPIO_SMTEN_SMTEN1_Pos) /*!< GPIO_T::SMTEN: SMTEN1 Mask */ + +#define GPIO_SMTEN_SMTEN2_Pos (2) /*!< GPIO_T::SMTEN: SMTEN2 Position */ +#define GPIO_SMTEN_SMTEN2_Msk (0x1ul << GPIO_SMTEN_SMTEN2_Pos) /*!< GPIO_T::SMTEN: SMTEN2 Mask */ + +#define GPIO_SMTEN_SMTEN3_Pos (3) /*!< GPIO_T::SMTEN: SMTEN3 Position */ +#define GPIO_SMTEN_SMTEN3_Msk (0x1ul << GPIO_SMTEN_SMTEN3_Pos) /*!< GPIO_T::SMTEN: SMTEN3 Mask */ + +#define GPIO_SMTEN_SMTEN4_Pos (4) /*!< GPIO_T::SMTEN: SMTEN4 Position */ +#define GPIO_SMTEN_SMTEN4_Msk (0x1ul << GPIO_SMTEN_SMTEN4_Pos) /*!< GPIO_T::SMTEN: SMTEN4 Mask */ + +#define GPIO_SMTEN_SMTEN5_Pos (5) /*!< GPIO_T::SMTEN: SMTEN5 Position */ +#define GPIO_SMTEN_SMTEN5_Msk (0x1ul << GPIO_SMTEN_SMTEN5_Pos) /*!< GPIO_T::SMTEN: SMTEN5 Mask */ + +#define GPIO_SMTEN_SMTEN6_Pos (6) /*!< GPIO_T::SMTEN: SMTEN6 Position */ +#define GPIO_SMTEN_SMTEN6_Msk (0x1ul << GPIO_SMTEN_SMTEN6_Pos) /*!< GPIO_T::SMTEN: SMTEN6 Mask */ + +#define GPIO_SMTEN_SMTEN7_Pos (7) /*!< GPIO_T::SMTEN: SMTEN7 Position */ +#define GPIO_SMTEN_SMTEN7_Msk (0x1ul << GPIO_SMTEN_SMTEN7_Pos) /*!< GPIO_T::SMTEN: SMTEN7 Mask */ + +#define GPIO_SMTEN_SMTEN8_Pos (8) /*!< GPIO_T::SMTEN: SMTEN8 Position */ +#define GPIO_SMTEN_SMTEN8_Msk (0x1ul << GPIO_SMTEN_SMTEN8_Pos) /*!< GPIO_T::SMTEN: SMTEN8 Mask */ + +#define GPIO_SMTEN_SMTEN9_Pos (9) /*!< GPIO_T::SMTEN: SMTEN9 Position */ +#define GPIO_SMTEN_SMTEN9_Msk (0x1ul << GPIO_SMTEN_SMTEN9_Pos) /*!< GPIO_T::SMTEN: SMTEN9 Mask */ + +#define GPIO_SMTEN_SMTEN10_Pos (10) /*!< GPIO_T::SMTEN: SMTEN10 Position */ +#define GPIO_SMTEN_SMTEN10_Msk (0x1ul << GPIO_SMTEN_SMTEN10_Pos) /*!< GPIO_T::SMTEN: SMTEN10 Mask */ + +#define GPIO_SMTEN_SMTEN11_Pos (11) /*!< GPIO_T::SMTEN: SMTEN11 Position */ +#define GPIO_SMTEN_SMTEN11_Msk (0x1ul << GPIO_SMTEN_SMTEN11_Pos) /*!< GPIO_T::SMTEN: SMTEN11 Mask */ + +#define GPIO_SMTEN_SMTEN12_Pos (12) /*!< GPIO_T::SMTEN: SMTEN12 Position */ +#define GPIO_SMTEN_SMTEN12_Msk (0x1ul << GPIO_SMTEN_SMTEN12_Pos) /*!< GPIO_T::SMTEN: SMTEN12 Mask */ + +#define GPIO_SMTEN_SMTEN13_Pos (13) /*!< GPIO_T::SMTEN: SMTEN13 Position */ +#define GPIO_SMTEN_SMTEN13_Msk (0x1ul << GPIO_SMTEN_SMTEN13_Pos) /*!< GPIO_T::SMTEN: SMTEN13 Mask */ + +#define GPIO_SMTEN_SMTEN14_Pos (14) /*!< GPIO_T::SMTEN: SMTEN14 Position */ +#define GPIO_SMTEN_SMTEN14_Msk (0x1ul << GPIO_SMTEN_SMTEN14_Pos) /*!< GPIO_T::SMTEN: SMTEN14 Mask */ + +#define GPIO_SMTEN_SMTEN15_Pos (15) /*!< GPIO_T::SMTEN: SMTEN15 Position */ +#define GPIO_SMTEN_SMTEN15_Msk (0x1ul << GPIO_SMTEN_SMTEN15_Pos) /*!< GPIO_T::SMTEN: SMTEN15 Mask */ + +#define GPIO_SLEWCTL_HSREN0_Pos (0) /*!< GPIO_T::SLEWCTL: HSREN0 Position */ +#define GPIO_SLEWCTL_HSREN0_Msk (0x3ul << GPIO_SLEWCTL_HSREN0_Pos) /*!< GPIO_T::SLEWCTL: HSREN0 Mask */ + +#define GPIO_SLEWCTL_HSREN1_Pos (2) /*!< GPIO_T::SLEWCTL: HSREN1 Position */ +#define GPIO_SLEWCTL_HSREN1_Msk (0x3ul << GPIO_SLEWCTL_HSREN1_Pos) /*!< GPIO_T::SLEWCTL: HSREN1 Mask */ + +#define GPIO_SLEWCTL_HSREN2_Pos (4) /*!< GPIO_T::SLEWCTL: HSREN2 Position */ +#define GPIO_SLEWCTL_HSREN2_Msk (0x3ul << GPIO_SLEWCTL_HSREN2_Pos) /*!< GPIO_T::SLEWCTL: HSREN2 Mask */ + +#define GPIO_SLEWCTL_HSREN3_Pos (6) /*!< GPIO_T::SLEWCTL: HSREN3 Position */ +#define GPIO_SLEWCTL_HSREN3_Msk (0x3ul << GPIO_SLEWCTL_HSREN3_Pos) /*!< GPIO_T::SLEWCTL: HSREN3 Mask */ + +#define GPIO_SLEWCTL_HSREN4_Pos (8) /*!< GPIO_T::SLEWCTL: HSREN4 Position */ +#define GPIO_SLEWCTL_HSREN4_Msk (0x3ul << GPIO_SLEWCTL_HSREN4_Pos) /*!< GPIO_T::SLEWCTL: HSREN4 Mask */ + +#define GPIO_SLEWCTL_HSREN5_Pos (10) /*!< GPIO_T::SLEWCTL: HSREN5 Position */ +#define GPIO_SLEWCTL_HSREN5_Msk (0x3ul << GPIO_SLEWCTL_HSREN5_Pos) /*!< GPIO_T::SLEWCTL: HSREN5 Mask */ + +#define GPIO_SLEWCTL_HSREN6_Pos (12) /*!< GPIO_T::SLEWCTL: HSREN6 Position */ +#define GPIO_SLEWCTL_HSREN6_Msk (0x3ul << GPIO_SLEWCTL_HSREN6_Pos) /*!< GPIO_T::SLEWCTL: HSREN6 Mask */ + +#define GPIO_SLEWCTL_HSREN7_Pos (14) /*!< GPIO_T::SLEWCTL: HSREN7 Position */ +#define GPIO_SLEWCTL_HSREN7_Msk (0x3ul << GPIO_SLEWCTL_HSREN7_Pos) /*!< GPIO_T::SLEWCTL: HSREN7 Mask */ + +#define GPIO_SLEWCTL_HSREN8_Pos (16) /*!< GPIO_T::SLEWCTL: HSREN8 Position */ +#define GPIO_SLEWCTL_HSREN8_Msk (0x3ul << GPIO_SLEWCTL_HSREN8_Pos) /*!< GPIO_T::SLEWCTL: HSREN8 Mask */ + +#define GPIO_SLEWCTL_HSREN9_Pos (18) /*!< GPIO_T::SLEWCTL: HSREN9 Position */ +#define GPIO_SLEWCTL_HSREN9_Msk (0x3ul << GPIO_SLEWCTL_HSREN9_Pos) /*!< GPIO_T::SLEWCTL: HSREN9 Mask */ + +#define GPIO_SLEWCTL_HSREN10_Pos (20) /*!< GPIO_T::SLEWCTL: HSREN10 Position */ +#define GPIO_SLEWCTL_HSREN10_Msk (0x3ul << GPIO_SLEWCTL_HSREN10_Pos) /*!< GPIO_T::SLEWCTL: HSREN10 Mask */ + +#define GPIO_SLEWCTL_HSREN11_Pos (22) /*!< GPIO_T::SLEWCTL: HSREN11 Position */ +#define GPIO_SLEWCTL_HSREN11_Msk (0x3ul << GPIO_SLEWCTL_HSREN11_Pos) /*!< GPIO_T::SLEWCTL: HSREN11 Mask */ + +#define GPIO_SLEWCTL_HSREN12_Pos (24) /*!< GPIO_T::SLEWCTL: HSREN12 Position */ +#define GPIO_SLEWCTL_HSREN12_Msk (0x3ul << GPIO_SLEWCTL_HSREN12_Pos) /*!< GPIO_T::SLEWCTL: HSREN12 Mask */ + +#define GPIO_SLEWCTL_HSREN13_Pos (26) /*!< GPIO_T::SLEWCTL: HSREN13 Position */ +#define GPIO_SLEWCTL_HSREN13_Msk (0x3ul << GPIO_SLEWCTL_HSREN13_Pos) /*!< GPIO_T::SLEWCTL: HSREN13 Mask */ + +#define GPIO_SLEWCTL_HSREN14_Pos (28) /*!< GPIO_T::SLEWCTL: HSREN14 Position */ +#define GPIO_SLEWCTL_HSREN14_Msk (0x3ul << GPIO_SLEWCTL_HSREN14_Pos) /*!< GPIO_T::SLEWCTL: HSREN14 Mask */ + +#define GPIO_SLEWCTL_HSREN15_Pos (30) /*!< GPIO_T::SLEWCTL: HSREN15 Position */ +#define GPIO_SLEWCTL_HSREN15_Msk (0x3ul << GPIO_SLEWCTL_HSREN15_Pos) /*!< GPIO_T::SLEWCTL: HSREN15 Mask */ + +#define GPIO_PUSEL_PUSEL0_Pos (0) /*!< GPIO_T::PUSEL: PUSEL0 Position */ +#define GPIO_PUSEL_PUSEL0_Msk (0x3ul << GPIO_PUSEL_PUSEL0_Pos) /*!< GPIO_T::PUSEL: PUSEL0 Mask */ + +#define GPIO_PUSEL_PUSEL1_Pos (2) /*!< GPIO_T::PUSEL: PUSEL1 Position */ +#define GPIO_PUSEL_PUSEL1_Msk (0x3ul << GPIO_PUSEL_PUSEL1_Pos) /*!< GPIO_T::PUSEL: PUSEL1 Mask */ + +#define GPIO_PUSEL_PUSEL2_Pos (4) /*!< GPIO_T::PUSEL: PUSEL2 Position */ +#define GPIO_PUSEL_PUSEL2_Msk (0x3ul << GPIO_PUSEL_PUSEL2_Pos) /*!< GPIO_T::PUSEL: PUSEL2 Mask */ + +#define GPIO_PUSEL_PUSEL3_Pos (6) /*!< GPIO_T::PUSEL: PUSEL3 Position */ +#define GPIO_PUSEL_PUSEL3_Msk (0x3ul << GPIO_PUSEL_PUSEL3_Pos) /*!< GPIO_T::PUSEL: PUSEL3 Mask */ + +#define GPIO_PUSEL_PUSEL4_Pos (8) /*!< GPIO_T::PUSEL: PUSEL4 Position */ +#define GPIO_PUSEL_PUSEL4_Msk (0x3ul << GPIO_PUSEL_PUSEL4_Pos) /*!< GPIO_T::PUSEL: PUSEL4 Mask */ + +#define GPIO_PUSEL_PUSEL5_Pos (10) /*!< GPIO_T::PUSEL: PUSEL5 Position */ +#define GPIO_PUSEL_PUSEL5_Msk (0x3ul << GPIO_PUSEL_PUSEL5_Pos) /*!< GPIO_T::PUSEL: PUSEL5 Mask */ + +#define GPIO_PUSEL_PUSEL6_Pos (12) /*!< GPIO_T::PUSEL: PUSEL6 Position */ +#define GPIO_PUSEL_PUSEL6_Msk (0x3ul << GPIO_PUSEL_PUSEL6_Pos) /*!< GPIO_T::PUSEL: PUSEL6 Mask */ + +#define GPIO_PUSEL_PUSEL7_Pos (14) /*!< GPIO_T::PUSEL: PUSEL7 Position */ +#define GPIO_PUSEL_PUSEL7_Msk (0x3ul << GPIO_PUSEL_PUSEL7_Pos) /*!< GPIO_T::PUSEL: PUSEL7 Mask */ + +#define GPIO_PUSEL_PUSEL8_Pos (16) /*!< GPIO_T::PUSEL: PUSEL8 Position */ +#define GPIO_PUSEL_PUSEL8_Msk (0x3ul << GPIO_PUSEL_PUSEL8_Pos) /*!< GPIO_T::PUSEL: PUSEL8 Mask */ + +#define GPIO_PUSEL_PUSEL9_Pos (18) /*!< GPIO_T::PUSEL: PUSEL9 Position */ +#define GPIO_PUSEL_PUSEL9_Msk (0x3ul << GPIO_PUSEL_PUSEL9_Pos) /*!< GPIO_T::PUSEL: PUSEL9 Mask */ + +#define GPIO_PUSEL_PUSEL10_Pos (20) /*!< GPIO_T::PUSEL: PUSEL10 Position */ +#define GPIO_PUSEL_PUSEL10_Msk (0x3ul << GPIO_PUSEL_PUSEL10_Pos) /*!< GPIO_T::PUSEL: PUSEL10 Mask */ + +#define GPIO_PUSEL_PUSEL11_Pos (22) /*!< GPIO_T::PUSEL: PUSEL11 Position */ +#define GPIO_PUSEL_PUSEL11_Msk (0x3ul << GPIO_PUSEL_PUSEL11_Pos) /*!< GPIO_T::PUSEL: PUSEL11 Mask */ + +#define GPIO_PUSEL_PUSEL12_Pos (24) /*!< GPIO_T::PUSEL: PUSEL12 Position */ +#define GPIO_PUSEL_PUSEL12_Msk (0x3ul << GPIO_PUSEL_PUSEL12_Pos) /*!< GPIO_T::PUSEL: PUSEL12 Mask */ + +#define GPIO_PUSEL_PUSEL13_Pos (26) /*!< GPIO_T::PUSEL: PUSEL13 Position */ +#define GPIO_PUSEL_PUSEL13_Msk (0x3ul << GPIO_PUSEL_PUSEL13_Pos) /*!< GPIO_T::PUSEL: PUSEL13 Mask */ + +#define GPIO_PUSEL_PUSEL14_Pos (28) /*!< GPIO_T::PUSEL: PUSEL14 Position */ +#define GPIO_PUSEL_PUSEL14_Msk (0x3ul << GPIO_PUSEL_PUSEL14_Pos) /*!< GPIO_T::PUSEL: PUSEL14 Mask */ + +#define GPIO_PUSEL_PUSEL15_Pos (30) /*!< GPIO_T::PUSEL: PUSEL15 Position */ +#define GPIO_PUSEL_PUSEL15_Msk (0x3ul << GPIO_PUSEL_PUSEL15_Pos) /*!< GPIO_T::PUSEL: PUSEL15 Mask */ + +#define GPIO_DBCTL_DBCLKSEL_Pos (0) /*!< GPIO_T::DBCTL: DBCLKSEL Position */ +#define GPIO_DBCTL_DBCLKSEL_Msk (0xful << GPIO_DBCTL_DBCLKSEL_Pos) /*!< GPIO_T::DBCTL: DBCLKSEL Mask */ + +#define GPIO_DBCTL_DBCLKSRC_Pos (4) /*!< GPIO_T::DBCTL: DBCLKSRC Position */ +#define GPIO_DBCTL_DBCLKSRC_Msk (0x1ul << GPIO_DBCTL_DBCLKSRC_Pos) /*!< GPIO_T::DBCTL: DBCLKSRC Mask */ + +#define GPIO_DBCTL_ICLKONA_Pos (16) /*!< GPIO_T::DBCTL: ICLKONA Position */ +#define GPIO_DBCTL_ICLKONA_Msk (0x1ul << GPIO_DBCTL_ICLKONA_Pos) /*!< GPIO_T::DBCTL: ICLKONA Mask */ + +#define GPIO_DBCTL_ICLKONB_Pos (17) /*!< GPIO_T::DBCTL: ICLKONB Position */ +#define GPIO_DBCTL_ICLKONB_Msk (0x1ul << GPIO_DBCTL_ICLKONB_Pos) /*!< GPIO_T::DBCTL: ICLKONB Mask */ + +#define GPIO_DBCTL_ICLKONC_Pos (18) /*!< GPIO_T::DBCTL: ICLKONC Position */ +#define GPIO_DBCTL_ICLKONC_Msk (0x1ul << GPIO_DBCTL_ICLKONC_Pos) /*!< GPIO_T::DBCTL: ICLKONC Mask */ + +#define GPIO_DBCTL_ICLKOND_Pos (19) /*!< GPIO_T::DBCTL: ICLKOND Position */ +#define GPIO_DBCTL_ICLKOND_Msk (0x1ul << GPIO_DBCTL_ICLKOND_Pos) /*!< GPIO_T::DBCTL: ICLKOND Mask */ + +#define GPIO_DBCTL_ICLKONE_Pos (20) /*!< GPIO_T::DBCTL: ICLKONE Position */ +#define GPIO_DBCTL_ICLKONE_Msk (0x1ul << GPIO_DBCTL_ICLKONE_Pos) /*!< GPIO_T::DBCTL: ICLKONE Mask */ + +#define GPIO_DBCTL_ICLKONF_Pos (21) /*!< GPIO_T::DBCTL: ICLKONF Position */ +#define GPIO_DBCTL_ICLKONF_Msk (0x1ul << GPIO_DBCTL_ICLKONF_Pos) /*!< GPIO_T::DBCTL: ICLKONF Mask */ + + +/**@}*/ /* GPIO_CONST */ +/**@}*/ /* end of GPIO register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __GPIO_REG_H__ */ \ No newline at end of file diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/i2c_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/i2c_reg.h new file mode 100644 index 00000000000..0d172723250 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/i2c_reg.h @@ -0,0 +1,706 @@ +/**************************************************************************//** + * @file i2c_reg.h + * @version V1.00 + * @brief I2C register definition header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __I2C_REG_H__ +#define __I2C_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/*---------------------- Inter-IC Bus Controller -------------------------*/ +/** + @addtogroup I2C Inter-IC Bus Controller (I2C) + Memory Mapped Structure for I2C Controller +@{ */ + +typedef struct +{ + + + /** + * @var I2C_T::CTL0 + * Offset: 0x00 I2C Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2] |AA |Assert Acknowledge Control + * | | |When AA =1 prior to address or data is received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter + * | | |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line + * |[3] |SI |I2C Interrupt Flag + * | | |When a new I2C state is present in the I2C_STATUS0 register, the SI flag is set by hardware + * | | |If bit INTEN (I2C_CTL0 [7]) is set, the I2C interrupt is requested + * | | |SI must be cleared by software. + * | | |Clear SI by writing 1 to this bit. + * | | |For ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer. + * |[4] |STO |I2C STOP Control + * | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected + * | | |This bit will be cleared by hardware automatically. + * |[5] |STA |I2C START Control + * | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. + * |[6] |I2CEN |I2C Controller Enable Bit + * | | |Set to enable I2C serial function controller + * | | |When I2CEN=1 the I2C serial function enable + * | | |The multi-function pin function must set to SDA, and SCL of I2C function first. + * | | |0 = I2C controller Disabled. + * | | |1 = I2C controller Enabled. + * |[7] |INTEN |Enable Interrupt + * | | |0 = I2C interrupt Disabled. + * | | |1 = I2C interrupt Enabled. + * @var I2C_T::DAT + * Offset: 0x08 I2C Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DAT |I2C Data + * | | |Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port. + * @var I2C_T::STATUS0 + * Offset: 0x0C I2C Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |STATUS |I2C Status + * | | |The three least significant bits are always 0 + * | | |The five most significant bits contain the status code + * | | |There are 28 possible status codes + * | | |When the content of I2C_STATUS0 is F8H, no serial interrupt is requested + * | | |Others I2C_STATUS0 values correspond to defined I2C states + * | | |When each of these states is entered, a status interrupt is requested (SI = 1) + * | | |A valid status code is present in I2C_STATUS0 one cycle after SI is set by hardware and is still present one cycle after SI has been reset by software + * | | |In addition, states 00H stands for a Bus Error + * | | |A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame + * | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit. + * @var I2C_T::CLKDIV + * Offset: 0x10 I2C Clock Divided Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |DIVIDER |I2C Clock Divided + * | | |Indicates the I2C clock rate: Data Baud Rate of I2C = (system clock) / (4x (I2C_CLKDIV+1)). + * | | |Note: The minimum value of I2C_CLKDIV is 4. + * @var I2C_T::TOCTL + * Offset: 0x14 I2C Time-out Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TOIF |Time-out Flag + * | | |This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1. + * | | |Note: Software can write 1 to clear this bit. + * |[1] |TOCDIV4 |Time-out Counter Input Clock Divided by 4 + * | | |When enabled, the time-out period is extended 4 times. + * | | |0 = Time-out period is extend 4 times Disabled. + * | | |1 = Time-out period is extend 4 times Enabled. + * |[2] |TOCEN |Time-out Counter Enable Bit + * | | |When enabled, the 14-bit time-out counter will start counting when SI is cleared + * | | |Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared. + * | | |0 = Time-out counter Disabled. + * | | |1 = Time-out counter Enabled. + * @var I2C_T::ADDR0~3 + * Offset: 0x04/0x18/0x1x/0x20 I2C Slave Address0~3 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GC |General Call Function + * | | |0 = General Call Function Disabled. + * | | |1 = General Call Function Enabled. + * |[10:1] |ADDR |I2C Address + * | | |The content of this register is irrelevant when I2C is in Master mode + * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address + * | | |The I2C hardware will react if either of the address is matched. + * | | |Note: When software set 10'h000, the address can not be used. + * @var I2C_T::ADDRMSK0~3 + * Offset: 0x24/0x28/0x2C/0x30 I2C Slave Address Mask0~3 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:1] |ADDRMSK |I2C Address Mask + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |I2C bus controllers support multiple address recognition with four address mask register + * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care + * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. + * | | |Note: The wake-up function can not use address mask. + * @var I2C_T::WKCTL + * Offset: 0x3C I2C Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |I2C Wake-up Enable Bit + * | | |0 = I2C wake-up function Disabled. + * | | |1 = I2C wake-up function Enabled. + * |[7] |NHDBUSEN |I2C No Hold BUS Enable Bit + * | | |0 = I2C hold bus after wake-up. + * | | |1 = I2C don't hold bus after wake-up. + * | | |Note: I2C controller could response when WKIF event is not clear, it may cause error data transmitted or received + * | | |If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again. + * @var I2C_T::WKSTS + * Offset: 0x40 I2C Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKIF |I2C Wake-up Flag + * | | |When chip is woken up from Power-down mode by I2C, this bit is set to 1 + * | | |Software can write 1 to clear this bit. + * |[1] |WKAKDONE |Wakeup Address Frame Acknowledge Bit Done + * | | |0 = The ACK bit cycle of address match frame isn't done. + * | | |1 = The ACK bit cycle of address match frame is done in power-down. + * | | |Note: This bit can't release WKIF. Software can write 1 to clear this bit. + * |[2] |WRSTSWK |Read/Write Status Bit in Address Wakeup Frame (Read Only) + * | | |0 = Write command be record on the address match wakeup frame. + * | | |1 = Read command be record on the address match wakeup frame. + * | | |Note: This bit will be cleared when software can write 1 to WKAKDONE (I2C_WKSTS[1]) bit. + * @var I2C_T::CTL1 + * Offset: 0x44 I2C Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TXPDMAEN |PDMA Transmit Channel Available + * | | |0 = Transmit PDMA function Disabled. + * | | |1 = Transmit PDMA function Enabled. + * |[1] |RXPDMAEN |PDMA Receive Channel Available + * | | |0 = Receive PDMA function Disabled. + * | | |1 = Receive PDMA function Enabled. + * |[2] |PDMARST |PDMA Reset + * | | |0 = No effect. + * | | |1 = Reset the I2C request to PDMA. + * |[3] |OVRIEN |I2C over Run Interrupt Control Bit + * | | |Setting OVRIEN to logic 1 will send a interrupt to system when the TWOFF bit is enabled and there is over run event in received buffer. + * |[4] |UDRIEN |I2C Under Run Interrupt Control Bit + * | | |Setting UDRIEN to logic 1 will send a interrupt to system when the TWOFF bit is enabled and there is under run event happened in transmitted buffer. + * |[5] |TWOBUFEN |Two-level BUFFER Enable Bit + * | | |0 = Two-level buffer Disabled. + * | | |1 = Two-level buffer Enabled. + * | | |Set to enable the two-level buffer for I2C transmitted or received buffer. + * | | |It is used to improve the performance of the I2C bus. + * | | |If this bit is set = 1, the control bit of STA for repeat start or STO bit should be set after the current SI is cleared. + * | | |For example: if there are 4 data shall be transmitted and then stop it. + * | | |The STO bit shall be set after the 3rd data's SI event being clear. + * | | |In this time, the 4th data can be transmitted and the I2C stop after the 4th data transmission done. + * |[6] |BUFRST |Two-level BUFFER Reset + * | | |0 = No effect. + * | | |1 = Reset the related counters, two-level buffer state machine, and the content of data buffer. + * |[7] |NSTRETCH |No Stretch on the I2C Bus + * | | |0 = The I2C SCL bus is stretched by hardware if the SI is not cleared in master mode. + * | | |1 = The I2C SCL bus is not stretched by hardware if the SI is not cleared in master mode. + * |[8] |PDMASTR |PDMA Stretch Bit + * | | |0 = I2C send STOP automatically after PDMA transfer done. (only master TX) + * | | |1 = I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared + * | | |(only master TX) + * |[9] |ADDR10EN |Address 10-bit Function Enable Bit + * | | |0 = Address match 10-bit function Disabled. + * | | |1 = Address match 10-bit function Enabled. + * @var I2C_T::STATUS1 + * Offset: 0x48 I2C Status Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADMAT0 |I2C Address 0 Match Status + * | | |When address 0 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * |[1] |ADMAT1 |I2C Address 1 Match Status + * | | |When address 1 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * |[2] |ADMAT2 |I2C Address 2 Match Status + * | | |When address 2 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * |[3] |ADMAT3 |I2C Address 3 Match Status + * | | |When address 3 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * |[4] |FULL |TWO-lEVEL BUFFER FULL + * | | |This bit indicates two-level buffer TX or RX full or not when the TWOBUFEN = 1. + * | | |This bit is set when POINTER is equal to 2. + * | | |Note:This bit is read only. + * |[5] |EMPTY |TWO-lEVEL BUFFER EMPTY + * | | |This bit indicates two-level buffer TX or RX empty or not when the TWOBUFEN = 1. + * | | |This bit is set when POINTER is equal to 0. + * | | |Note:This bit is read only. + * |[6] |OVR |I2C over Run Status Bit + * | | |This bit indicates the received two-level buffer TX or RX is over run when the TWOBUFEN = 1. + * | | |Note:This bit is read only. + * |[7] |UDR |I2C Under Run Status Bit + * | | |This bit indicates the transmitted two-level buffer TX or RX is under run when the TWOBUFEN = 1. + * | | |Note:This bit is read only. + * |[8] |ONBUSY |On Bus Busy (Read Only) + * | | |Indicates that a communication is in progress on the bus + * | | |It is set by hardware when a START condition is detected + * | | |It is cleared by hardware when a STOP condition is detected. + * | | |0 = The bus is IDLE (both SCLK and SDA High). + * | | |1 = The bus is busy. + * @var I2C_T::TMCTL + * Offset: 0x4C I2C Timing Configure Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |STCTL |Setup Time Configure Control + * | | |This field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode. + * | | |The delay setup time is numbers of peripheral clock = STCTL x PCLK. + * | | |Note: Setup time setting should not make SCL output less than three PCLKs. + * |[24:16] |HTCTL |Hold Time Configure Control + * | | |This field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode. + * | | |The delay hold time is numbers of peripheral clock = HTCTL x PCLK. + * @var I2C_T::BUSCTL + * Offset: 0x50 I2C Bus Management Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ACKMEN |Acknowledge Control by Manual + * | | |In order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit. + * | | |0 = Slave byte control Disabled. + * | | |1 = Slave byte control Enabled + * | | |The 9th bit can response the ACK or NACK according the received data by user + * | | |When the byte is received, stretching the SCLK signal low between the 8th and 9th SCLK pulse. + * | | |Note: If the BMDEN =1 and this bit is enabled, the information of I2C_STATUS0 will be fixed as 0xF0 in slave receive condition. + * |[1] |PECEN |Packet Error Checking Calculation Enable Bit + * | | |0 = Packet Error Checking Calculation Disabled. + * | | |1 = Packet Error Checking Calculation Enabled. + * | | |Note: When I2C enter powerdown mode, the bit should be enabled after wake-up if needed PEC calculation. + * |[2] |BMDEN |Bus Management Device Default Address Enable Bit + * | | |0 = Device default address Disable + * | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses NACKed + * | | |1 = Device default address Enabled + * | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses ACKed. + * |[3] |BMHEN |Bus Management Host Enable Bit + * | | |0 = Host function Disabled. + * | | |1 = Host function Enabled. + * |[4] |ALERTEN |Bus Management Alert Enable Bit + * | | |Device Mode (BMHEN =0). + * | | |0 = Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled. + * | | |1 = Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled. + * | | |Host Mode (BMHEN =1). + * | | |0 = BM_ALERT pin not supported. + * | | |1 = BM_ALERT pin supported. + * |[5] |SCTLOSTS |Suspend/Control Data Output Status + * | | |0 = The output of SUSCON pin is low. + * | | |1 = The output of SUSCON pin is high. + * |[6] |SCTLOEN |Suspend or Control Pin Output Enable Bit + * | | |0 = The SUSCON pin in input. + * | | |1 = The output enable is active on the SUSCON pin. + * |[7] |BUSEN |BUS Enable Bit + * | | |0 = The system management function Disabled. + * | | |1 = The system management function Enabled. + * | | |Note: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition. + * |[8] |PECTXEN |Packet Error Checking Byte Transmission/Reception + * | | |0 = No PEC transfer. + * | | |1 = PEC transmission is requested. + * | | |Note: 1.This bit has no effect in slave mode when ACKMEN =0. + * |[9] |TIDLE |Timer Check in Idle State + * | | |The BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle + * | | |This bit is used to define which condition is enabled. + * | | |0 = BUSTOUT is used to calculate the clock low period in bus active. + * | | |1 = BUSTOUT is used to calculate the IDLE period in bus Idle. + * | | |Note: The BUSY (I2C_BUSSTS[0]) indicate the current bus state. + * |[10] |PECCLR |PEC Clear at Repeat Start + * | | |The calculation of PEC starts when PECEN is set to 1 and it is cleared when the STA or STO bit is detected + * | | |This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation. + * | | |0 = PEC calculation is cleared by "Repeat Start" function Disabled. + * | | |1 = PEC calculation is cleared by "Repeat Start" function Enabled. + * |[11] |ACKM9SI |Acknowledge Manual Enable Extra SI Interrupt + * | | |0 = There is no SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1. + * | | |1 = There is SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1. + * |[12] |BCDIEN |Packet Error Checking Byte Count Done Interrupt Enable Bit + * | | |0 = Byte count done interrupt Disabled. + * | | |1 = Byte count done interrupt Enabled. + * | | |Note: This bit is used in PECEN =1. + * |[13] |PECDIEN |Packet Error Checking Byte Transfer Done Interrupt Enable Bit + * | | |0 = PEC transfer done interrupt Disabled. + * | | |1 = PEC transfer done interrupt Enabled. + * | | |Note: This bit is used in PECEN =1. + * @var I2C_T::BUSTCTL + * Offset: 0x54 I2C Bus Management Timer Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSTOEN |Bus Time Out Enable Bit + * | | |0 = Bus clock low time-out detection Disabled. + * | | |1 = Bus clock low time-out detection Enabled (bus clock is low for more than TTime-out (in BIDLE=0) or high more than TTime-out(in BIDLE =1) + * |[1] |CLKTOEN |Cumulative Clock Low Time Out Enable Bit + * | | |0 = Cumulative clock low time-out detection Disabled. + * | | |1 = Cumulative clock low time-out detection Enabled. + * | | |For Master, it calculates the period from START to ACK + * | | |For Slave, it calculates the period from START to STOP + * |[2] |BUSTOIEN |Time-out Interrupt Enable Bit + * | | |BUSY =1. + * | | |0 = SCLK low time-out interrupt Disabled. + * | | |1 = SCLK low time-out interrupt Enabled. + * | | |BUSY =0. + * | | |0 = Bus IDLE time-out interrupt Disabled. + * | | |1 = Bus IDLE time-out interrupt Enabled. + * |[3] |CLKTOIEN |Extended Clock Time Out Interrupt Enable Bit + * | | |0 = Clock time out interrupt Disabled. + * | | |1 = Clock time out interrupt Enabled. + * |[4] |TORSTEN |Time Out Reset Enable Bit + * | | |0 = I2C state machine reset Disabled. + * | | |1 = I2C state machine reset Enabled. (The clock and data bus will be released to high) + * @var I2C_T::BUSSTS + * Offset: 0x58 I2C Bus Management Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |Bus Busy (Read Only) + * | | |Indicates that a communication is in progress on the bus + * | | |It is set by hardware when a START condition is detected + * | | |It is cleared by hardware when a STOP condition is detected + * | | |0 = Bus is IDLE (both SCLK and SDA High). + * | | |1 = Bus is busy. + * |[1] |BCDONE |Byte Count Transmission/Receive Done + * | | |0 = Byte count transmission/ receive is not finished when the PECEN is set. + * | | |1 = Byte count transmission/ receive is finished when the PECEN is set. + * | | |Note: Software can write 1 to clear this bit. + * |[2] |PECERR |PEC Error in Reception + * | | |0 = PEC value equal the received PEC data packet. + * | | |1 = PEC value doesn't match the receive PEC data packet. + * | | |Note: Software can write 1 to clear this bit. + * |[3] |ALERT |SMBus Alert Status + * | | |Device Mode (BMHEN =0). + * | | |0 = Indicates SMBALERT pin state is low. + * | | |1 = Indicates SMBALERT pin state is high. + * | | |Host Mode (BMHEN =1). + * | | |0 = No SMBALERT event. + * | | |1 = Indicates there is SMBALERT event (falling edge) is detected in SMALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1. + * | | |Note: + * | | |1. The SMBALERT pin is an open-drain pin, the pull-high resistor is must in the system + * | | |2. Software can write 1 to clear this bit. + * |[4] |SCTLDIN |Bus Suspend or Control Signal Input Status (Read Only) + * | | |0 = The input status of SUSCON pin is 0. + * | | |1 = The input status of SUSCON pin is 1. + * |[5] |BUSTO |Bus Time-out Status + * | | |0 = There is no any time-out or external clock time-out. + * | | |1 = A time-out or external clock time-out occurred. + * | | |In bus busy, the bit indicates the total clock low time-out event occurred; otherwise, it indicates the bus idle time-out event occurred. + * | | |Note: Software can write 1 to clear this bit. + * |[6] |CLKTO |Clock Low Cumulate Time-out Status + * | | |0 = Cumulative clock low is no any time-out. + * | | |1 = Cumulative clock low time-out occurred. + * | | |Note: Software can write 1 to clear this bit. + * |[7] |PECDONE |PEC Byte Transmission/Receive Done + * | | |0 = PEC transmission/ receive is not finished when the PECEN is set. + * | | |1 = PEC transmission/ receive is finished when the PECEN is set. + * | | |Note: Software can write 1 to clear this bit. + * @var I2C_T::PKTSIZE + * Offset: 0x5C I2C Packet Error Checking Byte Number Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |PLDSIZE |Transfer Byte Number + * | | |The transmission or receive byte number in one transaction when the PECEN is set + * | | |The maximum transaction or receive byte is 256 Bytes. + * | | |Note: The byte number counting includes address, command code, and data frame. + * @var I2C_T::PKTCRC + * Offset: 0x60 I2C Packet Error Checking Byte Value Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |PECCRC |Packet Error Checking Byte Value + * | | |This byte indicates the packet error checking content after transmission or receive byte count by using the C(x) = X8 + X2 + X + 1 + * | | |It is read only. + * @var I2C_T::BUSTOUT + * Offset: 0x64 I2C Bus Management Timer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |BUSTO |Bus Management Time-out Value + * | | |Indicates the bus time-out value in bus is IDLE or SCLK low. + * | | |Note: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]) is set. + * @var I2C_T::CLKTOUT + * Offset: 0x68 I2C Bus Management Clock Low Timer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |CLKTO |Bus Clock Low Timer + * | | |The field is used to configure the cumulative clock extension time-out. + * | | |Note: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and clear to 0 first in the BUSEN is set. + */ + __IO uint32_t CTL0; /*!< [0x0000] I2C Control Register 0 */ + __IO uint32_t ADDR0; /*!< [0x0004] I2C Slave Address Register0 */ + __IO uint32_t DAT; /*!< [0x0008] I2C Data Register */ + __I uint32_t STATUS0; /*!< [0x000c] I2C Status Register 0 */ + __IO uint32_t CLKDIV; /*!< [0x0010] I2C Clock Divided Register */ + __IO uint32_t TOCTL; /*!< [0x0014] I2C Time-out Control Register */ + __IO uint32_t ADDR1; /*!< [0x0018] I2C Slave Address Register1 */ + __IO uint32_t ADDR2; /*!< [0x001c] I2C Slave Address Register2 */ + __IO uint32_t ADDR3; /*!< [0x0020] I2C Slave Address Register3 */ + __IO uint32_t ADDRMSK0; /*!< [0x0024] I2C Slave Address Mask Register0 */ + __IO uint32_t ADDRMSK1; /*!< [0x0028] I2C Slave Address Mask Register1 */ + __IO uint32_t ADDRMSK2; /*!< [0x002c] I2C Slave Address Mask Register2 */ + __IO uint32_t ADDRMSK3; /*!< [0x0030] I2C Slave Address Mask Register3 */ + __I uint32_t RESERVE0[2]; + __IO uint32_t WKCTL; /*!< [0x003c] I2C Wake-up Control Register */ + __IO uint32_t WKSTS; /*!< [0x0040] I2C Wake-up Status Register */ + __IO uint32_t CTL1; /*!< [0x0044] I2C Control Register 1 */ + __IO uint32_t STATUS1; /*!< [0x0048] I2C Status Register 1 */ + __IO uint32_t TMCTL; /*!< [0x004c] I2C Timing Configure Control Register */ + __IO uint32_t BUSCTL; /*!< [0x0050] I2C Bus Management Control Register */ + __IO uint32_t BUSTCTL; /*!< [0x0054] I2C Bus Management Timer Control Register */ + __IO uint32_t BUSSTS; /*!< [0x0058] I2C Bus Management Status Register */ + __IO uint32_t PKTSIZE; /*!< [0x005c] I2C Packet Error Checking Byte Number Register */ + __I uint32_t PKTCRC; /*!< [0x0060] I2C Packet Error Checking Byte Value Register */ + __IO uint32_t BUSTOUT; /*!< [0x0064] I2C Bus Management Timer Register */ + __IO uint32_t CLKTOUT; /*!< [0x0068] I2C Bus Management Clock Low Timer Register */ +} I2C_T; + +/** + @addtogroup I2C_CONST I2C Bit Field Definition + Constant Definitions for I2C Controller +@{ */ + +#define I2C_CTL0_AA_Pos (2) /*!< I2C_T::CTL0: AA Position */ +#define I2C_CTL0_AA_Msk (0x1ul << I2C_CTL0_AA_Pos) /*!< I2C_T::CTL0: AA Mask */ + +#define I2C_CTL0_SI_Pos (3) /*!< I2C_T::CTL0: SI Position */ +#define I2C_CTL0_SI_Msk (0x1ul << I2C_CTL0_SI_Pos) /*!< I2C_T::CTL0: SI Mask */ + +#define I2C_CTL0_STO_Pos (4) /*!< I2C_T::CTL0: STO Position */ +#define I2C_CTL0_STO_Msk (0x1ul << I2C_CTL0_STO_Pos) /*!< I2C_T::CTL0: STO Mask */ + +#define I2C_CTL0_STA_Pos (5) /*!< I2C_T::CTL0: STA Position */ +#define I2C_CTL0_STA_Msk (0x1ul << I2C_CTL0_STA_Pos) /*!< I2C_T::CTL0: STA Mask */ + +#define I2C_CTL0_I2CEN_Pos (6) /*!< I2C_T::CTL0: I2CEN Position */ +#define I2C_CTL0_I2CEN_Msk (0x1ul << I2C_CTL0_I2CEN_Pos) /*!< I2C_T::CTL0: I2CEN Mask */ + +#define I2C_CTL0_INTEN_Pos (7) /*!< I2C_T::CTL0: INTEN Position */ +#define I2C_CTL0_INTEN_Msk (0x1ul << I2C_CTL0_INTEN_Pos) /*!< I2C_T::CTL0: INTEN Mask */ + +#define I2C_ADDR0_GC_Pos (0) /*!< I2C_T::ADDR0: GC Position */ +#define I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos) /*!< I2C_T::ADDR0: GC Mask */ + +#define I2C_ADDR0_ADDR_Pos (1) /*!< I2C_T::ADDR0: ADDR Position */ +#define I2C_ADDR0_ADDR_Msk (0x3fful << I2C_ADDR0_ADDR_Pos) /*!< I2C_T::ADDR0: ADDR Mask */ + +#define I2C_DAT_DAT_Pos (0) /*!< I2C_T::DAT: DAT Position */ +#define I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos) /*!< I2C_T::DAT: DAT Mask */ + +#define I2C_STATUS0_STATUS_Pos (0) /*!< I2C_T::STATUS0: STATUS Position */ +#define I2C_STATUS0_STATUS_Msk (0xfful << I2C_STATUS0_STATUS_Pos) /*!< I2C_T::STATUS0: STATUS Mask */ + +#define I2C_CLKDIV_DIVIDER_Pos (0) /*!< I2C_T::CLKDIV: DIVIDER Position */ +#define I2C_CLKDIV_DIVIDER_Msk (0x3fful << I2C_CLKDIV_DIVIDER_Pos) /*!< I2C_T::CLKDIV: DIVIDER Mask */ + +#define I2C_TOCTL_TOIF_Pos (0) /*!< I2C_T::TOCTL: TOIF Position */ +#define I2C_TOCTL_TOIF_Msk (0x1ul << I2C_TOCTL_TOIF_Pos) /*!< I2C_T::TOCTL: TOIF Mask */ + +#define I2C_TOCTL_TOCDIV4_Pos (1) /*!< I2C_T::TOCTL: TOCDIV4 Position */ +#define I2C_TOCTL_TOCDIV4_Msk (0x1ul << I2C_TOCTL_TOCDIV4_Pos) /*!< I2C_T::TOCTL: TOCDIV4 Mask */ + +#define I2C_TOCTL_TOCEN_Pos (2) /*!< I2C_T::TOCTL: TOCEN Position */ +#define I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos) /*!< I2C_T::TOCTL: TOCEN Mask */ + +#define I2C_ADDR1_GC_Pos (0) /*!< I2C_T::ADDR1: GC Position */ +#define I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos) /*!< I2C_T::ADDR1: GC Mask */ + +#define I2C_ADDR1_ADDR_Pos (1) /*!< I2C_T::ADDR1: ADDR Position */ +#define I2C_ADDR1_ADDR_Msk (0x3fful << I2C_ADDR1_ADDR_Pos) /*!< I2C_T::ADDR1: ADDR Mask */ + +#define I2C_ADDR2_GC_Pos (0) /*!< I2C_T::ADDR2: GC Position */ +#define I2C_ADDR2_GC_Msk (0x1ul << I2C_ADDR2_GC_Pos) /*!< I2C_T::ADDR2: GC Mask */ + +#define I2C_ADDR2_ADDR_Pos (1) /*!< I2C_T::ADDR2: ADDR Position */ +#define I2C_ADDR2_ADDR_Msk (0x3fful << I2C_ADDR2_ADDR_Pos) /*!< I2C_T::ADDR2: ADDR Mask */ + +#define I2C_ADDR3_GC_Pos (0) /*!< I2C_T::ADDR3: GC Position */ +#define I2C_ADDR3_GC_Msk (0x1ul << I2C_ADDR3_GC_Pos) /*!< I2C_T::ADDR3: GC Mask */ + +#define I2C_ADDR3_ADDR_Pos (1) /*!< I2C_T::ADDR3: ADDR Position */ +#define I2C_ADDR3_ADDR_Msk (0x3fful << I2C_ADDR3_ADDR_Pos) /*!< I2C_T::ADDR3: ADDR Mask */ + +#define I2C_ADDRMSK0_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK0: ADDRMSK Position */ +#define I2C_ADDRMSK0_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK0_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK0: ADDRMSK Mask */ + +#define I2C_ADDRMSK1_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK1: ADDRMSK Position */ +#define I2C_ADDRMSK1_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK1_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK1: ADDRMSK Mask */ + +#define I2C_ADDRMSK2_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK2: ADDRMSK Position */ +#define I2C_ADDRMSK2_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK2_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK2: ADDRMSK Mask */ + +#define I2C_ADDRMSK3_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK3: ADDRMSK Position */ +#define I2C_ADDRMSK3_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK3_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK3: ADDRMSK Mask */ + +#define I2C_WKCTL_WKEN_Pos (0) /*!< I2C_T::WKCTL: WKEN Position */ +#define I2C_WKCTL_WKEN_Msk (0x1ul << I2C_WKCTL_WKEN_Pos) /*!< I2C_T::WKCTL: WKEN Mask */ + +#define I2C_WKCTL_NHDBUSEN_Pos (7) /*!< I2C_T::WKCTL: NHDBUSEN Position */ +#define I2C_WKCTL_NHDBUSEN_Msk (0x1ul << I2C_WKCTL_NHDBUSEN_Pos) /*!< I2C_T::WKCTL: NHDBUSEN Mask */ + +#define I2C_WKSTS_WKIF_Pos (0) /*!< I2C_T::WKSTS: WKIF Position */ +#define I2C_WKSTS_WKIF_Msk (0x1ul << I2C_WKSTS_WKIF_Pos) /*!< I2C_T::WKSTS: WKIF Mask */ + +#define I2C_WKSTS_WKAKDONE_Pos (1) /*!< I2C_T::WKSTS: WKAKDONE Position */ +#define I2C_WKSTS_WKAKDONE_Msk (0x1ul << I2C_WKSTS_WKAKDONE_Pos) /*!< I2C_T::WKSTS: WKAKDONE Mask */ + +#define I2C_WKSTS_WRSTSWK_Pos (2) /*!< I2C_T::WKSTS: WRSTSWK Position */ +#define I2C_WKSTS_WRSTSWK_Msk (0x1ul << I2C_WKSTS_WRSTSWK_Pos) /*!< I2C_T::WKSTS: WRSTSWK Mask */ + +#define I2C_CTL1_TXPDMAEN_Pos (0) /*!< I2C_T::CTL1: TXPDMAEN Position */ +#define I2C_CTL1_TXPDMAEN_Msk (0x1ul << I2C_CTL1_TXPDMAEN_Pos) /*!< I2C_T::CTL1: TXPDMAEN Mask */ + +#define I2C_CTL1_RXPDMAEN_Pos (1) /*!< I2C_T::CTL1: RXPDMAEN Position */ +#define I2C_CTL1_RXPDMAEN_Msk (0x1ul << I2C_CTL1_RXPDMAEN_Pos) /*!< I2C_T::CTL1: RXPDMAEN Mask */ + +#define I2C_CTL1_PDMARST_Pos (2) /*!< I2C_T::CTL1: PDMARST Position */ +#define I2C_CTL1_PDMARST_Msk (0x1ul << I2C_CTL1_PDMARST_Pos) /*!< I2C_T::CTL1: PDMARST Mask */ + +#define I2C_CTL1_OVRIEN_Pos (3) /*!< I2C_T::CTL1: OVRIEN Position */ +#define I2C_CTL1_OVRIEN_Msk (0x1ul << I2C_CTL1_OVRIEN_Pos) /*!< I2C_T::CTL1: OVRIEN Mask */ + +#define I2C_CTL1_UDRIEN_Pos (4) /*!< I2C_T::CTL1: UDRIEN Position */ +#define I2C_CTL1_UDRIEN_Msk (0x1ul << I2C_CTL1_UDRIEN_Pos) /*!< I2C_T::CTL1: UDRIEN Mask */ + +#define I2C_CTL1_TWOBUFEN_Pos (5) /*!< I2C_T::CTL1: TWOBUFEN Position */ +#define I2C_CTL1_TWOBUFEN_Msk (0x1ul << I2C_CTL1_TWOBUFEN_Pos) /*!< I2C_T::CTL1: TWOBUFEN Mask */ + +#define I2C_CTL1_BUFRST_Pos (6) /*!< I2C_T::CTL1: BUFRST Position */ +#define I2C_CTL1_BUFRST_Msk (0x1ul << I2C_CTL1_BUFRST_Pos) /*!< I2C_T::CTL1: BUFRST Mask */ + +#define I2C_CTL1_NSTRETCH_Pos (7) /*!< I2C_T::CTL1: NSTRETCH Position */ +#define I2C_CTL1_NSTRETCH_Msk (0x1ul << I2C_CTL1_NSTRETCH_Pos) /*!< I2C_T::CTL1: NSTRETCH Mask */ + +#define I2C_CTL1_PDMASTR_Pos (8) /*!< I2C_T::CTL1: PDMASTR Position */ +#define I2C_CTL1_PDMASTR_Msk (0x1ul << I2C_CTL1_PDMASTR_Pos) /*!< I2C_T::CTL1: PDMASTR Mask */ + +#define I2C_CTL1_ADDR10EN_Pos (9) /*!< I2C_T::CTL1: ADDR10EN Position */ +#define I2C_CTL1_ADDR10EN_Msk (0x1ul << I2C_CTL1_ADDR10EN_Pos) /*!< I2C_T::CTL1: ADDR10EN Mask */ + +#define I2C_STATUS1_ADMAT0_Pos (0) /*!< I2C_T::STATUS1: ADMAT0 Position */ +#define I2C_STATUS1_ADMAT0_Msk (0x1ul << I2C_STATUS1_ADMAT0_Pos) /*!< I2C_T::STATUS1: ADMAT0 Mask */ + +#define I2C_STATUS1_ADMAT1_Pos (1) /*!< I2C_T::STATUS1: ADMAT1 Position */ +#define I2C_STATUS1_ADMAT1_Msk (0x1ul << I2C_STATUS1_ADMAT1_Pos) /*!< I2C_T::STATUS1: ADMAT1 Mask */ + +#define I2C_STATUS1_ADMAT2_Pos (2) /*!< I2C_T::STATUS1: ADMAT2 Position */ +#define I2C_STATUS1_ADMAT2_Msk (0x1ul << I2C_STATUS1_ADMAT2_Pos) /*!< I2C_T::STATUS1: ADMAT2 Mask */ + +#define I2C_STATUS1_ADMAT3_Pos (3) /*!< I2C_T::STATUS1: ADMAT3 Position */ +#define I2C_STATUS1_ADMAT3_Msk (0x1ul << I2C_STATUS1_ADMAT3_Pos) /*!< I2C_T::STATUS1: ADMAT3 Mask */ + +#define I2C_STATUS1_FULL_Pos (4) /*!< I2C_T::STATUS1: FULL Position */ +#define I2C_STATUS1_FULL_Msk (0x1ul << I2C_STATUS1_FULL_Pos) /*!< I2C_T::STATUS1: FULL Mask */ + +#define I2C_STATUS1_EMPTY_Pos (5) /*!< I2C_T::STATUS1: EMPTY Position */ +#define I2C_STATUS1_EMPTY_Msk (0x1ul << I2C_STATUS1_EMPTY_Pos) /*!< I2C_T::STATUS1: EMPTY Mask */ + +#define I2C_STATUS1_OVR_Pos (6) /*!< I2C_T::STATUS1: OVR Position */ +#define I2C_STATUS1_OVR_Msk (0x1ul << I2C_STATUS1_OVR_Pos) /*!< I2C_T::STATUS1: OVR Mask */ + +#define I2C_STATUS1_UDR_Pos (7) /*!< I2C_T::STATUS1: UDR Position */ +#define I2C_STATUS1_UDR_Msk (0x1ul << I2C_STATUS1_UDR_Pos) /*!< I2C_T::STATUS1: UDR Mask */ + +#define I2C_STATUS1_ONBUSY_Pos (8) /*!< I2C_T::STATUS1: ONBUSY Position */ +#define I2C_STATUS1_ONBUSY_Msk (0x1ul << I2C_STATUS1_ONBUSY_Pos) /*!< I2C_T::STATUS1: ONBUSY Mask */ + +#define I2C_TMCTL_STCTL_Pos (0) /*!< I2C_T::TMCTL: STCTL Position */ +#define I2C_TMCTL_STCTL_Msk (0x1fful << I2C_TMCTL_STCTL_Pos) /*!< I2C_T::TMCTL: STCTL Mask */ + +#define I2C_TMCTL_HTCTL_Pos (16) /*!< I2C_T::TMCTL: HTCTL Position */ +#define I2C_TMCTL_HTCTL_Msk (0x1fful << I2C_TMCTL_HTCTL_Pos) /*!< I2C_T::TMCTL: HTCTL Mask */ + +#define I2C_BUSCTL_ACKMEN_Pos (0) /*!< I2C_T::BUSCTL: ACKMEN Position */ +#define I2C_BUSCTL_ACKMEN_Msk (0x1ul << I2C_BUSCTL_ACKMEN_Pos) /*!< I2C_T::BUSCTL: ACKMEN Mask */ + +#define I2C_BUSCTL_PECEN_Pos (1) /*!< I2C_T::BUSCTL: PECEN Position */ +#define I2C_BUSCTL_PECEN_Msk (0x1ul << I2C_BUSCTL_PECEN_Pos) /*!< I2C_T::BUSCTL: PECEN Mask */ + +#define I2C_BUSCTL_BMDEN_Pos (2) /*!< I2C_T::BUSCTL: BMDEN Position */ +#define I2C_BUSCTL_BMDEN_Msk (0x1ul << I2C_BUSCTL_BMDEN_Pos) /*!< I2C_T::BUSCTL: BMDEN Mask */ + +#define I2C_BUSCTL_BMHEN_Pos (3) /*!< I2C_T::BUSCTL: BMHEN Position */ +#define I2C_BUSCTL_BMHEN_Msk (0x1ul << I2C_BUSCTL_BMHEN_Pos) /*!< I2C_T::BUSCTL: BMHEN Mask */ + +#define I2C_BUSCTL_ALERTEN_Pos (4) /*!< I2C_T::BUSCTL: ALERTEN Position */ +#define I2C_BUSCTL_ALERTEN_Msk (0x1ul << I2C_BUSCTL_ALERTEN_Pos) /*!< I2C_T::BUSCTL: ALERTEN Mask */ + +#define I2C_BUSCTL_SCTLOSTS_Pos (5) /*!< I2C_T::BUSCTL: SCTLOSTS Position */ +#define I2C_BUSCTL_SCTLOSTS_Msk (0x1ul << I2C_BUSCTL_SCTLOSTS_Pos) /*!< I2C_T::BUSCTL: SCTLOSTS Mask */ + +#define I2C_BUSCTL_SCTLOEN_Pos (6) /*!< I2C_T::BUSCTL: SCTLOEN Position */ +#define I2C_BUSCTL_SCTLOEN_Msk (0x1ul << I2C_BUSCTL_SCTLOEN_Pos) /*!< I2C_T::BUSCTL: SCTLOEN Mask */ + +#define I2C_BUSCTL_BUSEN_Pos (7) /*!< I2C_T::BUSCTL: BUSEN Position */ +#define I2C_BUSCTL_BUSEN_Msk (0x1ul << I2C_BUSCTL_BUSEN_Pos) /*!< I2C_T::BUSCTL: BUSEN Mask */ + +#define I2C_BUSCTL_PECTXEN_Pos (8) /*!< I2C_T::BUSCTL: PECTXEN Position */ +#define I2C_BUSCTL_PECTXEN_Msk (0x1ul << I2C_BUSCTL_PECTXEN_Pos) /*!< I2C_T::BUSCTL: PECTXEN Mask */ + +#define I2C_BUSCTL_TIDLE_Pos (9) /*!< I2C_T::BUSCTL: TIDLE Position */ +#define I2C_BUSCTL_TIDLE_Msk (0x1ul << I2C_BUSCTL_TIDLE_Pos) /*!< I2C_T::BUSCTL: TIDLE Mask */ + +#define I2C_BUSCTL_PECCLR_Pos (10) /*!< I2C_T::BUSCTL: PECCLR Position */ +#define I2C_BUSCTL_PECCLR_Msk (0x1ul << I2C_BUSCTL_PECCLR_Pos) /*!< I2C_T::BUSCTL: PECCLR Mask */ + +#define I2C_BUSCTL_ACKM9SI_Pos (11) /*!< I2C_T::BUSCTL: ACKM9SI Position */ +#define I2C_BUSCTL_ACKM9SI_Msk (0x1ul << I2C_BUSCTL_ACKM9SI_Pos) /*!< I2C_T::BUSCTL: ACKM9SI Mask */ + +#define I2C_BUSCTL_BCDIEN_Pos (12) /*!< I2C_T::BUSCTL: BCDIEN Position */ +#define I2C_BUSCTL_BCDIEN_Msk (0x1ul << I2C_BUSCTL_BCDIEN_Pos) /*!< I2C_T::BUSCTL: BCDIEN Mask */ + +#define I2C_BUSCTL_PECDIEN_Pos (13) /*!< I2C_T::BUSCTL: PECDIEN Position */ +#define I2C_BUSCTL_PECDIEN_Msk (0x1ul << I2C_BUSCTL_PECDIEN_Pos) /*!< I2C_T::BUSCTL: PECDIEN Mask */ + +#define I2C_BUSTCTL_BUSTOEN_Pos (0) /*!< I2C_T::BUSTCTL: BUSTOEN Position */ +#define I2C_BUSTCTL_BUSTOEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOEN Mask */ + +#define I2C_BUSTCTL_CLKTOEN_Pos (1) /*!< I2C_T::BUSTCTL: CLKTOEN Position */ +#define I2C_BUSTCTL_CLKTOEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOEN Mask */ + +#define I2C_BUSTCTL_BUSTOIEN_Pos (2) /*!< I2C_T::BUSTCTL: BUSTOIEN Position */ +#define I2C_BUSTCTL_BUSTOIEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOIEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOIEN Mask */ + +#define I2C_BUSTCTL_CLKTOIEN_Pos (3) /*!< I2C_T::BUSTCTL: CLKTOIEN Position */ +#define I2C_BUSTCTL_CLKTOIEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOIEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOIEN Mask */ + +#define I2C_BUSTCTL_TORSTEN_Pos (4) /*!< I2C_T::BUSTCTL: TORSTEN Position */ +#define I2C_BUSTCTL_TORSTEN_Msk (0x1ul << I2C_BUSTCTL_TORSTEN_Pos) /*!< I2C_T::BUSTCTL: TORSTEN Mask */ + +#define I2C_BUSSTS_BUSY_Pos (0) /*!< I2C_T::BUSSTS: BUSY Position */ +#define I2C_BUSSTS_BUSY_Msk (0x1ul << I2C_BUSSTS_BUSY_Pos) /*!< I2C_T::BUSSTS: BUSY Mask */ + +#define I2C_BUSSTS_BCDONE_Pos (1) /*!< I2C_T::BUSSTS: BCDONE Position */ +#define I2C_BUSSTS_BCDONE_Msk (0x1ul << I2C_BUSSTS_BCDONE_Pos) /*!< I2C_T::BUSSTS: BCDONE Mask */ + +#define I2C_BUSSTS_PECERR_Pos (2) /*!< I2C_T::BUSSTS: PECERR Position */ +#define I2C_BUSSTS_PECERR_Msk (0x1ul << I2C_BUSSTS_PECERR_Pos) /*!< I2C_T::BUSSTS: PECERR Mask */ + +#define I2C_BUSSTS_ALERT_Pos (3) /*!< I2C_T::BUSSTS: ALERT Position */ +#define I2C_BUSSTS_ALERT_Msk (0x1ul << I2C_BUSSTS_ALERT_Pos) /*!< I2C_T::BUSSTS: ALERT Mask */ + +#define I2C_BUSSTS_SCTLDIN_Pos (4) /*!< I2C_T::BUSSTS: SCTLDIN Position */ +#define I2C_BUSSTS_SCTLDIN_Msk (0x1ul << I2C_BUSSTS_SCTLDIN_Pos) /*!< I2C_T::BUSSTS: SCTLDIN Mask */ + +#define I2C_BUSSTS_BUSTO_Pos (5) /*!< I2C_T::BUSSTS: BUSTO Position */ +#define I2C_BUSSTS_BUSTO_Msk (0x1ul << I2C_BUSSTS_BUSTO_Pos) /*!< I2C_T::BUSSTS: BUSTO Mask */ + +#define I2C_BUSSTS_CLKTO_Pos (6) /*!< I2C_T::BUSSTS: CLKTO Position */ +#define I2C_BUSSTS_CLKTO_Msk (0x1ul << I2C_BUSSTS_CLKTO_Pos) /*!< I2C_T::BUSSTS: CLKTO Mask */ + +#define I2C_BUSSTS_PECDONE_Pos (7) /*!< I2C_T::BUSSTS: PECDONE Position */ +#define I2C_BUSSTS_PECDONE_Msk (0x1ul << I2C_BUSSTS_PECDONE_Pos) /*!< I2C_T::BUSSTS: PECDONE Mask */ + +#define I2C_PKTSIZE_PLDSIZE_Pos (0) /*!< I2C_T::PKTSIZE: PLDSIZE Position */ +#define I2C_PKTSIZE_PLDSIZE_Msk (0x1fful << I2C_PKTSIZE_PLDSIZE_Pos) /*!< I2C_T::PKTSIZE: PLDSIZE Mask */ + +#define I2C_PKTCRC_PECCRC_Pos (0) /*!< I2C_T::PKTCRC: PECCRC Position */ +#define I2C_PKTCRC_PECCRC_Msk (0xfful << I2C_PKTCRC_PECCRC_Pos) /*!< I2C_T::PKTCRC: PECCRC Mask */ + +#define I2C_BUSTOUT_BUSTO_Pos (0) /*!< I2C_T::BUSTOUT: BUSTO Position */ +#define I2C_BUSTOUT_BUSTO_Msk (0xfful << I2C_BUSTOUT_BUSTO_Pos) /*!< I2C_T::BUSTOUT: BUSTO Mask */ + +#define I2C_CLKTOUT_CLKTO_Pos (0) /*!< I2C_T::CLKTOUT: CLKTO Position */ +#define I2C_CLKTOUT_CLKTO_Msk (0xfful << I2C_CLKTOUT_CLKTO_Pos) /*!< I2C_T::CLKTOUT: CLKTO Mask */ + +/**@}*/ /* I2C_CONST */ +/**@}*/ /* end of I2C register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __I2C_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/opa_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/opa_reg.h new file mode 100644 index 00000000000..c9616bc1628 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/opa_reg.h @@ -0,0 +1,136 @@ +/**************************************************************************//** + * @file opa_reg.h + * @version V1.00 + * @brief OPA register definition header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __OPA_REG_H__ +#define __OPA_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup OPA OP Amplifier (OPA) + Memory Mapped Structure for OPA Controller +@{ */ + +typedef struct +{ + + + /** + * @var OPA_T::CTL + * Offset: 0x00 OP Amplifier Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |OPEN0 |OP Amplifier 0 Enable Bit + * | | |0 = Disable OP amplifier0. + * | | |1 = Enabled OP amplifier0. + * | | |Note: OP Amplifier 0 output needs wait stable 20us after OPEN0 is set. + * |[4] |OPDOEN0 |OP Amplifier 0 Schmitt Trigger Non-inverting Buffer Enable Bit + * | | |0 = Disable OP amplifier0 schmitt trigger non-invert buffer. + * | | |1 = Enable OP amplifier0 schmitt trigger non-invert buffer. + * |[8] |OPDOIEN0 |OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Enable Bit + * | | |0 = OP Amplifier 0 digital output interrupt function Disabled. + * | | |1 = OP Amplifier 0 digital output interrupt function Enabled. + * | | |The OPDOIF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt trigger non-inverting buffer digital + * | | |output changes state, in the meanwhile, if OPDOIEN0 is set to 1, a comparator interrupt request is generated. + * @var OPA_T::STATUS + * Offset: 0x04 OP Amplifier Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |OPDO0 |OP Amplifier 0 Digital Output + * | | |Synchronized to the APB clock to allow reading by software. + * | | |Cleared when the Schmitt trigger buffer is disabled (OPDOEN0 = 0) + * |[4] |OPDOIF0 |OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Flag + * | | |OPDOIF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt trigger non-inverting buffer digital + * | | |output changes state. This bit is cleared by writing 1 to it. + * @var OPA_T::CALCTL + * Offset: 0x08 OP Amplifier Calibration Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CALTRG0 |OP Amplifier 0 Calibration Trigger Bit + * | | |0 = Stop, hardware auto clear. + * | | |1 = Start. + * | | |Note: Before enable this bit, it should set OPEN0 in advance. + * |[16] |CALRVS0 |OPA0 Calibration Reference Voltage Selection + * | | |0 = VREF is 1/2 AVDD. + * | | |1 = VREF from high vcm to low vcm. + * @var OPA_T::CALST + * Offset: 0x0C OP Amplifier Calibration Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DONE0 |OP Amplifier 0 Calibration Done Status + * | | |0 = Calibrating. + * | | |1 = Calibration Done. + * |[1] |CALNS0 |OP Amplifier 0 Calibration Result Status for NMOS + * | | |0 = Pass. + * | | |1 = Fail. + * |[2] |CALPS0 |OP Amplifier 0 Calibration Result Status for PMOS + * | | |0 = Pass. + * | | |1 = Fail. + */ + __IO uint32_t CTL; /*!< [0x0000] OP Amplifier Control Register */ + __IO uint32_t STATUS; /*!< [0x0004] OP Amplifier Status Register */ + __IO uint32_t CALCTL; /*!< [0x0008] OP Amplifier Calibration Control Register */ + __I uint32_t CALST; /*!< [0x000c] OP Amplifier Calibration Status Register */ +} OPA_T; + +/** + @addtogroup OPA_CONST OPA Bit Field Definition + Constant Definitions for OPA Controller +@{ */ + +#define OPA_CTL_OPEN0_Pos (0) /*!< OPA_T::CTL: OPEN0 Position */ +#define OPA_CTL_OPEN0_Msk (0x1ul << OPA_CTL_OPEN0_Pos) /*!< OPA_T::CTL: OPEN0 Mask */ + +#define OPA_CTL_OPDOEN0_Pos (4) /*!< OPA_T::CTL: OPDOEN0 Position */ +#define OPA_CTL_OPDOEN0_Msk (0x1ul << OPA_CTL_OPDOEN0_Pos) /*!< OPA_T::CTL: OPDOEN0 Mask */ + +#define OPA_CTL_OPDOIEN0_Pos (8) /*!< OPA_T::CTL: OPDOIEN0 Position */ +#define OPA_CTL_OPDOIEN0_Msk (0x1ul << OPA_CTL_OPDOIEN0_Pos) /*!< OPA_T::CTL: OPDOIEN0 Mask */ + +#define OPA_STATUS_OPDO0_Pos (0) /*!< OPA_T::STATUS: OPDO0 Position */ +#define OPA_STATUS_OPDO0_Msk (0x1ul << OPA_STATUS_OPDO0_Pos) /*!< OPA_T::STATUS: OPDO0 Mask */ + +#define OPA_STATUS_OPDOIF0_Pos (4) /*!< OPA_T::STATUS: OPDOIF0 Position */ +#define OPA_STATUS_OPDOIF0_Msk (0x1ul << OPA_STATUS_OPDOIF0_Pos) /*!< OPA_T::STATUS: OPDOIF0 Mask */ + +#define OPA_CALCTL_CALTRG0_Pos (0) /*!< OPA_T::CALCTL: CALTRG0 Position */ +#define OPA_CALCTL_CALTRG0_Msk (0x1ul << OPA_CALCTL_CALTRG0_Pos) /*!< OPA_T::CALCTL: CALTRG0 Mask */ + +#define OPA_CALCTL_CALRVS0_Pos (16) /*!< OPA_T::CALCTL: CALRVS0 Position */ +#define OPA_CALCTL_CALRVS0_Msk (0x1ul << OPA_CALCTL_CALRVS0_Pos) /*!< OPA_T::CALCTL: CALRVS0 Mask */ + +#define OPA_CALST_DONE0_Pos (0) /*!< OPA_T::CALST: DONE0 Position */ +#define OPA_CALST_DONE0_Msk (0x1ul << OPA_CALST_DONE0_Pos) /*!< OPA_T::CALST: DONE0 Mask */ + +#define OPA_CALST_CALNS0_Pos (1) /*!< OPA_T::CALST: CALNS0 Position */ +#define OPA_CALST_CALNS0_Msk (0x1ul << OPA_CALST_CALNS0_Pos) /*!< OPA_T::CALST: CALNS0 Mask */ + +#define OPA_CALST_CALPS0_Pos (2) /*!< OPA_T::CALST: CALPS0 Position */ +#define OPA_CALST_CALPS0_Msk (0x1ul << OPA_CALST_CALPS0_Pos) /*!< OPA_T::CALST: CALPS0 Mask */ + + + +/**@}*/ /* OPA_CONST */ +/**@}*/ /* end of OPA register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __OPA_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/pdma_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/pdma_reg.h new file mode 100644 index 00000000000..b69eac1b652 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/pdma_reg.h @@ -0,0 +1,722 @@ +/**************************************************************************//** + * @file pdma_reg.h + * @version V1.00 + * @brief PDMA register definition header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __PDMA_REG_H__ +#define __PDMA_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup PDMA Peripheral Direct Memory Access Controller (PDMA) + Memory Mapped Structure for PDMA Controller +@{ */ + + +typedef struct +{ + /** + * @var DSCT_T::CTL + * Offset: 0x00 Descriptor Table Control Register of PDMA Channel n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |OPMODE |PDMA Operation Mode Selection + * | | |00 = Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically. + * | | |01 = Basic mode: The descriptor table only has one task + * | | |When this task is finished, the PDMA_INTSTS[n] will be asserted. + * | | |10 = Scatter-Gather mode: When operating in this mode, user must give the next descriptor table address in PDMA_DSCT_NEXT register; PDMA controller will ignore this task, then load the next task to execute. + * | | |11 = Reserved. + * | | |Note: Before filling transfer task in the Descriptor Table, user must check if the descriptor table is complete. + * |[2] |TXTYPE |Transfer Type + * | | |0 = Burst transfer type. + * | | |1 = Single transfer type. + * |[6:4] |BURSIZE |Burst Size + * | | |This field is used for peripheral to determine the burst size or used for determine the re-arbitration size. + * | | |000 = 128 Transfers. + * | | |001 = 64 Transfers. + * | | |010 = 32 Transfers. + * | | |011 = 16 Transfers. + * | | |100 = 8 Transfers. + * | | |101 = 4 Transfers. + * | | |110 = 2 Transfers. + * | | |111 = 1 Transfers. + * | | |Note: This field is only useful in burst transfer type. + * |[7] |TBINTDIS |Table Interrupt Disable Bit + * | | |This field can be used to decide whether to enable table interrupt or not + * | | |If the TBINTDIS bit is enabled when PDMA controller finishes transfer task, it will not generates transfer done interrupt. + * | | |0 = Table interrupt Enabled. + * | | |1 = Table interrupt Disabled. + * |[9:8] |SAINC |Source Address Increment + * | | |This field is used to set the source address increment size. + * | | |11 = No increment (fixed address). + * | | |Others = Increment and size is depended on TXWIDTH selection. + * |[11:10] |DAINC |Destination Address Increment + * | | |This field is used to set the destination address increment size. + * | | |11 = No increment (fixed address). + * | | |Others = Increment and size is depended on TXWIDTH selection. + * |[13:12] |TXWIDTH |Transfer Width Selection + * | | |This field is used for transfer width. + * | | |00 = One byte (8 bit) is transferred for every operation. + * | | |01= One half-word (16 bit) is transferred for every operation. + * | | |10 = One word (32-bit) is transferred for every operation. + * | | |11 = Reserved. + * | | |Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection + * |[14] |TXACK |Transfer Acknowledge Selection + * | | |0 = transfer ack when transfer done. + * | | |1 = transfer ack when PDMA get transfer data. + * | | |Note: This function only support UART_RX and SPI_RX. + * |[15] |STRIDEEN |Stride Mode Enable Bit + * | | |0 = Stride transfer mode Disabled. + * | | |1 = Stride transfer mode Enabled. + * |[31:16] |TXCNT |Transfer Count + * | | |The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1); The maximum transfer count is 16384, every transfer may be byte, half-word or word that is dependent on TXWIDTH field. + * | | |Note: When PDMA finish each transfer data, this field will be decrease immediately. + * @var DSCT_T::SA + * Offset: 0x04 Source Address Register of PDMA Channel n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SA |PDMA Transfer Source Address + * | | |This field indicates a 32-bit source address of PDMA controller. + * @var DSCT_T::DA + * Offset: 0x08 Destination Address Register of PDMA Channel n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DA |PDMA Transfer Destination Address + * | | |This field indicates a 32-bit destination address of PDMA controller. + * @var DSCT_T::NEXT + * Offset: 0x0C Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |NEXT |PDMA Next Descriptor Table Offset + * | | |This field indicates the offset of the next descriptor table address in system memory. + * | | |Write Operation: + * | | |If the system memory based address is 0x2000_0000 (PDMA_SCATBA), and the next descriptor table is start from 0x2000_0100, then this field must fill in 0x0100. + * | | |Read Operation: + * | | |When operating in scatter-gather mode, the last two bits NEXT[1:0] will become reserved, and indicate the first next address of system memory. + * | | |When operating in scatter-gather mode, the last two bits NEXT[1:0] will become scatter-gather mode control indicator as below. + * | | |0 = Idle mode. + * | | |1 = operating in the basic mode (final scatter-gather table). + * | | |2 = loading scatter-gather table from SRAM. + * | | |3 = operating in the scatter-gather mode. + * | | |Note1: The descriptor table address must be word boundary. + * | | |Note2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete. + * |[31:16] |EXENEXT |PDMA Execution Next Descriptor Table Offset + * | | |This field indicates the offset of next descriptor table address of current execution descriptor table in system memory. + * | | |Note: write operation is useless in this field. + */ + __IO uint32_t CTL; /*!< [0x0000] Descriptor Table Control Register of PDMA Channel n. */ + __IO uint32_t SA; /*!< [0x0004] Source Address Register of PDMA Channel n */ + __IO uint32_t DA; /*!< [0x0008] Destination Address Register of PDMA Channel n */ + __IO uint32_t NEXT; /*!< [0x000c] First Scatter-Gather Descriptor Table Offset Address of PDMA Channel n */ + +} DSCT_T; + +typedef struct +{ + /** + * @var STRIDE_T::STC + * Offset: 0x500 Stride Transfer Count Register of PDMA Channel n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |STC |PDMA Stride Transfer Count + * | | |The 16-bit register defines the stride transfer count of each row. + * @var STRIDE_T::ASOCR + * Offset: 0x504 Address Stride Offset Register of PDMA Channel n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |SASOL |VDMA Source Address Stride Offset Length + * | | |The 16-bit register defines the source address stride transfer offset count of each row. + * |[31:16] |DASOL |VDMA Destination Address Stride Offset Length + * | | |The 16-bit register defines the destination address stride transfer offset count of each row. + */ + __IO uint32_t STC; /*!< [0x0500] Stride Transfer Count Register of PDMA Channel 0 */ + __IO uint32_t ASOCR; /*!< [0x0504] Address Stride Offset Register of PDMA Channel 0 */ +} STRIDE_T; + + + +typedef struct +{ + /** + * @var PDMA_T::CURSCAT + * Offset: 0x100 Current Scatter-gather Descriptor Table Address of PDMA Channel n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURADDR |PDMA Current Description Address (Read Only) + * | | |This field indicates a 32-bit current external description address of PDMA controller. + * | | |Note: This field is read only and used for Scatter-Gather mode only to indicate the current external description address. + * @var PDMA_T::CHCTL + * Offset: 0x400 PDMA Channel Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |CHENn |PDMA Channel Enable Bits + * | | |Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled. + * | | |0 = PDMA channel [n] Disabled. + * | | |1 = PDMA channel [n] Enabled. + * | | |Note: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit. + * @var PDMA_T::PAUSE + * Offset: 0x404 PDMA Transfer Pause Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |PAUSEn |PDMA Channel N Transfer Pause Control (Write Only) + * | | |User can set PAUSEn bit field to pause the PDMA transfer + * | | |When user sets PAUSEn bit, the PDMA controller will pause the on-going transfer, then clear the channel enable bit CHEN(PDMA_CHCTL [n], n=0,1..7) and clear request active flag + * | | |If the paused channel is re-enabled again, the remaining transfers will be processed. + * | | |0 = No effect. + * | | |1 = Pause PDMA channel n transfer. + * @var PDMA_T::SWREQ + * Offset: 0x408 PDMA Software Request Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |SWREQn |PDMA Software Request (Write Only) + * | | |Set this bit to 1 to generate a software request to PDMA [n]. + * | | |0 = No effect. + * | | |1 = Generate a software request. + * | | |Note1: User can read PDMA_TRGSTS register to know which channel is on active + * | | |Active flag may be triggered by software request or peripheral request. + * | | |Note2: If user does not enable corresponding PDMA channel, the software request will be ignored. + * @var PDMA_T::TRGSTS + * Offset: 0x40C PDMA Channel Request Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |REQSTSn |PDMA Channel Request Status (Read Only) + * | | |This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral + * | | |When PDMA controller finishes channel transfer, this bit will be cleared automatically. + * | | |0 = PDMA Channel n has no request. + * | | |1 = PDMA Channel n has a request. + * | | |Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer. + * @var PDMA_T::PRISET + * Offset: 0x410 PDMA Fixed Priority Setting Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |FPRISETn |PDMA Fixed Priority Setting + * | | |Set this bit to 1 to enable fixed priority level. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set PDMA channel [n] to fixed priority channel. + * | | |Read Operation: + * | | |0 = Corresponding PDMA channel is round-robin priority. + * | | |1 = Corresponding PDMA channel is fixed priority. + * | | |Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register. + * @var PDMA_T::PRICLR + * Offset: 0x414 PDMA Fixed Priority Clear Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |FPRICLRn |PDMA Fixed Priority Clear Bits (Write Only) + * | | |Set this bit to 1 to clear fixed priority level. + * | | |0 = No effect. + * | | |1 = Clear PDMA channel [n] fixed priority setting. + * | | |Note: User can read PDMA_PRISET register to know the channel priority. + * @var PDMA_T::INTEN + * Offset: 0x418 PDMA Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |INTENn |PDMA Interrupt Enable Bits + * | | |This field is used to enable PDMA channel[n] interrupt. + * | | |0 = PDMA channel n interrupt Disabled. + * | | |1 = PDMA channel n interrupt Enabled. + * @var PDMA_T::INTSTS + * Offset: 0x41C PDMA Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ABTIF |PDMA Read/Write Target Abort Interrupt Flag (Read Only) + * | | |This bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error. + * | | |0 = No AHB bus ERROR response received. + * | | |1 = AHB bus ERROR response received. + * |[1] |TDIF |Transfer Done Interrupt Flag (Read Only) + * | | |This bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer. + * | | |0 = Not finished yet. + * | | |1 = PDMA channel has finished transmission. + * |[2] |ALIGNF |Transfer Alignment Interrupt Flag (Read Only) + * | | |0 = PDMA channel source address and destination address both follow transfer width setting. + * | | |1 = PDMA channel source address or destination address is not follow transfer width setting. + * |[8] |REQTOF0 |Request Time-out Flag for Channel 0 + * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC0, user can write 1 to clear these bits. + * | | |0 = No request time-out. + * | | |1 = Peripheral request time-out. + * |[9] |REQTOF1 |Request Time-out Flag for Channel 1 + * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC1, user can write 1 to clear these bits. + * | | |0 = No request time-out. + * | | |1 = Peripheral request time-out. + * @var PDMA_T::ABTSTS + * Offset: 0x420 PDMA Channel Read/Write Target Abort Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |ABTIFn |PDMA Read/Write Target Abort Interrupt Status Flag + * | | |This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits. + * | | |0 = No AHB bus ERROR response received when channel n transfer. + * | | |1 = AHB bus ERROR response received when channel n transfer. + * @var PDMA_T::TDSTS + * Offset: 0x424 PDMA Channel Transfer Done Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |TDIF0 |Transfer Done Flag + * | | |This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. + * | | |0 = PDMA channel transfer has not finished. + * | | |1 = PDMA channel has finished transmission. + * @var PDMA_T::ALIGN + * Offset: 0x428 PDMA Transfer Alignment Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |ALIGNn |Transfer Alignment Flag + * | | |0 = PDMA channel source address and destination address both follow transfer width setting. + * | | |1 = PDMA channel source address or destination address is not follow transfer width setting. + * @var PDMA_T::TACTSTS + * Offset: 0x42C PDMA Transfer Active Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |TXACTFn |Transfer on Active Flag (Read Only) + * | | |This bit indicates which PDMA channel is in active. + * | | |0 = PDMA channel is not finished. + * | | |1 = PDMA channel is active. + * @var PDMA_T::TOUTPSC + * Offset: 0x430 PDMA Time-out Prescaler Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |TOUTPSC0 |PDMA Channel 0 Time-out Clock Source Prescaler Bits + * | | |000 = PDMA channel 0 time-out clock source is HCLK/28. + * | | |001 = PDMA channel 0 time-out clock source is HCLK/29. + * | | |010 = PDMA channel 0 time-out clock source is HCLK/210. + * | | |011 = PDMA channel 0 time-out clock source is HCLK/211. + * | | |100 = PDMA channel 0 time-out clock source is HCLK/212. + * | | |101 = PDMA channel 0 time-out clock source is HCLK/213. + * | | |110 = PDMA channel 0 time-out clock source is HCLK/214. + * | | |111 = PDMA channel 0 time-out clock source is HCLK/215. + * |[6:4] |TOUTPSC1 |PDMA Channel 1 Time-out Clock Source Prescaler Bits + * | | |000 = PDMA channel 1 time-out clock source is HCLK/28. + * | | |001 = PDMA channel 1 time-out clock source is HCLK/29. + * | | |010 = PDMA channel 1 time-out clock source is HCLK/210. + * | | |011 = PDMA channel 1 time-out clock source is HCLK/211. + * | | |100 = PDMA channel 1 time-out clock source is HCLK/212. + * | | |101 = PDMA channel 1 time-out clock source is HCLK/213. + * | | |110 = PDMA channel 1 time-out clock source is HCLK/214. + * | | |111 = PDMA channel 1 time-out clock source is HCLK/215. + * @var PDMA_T::TOUTEN + * Offset: 0x434 PDMA Time-out Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |TOUTENn |PDMA Time-out Enable Bits + * | | |0 = PDMA Channel n time-out function Disabled. + * | | |1 = PDMA Channel n time-out function Enabled. + * @var PDMA_T::TOUTIEN + * Offset: 0x438 PDMA Time-out Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |TOUTIENn |PDMA Time-out Interrupt Enable Bits + * | | |0 = PDMA Channel n time-out interrupt Disabled. + * | | |1 = PDMA Channel n time-out interrupt Enabled. + * @var PDMA_T::SCATBA + * Offset: 0x43C PDMA Scatter-gather Descriptor Table Base Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:16] |SCATBA |PDMA Scatter-gather Descriptor Table Address + * | | |In Scatter-Gather mode, this is the base address for calculating the next link - list address + * | | |The next link address equation is + * | | |Next Link Address = PDMA_SCATBA + PDMA_DSCT_NEXT. + * | | |Note: Only useful in Scatter-Gather mode. + * @var PDMA_T::TOC0_1 + * Offset: 0x440 PDMA Time-out Counter Ch1 and Ch0 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TOC0 |Time-out Counter for Channel 0 + * | | |This controls the period of time-out function for channel 0 + * | | |The calculation unit is based on 10 kHz clock. + * |[31:16] |TOC1 |Time-out Counter for Channel 1 + * | | |This controls the period of time-out function for channel 1 + * | | |The calculation unit is based on 10 kHz clock. + * @var PDMA_T::CHRST + * Offset: 0x460 PDMA Channel Reset Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CHnRST |Channel N Reset + * | | |0 = corresponding channel n is not reset. + * | | |1 = corresponding channel n is reset. + * @var PDMA_T::REQSEL0_3 + * Offset: 0x480 PDMA Request Source Select Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |REQSRC0 |Channel 0 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 0 + * | | |User can configure the peripheral by setting REQSRC0. + * | | |0 = Disable PDMA peripheral request. + * | | |1 = Reserved. + * | | |2 = Channel connects to USB_TX. + * | | |3 = Channel connects to USB_RX. + * | | |4 = Channel connects to UART0_TX. + * | | |5 = Channel connects to UART0_RX. + * | | |6 = Channel connects to UART1_TX. + * | | |7 = Channel connects to UART1_RX. + * | | |8 = Channel connects to UART2_TX. + * | | |9 = Channel connects to UART2_RX. + * | | |10=Channel connects to UART3_TX. + * | | |11 = Channel connects to UART3_RX. + * | | |12 = Channel connects to UART4_TX. + * | | |13 = Channel connects to UART4_RX. + * | | |14 = Channel connects to UART5_TX. + * | | |15 = Channel connects to UART5_RX. + * | | |16 = Channel connects to USCI0_TX. + * | | |17 = Channel connects to USCI0_RX. + * | | |18 = Channel connects to USCI1_TX. + * | | |19 = Channel connects to USCI1_RX. + * | | |20 = Channel connects to SPI0_TX. + * | | |21 = Channel connects to SPI0_RX. + * | | |22 = Channel connects to SPI1_TX. + * | | |23 = Channel connects to SPI1_RX. + * | | |24 = Channel connects to SPI2_TX. + * | | |25 = Channel connects to SPI2_RX. + * | | |26 = Channel connects to SPI3_TX. + * | | |27 = Channel connects to SPI3_RX. + * | | |28 = Channel connects to SPI4_TX. + * | | |29 = Channel connects to SPI4_RX. + * | | |30 = Reserved. + * | | |31 = Reserved. + * | | |32 = Channel connects to PWM0_P1_RX. + * | | |33 = Channel connects to PWM0_P2_RX. + * | | |34 = Channel connects to PWM0_P3_RX. + * | | |35 = Channel connects to PWM1_P1_RX. + * | | |36 = Channel connects to PWM1_P2_RX. + * | | |37 = Channel connects to PWM1_P3_RX. + * | | |38 = Channel connects to I2C0_TX. + * | | |39 = Channel connects to I2C0_RX. + * | | |40 = Channel connects to I2C1_TX. + * | | |41 = Channel connects to I2C1_RX. + * | | |42 = Channel connects to I2C2_TX. + * | | |43 = Channel connects to I2C2_RX. + * | | |44 = Channel connects to I2S0_TX. + * | | |45 = Channel connects to I2S0_RX. + * | | |46 = Channel connects to TMR0. + * | | |47 = Channel connects to TMR1. + * | | |48 = Channel connects to TMR2. + * | | |49 = Channel connects to TMR3. + * | | |50 = Channel connects to ADC_RX. + * | | |51 = Channel connects to DAC0_TX. + * | | |52 = Channel connects to DAC1_TX. + * | | |53 = Channel connects to PWM0_CH0_TX. + * | | |54 = Channel connects to PWM0_CH1_TX. + * | | |55 = Channel connects to PWM0_CH2_TX. + * | | |56 = Channel connects to PWM0_CH3_TX. + * | | |57 = Channel connects to PWM0_CH4_TX. + * | | |58 = Channel connects to PWM0_CH5_TX. + * | | |59 = Channel connects to PWM1_CH0_TX. + * | | |60 = Channel connects to PWM1_CH1_TX. + * | | |61 = Channel connects to PWM1_CH2_TX. + * | | |62 = Channel connects to PWM1_CH3_TX. + * | | |63 = Channel connects to PWM1_CH4_TX. + * | | |64 = Channel connects to PWM1_CH5_TX. + * | | |65 = Channel connects to ETMC_RX. + * | | |Others = Reserved. + * | | |Note 1: A peripheral cannot be assigned to two channels at the same time. + * | | |Note 2: This field is useless when transfer between memory and memory. + * |[14:8] |REQSRC1 |Channel 1 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 1 + * | | |User can configure the peripheral setting by REQSRC1. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[22:16] |REQSRC2 |Channel 2 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 2 + * | | |User can configure the peripheral setting by REQSRC2. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[30:24] |REQSRC3 |Channel 3 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 3 + * | | |User can configure the peripheral setting by REQSRC3. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * @var PDMA_T::REQSEL4_7 + * Offset: 0x484 PDMA Request Source Select Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |REQSRC4 |Channel 4 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 4 + * | | |User can configure the peripheral setting by REQSRC4. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[14:8] |REQSRC5 |Channel 5 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 5 + * | | |User can configure the peripheral setting by REQSRC5. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[22:16] |REQSRC6 |Channel 6 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 6 + * | | |User can configure the peripheral setting by REQSRC6. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[30:24] |REQSRC7 |Channel 7 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 7 + * | | |User can configure the peripheral setting by REQSRC7. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + */ + DSCT_T DSCT[8]; /*!< [0x0000 ~ 0x007C] Control Register of PDMA Channel 0 ~ 7 */ + __I uint32_t RESERVE0[32]; + __I uint32_t CURSCAT[8]; /*!< [0x0100 ~ 0x11c] Current Scatter-gather Descriptor Table Address of PDMA Channel n */ + __I uint32_t RESERVE1[184]; + __IO uint32_t CHCTL; /*!< [0x0400] PDMA Channel Control Register */ + __O uint32_t PAUSE; /*!< [0x0404] PDMA Transfer Pause Control Register */ + __O uint32_t SWREQ; /*!< [0x0408] PDMA Software Request Register */ + __I uint32_t TRGSTS; /*!< [0x040c] PDMA Channel Request Status Register */ + __IO uint32_t PRISET; /*!< [0x0410] PDMA Fixed Priority Setting Register */ + __O uint32_t PRICLR; /*!< [0x0414] PDMA Fixed Priority Clear Register */ + __IO uint32_t INTEN; /*!< [0x0418] PDMA Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x041c] PDMA Interrupt Status Register */ + __IO uint32_t ABTSTS; /*!< [0x0420] PDMA Channel Read/Write Target Abort Flag Register */ + __IO uint32_t TDSTS; /*!< [0x0424] PDMA Channel Transfer Done Flag Register */ + __IO uint32_t ALIGN; /*!< [0x0428] PDMA Transfer Alignment Status Register */ + __I uint32_t TACTSTS; /*!< [0x042c] PDMA Transfer Active Flag Register */ + __IO uint32_t TOUTPSC; /*!< [0x0430] PDMA Time-out Prescaler Register */ + __IO uint32_t TOUTEN; /*!< [0x0434] PDMA Time-out Enable Register */ + __IO uint32_t TOUTIEN; /*!< [0x0438] PDMA Time-out Interrupt Enable Register */ + __IO uint32_t SCATBA; /*!< [0x043c] PDMA Scatter-gather Descriptor Table Base Address Register */ + __IO uint32_t TOC0_1; /*!< [0x0440] PDMA Time-out Counter Ch1 and Ch0 Register */ + __I uint32_t RESERVE2[7]; + __IO uint32_t CHRST; /*!< [0x0460] PDMA Channel Reset Register */ + __I uint32_t RESERVE3[7]; + __IO uint32_t REQSEL0_3; /*!< [0x0480] PDMA Request Source Select Register 0 */ + __IO uint32_t REQSEL4_7; /*!< [0x0484] PDMA Request Source Select Register 1 */ + __I uint32_t RESERVE4[30]; + STRIDE_T STRIDE[6]; /*!< [0x0500 ~ 0x528] Stride Register of PDMA Channel 0 ~ 5 */ +} PDMA_T; + +/** + @addtogroup PDMA_CONST PDMA Bit Field Definition + Constant Definitions for PDMA Controller +@{ */ + +#define PDMA_DSCT_CTL_OPMODE_Pos (0) /*!< PDMA_T::DSCT_CTL: OPMODE Position */ +#define PDMA_DSCT_CTL_OPMODE_Msk (0x3ul << PDMA_DSCT_CTL_OPMODE_Pos) /*!< PDMA_T::DSCT_CTL: OPMODE Mask */ + +#define PDMA_DSCT_CTL_TXTYPE_Pos (2) /*!< PDMA_T::DSCT_CTL: TXTYPE Position */ +#define PDMA_DSCT_CTL_TXTYPE_Msk (0x1ul << PDMA_DSCT_CTL_TXTYPE_Pos) /*!< PDMA_T::DSCT_CTL: TXTYPE Mask */ + +#define PDMA_DSCT_CTL_BURSIZE_Pos (4) /*!< PDMA_T::DSCT_CTL: BURSIZE Position */ +#define PDMA_DSCT_CTL_BURSIZE_Msk (0x7ul << PDMA_DSCT_CTL_BURSIZE_Pos) /*!< PDMA_T::DSCT_CTL: BURSIZE Mask */ + +#define PDMA_DSCT_CTL_TBINTDIS_Pos (7) /*!< PDMA_T::DSCT_CTL: TBINTDIS Position */ +#define PDMA_DSCT_CTL_TBINTDIS_Msk (0x1ul << PDMA_DSCT_CTL_TBINTDIS_Pos) /*!< PDMA_T::DSCT_CTL: TBINTDIS Mask */ + +#define PDMA_DSCT_CTL_SAINC_Pos (8) /*!< PDMA_T::DSCT_CTL: SAINC Position */ +#define PDMA_DSCT_CTL_SAINC_Msk (0x3ul << PDMA_DSCT_CTL_SAINC_Pos) /*!< PDMA_T::DSCT_CTL: SAINC Mask */ + +#define PDMA_DSCT_CTL_DAINC_Pos (10) /*!< PDMA_T::DSCT_CTL: DAINC Position */ +#define PDMA_DSCT_CTL_DAINC_Msk (0x3ul << PDMA_DSCT_CTL_DAINC_Pos) /*!< PDMA_T::DSCT_CTL: DAINC Mask */ + +#define PDMA_DSCT_CTL_TXWIDTH_Pos (12) /*!< PDMA_T::DSCT_CTL: TXWIDTH Position */ +#define PDMA_DSCT_CTL_TXWIDTH_Msk (0x3ul << PDMA_DSCT_CTL_TXWIDTH_Pos) /*!< PDMA_T::DSCT_CTL: TXWIDTH Mask */ + +#define PDMA_DSCT_CTL_TXACK_Pos (14) /*!< PDMA_T::DSCT_CTL: TXACK Position */ +#define PDMA_DSCT_CTL_TXACK_Msk (0x1ul << PDMA_DSCT_CTL_TXACK_Pos) /*!< PDMA_T::DSCT_CTL: TXACK Mask */ + +#define PDMA_DSCT_CTL_STRIDE_EN_Pos (15) /*!< PDMA_T::DSCT_CTL: STRIDEEN Position */ +#define PDMA_DSCT_CTL_STRIDE_EN_Msk (0x1ul << PDMA_DSCT_CTL_STRIDE_EN_Pos) /*!< PDMA_T::DSCT_CTL: STRIDEEN Mask */ + +#define PDMA_DSCT_CTL_TXCNT_Pos (16) /*!< PDMA_T::DSCT_CTL: TXCNT Position */ +#define PDMA_DSCT_CTL_TXCNT_Msk (0xfffful << PDMA_DSCT_CTL_TXCNT_Pos) /*!< PDMA_T::DSCT_CTL: TXCNT Mask */ + +#define PDMA_DSCT_SA_SA_Pos (0) /*!< PDMA_T::DSCT_SA: SA Position */ +#define PDMA_DSCT_SA_SA_Msk (0xfffffffful << PDMA_DSCT_SA_SA_Pos) /*!< PDMA_T::DSCT_SA: SA Mask */ + +#define PDMA_DSCT_DA_DA_Pos (0) /*!< PDMA_T::DSCT_DA: DA Position */ +#define PDMA_DSCT_DA_DA_Msk (0xfffffffful << PDMA_DSCT_DA_DA_Pos) /*!< PDMA_T::DSCT_DA: DA Mask */ + +#define PDMA_DSCT_NEXT_NEXT_Pos (0) /*!< PDMA_T::DSCT_NEXT: NEXT Position */ +#define PDMA_DSCT_NEXT_NEXT_Msk (0xfffful << PDMA_DSCT_NEXT_NEXT_Pos) /*!< PDMA_T::DSCT_NEXT: NEXT Mask */ + +#define PDMA_DSCT_NEXT_EXENEXT_Pos (16) /*!< PDMA_T::DSCT_NEXT: EXENEXT Position */ +#define PDMA_DSCT_NEXT_EXENEXT_Msk (0xfffful << PDMA_DSCT0_NEXT_EXENEXT_Pos) /*!< PDMA_T::DSCT_NEXT: EXENEXT Mask */ + +#define PDMA_CURSCAT_CURADDR_Pos (0) /*!< PDMA_T::CURSCAT: CURADDR Position */ +#define PDMA_CURSCAT_CURADDR_Msk (0xfffffffful << PDMA_CURSCAT_CURADDR_Pos) /*!< PDMA_T::CURSCAT: CURADDR Mask */ + +#define PDMA_CHCTL_CHENn_Pos (0) /*!< PDMA_T::CHCTL: CHENn Position */ +#define PDMA_CHCTL_CHENn_Msk (0xfful << PDMA_CHCTL_CHENn_Pos) /*!< PDMA_T::CHCTL: CHENn Mask */ + +#define PDMA_PAUSE_PAUSEn_Pos (0) /*!< PDMA_T::PAUSE: PAUSEn Position */ +#define PDMA_PAUSE_PAUSEn_Msk (0xfful << PDMA_PAUSE_PAUSEn_Pos) /*!< PDMA_T::PAUSE: PAUSEn Mask */ + +#define PDMA_SWREQ_SWREQn_Pos (0) /*!< PDMA_T::SWREQ: SWREQn Position */ +#define PDMA_SWREQ_SWREQn_Msk (0xfful << PDMA_SWREQ_SWREQn_Pos) /*!< PDMA_T::SWREQ: SWREQn Mask */ + +#define PDMA_TRGSTS_REQSTSn_Pos (0) /*!< PDMA_T::TRGSTS: REQSTSn Position */ +#define PDMA_TRGSTS_REQSTSn_Msk (0xfful << PDMA_TRGSTS_REQSTSn_Pos) /*!< PDMA_T::TRGSTS: REQSTSn Mask */ + +#define PDMA_PRISET_FPRISETn_Pos (0) /*!< PDMA_T::PRISET: FPRISETn Position */ +#define PDMA_PRISET_FPRISETn_Msk (0xfful << PDMA_PRISET_FPRISETn_Pos) /*!< PDMA_T::PRISET: FPRISETn Mask */ + +#define PDMA_PRICLR_FPRICLRn_Pos (0) /*!< PDMA_T::PRICLR: FPRICLRn Position */ +#define PDMA_PRICLR_FPRICLRn_Msk (0xfful << PDMA_PRICLR_FPRICLRn_Pos) /*!< PDMA_T::PRICLR: FPRICLRn Mask */ + +#define PDMA_INTEN_INTENn_Pos (0) /*!< PDMA_T::INTEN: INTENn Position */ +#define PDMA_INTEN_INTENn_Msk (0xfffful << PDMA_INTEN_INTENn_Pos) /*!< PDMA_T::INTEN: INTENn Mask */ + +#define PDMA_INTSTS_ABTIF_Pos (0) /*!< PDMA_T::INTSTS: ABTIF Position */ +#define PDMA_INTSTS_ABTIF_Msk (0x1ul << PDMA_INTSTS_ABTIF_Pos) /*!< PDMA_T::INTSTS: ABTIF Mask */ + +#define PDMA_INTSTS_TDIF_Pos (1) /*!< PDMA_T::INTSTS: TDIF Position */ +#define PDMA_INTSTS_TDIF_Msk (0x1ul << PDMA_INTSTS_TDIF_Pos) /*!< PDMA_T::INTSTS: TDIF Mask */ + +#define PDMA_INTSTS_ALIGNF_Pos (2) /*!< PDMA_T::INTSTS: ALIGNF Position */ +#define PDMA_INTSTS_ALIGNF_Msk (0x1ul << PDMA_INTSTS_ALIGNF_Pos) /*!< PDMA_T::INTSTS: ALIGNF Mask */ + +#define PDMA_INTSTS_REQTOF0_Pos (8) /*!< PDMA_T::INTSTS: REQTOF0 Position */ +#define PDMA_INTSTS_REQTOF0_Msk (0x1ul << PDMA_INTSTS_REQTOF0_Pos) /*!< PDMA_T::INTSTS: REQTOF0 Mask */ + +#define PDMA_INTSTS_REQTOF1_Pos (9) /*!< PDMA_T::INTSTS: REQTOF1 Position */ +#define PDMA_INTSTS_REQTOF1_Msk (0x1ul << PDMA_INTSTS_REQTOF1_Pos) /*!< PDMA_T::INTSTS: REQTOF1 Mask */ + +#define PDMA_ABTSTS_ABTIF0_Pos (0) /*!< PDMA_T::ABTSTS: ABTIF0 Position */ +#define PDMA_ABTSTS_ABTIF0_Msk (0x1ul << PDMA_ABTSTS_ABTIF0_Pos) /*!< PDMA_T::ABTSTS: ABTIF0 Mask */ + +#define PDMA_ABTSTS_ABTIF1_Pos (1) /*!< PDMA_T::ABTSTS: ABTIF1 Position */ +#define PDMA_ABTSTS_ABTIF1_Msk (0x1ul << PDMA_ABTSTS_ABTIF1_Pos) /*!< PDMA_T::ABTSTS: ABTIF1 Mask */ + +#define PDMA_ABTSTS_ABTIF2_Pos (2) /*!< PDMA_T::ABTSTS: ABTIF2 Position */ +#define PDMA_ABTSTS_ABTIF2_Msk (0x1ul << PDMA_ABTSTS_ABTIF2_Pos) /*!< PDMA_T::ABTSTS: ABTIF2 Mask */ + +#define PDMA_ABTSTS_ABTIF3_Pos (3) /*!< PDMA_T::ABTSTS: ABTIF3 Position */ +#define PDMA_ABTSTS_ABTIF3_Msk (0x1ul << PDMA_ABTSTS_ABTIF3_Pos) /*!< PDMA_T::ABTSTS: ABTIF3 Mask */ + +#define PDMA_ABTSTS_ABTIF4_Pos (4) /*!< PDMA_T::ABTSTS: ABTIF4 Position */ +#define PDMA_ABTSTS_ABTIF4_Msk (0x1ul << PDMA_ABTSTS_ABTIF4_Pos) /*!< PDMA_T::ABTSTS: ABTIF4 Mask */ + +#define PDMA_ABTSTS_ABTIF5_Pos (5) /*!< PDMA_T::ABTSTS: ABTIF5 Position */ +#define PDMA_ABTSTS_ABTIF5_Msk (0x1ul << PDMA_ABTSTS_ABTIF5_Pos) /*!< PDMA_T::ABTSTS: ABTIF5 Mask */ + +#define PDMA_ABTSTS_ABTIF6_Pos (6) /*!< PDMA_T::ABTSTS: ABTIF6 Position */ +#define PDMA_ABTSTS_ABTIF6_Msk (0x1ul << PDMA_ABTSTS_ABTIF6_Pos) /*!< PDMA_T::ABTSTS: ABTIF6 Mask */ + +#define PDMA_ABTSTS_ABTIF7_Pos (7) /*!< PDMA_T::ABTSTS: ABTIF7 Position */ +#define PDMA_ABTSTS_ABTIF7_Msk (0x1ul << PDMA_ABTSTS_ABTIF7_Pos) /*!< PDMA_T::ABTSTS: ABTIF7 Mask */ + +#define PDMA_TDSTS_TDIF0_Pos (0) /*!< PDMA_T::TDSTS: TDIF0 Position */ +#define PDMA_TDSTS_TDIF0_Msk (0x1ul << PDMA_TDSTS_TDIF0_Pos) /*!< PDMA_T::TDSTS: TDIF0 Mask */ + +#define PDMA_TDSTS_TDIF1_Pos (1) /*!< PDMA_T::TDSTS: TDIF1 Position */ +#define PDMA_TDSTS_TDIF1_Msk (0x1ul << PDMA_TDSTS_TDIF1_Pos) /*!< PDMA_T::TDSTS: TDIF1 Mask */ + +#define PDMA_TDSTS_TDIF2_Pos (2) /*!< PDMA_T::TDSTS: TDIF2 Position */ +#define PDMA_TDSTS_TDIF2_Msk (0x1ul << PDMA_TDSTS_TDIF2_Pos) /*!< PDMA_T::TDSTS: TDIF2 Mask */ + +#define PDMA_TDSTS_TDIF3_Pos (3) /*!< PDMA_T::TDSTS: TDIF3 Position */ +#define PDMA_TDSTS_TDIF3_Msk (0x1ul << PDMA_TDSTS_TDIF3_Pos) /*!< PDMA_T::TDSTS: TDIF3 Mask */ + +#define PDMA_TDSTS_TDIF4_Pos (4) /*!< PDMA_T::TDSTS: TDIF4 Position */ +#define PDMA_TDSTS_TDIF4_Msk (0x1ul << PDMA_TDSTS_TDIF4_Pos) /*!< PDMA_T::TDSTS: TDIF4 Mask */ + +#define PDMA_TDSTS_TDIF5_Pos (5) /*!< PDMA_T::TDSTS: TDIF5 Position */ +#define PDMA_TDSTS_TDIF5_Msk (0x1ul << PDMA_TDSTS_TDIF5_Pos) /*!< PDMA_T::TDSTS: TDIF5 Mask */ + +#define PDMA_TDSTS_TDIF6_Pos (6) /*!< PDMA_T::TDSTS: TDIF6 Position */ +#define PDMA_TDSTS_TDIF6_Msk (0x1ul << PDMA_TDSTS_TDIF6_Pos) /*!< PDMA_T::TDSTS: TDIF6 Mask */ + +#define PDMA_TDSTS_TDIF7_Pos (7) /*!< PDMA_T::TDSTS: TDIF7 Position */ +#define PDMA_TDSTS_TDIF7_Msk (0x1ul << PDMA_TDSTS_TDIF7_Pos) /*!< PDMA_T::TDSTS: TDIF7 Mask */ + +#define PDMA_ALIGN_ALIGNn_Pos (0) /*!< PDMA_T::ALIGN: ALIGNn Position */ +#define PDMA_ALIGN_ALIGNn_Msk (0xfful << PDMA_ALIGN_ALIGNn_Pos) /*!< PDMA_T::ALIGN: ALIGNn Mask */ + +#define PDMA_TACTSTS_TXACTFn_Pos (0) /*!< PDMA_T::TACTSTS: TXACTFn Position */ +#define PDMA_TACTSTS_TXACTFn_Msk (0xfful << PDMA_TACTSTS_TXACTFn_Pos) /*!< PDMA_T::TACTSTS: TXACTFn Mask */ + +#define PDMA_TOUTPSC_TOUTPSC0_Pos (0) /*!< PDMA_T::TOUTPSC: TOUTPSC0 Position */ +#define PDMA_TOUTPSC_TOUTPSC0_Msk (0x7ul << PDMA_TOUTPSC_TOUTPSC0_Pos) /*!< PDMA_T::TOUTPSC: TOUTPSC0 Mask */ + +#define PDMA_TOUTPSC_TOUTPSC1_Pos (4) /*!< PDMA_T::TOUTPSC: TOUTPSC1 Position */ +#define PDMA_TOUTPSC_TOUTPSC1_Msk (0x7ul << PDMA_TOUTPSC_TOUTPSC1_Pos) /*!< PDMA_T::TOUTPSC: TOUTPSC1 Mask */ + +#define PDMA_TOUTEN_TOUTENn_Pos (0) /*!< PDMA_T::TOUTEN: TOUTENn Position */ +#define PDMA_TOUTEN_TOUTENn_Msk (0x3ul << PDMA_TOUTEN_TOUTENn_Pos) /*!< PDMA_T::TOUTEN: TOUTENn Mask */ + +#define PDMA_TOUTIEN_TOUTIENn_Pos (0) /*!< PDMA_T::TOUTIEN: TOUTIENn Position */ +#define PDMA_TOUTIEN_TOUTIENn_Msk (0x3ul << PDMA_TOUTIEN_TOUTIENn_Pos) /*!< PDMA_T::TOUTIEN: TOUTIENn Mask */ + +#define PDMA_SCATBA_SCATBA_Pos (16) /*!< PDMA_T::SCATBA: SCATBA Position */ +#define PDMA_SCATBA_SCATBA_Msk (0xfffful << PDMA_SCATBA_SCATBA_Pos) /*!< PDMA_T::SCATBA: SCATBA Mask */ + +#define PDMA_TOC0_1_TOC0_Pos (0) /*!< PDMA_T::TOC0_1: TOC0 Position */ +#define PDMA_TOC0_1_TOC0_Msk (0xfffful << PDMA_TOC0_1_TOC0_Pos) /*!< PDMA_T::TOC0_1: TOC0 Mask */ + +#define PDMA_TOC0_1_TOC1_Pos (16) /*!< PDMA_T::TOC0_1: TOC1 Position */ +#define PDMA_TOC0_1_TOC1_Msk (0xfffful << PDMA_TOC0_1_TOC1_Pos) /*!< PDMA_T::TOC0_1: TOC1 Mask */ + +#define PDMA_CHRST_CHnRST_Pos (0) /*!< PDMA_T::CHRST: CHnRST Position */ +#define PDMA_CHRST_CHnRST_Msk (0xfffful << PDMA_CHRST_CHnRST_Pos) /*!< PDMA_T::CHRST: CHnRST Mask */ + +#define PDMA_REQSEL0_3_REQSRC0_Pos (0) /*!< PDMA_T::REQSEL0_3: REQSRC0 Position */ +#define PDMA_REQSEL0_3_REQSRC0_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC0_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC0 Mask */ + +#define PDMA_REQSEL0_3_REQSRC1_Pos (8) /*!< PDMA_T::REQSEL0_3: REQSRC1 Position */ +#define PDMA_REQSEL0_3_REQSRC1_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC1_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC1 Mask */ + +#define PDMA_REQSEL0_3_REQSRC2_Pos (16) /*!< PDMA_T::REQSEL0_3: REQSRC2 Position */ +#define PDMA_REQSEL0_3_REQSRC2_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC2_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC2 Mask */ + +#define PDMA_REQSEL0_3_REQSRC3_Pos (24) /*!< PDMA_T::REQSEL0_3: REQSRC3 Position */ +#define PDMA_REQSEL0_3_REQSRC3_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC3_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC3 Mask */ + +#define PDMA_REQSEL4_7_REQSRC4_Pos (0) /*!< PDMA_T::REQSEL4_7: REQSRC4 Position */ +#define PDMA_REQSEL4_7_REQSRC4_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC4_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC4 Mask */ + +#define PDMA_REQSEL4_7_REQSRC5_Pos (8) /*!< PDMA_T::REQSEL4_7: REQSRC5 Position */ +#define PDMA_REQSEL4_7_REQSRC5_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC5_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC5 Mask */ + +#define PDMA_REQSEL4_7_REQSRC6_Pos (16) /*!< PDMA_T::REQSEL4_7: REQSRC6 Position */ +#define PDMA_REQSEL4_7_REQSRC6_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC6_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC6 Mask */ + +#define PDMA_REQSEL4_7_REQSRC7_Pos (24) /*!< PDMA_T::REQSEL4_7: REQSRC7 Position */ +#define PDMA_REQSEL4_7_REQSRC7_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC7_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC7 Mask */ + +#define PDMA_STCR_STC_Pos (0) /*!< PDMA_T::STCR: STC Position */ +#define PDMA_STCR_STC_Msk (0xfffful << PDMA_STCR_STC_Pos) /*!< PDMA_T::STCR: STC Mask */ + +#define PDMA_ASOCR_SASOL_Pos (0) /*!< PDMA_T::ASOCR: SASOL Position */ +#define PDMA_ASOCR_SASOL_Msk (0xfffful << PDMA_ASOCR_SASOL_Pos) /*!< PDMA_T::ASOCR: SASOL Mask */ + +#define PDMA_ASOCR_DASOL_Pos (16) /*!< PDMA_T::ASOCR: DASOL Position */ +#define PDMA_ASOCR_DASOL_Msk (0xfffful << PDMA_ASOCR_DASOL_Pos) /*!< PDMA_T::ASOCR: DASOL Mask */ + +/**@}*/ /* PDMA_CONST */ +/**@}*/ /* end of PDMA register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __PDMA_REG_H__ */ \ No newline at end of file diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/psio_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/psio_reg.h new file mode 100644 index 00000000000..ac34f92d7a2 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/psio_reg.h @@ -0,0 +1,1450 @@ +/**************************************************************************//** + * @file psio_reg.h + * @version V1.00 + * @brief PSIO register definition header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __PSIO_REG_H__ +#define __PSIO_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup PSIO Programable Serial IO (PSIO) + Memory Mapped Structure for PSIO Controller +@{ */ + +typedef struct +{ + /** + * @var SCCT_T::SCCTL + * Offset: 0x20 PSIO Slot Controller n Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |INISLOT |Initial Slot Period + * | | |The initial slot of the repeat period + * | | |0000 = No use. + * | | |0001 = SLOT0. + * | | |0010 = SLOT1. + * | | |0011 = SLOT2. + * | | |0100 = SLOT3. + * | | |0101 = SLOT4. + * | | |0110 = SLOT5. + * | | |0111 = SLOT6. + * | | |1000 = SLOT7. + * |[7:4] |ENDSLOT |End Slot Period + * | | |The end slot of the repeat period + * | | |0000 = No use. + * | | |0001 = SLOT0. + * | | |0010 = SLOT1. + * | | |0011 = SLOT2. + * | | |0100 = SLOT3. + * | | |0101 = SLOT4. + * | | |0110 = SLOT5. + * | | |0111 = SLOT6. + * | | |1000 = SLOT7. + * |[13:8] |SPLCNT |Slot Period Loop Count + * | | |000000 ~ 111110: loop count + * | | |000000 = slot period loop count function is disable. + * | | |000001= repeat selection loop once, which means total go through selected repeat slots 2 times. + * | | |111111 = loop until stop PSIO slot controller. + * | | |Note1: If setting this register 111111 with PDMA mode and OUTPUT mode, it will stop automatically when PDMA is finish and output data in shift register is finished. + * | | |Note2: If setting this register 111111 with PDMA mode and INPUT mode, it will stop automatically when pdma is finish. + * | | |Note3: If PSIO receives stop instruction during repeat mode, it will stop only when the current loop is finished. + * |[15:14] |TRIGSRC |PSIO_TMRxPSIO_SCn Trigger Source + * | | |00 = Trigger by software. + * | | |01 = Trigger PSIO_TMRxPSIO_SCn when related PSIO_PIN occurred falling edge. + * | | |02 = Trigger PSIO_TMRxPSIO_SCn when related PSIO_PIN occurred rising edge. + * | | |03 = Trigger PSIO_TMRxPSIO_SCn when related PSIO_PIN occurred rising edge or falling edge. + * | | |Note1: PSIO slot controller pin can only be trigger by related pins which is setting from PSIOn_GENCTL[25:24] SC_SEL. + * | | |Note2: Configuring rising or falling signal trigger PSIO, the signal need to hold for at least two PSIO_CLK for de-bounce or PSIO will not be triggered. + * |[16] |START |PSIO_TMRxPSIO_SCn Start + * | | |0 = Stop PSIO_TMRxPSIO_SCn. + * | | |1 = Start PSIO_TMRxPSIO_SCn to count and active related PSIO_PIN. + * | | |Note: this bit is always read as 0. + * |[17] |REPEAT |Whole Repeat Mode + * | | |Slot controller repeats counting forever. It can stop by clear START bit. + * | | |0 = Repeat mode disabled. + * | | |1 = Repeat mode enabled. + * | | |Note1: If this bit is enabled with PDMA mode, slot controller will stop automatically when the PDMA finish transferring number of data. + * | | |Note2: If PSIO receives stop instruction during repeat mode, it will stop only when the current loop is finished. + * |[24] |BUSY |PSIO_TMRxPSIO_SCn Busy Flag + * | | |0 = PSIO_TMRxPSIO_SCn is not busy. + * | | |1 = PSIO_TMRxPSIO_SCn is busy. + * | | |Note: This bit will be set to 1 when slot controller start to count automatically and it will be cleared to 0 automatically when slot controller stop counting, too + * |[25] |IDLE |PSIO_TMRxPSIO_SCn Idle Flag + * | | |0 = PSIO_TMRxPSIO_SCn is not IDLE. + * | | |1 = PSIO_TMRxPSIO_SCn is IDLE. + * | | |Note1: This bit will be cleared to 0 when slot controller start to count automatically. + * | | |Note2: This bit will be set to 1 when configuring it 1 by software. + * | | |Note3: This bit is set to distinguish INTERVAL_OUTPUT(PSIOn_GENCTL[5:4]) and INITIAL_OUTPUT(PSIOn_GENCTL[3:2]). + * @var SCCT_T::SCSLOT + * Offset: 0x24 PSIO Slot Controller n Slot Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |SLOT0 |PSIO Slot Controller Slot0 Tick Count + * | | |0 to 15 + * | | |Note1: Filling in all 0 to this field indicates to disable this slot. + * | | |Note2: The disabled slot should not be set between the enabled slots, or the order of enabled slot which is after the disabled slot will not be enable. + * | | |Note3: The shortest slot length is 6 when I/O mode is switched from output mode to input mode. + * |[7:4] |SLOT1 |PSIO Slot Controller Slot1 Tick Count + * | | |0 to 15 + * | | |Note1: Filling in all 0 to this field indicates to disable this slot. + * | | |Note2: The disabled slot should not be set between the enabled slots, or the order of enabled slot which is after the disabled slot will not be enable. + * | | |Note3: The shortest slot length is 6 when I/O mode is switched from output mode to input mode. + * |[11:8] |SLOT2 |PSIO Slot Controller Slot2 Tick Count + * | | |0 to 15 + * | | |Note1: Filling in all 0 to this field indicates to disable this slot. + * | | |Note2: The disabled slot should not be set between the enabled slots, or the order of enabled slot which is after the disabled slot will not be enable. + * | | |Note3: The shortest slot length is 6 when I/O mode is switched from output mode to input mode. + * |[15:12] |SLOT3 |PSIO Slot Controller Slot3 Tick Count + * | | |0 to 15. + * | | |Note1: Filling in all 0 to this field indicates to disable this slot. + * | | |Note2: The disabled slot should not be set between the enabled slots, or the order of enabled slot which is after the disabled slot will not be enable. + * | | |Note3: The shortest slot length is 6 when I/O mode is switched from output mode to input mode. + * |[19:16] |SLOT4 |PSIO Slot Controller Slot4 Tick Count + * | | |0 to 15 + * | | |Note1: Filling in all 0 to this field indicates to disable this slot. + * | | |Note2: The disabled slot should not be set between the enabled slots, or the order of enabled slot which is after the disabled slot will not be enable. + * | | |Note3: The shortest slot length is 6 when I/O mode is switched from output mode to input mode. + * |[23:20] |SLOT5 |PSIO Slot Controller Slot5 Tick Count + * | | |0 to 15 + * | | |Note1: Filling in all 0 to this field indicates to disable this slot. + * | | |Note2: The disabled slot should not be set between the enabled slots, or the order of enabled slot which is after the disabled slot will not be enable. + * | | |Note3: The shortest slot length is 6 when I/O mode is switched from output mode to input mode. + * |[27:24] |SLOT6 |PSIO Slot Controller Slot6 Tick Count + * | | |0 to 15 + * | | |Note1: Filling in all 0 to this field indicates to disable this slot. + * | | |Note2: The disabled slot should not be set between the enabled slots, or the order of enabled slot which is after the disabled slot will not be enable. + * | | |Note3: The shortest slot length is 6 when I/O mode is switched from output mode to input mode. + * |[31:28] |SLOT7 |PSIO Slot Controller Slot7 Tick Count + * | | |0 to 15 + * | | |Note1: Filling in all 0 to this field indicates to disable this slot. + * | | |Note2: The disabled slot should not be set between the enabled slots, or the order of enabled slot which is after the disabled slot will not be enable. + * | | |Note3: The shortest slot length is 6 when I/O mode is switched from output mode to input mode. + */ + __IO uint32_t SCCTL; /*!< PSIO Slot Counter n Control register */ + __IO uint32_t SCSLOT; /*!< PSIO Slot Counter n Slot Register */ + +} SCCT_T; + +typedef struct +{ + /** + * @var GNCT_T::GENCTL + * Offset: 0x40 PSIOn General Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |IOMODE |IO Mode + * | | |I/O mode state represent the I/O state when slot controller has not started counting or slot controller has started counting but has not cross the switch I/O mode check point. + * | | |00 = Input mode. + * | | |01 = Output mode. + * | | |10 = Open-drain. + * | | |11 = Quasi-bidirectional Mode. + * | | |Note1: When slot controller stops counting, it will switch to the current I/O mode setting. + * | | |Note2: When PSIO uses quasi mode or open drain mode to trigger slot controller, the initial or interval state need to be set output high level, or the pin will not be trigger. + * |[3:2] |INITIAL |Initial Output + * | | |The output state of PSIO when slot controller stops counting and IDLE (PSIO_SCnCTL[25]) is 1. + * | | |00 = Low level. + * | | |01 = High level. + * | | |10 = Last output. + * | | |11 = Toggle. + * | | |Note1: Only when IO_MODE is not input mode, then this register is effective. + * | | |Note2: This bit is effective only when IDLE(PSIO_SCnCTL[25]) is high. + * |[5:4] |INTERVAL |Interval Output + * | | |The output of PSIO when slot controller stops counting and IDLE (PSIO_SCnCTL[25]) is 0. + * | | |00 = Low level. + * | | |01 = High level. + * | | |10 = Last output. + * | | |11 = Toggle. + * | | |Note1: Only when IO_MODE is not input mode, then this register is effective. + * | | |Note2: This bit is effective only when IDLE(PSIO_SCnCTL[25]) is low. + * |[11:8] |SW0CP |Switch0 Check Point + * | | |0000 = No use. + * | | |0001 = CHECK POINT0. + * | | |0010 = CHECK POINT1. + * | | |0011 = CHECK POINT 2. + * | | |0100 = CHECK POINT 3. + * | | |0101 = CHECK POINT 4. + * | | |0110 = CHECK POINT 5. + * | | |0111= CHECK POINT 6. + * | | |1000 = CHECK POINT 7. + * | | |Others: reserved + * |[15:12] |SW1CP |Switch1 Check Point + * | | |0000 = No use. + * | | |0001 = CHECK POINT0. + * | | |0010 = CHECK POINT1. + * | | |0011 = CHECK POINT 2. + * | | |0100 = CHECK POINT 3. + * | | |0101 = CHECK POINT 4. + * | | |0110 = CHECK POINT 5. + * | | |0111= CHECK POINT 6. + * | | |1000 = CHECK POINT 7. + * | | |Others: reserved + * |[17:16] |MODESW0 |Mode Switch0 Point + * | | |Mode at the switch0 point + * | | |00 = Input mode. + * | | |01 = Output mode. + * | | |10 = Open-drain. + * | | |11 = Quasi-bidirectional Mode. + * |[19:18] |MODESW1 |Mode Switch1 Point + * | | |Mode at the switch1 point + * | | |00 = Input mode. + * | | |01 = Output mode. + * | | |10 = Open-drain mode. + * | | |11 = Quasi-bidirectional Mode. + * |[25:24] |SCSEL |Slot Controller Selection + * | | |Select slot controller for check point + * | | |00 = SLOT CONTROLLER0. + * | | |01 = SLOT CONTROLLER1. + * | | |10 = SLOT CONTROLLER2. + * | | |11 = SLOT CONTROLLER3. + * |[26] |PINEN |Pin Enable Bit + * | | |0 = Pin Disabled. + * | | |1 = Pin Enabled. + * @var GNCT_T::DATCTL + * Offset: 0x44 PSIOn Data Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |OUTDATWD |Output Data Width + * | | |Indicate the data width of OUTPUT DATA register. + * | | |Output data size = OUTDATWD +1. + * | | |e.g. + * | | |5'b00000 = 1 bit. + * | | |5'b11111=32 bit. + * |[12:8] |INDATWD |Input Data Width + * | | |Indicate the data width of INPUT DATA register. + * | | |Input data size = INDATWD +1. + * | | |e.g. + * | | |5'b00000 = 1 bit. + * | | |5'b11111=32 bit. + * |[16] |ORDER |Order + * | | |The order of output data and input data + * | | |Data transfer start form + * | | |0 = LSB. + * | | |1 = MSB. + * |[25:24] |OUTDEPTH |Output Data Depth + * | | |Represent the data depth of the output buffer, when data width is larger than 16-bit, this setting can be ignored. + * | | |When the data width is between 9-bit and 16 bit , + * | | |0 = OUTDEPTH [0], the data depth is 1. + * | | |1 = OUTDEPTH [0], the data depth is 2. + * | | |When the data width is less than or equal to 8-bit. + * | | |0 = OUTDEPTH, the data depth is 1. + * | | |1 = OUTDEPTH, the data depth is 2. + * | | |2 = OUTDEPTH, the data depth is 3. + * | | |3 = OUTDEPTH, the data depth is 4. + * | | |Note1: data depth impact when the output empty flag and output under flow flag will be set to 1. + * | | |Note2: There is no difference of data depth no matter using software program data or PDMA program data. + * |[29:28] |INDEPTH |Input Data Depth + * | | |Represent the data depth of the input buffer, when data width is larger than 16-bit, this setting can be ignored. + * | | |When the data width is between 9-bit and 16 bit , + * | | |0 = INDEPTH[0], the data depth is 1. + * | | |1 = INDEPTH[0], the data depth is 2. + * | | |When the data width is less than or equal to 8-bit. + * | | |0 = INDEPTH, the data depth is 1. + * | | |1 = INDEPTH, the data depth is 2. + * | | |2 = INDEPTH, the data depth is 3. + * | | |3 = INDEPTH, the data depth is 4. + * | | |Note1: data depth impact when the full flag and input over flow flag will be set to 1. + * | | |Note2: There is no difference of data depth no matter using software program data or PDMA program data. + * @var GNCT_T::INSTS + * Offset: 0x48 PSIOn Input Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |INSTS |Input Status + * | | |Status input buffer + * | | |(read clear) + * | | |Note: When the valid bit is set, the valid bits number of INSTS is equal to the number of check points from the previous time INSTS update to the current INSTS update. + * @var GNCT_T::INDAT + * Offset: 0x4C PSIOn Input Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |INDAT |Input Data Buffer + * | | |This register can be read clear. + * | | |Note: The input data sample time is according to the slot length + * | | |The sampling time is near 3/4 slot + * | | |When the slot length is 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, PSIO sample input data when the slot controller count to 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9. + * @var GNCT_T::OUTDAT + * Offset: 0x50 PSIOn Output Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |OUTDAT |Output Data Buffer + * | | |This field is used to configure output data. + * @var GNCT_T::CPCTL0 + * Offset: 0x54 PSIOn Check Point Control 0 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |CKPT0 |Check Point 0 + * | | |0000 = No use. + * | | |0001 = SLOT0. + * | | |0010 = SLOT1. + * | | |0011 = SLOT2. + * | | |0100 = SLOT3. + * | | |0101 = SLOT4. + * | | |0110 = SLOT5. + * | | |0111 = SLOT6. + * | | |1000 = SLOT6. + * | | |Others = Reserved. + * | | |Note1: If there are two check points select the same SLOT, pin will follow settings of the smaller check point number. + * | | |Note2: The correlated SLOT should be filled in order from SLOT0 to SLOT7, or the check point action will not be triggered. + * |[6:4] |CKPT1 |Check Point 1 + * | | |0000 = No use. + * | | |0001 = SLOT0. + * | | |0010 = SLOT1. + * | | |0011 = SLOT2. + * | | |0100 = SLOT3. + * | | |0101 = SLOT4. + * | | |0110 = SLOT5. + * | | |0111 = SLOT6. + * | | |1000 = SLOT6. + * | | |Others = Reserved. + * | | |Note1: If there are two check points select the same SLOT, pin will follow settings of the smaller check point number. + * | | |Note2: The correlated SLOT should be filled in order from SLOT0 to SLOT7, or the check point action will not be triggered. + * |[10:8] |CKPT2 |Check Point 2 + * | | |0000 = No use. + * | | |0001 = SLOT0. + * | | |0010 = SLOT1. + * | | |0011 = SLOT2. + * | | |0100 = SLOT3. + * | | |0101 = SLOT4. + * | | |0110 = SLOT5. + * | | |0111 = SLOT6. + * | | |1000 = SLOT6. + * | | |Others = Reserved. + * | | |Note1: If there are two check points select the same SLOT, pin will follow settings of the smaller check point number. + * | | |Note2: The correlated SLOT should be filled in order from SLOT0 to SLOT7, or the check point action will not be triggered. + * |[14:12] |CKPT3 |Check Point 3 + * | | |0000 = No use. + * | | |0001 = SLOT0. + * | | |0010 = SLOT1. + * | | |0011 = SLOT2. + * | | |0100 = SLOT3. + * | | |0101 = SLOT4. + * | | |0110 = SLOT5. + * | | |0111 = SLOT6. + * | | |1000 = SLOT6. + * | | |Others = Reserved. + * | | |Note1: If there are two check points select the same SLOT, pin will follow settings of the smaller check point number. + * | | |Note2: The correlated SLOT should be filled in order from SLOT0 to SLOT7, or the check point action will not be triggered. + * |[18:16] |CKPT4 |Check Point 4 + * | | |0000 = No use. + * | | |0001 = SLOT0. + * | | |0010 = SLOT1. + * | | |0011 = SLOT2. + * | | |0100 = SLOT3. + * | | |0101 = SLOT4. + * | | |0110 = SLOT5. + * | | |0111 = SLOT6. + * | | |1000 = SLOT6. + * | | |Others = Reserved. + * | | |Note1: If there are two check points select the same SLOT, pin will follow settings of the smaller check point number. + * | | |Note2: The correlated SLOT should be filled in order from SLOT0 to SLOT7, or the check point action will not be triggered. + * |[22:20] |CKPT5 |Check Point 5 + * | | |0000 = No use. + * | | |0001 = SLOT0. + * | | |0010 = SLOT1. + * | | |0011 = SLOT2. + * | | |0100 = SLOT3. + * | | |0101 = SLOT4. + * | | |0110 = SLOT5. + * | | |0111 = SLOT6. + * | | |1000 = SLOT6. + * | | |Others = Reserved. + * | | |Note1: If there are two check points select the same SLOT, pin will follow settings of the smaller check point number. + * | | |Note2: The correlated SLOT should be filled in order from SLOT0 to SLOT7, or the check point action will not be triggered. + * |[26:24] |CKPT6 |Check Point 6 + * | | |0000 = No use. + * | | |0001 = SLOT0. + * | | |0010 = SLOT1. + * | | |0011 = SLOT2. + * | | |0100 = SLOT3. + * | | |0101 = SLOT4. + * | | |0110 = SLOT5. + * | | |0111 = SLOT6. + * | | |1000 = SLOT6. + * | | |Others = Reserved. + * | | |Note1: If there are two check points select the same SLOT, pin will follow settings of the smaller check point number. + * | | |Note2: The correlated SLOT should be filled in order from SLOT0 to SLOT7, or the check point action will not be triggered. + * |[30:28] |CKPT7 |Check Point 7 + * | | |This field is used to link check point and slot controller slot. + * | | |0000 = No use. + * | | |0001 = SLOT0. + * | | |0010 = SLOT1. + * | | |0011 = SLOT2. + * | | |0100 = SLOT3. + * | | |0101 = SLOT4. + * | | |0110 = SLOT5. + * | | |0111 = SLOT6. + * | | |1000 = SLOT7. + * | | |Others = Reserved. + * | | |Note1: If there are two check points select the same SLOT, pin will follow settings of the smaller check point number. + * | | |Note2: The correlated SLOT should be filled in order from SLOT0 to SLOT7, or the check point action will not be triggered. + * @var GNCT_T::CPCTL1 + * Offset: 0x58 PSIOn Check Point Control1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |CKPT0ACT |Check Point 0 Action + * | | |Select check point action at check point0 + * | | |000 = output level low. + * | | |001 = output level high. + * | | |010 = output from data buffer. + * | | |011 = output toggle. + * | | |100 = input data buffer. + * | | |101 = input status. + * | | |110 = input status record and update. + * | | |Others = reserved. + * | | |Note: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0]) + * |[6:4] |CKPT1ACT |Check Point 1 Action + * | | |Select check point action at check point1 + * | | |000 = output level low. + * | | |001 = output level high. + * | | |010 = output from data buffer. + * | | |011 = output toggle. + * | | |100 = input data buffer. + * | | |101 = input status. + * | | |110 = input status record and update. + * | | |Others = reserved. + * | | |Note: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0]) + * |[10:8] |CKPT2ACT |Check Point 2 Action + * | | |Select check point action at check point2 + * | | |000 = output level low. + * | | |001 = output level high. + * | | |010 = output from data buffer. + * | | |011 = output toggle. + * | | |100 = input data buffer. + * | | |101 = input status. + * | | |110 = input status record and update. + * | | |Others = reserved. + * | | |Note: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0]) + * |[14:12] |CKPT3ACT |Check Point 3 Action + * | | |Select check point action at check point3 + * | | |000 = output level low. + * | | |001 = output level high. + * | | |010 = output from data buffer. + * | | |011 = output toggle. + * | | |100 = input data buffer. + * | | |101 = input status. + * | | |110 = input status record and update. + * | | |Others = reserved. + * | | |Note: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0]) + * |[18:16] |CKPT4ACT |Check Point 4 Action + * | | |Select check point action at check point4 + * | | |000 = output level low. + * | | |001 = output level high. + * | | |010 = output from data buffer. + * | | |011 = output toggle. + * | | |100 = input data buffer. + * | | |101 = input status. + * | | |110 = input status record and update. + * | | |Others = reserved. + * | | |Note: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0]) + * |[22:20] |CKPT5ACT |Check Point 5 Action + * | | |Select check point action at check point5 + * | | |000 = output level low. + * | | |001 = output level high. + * | | |010 = output from data buffer. + * | | |011 = output toggle. + * | | |100 = input data buffer. + * | | |101 = input status. + * | | |110 = input status record and update. + * | | |Others = reserved. + * | | |Note: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0]) + * |[26:24] |CKPT6ACT |Check Point 6 Action + * | | |Select check point action at check point6 + * | | |000 = output level low. + * | | |001 = output level high. + * | | |010 = output from data buffer. + * | | |011 = output toggle. + * | | |100 = input data buffer. + * | | |101 = input status. + * | | |110 = input status record and update. + * | | |Others = reserved. + * | | |Note: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0]) + * |[30:28] |CKPT7ACT |Check Point 7 Action + * | | |Select check point action at check point7 + * | | |000 = output level low. + * | | |001 = output level high. + * | | |010 = output from data buffer. + * | | |011 = output toggle. + * | | |100 = input data buffer. + * | | |101 = input status. + * | | |110 = input status record and update. + * | | |Others = reserved. + * | | |Note: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0]) + */ + __IO uint32_t GENCTL; /*!< PSIOn General Control Register */ + __IO uint32_t DATCTL; /*!< PSIOn Data Control Register */ + __I uint32_t INSTS; /*!< PSIOn Input Status Register */ + __I uint32_t INDAT; /*!< PSIOn Input Data Register */ + __O uint32_t OUTDAT; /*!< PSIOn Output Data Register */ + __IO uint32_t CPCTL0; /*!< PSIOn Check Point Control 0 Register */ + __IO uint32_t CPCTL1; /*!< PSIOn Check Point Control1 Register */ + __I uint32_t RESERVED0[1]; +} GNCT_T; + +typedef struct +{ + /** + * @var PSIO_T::INTCTL + * Offset: 0x00 PSIO Interrupt Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |CONI0SS |Configurable Interrupt 0 Slot Selection + * | | |0000: NO USE + * | | |0001: SLOT0 + * | | |0010: SLOT1 + * | | |0011: SLOT2 + * | | |0100: SLOT3 + * | | |0101: SLOT4 + * | | |0110: SLOT5 + * | | |0111: SLOT6 + * | | |1000: SLOT7 + * | | |1001 u2013 1111:Reserved + * |[6:4] |CONI1SS |Configurable Interrupt 1 Slot Selection + * | | |0000: NO USE + * | | |0001: SLOT0 + * | | |0010: SLOT1 + * | | |0011: SLOT2 + * | | |0100: SLOT3 + * | | |0101: SLOT4 + * | | |0110: SLOT5 + * | | |0111: SLOT6 + * | | |1000: SLOT7 + * | | |1001 u2013 1111:Reserved + * |[9:8] |CONI0SCS |Configurable Interrupt 0 Slot Controller Selection + * | | |Select Slot controller for INT0 + * | | |00 = Slot controller 0. + * | | |01 = Slot controller 1. + * | | |10 = Slot controller 2. + * | | |11 = Slot controller 3. + * |[13:12] |CONI1SCS |Configurable Interrupt 1 Slot Controller Selection + * | | |Select Slot controller for INT1 + * | | |00 = Slot controller 0. + * | | |01 = Slot controller 1. + * | | |10 = Slot controller 2. + * | | |11 = Slot controller 3. + * |[31] |LOOPBACK |Loop Back Test Enable Bit + * | | |If this bit is enabled, PIN0 output will be connected to PIN1 input, PIN1 output will be connected to PIN0 input. + * | | |So do the others pin. + * @var PSIO_T::INTEN + * Offset: 0x04 PSIO Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CON0IE |Configurable Interrupt 0 Enable Bit + * | | |This field is used to enable selective interrupt 0. + * | | |0 = Selective interrupt 0 Disabled. + * | | |1 = Selective interrupt 0 Enabled. + * |[1] |CON1IE |Configurable Interrupt 1 Enable Bit + * | | |This field is used to enable selective interrupt 1. + * | | |0 = Selective interrupt 1 Disabled. + * | | |1 = Selective interrupt 1 Enabled. + * |[2] |MISMATIE |Mismatch Interrupt Enable Bit + * | | |This field is used to enable mismatch interrupt. + * | | |0 = Mismatch interrupt Disabled. + * | | |1 = Mismatch interrupt Enabled. + * |[3] |TERRIE |Transfer Error Interrupt Enable Bit + * | | |This field is used to enable transfer error interrupt. + * | | |0 = Transfer error interrupt Disabled. + * | | |1 = Transfer error interrupt Enabled. + * |[4] |SC0IE |Slot Controller 0 Done Interrupt Enable Bit + * | | |This field is used to enable Slot controller 0 finish interrupt. + * | | |0 = Slot controller 0 finish interrupt Disabled. + * | | |1 = Slot controller 0 finish interrupt Enabled. + * | | |Note: This bit can be cleared by writing 1. + * |[5] |SC1IE |Slot Controller 1 Done Interrupt Enable Bit + * | | |This field is used to enable Slot controller 1 finish interrupt. + * | | |0 = Slot controller 1 finish interrupt Disabled. + * | | |1 = Slot controller 1 finish interrupt Enabled. + * | | |Note: This bit can be cleared by writing 1. + * |[6] |SC2IE |Slot Controller 2 Done Interrupt Enable Bit + * | | |This field is used to enable Slot controller 2 finish interrupt. + * | | |0 = Slot controller 2 finish interrupt Disabled. + * | | |1 = Slot controller 2 finish interrupt Enabled. + * | | |Note: This bit can be cleared by writing 1. + * |[7] |SC3IE |Slot Controller 3 Done Interrupt Enable Bit + * | | |This field is used to enable Slot controller 3 finish interrupt. + * | | |0 = Slot controller 3 finish interrupt Disabled. + * | | |1 = Slot controller 3 finish interrupt Enabled. + * | | |Note: This bit can be cleared by writing 1. + * @var PSIO_T::INTSTS + * Offset: 0x08 PSIO Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CON0IF |Configurable Interrupt 0 Flag + * | | |The setting interrupt is trigger at the end of the check point of the pin. + * | | |The setting interrupt is trigger at the end of the check point of the pin. + * | | |0 = Condition in PSIO_INTCTL is not triggered. + * | | |1 = Condition in PSIO_INTCTL is triggered. + * | | |Note: This bit can be cleared by writing 1. + * |[1] |CON1IF |Configurable Interrupt 1 Flag + * | | |The setting interrupt is trigger at the end of the check point of the pin. + * | | |0 = Condition in PSIO_INTCTL is not triggered. + * | | |1 = Condition in PSIO_INTCTL is triggered. + * | | |Note: This bit can be cleared by writing 1. + * |[2] |MISMATIF |Mismatch Interrupt Flag + * | | |This flag shows the amounts of data are not the same in each pins with PDMA enabled. + * | | |If this situation happens, all slot controllers stop counting. + * | | |0 = Each pin with PDMA enabled receive or transfer data in the same rate. + * | | |1 = Each pin with PDMA enabled receive or transfer data in different rate. + * | | |Note1: This flag is only effective on the pin with PDMA enabled. + * | | |Note2: This bit can be cleared by writing 1. + * |[3] |TERRIF |Transfer Error Interrupt Status Flag + * | | |This field is used for transfer error interrupt status flag + * | | |The transfer error states is at PSIO_DATCTL register which includes receive buffer overflow error INOVER (PSIOn_DATCTL[14]), transmit buffer shortage error OUTUFER (PSIOn_DATCTL[6]) + * | | |0 = Transfer error interrupt did not occur. + * | | |1 = Transfer error interrupt occurred. + * | | |Note1: This field is the status flag of INOVER or OUTUFER. + * | | |Note2: This bit can only be cleared by writing 1 to coordinate transfer error. + * |[4] |SC0IF |Slot Controller 0 Done Interrupt Status Flag + * | | |This field is used for slot controller 0 finish interrupt status flag. + * | | |0 = Slot controller 0 done interrupt did not occur. + * | | |1 = Slot controller 0 done interrupt occurred. + * | | |Note: This bit can be cleared by writing 1. + * |[5] |SC1IF |Slot Controller 1 Done Interrupt Status Flag + * | | |This field is used for slot controller 1 finish interrupt status flag. + * | | |0 = Slot controller 1 done interrupt did not occur. + * | | |1 = Slot controller 1 done interrupt occurred. + * | | |Note: This bit can be cleared by writing 1. + * |[6] |SC2IF |Slot Controller 2 Done Interrupt Status Flag + * | | |This field is used for slot controller 2 finish interrupt status flag. + * | | |0 = Slot controller 2 done interrupt did not occur. + * | | |1 = Slot controller 2 done interrupt occurred. + * | | |Note: This bit can be cleared by writing 1. + * |[7] |SC3IF |Slot Controller 3 Done Interrupt Status Flag + * | | |This field is used for slot controller 3 finish interrupt status flag. + * | | |0 = Slot controller 3 done interrupt did not occur. + * | | |1 = Slot controller 3 done interrupt occurred. + * | | |Note: This bit can be cleared by writing 1. + * @var PSIO_T::TRANSTS + * Offset: 0x0C PSIO Transfer Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |INFULL0 |Input Data Full Flag0 (Read Only) + * | | |0 = The pin0 input data is empty. + * | | |1 = The pin0 input data is full. + * | | |Note: This bit will be cleared automatically when related slot controller start and pin enabled. + * |[1] |INOVER0 |Input Data Overflow Flag0 + * | | |0 = The pin0 input data does not occur overflow. + * | | |1 = The pin0 input data occurs overflow. + * | | |Note1: When input Overflow happened, it will keep the current data, and discard the upcoming data. + * | | |Note2: When overflow happens, related slot controller will be stopped. + * | | |Note3: This bit can be cleared by configure 1 to it. + * | | |Note4: This bit will be cleared automatically when related slot controller start and pin enabled. + * |[2] |OUTEPY0 |Output Data Empty Flag0 (Read Only) + * | | |0 = The pin0 output data is full. + * | | |1 = The pin0 output data is empty. + * |[3] |OUTUF0 |Output Data Underflow Flag0 + * | | |When PSIO is still output data but PSIOn_OUTDAT have not been ready. This flag will be set to 1. + * | | |0 = The pin0 output data is not underflow. + * | | |1 = The pin0 output data is underflow. + * | | |Note1: When output data shortage happened, it will output 0. + * | | |Note2: When underflow happens, related slot controller will be stopped. + * | | |Note3: This bit can be cleared by configure 1 to it. + * | | |Note4: This bit will be cleared automatically when related slot controller start and pin enabled. + * |[4] |INFULL1 |Input Data Full Flag1 (Read Only) + * | | |0 = The pin1 input data is empty. + * | | |1 = The pin1 input data is full. + * | | |Note: This bit will be cleared automatically when related slot controller start and pin enabled. + * |[5] |INOVER1 |Input Data Overflow Flag1 + * | | |0 = The pin1 input data does not occur overflow. + * | | |1 = The pin1 input data occurs overflow. + * | | |Note1: When input Overflow happened, it will keep the current data, and discard the upcoming data. + * | | |Note2: When overflow happens, related slot controller will be stopped. + * | | |Note3: This bit can be cleared by configure 1 to it. + * | | |Note4: This bit will be cleared automatically when related slot controller start and pin enabled. + * |[6] |OUTEPY1 |Output Data Empty Flag1 + * | | |0 = The pin1 output data is full. + * | | |1 = The pin1 output data is empty. + * |[7] |OUTUF1 |Output Data Underflow Flag1 + * | | |When PSIO is still output data but PSIOn_OUTDAT have not been ready. This flag will be set to 1. + * | | |0 = The pin1 output data is not underflow. + * | | |1 = The pin1 output data is underflow. + * | | |Note1: When output data shortage happened, it will output 0. + * | | |Note2: When underflow happens, related slot controller will be stopped. + * | | |Note3: This bit can be cleared by configure 1 to it. + * | | |Note4: This bit will be cleared automatically when related slot controller start and pin enabled. + * |[8] |INFULL2 |Input Data Full Flag2 (Read Only) + * | | |0 = The pin2 input data is empty. + * | | |1 = The pin2 input data is full. + * | | |Note: This bit will be cleared automatically when related slot controller start and pin is enabled. + * |[9] |INOVER2 |Input Data Overflow Flag2 + * | | |0 = The pin2 input data does not occur overflow. + * | | |1 = The pin2 input data occurs overflow. + * | | |Note1: When input Overflow happened, it will keep the current data, and discard the upcoming data. + * | | |Note2: When overflow happens, related slot controller will be stopped. + * | | |Note3: This bit can be cleared by configure 1 to it. + * | | |Note4: This bit will be cleared automatically when related slot controller start and pin enabled. + * |[10] |OUTEPY2 |Output Data Empty Flag2 (Read Only) + * | | |0 = The pin2 output data is full. + * | | |1 = The pin2 output data is empty. + * |[11] |OUTUF2 |Output Data Underflow Flag2 + * | | |When PSIO is still output data but PSIOn_OUTDAT have not been ready. This flag will be set to 1. + * | | |0 = The pin3 output data is not underflow. + * | | |1 = The pin3 output data is underflow. + * | | |Note1: When output data shortage happened, it will output 0. + * | | |Note2: When underflow happens, related slot controller will be stopped. + * | | |Note3: This bit can be cleared by configure 1 to it. + * | | |Note4: This bit will be cleared automatically when related slot controller start and pin enabled. + * |[12] |INFULL3 |Input Data Full Flag3 (Read Only) + * | | |0 = The pin3 input data is empty. + * | | |1 = The pin3 input data is full. + * | | |Note: This bit will be cleared automatically when related slot controller start and pin is enabled. + * |[13] |INOVER3 |Input Data Overflow Flag3 + * | | |0 = The pin3 input data does not occur overflow. + * | | |1 = The pin3 input data occurs overflow. + * | | |Note1: When input Overflow happened, it will keep the current data, and discard the upcoming data. + * | | |Note2: When overflow happens, related slot controller will be stopped. + * | | |Note3: This bit can be cleared by configure 1 to it. + * | | |Note4: This bit will be cleared automatically when related slot controller start and pin enabled. + * |[14] |OUTEPY3 |Output Data Empty Flag3 (Read Only) + * | | |0 = The pin3 output data is full. + * | | |1 = The pin3 output data is empty. + * |[15] |OUTUF3 |Output Data Underflow Flag3 + * | | |When PSIO is still output data but PSIOn_OUTDAT have not been ready. This flag will be set to 1. + * | | |0 = The pin3 output data is not underflow. + * | | |1 = The pin3 output data is underflow. + * | | |Note1: When output data shortage happened, it will output 0. + * | | |Note2: When underflow happens, related slot controller will be stopped. + * | | |Note3: This bit can be cleared by configure 1 to it. + * | | |Note4: This bit will be cleared automatically when related slot controller start and pin enabled. + * |[16] |INFULL4 |Input Data Full Flag4 (Read Only) + * | | |0 = The pin4 input data is empty. + * | | |1 = The pin4 input data is full. + * | | |Note: This bit will be cleared automatically when related slot controller start and pin is enabled. + * |[17] |INOVER4 |Input Data Overflow Flag4 + * | | |0 = The pin4 input data does not occur overflow. + * | | |1 = The pin4 input data occurs overflow. + * | | |Note1: When input Overflow happened, it will keep the current data, and discard the upcoming data. + * | | |Note2: When overflow happens, related slot controller will be stopped. + * | | |Note3: This bit can be cleared by configure 1 to it. + * | | |Note4: This bit will be cleared automatically when related slot controller start and pin enabled. + * |[18] |OUTEPY4 |Output Data Empty Flag4 (Read Only) + * | | |0 = The pin4 output data is full. + * | | |1 = The pin4 output data is empty. + * |[19] |OUTUF4 |Output Data Underflow Flag4 + * | | |When PSIO is still output data but PSIOn_OUTDAT have not been ready. This flag will be set to 1. + * | | |0 = The pin4 output data is not underflow. + * | | |1 = The pin4 output data is underflow. + * | | |Note1: When output data shortage happened, it will output 0. + * | | |Note2: When underflow happens, related slot controller will be stopped. + * | | |Note3: This bit can be cleared by configure 1 to it. + * | | |Note4: This bit will be cleared automatically when related slot controller start and pin enabled. + * |[20] |INFULL5 |Input Data Full Flag5 (Read Only) + * | | |0 = The pin5 input data is empty. + * | | |1 = The pin5 input data is full. + * | | |Note: This bit will be cleared automatically when related slot controller start and pin enabled. + * |[21] |INOVER5 |Input Data Overflow Flag5 + * | | |0 = The pin5 input data does not occur overflow. + * | | |1 = The pin5 input data occurs overflow. + * | | |Note1: When input Overflow happened, it will keep the current data, and discard the upcoming data. + * | | |Note2: When overflow happens, related slot controller will be stopped. + * | | |Note3: This bit can be cleared by configure 1 to it. + * | | |Note4: This bit will be cleared automatically when related slot controller start and pin enabled. + * |[22] |OUTEPY5 |Output Data Empty Flag5 (Read Only) + * | | |0 = The pin5 output data is full. + * | | |1 = The pin5 output data is empty. + * |[23] |OUTUF5 |Output Data Underflow Flag5 + * | | |When PSIO is still output data but PSIOn_OUTDAT have not been ready. This flag will be set to 1. + * | | |0 = The pin5 output data is not underflow. + * | | |1 = The pin5 output data is underflow. + * | | |Note1: When output data shortage happened, it will output 0. + * | | |Note2: When underflow happens, related slot controller will be stopped. + * | | |Note3: This bit can be cleared by configure 1 to it. + * | | |Note4: This bit will be cleared automatically when related slot controller start and pin is enabled. + * |[24] |INFULL6 |Input Data Full Flag6 (Read Only) + * | | |0 = The pin6 input data is empty. + * | | |1 = The pin6 input data is full. + * | | |Note: This bit will be cleared automatically when related slot controller start and pin enabled. + * |[25] |INOVER6 |Input Data Overflow Flag6 + * | | |0 = The pin6 input data does not occur overflow. + * | | |1 = The pin6 input data occurs overflow. + * | | |Note1: When input Overflow happened, it will keep the current data, and discard the upcoming data. + * | | |Note2: When overflow happens, related slot controller will be stopped. + * | | |Note3: This bit can be cleared by configure 1 to it. + * | | |Note4: This bit will be cleared automatically when related slot controller start and pin enabled. + * |[26] |OUTEPY6 |Output Data Empty Flag6 (Read Only) + * | | |0 = The pin6 output data is full. + * | | |1 = The pin6 output data is empty. + * |[27] |OUTUF6 |Output Data Underflow Flag6 + * | | |When PSIO is still output data but PSIOn_OUTDAT have not been ready. This flag will be set to 1. + * | | |0 = The pin6 output data is not underflow. + * | | |1 = The pin6 output data is underflow. + * | | |Note1: When output data shortage happened, it will output 0. + * | | |Note2: When underflow happens, related slot controller will be stopped. + * | | |Note3: This bit can be cleared by configure 1 to it. + * | | |Note4: This bit will be cleared automatically when related slot controller start and pin enabled. + * |[28] |INFULL7 |Input Data Full Flag7 (Read Only) + * | | |0 = The pin7 input data is empty. + * | | |1 = The pin7 input data is full. + * | | |Note: This bit will be cleared automatically when related slot controller start and pin enabled. + * |[29] |INOVER7 |Input Data Overflow Flag7 + * | | |0 = The pin7 input data does not occur overflow. + * | | |1 = The pin7 input data occurs overflow. + * | | |Note1: When input Overflow happened, it will keep the current data, and discard the upcoming data. + * | | |Note2: When overflow happens, related slot controller will be stopped. + * | | |Note3: This bit can be cleared by configure 1 to it. + * | | |Note4: This bit will be cleared automatically when related slot controller start and pin enabled. + * |[30] |OUTEPY7 |Output Data Empty Flag7 (Read Only) + * | | |0 = The pin7 output data is full. + * | | |1 = The pin7 output data is empty. + * |[31] |OUTUF7 |Output Data Underflow Flag7 + * | | |When PSIO is still output data but PSIOn_OUTDAT have not been ready. This flag will be set to 1. + * | | |0 = The pin7 output data is not underflow. + * | | |1 = The pin7 output data is underflow. + * | | |Note1: When output data shortage happened, it will output 0. + * | | |Note2: When underflow happens, related slot controller will be stopped. + * | | |Note3: This bit can be cleared by configure 1 to it. + * | | |Note4: This bit will be cleared automatically when related slot controller start and pin enabled. + * @var PSIO_T::ISSTS + * Offset: 0x10 PSIO Input Status State Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |VALID0 |Input Status Valid 0 + * | | |0 = The pin 0 input Status is not ready. + * | | |1 = The pin 0 input Status is ready. + * | | |Note: This valid bit will be cleared automatically if PSIOn_INSTS is read. + * |[1] |INSTSOV0 |Input Status Overflow 0 + * | | |0 = The pin 0 input Status does not overflow. + * | | |1 = The pin 0 input Status occur overflow. + * | | |Note: This overflow bit can be write 1 clear.. + * |[2] |VALID1 |Input Status Valid 1 + * | | |0 = The pin 1 input Status is not ready. + * | | |1 = The pin 1 input Status is ready. + * | | |Note: This valid bit will be cleared automatically if PSIOn_INSTS is read. + * |[3] |INSTSOV1 |Input Status Overflow 1 + * | | |0 = The pin 1 input Status does not overflow. + * | | |1 = The pin 1 input Status occur overflow. + * | | |Note: This overflow bit can be write 1 clear.. + * |[4] |VALID2 |Input Status Valid 2 + * | | |0 = The pin 2 input Status is not ready. + * | | |1 = The pin 2 input Status is ready. + * | | |Note: This valid bit will be cleared automatically if PSIOn_INSTS is read. + * |[5] |INSTSOV2 |Input Status Overflow 2 + * | | |0 = The pin 2 input Status does not overflow. + * | | |1 = The pin 2 input Status occur overflow. + * | | |Note: This overflow bit can be write 1 clear.. + * |[6] |VALID3 |Input Status Valid 3 + * | | |0 = The pin 3 input Status is not ready. + * | | |1 = The pin 3 input Status is ready. + * | | |Note: This valid bit will be cleared automatically if PSIOn_INSTS is read. + * |[7] |INSTSOV3 |Input Status Overflow 3 + * | | |0 = The pin 3 input Status does not overflow. + * | | |1 = The pin 3 input Status occur overflow. + * | | |Note: This overflow bit can be write 1 clear.. + * |[8] |VALID4 |Input Status Valid 4 + * | | |0 = The pin 4 input Status is not ready. + * | | |1 = The pin 4 input Status is ready. + * | | |Note: This valid bit will be cleared automatically if PSIOn_INSTS is read. + * |[9] |INSTSOV4 |Input Status Overflow 4 + * | | |0 = The pin 4 input Status does not overflow. + * | | |1 = The pin 4 input Status occur overflow. + * | | |Note: This overflow bit can be write 1 clear.. + * |[10] |VALID5 |Input Status Valid 5 + * | | |0 = The pin 5 input Status is not ready. + * | | |1 = The pin 5 input Status is ready. + * | | |Note: This valid bit will be cleared automatically if PSIOn_INSTS is read. + * |[11] |INSTSOV5 |Input Status Overflow 5 + * | | |0 = The pin 5 input Status does not overflow. + * | | |1 = The pin 5 input Status occur overflow. + * | | |Note: This overflow bit can be write 1 clear.. + * |[12] |VALID6 |Input Status Valid 6 + * | | |0 = The pin 6 input Status is not ready. + * | | |1 = The pin 6 input Status is ready. + * | | |Note: This valid bit will be cleared automatically if PSIOn_INSTS is read. + * |[13] |INSTSOV6 |Input Status Overflow 6 + * | | |0 = The pin 6 input Status does not overflow. + * | | |1 = The pin 6 input Status occur overflow. + * | | |Note: This overflow bit can be write 1 clear.. + * |[14] |VALID7 |Input Status Valid 7 + * | | |0 = The pin7 input Status is not ready. + * | | |1 = The pin7 input Status is ready. + * | | |Note: This valid bit will be cleared automatically if PSIOn_INSTS is read. + * |[15] |INSTSOV7 |Input Status Overflow 7 + * | | |0 = The pin7 input Status does not overflow. + * | | |1 = The pin7 input Status occur overflow. + * | | |Note: This overflow bit can be write 1 clear.. + * @var PSIO_T::PDMACTL + * Offset: 0x14 PSIO PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |OPIN0EN |Output PDMA Pin0 Enable Bit + * | | |0 = Pin0 output PDMA function Disabled. + * | | |1 = Pin0 output PDMA function Enabled. + * |[1] |OPIN1EN |Output PDMA Pin1 Enable Bit + * | | |0 = Pin1 output PDMA function Disabled. + * | | |1 = Pin1 output PDMA function Enabled. + * |[2] |OPIN2EN |Output PDMA Pin2 Enable Bit + * | | |0 = Pin2 output PDMA function Disabled. + * | | |1 = Pin2 output PDMA function Enabled. + * |[3] |OPIN3EN |Output PDMA Pin3 Enable Bit + * | | |0 = Pin3 output PDMA function Disabled. + * | | |1 = Pin3 output PDMA function Enabled. + * |[4] |OPIN4EN |Output PDMA Pin4 Enable Bit + * | | |0 = Pin4 output PDMA function Disabled. + * | | |1 = Pin4 output PDMA function Enabled. + * |[5] |OPIN5EN |Output PDMA Pin5 Enable Bit + * | | |0 = Pin5 output PDMA function Disabled. + * | | |1 = Pin5 output PDMA function Enabled. + * |[6] |OPIN6EN |Output PDMA Pin6 Enable Bit + * | | |0 = Pin6 output PDMA function Disabled. + * | | |1 = Pin6 output PDMA function Enabled. + * |[7] |OPIN7EN |Output PDMA Pin7 Enable Bit + * | | |0 = Pin7 output PDMA function Disabled. + * | | |1 = Pin7 output PDMA function Enabled. + * |[8] |IPIN0EN |Input PDMA Pin0 Enable Bit + * | | |0 = Pin0 input PDMA function Disabled. + * | | |1 = Pin0 input PDMA function Enabled. + * |[9] |IPIN1EN |Input PDMA Pin1 Enable Bit + * | | |0 = Pin1 input PDMA function Disabled. + * | | |1 = Pin1 input PDMA function Enabled. + * |[10] |IPIN2EN |Input PDMA Pin2 Enable Bit + * | | |0 = Pin2 input PDMA function Disabled. + * | | |1 = Pin2 input PDMA function Enabled. + * |[11] |IPIN3EN |Input PDMA Pin3 Enable Bit + * | | |0 = Pin3 input PDMA function Disabled. + * | | |1 = Pin3 input PDMA function Enabled. + * |[12] |IPIN4EN |Input PDMA Pin4 Enable Bit + * | | |0 = Pin4 input PDMA function Disabled. + * | | |1 = Pin4 input PDMA function Enabled. + * |[13] |IPIN5EN |Input PDMA Pin5 Enable Bit + * | | |0 = Pin5 input PDMA function Disabled. + * | | |1 = Pin5 input PDMA function Enabled. + * |[14] |IPIN6EN |Input PDMA Pin6 Enable Bit + * | | |0 = Pin6 input PDMA function Disabled. + * | | |1 = Pin6 input PDMA function Enabled. + * |[15] |IPIN7EN |Input PDMA Pin7 Enable Bit + * | | |0 = Pin7 input PDMA function Disabled. + * | | |1 = Pin7 input PDMA function Enabled. + * |[19:16] |OUTNUM |PDMA Output Current Number (Read Only) + * | | |0000 = PDMA IDLE. + * | | |0001 = pin 0. + * | | |0010 = pin 1. + * | | |0011 = pin 2. + * | | |0100 = pin 3. + * | | |0101 = pin 4. + * | | |0110 = pin 5. + * | | |0111 = pin 6. + * | | |1000 = pin 7. + * | | |1001 = PDMA WAIT. + * | | |Others = reserved. + * | | |This register shows the current pin number of output register write by PDMA. + * |[21:20] |OUTSCSEL |PDMA Output Data Slot Controller Selection + * | | |00: slot controller 0. + * | | |01: slot controller 1. + * | | |10: slot controller 2. + * | | |11: slot controller 3. + * |[27:24] |INNUM |PDMA Input Current Number (Read Only) + * | | |0000 = PDMA IDLE. + * | | |0001 = pin 0. + * | | |0010 = pin 1. + * | | |0011 = pin 2. + * | | |0100 = pin 3. + * | | |0101 = pin 4. + * | | |0110 = pin 5. + * | | |0111 = pin 6. + * | | |1000 = pin 7. + * | | |1001 = PDMA WAIT. + * | | |Others = reserved. + * | | |This register shows the current pin number of input register read by PDMA. + * |[29:28] |INSCSEL |PDMA Input Data Slot Controller Selection + * | | |00: slot controller 0. + * | | |01: slot controller 1. + * | | |10: slot controller 2. + * | | |11: slot controller 3. + * @var PSIO_T::PODAT + * Offset: 0x18 PSIO PDMA Output Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |PDMAOUT |PDMA Output Data + * | | |This register is used for PSIO with PDMA single mode, and set PDMA with fixed address. + * | | |When PSIO in PDMA mode, setting PDMA to write data to this register. + * | | |The data in this register will be placed to corresponding PSIOn_OUTDATA register in order, when Output Data Empty Flag is 1 and PDMA mode enabled. + * @var PSIO_T::PIDAT + * Offset: 0x1C PSIO PDMA Input Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |PDMAIN |PDMA Input Data + * | | |This register is used for PSIO with PDMA single mode, and set PDMA with fixed address. + * | | |When PSIO in PDMA mode, setting PDMA to read data from this register. + * | | |The data in this register will be updated from corresponding PSIOn_INDATA register in order, when Input Data Full Flag is 1 and PDMA mode enable. + */ + __IO uint32_t INTCTL; /*!< [0x0000] PSIO Interrupt Control Register */ + __IO uint32_t INTEN; /*!< [0x0004] PSIO Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x0008] PSIO Interrupt Status Register */ + __IO uint32_t TRANSTS; /*!< [0x000c] PSIO Transfer Status Register */ + __IO uint32_t ISSTS; /*!< [0x0010] PSIO Input Status State Register */ + __IO uint32_t PDMACTL; /*!< [0x0014] PSIO PDMA Control Register */ + __O uint32_t PODAT; /*!< [0x0018] PSIO PDMA Output Data Register */ + __IO uint32_t PIDAT; /*!< [0x001c] PSIO PDMA Input Data Register */ + SCCT_T SCCT[4]; /*!< [0x0020 ~ 0x0048] PSIO Slot Controller Registers */ + GNCT_T GNCT[8]; /*!< [0x0040 ~ 0x0138] PSIO Control Registers */ +} PSIO_T; + +/** + @addtogroup PSIO_CONST PSIO Bit Field Definition + Constant Definitions for PSIO Controller +@{ */ + +#define PSIO_INTCTL_CONI0SS_Pos (0) /*!< PSIO_T::INTCTL: INT0CSEL Position */ +#define PSIO_INTCTL_CONI0SS_Msk (0xful << PSIO_INTCTL_CONI0SS_Pos) /*!< PSIO_T::INTCTL: INT0CSEL Mask */ + +#define PSIO_INTCTL_CONI1SS_Pos (4) /*!< PSIO_T::INTCTL: INT1CSEL Position */ +#define PSIO_INTCTL_CONI1SS_Msk (0xful << PSIO_INTCTL_CONI1SS_Pos) /*!< PSIO_T::INTCTL: INT1CSEL Mask */ + +#define PSIO_INTCTL_CONI0SCS_Pos (8) /*!< PSIO_T::INTCTL: INT0SSEL Position */ +#define PSIO_INTCTL_CONI0SCS_Msk (0x3ul << PSIO_INTCTL_CONI0SCS_Pos) /*!< PSIO_T::INTCTL: INT0SSEL Mask */ + +#define PSIO_INTCTL_CONI1SCS_Pos (12) /*!< PSIO_T::INTCTL: INT1SSEL Position */ +#define PSIO_INTCTL_CONI1SCS_Msk (0x3ul << PSIO_INTCTL_CONI1SCS_Pos) /*!< PSIO_T::INTCTL: INT1SSEL Mask */ + +#define PSIO_INTCTL_LOOPBACK_Pos (31) /*!< PSIO_T::INTCTL: LOOPBACK Position */ +#define PSIO_INTCTL_LOOPBACK_Msk (0x1ul << PSIO_INTCTL_LOOPBACK_Pos) /*!< PSIO_T::INTCTL: LOOPBACK Mask */ + +#define PSIO_INTEN_CON0IE_Pos (0) /*!< PSIO_T::INTEN: INTEN0 Position */ +#define PSIO_INTEN_CON0IE_Msk (0x1ul << PSIO_INTEN_CON0IE_Pos) /*!< PSIO_T::INTEN: INTEN0 Mask */ + +#define PSIO_INTEN_CON1IE_Pos (1) /*!< PSIO_T::INTEN: INTEN1 Position */ +#define PSIO_INTEN_CON1IE_Msk (0x1ul << PSIO_INTEN_CON1IE_Pos) /*!< PSIO_T::INTEN: INTEN1 Mask */ + +#define PSIO_INTEN_MISMATIE_Pos (2) /*!< PSIO_T::INTEN: MISMATIE Position */ +#define PSIO_INTEN_MISMATIE_Msk (0x1ul << PSIO_INTEN_MISMATIE_Pos) /*!< PSIO_T::INTEN: MISMATIE Mask */ + +#define PSIO_INTEN_TERRIE_Pos (3) /*!< PSIO_T::INTEN: TERRIE Position */ +#define PSIO_INTEN_TERRIE_Msk (0x1ul << PSIO_INTEN_TERRIE_Pos) /*!< PSIO_T::INTEN: TERRIE Mask */ + +#define PSIO_INTEN_SC0IE_Pos (4) /*!< PSIO_T::INTEN: SC0IE Position */ +#define PSIO_INTEN_SC0IE_Msk (0x1ul << PSIO_INTEN_SC0IE_Pos) /*!< PSIO_T::INTEN: SC0IE Mask */ + +#define PSIO_INTEN_SC1IE_Pos (5) /*!< PSIO_T::INTEN: SC1IE Position */ +#define PSIO_INTEN_SC1IE_Msk (0x1ul << PSIO_INTEN_SC1IE_Pos) /*!< PSIO_T::INTEN: SC1IE Mask */ + +#define PSIO_INTEN_SC2IE_Pos (6) /*!< PSIO_T::INTEN: SC2IE Position */ +#define PSIO_INTEN_SC2IE_Msk (0x1ul << PSIO_INTEN_SC2IE_Pos) /*!< PSIO_T::INTEN: SC2IE Mask */ + +#define PSIO_INTEN_SC3IE_Pos (7) /*!< PSIO_T::INTEN: SC3IE Position */ +#define PSIO_INTEN_SC3IE_Msk (0x1ul << PSIO_INTEN_SC3IE_Pos) /*!< PSIO_T::INTEN: SC3IE Mask */ + +#define PSIO_INTSTS_CON0IF_Pos (0) /*!< PSIO_T::INTSTS: INTIF0 Position */ +#define PSIO_INTSTS_CON0IF_Msk (0x1ul << PSIO_INTSTS_CON0IF_Pos) /*!< PSIO_T::INTSTS: INTIF0 Mask */ + +#define PSIO_INTSTS_CON1IF_Pos (1) /*!< PSIO_T::INTSTS: INTIF1 Position */ +#define PSIO_INTSTS_CON1IF_Msk (0x1ul << PSIO_INTSTS_CON1IF_Pos) /*!< PSIO_T::INTSTS: INTIF1 Mask */ + +#define PSIO_INTSTS_MISMATIF_Pos (2) /*!< PSIO_T::INTSTS: MISMATIF Position */ +#define PSIO_INTSTS_MISMATIF_Msk (0x1ul << PSIO_INTSTS_MISMATIF_Pos) /*!< PSIO_T::INTSTS: MISMATIF Mask */ + +#define PSIO_INTSTS_TERRIF_Pos (3) /*!< PSIO_T::INTSTS: TERRIF Position */ +#define PSIO_INTSTS_TERRIF_Msk (0x1ul << PSIO_INTSTS_TERRIF_Pos) /*!< PSIO_T::INTSTS: TERRIF Mask */ + +#define PSIO_INTSTS_SC0IF_Pos (4) /*!< PSIO_T::INTSTS: SC0IF Position */ +#define PSIO_INTSTS_SC0IF_Msk (0x1ul << PSIO_INTSTS_SC0IF_Pos) /*!< PSIO_T::INTSTS: SC0IF Mask */ + +#define PSIO_INTSTS_SC1IF_Pos (5) /*!< PSIO_T::INTSTS: SC1IF Position */ +#define PSIO_INTSTS_SC1IF_Msk (0x1ul << PSIO_INTSTS_SC1IF_Pos) /*!< PSIO_T::INTSTS: SC1IF Mask */ + +#define PSIO_INTSTS_SC2IF_Pos (6) /*!< PSIO_T::INTSTS: SC2IF Position */ +#define PSIO_INTSTS_SC2IF_Msk (0x1ul << PSIO_INTSTS_SC2IF_Pos) /*!< PSIO_T::INTSTS: SC2IF Mask */ + +#define PSIO_INTSTS_SC3IF_Pos (7) /*!< PSIO_T::INTSTS: SC3IF Position */ +#define PSIO_INTSTS_SC3IF_Msk (0x1ul << PSIO_INTSTS_SC3IF_Pos) /*!< PSIO_T::INTSTS: SC3IF Mask */ + +#define PSIO_TRANSTS_INFULL0_Pos (0) /*!< PSIO_T::TRANSTS: INFULL0 Position */ +#define PSIO_TRANSTS_INFULL0_Msk (0x1ul << PSIO_TRANSTS_INFULL0_Pos) /*!< PSIO_T::TRANSTS: INFULL0 Mask */ + +#define PSIO_TRANSTS_INOVER0_Pos (1) /*!< PSIO_T::TRANSTS: INOVER0 Position */ +#define PSIO_TRANSTS_INOVER0_Msk (0x1ul << PSIO_TRANSTS_INOVER0_Pos) /*!< PSIO_T::TRANSTS: INOVER0 Mask */ + +#define PSIO_TRANSTS_OUTEPY0_Pos (2) /*!< PSIO_T::TRANSTS: OUTEPY0 Position */ +#define PSIO_TRANSTS_OUTEPY0_Msk (0x1ul << PSIO_TRANSTS_OUTEPY0_Pos) /*!< PSIO_T::TRANSTS: OUTEPY0 Mask */ + +#define PSIO_TRANSTS_OUTUF0_Pos (3) /*!< PSIO_T::TRANSTS: OUTUF0 Position */ +#define PSIO_TRANSTS_OUTUF0_Msk (0x1ul << PSIO_TRANSTS_OUTUF0_Pos) /*!< PSIO_T::TRANSTS: OUTUF0 Mask */ + +#define PSIO_TRANSTS_INFULL1_Pos (4) /*!< PSIO_T::TRANSTS: INFULL1 Position */ +#define PSIO_TRANSTS_INFULL1_Msk (0x1ul << PSIO_TRANSTS_INFULL1_Pos) /*!< PSIO_T::TRANSTS: INFULL1 Mask */ + +#define PSIO_TRANSTS_INOVER1_Pos (5) /*!< PSIO_T::TRANSTS: INOVER1 Position */ +#define PSIO_TRANSTS_INOVER1_Msk (0x1ul << PSIO_TRANSTS_INOVER1_Pos) /*!< PSIO_T::TRANSTS: INOVER1 Mask */ + +#define PSIO_TRANSTS_OUTEPY1_Pos (6) /*!< PSIO_T::TRANSTS: OUTEPY1 Position */ +#define PSIO_TRANSTS_OUTEPY1_Msk (0x1ul << PSIO_TRANSTS_OUTEPY1_Pos) /*!< PSIO_T::TRANSTS: OUTEPY1 Mask */ + +#define PSIO_TRANSTS_OUTUF1_Pos (7) /*!< PSIO_T::TRANSTS: OUTUF1 Position */ +#define PSIO_TRANSTS_OUTUF1_Msk (0x1ul << PSIO_TRANSTS_OUTUF1_Pos) /*!< PSIO_T::TRANSTS: OUTUF1 Mask */ + +#define PSIO_TRANSTS_INFULL2_Pos (8) /*!< PSIO_T::TRANSTS: INFULL2 Position */ +#define PSIO_TRANSTS_INFULL2_Msk (0x1ul << PSIO_TRANSTS_INFULL2_Pos) /*!< PSIO_T::TRANSTS: INFULL2 Mask */ + +#define PSIO_TRANSTS_INOVER2_Pos (9) /*!< PSIO_T::TRANSTS: INOVER2 Position */ +#define PSIO_TRANSTS_INOVER2_Msk (0x1ul << PSIO_TRANSTS_INOVER2_Pos) /*!< PSIO_T::TRANSTS: INOVER2 Mask */ + +#define PSIO_TRANSTS_OUTEPY2_Pos (10) /*!< PSIO_T::TRANSTS: OUTEPY2 Position */ +#define PSIO_TRANSTS_OUTEPY2_Msk (0x1ul << PSIO_TRANSTS_OUTEPY2_Pos) /*!< PSIO_T::TRANSTS: OUTEPY2 Mask */ + +#define PSIO_TRANSTS_OUTUF2_Pos (11) /*!< PSIO_T::TRANSTS: OUTUF2 Position */ +#define PSIO_TRANSTS_OUTUF2_Msk (0x1ul << PSIO_TRANSTS_OUTUF2_Pos) /*!< PSIO_T::TRANSTS: OUTUF2 Mask */ + +#define PSIO_TRANSTS_INFULL3_Pos (12) /*!< PSIO_T::TRANSTS: INFULL3 Position */ +#define PSIO_TRANSTS_INFULL3_Msk (0x1ul << PSIO_TRANSTS_INFULL3_Pos) /*!< PSIO_T::TRANSTS: INFULL3 Mask */ + +#define PSIO_TRANSTS_INOVER3_Pos (13) /*!< PSIO_T::TRANSTS: INOVER3 Position */ +#define PSIO_TRANSTS_INOVER3_Msk (0x1ul << PSIO_TRANSTS_INOVER3_Pos) /*!< PSIO_T::TRANSTS: INOVER3 Mask */ + +#define PSIO_TRANSTS_OUTEPY3_Pos (14) /*!< PSIO_T::TRANSTS: OUTEPY3 Position */ +#define PSIO_TRANSTS_OUTEPY3_Msk (0x1ul << PSIO_TRANSTS_OUTEPY3_Pos) /*!< PSIO_T::TRANSTS: OUTEPY3 Mask */ + +#define PSIO_TRANSTS_OUTUF3_Pos (15) /*!< PSIO_T::TRANSTS: OUTUF3 Position */ +#define PSIO_TRANSTS_OUTUF3_Msk (0x1ul << PSIO_TRANSTS_OUTUF3_Pos) /*!< PSIO_T::TRANSTS: OUTUF3 Mask */ + +#define PSIO_TRANSTS_INFULL4_Pos (16) /*!< PSIO_T::TRANSTS: INFULL4 Position */ +#define PSIO_TRANSTS_INFULL4_Msk (0x1ul << PSIO_TRANSTS_INFULL4_Pos) /*!< PSIO_T::TRANSTS: INFULL4 Mask */ + +#define PSIO_TRANSTS_INOVER4_Pos (17) /*!< PSIO_T::TRANSTS: INOVER4 Position */ +#define PSIO_TRANSTS_INOVER4_Msk (0x1ul << PSIO_TRANSTS_INOVER4_Pos) /*!< PSIO_T::TRANSTS: INOVER4 Mask */ + +#define PSIO_TRANSTS_OUTEPY4_Pos (18) /*!< PSIO_T::TRANSTS: OUTEPY4 Position */ +#define PSIO_TRANSTS_OUTEPY4_Msk (0x1ul << PSIO_TRANSTS_OUTEPY4_Pos) /*!< PSIO_T::TRANSTS: OUTEPY4 Mask */ + +#define PSIO_TRANSTS_OUTUF4_Pos (19) /*!< PSIO_T::TRANSTS: OUTUF4 Position */ +#define PSIO_TRANSTS_OUTUF4_Msk (0x1ul << PSIO_TRANSTS_OUTUF4_Pos) /*!< PSIO_T::TRANSTS: OUTUF4 Mask */ + +#define PSIO_TRANSTS_INFULL5_Pos (20) /*!< PSIO_T::TRANSTS: INFULL5 Position */ +#define PSIO_TRANSTS_INFULL5_Msk (0x1ul << PSIO_TRANSTS_INFULL5_Pos) /*!< PSIO_T::TRANSTS: INFULL5 Mask */ + +#define PSIO_TRANSTS_INOVER5_Pos (21) /*!< PSIO_T::TRANSTS: INOVER5 Position */ +#define PSIO_TRANSTS_INOVER5_Msk (0x1ul << PSIO_TRANSTS_INOVER5_Pos) /*!< PSIO_T::TRANSTS: INOVER5 Mask */ + +#define PSIO_TRANSTS_OUTEPY5_Pos (22) /*!< PSIO_T::TRANSTS: OUTEPY5 Position */ +#define PSIO_TRANSTS_OUTEPY5_Msk (0x1ul << PSIO_TRANSTS_OUTEPY5_Pos) /*!< PSIO_T::TRANSTS: OUTEPY5 Mask */ + +#define PSIO_TRANSTS_OUTUF5_Pos (23) /*!< PSIO_T::TRANSTS: OUTUF5 Position */ +#define PSIO_TRANSTS_OUTUF5_Msk (0x1ul << PSIO_TRANSTS_OUTUF5_Pos) /*!< PSIO_T::TRANSTS: OUTUF5 Mask */ + +#define PSIO_TRANSTS_INFULL6_Pos (24) /*!< PSIO_T::TRANSTS: INFULL6 Position */ +#define PSIO_TRANSTS_INFULL6_Msk (0x1ul << PSIO_TRANSTS_INFULL6_Pos) /*!< PSIO_T::TRANSTS: INFULL6 Mask */ + +#define PSIO_TRANSTS_INOVER6_Pos (25) /*!< PSIO_T::TRANSTS: INOVER6 Position */ +#define PSIO_TRANSTS_INOVER6_Msk (0x1ul << PSIO_TRANSTS_INOVER6_Pos) /*!< PSIO_T::TRANSTS: INOVER6 Mask */ + +#define PSIO_TRANSTS_OUTEPY6_Pos (26) /*!< PSIO_T::TRANSTS: OUTEPY6 Position */ +#define PSIO_TRANSTS_OUTEPY6_Msk (0x1ul << PSIO_TRANSTS_OUTEPY6_Pos) /*!< PSIO_T::TRANSTS: OUTEPY6 Mask */ + +#define PSIO_TRANSTS_OUTUF6_Pos (27) /*!< PSIO_T::TRANSTS: OUTUF6 Position */ +#define PSIO_TRANSTS_OUTUF6_Msk (0x1ul << PSIO_TRANSTS_OUTUF6_Pos) /*!< PSIO_T::TRANSTS: OUTUF6 Mask */ + +#define PSIO_TRANSTS_INFULL7_Pos (28) /*!< PSIO_T::TRANSTS: INFULL7 Position */ +#define PSIO_TRANSTS_INFULL7_Msk (0x1ul << PSIO_TRANSTS_INFULL7_Pos) /*!< PSIO_T::TRANSTS: INFULL7 Mask */ + +#define PSIO_TRANSTS_INOVER7_Pos (29) /*!< PSIO_T::TRANSTS: INOVER7 Position */ +#define PSIO_TRANSTS_INOVER7_Msk (0x1ul << PSIO_TRANSTS_INOVER7_Pos) /*!< PSIO_T::TRANSTS: INOVER7 Mask */ + +#define PSIO_TRANSTS_OUTEPY7_Pos (30) /*!< PSIO_T::TRANSTS: OUTEPY7 Position */ +#define PSIO_TRANSTS_OUTEPY7_Msk (0x1ul << PSIO_TRANSTS_OUTEPY7_Pos) /*!< PSIO_T::TRANSTS: OUTEPY7 Mask */ + +#define PSIO_TRANSTS_OUTUF7_Pos (31) /*!< PSIO_T::TRANSTS: OUTUF7 Position */ +#define PSIO_TRANSTS_OUTUF7_Msk (0x1ul << PSIO_TRANSTS_OUTUF7_Pos) /*!< PSIO_T::TRANSTS: OUTUF7 Mask */ + +#define PSIO_ISSTS_VALID0_Pos (0) /*!< PSIO_T::ISSTS: VALID0 Position */ +#define PSIO_ISSTS_VALID0_Msk (0x1ul << PSIO_ISSTS_VALID0_Pos) /*!< PSIO_T::ISSTS: VALID0 Mask */ + +#define PSIO_ISSTS_INSTSOV0_Pos (1) /*!< PSIO_T::ISSTS: INSTSOV0 Position */ +#define PSIO_ISSTS_INSTSOV0_Msk (0x1ul << PSIO_ISSTS_INSTSOV0_Pos) /*!< PSIO_T::ISSTS: INSTSOV0 Mask */ + +#define PSIO_ISSTS_VALID1_Pos (2) /*!< PSIO_T::ISSTS: VALID1 Position */ +#define PSIO_ISSTS_VALID1_Msk (0x1ul << PSIO_ISSTS_VALID1_Pos) /*!< PSIO_T::ISSTS: VALID1 Mask */ + +#define PSIO_ISSTS_INSTSOV1_Pos (3) /*!< PSIO_T::ISSTS: INSTSOV1 Position */ +#define PSIO_ISSTS_INSTSOV1_Msk (0x1ul << PSIO_ISSTS_INSTSOV1_Pos) /*!< PSIO_T::ISSTS: INSTSOV1 Mask */ + +#define PSIO_ISSTS_VALID2_Pos (4) /*!< PSIO_T::ISSTS: VALID2 Position */ +#define PSIO_ISSTS_VALID2_Msk (0x1ul << PSIO_ISSTS_VALID2_Pos) /*!< PSIO_T::ISSTS: VALID2 Mask */ + +#define PSIO_ISSTS_INSTSOV2_Pos (5) /*!< PSIO_T::ISSTS: INSTSOV2 Position */ +#define PSIO_ISSTS_INSTSOV2_Msk (0x1ul << PSIO_ISSTS_INSTSOV2_Pos) /*!< PSIO_T::ISSTS: INSTSOV2 Mask */ + +#define PSIO_ISSTS_VALID3_Pos (6) /*!< PSIO_T::ISSTS: VALID3 Position */ +#define PSIO_ISSTS_VALID3_Msk (0x1ul << PSIO_ISSTS_VALID3_Pos) /*!< PSIO_T::ISSTS: VALID3 Mask */ + +#define PSIO_ISSTS_INSTSOV3_Pos (7) /*!< PSIO_T::ISSTS: INSTSOV3 Position */ +#define PSIO_ISSTS_INSTSOV3_Msk (0x1ul << PSIO_ISSTS_INSTSOV3_Pos) /*!< PSIO_T::ISSTS: INSTSOV3 Mask */ + +#define PSIO_ISSTS_VALID4_Pos (8) /*!< PSIO_T::ISSTS: VALID4 Position */ +#define PSIO_ISSTS_VALID4_Msk (0x1ul << PSIO_ISSTS_VALID4_Pos) /*!< PSIO_T::ISSTS: VALID4 Mask */ + +#define PSIO_ISSTS_INSTSOV4_Pos (9) /*!< PSIO_T::ISSTS: INSTSOV4 Position */ +#define PSIO_ISSTS_INSTSOV4_Msk (0x1ul << PSIO_ISSTS_INSTSOV4_Pos) /*!< PSIO_T::ISSTS: INSTSOV4 Mask */ + +#define PSIO_ISSTS_VALID5_Pos (10) /*!< PSIO_T::ISSTS: VALID5 Position */ +#define PSIO_ISSTS_VALID5_Msk (0x1ul << PSIO_ISSTS_VALID5_Pos) /*!< PSIO_T::ISSTS: VALID5 Mask */ + +#define PSIO_ISSTS_INSTSOV5_Pos (11) /*!< PSIO_T::ISSTS: INSTSOV5 Position */ +#define PSIO_ISSTS_INSTSOV5_Msk (0x1ul << PSIO_ISSTS_INSTSOV5_Pos) /*!< PSIO_T::ISSTS: INSTSOV5 Mask */ + +#define PSIO_ISSTS_VALID6_Pos (12) /*!< PSIO_T::ISSTS: VALID6 Position */ +#define PSIO_ISSTS_VALID6_Msk (0x1ul << PSIO_ISSTS_VALID6_Pos) /*!< PSIO_T::ISSTS: VALID6 Mask */ + +#define PSIO_ISSTS_INSTSOV6_Pos (13) /*!< PSIO_T::ISSTS: INSTSOV6 Position */ +#define PSIO_ISSTS_INSTSOV6_Msk (0x1ul << PSIO_ISSTS_INSTSOV6_Pos) /*!< PSIO_T::ISSTS: INSTSOV6 Mask */ + +#define PSIO_ISSTS_VALID7_Pos (14) /*!< PSIO_T::ISSTS: VALID7 Position */ +#define PSIO_ISSTS_VALID7_Msk (0x1ul << PSIO_ISSTS_VALID7_Pos) /*!< PSIO_T::ISSTS: VALID7 Mask */ + +#define PSIO_ISSTS_INSTSOV7_Pos (15) /*!< PSIO_T::ISSTS: INSTSOV7 Position */ +#define PSIO_ISSTS_INSTSOV7_Msk (0x1ul << PSIO_ISSTS_INSTSOV7_Pos) /*!< PSIO_T::ISSTS: INSTSOV7 Mask */ + +#define PSIO_PDMACTL_OPIN0EN_Pos (0) /*!< PSIO_T::PDMACTL: OPIN0EN Position */ +#define PSIO_PDMACTL_OPIN0EN_Msk (0x1ul << PSIO_PDMACTL_OPIN0EN_Pos) /*!< PSIO_T::PDMACTL: OPIN0EN Mask */ + +#define PSIO_PDMACTL_OPIN1EN_Pos (1) /*!< PSIO_T::PDMACTL: OPIN1EN Position */ +#define PSIO_PDMACTL_OPIN1EN_Msk (0x1ul << PSIO_PDMACTL_OPIN1EN_Pos) /*!< PSIO_T::PDMACTL: OPIN1EN Mask */ + +#define PSIO_PDMACTL_OPIN2EN_Pos (2) /*!< PSIO_T::PDMACTL: OPIN2EN Position */ +#define PSIO_PDMACTL_OPIN2EN_Msk (0x1ul << PSIO_PDMACTL_OPIN2EN_Pos) /*!< PSIO_T::PDMACTL: OPIN2EN Mask */ + +#define PSIO_PDMACTL_OPIN3EN_Pos (3) /*!< PSIO_T::PDMACTL: OPIN3EN Position */ +#define PSIO_PDMACTL_OPIN3EN_Msk (0x1ul << PSIO_PDMACTL_OPIN3EN_Pos) /*!< PSIO_T::PDMACTL: OPIN3EN Mask */ + +#define PSIO_PDMACTL_OPIN4EN_Pos (4) /*!< PSIO_T::PDMACTL: OPIN4EN Position */ +#define PSIO_PDMACTL_OPIN4EN_Msk (0x1ul << PSIO_PDMACTL_OPIN4EN_Pos) /*!< PSIO_T::PDMACTL: OPIN4EN Mask */ + +#define PSIO_PDMACTL_OPIN5EN_Pos (5) /*!< PSIO_T::PDMACTL: OPIN5EN Position */ +#define PSIO_PDMACTL_OPIN5EN_Msk (0x1ul << PSIO_PDMACTL_OPIN5EN_Pos) /*!< PSIO_T::PDMACTL: OPIN5EN Mask */ + +#define PSIO_PDMACTL_OPIN6EN_Pos (6) /*!< PSIO_T::PDMACTL: OPIN6EN Position */ +#define PSIO_PDMACTL_OPIN6EN_Msk (0x1ul << PSIO_PDMACTL_OPIN6EN_Pos) /*!< PSIO_T::PDMACTL: OPIN6EN Mask */ + +#define PSIO_PDMACTL_OPIN7EN_Pos (7) /*!< PSIO_T::PDMACTL: OPIN7EN Position */ +#define PSIO_PDMACTL_OPIN7EN_Msk (0x1ul << PSIO_PDMACTL_OPIN7EN_Pos) /*!< PSIO_T::PDMACTL: OPIN7EN Mask */ + +#define PSIO_PDMACTL_IPIN0EN_Pos (8) /*!< PSIO_T::PDMACTL: IPIN0EN Position */ +#define PSIO_PDMACTL_IPIN0EN_Msk (0x1ul << PSIO_PDMACTL_IPIN0EN_Pos) /*!< PSIO_T::PDMACTL: IPIN0EN Mask */ + +#define PSIO_PDMACTL_IPIN1EN_Pos (9) /*!< PSIO_T::PDMACTL: IPIN1EN Position */ +#define PSIO_PDMACTL_IPIN1EN_Msk (0x1ul << PSIO_PDMACTL_IPIN1EN_Pos) /*!< PSIO_T::PDMACTL: IPIN1EN Mask */ + +#define PSIO_PDMACTL_IPIN2EN_Pos (10) /*!< PSIO_T::PDMACTL: IPIN2EN Position */ +#define PSIO_PDMACTL_IPIN2EN_Msk (0x1ul << PSIO_PDMACTL_IPIN2EN_Pos) /*!< PSIO_T::PDMACTL: IPIN2EN Mask */ + +#define PSIO_PDMACTL_IPIN3EN_Pos (11) /*!< PSIO_T::PDMACTL: IPIN3EN Position */ +#define PSIO_PDMACTL_IPIN3EN_Msk (0x1ul << PSIO_PDMACTL_IPIN3EN_Pos) /*!< PSIO_T::PDMACTL: IPIN3EN Mask */ + +#define PSIO_PDMACTL_IPIN4EN_Pos (12) /*!< PSIO_T::PDMACTL: IPIN4EN Position */ +#define PSIO_PDMACTL_IPIN4EN_Msk (0x1ul << PSIO_PDMACTL_IPIN4EN_Pos) /*!< PSIO_T::PDMACTL: IPIN4EN Mask */ + +#define PSIO_PDMACTL_IPIN5EN_Pos (13) /*!< PSIO_T::PDMACTL: IPIN5EN Position */ +#define PSIO_PDMACTL_IPIN5EN_Msk (0x1ul << PSIO_PDMACTL_IPIN5EN_Pos) /*!< PSIO_T::PDMACTL: IPIN5EN Mask */ + +#define PSIO_PDMACTL_IPIN6EN_Pos (14) /*!< PSIO_T::PDMACTL: IPIN6EN Position */ +#define PSIO_PDMACTL_IPIN6EN_Msk (0x1ul << PSIO_PDMACTL_IPIN6EN_Pos) /*!< PSIO_T::PDMACTL: IPIN6EN Mask */ + +#define PSIO_PDMACTL_IPIN7EN_Pos (15) /*!< PSIO_T::PDMACTL: IPIN7EN Position */ +#define PSIO_PDMACTL_IPIN7EN_Msk (0x1ul << PSIO_PDMACTL_IPIN7EN_Pos) /*!< PSIO_T::PDMACTL: IPIN7EN Mask */ + +#define PSIO_PDMACTL_OUTNUM_Pos (16) /*!< PSIO_T::PDMACTL: OUTNUM Position */ +#define PSIO_PDMACTL_OUTNUM_Msk (0x7ul << PSIO_PDMACTL_OUTNUM_Pos) /*!< PSIO_T::PDMACTL: OUTNUM Mask */ + +#define PSIO_PDMACTL_OUTSCSEL_Pos (20) /*!< PSIO_T::PDMACTL: OUTSCSEL Position */ +#define PSIO_PDMACTL_OUTSCSEL_Msk (0x3ul << PSIO_PDMACTL_OUTSCSEL_Pos) /*!< PSIO_T::PDMACTL: OUTSCSEL Mask */ + +#define PSIO_PDMACTL_INNUM_Pos (24) /*!< PSIO_T::PDMACTL: INNUM Position */ +#define PSIO_PDMACTL_INNUM_Msk (0x7ul << PSIO_PDMACTL_INNUM_Pos) /*!< PSIO_T::PDMACTL: INNUM Mask */ + +#define PSIO_PDMACTL_INSCSEL_Pos (28) /*!< PSIO_T::PDMACTL: INSCSEL Position */ +#define PSIO_PDMACTL_INSCSEL_Msk (0x3ul << PSIO_PDMACTL_INSCSEL_Pos) /*!< PSIO_T::PDMACTL: INSCSEL Mask */ + +#define PSIO_PODAT_PDMAOUT_Pos (0) /*!< PSIO_T::PODAT: PDMAOUT Position */ +#define PSIO_PODAT_PDMAOUT_Msk (0xfffffffful << PSIO_PODAT_PDMAOUT_Pos) /*!< PSIO_T::PODAT: PDMAOUT Mask */ + +#define PSIO_PIDAT_PDMA_IN_Pos (0) /*!< PSIO_T::PIDAT: PDMA_IN Position */ +#define PSIO_PIDAT_PDMA_IN_Msk (0xfffffffful << PSIO_PIDAT_PDMA_IN_Pos) /*!< PSIO_T::PIDAT: PDMA_IN Mask */ + +#define PSIO_SCCT_SCCTL_INISLOT_Pos (0) /*!< PSIO_T::SCCTL: INISLOT Position */ +#define PSIO_SCCT_SCCTL_INISLOT_Msk (0xful << PSIO_SCCT_SCCTL_INISLOT_Pos) /*!< PSIO_T::SCCTL: INISLOT Mask */ + +#define PSIO_SCCT_SCCTL_ENDSLOT_Pos (4) /*!< PSIO_T::SCCTL: ENDSLOT Position */ +#define PSIO_SCCT_SCCTL_ENDSLOT_Msk (0xful << PSIO_SCCT_SCCTL_ENDSLOT_Pos) /*!< PSIO_T::SCCTL: ENDSLOT Mask */ + +#define PSIO_SCCT_SCCTL_SPLCNT_Pos (8) /*!< PSIO_T::SCCTL: SPLCNT Position */ +#define PSIO_SCCT_SCCTL_SPLCNT_Msk (0x3ful << PSIO_SCCT_SCCTL_SPLCNT_Pos) /*!< PSIO_T::SCCTL: SPLCNT Mask */ + +#define PSIO_SCCT_SCCTL_TRIGSRC_Pos (14) /*!< PSIO_T::SCCTL: TRIGSRC Position */ +#define PSIO_SCCT_SCCTL_TRIGSRC_Msk (0x3ul << PSIO_SCCT_SCCTL_TRIGSRC_Pos) /*!< PSIO_T::SCCTL: TRIGSRC Mask */ + +#define PSIO_SCCT_SCCTL_START_Pos (16) /*!< PSIO_T::SCCTL: START Position */ +#define PSIO_SCCT_SCCTL_START_Msk (0x1ul << PSIO_SCCT_SCCTL_START_Pos) /*!< PSIO_T::SCCTL: START Mask */ + +#define PSIO_SCCT_SCCTL_REPEAT_Pos (17) /*!< PSIO_T::SCCTL: REPEAT Position */ +#define PSIO_SCCT_SCCTL_REPEAT_Msk (0x1ul << PSIO_SCCT_SCCTL_REPEAT_Pos) /*!< PSIO_T::SCCTL: REPEAT Mask */ + +#define PSIO_SCCT_SCCTL_STOP_Pos (18) /*!< PSIO_T::SCCTL: STOP Position */ +#define PSIO_SCCT_SCCTL_STOP_Msk (0x1ul << PSIO_SCCT_SCCTL_STOP_Pos) /*!< PSIO_T::SCCTL: STOP Mask */ + +#define PSIO_SCCT_SCCTL_BUSY_Pos (24) /*!< PSIO_T::SCCTL: BUSY Position */ +#define PSIO_SCCT_SCCTL_BUSY_Msk (0x1ul << PSIO_SCCT_SCCTL_BUSY_Pos) /*!< PSIO_T::SCCTL: BUSY Mask */ + +#define PSIO_SCCT_SCCTL_IDLE_Pos (25) /*!< PSIO_T::SCCTL: IDLE Position */ +#define PSIO_SCCT_SCCTL_IDLE_Msk (0x1ul << PSIO_SCCT_SCCTL_IDLE_Pos) /*!< PSIO_T::SCCTL: IDLE Mask */ + +#define PSIO_SCCT_SCSLOT_SLOT0CNT_Pos (0) /*!< PSIO_T::SCSLOT: SLOT0CNT Position */ +#define PSIO_SCCT_SCSLOT_SLOT0CNT_Msk (0xful << PSIO_SCCT_SCSLOT_SLOT0CNT_Pos) /*!< PSIO_T::SCSLOT: SLOT0CNT Mask */ + +#define PSIO_SCCT_SCSLOT_SLOT1CNT_Pos (4) /*!< PSIO_T::SCSLOT: SLOT1CNT Position */ +#define PSIO_SCCT_SCSLOT_SLOT1CNT_Msk (0xful << PSIO_SCCT_SCSLOT_SLOT1CNT_Pos) /*!< PSIO_T::SCSLOT: SLOT1CNT Mask */ + +#define PSIO_SCCT_SCSLOT_SLOT2CNT_Pos (8) /*!< PSIO_T::SCSLOT: SLOT2CNT Position */ +#define PSIO_SCCT_SCSLOT_SLOT2CNT_Msk (0xful << PSIO_SCCT_SCSLOT_SLOT2CNT_Pos) /*!< PSIO_T::SCSLOT: SLOT2CNT Mask */ + +#define PSIO_SCCT_SCSLOT_SLOT3CNT_Pos (12) /*!< PSIO_T::SCSLOT: SLOT3CNT Position */ +#define PSIO_SCCT_SCSLOT_SLOT3CNT_Msk (0xful << PSIO_SCCT_SCSLOT_SLOT3CNT_Pos) /*!< PSIO_T::SCSLOT: SLOT3CNT Mask */ + +#define PSIO_SCCT_SCSLOT_SLOT4CNT_Pos (16) /*!< PSIO_T::SCSLOT: SLOT4CNT Position */ +#define PSIO_SCCT_SCSLOT_SLOT4CNT_Msk (0xful << PSIO_SCCT_SCSLOT_SLOT4CNT_Pos) /*!< PSIO_T::SCSLOT: SLOT4CNT Mask */ + +#define PSIO_SCCT_SCSLOT_SLOT5CNT_Pos (20) /*!< PSIO_T::SCSLOT: SLOT5CNT Position */ +#define PSIO_SCCT_SCSLOT_SLOT5CNT_Msk (0xful << PSIO_SCCT_SCSLOT_SLOT5CNT_Pos) /*!< PSIO_T::SCSLOT: SLOT5CNT Mask */ + +#define PSIO_SCCT_SCSLOT_SLOT6CNT_Pos (24) /*!< PSIO_T::SCSLOT: SLOT6CNT Position */ +#define PSIO_SCCT_SCSLOT_SLOT6CNT_Msk (0xful << PSIO_SCCT_SCSLOT_SLOT6CNT_Pos) /*!< PSIO_T::SCSLOT: SLOT6CNT Mask */ + +#define PSIO_SCCT_SCSLOT_SLOT7CNT_Pos (28) /*!< PSIO_T::SCSLOT: SLOT7CNT Position */ +#define PSIO_SCCT_SCSLOT_SLOT7CNT_Msk (0xful << PSIO_SCCT_SCSLOT_SLOT7CNT_Pos) /*!< PSIO_T::SCSLOT: SLOT7CNT Mask */ + +#define PSIO_GNCT_GENCTL_IOMODE_Pos (0) /*!< PSIO_T::GENCTL: IOMODE Position */ +#define PSIO_GNCT_GENCTL_IOMODE_Msk (0x3ul << PSIO_GNCT_GENCTL_IOMODE_Pos) /*!< PSIO_T::GENCTL: IOMODE Mask */ + +#define PSIO_GNCT_GENCTL_INITIAL_Pos (2) /*!< PSIO_T::GENCTL: INITIAL Position */ +#define PSIO_GNCT_GENCTL_INITIAL_Msk (0x3ul << PSIO_GNCT_GENCTL_INITIAL_Pos) /*!< PSIO_T::GENCTL: INITIAL Mask */ + +#define PSIO_GNCT_GENCTL_INTERVAL_Pos (4) /*!< PSIO_T::GENCTL: INTERVAL Position */ +#define PSIO_GNCT_GENCTL_INTERVAL_Msk (0x3ul << PSIO_GNCT_GENCTL_INTERVAL_Pos) /*!< PSIO_T::GENCTL: INTERVAL Mask */ + +#define PSIO_GNCT_GENCTL_SW0CP_Pos (8) /*!< PSIO_T::GENCTL: SW0CP Position */ +#define PSIO_GNCT_GENCTL_SW0CP_Msk (0xful << PSIO_GNCT_GENCTL_SW0CP_Pos) /*!< PSIO_T::GENCTL: SW0CP Mask */ + +#define PSIO_GNCT_GENCTL_SW1CP_Pos (12) /*!< PSIO_T::GENCTL: SW1CP Position */ +#define PSIO_GNCT_GENCTL_SW1CP_Msk (0xful << PSIO_GNCT_GENCTL_SW1CP_Pos) /*!< PSIO_T::GENCTL: SW1CP Mask */ + +#define PSIO_GNCT_GENCTL_MODESW0_Pos (16) /*!< PSIO_T::GENCTL: MODESW0 Position */ +#define PSIO_GNCT_GENCTL_MODESW0_Msk (0x3ul << PSIO_GNCT_GENCTL_MODESW0_Pos) /*!< PSIO_T::GENCTL: MODESW0 Mask */ + +#define PSIO_GNCT_GENCTL_MODESW1_Pos (18) /*!< PSIO_T::GENCTL: MODESW1 Position */ +#define PSIO_GNCT_GENCTL_MODESW1_Msk (0x3ul << PSIO_GNCT_GENCTL_MODESW1_Pos) /*!< PSIO_T::GENCTL: MODESW1 Mask */ + +#define PSIO_GNCT_GENCTL_SCSEL_Pos (24) /*!< PSIO_T::GENCTL: SCSEL Position */ +#define PSIO_GNCT_GENCTL_SCSEL_Msk (0x3ul << PSIO_GNCT_GENCTL_SCSEL_Pos) /*!< PSIO_T::GENCTL: SCSEL Mask */ + +#define PSIO_GNCT_GENCTL_PINEN_Pos (26) /*!< PSIO_T::GENCTL: PINEN Position */ +#define PSIO_GNCT_GENCTL_PINEN_Msk (0x1ul << PSIO_GNCT_GENCTL_PINEN_Pos) /*!< PSIO_T::GENCTL: PINEN Mask */ + +#define PSIO_GNCT_DATCTL_OUTDATWD_Pos (0) /*!< PSIO_T::DATCTL: OUTDATWD Position */ +#define PSIO_GNCT_DATCTL_OUTDATWD_Msk (0x1ful << PSIO_GNCT_DATCTL_OUTDATWD_Pos) /*!< PSIO_T::DATCTL: OUTDATWD Mask */ + +#define PSIO_GNCT_DATCTL_INDATWD_Pos (8) /*!< PSIO_T::DATCTL: INDATWD Position */ +#define PSIO_GNCT_DATCTL_INDATWD_Msk (0x1ful << PSIO_GNCT_DATCTL_INDATWD_Pos) /*!< PSIO_T::DATCTL: INDATWD Mask */ + +#define PSIO_GNCT_DATCTL_ORDER_Pos (16) /*!< PSIO_T::DATCTL: ORDER Position */ +#define PSIO_GNCT_DATCTL_ORDER_Msk (0x1ul << PSIO_GNCT_DATCTL_ORDER_Pos) /*!< PSIO_T::DATCTL: ORDER Mask */ + +#define PSIO_GNCT_DATCTL_OUTDEPTH_Pos (24) /*!< PSIO_T::DATCTL: OUTDEPTH Position */ +#define PSIO_GNCT_DATCTL_OUTDEPTH_Msk (0x3ul << PSIO_GNCT_DATCTL_OUTDEPTH_Pos) /*!< PSIO_T::DATCTL: OUTDEPTH Mask */ + +#define PSIO_GNCT_DATCTL_INDEPTH_Pos (28) /*!< PSIO_T::DATCTL: INDEPTH Position */ +#define PSIO_GNCT_DATCTL_INDEPTH_Msk (0x3ul << PSIO_GNCT_DATCTL_INDEPTH_Pos) /*!< PSIO_T::DATCTL: INDEPTH Mask */ + +#define PSIO_GNCT_INSTS_INSTS_Pos (0) /*!< PSIO_T::INSTS: INSTS Position */ +#define PSIO_GNCT_INSTS_INSTS_Msk (0x3ffffffful << PSIO_GNCT_INSTS_INSTS_Pos) /*!< PSIO_T::INSTS: INSTS Mask */ + +#define PSIO_GNCT_INSTS_INSTSOV_Pos (30) /*!< PSIO_T::INSTS: INSTSOV Position */ +#define PSIO_GNCT_INSTS_INSTSOV_Msk (0x1ul << PSIO_GNCT_INSTS_INSTSOV_Pos) /*!< PSIO_T::INSTS: INSTSOV Mask */ + +#define PSIO_GNCT_INSTS_VALID_Pos (31) /*!< PSIO_T::INSTS: VALID Position */ +#define PSIO_GNCT_INSTS_VALID_Msk (0x1ul << PSIO_GNCT_INSTS_VALID_Pos) /*!< PSIO_T::INSTS: VALID Mask */ + +#define PSIO_GNCT_INDAT_INDAT_Pos (0) /*!< PSIO_T::INDAT: INDAT Position */ +#define PSIO_GNCT_INDAT_INDAT_Msk (0xfffffffful << PSIO_GNCT_INDAT_INDAT_Pos) /*!< PSIO_T::INDAT: INDAT Mask */ + +#define PSIO_GNCT_OUTDAT_OUTDAT_Pos (0) /*!< PSIO_T::OUTDAT: OUTDAT Position */ +#define PSIO_GNCT_OUTDAT_OUTDAT_Msk (0xfffffffful << PSIO_GNCT_OUTDAT_OUTDAT_Pos) /*!< PSIO_T::OUTDAT: OUTDAT Mask */ + +#define PSIO_GNCT_CPCTL0_CKPT0_Pos (0) /*!< PSIO_T::CPCTL0: CKPT0 Position */ +#define PSIO_GNCT_CPCTL0_CKPT0_Msk (0xFul << PSIO_GNCT_CPCTL0_CKPT0_Pos) /*!< PSIO_T::CPCTL0: CKPT0 Mask */ + +#define PSIO_GNCT_CPCTL0_CKPT1_Pos (4) /*!< PSIO_T::CPCTL0: CKPT1 Position */ +#define PSIO_GNCT_CPCTL0_CKPT1_Msk (0xFul << PSIO_GNCT_CPCTL0_CKPT1_Pos) /*!< PSIO_T::CPCTL0: CKPT1 Mask */ + +#define PSIO_GNCT_CPCTL0_CKPT2_Pos (8) /*!< PSIO_T::CPCTL0: CKPT2 Position */ +#define PSIO_GNCT_CPCTL0_CKPT2_Msk (0xFul << PSIO_GNCT_CPCTL0_CKPT2_Pos) /*!< PSIO_T::CPCTL0: CKPT2 Mask */ + +#define PSIO_GNCT_CPCTL0_CKPT3_Pos (12) /*!< PSIO_T::CPCTL0: CKPT3 Position */ +#define PSIO_GNCT_CPCTL0_CKPT3_Msk (0xFul << PSIO_GNCT_CPCTL0_CKPT3_Pos) /*!< PSIO_T::CPCTL0: CKPT3 Mask */ + +#define PSIO_GNCT_CPCTL0_CKPT4_Pos (16) /*!< PSIO_T::CPCTL0: CKPT4 Position */ +#define PSIO_GNCT_CPCTL0_CKPT4_Msk (0xFul << PSIO_GNCT_CPCTL0_CKPT4_Pos) /*!< PSIO_T::CPCTL0: CKPT4 Mask */ + +#define PSIO_GNCT_CPCTL0_CKPT5_Pos (20) /*!< PSIO_T::CPCTL0: CKPT5 Position */ +#define PSIO_GNCT_CPCTL0_CKPT5_Msk (0xFul << PSIO_GNCT_CPCTL0_CKPT5_Pos) /*!< PSIO_T::CPCTL0: CKPT5 Mask */ + +#define PSIO_GNCT_CPCTL0_CKPT6_Pos (24) /*!< PSIO_T::CPCTL0: CKPT6 Position */ +#define PSIO_GNCT_CPCTL0_CKPT6_Msk (0xFul << PSIO_GNCT_CPCTL0_CKPT6_Pos) /*!< PSIO_T::CPCTL0: CKPT6 Mask */ + +#define PSIO_GNCT_CPCTL0_CKPT7_Pos (28) /*!< PSIO_T::CPCTL0: CKPT7 Position */ +#define PSIO_GNCT_CPCTL0_CKPT7_Msk (0xFul << PSIO_GNCT_CPCTL0_CKPT7_Pos) /*!< PSIO_T::CPCTL0: CKPT7 Mask */ + +#define PSIO_GNCT_CPCTL1_CKPT0ACT_Pos (0) /*!< PSIO_T::CPCTL1: CKPT0ACT Position */ +#define PSIO_GNCT_CPCTL1_CKPT0ACT_Msk (0x7ul << PSIO_GNCT_CPCTL1_CKPT0ACT_Pos) /*!< PSIO_T::CPCTL1: CKPT0ACT Mask */ + +#define PSIO_GNCT_CPCTL1_CKPT1ACT_Pos (4) /*!< PSIO_T::CPCTL1: CKPT1ACT Position */ +#define PSIO_GNCT_CPCTL1_CKPT1ACT_Msk (0x7ul << PSIO_GNCT_CPCTL1_CKPT1ACT_Pos) /*!< PSIO_T::CPCTL1: CKPT1ACT Mask */ + +#define PSIO_GNCT_CPCTL1_CKPT2ACT_Pos (8) /*!< PSIO_T::CPCTL1: CKPT2ACT Position */ +#define PSIO_GNCT_CPCTL1_CKPT2ACT_Msk (0x7ul << PSIO_GNCT_CPCTL1_CKPT2ACT_Pos) /*!< PSIO_T::CPCTL1: CKPT2ACT Mask */ + +#define PSIO_GNCT_CPCTL1_CKPT3ACT_Pos (12) /*!< PSIO_T::CPCTL1: CKPT3ACT Position */ +#define PSIO_GNCT_CPCTL1_CKPT3ACT_Msk (0x7ul << PSIO_GNCT_CPCTL1_CKPT3ACT_Pos) /*!< PSIO_T::CPCTL1: CKPT3ACT Mask */ + +#define PSIO_GNCT_CPCTL1_CKPT4ACT_Pos (16) /*!< PSIO_T::CPCTL1: CKPT4ACT Position */ +#define PSIO_GNCT_CPCTL1_CKPT4ACT_Msk (0x7ul << PSIO_GNCT_CPCTL1_CKPT4ACT_Pos) /*!< PSIO_T::CPCTL1: CKPT4ACT Mask */ + +#define PSIO_GNCT_CPCTL1_CKPT5ACT_Pos (20) /*!< PSIO_T::CPCTL1: CKPT5ACT Position */ +#define PSIO_GNCT_CPCTL1_CKPT5ACT_Msk (0x7ul << PSIO_GNCT_CPCTL1_CKPT5ACT_Pos) /*!< PSIO_T::CPCTL1: CKPT5ACT Mask */ + +#define PSIO_GNCT_CPCTL1_CKPT6ACT_Pos (24) /*!< PSIO_T::CPCTL1: CKPT6ACT Position */ +#define PSIO_GNCT_CPCTL1_CKPT6ACT_Msk (0x7ul << PSIO_GNCT_CPCTL1_CKPT6ACT_Pos) /*!< PSIO_T::CPCTL1: CKPT6ACT Mask */ + +#define PSIO_GNCT_CPCTL1_CKPT7ACT_Pos (28) /*!< PSIO_T::CPCTL1: CKPT7ACT Position */ +#define PSIO_GNCT_CPCTL1_CKPT7ACT_Msk (0x7ul << PSIO_GNCT_CPCTL1_CKPT7ACT_Pos) /*!< PSIO_T::CPCTL1: CKPT7ACT Mask */ + +/**@}*/ /* PSIO_CONST */ +/**@}*/ /* end of PSIO register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __PSIO_REG_H__ */ \ No newline at end of file diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/pwm_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/pwm_reg.h new file mode 100644 index 00000000000..99a266e4301 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/pwm_reg.h @@ -0,0 +1,2657 @@ +/**************************************************************************//** + * @file pwm_reg.h + * @version V1.00 + * @brief PWM register definition header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __PWM_REG_H__ +#define __PWM_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup PWM Pulse Width Modulation Controller (PWM) + Memory Mapped Structure for PWM Controller +@{ */ + +typedef struct +{ + /** + * @var CAPDAT_T::RCAPDAT + * Offset: 0x20C~0x238 PWM Rising Capture Data Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RCAPDAT |PWM Rising Capture Data (Read Only) + * | | |When rising capture condition happened, the PWM counter value will be saved in this register. + * @var CAPDAT_T::FCAPDAT + * Offset: 0x210 PWM Falling Capture Data Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FCAPDAT |PWWM Falling Capture Data (Read Only) + * | | |When falling capture condition happened, the PWWM counter value will be saved in this register. + */ + __IO uint32_t RCAPDAT; /*!< [0x20C/0x214/0x21C/0x224/0x22C/0x234] PWM Rising Capture Data Register 0~5 */ + __IO uint32_t FCAPDAT; /*!< [0x210/0x218/0x220/0x228/0x230/0x238] PWM Falling Capture Data Register 0~5 */ +} CAPDAT_T; + +typedef struct +{ + + + /** + * @var PWM_T::CTL0 + * Offset: 0x00 PWM Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CTRLDn |Center Load Enable Bits + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[16] |IMMLDENn |Immediately Load Enable Bits + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid. + * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect) + * | | |If counter halt is enabled, PWM all counters will keep current value until exit ICE debug mode. + * | | |0 = ICE debug mode counter halt Disable. + * | | |1 = ICE debug mode counter halt Enable. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable Bit (Write Protect) + * | | |0 = ICE debug mode acknowledgement effects PWM output. + * | | |PWM pin will be forced as tri-state while ICE debug mode acknowledged. + * | | |1 = ICE debug mode acknowledgement disabled. + * | | |PWM pin will keep output no matter ICE debug mode acknowledged or not. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * @var PWM_T::CTL1 + * Offset: 0x04 PWM Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CNTTYPE0 |PWM Counter Behavior Type 0 + * | | |The two bits control channel1 and channel0 + * | | |00 = Up counter type (supported in capture mode). + * | | |01 = Down count type (supported in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[5:4] |CNTTYPE2 |PWM Counter Behavior Type 2 + * | | |The two bits control channel3 and channel2 + * | | |00 = Up counter type (supported in capture mode). + * | | |01 = Down count type (supported in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[9:8] |CNTTYPE4 |PWM Counter Behavior Type 4 + * | | |The two bits control channel5 and channel4 + * | | |00 = Up counter type (supported in capture mode). + * | | |01 = Down count type (supported in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[26:24] |OUTMODEn |PWM Output Mode + * | | |Each bit n controls the output mode of corresponding PWM channel n. + * | | |0 = PWM independent mode. + * | | |1 = PWM complementary mode. + * | | |Note: When operating in group function, these bits must all set to the same mode. + * @var PWM_T::CLKSRC + * Offset: 0x10 PWM Clock Source Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |ECLKSRC0 |PWM_CH01 External Clock Source Select + * | | |000 = PWMx_CLK, x denotes 0 or 1. + * | | |001 = TIMER0 overflow. + * | | |010 = TIMER1 overflow. + * | | |011 = TIMER2 overflow. + * | | |100 = TIMER3 overflow. + * | | |Others = Reserved. + * |[10:8] |ECLKSRC2 |PWM_CH23 External Clock Source Select + * | | |000 = PWMx_CLK, x denotes 0 or 1. + * | | |001 = TIMER0 overflow. + * | | |010 = TIMER1 overflow. + * | | |011 = TIMER2 overflow. + * | | |100 = TIMER3 overflow. + * | | |Others = Reserved. + * |[18:16] |ECLKSRC4 |PWM_CH45 External Clock Source Select + * | | |000 = PWMx_CLK, x denotes 0 or 1. + * | | |001 = TIMER0 overflow. + * | | |010 = TIMER1 overflow. + * | | |011 = TIMER2 overflow. + * | | |100 = TIMER3 overflow. + * | | |Others = Reserved. + * @var PWM_T::CLKPSC[3] + * Offset: 0x14~0x1C PWM Clock Prescale Register 0/1, 2/3, 4/5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CLKPSC |PWM Counter Clock Prescale + * | | |The clock of PWM counter is decided by clock prescaler + * | | |Each PWM pair share one PWM counter clock prescaler + * | | |The clock of PWM counter is divided by (CLKPSC+ 1) + * @var PWM_T::CNTEN + * Offset: 0x20 PWM Counter Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTEN0 |PWM Counter Enable Bit 0 + * | | |0 = PWM Counter and clock prescaler Stop Running. + * | | |1 = PWM Counter and clock prescaler Start Running. + * |[2] |CNTEN2 |PWM Counter Enable Bit 2 + * | | |0 = PWM Counter and clock prescaler Stop Running. + * | | |1 = PWM Counter and clock prescaler Start Running. + * |[4] |CNTEN4 |PWM Counter Enable Bit 4 + * | | |0 = PWM Counter and clock prescaler Stop Running. + * | | |1 = PWM Counter and clock prescaler Start Running. + * @var PWM_T::CNTCLR + * Offset: 0x24 PWM Clear Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTCLR0 |Clear PWM Counter Control Bit 0 + * | | |It is automatically cleared by hardware. + * | | |0 = No effect. + * | | |1 = Clear 16-bit PWM counter to 0000H. + * |[2] |CNTCLR2 |Clear PWM Counter Control Bit 2 + * | | |It is automatically cleared by hardware. + * | | |0 = No effect. + * | | |1 = Clear 16-bit PWM counter to 0000H. + * |[4] |CNTCLR4 |Clear PWM Counter Control Bit 4 + * | | |It is automatically cleared by hardware. + * | | |0 = No effect. + * | | |1 = Clear 16-bit PWM counter to 0000H. + * @var PWM_T::PERIOD[6] + * Offset: 0x30~0x44 PWM Period Register 0, 2, 4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PERIOD |PWM Period Register + * | | |Up-Count mode: In this mode, PWM counter counts from 0 to PERIOD, and restarts from 0. + * | | |Down-Count mode: In this mode, PWM counter counts from PERIOD to 0, and restarts from PERIOD. + * | | |PWM period time = (PERIOD+1) * PWM_CLK period. + * | | |Up-Down-Count mode: In this mode, PWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again. + * | | |PWM period time = 2 * PERIOD * PWM_CLK period. + * @var PWM_T::CMPDAT[6] + * Offset: 0x50~0x64 PWM Comparator Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMP |PWM Comparator Register + * | | |CMP is used to compare with CNTR to generate PWM waveform, interrupt and trigger EADC. + * | | |In independent mode, PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point. + * | | |In complementary mode, PWM_CMPDAT0, 2, 4 denote as first compared point, and PWM_CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs PWM_CH0 and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5. + * @var PWM_T::DTCTL[3] + * Offset: 0x70~0x78 PWM Dead-time Control Register 0/1, 2/3, 4/5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |DTCNT |Dead-time Counter (Write Protect) + * | | |The dead-time can be calculated from the following formula: + * | | |DTCKSEL=0: Dead-time = (DTCNT[11:0]+1) * PWM_CLK period. + * | | |DTCKSEL=1: Dead-time = (DTCNT[11:0]+1) * PWM_CLK period * (CLKPSC+1). + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[16] |DTEN |Enable Dead-time Insertion for PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect) + * | | |Dead-time insertion is only active when this pair of complementary PWM is enabled + * | | |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. + * | | |0 = Dead-time insertion Disabled on the pin pair. + * | | |1 = Dead-time insertion Enabled on the pin pair. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[24] |DTCKSEL |Dead-time Clock Select (Write Protect) + * | | |0 = Dead-time clock source from PWM_CLK. + * | | |1 = Dead-time clock source from prescaler output. + * | | |Note: This bit is write protected. Refer to REGWRPROT register. + * @var PWM_T::CNT[6] + * Offset: 0x90~0xA4 PWM Counter Register 0, 2, 4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CNT |PWM Data Register (Read Only) + * | | |User can monitor CNTR to know the current value in 16-bit period counter. + * |[16] |DIRF |PWM Direction Indicator Flag (Read Only) + * | | |0 = Counter is counting down. + * | | |1 = Counter is counting up. + * @var PWM_T::WGCTL0 + * Offset: 0xB0 PWM Generation Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |ZPCTL0 |PWM Zero Point Control + * | | |00 = Do nothing. + * | | |01 = PWM zero point output Low. + * | | |10 = PWM zero point output High. + * | | |11 = PWM zero point output Toggle. + * | | |Note: PWM can control output level when PWM counter counts to 0. + * |[3:2] |ZPCTL1 |PWM Zero Point Control + * | | |00 = Do nothing. + * | | |01 = PWM zero point output Low. + * | | |10 = PWM zero point output High. + * | | |11 = PWM zero point output Toggle. + * | | |Note: PWM can control output level when PWM counter counts to 0. + * |[5:4] |ZPCTL2 |PWM Zero Point Control + * | | |00 = Do nothing. + * | | |01 = PWM zero point output Low. + * | | |10 = PWM zero point output High. + * | | |11 = PWM zero point output Toggle. + * | | |Note: PWM can control output level when PWM counter counts to 0. + * |[7:6] |ZPCTL3 |PWM Zero Point Control + * | | |00 = Do nothing. + * | | |01 = PWM zero point output Low. + * | | |10 = PWM zero point output High. + * | | |11 = PWM zero point output Toggle. + * | | |Note: PWM can control output level when PWM counter counts to 0. + * |[9:8] |ZPCTL4 |PWM Zero Point Control + * | | |00 = Do nothing. + * | | |01 = PWM zero point output Low. + * | | |10 = PWM zero point output High. + * | | |11 = PWM zero point output Toggle. + * | | |Note: PWM can control output level when PWM counter counts to 0. + * |[11:10] |ZPCTL5 |PWM Zero Point Control + * | | |00 = Do nothing. + * | | |01 = PWM zero point output Low. + * | | |10 = PWM zero point output High. + * | | |11 = PWM zero point output Toggle. + * | | |Note: PWM can control output level when PWM counter counts to 0. + * |[17:16] |PRDPCTL0 |PWM Period (Center) Point Control + * | | |00 = Do nothing. + * | | |01 = PWM period (center) point output Low. + * | | |10 = PWM period (center) point output High. + * | | |11 = PWM period (center) point output Toggle. + * | | |Note1: PWM can control output level when PWM counter counts to (PERIODn+1). + * | | |Note2: This bit is center point control when PWM counter operating in up-down counter type. + * |[19:18] |PRDPCTL1 |PWM Period (Center) Point Control + * | | |00 = Do nothing. + * | | |01 = PWM period (center) point output Low. + * | | |10 = PWM period (center) point output High. + * | | |11 = PWM period (center) point output Toggle. + * | | |Note1: PWM can control output level when PWM counter counts to (PERIODn+1). + * | | |Note2: This bit is center point control when PWM counter operating in up-down counter type. + * |[21:20] |PRDPCTL2 |PWM Period (Center) Point Control + * | | |00 = Do nothing. + * | | |01 = PWM period (center) point output Low. + * | | |10 = PWM period (center) point output High. + * | | |11 = PWM period (center) point output Toggle. + * | | |Note1: PWM can control output level when PWM counter counts to (PERIODn+1). + * | | |Note2: This bit is center point control when PWM counter operating in up-down counter type. + * |[23:22] |PRDPCTL3 |PWM Period (Center) Point Control + * | | |00 = Do nothing. + * | | |01 = PWM period (center) point output Low. + * | | |10 = PWM period (center) point output High. + * | | |11 = PWM period (center) point output Toggle. + * | | |Note1: PWM can control output level when PWM counter counts to (PERIODn+1). + * | | |Note2: This bit is center point control when PWM counter operating in up-down counter type. + * |[25:24] |PRDPCTL4 |PWM Period (Center) Point Control + * | | |00 = Do nothing. + * | | |01 = PWM period (center) point output Low. + * | | |10 = PWM period (center) point output High. + * | | |11 = PWM period (center) point output Toggle. + * | | |Note1: PWM can control output level when PWM counter counts to (PERIODn+1). + * | | |Note2: This bit is center point control when PWM counter operating in up-down counter type. + * |[27:26] |PRDPCTL5 |PWM Period (Center) Point Control + * | | |00 = Do nothing. + * | | |01 = PWM period (center) point output Low. + * | | |10 = PWM period (center) point output High. + * | | |11 = PWM period (center) point output Toggle. + * | | |Note1: PWM can control output level when PWM counter counts to (PERIODn+1). + * | | |Note2: This bit is center point control when PWM counter operating in up-down counter type. + * @var PWM_T::WGCTL1 + * Offset: 0xB4 PWM Generation Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CMPUCTL0 |PWM Compare Up Point Control + * | | |00 = Do nothing. + * | | |01 = PWM compare up point output Low. + * | | |10 = PWM compare up point output High. + * | | |11 = PWM compare up point output Toggle. + * | | |Note1: PWM can control output level when PWM counter counts up to CMPDAT. + * | | |Note2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. + * |[3:2] |CMPUCTL1 |PWM Compare Up Point Control + * | | |00 = Do nothing. + * | | |01 = PWM compare up point output Low. + * | | |10 = PWM compare up point output High. + * | | |11 = PWM compare up point output Toggle. + * | | |Note1: PWM can control output level when PWM counter counts up to CMPDAT. + * | | |Note2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. + * |[5:4] |CMPUCTL2 |PWM Compare Up Point Control + * | | |00 = Do nothing. + * | | |01 = PWM compare up point output Low. + * | | |10 = PWM compare up point output High. + * | | |11 = PWM compare up point output Toggle. + * | | |Note1: PWM can control output level when PWM counter counts up to CMPDAT. + * | | |Note2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. + * |[7:6] |CMPUCTL3 |PWM Compare Up Point Control + * | | |00 = Do nothing. + * | | |01 = PWM compare up point output Low. + * | | |10 = PWM compare up point output High. + * | | |11 = PWM compare up point output Toggle. + * | | |Note1: PWM can control output level when PWM counter counts up to CMPDAT. + * | | |Note2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. + * |[9:8] |CMPUCTL4 |PWM Compare Up Point Control + * | | |00 = Do nothing. + * | | |01 = PWM compare up point output Low. + * | | |10 = PWM compare up point output High. + * | | |11 = PWM compare up point output Toggle. + * | | |Note1: PWM can control output level when PWM counter counts up to CMPDAT. + * | | |Note2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. + * |[11:10] |CMPUCTL5 |PWM Compare Up Point Control + * | | |00 = Do nothing. + * | | |01 = PWM compare up point output Low. + * | | |10 = PWM compare up point output High. + * | | |11 = PWM compare up point output Toggle. + * | | |Note1: PWM can control output level when PWM counter counts up to CMPDAT. + * | | |Note2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4. + * |[17:16] |CMPDCTL0 |PWM Compare Down Point Control + * | | |00 = Do nothing. + * | | |01 = PWM compare down point output Low. + * | | |10 = PWM compare down point output High. + * | | |11 = PWM compare down point output Toggle. + * | | |Note1: PWM can control output level when PWM counter counts down to CMPDAT. + * | | |Note2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. + * |[19:18] |CMPDCTL1 |PWM Compare Down Point Control + * | | |00 = Do nothing. + * | | |01 = PWM compare down point output Low. + * | | |10 = PWM compare down point output High. + * | | |11 = PWM compare down point output Toggle. + * | | |Note1: PWM can control output level when PWM counter counts down to CMPDAT. + * | | |Note2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. + * |[21:20] |CMPDCTL2 |PWM Compare Down Point Control + * | | |00 = Do nothing. + * | | |01 = PWM compare down point output Low. + * | | |10 = PWM compare down point output High. + * | | |11 = PWM compare down point output Toggle. + * | | |Note1: PWM can control output level when PWM counter counts down to CMPDAT. + * | | |Note2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. + * |[23:22] |CMPDCTL3 |PWM Compare Down Point Control + * | | |00 = Do nothing. + * | | |01 = PWM compare down point output Low. + * | | |10 = PWM compare down point output High. + * | | |11 = PWM compare down point output Toggle. + * | | |Note1: PWM can control output level when PWM counter counts down to CMPDAT. + * | | |Note2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. + * |[25:24] |CMPDCTL4 |PWM Compare Down Point Control + * | | |00 = Do nothing. + * | | |01 = PWM compare down point output Low. + * | | |10 = PWM compare down point output High. + * | | |11 = PWM compare down point output Toggle. + * | | |Note1: PWM can control output level when PWM counter counts down to CMPDAT. + * | | |Note2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. + * |[27:26] |CMPDCTL5 |PWM Compare Down Point Control + * | | |00 = Do nothing. + * | | |01 = PWM compare down point output Low. + * | | |10 = PWM compare down point output High. + * | | |11 = PWM compare down point output Toggle. + * | | |Note1: PWM can control output level when PWM counter counts down to CMPDAT. + * | | |Note2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4. + * @var PWM_T::MSKEN + * Offset: 0xB8 PWM Mask Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKEN0 |PWM Mask Enable Bits + * | | |The PWM output signal will be masked when this bit is enabled + * | | |The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. + * | | |0 = PWM output signal is non-masked. + * | | |1 = PWM output signal is masked and output MSKDATn data. + * |[1] |MSKEN1 |PWM Mask Enable Bits + * | | |The PWM output signal will be masked when this bit is enabled + * | | |The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. + * | | |0 = PWM output signal is non-masked. + * | | |1 = PWM output signal is masked and output MSKDATn data. + * |[2] |MSKEN2 |PWM Mask Enable Bits + * | | |The PWM output signal will be masked when this bit is enabled + * | | |The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. + * | | |0 = PWM output signal is non-masked. + * | | |1 = PWM output signal is masked and output MSKDATn data. + * |[3] |MSKEN3 |PWM Mask Enable Bits + * | | |The PWM output signal will be masked when this bit is enabled + * | | |The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. + * | | |0 = PWM output signal is non-masked. + * | | |1 = PWM output signal is masked and output MSKDATn data. + * |[4] |MSKEN4 |PWM Mask Enable Bits + * | | |The PWM output signal will be masked when this bit is enabled + * | | |The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. + * | | |0 = PWM output signal is non-masked. + * | | |1 = PWM output signal is masked and output MSKDATn data. + * |[5] |MSKEN5 |PWM Mask Enable Bits + * | | |The PWM output signal will be masked when this bit is enabled + * | | |The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. + * | | |0 = PWM output signal is non-masked. + * | | |1 = PWM output signal is masked and output MSKDATn data. + * @var PWM_T::MSK + * Offset: 0xBC PWM Mask Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKDAT0 |PWM Mask Data Bit + * | | |This data bit control the state of PWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding PWM channel n. + * | | |0 = Output logic low to PWM channel n. + * | | |1 = Output logic high to PWM channel n. + * |[1] |MSKDAT1 |PWM Mask Data Bit + * | | |This data bit control the state of PWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding PWM channel n. + * | | |0 = Output logic low to PWM channel n. + * | | |1 = Output logic high to PWM channel n. + * |[2] |MSKDAT2 |PWM Mask Data Bit + * | | |This data bit control the state of PWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding PWM channel n. + * | | |0 = Output logic low to PWM channel n. + * | | |1 = Output logic high to PWM channel n. + * |[3] |MSKDAT3 |PWM Mask Data Bit + * | | |This data bit control the state of PWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding PWM channel n. + * | | |0 = Output logic low to PWM channel n. + * | | |1 = Output logic high to PWM channel n. + * |[4] |MSKDAT4 |PWM Mask Data Bit + * | | |This data bit control the state of PWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding PWM channel n. + * | | |0 = Output logic low to PWM channel n. + * | | |1 = Output logic high to PWM channel n. + * |[5] |MSKDAT5 |PWM Mask Data Bit + * | | |This data bit control the state of PWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding PWM channel n. + * | | |0 = Output logic low to PWM channel n. + * | | |1 = Output logic high to PWM channel n. + * @var PWM_T::BNF + * Offset: 0xC0 PWM Brake Noise Filter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRK0NFEN |PWM Brake 0 Noise Filter Enable Bit + * | | |0 = Noise filter of PWM Brake 0 Disabled. + * | | |1 = Noise filter of PWM Brake 0 Enabled. + * |[3:1] |BRK0NFSEL |Brake 0 Edge Detector Filter Clock Selection + * | | |000 = Filter clock = HCLK. + * | | |001 = Filter clock = HCLK/2. + * | | |010 = Filter clock = HCLK/4. + * | | |011 = Filter clock = HCLK/8. + * | | |100 = Filter clock = HCLK/16. + * | | |101 = Filter clock = HCLK/32. + * | | |110 = Filter clock = HCLK/64. + * | | |111 = Filter clock = HCLK/128. + * |[6:4] |BRK0NFCNT |Brake 0 Edge Detector Filter Count + * | | |The register bits control the Brake0 filter counter to count from 0 to BRK1FCNT. + * |[7] |BRK0PINV |Brake 0 Pin Inverse + * | | |0 = The state of pin PWMx_BRAKE0 is passed to the negative edge detector. + * | | |1 = The inversed state of pin PWMx_BRAKE10 is passed to the negative edge detector. + * |[8] |BRK1FEN |PWM Brake 1 Noise Filter Enable Bit + * | | |0 = Noise filter of PWM Brake 1 Disabled. + * | | |1 = Noise filter of PWM Brake 1 Enabled. + * |[11:9] |BRK1NFSEL |Brake 1 Edge Detector Filter Clock Selection + * | | |000 = Filter clock = HCLK. + * | | |001 = Filter clock = HCLK/2. + * | | |010 = Filter clock = HCLK/4. + * | | |011 = Filter clock = HCLK/8. + * | | |100 = Filter clock = HCLK/16. + * | | |101 = Filter clock = HCLK/32. + * | | |110 = Filter clock = HCLK/64. + * | | |111 = Filter clock = HCLK/128. + * |[14:12] |BRK1FCNT |Brake 1 Edge Detector Filter Count + * | | |The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT. + * |[15] |BRK1PINV |Brake 1 Pin Inverse + * | | |0 = The state of pin PWMx_BRAKE1 is passed to the negative edge detector. + * | | |1 = The inversed state of pin PWMx_BRAKE1 is passed to the negative edge detector. + * |[16] |BK0SRC |Brake 0 Pin Source Select + * | | |For PWM0 setting: + * | | |0 = Brake 0 pin source come from PWM0_BRAKE0. + * | | |1 = Brake 0 pin source come from PWM1_BRAKE0. + * | | |For PWM1 setting: + * | | |0 = Brake 0 pin source come from PWM1_BRAKE0. + * | | |1 = Brake 0 pin source come from PWM0_BRAKE0. + * |[24] |BK1SRC |Brake 1 Pin Source Select + * | | |For PWM0 setting: + * | | |0 = Brake 1 pin source come from PWM0_BRAKE1. + * | | |1 = Brake 1 pin source come from PWM1_BRAKE1. + * | | |For PWM1 setting: + * | | |0 = Brake 1 pin source come from PWM1_BRAKE1. + * | | |1 = Brake 1 pin source come from PWM0_BRAKE1. + * @var PWM_T::FAILBRK + * Offset: 0xC4 PWM System Fail Brake Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CSSBRKEN |Clock Security System Detection Trigger PWM Brake Function 0 Enable Bit + * | | |0 = Brake Function triggered by CSS detection Disabled. + * | | |1 = Brake Function triggered by CSS detection Enabled. + * |[1] |BODBRKEN |Brown-out Detection Trigger PWM Brake Function 0 Enable Bit + * | | |0 = Brake Function triggered by BOD Disabled. + * | | |1 = Brake Function triggered by BOD Enabled. + * |[3] |CORBRKEN |Core Lockup Detection Trigger PWM Brake Function 0 Enable Bit + * | | |0 = Brake Function triggered by Core lockup detection Disabled. + * | | |1 = Brake Function triggered by Core lockup detection Enabled. + * @var PWM_T::BRKCTL[3] + * Offset: 0xC8~0xD0 PWM Brake Edge Detect Control Register 0/1, 2/3, 4/5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CPO0EBEN |Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect) + * | | |0 = ACMP0_O as edge-detect brake source Disabled. + * | | |1 = ACMP0_O as edge-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[1] |CPO1EBEN |Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect) + * | | |0 = ACMP1_O as edge-detect brake source Disabled. + * | | |1 = ACMP1_O as edge-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[4] |BRKP0EEN |Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect) + * | | |0 = BKP0 pin as edge-detect brake source Disabled. + * | | |1 = BKP0 pin as edge-detect brake source Enabled. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[5] |BRKP1EEN |Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect) + * | | |0 = BKP1 pin as edge-detect brake source Disabled. + * | | |1 = BKP1 pin as edge-detect brake source Enabled. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[7] |SYSEBEN |Enable System Fail As Edge-detect Brake Source (Write Protect) + * | | |0 = System Fail condition as edge-detect brake source Disabled. + * | | |1 = System Fail condition as edge-detect brake source Enabled. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[8] |CPO0LBEN |Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect) + * | | |0 = ACMP0_O as level-detect brake source Disabled. + * | | |1 = ACMP0_O as level-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[9] |CPO1LBEN |Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect) + * | | |0 = ACMP1_O as level-detect brake source Disabled. + * | | |1 = ACMP1_O as level-detect brake source Enabled. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[12] |BRKP0LEN |Enable BKP0 Pin As Level-detect Brake Source (Write Protect) + * | | |0 = PWMx_BRAKE0 pin as level-detect brake source Disabled. + * | | |1 = PWMx_BRAKE0 pin as level-detect brake source Enabled. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[13] |BRKP1LEN |Enable BKP1 Pin As Level-detect Brake Source (Write Protect) + * | | |0 = PWMx_BRAKE1 pin as level-detect brake source Disabled. + * | | |1 = PWMx_BRAKE1 pin as level-detect brake source Enabled. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[15] |SYSLBEN |Enable System Fail As Level-detect Brake Source (Write Protect) + * | | |0 = System Fail condition as level-detect brake source Disabled. + * | | |1 = System Fail condition as level-detect brake source Enabled. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[17:16] |BRKAEVEN |PWM Brake Action Select for Even Channel (Write Protect) + * | | |00 = PWM even channel level-detect brake function not affect channel output. + * | | |01 = PWM even channel output tri-state when level-detect brake happened. + * | | |10 = PWM even channel output low level when level-detect brake happened. + * | | |11 = PWM even channel output high level when level-detect brake happened. + * | | |Note: These bits are write protected. Refer to SYS_REGLCTL register. + * |[19:18] |BRKAODD |PWM Brake Action Select for Odd Channel (Write Protect) + * | | |00 = PWM odd channel level-detect brake function not affect channel output. + * | | |01 = PWM odd channel output tri-state when level-detect brake happened. + * | | |10 = PWM odd channel output low level when level-detect brake happened. + * | | |11 = PWM odd channel output high level when level-detect brake happened. + * | | |Note: These bits are write protected. Refer to SYS_REGLCTL register. + * @var PWM_T::POLCTL + * Offset: 0xD4 PWM Pin Polar Inverse Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PINV0 |PWM PIN Polar Inverse Control + * | | |The register controls polarity state of PWM output. + * | | |0 = PWM output polar inverse Disabled. + * | | |1 = PWM output polar inverse Enabled. + * |[1] |PINV1 |PWM PIN Polar Inverse Control + * | | |The register controls polarity state of PWM output. + * | | |0 = PWM output polar inverse Disabled. + * | | |1 = PWM output polar inverse Enabled. + * |[2] |PINV2 |PWM PIN Polar Inverse Control + * | | |The register controls polarity state of PWM output. + * | | |0 = PWM output polar inverse Disabled. + * | | |1 = PWM output polar inverse Enabled. + * |[3] |PINV3 |PWM PIN Polar Inverse Control + * | | |The register controls polarity state of PWM output. + * | | |0 = PWM output polar inverse Disabled. + * | | |1 = PWM output polar inverse Enabled. + * |[4] |PINV4 |PWM PIN Polar Inverse Control + * | | |The register controls polarity state of PWM output. + * | | |0 = PWM output polar inverse Disabled. + * | | |1 = PWM output polar inverse Enabled. + * |[5] |PINV5 |PWM PIN Polar Inverse Control + * | | |The register controls polarity state of PWM output. + * | | |0 = PWM output polar inverse Disabled. + * | | |1 = PWM output polar inverse Enabled. + * @var PWM_T::POEN + * Offset: 0xD8 PWM Output Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |POEN0 |PWM Pin Output Enable Bits + * | | |0 = PWM pin at tri-state. + * | | |1 = PWM pin in output mode. + * |[1] |POEN1 |PWM Pin Output Enable Bits + * | | |0 = PWM pin at tri-state. + * | | |1 = PWM pin in output mode. + * |[2] |POEN2 |PWM Pin Output Enable Bits + * | | |0 = PWM pin at tri-state. + * | | |1 = PWM pin in output mode. + * |[3] |POEN3 |PWM Pin Output Enable Bits + * | | |0 = PWM pin at tri-state. + * | | |1 = PWM pin in output mode. + * |[4] |POEN4 |PWM Pin Output Enable Bits + * | | |0 = PWM pin at tri-state. + * | | |1 = PWM pin in output mode. + * |[5] |POEN5 |PWM Pin Output Enable Bits + * | | |0 = PWM pin at tri-state. + * | | |1 = PWM pin in output mode. + * @var PWM_T::SWBRK + * Offset: 0xDC PWM Software Brake Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKETRG0 |PWM Edge Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger Edge brake, and set BRKEIFn to 1 in PWM_INTSTS1 register. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[1] |BRKETRG2 |PWM Edge Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger Edge brake, and set BRKEIFn to 1 in PWM_INTSTS1 register. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[2] |BRKETRG4 |PWM Edge Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger Edge brake, and set BRKEIFn to 1 in PWM_INTSTS1 register. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[8] |BRKLTRG0 |PWM Level Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM_INTSTS1 register. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[9] |BRKLTRG2 |PWM Level Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM_INTSTS1 register. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[10] |BRKLTRG4 |PWM Level Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM_INTSTS1 register. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * @var PWM_T::INTEN0 + * Offset: 0xE0 PWM Interrupt Enable Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIEN0 |PWM Zero Point Interrupt Enable Bit 0 + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[2] |ZIEN2 |PWM Zero Point Interrupt Enable Bit 2 + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[4] |ZIEN4 |PWM Zero Point Interrupt Enable Bit 4 + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[8] |PIEN0 |PWM Period Point Interrupt Enable Bit 0 + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note: When up-down counter type, period point means center point. + * |[10] |PIEN2 |PWM Period Point Interrupt Enable Bit 2 + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note: When up-down counter type, period point means center point. + * |[12] |PIEN4 |PWM Period Point Interrupt Enable Bit 4 + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note: When up-down counter type, period point means center point. + * |[16] |CMPUIEN0 |PWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding PWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. + * |[17] |CMPUIEN1 |PWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding PWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. + * |[18] |CMPUIEN2 |PWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding PWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. + * |[19] |CMPUIEN3 |PWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding PWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. + * |[20] |CMPUIEN4 |PWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding PWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. + * |[21] |CMPUIEN5 |PWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding PWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4. + * |[24] |CMPDIEN0 |PWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. + * |[25] |CMPDIEN1 |PWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. + * |[26] |CMPDIEN2 |PWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. + * |[27] |CMPDIEN3 |PWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. + * |[28] |CMPDIEN4 |PWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. + * |[29] |CMPDIEN5 |PWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4. + * @var PWM_T::INTEN1 + * Offset: 0xE4 PWM Interrupt Enable Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKEIEN0_1|PWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect) + * | | |0 = Edge-detect Brake interrupt for channel0/1 Disabled. + * | | |1 = Edge-detect Brake interrupt for channel0/1 Enabled. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[1] |BRKEIEN2_3|PWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect) + * | | |0 = Edge-detect Brake interrupt for channel2/3 Disabled. + * | | |1 = Edge-detect Brake interrupt for channel2/3 Enabled. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[2] |BRKEIEN4_5|PWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect) + * | | |0 = Edge-detect Brake interrupt for channel4/5 Disabled. + * | | |1 = Edge-detect Brake interrupt for channel4/5 Enabled. + * | | |Note: This bitr is write protected. Refer to SYS_REGLCTL register. + * |[8] |BRKLIEN0_1|PWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect) + * | | |0 = Level-detect Brake interrupt for channel0/1 Disabled. + * | | |1 = Level-detect Brake interrupt for channel0/1 Enabled. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[9] |BRKLIEN2_3|PWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect) + * | | |0 = Level-detect Brake interrupt for channel2/3 Disabled. + * | | |1 = Level-detect Brake interrupt for channel2/3 Enabled. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[10] |BRKLIEN4_5|PWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect) + * | | |0 = Level-detect Brake interrupt for channel4/5 Disabled. + * | | |1 = Level-detect Brake interrupt for channel4/5 Enabled. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * @var PWM_T::INTSTS0 + * Offset: 0xE8 PWM Interrupt Flag Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIF0 |PWM Zero Point Interrupt Flag 0 + * | | |This bit is set by hardware when PWM_CH0 counter reaches 0. + * | | |Note: This bit can be cleared to 0 by software writing 1. + * |[2] |ZIF2 |PWM Zero Point Interrupt Flag 2 + * | | |This bit is set by hardware when PWM_CH2 counter reaches 0. + * | | |Note: This bit can be cleared to 0 by software writing 1. + * |[4] |ZIF4 |PWM Zero Point Interrupt Flag 4 + * | | |This bit is set by hardware when PWM_CH4 counter reaches 0. + * | | |Note: This bit can be cleared to 0 by software writing 1. + * |[8] |PIF0 |PWM Period Point Interrupt Flag 0 + * | | |This bit is set by hardware when PWM_CH0 counter reaches PWM_PERIOD0. + * | | |Note: This bit can be cleared to 0 by software writing 1. + * |[10] |PIF2 |PWM Period Point Interrupt Flag 2 + * | | |This bit is set by hardware when PWM_CH2 counter reaches PWM_PERIOD2. + * | | |Note: This bit can be cleared to 0 by software writing 1. + * |[12] |PIF4 |PWM Period Point Interrupt Flag 4 + * | | |This bit is set by hardware when PWM_CH4 counter reaches PWM_PERIOD4. + * | | |Note: This bit can be cleared to 0 by software writing 1. + * |[21:16] |CMPUIFn |PWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when PWM counter up count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4. + * |[24] |CMPDIF0 |PWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. + * |[25] |CMPDIF1 |PWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. + * |[26] |CMPDIF2 |PWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. + * |[27] |CMPDIF3 |PWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. + * |[28] |CMPDIF4 |PWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. + * |[29] |CMPDIF5 |PWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4. + * @var PWM_T::INTSTS1 + * Offset: 0xEC PWM Interrupt Flag Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKEIF0 |PWM Channel0 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = PWM channel0 edge-detect brake event do not happened. + * | | |1 = When PWM channel0 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[1] |BRKEIF1 |PWM Channel1 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = PWM channel1 edge-detect brake event do not happened. + * | | |1 = When PWM channel1 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[2] |BRKEIF2 |PWM Channel2 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = PWM channel2 edge-detect brake event do not happened. + * | | |1 = When PWM channel2 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[3] |BRKEIF3 |PWM Channel3 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = PWM channel3 edge-detect brake event do not happened. + * | | |1 = When PWM channel3 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[4] |BRKEIF4 |PWM Channel4 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = PWM channel4 edge-detect brake event do not happened. + * | | |1 = When PWM channel4 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[5] |BRKEIF5 |PWM Channel5 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = PWM channel5 edge-detect brake event do not happened. + * | | |1 = When PWM channel5 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[8] |BRKLIF0 |PWM Channel0 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = PWM channel0 level-detect brake event do not happened. + * | | |1 = When PWM channel0 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[9] |BRKLIF1 |PWM Channel1 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = PWM channel1 level-detect brake event do not happened. + * | | |1 = When PWM channel1 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[10] |BRKLIF2 |PWM Channel2 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = PWM channel2 level-detect brake event do not happened. + * | | |1 = When PWM channel2 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[11] |BRKLIF3 |PWM Channel3 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = PWM channel3 level-detect brake event do not happened. + * | | |1 = When PWM channel3 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[12] |BRKLIF4 |PWM Channel4 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = PWM channel4 level-detect brake event do not happened. + * | | |1 = When PWM channel4 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[13] |BRKLIF5 |PWM Channel5 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = PWM channel5 level-detect brake event do not happened. + * | | |1 = When PWM channel5 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[16] |BRKESTS0 |PWM Channel0 Edge-detect Brake Status (Read Only) + * | | |0 = PWM channel0 edge-detect brake state is released. + * | | |1 = When PWM channel0 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel0 at brake state. + * |[17] |BRKESTS1 |PWM Channel1 Edge-detect Brake Status (Read Only) + * | | |0 = PWM channel1 edge-detect brake state is released. + * | | |1 = When PWM channel1 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel1 at brake state. + * |[18] |BRKESTS2 |PWM Channel2 Edge-detect Brake Status (Read Only) + * | | |0 = PWM channel2 edge-detect brake state is released. + * | | |1 = When PWM channel2 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel2 at brake state. + * |[19] |BRKESTS3 |PWM Channel3 Edge-detect Brake Status (Read Only) + * | | |0 = PWM channel3 edge-detect brake state is released. + * | | |1 = When PWM channel3 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel3 at brake state. + * |[20] |BRKESTS4 |PWM Channel4 Edge-detect Brake Status (Read Only) + * | | |0 = PWM channel4 edge-detect brake state is released. + * | | |1 = When PWM channel4 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel4 at brake state. + * |[21] |BRKESTS5 |PWM Channel5 Edge-detect Brake Status (Read Only) + * | | |0 = PWM channel5 edge-detect brake state is released. + * | | |1 = When PWM channel5 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel5 at brake state. + * |[24] |BRKLSTS0 |PWM Channel0 Level-detect Brake Status (Read Only) + * | | |0 = PWM channel0 level-detect brake state is released. + * | | |1 = When PWM channel0 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel0 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished + * | | |The PWM waveform will start output from next full PWM period. + * |[25] |BRKLSTS1 |PWM Channel1 Level-detect Brake Status (Read Only) + * | | |0 = PWM channel1 level-detect brake state is released. + * | | |1 = When PWM channel1 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel1 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished + * | | |The PWM waveform will start output from next full PWM period. + * |[26] |BRKLSTS2 |PWM Channel2 Level-detect Brake Status (Read Only) + * | | |0 = PWM channel2 level-detect brake state is released. + * | | |1 = When PWM channel2 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel2 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished + * | | |The PWM waveform will start output from next full PWM period. + * |[27] |BRKLSTS3 |PWM Channel3 Level-detect Brake Status (Read Only) + * | | |0 = PWM channel3 level-detect brake state is released. + * | | |1 = When PWM channel3 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel3 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished + * | | |The PWM waveform will start output from next full PWM period. + * |[28] |BRKLSTS4 |PWM Channel4 Level-detect Brake Status (Read Only) + * | | |0 = PWM channel4 level-detect brake state is released. + * | | |1 = When PWM channel4 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel4 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished + * | | |The PWM waveform will start output from next full PWM period. + * |[29] |BRKLSTS5 |PWM Channel5 Level-detect Brake Status (Read Only) + * | | |0 = PWM channel5 level-detect brake state is released. + * | | |1 = When PWM channel5 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel5 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, PWM will release brake state until current PWM period finished + * | | |The PWM waveform will start output from next full PWM period. + * @var PWM_T::EADCTS0 + * Offset: 0xF8 PWM Trigger EADC Source Select Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |TRGSEL0 |PWM_CH0 Trigger EADC Source Select + * | | |0000 = PWM_CH0 zero point. + * | | |0001 = PWM_CH0 period point. + * | | |0010 = PWM_CH0 zero or period point. + * | | |0011 = PWM_CH0 up-count CMPDAT point. + * | | |0100 = PWM_CH0 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = PWM_CH1 up-count CMPDAT point. + * | | |1001 = PWM_CH1 down-count CMPDAT point. + * | | |Others = reserved. + * |[7] |TRGEN0 |PWM_CH0 Trigger EADC Enable Bit + * | | |0 = PWM_CH0 Trigger EADC function Disabled. + * | | |1 = PWM_CH0 Trigger EADC function Enabled. + * |[11:8] |TRGSEL1 |PWM_CH1 Trigger EADC Source Select + * | | |0000 = PWM_CH0 zero point. + * | | |0001 = PWM_CH0 period point. + * | | |0010 = PWM_CH0 zero or period point. + * | | |0011 = PWM_CH0 up-count CMPDAT point. + * | | |0100 = PWM_CH0 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = PWM_CH1 up-count CMPDAT point. + * | | |1001 = PWM_CH1 down-count CMPDAT point. + * | | |Others = reserved. + * |[15] |TRGEN1 |PWM_CH1 Trigger EADC Enable Bit + * | | |0 = PWM_CH1 Trigger EADC function Disabled. + * | | |1 = PWM_CH1 Trigger EADC function Enabled. + * |[19:16] |TRGSEL2 |PWM_CH2 Trigger EADC Source Select + * | | |0000 = PWM_CH2 zero point. + * | | |0001 = PWM_CH2 period point. + * | | |0010 = PWM_CH2 zero or period point. + * | | |0011 = PWM_CH2 up-count CMPDAT point. + * | | |0100 = PWM_CH2 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = PWM_CH3 up-count CMPDAT point. + * | | |1001 = PWM_CH3 down-count CMPDAT point. + * | | |Others = reserved. + * |[23] |TRGEN2 |PWM_CH2 Trigger EADC Enable Bit + * | | |0 = PWM_CH2 Trigger EADC function Disabled. + * | | |1 = PWM_CH2 Trigger EADC function Enabled. + * |[27:24] |TRGSEL3 |PWM_CH3 Trigger EADC Source Select + * | | |0000 = PWM_CH2 zero point. + * | | |0001 = PWM_CH2 period point. + * | | |0010 = PWM_CH2 zero or period point. + * | | |0011 = PWM_CH2 up-count CMPDAT point. + * | | |0100 = PWM_CH2 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = PWM_CH3 up-count CMPDAT point. + * | | |1001 = PWM_CH3 down-count CMPDAT point. + * | | |Others = reserved. + * |[31] |TRGEN3 |PWM_CH3 Trigger EADC Enable Bit + * | | |0 = PWM_CH3 Trigger EADC function Disabled. + * | | |1 = PWM_CH3 Trigger EADC function Enabled. + * @var PWM_T::EADCTS1 + * Offset: 0xFC PWM Trigger EADC Source Select Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |TRGSEL4 |PWM_CH4 Trigger EADC Source Select + * | | |0000 = PWM_CH4 zero point. + * | | |0001 = PWM_CH4 period point. + * | | |0010 = PWM_CH4 zero or period point. + * | | |0011 = PWM_CH4 up-count CMPDAT point. + * | | |0100 = PWM_CH4 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = PWM_CH5 up-count CMPDAT point. + * | | |1001 = PWM_CH5 down-count CMPDAT point. + * | | |Others = reserved. + * |[7] |TRGEN4 |PWM_CH4 Trigger EADC Enable Bit + * | | |0 = PWM_CH4 Trigger EADC function Disabled. + * | | |1 = PWM_CH4 Trigger EADC function Enabled. + * |[11:8] |TRGSEL5 |PWM_CH5 Trigger EADC Source Select + * | | |0000 = PWM_CH4 zero point. + * | | |0001 = PWM_CH4 period point. + * | | |0010 = PWM_CH4 zero or period point. + * | | |0011 = PWM_CH4 up-count CMPDAT point. + * | | |0100 = PWM_CH4 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = PWM_CH5 up-count CMPDAT point. + * | | |1001 = PWM_CH5 down-count CMPDAT point. + * | | |Others = reserved. + * |[15] |TRGEN5 |PWM_CH5 Trigger EADC Enable Bit + * | | |0 = PWM_CH5 Trigger EADC function Disabled. + * | | |1 = PWM_CH5 Trigger EADC function Enabled. + * @var PWM_T::SSCTL + * Offset: 0x110 PWM Synchronous Start Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SSEN0 |PWM Synchronous Start Function Enable Bit 0 + * | | |When synchronous start function is enabled, the PWM_CH0 counter enable bit (CNTEN0) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). + * | | |0 = PWM synchronous start function Disabled. + * | | |1 = PWM synchronous start function Enabled. + * |[2] |SSEN2 |PWM Synchronous Start Function Enable Bit 2 + * | | |When synchronous start function is enabled, the PWM_CH2 counter enable bit (CNTEN2) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). + * | | |0 = PWM synchronous start function Disabled. + * | | |1 = PWM synchronous start function Enabled. + * |[4] |SSEN4 |PWM Synchronous Start Function Enable Bit 4 + * | | |When synchronous start function is enabled, the PWM_CH4 counter enable bit (CNTEN4) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). + * | | |0 = PWM synchronous start function Disabled. + * | | |1 = PWM synchronous start function Enabled. + * |[9:8] |SSRC |PWM Synchronous Start Source Select Bits + * | | |00 = Synchronous start source come from PWM0. + * | | |01 = Synchronous start source come from PWM1. + * | | |10 = Synchronous start source come from BPWM0. + * | | |11 = Synchronous start source come from BPWM1. + * @var PWM_T::SSTRG + * Offset: 0x114 PWM Synchronous Start Trigger Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTSEN |PWM Counter Synchronous Start Enable (Write Only) + * | | |PMW counter synchronous enable function is used to make selected PWM channels (include PWM0_CHx and PWM1_CHx) start counting at the same time. + * | | |Writing this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated PWM channel counter synchronous start function is enabled. + * @var PWM_T::STATUS + * Offset: 0x120 PWM Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTMAX0 |Time-base Counter 0 Equal to 0xFFFF Latched Flag + * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. + * | | |1 = indicates the time-base counter reached its maximum value. + * | | |Note: This bit can be cleared by software writing 1. + * |[2] |CNTMAX2 |Time-base Counter 2 Equal to 0xFFFF Latched Flag + * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. + * | | |1 = indicates the time-base counter reached its maximum value. + * | | |Note: This bit can be cleared by software writing 1. + * |[4] |CNTMAX4 |Time-base Counter 4 Equal to 0xFFFF Latched Flag + * | | |0 = The time-base counter never reached its maximum value 0xFFFF. + * | | |1 = The time-base counter reached its maximum value. + * | | |Note: This bit can be cleared by software writing 1. + * |[16] |EADCTRG0 |EADC Start of Conversion Status + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = An EADC start of conversion trigger event has occurred. + * | | |Note: This bit can be cleared by software writing 1. + * |[17] |EADCTRG1 |EADC Start of Conversion Status + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = An EADC start of conversion trigger event has occurred. + * | | |Note: This bit can be cleared by software writing 1. + * |[18] |EADCTRG2 |EADC Start of Conversion Status + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = An EADC start of conversion trigger event has occurred. + * | | |Note: This bit can be cleared by software writing 1. + * |[19] |EADCTRG3 |EADC Start of Conversion Status + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = An EADC start of conversion trigger event has occurred. + * | | |Note: This bit can be cleared by software writing 1. + * |[20] |EADCTRG4 |EADC Start of Conversion Status + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = An EADC start of conversion trigger event has occurred. + * | | |Note: This bit can be cleared by software writing 1. + * |[21] |EADCTRG5 |EADC Start of Conversion Status + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = An EADC start of conversion trigger event has occurred. + * | | |Note: This bit can be cleared by software writing 1. + * @var PWM_T::CAPINEN + * Offset: 0x200 PWM Capture Input Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPINEN0 |Capture Input Enable Bits + * | | |0 = PWM Channel capture input path Disabled + * | | |The input of PWM channel capture function is always regarded as 0. + * | | |1 = PWM Channel capture input path Enabled + * | | |The input of PWM channel capture function comes from correlative multifunction pin. + * |[1] |CAPINEN1 |Capture Input Enable Bits + * | | |0 = PWM Channel capture input path Disabled + * | | |The input of PWM channel capture function is always regarded as 0. + * | | |1 = PWM Channel capture input path Enabled + * | | |The input of PWM channel capture function comes from correlative multifunction pin. + * |[2] |CAPINEN2 |Capture Input Enable Bits + * | | |0 = PWM Channel capture input path Disabled + * | | |The input of PWM channel capture function is always regarded as 0. + * | | |1 = PWM Channel capture input path Enabled + * | | |The input of PWM channel capture function comes from correlative multifunction pin. + * |[3] |CAPINEN3 |Capture Input Enable Bits + * | | |0 = PWM Channel capture input path Disabled + * | | |The input of PWM channel capture function is always regarded as 0. + * | | |1 = PWM Channel capture input path Enabled + * | | |The input of PWM channel capture function comes from correlative multifunction pin. + * |[4] |CAPINEN4 |Capture Input Enable Bits + * | | |0 = PWM Channel capture input path Disabled + * | | |The input of PWM channel capture function is always regarded as 0. + * | | |1 = PWM Channel capture input path Enabled + * | | |The input of PWM channel capture function comes from correlative multifunction pin. + * |[5] |CAPINEN5 |Capture Input Enable Bits + * | | |0 = PWM Channel capture input path Disabled + * | | |The input of PWM channel capture function is always regarded as 0. + * | | |1 = PWM Channel capture input path Enabled + * | | |The input of PWM channel capture function comes from correlative multifunction pin. + * @var PWM_T::CAPCTL + * Offset: 0x204 PWM Capture Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPEN0 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[1] |CAPEN1 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[2] |CAPEN2 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[3] |CAPEN3 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[4] |CAPEN4 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[5] |CAPEN5 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[8] |CAPINV0 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[9] |CAPINV1 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[10] |CAPINV2 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[11] |CAPINV3 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[12] |CAPINV4 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[13] |CAPINV5 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[16] |RCRLDEN0 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[17] |RCRLDEN1 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[18] |RCRLDEN2 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[19] |RCRLDEN3 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[20] |RCRLDEN4 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[21] |RCRLDEN5 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[24] |FCRLDEN0 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[25] |FCRLDEN1 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[26] |FCRLDEN2 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[27] |FCRLDEN3 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[28] |FCRLDEN4 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[29] |FCRLDEN5 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * @var PWM_T::CAPSTS + * Offset: 0x208 PWM Capture Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CRLIFOV0 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[1] |CRLIFOV1 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[2] |CRLIFOV2 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[3] |CRLIFOV3 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[4] |CRLIFOV4 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[5] |CRLIFOV5 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[8] |CFLIFOV0 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * |[9] |CFLIFOV1 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * |[10] |CFLIFOV2 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * |[11] |CFLIFOV3 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * |[12] |CFLIFOV4 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * |[13] |CFLIFOV5 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * @var PWM_T::PDMACTL + * Offset: 0x23C PWM PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CHEN0_1 |Channel 0/1 PDMA Enable Bit + * | | |0 = Channel 0/1 PDMA function Disabled. + * | | |1 = Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory. + * |[2:1] |CAPMOD0_1 |Select PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 to Do PDMA Transfer + * | | |00 = Reserved. + * | | |01 = PWM_RCAPDAT0/1. + * | | |10 = PWM_FCAPDAT0/1. + * | | |11 = Both PWM_RCAPDAT0/1 and PWM_FCAPDAT0/1. + * |[3] |CAPORD0_1 |Capture Channel 0/1 Rising/Falling Order + * | | |Set this bit to determine whether the PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 is the first captured data transferred to memory through PDMA when CAPMOD0_1 =11. + * | | |0 = PWM_FCAPDAT0/1 is the first captured data to memory. + * | | |1 = PWM_RCAPDAT0/1 is the first captured data to memory. + * |[4] |CHSEL0_1 |Select Channel 0/1 to Do PDMA Transfer + * | | |0 = Channel0. + * | | |1 = Channel1. + * |[8] |CHEN2_3 |Channel 2/3 PDMA Enable Bit + * | | |0 = Channel 2/3 PDMA function Disabled. + * | | |1 = Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory. + * |[10:9] |CAPMOD2_3 |Select PWM_RCAPDAT2/3 or PWM_FCAODAT2/3 to Do PDMA Transfer + * | | |00 = Reserved. + * | | |01 = PWM_RCAPDAT2/3. + * | | |10 = PWM_FCAPDAT2/3. + * | | |11 = Both PWM_RCAPDAT2/3 and PWM_FCAPDAT2/3. + * |[11] |CAPORD2_3 |Capture Channel 2/3 Rising/Falling Order + * | | |Set this bit to determine whether the PWM_RCAPDAT2/3 or PWM_FCAPDAT2/3 is the first captured data transferred to memory through PDMA when CAPMOD2_3 =11. + * | | |0 = PWM_FCAPDAT2/3 is the first captured data to memory. + * | | |1 = PWM_RCAPDAT2/3 is the first captured data to memory. + * |[12] |CHSEL2_3 |Select Channel 2/3 to Do PDMA Transfer + * | | |0 = Channel2. + * | | |1 = Channel3. + * |[16] |CHEN4_5 |Channel 4/5 PDMA Enable Bit + * | | |0 = Channel 4/5 PDMA function Disabled. + * | | |1 = Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory. + * |[18:17] |CAPMOD4_5 |Select PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 to Do PDMA Transfer + * | | |00 = Reserved. + * | | |01 = PWM_RCAPDAT4/5. + * | | |10 = PWM_FCAPDAT4/5. + * | | |11 = Both PWM_RCAPDAT4/5 and PWM_FCAPDAT4/5. + * |[19] |CAPORD4_5 |Capture Channel 4/5 Rising/Falling Order + * | | |Set this bit to determine whether the PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 is the first captured data transferred to memory through PDMA when CAPMOD4_5 =11. + * | | |0 = PWM_FCAPDAT4/5 is the first captured data to memory. + * | | |1 = PWM_RCAPDAT4/5 is the first captured data to memory. + * |[20] |CHSEL4_5 |Select Channel 4/5 to Do PDMA Transfer + * | | |0 = Channel4. + * | | |1 = Channel5. + * @var PWM_T::PDMACAP[3] + * Offset: 0x240~0x248 PWM Capture Channel 01 23 45 PDMA Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CAPBUF |PWM Capture PDMA Register (Read Only) + * | | |This register is used as a buffer to transfer PWM capture rising or falling data to memory by PDMA. + * @var PWM_T::CAPIEN + * Offset: 0x250 PWM Capture Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPRIEN0 |PWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[1] |CAPRIEN1 |PWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[2] |CAPRIEN2 |PWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[3] |CAPRIEN3 |PWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[4] |CAPRIEN4 |PWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[5] |CAPRIEN5 |PWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[8] |CAPFIEN0 |PWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * |[9] |CAPFIEN1 |PWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * |[10] |CAPFIEN2 |PWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * |[11] |CAPFIEN3 |PWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * |[12] |CAPFIEN4 |PWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * |[13] |CAPFIEN5 |PWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * @var PWM_T::CAPIF + * Offset: 0x254 PWM Capture Interrupt Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CRLIF0 |PWM Capture Rising Latch Interrupt Flag + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data. + * | | |Note2: This bit is cleared by writing 1 to it. + * |[1] |CRLIF1 |PWM Capture Rising Latch Interrupt Flag + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data. + * | | |Note2: This bit is cleared by writing 1 to it. + * |[2] |CRLIF2 |PWM Capture Rising Latch Interrupt Flag + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data. + * | | |Note2: This bit is cleared by writing 1 to it. + * |[3] |CRLIF3 |PWM Capture Rising Latch Interrupt Flag + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data. + * | | |Note2: This bit is cleared by writing 1 to it. + * |[4] |CRLIF4 |PWM Capture Rising Latch Interrupt Flag + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data. + * | | |Note2: This bit is cleared by writing 1 to it. + * |[5] |CRLIF5 |PWM Capture Rising Latch Interrupt Flag + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data. + * | | |Note2: This bit is cleared by writing 1 to it. + * |[8] |CFLIF0 |PWM Capture Falling Latch Interrupt Flag + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data. + * | | |Note2: This bit is cleared by writing 1 to it. + * |[9] |CFLIF1 |PWM Capture Falling Latch Interrupt Flag + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data. + * | | |Note2: This bit is cleared by writing 1 to it. + * |[10] |CFLIF2 |PWM Capture Falling Latch Interrupt Flag + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data. + * | | |Note2: This bit is cleared by writing 1 to it. + * |[11] |CFLIF3 |PWM Capture Falling Latch Interrupt Flag + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data. + * | | |Note2: This bit is cleared by writing 1 to it. + * |[12] |CFLIF4 |PWM Capture Falling Latch Interrupt Flag + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data. + * | | |Note2: This bit is cleared by writing 1 to it. + * |[13] |CFLIF5 |PWM Capture Falling Latch Interrupt Flag + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data. + * | | |Note2: This bit is cleared by writing 1 to it. + * @var PWM_T::PBUF[6] + * Offset: 0x304~0x318 PWM PERIOD0, 2, 4 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PBUF |PWM Period Register Buffer (Read Only) + * | | |Used as PERIOD active register. + * @var PWM_T::CMPBUF[6] + * Offset: 0x31C~0x330 PWM CMPDAT0~5 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMPBUF |PWM Comparator Register Buffer (Read Only) + * | | |Used as CMP active register. + */ + __IO uint32_t CTL0; /*!< [0x0000] PWM Control Register 0 */ + __IO uint32_t CTL1; /*!< [0x0004] PWM Control Register 1 */ + __I uint32_t RESERVE0[2]; + __IO uint32_t CLKSRC; /*!< [0x0010] PWM Clock Source Register */ + __IO uint32_t CLKPSC[3]; /*!< [0x0014 ~ 0x001c] PWM Clock Prescale Register */ + __IO uint32_t CNTEN; /*!< [0x0020] PWM Counter Enable Register */ + __IO uint32_t CNTCLR; /*!< [0x0024] PWM Clear Counter Register */ + __I uint32_t RESERVE1[2]; + __IO uint32_t PERIOD[6]; /*!< [0x0030 ~ 0x0044] PWM Period Register 0 */ + __I uint32_t RESERVE4[2]; + __IO uint32_t CMPDAT[6]; /*!< [0x0050 ~ 0x0064] PWM Comparator Register 0 ~ 5 */ + __I uint32_t RESERVE5[2]; + __IO uint32_t DTCTL[3]; /*!< [0x0070 ~ 0x0078] PWM Dead-time Control Register */ + __I uint32_t RESERVE6[5]; + __I uint32_t CNT[6]; /*!< [0x0090] PWM Counter Register 0,2,4 */ + __I uint32_t RESERVE9[2]; + __IO uint32_t WGCTL0; /*!< [0x00b0] PWM Generation Register 0 */ + __IO uint32_t WGCTL1; /*!< [0x00b4] PWM Generation Register 1 */ + __IO uint32_t MSKEN; /*!< [0x00b8] PWM Mask Enable Register */ + __IO uint32_t MSK; /*!< [0x00bc] PWM Mask Data Register */ + __IO uint32_t BNF; /*!< [0x00c0] PWM Brake Noise Filter Register */ + __IO uint32_t FAILBRK; /*!< [0x00c4] PWM System Fail Brake Control Register */ + __IO uint32_t BRKCTL[3]; /*!< [0x00c8 ~ 0x00d0] PWM Brake Edge Detect Control Register */ + __IO uint32_t POLCTL; /*!< [0x00d4] PWM Pin Polar Inverse Register */ + __IO uint32_t POEN; /*!< [0x00d8] PWM Output Enable Register */ + __O uint32_t SWBRK; /*!< [0x00dc] PWM Software Brake Control Register */ + __IO uint32_t INTEN0; /*!< [0x00e0] PWM Interrupt Enable Register 0 */ + __IO uint32_t INTEN1; /*!< [0x00e4] PWM Interrupt Enable Register 1 */ + __IO uint32_t INTSTS0; /*!< [0x00e8] PWM Interrupt Flag Register 0 */ + __IO uint32_t INTSTS1; /*!< [0x00ec] PWM Interrupt Flag Register 1 */ + __I uint32_t RESERVE10[2]; + __IO uint32_t EADCTS0; /*!< [0x00f8] PWM Trigger EADC Source Select Register 0 */ + __IO uint32_t EADCTS1; /*!< [0x00fc] PWM Trigger EADC Source Select Register 1 */ + __I uint32_t RESERVE11[4]; + __IO uint32_t SSCTL; /*!< [0x0110] PWM Synchronous Start Control Register */ + __O uint32_t SSTRG; /*!< [0x0114] PWM Synchronous Start Trigger Register */ + __I uint32_t RESERVE12[2]; + __IO uint32_t STATUS; /*!< [0x0120] PWM Status Register */ + __I uint32_t RESERVE13[55]; + __IO uint32_t CAPINEN; /*!< [0x0200] PWM Capture Input Enable Register */ + __IO uint32_t CAPCTL; /*!< [0x0204] PWM Capture Control Register */ + __I uint32_t CAPSTS; /*!< [0x0208] PWM Capture Status Register */ + CAPDAT_T CAPDAT[6]; /*!< [0x020C] PWM Rising and Falling Capture Data Register 0~5 */ + __IO uint32_t PDMACTL; /*!< [0x023c] PWM PDMA Control Register */ + __I uint32_t PDMACAP[3]; /*!< [0x0240 ~ 0x0248] PWM Capture Channel 01, 23, 45 PDMA Register */ + __I uint32_t RESERVE14[1]; + __IO uint32_t CAPIEN; /*!< [0x0250] PWM Capture Interrupt Enable Register */ + __IO uint32_t CAPIF; /*!< [0x0254] PWM Capture Interrupt Flag Register */ + __I uint32_t RESERVE15[43]; + __I uint32_t PBUF[6]; /*!< [0x0304 ~ 0x0318] PWM PERIOD0 ~ 6 Buffer */ + __I uint32_t CMPBUF[6]; /*!< [0x031c ~ 0x0330] PWM CMPDAT0 ~ 5 Buffer */ + +} PWM_T; + +/** + @addtogroup PWM_CONST PWM Bit Field Definition + Constant Definitions for PWM Controller +@{ */ + +#define PWM_CTL0_CTRLDn_Pos (0) /*!< PWM_T::CTL0: CTRLDn Position */ +#define PWM_CTL0_CTRLDn_Msk (0x3ful << PWM_CTL0_CTRLDn_Pos) /*!< PWM_T::CTL0: CTRLDn Mask */ + +#define PWM_CTL0_CTRLD0_Pos (0) /*!< PWM_T::CTL0: CTRLD0 Position */ +#define PWM_CTL0_CTRLD0_Msk (0x1ul << PWM_CTL0_CTRLD0_Pos) /*!< PWM_T::CTL0: CTRLD0 Mask */ + +#define PWM_CTL0_CTRLD1_Pos (1) /*!< PWM_T::CTL0: CTRLD1 Position */ +#define PWM_CTL0_CTRLD1_Msk (0x1ul << PWM_CTL0_CTRLD1_Pos) /*!< PWM_T::CTL0: CTRLD1 Mask */ + +#define PWM_CTL0_CTRLD2_Pos (2) /*!< PWM_T::CTL0: CTRLD2 Position */ +#define PWM_CTL0_CTRLD2_Msk (0x1ul << PWM_CTL0_CTRLD2_Pos) /*!< PWM_T::CTL0: CTRLD2 Mask */ + +#define PWM_CTL0_CTRLD3_Pos (3) /*!< PWM_T::CTL0: CTRLD3 Position */ +#define PWM_CTL0_CTRLD3_Msk (0x1ul << PWM_CTL0_CTRLD3_Pos) /*!< PWM_T::CTL0: CTRLD3 Mask */ + +#define PWM_CTL0_CTRLD4_Pos (4) /*!< PWM_T::CTL0: CTRLD4 Position */ +#define PWM_CTL0_CTRLD4_Msk (0x1ul << PWM_CTL0_CTRLD4_Pos) /*!< PWM_T::CTL0: CTRLD4 Mask */ + +#define PWM_CTL0_CTRLD5_Pos (5) /*!< PWM_T::CTL0: CTRLD5 Position */ +#define PWM_CTL0_CTRLD5_Msk (0x1ul << PWM_CTL0_CTRLD5_Pos) /*!< PWM_T::CTL0: CTRLD5 Mask */ + +#define PWM_CTL0_IMMLDENn_Pos (16) /*!< PWM_T::CTL0: IMMLDENn Position */ +#define PWM_CTL0_IMMLDENn_Msk (0x3ful << PWM_CTL0_IMMLDENn_Pos) /*!< PWM_T::CTL0: IMMLDENn Mask */ + +#define PWM_CTL0_IMMLDEN0_Pos (16) /*!< PWM_T::CTL0: IMMLDEN0 Position */ +#define PWM_CTL0_IMMLDEN0_Msk (0x1ul << PWM_CTL0_IMMLDEN0_Pos) /*!< PWM_T::CTL0: IMMLDEN0 Mask */ + +#define PWM_CTL0_IMMLDEN1_Pos (17) /*!< PWM_T::CTL0: IMMLDEN1 Position */ +#define PWM_CTL0_IMMLDEN1_Msk (0x1ul << PWM_CTL0_IMMLDEN1_Pos) /*!< PWM_T::CTL0: IMMLDEN1 Mask */ + +#define PWM_CTL0_IMMLDEN2_Pos (18) /*!< PWM_T::CTL0: IMMLDEN2 Position */ +#define PWM_CTL0_IMMLDEN2_Msk (0x1ul << PWM_CTL0_IMMLDEN2_Pos) /*!< PWM_T::CTL0: IMMLDEN2 Mask */ + +#define PWM_CTL0_IMMLDEN3_Pos (19) /*!< PWM_T::CTL0: IMMLDEN3 Position */ +#define PWM_CTL0_IMMLDEN3_Msk (0x1ul << PWM_CTL0_IMMLDEN3_Pos) /*!< PWM_T::CTL0: IMMLDEN3 Mask */ + +#define PWM_CTL0_IMMLDEN4_Pos (20) /*!< PWM_T::CTL0: IMMLDEN4 Position */ +#define PWM_CTL0_IMMLDEN4_Msk (0x1ul << PWM_CTL0_IMMLDEN4_Pos) /*!< PWM_T::CTL0: IMMLDEN4 Mask */ + +#define PWM_CTL0_IMMLDEN5_Pos (21) /*!< PWM_T::CTL0: IMMLDEN5 Position */ +#define PWM_CTL0_IMMLDEN5_Msk (0x1ul << PWM_CTL0_IMMLDEN5_Pos) /*!< PWM_T::CTL0: IMMLDEN5 Mask */ + +#define PWM_CTL0_DBGHALT_Pos (30) /*!< PWM_T::CTL0: DBGHALT Position */ +#define PWM_CTL0_DBGHALT_Msk (0x1ul << PWM_CTL0_DBGHALT_Pos) /*!< PWM_T::CTL0: DBGHALT Mask */ + +#define PWM_CTL0_DBGTRIOFF_Pos (31) /*!< PWM_T::CTL0: DBGTRIOFF Position */ +#define PWM_CTL0_DBGTRIOFF_Msk (0x1ul << PWM_CTL0_DBGTRIOFF_Pos) /*!< PWM_T::CTL0: DBGTRIOFF Mask */ + +#define PWM_CTL1_CNTTYPE0_Pos (0) /*!< PWM_T::CTL1: CNTTYPE0 Position */ +#define PWM_CTL1_CNTTYPE0_Msk (0x3ul << PWM_CTL1_CNTTYPE0_Pos) /*!< PWM_T::CTL1: CNTTYPE0 Mask */ + +#define PWM_CTL1_CNTTYPE2_Pos (4) /*!< PWM_T::CTL1: CNTTYPE2 Position */ +#define PWM_CTL1_CNTTYPE2_Msk (0x3ul << PWM_CTL1_CNTTYPE2_Pos) /*!< PWM_T::CTL1: CNTTYPE2 Mask */ + +#define PWM_CTL1_CNTTYPE4_Pos (8) /*!< PWM_T::CTL1: CNTTYPE4 Position */ +#define PWM_CTL1_CNTTYPE4_Msk (0x3ul << PWM_CTL1_CNTTYPE4_Pos) /*!< PWM_T::CTL1: CNTTYPE4 Mask */ + +#define PWM_CTL1_OUTMODEn_Pos (24) /*!< PWM_T::CTL1: OUTMODEn Position */ +#define PWM_CTL1_OUTMODEn_Msk (0x7ul << PWM_CTL1_OUTMODEn_Pos) /*!< PWM_T::CTL1: OUTMODEn Mask */ + +#define PWM_CTL1_OUTMODE0_Pos (24) /*!< PWM_T::CTL1: OUTMODE0 Position */ +#define PWM_CTL1_OUTMODE0_Msk (0x1ul << PWM_CTL1_OUTMODE0_Pos) /*!< PWM_T::CTL1: OUTMODE0 Mask */ + +#define PWM_CTL1_OUTMODE2_Pos (25) /*!< PWM_T::CTL1: OUTMODE2 Position */ +#define PWM_CTL1_OUTMODE2_Msk (0x1ul << PWM_CTL1_OUTMODE2_Pos) /*!< PWM_T::CTL1: OUTMODE2 Mask */ + +#define PWM_CTL1_OUTMODE4_Pos (26) /*!< PWM_T::CTL1: OUTMODE4 Position */ +#define PWM_CTL1_OUTMODE4_Msk (0x1ul << PWM_CTL1_OUTMODE4_Pos) /*!< PWM_T::CTL1: OUTMODE4 Mask */ + +#define PWM_CLKSRC_ECLKSRC0_Pos (0) /*!< PWM_T::CLKSRC: ECLKSRC0 Position */ +#define PWM_CLKSRC_ECLKSRC0_Msk (0x7ul << PWM_CLKSRC_ECLKSRC0_Pos) /*!< PWM_T::CLKSRC: ECLKSRC0 Mask */ + +#define PWM_CLKSRC_ECLKSRC2_Pos (8) /*!< PWM_T::CLKSRC: ECLKSRC2 Position */ +#define PWM_CLKSRC_ECLKSRC2_Msk (0x7ul << PWM_CLKSRC_ECLKSRC2_Pos) /*!< PWM_T::CLKSRC: ECLKSRC2 Mask */ + +#define PWM_CLKSRC_ECLKSRC4_Pos (16) /*!< PWM_T::CLKSRC: ECLKSRC4 Position */ +#define PWM_CLKSRC_ECLKSRC4_Msk (0x7ul << PWM_CLKSRC_ECLKSRC4_Pos) /*!< PWM_T::CLKSRC: ECLKSRC4 Mask */ + +#define PWM_CLKPSC_CLKPSC_Pos (0) /*!< PWM_T::CLKPSC: CLKPSC Position */ +#define PWM_CLKPSC_CLKPSC_Msk (0xffful << PWM_CLKPSC_CLKPSC_Pos) /*!< PWM_T::CLKPSC: CLKPSC Mask */ + +#define PWM_CLKPSC0_1_CLKPSC_Pos (0) /*!< PWM_T::CLKPSC0_1: CLKPSC Position */ +#define PWM_CLKPSC0_1_CLKPSC_Msk (0xffful << PWM_CLKPSC0_1_CLKPSC_Pos) /*!< PWM_T::CLKPSC0_1: CLKPSC Mask */ + +#define PWM_CLKPSC2_3_CLKPSC_Pos (0) /*!< PWM_T::CLKPSC2_3: CLKPSC Position */ +#define PWM_CLKPSC2_3_CLKPSC_Msk (0xffful << PWM_CLKPSC2_3_CLKPSC_Pos) /*!< PWM_T::CLKPSC2_3: CLKPSC Mask */ + +#define PWM_CLKPSC4_5_CLKPSC_Pos (0) /*!< PWM_T::CLKPSC4_5: CLKPSC Position */ +#define PWM_CLKPSC4_5_CLKPSC_Msk (0xffful << PWM_CLKPSC4_5_CLKPSC_Pos) /*!< PWM_T::CLKPSC4_5: CLKPSC Mask */ + +#define PWM_CNTEN_CNTEN0_Pos (0) /*!< PWM_T::CNTEN: CNTEN0 Position */ +#define PWM_CNTEN_CNTEN0_Msk (0x1ul << PWM_CNTEN_CNTEN0_Pos) /*!< PWM_T::CNTEN: CNTEN0 Mask */ + +#define PWM_CNTEN_CNTEN2_Pos (2) /*!< PWM_T::CNTEN: CNTEN2 Position */ +#define PWM_CNTEN_CNTEN2_Msk (0x1ul << PWM_CNTEN_CNTEN2_Pos) /*!< PWM_T::CNTEN: CNTEN2 Mask */ + +#define PWM_CNTEN_CNTEN4_Pos (4) /*!< PWM_T::CNTEN: CNTEN4 Position */ +#define PWM_CNTEN_CNTEN4_Msk (0x1ul << PWM_CNTEN_CNTEN4_Pos) /*!< PWM_T::CNTEN: CNTEN4 Mask */ + +#define PWM_CNTCLR_CNTCLR0_Pos (0) /*!< PWM_T::CNTCLR: CNTCLR0 Position */ +#define PWM_CNTCLR_CNTCLR0_Msk (0x1ul << PWM_CNTCLR_CNTCLR0_Pos) /*!< PWM_T::CNTCLR: CNTCLR0 Mask */ + +#define PWM_CNTCLR_CNTCLR2_Pos (2) /*!< PWM_T::CNTCLR: CNTCLR2 Position */ +#define PWM_CNTCLR_CNTCLR2_Msk (0x1ul << PWM_CNTCLR_CNTCLR2_Pos) /*!< PWM_T::CNTCLR: CNTCLR2 Mask */ + +#define PWM_CNTCLR_CNTCLR4_Pos (4) /*!< PWM_T::CNTCLR: CNTCLR4 Position */ +#define PWM_CNTCLR_CNTCLR4_Msk (0x1ul << PWM_CNTCLR_CNTCLR4_Pos) /*!< PWM_T::CNTCLR: CNTCLR4 Mask */ + +#define PWM_PERIOD_PERIOD_Pos (0) /*!< PWM_T::PERIOD: PERIOD Position */ +#define PWM_PERIOD_PERIOD_Msk (0xfffful << PWM_PERIOD_PERIOD_Pos) /*!< PWM_T::PERIOD: PERIOD Mask */ + +#define PWM_CMPDAT_CMP_Pos (0) /*!< PWM_T::CMPDAT: CMP Position */ +#define PWM_CMPDAT_CMP_Msk (0xfffful << PWM_CMPDAT_CMP_Pos) /*!< PWM_T::CMPDAT: CMP Mask */ + +#define PWM_DTCTL_DTCNT_Pos (0) /*!< PWM_T::DTCTL: DTCNT Position */ +#define PWM_DTCTL_DTCNT_Msk (0xffful << PWM_DTCTL_DTCNT_Pos) /*!< PWM_T::DTCTL: DTCNT Mask */ + +#define PWM_DTCTL_DTEN_Pos (16) /*!< PWM_T::DTCTL: DTEN Position */ +#define PWM_DTCTL_DTEN_Msk (0x1ul << PWM_DTCTL_DTEN_Pos) /*!< PWM_T::DTCTL: DTEN Mask */ + +#define PWM_DTCTL_DTCKSEL_Pos (24) /*!< PWM_T::DTCTL: DTCKSEL Position */ +#define PWM_DTCTL_DTCKSEL_Msk (0x1ul << PWM_DTCTL_DTCKSEL_Pos) /*!< PWM_T::DTCTL: DTCKSEL Mask */ + +#define PWM_DTCTL0_1_DTCNT_Pos (0) /*!< PWM_T::DTCTL0_1: DTCNT Position */ +#define PWM_DTCTL0_1_DTCNT_Msk (0xffful << PWM_DTCTL0_1_DTCNT_Pos) /*!< PWM_T::DTCTL0_1: DTCNT Mask */ + +#define PWM_DTCTL0_1_DTEN_Pos (16) /*!< PWM_T::DTCTL0_1: DTEN Position */ +#define PWM_DTCTL0_1_DTEN_Msk (0x1ul << PWM_DTCTL0_1_DTEN_Pos) /*!< PWM_T::DTCTL0_1: DTEN Mask */ + +#define PWM_DTCTL0_1_DTCKSEL_Pos (24) /*!< PWM_T::DTCTL0_1: DTCKSEL Position */ +#define PWM_DTCTL0_1_DTCKSEL_Msk (0x1ul << PWM_DTCTL0_1_DTCKSEL_Pos) /*!< PWM_T::DTCTL0_1: DTCKSEL Mask */ + +#define PWM_DTCTL2_3_DTCNT_Pos (0) /*!< PWM_T::DTCTL2_3: DTCNT Position */ +#define PWM_DTCTL2_3_DTCNT_Msk (0xffful << PWM_DTCTL2_3_DTCNT_Pos) /*!< PWM_T::DTCTL2_3: DTCNT Mask */ + +#define PWM_DTCTL2_3_DTEN_Pos (16) /*!< PWM_T::DTCTL2_3: DTEN Position */ +#define PWM_DTCTL2_3_DTEN_Msk (0x1ul << PWM_DTCTL2_3_DTEN_Pos) /*!< PWM_T::DTCTL2_3: DTEN Mask */ + +#define PWM_DTCTL2_3_DTCKSEL_Pos (24) /*!< PWM_T::DTCTL2_3: DTCKSEL Position */ +#define PWM_DTCTL2_3_DTCKSEL_Msk (0x1ul << PWM_DTCTL2_3_DTCKSEL_Pos) /*!< PWM_T::DTCTL2_3: DTCKSEL Mask */ + +#define PWM_DTCTL4_5_DTCNT_Pos (0) /*!< PWM_T::DTCTL4_5: DTCNT Position */ +#define PWM_DTCTL4_5_DTCNT_Msk (0xffful << PWM_DTCTL4_5_DTCNT_Pos) /*!< PWM_T::DTCTL4_5: DTCNT Mask */ + +#define PWM_DTCTL4_5_DTEN_Pos (16) /*!< PWM_T::DTCTL4_5: DTEN Position */ +#define PWM_DTCTL4_5_DTEN_Msk (0x1ul << PWM_DTCTL4_5_DTEN_Pos) /*!< PWM_T::DTCTL4_5: DTEN Mask */ + +#define PWM_DTCTL4_5_DTCKSEL_Pos (24) /*!< PWM_T::DTCTL4_5: DTCKSEL Position */ +#define PWM_DTCTL4_5_DTCKSEL_Msk (0x1ul << PWM_DTCTL4_5_DTCKSEL_Pos) /*!< PWM_T::DTCTL4_5: DTCKSEL Mask */ + +#define PWM_CNT_CNT_Pos (0) /*!< PWM_T::CNT: CNT Position */ +#define PWM_CNT_CNT_Msk (0xfffful << PWM_CNT_CNT_Pos) /*!< PWM_T::CNT: CNT Mask */ + +#define PWM_CNT_DIRF_Pos (16) /*!< PWM_T::CNT: DIRF Position */ +#define PWM_CNT_DIRF_Msk (0x1ul << PWM_CNT_DIRF_Pos) /*!< PWM_T::CNT: DIRF Mask */ + +#define PWM_WGCTL0_ZPCTL0_Pos (0) /*!< PWM_T::WGCTL0: ZPCTL0 Position */ +#define PWM_WGCTL0_ZPCTL0_Msk (0x3ul << PWM_WGCTL0_ZPCTL0_Pos) /*!< PWM_T::WGCTL0: ZPCTL0 Mask */ + +#define PWM_WGCTL0_ZPCTL1_Pos (2) /*!< PWM_T::WGCTL0: ZPCTL1 Position */ +#define PWM_WGCTL0_ZPCTL1_Msk (0x3ul << PWM_WGCTL0_ZPCTL1_Pos) /*!< PWM_T::WGCTL0: ZPCTL1 Mask */ + +#define PWM_WGCTL0_ZPCTL2_Pos (4) /*!< PWM_T::WGCTL0: ZPCTL2 Position */ +#define PWM_WGCTL0_ZPCTL2_Msk (0x3ul << PWM_WGCTL0_ZPCTL2_Pos) /*!< PWM_T::WGCTL0: ZPCTL2 Mask */ + +#define PWM_WGCTL0_ZPCTL3_Pos (6) /*!< PWM_T::WGCTL0: ZPCTL3 Position */ +#define PWM_WGCTL0_ZPCTL3_Msk (0x3ul << PWM_WGCTL0_ZPCTL3_Pos) /*!< PWM_T::WGCTL0: ZPCTL3 Mask */ + +#define PWM_WGCTL0_ZPCTL4_Pos (8) /*!< PWM_T::WGCTL0: ZPCTL4 Position */ +#define PWM_WGCTL0_ZPCTL4_Msk (0x3ul << PWM_WGCTL0_ZPCTL4_Pos) /*!< PWM_T::WGCTL0: ZPCTL4 Mask */ + +#define PWM_WGCTL0_ZPCTL5_Pos (10) /*!< PWM_T::WGCTL0: ZPCTL5 Position */ +#define PWM_WGCTL0_ZPCTL5_Msk (0x3ul << PWM_WGCTL0_ZPCTL5_Pos) /*!< PWM_T::WGCTL0: ZPCTL5 Mask */ + +#define PWM_WGCTL0_PRDPCTL0_Pos (16) /*!< PWM_T::WGCTL0: PRDPCTL0 Position */ +#define PWM_WGCTL0_PRDPCTL0_Msk (0x3ul << PWM_WGCTL0_PRDPCTL0_Pos) /*!< PWM_T::WGCTL0: PRDPCTL0 Mask */ + +#define PWM_WGCTL0_PRDPCTL1_Pos (18) /*!< PWM_T::WGCTL0: PRDPCTL1 Position */ +#define PWM_WGCTL0_PRDPCTL1_Msk (0x3ul << PWM_WGCTL0_PRDPCTL1_Pos) /*!< PWM_T::WGCTL0: PRDPCTL1 Mask */ + +#define PWM_WGCTL0_PRDPCTL2_Pos (20) /*!< PWM_T::WGCTL0: PRDPCTL2 Position */ +#define PWM_WGCTL0_PRDPCTL2_Msk (0x3ul << PWM_WGCTL0_PRDPCTL2_Pos) /*!< PWM_T::WGCTL0: PRDPCTL2 Mask */ + +#define PWM_WGCTL0_PRDPCTL3_Pos (22) /*!< PWM_T::WGCTL0: PRDPCTL3 Position */ +#define PWM_WGCTL0_PRDPCTL3_Msk (0x3ul << PWM_WGCTL0_PRDPCTL3_Pos) /*!< PWM_T::WGCTL0: PRDPCTL3 Mask */ + +#define PWM_WGCTL0_PRDPCTL4_Pos (24) /*!< PWM_T::WGCTL0: PRDPCTL4 Position */ +#define PWM_WGCTL0_PRDPCTL4_Msk (0x3ul << PWM_WGCTL0_PRDPCTL4_Pos) /*!< PWM_T::WGCTL0: PRDPCTL4 Mask */ + +#define PWM_WGCTL0_PRDPCTL5_Pos (26) /*!< PWM_T::WGCTL0: PRDPCTL5 Position */ +#define PWM_WGCTL0_PRDPCTL5_Msk (0x3ul << PWM_WGCTL0_PRDPCTL5_Pos) /*!< PWM_T::WGCTL0: PRDPCTL5 Mask */ + +#define PWM_WGCTL1_CMPUCTLn_Pos (0) /*!< PWM_T::WGCTL1: CMPUCTLn Position */ +#define PWM_WGCTL1_CMPUCTLn_Msk (0xffful << PWM_WGCTL1_CMPUCTLn_Pos) /*!< PWM_T::WGCTL1: CMPUCTLn Mask */ + +#define PWM_WGCTL1_CMPUCTL0_Pos (0) /*!< PWM_T::WGCTL1: CMPUCTL0 Position */ +#define PWM_WGCTL1_CMPUCTL0_Msk (0x3ul << PWM_WGCTL1_CMPUCTL0_Pos) /*!< PWM_T::WGCTL1: CMPUCTL0 Mask */ + +#define PWM_WGCTL1_CMPUCTL1_Pos (2) /*!< PWM_T::WGCTL1: CMPUCTL1 Position */ +#define PWM_WGCTL1_CMPUCTL1_Msk (0x3ul << PWM_WGCTL1_CMPUCTL1_Pos) /*!< PWM_T::WGCTL1: CMPUCTL1 Mask */ + +#define PWM_WGCTL1_CMPUCTL2_Pos (4) /*!< PWM_T::WGCTL1: CMPUCTL2 Position */ +#define PWM_WGCTL1_CMPUCTL2_Msk (0x3ul << PWM_WGCTL1_CMPUCTL2_Pos) /*!< PWM_T::WGCTL1: CMPUCTL2 Mask */ + +#define PWM_WGCTL1_CMPUCTL3_Pos (6) /*!< PWM_T::WGCTL1: CMPUCTL3 Position */ +#define PWM_WGCTL1_CMPUCTL3_Msk (0x3ul << PWM_WGCTL1_CMPUCTL3_Pos) /*!< PWM_T::WGCTL1: CMPUCTL3 Mask */ + +#define PWM_WGCTL1_CMPUCTL4_Pos (8) /*!< PWM_T::WGCTL1: CMPUCTL4 Position */ +#define PWM_WGCTL1_CMPUCTL4_Msk (0x3ul << PWM_WGCTL1_CMPUCTL4_Pos) /*!< PWM_T::WGCTL1: CMPUCTL4 Mask */ + +#define PWM_WGCTL1_CMPUCTL5_Pos (10) /*!< PWM_T::WGCTL1: CMPUCTL5 Position */ +#define PWM_WGCTL1_CMPUCTL5_Msk (0x3ul << PWM_WGCTL1_CMPUCTL5_Pos) /*!< PWM_T::WGCTL1: CMPUCTL5 Mask */ + +#define PWM_WGCTL1_CMPDCTL0_Pos (16) /*!< PWM_T::WGCTL1: CMPDCTL0 Position */ +#define PWM_WGCTL1_CMPDCTL0_Msk (0x3ul << PWM_WGCTL1_CMPDCTL0_Pos) /*!< PWM_T::WGCTL1: CMPDCTL0 Mask */ + +#define PWM_WGCTL1_CMPDCTL1_Pos (18) /*!< PWM_T::WGCTL1: CMPDCTL1 Position */ +#define PWM_WGCTL1_CMPDCTL1_Msk (0x3ul << PWM_WGCTL1_CMPDCTL1_Pos) /*!< PWM_T::WGCTL1: CMPDCTL1 Mask */ + +#define PWM_WGCTL1_CMPDCTL2_Pos (20) /*!< PWM_T::WGCTL1: CMPDCTL2 Position */ +#define PWM_WGCTL1_CMPDCTL2_Msk (0x3ul << PWM_WGCTL1_CMPDCTL2_Pos) /*!< PWM_T::WGCTL1: CMPDCTL2 Mask */ + +#define PWM_WGCTL1_CMPDCTL3_Pos (22) /*!< PWM_T::WGCTL1: CMPDCTL3 Position */ +#define PWM_WGCTL1_CMPDCTL3_Msk (0x3ul << PWM_WGCTL1_CMPDCTL3_Pos) /*!< PWM_T::WGCTL1: CMPDCTL3 Mask */ + +#define PWM_WGCTL1_CMPDCTL4_Pos (24) /*!< PWM_T::WGCTL1: CMPDCTL4 Position */ +#define PWM_WGCTL1_CMPDCTL4_Msk (0x3ul << PWM_WGCTL1_CMPDCTL4_Pos) /*!< PWM_T::WGCTL1: CMPDCTL4 Mask */ + +#define PWM_WGCTL1_CMPDCTL5_Pos (26) /*!< PWM_T::WGCTL1: CMPDCTL5 Position */ +#define PWM_WGCTL1_CMPDCTL5_Msk (0x3ul << PWM_WGCTL1_CMPDCTL5_Pos) /*!< PWM_T::WGCTL1: CMPDCTL5 Mask */ + +#define PWM_MSKEN_MSKEN0_Pos (0) /*!< PWM_T::MSKEN: MSKEN0 Position */ +#define PWM_MSKEN_MSKEN0_Msk (0x1ul << PWM_MSKEN_MSKEN0_Pos) /*!< PWM_T::MSKEN: MSKEN0 Mask */ + +#define PWM_MSKEN_MSKEN1_Pos (1) /*!< PWM_T::MSKEN: MSKEN1 Position */ +#define PWM_MSKEN_MSKEN1_Msk (0x1ul << PWM_MSKEN_MSKEN1_Pos) /*!< PWM_T::MSKEN: MSKEN1 Mask */ + +#define PWM_MSKEN_MSKEN2_Pos (2) /*!< PWM_T::MSKEN: MSKEN2 Position */ +#define PWM_MSKEN_MSKEN2_Msk (0x1ul << PWM_MSKEN_MSKEN2_Pos) /*!< PWM_T::MSKEN: MSKEN2 Mask */ + +#define PWM_MSKEN_MSKEN3_Pos (3) /*!< PWM_T::MSKEN: MSKEN3 Position */ +#define PWM_MSKEN_MSKEN3_Msk (0x1ul << PWM_MSKEN_MSKEN3_Pos) /*!< PWM_T::MSKEN: MSKEN3 Mask */ + +#define PWM_MSKEN_MSKEN4_Pos (4) /*!< PWM_T::MSKEN: MSKEN4 Position */ +#define PWM_MSKEN_MSKEN4_Msk (0x1ul << PWM_MSKEN_MSKEN4_Pos) /*!< PWM_T::MSKEN: MSKEN4 Mask */ + +#define PWM_MSKEN_MSKEN5_Pos (5) /*!< PWM_T::MSKEN: MSKEN5 Position */ +#define PWM_MSKEN_MSKEN5_Msk (0x1ul << PWM_MSKEN_MSKEN5_Pos) /*!< PWM_T::MSKEN: MSKEN5 Mask */ + +#define PWM_MSK_MSKDAT0_Pos (0) /*!< PWM_T::MSK: MSKDAT0 Position */ +#define PWM_MSK_MSKDAT0_Msk (0x1ul << PWM_MSK_MSKDAT0_Pos) /*!< PWM_T::MSK: MSKDAT0 Mask */ + +#define PWM_MSK_MSKDAT1_Pos (1) /*!< PWM_T::MSK: MSKDAT1 Position */ +#define PWM_MSK_MSKDAT1_Msk (0x1ul << PWM_MSK_MSKDAT1_Pos) /*!< PWM_T::MSK: MSKDAT1 Mask */ + +#define PWM_MSK_MSKDAT2_Pos (2) /*!< PWM_T::MSK: MSKDAT2 Position */ +#define PWM_MSK_MSKDAT2_Msk (0x1ul << PWM_MSK_MSKDAT2_Pos) /*!< PWM_T::MSK: MSKDAT2 Mask */ + +#define PWM_MSK_MSKDAT3_Pos (3) /*!< PWM_T::MSK: MSKDAT3 Position */ +#define PWM_MSK_MSKDAT3_Msk (0x1ul << PWM_MSK_MSKDAT3_Pos) /*!< PWM_T::MSK: MSKDAT3 Mask */ + +#define PWM_MSK_MSKDAT4_Pos (4) /*!< PWM_T::MSK: MSKDAT4 Position */ +#define PWM_MSK_MSKDAT4_Msk (0x1ul << PWM_MSK_MSKDAT4_Pos) /*!< PWM_T::MSK: MSKDAT4 Mask */ + +#define PWM_MSK_MSKDAT5_Pos (5) /*!< PWM_T::MSK: MSKDAT5 Position */ +#define PWM_MSK_MSKDAT5_Msk (0x1ul << PWM_MSK_MSKDAT5_Pos) /*!< PWM_T::MSK: MSKDAT5 Mask */ + +#define PWM_BNF_BRK0FEN_Pos (0) /*!< PWM_T::BNF: BRK0NFEN Position */ +#define PWM_BNF_BRK0FEN_Msk (0x1ul << PWM_BNF_BRK0FEN_Pos) /*!< PWM_T::BNF: BRK0NFEN Mask */ + +#define PWM_BNF_BRK0NFSEL_Pos (1) /*!< PWM_T::BNF: BRK0NFSEL Position */ +#define PWM_BNF_BRK0NFSEL_Msk (0x7ul << PWM_BNF_BRK0NFSEL_Pos) /*!< PWM_T::BNF: BRK0NFSEL Mask */ + +#define PWM_BNF_BRK0NFCNT_Pos (4) /*!< PWM_T::BNF: BRK0NFCNT Position */ +#define PWM_BNF_BRK0NFCNT_Msk (0x7ul << PWM_BNF_BRK0NFCNT_Pos) /*!< PWM_T::BNF: BRK0NFCNT Mask */ + +#define PWM_BNF_BRK0PINV_Pos (7) /*!< PWM_T::BNF: BRK0PINV Position */ +#define PWM_BNF_BRK0PINV_Msk (0x1ul << PWM_BNF_BRK0PINV_Pos) /*!< PWM_T::BNF: BRK0PINV Mask */ + +#define PWM_BNF_BRK1FEN_Pos (8) /*!< PWM_T::BNF: BRK1FEN Position */ +#define PWM_BNF_BRK1FEN_Msk (0x1ul << PWM_BNF_BRK1FEN_Pos) /*!< PWM_T::BNF: BRK1FEN Mask */ + +#define PWM_BNF_BRK1NFSEL_Pos (9) /*!< PWM_T::BNF: BRK1NFSEL Position */ +#define PWM_BNF_BRK1NFSEL_Msk (0x7ul << PWM_BNF_BRK1NFSEL_Pos) /*!< PWM_T::BNF: BRK1NFSEL Mask */ + +#define PWM_BNF_BRK1FCNT_Pos (12) /*!< PWM_T::BNF: BRK1FCNT Position */ +#define PWM_BNF_BRK1FCNT_Msk (0x7ul << PWM_BNF_BRK1FCNT_Pos) /*!< PWM_T::BNF: BRK1FCNT Mask */ + +#define PWM_BNF_BRK1PINV_Pos (15) /*!< PWM_T::BNF: BRK1PINV Position */ +#define PWM_BNF_BRK1PINV_Msk (0x1ul << PWM_BNF_BRK1PINV_Pos) /*!< PWM_T::BNF: BRK1PINV Mask */ + +#define PWM_BNF_BK0SRC_Pos (16) /*!< PWM_T::BNF: BK0SRC Position */ +#define PWM_BNF_BK0SRC_Msk (0x1ul << PWM_BNF_BK0SRC_Pos) /*!< PWM_T::BNF: BK0SRC Mask */ + +#define PWM_BNF_BK1SRC_Pos (24) /*!< PWM_T::BNF: BK1SRC Position */ +#define PWM_BNF_BK1SRC_Msk (0x1ul << PWM_BNF_BK1SRC_Pos) /*!< PWM_T::BNF: BK1SRC Mask */ + +#define PWM_FAILBRK_CSSBRKEN_Pos (0) /*!< PWM_T::FAILBRK: CSSBRKEN Position */ +#define PWM_FAILBRK_CSSBRKEN_Msk (0x1ul << PWM_FAILBRK_CSSBRKEN_Pos) /*!< PWM_T::FAILBRK: CSSBRKEN Mask */ + +#define PWM_FAILBRK_BODBRKEN_Pos (1) /*!< PWM_T::FAILBRK: BODBRKEN Position */ +#define PWM_FAILBRK_BODBRKEN_Msk (0x1ul << PWM_FAILBRK_BODBRKEN_Pos) /*!< PWM_T::FAILBRK: BODBRKEN Mask */ + +#define PWM_FAILBRK_CORBRKEN_Pos (3) /*!< PWM_T::FAILBRK: CORBRKEN Position */ +#define PWM_FAILBRK_CORBRKEN_Msk (0x1ul << PWM_FAILBRK_CORBRKEN_Pos) /*!< PWM_T::FAILBRK: CORBRKEN Mask */ + +#define PWM_BRKCTL_CPO0EBEN_Pos (0) /*!< PWM_T::BRKCTL: CPO0EBEN Position */ +#define PWM_BRKCTL_CPO0EBEN_Msk (0x1ul << PWM_BRKCTL_CPO0EBEN_Pos) /*!< PWM_T::BRKCTL: CPO0EBEN Mask */ + +#define PWM_BRKCTL_CPO1EBEN_Pos (1) /*!< PWM_T::BRKCTL: CPO1EBEN Position */ +#define PWM_BRKCTL_CPO1EBEN_Msk (0x1ul << PWM_BRKCTL_CPO1EBEN_Pos) /*!< PWM_T::BRKCTL: CPO1EBEN Mask */ + +#define PWM_BRKCTL_BRKP0EEN_Pos (4) /*!< PWM_T::BRKCTL: BRKP0EEN Position */ +#define PWM_BRKCTL_BRKP0EEN_Msk (0x1ul << PWM_BRKCTL_BRKP0EEN_Pos) /*!< PWM_T::BRKCTL: BRKP0EEN Mask */ + +#define PWM_BRKCTL_BRKP1EEN_Pos (5) /*!< PWM_T::BRKCTL: BRKP1EEN Position */ +#define PWM_BRKCTL_BRKP1EEN_Msk (0x1ul << PWM_BRKCTL_BRKP1EEN_Pos) /*!< PWM_T::BRKCTL: BRKP1EEN Mask */ + +#define PWM_BRKCTL_SYSEBEN_Pos (7) /*!< PWM_T::BRKCTL: SYSEBEN Position */ +#define PWM_BRKCTL_SYSEBEN_Msk (0x1ul << PWM_BRKCTL_SYSEBEN_Pos) /*!< PWM_T::BRKCTL: SYSEBEN Mask */ + +#define PWM_BRKCTL_CPO0LBEN_Pos (8) /*!< PWM_T::BRKCTL: CPO0LBEN Position */ +#define PWM_BRKCTL_CPO0LBEN_Msk (0x1ul << PWM_BRKCTL_CPO0LBEN_Pos) /*!< PWM_T::BRKCTL: CPO0LBEN Mask */ + +#define PWM_BRKCTL_CPO1LBEN_Pos (9) /*!< PWM_T::BRKCTL: CPO1LBEN Position */ +#define PWM_BRKCTL_CPO1LBEN_Msk (0x1ul << PWM_BRKCTL_CPO1LBEN_Pos) /*!< PWM_T::BRKCTL: CPO1LBEN Mask */ + +#define PWM_BRKCTL_BRKP0LEN_Pos (12) /*!< PWM_T::BRKCTL: BRKP0LEN Position */ +#define PWM_BRKCTL_BRKP0LEN_Msk (0x1ul << PWM_BRKCTL_BRKP0LEN_Pos) /*!< PWM_T::BRKCTL: BRKP0LEN Mask */ + +#define PWM_BRKCTL_BRKP1LEN_Pos (13) /*!< PWM_T::BRKCTL: BRKP1LEN Position */ +#define PWM_BRKCTL_BRKP1LEN_Msk (0x1ul << PWM_BRKCTL_BRKP1LEN_Pos) /*!< PWM_T::BRKCTL: BRKP1LEN Mask */ + +#define PWM_BRKCTL_SYSLBEN_Pos (15) /*!< PWM_T::BRKCTL: SYSLBEN Position */ +#define PWM_BRKCTL_SYSLBEN_Msk (0x1ul << PWM_BRKCTL_SYSLBEN_Pos) /*!< PWM_T::BRKCTL: SYSLBEN Mask */ + +#define PWM_BRKCTL_BRKAEVEN_Pos (16) /*!< PWM_T::BRKCTL: BRKAEVEN Position */ +#define PWM_BRKCTL_BRKAEVEN_Msk (0x3ul << PWM_BRKCTL_BRKAEVEN_Pos) /*!< PWM_T::BRKCTL: BRKAEVEN Mask */ + +#define PWM_BRKCTL_BRKAODD_Pos (18) /*!< PWM_T::BRKCTL: BRKAODD Position */ +#define PWM_BRKCTL_BRKAODD_Msk (0x3ul << PWM_BRKCTL_BRKAODD_Pos) /*!< PWM_T::BRKCTL: BRKAODD Mask */ + +#define PWM_BRKCTL0_1_CPO0EBEN_Pos (0) /*!< PWM_T::BRKCTL0_1: CPO0EBEN Position */ +#define PWM_BRKCTL0_1_CPO0EBEN_Msk (0x1ul << PWM_BRKCTL0_1_CPO0EBEN_Pos) /*!< PWM_T::BRKCTL0_1: CPO0EBEN Mask */ + +#define PWM_BRKCTL0_1_CPO1EBEN_Pos (1) /*!< PWM_T::BRKCTL0_1: CPO1EBEN Position */ +#define PWM_BRKCTL0_1_CPO1EBEN_Msk (0x1ul << PWM_BRKCTL0_1_CPO1EBEN_Pos) /*!< PWM_T::BRKCTL0_1: CPO1EBEN Mask */ + +#define PWM_BRKCTL0_1_BRKP0EEN_Pos (4) /*!< PWM_T::BRKCTL0_1: BRKP0EEN Position */ +#define PWM_BRKCTL0_1_BRKP0EEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP0EEN_Pos) /*!< PWM_T::BRKCTL0_1: BRKP0EEN Mask */ + +#define PWM_BRKCTL0_1_BRKP1EEN_Pos (5) /*!< PWM_T::BRKCTL0_1: BRKP1EEN Position */ +#define PWM_BRKCTL0_1_BRKP1EEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP1EEN_Pos) /*!< PWM_T::BRKCTL0_1: BRKP1EEN Mask */ + +#define PWM_BRKCTL0_1_SYSEBEN_Pos (7) /*!< PWM_T::BRKCTL0_1: SYSEBEN Position */ +#define PWM_BRKCTL0_1_SYSEBEN_Msk (0x1ul << PWM_BRKCTL0_1_SYSEBEN_Pos) /*!< PWM_T::BRKCTL0_1: SYSEBEN Mask */ + +#define PWM_BRKCTL0_1_CPO0LBEN_Pos (8) /*!< PWM_T::BRKCTL0_1: CPO0LBEN Position */ +#define PWM_BRKCTL0_1_CPO0LBEN_Msk (0x1ul << PWM_BRKCTL0_1_CPO0LBEN_Pos) /*!< PWM_T::BRKCTL0_1: CPO0LBEN Mask */ + +#define PWM_BRKCTL0_1_CPO1LBEN_Pos (9) /*!< PWM_T::BRKCTL0_1: CPO1LBEN Position */ +#define PWM_BRKCTL0_1_CPO1LBEN_Msk (0x1ul << PWM_BRKCTL0_1_CPO1LBEN_Pos) /*!< PWM_T::BRKCTL0_1: CPO1LBEN Mask */ + +#define PWM_BRKCTL0_1_BRKP0LEN_Pos (12) /*!< PWM_T::BRKCTL0_1: BRKP0LEN Position */ +#define PWM_BRKCTL0_1_BRKP0LEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP0LEN_Pos) /*!< PWM_T::BRKCTL0_1: BRKP0LEN Mask */ + +#define PWM_BRKCTL0_1_BRKP1LEN_Pos (13) /*!< PWM_T::BRKCTL0_1: BRKP1LEN Position */ +#define PWM_BRKCTL0_1_BRKP1LEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP1LEN_Pos) /*!< PWM_T::BRKCTL0_1: BRKP1LEN Mask */ + +#define PWM_BRKCTL0_1_SYSLBEN_Pos (15) /*!< PWM_T::BRKCTL0_1: SYSLBEN Position */ +#define PWM_BRKCTL0_1_SYSLBEN_Msk (0x1ul << PWM_BRKCTL0_1_SYSLBEN_Pos) /*!< PWM_T::BRKCTL0_1: SYSLBEN Mask */ + +#define PWM_BRKCTL0_1_BRKAEVEN_Pos (16) /*!< PWM_T::BRKCTL0_1: BRKAEVEN Position */ +#define PWM_BRKCTL0_1_BRKAEVEN_Msk (0x3ul << PWM_BRKCTL0_1_BRKAEVEN_Pos) /*!< PWM_T::BRKCTL0_1: BRKAEVEN Mask */ + +#define PWM_BRKCTL0_1_BRKAODD_Pos (18) /*!< PWM_T::BRKCTL0_1: BRKAODD Position */ +#define PWM_BRKCTL0_1_BRKAODD_Msk (0x3ul << PWM_BRKCTL0_1_BRKAODD_Pos) /*!< PWM_T::BRKCTL0_1: BRKAODD Mask */ + +#define PWM_BRKCTL2_3_CPO0EBEN_Pos (0) /*!< PWM_T::BRKCTL2_3: CPO0EBEN Position */ +#define PWM_BRKCTL2_3_CPO0EBEN_Msk (0x1ul << PWM_BRKCTL2_3_CPO0EBEN_Pos) /*!< PWM_T::BRKCTL2_3: CPO0EBEN Mask */ + +#define PWM_BRKCTL2_3_CPO1EBEN_Pos (1) /*!< PWM_T::BRKCTL2_3: CPO1EBEN Position */ +#define PWM_BRKCTL2_3_CPO1EBEN_Msk (0x1ul << PWM_BRKCTL2_3_CPO1EBEN_Pos) /*!< PWM_T::BRKCTL2_3: CPO1EBEN Mask */ + +#define PWM_BRKCTL2_3_BRKP0EEN_Pos (4) /*!< PWM_T::BRKCTL2_3: BRKP0EEN Position */ +#define PWM_BRKCTL2_3_BRKP0EEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP0EEN_Pos) /*!< PWM_T::BRKCTL2_3: BRKP0EEN Mask */ + +#define PWM_BRKCTL2_3_BRKP1EEN_Pos (5) /*!< PWM_T::BRKCTL2_3: BRKP1EEN Position */ +#define PWM_BRKCTL2_3_BRKP1EEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP1EEN_Pos) /*!< PWM_T::BRKCTL2_3: BRKP1EEN Mask */ + +#define PWM_BRKCTL2_3_SYSEBEN_Pos (7) /*!< PWM_T::BRKCTL2_3: SYSEBEN Position */ +#define PWM_BRKCTL2_3_SYSEBEN_Msk (0x1ul << PWM_BRKCTL2_3_SYSEBEN_Pos) /*!< PWM_T::BRKCTL2_3: SYSEBEN Mask */ + +#define PWM_BRKCTL2_3_CPO0LBEN_Pos (8) /*!< PWM_T::BRKCTL2_3: CPO0LBEN Position */ +#define PWM_BRKCTL2_3_CPO0LBEN_Msk (0x1ul << PWM_BRKCTL2_3_CPO0LBEN_Pos) /*!< PWM_T::BRKCTL2_3: CPO0LBEN Mask */ + +#define PWM_BRKCTL2_3_CPO1LBEN_Pos (9) /*!< PWM_T::BRKCTL2_3: CPO1LBEN Position */ +#define PWM_BRKCTL2_3_CPO1LBEN_Msk (0x1ul << PWM_BRKCTL2_3_CPO1LBEN_Pos) /*!< PWM_T::BRKCTL2_3: CPO1LBEN Mask */ + +#define PWM_BRKCTL2_3_BRKP0LEN_Pos (12) /*!< PWM_T::BRKCTL2_3: BRKP0LEN Position */ +#define PWM_BRKCTL2_3_BRKP0LEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP0LEN_Pos) /*!< PWM_T::BRKCTL2_3: BRKP0LEN Mask */ + +#define PWM_BRKCTL2_3_BRKP1LEN_Pos (13) /*!< PWM_T::BRKCTL2_3: BRKP1LEN Position */ +#define PWM_BRKCTL2_3_BRKP1LEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP1LEN_Pos) /*!< PWM_T::BRKCTL2_3: BRKP1LEN Mask */ + +#define PWM_BRKCTL2_3_SYSLBEN_Pos (15) /*!< PWM_T::BRKCTL2_3: SYSLBEN Position */ +#define PWM_BRKCTL2_3_SYSLBEN_Msk (0x1ul << PWM_BRKCTL2_3_SYSLBEN_Pos) /*!< PWM_T::BRKCTL2_3: SYSLBEN Mask */ + +#define PWM_BRKCTL2_3_BRKAEVEN_Pos (16) /*!< PWM_T::BRKCTL2_3: BRKAEVEN Position */ +#define PWM_BRKCTL2_3_BRKAEVEN_Msk (0x3ul << PWM_BRKCTL2_3_BRKAEVEN_Pos) /*!< PWM_T::BRKCTL2_3: BRKAEVEN Mask */ + +#define PWM_BRKCTL2_3_BRKAODD_Pos (18) /*!< PWM_T::BRKCTL2_3: BRKAODD Position */ +#define PWM_BRKCTL2_3_BRKAODD_Msk (0x3ul << PWM_BRKCTL2_3_BRKAODD_Pos) /*!< PWM_T::BRKCTL2_3: BRKAODD Mask */ + +#define PWM_BRKCTL4_5_CPO0EBEN_Pos (0) /*!< PWM_T::BRKCTL4_5: CPO0EBEN Position */ +#define PWM_BRKCTL4_5_CPO0EBEN_Msk (0x1ul << PWM_BRKCTL4_5_CPO0EBEN_Pos) /*!< PWM_T::BRKCTL4_5: CPO0EBEN Mask */ + +#define PWM_BRKCTL4_5_CPO1EBEN_Pos (1) /*!< PWM_T::BRKCTL4_5: CPO1EBEN Position */ +#define PWM_BRKCTL4_5_CPO1EBEN_Msk (0x1ul << PWM_BRKCTL4_5_CPO1EBEN_Pos) /*!< PWM_T::BRKCTL4_5: CPO1EBEN Mask */ + +#define PWM_BRKCTL4_5_BRKP0EEN_Pos (4) /*!< PWM_T::BRKCTL4_5: BRKP0EEN Position */ +#define PWM_BRKCTL4_5_BRKP0EEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP0EEN_Pos) /*!< PWM_T::BRKCTL4_5: BRKP0EEN Mask */ + +#define PWM_BRKCTL4_5_BRKP1EEN_Pos (5) /*!< PWM_T::BRKCTL4_5: BRKP1EEN Position */ +#define PWM_BRKCTL4_5_BRKP1EEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP1EEN_Pos) /*!< PWM_T::BRKCTL4_5: BRKP1EEN Mask */ + +#define PWM_BRKCTL4_5_SYSEBEN_Pos (7) /*!< PWM_T::BRKCTL4_5: SYSEBEN Position */ +#define PWM_BRKCTL4_5_SYSEBEN_Msk (0x1ul << PWM_BRKCTL4_5_SYSEBEN_Pos) /*!< PWM_T::BRKCTL4_5: SYSEBEN Mask */ + +#define PWM_BRKCTL4_5_CPO0LBEN_Pos (8) /*!< PWM_T::BRKCTL4_5: CPO0LBEN Position */ +#define PWM_BRKCTL4_5_CPO0LBEN_Msk (0x1ul << PWM_BRKCTL4_5_CPO0LBEN_Pos) /*!< PWM_T::BRKCTL4_5: CPO0LBEN Mask */ + +#define PWM_BRKCTL4_5_CPO1LBEN_Pos (9) /*!< PWM_T::BRKCTL4_5: CPO1LBEN Position */ +#define PWM_BRKCTL4_5_CPO1LBEN_Msk (0x1ul << PWM_BRKCTL4_5_CPO1LBEN_Pos) /*!< PWM_T::BRKCTL4_5: CPO1LBEN Mask */ + +#define PWM_BRKCTL4_5_BRKP0LEN_Pos (12) /*!< PWM_T::BRKCTL4_5: BRKP0LEN Position */ +#define PWM_BRKCTL4_5_BRKP0LEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP0LEN_Pos) /*!< PWM_T::BRKCTL4_5: BRKP0LEN Mask */ + +#define PWM_BRKCTL4_5_BRKP1LEN_Pos (13) /*!< PWM_T::BRKCTL4_5: BRKP1LEN Position */ +#define PWM_BRKCTL4_5_BRKP1LEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP1LEN_Pos) /*!< PWM_T::BRKCTL4_5: BRKP1LEN Mask */ + +#define PWM_BRKCTL4_5_SYSLBEN_Pos (15) /*!< PWM_T::BRKCTL4_5: SYSLBEN Position */ +#define PWM_BRKCTL4_5_SYSLBEN_Msk (0x1ul << PWM_BRKCTL4_5_SYSLBEN_Pos) /*!< PWM_T::BRKCTL4_5: SYSLBEN Mask */ + +#define PWM_BRKCTL4_5_BRKAEVEN_Pos (16) /*!< PWM_T::BRKCTL4_5: BRKAEVEN Position */ +#define PWM_BRKCTL4_5_BRKAEVEN_Msk (0x3ul << PWM_BRKCTL4_5_BRKAEVEN_Pos) /*!< PWM_T::BRKCTL4_5: BRKAEVEN Mask */ + +#define PWM_BRKCTL4_5_BRKAODD_Pos (18) /*!< PWM_T::BRKCTL4_5: BRKAODD Position */ +#define PWM_BRKCTL4_5_BRKAODD_Msk (0x3ul << PWM_BRKCTL4_5_BRKAODD_Pos) /*!< PWM_T::BRKCTL4_5: BRKAODD Mask */ + +#define PWM_POLCTL_PINVn_Pos (0) /*!< PWM_T::POLCTL: PINVn Position */ +#define PWM_POLCTL_PINVn_Msk (0x3ful << PWM_POLCTL_PINVn_Pos) /*!< PWM_T::POLCTL: PINVn Mask */ + +#define PWM_POLCTL_PINV0_Pos (0) /*!< PWM_T::POLCTL: PINV0 Position */ +#define PWM_POLCTL_PINV0_Msk (0x1ul << PWM_POLCTL_PINV0_Pos) /*!< PWM_T::POLCTL: PINV0 Mask */ + +#define PWM_POLCTL_PINV1_Pos (1) /*!< PWM_T::POLCTL: PINV1 Position */ +#define PWM_POLCTL_PINV1_Msk (0x1ul << PWM_POLCTL_PINV1_Pos) /*!< PWM_T::POLCTL: PINV1 Mask */ + +#define PWM_POLCTL_PINV2_Pos (2) /*!< PWM_T::POLCTL: PINV2 Position */ +#define PWM_POLCTL_PINV2_Msk (0x1ul << PWM_POLCTL_PINV2_Pos) /*!< PWM_T::POLCTL: PINV2 Mask */ + +#define PWM_POLCTL_PINV3_Pos (3) /*!< PWM_T::POLCTL: PINV3 Position */ +#define PWM_POLCTL_PINV3_Msk (0x1ul << PWM_POLCTL_PINV3_Pos) /*!< PWM_T::POLCTL: PINV3 Mask */ + +#define PWM_POLCTL_PINV4_Pos (4) /*!< PWM_T::POLCTL: PINV4 Position */ +#define PWM_POLCTL_PINV4_Msk (0x1ul << PWM_POLCTL_PINV4_Pos) /*!< PWM_T::POLCTL: PINV4 Mask */ + +#define PWM_POLCTL_PINV5_Pos (5) /*!< PWM_T::POLCTL: PINV5 Position */ +#define PWM_POLCTL_PINV5_Msk (0x1ul << PWM_POLCTL_PINV5_Pos) /*!< PWM_T::POLCTL: PINV5 Mask */ + +#define PWM_POEN_POENn_Pos (0) /*!< PWM_T::POEN: POENn Position */ +#define PWM_POEN_POENn_Msk (0x3ful << PWM_POEN_POENn_Pos) /*!< PWM_T::POEN: POENn Mask */ + +#define PWM_POEN_POEN0_Pos (0) /*!< PWM_T::POEN: POEN0 Position */ +#define PWM_POEN_POEN0_Msk (0x1ul << PWM_POEN_POEN0_Pos) /*!< PWM_T::POEN: POEN0 Mask */ + +#define PWM_POEN_POEN1_Pos (1) /*!< PWM_T::POEN: POEN1 Position */ +#define PWM_POEN_POEN1_Msk (0x1ul << PWM_POEN_POEN1_Pos) /*!< PWM_T::POEN: POEN1 Mask */ + +#define PWM_POEN_POEN2_Pos (2) /*!< PWM_T::POEN: POEN2 Position */ +#define PWM_POEN_POEN2_Msk (0x1ul << PWM_POEN_POEN2_Pos) /*!< PWM_T::POEN: POEN2 Mask */ + +#define PWM_POEN_POEN3_Pos (3) /*!< PWM_T::POEN: POEN3 Position */ +#define PWM_POEN_POEN3_Msk (0x1ul << PWM_POEN_POEN3_Pos) /*!< PWM_T::POEN: POEN3 Mask */ + +#define PWM_POEN_POEN4_Pos (4) /*!< PWM_T::POEN: POEN4 Position */ +#define PWM_POEN_POEN4_Msk (0x1ul << PWM_POEN_POEN4_Pos) /*!< PWM_T::POEN: POEN4 Mask */ + +#define PWM_POEN_POEN5_Pos (5) /*!< PWM_T::POEN: POEN5 Position */ +#define PWM_POEN_POEN5_Msk (0x1ul << PWM_POEN_POEN5_Pos) /*!< PWM_T::POEN: POEN5 Mask */ + +#define PWM_SWBRK_BRKETRGn_Pos (0) /*!< PWM_T::SWBRK: BRKETRGn Position */ +#define PWM_SWBRK_BRKETRGn_Msk (0x7ul << PWM_SWBRK_BRKETRGn_Pos) /*!< PWM_T::SWBRK: BRKETRGn Mask */ + +#define PWM_SWBRK_BRKETRG0_Pos (0) /*!< PWM_T::SWBRK: BRKETRG0 Position */ +#define PWM_SWBRK_BRKETRG0_Msk (0x1ul << PWM_SWBRK_BRKETRG0_Pos) /*!< PWM_T::SWBRK: BRKETRG0 Mask */ + +#define PWM_SWBRK_BRKETRG2_Pos (1) /*!< PWM_T::SWBRK: BRKETRG2 Position */ +#define PWM_SWBRK_BRKETRG2_Msk (0x1ul << PWM_SWBRK_BRKETRG2_Pos) /*!< PWM_T::SWBRK: BRKETRG2 Mask */ + +#define PWM_SWBRK_BRKETRG4_Pos (2) /*!< PWM_T::SWBRK: BRKETRG4 Position */ +#define PWM_SWBRK_BRKETRG4_Msk (0x1ul << PWM_SWBRK_BRKETRG4_Pos) /*!< PWM_T::SWBRK: BRKETRG4 Mask */ + +#define PWM_SWBRK_BRKLTRGn_Pos (8) /*!< PWM_T::SWBRK: BRKLTRGn Position */ +#define PWM_SWBRK_BRKLTRGn_Msk (0x7ul << PWM_SWBRK_BRKLTRGn_Pos) /*!< PWM_T::SWBRK: BRKLTRGn Mask */ + +#define PWM_SWBRK_BRKLTRG0_Pos (8) /*!< PWM_T::SWBRK: BRKLTRG0 Position */ +#define PWM_SWBRK_BRKLTRG0_Msk (0x1ul << PWM_SWBRK_BRKLTRG0_Pos) /*!< PWM_T::SWBRK: BRKLTRG0 Mask */ + +#define PWM_SWBRK_BRKLTRG2_Pos (9) /*!< PWM_T::SWBRK: BRKLTRG2 Position */ +#define PWM_SWBRK_BRKLTRG2_Msk (0x1ul << PWM_SWBRK_BRKLTRG2_Pos) /*!< PWM_T::SWBRK: BRKLTRG2 Mask */ + +#define PWM_SWBRK_BRKLTRG4_Pos (10) /*!< PWM_T::SWBRK: BRKLTRG4 Position */ +#define PWM_SWBRK_BRKLTRG4_Msk (0x1ul << PWM_SWBRK_BRKLTRG4_Pos) /*!< PWM_T::SWBRK: BRKLTRG4 Mask */ + +#define PWM_INTEN0_ZIEN0_Pos (0) /*!< PWM_T::INTEN0: ZIEN0 Position */ +#define PWM_INTEN0_ZIEN0_Msk (0x1ul << PWM_INTEN0_ZIEN0_Pos) /*!< PWM_T::INTEN0: ZIEN0 Mask */ + +#define PWM_INTEN0_ZIEN2_Pos (2) /*!< PWM_T::INTEN0: ZIEN2 Position */ +#define PWM_INTEN0_ZIEN2_Msk (0x1ul << PWM_INTEN0_ZIEN2_Pos) /*!< PWM_T::INTEN0: ZIEN2 Mask */ + +#define PWM_INTEN0_ZIEN4_Pos (4) /*!< PWM_T::INTEN0: ZIEN4 Position */ +#define PWM_INTEN0_ZIEN4_Msk (0x1ul << PWM_INTEN0_ZIEN4_Pos) /*!< PWM_T::INTEN0: ZIEN4 Mask */ + +#define PWM_INTEN0_PIEN0_Pos (8) /*!< PWM_T::INTEN0: PIEN0 Position */ +#define PWM_INTEN0_PIEN0_Msk (0x1ul << PWM_INTEN0_PIEN0_Pos) /*!< PWM_T::INTEN0: PIEN0 Mask */ + +#define PWM_INTEN0_PIEN2_Pos (10) /*!< PWM_T::INTEN0: PIEN2 Position */ +#define PWM_INTEN0_PIEN2_Msk (0x1ul << PWM_INTEN0_PIEN2_Pos) /*!< PWM_T::INTEN0: PIEN2 Mask */ + +#define PWM_INTEN0_PIEN4_Pos (12) /*!< PWM_T::INTEN0: PIEN4 Position */ +#define PWM_INTEN0_PIEN4_Msk (0x1ul << PWM_INTEN0_PIEN4_Pos) /*!< PWM_T::INTEN0: PIEN4 Mask */ + +#define PWM_INTEN0_CMPUIENn_Pos (16) /*!< PWM_T::INTEN0: CMPUIENn Position */ +#define PWM_INTEN0_CMPUIENn_Msk (0x3ful << PWM_INTEN0_CMPUIENn_Pos) /*!< PWM_T::INTEN0: CMPUIENn Mask */ + +#define PWM_INTEN0_CMPUIEN0_Pos (16) /*!< PWM_T::INTEN0: CMPUIEN0 Position */ +#define PWM_INTEN0_CMPUIEN0_Msk (0x1ul << PWM_INTEN0_CMPUIEN0_Pos) /*!< PWM_T::INTEN0: CMPUIEN0 Mask */ + +#define PWM_INTEN0_CMPUIEN1_Pos (17) /*!< PWM_T::INTEN0: CMPUIEN1 Position */ +#define PWM_INTEN0_CMPUIEN1_Msk (0x1ul << PWM_INTEN0_CMPUIEN1_Pos) /*!< PWM_T::INTEN0: CMPUIEN1 Mask */ + +#define PWM_INTEN0_CMPUIEN2_Pos (18) /*!< PWM_T::INTEN0: CMPUIEN2 Position */ +#define PWM_INTEN0_CMPUIEN2_Msk (0x1ul << PWM_INTEN0_CMPUIEN2_Pos) /*!< PWM_T::INTEN0: CMPUIEN2 Mask */ + +#define PWM_INTEN0_CMPUIEN3_Pos (19) /*!< PWM_T::INTEN0: CMPUIEN3 Position */ +#define PWM_INTEN0_CMPUIEN3_Msk (0x1ul << PWM_INTEN0_CMPUIEN3_Pos) /*!< PWM_T::INTEN0: CMPUIEN3 Mask */ + +#define PWM_INTEN0_CMPUIEN4_Pos (20) /*!< PWM_T::INTEN0: CMPUIEN4 Position */ +#define PWM_INTEN0_CMPUIEN4_Msk (0x1ul << PWM_INTEN0_CMPUIEN4_Pos) /*!< PWM_T::INTEN0: CMPUIEN4 Mask */ + +#define PWM_INTEN0_CMPUIEN5_Pos (21) /*!< PWM_T::INTEN0: CMPUIEN5 Position */ +#define PWM_INTEN0_CMPUIEN5_Msk (0x1ul << PWM_INTEN0_CMPUIEN5_Pos) /*!< PWM_T::INTEN0: CMPUIEN5 Mask */ + +#define PWM_INTEN0_CMPDIENn_Pos (24) /*!< PWM_T::INTEN0: CMPDIENn Position */ +#define PWM_INTEN0_CMPDIENn_Msk (0x3ful << PWM_INTEN0_CMPDIENn_Pos) /*!< PWM_T::INTEN0: CMPDIENn Mask */ + +#define PWM_INTEN0_CMPDIEN0_Pos (24) /*!< PWM_T::INTEN0: CMPDIEN0 Position */ +#define PWM_INTEN0_CMPDIEN0_Msk (0x1ul << PWM_INTEN0_CMPDIEN0_Pos) /*!< PWM_T::INTEN0: CMPDIEN0 Mask */ + +#define PWM_INTEN0_CMPDIEN1_Pos (25) /*!< PWM_T::INTEN0: CMPDIEN1 Position */ +#define PWM_INTEN0_CMPDIEN1_Msk (0x1ul << PWM_INTEN0_CMPDIEN1_Pos) /*!< PWM_T::INTEN0: CMPDIEN1 Mask */ + +#define PWM_INTEN0_CMPDIEN2_Pos (26) /*!< PWM_T::INTEN0: CMPDIEN2 Position */ +#define PWM_INTEN0_CMPDIEN2_Msk (0x1ul << PWM_INTEN0_CMPDIEN2_Pos) /*!< PWM_T::INTEN0: CMPDIEN2 Mask */ + +#define PWM_INTEN0_CMPDIEN3_Pos (27) /*!< PWM_T::INTEN0: CMPDIEN3 Position */ +#define PWM_INTEN0_CMPDIEN3_Msk (0x1ul << PWM_INTEN0_CMPDIEN3_Pos) /*!< PWM_T::INTEN0: CMPDIEN3 Mask */ + +#define PWM_INTEN0_CMPDIEN4_Pos (28) /*!< PWM_T::INTEN0: CMPDIEN4 Position */ +#define PWM_INTEN0_CMPDIEN4_Msk (0x1ul << PWM_INTEN0_CMPDIEN4_Pos) /*!< PWM_T::INTEN0: CMPDIEN4 Mask */ + +#define PWM_INTEN0_CMPDIEN5_Pos (29) /*!< PWM_T::INTEN0: CMPDIEN5 Position */ +#define PWM_INTEN0_CMPDIEN5_Msk (0x1ul << PWM_INTEN0_CMPDIEN5_Pos) /*!< PWM_T::INTEN0: CMPDIEN5 Mask */ + +#define PWM_INTEN1_BRKEIEN0_1_Pos (0) /*!< PWM_T::INTEN1: BRKEIEN0_1 Position */ +#define PWM_INTEN1_BRKEIEN0_1_Msk (0x1ul << PWM_INTEN1_BRKEIEN0_1_Pos) /*!< PWM_T::INTEN1: BRKEIEN0_1 Mask */ + +#define PWM_INTEN1_BRKEIEN2_3_Pos (1) /*!< PWM_T::INTEN1: BRKEIEN2_3 Position */ +#define PWM_INTEN1_BRKEIEN2_3_Msk (0x1ul << PWM_INTEN1_BRKEIEN2_3_Pos) /*!< PWM_T::INTEN1: BRKEIEN2_3 Mask */ + +#define PWM_INTEN1_BRKEIEN4_5_Pos (2) /*!< PWM_T::INTEN1: BRKEIEN4_5 Position */ +#define PWM_INTEN1_BRKEIEN4_5_Msk (0x1ul << PWM_INTEN1_BRKEIEN4_5_Pos) /*!< PWM_T::INTEN1: BRKEIEN4_5 Mask */ + +#define PWM_INTEN1_BRKLIEN0_1_Pos (8) /*!< PWM_T::INTEN1: BRKLIEN0_1 Position */ +#define PWM_INTEN1_BRKLIEN0_1_Msk (0x1ul << PWM_INTEN1_BRKLIEN0_1_Pos) /*!< PWM_T::INTEN1: BRKLIEN0_1 Mask */ + +#define PWM_INTEN1_BRKLIEN2_3_Pos (9) /*!< PWM_T::INTEN1: BRKLIEN2_3 Position */ +#define PWM_INTEN1_BRKLIEN2_3_Msk (0x1ul << PWM_INTEN1_BRKLIEN2_3_Pos) /*!< PWM_T::INTEN1: BRKLIEN2_3 Mask */ + +#define PWM_INTEN1_BRKLIEN4_5_Pos (10) /*!< PWM_T::INTEN1: BRKLIEN4_5 Position */ +#define PWM_INTEN1_BRKLIEN4_5_Msk (0x1ul << PWM_INTEN1_BRKLIEN4_5_Pos) /*!< PWM_T::INTEN1: BRKLIEN4_5 Mask */ + +#define PWM_INTSTS0_ZIF0_Pos (0) /*!< PWM_T::INTSTS0: ZIF0 Position */ +#define PWM_INTSTS0_ZIF0_Msk (0x1ul << PWM_INTSTS0_ZIF0_Pos) /*!< PWM_T::INTSTS0: ZIF0 Mask */ + +#define PWM_INTSTS0_ZIF2_Pos (2) /*!< PWM_T::INTSTS0: ZIF2 Position */ +#define PWM_INTSTS0_ZIF2_Msk (0x1ul << PWM_INTSTS0_ZIF2_Pos) /*!< PWM_T::INTSTS0: ZIF2 Mask */ + +#define PWM_INTSTS0_ZIF4_Pos (4) /*!< PWM_T::INTSTS0: ZIF4 Position */ +#define PWM_INTSTS0_ZIF4_Msk (0x1ul << PWM_INTSTS0_ZIF4_Pos) /*!< PWM_T::INTSTS0: ZIF4 Mask */ + +#define PWM_INTSTS0_PIF0_Pos (8) /*!< PWM_T::INTSTS0: PIF0 Position */ +#define PWM_INTSTS0_PIF0_Msk (0x1ul << PWM_INTSTS0_PIF0_Pos) /*!< PWM_T::INTSTS0: PIF0 Mask */ + +#define PWM_INTSTS0_PIF2_Pos (10) /*!< PWM_T::INTSTS0: PIF2 Position */ +#define PWM_INTSTS0_PIF2_Msk (0x1ul << PWM_INTSTS0_PIF2_Pos) /*!< PWM_T::INTSTS0: PIF2 Mask */ + +#define PWM_INTSTS0_PIF4_Pos (12) /*!< PWM_T::INTSTS0: PIF4 Position */ +#define PWM_INTSTS0_PIF4_Msk (0x1ul << PWM_INTSTS0_PIF4_Pos) /*!< PWM_T::INTSTS0: PIF4 Mask */ + +#define PWM_INTSTS0_CMPUIFn_Pos (16) /*!< PWM_T::INTSTS0: CMPUIFn Position */ +#define PWM_INTSTS0_CMPUIFn_Msk (0x3ful << PWM_INTSTS0_CMPUIFn_Pos) /*!< PWM_T::INTSTS0: CMPUIFn Mask */ + +#define PWM_INTSTS0_CMPUIF0_Pos (16) /*!< PWM_T::INTSTS0: CMPUIF0 Position */ +#define PWM_INTSTS0_CMPUIF0_Msk (0x1ul << PWM_INTSTS0_CMPUIF0_Pos) /*!< PWM_T::INTSTS0: CMPUIF0 Mask */ + +#define PWM_INTSTS0_CMPUIF1_Pos (17) /*!< PWM_T::INTSTS0: CMPUIF1 Position */ +#define PWM_INTSTS0_CMPUIF1_Msk (0x1ul << PWM_INTSTS0_CMPUIF1_Pos) /*!< PWM_T::INTSTS0: CMPUIF1 Mask */ + +#define PWM_INTSTS0_CMPUIF2_Pos (18) /*!< PWM_T::INTSTS0: CMPUIF2 Position */ +#define PWM_INTSTS0_CMPUIF2_Msk (0x1ul << PWM_INTSTS0_CMPUIF2_Pos) /*!< PWM_T::INTSTS0: CMPUIF2 Mask */ + +#define PWM_INTSTS0_CMPUIF3_Pos (19) /*!< PWM_T::INTSTS0: CMPUIF3 Position */ +#define PWM_INTSTS0_CMPUIF3_Msk (0x1ul << PWM_INTSTS0_CMPUIF3_Pos) /*!< PWM_T::INTSTS0: CMPUIF3 Mask */ + +#define PWM_INTSTS0_CMPUIF4_Pos (20) /*!< PWM_T::INTSTS0: CMPUIF4 Position */ +#define PWM_INTSTS0_CMPUIF4_Msk (0x1ul << PWM_INTSTS0_CMPUIF4_Pos) /*!< PWM_T::INTSTS0: CMPUIF4 Mask */ + +#define PWM_INTSTS0_CMPUIF5_Pos (21) /*!< PWM_T::INTSTS0: CMPUIF5 Position */ +#define PWM_INTSTS0_CMPUIF5_Msk (0x1ul << PWM_INTSTS0_CMPUIF5_Pos) /*!< PWM_T::INTSTS0: CMPUIF5 Mask */ + +#define PWM_INTSTS0_CMPDIFn_Pos (24) /*!< PWM_T::INTSTS0: CMPDIFn Position */ +#define PWM_INTSTS0_CMPDIFn_Msk (0x3ful << PWM_INTSTS0_CMPDIFn_Pos) /*!< PWM_T::INTSTS0: CMPDIFn Mask */ + +#define PWM_INTSTS0_CMPDIF0_Pos (24) /*!< PWM_T::INTSTS0: CMPDIF0 Position */ +#define PWM_INTSTS0_CMPDIF0_Msk (0x1ul << PWM_INTSTS0_CMPDIF0_Pos) /*!< PWM_T::INTSTS0: CMPDIF0 Mask */ + +#define PWM_INTSTS0_CMPDIF1_Pos (25) /*!< PWM_T::INTSTS0: CMPDIF1 Position */ +#define PWM_INTSTS0_CMPDIF1_Msk (0x1ul << PWM_INTSTS0_CMPDIF1_Pos) /*!< PWM_T::INTSTS0: CMPDIF1 Mask */ + +#define PWM_INTSTS0_CMPDIF2_Pos (26) /*!< PWM_T::INTSTS0: CMPDIF2 Position */ +#define PWM_INTSTS0_CMPDIF2_Msk (0x1ul << PWM_INTSTS0_CMPDIF2_Pos) /*!< PWM_T::INTSTS0: CMPDIF2 Mask */ + +#define PWM_INTSTS0_CMPDIF3_Pos (27) /*!< PWM_T::INTSTS0: CMPDIF3 Position */ +#define PWM_INTSTS0_CMPDIF3_Msk (0x1ul << PWM_INTSTS0_CMPDIF3_Pos) /*!< PWM_T::INTSTS0: CMPDIF3 Mask */ + +#define PWM_INTSTS0_CMPDIF4_Pos (28) /*!< PWM_T::INTSTS0: CMPDIF4 Position */ +#define PWM_INTSTS0_CMPDIF4_Msk (0x1ul << PWM_INTSTS0_CMPDIF4_Pos) /*!< PWM_T::INTSTS0: CMPDIF4 Mask */ + +#define PWM_INTSTS0_CMPDIF5_Pos (29) /*!< PWM_T::INTSTS0: CMPDIF5 Position */ +#define PWM_INTSTS0_CMPDIF5_Msk (0x1ul << PWM_INTSTS0_CMPDIF5_Pos) /*!< PWM_T::INTSTS0: CMPDIF5 Mask */ + +#define PWM_INTSTS1_BRKEIF0_Pos (0) /*!< PWM_T::INTSTS1: BRKEIF0 Position */ +#define PWM_INTSTS1_BRKEIF0_Msk (0x1ul << PWM_INTSTS1_BRKEIF0_Pos) /*!< PWM_T::INTSTS1: BRKEIF0 Mask */ + +#define PWM_INTSTS1_BRKEIF1_Pos (1) /*!< PWM_T::INTSTS1: BRKEIF1 Position */ +#define PWM_INTSTS1_BRKEIF1_Msk (0x1ul << PWM_INTSTS1_BRKEIF1_Pos) /*!< PWM_T::INTSTS1: BRKEIF1 Mask */ + +#define PWM_INTSTS1_BRKEIF2_Pos (2) /*!< PWM_T::INTSTS1: BRKEIF2 Position */ +#define PWM_INTSTS1_BRKEIF2_Msk (0x1ul << PWM_INTSTS1_BRKEIF2_Pos) /*!< PWM_T::INTSTS1: BRKEIF2 Mask */ + +#define PWM_INTSTS1_BRKEIF3_Pos (3) /*!< PWM_T::INTSTS1: BRKEIF3 Position */ +#define PWM_INTSTS1_BRKEIF3_Msk (0x1ul << PWM_INTSTS1_BRKEIF3_Pos) /*!< PWM_T::INTSTS1: BRKEIF3 Mask */ + +#define PWM_INTSTS1_BRKEIF4_Pos (4) /*!< PWM_T::INTSTS1: BRKEIF4 Position */ +#define PWM_INTSTS1_BRKEIF4_Msk (0x1ul << PWM_INTSTS1_BRKEIF4_Pos) /*!< PWM_T::INTSTS1: BRKEIF4 Mask */ + +#define PWM_INTSTS1_BRKEIF5_Pos (5) /*!< PWM_T::INTSTS1: BRKEIF5 Position */ +#define PWM_INTSTS1_BRKEIF5_Msk (0x1ul << PWM_INTSTS1_BRKEIF5_Pos) /*!< PWM_T::INTSTS1: BRKEIF5 Mask */ + +#define PWM_INTSTS1_BRKLIF0_Pos (8) /*!< PWM_T::INTSTS1: BRKLIF0 Position */ +#define PWM_INTSTS1_BRKLIF0_Msk (0x1ul << PWM_INTSTS1_BRKLIF0_Pos) /*!< PWM_T::INTSTS1: BRKLIF0 Mask */ + +#define PWM_INTSTS1_BRKLIF1_Pos (9) /*!< PWM_T::INTSTS1: BRKLIF1 Position */ +#define PWM_INTSTS1_BRKLIF1_Msk (0x1ul << PWM_INTSTS1_BRKLIF1_Pos) /*!< PWM_T::INTSTS1: BRKLIF1 Mask */ + +#define PWM_INTSTS1_BRKLIF2_Pos (10) /*!< PWM_T::INTSTS1: BRKLIF2 Position */ +#define PWM_INTSTS1_BRKLIF2_Msk (0x1ul << PWM_INTSTS1_BRKLIF2_Pos) /*!< PWM_T::INTSTS1: BRKLIF2 Mask */ + +#define PWM_INTSTS1_BRKLIF3_Pos (11) /*!< PWM_T::INTSTS1: BRKLIF3 Position */ +#define PWM_INTSTS1_BRKLIF3_Msk (0x1ul << PWM_INTSTS1_BRKLIF3_Pos) /*!< PWM_T::INTSTS1: BRKLIF3 Mask */ + +#define PWM_INTSTS1_BRKLIF4_Pos (12) /*!< PWM_T::INTSTS1: BRKLIF4 Position */ +#define PWM_INTSTS1_BRKLIF4_Msk (0x1ul << PWM_INTSTS1_BRKLIF4_Pos) /*!< PWM_T::INTSTS1: BRKLIF4 Mask */ + +#define PWM_INTSTS1_BRKLIF5_Pos (13) /*!< PWM_T::INTSTS1: BRKLIF5 Position */ +#define PWM_INTSTS1_BRKLIF5_Msk (0x1ul << PWM_INTSTS1_BRKLIF5_Pos) /*!< PWM_T::INTSTS1: BRKLIF5 Mask */ + +#define PWM_INTSTS1_BRKESTS0_Pos (16) /*!< PWM_T::INTSTS1: BRKESTS0 Position */ +#define PWM_INTSTS1_BRKESTS0_Msk (0x1ul << PWM_INTSTS1_BRKESTS0_Pos) /*!< PWM_T::INTSTS1: BRKESTS0 Mask */ + +#define PWM_INTSTS1_BRKESTS1_Pos (17) /*!< PWM_T::INTSTS1: BRKESTS1 Position */ +#define PWM_INTSTS1_BRKESTS1_Msk (0x1ul << PWM_INTSTS1_BRKESTS1_Pos) /*!< PWM_T::INTSTS1: BRKESTS1 Mask */ + +#define PWM_INTSTS1_BRKESTS2_Pos (18) /*!< PWM_T::INTSTS1: BRKESTS2 Position */ +#define PWM_INTSTS1_BRKESTS2_Msk (0x1ul << PWM_INTSTS1_BRKESTS2_Pos) /*!< PWM_T::INTSTS1: BRKESTS2 Mask */ + +#define PWM_INTSTS1_BRKESTS3_Pos (19) /*!< PWM_T::INTSTS1: BRKESTS3 Position */ +#define PWM_INTSTS1_BRKESTS3_Msk (0x1ul << PWM_INTSTS1_BRKESTS3_Pos) /*!< PWM_T::INTSTS1: BRKESTS3 Mask */ + +#define PWM_INTSTS1_BRKESTS4_Pos (20) /*!< PWM_T::INTSTS1: BRKESTS4 Position */ +#define PWM_INTSTS1_BRKESTS4_Msk (0x1ul << PWM_INTSTS1_BRKESTS4_Pos) /*!< PWM_T::INTSTS1: BRKESTS4 Mask */ + +#define PWM_INTSTS1_BRKESTS5_Pos (21) /*!< PWM_T::INTSTS1: BRKESTS5 Position */ +#define PWM_INTSTS1_BRKESTS5_Msk (0x1ul << PWM_INTSTS1_BRKESTS5_Pos) /*!< PWM_T::INTSTS1: BRKESTS5 Mask */ + +#define PWM_INTSTS1_BRKLSTS0_Pos (24) /*!< PWM_T::INTSTS1: BRKLSTS0 Position */ +#define PWM_INTSTS1_BRKLSTS0_Msk (0x1ul << PWM_INTSTS1_BRKLSTS0_Pos) /*!< PWM_T::INTSTS1: BRKLSTS0 Mask */ + +#define PWM_INTSTS1_BRKLSTS1_Pos (25) /*!< PWM_T::INTSTS1: BRKLSTS1 Position */ +#define PWM_INTSTS1_BRKLSTS1_Msk (0x1ul << PWM_INTSTS1_BRKLSTS1_Pos) /*!< PWM_T::INTSTS1: BRKLSTS1 Mask */ + +#define PWM_INTSTS1_BRKLSTS2_Pos (26) /*!< PWM_T::INTSTS1: BRKLSTS2 Position */ +#define PWM_INTSTS1_BRKLSTS2_Msk (0x1ul << PWM_INTSTS1_BRKLSTS2_Pos) /*!< PWM_T::INTSTS1: BRKLSTS2 Mask */ + +#define PWM_INTSTS1_BRKLSTS3_Pos (27) /*!< PWM_T::INTSTS1: BRKLSTS3 Position */ +#define PWM_INTSTS1_BRKLSTS3_Msk (0x1ul << PWM_INTSTS1_BRKLSTS3_Pos) /*!< PWM_T::INTSTS1: BRKLSTS3 Mask */ + +#define PWM_INTSTS1_BRKLSTS4_Pos (28) /*!< PWM_T::INTSTS1: BRKLSTS4 Position */ +#define PWM_INTSTS1_BRKLSTS4_Msk (0x1ul << PWM_INTSTS1_BRKLSTS4_Pos) /*!< PWM_T::INTSTS1: BRKLSTS4 Mask */ + +#define PWM_INTSTS1_BRKLSTS5_Pos (29) /*!< PWM_T::INTSTS1: BRKLSTS5 Position */ +#define PWM_INTSTS1_BRKLSTS5_Msk (0x1ul << PWM_INTSTS1_BRKLSTS5_Pos) /*!< PWM_T::INTSTS1: BRKLSTS5 Mask */ + +#define PWM_EADCTS0_TRGSEL0_Pos (0) /*!< PWM_T::EADCTS0: TRGSEL0 Position */ +#define PWM_EADCTS0_TRGSEL0_Msk (0xful << PWM_EADCTS0_TRGSEL0_Pos) /*!< PWM_T::EADCTS0: TRGSEL0 Mask */ + +#define PWM_EADCTS0_TRGEN0_Pos (7) /*!< PWM_T::EADCTS0: TRGEN0 Position */ +#define PWM_EADCTS0_TRGEN0_Msk (0x1ul << PWM_EADCTS0_TRGEN0_Pos) /*!< PWM_T::EADCTS0: TRGEN0 Mask */ + +#define PWM_EADCTS0_TRGSEL1_Pos (8) /*!< PWM_T::EADCTS0: TRGSEL1 Position */ +#define PWM_EADCTS0_TRGSEL1_Msk (0xful << PWM_EADCTS0_TRGSEL1_Pos) /*!< PWM_T::EADCTS0: TRGSEL1 Mask */ + +#define PWM_EADCTS0_TRGEN1_Pos (15) /*!< PWM_T::EADCTS0: TRGEN1 Position */ +#define PWM_EADCTS0_TRGEN1_Msk (0x1ul << PWM_EADCTS0_TRGEN1_Pos) /*!< PWM_T::EADCTS0: TRGEN1 Mask */ + +#define PWM_EADCTS0_TRGSEL2_Pos (16) /*!< PWM_T::EADCTS0: TRGSEL2 Position */ +#define PWM_EADCTS0_TRGSEL2_Msk (0xful << PWM_EADCTS0_TRGSEL2_Pos) /*!< PWM_T::EADCTS0: TRGSEL2 Mask */ + +#define PWM_EADCTS0_TRGEN2_Pos (23) /*!< PWM_T::EADCTS0: TRGEN2 Position */ +#define PWM_EADCTS0_TRGEN2_Msk (0x1ul << PWM_EADCTS0_TRGEN2_Pos) /*!< PWM_T::EADCTS0: TRGEN2 Mask */ + +#define PWM_EADCTS0_TRGSEL3_Pos (24) /*!< PWM_T::EADCTS0: TRGSEL3 Position */ +#define PWM_EADCTS0_TRGSEL3_Msk (0xful << PWM_EADCTS0_TRGSEL3_Pos) /*!< PWM_T::EADCTS0: TRGSEL3 Mask */ + +#define PWM_EADCTS0_TRGEN3_Pos (31) /*!< PWM_T::EADCTS0: TRGEN3 Position */ +#define PWM_EADCTS0_TRGEN3_Msk (0x1ul << PWM_EADCTS0_TRGEN3_Pos) /*!< PWM_T::EADCTS0: TRGEN3 Mask */ + +#define PWM_EADCTS1_TRGSEL4_Pos (0) /*!< PWM_T::EADCTS1: TRGSEL4 Position */ +#define PWM_EADCTS1_TRGSEL4_Msk (0xful << PWM_EADCTS1_TRGSEL4_Pos) /*!< PWM_T::EADCTS1: TRGSEL4 Mask */ + +#define PWM_EADCTS1_TRGEN4_Pos (7) /*!< PWM_T::EADCTS1: TRGEN4 Position */ +#define PWM_EADCTS1_TRGEN4_Msk (0x1ul << PWM_EADCTS1_TRGEN4_Pos) /*!< PWM_T::EADCTS1: TRGEN4 Mask */ + +#define PWM_EADCTS1_TRGSEL5_Pos (8) /*!< PWM_T::EADCTS1: TRGSEL5 Position */ +#define PWM_EADCTS1_TRGSEL5_Msk (0xful << PWM_EADCTS1_TRGSEL5_Pos) /*!< PWM_T::EADCTS1: TRGSEL5 Mask */ + +#define PWM_EADCTS1_TRGEN5_Pos (15) /*!< PWM_T::EADCTS1: TRGEN5 Position */ +#define PWM_EADCTS1_TRGEN5_Msk (0x1ul << PWM_EADCTS1_TRGEN5_Pos) /*!< PWM_T::EADCTS1: TRGEN5 Mask */ + +#define PWM_SSCTL_SSEN0_Pos (0) /*!< PWM_T::SSCTL: SSEN0 Position */ +#define PWM_SSCTL_SSEN0_Msk (0x1ul << PWM_SSCTL_SSEN0_Pos) /*!< PWM_T::SSCTL: SSEN0 Mask */ + +#define PWM_SSCTL_SSEN2_Pos (2) /*!< PWM_T::SSCTL: SSEN2 Position */ +#define PWM_SSCTL_SSEN2_Msk (0x1ul << PWM_SSCTL_SSEN2_Pos) /*!< PWM_T::SSCTL: SSEN2 Mask */ + +#define PWM_SSCTL_SSEN4_Pos (4) /*!< PWM_T::SSCTL: SSEN4 Position */ +#define PWM_SSCTL_SSEN4_Msk (0x1ul << PWM_SSCTL_SSEN4_Pos) /*!< PWM_T::SSCTL: SSEN4 Mask */ + +#define PWM_SSCTL_SSRC_Pos (8) /*!< PWM_T::SSCTL: SSRC Position */ +#define PWM_SSCTL_SSRC_Msk (0x3ul << PWM_SSCTL_SSRC_Pos) /*!< PWM_T::SSCTL: SSRC Mask */ + +#define PWM_SSTRG_CNTSEN_Pos (0) /*!< PWM_T::SSTRG: CNTSEN Position */ +#define PWM_SSTRG_CNTSEN_Msk (0x1ul << PWM_SSTRG_CNTSEN_Pos) /*!< PWM_T::SSTRG: CNTSEN Mask */ + +#define PWM_STATUS_CNTMAX0_Pos (0) /*!< PWM_T::STATUS: CNTMAX0 Position */ +#define PWM_STATUS_CNTMAX0_Msk (0x1ul << PWM_STATUS_CNTMAX0_Pos) /*!< PWM_T::STATUS: CNTMAX0 Mask */ + +#define PWM_STATUS_CNTMAX2_Pos (2) /*!< PWM_T::STATUS: CNTMAX2 Position */ +#define PWM_STATUS_CNTMAX2_Msk (0x1ul << PWM_STATUS_CNTMAX2_Pos) /*!< PWM_T::STATUS: CNTMAX2 Mask */ + +#define PWM_STATUS_CNTMAX4_Pos (4) /*!< PWM_T::STATUS: CNTMAX4 Position */ +#define PWM_STATUS_CNTMAX4_Msk (0x1ul << PWM_STATUS_CNTMAX4_Pos) /*!< PWM_T::STATUS: CNTMAX4 Mask */ + +#define PWM_STATUS_EADCTRGn_Pos (16) /*!< PWM_T::STATUS: EADCTRGn Position */ +#define PWM_STATUS_EADCTRGn_Msk (0x3ful << PWM_STATUS_EADCTRGn_Pos) /*!< PWM_T::STATUS: EADCTRGn Mask */ + +#define PWM_STATUS_EADCTRG0_Pos (16) /*!< PWM_T::STATUS: EADCTRG0 Position */ +#define PWM_STATUS_EADCTRG0_Msk (0x1ul << PWM_STATUS_EADCTRG0_Pos) /*!< PWM_T::STATUS: EADCTRG0 Mask */ + +#define PWM_STATUS_EADCTRG1_Pos (17) /*!< PWM_T::STATUS: EADCTRG1 Position */ +#define PWM_STATUS_EADCTRG1_Msk (0x1ul << PWM_STATUS_EADCTRG1_Pos) /*!< PWM_T::STATUS: EADCTRG1 Mask */ + +#define PWM_STATUS_EADCTRG2_Pos (18) /*!< PWM_T::STATUS: EADCTRG2 Position */ +#define PWM_STATUS_EADCTRG2_Msk (0x1ul << PWM_STATUS_EADCTRG2_Pos) /*!< PWM_T::STATUS: EADCTRG2 Mask */ + +#define PWM_STATUS_EADCTRG3_Pos (19) /*!< PWM_T::STATUS: EADCTRG3 Position */ +#define PWM_STATUS_EADCTRG3_Msk (0x1ul << PWM_STATUS_EADCTRG3_Pos) /*!< PWM_T::STATUS: EADCTRG3 Mask */ + +#define PWM_STATUS_EADCTRG4_Pos (20) /*!< PWM_T::STATUS: EADCTRG4 Position */ +#define PWM_STATUS_EADCTRG4_Msk (0x1ul << PWM_STATUS_EADCTRG4_Pos) /*!< PWM_T::STATUS: EADCTRG4 Mask */ + +#define PWM_STATUS_EADCTRG5_Pos (21) /*!< PWM_T::STATUS: EADCTRG5 Position */ +#define PWM_STATUS_EADCTRG5_Msk (0x1ul << PWM_STATUS_EADCTRG5_Pos) /*!< PWM_T::STATUS: EADCTRG5 Mask */ + +#define PWM_CAPINEN_CAPINENn_Pos (0) /*!< PWM_T::CAPINEN: CAPINENn Position */ +#define PWM_CAPINEN_CAPINENn_Msk (0x3ful << PWM_CAPINEN_CAPINENn_Pos) /*!< PWM_T::CAPINEN: CAPINENn Mask */ + +#define PWM_CAPINEN_CAPINEN0_Pos (0) /*!< PWM_T::CAPINEN: CAPINEN0 Position */ +#define PWM_CAPINEN_CAPINEN0_Msk (0x1ul << PWM_CAPINEN_CAPINEN0_Pos) /*!< PWM_T::CAPINEN: CAPINEN0 Mask */ + +#define PWM_CAPINEN_CAPINEN1_Pos (1) /*!< PWM_T::CAPINEN: CAPINEN1 Position */ +#define PWM_CAPINEN_CAPINEN1_Msk (0x1ul << PWM_CAPINEN_CAPINEN1_Pos) /*!< PWM_T::CAPINEN: CAPINEN1 Mask */ + +#define PWM_CAPINEN_CAPINEN2_Pos (2) /*!< PWM_T::CAPINEN: CAPINEN2 Position */ +#define PWM_CAPINEN_CAPINEN2_Msk (0x1ul << PWM_CAPINEN_CAPINEN2_Pos) /*!< PWM_T::CAPINEN: CAPINEN2 Mask */ + +#define PWM_CAPINEN_CAPINEN3_Pos (3) /*!< PWM_T::CAPINEN: CAPINEN3 Position */ +#define PWM_CAPINEN_CAPINEN3_Msk (0x1ul << PWM_CAPINEN_CAPINEN3_Pos) /*!< PWM_T::CAPINEN: CAPINEN3 Mask */ + +#define PWM_CAPINEN_CAPINEN4_Pos (4) /*!< PWM_T::CAPINEN: CAPINEN4 Position */ +#define PWM_CAPINEN_CAPINEN4_Msk (0x1ul << PWM_CAPINEN_CAPINEN4_Pos) /*!< PWM_T::CAPINEN: CAPINEN4 Mask */ + +#define PWM_CAPINEN_CAPINEN5_Pos (5) /*!< PWM_T::CAPINEN: CAPINEN5 Position */ +#define PWM_CAPINEN_CAPINEN5_Msk (0x1ul << PWM_CAPINEN_CAPINEN5_Pos) /*!< PWM_T::CAPINEN: CAPINEN5 Mask */ + +#define PWM_CAPCTL_CAPENn_Pos (0) /*!< PWM_T::CAPCTL: CAPENn Position */ +#define PWM_CAPCTL_CAPENn_Msk (0x3ful << PWM_CAPCTL_CAPENn_Pos) /*!< PWM_T::CAPCTL: CAPENn Mask */ + +#define PWM_CAPCTL_CAPEN0_Pos (0) /*!< PWM_T::CAPCTL: CAPEN0 Position */ +#define PWM_CAPCTL_CAPEN0_Msk (0x1ul << PWM_CAPCTL_CAPEN0_Pos) /*!< PWM_T::CAPCTL: CAPEN0 Mask */ + +#define PWM_CAPCTL_CAPEN1_Pos (1) /*!< PWM_T::CAPCTL: CAPEN1 Position */ +#define PWM_CAPCTL_CAPEN1_Msk (0x1ul << PWM_CAPCTL_CAPEN1_Pos) /*!< PWM_T::CAPCTL: CAPEN1 Mask */ + +#define PWM_CAPCTL_CAPEN2_Pos (2) /*!< PWM_T::CAPCTL: CAPEN2 Position */ +#define PWM_CAPCTL_CAPEN2_Msk (0x1ul << PWM_CAPCTL_CAPEN2_Pos) /*!< PWM_T::CAPCTL: CAPEN2 Mask */ + +#define PWM_CAPCTL_CAPEN3_Pos (3) /*!< PWM_T::CAPCTL: CAPEN3 Position */ +#define PWM_CAPCTL_CAPEN3_Msk (0x1ul << PWM_CAPCTL_CAPEN3_Pos) /*!< PWM_T::CAPCTL: CAPEN3 Mask */ + +#define PWM_CAPCTL_CAPEN4_Pos (4) /*!< PWM_T::CAPCTL: CAPEN4 Position */ +#define PWM_CAPCTL_CAPEN4_Msk (0x1ul << PWM_CAPCTL_CAPEN4_Pos) /*!< PWM_T::CAPCTL: CAPEN4 Mask */ + +#define PWM_CAPCTL_CAPEN5_Pos (5) /*!< PWM_T::CAPCTL: CAPEN5 Position */ +#define PWM_CAPCTL_CAPEN5_Msk (0x1ul << PWM_CAPCTL_CAPEN5_Pos) /*!< PWM_T::CAPCTL: CAPEN5 Mask */ + +#define PWM_CAPCTL_CAPINVn_Pos (8) /*!< PWM_T::CAPCTL: CAPINVn Position */ +#define PWM_CAPCTL_CAPINVn_Msk (0x3ful << PWM_CAPCTL_CAPINVn_Pos) /*!< PWM_T::CAPCTL: CAPINVn Mask */ + +#define PWM_CAPCTL_CAPINV0_Pos (8) /*!< PWM_T::CAPCTL: CAPINV0 Position */ +#define PWM_CAPCTL_CAPINV0_Msk (0x1ul << PWM_CAPCTL_CAPINV0_Pos) /*!< PWM_T::CAPCTL: CAPINV0 Mask */ + +#define PWM_CAPCTL_CAPINV1_Pos (9) /*!< PWM_T::CAPCTL: CAPINV1 Position */ +#define PWM_CAPCTL_CAPINV1_Msk (0x1ul << PWM_CAPCTL_CAPINV1_Pos) /*!< PWM_T::CAPCTL: CAPINV1 Mask */ + +#define PWM_CAPCTL_CAPINV2_Pos (10) /*!< PWM_T::CAPCTL: CAPINV2 Position */ +#define PWM_CAPCTL_CAPINV2_Msk (0x1ul << PWM_CAPCTL_CAPINV2_Pos) /*!< PWM_T::CAPCTL: CAPINV2 Mask */ + +#define PWM_CAPCTL_CAPINV3_Pos (11) /*!< PWM_T::CAPCTL: CAPINV3 Position */ +#define PWM_CAPCTL_CAPINV3_Msk (0x1ul << PWM_CAPCTL_CAPINV3_Pos) /*!< PWM_T::CAPCTL: CAPINV3 Mask */ + +#define PWM_CAPCTL_CAPINV4_Pos (12) /*!< PWM_T::CAPCTL: CAPINV4 Position */ +#define PWM_CAPCTL_CAPINV4_Msk (0x1ul << PWM_CAPCTL_CAPINV4_Pos) /*!< PWM_T::CAPCTL: CAPINV4 Mask */ + +#define PWM_CAPCTL_CAPINV5_Pos (13) /*!< PWM_T::CAPCTL: CAPINV5 Position */ +#define PWM_CAPCTL_CAPINV5_Msk (0x1ul << PWM_CAPCTL_CAPINV5_Pos) /*!< PWM_T::CAPCTL: CAPINV5 Mask */ + +#define PWM_CAPCTL_RCRLDENn_Pos (16) /*!< PWM_T::CAPCTL: RCRLDENn Position */ +#define PWM_CAPCTL_RCRLDENn_Msk (0x3ful << PWM_CAPCTL_RCRLDENn_Pos) /*!< PWM_T::CAPCTL: RCRLDENn Mask */ + +#define PWM_CAPCTL_RCRLDEN0_Pos (16) /*!< PWM_T::CAPCTL: RCRLDEN0 Position */ +#define PWM_CAPCTL_RCRLDEN0_Msk (0x1ul << PWM_CAPCTL_RCRLDEN0_Pos) /*!< PWM_T::CAPCTL: RCRLDEN0 Mask */ + +#define PWM_CAPCTL_RCRLDEN1_Pos (17) /*!< PWM_T::CAPCTL: RCRLDEN1 Position */ +#define PWM_CAPCTL_RCRLDEN1_Msk (0x1ul << PWM_CAPCTL_RCRLDEN1_Pos) /*!< PWM_T::CAPCTL: RCRLDEN1 Mask */ + +#define PWM_CAPCTL_RCRLDEN2_Pos (18) /*!< PWM_T::CAPCTL: RCRLDEN2 Position */ +#define PWM_CAPCTL_RCRLDEN2_Msk (0x1ul << PWM_CAPCTL_RCRLDEN2_Pos) /*!< PWM_T::CAPCTL: RCRLDEN2 Mask */ + +#define PWM_CAPCTL_RCRLDEN3_Pos (19) /*!< PWM_T::CAPCTL: RCRLDEN3 Position */ +#define PWM_CAPCTL_RCRLDEN3_Msk (0x1ul << PWM_CAPCTL_RCRLDEN3_Pos) /*!< PWM_T::CAPCTL: RCRLDEN3 Mask */ + +#define PWM_CAPCTL_RCRLDEN4_Pos (20) /*!< PWM_T::CAPCTL: RCRLDEN4 Position */ +#define PWM_CAPCTL_RCRLDEN4_Msk (0x1ul << PWM_CAPCTL_RCRLDEN4_Pos) /*!< PWM_T::CAPCTL: RCRLDEN4 Mask */ + +#define PWM_CAPCTL_RCRLDEN5_Pos (21) /*!< PWM_T::CAPCTL: RCRLDEN5 Position */ +#define PWM_CAPCTL_RCRLDEN5_Msk (0x1ul << PWM_CAPCTL_RCRLDEN5_Pos) /*!< PWM_T::CAPCTL: RCRLDEN5 Mask */ + +#define PWM_CAPCTL_FCRLDENn_Pos (24) /*!< PWM_T::CAPCTL: FCRLDENn Position */ +#define PWM_CAPCTL_FCRLDENn_Msk (0x3ful << PWM_CAPCTL_FCRLDENn_Pos) /*!< PWM_T::CAPCTL: FCRLDENn Mask */ + +#define PWM_CAPCTL_FCRLDEN0_Pos (24) /*!< PWM_T::CAPCTL: FCRLDEN0 Position */ +#define PWM_CAPCTL_FCRLDEN0_Msk (0x1ul << PWM_CAPCTL_FCRLDEN0_Pos) /*!< PWM_T::CAPCTL: FCRLDEN0 Mask */ + +#define PWM_CAPCTL_FCRLDEN1_Pos (25) /*!< PWM_T::CAPCTL: FCRLDEN1 Position */ +#define PWM_CAPCTL_FCRLDEN1_Msk (0x1ul << PWM_CAPCTL_FCRLDEN1_Pos) /*!< PWM_T::CAPCTL: FCRLDEN1 Mask */ + +#define PWM_CAPCTL_FCRLDEN2_Pos (26) /*!< PWM_T::CAPCTL: FCRLDEN2 Position */ +#define PWM_CAPCTL_FCRLDEN2_Msk (0x1ul << PWM_CAPCTL_FCRLDEN2_Pos) /*!< PWM_T::CAPCTL: FCRLDEN2 Mask */ + +#define PWM_CAPCTL_FCRLDEN3_Pos (27) /*!< PWM_T::CAPCTL: FCRLDEN3 Position */ +#define PWM_CAPCTL_FCRLDEN3_Msk (0x1ul << PWM_CAPCTL_FCRLDEN3_Pos) /*!< PWM_T::CAPCTL: FCRLDEN3 Mask */ + +#define PWM_CAPCTL_FCRLDEN4_Pos (28) /*!< PWM_T::CAPCTL: FCRLDEN4 Position */ +#define PWM_CAPCTL_FCRLDEN4_Msk (0x1ul << PWM_CAPCTL_FCRLDEN4_Pos) /*!< PWM_T::CAPCTL: FCRLDEN4 Mask */ + +#define PWM_CAPCTL_FCRLDEN5_Pos (29) /*!< PWM_T::CAPCTL: FCRLDEN5 Position */ +#define PWM_CAPCTL_FCRLDEN5_Msk (0x1ul << PWM_CAPCTL_FCRLDEN5_Pos) /*!< PWM_T::CAPCTL: FCRLDEN5 Mask */ + +#define PWM_CAPSTS_CRLIFOVn_Pos (0) /*!< PWM_T::CAPSTS: CRLIFOVn Position */ +#define PWM_CAPSTS_CRLIFOVn_Msk (0x3ful << PWM_CAPSTS_CRLIFOVn_Pos) /*!< PWM_T::CAPSTS: CRLIFOVn Mask */ + +#define PWM_CAPSTS_CRLIFOV0_Pos (0) /*!< PWM_T::CAPSTS: CRLIFOV0 Position */ +#define PWM_CAPSTS_CRLIFOV0_Msk (0x1ul << PWM_CAPSTS_CRLIFOV0_Pos) /*!< PWM_T::CAPSTS: CRLIFOV0 Mask */ + +#define PWM_CAPSTS_CRLIFOV1_Pos (1) /*!< PWM_T::CAPSTS: CRLIFOV1 Position */ +#define PWM_CAPSTS_CRLIFOV1_Msk (0x1ul << PWM_CAPSTS_CRLIFOV1_Pos) /*!< PWM_T::CAPSTS: CRLIFOV1 Mask */ + +#define PWM_CAPSTS_CRLIFOV2_Pos (2) /*!< PWM_T::CAPSTS: CRLIFOV2 Position */ +#define PWM_CAPSTS_CRLIFOV2_Msk (0x1ul << PWM_CAPSTS_CRLIFOV2_Pos) /*!< PWM_T::CAPSTS: CRLIFOV2 Mask */ + +#define PWM_CAPSTS_CRLIFOV3_Pos (3) /*!< PWM_T::CAPSTS: CRLIFOV3 Position */ +#define PWM_CAPSTS_CRLIFOV3_Msk (0x1ul << PWM_CAPSTS_CRLIFOV3_Pos) /*!< PWM_T::CAPSTS: CRLIFOV3 Mask */ + +#define PWM_CAPSTS_CRLIFOV4_Pos (4) /*!< PWM_T::CAPSTS: CRLIFOV4 Position */ +#define PWM_CAPSTS_CRLIFOV4_Msk (0x1ul << PWM_CAPSTS_CRLIFOV4_Pos) /*!< PWM_T::CAPSTS: CRLIFOV4 Mask */ + +#define PWM_CAPSTS_CRLIFOV5_Pos (5) /*!< PWM_T::CAPSTS: CRLIFOV5 Position */ +#define PWM_CAPSTS_CRLIFOV5_Msk (0x1ul << PWM_CAPSTS_CRLIFOV5_Pos) /*!< PWM_T::CAPSTS: CRLIFOV5 Mask */ + +#define PWM_CAPSTS_CFLIFOVn_Pos (8) /*!< PWM_T::CAPSTS: CFLIFOVn Position */ +#define PWM_CAPSTS_CFLIFOVn_Msk (0x3ful << PWM_CAPSTS_CFLIFOVn_Pos) /*!< PWM_T::CAPSTS: CFLIFOVn Mask */ + +#define PWM_CAPSTS_CFLIFOV0_Pos (8) /*!< PWM_T::CAPSTS: CFLIFOV0 Position */ +#define PWM_CAPSTS_CFLIFOV0_Msk (0x1ul << PWM_CAPSTS_CFLIFOV0_Pos) /*!< PWM_T::CAPSTS: CFLIFOV0 Mask */ + +#define PWM_CAPSTS_CFLIFOV1_Pos (9) /*!< PWM_T::CAPSTS: CFLIFOV1 Position */ +#define PWM_CAPSTS_CFLIFOV1_Msk (0x1ul << PWM_CAPSTS_CFLIFOV1_Pos) /*!< PWM_T::CAPSTS: CFLIFOV1 Mask */ + +#define PWM_CAPSTS_CFLIFOV2_Pos (10) /*!< PWM_T::CAPSTS: CFLIFOV2 Position */ +#define PWM_CAPSTS_CFLIFOV2_Msk (0x1ul << PWM_CAPSTS_CFLIFOV2_Pos) /*!< PWM_T::CAPSTS: CFLIFOV2 Mask */ + +#define PWM_CAPSTS_CFLIFOV3_Pos (11) /*!< PWM_T::CAPSTS: CFLIFOV3 Position */ +#define PWM_CAPSTS_CFLIFOV3_Msk (0x1ul << PWM_CAPSTS_CFLIFOV3_Pos) /*!< PWM_T::CAPSTS: CFLIFOV3 Mask */ + +#define PWM_CAPSTS_CFLIFOV4_Pos (12) /*!< PWM_T::CAPSTS: CFLIFOV4 Position */ +#define PWM_CAPSTS_CFLIFOV4_Msk (0x1ul << PWM_CAPSTS_CFLIFOV4_Pos) /*!< PWM_T::CAPSTS: CFLIFOV4 Mask */ + +#define PWM_CAPSTS_CFLIFOV5_Pos (13) /*!< PWM_T::CAPSTS: CFLIFOV5 Position */ +#define PWM_CAPSTS_CFLIFOV5_Msk (0x1ul << PWM_CAPSTS_CFLIFOV5_Pos) /*!< PWM_T::CAPSTS: CFLIFOV5 Mask */ + +#define PWM_RCAPDAT_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT0: RCAPDAT Position */ +#define PWM_RCAPDAT_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT0: RCAPDAT Mask */ + +#define PWM_FCAPDAT_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT0: FCAPDAT Position */ +#define PWM_FCAPDAT_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT0: FCAPDAT Mask */ + +#define PWM_RCAPDAT0_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT0: RCAPDAT Position */ +#define PWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT0_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT0: RCAPDAT Mask */ + +#define PWM_FCAPDAT0_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT0: FCAPDAT Position */ +#define PWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT0_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT0: FCAPDAT Mask */ + +#define PWM_RCAPDAT1_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT1: RCAPDAT Position */ +#define PWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT1_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT1: RCAPDAT Mask */ + +#define PWM_FCAPDAT1_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT1: FCAPDAT Position */ +#define PWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT1_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT1: FCAPDAT Mask */ + +#define PWM_RCAPDAT2_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT2: RCAPDAT Position */ +#define PWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT2_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT2: RCAPDAT Mask */ + +#define PWM_FCAPDAT2_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT2: FCAPDAT Position */ +#define PWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT2_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT2: FCAPDAT Mask */ + +#define PWM_RCAPDAT3_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT3: RCAPDAT Position */ +#define PWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT3_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT3: RCAPDAT Mask */ + +#define PWM_FCAPDAT3_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT3: FCAPDAT Position */ +#define PWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT3_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT3: FCAPDAT Mask */ + +#define PWM_RCAPDAT4_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT4: RCAPDAT Position */ +#define PWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT4_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT4: RCAPDAT Mask */ + +#define PWM_FCAPDAT4_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT4: FCAPDAT Position */ +#define PWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT4_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT4: FCAPDAT Mask */ + +#define PWM_RCAPDAT5_RCAPDAT_Pos (0) /*!< PWM_T::RCAPDAT5: RCAPDAT Position */ +#define PWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT5_RCAPDAT_Pos) /*!< PWM_T::RCAPDAT5: RCAPDAT Mask */ + +#define PWM_FCAPDAT5_FCAPDAT_Pos (0) /*!< PWM_T::FCAPDAT5: FCAPDAT Position */ +#define PWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT5_FCAPDAT_Pos) /*!< PWM_T::FCAPDAT5: FCAPDAT Mask */ + +#define PWM_PDMACTL_CHEN0_1_Pos (0) /*!< PWM_T::PDMACTL: CHEN0_1 Position */ +#define PWM_PDMACTL_CHEN0_1_Msk (0x1ul << PWM_PDMACTL_CHEN0_1_Pos) /*!< PWM_T::PDMACTL: CHEN0_1 Mask */ + +#define PWM_PDMACTL_CAPMOD0_1_Pos (1) /*!< PWM_T::PDMACTL: CAPMOD0_1 Position */ +#define PWM_PDMACTL_CAPMOD0_1_Msk (0x3ul << PWM_PDMACTL_CAPMOD0_1_Pos) /*!< PWM_T::PDMACTL: CAPMOD0_1 Mask */ + +#define PWM_PDMACTL_CAPORD0_1_Pos (3) /*!< PWM_T::PDMACTL: CAPORD0_1 Position */ +#define PWM_PDMACTL_CAPORD0_1_Msk (0x1ul << PWM_PDMACTL_CAPORD0_1_Pos) /*!< PWM_T::PDMACTL: CAPORD0_1 Mask */ + +#define PWM_PDMACTL_CHSEL0_1_Pos (4) /*!< PWM_T::PDMACTL: CHSEL0_1 Position */ +#define PWM_PDMACTL_CHSEL0_1_Msk (0x1ul << PWM_PDMACTL_CHSEL0_1_Pos) /*!< PWM_T::PDMACTL: CHSEL0_1 Mask */ + +#define PWM_PDMACTL_CHEN2_3_Pos (8) /*!< PWM_T::PDMACTL: CHEN2_3 Position */ +#define PWM_PDMACTL_CHEN2_3_Msk (0x1ul << PWM_PDMACTL_CHEN2_3_Pos) /*!< PWM_T::PDMACTL: CHEN2_3 Mask */ + +#define PWM_PDMACTL_CAPMOD2_3_Pos (9) /*!< PWM_T::PDMACTL: CAPMOD2_3 Position */ +#define PWM_PDMACTL_CAPMOD2_3_Msk (0x3ul << PWM_PDMACTL_CAPMOD2_3_Pos) /*!< PWM_T::PDMACTL: CAPMOD2_3 Mask */ + +#define PWM_PDMACTL_CAPORD2_3_Pos (11) /*!< PWM_T::PDMACTL: CAPORD2_3 Position */ +#define PWM_PDMACTL_CAPORD2_3_Msk (0x1ul << PWM_PDMACTL_CAPORD2_3_Pos) /*!< PWM_T::PDMACTL: CAPORD2_3 Mask */ + +#define PWM_PDMACTL_CHSEL2_3_Pos (12) /*!< PWM_T::PDMACTL: CHSEL2_3 Position */ +#define PWM_PDMACTL_CHSEL2_3_Msk (0x1ul << PWM_PDMACTL_CHSEL2_3_Pos) /*!< PWM_T::PDMACTL: CHSEL2_3 Mask */ + +#define PWM_PDMACTL_CHEN4_5_Pos (16) /*!< PWM_T::PDMACTL: CHEN4_5 Position */ +#define PWM_PDMACTL_CHEN4_5_Msk (0x1ul << PWM_PDMACTL_CHEN4_5_Pos) /*!< PWM_T::PDMACTL: CHEN4_5 Mask */ + +#define PWM_PDMACTL_CAPMOD4_5_Pos (17) /*!< PWM_T::PDMACTL: CAPMOD4_5 Position */ +#define PWM_PDMACTL_CAPMOD4_5_Msk (0x3ul << PWM_PDMACTL_CAPMOD4_5_Pos) /*!< PWM_T::PDMACTL: CAPMOD4_5 Mask */ + +#define PWM_PDMACTL_CAPORD4_5_Pos (19) /*!< PWM_T::PDMACTL: CAPORD4_5 Position */ +#define PWM_PDMACTL_CAPORD4_5_Msk (0x1ul << PWM_PDMACTL_CAPORD4_5_Pos) /*!< PWM_T::PDMACTL: CAPORD4_5 Mask */ + +#define PWM_PDMACTL_CHSEL4_5_Pos (20) /*!< PWM_T::PDMACTL: CHSEL4_5 Position */ +#define PWM_PDMACTL_CHSEL4_5_Msk (0x1ul << PWM_PDMACTL_CHSEL4_5_Pos) /*!< PWM_T::PDMACTL: CHSEL4_5 Mask */ + +#define PWM_PDMACAP0_1_CAPBUF_Pos (0) /*!< PWM_T::PDMACAP0_1: CAPBUF Position */ +#define PWM_PDMACAP0_1_CAPBUF_Msk (0xfffful << PWM_PDMACAP0_1_CAPBUF_Pos) /*!< PWM_T::PDMACAP0_1: CAPBUF Mask */ + +#define PWM_PDMACAP2_3_CAPBUF_Pos (0) /*!< PWM_T::PDMACAP2_3: CAPBUF Position */ +#define PWM_PDMACAP2_3_CAPBUF_Msk (0xfffful << PWM_PDMACAP2_3_CAPBUF_Pos) /*!< PWM_T::PDMACAP2_3: CAPBUF Mask */ + +#define PWM_PDMACAP4_5_CAPBUF_Pos (0) /*!< PWM_T::PDMACAP4_5: CAPBUF Position */ +#define PWM_PDMACAP4_5_CAPBUF_Msk (0xfffful << PWM_PDMACAP4_5_CAPBUF_Pos) /*!< PWM_T::PDMACAP4_5: CAPBUF Mask */ + +#define PWM_CAPIEN_CAPRIENn_Pos (0) /*!< PWM_T::CAPIEN: CAPRIENn Position */ +#define PWM_CAPIEN_CAPRIENn_Msk (0x3ful << PWM_CAPIEN_CAPRIENn_Pos) /*!< PWM_T::CAPIEN: CAPRIENn Mask */ + +#define PWM_CAPIEN_CAPRIEN0_Pos (0) /*!< PWM_T::CAPIEN: CAPRIEN0 Position */ +#define PWM_CAPIEN_CAPRIEN0_Msk (0x1ul << PWM_CAPIEN_CAPRIEN0_Pos) /*!< PWM_T::CAPIEN: CAPRIEN0 Mask */ + +#define PWM_CAPIEN_CAPRIEN1_Pos (1) /*!< PWM_T::CAPIEN: CAPRIEN1 Position */ +#define PWM_CAPIEN_CAPRIEN1_Msk (0x1ul << PWM_CAPIEN_CAPRIEN1_Pos) /*!< PWM_T::CAPIEN: CAPRIEN1 Mask */ + +#define PWM_CAPIEN_CAPRIEN2_Pos (2) /*!< PWM_T::CAPIEN: CAPRIEN2 Position */ +#define PWM_CAPIEN_CAPRIEN2_Msk (0x1ul << PWM_CAPIEN_CAPRIEN2_Pos) /*!< PWM_T::CAPIEN: CAPRIEN2 Mask */ + +#define PWM_CAPIEN_CAPRIEN3_Pos (3) /*!< PWM_T::CAPIEN: CAPRIEN3 Position */ +#define PWM_CAPIEN_CAPRIEN3_Msk (0x1ul << PWM_CAPIEN_CAPRIEN3_Pos) /*!< PWM_T::CAPIEN: CAPRIEN3 Mask */ + +#define PWM_CAPIEN_CAPRIEN4_Pos (4) /*!< PWM_T::CAPIEN: CAPRIEN4 Position */ +#define PWM_CAPIEN_CAPRIEN4_Msk (0x1ul << PWM_CAPIEN_CAPRIEN4_Pos) /*!< PWM_T::CAPIEN: CAPRIEN4 Mask */ + +#define PWM_CAPIEN_CAPRIEN5_Pos (5) /*!< PWM_T::CAPIEN: CAPRIEN5 Position */ +#define PWM_CAPIEN_CAPRIEN5_Msk (0x1ul << PWM_CAPIEN_CAPRIEN5_Pos) /*!< PWM_T::CAPIEN: CAPRIEN5 Mask */ + +#define PWM_CAPIEN_CAPFIENn_Pos (8) /*!< PWM_T::CAPIEN: CAPFIENn Position */ +#define PWM_CAPIEN_CAPFIENn_Msk (0x3ful << PWM_CAPIEN_CAPFIENn_Pos) /*!< PWM_T::CAPIEN: CAPFIENn Mask */ + +#define PWM_CAPIEN_CAPFIEN0_Pos (8) /*!< PWM_T::CAPIEN: CAPFIEN0 Position */ +#define PWM_CAPIEN_CAPFIEN0_Msk (0x1ul << PWM_CAPIEN_CAPFIEN0_Pos) /*!< PWM_T::CAPIEN: CAPFIEN0 Mask */ + +#define PWM_CAPIEN_CAPFIEN1_Pos (9) /*!< PWM_T::CAPIEN: CAPFIEN1 Position */ +#define PWM_CAPIEN_CAPFIEN1_Msk (0x1ul << PWM_CAPIEN_CAPFIEN1_Pos) /*!< PWM_T::CAPIEN: CAPFIEN1 Mask */ + +#define PWM_CAPIEN_CAPFIEN2_Pos (10) /*!< PWM_T::CAPIEN: CAPFIEN2 Position */ +#define PWM_CAPIEN_CAPFIEN2_Msk (0x1ul << PWM_CAPIEN_CAPFIEN2_Pos) /*!< PWM_T::CAPIEN: CAPFIEN2 Mask */ + +#define PWM_CAPIEN_CAPFIEN3_Pos (11) /*!< PWM_T::CAPIEN: CAPFIEN3 Position */ +#define PWM_CAPIEN_CAPFIEN3_Msk (0x1ul << PWM_CAPIEN_CAPFIEN3_Pos) /*!< PWM_T::CAPIEN: CAPFIEN3 Mask */ + +#define PWM_CAPIEN_CAPFIEN4_Pos (12) /*!< PWM_T::CAPIEN: CAPFIEN4 Position */ +#define PWM_CAPIEN_CAPFIEN4_Msk (0x1ul << PWM_CAPIEN_CAPFIEN4_Pos) /*!< PWM_T::CAPIEN: CAPFIEN4 Mask */ + +#define PWM_CAPIEN_CAPFIEN5_Pos (13) /*!< PWM_T::CAPIEN: CAPFIEN5 Position */ +#define PWM_CAPIEN_CAPFIEN5_Msk (0x1ul << PWM_CAPIEN_CAPFIEN5_Pos) /*!< PWM_T::CAPIEN: CAPFIEN5 Mask */ + +#define PWM_CAPIF_CRLIFn_Pos (0) /*!< PWM_T::CAPIF: CRLIFn Position */ +#define PWM_CAPIF_CRLIFn_Msk (0x3ful << PWM_CAPIF_CRLIFn_Pos) /*!< PWM_T::CAPIF: CRLIFn Mask */ + +#define PWM_CAPIF_CRLIF0_Pos (0) /*!< PWM_T::CAPIF: CRLIF0 Position */ +#define PWM_CAPIF_CRLIF0_Msk (0x1ul << PWM_CAPIF_CRLIF0_Pos) /*!< PWM_T::CAPIF: CRLIF0 Mask */ + +#define PWM_CAPIF_CRLIF1_Pos (1) /*!< PWM_T::CAPIF: CRLIF1 Position */ +#define PWM_CAPIF_CRLIF1_Msk (0x1ul << PWM_CAPIF_CRLIF1_Pos) /*!< PWM_T::CAPIF: CRLIF1 Mask */ + +#define PWM_CAPIF_CRLIF2_Pos (2) /*!< PWM_T::CAPIF: CRLIF2 Position */ +#define PWM_CAPIF_CRLIF2_Msk (0x1ul << PWM_CAPIF_CRLIF2_Pos) /*!< PWM_T::CAPIF: CRLIF2 Mask */ + +#define PWM_CAPIF_CRLIF3_Pos (3) /*!< PWM_T::CAPIF: CRLIF3 Position */ +#define PWM_CAPIF_CRLIF3_Msk (0x1ul << PWM_CAPIF_CRLIF3_Pos) /*!< PWM_T::CAPIF: CRLIF3 Mask */ + +#define PWM_CAPIF_CRLIF4_Pos (4) /*!< PWM_T::CAPIF: CRLIF4 Position */ +#define PWM_CAPIF_CRLIF4_Msk (0x1ul << PWM_CAPIF_CRLIF4_Pos) /*!< PWM_T::CAPIF: CRLIF4 Mask */ + +#define PWM_CAPIF_CRLIF5_Pos (5) /*!< PWM_T::CAPIF: CRLIF5 Position */ +#define PWM_CAPIF_CRLIF5_Msk (0x1ul << PWM_CAPIF_CRLIF5_Pos) /*!< PWM_T::CAPIF: CRLIF5 Mask */ + +#define PWM_CAPIF_CFLIFn_Pos (8) /*!< PWM_T::CAPIF: CFLIFn Position */ +#define PWM_CAPIF_CFLIFn_Msk (0x3ful << PWM_CAPIF_CFLIFn_Pos) /*!< PWM_T::CAPIF: CFLIFn Mask */ + +#define PWM_CAPIF_CFLIF0_Pos (8) /*!< PWM_T::CAPIF: CFLIF0 Position */ +#define PWM_CAPIF_CFLIF0_Msk (0x1ul << PWM_CAPIF_CFLIF0_Pos) /*!< PWM_T::CAPIF: CFLIF0 Mask */ + +#define PWM_CAPIF_CFLIF1_Pos (9) /*!< PWM_T::CAPIF: CFLIF1 Position */ +#define PWM_CAPIF_CFLIF1_Msk (0x1ul << PWM_CAPIF_CFLIF1_Pos) /*!< PWM_T::CAPIF: CFLIF1 Mask */ + +#define PWM_CAPIF_CFLIF2_Pos (10) /*!< PWM_T::CAPIF: CFLIF2 Position */ +#define PWM_CAPIF_CFLIF2_Msk (0x1ul << PWM_CAPIF_CFLIF2_Pos) /*!< PWM_T::CAPIF: CFLIF2 Mask */ + +#define PWM_CAPIF_CFLIF3_Pos (11) /*!< PWM_T::CAPIF: CFLIF3 Position */ +#define PWM_CAPIF_CFLIF3_Msk (0x1ul << PWM_CAPIF_CFLIF3_Pos) /*!< PWM_T::CAPIF: CFLIF3 Mask */ + +#define PWM_CAPIF_CFLIF4_Pos (12) /*!< PWM_T::CAPIF: CFLIF4 Position */ +#define PWM_CAPIF_CFLIF4_Msk (0x1ul << PWM_CAPIF_CFLIF4_Pos) /*!< PWM_T::CAPIF: CFLIF4 Mask */ + +#define PWM_CAPIF_CFLIF5_Pos (13) /*!< PWM_T::CAPIF: CFLIF5 Position */ +#define PWM_CAPIF_CFLIF5_Msk (0x1ul << PWM_CAPIF_CFLIF5_Pos) /*!< PWM_T::CAPIF: CFLIF5 Mask */ + +#define PWM_PBUF_PBUF_Pos (0) /*!< PWM_T::PBUF0: PBUF Position */ +#define PWM_PBUF_PBUF_Msk (0xfffful << PWM_PBUF_PBUF_Pos) /*!< PWM_T::PBUF0: PBUF Mask */ + +#define PWM_PBUF0_PBUF_Pos (0) /*!< PWM_T::PBUF0: PBUF Position */ +#define PWM_PBUF0_PBUF_Msk (0xfffful << PWM_PBUF0_PBUF_Pos) /*!< PWM_T::PBUF0: PBUF Mask */ + +#define PWM_PBUF2_PBUF_Pos (0) /*!< PWM_T::PBUF2: PBUF Position */ +#define PWM_PBUF2_PBUF_Msk (0xfffful << PWM_PBUF2_PBUF_Pos) /*!< PWM_T::PBUF2: PBUF Mask */ + +#define PWM_PBUF4_PBUF_Pos (0) /*!< PWM_T::PBUF4: PBUF Position */ +#define PWM_PBUF4_PBUF_Msk (0xfffful << PWM_PBUF4_PBUF_Pos) /*!< PWM_T::PBUF4: PBUF Mask */ + +#define PWM_CMPBUF_CMPBUF_Pos (0) /*!< PWM_T::CMPBUF0: CMPBUF Position */ +#define PWM_CMPBUF_CMPBUF_Msk (0xfffful << PWM_CMPBUF_CMPBUF_Pos) /*!< PWM_T::CMPBUF0: CMPBUF Mask */ + +#define PWM_CMPBUF0_CMPBUF_Pos (0) /*!< PWM_T::CMPBUF0: CMPBUF Position */ +#define PWM_CMPBUF0_CMPBUF_Msk (0xfffful << PWM_CMPBUF0_CMPBUF_Pos) /*!< PWM_T::CMPBUF0: CMPBUF Mask */ + +#define PWM_CMPBUF1_CMPBUF_Pos (0) /*!< PWM_T::CMPBUF1: CMPBUF Position */ +#define PWM_CMPBUF1_CMPBUF_Msk (0xfffful << PWM_CMPBUF1_CMPBUF_Pos) /*!< PWM_T::CMPBUF1: CMPBUF Mask */ + +#define PWM_CMPBUF2_CMPBUF_Pos (0) /*!< PWM_T::CMPBUF2: CMPBUF Position */ +#define PWM_CMPBUF2_CMPBUF_Msk (0xfffful << PWM_CMPBUF2_CMPBUF_Pos) /*!< PWM_T::CMPBUF2: CMPBUF Mask */ + +#define PWM_CMPBUF3_CMPBUF_Pos (0) /*!< PWM_T::CMPBUF3: CMPBUF Position */ +#define PWM_CMPBUF3_CMPBUF_Msk (0xfffful << PWM_CMPBUF3_CMPBUF_Pos) /*!< PWM_T::CMPBUF3: CMPBUF Mask */ + +#define PWM_CMPBUF4_CMPBUF_Pos (0) /*!< PWM_T::CMPBUF4: CMPBUF Position */ +#define PWM_CMPBUF4_CMPBUF_Msk (0xfffful << PWM_CMPBUF4_CMPBUF_Pos) /*!< PWM_T::CMPBUF4: CMPBUF Mask */ + +#define PWM_CMPBUF5_CMPBUF_Pos (0) /*!< PWM_T::CMPBUF5: CMPBUF Position */ +#define PWM_CMPBUF5_CMPBUF_Msk (0xfffful << PWM_CMPBUF5_CMPBUF_Pos) /*!< PWM_T::CMPBUF5: CMPBUF Mask */ + +/**@}*/ /* PWM_CONST */ +/**@}*/ /* end of PWM register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __PWM_REG_H__ */ \ No newline at end of file diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/qspi_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/qspi_reg.h new file mode 100644 index 00000000000..d8018672f66 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/qspi_reg.h @@ -0,0 +1,591 @@ +/**************************************************************************//** + * @file qspi_reg.h + * @version V1.00 + * @brief QSPI register definition header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __QSPI_REG_H__ +#define __QSPI_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup QSPI Quad Serial Peripheral Interface Controller (QSPI) + Memory Mapped Structure for QSPI Controller +@{ */ +typedef struct +{ + + + /** + * @var QSPI_T::CTL + * Offset: 0x00 QSPI Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |QSPIEN |QSPI Transfer Control Enable Bit + * | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1 + * | | |In Slave mode, this device is ready to receive data when this bit is set to 1. + * | | |0 = Transfer control Disabled. + * | | |1 = Transfer control Enabled. + * | | |Note: Before changing the configurations of QSPIx_CTL, QSPIx_CLKDIV, QSPIx_SSCTL and QSPIx_FIFOCTL registers, user shall clear the QSPIEN (QSPIx_CTL[0]) and confirm the QSPIENSTS (QSPIx_STATUS[15]) is 0. + * |[1] |RXNEG |Receive on Negative Edge + * | | |0 = Received data input signal is latched on the rising edge of QSPI bus clock. + * | | |1 = Received data input signal is latched on the falling edge of QSPI bus clock. + * |[2] |TXNEG |Transmit on Negative Edge + * | | |0 = Transmitted data output signal is changed on the rising edge of QSPI bus clock. + * | | |1 = Transmitted data output signal is changed on the falling edge of QSPI bus clock. + * |[3] |CLKPOL |Clock Polarity + * | | |0 = QSPI bus clock is idle low. + * | | |1 = QSPI bus clock is idle high. + * |[7:4] |SUSPITV |Suspend Interval (Master Only) + * | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer + * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word + * | | |The default value is 0x3 + * | | |The period of the suspend interval is obtained according to the following equation. + * | | |(SUSPITV[3:0] + 0.5) * period of QSPICLK clock cycle + * | | |Example: + * | | |SUSPITV = 0x0 .... 0.5 QSPICLK clock cycle. + * | | |SUSPITV = 0x1 .... 1.5 QSPICLK clock cycle. + * | | |..... + * | | |SUSPITV = 0xE .... 14.5 QSPICLK clock cycle. + * | | |SUSPITV = 0xF .... 15.5 QSPICLK clock cycle. + * |[12:8] |DWIDTH |Data Width + * | | |This field specifies how many bits can be transmitted / received in one transaction + * | | |The minimum bit length is 8 bits and can up to 32 bits. + * | | |DWIDTH = 0x08 .... 8 bits. + * | | |DWIDTH = 0x09 .... 9 bits. + * | | |..... + * | | |DWIDTH = 0x1F .... 31 bits. + * | | |DWIDTH = 0x00 .... 32 bits. + * |[13] |LSB |Send LSB First + * | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first. + * | | |1 = The LSB, bit 0 of the QSPI TX register, is sent first to the QSPI data output pin, and the first bit received from the QSPI data input pin will be put in the LSB position of the RX register (bit 0 of QSPI_RX). + * |[14] |HALFDPX |QSPI Half-duplex Transfer Enable Bit + * | | |This bit is used to select full-duplex or half-duplex for QSPI transfer + * | | |The bit field DATDIR (QSPIx_CTL[20]) can be used to set the data direction in half-duplex transfer. + * | | |0 = QSPI operates in full-duplex transfer. + * | | |1 = QSPI operates in half-duplex transfer. + * |[15] |RXONLY |Receive-only Mode Enable Bit (Master Only) + * | | |This bit field is only available in Master mode + * | | |In receive-only mode, QSPI Master will generate QSPI bus clock continuously for receiving data bit from QSPI slave device and assert the BUSY status. + * | | |0 = Receive-only mode Disabled. + * | | |1 = Receive-only mode Enabled. + * |[16] |TWOBIT |2-bit Transfer Mode Enable Bit (Only Supported in QSPI0) + * | | |0 = 2-Bit Transfer mode Disabled. + * | | |1 = 2-Bit Transfer mode Enabled. + * | | |Note: When 2-Bit Transfer mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data + * | | |As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time. + * |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit + * | | |0 = QSPI unit transfer interrupt Disabled. + * | | |1 = QSPI unit transfer interrupt Enabled. + * |[18] |SLAVE |Slave Mode Control + * | | |0 = Master mode. + * | | |1 = Slave mode. + * |[19] |REORDER |Byte Reorder Function Enable Bit + * | | |0 = Byte Reorder function Disabled. + * | | |1 = Byte Reorder function Enabled + * | | |A byte suspend interval will be inserted among each byte + * | | |The period of the byte suspend interval depends on the setting of SUSPITV. + * | | |Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits. + * |[20] |DATDIR |Data Port Direction Control + * | | |This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer + * | | |0 = QSPI data is input direction. + * | | |1 = QSPI data is output direction. + * |[21] |DUALIOEN |Dual I/O Mode Enable Bit (Only Supported in QSPI0) + * | | |0 = Dual I/O mode Disabled. + * | | |1 = Dual I/O mode Enabled. + * |[22] |QUADIOEN |Quad I/O Mode Enable Bit (Only Supported in QSPI0) + * | | |0 = Quad I/O mode Disabled. + * | | |1 = Quad I/O mode Enabled. + * @var QSPI_T::CLKDIV + * Offset: 0x04 QSPI Clock Divider Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |DIVIDER |Clock Divider + * | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the QSPI bus clock of QSPI Master + * | | |The frequency is obtained according to the following equation. + * | | |where + * | | |is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2. + * @var QSPI_T::SSCTL + * Offset: 0x08 QSPI Slave Select Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SS |Slave Selection Control (Master Only) + * | | |If AUTOSS bit is cleared to 0, + * | | |0 = set the QSPIx_SS line to inactive state. + * | | |1 = set the QSPIx_SS line to active state. + * | | |If the AUTOSS bit is set to 1, + * | | |0 = Keep the QSPIx_SS line at inactive state. + * | | |1 = QSPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time + * | | |The active state of QSPIx_SS is specified in SSACTPOL (QSPIx_SSCTL[2]). + * |[2] |SSACTPOL |Slave Selection Active Polarity + * | | |This bit defines the active polarity of slave selection signal (QSPIx_SS). + * | | |0 = The slave selection signal QSPIx_SS is active low. + * | | |1 = The slave selection signal QSPIx_SS is active high. + * |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit (Master Only) + * | | |0 = Automatic slave selection function Disabled + * | | |Slave selection signal will be asserted/de-asserted according to SS (QSPIx_SSCTL[0]). + * | | |1 = Automatic slave selection function Enabled. + * |[4] |SLV3WIRE |Slave 3-wire Mode Enable Bit (Only Supported in QSPI0) + * | | |Slave 3-wire mode is only available in QSPI0 + * | | |In Slave 3-wire mode, the QSPI controller can work with 3-wire interface including QSPI0_CLK, QSPI0_MISO and QSPI0_MOSI pins. + * | | |0 = 4-wire bi-direction interface. + * | | |1 = 3-wire bi-direction interface. + * |[5] |SLVTOIEN |Slave Mode Time-out Interrupt Enable Bit (Only Supported in QSPI0) + * | | |0 = Slave mode time-out interrupt Disabled. + * | | |1 = Slave mode time-out interrupt Enabled. + * |[6] |SLVTORST |Slave Mode Time-out Reset Control (Only Supported in QSPI0) + * | | |0 = When Slave mode time-out event occurs, the TX and RX control circuit will not be reset. + * | | |1 = When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware. + * |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit + * | | |0 = Slave mode bit count error interrupt Disabled. + * | | |1 = Slave mode bit count error interrupt Enabled. + * |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit + * | | |0 = Slave mode TX under run interrupt Disabled. + * | | |1 = Slave mode TX under run interrupt Enabled. + * |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit + * | | |0 = Slave select active interrupt Disabled. + * | | |1 = Slave select active interrupt Enabled. + * |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit + * | | |0 = Slave select inactive interrupt Disabled. + * | | |1 = Slave select inactive interrupt Enabled. + * |[31:16] |SLVTOCNT |Slave Mode Time-out Period (Only Supported in QSPI0) + * | | |In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active + * | | |The clock source of the time-out counter is Slave peripheral clock + * | | |If the value is 0, it indicates the slave mode time-out function is disabled. + * @var QSPI_T::PDMACTL + * Offset: 0x0C QSPI PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TXPDMAEN |Transmit PDMA Enable Bit + * | | |0 = Transmit PDMA function Disabled. + * | | |1 = Transmit PDMA function Enabled. + * | | |Note: In QSPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function + * | | |User can enable TX PDMA function firstly or enable both functions simultaneously. + * |[1] |RXPDMAEN |Receive PDMA Enable Bit + * | | |0 = Receive PDMA function Disabled. + * | | |1 = Receive PDMA function Enabled. + * |[2] |PDMARST |PDMA Reset + * | | |0 = No effect. + * | | |1 = Reset the PDMA control logic of the QSPI controller. This bit will be automatically cleared to 0. + * @var QSPI_T::FIFOCTL + * Offset: 0x10 QSPI FIFO Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXRST |Receive Reset + * | | |0 = No effect. + * | | |1 = Reset receive FIFO pointer and receive circuit + * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 + * | | |User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not. + * |[1] |TXRST |Transmit Reset + * | | |0 = No effect. + * | | |1 = Reset transmit FIFO pointer and transmit circuit + * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 + * | | |User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not. + * | | |Note: If TX underflow event occurs in QSPI Slave mode, this bit can be used to make QSPI return to idle state. + * |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit + * | | |0 = RX FIFO threshold interrupt Disabled. + * | | |1 = RX FIFO threshold interrupt Enabled. + * |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit + * | | |0 = TX FIFO threshold interrupt Disabled. + * | | |1 = TX FIFO threshold interrupt Enabled. + * |[4] |RXTOIEN |Slave Receive Time-out Interrupt Enable Bit + * | | |0 = Receive time-out interrupt Disabled. + * | | |1 = Receive time-out interrupt Enabled. + * |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit + * | | |0 = Receive FIFO overrun interrupt Disabled. + * | | |1 = Receive FIFO overrun interrupt Enabled. + * |[6] |TXUFPOL |TX Underflow Data Polarity + * | | |0 = The QSPI data out is keep 0 if there is TX underflow event in Slave mode. + * | | |1 = The QSPI data out is keep 1 if there is TX underflow event in Slave mode. + * | | |Note: + * | | |1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active. + * | | |2. When TX underflow event occurs, QSPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward + * | | |Data stored in TX FIFO will be sent through QSPIx_MISO pin in the next transfer frame. + * |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit + * | | |When TX underflow event occurs in Slave mode, TXUFIF (QSPIx_STATUS[19]) will be set to 1 + * | | |This bit is used to enable the TX underflow interrupt. + * | | |0 = Slave TX underflow interrupt Disabled. + * | | |1 = Slave TX underflow interrupt Enabled. + * |[8] |RXFBCLR |Receive FIFO Buffer Clear + * | | |0 = No effect. + * | | |1 = Clear receive FIFO pointer + * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. + * | | |Note: The RX shift register will not be cleared. + * |[9] |TXFBCLR |Transmit FIFO Buffer Clear + * | | |0 = No effect. + * | | |1 = Clear transmit FIFO pointer + * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. + * | | |Note: The TX shift register will not be cleared. + * |[26:24] |RXTH |Receive FIFO Threshold + * | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0 + * |[30:28] |TXTH |Transmit FIFO Threshold + * | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0 + * @var QSPI_T::STATUS + * Offset: 0x14 QSPI Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |Busy Status (Read Only) + * | | |0 = QSPI controller is in idle state. + * | | |1 = QSPI controller is in busy state. + * | | |The following listing are the bus busy conditions: + * | | |a. QSPIx_CTL[0] = 1 and TXEMPTY = 0. + * | | |b + * | | |For QSPI Master mode, QSPIx_CTL[0] = 1 and TXEMPTY = 1 but the current transaction is not finished yet. + * | | |c. For QSPI Master mode, QSPIx_CTL[0] = 1 and RXONLY = 1. + * | | |d + * | | |For QSPI Slave mode, the QSPIx_CTL[0] = 1 and there is serial clock input into the QSPI core logic when slave select is active. + * | | |For QSPI Slave mode, the QSPIx_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive. + * |[1] |UNITIF |Unit Transfer Interrupt Flag + * | | |0 = No transaction has been finished since this bit was cleared to 0. + * | | |1 = QSPI controller has finished one unit transfer. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[2] |SSACTIF |Slave Select Active Interrupt Flag + * | | |0 = Slave select active interrupt was cleared or not occurred. + * | | |1 = Slave select active interrupt event occurred. + * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. + * |[3] |SSINAIF |Slave Select Inactive Interrupt Flag + * | | |0 = Slave select inactive interrupt was cleared or not occurred. + * | | |1 = Slave select inactive interrupt event occurred. + * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. + * |[4] |SSLINE |Slave Select Line Bus Status (Read Only) + * | | |0 = The slave select line status is 0. + * | | |1 = The slave select line status is 1. + * | | |Note: This bit is only available in Slave mode + * | | |If SSACTPOL (QSPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the QSPI slave select is in inactive status. + * |[5] |SLVTOIF |Slave Time-out Interrupt Flag (Only Supported in QSPI0) + * | | |When the slave select is active and the value of SLVTOCNT is not 0, as the bus clock is detected, the slave time-out counter in QSPI controller logic will be started + * | | |When the value of time-out counter is greater than or equal to the value of SLVTOCNT (QSPI_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted. + * | | |0 = Slave time-out is not active. + * | | |1 = Slave time-out is active. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag + * | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1. + * | | |0 = No Slave mode bit count error event. + * | | |1 = Slave mode bit count error event occurs. + * | | |Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state + * | | |This bit will be cleared by writing 1 to it. + * |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag + * | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1. + * | | |0 = No Slave TX under run event. + * | | |1 = Slave TX under run event occurs. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not empty. + * | | |1 = Receive FIFO buffer is empty. + * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not full. + * | | |1 = Receive FIFO buffer is full. + * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH. + * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH. + * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag + * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. + * | | |0 = No FIFO is overrun. + * | | |1 = Receive FIFO is overrun. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[12] |RXTOIF |Receive Time-out Interrupt Flag + * | | |0 = No receive FIFO time-out event. + * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 QSPI peripheral clock periods in Master mode or over 576 QSPI peripheral clock periods in Slave mode + * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[15] |QSPIENSTS |QSPI Enable Status (Read Only) + * | | |0 = The QSPI controller is disabled. + * | | |1 = The QSPI controller is enabled. + * | | |Note: The QSPI peripheral clock is asynchronous with the system clock + * | | |In order to make sure the QSPI control logic is disabled, this bit indicates the real status of QSPI controller. + * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not empty. + * | | |1 = Transmit FIFO buffer is empty. + * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not full. + * | | |1 = Transmit FIFO buffer is full. + * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH. + * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH. + * |[19] |TXUFIF |TX Underflow Interrupt Flag + * | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL. + * | | |0 = No effect. + * | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active. + * | | |Note 1: This bit will be cleared by writing 1 to it. + * | | |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done. + * |[23] |TXRXRST |TX or RX Reset Status (Read Only) + * | | |0 = The reset function of TXRST or RXRST is done. + * | | |1 = Doing the reset function of TXRST or RXRST. + * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles + * | | |User can check the status of this bit to monitor the reset function is doing or done. + * |[27:24] |RXCNT |Receive FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of receive FIFO buffer. + * |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of transmit FIFO buffer. + * @var QSPI_T::TX + * Offset: 0x20 QSPI Data Transmit Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TX |Data Transmit Register + * | | |The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers + * | | |The number of valid bits depends on the setting of DWIDTH (QSPIx_CTL[12:8]) in QSPI mode. + * | | |In QSPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted + * | | |If DWIDTH is set to 0x00 , the QSPI controller will perform a 32-bit transfer. + * | | |If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid + * | | |Note: In Master mode, QSPI controller will start to transfer the QSPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register. + * @var QSPI_T::RX + * Offset: 0x30 QSPI Data Receive Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RX |Data Receive Register + * | | |There are 4-level FIFO buffers in this controller + * | | |The data receive register holds the data received from QSPI data input pin + * | | |This is a read only register. + */ + __IO uint32_t CTL; /*!< [0x0000] QSPI Control Register */ + __IO uint32_t CLKDIV; /*!< [0x0004] QSPI Clock Divider Register */ + __IO uint32_t SSCTL; /*!< [0x0008] QSPI Slave Select Control Register */ + __IO uint32_t PDMACTL; /*!< [0x000c] QSPI PDMA Control Register */ + __IO uint32_t FIFOCTL; /*!< [0x0010] QSPI FIFO Control Register */ + __IO uint32_t STATUS; /*!< [0x0014] QSPI Status Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE0[2]; + /// @endcond //HIDDEN_SYMBOLS + __O uint32_t TX; /*!< [0x0020] QSPI Data Transmit Register */ + /// @cond HIDDEN_SYMBOLS + __I uint32_t RESERVE1[3]; + /// @endcond //HIDDEN_SYMBOLS + __I uint32_t RX; /*!< [0x0030] QSPI Data Receive Register */ + +} QSPI_T; + +/** + @addtogroup QSPI_CONST QSPI Bit Field Definition + Constant Definitions for QSPI Controller +@{ */ + +#define QSPI_CTL_QSPIEN_Pos (0) /*!< QSPI_T::CTL: QSPIEN Position */ +#define QSPI_CTL_QSPIEN_Msk (0x1ul << QSPI_CTL_QSPIEN_Pos) /*!< QSPI_T::CTL: QSPIEN Mask */ + +#define QSPI_CTL_RXNEG_Pos (1) /*!< QSPI_T::CTL: RXNEG Position */ +#define QSPI_CTL_RXNEG_Msk (0x1ul << QSPI_CTL_RXNEG_Pos) /*!< QSPI_T::CTL: RXNEG Mask */ + +#define QSPI_CTL_TXNEG_Pos (2) /*!< QSPI_T::CTL: TXNEG Position */ +#define QSPI_CTL_TXNEG_Msk (0x1ul << QSPI_CTL_TXNEG_Pos) /*!< QSPI_T::CTL: TXNEG Mask */ + +#define QSPI_CTL_CLKPOL_Pos (3) /*!< QSPI_T::CTL: CLKPOL Position */ +#define QSPI_CTL_CLKPOL_Msk (0x1ul << QSPI_CTL_CLKPOL_Pos) /*!< QSPI_T::CTL: CLKPOL Mask */ + +#define QSPI_CTL_SUSPITV_Pos (4) /*!< QSPI_T::CTL: SUSPITV Position */ +#define QSPI_CTL_SUSPITV_Msk (0xful << QSPI_CTL_SUSPITV_Pos) /*!< QSPI_T::CTL: SUSPITV Mask */ + +#define QSPI_CTL_DWIDTH_Pos (8) /*!< QSPI_T::CTL: DWIDTH Position */ +#define QSPI_CTL_DWIDTH_Msk (0x1ful << QSPI_CTL_DWIDTH_Pos) /*!< QSPI_T::CTL: DWIDTH Mask */ + +#define QSPI_CTL_LSB_Pos (13) /*!< QSPI_T::CTL: LSB Position */ +#define QSPI_CTL_LSB_Msk (0x1ul << QSPI_CTL_LSB_Pos) /*!< QSPI_T::CTL: LSB Mask */ + +#define QSPI_CTL_HALFDPX_Pos (14) /*!< QSPI_T::CTL: HALFDPX Position */ +#define QSPI_CTL_HALFDPX_Msk (0x1ul << QSPI_CTL_HALFDPX_Pos) /*!< QSPI_T::CTL: HALFDPX Mask */ + +#define QSPI_CTL_RXONLY_Pos (15) /*!< QSPI_T::CTL: RXONLY Position */ +#define QSPI_CTL_RXONLY_Msk (0x1ul << QSPI_CTL_RXONLY_Pos) /*!< QSPI_T::CTL: RXONLY Mask */ + +#define QSPI_CTL_TWOBIT_Pos (16) /*!< QSPI_T::CTL: TWOBIT Position */ +#define QSPI_CTL_TWOBIT_Msk (0x1ul << QSPI_CTL_TWOBIT_Pos) /*!< QSPI_T::CTL: TWOBIT Mask */ + +#define QSPI_CTL_UNITIEN_Pos (17) /*!< QSPI_T::CTL: UNITIEN Position */ +#define QSPI_CTL_UNITIEN_Msk (0x1ul << QSPI_CTL_UNITIEN_Pos) /*!< QSPI_T::CTL: UNITIEN Mask */ + +#define QSPI_CTL_SLAVE_Pos (18) /*!< QSPI_T::CTL: SLAVE Position */ +#define QSPI_CTL_SLAVE_Msk (0x1ul << QSPI_CTL_SLAVE_Pos) /*!< QSPI_T::CTL: SLAVE Mask */ + +#define QSPI_CTL_REORDER_Pos (19) /*!< QSPI_T::CTL: REORDER Position */ +#define QSPI_CTL_REORDER_Msk (0x1ul << QSPI_CTL_REORDER_Pos) /*!< QSPI_T::CTL: REORDER Mask */ + +#define QSPI_CTL_DATDIR_Pos (20) /*!< QSPI_T::CTL: DATDIR Position */ +#define QSPI_CTL_DATDIR_Msk (0x1ul << QSPI_CTL_DATDIR_Pos) /*!< QSPI_T::CTL: DATDIR Mask */ + +#define QSPI_CTL_DUALIOEN_Pos (21) /*!< QSPI_T::CTL: DUALIOEN Position */ +#define QSPI_CTL_DUALIOEN_Msk (0x1ul << QSPI_CTL_DUALIOEN_Pos) /*!< QSPI_T::CTL: DUALIOEN Mask */ + +#define QSPI_CTL_QUADIOEN_Pos (22) /*!< QSPI_T::CTL: QUADIOEN Position */ +#define QSPI_CTL_QUADIOEN_Msk (0x1ul << QSPI_CTL_QUADIOEN_Pos) /*!< QSPI_T::CTL: QUADIOEN Mask */ + +#define QSPI_CLKDIV_DIVIDER_Pos (0) /*!< QSPI_T::CLKDIV: DIVIDER Position */ +#define QSPI_CLKDIV_DIVIDER_Msk (0x1fful << QSPI_CLKDIV_DIVIDER_Pos) /*!< QSPI_T::CLKDIV: DIVIDER Mask */ + +#define QSPI_SSCTL_SS_Pos (0) /*!< QSPI_T::SSCTL: SS Position */ +#define QSPI_SSCTL_SS_Msk (0x1ul << QSPI_SSCTL_SS_Pos) /*!< QSPI_T::SSCTL: SS Mask */ + +#define QSPI_SSCTL_SSACTPOL_Pos (2) /*!< QSPI_T::SSCTL: SSACTPOL Position */ +#define QSPI_SSCTL_SSACTPOL_Msk (0x1ul << QSPI_SSCTL_SSACTPOL_Pos) /*!< QSPI_T::SSCTL: SSACTPOL Mask */ + +#define QSPI_SSCTL_AUTOSS_Pos (3) /*!< QSPI_T::SSCTL: AUTOSS Position */ +#define QSPI_SSCTL_AUTOSS_Msk (0x1ul << QSPI_SSCTL_AUTOSS_Pos) /*!< QSPI_T::SSCTL: AUTOSS Mask */ + +#define QSPI_SSCTL_SLV3WIRE_Pos (4) /*!< QSPI_T::SSCTL: SLV3WIRE Position */ +#define QSPI_SSCTL_SLV3WIRE_Msk (0x1ul << QSPI_SSCTL_SLV3WIRE_Pos) /*!< QSPI_T::SSCTL: SLV3WIRE Mask */ + +#define QSPI_SSCTL_SLVTOIEN_Pos (5) /*!< QSPI_T::SSCTL: SLVTOIEN Position */ +#define QSPI_SSCTL_SLVTOIEN_Msk (0x1ul << QSPI_SSCTL_SLVTOIEN_Pos) /*!< QSPI_T::SSCTL: SLVTOIEN Mask */ + +#define QSPI_SSCTL_SLVTORST_Pos (6) /*!< QSPI_T::SSCTL: SLVTORST Position */ +#define QSPI_SSCTL_SLVTORST_Msk (0x1ul << QSPI_SSCTL_SLVTORST_Pos) /*!< QSPI_T::SSCTL: SLVTORST Mask */ + +#define QSPI_SSCTL_SLVBEIEN_Pos (8) /*!< QSPI_T::SSCTL: SLVBEIEN Position */ +#define QSPI_SSCTL_SLVBEIEN_Msk (0x1ul << QSPI_SSCTL_SLVBEIEN_Pos) /*!< QSPI_T::SSCTL: SLVBEIEN Mask */ + +#define QSPI_SSCTL_SLVURIEN_Pos (9) /*!< QSPI_T::SSCTL: SLVURIEN Position */ +#define QSPI_SSCTL_SLVURIEN_Msk (0x1ul << QSPI_SSCTL_SLVURIEN_Pos) /*!< QSPI_T::SSCTL: SLVURIEN Mask */ + +#define QSPI_SSCTL_SSACTIEN_Pos (12) /*!< QSPI_T::SSCTL: SSACTIEN Position */ +#define QSPI_SSCTL_SSACTIEN_Msk (0x1ul << QSPI_SSCTL_SSACTIEN_Pos) /*!< QSPI_T::SSCTL: SSACTIEN Mask */ + +#define QSPI_SSCTL_SSINAIEN_Pos (13) /*!< QSPI_T::SSCTL: SSINAIEN Position */ +#define QSPI_SSCTL_SSINAIEN_Msk (0x1ul << QSPI_SSCTL_SSINAIEN_Pos) /*!< QSPI_T::SSCTL: SSINAIEN Mask */ + +#define QSPI_SSCTL_SLVTOCNT_Pos (16) /*!< QSPI_T::SSCTL: SLVTOCNT Position */ +#define QSPI_SSCTL_SLVTOCNT_Msk (0xfffful << QSPI_SSCTL_SLVTOCNT_Pos) /*!< QSPI_T::SSCTL: SLVTOCNT Mask */ + +#define QSPI_PDMACTL_TXPDMAEN_Pos (0) /*!< QSPI_T::PDMACTL: TXPDMAEN Position */ +#define QSPI_PDMACTL_TXPDMAEN_Msk (0x1ul << QSPI_PDMACTL_TXPDMAEN_Pos) /*!< QSPI_T::PDMACTL: TXPDMAEN Mask */ + +#define QSPI_PDMACTL_RXPDMAEN_Pos (1) /*!< QSPI_T::PDMACTL: RXPDMAEN Position */ +#define QSPI_PDMACTL_RXPDMAEN_Msk (0x1ul << QSPI_PDMACTL_RXPDMAEN_Pos) /*!< QSPI_T::PDMACTL: RXPDMAEN Mask */ + +#define QSPI_PDMACTL_PDMARST_Pos (2) /*!< QSPI_T::PDMACTL: PDMARST Position */ +#define QSPI_PDMACTL_PDMARST_Msk (0x1ul << QSPI_PDMACTL_PDMARST_Pos) /*!< QSPI_T::PDMACTL: PDMARST Mask */ + +#define QSPI_FIFOCTL_RXRST_Pos (0) /*!< QSPI_T::FIFOCTL: RXRST Position */ +#define QSPI_FIFOCTL_RXRST_Msk (0x1ul << QSPI_FIFOCTL_RXRST_Pos) /*!< QSPI_T::FIFOCTL: RXRST Mask */ + +#define QSPI_FIFOCTL_TXRST_Pos (1) /*!< QSPI_T::FIFOCTL: TXRST Position */ +#define QSPI_FIFOCTL_TXRST_Msk (0x1ul << QSPI_FIFOCTL_TXRST_Pos) /*!< QSPI_T::FIFOCTL: TXRST Mask */ + +#define QSPI_FIFOCTL_RXTHIEN_Pos (2) /*!< QSPI_T::FIFOCTL: RXTHIEN Position */ +#define QSPI_FIFOCTL_RXTHIEN_Msk (0x1ul << QSPI_FIFOCTL_RXTHIEN_Pos) /*!< QSPI_T::FIFOCTL: RXTHIEN Mask */ + +#define QSPI_FIFOCTL_TXTHIEN_Pos (3) /*!< QSPI_T::FIFOCTL: TXTHIEN Position */ +#define QSPI_FIFOCTL_TXTHIEN_Msk (0x1ul << QSPI_FIFOCTL_TXTHIEN_Pos) /*!< QSPI_T::FIFOCTL: TXTHIEN Mask */ + +#define QSPI_FIFOCTL_RXTOIEN_Pos (4) /*!< QSPI_T::FIFOCTL: RXTOIEN Position */ +#define QSPI_FIFOCTL_RXTOIEN_Msk (0x1ul << QSPI_FIFOCTL_RXTOIEN_Pos) /*!< QSPI_T::FIFOCTL: RXTOIEN Mask */ + +#define QSPI_FIFOCTL_RXOVIEN_Pos (5) /*!< QSPI_T::FIFOCTL: RXOVIEN Position */ +#define QSPI_FIFOCTL_RXOVIEN_Msk (0x1ul << QSPI_FIFOCTL_RXOVIEN_Pos) /*!< QSPI_T::FIFOCTL: RXOVIEN Mask */ + +#define QSPI_FIFOCTL_TXUFPOL_Pos (6) /*!< QSPI_T::FIFOCTL: TXUFPOL Position */ +#define QSPI_FIFOCTL_TXUFPOL_Msk (0x1ul << QSPI_FIFOCTL_TXUFPOL_Pos) /*!< QSPI_T::FIFOCTL: TXUFPOL Mask */ + +#define QSPI_FIFOCTL_TXUFIEN_Pos (7) /*!< QSPI_T::FIFOCTL: TXUFIEN Position */ +#define QSPI_FIFOCTL_TXUFIEN_Msk (0x1ul << QSPI_FIFOCTL_TXUFIEN_Pos) /*!< QSPI_T::FIFOCTL: TXUFIEN Mask */ + +#define QSPI_FIFOCTL_RXFBCLR_Pos (8) /*!< QSPI_T::FIFOCTL: RXFBCLR Position */ +#define QSPI_FIFOCTL_RXFBCLR_Msk (0x1ul << QSPI_FIFOCTL_RXFBCLR_Pos) /*!< QSPI_T::FIFOCTL: RXFBCLR Mask */ + +#define QSPI_FIFOCTL_TXFBCLR_Pos (9) /*!< QSPI_T::FIFOCTL: TXFBCLR Position */ +#define QSPI_FIFOCTL_TXFBCLR_Msk (0x1ul << QSPI_FIFOCTL_TXFBCLR_Pos) /*!< QSPI_T::FIFOCTL: TXFBCLR Mask */ + +#define QSPI_FIFOCTL_RXTH_Pos (24) /*!< QSPI_T::FIFOCTL: RXTH Position */ +#define QSPI_FIFOCTL_RXTH_Msk (0x7ul << QSPI_FIFOCTL_RXTH_Pos) /*!< QSPI_T::FIFOCTL: RXTH Mask */ + +#define QSPI_FIFOCTL_TXTH_Pos (28) /*!< QSPI_T::FIFOCTL: TXTH Position */ +#define QSPI_FIFOCTL_TXTH_Msk (0x7ul << QSPI_FIFOCTL_TXTH_Pos) /*!< QSPI_T::FIFOCTL: TXTH Mask */ + +#define QSPI_STATUS_BUSY_Pos (0) /*!< QSPI_T::STATUS: BUSY Position */ +#define QSPI_STATUS_BUSY_Msk (0x1ul << QSPI_STATUS_BUSY_Pos) /*!< QSPI_T::STATUS: BUSY Mask */ + +#define QSPI_STATUS_UNITIF_Pos (1) /*!< QSPI_T::STATUS: UNITIF Position */ +#define QSPI_STATUS_UNITIF_Msk (0x1ul << QSPI_STATUS_UNITIF_Pos) /*!< QSPI_T::STATUS: UNITIF Mask */ + +#define QSPI_STATUS_SSACTIF_Pos (2) /*!< QSPI_T::STATUS: SSACTIF Position */ +#define QSPI_STATUS_SSACTIF_Msk (0x1ul << QSPI_STATUS_SSACTIF_Pos) /*!< QSPI_T::STATUS: SSACTIF Mask */ + +#define QSPI_STATUS_SSINAIF_Pos (3) /*!< QSPI_T::STATUS: SSINAIF Position */ +#define QSPI_STATUS_SSINAIF_Msk (0x1ul << QSPI_STATUS_SSINAIF_Pos) /*!< QSPI_T::STATUS: SSINAIF Mask */ + +#define QSPI_STATUS_SSLINE_Pos (4) /*!< QSPI_T::STATUS: SSLINE Position */ +#define QSPI_STATUS_SSLINE_Msk (0x1ul << QSPI_STATUS_SSLINE_Pos) /*!< QSPI_T::STATUS: SSLINE Mask */ + +#define QSPI_STATUS_SLVTOIF_Pos (5) /*!< QSPI_T::STATUS: SLVTOIF Position */ +#define QSPI_STATUS_SLVTOIF_Msk (0x1ul << QSPI_STATUS_SLVTOIF_Pos) /*!< QSPI_T::STATUS: SLVTOIF Mask */ + +#define QSPI_STATUS_SLVBEIF_Pos (6) /*!< QSPI_T::STATUS: SLVBEIF Position */ +#define QSPI_STATUS_SLVBEIF_Msk (0x1ul << QSPI_STATUS_SLVBEIF_Pos) /*!< QSPI_T::STATUS: SLVBEIF Mask */ + +#define QSPI_STATUS_SLVURIF_Pos (7) /*!< QSPI_T::STATUS: SLVURIF Position */ +#define QSPI_STATUS_SLVURIF_Msk (0x1ul << QSPI_STATUS_SLVURIF_Pos) /*!< QSPI_T::STATUS: SLVURIF Mask */ + +#define QSPI_STATUS_RXEMPTY_Pos (8) /*!< QSPI_T::STATUS: RXEMPTY Position */ +#define QSPI_STATUS_RXEMPTY_Msk (0x1ul << QSPI_STATUS_RXEMPTY_Pos) /*!< QSPI_T::STATUS: RXEMPTY Mask */ + +#define QSPI_STATUS_RXFULL_Pos (9) /*!< QSPI_T::STATUS: RXFULL Position */ +#define QSPI_STATUS_RXFULL_Msk (0x1ul << QSPI_STATUS_RXFULL_Pos) /*!< QSPI_T::STATUS: RXFULL Mask */ + +#define QSPI_STATUS_RXTHIF_Pos (10) /*!< QSPI_T::STATUS: RXTHIF Position */ +#define QSPI_STATUS_RXTHIF_Msk (0x1ul << QSPI_STATUS_RXTHIF_Pos) /*!< QSPI_T::STATUS: RXTHIF Mask */ + +#define QSPI_STATUS_RXOVIF_Pos (11) /*!< QSPI_T::STATUS: RXOVIF Position */ +#define QSPI_STATUS_RXOVIF_Msk (0x1ul << QSPI_STATUS_RXOVIF_Pos) /*!< QSPI_T::STATUS: RXOVIF Mask */ + +#define QSPI_STATUS_RXTOIF_Pos (12) /*!< QSPI_T::STATUS: RXTOIF Position */ +#define QSPI_STATUS_RXTOIF_Msk (0x1ul << QSPI_STATUS_RXTOIF_Pos) /*!< QSPI_T::STATUS: RXTOIF Mask */ + +#define QSPI_STATUS_QSPIENSTS_Pos (15) /*!< QSPI_T::STATUS: QSPIENSTS Position */ +#define QSPI_STATUS_QSPIENSTS_Msk (0x1ul << QSPI_STATUS_QSPIENSTS_Pos) /*!< QSPI_T::STATUS: QSPIENSTS Mask */ + +#define QSPI_STATUS_TXEMPTY_Pos (16) /*!< QSPI_T::STATUS: TXEMPTY Position */ +#define QSPI_STATUS_TXEMPTY_Msk (0x1ul << QSPI_STATUS_TXEMPTY_Pos) /*!< QSPI_T::STATUS: TXEMPTY Mask */ + +#define QSPI_STATUS_TXFULL_Pos (17) /*!< QSPI_T::STATUS: TXFULL Position */ +#define QSPI_STATUS_TXFULL_Msk (0x1ul << QSPI_STATUS_TXFULL_Pos) /*!< QSPI_T::STATUS: TXFULL Mask */ + +#define QSPI_STATUS_TXTHIF_Pos (18) /*!< QSPI_T::STATUS: TXTHIF Position */ +#define QSPI_STATUS_TXTHIF_Msk (0x1ul << QSPI_STATUS_TXTHIF_Pos) /*!< QSPI_T::STATUS: TXTHIF Mask */ + +#define QSPI_STATUS_TXUFIF_Pos (19) /*!< QSPI_T::STATUS: TXUFIF Position */ +#define QSPI_STATUS_TXUFIF_Msk (0x1ul << QSPI_STATUS_TXUFIF_Pos) /*!< QSPI_T::STATUS: TXUFIF Mask */ + +#define QSPI_STATUS_TXRXRST_Pos (23) /*!< QSPI_T::STATUS: TXRXRST Position */ +#define QSPI_STATUS_TXRXRST_Msk (0x1ul << QSPI_STATUS_TXRXRST_Pos) /*!< QSPI_T::STATUS: TXRXRST Mask */ + +#define QSPI_STATUS_RXCNT_Pos (24) /*!< QSPI_T::STATUS: RXCNT Position */ +#define QSPI_STATUS_RXCNT_Msk (0xful << QSPI_STATUS_RXCNT_Pos) /*!< QSPI_T::STATUS: RXCNT Mask */ + +#define QSPI_STATUS_TXCNT_Pos (28) /*!< QSPI_T::STATUS: TXCNT Position */ +#define QSPI_STATUS_TXCNT_Msk (0xful << QSPI_STATUS_TXCNT_Pos) /*!< QSPI_T::STATUS: TXCNT Mask */ + +#define QSPI_TX_TX_Pos (0) /*!< QSPI_T::TX: TX Position */ +#define QSPI_TX_TX_Msk (0xfffffffful << QSPI_TX_TX_Pos) /*!< QSPI_T::TX: TX Mask */ + +#define QSPI_RX_RX_Pos (0) /*!< QSPI_T::RX: RX Position */ +#define QSPI_RX_RX_Msk (0xfffffffful << QSPI_RX_RX_Pos) /*!< QSPI_T::RX: RX Mask */ + + + +/**@}*/ /* QSPI_CONST */ +/**@}*/ /* end of QSPI register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __QSPI_REG_H__ */ \ No newline at end of file diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/rtc_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/rtc_reg.h new file mode 100644 index 00000000000..4903da158d0 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/rtc_reg.h @@ -0,0 +1,775 @@ +/**************************************************************************//** + * @file rtc_reg.h + * @version V1.00 + * @brief RTC register definition header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __RTC_REG_H__ +#define __RTC_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup RTC Real Time Clock Controller (RTC) + Memory Mapped Structure for RTC Controller +@{ */ + +typedef struct +{ + + + /** + * @var RTC_T::INIT + * Offset: 0x00 RTC Initiation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |INIT_ACTIVE|RTC Active Status (Read Only) + * | | |0 = RTC is at reset state. + * | | |1 = RTC is at normal active state. + * |[31:1] |INIT |RTC Initiation (Write Only) + * | | |When RTC block is powered on, RTC is at reset state. + * | | |User has to write a number (0xa5eb1357) to INIT to make RTC leave reset state. + * | | |Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently. + * | | |The INIT is a write-only field and read value will be always 0. + * @var RTC_T::FREQADJ + * Offset: 0x08 RTC Frequency Compensation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |FRACTION |Fraction Part + * | | |Formula: FRACTION = (fraction part of detected value) X 64. + * | | |Note: Digit in FCR must be expressed as hexadecimal number. + * |[12:8] |INTEGER |Integer Part + * | | |00000 = Integer part of detected value is 32752. + * | | |00001 = Integer part of detected value is 32753. + * | | |00010 = Integer part of detected value is 32754. + * | | |00011 = Integer part of detected value is 32755. + * | | |00100 = Integer part of detected value is 32756. + * | | |00101 = Integer part of detected value is 32757. + * | | |00110 = Integer part of detected value is 32758. + * | | |00111 = Integer part of detected value is 32759. + * | | |01000 = Integer part of detected value is 32760. + * | | |01001 = Integer part of detected value is 32761. + * | | |01010 = Integer part of detected value is 32762. + * | | |01011 = Integer part of detected value is 32763. + * | | |01100 = Integer part of detected value is 32764. + * | | |01101 = Integer part of detected value is 32765. + * | | |01110 = Integer part of detected value is 32766. + * | | |01111 = Integer part of detected value is 32767. + * | | |10000 = Integer part of detected value is 32768. + * | | |10001 = Integer part of detected value is 32769. + * | | |10010 = Integer part of detected value is 32770. + * | | |10011 = Integer part of detected value is 32771. + * | | |10100 = Integer part of detected value is 32772. + * | | |10101 = Integer part of detected value is 32773. + * | | |10110 = Integer part of detected value is 32774. + * | | |10111 = Integer part of detected value is 32775. + * | | |11000 = Integer part of detected value is 32776. + * | | |11001 = Integer part of detected value is 32777. + * | | |11010 = Integer part of detected value is 32778. + * | | |11011 = Integer part of detected value is 32779. + * | | |11100 = Integer part of detected value is 32780. + * | | |11101 = Integer part of detected value is 32781. + * | | |11110 = Integer part of detected value is 32782. + * | | |11111 = Integer part of detected value is 32783. + * |[31] |FCRBUSY |Frequency Compensation Register Write Operation Busy (Read Only) (only for M252_C/E) + * | | |0 = The new register write operation is acceptable. + * | | |1 = The last write operation is in progress and new register write operation prohibited. + * | | |Note: This bit is only used when DCOMPEN(RTC_CLKFMT[16]) enabled. + * @var RTC_T::TIME + * Offset: 0x0C RTC Time Loading Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |SEC |1-Sec Time Digit (0~9) + * |[6:4] |TENSEC |10-Sec Time Digit (0~5) + * |[11:8] |MIN |1-Min Time Digit (0~9) + * |[14:12] |TENMIN |10-Min Time Digit (0~5) + * |[19:16] |HR |1-Hour Time Digit (0~9) + * |[21:20] |TENHR |10-Hour Time Digit (0~2) + * | | |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) + * | | |means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.) + * @var RTC_T::CAL + * Offset: 0x10 RTC Calendar Loading Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |DAY |1-Day Calendar Digit (0~9) + * |[5:4] |TENDAY |10-Day Calendar Digit (0~3) + * |[11:8] |MON |1-Month Calendar Digit (0~9) + * |[12] |TENMON |10-Month Calendar Digit (0~1) + * |[19:16] |YEAR |1-Year Calendar Digit (0~9) + * |[23:20] |TENYEAR |10-Year Calendar Digit (0~9) + * @var RTC_T::CLKFMT + * Offset: 0x14 RTC Time Scale Selection Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |24HEN |24-hour / 12-hour Time Scale Selection + * | | |Indicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale. + * | | |0 = 12-hour time scale with AM and PM indication selected. + * | | |1 = 24-hour time scale selected. + * |[16] |DCOMPEN |Dynamic Compensation Enable Bit (only for M252_C/E) + * | | |0 = Dynamic Compensation Disabled. + * | | |1 = Dynamic Compensation Enabled. + * @var RTC_T::WEEKDAY + * Offset: 0x18 RTC Day of the Week Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |WEEKDAY |Day of the Week Register + * | | |000 = Sunday. + * | | |001 = Monday. + * | | |010 = Tuesday. + * | | |011 = Wednesday. + * | | |100 = Thursday. + * | | |101 = Friday. + * | | |110 = Saturday. + * | | |111 = Reserved. + * @var RTC_T::TALM + * Offset: 0x1C RTC Time Alarm Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |SEC |1-Sec Time Digit of Alarm Setting (0~9) + * |[6:4] |TENSEC |10-Sec Time Digit of Alarm Setting (0~5) + * |[11:8] |MIN |1-Min Time Digit of Alarm Setting (0~9) + * |[14:12] |TENMIN |10-Min Time Digit of Alarm Setting (0~5) + * |[19:16] |HR |1-Hour Time Digit of Alarm Setting (0~9) + * |[21:20] |TENHR |10-Hour Time Digit of Alarm Setting (0~2) + * | | |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) + * | | |means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.) + * @var RTC_T::CALM + * Offset: 0x20 RTC Calendar Alarm Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |DAY |1-Day Calendar Digit of Alarm Setting (0~9) + * |[5:4] |TENDAY |10-Day Calendar Digit of Alarm Setting (0~3) + * |[11:8] |MON |1-Month Calendar Digit of Alarm Setting (0~9) + * |[12] |TENMON |10-Month Calendar Digit of Alarm Setting (0~1) + * |[19:16] |YEAR |1-Year Calendar Digit of Alarm Setting (0~9) + * |[23:20] |TENYEAR |10-Year Calendar Digit of Alarm Setting (0~9) + * @var RTC_T::LEAPYEAR + * Offset: 0x24 RTC Leap Year Indicator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LEAPYEAR |Leap Year Indication Register (Read Only) + * | | |0 = This year is not a leap year. + * | | |1 = This year is leap year. + * @var RTC_T::INTEN + * Offset: 0x28 RTC Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ALMIEN |Alarm Interrupt Enable Bit + * | | |Set ALMIEN to 1 can also enable chip wake-up function when RTC alarm interrupt event is generated. + * | | |0 = RTC Alarm interrupt Disabled. + * | | |1 = RTC Alarm interrupt Enabled. + * |[1] |TICKIEN |Time Tick Interrupt Enable Bit + * | | |Set TICKIEN to 1 can also enable chip wake-up function when RTC tick interrupt event is generated. + * | | |0 = RTC Time Tick interrupt Disabled. + * | | |1 = RTC Time Tick interrupt Enabled. + * |[8] |TAMP0IEN |Tamper 0 Interrupt Enable Bit + * | | |Set TAMP0IEN to 1 can also enable chip wake-up function when tamper 0 interrupt event is generated. + * | | |0 = Tamper 0 interrupt Disabled. + * | | |1 = Tamper 0 interrupt Enabled. + * @var RTC_T::INTSTS + * Offset: 0x2C RTC Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ALMIF |RTC Alarm Interrupt Flag + * | | |0 = Alarm condition is not matched. + * | | |1 = Alarm condition is matched. + * | | |Note: Write 1 to clear this bit. + * |[1] |TICKIF |RTC Time Tick Interrupt Flag + * | | |0 = Tick condition does not occur. + * | | |1 = Tick condition occur. + * | | |Note: Write 1 to clear this bit. + * |[8] |TAMP0IF |Tamper 0 Interrupt Flag + * | | |0 = No Tamper 0 interrupt flag is generated. + * | | |1 = Tamper 0 interrupt flag is generated. + * | | |Note1: Write 1 to clear this bit. + * @var RTC_T::TICK + * Offset: 0x30 RTC Time Tick Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |TICK |Time Tick Register + * | | |These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request. + * | | |000 = Time tick is 1 second. + * | | |001 = Time tick is 1/2 second. + * | | |010 = Time tick is 1/4 second. + * | | |011 = Time tick is 1/8 second. + * | | |100 = Time tick is 1/16 second. + * | | |101 = Time tick is 1/32 second. + * | | |110 = Time tick is 1/64 second. + * | | |111 = Time tick is 1/128 second. + * @var RTC_T::TAMSK + * Offset: 0x34 RTC Time Alarm Mask Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSEC |Mask 1-Sec Time Digit of Alarm Setting (0~9) + * |[1] |MTENSEC |Mask 10-Sec Time Digit of Alarm Setting (0~5) + * |[2] |MMIN |Mask 1-Min Time Digit of Alarm Setting (0~9) + * |[3] |MTENMIN |Mask 10-Min Time Digit of Alarm Setting (0~5) + * |[4] |MHR |Mask 1-Hour Time Digit of Alarm Setting (0~9) + * |[5] |MTENHR |Mask 10-Hour Time Digit of Alarm Setting (0~2) + * @var RTC_T::CAMSK + * Offset: 0x38 RTC Calendar Alarm Mask Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MDAY |Mask 1-Day Calendar Digit of Alarm Setting (0~9) + * |[1] |MTENDAY |Mask 10-Day Calendar Digit of Alarm Setting (0~3) + * |[2] |MMON |Mask 1-Month Calendar Digit of Alarm Setting (0~9) + * |[3] |MTENMON |Mask 10-Month Calendar Digit of Alarm Setting (0~1) + * |[4] |MYEAR |Mask 1-Year Calendar Digit of Alarm Setting (0~9) + * |[5] |MTENYEAR |Mask 10-Year Calendar Digit of Alarm Setting (0~9) + * @var RTC_T::SPRCTL + * Offset: 0x3C RTC Spare Functional Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SPRCLRM |Spare Register Clear Mask Bit + * | | |0 = Spare register will be clear after TAMPER occur. + * | | |1 = Spare register will not be clear after TAMPER occur. + * |[2] |SPRRWEN |Spare Register Enable Bit + * | | |0 = Spare register is Disabled. + * | | |1 = Spare register is Enabled. + * | | |Note: When spare register is disabled, RTC_SPR0 ~ RTC_SPR4 cannot be accessed. + * |[5] |SPRCSTS |SPR Clear Flag + * | | |This bit indicates if the RTC_SPR0 ~ RTC_SPR4 content is cleared when specify tamper event is detected. + * | | |0 = Spare register content is not cleared. + * | | |1 = Spare register content is cleared. + * | | |Note1:Writes 1 to clear this bit. + * | | |Note2:This bit keep 1 when RTC_INTSTS[8] is not equal to 0. + * @var RTC_T::SPR + * Offset: 0x40~0x50 RTC Spare Register 0/1/2/3/4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SPARE |Spare Register + * | | |This field is used to store back-up information defined by user. + * | | |This field will be cleared by hardware automatically once a tamper pin event is detected. + * | | |Before storing back-up information in to RTC_SPRx register, user should check the register + * | | |read/write enable bit SPRRWEN (RTC_SPRCTL[2]) is enabled. + * @var RTC_T::LXTCTL + * Offset: 0x100 RTC 32KHz Oscillator Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:1] |GAIN |Oscillator Gain Option + * | | |User can select oscillator gain according to crystal external loading and operating temperature range. + * | | |The larger gain value corresponding to stronger driving capability and higher power consumption. + * | | |000 = L0 mode. + * | | |001 = L1 mode. + * | | |010 = L2 mode. + * | | |011 = L3 mode. + * | | |100 = L4 mode(Only for VBAT domain). + * | | |101 = L5 mode(Only for VBAT domain). + * | | |110 = L6 mode(Only for VBAT domain). + * | | |111 = L7 mode(Only for VBAT domain). + * |[7] |C32KS |RTC Clock 32K Source Selection: + * | | |0 = Internal RTC clock is from 32K crystal . + * | | |1 = Internal RTC clock is from LIRC32K. + * |[8] |IOCTLSEL |IO Pin Backup Control Selection (Only for VBAT Domain) + * | | |When low speed 32 kHz oscillator is disabled or TAMP0EN is disabled, PF.4 pin (X32KO pin), PF.5 pin (X32KI pin) or + * | | |PF.6 pin (TAMPER0 pin) can be used as GPIO function.User can program IOCTLSEL to decide PF.4, 5, 6 I/O function + * | | |is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0 control register. + * | | |0 = PF.4, 5, 6 pin I/O function is controlled by GPIO module. + * | | |1 = PF.4, 5, 6 pin I/O function is controlled by VBAT power domain. + * | | |Note1: IOCTLSEL will automatically be set by hardware to 1 when system power is off and RTC_GPIOCTL0 had been configured. + * | | |Note2: The GPIO control feature is not supported when there is not any VBAT power domain. + * |[13] |RTCLVDPD |RTC Low Voltage Detector Power Down (Only for VBAT domain) + * | | |0= RTC Low Voltage Detector active.. + * | | |1= RTC Low Voltage Detector enter power down. + * |[14] |RTCPORPD |RTC Power on Reset Power Down (Only for VBAT domain) + * | | |0= RTC POR active 1sec after first power up. + * | | |1= RTC POR enter power down. + * | | |Note: This bit only can be set to 1. + * @var RTC_T::GPIOCTL0 + * Offset: 0x104 RTC GPIO Control 0 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |OPMODE0 |IO Operation Mode(Only for VBAT domain) + * | | |00 = PF.4 is input only mode. + * | | |01 = PF.4 is output push pull mode. + * | | |10 = PF.4 is open drain mode. + * | | |11 = PF.4 is quasi-bidirectional mode. + * |[2] |DOUT0 |IO Output Data(Only for VBAT domain) + * | | |0 = PF.4 output low. + * | | |1 = PF.4 output high. + * |[3] |DINOFF0 |IO Pin Digital Input Path Disable Bit (Only for VBAT Domain) + * | | |0 = PF.4 digital input path Enabled. + * | | |1 = PF.4 digital input path Disabled (digital input tied to low). + * |[5:4] |PUSEL0 |IO Pull-up and Pull-down Enable Bits(Only for VBAT domain) + * | | |Determine PF.4 I/O pull-up or pull-down. + * | | |00 = PF.4 pull-up and pull-down disable. + * | | |01 = PF.4 pull-up enable. + * | | |10 = PF.4 pull-down enable. + * | | |11 = PF.4 pull-up and pull-down disable. + * | | |Note:Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up / pull-down control register only valid when OPMODE0 set as input tri-state + * | | |and open-drain mode. + * |[6] |SMTEN0 |Input Schmitt Trigger Enable Bit(Only for VBAT domain) + * | | |0 = PF.4 input schmitt trigger function Disabled. + * | | |1 = PF.4 input schmitt trigger function Enabled. + * |[9:8] |OPMODE1 |IO Operation Mode(Only for VBAT domain) + * | | |00 = PF.5 is input only mode. + * | | |01 = PF.5 is output push pull mode. + * | | |10 = PF.5 is open drain mode. + * | | |11 = PF.5 is quasi-bidirectional mode. + * |[10] |DOUT1 |IO Output Data(Only for VBAT domain) + * | | |0 = PF.5 output low. + * | | |1 = PF.5 output high. + * |[11] |DINOFF1 |IO Pin State Backup Selection(Only for VBAT domain) + * | | |0 = PF.5 digital input path Enabled. + * | | |1 = PF.5 digital input path Disabled (digital input tied to low). + * |[13:12] |PUSEL1 |IO Pull-up and Pull-down Enable Bits(Only for VBAT domain) + * | | |Determine PF.5 I/O pull-up or pull-down. + * | | |00 = PF.5 pull-up and pull-down disable. + * | | |01 = PF.5 pull-up enable. + * | | |10 = PF.5 pull-down enable. + * | | |11 = PF.5 pull-up and pull-down disable. + * | | |Note:Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up / pull-down control register only valid when OPMODE1 set as input tri-state + * | | |and open-drain mode. + * |[14] |SMTEN1 |Input Schmitt Trigger Enable Bit(Only for VBAT domain) + * | | |0 = PF.5 input schmitt trigger function Disabled. + * | | |1 = PF.5 input schmitt trigger function Enabled. + * |[17:16] |OPMODE2 |IO Operation Mode(Only for VBAT domain) + * | | |00 = PF.6 is input only mode. + * | | |01 = PF.6 is output push pull mode. + * | | |10 = PF.6 is open drain mode. + * | | |11 = PF.6 is quasi-bidirectional mode. + * |[18] |DOUT2 |IO Output Data(Only for VBAT domain) + * | | |0 = PF.6 output low. + * | | |1 = PF.6 output high. + * |[19] |DINOFF2 |IO Pin Digital Input Path Disable Bit (Only for VBAT Domain) + * | | |0 = PF.6 input schmitt trigger function Disabled. + * | | |1 = PF.6 input schmitt trigger function Enabled. + * |[21:20] |PUSEL2 |IO Pull-up and Pull-down Enable Bits(Only for VBAT domain) + * | | |Determine PF.6 I/O pull-up or pull-down. + * | | |00 = PF.6 pull-up and pull-down disable. + * | | |01 = PF.6 pull-up enable. + * | | |10 = PF.6 pull-down enable. + * | | |11 = PF.6 pull-up and pull-down disable. + * | | |Note:Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up / pull-down control register only valid when OPMODE2 set as input tri-state + * | | |and open-drain mode and PF6 as tamper pin. + * |[22] |SMTEN2 |Input Schmitt Trigger Enable Bit(Only for VBAT domain) + * | | |0 = PF.6 input schmitt trigger function Disabled. + * | | |1 = PF.6 input schmitt trigger function Enabled. + * @var RTC_T::DSTCTL + * Offset: 0x110 RTC Daylight Saving Time Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADDHR |Add 1 Hour + * | | |0 = No effect. + * | | |1 = RTC hour digit has been added one hour for summer time change. + * |[1] |SUBHR |Subtract 1 Hour + * | | |0 = No effect. + * | | |1 = RTC hour digit has been subtracted one hour for winter time change. + * |[2] |DSBAK |Daylight Saving Back + * | | |0= Normal mode. + * | | |1= Daylight saving mode. + * @var RTC_T::TAMPCTL + * Offset: 0x120 RTC Tamper Pin Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8] |TAMP0EN |Tamper0 Detect Enable Bit + * | | |0 = Tamper 0 detect Disabled. + * | | |1 = Tamper 0 detect Enabled. + * | | |Note: The reference is RTC-clock. Tamper detector need sync 2 ~ 3 RTC-clock. + * |[9] |TAMP0LV |Tamper 0 Level + * | | |This bit depend on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect Rising detection, will trigger tamper status when RTC_TAMPCTL[11] = 1. + * | | |Detect voltage level should be low. High will trigger tamper status when RTC_TAMPCTL[11] = 0. + * | | |1 = Detect Falling detection, will trigger tamper status when RTC_TAMPCTL[11] = 1. + * | | |Detect voltage level shoulld be high. Low will trigger tamper status when RTC_TAMPCTL[11] = 0. + * |[10] |TAMP0DBEN |Tamper 0 De-bounce Enable Bit + * | | |0 = Tamper 0 de-bounce Disabled. + * | | |1 = Tamper 0 de-bounce Enabled. + * | | |Note: In normal condition (25'C), it can deglitch 1~2 ns noise. + * |[11] |TAMP0TYPE |Tamper 0 Detect Type + * | | |0 = Tamper as edge detector. + * | | |1 = Tamper as Level detector. + * @var RTC_T::TAMPTIME + * Offset: 0x130 RTC Tamper Time Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |SEC |1-Sec Time Digit of TAMPER Time (0~9) + * |[6:4] |TENSEC |10-Sec Time Digit of TAMPER Time (0~5) + * |[11:8] |MIN |1-Min Time Digit of TAMPER Time (0~9) + * |[14:12] |TENMIN |10-Min Time Digit of TAMPER Time (0~5) + * |[19:16] |HR |1-Hour Time Digit of TAMPER Time (0~9) + * |[21:20] |TENHR |10-hour Time Digit of TAMPER Time (0~2) + * | | |Note: 24-hour time scale only. + * @var RTC_T::TAMPCAL + * Offset: 0x134 RTC Tamper Calendar Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |DAY |1-Day Calendar Digit of TAMPER Calendar (0~9) + * |[5:4] |TENDAY |10-Day Calendar Digit of TAMPER Calendar (0~3) + * |[11:8] |MON |1-Month Calendar Digit of TAMPER Calendar (0~9) + * |[12] |TENMON |10-Month Calendar Digit of TAMPER Calendar (0~1) + * |[19:16] |YEAR |1-Year Calendar Digit of TAMPER Calendar (0~9) + * |[23:20] |TENYEAR |10-Year Calendar Digit of TAMPER Calendar (0~9) + */ + __IO uint32_t INIT; /*!< [0x0000] RTC Initiation Register */ + __I uint32_t RESERVE0[1]; + __IO uint32_t FREQADJ; /*!< [0x0008] RTC Frequency Compensation Register */ + __IO uint32_t TIME; /*!< [0x000c] RTC Time Loading Register */ + __IO uint32_t CAL; /*!< [0x0010] RTC Calendar Loading Register */ + __IO uint32_t CLKFMT; /*!< [0x0014] RTC Time Scale Selection Register */ + __IO uint32_t WEEKDAY; /*!< [0x0018] RTC Day of the Week Register */ + __IO uint32_t TALM; /*!< [0x001c] RTC Time Alarm Register */ + __IO uint32_t CALM; /*!< [0x0020] RTC Calendar Alarm Register */ + __I uint32_t LEAPYEAR; /*!< [0x0024] RTC Leap Year Indicator Register */ + __IO uint32_t INTEN; /*!< [0x0028] RTC Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x002c] RTC Interrupt Status Register */ + __IO uint32_t TICK; /*!< [0x0030] RTC Time Tick Register */ + __IO uint32_t TAMSK; /*!< [0x0034] RTC Time Alarm Mask Register */ + __IO uint32_t CAMSK; /*!< [0x0038] RTC Calendar Alarm Mask Register */ + __IO uint32_t SPRCTL; /*!< [0x003c] RTC Spare Functional Control Register */ + __IO uint32_t SPR[5]; /*!< [0x0040 ~ 0x0050] RTC Spare Register 0 ~ 4 */ + __I uint32_t RESERVE1[43]; + __IO uint32_t LXTCTL; /*!< [0x0100] RTC 32KHz Oscillator Control Register */ + __IO uint32_t GPIOCTL0; /*!< [0x0104] RTC GPIO Control 0 Register */ + __I uint32_t RESERVE2[2]; + __IO uint32_t DSTCTL; /*!< [0x0110] RTC Daylight Saving Time Control Register */ + __I uint32_t RESERVE3[3]; + __IO uint32_t TAMPCTL; /*!< [0x0120] RTC Tamper Pin Control Register */ + __I uint32_t RESERVE4[3]; + __I uint32_t TAMPTIME; /*!< [0x0130] RTC Tamper Time Register */ + __I uint32_t TAMPCAL; /*!< [0x0134] RTC Tamper Calendar Register */ + +} RTC_T; + +/** + @addtogroup RTC_CONST RTC Bit Field Definition + Constant Definitions for RTC Controller +@{ */ + +#define RTC_INIT_ACTIVE_Pos (0) /*!< RTC_T::INIT: INIT_ACTIVE Position */ +#define RTC_INIT_ACTIVE_Msk (0x1ul << RTC_INIT_ACTIVE_Pos) /*!< RTC_T::INIT: INIT_ACTIVE Mask */ + +#define RTC_FREQADJ_FRACTION_Pos (0) /*!< RTC_T::FREQADJ: FRACTION Position */ +#define RTC_FREQADJ_FRACTION_Msk (0x3ful << RTC_FREQADJ_FRACTION_Pos) /*!< RTC_T::FREQADJ: FRACTION Mask */ + +#define RTC_FREQADJ_INTEGER_Pos (8) /*!< RTC_T::FREQADJ: INTEGER Position */ +#define RTC_FREQADJ_INTEGER_Msk (0x1ful << RTC_FREQADJ_INTEGER_Pos) /*!< RTC_T::FREQADJ: INTEGER Mask */ + +#define RTC_FREQADJ_FCRBUSY_Pos (31) /*!< RTC_T::FREQADJ: FCRBUSY Position */ +#define RTC_FREQADJ_FCRBUSY_Msk (0x1ful << RTC_FREQADJ_FCRBUSY_Pos) /*!< RTC_T::FREQADJ: FCRBUSY Mask */ + +#define RTC_TIME_SEC_Pos (0) /*!< RTC_T::TIME: SEC Position */ +#define RTC_TIME_SEC_Msk (0xful << RTC_TIME_SEC_Pos) /*!< RTC_T::TIME: SEC Mask */ + +#define RTC_TIME_TENSEC_Pos (4) /*!< RTC_T::TIME: TENSEC Position */ +#define RTC_TIME_TENSEC_Msk (0x7ul << RTC_TIME_TENSEC_Pos) /*!< RTC_T::TIME: TENSEC Mask */ + +#define RTC_TIME_MIN_Pos (8) /*!< RTC_T::TIME: MIN Position */ +#define RTC_TIME_MIN_Msk (0xful << RTC_TIME_MIN_Pos) /*!< RTC_T::TIME: MIN Mask */ + +#define RTC_TIME_TENMIN_Pos (12) /*!< RTC_T::TIME: TENMIN Position */ +#define RTC_TIME_TENMIN_Msk (0x7ul << RTC_TIME_TENMIN_Pos) /*!< RTC_T::TIME: TENMIN Mask */ + +#define RTC_TIME_HR_Pos (16) /*!< RTC_T::TIME: HR Position */ +#define RTC_TIME_HR_Msk (0xful << RTC_TIME_HR_Pos) /*!< RTC_T::TIME: HR Mask */ + +#define RTC_TIME_TENHR_Pos (20) /*!< RTC_T::TIME: TENHR Position */ +#define RTC_TIME_TENHR_Msk (0x3ul << RTC_TIME_TENHR_Pos) /*!< RTC_T::TIME: TENHR Mask */ + +#define RTC_CAL_DAY_Pos (0) /*!< RTC_T::CAL: DAY Position */ +#define RTC_CAL_DAY_Msk (0xful << RTC_CAL_DAY_Pos) /*!< RTC_T::CAL: DAY Mask */ + +#define RTC_CAL_TENDAY_Pos (4) /*!< RTC_T::CAL: TENDAY Position */ +#define RTC_CAL_TENDAY_Msk (0x3ul << RTC_CAL_TENDAY_Pos) /*!< RTC_T::CAL: TENDAY Mask */ + +#define RTC_CAL_MON_Pos (8) /*!< RTC_T::CAL: MON Position */ +#define RTC_CAL_MON_Msk (0xful << RTC_CAL_MON_Pos) /*!< RTC_T::CAL: MON Mask */ + +#define RTC_CAL_TENMON_Pos (12) /*!< RTC_T::CAL: TENMON Position */ +#define RTC_CAL_TENMON_Msk (0x1ul << RTC_CAL_TENMON_Pos) /*!< RTC_T::CAL: TENMON Mask */ + +#define RTC_CAL_YEAR_Pos (16) /*!< RTC_T::CAL: YEAR Position */ +#define RTC_CAL_YEAR_Msk (0xful << RTC_CAL_YEAR_Pos) /*!< RTC_T::CAL: YEAR Mask */ + +#define RTC_CAL_TENYEAR_Pos (20) /*!< RTC_T::CAL: TENYEAR Position */ +#define RTC_CAL_TENYEAR_Msk (0xful << RTC_CAL_TENYEAR_Pos) /*!< RTC_T::CAL: TENYEAR Mask */ + +#define RTC_CLKFMT_24HEN_Pos (0) /*!< RTC_T::CLKFMT: 24HEN Position */ +#define RTC_CLKFMT_24HEN_Msk (0x1ul << RTC_CLKFMT_24HEN_Pos) /*!< RTC_T::CLKFMT: 24HEN Mask */ + +#define RTC_CLKFMT_DCOMPEN_Pos (8) /*!< RTC_T::CLKFMT: DCOMPEN Position */ +#define RTC_CLKFMT_DCOMPEN_Msk (0x1ul << RTC_CLKFMT_DCOMPEN_Pos) /*!< RTC_T::CLKFMT: DCOMPEN Mask */ + +#define RTC_WEEKDAY_WEEKDAY_Pos (0) /*!< RTC_T::WEEKDAY: WEEKDAY Position */ +#define RTC_WEEKDAY_WEEKDAY_Msk (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos) /*!< RTC_T::WEEKDAY: WEEKDAY Mask */ + +#define RTC_TALM_SEC_Pos (0) /*!< RTC_T::TALM: SEC Position */ +#define RTC_TALM_SEC_Msk (0xful << RTC_TALM_SEC_Pos) /*!< RTC_T::TALM: SEC Mask */ + +#define RTC_TALM_TENSEC_Pos (4) /*!< RTC_T::TALM: TENSEC Position */ +#define RTC_TALM_TENSEC_Msk (0x7ul << RTC_TALM_TENSEC_Pos) /*!< RTC_T::TALM: TENSEC Mask */ + +#define RTC_TALM_MIN_Pos (8) /*!< RTC_T::TALM: MIN Position */ +#define RTC_TALM_MIN_Msk (0xful << RTC_TALM_MIN_Pos) /*!< RTC_T::TALM: MIN Mask */ + +#define RTC_TALM_TENMIN_Pos (12) /*!< RTC_T::TALM: TENMIN Position */ +#define RTC_TALM_TENMIN_Msk (0x7ul << RTC_TALM_TENMIN_Pos) /*!< RTC_T::TALM: TENMIN Mask */ + +#define RTC_TALM_HR_Pos (16) /*!< RTC_T::TALM: HR Position */ +#define RTC_TALM_HR_Msk (0xful << RTC_TALM_HR_Pos) /*!< RTC_T::TALM: HR Mask */ + +#define RTC_TALM_TENHR_Pos (20) /*!< RTC_T::TALM: TENHR Position */ +#define RTC_TALM_TENHR_Msk (0x3ul << RTC_TALM_TENHR_Pos) /*!< RTC_T::TALM: TENHR Mask */ + +#define RTC_CALM_DAY_Pos (0) /*!< RTC_T::CALM: DAY Position */ +#define RTC_CALM_DAY_Msk (0xful << RTC_CALM_DAY_Pos) /*!< RTC_T::CALM: DAY Mask */ + +#define RTC_CALM_TENDAY_Pos (4) /*!< RTC_T::CALM: TENDAY Position */ +#define RTC_CALM_TENDAY_Msk (0x3ul << RTC_CALM_TENDAY_Pos) /*!< RTC_T::CALM: TENDAY Mask */ + +#define RTC_CALM_MON_Pos (8) /*!< RTC_T::CALM: MON Position */ +#define RTC_CALM_MON_Msk (0xful << RTC_CALM_MON_Pos) /*!< RTC_T::CALM: MON Mask */ + +#define RTC_CALM_TENMON_Pos (12) /*!< RTC_T::CALM: TENMON Position */ +#define RTC_CALM_TENMON_Msk (0x1ul << RTC_CALM_TENMON_Pos) /*!< RTC_T::CALM: TENMON Mask */ + +#define RTC_CALM_YEAR_Pos (16) /*!< RTC_T::CALM: YEAR Position */ +#define RTC_CALM_YEAR_Msk (0xful << RTC_CALM_YEAR_Pos) /*!< RTC_T::CALM: YEAR Mask */ + +#define RTC_CALM_TENYEAR_Pos (20) /*!< RTC_T::CALM: TENYEAR Position */ +#define RTC_CALM_TENYEAR_Msk (0xful << RTC_CALM_TENYEAR_Pos) /*!< RTC_T::CALM: TENYEAR Mask */ + +#define RTC_LEAPYEAR_LEAPYEAR_Pos (0) /*!< RTC_T::LEAPYEAR: LEAPYEAR Position */ +#define RTC_LEAPYEAR_LEAPYEAR_Msk (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos) /*!< RTC_T::LEAPYEAR: LEAPYEAR Mask */ + +#define RTC_INTEN_ALMIEN_Pos (0) /*!< RTC_T::INTEN: ALMIEN Position */ +#define RTC_INTEN_ALMIEN_Msk (0x1ul << RTC_INTEN_ALMIEN_Pos) /*!< RTC_T::INTEN: ALMIEN Mask */ + +#define RTC_INTEN_TICKIEN_Pos (1) /*!< RTC_T::INTEN: TICKIEN Position */ +#define RTC_INTEN_TICKIEN_Msk (0x1ul << RTC_INTEN_TICKIEN_Pos) /*!< RTC_T::INTEN: TICKIEN Mask */ + +#define RTC_INTEN_TAMP0IEN_Pos (8) /*!< RTC_T::INTEN: TAMP0IEN Position */ +#define RTC_INTEN_TAMP0IEN_Msk (0x1ul << RTC_INTEN_TAMP0IEN_Pos) /*!< RTC_T::INTEN: TAMP0IEN Mask */ + +#define RTC_INTSTS_ALMIF_Pos (0) /*!< RTC_T::INTSTS: ALMIF Position */ +#define RTC_INTSTS_ALMIF_Msk (0x1ul << RTC_INTSTS_ALMIF_Pos) /*!< RTC_T::INTSTS: ALMIF Mask */ + +#define RTC_INTSTS_TICKIF_Pos (1) /*!< RTC_T::INTSTS: TICKIF Position */ +#define RTC_INTSTS_TICKIF_Msk (0x1ul << RTC_INTSTS_TICKIF_Pos) /*!< RTC_T::INTSTS: TICKIF Mask */ + +#define RTC_INTSTS_TAMP0IF_Pos (8) /*!< RTC_T::INTSTS: TAMP0IF Position */ +#define RTC_INTSTS_TAMP0IF_Msk (0x1ul << RTC_INTSTS_TAMP0IF_Pos) /*!< RTC_T::INTSTS: TAMP0IF Mask */ + +#define RTC_TICK_TICK_Pos (0) /*!< RTC_T::TICK: TICK Position */ +#define RTC_TICK_TICK_Msk (0x7ul << RTC_TICK_TICK_Pos) /*!< RTC_T::TICK: TICK Mask */ + +#define RTC_TAMSK_MSEC_Pos (0) /*!< RTC_T::TAMSK: MSEC Position */ +#define RTC_TAMSK_MSEC_Msk (0x1ul << RTC_TAMSK_MSEC_Pos) /*!< RTC_T::TAMSK: MSEC Mask */ + +#define RTC_TAMSK_MTENSEC_Pos (1) /*!< RTC_T::TAMSK: MTENSEC Position */ +#define RTC_TAMSK_MTENSEC_Msk (0x1ul << RTC_TAMSK_MTENSEC_Pos) /*!< RTC_T::TAMSK: MTENSEC Mask */ + +#define RTC_TAMSK_MMIN_Pos (2) /*!< RTC_T::TAMSK: MMIN Position */ +#define RTC_TAMSK_MMIN_Msk (0x1ul << RTC_TAMSK_MMIN_Pos) /*!< RTC_T::TAMSK: MMIN Mask */ + +#define RTC_TAMSK_MTENMIN_Pos (3) /*!< RTC_T::TAMSK: MTENMIN Position */ +#define RTC_TAMSK_MTENMIN_Msk (0x1ul << RTC_TAMSK_MTENMIN_Pos) /*!< RTC_T::TAMSK: MTENMIN Mask */ + +#define RTC_TAMSK_MHR_Pos (4) /*!< RTC_T::TAMSK: MHR Position */ +#define RTC_TAMSK_MHR_Msk (0x1ul << RTC_TAMSK_MHR_Pos) /*!< RTC_T::TAMSK: MHR Mask */ + +#define RTC_TAMSK_MTENHR_Pos (5) /*!< RTC_T::TAMSK: MTENHR Position */ +#define RTC_TAMSK_MTENHR_Msk (0x1ul << RTC_TAMSK_MTENHR_Pos) /*!< RTC_T::TAMSK: MTENHR Mask */ + +#define RTC_CAMSK_MDAY_Pos (0) /*!< RTC_T::CAMSK: MDAY Position */ +#define RTC_CAMSK_MDAY_Msk (0x1ul << RTC_CAMSK_MDAY_Pos) /*!< RTC_T::CAMSK: MDAY Mask */ + +#define RTC_CAMSK_MTENDAY_Pos (1) /*!< RTC_T::CAMSK: MTENDAY Position */ +#define RTC_CAMSK_MTENDAY_Msk (0x1ul << RTC_CAMSK_MTENDAY_Pos) /*!< RTC_T::CAMSK: MTENDAY Mask */ + +#define RTC_CAMSK_MMON_Pos (2) /*!< RTC_T::CAMSK: MMON Position */ +#define RTC_CAMSK_MMON_Msk (0x1ul << RTC_CAMSK_MMON_Pos) /*!< RTC_T::CAMSK: MMON Mask */ + +#define RTC_CAMSK_MTENMON_Pos (3) /*!< RTC_T::CAMSK: MTENMON Position */ +#define RTC_CAMSK_MTENMON_Msk (0x1ul << RTC_CAMSK_MTENMON_Pos) /*!< RTC_T::CAMSK: MTENMON Mask */ + +#define RTC_CAMSK_MYEAR_Pos (4) /*!< RTC_T::CAMSK: MYEAR Position */ +#define RTC_CAMSK_MYEAR_Msk (0x1ul << RTC_CAMSK_MYEAR_Pos) /*!< RTC_T::CAMSK: MYEAR Mask */ + +#define RTC_CAMSK_MTENYEAR_Pos (5) /*!< RTC_T::CAMSK: MTENYEAR Position */ +#define RTC_CAMSK_MTENYEAR_Msk (0x1ul << RTC_CAMSK_MTENYEAR_Pos) /*!< RTC_T::CAMSK: MTENYEAR Mask */ + +#define RTC_SPRCTL_SPRCLRM_Pos (0) /*!< RTC_T::SPRCTL: SPRCLRM Position */ +#define RTC_SPRCTL_SPRCLRM_Msk (0x1ul << RTC_SPRCTL_SPRCLRM_Pos) /*!< RTC_T::SPRCTL: SPRCLRM Mask */ + +#define RTC_SPRCTL_SPRRWEN_Pos (2) /*!< RTC_T::SPRCTL: SPRRWEN Position */ +#define RTC_SPRCTL_SPRRWEN_Msk (0x1ul << RTC_SPRCTL_SPRRWEN_Pos) /*!< RTC_T::SPRCTL: SPRRWEN Mask */ + +#define RTC_SPRCTL_SPRCSTS_Pos (5) /*!< RTC_T::SPRCTL: SPRCSTS Position */ +#define RTC_SPRCTL_SPRCSTS_Msk (0x1ul << RTC_SPRCTL_SPRCSTS_Pos) /*!< RTC_T::SPRCTL: SPRCSTS Mask */ + +#define RTC_SPR0_SPARE_Pos (0) /*!< RTC_T::SPR0: SPARE Position */ +#define RTC_SPR0_SPARE_Msk (0xfffffffful << RTC_SPR0_SPARE_Pos) /*!< RTC_T::SPR0: SPARE Mask */ + +#define RTC_SPR1_SPARE_Pos (0) /*!< RTC_T::SPR1: SPARE Position */ +#define RTC_SPR1_SPARE_Msk (0xfffffffful << RTC_SPR1_SPARE_Pos) /*!< RTC_T::SPR1: SPARE Mask */ + +#define RTC_SPR2_SPARE_Pos (0) /*!< RTC_T::SPR2: SPARE Position */ +#define RTC_SPR2_SPARE_Msk (0xfffffffful << RTC_SPR2_SPARE_Pos) /*!< RTC_T::SPR2: SPARE Mask */ + +#define RTC_SPR3_SPARE_Pos (0) /*!< RTC_T::SPR3: SPARE Position */ +#define RTC_SPR3_SPARE_Msk (0xfffffffful << RTC_SPR3_SPARE_Pos) /*!< RTC_T::SPR3: SPARE Mask */ + +#define RTC_SPR4_SPARE_Pos (0) /*!< RTC_T::SPR4: SPARE Position */ +#define RTC_SPR4_SPARE_Msk (0xfffffffful << RTC_SPR4_SPARE_Pos) /*!< RTC_T::SPR4: SPARE Mask */ + +#define RTC_LXTCTL_GAIN_Pos (1) /*!< RTC_T::LXTCTL: GAIN Position */ +#define RTC_LXTCTL_GAIN_Msk (0x7ul << RTC_LXTCTL_GAIN_Pos) /*!< RTC_T::LXTCTL: GAIN Mask */ + +#define RTC_LXTCTL_C32KS_Pos (7) /*!< RTC_T::LXTCTL: C32KS Position */ +#define RTC_LXTCTL_C32KS_Msk (0x1ul << RTC_LXTCTL_C32KS_Pos) /*!< RTC_T::LXTCTL: C32KS Mask */ + +#define RTC_LXTCTL_IOCTLSEL_Pos (8) /*!< RTC_T::LXTCTL: IOCTLSEL Position */ +#define RTC_LXTCTL_IOCTLSEL_Msk (0x1ul << RTC_LXTCTL_IOCTLSEL_Pos) /*!< RTC_T::LXTCTL: IOCTLSEL Mask */ + +#define RTC_LXTCTL_RTCLVDPD_Pos (13) /*!< RTC_T::LXTCTL: RTCLVDPD Position */ +#define RTC_LXTCTL_RTCLVDPD_Msk (0x1ul << RTC_LXTCTL_RTCLVDPD_Pos) /*!< RTC_T::LXTCTL: RTCLVDPD Mask */ + +#define RTC_LXTCTL_RTCPORPD_Pos (14) /*!< RTC_T::LXTCTL: RTCPORPD Position */ +#define RTC_LXTCTL_RTCPORPD_Msk (0x1ul << RTC_LXTCTL_RTCPORPD_Pos) /*!< RTC_T::LXTCTL: RTCPORPD Mask */ + +#define RTC_GPIOCTL0_OPMODE0_Pos (0) /*!< RTC_T::GPIOCTL0: OPMODE0 Position */ +#define RTC_GPIOCTL0_OPMODE0_Msk (0x3ul << RTC_GPIOCTL0_OPMODE0_Pos) /*!< RTC_T::GPIOCTL0: OPMODE0 Mask */ + +#define RTC_GPIOCTL0_DOUT0_Pos (2) /*!< RTC_T::GPIOCTL0: DOUT0 Position */ +#define RTC_GPIOCTL0_DOUT0_Msk (0x1ul << RTC_GPIOCTL0_DOUT0_Pos) /*!< RTC_T::GPIOCTL0: DOUT0 Mask */ + +#define RTC_GPIOCTL0_DINOFF0_Pos (3) /*!< RTC_T::GPIOCTL0: DINOFF0 Position */ +#define RTC_GPIOCTL0_DINOFF0_Msk (0x1ul << RTC_GPIOCTL0_DINOFF0_Pos) /*!< RTC_T::GPIOCTL0: DINOFF0 Mask */ + +#define RTC_GPIOCTL0_PUSEL0_Pos (4) /*!< RTC_T::GPIOCTL0: PUSEL0 Position */ +#define RTC_GPIOCTL0_PUSEL0_Msk (0x3ul << RTC_GPIOCTL0_PUSEL0_Pos) /*!< RTC_T::GPIOCTL0: PUSEL0 Mask */ + +#define RTC_GPIOCTL0_SMTEN0_Pos (6) /*!< RTC_T::GPIOCTL0: SMTEN0 Position */ +#define RTC_GPIOCTL0_SMTEN0_Msk (0x1ul << RTC_GPIOCTL0_SMTEN0_Pos) /*!< RTC_T::GPIOCTL0: SMTEN0 Mask */ + +#define RTC_GPIOCTL0_OPMODE1_Pos (8) /*!< RTC_T::GPIOCTL0: OPMODE1 Position */ +#define RTC_GPIOCTL0_OPMODE1_Msk (0x3ul << RTC_GPIOCTL0_OPMODE1_Pos) /*!< RTC_T::GPIOCTL0: OPMODE1 Mask */ + +#define RTC_GPIOCTL0_DOUT1_Pos (10) /*!< RTC_T::GPIOCTL0: DOUT1 Position */ +#define RTC_GPIOCTL0_DOUT1_Msk (0x1ul << RTC_GPIOCTL0_DOUT1_Pos) /*!< RTC_T::GPIOCTL0: DOUT1 Mask */ + +#define RTC_GPIOCTL0_DINOFF1_Pos (11) /*!< RTC_T::GPIOCTL0: DINOFF1 Position */ +#define RTC_GPIOCTL0_DINOFF1_Msk (0x1ul << RTC_GPIOCTL0_DINOFF1_Pos) /*!< RTC_T::GPIOCTL0: DINOFF1 Mask */ + +#define RTC_GPIOCTL0_PUSEL1_Pos (12) /*!< RTC_T::GPIOCTL0: PUSEL1 Position */ +#define RTC_GPIOCTL0_PUSEL1_Msk (0x3ul << RTC_GPIOCTL0_PUSEL1_Pos) /*!< RTC_T::GPIOCTL0: PUSEL1 Mask */ + +#define RTC_GPIOCTL0_SMTEN1_Pos (14) /*!< RTC_T::GPIOCTL0: SMTEN1 Position */ +#define RTC_GPIOCTL0_SMTEN1_Msk (0x1ul << RTC_GPIOCTL0_SMTEN1_Pos) /*!< RTC_T::GPIOCTL0: SMTEN1 Mask */ + +#define RTC_GPIOCTL0_OPMODE2_Pos (16) /*!< RTC_T::GPIOCTL0: OPMODE2 Position */ +#define RTC_GPIOCTL0_OPMODE2_Msk (0x3ul << RTC_GPIOCTL0_OPMODE2_Pos) /*!< RTC_T::GPIOCTL0: OPMODE2 Mask */ + +#define RTC_GPIOCTL0_DOUT2_Pos (18) /*!< RTC_T::GPIOCTL0: DOUT2 Position */ +#define RTC_GPIOCTL0_DOUT2_Msk (0x1ul << RTC_GPIOCTL0_DOUT2_Pos) /*!< RTC_T::GPIOCTL0: DOUT2 Mask */ + +#define RTC_GPIOCTL0_DINOFF2_Pos (19) /*!< RTC_T::GPIOCTL0: DINOFF2 Position */ +#define RTC_GPIOCTL0_DINOFF2_Msk (0x1ul << RTC_GPIOCTL0_DINOFF2_Pos) /*!< RTC_T::GPIOCTL0: DINOFF2 Mask */ + +#define RTC_GPIOCTL0_PUSEL2_Pos (20) /*!< RTC_T::GPIOCTL0: PUSEL2 Position */ +#define RTC_GPIOCTL0_PUSEL2_Msk (0x3ul << RTC_GPIOCTL0_PUSEL2_Pos) /*!< RTC_T::GPIOCTL0: PUSEL2 Mask */ + +#define RTC_GPIOCTL0_SMTEN2_Pos (22) /*!< RTC_T::GPIOCTL0: SMTEN2 Position */ +#define RTC_GPIOCTL0_SMTEN2_Msk (0x1ul << RTC_GPIOCTL0_SMTEN2_Pos) /*!< RTC_T::GPIOCTL0: SMTEN2 Mask */ + +#define RTC_DSTCTL_ADDHR_Pos (0) /*!< RTC_T::DSTCTL: ADDHR Position */ +#define RTC_DSTCTL_ADDHR_Msk (0x1ul << RTC_DSTCTL_ADDHR_Pos) /*!< RTC_T::DSTCTL: ADDHR Mask */ + +#define RTC_DSTCTL_SUBHR_Pos (1) /*!< RTC_T::DSTCTL: SUBHR Position */ +#define RTC_DSTCTL_SUBHR_Msk (0x1ul << RTC_DSTCTL_SUBHR_Pos) /*!< RTC_T::DSTCTL: SUBHR Mask */ + +#define RTC_DSTCTL_DSBAK_Pos (2) /*!< RTC_T::DSTCTL: DSBAK Position */ +#define RTC_DSTCTL_DSBAK_Msk (0x1ul << RTC_DSTCTL_DSBAK_Pos) /*!< RTC_T::DSTCTL: DSBAK Mask */ + +#define RTC_TAMPCTL_TAMP0EN_Pos (8) /*!< RTC_T::TAMPCTL: TAMP0EN Position */ +#define RTC_TAMPCTL_TAMP0EN_Msk (0x1ul << RTC_TAMPCTL_TAMP0EN_Pos) /*!< RTC_T::TAMPCTL: TAMP0EN Mask */ + +#define RTC_TAMPCTL_TAMP0LV_Pos (9) /*!< RTC_T::TAMPCTL: TAMP0LV Position */ +#define RTC_TAMPCTL_TAMP0LV_Msk (0x1ul << RTC_TAMPCTL_TAMP0LV_Pos) /*!< RTC_T::TAMPCTL: TAMP0LV Mask */ + +#define RTC_TAMPCTL_TAMP0DBEN_Pos (10) /*!< RTC_T::TAMPCTL: TAMP0DBEN Position */ +#define RTC_TAMPCTL_TAMP0DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP0DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP0DBEN Mask */ + +#define RTC_TAMPCTL_TAMP0TYPE_Pos (11) /*!< RTC_T::TAMPCTL: TAMP0TYPE Position */ +#define RTC_TAMPCTL_TAMP0TYPE_Msk (0x1ul << RTC_TAMPCTL_TAMP0TYPE_Pos) /*!< RTC_T::TAMPCTL: TAMP0TYPE Mask */ + +#define RTC_TAMPTIME_SEC_Pos (0) /*!< RTC_T::TAMPTIME: SEC Position */ +#define RTC_TAMPTIME_SEC_Msk (0xful << RTC_TAMPTIME_SEC_Pos) /*!< RTC_T::TAMPTIME: SEC Mask */ + +#define RTC_TAMPTIME_TENSEC_Pos (4) /*!< RTC_T::TAMPTIME: TENSEC Position */ +#define RTC_TAMPTIME_TENSEC_Msk (0x7ul << RTC_TAMPTIME_TENSEC_Pos) /*!< RTC_T::TAMPTIME: TENSEC Mask */ + +#define RTC_TAMPTIME_MIN_Pos (8) /*!< RTC_T::TAMPTIME: MIN Position */ +#define RTC_TAMPTIME_MIN_Msk (0xful << RTC_TAMPTIME_MIN_Pos) /*!< RTC_T::TAMPTIME: MIN Mask */ + +#define RTC_TAMPTIME_TENMIN_Pos (12) /*!< RTC_T::TAMPTIME: TENMIN Position */ +#define RTC_TAMPTIME_TENMIN_Msk (0x7ul << RTC_TAMPTIME_TENMIN_Pos) /*!< RTC_T::TAMPTIME: TENMIN Mask */ + +#define RTC_TAMPTIME_HR_Pos (16) /*!< RTC_T::TAMPTIME: HR Position */ +#define RTC_TAMPTIME_HR_Msk (0xful << RTC_TAMPTIME_HR_Pos) /*!< RTC_T::TAMPTIME: HR Mask */ + +#define RTC_TAMPTIME_TENHR_Pos (20) /*!< RTC_T::TAMPTIME: TENHR Position */ +#define RTC_TAMPTIME_TENHR_Msk (0x3ul << RTC_TAMPTIME_TENHR_Pos) /*!< RTC_T::TAMPTIME: TENHR Mask */ + +#define RTC_TAMPCAL_DAY_Pos (0) /*!< RTC_T::TAMPCAL: DAY Position */ +#define RTC_TAMPCAL_DAY_Msk (0xful << RTC_TAMPCAL_DAY_Pos) /*!< RTC_T::TAMPCAL: DAY Mask */ + +#define RTC_TAMPCAL_TENDAY_Pos (4) /*!< RTC_T::TAMPCAL: TENDAY Position */ +#define RTC_TAMPCAL_TENDAY_Msk (0x3ul << RTC_TAMPCAL_TENDAY_Pos) /*!< RTC_T::TAMPCAL: TENDAY Mask */ + +#define RTC_TAMPCAL_MON_Pos (8) /*!< RTC_T::TAMPCAL: MON Position */ +#define RTC_TAMPCAL_MON_Msk (0xful << RTC_TAMPCAL_MON_Pos) /*!< RTC_T::TAMPCAL: MON Mask */ + +#define RTC_TAMPCAL_TENMON_Pos (12) /*!< RTC_T::TAMPCAL: TENMON Position */ +#define RTC_TAMPCAL_TENMON_Msk (0x1ul << RTC_TAMPCAL_TENMON_Pos) /*!< RTC_T::TAMPCAL: TENMON Mask */ + +#define RTC_TAMPCAL_YEAR_Pos (16) /*!< RTC_T::TAMPCAL: YEAR Position */ +#define RTC_TAMPCAL_YEAR_Msk (0xful << RTC_TAMPCAL_YEAR_Pos) /*!< RTC_T::TAMPCAL: YEAR Mask */ + +#define RTC_TAMPCAL_TENYEAR_Pos (20) /*!< RTC_T::TAMPCAL: TENYEAR Position */ +#define RTC_TAMPCAL_TENYEAR_Msk (0xful << RTC_TAMPCAL_TENYEAR_Pos) /*!< RTC_T::TAMPCAL: TENYEAR Mask */ + + +/**@}*/ /* RTC_CONST */ +/**@}*/ /* end of RTC register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __RTC_REG_H__ */ \ No newline at end of file diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/sc_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/sc_reg.h new file mode 100644 index 00000000000..1db5c43488a --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/sc_reg.h @@ -0,0 +1,973 @@ +/**************************************************************************//** + * @file sc_reg.h + * @version V1.00 + * @brief SC register definition header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SC_REG_H__ +#define __SC_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup SC Smart Card Host Interface Controller (SC) + Memory Mapped Structure for SC Controller +@{ */ + +typedef struct +{ + + + /** + * @var SC_T::DAT + * Offset: 0x00 SC Receive/Transmit Holding Buffer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DAT |Receive/Transmit Holding Buffer + * | | |Write Operation: + * | | |By writing data to DAT, the SC will send out an 8-bit data. + * | | |Note: If SCEN (SCn_CTL[0]) is not enabled, DAT cannot be programmed. + * | | |Read Operation: + * | | |By reading DAT, the SC will return an 8-bit received data. + * @var SC_T::CTL + * Offset: 0x04 SC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SCEN |SC Controller Enable Bit + * | | |Set this bit to 1 to enable SC operation. If this bit is cleared, + * | | |0 = SC will force all transition to IDLE state. + * | | |1 = SC controller is enabled and all function can work correctly. + * | | |Note: SCEN must be set to 1 before filling in other SC registers, or smart card will not work properly. + * |[1] |RXOFF |RX Transition Disable Control Bit + * | | |This bit is used for disable Rx transition function. + * | | |0 = The receiver Enabled. + * | | |1 = The receiver Disabled. + * | | |Note: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored. + * |[2] |TXOFF |TX Transition Disable Control Bit + * | | |This bit is used for disable Tx transition function. + * | | |0 = The transceiver Enabled. + * | | |1 = The transceiver Disabled. + * |[3] |AUTOCEN |Auto Convention Enable Bit + * | | |This bit is used for enable auto convention function. + * | | |0 = Auto-convention Disabled. + * | | |1 = Auto-convention Enabled. + * | | |If user enables auto convention function, the setting step must be done before Answer to Reset (ATR) state and the first data must be 0x3B or 0x3F + * | | |After hardware received first data and stored it at buffer, hardware will decided the convention and change the CONSEL (SCn_CTL[5:4]) bits automatically when received first data is 0x3B or 0x3F + * | | |If received first byte is 0x3B, TS is direct convention, CONSEL (SCn_CTL[5:4]) will be set to 00 automatically, otherwise the TS is inverse convention, and CONSEL (SCn_CTL[5:4]) will be set to 11. + * | | |If the first data is not 0x3B or 0x3F, hardware will set ACERRIF (SCn_INTSTS[10]) and generate an interrupt to CPU when ACERRIEN (SCn_INTEN[10]) is enabled. + * |[5:4] |CONSEL |Convention Selection + * | | |00 = Direct convention. + * | | |01 = Reserved. + * | | |10 = Reserved. + * | | |11 = Inverse convention. + * | | |Note: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored. + * |[7:6] |RXTRGLV |Rx Buffer Trigger Level + * | | |When the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set + * | | |If RDAIEN (SCn_INTEN[0]) is enabled, an interrupt will be generated to CPU. + * | | |00 = Rx Buffer Trigger Level with 01 bytes. + * | | |01 = Rx Buffer Trigger Level with 02 bytes. + * | | |10 = Rx Buffer Trigger Level with 03 bytes. + * | | |11 = Reserved. + * |[12:8] |BGT |Block Guard Time (BGT) + * | | |Block guard time means the minimum interval between the leading edges of two consecutive characters between different transfer directions + * | | |This field indicates the counter for the bit length of block guard time + * | | |According to ISO 7816-3, in T = 0 mode, user must fill 15 (real block guard time = 16.5) to this field; in T = 1 mode, user must fill 21 (real block guard time = 22.5) to it. + * | | |Note: The real block guard time is BGT + 1. + * |[14:13] |TMRSEL |Timer Channel Selection + * | | |00 = All internal timer function Disabled. + * | | |11 = Internal 24 bit timer and two 8 bit timers Enabled + * | | |User can configure them by setting SCn_TMRCTL0[23:0], SCn_TMRCTL1[7:0] and SCn_TMRCTL2[7:0]. + * | | |Other configurations are reserved + * |[15] |NSB |Stop Bit Length + * | | |This field indicates the length of stop bit. + * | | |0 = The stop bit length is 2 ETU. + * | | |1= The stop bit length is 1 ETU. + * | | |Note1: The default stop bit length is 2. SC and UART adopts NSB to program the stop bit length. + * | | |Note2: In UART mode, RX can receive the data sequence in 1 stop bit or 2 stop bits with NSB is set to 0. + * |[18:16] |RXRTY |RX Error Retry Count Number + * | | |This field indicates the maximum number of receiver retries that are allowed when parity error has occurred + * | | |Note1: The real retry number is RXRTY + 1, so 8 is the maximum retry number. + * | | |Note2: This field cannot be changed when RXRTYEN enabled + * | | |The change flow is to disable RXRTYEN first and then fill in new retry value. + * |[19] |RXRTYEN |RX Error Retry Enable Bit + * | | |This bit enables receiver retry function when parity error has occurred. + * | | |0 = RX error retry function Disabled. + * | | |1 = RX error retry function Enabled. + * | | |Note: User must fill in the RXRTY value before enabling this bit. + * |[22:20] |TXRTY |TX Error Retry Count Number + * | | |This field indicates the maximum number of transmitter retries that are allowed when parity error has occurred. + * | | |Note1: The real retry number is TXRTY + 1, so 8 is the maximum retry number. + * | | |Note2: This field cannot be changed when TXRTYEN enabled + * | | |The change flow is to disable TXRTYEN first and then fill in new retry value. + * |[23] |TXRTYEN |TX Error Retry Enable Bit + * | | |This bit enables transmitter retry function when parity error has occurred. + * | | |0 = TX error retry function Disabled. + * | | |1 = TX error retry function Enabled. + * |[25:24] |CDDBSEL |Card Detect De-bounce Selection + * | | |This field indicates the card detect de-bounce selection. + * | | |00 = De-bounce sample card insert once per 384 (128 * 3) SC module clocks and de-bounce sample card removal once per 128 SC module clocks. + * | | |Other configurations are reserved. + * |[26] |CDLV |Card Detect Level Selection + * | | |0 = When hardware detects the card detect pin (SCn_CD) from high to low, it indicates a card is detected. + * | | |1 = When hardware detects the card detect pin (SCn_CD) from low to high, it indicates a card is detected. + * | | |Note: User must select card detect level before Smart Card controller enabled. + * |[30] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, user should check this bit before writing a new value to RXRTY and TXRTY fields. + * | | |0 = Synchronizing is completion, user can write new data to RXRTY and TXRTY. + * | | |1 = Last value is synchronizing. + * @var SC_T::ALTCTL + * Offset: 0x08 SC Alternate Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TXRST |TX Software Reset + * | | |When TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared. + * | | |0 = No effect. + * | | |1 = Reset the TX internal state machine and pointers. + * | | |Note: This bit will be auto cleared after reset is complete. + * |[1] |RXRST |Rx Software Reset + * | | |When RXRST is set, all the bytes in the receive buffer and Rx internal state machine will be cleared. + * | | |0 = No effect. + * | | |1 = Reset the Rx internal state machine and pointers. + * | | |Note: This bit will be auto cleared after reset is complete. + * |[2] |DACTEN |Deactivation Sequence Generator Enable Bit + * | | |This bit enables SC controller to initiate the card by deactivation sequence. + * | | |0 = No effect. + * | | |1 = Deactivation sequence generator Enabled. + * | | |Note1: When the deactivation sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1. + * | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]) + * | | |Thus, do not fill in this bit DACTEN, TXRST and RXRST at the same time. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. + * |[3] |ACTEN |Activation Sequence Generator Enable Bit + * | | |This bit enables SC controller to initiate the card by activation sequence. + * | | |0 = No effect. + * | | |1 = Activation sequence generator Enabled. + * | | |Note1: When the activation sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1. + * | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]) + * | | |Thus, do not fill in this bit ACTEN, TXRST and RXRST at the same time. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. + * | | |Note4: During the activation sequence, RX is disabled automatically and can not receive data + * | | |After the activation sequence completion, RXOFF (SCn_CTL[1]) keeps the state before hardware activation. + * |[4] |WARSTEN |Warm Reset Sequence Generator Enable Bit + * | | |This bit enables SC controller to initiate the card by warm reset sequence. + * | | |0 = No effect. + * | | |1 = Warm reset sequence generator Enabled. + * | | |Note1: When the warm reset sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1. + * | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]) + * | | |Thus, do not fill in this bit WARSTEN, TXRST and RXRST at the same time. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. + * | | |Note4: During the warm reset sequence, RX is disabled automatically and can not receive data + * | | |After the warm reset sequence completion, RXOFF (SCn_CTL[1]) keeps the state before perform warm reset sequence. + * |[5] |CNTEN0 |Internal Timer0 Start Enable Bit + * | | |This bit enables Timer 0 to start counting + * | | |User can fill 0 to stop it and set 1 to reload and count + * | | |The counter unit is ETU base. + * | | |0 = Stops counting. + * | | |1 = Start counting. + * | | |Note1: This field is used for internal 24 bit timer when TMRSEL (SCn_CTL[14:13]) is 11 only. + * | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL0[26] = 0), this bit will be auto-cleared by hardware. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. + * |[6] |CNTEN1 |Internal Timer1 Start Enable Bit + * | | |This bit enables Timer 1 to start counting + * | | |User can fill 0 to stop it and set 1 to reload and count + * | | |The counter unit is ETU base. + * | | |0 = Stops counting. + * | | |1 = Start counting. + * | | |Note1: This field is used for internal 8 bit timer when TMRSEL(SCn_CTL[14:13]) is 11 only + * | | |Do not fill CNTEN1 when TMRSEL (SCn_CTL[14:13]) is not equal to 11. + * | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL1[26] = 0), this bit will be auto-cleared by hardware. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. + * |[7] |CNTEN2 |Internal Timer2 Start Enable Bit + * | | |This bit enables Timer 2 to start counting + * | | |User can fill 0 to stop it and set 1 to reload and count + * | | |The counter unit is ETU base. + * | | |0 = Stops counting. + * | | |1 = Start counting. + * | | |Note1: This field is used for internal 8 bit timer when TMRSEL (SCn_CTL[14:13]) is 11 only + * | | |Do not fill in CNTEN2 when TMRSEL (SCn_CTL[14:13]) is not equal to 11. + * | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL2[26] = 0), this bit will be auto-cleared by hardware. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. + * |[9:8] |INITSEL |Initial Timing Selection + * | | |This fields indicates the initial timing of hardware activation, warm-reset or deactivation. + * | | |The unit of initial timing is SC module clock. + * | | |Activation: refer to SC Activation Sequence in Figure 7.14-54. + * | | |Warm-reset: refer to Warm-Reset Sequence in Figure 7.14-5. + * | | |Deactivation: refer to Deactivation Sequence in Figure 7.14-56. + * | | |Note: When set activation and warm reset in Timer0 operation mode 0011, it may have deviation at most 128 SC module clock cycles. + * |[11] |ADACEN |Auto Deactivation When Card Removal + * | | |This bit is used for enable hardware auto deactivation when smart card is removed. + * | | |0 = Auto deactivation Disabled. + * | | |1 = Auto deactivation Enabled. + * | | |Note: When the card is removed, hardware will stop any process and then do deactivation sequence if this bit is set + * | | |If auto deactivation process completes, hardware will set INITIF (SCn_INTSTS[8]) also. + * |[12] |RXBGTEN |Receiver Block Guard Time Function Enable Bit + * | | |This bit enables the receiver block guard time function. + * | | |0 = Receiver block guard time function Disabled. + * | | |1 = Receiver block guard time function Enabled. + * |[13] |ACTSTS0 |Internal Timer0 Active Status (Read Only) + * | | |This bit indicates the timer counter status of timer0. + * | | |0 = Timer0 is not active. + * | | |1 = Timer0 is active. + * | | |Note: Timer0 is active does not always mean timer0 is counting the CNT (SCn_TMRCTL0[23:0]). + * |[14] |ACTSTS1 |Internal Timer1 Active Status (Read Only) + * | | |This bit indicates the timer counter status of timer1. + * | | |0 = Timer1 is not active. + * | | |1 = Timer1 is active. + * | | |Note: Timer1 is active does not always mean timer1 is counting the CNT (SCn_TMRCTL1[7:0]). + * |[15] |ACTSTS2 |Internal Timer2 Active Status (Read Only) + * | | |This bit indicates the timer counter status of timer2. + * | | |0 = Timer2 is not active. + * | | |1 = Timer2 is active. + * | | |Note: Timer2 is active does not always mean timer2 is counting the CNT (SCn_TMRCTL2[7:0]). + * |[31] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, user should check this bit when writing a new value to SCn_ALTCTL register. + * | | |0 = Synchronizing is completion, user can write new data to SCn_ALTCTL register. + * | | |1 = Last value is synchronizing. + * @var SC_T::EGT + * Offset: 0x0C SC Extra Guard Time Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |EGT |Extra Guard Time + * | | |This field indicates the extra guard time value. + * | | |Note: The extra guard time unit is ETU base. + * @var SC_T::RXTOUT + * Offset: 0x10 SC Receive Buffer Time-out Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |RFTM |SC Receiver FIFO Time-out Counter + * | | |The time-out down counter resets and starts counting whenever the RX buffer received a new data + * | | |Once the counter decrease to 1 and no new data is received or CPU does not read data by reading SCn_DAT, a receiver time-out flag RXTOIF (SCn_INTSTS[9]) will be set, and hardware will generate an interrupt to CPU when RXTOIEN (SCn_INTEN[9]) is enabled. + * | | |Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5. + * | | |Note2: Filling in all 0 to this field indicates to disable this function. + * @var SC_T::ETUCTL + * Offset: 0x14 SC Element Time Unit Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |ETURDIV |ETU Rate Divider + * | | |The field is used for ETU clock rate divider. + * | | |The real ETU is ETURDIV + 1. + * | | |Note: User can configure this field, but this field must be greater than 0x04. + * @var SC_T::INTEN + * Offset: 0x18 SC Interrupt Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDAIEN |Receive Data Reach Interrupt Enable Bit + * | | |This field is used to enable received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt. + * | | |0 = Receive data reach trigger level interrupt Disabled. + * | | |1 = Receive data reach trigger level interrupt Enabled. + * |[1] |TBEIEN |Transmit Buffer Empty Interrupt Enable Bit + * | | |This field is used to enable transmit buffer empty interrupt. + * | | |0 = Transmit buffer empty interrupt Disabled. + * | | |1 = Transmit buffer empty interrupt Enabled. + * |[2] |TERRIEN |Transfer Error Interrupt Enable Bit + * | | |This field is used to enable transfer error interrupt + * | | |The transfer error states is at SCn_STATUS register which includes receiver break error BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5]), parity error PEF (SCn_STATUS[4]), receive buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), receiver retry over limit error RXOVERR (SCn_STATUS[22]) and transmitter retry over limit error TXOVERR (SCn_STATUS[30]). + * | | |0 = Transfer error interrupt Disabled. + * | | |1 = Transfer error interrupt Enabled. + * |[3] |TMR0IEN |Timer0 Interrupt Enable Bit + * | | |This field is used to enable Timer0 interrupt function. + * | | |0 = Timer0 interrupt Disabled. + * | | |1 = Timer0 interrupt Enabled. + * |[4] |TMR1IEN |Timer1 Interrupt Enable Bit + * | | |This field is used to enable the Timer1 interrupt function. + * | | |0 = Timer1 interrupt Disabled. + * | | |1 = Timer1 interrupt Enabled. + * |[5] |TMR2IEN |Timer2 Interrupt Enable Bit + * | | |This field is used to enable Timer2 interrupt function. + * | | |0 = Timer2 interrupt Disabled. + * | | |1 = Timer2 interrupt Enabled. + * |[6] |BGTIEN |Block Guard Time Interrupt Enable Bit + * | | |This field is used to enable block guard time interrupt in receive direction. + * | | |0 = Block guard time interrupt Disabled. + * | | |1 = Block guard time interrupt Enabled. + * | | |Note: This bit is valid only for receive direction block guard time. + * |[7] |CDIEN |Card Detect Interrupt Enable Bit + * | | |This field is used to enable card detect interrupt + * | | |The card detect status is CDPINSTS (SCn_STATUS[13]). + * | | |0 = Card detect interrupt Disabled. + * | | |1 = Card detect interrupt Enabled. + * |[8] |INITIEN |Initial End Interrupt Enable Bit + * | | |This field is used to enable activation (ACTEN (SCn_ALTCTL[3] = 1)), deactivation (DACTEN (SCn_ALTCTL[2] = 1)) and warm reset (WARSTEN (SCn_ALTCTL [4])) sequence complete interrupt. + * | | |0 = Initial end interrupt Disabled. + * | | |1 = Initial end interrupt Enabled. + * |[9] |RXTOIEN |Receiver Buffer Time-out Interrupt Enable Bit + * | | |This field is used to enable receiver buffer time-out interrupt. + * | | |0 = Receiver buffer time-out interrupt Disabled. + * | | |1 = Receiver buffer time-out interrupt Enabled. + * |[10] |ACERRIEN |Auto Convention Error Interrupt Enable Bit + * | | |This field is used to enable auto-convention error interrupt. + * | | |0 = Auto-convention error interrupt Disabled. + * | | |1 = Auto-convention error interrupt Enabled. + * @var SC_T::INTSTS + * Offset: 0x1C SC Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDAIF |Receive Data Reach Interrupt Status Flag (Read Only) + * | | |This field is used for received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt status flag. + * | | |0 = Number of receive buffer is less than RXTRGLV setting. + * | | |1 = Number of receive buffer data equals the RXTRGLV setting. + * | | |Note: This bit is read only + * | | |If user reads data from SCn_DAT and receiver buffer data byte number is less than RXTRGLV, this bit will be cleared automatically. + * |[1] |TBEIF |Transmit Buffer Empty Interrupt Status Flag (Read Only) + * | | |This field is used for transmit buffer empty interrupt status flag. + * | | |0 = Transmit buffer is not empty. + * | | |1 = Transmit buffer is empty. + * | | |Note: This bit is read only + * | | |If user wants to clear this bit, user must write data to DAT (SCn_DAT[7:0]) and then this bit will be cleared automatically. + * |[2] |TERRIF |Transfer Error Interrupt Status Flag + * | | |This field is used for transfer error interrupt status flag + * | | |The transfer error states is at SCn_STATUS register which includes receiver break error BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5], parity error PEF (SCn_STATUS[4] and receive buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), receiver retry over limit error RXOVERR (SCn_STATUS[22] or transmitter retry over limit error TXOVERR (SCn_STATUS[30]). + * | | |0 = Transfer error interrupt did not occur. + * | | |1 = Transfer error interrupt occurred. + * | | |Note1: This field is the status flag of BEF, FEF, PEF, RXOV, TXOV, RXOVERR or TXOVERR. + * | | |Note2: This bit can be cleared by writing 1 to it. + * |[3] |TMR0IF |Timer0 Interrupt Status Flag + * | | |This field is used for Timer0 interrupt status flag. + * | | |0 = Timer0 interrupt did not occur. + * | | |1 = Timer0 interrupt occurred. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[4] |TMR1IF |Timer1 Interrupt Status Flag + * | | |This field is used for Timer1 interrupt status flag. + * | | |0 = Timer1 interrupt did not occur. + * | | |1 = Timer1 interrupt occurred. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[5] |TMR2IF |Timer2 Interrupt Status Flag + * | | |This field is used for Timer2 interrupt status flag. + * | | |0 = Timer2 interrupt did not occur. + * | | |1 = Timer2 interrupt occurred. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[6] |BGTIF |Block Guard Time Interrupt Status Flag + * | | |This field is used for indicate block guard time interrupt status flag in receive direction. + * | | |0 = Block guard time interrupt did not occur. + * | | |1 = Block guard time interrupt occurred. + * | | |Note1: This bit is valid only when RXBGTEN (SCn_ALTCTL[12]) is enabled. + * | | |Note2: This bit can be cleared by writing 1 to it. + * |[7] |CDIF |Card Detect Interrupt Status Flag (Read Only) + * | | |This field is used for card detect interrupt status flag + * | | |The card detect status is CINSERT (SCn_STATUS[12]) and CREMOVE (SCn_STATUS[11]). + * | | |0 = Card detect event did not occur. + * | | |1 = Card detect event occurred. + * | | |Note: This bit is read only, user must to clear CINSERT or CREMOVE status to clear it. + * |[8] |INITIF |Initial End Interrupt Status Flag + * | | |This field is used for activation (ACTEN (SCn_ALTCTL[3])), deactivation (DACTEN (SCn_ALTCTL[2])) and warm reset (WARSTEN (SCn_ALTCTL[4])) sequence interrupt status flag. + * | | |0 = Initial sequence is not complete. + * | | |1 = Initial sequence is completed. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[9] |RXTOIF |Receive Buffer Time-out Interrupt Status Flag (Read Only) + * | | |This field is used for indicate receive buffer time-out interrupt status flag. + * | | |0 = Receive buffer time-out interrupt did not occur. + * | | |1 = Receive buffer time-out interrupt occurred. + * | | |Note: This bit is read only, user must read all receive buffer remaining data by reading SCn_DAT register to clear it. + * |[10] |ACERRIF |Auto Convention Error Interrupt Status Flag + * | | |This field indicates auto convention sequence error. + * | | |0 = Received TS at ATR state is 0x3B or 0x3F. + * | | |1 = Received TS at ATR state is neither 0x3B nor 0x3F. + * | | |Note: This bit can be cleared by writing 1 to it. + * @var SC_T::STATUS + * Offset: 0x20 SC Transfer Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXOV |Receive Overflow Error Status Flag + * | | |This bit is set when Rx buffer overflow. + * | | |0 = Rx buffer is not overflow. + * | | |1 = Rx buffer is overflow when the number of received bytes is greater than Rx buffer size (4 bytes). + * | | |Note: This bit can be cleared by writing 1 to it. + * |[1] |RXEMPTY |Receive Buffer Empty Status Flag (Read Only) + * | | |This bit indicates Rx buffer empty or not. + * | | |0 = Rx buffer is not empty. + * | | |1 = Rx buffer is empty, it means the last byte of Rx buffer has read from DAT (SCn_DAT[7:0]) by CPU. + * |[2] |RXFULL |Receive Buffer Full Status Flag (Read Only) + * | | |This bit indicates Rx buffer full or not. + * | | |0 = Rx buffer count is less than 4. + * | | |1 = Rx buffer count equals to 4. + * |[4] |PEF |Receiver Parity Error Status Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid "parity bit". + * | | |0 = Receiver parity error flag did not occur. + * | | |1 = Receiver parity error flag occurred. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. + * |[5] |FEF |Receiver Frame Error Status Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as logic 0). + * | | |0 = Receiver frame error flag did not occur. + * | | |1 = Receiver frame error flag occurred. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. + * |[6] |BEF |Receiver Break Error Status Flag + * | | |This bit is set to logic 1 whenever the received data input (Rx) held in the "spacing state" (logic 0) is longer than a full word transmission time (that is, the total time of "start bit" + "data bits" + "parity bit" + "stop bits"). + * | | |0 = Receiver break error flag did not occur. + * | | |1 = Receiver break error flag occurred. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. + * |[8] |TXOV |Transmit Overflow Error Interrupt Status Flag + * | | |This bit is set when Tx buffer overflow. + * | | |0 = Tx buffer is not overflow. + * | | |1 = Tx buffer is overflow when Tx buffer is full and an additional write operation to DAT (SCn_DAT[7:0]). + * | | |Note: This bit can be cleared by writing 1 to it. + * |[9] |TXEMPTY |Transmit Buffer Empty Status Flag (Read Only) + * | | |This bit indicates TX buffer empty or not. + * | | |0 = Tx buffer is not empty. + * | | |1 = Tx buffer is empty, it means the last byte of Tx buffer has been transferred to Transmitter Shift Register. + * | | |Note: This bit will be cleared when writing data into DAT (SCn_DAT[7:0]). + * |[10] |TXFULL |Transmit Buffer Full Status Flag (Read Only) + * | | |This bit indicates Tx buffer full or not. + * | | |0 = Tx buffer count is less than 4. + * | | |1 = Tx buffer count equals to 4. + * |[11] |CREMOVE |Card Removal Status of SCn_CD Pin + * | | |This bit is set whenever card has been removal. + * | | |0 = No effect. + * | | |1 = Card removed. + * | | |Note1: This bit can be cleared by writing "1" to it. + * | | |Note2: Card detect function will start after SCEN (SCn_CTL[0]) set. + * |[12] |CINSERT |Card Insert Status of SCn_CD Pin + * | | |This bit is set whenever card has been inserted. + * | | |0 = No effect. + * | | |1 = Card insert. + * | | |Note1: This bit can be cleared by writing "1" to it. + * | | |Note2: The card detect function will start after SCEN (SCn_CTL[0]) set. + * |[13] |CDPINSTS |Card Detect Pin Status (Read Only) + * | | |This bit is the pin status of SCn_CD. + * | | |0 = The SCn_CD pin state at low. + * | | |1 = The SCn_CD pin state at high. + * |[18:16] |RXPOINT |Receive Buffer Pointer Status (Read Only) + * | | |This field indicates the Rx buffer pointer status + * | | |When SC controller receives one byte from external device, RXPOINT increases one + * | | |When one byte of Rx buffer is read by CPU, RXPOINT decreases one. + * |[21] |RXRERR |Receiver Retry Error + * | | |This bit is used for receiver error retry and set by hardware. + * | | |0 = No Rx retry transfer. + * | | |1 = Rx has any error and retries transfer. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2 This bit is a flag and cannot generate any interrupt to CPU. + * | | |Note3: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. + * |[22] |RXOVERR |Receiver over Retry Error + * | | |This bit is used for receiver retry counts over than retry number limitation. + * | | |0 = Receiver retries counts is less than RXRTY (SCn_CTL[18:16]) + 1. + * | | |1 = Receiver retries counts is equal or over than RXRTY (SCn_CTL[18:16]) + 1. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. + * |[23] |RXACT |Receiver in Active Status Flag (Read Only) + * | | |This bit indicates Rx transfer status. + * | | |0 = This bit is cleared automatically when Rx transfer is finished. + * | | |1 = This bit is set by hardware when Rx transfer is in active. + * |[26:24] |TXPOINT |Transmit Buffer Pointer Status (Read Only) + * | | |This field indicates the Tx buffer pointer status + * | | |When CPU writes data into SCn_DAT, TXPOINT increases one + * | | |When one byte of Tx buffer is transferred to transmitter shift register, TXPOINT decreases one. + * |[29] |TXRERR |Transmitter Retry Error + * | | |This bit is used for indicate transmitter error retry and set by hardware.. + * | | |0 = No Tx retry transfer. + * | | |1 = Tx has any error and retries transfer. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: This bit is a flag and cannot generate any interrupt to CPU. + * |[30] |TXOVERR |Transmitter over Retry Error + * | | |This bit is used for transmitter retry counts over than retry number limitation. + * | | |0 = Transmitter retries counts is less than TXRTY (SCn_CTL[22:20]) + 1. + * | | |1 = Transmitter retries counts is equal or over to TXRTY (SCn_CTL[22:20]) + 1. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[31] |TXACT |Transmit in Active Status Flag (Read Only) + * | | |This bit indicates Tx transmit status. + * | | |0 = This bit is cleared automatically when Tx transfer is finished or the last byte transmission has completed. + * | | |1 = Transmit is active and this bit is set by hardware when Tx transfer is in active and the STOP bit of the last byte has not been transmitted. + * @var SC_T::PINCTL + * Offset: 0x24 SC Pin Control State Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PWREN |SCn_PWR Pin Signal + * | | |User can set PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]) to decide SCn_PWR pin is in high or low level. + * | | |Write this field to drive SCn_PWR pin + * | | |Refer PWRINV (SCn_PINCTL[11]) description for programming SCn_PWR pin voltage level. + * | | |Read this field to get SCn_PWR signal status. + * | | |0 = SCn_PWR signal status is low. + * | | |1 = SCn_PWR signal status is high. + * | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically + * | | |Thus, do not fill in this field when operating in these modes. + * |[1] |RSTEN |SCn_RST Pin Signal + * | | |User can set RSTEN (SCn_PINCTL[1]) to decide SCn_RST pin is in high or low level. + * | | |Write this field to drive SCn_RST pin. + * | | |0 = Drive SCn_RST pin to low. + * | | |1 = Drive SCn_RST pin to high. + * | | |Read this field to get SCn_RST signal status. + * | | |0 = SCn_RST signal status is low. + * | | |1 = SCn_RST signal status is high. + * | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically + * | | |Thus, do not fill in this field when operating in these modes. + * |[6] |CLKKEEP |SC Clock Enable Bit + * | | |0 = SC clock generation Disabled. + * | | |1 = SC clock always keeps free running. + * | | |Note: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically + * | | |Thus, do not fill in this field when operating in these modes. + * |[9] |SCDATA |SCn_DATA Pin Signal + * | | |This bit is the signal status of SCn_DATA but user can drive SCn_DATA pin to high or low by setting this bit. + * | | |0 = Drive SCn_DATA pin to low. + * | | |1 = Drive SCn_DATA pin to high. + * | | |Read this field to get SCn_DATA signal status. + * | | |0 = SCn_DATA signal status is low. + * | | |1 = SCn_DATA signal status is high. + * | | |Note: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically + * | | |Thus, do not fill in this field when SC is in these modes. + * |[11] |PWRINV |SCn_PWR Pin Inverse + * | | |This bit is used for inverse the SCn_PWR pin. + * | | |There are four kinds of combination for SCn_PWR pin setting by PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]). + * | | |PWRINV (SCn_PINCTL[11]) is bit 1 and PWREN (SCn_PINCTL[0]) is bit 0 and all conditions as below list, + * | | |00 = SCn_PWR pin is 0. + * | | |01 = SCn_PWR pin is 1. + * | | |10 = SCn_PWR pin is 1. + * | | |11 = SCn_PWR pin is 0. + * | | |Note: User must select PWRINV (SCn_PINCTL[11]) before smart card is enabled by SCEN (SCn_CTL[0]). + * |[16] |DATASTS |SCn_DATA Pin Status (Read Only) + * | | |This bit is the pin status of SCn_DATA. + * | | |0 = The SCn_DATA pin status is low. + * | | |1 = The SCn_DATA pin status is high. + * |[17] |PWRSTS |SCn_PWR Pin Status (Read Only) + * | | |This bit is the pin status of SCn_PWR. + * | | |0 = SCn_PWR pin to low. + * | | |1 = SCn_PWR pin to high. + * |[18] |RSTSTS |SCn_RST Pin Status (Read Only) + * | | |This bit is the pin status of SCn_RST. + * | | |0 = SCn_RST pin is low. + * | | |1 = SCn_RST pin is high. + * |[30] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, user should check this bit when writing a new value to SCn_PINCTL register. + * | | |0 = Synchronizing is completion, user can write new data to SCn_PINCTL register. + * | | |1 = Last value is synchronizing. + * @var SC_T::TMRCTL0 + * Offset: 0x28 SC Internal Timer0 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CNT |Timer0 Counter Value + * | | |This field indicates the internal Timer0 counter values. + * | | |Note: Unit of Timer0 counter is ETU base. + * |[27:24] |OPMODE |Timer0 Operation Mode Selection + * | | |This field indicates the internal 24-bit Timer0 operation selection. + * | | |Refer to Table 7.14-3 for programming Timer0. + * |[31] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, user should check this bit when writing a new value to the SCn_TMRCTL0 register. + * | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL0 register. + * | | |1 = Last value is synchronizing. + * @var SC_T::TMRCTL1 + * Offset: 0x2C SC Internal Timer1 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |CNT |Timer 1 Counter Value + * | | |This field indicates the internal Timer1 counter values. + * | | |Note: Unit of Timer1 counter is ETU base. + * |[27:24] |OPMODE |Timer 1 Operation Mode Selection + * | | |This field indicates the internal 8-bit Timer1 operation selection. + * | | |Refer to Table 7.14-3 for programming Timer1. + * |[31] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, software should check this bit when writing a new value to SCn_TMRCTL1 register. + * | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL1 register. + * | | |1 = Last value is synchronizing. + * @var SC_T::TMRCTL2 + * Offset: 0x30 SC Internal Timer2 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |CNT |Timer 2 Counter Value + * | | |This field indicates the internal Timer2 counter values. + * | | |Note: Unit of Timer2 counter is ETU base. + * |[27:24] |OPMODE |Timer 2 Operation Mode Selection + * | | |This field indicates the internal 8-bit Timer2 operation selection + * | | |Refer to Table 7.14-3 for programming Timer2. + * |[31] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, user should check this bit when writing a new value to SCn_TMRCTL2 register. + * | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL2 register. + * | | |1 = Last value is synchronizing. + * @var SC_T::UARTCTL + * Offset: 0x34 SC UART Mode Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |UARTEN |UART Mode Enable Bit + * | | |Sets this bit to enable UART mode function. + * | | |0 = Smart Card mode. + * | | |1 = UART mode. + * | | |Note1: When operating in UART mode, user must set CONSEL (SCn_CTL[5:4]) = 00 and AUTOCEN (SCn_CTL[3]) = 0. + * | | |Note2: When operating in Smart Card mode, user must set UARTEN (SCn_UARTCTL[0]) = 0. + * | | |Note3: When UART mode is enabled, hardware will generate a reset to reset FIFO and internal state machine. + * |[5:4] |WLS |Word Length Selection + * | | |This field is used for select UART data length. + * | | |00 = Word length is 8 bits. + * | | |01 = Word length is 7 bits. + * | | |10 = Word length is 6 bits. + * | | |11 = Word length is 5 bits. + * | | |Note: In smart card mode, this WLS must be 00. + * |[6] |PBOFF |Parity Bit Disable Bit + * | | |Sets this bit is used for disable parity check function. + * | | |0 = Parity bit is generated or checked between the "last data word bit" and "stop bit" of the serial data. + * | | |1 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer. + * | | |Note: In smart card mode, this field must be 0 (default setting is with parity bit). + * |[7] |OPE |Odd Parity Enable Bit + * | | |This is used for odd/even parity selection. + * | | |0 = Even number of logic 1 are transmitted or check the data word and parity bits in receiving mode. + * | | |1 = Odd number of logic 1 are transmitted or check the data word and parity bits in receiving mode. + * | | |Note: This bit has effect only when PBOFF bit is 0. + * @var SC_T::ACTCTL + * Offset: 0x4C SC Activation Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |T1EXT |T1 Extend Time of Hardware Activation + * | | |This field provide the configurable cycles to extend the activation time T1 period. + * | | |The cycle scaling factor is 2048. + * | | |Extend cycles = (filled value * 2048) cycles. + * | | |Refer to SC activation sequence in Figure 7.14-4. + * | | |For example, + * | | |SCLK = 4MHz, each cycle = 0.25us,. + * | | |Filled 20 to this field + * | | |Extend time = 20 * 2048 * 0.25us = 10.24 ms. + * | | |Note: Setting 0 to this field conforms to the protocol ISO/IEC 7816-3 + */ + __IO uint32_t DAT; /*!< [0x0000] SC Receive/Transmit Holding Buffer Register */ + __IO uint32_t CTL; /*!< [0x0004] SC Control Register */ + __IO uint32_t ALTCTL; /*!< [0x0008] SC Alternate Control Register */ + __IO uint32_t EGT; /*!< [0x000c] SC Extra Guard Time Register */ + __IO uint32_t RXTOUT; /*!< [0x0010] SC Receive Buffer Time-out Counter Register */ + __IO uint32_t ETUCTL; /*!< [0x0014] SC Element Time Unit Control Register */ + __IO uint32_t INTEN; /*!< [0x0018] SC Interrupt Enable Control Register */ + __IO uint32_t INTSTS; /*!< [0x001c] SC Interrupt Status Register */ + __IO uint32_t STATUS; /*!< [0x0020] SC Transfer Status Register */ + __IO uint32_t PINCTL; /*!< [0x0024] SC Pin Control State Register */ + __IO uint32_t TMRCTL0; /*!< [0x0028] SC Internal Timer0 Control Register */ + __IO uint32_t TMRCTL1; /*!< [0x002c] SC Internal Timer1 Control Register */ + __IO uint32_t TMRCTL2; /*!< [0x0030] SC Internal Timer2 Control Register */ + __IO uint32_t UARTCTL; /*!< [0x0034] SC UART Mode Control Register */ + __I uint32_t RESERVE0[5]; + __IO uint32_t ACTCTL; /*!< [0x004c] SC Activation Control Register */ + __I uint32_t RESERVE1[1004]; + +} SC_T; + +/** + @addtogroup SC_CONST SC Bit Field Definition + Constant Definitions for SC Controller +@{ */ + +#define SC_DAT_DAT_Pos (0) /*!< SC_T::DAT: DAT Position */ +#define SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos) /*!< SC_T::DAT: DAT Mask */ + +#define SC_CTL_SCEN_Pos (0) /*!< SC_T::CTL: SCEN Position */ +#define SC_CTL_SCEN_Msk (0x1ul << SC_CTL_SCEN_Pos) /*!< SC_T::CTL: SCEN Mask */ + +#define SC_CTL_RXOFF_Pos (1) /*!< SC_T::CTL: RXOFF Position */ +#define SC_CTL_RXOFF_Msk (0x1ul << SC_CTL_RXOFF_Pos) /*!< SC_T::CTL: RXOFF Mask */ + +#define SC_CTL_TXOFF_Pos (2) /*!< SC_T::CTL: TXOFF Position */ +#define SC_CTL_TXOFF_Msk (0x1ul << SC_CTL_TXOFF_Pos) /*!< SC_T::CTL: TXOFF Mask */ + +#define SC_CTL_AUTOCEN_Pos (3) /*!< SC_T::CTL: AUTOCEN Position */ +#define SC_CTL_AUTOCEN_Msk (0x1ul << SC_CTL_AUTOCEN_Pos) /*!< SC_T::CTL: AUTOCEN Mask */ + +#define SC_CTL_CONSEL_Pos (4) /*!< SC_T::CTL: CONSEL Position */ +#define SC_CTL_CONSEL_Msk (0x3ul << SC_CTL_CONSEL_Pos) /*!< SC_T::CTL: CONSEL Mask */ + +#define SC_CTL_RXTRGLV_Pos (6) /*!< SC_T::CTL: RXTRGLV Position */ +#define SC_CTL_RXTRGLV_Msk (0x3ul << SC_CTL_RXTRGLV_Pos) /*!< SC_T::CTL: RXTRGLV Mask */ + +#define SC_CTL_BGT_Pos (8) /*!< SC_T::CTL: BGT Position */ +#define SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos) /*!< SC_T::CTL: BGT Mask */ + +#define SC_CTL_TMRSEL_Pos (13) /*!< SC_T::CTL: TMRSEL Position */ +#define SC_CTL_TMRSEL_Msk (0x3ul << SC_CTL_TMRSEL_Pos) /*!< SC_T::CTL: TMRSEL Mask */ + +#define SC_CTL_NSB_Pos (15) /*!< SC_T::CTL: NSB Position */ +#define SC_CTL_NSB_Msk (0x1ul << SC_CTL_NSB_Pos) /*!< SC_T::CTL: NSB Mask */ + +#define SC_CTL_RXRTY_Pos (16) /*!< SC_T::CTL: RXRTY Position */ +#define SC_CTL_RXRTY_Msk (0x7ul << SC_CTL_RXRTY_Pos) /*!< SC_T::CTL: RXRTY Mask */ + +#define SC_CTL_RXRTYEN_Pos (19) /*!< SC_T::CTL: RXRTYEN Position */ +#define SC_CTL_RXRTYEN_Msk (0x1ul << SC_CTL_RXRTYEN_Pos) /*!< SC_T::CTL: RXRTYEN Mask */ + +#define SC_CTL_TXRTY_Pos (20) /*!< SC_T::CTL: TXRTY Position */ +#define SC_CTL_TXRTY_Msk (0x7ul << SC_CTL_TXRTY_Pos) /*!< SC_T::CTL: TXRTY Mask */ + +#define SC_CTL_TXRTYEN_Pos (23) /*!< SC_T::CTL: TXRTYEN Position */ +#define SC_CTL_TXRTYEN_Msk (0x1ul << SC_CTL_TXRTYEN_Pos) /*!< SC_T::CTL: TXRTYEN Mask */ + +#define SC_CTL_CDDBSEL_Pos (24) /*!< SC_T::CTL: CDDBSEL Position */ +#define SC_CTL_CDDBSEL_Msk (0x3ul << SC_CTL_CDDBSEL_Pos) /*!< SC_T::CTL: CDDBSEL Mask */ + +#define SC_CTL_CDLV_Pos (26) /*!< SC_T::CTL: CDLV Position */ +#define SC_CTL_CDLV_Msk (0x1ul << SC_CTL_CDLV_Pos) /*!< SC_T::CTL: CDLV Mask */ + +#define SC_CTL_SYNC_Pos (30) /*!< SC_T::CTL: SYNC Position */ +#define SC_CTL_SYNC_Msk (0x1ul << SC_CTL_SYNC_Pos) /*!< SC_T::CTL: SYNC Mask */ + +#define SC_ALTCTL_TXRST_Pos (0) /*!< SC_T::ALTCTL: TXRST Position */ +#define SC_ALTCTL_TXRST_Msk (0x1ul << SC_ALTCTL_TXRST_Pos) /*!< SC_T::ALTCTL: TXRST Mask */ + +#define SC_ALTCTL_RXRST_Pos (1) /*!< SC_T::ALTCTL: RXRST Position */ +#define SC_ALTCTL_RXRST_Msk (0x1ul << SC_ALTCTL_RXRST_Pos) /*!< SC_T::ALTCTL: RXRST Mask */ + +#define SC_ALTCTL_DACTEN_Pos (2) /*!< SC_T::ALTCTL: DACTEN Position */ +#define SC_ALTCTL_DACTEN_Msk (0x1ul << SC_ALTCTL_DACTEN_Pos) /*!< SC_T::ALTCTL: DACTEN Mask */ + +#define SC_ALTCTL_ACTEN_Pos (3) /*!< SC_T::ALTCTL: ACTEN Position */ +#define SC_ALTCTL_ACTEN_Msk (0x1ul << SC_ALTCTL_ACTEN_Pos) /*!< SC_T::ALTCTL: ACTEN Mask */ + +#define SC_ALTCTL_WARSTEN_Pos (4) /*!< SC_T::ALTCTL: WARSTEN Position */ +#define SC_ALTCTL_WARSTEN_Msk (0x1ul << SC_ALTCTL_WARSTEN_Pos) /*!< SC_T::ALTCTL: WARSTEN Mask */ + +#define SC_ALTCTL_CNTEN0_Pos (5) /*!< SC_T::ALTCTL: CNTEN0 Position */ +#define SC_ALTCTL_CNTEN0_Msk (0x1ul << SC_ALTCTL_CNTEN0_Pos) /*!< SC_T::ALTCTL: CNTEN0 Mask */ + +#define SC_ALTCTL_CNTEN1_Pos (6) /*!< SC_T::ALTCTL: CNTEN1 Position */ +#define SC_ALTCTL_CNTEN1_Msk (0x1ul << SC_ALTCTL_CNTEN1_Pos) /*!< SC_T::ALTCTL: CNTEN1 Mask */ + +#define SC_ALTCTL_CNTEN2_Pos (7) /*!< SC_T::ALTCTL: CNTEN2 Position */ +#define SC_ALTCTL_CNTEN2_Msk (0x1ul << SC_ALTCTL_CNTEN2_Pos) /*!< SC_T::ALTCTL: CNTEN2 Mask */ + +#define SC_ALTCTL_INITSEL_Pos (8) /*!< SC_T::ALTCTL: INITSEL Position */ +#define SC_ALTCTL_INITSEL_Msk (0x3ul << SC_ALTCTL_INITSEL_Pos) /*!< SC_T::ALTCTL: INITSEL Mask */ + +#define SC_ALTCTL_ADACEN_Pos (11) /*!< SC_T::ALTCTL: ADACEN Position */ +#define SC_ALTCTL_ADACEN_Msk (0x1ul << SC_ALTCTL_ADACEN_Pos) /*!< SC_T::ALTCTL: ADACEN Mask */ + +#define SC_ALTCTL_RXBGTEN_Pos (12) /*!< SC_T::ALTCTL: RXBGTEN Position */ +#define SC_ALTCTL_RXBGTEN_Msk (0x1ul << SC_ALTCTL_RXBGTEN_Pos) /*!< SC_T::ALTCTL: RXBGTEN Mask */ + +#define SC_ALTCTL_ACTSTS0_Pos (13) /*!< SC_T::ALTCTL: ACTSTS0 Position */ +#define SC_ALTCTL_ACTSTS0_Msk (0x1ul << SC_ALTCTL_ACTSTS0_Pos) /*!< SC_T::ALTCTL: ACTSTS0 Mask */ + +#define SC_ALTCTL_ACTSTS1_Pos (14) /*!< SC_T::ALTCTL: ACTSTS1 Position */ +#define SC_ALTCTL_ACTSTS1_Msk (0x1ul << SC_ALTCTL_ACTSTS1_Pos) /*!< SC_T::ALTCTL: ACTSTS1 Mask */ + +#define SC_ALTCTL_ACTSTS2_Pos (15) /*!< SC_T::ALTCTL: ACTSTS2 Position */ +#define SC_ALTCTL_ACTSTS2_Msk (0x1ul << SC_ALTCTL_ACTSTS2_Pos) /*!< SC_T::ALTCTL: ACTSTS2 Mask */ + +#define SC_ALTCTL_SYNC_Pos (31) /*!< SC_T::ALTCTL: SYNC Position */ +#define SC_ALTCTL_SYNC_Msk (0x1ul << SC_ALTCTL_SYNC_Pos) /*!< SC_T::ALTCTL: SYNC Mask */ + +#define SC_EGT_EGT_Pos (0) /*!< SC_T::EGT: EGT Position */ +#define SC_EGT_EGT_Msk (0xfful << SC_EGT_EGT_Pos) /*!< SC_T::EGT: EGT Mask */ + +#define SC_RXTOUT_RFTM_Pos (0) /*!< SC_T::RXTOUT: RFTM Position */ +#define SC_RXTOUT_RFTM_Msk (0x1fful << SC_RXTOUT_RFTM_Pos) /*!< SC_T::RXTOUT: RFTM Mask */ + +#define SC_ETUCTL_ETURDIV_Pos (0) /*!< SC_T::ETUCTL: ETURDIV Position */ +#define SC_ETUCTL_ETURDIV_Msk (0xffful << SC_ETUCTL_ETURDIV_Pos) /*!< SC_T::ETUCTL: ETURDIV Mask */ + +#define SC_INTEN_RDAIEN_Pos (0) /*!< SC_T::INTEN: RDAIEN Position */ +#define SC_INTEN_RDAIEN_Msk (0x1ul << SC_INTEN_RDAIEN_Pos) /*!< SC_T::INTEN: RDAIEN Mask */ + +#define SC_INTEN_TBEIEN_Pos (1) /*!< SC_T::INTEN: TBEIEN Position */ +#define SC_INTEN_TBEIEN_Msk (0x1ul << SC_INTEN_TBEIEN_Pos) /*!< SC_T::INTEN: TBEIEN Mask */ + +#define SC_INTEN_TERRIEN_Pos (2) /*!< SC_T::INTEN: TERRIEN Position */ +#define SC_INTEN_TERRIEN_Msk (0x1ul << SC_INTEN_TERRIEN_Pos) /*!< SC_T::INTEN: TERRIEN Mask */ + +#define SC_INTEN_TMR0IEN_Pos (3) /*!< SC_T::INTEN: TMR0IEN Position */ +#define SC_INTEN_TMR0IEN_Msk (0x1ul << SC_INTEN_TMR0IEN_Pos) /*!< SC_T::INTEN: TMR0IEN Mask */ + +#define SC_INTEN_TMR1IEN_Pos (4) /*!< SC_T::INTEN: TMR1IEN Position */ +#define SC_INTEN_TMR1IEN_Msk (0x1ul << SC_INTEN_TMR1IEN_Pos) /*!< SC_T::INTEN: TMR1IEN Mask */ + +#define SC_INTEN_TMR2IEN_Pos (5) /*!< SC_T::INTEN: TMR2IEN Position */ +#define SC_INTEN_TMR2IEN_Msk (0x1ul << SC_INTEN_TMR2IEN_Pos) /*!< SC_T::INTEN: TMR2IEN Mask */ + +#define SC_INTEN_BGTIEN_Pos (6) /*!< SC_T::INTEN: BGTIEN Position */ +#define SC_INTEN_BGTIEN_Msk (0x1ul << SC_INTEN_BGTIEN_Pos) /*!< SC_T::INTEN: BGTIEN Mask */ + +#define SC_INTEN_CDIEN_Pos (7) /*!< SC_T::INTEN: CDIEN Position */ +#define SC_INTEN_CDIEN_Msk (0x1ul << SC_INTEN_CDIEN_Pos) /*!< SC_T::INTEN: CDIEN Mask */ + +#define SC_INTEN_INITIEN_Pos (8) /*!< SC_T::INTEN: INITIEN Position */ +#define SC_INTEN_INITIEN_Msk (0x1ul << SC_INTEN_INITIEN_Pos) /*!< SC_T::INTEN: INITIEN Mask */ + +#define SC_INTEN_RXTOIEN_Pos (9) /*!< SC_T::INTEN: RXTOIEN Position */ +#define SC_INTEN_RXTOIEN_Msk (0x1ul << SC_INTEN_RXTOIEN_Pos) /*!< SC_T::INTEN: RXTOIEN Mask */ + +#define SC_INTEN_ACERRIEN_Pos (10) /*!< SC_T::INTEN: ACERRIEN Position */ +#define SC_INTEN_ACERRIEN_Msk (0x1ul << SC_INTEN_ACERRIEN_Pos) /*!< SC_T::INTEN: ACERRIEN Mask */ + +#define SC_INTSTS_RDAIF_Pos (0) /*!< SC_T::INTSTS: RDAIF Position */ +#define SC_INTSTS_RDAIF_Msk (0x1ul << SC_INTSTS_RDAIF_Pos) /*!< SC_T::INTSTS: RDAIF Mask */ + +#define SC_INTSTS_TBEIF_Pos (1) /*!< SC_T::INTSTS: TBEIF Position */ +#define SC_INTSTS_TBEIF_Msk (0x1ul << SC_INTSTS_TBEIF_Pos) /*!< SC_T::INTSTS: TBEIF Mask */ + +#define SC_INTSTS_TERRIF_Pos (2) /*!< SC_T::INTSTS: TERRIF Position */ +#define SC_INTSTS_TERRIF_Msk (0x1ul << SC_INTSTS_TERRIF_Pos) /*!< SC_T::INTSTS: TERRIF Mask */ + +#define SC_INTSTS_TMR0IF_Pos (3) /*!< SC_T::INTSTS: TMR0IF Position */ +#define SC_INTSTS_TMR0IF_Msk (0x1ul << SC_INTSTS_TMR0IF_Pos) /*!< SC_T::INTSTS: TMR0IF Mask */ + +#define SC_INTSTS_TMR1IF_Pos (4) /*!< SC_T::INTSTS: TMR1IF Position */ +#define SC_INTSTS_TMR1IF_Msk (0x1ul << SC_INTSTS_TMR1IF_Pos) /*!< SC_T::INTSTS: TMR1IF Mask */ + +#define SC_INTSTS_TMR2IF_Pos (5) /*!< SC_T::INTSTS: TMR2IF Position */ +#define SC_INTSTS_TMR2IF_Msk (0x1ul << SC_INTSTS_TMR2IF_Pos) /*!< SC_T::INTSTS: TMR2IF Mask */ + +#define SC_INTSTS_BGTIF_Pos (6) /*!< SC_T::INTSTS: BGTIF Position */ +#define SC_INTSTS_BGTIF_Msk (0x1ul << SC_INTSTS_BGTIF_Pos) /*!< SC_T::INTSTS: BGTIF Mask */ + +#define SC_INTSTS_CDIF_Pos (7) /*!< SC_T::INTSTS: CDIF Position */ +#define SC_INTSTS_CDIF_Msk (0x1ul << SC_INTSTS_CDIF_Pos) /*!< SC_T::INTSTS: CDIF Mask */ + +#define SC_INTSTS_INITIF_Pos (8) /*!< SC_T::INTSTS: INITIF Position */ +#define SC_INTSTS_INITIF_Msk (0x1ul << SC_INTSTS_INITIF_Pos) /*!< SC_T::INTSTS: INITIF Mask */ + +#define SC_INTSTS_RXTOIF_Pos (9) /*!< SC_T::INTSTS: RXTOIF Position */ +#define SC_INTSTS_RXTOIF_Msk (0x1ul << SC_INTSTS_RXTOIF_Pos) /*!< SC_T::INTSTS: RXTOIF Mask */ + +#define SC_INTSTS_ACERRIF_Pos (10) /*!< SC_T::INTSTS: ACERRIF Position */ +#define SC_INTSTS_ACERRIF_Msk (0x1ul << SC_INTSTS_ACERRIF_Pos) /*!< SC_T::INTSTS: ACERRIF Mask */ + +#define SC_STATUS_RXOV_Pos (0) /*!< SC_T::STATUS: RXOV Position */ +#define SC_STATUS_RXOV_Msk (0x1ul << SC_STATUS_RXOV_Pos) /*!< SC_T::STATUS: RXOV Mask */ + +#define SC_STATUS_RXEMPTY_Pos (1) /*!< SC_T::STATUS: RXEMPTY Position */ +#define SC_STATUS_RXEMPTY_Msk (0x1ul << SC_STATUS_RXEMPTY_Pos) /*!< SC_T::STATUS: RXEMPTY Mask */ + +#define SC_STATUS_RXFULL_Pos (2) /*!< SC_T::STATUS: RXFULL Position */ +#define SC_STATUS_RXFULL_Msk (0x1ul << SC_STATUS_RXFULL_Pos) /*!< SC_T::STATUS: RXFULL Mask */ + +#define SC_STATUS_PEF_Pos (4) /*!< SC_T::STATUS: PEF Position */ +#define SC_STATUS_PEF_Msk (0x1ul << SC_STATUS_PEF_Pos) /*!< SC_T::STATUS: PEF Mask */ + +#define SC_STATUS_FEF_Pos (5) /*!< SC_T::STATUS: FEF Position */ +#define SC_STATUS_FEF_Msk (0x1ul << SC_STATUS_FEF_Pos) /*!< SC_T::STATUS: FEF Mask */ + +#define SC_STATUS_BEF_Pos (6) /*!< SC_T::STATUS: BEF Position */ +#define SC_STATUS_BEF_Msk (0x1ul << SC_STATUS_BEF_Pos) /*!< SC_T::STATUS: BEF Mask */ + +#define SC_STATUS_TXOV_Pos (8) /*!< SC_T::STATUS: TXOV Position */ +#define SC_STATUS_TXOV_Msk (0x1ul << SC_STATUS_TXOV_Pos) /*!< SC_T::STATUS: TXOV Mask */ + +#define SC_STATUS_TXEMPTY_Pos (9) /*!< SC_T::STATUS: TXEMPTY Position */ +#define SC_STATUS_TXEMPTY_Msk (0x1ul << SC_STATUS_TXEMPTY_Pos) /*!< SC_T::STATUS: TXEMPTY Mask */ + +#define SC_STATUS_TXFULL_Pos (10) /*!< SC_T::STATUS: TXFULL Position */ +#define SC_STATUS_TXFULL_Msk (0x1ul << SC_STATUS_TXFULL_Pos) /*!< SC_T::STATUS: TXFULL Mask */ + +#define SC_STATUS_CREMOVE_Pos (11) /*!< SC_T::STATUS: CREMOVE Position */ +#define SC_STATUS_CREMOVE_Msk (0x1ul << SC_STATUS_CREMOVE_Pos) /*!< SC_T::STATUS: CREMOVE Mask */ + +#define SC_STATUS_CINSERT_Pos (12) /*!< SC_T::STATUS: CINSERT Position */ +#define SC_STATUS_CINSERT_Msk (0x1ul << SC_STATUS_CINSERT_Pos) /*!< SC_T::STATUS: CINSERT Mask */ + +#define SC_STATUS_CDPINSTS_Pos (13) /*!< SC_T::STATUS: CDPINSTS Position */ +#define SC_STATUS_CDPINSTS_Msk (0x1ul << SC_STATUS_CDPINSTS_Pos) /*!< SC_T::STATUS: CDPINSTS Mask */ + +#define SC_STATUS_RXPOINT_Pos (16) /*!< SC_T::STATUS: RXPOINT Position */ +#define SC_STATUS_RXPOINT_Msk (0x7ul << SC_STATUS_RXPOINT_Pos) /*!< SC_T::STATUS: RXPOINT Mask */ + +#define SC_STATUS_RXRERR_Pos (21) /*!< SC_T::STATUS: RXRERR Position */ +#define SC_STATUS_RXRERR_Msk (0x1ul << SC_STATUS_RXRERR_Pos) /*!< SC_T::STATUS: RXRERR Mask */ + +#define SC_STATUS_RXOVERR_Pos (22) /*!< SC_T::STATUS: RXOVERR Position */ +#define SC_STATUS_RXOVERR_Msk (0x1ul << SC_STATUS_RXOVERR_Pos) /*!< SC_T::STATUS: RXOVERR Mask */ + +#define SC_STATUS_RXACT_Pos (23) /*!< SC_T::STATUS: RXACT Position */ +#define SC_STATUS_RXACT_Msk (0x1ul << SC_STATUS_RXACT_Pos) /*!< SC_T::STATUS: RXACT Mask */ + +#define SC_STATUS_TXPOINT_Pos (24) /*!< SC_T::STATUS: TXPOINT Position */ +#define SC_STATUS_TXPOINT_Msk (0x7ul << SC_STATUS_TXPOINT_Pos) /*!< SC_T::STATUS: TXPOINT Mask */ + +#define SC_STATUS_TXRERR_Pos (29) /*!< SC_T::STATUS: TXRERR Position */ +#define SC_STATUS_TXRERR_Msk (0x1ul << SC_STATUS_TXRERR_Pos) /*!< SC_T::STATUS: TXRERR Mask */ + +#define SC_STATUS_TXOVERR_Pos (30) /*!< SC_T::STATUS: TXOVERR Position */ +#define SC_STATUS_TXOVERR_Msk (0x1ul << SC_STATUS_TXOVERR_Pos) /*!< SC_T::STATUS: TXOVERR Mask */ + +#define SC_STATUS_TXACT_Pos (31) /*!< SC_T::STATUS: TXACT Position */ +#define SC_STATUS_TXACT_Msk (0x1ul << SC_STATUS_TXACT_Pos) /*!< SC_T::STATUS: TXACT Mask */ + +#define SC_PINCTL_PWREN_Pos (0) /*!< SC_T::PINCTL: PWREN Position */ +#define SC_PINCTL_PWREN_Msk (0x1ul << SC_PINCTL_PWREN_Pos) /*!< SC_T::PINCTL: PWREN Mask */ + +#define SC_PINCTL_RSTEN_Pos (1) /*!< SC_T::PINCTL: RSTEN Position */ +#define SC_PINCTL_RSTEN_Msk (0x1ul << SC_PINCTL_RSTEN_Pos) /*!< SC_T::PINCTL: RSTEN Mask */ + +#define SC_PINCTL_CLKKEEP_Pos (6) /*!< SC_T::PINCTL: CLKKEEP Position */ +#define SC_PINCTL_CLKKEEP_Msk (0x1ul << SC_PINCTL_CLKKEEP_Pos) /*!< SC_T::PINCTL: CLKKEEP Mask */ + +#define SC_PINCTL_SCDATA_Pos (9) /*!< SC_T::PINCTL: SCDATA Position */ +#define SC_PINCTL_SCDATA_Msk (0x1ul << SC_PINCTL_SCDATA_Pos) /*!< SC_T::PINCTL: SCDATA Mask */ + +#define SC_PINCTL_PWRINV_Pos (11) /*!< SC_T::PINCTL: PWRINV Position */ +#define SC_PINCTL_PWRINV_Msk (0x1ul << SC_PINCTL_PWRINV_Pos) /*!< SC_T::PINCTL: PWRINV Mask */ + +#define SC_PINCTL_DATASTS_Pos (16) /*!< SC_T::PINCTL: DATASTS Position */ +#define SC_PINCTL_DATASTS_Msk (0x1ul << SC_PINCTL_DATASTS_Pos) /*!< SC_T::PINCTL: DATASTS Mask */ + +#define SC_PINCTL_PWRSTS_Pos (17) /*!< SC_T::PINCTL: PWRSTS Position */ +#define SC_PINCTL_PWRSTS_Msk (0x1ul << SC_PINCTL_PWRSTS_Pos) /*!< SC_T::PINCTL: PWRSTS Mask */ + +#define SC_PINCTL_RSTSTS_Pos (18) /*!< SC_T::PINCTL: RSTSTS Position */ +#define SC_PINCTL_RSTSTS_Msk (0x1ul << SC_PINCTL_RSTSTS_Pos) /*!< SC_T::PINCTL: RSTSTS Mask */ + +#define SC_PINCTL_SYNC_Pos (30) /*!< SC_T::PINCTL: SYNC Position */ +#define SC_PINCTL_SYNC_Msk (0x1ul << SC_PINCTL_SYNC_Pos) /*!< SC_T::PINCTL: SYNC Mask */ + +#define SC_TMRCTL0_CNT_Pos (0) /*!< SC_T::TMRCTL0: CNT Position */ +#define SC_TMRCTL0_CNT_Msk (0xfffffful << SC_TMRCTL0_CNT_Pos) /*!< SC_T::TMRCTL0: CNT Mask */ + +#define SC_TMRCTL0_OPMODE_Pos (24) /*!< SC_T::TMRCTL0: OPMODE Position */ +#define SC_TMRCTL0_OPMODE_Msk (0xful << SC_TMRCTL0_OPMODE_Pos) /*!< SC_T::TMRCTL0: OPMODE Mask */ + +#define SC_TMRCTL0_SYNC_Pos (31) /*!< SC_T::TMRCTL0: SYNC Position */ +#define SC_TMRCTL0_SYNC_Msk (0x1ul << SC_TMRCTL0_SYNC_Pos) /*!< SC_T::TMRCTL0: SYNC Mask */ + +#define SC_TMRCTL1_CNT_Pos (0) /*!< SC_T::TMRCTL1: CNT Position */ +#define SC_TMRCTL1_CNT_Msk (0xfful << SC_TMRCTL1_CNT_Pos) /*!< SC_T::TMRCTL1: CNT Mask */ + +#define SC_TMRCTL1_OPMODE_Pos (24) /*!< SC_T::TMRCTL1: OPMODE Position */ +#define SC_TMRCTL1_OPMODE_Msk (0xful << SC_TMRCTL1_OPMODE_Pos) /*!< SC_T::TMRCTL1: OPMODE Mask */ + +#define SC_TMRCTL1_SYNC_Pos (31) /*!< SC_T::TMRCTL1: SYNC Position */ +#define SC_TMRCTL1_SYNC_Msk (0x1ul << SC_TMRCTL1_SYNC_Pos) /*!< SC_T::TMRCTL1: SYNC Mask */ + +#define SC_TMRCTL2_CNT_Pos (0) /*!< SC_T::TMRCTL2: CNT Position */ +#define SC_TMRCTL2_CNT_Msk (0xfful << SC_TMRCTL2_CNT_Pos) /*!< SC_T::TMRCTL2: CNT Mask */ + +#define SC_TMRCTL2_OPMODE_Pos (24) /*!< SC_T::TMRCTL2: OPMODE Position */ +#define SC_TMRCTL2_OPMODE_Msk (0xful << SC_TMRCTL2_OPMODE_Pos) /*!< SC_T::TMRCTL2: OPMODE Mask */ + +#define SC_TMRCTL2_SYNC_Pos (31) /*!< SC_T::TMRCTL2: SYNC Position */ +#define SC_TMRCTL2_SYNC_Msk (0x1ul << SC_TMRCTL2_SYNC_Pos) /*!< SC_T::TMRCTL2: SYNC Mask */ + +#define SC_UARTCTL_UARTEN_Pos (0) /*!< SC_T::UARTCTL: UARTEN Position */ +#define SC_UARTCTL_UARTEN_Msk (0x1ul << SC_UARTCTL_UARTEN_Pos) /*!< SC_T::UARTCTL: UARTEN Mask */ + +#define SC_UARTCTL_WLS_Pos (4) /*!< SC_T::UARTCTL: WLS Position */ +#define SC_UARTCTL_WLS_Msk (0x3ul << SC_UARTCTL_WLS_Pos) /*!< SC_T::UARTCTL: WLS Mask */ + +#define SC_UARTCTL_PBOFF_Pos (6) /*!< SC_T::UARTCTL: PBOFF Position */ +#define SC_UARTCTL_PBOFF_Msk (0x1ul << SC_UARTCTL_PBOFF_Pos) /*!< SC_T::UARTCTL: PBOFF Mask */ + +#define SC_UARTCTL_OPE_Pos (7) /*!< SC_T::UARTCTL: OPE Position */ +#define SC_UARTCTL_OPE_Msk (0x1ul << SC_UARTCTL_OPE_Pos) /*!< SC_T::UARTCTL: OPE Mask */ + +#define SC_ACTCTL_T1EXT_Pos (0) /*!< SC_T::ACTCTL: T1EXT Position */ +#define SC_ACTCTL_T1EXT_Msk (0x1ful << SC_ACTCTL_T1EXT_Pos) /*!< SC_T::ACTCTL: T1EXT Mask */ + +/**@}*/ /* SC_CONST */ +/**@}*/ /* end of SC register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __SC_REG_H__ */ \ No newline at end of file diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/spi_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/spi_reg.h new file mode 100644 index 00000000000..67f7cecbf40 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/spi_reg.h @@ -0,0 +1,838 @@ +/**************************************************************************//** + * @file spi_reg.h + * @version V1.00 + * @brief SPI register definition header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SPI_REG_H__ +#define __SPI_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup SPI Serial Peripheral Interface Controller (SPI) + Memory Mapped Structure for SPI Controller +@{ */ + +typedef struct +{ + + + /** + * @var SPI_T::CTL + * Offset: 0x00 SPI Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SPIEN |SPI Transfer Control Enable Bit + * | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1 + * | | |In Slave mode, this device is ready to receive data when this bit is set to 1. + * | | |0 = Transfer control Disabled. + * | | |1 = Transfer control Enabled. + * | | |Note: Before changing the configurations of SPIx_CTL, SPIx_CLKDIV, SPIx_SSCTL and SPIx_FIFOCTL registers, user shall clear the SPIEN (SPIx_CTL[0]) and confirm the SPIENSTS (SPIx_STATUS[15]) is 0. + * |[1] |RXNEG |Receive on Negative Edge + * | | |0 = Received data input signal is latched on the rising edge of SPI bus clock. + * | | |1 = Received data input signal is latched on the falling edge of SPI bus clock. + * |[2] |TXNEG |Transmit on Negative Edge + * | | |0 = Transmitted data output signal is changed on the rising edge of SPI bus clock. + * | | |1 = Transmitted data output signal is changed on the falling edge of SPI bus clock. + * |[3] |CLKPOL |Clock Polarity + * | | |0 = SPI bus clock is idle low. + * | | |1 = SPI bus clock is idle high. + * |[7:4] |SUSPITV |Suspend Interval (Master Only) + * | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer + * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word + * | | |The default value is 0x3 + * | | |The period of the suspend interval is obtained according to the following equation. + * | | |(SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle + * | | |Example: + * | | |SUSPITV = 0x0 u2026. 0.5 SPICLK clock cycle. + * | | |SUSPITV = 0x1 u2026. 1.5 SPICLK clock cycle. + * | | |u2026u2026 + * | | |SUSPITV = 0xE u2026. 14.5 SPICLK clock cycle. + * | | |SUSPITV = 0xF u2026. 15.5 SPICLK clock cycle. + * |[12:8] |DWIDTH |Data Width + * | | |This field specifies how many bits can be transmitted / received in one transaction + * | | |The minimum bit length is 8 bits and can up to 32 bits. + * | | |DWIDTH = 0x08 u2026. 8 bits. + * | | |DWIDTH = 0x09 u2026. 9 bits. + * | | |u2026u2026 + * | | |DWIDTH = 0x1F u2026. 31 bits. + * | | |DWIDTH = 0x00 u2026. 32 bits. + * | | |Note: For SPI1, this bit field will decide the depth of TX/RX FIFO configuration in SPI mode + * | | |Therefore, changing this bit field will clear TX/RX FIFO by hardware automatically in SPI1. + * |[13] |LSB |Send LSB First + * | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first. + * | | |1 = The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX). + * |[14] |HALFDPX |SPI Half-duplex Transfer Enable Bit + * | | |This bit is used to select full-duplex or half-duplex for SPI transfer + * | | |The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer. + * | | |0 = SPI operates in full-duplex transfer. + * | | |1 = SPI operates in half-duplex transfer. + * |[15] |RXONLY |Receive-only Mode Enable Bit (Master Only) + * | | |This bit field is only available in Master mode + * | | |In receive-only mode, SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status. + * | | |0 = Receive-only mode Disabled. + * | | |1 = Receive-only mode Enabled. + * |[16] |TWOBIT |2-bit Transfer Mode Enable Bit (Only Supported in SPI0) + * | | |0 = 2-bit Transfer mode Disabled. + * | | |1 = 2-bit Transfer mode Enabled. + * | | |Note: When 2-bit Transfer mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data + * | | |As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time. + * |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit + * | | |0 = SPI unit transfer interrupt Disabled. + * | | |1 = SPI unit transfer interrupt Enabled. + * |[18] |SLAVE |Slave Mode Control + * | | |0 = Master mode. + * | | |1 = Slave mode. + * |[19] |REORDER |Byte Reorder Function Enable Bit + * | | |0 = Byte Reorder function Disabled. + * | | |1 = Byte Reorder function Enabled + * | | |A byte suspend interval will be inserted among each byte + * | | |The period of the byte suspend interval depends on the setting of SUSPITV. + * | | |Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits. + * |[20] |DATDIR |Data Port Direction Control + * | | |This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer + * | | |0 = SPI data is input direction. + * | | |1 = SPI data is output direction. + * |[21] |DUALIOEN |Dual I/O Mode Enable Bit (Only Supported in SPI0) + * | | |0 = Dual I/O mode Disabled. + * | | |1 = Dual I/O mode Enabled. + * |[22] |QUADIOEN |Quad I/O Mode Enable Bit (Only Supported in SPI0) + * | | |0 = Quad I/O mode Disabled. + * | | |1 = Quad I/O mode Enabled. + * @var SPI_T::CLKDIV + * Offset: 0x04 SPI Clock Divider Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |DIVIDER |Clock Divider + * | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI Master + * | | |The frequency is obtained according to the following equation. + * | | |where + * | | |is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2. + * | | |Note: Not supported in I2S mode. + * @var SPI_T::SSCTL + * Offset: 0x08 SPI Slave Select Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SS |Slave Selection Control (Master Only) + * | | |If AUTOSS bit is cleared to 0, + * | | |0 = set the SPIx_SS line to inactive state. + * | | |1 = set the SPIx_SS line to active state. + * | | |If the AUTOSS bit is set to 1, + * | | |0 = Keep the SPIx_SS line at inactive state. + * | | |1 = SPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time + * | | |The active state of SPIx_SS is specified in SSACTPOL (SPIx_SSCTL[2]). + * |[2] |SSACTPOL |Slave Selection Active Polarity + * | | |This bit defines the active polarity of slave selection signal (SPIx_SS). + * | | |0 = The slave selection signal SPIx_SS is active low. + * | | |1 = The slave selection signal SPIx_SS is active high. + * |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit (Master Only) + * | | |0 = Automatic slave selection function Disabled + * | | |Slave selection signal will be asserted/de-asserted according to SS (SPIx_SSCTL[0]). + * | | |1 = Automatic slave selection function Enabled. + * |[4] |SLV3WIRE |Slave 3-wire Mode Enable Bit (Only Supported in SPI0) + * | | |Slave 3-wire mode is only available in SPI0 + * | | |In Slave 3-wire mode, the SPI controller can work with 3-wire interface including SPI0_CLK, SPI0_MISO and SPI0_MOSI pins. + * | | |0 = 4-wire bi-direction interface. + * | | |1 = 3-wire bi-direction interface. + * |[5] |SLVTOIEN |Slave Mode Time-out Interrupt Enable Bit (Only Supported in SPI0) + * | | |0 = Slave mode time-out interrupt Disabled. + * | | |1 = Slave mode time-out interrupt Enabled. + * |[6] |SLVTORST |Slave Mode Time-out Reset Control (Only Supported in SPI0) + * | | |0 = When Slave mode time-out event occurs, the TX and RX control circuit will not be reset. + * | | |1 = When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware. + * |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit + * | | |0 = Slave mode bit count error interrupt Disabled. + * | | |1 = Slave mode bit count error interrupt Enabled. + * |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit + * | | |0 = Slave mode TX under run interrupt Disabled. + * | | |1 = Slave mode TX under run interrupt Enabled. + * |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit + * | | |0 = Slave select active interrupt Disabled. + * | | |1 = Slave select active interrupt Enabled. + * |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit + * | | |0 = Slave select inactive interrupt Disabled. + * | | |1 = Slave select inactive interrupt Enabled. + * |[31:16] |SLVTOCNT |Slave Mode Time-out Period (Only Supported in SPI0) + * | | |In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active + * | | |The clock source of the time-out counter is Slave peripheral clock + * | | |If the value is 0, it indicates the slave mode time-out function is disabled. + * @var SPI_T::PDMACTL + * Offset: 0x0C SPI PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TXPDMAEN |Transmit PDMA Enable Bit + * | | |0 = Transmit PDMA function Disabled. + * | | |1 = Transmit PDMA function Enabled. + * | | |Note: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function + * | | |User can enable TX PDMA function firstly or enable both functions simultaneously. + * |[1] |RXPDMAEN |Receive PDMA Enable Bit + * | | |0 = Receive PDMA function Disabled. + * | | |1 = Receive PDMA function Enabled. + * |[2] |PDMARST |PDMA Reset + * | | |0 = No effect. + * | | |1 = Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0. + * @var SPI_T::FIFOCTL + * Offset: 0x10 SPI FIFO Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXRST |Receive Reset (Only for SPI) + * | | |0 = No effect. + * | | |1 = Reset receive FIFO pointer and receive circuit + * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 + * | | |User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not. + * |[1] |TXRST |Transmit Reset (Only for SPI) + * | | |0 = No effect. + * | | |1 = Reset transmit FIFO pointer and transmit circuit + * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 + * | | |User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not. + * | | |Note: If TX underflow event occurs in SPI Slave mode, this bit can be used to make SPI return to idle state. + * |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit + * | | |0 = RX FIFO threshold interrupt Disabled. + * | | |1 = RX FIFO threshold interrupt Enabled. + * |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit + * | | |0 = TX FIFO threshold interrupt Disabled. + * | | |1 = TX FIFO threshold interrupt Enabled. + * |[4] |RXTOIEN |Slave Receive Time-out Interrupt Enable Bit + * | | |0 = Receive time-out interrupt Disabled. + * | | |1 = Receive time-out interrupt Enabled. + * |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit + * | | |0 = Receive FIFO overrun interrupt Disabled. + * | | |1 = Receive FIFO overrun interrupt Enabled. + * |[6] |TXUFPOL |TX Underflow Data Polarity + * | | |0 = The SPI data out is keep 0 if there is TX underflow event in Slave mode. + * | | |1 = The SPI data out is keep 1 if there is TX underflow event in Slave mode. + * | | |Note: + * | | |1 + * | | |The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active. + * | | |2. This bit should be set as 0 in I2S mode. + * | | |3 + * | | |When TX underflow event occurs, SPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward + * | | |Data stored in TX FIFO will be sent through SPIx_MISO pin in the next transfer frame. + * |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit + * | | |When TX underflow event occurs in Slave mode, TXUFIF (SPIx_STATUS[19]) will be set to 1 + * | | |This bit is used to enable the TX underflow interrupt. + * | | |0 = Slave TX underflow interrupt Disabled. + * | | |1 = Slave TX underflow interrupt Enabled. + * |[8] |RXFBCLR |Receive FIFO Buffer Clear + * | | |0 = No effect. + * | | |1 = Clear receive FIFO pointer + * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. + * | | |Note: The RX shift register will not be cleared. + * |[9] |TXFBCLR |Transmit FIFO Buffer Clear + * | | |0 = No effect. + * | | |1 = Clear transmit FIFO pointer + * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. + * | | |Note: The TX shift register will not be cleared. + * |[26:24] |RXTH |Receive FIFO Threshold + * | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0 + * | | |For SPI1, the MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length. + * |[30:28] |TXTH |Transmit FIFO Threshold + * | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0 + * | | |For SPI1, the MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length + * @var SPI_T::STATUS + * Offset: 0x14 SPI Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |Busy Status (Read Only) + * | | |0 = SPI controller is in idle state. + * | | |1 = SPI controller is in busy state. + * | | |The following lists the bus busy conditions: + * | | |a. SPIx_CTL[0] = 1 and TXEMPTY = 0. + * | | |b + * | | |For SPI Master mode, SPIx_CTL[0] = 1 and TXEMPTY = 1 but the current transaction is not finished yet. + * | | |c. For SPI Master mode, SPIx_CTL[0] = 1 and RXONLY = 1. + * | | |d + * | | |For SPI Slave mode, the SPIx_CTL[0] = 1 and there is serial clock input into the SPI core logic when slave select is active. + * | | |For SPI Slave mode, the SPIx_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive. + * |[1] |UNITIF |Unit Transfer Interrupt Flag + * | | |0 = No transaction has been finished since this bit was cleared to 0. + * | | |1 = SPI controller has finished one unit transfer. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[2] |SSACTIF |Slave Select Active Interrupt Flag + * | | |0 = Slave select active interrupt was cleared or not occurred. + * | | |1 = Slave select active interrupt event occurred. + * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. + * |[3] |SSINAIF |Slave Select Inactive Interrupt Flag + * | | |0 = Slave select inactive interrupt was cleared or not occurred. + * | | |1 = Slave select inactive interrupt event occurred. + * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. + * |[4] |SSLINE |Slave Select Line Bus Status (Read Only) + * | | |0 = The slave select line status is 0. + * | | |1 = The slave select line status is 1. + * | | |Note: This bit is only available in Slave mode + * | | |If SSACTPOL (SPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status. + * |[5] |SLVTOIF |Slave Time-out Interrupt Flag (Only Supported in SPI0) + * | | |When the slave select is active and the value of SLVTOCNT is not 0, as the bus clock is detected, the slave time-out counter in SPI controller logic will be started + * | | |When the value of time-out counter is greater than or equal to the value of SLVTOCNT (SPI_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted. + * | | |0 = Slave time-out is not active. + * | | |1 = Slave time-out is active. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag + * | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1. + * | | |0 = No Slave mode bit count error event. + * | | |1 = Slave mode bit count error event occurred. + * | | |Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state + * | | |This bit will be cleared by writing 1 to it. + * |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag + * | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1. + * | | |0 = No Slave TX under run event. + * | | |1 = Slave TX under run event occurred. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not empty. + * | | |1 = Receive FIFO buffer is empty. + * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not full. + * | | |1 = Receive FIFO buffer is full. + * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH. + * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH. + * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag + * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. + * | | |0 = No FIFO is overrun. + * | | |1 = Receive FIFO is overrun. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[12] |RXTOIF |Receive Time-out Interrupt Flag + * | | |0 = No receive FIFO time-out event. + * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode + * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[15] |SPIENSTS |SPI Enable Status (Read Only) + * | | |0 = SPI controller Disabled. + * | | |1 = SPI controller Enabled. + * | | |Note: The SPI peripheral clock is asynchronous with the system clock + * | | |In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller. + * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not empty. + * | | |1 = Transmit FIFO buffer is empty. + * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not full. + * | | |1 = Transmit FIFO buffer is full. + * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH. + * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH. + * |[19] |TXUFIF |TX Underflow Interrupt Flag + * | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL. + * | | |0 = No effect. + * | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active. + * | | |Note 1: This bit will be cleared by writing 1 to it. + * | | |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done. + * |[23] |TXRXRST |TX or RX Reset Status (Read Only) + * | | |0 = The reset function of TXRST or RXRST is done. + * | | |1 = Doing the reset function of TXRST or RXRST. + * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles + * | | |User can check the status of this bit to monitor the reset function is doing or done. + * |[27:24] |RXCNT |Receive FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of receive FIFO buffer. + * |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of transmit FIFO buffer. + * @var SPI_T::TX + * Offset: 0x20 SPI Data Transmit Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TX |Data Transmit Register + * | | |The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers + * | | |The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S mode. + * | | |In SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted + * | | |If DWIDTH is set to 0x00, the SPI controller will perform a 32-bit transfer. + * | | |In I2S mode, if WDWIDTH (SPIx_I2SCTL[5:4]) is set to 0x2, the data width of audio channel is 24-bit and corresponding to TX[23:0] + * | | |If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid and referred to the data arrangement in I2S mode FIFO operation section + * | | |Note: In Master mode, SPI controller will start to transfer the SPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register. + * @var SPI_T::RX + * Offset: 0x30 SPI Data Receive Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RX |Data Receive Register + * | | |There are 4-level FIFO buffers in this controller + * | | |The data receive register holds the data received from SPI data input pin + * | | |If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register + * | | |This is a read only register. + * @var SPI_T::I2SCTL + * Offset: 0x60 I2S Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |I2SEN |I2S Controller Enable Bit + * | | |0 = Disabled I2S mode. + * | | |1 = Enabled I2S mode. + * | | |Note: + * | | |1. If enabling this bit, I2Sx_BCLK will start to output in Master mode. + * | | |2 + * | | |Before changing the configurations of SPIx_I2SCTL, SPIx_I2SCLK, and SPIx_FIFOCTL registers, user shall clear the I2SEN (SPIx_I2SCTL[0]) and confirm the I2SENSTS (SPIx_I2SSTS[15]) is 0. + * |[1] |TXEN |Transmit Enable Bit + * | | |0 = Data transmit Disabled. + * | | |1 = Data transmit Enabled. + * |[2] |RXEN |Receive Enable Bit + * | | |0 = Data receive Disabled. + * | | |1 = Data receive Enabled. + * |[3] |MUTE |Transmit Mute Enable Bit + * | | |0 = Transmit data is shifted from buffer. + * | | |1 = Transmit channel zero. + * |[5:4] |WDWIDTH |Word Width + * | | |00 = data size is 8-bit. + * | | |01 = data size is 16-bit. + * | | |10 = data size is 24-bit. + * | | |11 = data size is 32-bit. + * |[6] |MONO |Monaural Data + * | | |0 = Data is stereo format. + * | | |1 = Data is monaural format. + * |[7] |ORDER |Stereo Data Order in FIFO + * | | |0 = Left channel data at high byte. + * | | |1 = Left channel data at low byte. + * |[8] |SLAVE |Slave Mode + * | | |I2S can operate as master or slave + * | | |For Master mode, I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from this chip to audio CODEC chip + * | | |In Slave mode, I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and I2Sx_LRCLK signals are received from outer audio CODEC chip. + * | | |0 = Master mode. + * | | |1 = Slave mode. + * |[15] |MCLKEN |Master Clock Enable Bit + * | | |If MCLKEN is set to 1, I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices. + * | | |0 = Master clock Disabled. + * | | |1 = Master clock Enabled. + * |[16] |RZCEN |Right Channel Zero Cross Detection Enable Bit + * | | |If this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1 + * | | |This function is only available in transmit operation. + * | | |0 = Right channel zero cross detection Disabled. + * | | |1 = Right channel zero cross detection Enabled. + * |[17] |LZCEN |Left Channel Zero Cross Detection Enable Bit + * | | |If this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1 + * | | |This function is only available in transmit operation. + * | | |0 = Left channel zero cross detection Disabled. + * | | |1 = Left channel zero cross detection Enabled. + * |[23] |RXLCH |Receive Left Channel Enable Bit + * | | |When monaural format is selected (MONO = 1), I2S controller will receive right channel data if RXLCH is set to 0, and receive left channel data if RXLCH is set to 1. + * | | |0 = Receive right channel data in Mono mode. + * | | |1 = Receive left channel data in Mono mode. + * |[24] |RZCIEN |Right Channel Zero Cross Interrupt Enable Bit + * | | |Interrupt occurs if this bit is set to 1 and right channel zero cross event occurs. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[25] |LZCIEN |Left Channel Zero Cross Interrupt Enable Bit + * | | |Interrupt occurs if this bit is set to 1 and left channel zero cross event occurs. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[29:28] |FORMAT |Data Format Selection + * | | |00 = I2S data format. + * | | |01 = MSB justified data format. + * | | |10 = PCM mode A. + * | | |11 = PCM mode B. + * |[31] |SLVERRIEN |Bit Clock Loss Interrupt Enable Bit for Slave Mode + * | | |Interrupt occurs if this bit is set to 1 and bit clock loss event occurs. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * @var SPI_T::I2SCLK + * Offset: 0x64 I2S Clock Divider Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |MCLKDIV |Master Clock Divider + * | | |If MCLKEN is set to 1, I2S controller will generate master clock for external audio devices + * | | |The frequency of master clock, fMCLK, is determined by the following expressions: + * | | |If MCLKDIV >= 1,. + * | | |If MCLKDIV = 0,. + * | | |where + * | | |is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2 + * | | |In general, the master clock rate is 256 times sampling clock rate. + * |[17:8] |BCLKDIV |Bit Clock Divider + * | | |The I2S controller will generate bit clock in Master mode + * | | |The clock frequency of bit clock , fBCLK, is determined by the following expression: + * | | |where + * | | |is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2. + * | | |In I2S Slave mode, this field is used to define the frequency of peripheral clock and it's determined by . + * | | |The peripheral clock frequency in I2S Slave mode must be equal to or faster than 6 times of input bit clock. + * @var SPI_T::I2SSTS + * Offset: 0x68 I2S Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4] |RIGHT |Right Channel (Read Only) + * | | |This bit indicates the current transmit data is belong to which channel. + * | | |0 = Left channel. + * | | |1 = Right channel. + * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not empty. + * | | |1 = Receive FIFO buffer is empty. + * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not full. + * | | |1 = Receive FIFO buffer is full. + * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH. + * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH. + * | | |Note: If RXTHIEN = 1 and RXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request. + * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag + * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[12] |RXTOIF |Receive Time-out Interrupt Flag + * | | |0 = No receive FIFO time-out event. + * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock period in Master mode or over 576 SPI peripheral clock period in Slave mode + * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[15] |I2SENSTS |I2S Enable Status (Read Only) + * | | |0 = The SPI/I2S control logic is disabled. + * | | |1 = The SPI/I2S control logic is enabled. + * | | |Note: The SPI peripheral clock is asynchronous with the system clock + * | | |In order to make sure the SPI/I2S control logic is disabled, this bit indicates the real status of SPI/I2S control logic for user. + * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not empty. + * | | |1 = Transmit FIFO buffer is empty. + * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not full. + * | | |1 = Transmit FIFO buffer is full. + * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH. + * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH. + * | | |Note: If TXTHIEN = 1 and TXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request. + * |[19] |TXUFIF |Transmit FIFO Underflow Interrupt Flag + * | | |When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input, this bit will be set to 1. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[20] |RZCIF |Right Channel Zero Cross Interrupt Flag + * | | |0 = No zero cross event occurred on right channel. + * | | |1 = Zero cross event occurred on right channel. + * |[21] |LZCIF |Left Channel Zero Cross Interrupt Flag + * | | |0 = No zero cross event occurred on left channel. + * | | |1 = Zero cross event occurred on left channel. + * |[22] |SLVERRIF |Bit Clock Loss Interrupt Flag for Slave Mode + * | | |0 = No bit clock loss event occurred. + * | | |1 = Bit clock loss event occurred. + * | | |This bit will be cleared by writing 1 to it. + * |[23] |TXRXRST |TX or RX Reset Status (Read Only) + * | | |0 = The reset function of TXRST or RXRST is done. + * | | |1 = Doing the reset function of TXRST or RXRST. + * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles + * | | |User can check the status of this bit to monitor the reset function is doing or done. + * |[26:24] |RXCNT |Receive FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of receive FIFO buffer. + * |[30:28] |TXCNT |Transmit FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of transmit FIFO buffer. + */ + __IO uint32_t CTL; /*!< [0x0000] SPI Control Register */ + __IO uint32_t CLKDIV; /*!< [0x0004] SPI Clock Divider Register */ + __IO uint32_t SSCTL; /*!< [0x0008] SPI Slave Select Control Register */ + __IO uint32_t PDMACTL; /*!< [0x000c] SPI PDMA Control Register */ + __IO uint32_t FIFOCTL; /*!< [0x0010] SPI FIFO Control Register */ + __IO uint32_t STATUS; /*!< [0x0014] SPI Status Register */ + __I uint32_t RESERVE0[2]; + __O uint32_t TX; /*!< [0x0020] SPI Data Transmit Register */ + __I uint32_t RESERVE1[3]; + __I uint32_t RX; /*!< [0x0030] SPI Data Receive Register */ + __I uint32_t RESERVE2[11]; + __IO uint32_t I2SCTL; /*!< [0x0060] I2S Control Register */ + __IO uint32_t I2SCLK; /*!< [0x0064] I2S Clock Divider Control Register */ + __IO uint32_t I2SSTS; /*!< [0x0068] I2S Status Register */ + +} SPI_T; + +/** + @addtogroup SPI_CONST SPI Bit Field Definition + Constant Definitions for SPI Controller +@{ */ + +#define SPI_CTL_SPIEN_Pos (0) /*!< SPI_T::CTL: SPIEN Position */ +#define SPI_CTL_SPIEN_Msk (0x1ul << SPI_CTL_SPIEN_Pos) /*!< SPI_T::CTL: SPIEN Mask */ + +#define SPI_CTL_RXNEG_Pos (1) /*!< SPI_T::CTL: RXNEG Position */ +#define SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos) /*!< SPI_T::CTL: RXNEG Mask */ + +#define SPI_CTL_TXNEG_Pos (2) /*!< SPI_T::CTL: TXNEG Position */ +#define SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos) /*!< SPI_T::CTL: TXNEG Mask */ + +#define SPI_CTL_CLKPOL_Pos (3) /*!< SPI_T::CTL: CLKPOL Position */ +#define SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos) /*!< SPI_T::CTL: CLKPOL Mask */ + +#define SPI_CTL_SUSPITV_Pos (4) /*!< SPI_T::CTL: SUSPITV Position */ +#define SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos) /*!< SPI_T::CTL: SUSPITV Mask */ + +#define SPI_CTL_DWIDTH_Pos (8) /*!< SPI_T::CTL: DWIDTH Position */ +#define SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos) /*!< SPI_T::CTL: DWIDTH Mask */ + +#define SPI_CTL_LSB_Pos (13) /*!< SPI_T::CTL: LSB Position */ +#define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos) /*!< SPI_T::CTL: LSB Mask */ + +#define SPI_CTL_HALFDPX_Pos (14) /*!< SPI_T::CTL: HALFDPX Position */ +#define SPI_CTL_HALFDPX_Msk (0x1ul << SPI_CTL_HALFDPX_Pos) /*!< SPI_T::CTL: HALFDPX Mask */ + +#define SPI_CTL_RXONLY_Pos (15) /*!< SPI_T::CTL: RXONLY Position */ +#define SPI_CTL_RXONLY_Msk (0x1ul << SPI_CTL_RXONLY_Pos) /*!< SPI_T::CTL: RXONLY Mask */ + +#define SPI_CTL_UNITIEN_Pos (17) /*!< SPI_T::CTL: UNITIEN Position */ +#define SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos) /*!< SPI_T::CTL: UNITIEN Mask */ + +#define SPI_CTL_SLAVE_Pos (18) /*!< SPI_T::CTL: SLAVE Position */ +#define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos) /*!< SPI_T::CTL: SLAVE Mask */ + +#define SPI_CTL_REORDER_Pos (19) /*!< SPI_T::CTL: REORDER Position */ +#define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos) /*!< SPI_T::CTL: REORDER Mask */ + +#define SPI_CTL_DATDIR_Pos (20) /*!< SPI_T::CTL: DATDIR Position */ +#define SPI_CTL_DATDIR_Msk (0x1ul << SPI_CTL_DATDIR_Pos) /*!< SPI_T::CTL: DATDIR Mask */ + +#define SPI_CLKDIV_DIVIDER_Pos (0) /*!< SPI_T::CLKDIV: DIVIDER Position */ +#define SPI_CLKDIV_DIVIDER_Msk (0x1fful << SPI_CLKDIV_DIVIDER_Pos) /*!< SPI_T::CLKDIV: DIVIDER Mask */ + +#define SPI_SSCTL_SS_Pos (0) /*!< SPI_T::SSCTL: SS Position */ +#define SPI_SSCTL_SS_Msk (0x1ul << SPI_SSCTL_SS_Pos) /*!< SPI_T::SSCTL: SS Mask */ + +#define SPI_SSCTL_SSACTPOL_Pos (2) /*!< SPI_T::SSCTL: SSACTPOL Position */ +#define SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos) /*!< SPI_T::SSCTL: SSACTPOL Mask */ + +#define SPI_SSCTL_AUTOSS_Pos (3) /*!< SPI_T::SSCTL: AUTOSS Position */ +#define SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos) /*!< SPI_T::SSCTL: AUTOSS Mask */ + +#define SPI_SSCTL_SLVBEIEN_Pos (8) /*!< SPI_T::SSCTL: SLVBEIEN Position */ +#define SPI_SSCTL_SLVBEIEN_Msk (0x1ul << SPI_SSCTL_SLVBEIEN_Pos) /*!< SPI_T::SSCTL: SLVBEIEN Mask */ + +#define SPI_SSCTL_SLVURIEN_Pos (9) /*!< SPI_T::SSCTL: SLVURIEN Position */ +#define SPI_SSCTL_SLVURIEN_Msk (0x1ul << SPI_SSCTL_SLVURIEN_Pos) /*!< SPI_T::SSCTL: SLVURIEN Mask */ + +#define SPI_SSCTL_SSACTIEN_Pos (12) /*!< SPI_T::SSCTL: SSACTIEN Position */ +#define SPI_SSCTL_SSACTIEN_Msk (0x1ul << SPI_SSCTL_SSACTIEN_Pos) /*!< SPI_T::SSCTL: SSACTIEN Mask */ + +#define SPI_SSCTL_SSINAIEN_Pos (13) /*!< SPI_T::SSCTL: SSINAIEN Position */ +#define SPI_SSCTL_SSINAIEN_Msk (0x1ul << SPI_SSCTL_SSINAIEN_Pos) /*!< SPI_T::SSCTL: SSINAIEN Mask */ + +#define SPI_PDMACTL_TXPDMAEN_Pos (0) /*!< SPI_T::PDMACTL: TXPDMAEN Position */ +#define SPI_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos) /*!< SPI_T::PDMACTL: TXPDMAEN Mask */ + +#define SPI_PDMACTL_RXPDMAEN_Pos (1) /*!< SPI_T::PDMACTL: RXPDMAEN Position */ +#define SPI_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos) /*!< SPI_T::PDMACTL: RXPDMAEN Mask */ + +#define SPI_PDMACTL_PDMARST_Pos (2) /*!< SPI_T::PDMACTL: PDMARST Position */ +#define SPI_PDMACTL_PDMARST_Msk (0x1ul << SPI_PDMACTL_PDMARST_Pos) /*!< SPI_T::PDMACTL: PDMARST Mask */ + +#define SPI_FIFOCTL_RXRST_Pos (0) /*!< SPI_T::FIFOCTL: RXRST Position */ +#define SPI_FIFOCTL_RXRST_Msk (0x1ul << SPI_FIFOCTL_RXRST_Pos) /*!< SPI_T::FIFOCTL: RXRST Mask */ + +#define SPI_FIFOCTL_TXRST_Pos (1) /*!< SPI_T::FIFOCTL: TXRST Position */ +#define SPI_FIFOCTL_TXRST_Msk (0x1ul << SPI_FIFOCTL_TXRST_Pos) /*!< SPI_T::FIFOCTL: TXRST Mask */ + +#define SPI_FIFOCTL_RXTHIEN_Pos (2) /*!< SPI_T::FIFOCTL: RXTHIEN Position */ +#define SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos) /*!< SPI_T::FIFOCTL: RXTHIEN Mask */ + +#define SPI_FIFOCTL_TXTHIEN_Pos (3) /*!< SPI_T::FIFOCTL: TXTHIEN Position */ +#define SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos) /*!< SPI_T::FIFOCTL: TXTHIEN Mask */ + +#define SPI_FIFOCTL_RXTOIEN_Pos (4) /*!< SPI_T::FIFOCTL: RXTOIEN Position */ +#define SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos) /*!< SPI_T::FIFOCTL: RXTOIEN Mask */ + +#define SPI_FIFOCTL_RXOVIEN_Pos (5) /*!< SPI_T::FIFOCTL: RXOVIEN Position */ +#define SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos) /*!< SPI_T::FIFOCTL: RXOVIEN Mask */ + +#define SPI_FIFOCTL_TXUFPOL_Pos (6) /*!< SPI_T::FIFOCTL: TXUFPOL Position */ +#define SPI_FIFOCTL_TXUFPOL_Msk (0x1ul << SPI_FIFOCTL_TXUFPOL_Pos) /*!< SPI_T::FIFOCTL: TXUFPOL Mask */ + +#define SPI_FIFOCTL_TXUFIEN_Pos (7) /*!< SPI_T::FIFOCTL: TXUFIEN Position */ +#define SPI_FIFOCTL_TXUFIEN_Msk (0x1ul << SPI_FIFOCTL_TXUFIEN_Pos) /*!< SPI_T::FIFOCTL: TXUFIEN Mask */ + +#define SPI_FIFOCTL_RXFBCLR_Pos (8) /*!< SPI_T::FIFOCTL: RXFBCLR Position */ +#define SPI_FIFOCTL_RXFBCLR_Msk (0x1ul << SPI_FIFOCTL_RXFBCLR_Pos) /*!< SPI_T::FIFOCTL: RXFBCLR Mask */ + +#define SPI_FIFOCTL_TXFBCLR_Pos (9) /*!< SPI_T::FIFOCTL: TXFBCLR Position */ +#define SPI_FIFOCTL_TXFBCLR_Msk (0x1ul << SPI_FIFOCTL_TXFBCLR_Pos) /*!< SPI_T::FIFOCTL: TXFBCLR Mask */ + +#define SPI_FIFOCTL_RXTH_Pos (24) /*!< SPI_T::FIFOCTL: RXTH Position */ +#define SPI_FIFOCTL_RXTH_Msk (0x7ul << SPI_FIFOCTL_RXTH_Pos) /*!< SPI_T::FIFOCTL: RXTH Mask */ + +#define SPI_FIFOCTL_TXTH_Pos (28) /*!< SPI_T::FIFOCTL: TXTH Position */ +#define SPI_FIFOCTL_TXTH_Msk (0x7ul << SPI_FIFOCTL_TXTH_Pos) /*!< SPI_T::FIFOCTL: TXTH Mask */ + +#define SPI_STATUS_BUSY_Pos (0) /*!< SPI_T::STATUS: BUSY Position */ +#define SPI_STATUS_BUSY_Msk (0x1ul << SPI_STATUS_BUSY_Pos) /*!< SPI_T::STATUS: BUSY Mask */ + +#define SPI_STATUS_UNITIF_Pos (1) /*!< SPI_T::STATUS: UNITIF Position */ +#define SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos) /*!< SPI_T::STATUS: UNITIF Mask */ + +#define SPI_STATUS_SSACTIF_Pos (2) /*!< SPI_T::STATUS: SSACTIF Position */ +#define SPI_STATUS_SSACTIF_Msk (0x1ul << SPI_STATUS_SSACTIF_Pos) /*!< SPI_T::STATUS: SSACTIF Mask */ + +#define SPI_STATUS_SSINAIF_Pos (3) /*!< SPI_T::STATUS: SSINAIF Position */ +#define SPI_STATUS_SSINAIF_Msk (0x1ul << SPI_STATUS_SSINAIF_Pos) /*!< SPI_T::STATUS: SSINAIF Mask */ + +#define SPI_STATUS_SSLINE_Pos (4) /*!< SPI_T::STATUS: SSLINE Position */ +#define SPI_STATUS_SSLINE_Msk (0x1ul << SPI_STATUS_SSLINE_Pos) /*!< SPI_T::STATUS: SSLINE Mask */ + +#define SPI_STATUS_SLVBEIF_Pos (6) /*!< SPI_T::STATUS: SLVBEIF Position */ +#define SPI_STATUS_SLVBEIF_Msk (0x1ul << SPI_STATUS_SLVBEIF_Pos) /*!< SPI_T::STATUS: SLVBEIF Mask */ + +#define SPI_STATUS_SLVURIF_Pos (7) /*!< SPI_T::STATUS: SLVURIF Position */ +#define SPI_STATUS_SLVURIF_Msk (0x1ul << SPI_STATUS_SLVURIF_Pos) /*!< SPI_T::STATUS: SLVURIF Mask */ + +#define SPI_STATUS_RXEMPTY_Pos (8) /*!< SPI_T::STATUS: RXEMPTY Position */ +#define SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos) /*!< SPI_T::STATUS: RXEMPTY Mask */ + +#define SPI_STATUS_RXFULL_Pos (9) /*!< SPI_T::STATUS: RXFULL Position */ +#define SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos) /*!< SPI_T::STATUS: RXFULL Mask */ + +#define SPI_STATUS_RXTHIF_Pos (10) /*!< SPI_T::STATUS: RXTHIF Position */ +#define SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos) /*!< SPI_T::STATUS: RXTHIF Mask */ + +#define SPI_STATUS_RXOVIF_Pos (11) /*!< SPI_T::STATUS: RXOVIF Position */ +#define SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos) /*!< SPI_T::STATUS: RXOVIF Mask */ + +#define SPI_STATUS_RXTOIF_Pos (12) /*!< SPI_T::STATUS: RXTOIF Position */ +#define SPI_STATUS_RXTOIF_Msk (0x1ul << SPI_STATUS_RXTOIF_Pos) /*!< SPI_T::STATUS: RXTOIF Mask */ + +#define SPI_STATUS_SPIENSTS_Pos (15) /*!< SPI_T::STATUS: SPIENSTS Position */ +#define SPI_STATUS_SPIENSTS_Msk (0x1ul << SPI_STATUS_SPIENSTS_Pos) /*!< SPI_T::STATUS: SPIENSTS Mask */ + +#define SPI_STATUS_TXEMPTY_Pos (16) /*!< SPI_T::STATUS: TXEMPTY Position */ +#define SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos) /*!< SPI_T::STATUS: TXEMPTY Mask */ + +#define SPI_STATUS_TXFULL_Pos (17) /*!< SPI_T::STATUS: TXFULL Position */ +#define SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos) /*!< SPI_T::STATUS: TXFULL Mask */ + +#define SPI_STATUS_TXTHIF_Pos (18) /*!< SPI_T::STATUS: TXTHIF Position */ +#define SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos) /*!< SPI_T::STATUS: TXTHIF Mask */ + +#define SPI_STATUS_TXUFIF_Pos (19) /*!< SPI_T::STATUS: TXUFIF Position */ +#define SPI_STATUS_TXUFIF_Msk (0x1ul << SPI_STATUS_TXUFIF_Pos) /*!< SPI_T::STATUS: TXUFIF Mask */ + +#define SPI_STATUS_TXRXRST_Pos (23) /*!< SPI_T::STATUS: TXRXRST Position */ +#define SPI_STATUS_TXRXRST_Msk (0x1ul << SPI_STATUS_TXRXRST_Pos) /*!< SPI_T::STATUS: TXRXRST Mask */ + +#define SPI_STATUS_RXCNT_Pos (24) /*!< SPI_T::STATUS: RXCNT Position */ +#define SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos) /*!< SPI_T::STATUS: RXCNT Mask */ + +#define SPI_STATUS_TXCNT_Pos (28) /*!< SPI_T::STATUS: TXCNT Position */ +#define SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos) /*!< SPI_T::STATUS: TXCNT Mask */ + +#define SPI_TX_TX_Pos (0) /*!< SPI_T::TX: TX Position */ +#define SPI_TX_TX_Msk (0xfffffffful << SPI_TX_TX_Pos) /*!< SPI_T::TX: TX Mask */ + +#define SPI_RX_RX_Pos (0) /*!< SPI_T::RX: RX Position */ +#define SPI_RX_RX_Msk (0xfffffffful << SPI_RX_RX_Pos) /*!< SPI_T::RX: RX Mask */ + +#define SPI_I2SCTL_I2SEN_Pos (0) /*!< SPI_T::I2SCTL: I2SEN Position */ +#define SPI_I2SCTL_I2SEN_Msk (0x1ul << SPI_I2SCTL_I2SEN_Pos) /*!< SPI_T::I2SCTL: I2SEN Mask */ + +#define SPI_I2SCTL_TXEN_Pos (1) /*!< SPI_T::I2SCTL: TXEN Position */ +#define SPI_I2SCTL_TXEN_Msk (0x1ul << SPI_I2SCTL_TXEN_Pos) /*!< SPI_T::I2SCTL: TXEN Mask */ + +#define SPI_I2SCTL_RXEN_Pos (2) /*!< SPI_T::I2SCTL: RXEN Position */ +#define SPI_I2SCTL_RXEN_Msk (0x1ul << SPI_I2SCTL_RXEN_Pos) /*!< SPI_T::I2SCTL: RXEN Mask */ + +#define SPI_I2SCTL_MUTE_Pos (3) /*!< SPI_T::I2SCTL: MUTE Position */ +#define SPI_I2SCTL_MUTE_Msk (0x1ul << SPI_I2SCTL_MUTE_Pos) /*!< SPI_T::I2SCTL: MUTE Mask */ + +#define SPI_I2SCTL_WDWIDTH_Pos (4) /*!< SPI_T::I2SCTL: WDWIDTH Position */ +#define SPI_I2SCTL_WDWIDTH_Msk (0x3ul << SPI_I2SCTL_WDWIDTH_Pos) /*!< SPI_T::I2SCTL: WDWIDTH Mask */ + +#define SPI_I2SCTL_MONO_Pos (6) /*!< SPI_T::I2SCTL: MONO Position */ +#define SPI_I2SCTL_MONO_Msk (0x1ul << SPI_I2SCTL_MONO_Pos) /*!< SPI_T::I2SCTL: MONO Mask */ + +#define SPI_I2SCTL_ORDER_Pos (7) /*!< SPI_T::I2SCTL: ORDER Position */ +#define SPI_I2SCTL_ORDER_Msk (0x1ul << SPI_I2SCTL_ORDER_Pos) /*!< SPI_T::I2SCTL: ORDER Mask */ + +#define SPI_I2SCTL_SLAVE_Pos (8) /*!< SPI_T::I2SCTL: SLAVE Position */ +#define SPI_I2SCTL_SLAVE_Msk (0x1ul << SPI_I2SCTL_SLAVE_Pos) /*!< SPI_T::I2SCTL: SLAVE Mask */ + +#define SPI_I2SCTL_MCLKEN_Pos (15) /*!< SPI_T::I2SCTL: MCLKEN Position */ +#define SPI_I2SCTL_MCLKEN_Msk (0x1ul << SPI_I2SCTL_MCLKEN_Pos) /*!< SPI_T::I2SCTL: MCLKEN Mask */ + +#define SPI_I2SCTL_RZCEN_Pos (16) /*!< SPI_T::I2SCTL: RZCEN Position */ +#define SPI_I2SCTL_RZCEN_Msk (0x1ul << SPI_I2SCTL_RZCEN_Pos) /*!< SPI_T::I2SCTL: RZCEN Mask */ + +#define SPI_I2SCTL_LZCEN_Pos (17) /*!< SPI_T::I2SCTL: LZCEN Position */ +#define SPI_I2SCTL_LZCEN_Msk (0x1ul << SPI_I2SCTL_LZCEN_Pos) /*!< SPI_T::I2SCTL: LZCEN Mask */ + +#define SPI_I2SCTL_RXLCH_Pos (23) /*!< SPI_T::I2SCTL: RXLCH Position */ +#define SPI_I2SCTL_RXLCH_Msk (0x1ul << SPI_I2SCTL_RXLCH_Pos) /*!< SPI_T::I2SCTL: RXLCH Mask */ + +#define SPI_I2SCTL_RZCIEN_Pos (24) /*!< SPI_T::I2SCTL: RZCIEN Position */ +#define SPI_I2SCTL_RZCIEN_Msk (0x1ul << SPI_I2SCTL_RZCIEN_Pos) /*!< SPI_T::I2SCTL: RZCIEN Mask */ + +#define SPI_I2SCTL_LZCIEN_Pos (25) /*!< SPI_T::I2SCTL: LZCIEN Position */ +#define SPI_I2SCTL_LZCIEN_Msk (0x1ul << SPI_I2SCTL_LZCIEN_Pos) /*!< SPI_T::I2SCTL: LZCIEN Mask */ + +#define SPI_I2SCTL_FORMAT_Pos (28) /*!< SPI_T::I2SCTL: FORMAT Position */ +#define SPI_I2SCTL_FORMAT_Msk (0x3ul << SPI_I2SCTL_FORMAT_Pos) /*!< SPI_T::I2SCTL: FORMAT Mask */ + +#define SPI_I2SCTL_SLVERRIEN_Pos (31) /*!< SPI_T::I2SCTL: SLVERRIEN Position */ +#define SPI_I2SCTL_SLVERRIEN_Msk (0x1ul << SPI_I2SCTL_SLVERRIEN_Pos) /*!< SPI_T::I2SCTL: SLVERRIEN Mask */ + +#define SPI_I2SCLK_MCLKDIV_Pos (0) /*!< SPI_T::I2SCLK: MCLKDIV Position */ +#define SPI_I2SCLK_MCLKDIV_Msk (0x7ful << SPI_I2SCLK_MCLKDIV_Pos) /*!< SPI_T::I2SCLK: MCLKDIV Mask */ + +#define SPI_I2SCLK_BCLKDIV_Pos (8) /*!< SPI_T::I2SCLK: BCLKDIV Position */ +#define SPI_I2SCLK_BCLKDIV_Msk (0x3fful << SPI_I2SCLK_BCLKDIV_Pos) /*!< SPI_T::I2SCLK: BCLKDIV Mask */ + +#define SPI_I2SSTS_RIGHT_Pos (4) /*!< SPI_T::I2SSTS: RIGHT Position */ +#define SPI_I2SSTS_RIGHT_Msk (0x1ul << SPI_I2SSTS_RIGHT_Pos) /*!< SPI_T::I2SSTS: RIGHT Mask */ + +#define SPI_I2SSTS_RXEMPTY_Pos (8) /*!< SPI_T::I2SSTS: RXEMPTY Position */ +#define SPI_I2SSTS_RXEMPTY_Msk (0x1ul << SPI_I2SSTS_RXEMPTY_Pos) /*!< SPI_T::I2SSTS: RXEMPTY Mask */ + +#define SPI_I2SSTS_RXFULL_Pos (9) /*!< SPI_T::I2SSTS: RXFULL Position */ +#define SPI_I2SSTS_RXFULL_Msk (0x1ul << SPI_I2SSTS_RXFULL_Pos) /*!< SPI_T::I2SSTS: RXFULL Mask */ + +#define SPI_I2SSTS_RXTHIF_Pos (10) /*!< SPI_T::I2SSTS: RXTHIF Position */ +#define SPI_I2SSTS_RXTHIF_Msk (0x1ul << SPI_I2SSTS_RXTHIF_Pos) /*!< SPI_T::I2SSTS: RXTHIF Mask */ + +#define SPI_I2SSTS_RXOVIF_Pos (11) /*!< SPI_T::I2SSTS: RXOVIF Position */ +#define SPI_I2SSTS_RXOVIF_Msk (0x1ul << SPI_I2SSTS_RXOVIF_Pos) /*!< SPI_T::I2SSTS: RXOVIF Mask */ + +#define SPI_I2SSTS_RXTOIF_Pos (12) /*!< SPI_T::I2SSTS: RXTOIF Position */ +#define SPI_I2SSTS_RXTOIF_Msk (0x1ul << SPI_I2SSTS_RXTOIF_Pos) /*!< SPI_T::I2SSTS: RXTOIF Mask */ + +#define SPI_I2SSTS_I2SENSTS_Pos (15) /*!< SPI_T::I2SSTS: I2SENSTS Position */ +#define SPI_I2SSTS_I2SENSTS_Msk (0x1ul << SPI_I2SSTS_I2SENSTS_Pos) /*!< SPI_T::I2SSTS: I2SENSTS Mask */ + +#define SPI_I2SSTS_TXEMPTY_Pos (16) /*!< SPI_T::I2SSTS: TXEMPTY Position */ +#define SPI_I2SSTS_TXEMPTY_Msk (0x1ul << SPI_I2SSTS_TXEMPTY_Pos) /*!< SPI_T::I2SSTS: TXEMPTY Mask */ + +#define SPI_I2SSTS_TXFULL_Pos (17) /*!< SPI_T::I2SSTS: TXFULL Position */ +#define SPI_I2SSTS_TXFULL_Msk (0x1ul << SPI_I2SSTS_TXFULL_Pos) /*!< SPI_T::I2SSTS: TXFULL Mask */ + +#define SPI_I2SSTS_TXTHIF_Pos (18) /*!< SPI_T::I2SSTS: TXTHIF Position */ +#define SPI_I2SSTS_TXTHIF_Msk (0x1ul << SPI_I2SSTS_TXTHIF_Pos) /*!< SPI_T::I2SSTS: TXTHIF Mask */ + +#define SPI_I2SSTS_TXUFIF_Pos (19) /*!< SPI_T::I2SSTS: TXUFIF Position */ +#define SPI_I2SSTS_TXUFIF_Msk (0x1ul << SPI_I2SSTS_TXUFIF_Pos) /*!< SPI_T::I2SSTS: TXUFIF Mask */ + +#define SPI_I2SSTS_RZCIF_Pos (20) /*!< SPI_T::I2SSTS: RZCIF Position */ +#define SPI_I2SSTS_RZCIF_Msk (0x1ul << SPI_I2SSTS_RZCIF_Pos) /*!< SPI_T::I2SSTS: RZCIF Mask */ + +#define SPI_I2SSTS_LZCIF_Pos (21) /*!< SPI_T::I2SSTS: LZCIF Position */ +#define SPI_I2SSTS_LZCIF_Msk (0x1ul << SPI_I2SSTS_LZCIF_Pos) /*!< SPI_T::I2SSTS: LZCIF Mask */ + +#define SPI_I2SSTS_SLVERRIF_Pos (22) /*!< SPI_T::I2SSTS: SLVERRIF Position */ +#define SPI_I2SSTS_SLVERRIF_Msk (0x1ul << SPI_I2SSTS_SLVERRIF_Pos) /*!< SPI_T::I2SSTS: SLVERRIF Mask */ + +#define SPI_I2SSTS_TXRXRST_Pos (23) /*!< SPI_T::I2SSTS: TXRXRST Position */ +#define SPI_I2SSTS_TXRXRST_Msk (0x1ul << SPI_I2SSTS_TXRXRST_Pos) /*!< SPI_T::I2SSTS: TXRXRST Mask */ + +#define SPI_I2SSTS_RXCNT_Pos (24) /*!< SPI_T::I2SSTS: RXCNT Position */ +#define SPI_I2SSTS_RXCNT_Msk (0x7ul << SPI_I2SSTS_RXCNT_Pos) /*!< SPI_T::I2SSTS: RXCNT Mask */ + +#define SPI_I2SSTS_TXCNT_Pos (28) /*!< SPI_T::I2SSTS: TXCNT Position */ +#define SPI_I2SSTS_TXCNT_Msk (0x7ul << SPI_I2SSTS_TXCNT_Pos) /*!< SPI_T::I2SSTS: TXCNT Mask */ + +/**@}*/ /* SPI_CONST */ +/**@}*/ /* end of SPI register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __SPI_REG_H__ */ \ No newline at end of file diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/sys_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/sys_reg.h new file mode 100644 index 00000000000..7dc71f90498 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/sys_reg.h @@ -0,0 +1,2442 @@ +/**************************************************************************//** + * @file sys_reg.h + * @version V1.00 + * @brief SYS register definition header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SYS_REG_H__ +#define __SYS_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup SYS System Manger Controller (SYS) + Memory Mapped Structure for SYS Controller +@{ */ + +typedef struct +{ + + + /** + * @var SYS_T::PDID + * Offset: 0x00 Part Device Identification Number Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |PDID |Part Device Identification Number (Read Only) + * | | |This register reflects device part number code + * | | |Software can read this register to identify which device is used. + * @var SYS_T::RSTSTS + * Offset: 0x04 System Reset Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PORF |POR Reset Flag + * | | |The POR reset flag is set by the "Reset Signal" from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source. + * | | |0 = No reset from POR or CHIPRST. + * | | |1 = Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system. + * | | |Note: Write 1 to clear this bit to 0. + * |[1] |PINRF |NRESET Pin Reset Flag + * | | |The nRESET pin reset flag is set by the "Reset Signal" from the nRESET Pin to indicate the previous reset source. + * | | |0 = No reset from nRESET pin. + * | | |1 = Pin nRESET had issued the reset signal to reset the system. + * | | |Note: Write 1 to clear this bit to 0. + * |[2] |WDTRF |WDT Reset Flag + * | | |The WDT reset flag is set by the "Reset Signal" from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source. + * | | |0 = No reset from watchdog timer or window watchdog timer. + * | | |1 = The watchdog timer or window watchdog timer had issued the reset signal to reset the system. + * | | |Note1: Write 1 to clear this bit to 0. + * | | |Note2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset + * | | |Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset. + * |[3] |LVRF |LVR Reset Flag + * | | |The LVR reset flag is set by the "Reset Signal" from the Low Voltage Reset Controller to indicate the previous reset source. + * | | |0 = No reset from LVR. + * | | |1 = LVR controller had issued the reset signal to reset the system. + * | | |Note: Write 1 to clear this bit to 0. + * |[4] |BODRF |BOD Reset Flag + * | | |The BOD reset flag is set by the "Reset Signal" from the Brown-Out Detector to indicate the previous reset source. + * | | |0 = No reset from BOD. + * | | |1 = The BOD had issued the reset signal to reset the system. + * | | |Note: Write 1 to clear this bit to 0. + * |[5] |SYSRF |System Reset Flag + * | | |The system reset flag is set by the "Reset Signal" from the Cortex-M23 Core to indicate the previous reset source. + * | | |0 = No reset from Cortex-M23. + * | | |1 = The Cortex-M23 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M23 core. + * | | |Note: Write 1 to clear this bit to 0. + * |[6] |PMURF |PMU reset flag + * | | |The PMU reset flag is set by any reset signal when MCU is in power down state. + * | | |0 = No reset in power down state. + * | | |1 = Any reset signal happens in power down state. + * | | |Note: Write 1 to clear this bit to 0. + * |[7] |CPURF |CPU Reset Flag + * | | |The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M23 Core and Flash Memory Controller (FMC). + * | | |0 = No reset from CPU. + * | | |1 = The Cortex-M23 Core and FMC are reset by software setting CPURST to 1. + * | | |Note: Write to clear this bit to 0. + * |[8] |CPULKRF |CPU Lockup Reset Flag + * | | |0 = No reset from CPU lockup happened. + * | | |1 = The Cortex-M23 lockup happened and chip is reset. + * | | |Note: Write 1 to clear this bit to 0. + * | | |Note2: When CPU lockup happened under ICE is connected, This flag will set to 1 but chip will not reset. + * |[9] |VBATLVRF |VBAT LVR Reset Flag + * | | |The VBAT LVR reset flag is set by the “Reset Signal” from the VBAT Low Voltage Reset Controller to indicate the previous reset source. + * | | |0 = No reset from VBAT LVR. + * | | |1 = VBAT LVR controller had issued the reset signal to reset the system. + * | | |Note: Write 1 to clear this bit to 0. + * @var SYS_T::IPRST0 + * Offset: 0x08 Peripheral Reset Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CHIPRST |Chip One-shot Reset (Write Protect) + * | | |Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles. + * | | |The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload. + * | | |About the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 6.2.2 + * | | |0 = Chip normal operation. + * | | |1 = Chip one-shot reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[1] |CPURST |Processor Core One-shot Reset (Write Protect) + * | | |Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles. + * | | |0 = Processor core normal operation. + * | | |1 = Processor core one-shot reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[2] |PDMARST |PDMA Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the PDMA + * | | |User needs to set this bit to 0 to release from reset state. + * | | |0 = PDMA controller normal operation. + * | | |1 = PDMA controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[3] |EBIRST |EBI Controller Reset (Write Protect) + * | | |Set this bit to 1 will generate a reset signal to the EBI + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = EBI controller normal operation. + * | | |1 = EBI controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[7] |CRCRST |CRC Calculation Controller Reset (Write Protect) + * | | |Set this bit to 1 will generate a reset signal to the CRC calculation controller + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = CRC calculation controller normal operation. + * | | |1 = CRC calculation controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[12] |CRYPTRST |CRYPTO Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the CRYPTO controller + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = CRYPTO controller normal operation. + * | | |1 = CRYPTO controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var SYS_T::IPRST1 + * Offset: 0x0C Peripheral Reset Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |GPIORST |GPIO Controller Reset + * | | |0 = GPIO controller normal operation. + * | | |1 = GPIO controller reset. + * |[2] |TMR0RST |Timer0 Controller Reset + * | | |0 = Timer0 controller normal operation. + * | | |1 = Timer0 controller reset. + * |[3] |TMR1RST |Timer1 Controller Reset + * | | |0 = Timer1 controller normal operation. + * | | |1 = Timer1 controller reset. + * |[4] |TMR2RST |Timer2 Controller Reset + * | | |0 = Timer2 controller normal operation. + * | | |1 = Timer2 controller reset. + * |[5] |TMR3RST |Timer3 Controller Reset + * | | |0 = Timer3 controller normal operation. + * | | |1 = Timer3 controller reset. + * |[7] |ACMP01RST |Analog Comparator 0/1 Controller Reset + * | | |0 = Analog Comparator 0/1 controller normal operation. + * | | |1 = Analog Comparator 0/1 controller reset. + * |[8] |I2C0RST |I2C0 Controller Reset + * | | |0 = I2C0 controller normal operation. + * | | |1 = I2C0 controller reset. + * |[9] |I2C1RST |I2C1 Controller Reset + * | | |0 = I2C1 controller normal operation. + * | | |1 = I2C1 controller reset. + * |[12] |QSPI0RST |QSPI0 Controller Reset + * | | |0 = QSPI0 controller normal operation. + * | | |1 = QSPI0 controller reset. + * |[13] |SPI0RST |SPI0 Controller Reset + * | | |0 = SPI0 controller normal operation. + * | | |1 = SPI0 controller reset. + * |[16] |UART0RST |UART0 Controller Reset + * | | |0 = UART0 controller normal operation. + * | | |1 = UART0 controller reset. + * |[17] |UART1RST |UART1 Controller Reset + * | | |0 = UART1 controller normal operation. + * | | |1 = UART1 controller reset. + * |[18] |UART2RST |UART2 Controller Reset + * | | |0 = UART2 controller normal operation. + * | | |1 = UART2 controller reset. + * |[27] |USBDRST |USBD Controller Reset + * | | |0 = USBD controller normal operation. + * | | |1 = USBD controller reset. + * |[28] |EADCRST |EADC Controller Reset + * | | |0 = EADC controller normal operation. + * | | |1 = EADC controller reset. + * @var SYS_T::IPRST2 + * Offset: 0x10 Peripheral Reset Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SC0RST |SC0 Controller Reset + * | | |0 = SC0 controller normal operation. + * | | |1 = SC0 controller reset. + * |[8] |USCI0RST |USCI0 Controller Reset + * | | |0 = USCI0 controller normal operation. + * | | |1 = USCI0 controller reset. + * |[9] |USCI1RST |USCI1 Controller Reset + * | | |0 = USCI1 controller normal operation. + * | | |1 = USCI1 controller reset. + * |[10] |USCI2RST |USCI2 Controller Reset + * | | |0 = USCI2 controller normal operation. + * | | |1 = USCI2 controller reset. + * |[12] |DACRST |DAC Controller Reset + * | | |0 = DAC controller normal operation. + * | | |1 = DAC controller reset. + * |[16] |PWM0RST |PWM0 Controller Reset + * | | |0 = PWM0 controller normal operation. + * | | |1 = PWM0 controller reset. + * |[17] |PWM1RST |PWM1 Controller Reset + * | | |0 = PWM1 controller normal operation. + * | | |1 = PWM1 controller reset. + * |[18] |BPWM0RST |BPWM0 Controller Reset + * | | |0 = BPWM0 controller normal operation. + * | | |1 = BPWM0 controller reset. + * |[19] |BPWM1RST |BPWM1 Controller Reset + * | | |0 = BPWM1 controller normal operation. + * | | |1 = BPWM1 controller reset. + * |[30] |OPARST |OP Amplifier (OPA) Controller Reset + * | | |0 = OPA controller normal operation. + * | | |1 = OPA controller reset. + * |[31] |PSIORST |PSIORST + * @var SYS_T::BODCTL + * Offset: 0x18 Brown-out Detector Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BODEN |Brown-out Detector Enable Bit (Write Protect) + * | | |The default value is set by flash controller user configuration register CBODEN (CONFIG0 [19]). + * | | |0 = Brown-out Detector function Disabled. + * | | |1 = Brown-out Detector function Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[3] |BODRSTEN |Brown-out Reset Enable Bit (Write Protect) + * | | |The default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit . + * | | |0 = Brown-out "INTERRUPT" function Enabled. + * | | |1 = Brown-out "RESET" function Enabled. + * | | |Note1: + * | | |While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high). + * | | |While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high + * | | |BOD interrupt will keep till to the BODEN set to 0 + * | | |BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low). + * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[4] |BODIF |Brown-out Detector Interrupt Flag + * | | |0 = Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting. + * | | |1 = When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled. + * | | |Note: Write 1 to clear this bit to 0. + * |[5] |BODLPM |Brown-out Detector Low Power Mode (Write Protect) + * | | |0 = BOD operate in normal mode (default). + * | | |1 = BOD Low Power mode Enabled. + * | | |Note1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response. + * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[6] |BODOUT |Brown-out Detector Output Status + * | | |0 = Brown-out Detector output status is 0. + * | | |It means the detected voltage is higher than BODVL setting or BODEN is 0. + * | | |1 = Brown-out Detector output status is 1. + * | | |It means the detected voltage is lower than BODVL setting + * | | |If the BODEN is 0, BOD function disabled , this bit always responds 0000. + * |[7] |LVREN |Low Voltage Reset Enable Bit (Write Protect) + * | | |The LVR function resets the chip when the input power voltage is lower than LVR circuit setting + * | | |LVR function is enabled by default. + * | | |0 = Low Voltage Reset function Disabled. + * | | |1 = Low Voltage Reset function Enabled. + * | | |Note1: After enabling the bit, the LVR function will be active with 100us delay for LVR output stable (default). + * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[10:8] |BODDGSEL |Brown-out Detector Output De-glitch Time Select (Write Protect) + * | | |000 = BOD output is sampled by LIRC. + * | | |001 = 4 system clock (HCLK). + * | | |010 = 8 system clock (HCLK). + * | | |011 = 16 system clock (HCLK). + * | | |100 = 32 system clock (HCLK). + * | | |101 = 64 system clock (HCLK). + * | | |110 = 128 system clock (HCLK). + * | | |111 = 256 system clock (HCLK). + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[14:12] |LVRDGSEL |LVR Output De-glitch Time Select (Write Protect) + * | | |000 = Without de-glitch function. + * | | |001 = 4 MIRC clock (4.032 MHz), 1 us. + * | | |010 = 8 MIRC clock (4.032 MHz), 2 us. + * | | |011 = 16 MIRC clock (4.032 MHz), 4 us. + * | | |100 = 32 MIRC clock (4.032 MHz), 8 us. + * | | |101 = 64 MIRC clock (4.032 MHz), 16 us. + * | | |110 = 128 MIRC clock (4.032 MHz), 32 us. + * | | |111 = 256 MIRC clock (4.032 MHz), 64 us. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note: The MIRC enabled automatically when LVRDGSEL is not 000 and LVREN is 1. + * |[18:16] |BODVL |Brown-out Detector Threshold Voltage Selection (Write Protect) + * | | |The default value is set by flash controller user configuration register CBOV (CONFIG0 [23:21]). + * | | |000 = Reserved. + * | | |001 = Brown-Out Detector threshold voltage is 1.8V. + * | | |010 = Brown-Out Detector threshold voltage is 2.0V. + * | | |011 = Brown-Out Detector threshold voltage is 2.4V. + * | | |100 = Brown-Out Detector threshold voltage is 2.7V. + * | | |101 = Brown-Out Detector threshold voltage is 3.0V. + * | | |110 = Brown-Out Detector threshold voltage is 3.7V. + * | | |111 = Brown-Out Detector threshold voltage is 4.4V. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var SYS_T::IVSCTL + * Offset: 0x1C Internal Voltage Source Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |VTEMPEN |Temperature Sensor Enable Bit + * | | |This bit is used to enable/disable temperature sensor function. + * | | |0 = Temperature sensor function Disabled (default). + * | | |1 = Temperature sensor function Enabled. + * |[1] |VBATUGEN |VBAT Unity Gain Buffer Enable Bit + * | | |This bit is used to enable/disable VBAT unity gain buffer function. + * | | |0 = VBAT unity gain buffer function Disabled (default). + * | | |1 = VBAT unity gain buffer function Enabled. + * | | |Note: After this bit is set to 1, the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result + * @var SYS_T::PORCTL0 + * Offset: 0x24 Power-On-reset Controller Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PORMASK |Power-on Reset Enable Bit (Write Protect) + * | | |When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again + * | | |User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. + * | | |The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: + * | | |nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var SYS_T::VREFCTL + * Offset: 0x28 VREF Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |IVRS |Internal Voltage Reference Scale (Write Protect) + * | | |0 = Internal voltage reference(INT_VREF) set to 1.536V. + * | | |1 = Internal voltage reference(INT_VREF) set to 2.048V. + * | | |2 = Internal voltage reference(INT_VREF) set to 2.56V. + * | | |3 = Internal voltage reference(INT_VREF) set to 3.072V. + * | | |4 = Internal voltage reference(INT_VREF) set to 4.096V. + * | | |Others = Reserved. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[3] |IVREN |Internal Voltage Reference Module Enable(Write Protect) + * | | |0 = Internal voltage reference module is disabled. + * | | |1 = Internal voltage reference module is enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[10] |PRELOAD |1. Preload Active + * | | |2. Preload inactive + * @var SYS_T::GPA_MFPL + * Offset: 0x30 GPIOA Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PA0MFP |PA.0 Multi-function Pin Selection + * |[7:4] |PA1MFP |PA.1 Multi-function Pin Selection + * |[11:8] |PA2MFP |PA.2 Multi-function Pin Selection + * |[15:12] |PA3MFP |PA.3 Multi-function Pin Selection + * |[19:16] |PA4MFP |PA.4 Multi-function Pin Selection + * |[23:20] |PA5MFP |PA.5 Multi-function Pin Selection + * |[27:24] |PA6MFP |PA.6 Multi-function Pin Selection + * |[31:28] |PA7MFP |PA.7 Multi-function Pin Selection + * @var SYS_T::GPA_MFPH + * Offset: 0x34 GPIOA High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PA8MFP |PA.8 Multi-function Pin Selection + * |[7:4] |PA9MFP |PA.9 Multi-function Pin Selection + * |[11:8] |PA10MFP |PA.10 Multi-function Pin Selection + * |[15:12] |PA11MFP |PA.11 Multi-function Pin Selection + * |[19:16] |PA12MFP |PA.12 Multi-function Pin Selection + * |[23:20] |PA13MFP |PA.13 Multi-function Pin Selection + * |[27:24] |PA14MFP |PA.14 Multi-function Pin Selection + * |[31:28] |PA15MFP |PA.15 Multi-function Pin Selection + * @var SYS_T::GPB_MFPL + * Offset: 0x38 GPIOB Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PB0MFP |PB.0 Multi-function Pin Selection + * |[7:4] |PB1MFP |PB.1 Multi-function Pin Selection + * |[11:8] |PB2MFP |PB.2 Multi-function Pin Selection + * |[15:12] |PB3MFP |PB.3 Multi-function Pin Selection + * |[19:16] |PB4MFP |PB.4 Multi-function Pin Selection + * |[23:20] |PB5MFP |PB.5 Multi-function Pin Selection + * |[27:24] |PB6MFP |PB.6 Multi-function Pin Selection + * |[31:28] |PB7MFP |PB.7 Multi-function Pin Selection + * @var SYS_T::GPB_MFPH + * Offset: 0x3C GPIOB High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PB8MFP |PB.8 Multi-function Pin Selection + * |[7:4] |PB9MFP |PB.9 Multi-function Pin Selection + * |[11:8] |PB10MFP |PB.10 Multi-function Pin Selection + * |[15:12] |PB11MFP |PB.11 Multi-function Pin Selection + * |[19:16] |PB12MFP |PB.12 Multi-function Pin Selection + * |[23:20] |PB13MFP |PB.13 Multi-function Pin Selection + * |[27:24] |PB14MFP |PB.14 Multi-function Pin Selection + * |[31:28] |PB15MFP |PB.15 Multi-function Pin Selection + * @var SYS_T::GPC_MFPL + * Offset: 0x40 GPIOC Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PC0MFP |PC.0 Multi-function Pin Selection + * |[7:4] |PC1MFP |PC.1 Multi-function Pin Selection + * |[11:8] |PC2MFP |PC.2 Multi-function Pin Selection + * |[15:12] |PC3MFP |PC.3 Multi-function Pin Selection + * |[19:16] |PC4MFP |PC.4 Multi-function Pin Selection + * |[23:20] |PC5MFP |PC.5 Multi-function Pin Selection + * |[27:24] |PC6MFP |PC.6 Multi-function Pin Selection + * |[31:28] |PC7MFP |PC.7 Multi-function Pin Selection + * @var SYS_T::GPC_MFPH + * Offset: 0x44 GPIOC High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PC8MFP |PC.8 Multi-function Pin Selection + * |[7:4] |PC9MFP |PC.9 Multi-function Pin Selection + * |[11:8] |PC10MFP |PC.10 Multi-function Pin Selection + * |[15:12] |PC11MFP |PC.11 Multi-function Pin Selection + * |[19:16] |PC12MFP |PC.12 Multi-function Pin Selection + * |[23:20] |PC13MFP |PC.13 Multi-function Pin Selection + * |[27:24] |PC14MFP |PC.14 Multi-function Pin Selection + * |[31:28] |PC15MFP |PC.15 Multi-function Pin Selection + * @var SYS_T::GPD_MFPL + * Offset: 0x48 GPIOD Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PD0MFP |PD.0 Multi-function Pin Selection + * |[7:4] |PD1MFP |PD.1 Multi-function Pin Selection + * |[11:8] |PD2MFP |PD.2 Multi-function Pin Selection + * |[15:12] |PD3MFP |PD.3 Multi-function Pin Selection + * |[19:16] |PD4MFP |PD.4 Multi-function Pin Selection + * |[23:20] |PD5MFP |PD.5 Multi-function Pin Selection + * |[27:24] |PD6MFP |PD.6 Multi-function Pin Selection + * |[31:28] |PD7MFP |PD.7 Multi-function Pin Selection + * @var SYS_T::GPD_MFPH + * Offset: 0x4C GPIOD High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PD8MFP |PD.8 Multi-function Pin Selection + * |[7:4] |PD9MFP |PD.9 Multi-function Pin Selection + * |[11:8] |PD10MFP |PD.10 Multi-function Pin Selection + * |[15:12] |PD11MFP |PD.11 Multi-function Pin Selection + * |[19:16] |PD12MFP |PD.12 Multi-function Pin Selection + * |[23:20] |PD13MFP |PD.13 Multi-function Pin Selection + * |[27:24] |PD14MFP |PD.14 Multi-function Pin Selection + * |[31:28] |PD15MFP |PD.15 Multi-function Pin Selection + * @var SYS_T::GPE_MFPL + * Offset: 0x50 GPIOE Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PE0MFP |PE.0 Multi-function Pin Selection + * |[7:4] |PE1MFP |PE.1 Multi-function Pin Selection + * |[11:8] |PE2MFP |PE.2 Multi-function Pin Selection + * |[15:12] |PE3MFP |PE.3 Multi-function Pin Selection + * |[19:16] |PE4MFP |PE.4 Multi-function Pin Selection + * |[23:20] |PE5MFP |PE.5 Multi-function Pin Selection + * |[27:24] |PE6MFP |PE.6 Multi-function Pin Selection + * |[31:28] |PE7MFP |PE.7 Multi-function Pin Selection + * @var SYS_T::GPE_MFPH + * Offset: 0x54 GPIOE High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PE8MFP |PE.8 Multi-function Pin Selection + * |[7:4] |PE9MFP |PE.9 Multi-function Pin Selection + * |[11:8] |PE10MFP |PE.10 Multi-function Pin Selection + * |[15:12] |PE11MFP |PE.11 Multi-function Pin Selection + * |[19:16] |PE12MFP |PE.12 Multi-function Pin Selection + * |[23:20] |PE13MFP |PE.13 Multi-function Pin Selection + * |[27:24] |PE14_MFP |PE.14 Multi-function Pin Selection + * |[31:28] |PE15_MFP |PE.15 Multi-function Pin Selection + * @var SYS_T::GPF_MFPL + * Offset: 0x58 GPIOF Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PF0MFP |PF.0 Multi-function Pin Selection + * |[7:4] |PF1MFP |PF.1 Multi-function Pin Selection + * |[11:8] |PF2MFP |PF.2 Multi-function Pin Selection + * |[15:12] |PF3MFP |PF.3 Multi-function Pin Selection + * |[19:16] |PF4MFP |PF.4 Multi-function Pin Selection + * |[23:20] |PF5MFP |PF.5 Multi-function Pin Selection + * |[27:24] |PF6MFP |PF.6 Multi-function Pin Selection + * |[31:28] |PF7MFP |PF.7 Multi-function Pin Selection + * @var SYS_T::GPF_MFPH + * Offset: 0x5C GPIOF High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PF8MFP |PF.8 Multi-function Pin Selection + * |[7:4] |PF9MFP |PF.9 Multi-function Pin Selection + * |[11:8] |PF10MFP |PF.10 Multi-function Pin Selection + * |[15:12] |PF11MFP |PF.11 Multi-function Pin Selection + * |[19:16] |PF12MFP |PF.12 Multi-function Pin Selection + * |[23:20] |PF13MFP |PF.13 Multi-function Pin Selection + * |[27:24] |PF14MFP |PF.14 Multi-function Pin Selection + * |[31:28] |PF15MFP |PF.15 Multi-function Pin Selection + * @var SYS_T::GPA_MFOS + * Offset: 0x80 GPIOA Multiple Function Output Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MFOS0 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[1] |MFOS1 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[2] |MFOS2 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[3] |MFOS3 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[4] |MFOS4 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[5] |MFOS5 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[6] |MFOS6 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[7] |MFOS7 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[8] |MFOS8 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[9] |MFOS9 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[10] |MFOS10 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[11] |MFOS11 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[12] |MFOS12 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[13] |MFOS13 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[14] |MFOS14 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[15] |MFOS15 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * @var SYS_T::GPB_MFOS + * Offset: 0x84 GPIOB Multiple Function Output Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MFOS0 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[1] |MFOS1 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[2] |MFOS2 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[3] |MFOS3 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[4] |MFOS4 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[5] |MFOS5 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[6] |MFOS6 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[7] |MFOS7 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[8] |MFOS8 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[9] |MFOS9 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[10] |MFOS10 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[11] |MFOS11 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[12] |MFOS12 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[13] |MFOS13 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[14] |MFOS14 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[15] |MFOS15 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * @var SYS_T::GPC_MFOS + * Offset: 0x88 GPIOC Multiple Function Output Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MFOS0 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[1] |MFOS1 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[2] |MFOS2 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[3] |MFOS3 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[4] |MFOS4 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[5] |MFOS5 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[6] |MFOS6 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[7] |MFOS7 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[8] |MFOS8 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[9] |MFOS9 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[10] |MFOS10 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[11] |MFOS11 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[12] |MFOS12 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[13] |MFOS13 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[14] |MFOS14 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[15] |MFOS15 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * @var SYS_T::GPD_MFOS + * Offset: 0x8C GPIOD Multiple Function Output Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MFOS0 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[1] |MFOS1 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[2] |MFOS2 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[3] |MFOS3 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[4] |MFOS4 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[5] |MFOS5 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[6] |MFOS6 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[7] |MFOS7 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[8] |MFOS8 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[9] |MFOS9 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[10] |MFOS10 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[11] |MFOS11 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[12] |MFOS12 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[13] |MFOS13 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[14] |MFOS14 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[15] |MFOS15 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * @var SYS_T::GPE_MFOS + * Offset: 0x90 GPIOE Multiple Function Output Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MFOS0 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[1] |MFOS1 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[2] |MFOS2 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[3] |MFOS3 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[4] |MFOS4 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[5] |MFOS5 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[6] |MFOS6 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[7] |MFOS7 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[8] |MFOS8 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[9] |MFOS9 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[10] |MFOS10 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[11] |MFOS11 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[12] |MFOS12 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[13] |MFOS13 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[14] |MFOS14 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[15] |MFOS15 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * @var SYS_T::GPF_MFOS + * Offset: 0x94 GPIOF Multiple Function Output Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MFOS0 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[1] |MFOS1 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[2] |MFOS2 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[3] |MFOS3 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[4] |MFOS4 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[5] |MFOS5 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[6] |MFOS6 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[7] |MFOS7 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[8] |MFOS8 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[9] |MFOS9 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[10] |MFOS10 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[11] |MFOS11 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[12] |MFOS12 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[13] |MFOS13 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[14] |MFOS14 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * |[15] |MFOS15 |GPIOA-f Pin[n] Multiple Function Pin Output Mode Select + * | | |This bit used to select multiple function pin output mode type for Px.n pin + * | | |0 = Multiple funtion pin output mode type is Push-pull mode. + * | | |1 = Multiple funtion pin output mode type is Open-drain mode. + * | | |Note: + * | | |Max. n=15. + * @var SYS_T::MODCTL + * Offset: 0xC0 Modulation Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MODEN |Modulation Function Enable Bit + * | | |This bit enables modulation funcion by modulating with PWM0 channel output and USCI0(USCI0_DAT0) or UART0(UART0_TXD) output. + * | | |0 = Modulation Function Disabled. + * | | |1 = Modulation Function Enabled. + * |[1] |MODH |Modulation at Data High + * | | |Select modulation pulse(PWM0) at high or low of UART0_TXD or USCI0_DAT0 + * | | |0: Modulation pulse at UART0_TXD low or USCI0_DAT0 low. + * | | |1: Modulation pulse at UART0_TXD high or USCI0_DAT0 high. + * |[7:4] |MODPWMSEL |PWM0 Channel Select for Modulation + * | | |Select the PWM0 channel to modulate with the UART0_TXD or USCI0_DAT0. + * | | |0000: PWM0 Channel 0 modulate with UART0_TXD. + * | | |0001: PWM0 Channel 1 modulate with UART0_TXD. + * | | |0010: PWM0 Channel 2 modulate with UART0_TXD. + * | | |0011: PWM0 Channel 3 modulete with UART0_TXD. + * | | |0100: PWM0 Channel 4 modulete with UART0_TXD. + * | | |0101: PWM0 Channel 5 modulete with UART0_TXD. + * | | |0110: Reserved. + * | | |0111: Reserved. + * | | |1000: PWM0 Channel 0 modulate with USCI0_DAT0. + * | | |1001: PWM0 Channel 1 modulate with USCI0_DAT0. + * | | |1010: PWM0 Channel 2 modulate with USCI0_DAT0. + * | | |1011: PWM0 Channel 3 modulete with USCI0_DAT0. + * | | |1100: PWM0 Channel 4 modulete with USCI0_DAT0. + * | | |1101: PWM0 Channel 5 modulete with USCI0_DAT0. + * | | |1110: Reserved. + * | | |1111: Reserved. + * | | |Note: This bis is valid while MODEN (SYS_MODCTL[0]) is set to 1. + * @var SYS_T::SRAM_BISTCTL + * Offset: 0xD0 System SRAM BIST Test Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SRBIST |SRAM Bank0 BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for SRAM bank0. + * | | |0 = system SRAM BIST Disabled. + * | | |1 = system SRAM BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[2] |FMCBIST |FMC CACHE BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for CACHE RAM + * | | |0 = system CACHE BIST Disabled. + * | | |1 = system CACHE BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[4] |USBBIST |USB BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for USB RAM + * | | |0 = system USB BIST Disabled. + * | | |1 = system USB BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[7] |PDMABIST |PDMA BIST Enable Bit (Write Protect) + * | | |This bit enables BIST test for PDMA RAM + * | | |0 = system PDMA BIST Disabled. + * | | |1 = system PDMA BIST Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var SYS_T::SRAM_BISTSTS + * Offset: 0xD4 System SRAM BIST Test Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SRBISTEF |1st System SRAM BIST Fail Flag + * | | |0 = 1st system SRAM BIST test pass. + * | | |1 = 1st system SRAM BIST test fail. + * |[1] |CR0BISTEF |CACHE0 SRAM BIST Fail Flag + * | | |0 = System CACHE RAM BIST test pass. + * | | |1 = System CACHE RAM BIST test fail. + * |[2] |CR1BISTEF |CACHE1 SRAM BIST Fail Flag + * | | |0 = System CACHE RAM BIST test pass. + * | | |1 = System CACHE RAM BIST test fail. + * |[4] |USBBEF |USB SRAM BIST Fail Flag + * | | |0 = USB SRAM BIST test pass. + * | | |1 = USB SRAM BIST test fail. + * |[7] |PDMABISTF |PDMA SRAM BIST Failed Flag + * | | |0 = 1st PDMA SRAM BIST pass. + * | | |1 =1st PDMA SRAM BIST failed. + * |[16] |SRBEND |1st SRAM BIST Test Finish + * | | |0 = 1st system SRAM BIST active. + * | | |1 =1st system SRAM BIST finish. + * |[17] |CR0BEND |CACHE 0 SRAM BIST Test Finish + * | | |0 = System CACHE RAM BIST is active. + * | | |1 = System CACHE RAM BIST test finish. + * |[18] |CR1BEND |CACHE 1 SRAM BIST Test Finish + * | | |0 = System CACHE RAM BIST is active. + * | | |1 = System CACHE RAM BIST test finish. + * |[20] |USBBEND |USB SRAM BIST Test Finish + * | | |0 = USB SRAM BIST is active. + * | | |1 = USB SRAM BIST test finish. + * |[23] |PDMAEND |PDMA SRAM BIST Test Finish + * | | |0 = PDMA SRAM BIST is active. + * | | |1 = PDMA SRAM BIST test finish. + * @var SYS_T::HIRCTRIMCTL + * Offset: 0xF0 HIRC Trim Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |FREQSEL |Trim Frequency Selection + * | | |This field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC) auto trim. + * | | |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. + * | | |00 = Disable HIRC auto trim function. + * | | |01 = Enable HIRC auto trim function and trim HIRC to 48 MHz. + * | | |10 = Reserved.. + * | | |11 = Reserved. + * |[5:4] |LOOPSEL |Trim Calculation Loop Selection + * | | |This field defines that trim value calculation is based on how many reference clocks. + * | | |00 = Trim value calculation is based on average difference in 4 clocks of reference clock. + * | | |01 = Trim value calculation is based on average difference in 8 clocks of reference clock. + * | | |10 = Trim value calculation is based on average difference in 16 clocks of reference clock. + * | | |11 = Trim value calculation is based on average difference in 32 clocks of reference clock. + * | | |Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock. + * |[7:6] |RETRYCNT |Trim Value Update Limitation Count + * | | |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked. + * | | |Once the HIRC locked, the internal trim value update counter will be reset. + * | | |If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00. + * | | |00 = Trim retry count limitation is 64 loops. + * | | |01 = Trim retry count limitation is 128 loops. + * | | |10 = Trim retry count limitation is 256 loops. + * | | |11 = Trim retry count limitation is 512 loops. + * |[8] |CESTOPEN |Clock Error Stop Enable Bit + * | | |0 = The trim operation is keep going if clock is inaccuracy. + * | | |1 = The trim operation is stopped if clock is inaccuracy. + * |[9] |BOUNDEN |Boundary Enable + * | | |0 = Boundary function is disable. + * | | |1 = Boundary function is enable. + * |[10] |REFCKSEL |Reference Clock Selection + * | | |0 = HIRC trim reference from external 32.768 kHz crystal oscillator. + * | | |1 = HIRC trim reference from internal USB synchronous mode. + * |[20:16] |BOUNDARY |Boundary Selection + * | | |Fill the boundary range from 0x1 to 0x1F, 0x0 is reserved. + * | | |Note: This field is effective only when the BOUNDEN(SYS_HIRCTRIMCTL[9]) is enable + * @var SYS_T::HIRCTRIMIEN + * Offset: 0xF4 HIRC Trim Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TFALIEN |Trim Failure Interrupt Enable Bit + * | | |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_HIRCCTL[1:0]). + * | | |If this bit is high and TFAILIF(SYS_HIRCSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. + * | | |0 = Disable TFAILIF(SYS_HIRCSTS[1]) status to trigger an interrupt to CPU. + * | | |1 = Enable TFAILIF(SYS_HIRCSTS[1]) status to trigger an interrupt to CPU. + * |[2] |CLKEIEN |Clock Error Interrupt Enable Bit + * | | |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. + * | | |If this bit is set to1, and CLKERRIF(SYS_HIRCSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. + * | | |0 = Disable CLKERRIF(SYS_HIRCSTS[2]) status to trigger an interrupt to CPU. + * | | |1 = Enable CLKERRIF(SYS_HIRCSTS[2]) status to trigger an interrupt to CPU. + * @var SYS_T::HIRCTRIMSTS + * Offset: 0xF8 HIRC Trim Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FREQLOCK |HIRC Frequency Lock Status + * | | |This bit indicates the HIRC frequency is locked. + * | | |This is a status bit and doesn't trigger any interrupt + * | | |Write 1 to clear this to 0 + * | | |This bit will be set automatically, if the frequecy is lock and the RC_TRIM is enabled. + * | | |0 = The internal high-speed oscillator frequency doesn't lock at 48 MHz yet. + * | | |1 = The internal high-speed oscillator frequency locked at 48 MHz. + * |[1] |TFAILIF |Trim Failure Interrupt Status + * | | |This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked + * | | |Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_HIRCCTL[1:0]) will be cleared to 00 by hardware automatically. + * | | |If this bit is set and TFAILIEN(SYS_HIRCIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached + * | | |Write 1 to clear this to 0. + * | | |0 = Trim value update limitation count does not reach. + * | | |1 = Trim value update limitation count reached and HIRC frequency still not locked. + * |[2] |CLKERIF |Clock Error Interrupt Status + * | | |When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 48MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy + * | | |Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_HIRCCTL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_HIRCCTL[8]) is set to 1. + * | | |If this bit is set and CLKEIEN(SYS_HIRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy + * | | |Write 1 to clear this to 0. + * | | |0 = Clock frequency is accuracy. + * | | |1 = Clock frequency is inaccuracy. + * |[3] |OVBDIF |Over Boundary Status + * | | |When the over boundary function is set, if there occurs the over boundary condition, this flag will be set. + * | | |0 = Over boundary coundition did not occur. + * | | |1 = Over boundary coundition occurred. + * | | |Note: Write 1 to clear this flag. + * @var SYS_T::REGLCTL + * Offset: 0x100 Register Lock Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |REGLCTL |Register Lock Control Code (Write Only) + * | | |Some registers have write-protection function + * | | |Writing these registers have to disable the protected function by writing the sequence value "59h", "16h", "88h" to this field + * | | |After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write. + * | | |Register Lock Control Disable Index (Read Only) + * | | |0 = Write-protection Enabled for writing protected registers + * | | |Any write to the protected register is ignored. + * | | |1 = Write-protection Disabled for writing protected registers. + * | | |The Protected registers are: + * | | |NMIEN address 0x4000_0300 + * | | |FMC_ISPCTL address 0x4000_C000 (Flash ISP Control register) + * | | |FMC_ISPTRG address 0x4000_C010 (ISP Trigger Control register) + * | | |FMC_ISPSTS address 0x4000_C040 + * | | |WDT_CTL address 0x4004_0000 + * | | |FMC_FTCTL address 0x4000_5018 + * | | |FMC_ICPCMD address 0x4000_501C + * | | |EADC_TEST address 0x4004_3200 + * | | |AHBMCTL address 0x40000400 + * | | |SYS_IPRST0 address 0x4000_0008 + * | | |SYS_BODCTL address 0x4000_0018 + * | | |SYS_PORCTL address 0x4000_0024 + * | | |SYS_SRAM_BISTCTL address 0x4000_00D0 + * | | |SYS_PORCTL1 address 0x4000_01EC + * | | |CLK_PWRCTL address 0x4000_0200 + * | | |CLK_APBCLK0[0] address 0x4000_0208 + * | | |CLK_CLKSEL0 address 0x4000_0210 + * | | |CLK_CLKSEL1[3:0] address 0x4000_0214 + * | | |CLK_PLLCTL address 0x40000240 + * | | |CLK_PMUCTL address 0x4000_0290 + * | | |CLK_HXTFSEL address 0x4000_02B4 + * | | |PWM_CTL0 address 0x4005_8000 + * | | |PWM_CTL0 address 0x4005_9000 + * | | |PWM_DTCTL0_1 address 0x4005_8070 + * | | |PWM_DTCTL0_1 address 0x4005_9070 + * | | |PWM_DTCTL2_3 address 0x4005_8074 + * | | |PWM_DTCTL2_3 address 0x4005_9074 + * | | |PWM_DTCTL4_5 address 0x4005_8078 + * | | |PWM_DTCTL4_5 address 0x4005_9078 + * | | |PWM_BRKCTL0_1 address 0x4005_80C8 + * | | |PWM_BRKCTL0_1 address 0x4005_90C8 + * | | |PWM_BRKCTL2_3 address0x4005_80CC + * | | |PWM_BRKCTL2_3 address0x4005_90CC + * | | |PWM_BRKCTL4_5 address0x4005_80D0 + * | | |PWM_BRKCTL4_5 address0x4005_90D0 + * | | |PWM_INTEN1 address0x4005_80E4 + * | | |PWM_INTEN1 address0x4005_90E4 + * | | |PWM_INTSTS1 address0x4005_80EC + * | | |PWM_INTSTS1 address0x4005_90EC + * @var SYS_T::MIRCTRIMCTL + * Offset: 0x104 MIRC Trim Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |FREQSEL |Trim Frequency Selection + * | | |This field indicates the target frequency of medium speed RC oscillator (MIRC) auto trim. + * | | |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. + * | | |00 = Disable HIRC auto trim function. + * | | |01 = Reserved. + * | | |10 = Enable HIRC auto trim function and trim MIRC to 4.032 MHz. + * |[5:4] |LOOPSEL |Trim Calculation Loop Selection + * | | |This field defines that trim value calculation is based on how many reference clocks. + * | | |00 = Reserved. + * | | |01 = Trim value calculation is based on average difference in 8 clocks of reference clock. + * | | |10 = Trim value calculation is based on average difference in 16 clocks of reference clock. + * | | |11 = Trim value calculation is based on average difference in 32 clocks of reference clock. + * | | |Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock. + * |[7:6] |RETRYCNT |Trim Value Update Limitation Count + * | | |This field defines that how many times the auto trim circuit will try to update the MIRC trim value before the frequency of MIRC locked. + * | | |Once the MIRC locked, the internal trim value update counter will be reset. + * | | |If the trim value update counter reached this limitation value and frequency of MIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00. + * | | |00 = Trim retry count limitation is 64 loops. + * | | |01 = Trim retry count limitation is 128 loops. + * | | |10 = Trim retry count limitation is 256 loops. + * | | |11 = Trim retry count limitation is 512 loops. + * |[8] |CESTOPEN |Clock Error Stop Enable Bit + * | | |0 = The trim operation is keep going if clock is inaccuracy. + * | | |1 = The trim operation is stopped if clock is inaccuracy. + * |[9] |BOUNDEN |Boundary Enable + * | | |0 = Boundary function is disable. + * | | |1 = Boundary function is enable. + * |[10] |REFCKSEL |Reference Clock Selection + * | | |0 = MIRC trim reference from external 32.768 kHz crystal oscillator. + * | | |1 = MIRC trim reference from internal USB synchronous mode. + * |[20:16] |BOUNDARY |Boundary Selection + * | | |Fill the boundary range from 0x1 to 0x1F, 0x0 is reserved. + * | | |Note: This field is effective only when the BOUNDEN(SYS_MIRCTRIMCTL[9]) is enable + * @var SYS_T::MIRCTRIMIEN + * Offset: 0x108 MIRC Trim Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TFALIEN |Trim Failure Interrupt Enable Bit + * | | |This bit controls if an interrupt will be triggered while MIRC trim value update limitation count reached and MIRC frequency still not locked on target frequency set by FREQSEL(SYS_ MIRCCTL[1:0]). + * | | |If this bit is high and TFAILIF(SYS_ MIRCSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that MIRC trim value update limitation count was reached. + * | | |0 = Disable TFAILIF(SYS_MIRCSTS[1]) status to trigger an interrupt to CPU. + * | | |1 = Enable TFAILIF(SYS_MIRCSTS[1]) status to trigger an interrupt to CPU. + * |[2] |CLKEIEN |Clock Error Interrupt Enable Bit + * | | |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. + * | | |If this bit is set to1, and CLKERRIF(SYS_MIRCSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. + * | | |0 = Disable CLKERRIF(SYS_MIRCSTS[2]) status to trigger an interrupt to CPU. + * | | |1 = Enable CLKERRIF(SYS_MIRCSTS[2]) status to trigger an interrupt to CPU. + * @var SYS_T::MIRCTRIMSTS + * Offset: 0x10C MIRC Trim Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FREQLOCK |MIRC Frequency Lock Status + * | | |This bit indicates the MIRC frequency is locked. + * | | |This is a status bit and doesn't trigger any interrupt + * | | |Write 1 to clear this to 0 + * | | |This bit will be set automatically, if the frequecy is lock and the RC_TRIM is enabled. + * | | |0 = The internal medium-speed oscillator frequency doesn't lock yet. + * | | |1 = The internal medium-speed oscillator frequency locked. + * |[1] |TFAILIF |Trim Failure Interrupt Status + * | | |This bit indicates that MIRC trim value update limitation count reached and the MIRC clock frequency still doesn't be locked + * | | |Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_MIRCCTL[1:0]) will be cleared to 00 by hardware automatically. + * | | |If this bit is set and TFAILIEN(SYS_MIRCIEN[1]) is high, an interrupt will be triggered to notify that MIRC trim value update limitation count was reached + * | | |Write 1 to clear this to 0. + * | | |0 = Trim value update limitation count does not reach. + * | | |1 = Trim value update limitation count reached and MIRC frequency still not locked. + * |[2] |CLKERIF |Clock Error Interrupt Status + * | | |When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or internal medium speed RC oscillator (MIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy + * | | |Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_MIRCCTL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_MIRCCTL[8]) is set to 1. + * | | |If this bit is set and CLKEIEN(SYS_MIRCIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy + * | | |Write 1 to clear this to 0. + * | | |0 = Clock frequency is accuracy. + * | | |1 = Clock frequency is inaccuracy. + * |[3] |OVBDIF |Over Boundary Status + * | | |When the over boundary function is set, if there occurs the over boundary condition, this flag will be set. + * | | |0 = Over boundary coundition did not occur. + * | | |1 = Over boundary coundition occurred. + * | | |Note: Write 1 to clear this flag. + * @var SYS_T::RTCLVRIEN + * Offset: 0x144 RTC LVR interrupt control register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |IE |RTC LVR interrupt enable(Write Protect) + * | | |0 : disable (default) + * | | |1: enable + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * @var SYS_T::RTCLVRSTS + * Offset: 0x148 RTC LVR interrupt status register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |IF |RTC LVR interrupt flag(Write Protect) + * | | |When a positive edge of RTCLVR is detected, this bit will be set to 1 and will be cleared when a 1 is set to this bit. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[8] |RTCLVR |RTCLVR value (read only) + * @var SYS_T::PORCTL1 + * Offset: 0x1EC Power-On-reset Controller Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |POROFF |Power-on Reset Enable Bit (Write Protect) + * | | |After powered on, User can turn off internal analog POR circuit to save power by writing 0x5AA5 to this field. + * | | |The analog POR circuit will be active again when this field is set to another value or chip is reset by other reset source, including: + * | | |nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var SYS_T::PLCTL + * Offset: 0x1F8 Power Level Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |PLSEL |Power Level Select(Write Protect) + * | | |00 = Set to power level 0 (PL0) + * | | |01 = Reserved + * | | |10 = Set to power level 2 (PL2) + * | | |11= Reserved + * | | |Note : When at PL2, HCLK has to be lower than 4Mhz + * @var SYS_T::PLSTS + * Offset: 0x1FC Power Level Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PLCBUSY |Power Level Change Busy Bit (Read Only) + * | | |This bit is set by hardware when power level is changing . After power level change is completed, this bit will be cleared automatically by hardware. + * | | |0 = Power level change is completed. + * | | |1 = Power level change is ongoing. + * |[9:8] |CURPL |Current Power Level (Read Only) + * | | |This bit field reflect the current power level. + * | | |00 = Current power level is PL0. + * | | |01 = Reserved. + * | | |10 = Current power level is PL2. + * | | |Others = Reserved. + */ + __I uint32_t PDID; /*!< [0x0000] Part Device Identification Number Register */ + __IO uint32_t RSTSTS; /*!< [0x0004] System Reset Status Register */ + __IO uint32_t IPRST0; /*!< [0x0008] Peripheral Reset Control Register 0 */ + __IO uint32_t IPRST1; /*!< [0x000c] Peripheral Reset Control Register 1 */ + __IO uint32_t IPRST2; /*!< [0x0010] Peripheral Reset Control Register 2 */ + __I uint32_t RESERVE0[1]; + __IO uint32_t BODCTL; /*!< [0x0018] Brown-out Detector Control Register */ + __IO uint32_t IVSCTL; /*!< [0x001c] Internal Voltage Source Control Register */ + __I uint32_t RESERVE1[1]; + __IO uint32_t PORCTL0; /*!< [0x0024] Power-On-reset Controller Register 0 */ + __IO uint32_t VREFCTL; /*!< [0x0028] VREF Control Register */ + __I uint32_t RESERVE2[1]; + __IO uint32_t GPA_MFPL; /*!< [0x0030] GPIOA Low Byte Multiple Function Control Register */ + __IO uint32_t GPA_MFPH; /*!< [0x0034] GPIOA High Byte Multiple Function Control Register */ + __IO uint32_t GPB_MFPL; /*!< [0x0038] GPIOB Low Byte Multiple Function Control Register */ + __IO uint32_t GPB_MFPH; /*!< [0x003c] GPIOB High Byte Multiple Function Control Register */ + __IO uint32_t GPC_MFPL; /*!< [0x0040] GPIOC Low Byte Multiple Function Control Register */ + __IO uint32_t GPC_MFPH; /*!< [0x0044] GPIOC High Byte Multiple Function Control Register */ + __IO uint32_t GPD_MFPL; /*!< [0x0048] GPIOD Low Byte Multiple Function Control Register */ + __IO uint32_t GPD_MFPH; /*!< [0x004c] GPIOD High Byte Multiple Function Control Register */ + __IO uint32_t GPE_MFPL; /*!< [0x0050] GPIOE Low Byte Multiple Function Control Register */ + __IO uint32_t GPE_MFPH; /*!< [0x0054] GPIOE High Byte Multiple Function Control Register */ + __IO uint32_t GPF_MFPL; /*!< [0x0058] GPIOF Low Byte Multiple Function Control Register */ + __IO uint32_t GPF_MFPH; /*!< [0x005c] GPIOF High Byte Multiple Function Control Register */ + __I uint32_t RESERVE3[8]; + __IO uint32_t GPA_MFOS; /*!< [0x0080] GPIOA Multiple Function Output Select Register */ + __IO uint32_t GPB_MFOS; /*!< [0x0084] GPIOB Multiple Function Output Select Register */ + __IO uint32_t GPC_MFOS; /*!< [0x0088] GPIOC Multiple Function Output Select Register */ + __IO uint32_t GPD_MFOS; /*!< [0x008c] GPIOD Multiple Function Output Select Register */ + __IO uint32_t GPE_MFOS; /*!< [0x0090] GPIOE Multiple Function Output Select Register */ + __IO uint32_t GPF_MFOS; /*!< [0x0094] GPIOF Multiple Function Output Select Register */ + __I uint32_t RESERVE4[10]; + __IO uint32_t MODCTL; /*!< [0x00c0] Modulation Control Register */ + __I uint32_t RESERVE5[3]; + __IO uint32_t SRAM_BISTCTL; /*!< [0x00d0] System SRAM BIST Test Control Register */ + __I uint32_t SRAM_BISTSTS; /*!< [0x00d4] System SRAM BIST Test Status Register */ + __I uint32_t RESERVE6[6]; + __IO uint32_t HIRCTRIMCTL; /*!< [0x00f0] HIRC Trim Control Register */ + __IO uint32_t HIRCTRIMIEN; /*!< [0x00f4] HIRC Trim Interrupt Enable Register */ + __IO uint32_t HIRCTRIMSTS; /*!< [0x00f8] HIRC Trim Interrupt Status Register */ + __I uint32_t RESERVE7[1]; + __O uint32_t REGLCTL; /*!< [0x0100] Register Lock Control Register */ + __IO uint32_t MIRCTRIMCTL; /*!< [0x0104] MIRC Trim Control Register */ + __IO uint32_t MIRCTRIMIEN; /*!< [0x0108] MIRC Trim Interrupt Enable Register */ + __IO uint32_t MIRCTRIMSTS; /*!< [0x010c] MIRC Trim Interrupt Status Register */ + __I uint32_t RESERVE8[13]; + __IO uint32_t RTCLVRIEN; /*!< [0x0144] RTC LVR interrupt control register */ + __IO uint32_t RTCLVRSTS; /*!< [0x0148] RTC LVR interrupt status register */ + __I uint32_t RESERVE9[40]; + __IO uint32_t PORCTL1; /*!< [0x01ec] Power-On-reset Controller Register 1 */ + __I uint32_t RESERVE10[2]; + __IO uint32_t PLCTL; /*!< [0x01F8] Power Level Control Register */ + __I uint32_t PLSTS; /*!< [0x01Fc] Power Level Status Register */ +} SYS_T; + +/** + @addtogroup SYS_CONST SYS Bit Field Definition + Constant Definitions for SYS Controller +@{ */ + +#define SYS_PDID_PDID_Pos (0) /*!< SYS_T::PDID: PDID Position */ +#define SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos) /*!< SYS_T::PDID: PDID Mask */ + +#define SYS_RSTSTS_PORF_Pos (0) /*!< SYS_T::RSTSTS: PORF Position */ +#define SYS_RSTSTS_PORF_Msk (0x1ul << SYS_RSTSTS_PORF_Pos) /*!< SYS_T::RSTSTS: PORF Mask */ + +#define SYS_RSTSTS_PINRF_Pos (1) /*!< SYS_T::RSTSTS: PINRF Position */ +#define SYS_RSTSTS_PINRF_Msk (0x1ul << SYS_RSTSTS_PINRF_Pos) /*!< SYS_T::RSTSTS: PINRF Mask */ + +#define SYS_RSTSTS_WDTRF_Pos (2) /*!< SYS_T::RSTSTS: WDTRF Position */ +#define SYS_RSTSTS_WDTRF_Msk (0x1ul << SYS_RSTSTS_WDTRF_Pos) /*!< SYS_T::RSTSTS: WDTRF Mask */ + +#define SYS_RSTSTS_LVRF_Pos (3) /*!< SYS_T::RSTSTS: LVRF Position */ +#define SYS_RSTSTS_LVRF_Msk (0x1ul << SYS_RSTSTS_LVRF_Pos) /*!< SYS_T::RSTSTS: LVRF Mask */ + +#define SYS_RSTSTS_BODRF_Pos (4) /*!< SYS_T::RSTSTS: BODRF Position */ +#define SYS_RSTSTS_BODRF_Msk (0x1ul << SYS_RSTSTS_BODRF_Pos) /*!< SYS_T::RSTSTS: BODRF Mask */ + +#define SYS_RSTSTS_SYSRF_Pos (5) /*!< SYS_T::RSTSTS: SYSRF Position */ +#define SYS_RSTSTS_SYSRF_Msk (0x1ul << SYS_RSTSTS_SYSRF_Pos) /*!< SYS_T::RSTSTS: SYSRF Mask */ + +#define SYS_RSTSTS_PMURF_Pos (6) /*!< SYS_T::RSTSTS: PMURF Position */ +#define SYS_RSTSTS_PMURF_Msk (0x1ul << SYS_RSTSTS_PMURF_Pos) /*!< SYS_T::RSTSTS: PMURF Mask */ + +#define SYS_RSTSTS_CPURF_Pos (7) /*!< SYS_T::RSTSTS: CPURF Position */ +#define SYS_RSTSTS_CPURF_Msk (0x1ul << SYS_RSTSTS_CPURF_Pos) /*!< SYS_T::RSTSTS: CPURF Mask */ + +#define SYS_RSTSTS_CPULKRF_Pos (8) /*!< SYS_T::RSTSTS: CPULKRF Position */ +#define SYS_RSTSTS_CPULKRF_Msk (0x1ul << SYS_RSTSTS_CPULKRF_Pos) /*!< SYS_T::RSTSTS: CPULKRF Mask */ + +#define SYS_RSTSTS_VBATLVRF_Pos (9) /*!< SYS_T::RSTSTS: VBATLVRF Position */ +#define SYS_RSTSTS_VBATLVRF_Msk (0x1ul << SYS_RSTSTS_VBATLVRF_Pos) /*!< SYS_T::RSTSTS: VBATLVRF Mask */ + +#define SYS_IPRST0_CHIPRST_Pos (0) /*!< SYS_T::IPRST0: CHIPRST Position */ +#define SYS_IPRST0_CHIPRST_Msk (0x1ul << SYS_IPRST0_CHIPRST_Pos) /*!< SYS_T::IPRST0: CHIPRST Mask */ + +#define SYS_IPRST0_CPURST_Pos (1) /*!< SYS_T::IPRST0: CPURST Position */ +#define SYS_IPRST0_CPURST_Msk (0x1ul << SYS_IPRST0_CPURST_Pos) /*!< SYS_T::IPRST0: CPURST Mask */ + +#define SYS_IPRST0_PDMARST_Pos (2) /*!< SYS_T::IPRST0: PDMARST Position */ +#define SYS_IPRST0_PDMARST_Msk (0x1ul << SYS_IPRST0_PDMARST_Pos) /*!< SYS_T::IPRST0: PDMARST Mask */ + +#define SYS_IPRST0_EBIRST_Pos (3) /*!< SYS_T::IPRST0: EBIRST Position */ +#define SYS_IPRST0_EBIRST_Msk (0x1ul << SYS_IPRST0_EBIRST_Pos) /*!< SYS_T::IPRST0: EBIRST Mask */ + +#define SYS_IPRST0_CRCRST_Pos (7) /*!< SYS_T::IPRST0: CRCRST Position */ +#define SYS_IPRST0_CRCRST_Msk (0x1ul << SYS_IPRST0_CRCRST_Pos) /*!< SYS_T::IPRST0: CRCRST Mask */ + +#define SYS_IPRST0_CRYPTRST_Pos (12) /*!< SYS_T::IPRST0: CRYPTRST Position */ +#define SYS_IPRST0_CRYPTRST_Msk (0x1ul << SYS_IPRST0_CRYPTRST_Pos) /*!< SYS_T::IPRST0: CRYPTRST Mask */ + +#define SYS_IPRST1_GPIORST_Pos (1) /*!< SYS_T::IPRST1: GPIORST Position */ +#define SYS_IPRST1_GPIORST_Msk (0x1ul << SYS_IPRST1_GPIORST_Pos) /*!< SYS_T::IPRST1: GPIORST Mask */ + +#define SYS_IPRST1_TMR0RST_Pos (2) /*!< SYS_T::IPRST1: TMR0RST Position */ +#define SYS_IPRST1_TMR0RST_Msk (0x1ul << SYS_IPRST1_TMR0RST_Pos) /*!< SYS_T::IPRST1: TMR0RST Mask */ + +#define SYS_IPRST1_TMR1RST_Pos (3) /*!< SYS_T::IPRST1: TMR1RST Position */ +#define SYS_IPRST1_TMR1RST_Msk (0x1ul << SYS_IPRST1_TMR1RST_Pos) /*!< SYS_T::IPRST1: TMR1RST Mask */ + +#define SYS_IPRST1_TMR2RST_Pos (4) /*!< SYS_T::IPRST1: TMR2RST Position */ +#define SYS_IPRST1_TMR2RST_Msk (0x1ul << SYS_IPRST1_TMR2RST_Pos) /*!< SYS_T::IPRST1: TMR2RST Mask */ + +#define SYS_IPRST1_TMR3RST_Pos (5) /*!< SYS_T::IPRST1: TMR3RST Position */ +#define SYS_IPRST1_TMR3RST_Msk (0x1ul << SYS_IPRST1_TMR3RST_Pos) /*!< SYS_T::IPRST1: TMR3RST Mask */ + +#define SYS_IPRST1_ACMP01RST_Pos (7) /*!< SYS_T::IPRST1: ACMP01RST Position */ +#define SYS_IPRST1_ACMP01RST_Msk (0x1ul << SYS_IPRST1_ACMP01RST_Pos) /*!< SYS_T::IPRST1: ACMP01RST Mask */ + +#define SYS_IPRST1_I2C0RST_Pos (8) /*!< SYS_T::IPRST1: I2C0RST Position */ +#define SYS_IPRST1_I2C0RST_Msk (0x1ul << SYS_IPRST1_I2C0RST_Pos) /*!< SYS_T::IPRST1: I2C0RST Mask */ + +#define SYS_IPRST1_I2C1RST_Pos (9) /*!< SYS_T::IPRST1: I2C1RST Position */ +#define SYS_IPRST1_I2C1RST_Msk (0x1ul << SYS_IPRST1_I2C1RST_Pos) /*!< SYS_T::IPRST1: I2C1RST Mask */ + +#define SYS_IPRST1_QSPI0RST_Pos (12) /*!< SYS_T::IPRST1: QSPI0RST Position */ +#define SYS_IPRST1_QSPI0RST_Msk (0x1ul << SYS_IPRST1_QSPI0RST_Pos) /*!< SYS_T::IPRST1: QSPI0RST Mask */ + +#define SYS_IPRST1_SPI0RST_Pos (13) /*!< SYS_T::IPRST1: SPI0RST Position */ +#define SYS_IPRST1_SPI0RST_Msk (0x1ul << SYS_IPRST1_SPI0RST_Pos) /*!< SYS_T::IPRST1: SPI0RST Mask */ + +#define SYS_IPRST1_UART0RST_Pos (16) /*!< SYS_T::IPRST1: UART0RST Position */ +#define SYS_IPRST1_UART0RST_Msk (0x1ul << SYS_IPRST1_UART0RST_Pos) /*!< SYS_T::IPRST1: UART0RST Mask */ + +#define SYS_IPRST1_UART1RST_Pos (17) /*!< SYS_T::IPRST1: UART1RST Position */ +#define SYS_IPRST1_UART1RST_Msk (0x1ul << SYS_IPRST1_UART1RST_Pos) /*!< SYS_T::IPRST1: UART1RST Mask */ + +#define SYS_IPRST1_UART2RST_Pos (18) /*!< SYS_T::IPRST1: UART2RST Position */ +#define SYS_IPRST1_UART2RST_Msk (0x1ul << SYS_IPRST1_UART2RST_Pos) /*!< SYS_T::IPRST1: UART2RST Mask */ + +#define SYS_IPRST1_USBDRST_Pos (27) /*!< SYS_T::IPRST1: USBDRST Position */ +#define SYS_IPRST1_USBDRST_Msk (0x1ul << SYS_IPRST1_USBDRST_Pos) /*!< SYS_T::IPRST1: USBDRST Mask */ + +#define SYS_IPRST1_EADCRST_Pos (28) /*!< SYS_T::IPRST1: EADCRST Position */ +#define SYS_IPRST1_EADCRST_Msk (0x1ul << SYS_IPRST1_EADCRST_Pos) /*!< SYS_T::IPRST1: EADCRST Mask */ + +#define SYS_IPRST2_SC0RST_Pos (0) /*!< SYS_T::IPRST2: SC0RST Position */ +#define SYS_IPRST2_SC0RST_Msk (0x1ul << SYS_IPRST2_SC0RST_Pos) /*!< SYS_T::IPRST2: SC0RST Mask */ + +#define SYS_IPRST2_USCI0RST_Pos (8) /*!< SYS_T::IPRST2: USCI0RST Position */ +#define SYS_IPRST2_USCI0RST_Msk (0x1ul << SYS_IPRST2_USCI0RST_Pos) /*!< SYS_T::IPRST2: USCI0RST Mask */ + +#define SYS_IPRST2_USCI1RST_Pos (9) /*!< SYS_T::IPRST2: USCI1RST Position */ +#define SYS_IPRST2_USCI1RST_Msk (0x1ul << SYS_IPRST2_USCI1RST_Pos) /*!< SYS_T::IPRST2: USCI1RST Mask */ + +#define SYS_IPRST2_USCI2RST_Pos (10) /*!< SYS_T::IPRST2: USCI2RST Position */ +#define SYS_IPRST2_USCI2RST_Msk (0x1ul << SYS_IPRST2_USCI2RST_Pos) /*!< SYS_T::IPRST2: USCI2RST Mask */ + +#define SYS_IPRST2_DACRST_Pos (12) /*!< SYS_T::IPRST2: DACRST Position */ +#define SYS_IPRST2_DACRST_Msk (0x1ul << SYS_IPRST2_DACRST_Pos) /*!< SYS_T::IPRST2: DACRST Mask */ + +#define SYS_IPRST2_PWM0RST_Pos (16) /*!< SYS_T::IPRST2: PWM0RST Position */ +#define SYS_IPRST2_PWM0RST_Msk (0x1ul << SYS_IPRST2_PWM0RST_Pos) /*!< SYS_T::IPRST2: PWM0RST Mask */ + +#define SYS_IPRST2_PWM1RST_Pos (17) /*!< SYS_T::IPRST2: PWM1RST Position */ +#define SYS_IPRST2_PWM1RST_Msk (0x1ul << SYS_IPRST2_PWM1RST_Pos) /*!< SYS_T::IPRST2: PWM1RST Mask */ + +#define SYS_IPRST2_BPWM0RST_Pos (18) /*!< SYS_T::IPRST2: BPWM0RST Position */ +#define SYS_IPRST2_BPWM0RST_Msk (0x1ul << SYS_IPRST2_BPWM0RST_Pos) /*!< SYS_T::IPRST2: BPWM0RST Mask */ + +#define SYS_IPRST2_BPWM1RST_Pos (19) /*!< SYS_T::IPRST2: BPWM1RST Position */ +#define SYS_IPRST2_BPWM1RST_Msk (0x1ul << SYS_IPRST2_BPWM1RST_Pos) /*!< SYS_T::IPRST2: BPWM1RST Mask */ + +#define SYS_IPRST2_OPARST_Pos (30) /*!< SYS_T::IPRST2: OPARST Position */ +#define SYS_IPRST2_OPARST_Msk (0x1ul << SYS_IPRST2_OPARST_Pos) /*!< SYS_T::IPRST2: OPARST Mask */ + +#define SYS_IPRST2_PSIORST_Pos (31) /*!< SYS_T::IPRST2: PSIORST Position */ +#define SYS_IPRST2_PSIORST_Msk (0x1ul << SYS_IPRST2_PSIORST_Pos) /*!< SYS_T::IPRST2: PSIORST Mask */ + +#define SYS_BODCTL_BODEN_Pos (0) /*!< SYS_T::BODCTL: BODEN Position */ +#define SYS_BODCTL_BODEN_Msk (0x1ul << SYS_BODCTL_BODEN_Pos) /*!< SYS_T::BODCTL: BODEN Mask */ + +#define SYS_BODCTL_BODRSTEN_Pos (3) /*!< SYS_T::BODCTL: BODRSTEN Position */ +#define SYS_BODCTL_BODRSTEN_Msk (0x1ul << SYS_BODCTL_BODRSTEN_Pos) /*!< SYS_T::BODCTL: BODRSTEN Mask */ + +#define SYS_BODCTL_BODIF_Pos (4) /*!< SYS_T::BODCTL: BODIF Position */ +#define SYS_BODCTL_BODIF_Msk (0x1ul << SYS_BODCTL_BODIF_Pos) /*!< SYS_T::BODCTL: BODIF Mask */ + +#define SYS_BODCTL_BODLPM_Pos (5) /*!< SYS_T::BODCTL: BODLPM Position */ +#define SYS_BODCTL_BODLPM_Msk (0x1ul << SYS_BODCTL_BODLPM_Pos) /*!< SYS_T::BODCTL: BODLPM Mask */ + +#define SYS_BODCTL_BODOUT_Pos (6) /*!< SYS_T::BODCTL: BODOUT Position */ +#define SYS_BODCTL_BODOUT_Msk (0x1ul << SYS_BODCTL_BODOUT_Pos) /*!< SYS_T::BODCTL: BODOUT Mask */ + +#define SYS_BODCTL_LVREN_Pos (7) /*!< SYS_T::BODCTL: LVREN Position */ +#define SYS_BODCTL_LVREN_Msk (0x1ul << SYS_BODCTL_LVREN_Pos) /*!< SYS_T::BODCTL: LVREN Mask */ + +#define SYS_BODCTL_BODDGSEL_Pos (8) /*!< SYS_T::BODCTL: BODDGSEL Position */ +#define SYS_BODCTL_BODDGSEL_Msk (0x7ul << SYS_BODCTL_BODDGSEL_Pos) /*!< SYS_T::BODCTL: BODDGSEL Mask */ + +#define SYS_BODCTL_LVRDGSEL_Pos (12) /*!< SYS_T::BODCTL: LVRDGSEL Position */ +#define SYS_BODCTL_LVRDGSEL_Msk (0x7ul << SYS_BODCTL_LVRDGSEL_Pos) /*!< SYS_T::BODCTL: LVRDGSEL Mask */ + +#define SYS_BODCTL_BODVL_Pos (16) /*!< SYS_T::BODCTL: BODVL Position */ +#define SYS_BODCTL_BODVL_Msk (0x7ul << SYS_BODCTL_BODVL_Pos) /*!< SYS_T::BODCTL: BODVL Mask */ + +#define SYS_IVSCTL_VTEMPEN_Pos (0) /*!< SYS_T::IVSCTL: VTEMPEN Position */ +#define SYS_IVSCTL_VTEMPEN_Msk (0x1ul << SYS_IVSCTL_VTEMPEN_Pos) /*!< SYS_T::IVSCTL: VTEMPEN Mask */ + +#define SYS_IVSCTL_VBATUGEN_Pos (1) /*!< SYS_T::IVSCTL: VBATUGEN Position */ +#define SYS_IVSCTL_VBATUGEN_Msk (0x1ul << SYS_IVSCTL_VBATUGEN_Pos) /*!< SYS_T::IVSCTL: VBATUGEN Mask */ + +#define SYS_PORCTL0_PORMASK_Pos (0) /*!< SYS_T::PORCTL0: PORMASK Position */ +#define SYS_PORCTL0_PORMASK_Msk (0xfffful << SYS_PORCTL0_PORMASK_Pos) /*!< SYS_T::PORCTL0: PORMASK Mask */ + +#define SYS_VREFCTL_IVRS_Pos (0) /*!< SYS_T::VREFCTL: IVRS Position */ +#define SYS_VREFCTL_IVRS_Msk (0x7ul << SYS_VREFCTL_IVRS_Pos) /*!< SYS_T::VREFCTL: IVRS Mask */ + +#define SYS_VREFCTL_IVREN_Pos (3) /*!< SYS_T::VREFCTL: IVREN Position */ +#define SYS_VREFCTL_IVREN_Msk (0x1ul << SYS_VREFCTL_IVREN_Pos) /*!< SYS_T::VREFCTL: IVREN Mask */ + +#define SYS_VREFCTL_PRELOAD_Pos (10) /*!< SYS_T::VREFCTL: PRELOAD Position */ +#define SYS_VREFCTL_PRELOAD_Msk (0x1ul << SYS_VREFCTL_PRELOAD_Pos) /*!< SYS_T::VREFCTL: PRELOAD Mask */ + +#define SYS_GPA_MFPL_PA0MFP_Pos (0) /*!< SYS_T::GPA_MFPL: PA0MFP Position */ +#define SYS_GPA_MFPL_PA0MFP_Msk (0xful << SYS_GPA_MFPL_PA0MFP_Pos) /*!< SYS_T::GPA_MFPL: PA0MFP Mask */ + +#define SYS_GPA_MFPL_PA1MFP_Pos (4) /*!< SYS_T::GPA_MFPL: PA1MFP Position */ +#define SYS_GPA_MFPL_PA1MFP_Msk (0xful << SYS_GPA_MFPL_PA1MFP_Pos) /*!< SYS_T::GPA_MFPL: PA1MFP Mask */ + +#define SYS_GPA_MFPL_PA2MFP_Pos (8) /*!< SYS_T::GPA_MFPL: PA2MFP Position */ +#define SYS_GPA_MFPL_PA2MFP_Msk (0xful << SYS_GPA_MFPL_PA2MFP_Pos) /*!< SYS_T::GPA_MFPL: PA2MFP Mask */ + +#define SYS_GPA_MFPL_PA3MFP_Pos (12) /*!< SYS_T::GPA_MFPL: PA3MFP Position */ +#define SYS_GPA_MFPL_PA3MFP_Msk (0xful << SYS_GPA_MFPL_PA3MFP_Pos) /*!< SYS_T::GPA_MFPL: PA3MFP Mask */ + +#define SYS_GPA_MFPL_PA4MFP_Pos (16) /*!< SYS_T::GPA_MFPL: PA4MFP Position */ +#define SYS_GPA_MFPL_PA4MFP_Msk (0xful << SYS_GPA_MFPL_PA4MFP_Pos) /*!< SYS_T::GPA_MFPL: PA4MFP Mask */ + +#define SYS_GPA_MFPL_PA5MFP_Pos (20) /*!< SYS_T::GPA_MFPL: PA5MFP Position */ +#define SYS_GPA_MFPL_PA5MFP_Msk (0xful << SYS_GPA_MFPL_PA5MFP_Pos) /*!< SYS_T::GPA_MFPL: PA5MFP Mask */ + +#define SYS_GPA_MFPL_PA6MFP_Pos (24) /*!< SYS_T::GPA_MFPL: PA6MFP Position */ +#define SYS_GPA_MFPL_PA6MFP_Msk (0xful << SYS_GPA_MFPL_PA6MFP_Pos) /*!< SYS_T::GPA_MFPL: PA6MFP Mask */ + +#define SYS_GPA_MFPL_PA7MFP_Pos (28) /*!< SYS_T::GPA_MFPL: PA7MFP Position */ +#define SYS_GPA_MFPL_PA7MFP_Msk (0xful << SYS_GPA_MFPL_PA7MFP_Pos) /*!< SYS_T::GPA_MFPL: PA7MFP Mask */ + +#define SYS_GPA_MFPH_PA8MFP_Pos (0) /*!< SYS_T::GPA_MFPH: PA8MFP Position */ +#define SYS_GPA_MFPH_PA8MFP_Msk (0xful << SYS_GPA_MFPH_PA8MFP_Pos) /*!< SYS_T::GPA_MFPH: PA8MFP Mask */ + +#define SYS_GPA_MFPH_PA9MFP_Pos (4) /*!< SYS_T::GPA_MFPH: PA9MFP Position */ +#define SYS_GPA_MFPH_PA9MFP_Msk (0xful << SYS_GPA_MFPH_PA9MFP_Pos) /*!< SYS_T::GPA_MFPH: PA9MFP Mask */ + +#define SYS_GPA_MFPH_PA10MFP_Pos (8) /*!< SYS_T::GPA_MFPH: PA10MFP Position */ +#define SYS_GPA_MFPH_PA10MFP_Msk (0xful << SYS_GPA_MFPH_PA10MFP_Pos) /*!< SYS_T::GPA_MFPH: PA10MFP Mask */ + +#define SYS_GPA_MFPH_PA11MFP_Pos (12) /*!< SYS_T::GPA_MFPH: PA11MFP Position */ +#define SYS_GPA_MFPH_PA11MFP_Msk (0xful << SYS_GPA_MFPH_PA11MFP_Pos) /*!< SYS_T::GPA_MFPH: PA11MFP Mask */ + +#define SYS_GPA_MFPH_PA12MFP_Pos (16) /*!< SYS_T::GPA_MFPH: PA12MFP Position */ +#define SYS_GPA_MFPH_PA12MFP_Msk (0xful << SYS_GPA_MFPH_PA12MFP_Pos) /*!< SYS_T::GPA_MFPH: PA12MFP Mask */ + +#define SYS_GPA_MFPH_PA13MFP_Pos (20) /*!< SYS_T::GPA_MFPH: PA13MFP Position */ +#define SYS_GPA_MFPH_PA13MFP_Msk (0xful << SYS_GPA_MFPH_PA13MFP_Pos) /*!< SYS_T::GPA_MFPH: PA13MFP Mask */ + +#define SYS_GPA_MFPH_PA14MFP_Pos (24) /*!< SYS_T::GPA_MFPH: PA14MFP Position */ +#define SYS_GPA_MFPH_PA14MFP_Msk (0xful << SYS_GPA_MFPH_PA14MFP_Pos) /*!< SYS_T::GPA_MFPH: PA14MFP Mask */ + +#define SYS_GPA_MFPH_PA15MFP_Pos (28) /*!< SYS_T::GPA_MFPH: PA15MFP Position */ +#define SYS_GPA_MFPH_PA15MFP_Msk (0xful << SYS_GPA_MFPH_PA15MFP_Pos) /*!< SYS_T::GPA_MFPH: PA15MFP Mask */ + +#define SYS_GPB_MFPL_PB0MFP_Pos (0) /*!< SYS_T::GPB_MFPL: PB0MFP Position */ +#define SYS_GPB_MFPL_PB0MFP_Msk (0xful << SYS_GPB_MFPL_PB0MFP_Pos) /*!< SYS_T::GPB_MFPL: PB0MFP Mask */ + +#define SYS_GPB_MFPL_PB1MFP_Pos (4) /*!< SYS_T::GPB_MFPL: PB1MFP Position */ +#define SYS_GPB_MFPL_PB1MFP_Msk (0xful << SYS_GPB_MFPL_PB1MFP_Pos) /*!< SYS_T::GPB_MFPL: PB1MFP Mask */ + +#define SYS_GPB_MFPL_PB2MFP_Pos (8) /*!< SYS_T::GPB_MFPL: PB2MFP Position */ +#define SYS_GPB_MFPL_PB2MFP_Msk (0xful << SYS_GPB_MFPL_PB2MFP_Pos) /*!< SYS_T::GPB_MFPL: PB2MFP Mask */ + +#define SYS_GPB_MFPL_PB3MFP_Pos (12) /*!< SYS_T::GPB_MFPL: PB3MFP Position */ +#define SYS_GPB_MFPL_PB3MFP_Msk (0xful << SYS_GPB_MFPL_PB3MFP_Pos) /*!< SYS_T::GPB_MFPL: PB3MFP Mask */ + +#define SYS_GPB_MFPL_PB4MFP_Pos (16) /*!< SYS_T::GPB_MFPL: PB4MFP Position */ +#define SYS_GPB_MFPL_PB4MFP_Msk (0xful << SYS_GPB_MFPL_PB4MFP_Pos) /*!< SYS_T::GPB_MFPL: PB4MFP Mask */ + +#define SYS_GPB_MFPL_PB5MFP_Pos (20) /*!< SYS_T::GPB_MFPL: PB5MFP Position */ +#define SYS_GPB_MFPL_PB5MFP_Msk (0xful << SYS_GPB_MFPL_PB5MFP_Pos) /*!< SYS_T::GPB_MFPL: PB5MFP Mask */ + +#define SYS_GPB_MFPL_PB6MFP_Pos (24) /*!< SYS_T::GPB_MFPL: PB6MFP Position */ +#define SYS_GPB_MFPL_PB6MFP_Msk (0xful << SYS_GPB_MFPL_PB6MFP_Pos) /*!< SYS_T::GPB_MFPL: PB6MFP Mask */ + +#define SYS_GPB_MFPL_PB7MFP_Pos (28) /*!< SYS_T::GPB_MFPL: PB7MFP Position */ +#define SYS_GPB_MFPL_PB7MFP_Msk (0xful << SYS_GPB_MFPL_PB7MFP_Pos) /*!< SYS_T::GPB_MFPL: PB7MFP Mask */ + +#define SYS_GPB_MFPH_PB8MFP_Pos (0) /*!< SYS_T::GPB_MFPH: PB8MFP Position */ +#define SYS_GPB_MFPH_PB8MFP_Msk (0xful << SYS_GPB_MFPH_PB8MFP_Pos) /*!< SYS_T::GPB_MFPH: PB8MFP Mask */ + +#define SYS_GPB_MFPH_PB9MFP_Pos (4) /*!< SYS_T::GPB_MFPH: PB9MFP Position */ +#define SYS_GPB_MFPH_PB9MFP_Msk (0xful << SYS_GPB_MFPH_PB9MFP_Pos) /*!< SYS_T::GPB_MFPH: PB9MFP Mask */ + +#define SYS_GPB_MFPH_PB10MFP_Pos (8) /*!< SYS_T::GPB_MFPH: PB10MFP Position */ +#define SYS_GPB_MFPH_PB10MFP_Msk (0xful << SYS_GPB_MFPH_PB10MFP_Pos) /*!< SYS_T::GPB_MFPH: PB10MFP Mask */ + +#define SYS_GPB_MFPH_PB11MFP_Pos (12) /*!< SYS_T::GPB_MFPH: PB11MFP Position */ +#define SYS_GPB_MFPH_PB11MFP_Msk (0xful << SYS_GPB_MFPH_PB11MFP_Pos) /*!< SYS_T::GPB_MFPH: PB11MFP Mask */ + +#define SYS_GPB_MFPH_PB12MFP_Pos (16) /*!< SYS_T::GPB_MFPH: PB12MFP Position */ +#define SYS_GPB_MFPH_PB12MFP_Msk (0xful << SYS_GPB_MFPH_PB12MFP_Pos) /*!< SYS_T::GPB_MFPH: PB12MFP Mask */ + +#define SYS_GPB_MFPH_PB13MFP_Pos (20) /*!< SYS_T::GPB_MFPH: PB13MFP Position */ +#define SYS_GPB_MFPH_PB13MFP_Msk (0xful << SYS_GPB_MFPH_PB13MFP_Pos) /*!< SYS_T::GPB_MFPH: PB13MFP Mask */ + +#define SYS_GPB_MFPH_PB14MFP_Pos (24) /*!< SYS_T::GPB_MFPH: PB14MFP Position */ +#define SYS_GPB_MFPH_PB14MFP_Msk (0xful << SYS_GPB_MFPH_PB14MFP_Pos) /*!< SYS_T::GPB_MFPH: PB14MFP Mask */ + +#define SYS_GPB_MFPH_PB15MFP_Pos (28) /*!< SYS_T::GPB_MFPH: PB15MFP Position */ +#define SYS_GPB_MFPH_PB15MFP_Msk (0xful << SYS_GPB_MFPH_PB15MFP_Pos) /*!< SYS_T::GPB_MFPH: PB15MFP Mask */ + +#define SYS_GPC_MFPL_PC0MFP_Pos (0) /*!< SYS_T::GPC_MFPL: PC0MFP Position */ +#define SYS_GPC_MFPL_PC0MFP_Msk (0xful << SYS_GPC_MFPL_PC0MFP_Pos) /*!< SYS_T::GPC_MFPL: PC0MFP Mask */ + +#define SYS_GPC_MFPL_PC1MFP_Pos (4) /*!< SYS_T::GPC_MFPL: PC1MFP Position */ +#define SYS_GPC_MFPL_PC1MFP_Msk (0xful << SYS_GPC_MFPL_PC1MFP_Pos) /*!< SYS_T::GPC_MFPL: PC1MFP Mask */ + +#define SYS_GPC_MFPL_PC2MFP_Pos (8) /*!< SYS_T::GPC_MFPL: PC2MFP Position */ +#define SYS_GPC_MFPL_PC2MFP_Msk (0xful << SYS_GPC_MFPL_PC2MFP_Pos) /*!< SYS_T::GPC_MFPL: PC2MFP Mask */ + +#define SYS_GPC_MFPL_PC3MFP_Pos (12) /*!< SYS_T::GPC_MFPL: PC3MFP Position */ +#define SYS_GPC_MFPL_PC3MFP_Msk (0xful << SYS_GPC_MFPL_PC3MFP_Pos) /*!< SYS_T::GPC_MFPL: PC3MFP Mask */ + +#define SYS_GPC_MFPL_PC4MFP_Pos (16) /*!< SYS_T::GPC_MFPL: PC4MFP Position */ +#define SYS_GPC_MFPL_PC4MFP_Msk (0xful << SYS_GPC_MFPL_PC4MFP_Pos) /*!< SYS_T::GPC_MFPL: PC4MFP Mask */ + +#define SYS_GPC_MFPL_PC5MFP_Pos (20) /*!< SYS_T::GPC_MFPL: PC5MFP Position */ +#define SYS_GPC_MFPL_PC5MFP_Msk (0xful << SYS_GPC_MFPL_PC5MFP_Pos) /*!< SYS_T::GPC_MFPL: PC5MFP Mask */ + +#define SYS_GPC_MFPL_PC6MFP_Pos (24) /*!< SYS_T::GPC_MFPL: PC6MFP Position */ +#define SYS_GPC_MFPL_PC6MFP_Msk (0xful << SYS_GPC_MFPL_PC6MFP_Pos) /*!< SYS_T::GPC_MFPL: PC6MFP Mask */ + +#define SYS_GPC_MFPL_PC7MFP_Pos (28) /*!< SYS_T::GPC_MFPL: PC7MFP Position */ +#define SYS_GPC_MFPL_PC7MFP_Msk (0xful << SYS_GPC_MFPL_PC7MFP_Pos) /*!< SYS_T::GPC_MFPL: PC7MFP Mask */ + +#define SYS_GPC_MFPH_PC8MFP_Pos (0) /*!< SYS_T::GPC_MFPH: PC8MFP Position */ +#define SYS_GPC_MFPH_PC8MFP_Msk (0xful << SYS_GPC_MFPH_PC8MFP_Pos) /*!< SYS_T::GPC_MFPH: PC8MFP Mask */ + +#define SYS_GPC_MFPH_PC9MFP_Pos (4) /*!< SYS_T::GPC_MFPH: PC9MFP Position */ +#define SYS_GPC_MFPH_PC9MFP_Msk (0xful << SYS_GPC_MFPH_PC9MFP_Pos) /*!< SYS_T::GPC_MFPH: PC9MFP Mask */ + +#define SYS_GPC_MFPH_PC10MFP_Pos (8) /*!< SYS_T::GPC_MFPH: PC10MFP Position */ +#define SYS_GPC_MFPH_PC10MFP_Msk (0xful << SYS_GPC_MFPH_PC10MFP_Pos) /*!< SYS_T::GPC_MFPH: PC10MFP Mask */ + +#define SYS_GPC_MFPH_PC11MFP_Pos (12) /*!< SYS_T::GPC_MFPH: PC11MFP Position */ +#define SYS_GPC_MFPH_PC11MFP_Msk (0xful << SYS_GPC_MFPH_PC11MFP_Pos) /*!< SYS_T::GPC_MFPH: PC11MFP Mask */ + +#define SYS_GPC_MFPH_PC12MFP_Pos (16) /*!< SYS_T::GPC_MFPH: PC12MFP Position */ +#define SYS_GPC_MFPH_PC12MFP_Msk (0xful << SYS_GPC_MFPH_PC12MFP_Pos) /*!< SYS_T::GPC_MFPH: PC12MFP Mask */ + +#define SYS_GPC_MFPH_PC13MFP_Pos (20) /*!< SYS_T::GPC_MFPH: PC13MFP Position */ +#define SYS_GPC_MFPH_PC13MFP_Msk (0xful << SYS_GPC_MFPH_PC13MFP_Pos) /*!< SYS_T::GPC_MFPH: PC13MFP Mask */ + +#define SYS_GPC_MFPH_PC14MFP_Pos (24) /*!< SYS_T::GPC_MFPH: PC14MFP Position */ +#define SYS_GPC_MFPH_PC14MFP_Msk (0xful << SYS_GPC_MFPH_PC14MFP_Pos) /*!< SYS_T::GPC_MFPH: PC14MFP Mask */ + +#define SYS_GPC_MFPH_PC15MFP_Pos (28) /*!< SYS_T::GPC_MFPH: PC15MFP Position */ +#define SYS_GPC_MFPH_PC15MFP_Msk (0xful << SYS_GPC_MFPH_PC15MFP_Pos) /*!< SYS_T::GPC_MFPH: PC15MFP Mask */ + +#define SYS_GPD_MFPL_PD0MFP_Pos (0) /*!< SYS_T::GPD_MFPL: PD0MFP Position */ +#define SYS_GPD_MFPL_PD0MFP_Msk (0xful << SYS_GPD_MFPL_PD0MFP_Pos) /*!< SYS_T::GPD_MFPL: PD0MFP Mask */ + +#define SYS_GPD_MFPL_PD1MFP_Pos (4) /*!< SYS_T::GPD_MFPL: PD1MFP Position */ +#define SYS_GPD_MFPL_PD1MFP_Msk (0xful << SYS_GPD_MFPL_PD1MFP_Pos) /*!< SYS_T::GPD_MFPL: PD1MFP Mask */ + +#define SYS_GPD_MFPL_PD2MFP_Pos (8) /*!< SYS_T::GPD_MFPL: PD2MFP Position */ +#define SYS_GPD_MFPL_PD2MFP_Msk (0xful << SYS_GPD_MFPL_PD2MFP_Pos) /*!< SYS_T::GPD_MFPL: PD2MFP Mask */ + +#define SYS_GPD_MFPL_PD3MFP_Pos (12) /*!< SYS_T::GPD_MFPL: PD3MFP Position */ +#define SYS_GPD_MFPL_PD3MFP_Msk (0xful << SYS_GPD_MFPL_PD3MFP_Pos) /*!< SYS_T::GPD_MFPL: PD3MFP Mask */ + +#define SYS_GPD_MFPL_PD4MFP_Pos (16) /*!< SYS_T::GPD_MFPL: PD4MFP Position */ +#define SYS_GPD_MFPL_PD4MFP_Msk (0xful << SYS_GPD_MFPL_PD4MFP_Pos) /*!< SYS_T::GPD_MFPL: PD4MFP Mask */ + +#define SYS_GPD_MFPL_PD5MFP_Pos (20) /*!< SYS_T::GPD_MFPL: PD5MFP Position */ +#define SYS_GPD_MFPL_PD5MFP_Msk (0xful << SYS_GPD_MFPL_PD5MFP_Pos) /*!< SYS_T::GPD_MFPL: PD5MFP Mask */ + +#define SYS_GPD_MFPL_PD6MFP_Pos (24) /*!< SYS_T::GPD_MFPL: PD6MFP Position */ +#define SYS_GPD_MFPL_PD6MFP_Msk (0xful << SYS_GPD_MFPL_PD6MFP_Pos) /*!< SYS_T::GPD_MFPL: PD6MFP Mask */ + +#define SYS_GPD_MFPL_PD7MFP_Pos (28) /*!< SYS_T::GPD_MFPL: PD7MFP Position */ +#define SYS_GPD_MFPL_PD7MFP_Msk (0xful << SYS_GPD_MFPL_PD7MFP_Pos) /*!< SYS_T::GPD_MFPL: PD7MFP Mask */ + +#define SYS_GPD_MFPH_PD8MFP_Pos (0) /*!< SYS_T::GPD_MFPH: PD8MFP Position */ +#define SYS_GPD_MFPH_PD8MFP_Msk (0xful << SYS_GPD_MFPH_PD8MFP_Pos) /*!< SYS_T::GPD_MFPH: PD8MFP Mask */ + +#define SYS_GPD_MFPH_PD9MFP_Pos (4) /*!< SYS_T::GPD_MFPH: PD9MFP Position */ +#define SYS_GPD_MFPH_PD9MFP_Msk (0xful << SYS_GPD_MFPH_PD9MFP_Pos) /*!< SYS_T::GPD_MFPH: PD9MFP Mask */ + +#define SYS_GPD_MFPH_PD10MFP_Pos (8) /*!< SYS_T::GPD_MFPH: PD10MFP Position */ +#define SYS_GPD_MFPH_PD10MFP_Msk (0xful << SYS_GPD_MFPH_PD10MFP_Pos) /*!< SYS_T::GPD_MFPH: PD10MFP Mask */ + +#define SYS_GPD_MFPH_PD11MFP_Pos (12) /*!< SYS_T::GPD_MFPH: PD11MFP Position */ +#define SYS_GPD_MFPH_PD11MFP_Msk (0xful << SYS_GPD_MFPH_PD11MFP_Pos) /*!< SYS_T::GPD_MFPH: PD11MFP Mask */ + +#define SYS_GPD_MFPH_PD12MFP_Pos (16) /*!< SYS_T::GPD_MFPH: PD12MFP Position */ +#define SYS_GPD_MFPH_PD12MFP_Msk (0xful << SYS_GPD_MFPH_PD12MFP_Pos) /*!< SYS_T::GPD_MFPH: PD12MFP Mask */ + +#define SYS_GPD_MFPH_PD13MFP_Pos (20) /*!< SYS_T::GPD_MFPH: PD13MFP Position */ +#define SYS_GPD_MFPH_PD13MFP_Msk (0xful << SYS_GPD_MFPH_PD13MFP_Pos) /*!< SYS_T::GPD_MFPH: PD13MFP Mask */ + +#define SYS_GPD_MFPH_PD14MFP_Pos (24) /*!< SYS_T::GPD_MFPH: PD14MFP Position */ +#define SYS_GPD_MFPH_PD14MFP_Msk (0xful << SYS_GPD_MFPH_PD14MFP_Pos) /*!< SYS_T::GPD_MFPH: PD14MFP Mask */ + +#define SYS_GPD_MFPH_PD15MFP_Pos (28) /*!< SYS_T::GPD_MFPH: PD15MFP Position */ +#define SYS_GPD_MFPH_PD15MFP_Msk (0xful << SYS_GPD_MFPH_PD15MFP_Pos) /*!< SYS_T::GPD_MFPH: PD15MFP Mask */ + +#define SYS_GPE_MFPL_PE0MFP_Pos (0) /*!< SYS_T::GPE_MFPL: PE0MFP Position */ +#define SYS_GPE_MFPL_PE0MFP_Msk (0xful << SYS_GPE_MFPL_PE0MFP_Pos) /*!< SYS_T::GPE_MFPL: PE0MFP Mask */ + +#define SYS_GPE_MFPL_PE1MFP_Pos (4) /*!< SYS_T::GPE_MFPL: PE1MFP Position */ +#define SYS_GPE_MFPL_PE1MFP_Msk (0xful << SYS_GPE_MFPL_PE1MFP_Pos) /*!< SYS_T::GPE_MFPL: PE1MFP Mask */ + +#define SYS_GPE_MFPL_PE2MFP_Pos (8) /*!< SYS_T::GPE_MFPL: PE2MFP Position */ +#define SYS_GPE_MFPL_PE2MFP_Msk (0xful << SYS_GPE_MFPL_PE2MFP_Pos) /*!< SYS_T::GPE_MFPL: PE2MFP Mask */ + +#define SYS_GPE_MFPL_PE3MFP_Pos (12) /*!< SYS_T::GPE_MFPL: PE3MFP Position */ +#define SYS_GPE_MFPL_PE3MFP_Msk (0xful << SYS_GPE_MFPL_PE3MFP_Pos) /*!< SYS_T::GPE_MFPL: PE3MFP Mask */ + +#define SYS_GPE_MFPL_PE4MFP_Pos (16) /*!< SYS_T::GPE_MFPL: PE4MFP Position */ +#define SYS_GPE_MFPL_PE4MFP_Msk (0xful << SYS_GPE_MFPL_PE4MFP_Pos) /*!< SYS_T::GPE_MFPL: PE4MFP Mask */ + +#define SYS_GPE_MFPL_PE5MFP_Pos (20) /*!< SYS_T::GPE_MFPL: PE5MFP Position */ +#define SYS_GPE_MFPL_PE5MFP_Msk (0xful << SYS_GPE_MFPL_PE5MFP_Pos) /*!< SYS_T::GPE_MFPL: PE5MFP Mask */ + +#define SYS_GPE_MFPL_PE6MFP_Pos (24) /*!< SYS_T::GPE_MFPL: PE6MFP Position */ +#define SYS_GPE_MFPL_PE6MFP_Msk (0xful << SYS_GPE_MFPL_PE6MFP_Pos) /*!< SYS_T::GPE_MFPL: PE6MFP Mask */ + +#define SYS_GPE_MFPL_PE7MFP_Pos (28) /*!< SYS_T::GPE_MFPL: PE7MFP Position */ +#define SYS_GPE_MFPL_PE7MFP_Msk (0xful << SYS_GPE_MFPL_PE7MFP_Pos) /*!< SYS_T::GPE_MFPL: PE7MFP Mask */ + +#define SYS_GPE_MFPH_PE8MFP_Pos (0) /*!< SYS_T::GPE_MFPH: PE8MFP Position */ +#define SYS_GPE_MFPH_PE8MFP_Msk (0xful << SYS_GPE_MFPH_PE8MFP_Pos) /*!< SYS_T::GPE_MFPH: PE8MFP Mask */ + +#define SYS_GPE_MFPH_PE9MFP_Pos (4) /*!< SYS_T::GPE_MFPH: PE9MFP Position */ +#define SYS_GPE_MFPH_PE9MFP_Msk (0xful << SYS_GPE_MFPH_PE9MFP_Pos) /*!< SYS_T::GPE_MFPH: PE9MFP Mask */ + +#define SYS_GPE_MFPH_PE10MFP_Pos (8) /*!< SYS_T::GPE_MFPH: PE10MFP Position */ +#define SYS_GPE_MFPH_PE10MFP_Msk (0xful << SYS_GPE_MFPH_PE10MFP_Pos) /*!< SYS_T::GPE_MFPH: PE10MFP Mask */ + +#define SYS_GPE_MFPH_PE11MFP_Pos (12) /*!< SYS_T::GPE_MFPH: PE11MFP Position */ +#define SYS_GPE_MFPH_PE11MFP_Msk (0xful << SYS_GPE_MFPH_PE11MFP_Pos) /*!< SYS_T::GPE_MFPH: PE11MFP Mask */ + +#define SYS_GPE_MFPH_PE12MFP_Pos (16) /*!< SYS_T::GPE_MFPH: PE12MFP Position */ +#define SYS_GPE_MFPH_PE12MFP_Msk (0xful << SYS_GPE_MFPH_PE12MFP_Pos) /*!< SYS_T::GPE_MFPH: PE12MFP Mask */ + +#define SYS_GPE_MFPH_PE13MFP_Pos (20) /*!< SYS_T::GPE_MFPH: PE13MFP Position */ +#define SYS_GPE_MFPH_PE13MFP_Msk (0xful << SYS_GPE_MFPH_PE13MFP_Pos) /*!< SYS_T::GPE_MFPH: PE13MFP Mask */ + +#define SYS_GPE_MFPH_PE14MFP_Pos (24) /*!< SYS_T::GPE_MFPH: PE14_MFP Position */ +#define SYS_GPE_MFPH_PE14MFP_Msk (0xful << SYS_GPE_MFPH_PE14MFP_Pos) /*!< SYS_T::GPE_MFPH: PE14_MFP Mask */ + +#define SYS_GPE_MFPH_PE15MFP_Pos (28) /*!< SYS_T::GPE_MFPH: PE15_MFP Position */ +#define SYS_GPE_MFPH_PE15MFP_Msk (0xful << SYS_GPE_MFPH_PE15MFP_Pos) /*!< SYS_T::GPE_MFPH: PE15_MFP Mask */ + +#define SYS_GPF_MFPL_PF0MFP_Pos (0) /*!< SYS_T::GPF_MFPL: PF0MFP Position */ +#define SYS_GPF_MFPL_PF0MFP_Msk (0xful << SYS_GPF_MFPL_PF0MFP_Pos) /*!< SYS_T::GPF_MFPL: PF0MFP Mask */ + +#define SYS_GPF_MFPL_PF1MFP_Pos (4) /*!< SYS_T::GPF_MFPL: PF1MFP Position */ +#define SYS_GPF_MFPL_PF1MFP_Msk (0xful << SYS_GPF_MFPL_PF1MFP_Pos) /*!< SYS_T::GPF_MFPL: PF1MFP Mask */ + +#define SYS_GPF_MFPL_PF2MFP_Pos (8) /*!< SYS_T::GPF_MFPL: PF2MFP Position */ +#define SYS_GPF_MFPL_PF2MFP_Msk (0xful << SYS_GPF_MFPL_PF2MFP_Pos) /*!< SYS_T::GPF_MFPL: PF2MFP Mask */ + +#define SYS_GPF_MFPL_PF3MFP_Pos (12) /*!< SYS_T::GPF_MFPL: PF3MFP Position */ +#define SYS_GPF_MFPL_PF3MFP_Msk (0xful << SYS_GPF_MFPL_PF3MFP_Pos) /*!< SYS_T::GPF_MFPL: PF3MFP Mask */ + +#define SYS_GPF_MFPL_PF4MFP_Pos (16) /*!< SYS_T::GPF_MFPL: PF4MFP Position */ +#define SYS_GPF_MFPL_PF4MFP_Msk (0xful << SYS_GPF_MFPL_PF4MFP_Pos) /*!< SYS_T::GPF_MFPL: PF4MFP Mask */ + +#define SYS_GPF_MFPL_PF5MFP_Pos (20) /*!< SYS_T::GPF_MFPL: PF5MFP Position */ +#define SYS_GPF_MFPL_PF5MFP_Msk (0xful << SYS_GPF_MFPL_PF5MFP_Pos) /*!< SYS_T::GPF_MFPL: PF5MFP Mask */ + +#define SYS_GPF_MFPL_PF6MFP_Pos (24) /*!< SYS_T::GPF_MFPL: PF6MFP Position */ +#define SYS_GPF_MFPL_PF6MFP_Msk (0xful << SYS_GPF_MFPL_PF6MFP_Pos) /*!< SYS_T::GPF_MFPL: PF6MFP Mask */ + +#define SYS_GPF_MFPL_PF7MFP_Pos (28) /*!< SYS_T::GPF_MFPL: PF7MFP Position */ +#define SYS_GPF_MFPL_PF7MFP_Msk (0xful << SYS_GPF_MFPL_PF7MFP_Pos) /*!< SYS_T::GPF_MFPL: PF7MFP Mask */ + +#define SYS_GPF_MFPH_PF8MFP_Pos (0) /*!< SYS_T::GPF_MFPH: PF8MFP Position */ +#define SYS_GPF_MFPH_PF8MFP_Msk (0xful << SYS_GPF_MFPH_PF8MFP_Pos) /*!< SYS_T::GPF_MFPH: PF8MFP Mask */ + +#define SYS_GPF_MFPH_PF9MFP_Pos (4) /*!< SYS_T::GPF_MFPH: PF9MFP Position */ +#define SYS_GPF_MFPH_PF9MFP_Msk (0xful << SYS_GPF_MFPH_PF9MFP_Pos) /*!< SYS_T::GPF_MFPH: PF9MFP Mask */ + +#define SYS_GPF_MFPH_PF10MFP_Pos (8) /*!< SYS_T::GPF_MFPH: PF10MFP Position */ +#define SYS_GPF_MFPH_PF10MFP_Msk (0xful << SYS_GPF_MFPH_PF10MFP_Pos) /*!< SYS_T::GPF_MFPH: PF10MFP Mask */ + +#define SYS_GPF_MFPH_PF11MFP_Pos (12) /*!< SYS_T::GPF_MFPH: PF11MFP Position */ +#define SYS_GPF_MFPH_PF11MFP_Msk (0xful << SYS_GPF_MFPH_PF11MFP_Pos) /*!< SYS_T::GPF_MFPH: PF11MFP Mask */ + +#define SYS_GPF_MFPH_PF12MFP_Pos (16) /*!< SYS_T::GPF_MFPH: PF12MFP Position */ +#define SYS_GPF_MFPH_PF12MFP_Msk (0xful << SYS_GPF_MFPH_PF12MFP_Pos) /*!< SYS_T::GPF_MFPH: PF12MFP Mask */ + +#define SYS_GPF_MFPH_PF13MFP_Pos (20) /*!< SYS_T::GPF_MFPH: PF13MFP Position */ +#define SYS_GPF_MFPH_PF13MFP_Msk (0xful << SYS_GPF_MFPH_PF13MFP_Pos) /*!< SYS_T::GPF_MFPH: PF13MFP Mask */ + +#define SYS_GPF_MFPH_PF14MFP_Pos (24) /*!< SYS_T::GPF_MFPH: PF14MFP Position */ +#define SYS_GPF_MFPH_PF14MFP_Msk (0xful << SYS_GPF_MFPH_PF14MFP_Pos) /*!< SYS_T::GPF_MFPH: PF14MFP Mask */ + +#define SYS_GPF_MFPH_PF15MFP_Pos (28) /*!< SYS_T::GPF_MFPH: PF15MFP Position */ +#define SYS_GPF_MFPH_PF15MFP_Msk (0xful << SYS_GPF_MFPH_PF15MFP_Pos) /*!< SYS_T::GPF_MFPH: PF15MFP Mask */ + +#define SYS_GPA_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPA_MFOS: MFOS0 Position */ +#define SYS_GPA_MFOS_MFOS0_Msk (0x1ul << SYS_GPA_MFOS_MFOS0_Pos) /*!< SYS_T::GPA_MFOS: MFOS0 Mask */ + +#define SYS_GPA_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPA_MFOS: MFOS1 Position */ +#define SYS_GPA_MFOS_MFOS1_Msk (0x1ul << SYS_GPA_MFOS_MFOS1_Pos) /*!< SYS_T::GPA_MFOS: MFOS1 Mask */ + +#define SYS_GPA_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPA_MFOS: MFOS2 Position */ +#define SYS_GPA_MFOS_MFOS2_Msk (0x1ul << SYS_GPA_MFOS_MFOS2_Pos) /*!< SYS_T::GPA_MFOS: MFOS2 Mask */ + +#define SYS_GPA_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPA_MFOS: MFOS3 Position */ +#define SYS_GPA_MFOS_MFOS3_Msk (0x1ul << SYS_GPA_MFOS_MFOS3_Pos) /*!< SYS_T::GPA_MFOS: MFOS3 Mask */ + +#define SYS_GPA_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPA_MFOS: MFOS4 Position */ +#define SYS_GPA_MFOS_MFOS4_Msk (0x1ul << SYS_GPA_MFOS_MFOS4_Pos) /*!< SYS_T::GPA_MFOS: MFOS4 Mask */ + +#define SYS_GPA_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPA_MFOS: MFOS5 Position */ +#define SYS_GPA_MFOS_MFOS5_Msk (0x1ul << SYS_GPA_MFOS_MFOS5_Pos) /*!< SYS_T::GPA_MFOS: MFOS5 Mask */ + +#define SYS_GPA_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPA_MFOS: MFOS6 Position */ +#define SYS_GPA_MFOS_MFOS6_Msk (0x1ul << SYS_GPA_MFOS_MFOS6_Pos) /*!< SYS_T::GPA_MFOS: MFOS6 Mask */ + +#define SYS_GPA_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPA_MFOS: MFOS7 Position */ +#define SYS_GPA_MFOS_MFOS7_Msk (0x1ul << SYS_GPA_MFOS_MFOS7_Pos) /*!< SYS_T::GPA_MFOS: MFOS7 Mask */ + +#define SYS_GPA_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPA_MFOS: MFOS8 Position */ +#define SYS_GPA_MFOS_MFOS8_Msk (0x1ul << SYS_GPA_MFOS_MFOS8_Pos) /*!< SYS_T::GPA_MFOS: MFOS8 Mask */ + +#define SYS_GPA_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPA_MFOS: MFOS9 Position */ +#define SYS_GPA_MFOS_MFOS9_Msk (0x1ul << SYS_GPA_MFOS_MFOS9_Pos) /*!< SYS_T::GPA_MFOS: MFOS9 Mask */ + +#define SYS_GPA_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPA_MFOS: MFOS10 Position */ +#define SYS_GPA_MFOS_MFOS10_Msk (0x1ul << SYS_GPA_MFOS_MFOS10_Pos) /*!< SYS_T::GPA_MFOS: MFOS10 Mask */ + +#define SYS_GPA_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPA_MFOS: MFOS11 Position */ +#define SYS_GPA_MFOS_MFOS11_Msk (0x1ul << SYS_GPA_MFOS_MFOS11_Pos) /*!< SYS_T::GPA_MFOS: MFOS11 Mask */ + +#define SYS_GPA_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPA_MFOS: MFOS12 Position */ +#define SYS_GPA_MFOS_MFOS12_Msk (0x1ul << SYS_GPA_MFOS_MFOS12_Pos) /*!< SYS_T::GPA_MFOS: MFOS12 Mask */ + +#define SYS_GPA_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPA_MFOS: MFOS13 Position */ +#define SYS_GPA_MFOS_MFOS13_Msk (0x1ul << SYS_GPA_MFOS_MFOS13_Pos) /*!< SYS_T::GPA_MFOS: MFOS13 Mask */ + +#define SYS_GPA_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPA_MFOS: MFOS14 Position */ +#define SYS_GPA_MFOS_MFOS14_Msk (0x1ul << SYS_GPA_MFOS_MFOS14_Pos) /*!< SYS_T::GPA_MFOS: MFOS14 Mask */ + +#define SYS_GPA_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPA_MFOS: MFOS15 Position */ +#define SYS_GPA_MFOS_MFOS15_Msk (0x1ul << SYS_GPA_MFOS_MFOS15_Pos) /*!< SYS_T::GPA_MFOS: MFOS15 Mask */ + +#define SYS_GPB_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPB_MFOS: MFOS0 Position */ +#define SYS_GPB_MFOS_MFOS0_Msk (0x1ul << SYS_GPB_MFOS_MFOS0_Pos) /*!< SYS_T::GPB_MFOS: MFOS0 Mask */ + +#define SYS_GPB_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPB_MFOS: MFOS1 Position */ +#define SYS_GPB_MFOS_MFOS1_Msk (0x1ul << SYS_GPB_MFOS_MFOS1_Pos) /*!< SYS_T::GPB_MFOS: MFOS1 Mask */ + +#define SYS_GPB_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPB_MFOS: MFOS2 Position */ +#define SYS_GPB_MFOS_MFOS2_Msk (0x1ul << SYS_GPB_MFOS_MFOS2_Pos) /*!< SYS_T::GPB_MFOS: MFOS2 Mask */ + +#define SYS_GPB_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPB_MFOS: MFOS3 Position */ +#define SYS_GPB_MFOS_MFOS3_Msk (0x1ul << SYS_GPB_MFOS_MFOS3_Pos) /*!< SYS_T::GPB_MFOS: MFOS3 Mask */ + +#define SYS_GPB_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPB_MFOS: MFOS4 Position */ +#define SYS_GPB_MFOS_MFOS4_Msk (0x1ul << SYS_GPB_MFOS_MFOS4_Pos) /*!< SYS_T::GPB_MFOS: MFOS4 Mask */ + +#define SYS_GPB_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPB_MFOS: MFOS5 Position */ +#define SYS_GPB_MFOS_MFOS5_Msk (0x1ul << SYS_GPB_MFOS_MFOS5_Pos) /*!< SYS_T::GPB_MFOS: MFOS5 Mask */ + +#define SYS_GPB_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPB_MFOS: MFOS6 Position */ +#define SYS_GPB_MFOS_MFOS6_Msk (0x1ul << SYS_GPB_MFOS_MFOS6_Pos) /*!< SYS_T::GPB_MFOS: MFOS6 Mask */ + +#define SYS_GPB_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPB_MFOS: MFOS7 Position */ +#define SYS_GPB_MFOS_MFOS7_Msk (0x1ul << SYS_GPB_MFOS_MFOS7_Pos) /*!< SYS_T::GPB_MFOS: MFOS7 Mask */ + +#define SYS_GPB_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPB_MFOS: MFOS8 Position */ +#define SYS_GPB_MFOS_MFOS8_Msk (0x1ul << SYS_GPB_MFOS_MFOS8_Pos) /*!< SYS_T::GPB_MFOS: MFOS8 Mask */ + +#define SYS_GPB_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPB_MFOS: MFOS9 Position */ +#define SYS_GPB_MFOS_MFOS9_Msk (0x1ul << SYS_GPB_MFOS_MFOS9_Pos) /*!< SYS_T::GPB_MFOS: MFOS9 Mask */ + +#define SYS_GPB_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPB_MFOS: MFOS10 Position */ +#define SYS_GPB_MFOS_MFOS10_Msk (0x1ul << SYS_GPB_MFOS_MFOS10_Pos) /*!< SYS_T::GPB_MFOS: MFOS10 Mask */ + +#define SYS_GPB_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPB_MFOS: MFOS11 Position */ +#define SYS_GPB_MFOS_MFOS11_Msk (0x1ul << SYS_GPB_MFOS_MFOS11_Pos) /*!< SYS_T::GPB_MFOS: MFOS11 Mask */ + +#define SYS_GPB_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPB_MFOS: MFOS12 Position */ +#define SYS_GPB_MFOS_MFOS12_Msk (0x1ul << SYS_GPB_MFOS_MFOS12_Pos) /*!< SYS_T::GPB_MFOS: MFOS12 Mask */ + +#define SYS_GPB_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPB_MFOS: MFOS13 Position */ +#define SYS_GPB_MFOS_MFOS13_Msk (0x1ul << SYS_GPB_MFOS_MFOS13_Pos) /*!< SYS_T::GPB_MFOS: MFOS13 Mask */ + +#define SYS_GPB_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPB_MFOS: MFOS14 Position */ +#define SYS_GPB_MFOS_MFOS14_Msk (0x1ul << SYS_GPB_MFOS_MFOS14_Pos) /*!< SYS_T::GPB_MFOS: MFOS14 Mask */ + +#define SYS_GPB_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPB_MFOS: MFOS15 Position */ +#define SYS_GPB_MFOS_MFOS15_Msk (0x1ul << SYS_GPB_MFOS_MFOS15_Pos) /*!< SYS_T::GPB_MFOS: MFOS15 Mask */ + +#define SYS_GPC_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPC_MFOS: MFOS0 Position */ +#define SYS_GPC_MFOS_MFOS0_Msk (0x1ul << SYS_GPC_MFOS_MFOS0_Pos) /*!< SYS_T::GPC_MFOS: MFOS0 Mask */ + +#define SYS_GPC_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPC_MFOS: MFOS1 Position */ +#define SYS_GPC_MFOS_MFOS1_Msk (0x1ul << SYS_GPC_MFOS_MFOS1_Pos) /*!< SYS_T::GPC_MFOS: MFOS1 Mask */ + +#define SYS_GPC_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPC_MFOS: MFOS2 Position */ +#define SYS_GPC_MFOS_MFOS2_Msk (0x1ul << SYS_GPC_MFOS_MFOS2_Pos) /*!< SYS_T::GPC_MFOS: MFOS2 Mask */ + +#define SYS_GPC_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPC_MFOS: MFOS3 Position */ +#define SYS_GPC_MFOS_MFOS3_Msk (0x1ul << SYS_GPC_MFOS_MFOS3_Pos) /*!< SYS_T::GPC_MFOS: MFOS3 Mask */ + +#define SYS_GPC_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPC_MFOS: MFOS4 Position */ +#define SYS_GPC_MFOS_MFOS4_Msk (0x1ul << SYS_GPC_MFOS_MFOS4_Pos) /*!< SYS_T::GPC_MFOS: MFOS4 Mask */ + +#define SYS_GPC_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPC_MFOS: MFOS5 Position */ +#define SYS_GPC_MFOS_MFOS5_Msk (0x1ul << SYS_GPC_MFOS_MFOS5_Pos) /*!< SYS_T::GPC_MFOS: MFOS5 Mask */ + +#define SYS_GPC_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPC_MFOS: MFOS6 Position */ +#define SYS_GPC_MFOS_MFOS6_Msk (0x1ul << SYS_GPC_MFOS_MFOS6_Pos) /*!< SYS_T::GPC_MFOS: MFOS6 Mask */ + +#define SYS_GPC_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPC_MFOS: MFOS7 Position */ +#define SYS_GPC_MFOS_MFOS7_Msk (0x1ul << SYS_GPC_MFOS_MFOS7_Pos) /*!< SYS_T::GPC_MFOS: MFOS7 Mask */ + +#define SYS_GPC_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPC_MFOS: MFOS8 Position */ +#define SYS_GPC_MFOS_MFOS8_Msk (0x1ul << SYS_GPC_MFOS_MFOS8_Pos) /*!< SYS_T::GPC_MFOS: MFOS8 Mask */ + +#define SYS_GPC_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPC_MFOS: MFOS9 Position */ +#define SYS_GPC_MFOS_MFOS9_Msk (0x1ul << SYS_GPC_MFOS_MFOS9_Pos) /*!< SYS_T::GPC_MFOS: MFOS9 Mask */ + +#define SYS_GPC_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPC_MFOS: MFOS10 Position */ +#define SYS_GPC_MFOS_MFOS10_Msk (0x1ul << SYS_GPC_MFOS_MFOS10_Pos) /*!< SYS_T::GPC_MFOS: MFOS10 Mask */ + +#define SYS_GPC_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPC_MFOS: MFOS11 Position */ +#define SYS_GPC_MFOS_MFOS11_Msk (0x1ul << SYS_GPC_MFOS_MFOS11_Pos) /*!< SYS_T::GPC_MFOS: MFOS11 Mask */ + +#define SYS_GPC_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPC_MFOS: MFOS12 Position */ +#define SYS_GPC_MFOS_MFOS12_Msk (0x1ul << SYS_GPC_MFOS_MFOS12_Pos) /*!< SYS_T::GPC_MFOS: MFOS12 Mask */ + +#define SYS_GPC_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPC_MFOS: MFOS13 Position */ +#define SYS_GPC_MFOS_MFOS13_Msk (0x1ul << SYS_GPC_MFOS_MFOS13_Pos) /*!< SYS_T::GPC_MFOS: MFOS13 Mask */ + +#define SYS_GPC_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPC_MFOS: MFOS14 Position */ +#define SYS_GPC_MFOS_MFOS14_Msk (0x1ul << SYS_GPC_MFOS_MFOS14_Pos) /*!< SYS_T::GPC_MFOS: MFOS14 Mask */ + +#define SYS_GPC_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPC_MFOS: MFOS15 Position */ +#define SYS_GPC_MFOS_MFOS15_Msk (0x1ul << SYS_GPC_MFOS_MFOS15_Pos) /*!< SYS_T::GPC_MFOS: MFOS15 Mask */ + +#define SYS_GPD_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPD_MFOS: MFOS0 Position */ +#define SYS_GPD_MFOS_MFOS0_Msk (0x1ul << SYS_GPD_MFOS_MFOS0_Pos) /*!< SYS_T::GPD_MFOS: MFOS0 Mask */ + +#define SYS_GPD_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPD_MFOS: MFOS1 Position */ +#define SYS_GPD_MFOS_MFOS1_Msk (0x1ul << SYS_GPD_MFOS_MFOS1_Pos) /*!< SYS_T::GPD_MFOS: MFOS1 Mask */ + +#define SYS_GPD_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPD_MFOS: MFOS2 Position */ +#define SYS_GPD_MFOS_MFOS2_Msk (0x1ul << SYS_GPD_MFOS_MFOS2_Pos) /*!< SYS_T::GPD_MFOS: MFOS2 Mask */ + +#define SYS_GPD_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPD_MFOS: MFOS3 Position */ +#define SYS_GPD_MFOS_MFOS3_Msk (0x1ul << SYS_GPD_MFOS_MFOS3_Pos) /*!< SYS_T::GPD_MFOS: MFOS3 Mask */ + +#define SYS_GPD_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPD_MFOS: MFOS4 Position */ +#define SYS_GPD_MFOS_MFOS4_Msk (0x1ul << SYS_GPD_MFOS_MFOS4_Pos) /*!< SYS_T::GPD_MFOS: MFOS4 Mask */ + +#define SYS_GPD_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPD_MFOS: MFOS5 Position */ +#define SYS_GPD_MFOS_MFOS5_Msk (0x1ul << SYS_GPD_MFOS_MFOS5_Pos) /*!< SYS_T::GPD_MFOS: MFOS5 Mask */ + +#define SYS_GPD_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPD_MFOS: MFOS6 Position */ +#define SYS_GPD_MFOS_MFOS6_Msk (0x1ul << SYS_GPD_MFOS_MFOS6_Pos) /*!< SYS_T::GPD_MFOS: MFOS6 Mask */ + +#define SYS_GPD_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPD_MFOS: MFOS7 Position */ +#define SYS_GPD_MFOS_MFOS7_Msk (0x1ul << SYS_GPD_MFOS_MFOS7_Pos) /*!< SYS_T::GPD_MFOS: MFOS7 Mask */ + +#define SYS_GPD_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPD_MFOS: MFOS8 Position */ +#define SYS_GPD_MFOS_MFOS8_Msk (0x1ul << SYS_GPD_MFOS_MFOS8_Pos) /*!< SYS_T::GPD_MFOS: MFOS8 Mask */ + +#define SYS_GPD_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPD_MFOS: MFOS9 Position */ +#define SYS_GPD_MFOS_MFOS9_Msk (0x1ul << SYS_GPD_MFOS_MFOS9_Pos) /*!< SYS_T::GPD_MFOS: MFOS9 Mask */ + +#define SYS_GPD_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPD_MFOS: MFOS10 Position */ +#define SYS_GPD_MFOS_MFOS10_Msk (0x1ul << SYS_GPD_MFOS_MFOS10_Pos) /*!< SYS_T::GPD_MFOS: MFOS10 Mask */ + +#define SYS_GPD_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPD_MFOS: MFOS11 Position */ +#define SYS_GPD_MFOS_MFOS11_Msk (0x1ul << SYS_GPD_MFOS_MFOS11_Pos) /*!< SYS_T::GPD_MFOS: MFOS11 Mask */ + +#define SYS_GPD_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPD_MFOS: MFOS12 Position */ +#define SYS_GPD_MFOS_MFOS12_Msk (0x1ul << SYS_GPD_MFOS_MFOS12_Pos) /*!< SYS_T::GPD_MFOS: MFOS12 Mask */ + +#define SYS_GPD_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPD_MFOS: MFOS13 Position */ +#define SYS_GPD_MFOS_MFOS13_Msk (0x1ul << SYS_GPD_MFOS_MFOS13_Pos) /*!< SYS_T::GPD_MFOS: MFOS13 Mask */ + +#define SYS_GPD_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPD_MFOS: MFOS14 Position */ +#define SYS_GPD_MFOS_MFOS14_Msk (0x1ul << SYS_GPD_MFOS_MFOS14_Pos) /*!< SYS_T::GPD_MFOS: MFOS14 Mask */ + +#define SYS_GPD_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPD_MFOS: MFOS15 Position */ +#define SYS_GPD_MFOS_MFOS15_Msk (0x1ul << SYS_GPD_MFOS_MFOS15_Pos) /*!< SYS_T::GPD_MFOS: MFOS15 Mask */ + +#define SYS_GPE_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPE_MFOS: MFOS0 Position */ +#define SYS_GPE_MFOS_MFOS0_Msk (0x1ul << SYS_GPE_MFOS_MFOS0_Pos) /*!< SYS_T::GPE_MFOS: MFOS0 Mask */ + +#define SYS_GPE_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPE_MFOS: MFOS1 Position */ +#define SYS_GPE_MFOS_MFOS1_Msk (0x1ul << SYS_GPE_MFOS_MFOS1_Pos) /*!< SYS_T::GPE_MFOS: MFOS1 Mask */ + +#define SYS_GPE_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPE_MFOS: MFOS2 Position */ +#define SYS_GPE_MFOS_MFOS2_Msk (0x1ul << SYS_GPE_MFOS_MFOS2_Pos) /*!< SYS_T::GPE_MFOS: MFOS2 Mask */ + +#define SYS_GPE_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPE_MFOS: MFOS3 Position */ +#define SYS_GPE_MFOS_MFOS3_Msk (0x1ul << SYS_GPE_MFOS_MFOS3_Pos) /*!< SYS_T::GPE_MFOS: MFOS3 Mask */ + +#define SYS_GPE_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPE_MFOS: MFOS4 Position */ +#define SYS_GPE_MFOS_MFOS4_Msk (0x1ul << SYS_GPE_MFOS_MFOS4_Pos) /*!< SYS_T::GPE_MFOS: MFOS4 Mask */ + +#define SYS_GPE_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPE_MFOS: MFOS5 Position */ +#define SYS_GPE_MFOS_MFOS5_Msk (0x1ul << SYS_GPE_MFOS_MFOS5_Pos) /*!< SYS_T::GPE_MFOS: MFOS5 Mask */ + +#define SYS_GPE_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPE_MFOS: MFOS6 Position */ +#define SYS_GPE_MFOS_MFOS6_Msk (0x1ul << SYS_GPE_MFOS_MFOS6_Pos) /*!< SYS_T::GPE_MFOS: MFOS6 Mask */ + +#define SYS_GPE_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPE_MFOS: MFOS7 Position */ +#define SYS_GPE_MFOS_MFOS7_Msk (0x1ul << SYS_GPE_MFOS_MFOS7_Pos) /*!< SYS_T::GPE_MFOS: MFOS7 Mask */ + +#define SYS_GPE_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPE_MFOS: MFOS8 Position */ +#define SYS_GPE_MFOS_MFOS8_Msk (0x1ul << SYS_GPE_MFOS_MFOS8_Pos) /*!< SYS_T::GPE_MFOS: MFOS8 Mask */ + +#define SYS_GPE_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPE_MFOS: MFOS9 Position */ +#define SYS_GPE_MFOS_MFOS9_Msk (0x1ul << SYS_GPE_MFOS_MFOS9_Pos) /*!< SYS_T::GPE_MFOS: MFOS9 Mask */ + +#define SYS_GPE_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPE_MFOS: MFOS10 Position */ +#define SYS_GPE_MFOS_MFOS10_Msk (0x1ul << SYS_GPE_MFOS_MFOS10_Pos) /*!< SYS_T::GPE_MFOS: MFOS10 Mask */ + +#define SYS_GPE_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPE_MFOS: MFOS11 Position */ +#define SYS_GPE_MFOS_MFOS11_Msk (0x1ul << SYS_GPE_MFOS_MFOS11_Pos) /*!< SYS_T::GPE_MFOS: MFOS11 Mask */ + +#define SYS_GPE_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPE_MFOS: MFOS12 Position */ +#define SYS_GPE_MFOS_MFOS12_Msk (0x1ul << SYS_GPE_MFOS_MFOS12_Pos) /*!< SYS_T::GPE_MFOS: MFOS12 Mask */ + +#define SYS_GPE_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPE_MFOS: MFOS13 Position */ +#define SYS_GPE_MFOS_MFOS13_Msk (0x1ul << SYS_GPE_MFOS_MFOS13_Pos) /*!< SYS_T::GPE_MFOS: MFOS13 Mask */ + +#define SYS_GPE_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPE_MFOS: MFOS14 Position */ +#define SYS_GPE_MFOS_MFOS14_Msk (0x1ul << SYS_GPE_MFOS_MFOS14_Pos) /*!< SYS_T::GPE_MFOS: MFOS14 Mask */ + +#define SYS_GPE_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPE_MFOS: MFOS15 Position */ +#define SYS_GPE_MFOS_MFOS15_Msk (0x1ul << SYS_GPE_MFOS_MFOS15_Pos) /*!< SYS_T::GPE_MFOS: MFOS15 Mask */ + +#define SYS_GPF_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPF_MFOS: MFOS0 Position */ +#define SYS_GPF_MFOS_MFOS0_Msk (0x1ul << SYS_GPF_MFOS_MFOS0_Pos) /*!< SYS_T::GPF_MFOS: MFOS0 Mask */ + +#define SYS_GPF_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPF_MFOS: MFOS1 Position */ +#define SYS_GPF_MFOS_MFOS1_Msk (0x1ul << SYS_GPF_MFOS_MFOS1_Pos) /*!< SYS_T::GPF_MFOS: MFOS1 Mask */ + +#define SYS_GPF_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPF_MFOS: MFOS2 Position */ +#define SYS_GPF_MFOS_MFOS2_Msk (0x1ul << SYS_GPF_MFOS_MFOS2_Pos) /*!< SYS_T::GPF_MFOS: MFOS2 Mask */ + +#define SYS_GPF_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPF_MFOS: MFOS3 Position */ +#define SYS_GPF_MFOS_MFOS3_Msk (0x1ul << SYS_GPF_MFOS_MFOS3_Pos) /*!< SYS_T::GPF_MFOS: MFOS3 Mask */ + +#define SYS_GPF_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPF_MFOS: MFOS4 Position */ +#define SYS_GPF_MFOS_MFOS4_Msk (0x1ul << SYS_GPF_MFOS_MFOS4_Pos) /*!< SYS_T::GPF_MFOS: MFOS4 Mask */ + +#define SYS_GPF_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPF_MFOS: MFOS5 Position */ +#define SYS_GPF_MFOS_MFOS5_Msk (0x1ul << SYS_GPF_MFOS_MFOS5_Pos) /*!< SYS_T::GPF_MFOS: MFOS5 Mask */ + +#define SYS_GPF_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPF_MFOS: MFOS6 Position */ +#define SYS_GPF_MFOS_MFOS6_Msk (0x1ul << SYS_GPF_MFOS_MFOS6_Pos) /*!< SYS_T::GPF_MFOS: MFOS6 Mask */ + +#define SYS_GPF_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPF_MFOS: MFOS7 Position */ +#define SYS_GPF_MFOS_MFOS7_Msk (0x1ul << SYS_GPF_MFOS_MFOS7_Pos) /*!< SYS_T::GPF_MFOS: MFOS7 Mask */ + +#define SYS_GPF_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPF_MFOS: MFOS8 Position */ +#define SYS_GPF_MFOS_MFOS8_Msk (0x1ul << SYS_GPF_MFOS_MFOS8_Pos) /*!< SYS_T::GPF_MFOS: MFOS8 Mask */ + +#define SYS_GPF_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPF_MFOS: MFOS9 Position */ +#define SYS_GPF_MFOS_MFOS9_Msk (0x1ul << SYS_GPF_MFOS_MFOS9_Pos) /*!< SYS_T::GPF_MFOS: MFOS9 Mask */ + +#define SYS_GPF_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPF_MFOS: MFOS10 Position */ +#define SYS_GPF_MFOS_MFOS10_Msk (0x1ul << SYS_GPF_MFOS_MFOS10_Pos) /*!< SYS_T::GPF_MFOS: MFOS10 Mask */ + +#define SYS_GPF_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPF_MFOS: MFOS11 Position */ +#define SYS_GPF_MFOS_MFOS11_Msk (0x1ul << SYS_GPF_MFOS_MFOS11_Pos) /*!< SYS_T::GPF_MFOS: MFOS11 Mask */ + +#define SYS_GPF_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPF_MFOS: MFOS12 Position */ +#define SYS_GPF_MFOS_MFOS12_Msk (0x1ul << SYS_GPF_MFOS_MFOS12_Pos) /*!< SYS_T::GPF_MFOS: MFOS12 Mask */ + +#define SYS_GPF_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPF_MFOS: MFOS13 Position */ +#define SYS_GPF_MFOS_MFOS13_Msk (0x1ul << SYS_GPF_MFOS_MFOS13_Pos) /*!< SYS_T::GPF_MFOS: MFOS13 Mask */ + +#define SYS_GPF_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPF_MFOS: MFOS14 Position */ +#define SYS_GPF_MFOS_MFOS14_Msk (0x1ul << SYS_GPF_MFOS_MFOS14_Pos) /*!< SYS_T::GPF_MFOS: MFOS14 Mask */ + +#define SYS_GPF_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPF_MFOS: MFOS15 Position */ +#define SYS_GPF_MFOS_MFOS15_Msk (0x1ul << SYS_GPF_MFOS_MFOS15_Pos) /*!< SYS_T::GPF_MFOS: MFOS15 Mask */ + +#define SYS_MODCTL_MODEN_Pos (0) /*!< SYS_T::MODCTL: MODEN Position */ +#define SYS_MODCTL_MODEN_Msk (0x1ul << SYS_MODCTL_MODEN_Pos) /*!< SYS_T::MODCTL: MODEN Mask */ + +#define SYS_MODCTL_MODH_Pos (1) /*!< SYS_T::MODCTL: MODH Position */ +#define SYS_MODCTL_MODH_Msk (0x1ul << SYS_MODCTL_MODH_Pos) /*!< SYS_T::MODCTL: MODH Mask */ + +#define SYS_MODCTL_MODPWMSEL_Pos (4) /*!< SYS_T::MODCTL: MODPWMSEL Position */ +#define SYS_MODCTL_MODPWMSEL_Msk (0xful << SYS_MODCTL_MODPWMSEL_Pos) /*!< SYS_T::MODCTL: MODPWMSEL Mask */ + +#define SYS_SRAM_BISTCTL_SRBIST_Pos (0) /*!< SYS_T::SRAM_BISTCTL: SRBIST Position */ +#define SYS_SRAM_BISTCTL_SRBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: SRBIST Mask */ + +#define SYS_SRAM_BISTCTL_FMCBIST_Pos (2) /*!< SYS_T::SRAM_BISTCTL: FMCBIST Position */ +#define SYS_SRAM_BISTCTL_FMCBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_FMCBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: FMCBIST Mask */ + +#define SYS_SRAM_BISTCTL_USBBIST_Pos (4) /*!< SYS_T::SRAM_BISTCTL: USBBIST Position */ +#define SYS_SRAM_BISTCTL_USBBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_USBBIST_Pos) /*!< SYS_T::SRAM_BISTCTL: USBBIST Mask */ + +#define SYS_SRAM_BISTCTL_PDMABIST_Pos (7) /*!< SYS_T::SRAM_BISTCTL: PDMABIST Position */ +#define SYS_SRAM_BISTCTL_PDMABIST_Msk (0x1ul << SYS_SRAM_BISTCTL_PDMABIST_Pos) /*!< SYS_T::SRAM_BISTCTL: PDMABIST Mask */ + +#define SYS_SRAM_BISTSTS_SRBISTEF_Pos (0) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF Position */ +#define SYS_SRAM_BISTSTS_SRBISTEF_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBISTEF Mask */ + +#define SYS_SRAM_BISTSTS_CR0BISTEF_Pos (1) /*!< SYS_T::SRAM_BISTSTS: CR0BISTEF Position*/ +#define SYS_SRAM_BISTSTS_CR0BISTEF_Msk (0x1ul << SYS_SRAM_BISTSTS_CR0BISTEF_Pos) /*!< SYS_T::SRAM_BISTSTS: CR0BISTEF Mask */ + +#define SYS_SRAM_BISTSTS_CR1BISTEF_Pos (2) /*!< SYS_T::SRAM_BISTSTS: CR1BISTEF Position*/ +#define SYS_SRAM_BISTSTS_CR1BISTEF_Msk (0x1ul << SYS_SRAM_BISTSTS_CR1BISTEF_Pos) /*!< SYS_T::SRAM_BISTSTS: CR1BISTEF Mask */ + +#define SYS_SRAM_BISTSTS_USBBEF_Pos (4) /*!< SYS_T::SRAM_BISTSTS: USBBEF Position */ +#define SYS_SRAM_BISTSTS_USBBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_USBBEF_Pos) /*!< SYS_T::SRAM_BISTSTS: USBBEF Mask */ + +#define SYS_SRAM_BISTSTS_PDMABISTF_Pos (7) /*!< SYS_T::SRAM_BISTSTS: PDMABISTF Position*/ +#define SYS_SRAM_BISTSTS_PDMABISTF_Msk (0x1ul << SYS_SRAM_BISTSTS_PDMABISTF_Pos) /*!< SYS_T::SRAM_BISTSTS: PDMABISTF Mask */ + +#define SYS_SRAM_BISTSTS_SRBEND_Pos (16) /*!< SYS_T::SRAM_BISTSTS: SRBEND Position */ +#define SYS_SRAM_BISTSTS_SRBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: SRBEND Mask */ + +#define SYS_SRAM_BISTSTS_CR0BEND_Pos (17) /*!< SYS_T::SRAM_BISTSTS: CR0BEND Position */ +#define SYS_SRAM_BISTSTS_CR0BEND_Msk (0x1ul << SYS_SRAM_BISTSTS_CR0BEND_Pos) /*!< SYS_T::SRAM_BISTSTS: CR0BEND Mask */ + +#define SYS_SRAM_BISTSTS_CR1BEND_Pos (18) /*!< SYS_T::SRAM_BISTSTS: CR1BEND Position */ +#define SYS_SRAM_BISTSTS_CR1BEND_Msk (0x1ul << SYS_SRAM_BISTSTS_CR1BEND_Pos) /*!< SYS_T::SRAM_BISTSTS: CR1BEND Mask */ + +#define SYS_SRAM_BISTSTS_USBBEND_Pos (20) /*!< SYS_T::SRAM_BISTSTS: USBBEND Position */ +#define SYS_SRAM_BISTSTS_USBBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_USBBEND_Pos) /*!< SYS_T::SRAM_BISTSTS: USBBEND Mask */ + +#define SYS_SRAM_BISTSTS_PDMAEND_Pos (23) /*!< SYS_T::SRAM_BISTSTS: PDMAEND Position */ +#define SYS_SRAM_BISTSTS_PDMAEND_Msk (0x1ul << SYS_SRAM_BISTSTS_PDMAEND_Pos) /*!< SYS_T::SRAM_BISTSTS: PDMAEND Mask */ + +#define SYS_HIRCTRIMCTL_FREQSEL_Pos (0) /*!< SYS_T::HIRCTRIMCTL: FREQSEL Position */ +#define SYS_HIRCTRIMCTL_FREQSEL_Msk (0x3ul << SYS_HIRCTRIMCTL_FREQSEL_Pos) /*!< SYS_T::HIRCTRIMCTL: FREQSEL Mask */ + +#define SYS_HIRCTRIMCTL_LOOPSEL_Pos (4) /*!< SYS_T::HIRCTRIMCTL: LOOPSEL Position */ +#define SYS_HIRCTRIMCTL_LOOPSEL_Msk (0x3ul << SYS_HIRCTRIMCTL_LOOPSEL_Pos) /*!< SYS_T::HIRCTRIMCTL: LOOPSEL Mask */ + +#define SYS_HIRCTRIMCTL_RETRYCNT_Pos (6) /*!< SYS_T::HIRCTRIMCTL: RETRYCNT Position */ +#define SYS_HIRCTRIMCTL_RETRYCNT_Msk (0x3ul << SYS_HIRCTRIMCTL_RETRYCNT_Pos) /*!< SYS_T::HIRCTRIMCTL: RETRYCNT Mask */ + +#define SYS_HIRCTRIMCTL_CESTOPEN_Pos (8) /*!< SYS_T::HIRCTRIMCTL: CESTOPEN Position */ +#define SYS_HIRCTRIMCTL_CESTOPEN_Msk (0x1ul << SYS_HIRCTRIMCTL_CESTOPEN_Pos) /*!< SYS_T::HIRCTRIMCTL: CESTOPEN Mask */ + +#define SYS_HIRCTRIMCTL_BOUNDEN_Pos (9) /*!< SYS_T::HIRCTRIMCTL: BOUNDEN Position */ +#define SYS_HIRCTRIMCTL_BOUNDEN_Msk (0x1ul << SYS_HIRCTRIMCTL_BOUNDEN_Pos) /*!< SYS_T::HIRCTRIMCTL: BOUNDEN Mask */ + +#define SYS_HIRCTRIMCTL_REFCKSEL_Pos (10) /*!< SYS_T::HIRCTRIMCTL: REFCKSEL Position */ +#define SYS_HIRCTRIMCTL_REFCKSEL_Msk (0x1ul << SYS_HIRCTRIMCTL_REFCKSEL_Pos) /*!< SYS_T::HIRCTRIMCTL: REFCKSEL Mask */ + +#define SYS_HIRCTRIMCTL_BOUNDARY_Pos (16) /*!< SYS_T::HIRCTRIMCTL: BOUNDARY Position */ +#define SYS_HIRCTRIMCTL_BOUNDARY_Msk (0x1ful << SYS_HIRCTRIMCTL_BOUNDARY_Pos) /*!< SYS_T::HIRCTRIMCTL: BOUNDARY Mask */ + +#define SYS_HIRCTRIMIEN_TFALIEN_Pos (1) /*!< SYS_T::HIRCTRIMIEN: TFALIEN Position */ +#define SYS_HIRCTRIMIEN_TFALIEN_Msk (0x1ul << SYS_HIRCTRIMIEN_TFALIEN_Pos) /*!< SYS_T::HIRCTRIMIEN: TFALIEN Mask */ + +#define SYS_HIRCTRIMIEN_CLKEIEN_Pos (2) /*!< SYS_T::HIRCTRIMIEN: CLKEIEN Position */ +#define SYS_HIRCTRIMIEN_CLKEIEN_Msk (0x1ul << SYS_HIRCTRIMIEN_CLKEIEN_Pos) /*!< SYS_T::HIRCTRIMIEN: CLKEIEN Mask */ + +#define SYS_HIRCTRIMSTS_FREQLOCK_Pos (0) /*!< SYS_T::HIRCTRIMSTS: FREQLOCK Position */ +#define SYS_HIRCTRIMSTS_FREQLOCK_Msk (0x1ul << SYS_HIRCTRIMSTS_FREQLOCK_Pos) /*!< SYS_T::HIRCTRIMSTS: FREQLOCK Mask */ + +#define SYS_HIRCTRIMSTS_TFAILIF_Pos (1) /*!< SYS_T::HIRCTRIMSTS: TFAILIF Position */ +#define SYS_HIRCTRIMSTS_TFAILIF_Msk (0x1ul << SYS_HIRCTRIMSTS_TFAILIF_Pos) /*!< SYS_T::HIRCTRIMSTS: TFAILIF Mask */ + +#define SYS_HIRCTRIMSTS_CLKERIF_Pos (2) /*!< SYS_T::HIRCTRIMSTS: CLKERIF Position */ +#define SYS_HIRCTRIMSTS_CLKERIF_Msk (0x1ul << SYS_HIRCTRIMSTS_CLKERIF_Pos) /*!< SYS_T::HIRCTRIMSTS: CLKERIF Mask */ + +#define SYS_HIRCTRIMSTS_OVBDIF_Pos (3) /*!< SYS_T::HIRCTRIMSTS: OVBDIF Position */ +#define SYS_HIRCTRIMSTS_OVBDIF_Msk (0x1ul << SYS_HIRCTRIMSTS_OVBDIF_Pos) /*!< SYS_T::HIRCTRIMSTS: OVBDIF Mask */ + +#define SYS_REGLCTL_REGLCTL_Pos (0) /*!< SYS_T::REGLCTL: REGLCTL Position */ +#define SYS_REGLCTL_REGLCTL_Msk (0xfful << SYS_REGLCTL_REGLCTL_Pos) /*!< SYS_T::REGLCTL: REGLCTL Mask */ + +#define SYS_MIRCTRIMCTL_FREQSEL_Pos (0) /*!< SYS_T::MIRCTRIMCTL: FREQSEL Position */ +#define SYS_MIRCTRIMCTL_FREQSEL_Msk (0x3ul << SYS_MIRCTRIMCTL_FREQSEL_Pos) /*!< SYS_T::MIRCTRIMCTL: FREQSEL Mask */ + +#define SYS_MIRCTRIMCTL_LOOPSEL_Pos (4) /*!< SYS_T::MIRCTRIMCTL: LOOPSEL Position */ +#define SYS_MIRCTRIMCTL_LOOPSEL_Msk (0x3ul << SYS_MIRCTRIMCTL_LOOPSEL_Pos) /*!< SYS_T::MIRCTRIMCTL: LOOPSEL Mask */ + +#define SYS_MIRCTRIMCTL_RETRYCNT_Pos (6) /*!< SYS_T::MIRCTRIMCTL: RETRYCNT Position */ +#define SYS_MIRCTRIMCTL_RETRYCNT_Msk (0x3ul << SYS_MIRCTRIMCTL_RETRYCNT_Pos) /*!< SYS_T::MIRCTRIMCTL: RETRYCNT Mask */ + +#define SYS_MIRCTRIMCTL_CESTOPEN_Pos (8) /*!< SYS_T::MIRCTRIMCTL: CESTOPEN Position */ +#define SYS_MIRCTRIMCTL_CESTOPEN_Msk (0x1ul << SYS_MIRCTRIMCTL_CESTOPEN_Pos) /*!< SYS_T::MIRCTRIMCTL: CESTOPEN Mask */ + +#define SYS_MIRCTRIMCTL_BOUNDEN_Pos (9) /*!< SYS_T::MIRCTRIMCTL: BOUNDEN Position */ +#define SYS_MIRCTRIMCTL_BOUNDEN_Msk (0x1ul << SYS_MIRCTRIMCTL_BOUNDEN_Pos) /*!< SYS_T::MIRCTRIMCTL: BOUNDEN Mask */ + +#define SYS_MIRCTRIMCTL_REFCKSEL_Pos (10) /*!< SYS_T::MIRCTRIMCTL: REFCKSEL Position */ +#define SYS_MIRCTRIMCTL_REFCKSEL_Msk (0x1ul << SYS_MIRCTRIMCTL_REFCKSEL_Pos) /*!< SYS_T::MIRCTRIMCTL: REFCKSEL Mask */ + +#define SYS_MIRCTRIMCTL_BOUNDARY_Pos (16) /*!< SYS_T::MIRCTRIMCTL: BOUNDARY Position */ +#define SYS_MIRCTRIMCTL_BOUNDARY_Msk (0x1ful << SYS_MIRCTRIMCTL_BOUNDARY_Pos) /*!< SYS_T::MIRCTRIMCTL: BOUNDARY Mask */ + +#define SYS_MIRCTRIMIEN_TFALIEN_Pos (1) /*!< SYS_T::MIRCTRIMIEN: TFALIEN Position */ +#define SYS_MIRCTRIMIEN_TFALIEN_Msk (0x1ul << SYS_MIRCTRIMIEN_TFALIEN_Pos) /*!< SYS_T::MIRCTRIMIEN: TFALIEN Mask */ + +#define SYS_MIRCTRIMIEN_CLKEIEN_Pos (2) /*!< SYS_T::MIRCTRIMIEN: CLKEIEN Position */ +#define SYS_MIRCTRIMIEN_CLKEIEN_Msk (0x1ul << SYS_MIRCTRIMIEN_CLKEIEN_Pos) /*!< SYS_T::MIRCTRIMIEN: CLKEIEN Mask */ + +#define SYS_MIRCTRIMSTS_FREQLOCK_Pos (0) /*!< SYS_T::MIRCTRIMSTS: FREQLOCK Position */ +#define SYS_MIRCTRIMSTS_FREQLOCK_Msk (0x1ul << SYS_MIRCTRIMSTS_FREQLOCK_Pos) /*!< SYS_T::MIRCTRIMSTS: FREQLOCK Mask */ + +#define SYS_MIRCTRIMSTS_TFAILIF_Pos (1) /*!< SYS_T::MIRCTRIMSTS: TFAILIF Position */ +#define SYS_MIRCTRIMSTS_TFAILIF_Msk (0x1ul << SYS_MIRCTRIMSTS_TFAILIF_Pos) /*!< SYS_T::MIRCTRIMSTS: TFAILIF Mask */ + +#define SYS_MIRCTRIMSTS_CLKERIF_Pos (2) /*!< SYS_T::MIRCTRIMSTS: CLKERIF Position */ +#define SYS_MIRCTRIMSTS_CLKERIF_Msk (0x1ul << SYS_MIRCTRIMSTS_CLKERIF_Pos) /*!< SYS_T::MIRCTRIMSTS: CLKERIF Mask */ + +#define SYS_MIRCTRIMSTS_OVBDIF_Pos (3) /*!< SYS_T::MIRCTRIMSTS: OVBDIF Position */ +#define SYS_MIRCTRIMSTS_OVBDIF_Msk (0x1ul << SYS_MIRCTRIMSTS_OVBDIF_Pos) /*!< SYS_T::MIRCTRIMSTS: OVBDIF Mask */ + +#define SYS_RTCLVRIEN_IE_Pos (0) /*!< SYS_T::RTCLVRIEN: IE Position */ +#define SYS_RTCLVRIEN_IE_Msk (0x1ul << SYS_RTCLVRIEN_IE_Pos) /*!< SYS_T::RTCLVRIEN: IE Mask */ + +#define SYS_RTCLVRSTS_IF_Pos (0) /*!< SYS_T::RTCLVRSTS: IF Position */ +#define SYS_RTCLVRSTS_IF_Msk (0x1ul << SYS_RTCLVRSTS_IF_Pos) /*!< SYS_T::RTCLVRSTS: IF Mask */ + +#define SYS_RTCLVRSTS_RTCLVR_Pos (8) /*!< SYS_T::RTCLVRSTS: RTCLVR Position */ +#define SYS_RTCLVRSTS_RTCLVR_Msk (0x1ul << SYS_RTCLVRSTS_RTCLVR_Pos) /*!< SYS_T::RTCLVRSTS: RTCLVR Mask */ + +#define SYS_PORCTL1_POROFF_Pos (0) /*!< SYS_T::PORCTL1: POROFF Position */ +#define SYS_PORCTL1_POROFF_Msk (0xfffful << SYS_PORCTL1_POROFF_Pos) /*!< SYS_T::PORCTL1: POROFF Mask */ + +#define SYS_PLCTL_PLSEL_Pos (0) /*!< SYS_T::PLCTL: PLSEL Position */ +#define SYS_PLCTL_PLSEL_Msk (0x3ul << SYS_PLCTL_PLSEL_Pos) /*!< SYS_T::PLCTL: PLSEL Mask */ + +#define SYS_PLSTS_PLCBUSY_Pos (0) /*!< SYS_T::PLSTS: PLCBUSY Position */ +#define SYS_PLSTS_PLCBUSY_Msk (0x1ul << SYS_PLSTS_PLCBUSY_Pos) /*!< SYS_T::PLSTS: PLCBUSY Mask */ + +#define SYS_PLSTS_CURPL_Pos (8) /*!< SYS_T::PLSTS: CURPL Position */ +#define SYS_PLSTS_CURPL_Msk (0x3ul << SYS_PLSTS_CURPL_Pos) /*!< SYS_T::PLSTS: CURPL Mask */ + +/**@}*/ /* SYS_CONST */ +/**@}*/ /* end of SYS register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __SYS_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/timer_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/timer_reg.h new file mode 100644 index 00000000000..5ae5304b298 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/timer_reg.h @@ -0,0 +1,673 @@ +/**************************************************************************//** + * @file timer_reg.h + * @version V1.00 + * @brief TIMER register definition header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __TIMER_REG_H__ +#define __TIMER_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup TIMER Timer Controller (TIMER) + Memory Mapped Structure for TIMER Controller +@{ */ + +typedef struct +{ + + + /** + * @var TIMER_T::CTL + * Offset: 0x00 Timer Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |PSC |Prescale Counter + * | | |Timer input clock or event source is divided by (PSC+1) before it is fed to the timer up counter + * | | |If this field is 0 (PSC = 0), then there is no scaling. + * | | |Note: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value. + * |[15] |FUNCSEL |Function Selection + * | | |0 = Timer controller is used as timer function. + * | | |1 = Timer controller is used as PWM function. + * | | |Note: When timer is used as PWM, the clock source of time controller will be forced to PCLKx automatically. + * |[19] |INTRGEN |Inter-timer Trigger Mode Enable Bit + * | | |Setting this bit will enable the inter-timer trigger capture function. + * | | |The Timer0/2 will be in event counter mode and counting with external clock source or event + * | | |Also, Timer1/3 will be in trigger-counting mode of capture function. + * | | |0 = Inter-Timer Trigger Capture mode Disabled. + * | | |1 = Inter-Timer Trigger Capture mode Enabled. + * | | |Note: For Timer1/3, this bit is ignored and the read back value is always 0. + * |[20] |PERIOSEL |Periodic Mode Behavior Selection Enable Bit + * | | |0 = The behavior selection in periodic mode is Disabled. + * | | |When user updates CMPDAT while timer is running in periodic mode, + * | | |CNT will be reset to default value. + * | | |1 = The behavior selection in periodic mode is Enabled. + * | | |When user update CMPDAT while timer is running in periodic mode, the limitations as bellows list, + * | | |If updated CMPDAT value > CNT, CMPDAT will be updated and CNT keep running continually. + * | | |If updated CMPDAT value = CNT, timer time-out interrupt will be asserted. + * | | |If updated CMPDAT value < CNT, CNT will be reset to default value. + * |[21] |TGLPINSEL |Toggle-output Pin Select + * | | |0 = Toggle mode output to TMx (Timer Event Counter Pin). + * | | |1 = Toggle mode output to TMx_EXT (Timer External Capture Pin). + * |[22] |CAPSRC |Capture Pin Source Selection + * | | |0 = Capture Function source is from TMx_EXT (x= 0~3) pin. + * | | |1 = Capture Function source is from internal ACMP output signal, internal clock (MIRC, LIRC, HIRC), or external clock (HXT, LXT). + * | | |Note: When CAPSRC = 1, User can set INTERCAPSEL (TIMERx_EXTCTL[10:8]) to decide which internal ACMP output signal or which clock is as timer capture source. + * |[23] |WKEN |Wake-up Function Enable Bit + * | | |If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU. + * | | |0 = Wake-up function Disabled if timer interrupt signal generated. + * | | |1 = Wake-up function Enabled if timer interrupt signal generated. + * |[24] |EXTCNTEN |Event Counter Mode Enable Bit + * | | |This bit is for external counting pin function enabled. + * | | |0 = Event counter mode Disabled. + * | | |1 = Event counter mode Enabled. + * | | |Note: When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source. + * |[25] |ACTSTS |Timer Active Status Bit (Read Only) + * | | |This bit indicates the 24-bit up counter status. + * | | |0 = 24-bit up counter is not active. + * | | |1 = 24-bit up counter is active. + * | | |Note: This bit may active when CNT 0 transition to CNT 1. + * |[28:27] |OPMODE |Timer Counting Mode Select + * | | |00 = The timer controller is operated in One-shot mode. + * | | |01 = The timer controller is operated in Periodic mode. + * | | |10 = The timer controller is operated in Toggle-output mode. + * | | |11 = The timer controller is operated in Continuous Counting mode. + * |[29] |INTEN |Timer Interrupt Enable Bit + * | | |0 = Timer time-out interrupt Disabled. + * | | |1 = Timer time-out interrupt Enabled. + * | | |Note: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU. + * |[30] |CNTEN |Timer Counting Enable Bit + * | | |0 = Stops/Suspends counting. + * | | |1 = Starts counting. + * | | |Note1: In stop status, and then set CNTEN to 1 will enable the 24-bit up counter to keep counting from the last stop counting value. + * | | |Note2: This bit is auto-cleared by hardware in one-shot mode (TIMER_CTL[28:27] = 00) when the timer time-out interrupt flag TIF (TIMERx_INTSTS[0]) is generated. + * | | |Note3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not. + * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Bit (Write Protect) + * | | |0 = ICE debug mode acknowledgement effects TIMER counting. + * | | |TIMER counter will be held while CPU is held by ICE. + * | | |1 = ICE debug mode acknowledgement Disabled. + * | | |TIMER counter will keep going no matter CPU is held by ICE or not. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var TIMER_T::CMP + * Offset: 0x04 Timer Comparator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CMPDAT |Timer Comparator Value + * | | |CMPDAT is a 24-bit compared value register + * | | |When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1. + * | | |Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT). + * | | |Note1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state. + * | | |Note2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field + * | | |But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field. + * @var TIMER_T::INTSTS + * Offset: 0x08 Timer Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TIF |Timer Interrupt Flag + * | | |This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value. + * | | |0 = No effect. + * | | |1 = CNT value matches the CMPDAT value. + * | | |Note: This bit is cleared by writing 1 to it. + * |[1] |TWKF |Timer Wake-up Flag + * | | |This bit indicates the interrupt wake-up flag status of timer. + * | | |0 = Timer does not cause CPU wake-up. + * | | |1 = CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated. + * | | |Note: This bit is cleared by writing 1 to it. + * @var TIMER_T::CNT + * Offset: 0x0C Timer Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CNT |Timer Data Register + * | | |Read operation. + * | | |Read this register to get CNT value. For example: + * | | |If EXTCNTEN (TIMERx_CTL[24]) is 0, user can read CNT value for getting current 24-bit counter value. + * | | |If EXTCNTEN (TIMERx_CTL[24]) is 1, user can read CNT value for getting current 24-bit event input counter value. + * | | |Write operation. + * | | |Writing any value to this register will reset current CNT value to 0 and reload internal 8-bit prescale counter. + * |[31] |RSTACT |Timer Data Register Reset Active (Read Only) + * | | |This bit indicates if the counter reset operation active. + * | | |When user writes this CNT register, timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter + * | | |At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress + * | | |Once the counter reset operation done, timer clear this bit to 0 automatically. + * | | |0 = Reset operation is done. + * | | |1 = Reset operation triggered by writing TIMERx_CNT is in progress. + * @var TIMER_T::CAP + * Offset: 0x10 Timer Capture Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CAPDAT |Timer Capture Data Register + * | | |When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field. + * @var TIMER_T::EXTCTL + * Offset: 0x14 Timer External Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTPHASE |Timer External Count Phase + * | | |This bit indicates the detection phase of external counting pin TMx (x= 0~3). + * | | |0 = A falling edge of external counting pin will be counted. + * | | |1 = A rising edge of external counting pin will be counted. + * |[3] |CAPEN |Timer Capture Enable Bit + * | | |This bit enables the capture input function. + * | | |0 =Capture source Disabled. + * | | |1 =Capture source Enabled. + * | | |Note: When CAPEN is 1, user can set INTERCAPSEL (TIMERx_EXTCTL [10:8]) to select capture source. + * |[4] |CAPFUNCS |Capture Function Selection + * | | |0 = External Capture Mode Enabled. + * | | |1 = External Reset Mode Enabled. + * | | |Note1: When CAPFUNCS is 0, transition on TMx_EXT (x= 0~3) pin is using to save current 24-bit timer counter value (CNT value) to CAPDAT field. + * | | |Note2: When CAPFUNCS is 1, transition on TMx_EXT (x= 0~3) pin is using to save current 24-bit timer counter value (CNT value) to CAPDAT field then CNT value will be reset immediately. + * |[5] |CAPIEN |Timer External Capture Interrupt Enable Bit + * | | |0 = TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock detection Interrupt Disabled. + * | | |1 = TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock detection Interrupt Enabled. + * | | |Note: CAPIEN is used to enable timer external interrupt + * | | |If CAPIEN enabled, timer will rise an interrupt when CAPIF (TIMERx_EINTSTS[0]) is 1. + * | | |For example, while CAPIEN = 1, CAPEN = 1, and CAPEDGE = 00, a 1 to 0 transition on the Tx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock will cause the CAPIF to be set then the interrupt signal is generated and sent to NVIC to inform CPU. + * |[6] |CAPDBEN |Timer External Capture Pin De-bounce Enable Bit + * | | |0 = TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Disabled. + * | | |1 = TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Enabled. + * | | |Note: If this bit is enabled, the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit. + * |[7] |CNTDBEN |Timer Counter Pin De-bounce Enable Bit + * | | |0 = TMx (x= 0~3) pin de-bounce Disabled. + * | | |1 = TMx (x= 0~3) pin de-bounce Enabled. + * | | |Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit. + * |[10:8] |INTERCAPSEL|Internal Capture Source Select + * | | |000 = Capture Function source is from internal ACMP0 output signal. + * | | |001 = Capture Function source is from internal ACMP1 output signal. + * | | |010 = Capture Function source is from HXT. + * | | |011 = Capture Function source is from LXT. + * | | |100 = Capture Function source is from HIRC. + * | | |101 = Capture Function source is from LIRC. + * | | |110 = Capture Function source is from MIRC. + * | | |111 = Reserved. + * | | |Note: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1. + * |[14:12] |CAPEDGE |Timer External Capture Pin Edge Detect + * | | |When first capture event is generated, the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0. + * | | |000 = Capture event occurred when detect falling edge transfer on TMx_EXT (x= 0~3) pin. + * | | |001 = Capture event occurred when detect rising edge transfer on TMx_EXT (x= 0~3) pin. + * | | |010 = Capture event occurred when detect both falling and rising edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at falling edge transfer. + * | | |011 = Capture event occurred when detect both rising and falling edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at rising edge transfer. + * | | |110 = First capture event occurred at falling edge, follows capture events are at rising edge transfer on TMx_EXT (x= 0~3) pin. + * | | |111 = First capture event occurred at rising edge, follows capture events are at falling edge transfer on TMx_EXT (x= 0~3) pin. + * | | |100, 101 = Reserved. + * | | |Note: Set CAPSRC (TIMERx_CTL[22]) and INTERCAPSEL (TIMERx_EXTCTL[10:8]) to select capture source. + * |[16] |ECNTSSEL |Event Counter Source Selection to Trigger Event Counter Function + * | | |0 = Event Counter input source is from TMx (x= 0~3) pin. + * | | |1 = Event Counter input source is from USB internal SOF output signal. + * |[31:28] |CAPDIVSCL |Timer Capture Source Divider Scale + * | | |This bits indicate the divide scale for capture source divider + * | | |0000 = Capture source/1. + * | | |0001 = Capture source/2. + * | | |0010 = Capture source/4. + * | | |0011 = Capture source/8. + * | | |0100 = Capture source/16. + * | | |0101 = Capture source/32. + * | | |0110 = Capture source/64. + * | | |0111 = Capture source/128. + * | | |1000 = Capture source/256. + * | | |1001~1111 = Reserved. + * | | |Note: Sets INTERCAPSEL (TIMERx_EXTCTL[10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source. + * @var TIMER_T::EINTSTS + * Offset: 0x18 Timer External Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPIF |Timer External Capture Interrupt Flag + * | | |This bit indicates the timer external capture interrupt flag status. + * | | |0 = TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock interrupt did not occur. + * | | |1 = TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock interrupt occurred. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2: When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on Tx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, this bit will set to 1 by hardware. + * | | |Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status + * | | |If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value. + * @var TIMER_T::TRGCTL + * Offset: 0x1C Timer Trigger Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TRGSSEL |Trigger Source Select Bit + * | | |This bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal. + * | | |0 = Time-out interrupt signal is used to internal trigger PWM, PDMA, DAC, and EADC. + * | | |1 = Capture interrupt signal is used to internal trigger PWM, PDMA, DAC, and EADC. + * |[1] |TRGPWM |Trigger PWM/BPWM Enable Bit + * | | |If this bit is set to 1, each timer time-out event or capture event can be as PWM/BPWM counter clock source. + * | | |0 = Timer interrupt trigger PWM/BPWM Disabled. + * | | |1 = Timer interrupt trigger PWM/BPWM Enabled. + * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal as PWM/BPWM counter clock source. + * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal as PWM/BPWM counter clock source. + * |[2] |TRGEADC |Trigger EADC Enable Bit + * | | |If this bit is set to 1, each timer time-out event or capture event can be triggered EADC conversion. + * | | |0 = Timer interrupt trigger EADC Disabled. + * | | |1 = Timer interrupt trigger EADC Enabled. + * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger EADC conversion. + * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger ADC conversion. + * |[3] |TRGDAC |Trigger DAC Enable Bit + * | | |If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered DAC. + * | | |0 = Timer interrupt trigger DAC Disabled. + * | | |1 = Timer interrupt trigger DAC Enabled. + * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger DAC. + * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger DAC. + * |[4] |TRGPDMA |Trigger PDMA Enable Bit + * | | |If this bit is set to 1, each timer time-out event or capture event can be triggered PDMA transfer. + * | | |0 = Timer interrupt trigger PDMA Disabled. + * | | |1 = Timer interrupt trigger PDMA Enabled. + * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger PDMA transfer. + * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger PDMA transfer. + * @var TIMER_T::PWMCTL + * Offset: 0x40 Timer PWM Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTEN |PWM Counter Enable Bit + * | | |0 = PWM counter and clock prescale Stop Running. + * | | |1 = PWM counter and clock prescale Start Running. + * |[3] |CNTMODE |PWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[12] |PWMINTWKEN|PWM Interrupt Wake-up Enable + * | | |If PWM interrupt occurs when chip is at power down mode, PWMINTWKEN can determine whether chip wake-up occurs or not. + * | | |0 = PWM interrupt wake-up disable. + * | | |1 = PWM interrupt wake-up enable. + * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect) + * | | |If debug mode counter halt is enabled, PWM counter will keep current value until exit ICE debug mode. + * | | |0 = ICE debug mode counter halt disable. + * | | |1 = ICE debug mode counter halt enable. + * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. + * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable Bit (Write Protect) + * | | |0 = ICE debug mode acknowledgement effects PWM output. + * | | |PWM output pin will be forced as tri-state while ICE debug mode acknowledged. + * | | |1 = ICE debug mode acknowledgement disabled. + * | | |PWM output pin will keep output no matter ICE debug mode acknowledged or not. + * | | |Note: This bit is write protected. Refer toSYS_REGLCTL register. + * @var TIMER_T::PWMCLKPSC + * Offset: 0x44 Timer PWM Counter Clock Pre-scale Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |CLKPSC |PWM Counter Clock Pre-scale + * | | |The active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1) + * | | |If CLKPSC is 0, then there is no scaling in PWM counter clock source. + * @var TIMER_T::PWMCNTCLR + * Offset: 0x48 Timer PWM Clear Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTCLR |Clear PWM Counter Control Bit + * | | |It is automatically cleared by hardware. + * | | |0 = No effect. + * | | |1 = Clear 16-bit PWM counter to 0x00000 in up count type. + * | | |Note: Timer peripheral clock source should be set as PCLK to ensure that this bit can automatically cleared by hardware. + * @var TIMER_T::PWMPERIOD + * Offset: 0x4C Timer PWM Period Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PERIOD |PWM Period Register + * | | |In up count type: PWM counter counts from 0 to PERIOD, and restarts from 0. + * | | |In up count type: + * | | |PWM period time = (PERIOD + 1) * (CLKPSC + 1) * TMRx_PWMCLK. + * @var TIMER_T::PWMCMPDAT + * Offset: 0x50 Timer PWM Comparator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMP |PWM Comparator Register + * | | |PWM CMP is used to compare with PWM CNT to generate PWM output waveform, interrupt events and trigger EADC, PDMA, and DAC starting converting. + * @var TIMER_T::PWMCNT + * Offset: 0x54 Timer PWM Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CNT |PWM Counter Value Register (Read Only) + * | | |User can monitor CNT to know the current counter value in 16-bit period counter. + * @var TIMER_T::PWMPOLCTL + * Offset: 0x58 Timer PWM Pin Output Polar Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PINV |PWMx Output Pin Polar Control Bit + * | | |The bit is used to control polarity state of PWMx_OUT pin. + * | | |0 = PWMx_OUT pin polar inverse Disabled. + * | | |1 = PWMx_OUT polar inverse Enabled. + * | | |Note: Sets POSEL (TIMERx_PWMPOCTL[8]) to select Tx or Tx_EXT as PWMx output pin. + * @var TIMER_T::PWMPOCTL + * Offset: 0x5C Timer PWM Pin Output Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |POEN |PWMx Output Pin Enable Bit + * | | |0 = PWMx_OUT pin at tri-state mode. + * | | |1 = PWMx_OUT pin in output mode. + * | | |Note: Sets POSEL (TIMERx_PWMPOCTL[8]) to select Tx or Tx_EXT as PWMx output pin. + * |[8] |POSEL |PWM Output Pin Select + * | | |0 = PWMx_OUT pin is Tx. + * | | |1 = PWMx_OUT pin is Tx_EXT. + * @var TIMER_T::PWMINTEN0 + * Offset: 0x60 Timer PWM Interrupt Enable Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |PIEN |PWM Period Point Interrupt Enable Bit + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * |[2] |CMPUIEN |PWM Compare Up Count Interrupt Enable Bit + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * @var TIMER_T::PWMINTSTS0 + * Offset: 0x64 Timer PWM Interrupt Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |PIF |PWM Period Point Interrupt Flag + * | | |This bit is set by hardware when TIMERx_PWM counter reaches PERIOD. + * | | |Note: This bit is cleared by writing 1 to it. + * |[2] |CMPUIF |PWM Compare Up Count Interrupt Flag + * | | |This bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP. + * | | |Note1: If CMP equal to PERIOD, there is no CMPUIF flag in up count type. + * | | |Note2: This bit is cleared by writing 1 to it. + * @var TIMER_T::PWMTRGCTL + * Offset: 0x68 Timer PWM Trigger Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |TRGSEL |PWM Counter Event Source Select to Trigger Conversion + * | | |00 = Trigger conversion at period point (PIF). + * | | |01 = Trigger conversion at compare up count point (CMPUIF). + * | | |10 = Trigger conversion at period or compare up count point (PIF or CMPUIF). + * | | |11 = Reserved. + * |[7] |PWMTRGEADC|PWM Counter Event Trigger EADC Conversion Enable Bit + * | | |0 = PWM counter event trigger EADC conversion Disabled. + * | | |1 = PWM counter event trigger EADC conversion Enabled. + * | | |Note: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source. + * |[8] |PWMTRGDAC |PWM Counter Event Trigger DAC Conversion Enable Bit + * | | |If this bit is set to 1, PWM can trigger DAC conversion. + * | | |0 = PWM trigger DAC Disabled. + * | | |1 = PWM trigger DAC Enabled. + * | | |Note: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source. + * |[9] |PWMTRGPDMA|PWM Counter Event Trigger PDMA Conversion Enable Bit + * | | |If this bit is set to 1, PWM can trigger PDMA conversion. + * | | |0 = PWM trigger PDMA Disabled. + * | | |1 = PWM trigger PDMA Enabled. + * | | |Note: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source. + * @var TIMER_T::PWMSTATUS + * Offset: 0x6C Timer PWM Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTMAXF |PWM Counter Equal to 0xFFFF Flag + * | | |0 = The PWM counter value never reached its maximum value 0xFFFF. + * | | |1 = The PWM counter value has reached its maximum value. + * | | |Note: This bit is cleared by writing 1 to it. + * |[8] |PWMINTWKF |PWM Interrupt Wake-up Flag + * | | |0 = PWM interrupt wake-up is not occurred. + * | | |1 = PWM interrupt wake-up has occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * |[16] |EADCTRGF |Trigger EADC Start Conversion Flag + * | | |0 = PWM counter event trigger EADC start conversion is not occurred. + * | | |1 = PWM counter event trigger EADC start conversion has occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * |[17] |DACTRGF |Trigger DAC Start Conversion Flag + * | | |0 = PWM counter event trigger DAC start conversion is not occurred. + * | | |1 = PWM counter event trigger DAC start conversion has occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * |[18] |PDMATRGF |Trigger PDMA Start Conversion Flag + * | | |0 = PWM counter event trigger PDMA start conversion is not occurred. + * | | |1 = PWM counter event trigger PDMA start conversion has occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * @var TIMER_T::PWMPBUF + * Offset: 0x70 Timer PWM Period Buffer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PBUF |PWM Period Buffer Register (Read Only) + * | | |Used as PERIOD active register. + * @var TIMER_T::PWMCMPBUF + * Offset: 0x74 Timer PWM Comparator Buffer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMPBUF |PWM Comparator Buffer Register (Read Only) + * | | |Used as CMP active register. + */ + __IO uint32_t CTL; /*!< [0x0000] Timer Control Register */ + __IO uint32_t CMP; /*!< [0x0004] Timer Comparator Register */ + __IO uint32_t INTSTS; /*!< [0x0008] Timer Interrupt Status Register */ + __IO uint32_t CNT; /*!< [0x000c] Timer Data Register */ + __I uint32_t CAP; /*!< [0x0010] Timer Capture Data Register */ + __IO uint32_t EXTCTL; /*!< [0x0014] Timer External Control Register */ + __IO uint32_t EINTSTS; /*!< [0x0018] Timer External Interrupt Status Register */ + __IO uint32_t TRGCTL; /*!< [0x001c] Timer Trigger Control Register */ + __I uint32_t RESERVE0[8]; + __IO uint32_t PWMCTL; /*!< [0x0040] Timer PWM Control Register */ + __IO uint32_t PWMCLKPSC; /*!< [0x0044] Timer PWM Counter Clock Pre-scale Register */ + __IO uint32_t PWMCNTCLR; /*!< [0x0048] Timer PWM Clear Counter Register */ + __IO uint32_t PWMPERIOD; /*!< [0x004c] Timer PWM Period Register */ + __IO uint32_t PWMCMPDAT; /*!< [0x0050] Timer PWM Comparator Register */ + __I uint32_t PWMCNT; /*!< [0x0054] Timer PWM Counter Register */ + __IO uint32_t PWMPOLCTL; /*!< [0x0058] Timer PWM Pin Output Polar Control Register */ + __IO uint32_t PWMPOCTL; /*!< [0x005c] Timer PWM Pin Output Control Register */ + __IO uint32_t PWMINTEN0; /*!< [0x0060] Timer PWM Interrupt Enable Register 0 */ + __IO uint32_t PWMINTSTS0; /*!< [0x0064] Timer PWM Interrupt Status Register 0 */ + __IO uint32_t PWMTRGCTL; /*!< [0x0068] Timer PWM Trigger Control Register */ + __IO uint32_t PWMSTATUS; /*!< [0x006c] Timer PWM Status Register */ + __I uint32_t PWMPBUF; /*!< [0x0070] Timer PWM Period Buffer Register */ + __I uint32_t PWMCMPBUF; /*!< [0x0074] Timer PWM Comparator Buffer Register */ + +} TIMER_T; + +/** + @addtogroup TIMER_CONST TIMER Bit Field Definition + Constant Definitions for TIMER Controller +@{ */ + +#define TIMER_CTL_PSC_Pos (0) /*!< TIMER_T::CTL: PSC Position */ +#define TIMER_CTL_PSC_Msk (0xfful << TIMER_CTL_PSC_Pos) /*!< TIMER_T::CTL: PSC Mask */ + +#define TIMER_CTL_FUNCSEL_Pos (15) /*!< TIMER_T::CTL: FUNCSEL Position */ +#define TIMER_CTL_FUNCSEL_Msk (0x1ul << TIMER_CTL_FUNCSEL_Pos) /*!< TIMER_T::CTL: FUNCSEL Mask */ + +#define TIMER_CTL_INTRGEN_Pos (19) /*!< TIMER_T::CTL: INTRGEN Position */ +#define TIMER_CTL_INTRGEN_Msk (0x1ul << TIMER_CTL_INTRGEN_Pos) /*!< TIMER_T::CTL: INTRGEN Mask */ + +#define TIMER_CTL_PERIOSEL_Pos (20) /*!< TIMER_T::CTL: PERIOSEL Position */ +#define TIMER_CTL_PERIOSEL_Msk (0x1ul << TIMER_CTL_PERIOSEL_Pos) /*!< TIMER_T::CTL: PERIOSEL Mask */ + +#define TIMER_CTL_TGLPINSEL_Pos (21) /*!< TIMER_T::CTL: TGLPINSEL Position */ +#define TIMER_CTL_TGLPINSEL_Msk (0x1ul << TIMER_CTL_TGLPINSEL_Pos) /*!< TIMER_T::CTL: TGLPINSEL Mask */ + +#define TIMER_CTL_CAPSRC_Pos (22) /*!< TIMER_T::CTL: CAPSRC Position */ +#define TIMER_CTL_CAPSRC_Msk (0x1ul << TIMER_CTL_CAPSRC_Pos) /*!< TIMER_T::CTL: CAPSRC Mask */ + +#define TIMER_CTL_WKEN_Pos (23) /*!< TIMER_T::CTL: WKEN Position */ +#define TIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos) /*!< TIMER_T::CTL: WKEN Mask */ + +#define TIMER_CTL_EXTCNTEN_Pos (24) /*!< TIMER_T::CTL: EXTCNTEN Position */ +#define TIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos) /*!< TIMER_T::CTL: EXTCNTEN Mask */ + +#define TIMER_CTL_ACTSTS_Pos (25) /*!< TIMER_T::CTL: ACTSTS Position */ +#define TIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos) /*!< TIMER_T::CTL: ACTSTS Mask */ + +#define TIMER_CTL_OPMODE_Pos (27) /*!< TIMER_T::CTL: OPMODE Position */ +#define TIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos) /*!< TIMER_T::CTL: OPMODE Mask */ + +#define TIMER_CTL_INTEN_Pos (29) /*!< TIMER_T::CTL: INTEN Position */ +#define TIMER_CTL_INTEN_Msk (0x1ul << TIMER_CTL_INTEN_Pos) /*!< TIMER_T::CTL: INTEN Mask */ + +#define TIMER_CTL_CNTEN_Pos (30) /*!< TIMER_T::CTL: CNTEN Position */ +#define TIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos) /*!< TIMER_T::CTL: CNTEN Mask */ + +#define TIMER_CTL_ICEDEBUG_Pos (31) /*!< TIMER_T::CTL: ICEDEBUG Position */ +#define TIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos) /*!< TIMER_T::CTL: ICEDEBUG Mask */ + +#define TIMER_CMP_CMPDAT_Pos (0) /*!< TIMER_T::CMP: CMPDAT Position */ +#define TIMER_CMP_CMPDAT_Msk (0xfffffful << TIMER_CMP_CMPDAT_Pos) /*!< TIMER_T::CMP: CMPDAT Mask */ + +#define TIMER_INTSTS_TIF_Pos (0) /*!< TIMER_T::INTSTS: TIF Position */ +#define TIMER_INTSTS_TIF_Msk (0x1ul << TIMER_INTSTS_TIF_Pos) /*!< TIMER_T::INTSTS: TIF Mask */ + +#define TIMER_INTSTS_TWKF_Pos (1) /*!< TIMER_T::INTSTS: TWKF Position */ +#define TIMER_INTSTS_TWKF_Msk (0x1ul << TIMER_INTSTS_TWKF_Pos) /*!< TIMER_T::INTSTS: TWKF Mask */ + +#define TIMER_CNT_CNT_Pos (0) /*!< TIMER_T::CNT: CNT Position */ +#define TIMER_CNT_CNT_Msk (0xfffffful << TIMER_CNT_CNT_Pos) /*!< TIMER_T::CNT: CNT Mask */ + +#define TIMER_CNT_RSTACT_Pos (31) /*!< TIMER_T::CNT: RSTACT Position */ +#define TIMER_CNT_RSTACT_Msk (0x1ul << TIMER_CNT_RSTACT_Pos) /*!< TIMER_T::CNT: RSTACT Mask */ + +#define TIMER_CAP_CAPDAT_Pos (0) /*!< TIMER_T::CAP: CAPDAT Position */ +#define TIMER_CAP_CAPDAT_Msk (0xfffffful << TIMER_CAP_CAPDAT_Pos) /*!< TIMER_T::CAP: CAPDAT Mask */ + +#define TIMER_EXTCTL_CNTPHASE_Pos (0) /*!< TIMER_T::EXTCTL: CNTPHASE Position */ +#define TIMER_EXTCTL_CNTPHASE_Msk (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos) /*!< TIMER_T::EXTCTL: CNTPHASE Mask */ + +#define TIMER_EXTCTL_CAPEN_Pos (3) /*!< TIMER_T::EXTCTL: CAPEN Position */ +#define TIMER_EXTCTL_CAPEN_Msk (0x1ul << TIMER_EXTCTL_CAPEN_Pos) /*!< TIMER_T::EXTCTL: CAPEN Mask */ + +#define TIMER_EXTCTL_CAPFUNCS_Pos (4) /*!< TIMER_T::EXTCTL: CAPFUNCS Position */ +#define TIMER_EXTCTL_CAPFUNCS_Msk (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< TIMER_T::EXTCTL: CAPFUNCS Mask */ + +#define TIMER_EXTCTL_CAPIEN_Pos (5) /*!< TIMER_T::EXTCTL: CAPIEN Position */ +#define TIMER_EXTCTL_CAPIEN_Msk (0x1ul << TIMER_EXTCTL_CAPIEN_Pos) /*!< TIMER_T::EXTCTL: CAPIEN Mask */ + +#define TIMER_EXTCTL_CAPDBEN_Pos (6) /*!< TIMER_T::EXTCTL: CAPDBEN Position */ +#define TIMER_EXTCTL_CAPDBEN_Msk (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos) /*!< TIMER_T::EXTCTL: CAPDBEN Mask */ + +#define TIMER_EXTCTL_CNTDBEN_Pos (7) /*!< TIMER_T::EXTCTL: CNTDBEN Position */ +#define TIMER_EXTCTL_CNTDBEN_Msk (0x1ul << TIMER_EXTCTL_CNTDBEN_Pos) /*!< TIMER_T::EXTCTL: CNTDBEN Mask */ + +#define TIMER_EXTCTL_INTERCAPSEL_Pos (8) /*!< TIMER_T::EXTCTL: INTERCAPSEL Position */ +#define TIMER_EXTCTL_INTERCAPSEL_Msk (0x7ul << TIMER_EXTCTL_INTERCAPSEL_Pos) /*!< TIMER_T::EXTCTL: INTERCAPSEL Mask */ + +#define TIMER_EXTCTL_CAPEDGE_Pos (12) /*!< TIMER_T::EXTCTL: CAPEDGE Position */ +#define TIMER_EXTCTL_CAPEDGE_Msk (0x7ul << TIMER_EXTCTL_CAPEDGE_Pos) /*!< TIMER_T::EXTCTL: CAPEDGE Mask */ + +#define TIMER_EXTCTL_ECNTSSEL_Pos (16) /*!< TIMER_T::EXTCTL: ECNTSSEL Position */ +#define TIMER_EXTCTL_ECNTSSEL_Msk (0x1ul << TIMER_EXTCTL_ECNTSSEL_Pos) /*!< TIMER_T::EXTCTL: ECNTSSEL Mask */ + +#define TIMER_EXTCTL_CAPDIVSCL_Pos (28) /*!< TIMER_T::EXTCTL: CAPDIVSCL Position */ +#define TIMER_EXTCTL_CAPDIVSCL_Msk (0xful << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< TIMER_T::EXTCTL: CAPDIVSCL Mask */ + +#define TIMER_EINTSTS_CAPIF_Pos (0) /*!< TIMER_T::EINTSTS: CAPIF Position */ +#define TIMER_EINTSTS_CAPIF_Msk (0x1ul << TIMER_EINTSTS_CAPIF_Pos) /*!< TIMER_T::EINTSTS: CAPIF Mask */ + +#define TIMER_TRGCTL_TRGSSEL_Pos (0) /*!< TIMER_T::TRGCTL: TRGSSEL Position */ +#define TIMER_TRGCTL_TRGSSEL_Msk (0x1ul << TIMER_TRGCTL_TRGSSEL_Pos) /*!< TIMER_T::TRGCTL: TRGSSEL Mask */ + +#define TIMER_TRGCTL_TRGPWM_Pos (1) /*!< TIMER_T::TRGCTL: TRGPWM Position */ +#define TIMER_TRGCTL_TRGPWM_Msk (0x1ul << TIMER_TRGCTL_TRGPWM_Pos) /*!< TIMER_T::TRGCTL: TRGPWM Mask */ + +#define TIMER_TRGCTL_TRGEADC_Pos (2) /*!< TIMER_T::TRGCTL: TRGEADC Position */ +#define TIMER_TRGCTL_TRGEADC_Msk (0x1ul << TIMER_TRGCTL_TRGEADC_Pos) /*!< TIMER_T::TRGCTL: TRGEADC Mask */ + +#define TIMER_TRGCTL_TRGDAC_Pos (3) /*!< TIMER_T::TRGCTL: TRGDAC Position */ +#define TIMER_TRGCTL_TRGDAC_Msk (0x1ul << TIMER_TRGCTL_TRGDAC_Pos) /*!< TIMER_T::TRGCTL: TRGDAC Mask */ + +#define TIMER_TRGCTL_TRGPDMA_Pos (4) /*!< TIMER_T::TRGCTL: TRGPDMA Position */ +#define TIMER_TRGCTL_TRGPDMA_Msk (0x1ul << TIMER_TRGCTL_TRGPDMA_Pos) /*!< TIMER_T::TRGCTL: TRGPDMA Mask */ + +#define TIMER_PWMCTL_CNTEN_Pos (0) /*!< TIMER_T::PWMCTL: CNTEN Position */ +#define TIMER_PWMCTL_CNTEN_Msk (0x1ul << TIMER_PWMCTL_CNTEN_Pos) /*!< TIMER_T::PWMCTL: CNTEN Mask */ + +#define TIMER_PWMCTL_CNTMODE_Pos (3) /*!< TIMER_T::PWMCTL: CNTMODE Position */ +#define TIMER_PWMCTL_CNTMODE_Msk (0x1ul << TIMER_PWMCTL_CNTMODE_Pos) /*!< TIMER_T::PWMCTL: CNTMODE Mask */ + +#define TIMER_PWMCTL_PWMINTWKEN_Pos (12) /*!< TIMER_T::PWMCTL: PWMINTWKEN Position */ +#define TIMER_PWMCTL_PWMINTWKEN_Msk (0x1ul << TIMER_PWMCTL_PWMINTWKEN_Pos) /*!< TIMER_T::PWMCTL: PWMINTWKEN Mask */ + +#define TIMER_PWMCTL_DBGHALT_Pos (30) /*!< TIMER_T::PWMCTL: DBGHALT Position */ +#define TIMER_PWMCTL_DBGHALT_Msk (0x1ul << TIMER_PWMCTL_DBGHALT_Pos) /*!< TIMER_T::PWMCTL: DBGHALT Mask */ + +#define TIMER_PWMCTL_DBGTRIOFF_Pos (31) /*!< TIMER_T::PWMCTL: DBGTRIOFF Position */ +#define TIMER_PWMCTL_DBGTRIOFF_Msk (0x1ul << TIMER_PWMCTL_DBGTRIOFF_Pos) /*!< TIMER_T::PWMCTL: DBGTRIOFF Mask */ + +#define TIMER_PWMCLKPSC_CLKPSC_Pos (0) /*!< TIMER_T::PWMCLKPSC: CLKPSC Position */ +#define TIMER_PWMCLKPSC_CLKPSC_Msk (0xfful << TIMER_PWMCLKPSC_CLKPSC_Pos) /*!< TIMER_T::PWMCLKPSC: CLKPSC Mask */ + +#define TIMER_PWMCNTCLR_CNTCLR_Pos (0) /*!< TIMER_T::PWMCNTCLR: CNTCLR Position */ +#define TIMER_PWMCNTCLR_CNTCLR_Msk (0x1ul << TIMER_PWMCNTCLR_CNTCLR_Pos) /*!< TIMER_T::PWMCNTCLR: CNTCLR Mask */ + +#define TIMER_PWMPERIOD_PERIOD_Pos (0) /*!< TIMER_T::PWMPERIOD: PERIOD Position */ +#define TIMER_PWMPERIOD_PERIOD_Msk (0xfffful << TIMER_PWMPERIOD_PERIOD_Pos) /*!< TIMER_T::PWMPERIOD: PERIOD Mask */ + +#define TIMER_PWMCMPDAT_CMP_Pos (0) /*!< TIMER_T::PWMCMPDAT: CMP Position */ +#define TIMER_PWMCMPDAT_CMP_Msk (0xfffful << TIMER_PWMCMPDAT_CMP_Pos) /*!< TIMER_T::PWMCMPDAT: CMP Mask */ + +#define TIMER_PWMCNT_CNT_Pos (0) /*!< TIMER_T::PWMCNT: CNT Position */ +#define TIMER_PWMCNT_CNT_Msk (0xfffful << TIMER_PWMCNT_CNT_Pos) /*!< TIMER_T::PWMCNT: CNT Mask */ + +#define TIMER_PWMPOLCTL_PINV_Pos (0) /*!< TIMER_T::PWMPOLCTL: PINV Position */ +#define TIMER_PWMPOLCTL_PINV_Msk (0x1ul << TIMER_PWMPOLCTL_PINV_Pos) /*!< TIMER_T::PWMPOLCTL: PINV Mask */ + +#define TIMER_PWMPOCTL_POEN_Pos (0) /*!< TIMER_T::PWMPOCTL: POEN Position */ +#define TIMER_PWMPOCTL_POEN_Msk (0x1ul << TIMER_PWMPOCTL_POEN_Pos) /*!< TIMER_T::PWMPOCTL: POEN Mask */ + +#define TIMER_PWMPOCTL_POSEL_Pos (8) /*!< TIMER_T::PWMPOCTL: POSEL Position */ +#define TIMER_PWMPOCTL_POSEL_Msk (0x1ul << TIMER_PWMPOCTL_POSEL_Pos) /*!< TIMER_T::PWMPOCTL: POSEL Mask */ + +#define TIMER_PWMINTEN0_PIEN_Pos (1) /*!< TIMER_T::PWMINTEN0: PIEN Position */ +#define TIMER_PWMINTEN0_PIEN_Msk (0x1ul << TIMER_PWMINTEN0_PIEN_Pos) /*!< TIMER_T::PWMINTEN0: PIEN Mask */ + +#define TIMER_PWMINTEN0_CMPUIEN_Pos (2) /*!< TIMER_T::PWMINTEN0: CMPUIEN Position */ +#define TIMER_PWMINTEN0_CMPUIEN_Msk (0x1ul << TIMER_PWMINTEN0_CMPUIEN_Pos) /*!< TIMER_T::PWMINTEN0: CMPUIEN Mask */ + +#define TIMER_PWMINTSTS0_PIF_Pos (1) /*!< TIMER_T::PWMINTSTS0: PIF Position */ +#define TIMER_PWMINTSTS0_PIF_Msk (0x1ul << TIMER_PWMINTSTS0_PIF_Pos) /*!< TIMER_T::PWMINTSTS0: PIF Mask */ + +#define TIMER_PWMINTSTS0_CMPUIF_Pos (2) /*!< TIMER_T::PWMINTSTS0: CMPUIF Position */ +#define TIMER_PWMINTSTS0_CMPUIF_Msk (0x1ul << TIMER_PWMINTSTS0_CMPUIF_Pos) /*!< TIMER_T::PWMINTSTS0: CMPUIF Mask */ + +#define TIMER_PWMTRGCTL_TRGSEL_Pos (0) /*!< TIMER_T::PWMTRGCTL: TRGSEL Position */ +#define TIMER_PWMTRGCTL_TRGSEL_Msk (0x3ul << TIMER_PWMTRGCTL_TRGSEL_Pos) /*!< TIMER_T::PWMTRGCTL: TRGSEL Mask */ + +#define TIMER_PWMTRGCTL_PWMTRGEADC_Pos (7) /*!< TIMER_T::PWMTRGCTL: PWMTRGEADC Position*/ +#define TIMER_PWMTRGCTL_PWMTRGEADC_Msk (0x1ul << TIMER_PWMTRGCTL_PWMTRGEADC_Pos) /*!< TIMER_T::PWMTRGCTL: PWMTRGEADC Mask */ + +#define TIMER_PWMTRGCTL_PWMTRGDAC_Pos (8) /*!< TIMER_T::PWMTRGCTL: PWMTRGDAC Position */ +#define TIMER_PWMTRGCTL_PWMTRGDAC_Msk (0x1ul << TIMER_PWMTRGCTL_PWMTRGDAC_Pos) /*!< TIMER_T::PWMTRGCTL: PWMTRGDAC Mask */ + +#define TIMER_PWMTRGCTL_PWMTRGPDMA_Pos (9) /*!< TIMER_T::PWMTRGCTL: PWMTRGPDMA Position*/ +#define TIMER_PWMTRGCTL_PWMTRGPDMA_Msk (0x1ul << TIMER_PWMTRGCTL_PWMTRGPDMA_Pos) /*!< TIMER_T::PWMTRGCTL: PWMTRGPDMA Mask */ + +#define TIMER_PWMSTATUS_CNTMAXF_Pos (0) /*!< TIMER_T::PWMSTATUS: CNTMAXF Position */ +#define TIMER_PWMSTATUS_CNTMAXF_Msk (0x1ul << TIMER_PWMSTATUS_CNTMAXF_Pos) /*!< TIMER_T::PWMSTATUS: CNTMAXF Mask */ + +#define TIMER_PWMSTATUS_PWMINTWKF_Pos (8) /*!< TIMER_T::PWMSTATUS: PWMINTWKF Position */ +#define TIMER_PWMSTATUS_PWMINTWKF_Msk (0x1ul << TIMER_PWMSTATUS_PWMINTWKF_Pos) /*!< TIMER_T::PWMSTATUS: PWMINTWKF Mask */ + +#define TIMER_PWMSTATUS_EADCTRGF_Pos (16) /*!< TIMER_T::PWMSTATUS: EADCTRGF Position */ +#define TIMER_PWMSTATUS_EADCTRGF_Msk (0x1ul << TIMER_PWMSTATUS_EADCTRGF_Pos) /*!< TIMER_T::PWMSTATUS: EADCTRGF Mask */ + +#define TIMER_PWMSTATUS_DACTRGF_Pos (17) /*!< TIMER_T::PWMSTATUS: DACTRGF Position */ +#define TIMER_PWMSTATUS_DACTRGF_Msk (0x1ul << TIMER_PWMSTATUS_DACTRGF_Pos) /*!< TIMER_T::PWMSTATUS: DACTRGF Mask */ + +#define TIMER_PWMSTATUS_PDMATRGF_Pos (18) /*!< TIMER_T::PWMSTATUS: PDMATRGF Position */ +#define TIMER_PWMSTATUS_PDMATRGF_Msk (0x1ul << TIMER_PWMSTATUS_PDMATRGF_Pos) /*!< TIMER_T::PWMSTATUS: PDMATRGF Mask */ + +#define TIMER_PWMPBUF_PBUF_Pos (0) /*!< TIMER_T::PWMPBUF: PBUF Position */ +#define TIMER_PWMPBUF_PBUF_Msk (0xfffful << TIMER_PWMPBUF_PBUF_Pos) /*!< TIMER_T::PWMPBUF: PBUF Mask */ + +#define TIMER_PWMCMPBUF_CMPBUF_Pos (0) /*!< TIMER_T::PWMCMPBUF: CMPBUF Position */ +#define TIMER_PWMCMPBUF_CMPBUF_Msk (0xfffful << TIMER_PWMCMPBUF_CMPBUF_Pos) /*!< TIMER_T::PWMCMPBUF: CMPBUF Mask */ + +/**@}*/ /* TIMER_CONST */ +/**@}*/ /* end of TIMER register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __TIMER_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/uart_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/uart_reg.h new file mode 100644 index 00000000000..4666a126f54 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/uart_reg.h @@ -0,0 +1,1292 @@ +/**************************************************************************//** + * @file uart_reg.h + * @version V1.00 + * @brief UART register definition header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __UART_REG_H__ +#define __UART_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup UART Universal Asynchronous Receiver/Transmitter Controller (UART) + Memory Mapped Structure for UART Controller +@{ */ + +typedef struct +{ + + + /** + * @var UART_T::DAT + * Offset: 0x00 UART Receive/Transmit Buffer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DAT |Data Receive/Transmit Buffer + * | | |Write Operation: + * | | |By writing one byte to this register, the data byte will be stored in transmitter FIFO. + * | | |The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD. + * | | |Read Operation: + * | | |By reading this register, the UART controller will return an 8-bit data received from receiver FIFO. + * |[8] |PARITY |Parity Bit Receive/Transmit Buffer + * | | |Write Operation: + * | | |By writing to this bit, the PARITY bit will be stored in transmitter FIFO. + * | | |If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD. + * | | |Read Operation: + * | | |If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the PARITY bit can be read by this bit. + * | | |Note: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set. + * @var UART_T::INTEN + * Offset: 0x04 UART Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDAIEN |Receive Data Available Interrupt Enable Bit + * | | |0 = Receive data available interrupt Disabled. + * | | |1 = Receive data available interrupt Enabled. + * |[1] |THREIEN |Transmit Holding Register Empty Interrupt Enable Bit + * | | |0 = Transmit holding register empty interrupt Disabled. + * | | |1 = Transmit holding register empty interrupt Enabled. + * |[2] |RLSIEN |Receive Line Status Interrupt Enable Bit + * | | |0 = Receive Line Status interrupt Disabled. + * | | |1 = Receive Line Status interrupt Enabled. + * |[3] |MODEMIEN |Modem Status Interrupt Enable Bit + * | | |0 = Modem status interrupt Disabled. + * | | |1 = Modem status interrupt Enabled. + * |[4] |RXTOIEN |RX Time-out Interrupt Enable Bit + * | | |0 = RX time-out interrupt Disabled. + * | | |1 = RX time-out interrupt Enabled. + * |[5] |BUFERRIEN |Buffer Error Interrupt Enable Bit + * | | |0 = Buffer error interrupt Disabled. + * | | |1 = Buffer error interrupt Enabled. + * |[6] |WKIEN |Wake-up Interrupt Enable Bit + * | | |0 = Wake-up Interrupt Disabled. + * | | |1 = Wake-up Interrupt Enabled. + * |[8] |LINIEN |LIN Bus Interrupt Enable Bit + * | | |0 = LIN bus interrupt Disabled. + * | | |1 = LIN bus interrupt Enabled. + * | | |Note: This bit is used for LIN function mode. + * |[11] |TOCNTEN |Receive Buffer Time-out Counter Enable Bit + * | | |0 = Receive Buffer Time-out counter Disabled. + * | | |1 = Receive Buffer Time-out counter Enabled. + * |[12] |ATORTSEN |nRTS Auto-flow Control Enable Bit + * | | |0 = nRTS auto-flow control Disabled. + * | | |1 = nRTS auto-flow control Enabled. + * | | |Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal. + * |[13] |ATOCTSEN |nCTS Auto-flow Control Enable Bit + * | | |0 = nCTS auto-flow control Disabled. + * | | |1 = nCTS auto-flow control Enabled. + * | | |Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted). + * |[14] |TXPDMAEN |TX PDMA Enable Bit + * | | |0 = TX PDMA Disabled. + * | | |1 = TX PDMA Enabled. + * | | |Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. + * | | |If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA transmit request operation is stopped. + * | | |Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing "1" to corresponding BIF, FEF and PEF to make UART PDMA transmit request operation continue. + * |[15] |RXPDMAEN |RX PDMA Enable Bit + * | | |This bit can enable or disable RX PDMA service. + * | | |0 = RX PDMA Disabled. + * | | |1 = RX PDMA Enabled. + * | | |Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused + * | | |If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA receive request operation is stopped. + * | | |Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing "1" to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue. + * |[16] |SWBEIEN |Single-wire Bit Error Detection Interrupt Enable Bit + * | | |Set this bit, the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set. + * | | |0 = Single-wire Bit Error Detect Inerrupt Disabled. + * | | |1 = Single-wire Bit Error Detect Inerrupt Enabled. + * | | |Note: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode. + * |[18] |ABRIEN |Auto-baud Rate Interrupt Enable Bit + * | | |0 = Auto-baud rate interrupt Disabled. + * | | |1 = Auto-baud rate interrupt Enabled. + * |[22] |TXENDIEN |Transmitter Empty Interrupt Enable Bit + * | | |If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) + * | | |is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted). + * | | |0 = Transmitter empty interrupt Disabled. + * | | |1 = Transmitter empty interrupt Enabled. + * @var UART_T::FIFO + * Offset: 0x08 UART FIFO Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |RXRST |RX Field Software Reset + * | | |When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared. + * | | |0 = No effect. + * | | |1 = Reset the RX internal state machine and pointers. + * | | |Note1: This bit will automatically clear at least 3 UART peripheral clock cycles. + * | | |Note2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set. + * |[2] |TXRST |TX Field Software Reset + * | | |When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared. + * | | |0 = No effect. + * | | |1 = Reset the TX internal state machine and pointers. + * | | |Note1: This bit will automatically clear at least 3 UART peripheral clock cycles. + * | | |Note2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set. + * |[7:4] |RFITL |RX FIFO Interrupt Trigger Level + * | | |When the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated). + * | | |0000 = RX FIFO Interrupt Trigger Level is 1 byte. + * | | |0001 = RX FIFO Interrupt Trigger Level is 4 bytes. + * | | |0010 = RX FIFO Interrupt Trigger Level is 8 bytes. + * | | |0011 = RX FIFO Interrupt Trigger Level is 14 bytes. + * | | |Others = Reserved. + * |[8] |RXOFF |Receiver Disable Bit + * | | |The receiver is disabled or not (set 1 to disable receiver). + * | | |0 = Receiver Enabled. + * | | |1 = Receiver Disabled. + * | | |Note: This bit is used for RS-485 Normal Multi-drop mode. + * | | |It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed. + * |[19:16] |RTSTRGLV |nRTS Trigger Level for Auto-flow Control + * | | |0000 = nRTS Trigger Level is 1 byte. + * | | |0001 = nRTS Trigger Level is 4 bytes. + * | | |0010 = nRTS Trigger Level is 8 bytes. + * | | |0011 = nRTS Trigger Level is 14 bytes. + * | | |Others = Reserved. + * | | |Note: This field is used for auto nRTS flow control. + * @var UART_T::LINE + * Offset: 0x0C UART Line Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |WLS |Word Length Selection + * | | |This field sets UART word length. + * | | |00 = 5 bits. + * | | |01 = 6 bits. + * | | |10 = 7 bits. + * | | |11 = 8 bits. + * |[2] |NSB |Number of "STOP Bit" + * | | |0 = One "STOP bit" is generated in the transmitted data. + * | | |1 = When select 5-bit word length, 1.5 "STOP bit" is generated in the transmitted data. + * | | |When select 6-, 7- and 8-bit word length, 2 "STOP bit" is generated in the transmitted data. + * |[3] |PBE |Parity Bit Enable Bit + * | | |0 = PARITY bit generated Disabled. + * | | |1 = PARITY bit generated Enabled. + * | | |Note: PARITY bit is generated on each outgoing character and is checked on each incoming data. + * |[4] |EPE |Even Parity Enable Bit + * | | |0 = Odd number of logic 1's is transmitted and checked in each word. + * | | |1 = Even number of logic 1's is transmitted and checked in each word. + * | | |Note: This bit has effect only when PBE (UART_LINE[3]) is set. + * |[5] |SPE |Stick Parity Enable Bit + * | | |0 = Stick parity Disabled. + * | | |1 = Stick parity Enabled. + * | | |Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the PARITY bit is transmitted and checked as logic 0. + * | | |If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the PARITY bit is transmitted and checked as 1. + * |[6] |BCB |Break Control Bit + * | | |0 = Break Control Disabled. + * | | |1 = Break Control Enabled. + * | | |Note: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0) + * | | |This bit acts only on TX line and has no effect on the transmitter logic. + * |[7] |PSS |PARITY Bit Source Selection + * | | |The PARITY bit can be selected to be generated and checked automatically or by software. + * | | |0 = PARITY bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically. + * | | |1 = PARITY bit generated and checked by software. + * | | |Note1: This bit has effect only when PBE (UART_LINE[3]) is set. + * | | |Note2: If PSS is 0, the PARITY bit is transmitted and checked automatically. + * | | |If PSS is 1, the transmitted PARITY bit value can be determined by writing PARITY (UART_DAT[8]) and the PARITY bit can be read by reading PARITY (UART_DAT[8]). + * |[8] |TXDINV |TX Data Inverted + * | | |0 = Transmitted data signal inverted Disabled. + * | | |1 = Transmitted data signal inverted Enabled. + * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function. + * |[9] |RXDINV |RX Data Inverted + * | | |0 = Received data signal inverted Disabled. + * | | |1 = Received data signal inverted Enabled. + * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function. + * @var UART_T::MODEM + * Offset: 0x10 UART Modem Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |RTS |nRTS (Request-to-send) Signal Control + * | | |This bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration. + * | | |0 = nRTS signal is active. + * | | |1 = nRTS signal is inactive. + * | | |Note1: The nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode. + * | | |Note2: The nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. + * | | |Note3: Single-wire mode is support this feature. + * |[9] |RTSACTLV |nRTS Pin Active Level + * | | |This bit defines the active level state of nRTS pin output. + * | | |0 = nRTS pin output is high level active. + * | | |1 = nRTS pin output is low level active. (Default) + * | | |Note1: Refer to Figure 7.13-13 and Figure 7.13-14 for UART function mode. + * | | |Note2: Refer to Figure 7.13-24 and Figure 7.13-25 for RS-485 function mode. + * | | |Note3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * |[13] |RTSSTS |nRTS Pin Status (Read Only) + * | | |This bit mirror from nRTS pin output of voltage logic status. + * | | |0 = nRTS pin output is low level voltage logic state. + * | | |1 = nRTS pin output is high level voltage logic state. + * @var UART_T::MODEMSTS + * Offset: 0x14 UART Modem Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CTSDETF |Detect nCTS State Change Flag + * | | |This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1. + * | | |0 = nCTS input has not change state. + * | | |1 = nCTS input has change state. + * | | |Note: This bit can be cleared by writing '1' to it. + * |[4] |CTSSTS |nCTS Pin Status (Read Only) + * | | |This bit mirror from nCTS pin input of voltage logic status. + * | | |0 = nCTS pin input is low level voltage logic state. + * | | |1 = nCTS pin input is high level voltage logic state. + * | | |Note: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected. + * |[8] |CTSACTLV |nCTS Pin Active Level + * | | |This bit defines the active level state of nCTS pin input. + * | | |0 = nCTS pin input is high level active. + * | | |1 = nCTS pin input is low level active. (Default) + * | | |Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * @var UART_T::FIFOSTS + * Offset: 0x18 UART FIFO Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXOVIF |RX Overflow Error Interrupt Flag + * | | |This bit is set when RX FIFO overflow. + * | | |If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set. + * | | |0 = RX FIFO is not overflow. + * | | |1 = RX FIFO is overflow. + * | | |Note: This bit can be cleared by writing "1" to it. + * |[1] |ABRDIF |Auto-baud Rate Detect Interrupt Flag + * | | |This bit is set to logic "1" when auto-baud rate detect function is finished. + * | | |0 = Auto-baud rate detect function is not finished. + * | | |1 = Auto-baud rate detect function is finished. + * | | |Note: This bit can be cleared by writing "1" to it. + * |[2] |ABRDTOIF |Auto-baud Rate Detect Time-out Interrupt Flag + * | | |This bit is set to logic "1" in Auto-baud Rate Detect mode when the baud rate counter is overflow. + * | | |0 = Auto-baud rate counter is underflow. + * | | |1 = Auto-baud rate counter is overflow. + * | | |Note: This bit can be cleared by writing "1" to it. + * |[3] |ADDRDETF |RS-485 Address Byte Detect Flag + * | | |0 = Receiver detects a data that is not an address bit (bit 9 = '0'). + * | | |1 = Receiver detects a data that is an address bit (bit 9 = '1'). + * | | |Note1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to "1" to enable Address detection mode. + * | | |Note2: This bit can be cleared by writing "1" to it. + * |[4] |PEF |Parity Error Flag + * | | |This bit is set to logic "1" whenever the received character does not have a valid "PARITY bit". + * | | |0 = No parity error is generated. + * | | |1 = Parity error is generated. + * | | |Note: This bit can be cleared by writing "1" to it. + * |[5] |FEF |Framing Error Flag + * | | |This bit is set to logic "1" whenever the received character does not have a valid "STOP bit" (that is, the STOP bit following the last data bit or PARITY bit is detected as logic 0). + * | | |0 = No framing error is generated. + * | | |1 = Framing error is generated. + * | | |Note: This bit can be cleared by writing "1" to it. + * |[6] |BIF |Break Interrupt Flag + * | | |This bit is set to logic "1" whenever the received data input (RX) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "START bit" + data bits + parity + STOP bits). + * | | |0 = No Break interrupt is generated. + * | | |1 = Break interrupt is generated. + * | | |Note: This bit can be cleared by writing "1" to it. + * |[13:8] |RXPTR |RX FIFO Pointer (Read Only) + * | | |This field indicates the RX FIFO Buffer Pointer. + * | | |When UART receives one byte from external device, RXPTR increases one. + * | | |When one byte of RX FIFO is read by CPU, RXPTR decreases one. + * | | |The Maximum value shown in RXPTR is 15 + * | | |When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. + * | | |As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15. + * |[14] |RXEMPTY |Receiver FIFO Empty (Read Only) + * | | |This bit initiate RX FIFO empty or not. + * | | |0 = RX FIFO is not empty. + * | | |1 = RX FIFO is empty. + * | | |Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. + * | | |It will be cleared when UART receives any new data. + * |[15] |RXFULL |Receiver FIFO Full (Read Only) + * | | |This bit initiates RX FIFO full or not. + * | | |0 = RX FIFO is not full. + * | | |1 = RX FIFO is full. + * | | |Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. + * |[21:16] |TXPTR |TX FIFO Pointer (Read Only) + * | | |This field indicates the TX FIFO Buffer Pointer. + * | | |When CPU writes one byte into UART_DAT, TXPTR increases one. + * | | |When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one. + * | | |The Maximum value shown in TXPTR is 15. + * | | |When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. + * | | |As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15. + * |[22] |TXEMPTY |Transmitter FIFO Empty (Read Only) + * | | |This bit indicates TX FIFO empty or not. + * | | |0 = TX FIFO is not empty. + * | | |1 = TX FIFO is empty. + * | | |Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high + * | | |It will be cleared when writing data into UART_DAT (TX FIFO not empty). + * |[23] |TXFULL |Transmitter FIFO Full (Read Only) + * | | |This bit indicates TX FIFO full or not. + * | | |0 = TX FIFO is not full. + * | | |1 = TX FIFO is full. + * | | |Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. + * |[24] |TXOVIF |TX Overflow Error Interrupt Flag + * | | |If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1. + * | | |0 = TX FIFO is not overflow. + * | | |1 = TX FIFO is overflow. + * | | |Note: This bit can be cleared by writing "1" to it. + * |[28] |TXEMPTYF |Transmitter Empty Flag (Read Only) + * | | |This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted. + * | | |0 = TX FIFO is not empty or the STOP bit of the last byte has been not transmitted. + * | | |1 = TX FIFO is empty and the STOP bit of the last byte has been transmitted. + * | | |Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. + * |[29] |RXIDLE |RX Idle Status (Read Only) + * | | |This bit is set by hardware when RX is idle. + * | | |0 = RX is busy. + * | | |1 = RX is idle. (Default) + * |[31] |TXRXACT |TX and RX Active Status (Read Only) + * | | |This bit indicates TX and RX are active or inactive. + * | | |0 = TX and RX are inactive. + * | | |1 = TX and RX are active. (Default) + * | | |Note: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. + * | | |The UART controller can not transmit or receive data at this moment. + * | | |Otherwise this bit is set. + * @var UART_T::INTSTS + * Offset: 0x1C UART Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDAIF |Receive Data Available Interrupt Flag + * | | |When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. + * | | |If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated. + * | | |0 = No RDA interrupt flag is generated. + * | | |1 = RDA interrupt flag is generated. + * | | |Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]). + * |[1] |THREIF |Transmit Holding Register Empty Interrupt Flag + * | | |This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. + * | | |If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated. + * | | |0 = No THRE interrupt flag is generated. + * | | |1 = THRE interrupt flag is generated. + * | | |Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty). + * |[2] |RLSIF |Receive Line Interrupt Flag (Read Only) + * | | |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). + * | | |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated. + * | | |0 = No RLS interrupt flag is generated. + * | | |1 = RLS interrupt flag is generated. + * | | |Note1: In RS-485 function mode, this field is set include "receiver detect and received address byte character (bit9 = "1") bit". + * | | |At the same time, the bit of ADDRDETF (UART_FIFOSTS[3]) is also set. + * | | |Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. + * | | |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. + * |[3] |MODEMIF |MODEM Interrupt Flag (Read Only) + * | | |This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS[0]) = 1). + * | | |If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated. + * | | |0 = No Modem interrupt flag is generated. + * | | |1 = Modem interrupt flag is generated. + * | | |Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]). + * |[4] |RXTOIF |RX Time-out Interrupt Flag (Read Only) + * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). + * | | |If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated. + * | | |0 = No RX time-out interrupt flag is generated. + * | | |1 = RX time-out interrupt flag is generated. + * | | |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it. + * |[5] |BUFERRIF |Buffer Error Interrupt Flag (Read Only) + * | | |This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). + * | | |When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. + * | | |If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated. + * | | |0 = No buffer error interrupt flag is generated. + * | | |1 = Buffer error interrupt flag is generated. + * | | |Note: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]). + * |[6] |WKIF |UART Wake-up Interrupt Flag (Read Only) + * | | |This bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1. + * | | |0 = No UART wake-up interrupt flag is generated. + * | | |1 = UART wake-up interrupt flag is generated. + * | | |Note: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag. + * |[7] |LINIF |LIN Bus Interrupt Flag + * | | |This bit is set when LIN slave header detect (SLVHDETF (UART_LINSTS[0] =1)), LIN break detect (BRKDETF(UART_LINSTS[8]=1)), bit error detect (BITEF(UART_LINSTS[9]=1)), + * | | |LIN slave ID parity error (SLVIDPEF(UART_LINSTS[2] = 1)) or LIN slave header error detect (SLVHEF (UART_LINSTS[1])). + * | | |If LINIEN (UART_INTEN [8]) is enabled the LIN interrupt will be generated. + * | | |0 = None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated. + * | | |1 = At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated. + * | | |Note: This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]) + * | | |and SLVHEF(UART_LINSTS[1]) all are cleared and software writing "1" to LINIF(UART_INTSTS[7]). + * |[8] |RDAINT |Receive Data Available Interrupt Indicator (Read Only) + * | | |This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1. + * | | |0 = No RDA interrupt is generated. + * | | |1 = RDA interrupt is generated. + * |[9] |THREINT |Transmit Holding Register Empty Interrupt Indicator (Read Only) + * | | |This bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1. + * | | |0 = No THRE interrupt is generated. + * | | |1 = THRE interrupt is generated. + * |[10] |RLSINT |Receive Line Status Interrupt Indicator (Read Only) + * | | |This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1. + * | | |0 = No RLS interrupt is generated. + * | | |1 = RLS interrupt is generated. + * |[11] |MODEMINT |MODEM Status Interrupt Indicator (Read Only) + * | | |This bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1. + * | | |0 = No Modem interrupt is generated. + * | | |1 = Modem interrupt is generated. + * |[12] |RXTOINT |RX Time-out Interrupt Indicator (Read Only) + * | | |This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1. + * | | |0 = No RX time-out interrupt is generated. + * | | |1 = RX time-out interrupt is generated. + * |[13] |BUFERRINT |Buffer Error Interrupt Indicator (Read Only) + * | | |This bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1. + * | | |0 = No buffer error interrupt is generated. + * | | |1 = Buffer error interrupt is generated. + * |[14] |WKINT |UART Wake-up Interrupt Indicator (Read Only) + * | | |This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1. + * | | |0 = No UART wake-up interrupt is generated. + * | | |1 = UART wake-up interrupt is generated. + * |[15] |LININT |LIN Bus Interrupt Indicator (Read Only) + * | | |This bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1. + * | | |0 = No LIN Bus interrupt is generated. + * | | |1 = The LIN Bus interrupt is generated. + * |[16] |SBEIF |Single-wire Bit Error Detection Interrupt Flag + * | | |This bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode. + * | | |0 = No single-wire bit error detection interrupt flag is generated. + * | | |1 = Single-wire bit error detection interrupt flag is generated. + * | | |Note1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode. + * | | |Note2: This bit can be cleared by writing "1" to it. + * |[18] |HWRLSIF |PDMA Mode Receive Line Status Flag (Read Only) + * | | |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). + * | | |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated. + * | | |0 = No RLS interrupt flag is generated in PDMA mode. + * | | |1 = RLS interrupt flag is generated in PDMA mode. + * | | |Note1: In RS-485 function mode, this field include "receiver detect any address byte received address byte character (bit9 = "1") bit". + * | | |Note2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. + * | | |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. + * |[19] |HWMODIF |PDMA Mode MODEM Interrupt Flag (Read Only) + * | | |This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS [0] =1)). + * | | |If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated. + * | | |0 = No Modem interrupt flag is generated in PDMA mode. + * | | |1 = Modem interrupt flag is generated in PDMA mode. + * | | |Note: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]). + * |[20] |HWTOIF |PDMA Mode RX Time-out Interrupt Flag (Read Only) + * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). + * | | |If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated . + * | | |0 = No RX time-out interrupt flag is generated in PDMA mode. + * | | |1 = RX time-out interrupt flag is generated in PDMA mode. + * | | |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it. + * |[21] |HWBUFEIF |PDMA Mode Buffer Error Interrupt Flag (Read Only) + * | | |This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). + * | | |When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. + * | | |If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated. + * | | |0 = No buffer error interrupt flag is generated in PDMA mode. + * | | |1 = Buffer error interrupt flag is generated in PDMA mode. + * | | |Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared. + * |[22] |TXENDIF |Transmitter Empty Interrupt Flag + * | | |This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set) + * | | |If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated. + * | | |0 = No transmitter empty interrupt flag is generated. + * | | |1 = Transmitter empty interrupt flag is generated. + * | | |Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. + * |[24] |SWBEINT |Single-wire Bit Error Detect Interrupt Indicator (Read Only) + * | | |This bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1. + * | | |0 = No Single-wire Bit Error Detection Interrupt generated. + * | | |1 = Single-wire Bit Error Detection Interrupt generated. + * |[26] |HWRLSINT |PDMA Mode Receive Line Status Interrupt Indicator (Read Only) + * | | |This bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1. + * | | |0 = No RLS interrupt is generated in PDMA mode. + * | | |1 = RLS interrupt is generated in PDMA mode. + * |[27] |HWMODINT |PDMA Mode MODEM Status Interrupt Indicator (Read Only) + * | | |This bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1. + * | | |0 = No Modem interrupt is generated in PDMA mode. + * | | |1 = Modem interrupt is generated in PDMA mode. + * |[28] |HWTOINT |PDMA Mode RX Time-out Interrupt Indicator (Read Only) + * | | |This bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1. + * | | |0 = No RX time-out interrupt is generated in PDMA mode. + * | | |1 = RX time-out interrupt is generated in PDMA mode. + * |[29] |HWBUFEINT |PDMA Mode Buffer Error Interrupt Indicator (Read Only) + * | | |This bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1. + * | | |0 = No buffer error interrupt is generated in PDMA mode. + * | | |1 = Buffer error interrupt is generated in PDMA mode. + * |[30] |TXENDINT |Transmitter Empty Interrupt Indicator (Read Only) + * | | |This bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1. + * | | |0 = No Transmitter Empty interrupt is generated. + * | | |1 = Transmitter Empty interrupt is generated. + * |[31] |ABRINT |Auto-baud Rate Interrupt Indicator (Read Only) + * | | |This bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1. + * | | |0 = No Auto-baud Rate interrupt is generated. + * | | |1 = The Auto-baud Rate interrupt is generated. + * @var UART_T::TOUT + * Offset: 0x20 UART Time-out Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |TOIC |Time-out Interrupt Comparator + * | | |The time-out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word if time out counter is enabled by setting TOCNTEN (UART_INTEN[11]). + * | | |Once the content of time-out counter is equal to that of time-out interrupt comparator (TOIC (UART_TOUT[7:0])), a receiver time-out interrupt (RXTOINT(UART_INTSTS[12])) is generated if RXTOIEN (UART_INTEN [4]) enabled. + * | | |A new incoming data word or RX FIFO empty will clear RXTOIF (UART_INTSTS[4]). + * | | |In order to avoid receiver time-out interrupt generation immediately during one character is being received, TOIC value should be set between 40 and 255. + * | | |So, for example, if TOIC is set with 40, the time-out interrupt is generated after four characters are not received when 1 stop bit and no parity check is set for UART transfer. + * |[15:8] |DLY |TX Delay Time Value + * | | |This field is used to programming the transfer delay time between the last STOP bit and next START bit. + * | | |The unit is bit time. + * @var UART_T::BAUD + * Offset: 0x24 UART Baud Rate Divider Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |BRD |Baud Rate Divider + * | | |The field indicates the baud rate divider. + * | | |This filed is used in baud rate calculation. + * | | |The detail description is shown in Table 7.13-4. + * |[27:24] |EDIVM1 |Extra Divider for BAUD Rate Mode 1 + * | | |This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. + * | | |The detail description is shown in Table 7.13-4. + * |[28] |BAUDM0 |BAUD Rate Mode Selection Bit 0 + * | | |This bit is baud rate mode selection bit 0. + * | | |UART provides three baud rate calculation modes. + * | | |This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. + * | | |The detail description is shown in Table 7.13-4. + * |[29] |BAUDM1 |BAUD Rate Mode Selection Bit 1 + * | | |This bit is baud rate mode selection bit 1. + * | | |UART provides three baud rate calculation modes. + * | | |This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. + * | | |The detail description is shown in Table 7.13-4. + * | | |Note: In IrDA mode must be operated in mode 0. + * @var UART_T::IRDA + * Offset: 0x28 UART IrDA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TXEN |IrDA Receiver/Transmitter Selection Enable Bit + * | | |0 = IrDA Transmitter Disabled and Receiver Enabled. (Default) + * | | |1 = IrDA Transmitter Enabled and Receiver Disabled. + * |[5] |TXINV |IrDA Inverse Transmitting Output Signal + * | | |0 = None inverse transmitting signal. (Default). + * | | |1 = Inverse transmitting output signal. + * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function. + * |[6] |RXINV |IrDA Inverse Receive Input Signal + * | | |0 = None inverse receiving input signal. + * | | |1 = Inverse receiving input signal. (Default) + * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function. + * @var UART_T::ALTCTL + * Offset: 0x2C UART Alternate Control/Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |BRKFL |UART LIN Break Field Length + * | | |This field indicates a 4-bit LIN TX break field count. + * | | |Note1: This break field length is BRKFL + 1. + * | | |Note2: According to LIN spec, the reset value is 0xC (break field length = 13). + * |[6] |LINRXEN |LIN RX Enable Bit + * | | |0 = LIN RX mode Disabled. + * | | |1 = LIN RX mode Enabled. + * |[7] |LINTXEN |LIN TX Break Mode Enable Bit + * | | |0 = LIN TX Break mode Disabled. + * | | |1 = LIN TX Break mode Enabled. + * | | |Note: When TX break field transfer operation finished, this bit will be cleared automatically. + * |[8] |RS485NMM |RS-485 Normal Multi-drop Operation Mode (NMM) + * | | |0 = RS-485 Normal Multi-drop Operation mode (NMM) Disabled. + * | | |1 = RS-485 Normal Multi-drop Operation mode (NMM) Enabled. + * | | |Note: It cannot be active with RS-485_AAD operation mode. + * |[9] |RS485AAD |RS-485 Auto Address Detection Operation Mode (AAD) + * | | |0 = RS-485 Auto Address Detection Operation mode (AAD) Disabled. + * | | |1 = RS-485 Auto Address Detection Operation mode (AAD) Enabled. + * | | |Note: It cannot be active with RS-485_NMM operation mode. + * |[10] |RS485AUD |RS-485 Auto Direction Function (AUD) + * | | |0 = RS-485 Auto Direction Operation function (AUD) Disabled. + * | | |1 = RS-485 Auto Direction Operation function (AUD) Enabled. + * | | |Note: It can be active with RS-485_AAD or RS-485_NMM operation mode. + * |[15] |ADDRDEN |RS-485 Address Detection Enable Bit + * | | |This bit is used to enable RS-485 Address Detection mode. + * | | |0 = Address detection mode Disabled. + * | | |1 = Address detection mode Enabled. + * | | |Note: This bit is used for RS-485 any operation mode. + * |[17] |ABRIF |Auto-baud Rate Interrupt Flag (Read Only) + * | | |This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. + * | | |0 = No auto-baud rate interrupt flag is generated. + * | | |1 = Auto-baud rate interrupt flag is generated. + * | | |Note: This bit is read only, but it can be cleared by writing "1" to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]). + * |[18] |ABRDEN |Auto-baud Rate Detect Enable Bit + * | | |0 = Auto-baud rate detect function Disabled. + * | | |1 = Auto-baud rate detect function Enabled. + * | | |Note : This bit is cleared automatically after auto-baud detection is finished. + * |[20:19] |ABRDBITS |Auto-baud Rate Detect Bit Length + * | | |00 = 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01. + * | | |01 = 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02. + * | | |10 = 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08. + * | | |11 = 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80. + * | | |Note : The calculation of bit number includes the START bit. + * |[31:24] |ADDRMV |Address Match Value + * | | |This field contains the RS-485 address match values. + * | | |Note: This field is used for RS-485 auto address detection mode. + * @var UART_T::FUNCSEL + * Offset: 0x30 UART Function Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |FUNCSEL |Function Select + * | | |000 = UART function. + * | | |001 = LIN function. + * | | |010 = IrDA function. + * | | |011 = RS-485 function. + * | | |100 = UART Single-wire function. + * | | |Others = Reserved. + * |[3] |TXRXDIS |TX and RX Disable Bit + * | | |Setting this bit can disable TX and RX. + * | | |0 = TX and RX Enabled. + * | | |1 = TX and RX Disabled. + * | | |Note: The TX and RX will not disable immediately when this bit is set. + * | | |The TX and RX compelet current task before disable TX and RX. + * | | |When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared. + * @var UART_T::LINCTL + * Offset: 0x34 UART LIN Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SLVEN |LIN Slave Mode Enable Bit + * | | |0 = LIN slave mode Disabled. + * | | |1 = LIN slave mode Enabled. + * |[1] |SLVHDEN |LIN Slave Header Detection Enable Bit + * | | |0 = LIN slave header detection Disabled. + * | | |1 = LIN slave header detection Enabled. + * | | |Note1: This bit is only valid in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1). + * | | |Note2: In LIN function mode, when detect header field (break + sync + frame ID), SLVHDETF (UART_LINSTS [0]) flag will be asserted. + * | | |If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated. + * |[2] |SLVAREN |LIN Slave Automatic Resynchronization Mode Enable Bit + * | | |0 = LIN automatic resynchronization Disabled. + * | | |1 = LIN automatic resynchronization Enabled. + * | | |Note1: This bit only is valid in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1). + * | | |Note2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1). + * | | |Note3: The control and interactions of this field are explained in 7.13.5.10 (Slave mode with automatic resynchronization). + * |[3] |SLVDUEN |LIN Slave Divider Update Method Enable Bit + * | | |0 = UART_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time). + * | | |1 = UART_BAUD is updated at the next received character.User must set the bit before checksum reception. + * | | |Note1: This bit only is valid in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1). + * | | |Note2: This bit used for LIN Slave Automatic Resynchronization mode. + * | | |(for Non-Automatic Resynchronization mode, this bit should be kept cleared) + * | | |Note3: The control and interactions of this field are explained in 7.13.5.10 (Slave mode with automatic resynchronization). + * |[4] |MUTE |LIN Mute Mode Enable Bit + * | | |0 = LIN mute mode Disabled. + * | | |1 = LIN mute mode Enabled. + * | | |Note: The exit from mute mode condition and each control and interactions of this field are explained in 7.13.5.10 (LIN slave mode). + * |[8] |SENDH |LIN TX Send Header Enable Bit + * | | |The LIN TX header can be "break field" or "break and sync field" or "break, sync and frame ID field", it is depend on setting HSEL (UART_LINCTL[23:22]). + * | | |0 = Send LIN TX header Disabled. + * | | |1 = Send LIN TX header Enabled. + * | | |Note1: This bit is shadow bit of LINTXEN (UART_ALTCTL [7]); user can read/write it by setting LINTXEN (UART_ALTCTL [7]) or SENDH (UART_LINCTL [8]). + * | | |Note2: When transmitter header field (it may be "break" or "break + sync" or "break + sync + frame ID" selected by HSEL (UART_LINCTL[23:22]) field) transfer operation finished, this bit will be cleared automatically. + * |[9] |IDPEN |LIN ID Parity Enable Bit + * | | |0 = LIN frame ID parity Disabled. + * | | |1 = LIN frame ID parity Enabled. + * | | |Note1: This bit can be used for LIN master to sending header field (SENDH (UART_LINCTL[8])) = 1 and HSEL (UART_LINCTL[23:22]) = 10 or be used for enable LIN slave received frame ID parity checked. + * | | |Note2: This bit is only used when the operation header transmitter is in HSEL (UART_LINCTL[23:22]) = 10. + * |[10] |BRKDETEN |LIN Break Detection Enable Bit + * | | |When detect consecutive dominant greater than 11 bits, and are followed by a delimiter character, the BRKDETF (UART_LINSTS[8]) flag is set at the end of break field. + * | | |If the LINIEN (UART_INTEN [8])=1, an interrupt will be generated. + * | | |0 = LIN break detection Disabled . + * | | |1 = LIN break detection Enabled. + * |[11] |LINRXOFF |LIN Receiver Disable Bit + * | | |If the receiver is enabled (LINRXOFF (UART_LINCTL[11]) = 0), all received byte data will be accepted and stored in the RX FIFO, and if the receiver is disabled (LINRXOFF (UART_LINCTL[11] = 1), all received byte data will be ignore. + * | | |0 = LIN receiver Enabled. + * | | |1 = LIN receiver Disabled. + * | | |Note: This bit is only valid when operating in LIN function mode (FUNCSEL (UART_FUNCSEL[1:0]) = 01). + * |[12] |BITERREN |Bit Error Detect Enable Bit + * | | |0 = Bit error detection function Disabled. + * | | |1 = Bit error detection function Enabled. + * | | |Note: In LIN function mode, when occur bit error, the BITEF (UART_LINSTS[9]) flag will be asserted. + * | | |If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated. + * |[19:16] |BRKFL |LIN Break Field Length + * | | |This field indicates a 4-bit LIN TX break field count. + * | | |Note1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]), User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]). + * | | |Note2: This break field length is BRKFL + 1. + * | | |Note3: According to LIN spec, the reset value is 12 (break field length = 13). + * |[21:20] |BSL |LIN Break/Sync Delimiter Length + * | | |00 = The LIN break/sync delimiter length is 1-bit time. + * | | |01 = The LIN break/sync delimiter length is 2-bit time. + * | | |10 = The LIN break/sync delimiter length is 3-bit time. + * | | |11 = The LIN break/sync delimiter length is 4-bit time. + * | | |Note: This bit used for LIN master to sending header field. + * |[23:22] |HSEL |LIN Header Select + * | | |00 = The LIN header includes "break field". + * | | |01 = The LIN header includes "break field" and "sync field". + * | | |10 = The LIN header includes "break field", "sync field" and "frame ID field". + * | | |11 = Reserved. + * | | |Note: This bit is used to master mode for LIN to send header field (SENDH (UART_LINCTL [8]) = 1) or used to slave to indicates exit from mute mode condition (MUTE (UART_LINCTL[4] = 1). + * |[31:24] |PID |LIN PID Bits + * | | |This field contains the LIN frame ID value in LIN function mode, and the frame ID parity can be generated by software or hardware depends on IDPEN (UART_LINCTL[9]) = 1. + * | | |If the parity generated by hardware, user fill ID0~ID5 (PID [29:24]), hardware will calculate P0 (PID[30]) and P1 (PID[31]), otherwise user must filled frame ID and parity in this field. + * | | |Note1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first). + * | | |Note2: This field can be used for LIN master mode or slave mode. + * @var UART_T::LINSTS + * Offset: 0x38 UART LIN Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SLVHDETF |LIN Slave Header Detection Flag + * | | |This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it. + * | | |0 = LIN header not detected. + * | | |1 = LIN header detected (break + sync + frame ID). + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: This bit is only valid in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enable LIN slave header detection function (SLVHDEN (UART_LINCTL [1])). + * | | |Note3: When enable ID parity check IDPEN (UART_LINCTL [9]), if hardware detect complete header ("break + sync + frame ID"), the SLVHDETF will be set whether the frame ID correct or not. + * |[1] |SLVHEF |LIN Slave Header Error Flag + * | | |This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. + * | | |The header errors include "break delimiter is too short (less than 0.5 bit time)", "frame error in sync field or Identifier field", "sync field data is not 0x55 in Non-Automatic Resynchronization mode", + * | | |"sync field deviation error with Automatic Resynchronization mode", "sync field measure time-out with Automatic Resynchronization mode" and "LIN header reception time-out". + * | | |0 = LIN header error not detected. + * | | |1 = LIN header error detected. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: This bit is only valid when UART is operated in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enables LIN slave header detection function (SLVHDEN (UART_LINCTL [1])). + * |[2] |SLVIDPEF |LIN Slave ID Parity Error Flag + * | | |This bit is set by hardware when receipted frame ID parity is not correct. + * | | |0 = No active. + * | | |1 = Receipted frame ID parity is not correct. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: This bit is only valid in LIN slave mode (SLVEN (UART_LINCTL [0])= 1) and enable LIN frame ID parity check function IDPEN (UART_LINCTL [9]). + * |[3] |SLVSYNCF |LIN Slave Sync Field + * | | |This bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. + * | | |When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit. + * | | |0 = The current character is not at LIN sync state. + * | | |1 = The current character is at LIN sync state. + * | | |Note1: This bit is only valid in LIN Slave mode (SLVEN(UART_LINCTL[0]) = 1). + * | | |Note2: This bit can be cleared by writing 1 to it. + * | | |Note3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header. + * |[8] |BRKDETF |LIN Break Detection Flag + * | | |This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software. + * | | |0 = LIN break not detected. + * | | |1 = LIN break detected. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: This bit is only valid when LIN break detection function is enabled (BRKDETEN (UART_LINCTL[10]) =1). + * |[9] |BITEF |Bit Error Detect Status Flag + * | | |At TX transfer state, hardware will monitor the bus state, if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state, BITEF (UART_LINSTS[9]) will be set. + * | | |When occur bit error, if the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated. + * | | |0 = Bit error not detected. + * | | |1 = Bit error detected. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: This bit is only valid when enable bit error detection function (BITERREN (UART_LINCTL [12]) = 1). + * @var UART_T::BRCOMP + * Offset: 0x3C UART Baud Rate Compensation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |BRCOMP |Baud Rate Compensation Patten + * | | |These 9-bits are used to define the relative bit is compensated or not. + * | | |BRCOMP[7:0] is used to define the compensation of UART_DAT[7:0] and BRCOM[8] is used to define the PARITY bit. + * |[31] |BRCOMPDEC |Baud Rate Compensation Decrease + * | | |0 = Positive (increase one module clock) compensation for each compensated bit. + * | | |1 = Negative (decrease one module clock) compensation for each compensated bit. + * @var UART_T::WKCTL + * Offset: 0x40 UART Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKCTSEN |nCTS Wake-up Enable Bit + * | | |0 = nCTS Wake-up system function Disabled. + * | | |1 = nCTS Wake-up system function Enabled. + * | | |Note:When the system is in Power-down mode, an external.nCTS change will wake up system from Power-down mode. + * |[1] |WKDATEN |Incoming Data Wake-up Enable Bit + * | | |0 = Incoming data wake-up system function Disabled. + * | | |1 = Incoming data wake-up system function Enabled. + * | | |Note:When the system is in Power-down mode, incoming data will wake-up system from Power-down mode. + * |[2] |WKRFRTEN |Received Data FIFO Reached Threshold Wake-up Enable Bit + * | | |0 = Received Data FIFO reached threshold wake-up system function Disabled. + * | | |1 = Received Data FIFO reached threshold wake-up system function Enabled. + * | | |Note: When the system is in Power-down mode, Received Data FIFO reached threshold will wake-up system from Power-down mode. + * |[3] |WKRS485EN |RS-485 Address Match (AAD Mode) Wake-up Enable Bit + * | | |0 = RS-485 Address Match (AAD mode) wake-up system function Disabled. + * | | |1 = RS-485 Address Match (AAD mode) wake-up system function Enabled. + * | | |Note1: When the system is in.Power-down mode, RS-485 Address Match will wake-up system from Power-down mode. + * | | |Note2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1. + * |[4] |WKTOUTEN |Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit + * | | |0 = Received Data FIFO reached threshold time-out wake-up system function Disabled. + * | | |1 = Received Data FIFO reached threshold time-out wake-up system function Enabled. + * | | |Note1: When the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake up system from Power-down mode. + * | | |Note2: It is suggested the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1. + * @var UART_T::WKSTS + * Offset: 0x44 UART Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CTSWKF |nCTS Wake-up Flag + * | | |This bit is set if chip wake-up from power-down state by nCTS wake-up. + * | | |0 = Chip stays in power-down state. + * | | |1 = Chip wake-up from power-down state by nCTS wake-up. + * | | |Note1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to "1". + * | | |Note2: This bit can be cleared by writing "1" to it. + * |[1] |DATWKF |Incoming Data Wake-up Flag + * | | |This bit is set if chip wake-up from power-down state by data wake-up. + * | | |0 = Chip stays in power-down state. + * | | |1 = Chip wake-up from power-down state by Incoming Data wake-up. + * | | |Note1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to "1". + * | | |Note2: This bit can be cleared by writing "1" to it. + * |[2] |RFRTWKF |Received Data FIFO Reached Threshold Wake-up Flag + * | | |This bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up. + * | | |0 = Chip stays in power-down state. + * | | |1 = Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up. + * | | |Note1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to "1". + * | | |Note2: This bit can be cleared by writing "1" to it. + * |[3] |RS485WKF |RS-485 Address Match (AAD Mode) Wake-up Flag + * | | |This bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode). + * | | |0 = Chip stays in power-down state. + * | | |1 = Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up. + * | | |Note1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to "1". + * | | |Note2: This bit can be cleared by writing "1" to it. + * |[4] |TOUTWKF |Received Data FIFO Threshold Time-out Wake-up Flag + * | | |This bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up. + * | | |0 = Chip stays in power-down state. + * | | |1 = Chip wake-up from power-down state by Received Data FIFO reached threshold time-out. + * | | |Note1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to "1". + * | | |Note2: This bit can be cleared by writing "1" to it. + * @var UART_T::DWKCOMP + * Offset: 0x48 UART Incoming Data Wake-up Compensation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |STCOMP |Start Bit Compensation Value + * | | |These bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is wake-up from Power-down mode. + * | | |Note: It is valid only when WKDATEN (UART_WKCTL[1]) is set. + */ + __IO uint32_t DAT; /*!< [0x0000] UART Receive/Transmit Buffer Register */ + __IO uint32_t INTEN; /*!< [0x0004] UART Interrupt Enable Register */ + __IO uint32_t FIFO; /*!< [0x0008] UART FIFO Control Register */ + __IO uint32_t LINE; /*!< [0x000c] UART Line Control Register */ + __IO uint32_t MODEM; /*!< [0x0010] UART Modem Control Register */ + __IO uint32_t MODEMSTS; /*!< [0x0014] UART Modem Status Register */ + __IO uint32_t FIFOSTS; /*!< [0x0018] UART FIFO Status Register */ + __IO uint32_t INTSTS; /*!< [0x001c] UART Interrupt Status Register */ + __IO uint32_t TOUT; /*!< [0x0020] UART Time-out Register */ + __IO uint32_t BAUD; /*!< [0x0024] UART Baud Rate Divider Register */ + __IO uint32_t IRDA; /*!< [0x0028] UART IrDA Control Register */ + __IO uint32_t ALTCTL; /*!< [0x002c] UART Alternate Control/Status Register */ + __IO uint32_t FUNCSEL; /*!< [0x0030] UART Function Select Register */ + __IO uint32_t LINCTL; /*!< [0x0034] UART LIN Control Register */ + __IO uint32_t LINSTS; /*!< [0x0038] UART LIN Status Register */ + __IO uint32_t BRCOMP; /*!< [0x003c] UART Baud Rate Compensation Register */ + __IO uint32_t WKCTL; /*!< [0x0040] UART Wake-up Control Register */ + __IO uint32_t WKSTS; /*!< [0x0044] UART Wake-up Status Register */ + __IO uint32_t DWKCOMP; /*!< [0x0048] UART Incoming Data Wake-up Compensation Register */ + +} UART_T; + +/** + @addtogroup UART_CONST UART Bit Field Definition + Constant Definitions for UART Controller +@{ */ + +#define UART_DAT_DAT_Pos (0) /*!< UART_T::DAT: DAT Position */ +#define UART_DAT_DAT_Msk (0xfful << UART_DAT_DAT_Pos) /*!< UART_T::DAT: DAT Mask */ + +#define UART_DAT_PARITY_Pos (8) /*!< UART_T::DAT: PARITY Position */ +#define UART_DAT_PARITY_Msk (0x1ul << UART_DAT_PARITY_Pos) /*!< UART_T::DAT: PARITY Mask */ + +#define UART_INTEN_RDAIEN_Pos (0) /*!< UART_T::INTEN: RDAIEN Position */ +#define UART_INTEN_RDAIEN_Msk (0x1ul << UART_INTEN_RDAIEN_Pos) /*!< UART_T::INTEN: RDAIEN Mask */ + +#define UART_INTEN_THREIEN_Pos (1) /*!< UART_T::INTEN: THREIEN Position */ +#define UART_INTEN_THREIEN_Msk (0x1ul << UART_INTEN_THREIEN_Pos) /*!< UART_T::INTEN: THREIEN Mask */ + +#define UART_INTEN_RLSIEN_Pos (2) /*!< UART_T::INTEN: RLSIEN Position */ +#define UART_INTEN_RLSIEN_Msk (0x1ul << UART_INTEN_RLSIEN_Pos) /*!< UART_T::INTEN: RLSIEN Mask */ + +#define UART_INTEN_MODEMIEN_Pos (3) /*!< UART_T::INTEN: MODEMIEN Position */ +#define UART_INTEN_MODEMIEN_Msk (0x1ul << UART_INTEN_MODEMIEN_Pos) /*!< UART_T::INTEN: MODEMIEN Mask */ + +#define UART_INTEN_RXTOIEN_Pos (4) /*!< UART_T::INTEN: RXTOIEN Position */ +#define UART_INTEN_RXTOIEN_Msk (0x1ul << UART_INTEN_RXTOIEN_Pos) /*!< UART_T::INTEN: RXTOIEN Mask */ + +#define UART_INTEN_BUFERRIEN_Pos (5) /*!< UART_T::INTEN: BUFERRIEN Position */ +#define UART_INTEN_BUFERRIEN_Msk (0x1ul << UART_INTEN_BUFERRIEN_Pos) /*!< UART_T::INTEN: BUFERRIEN Mask */ + +#define UART_INTEN_WKIEN_Pos (6) /*!< UART_T::INTEN: WKIEN Position */ +#define UART_INTEN_WKIEN_Msk (0x1ul << UART_INTEN_WKIEN_Pos) /*!< UART_T::INTEN: WKIEN Mask */ + +#define UART_INTEN_LINIEN_Pos (8) /*!< UART_T::INTEN: LINIEN Position */ +#define UART_INTEN_LINIEN_Msk (0x1ul << UART_INTEN_LINIEN_Pos) /*!< UART_T::INTEN: LINIEN Mask */ + +#define UART_INTEN_TOCNTEN_Pos (11) /*!< UART_T::INTEN: TOCNTEN Position */ +#define UART_INTEN_TOCNTEN_Msk (0x1ul << UART_INTEN_TOCNTEN_Pos) /*!< UART_T::INTEN: TOCNTEN Mask */ + +#define UART_INTEN_ATORTSEN_Pos (12) /*!< UART_T::INTEN: ATORTSEN Position */ +#define UART_INTEN_ATORTSEN_Msk (0x1ul << UART_INTEN_ATORTSEN_Pos) /*!< UART_T::INTEN: ATORTSEN Mask */ + +#define UART_INTEN_ATOCTSEN_Pos (13) /*!< UART_T::INTEN: ATOCTSEN Position */ +#define UART_INTEN_ATOCTSEN_Msk (0x1ul << UART_INTEN_ATOCTSEN_Pos) /*!< UART_T::INTEN: ATOCTSEN Mask */ + +#define UART_INTEN_TXPDMAEN_Pos (14) /*!< UART_T::INTEN: TXPDMAEN Position */ +#define UART_INTEN_TXPDMAEN_Msk (0x1ul << UART_INTEN_TXPDMAEN_Pos) /*!< UART_T::INTEN: TXPDMAEN Mask */ + +#define UART_INTEN_RXPDMAEN_Pos (15) /*!< UART_T::INTEN: RXPDMAEN Position */ +#define UART_INTEN_RXPDMAEN_Msk (0x1ul << UART_INTEN_RXPDMAEN_Pos) /*!< UART_T::INTEN: RXPDMAEN Mask */ + +#define UART_INTEN_SWBEIEN_Pos (16) /*!< UART_T::INTEN: SWBEIEN Position */ +#define UART_INTEN_SWBEIEN_Msk (0x1ul << UART_INTEN_SWBEIEN_Pos) /*!< UART_T::INTEN: SWBEIEN Mask */ + +#define UART_INTEN_ABRIEN_Pos (18) /*!< UART_T::INTEN: ABRIEN Position */ +#define UART_INTEN_ABRIEN_Msk (0x1ul << UART_INTEN_ABRIEN_Pos) /*!< UART_T::INTEN: ABRIEN Mask */ + +#define UART_INTEN_TXENDIEN_Pos (22) /*!< UART_T::INTEN: TXENDIEN Position */ +#define UART_INTEN_TXENDIEN_Msk (0x1ul << UART_INTEN_TXENDIEN_Pos) /*!< UART_T::INTEN: TXENDIEN Mask */ + +#define UART_FIFO_RXRST_Pos (1) /*!< UART_T::FIFO: RXRST Position */ +#define UART_FIFO_RXRST_Msk (0x1ul << UART_FIFO_RXRST_Pos) /*!< UART_T::FIFO: RXRST Mask */ + +#define UART_FIFO_TXRST_Pos (2) /*!< UART_T::FIFO: TXRST Position */ +#define UART_FIFO_TXRST_Msk (0x1ul << UART_FIFO_TXRST_Pos) /*!< UART_T::FIFO: TXRST Mask */ + +#define UART_FIFO_RFITL_Pos (4) /*!< UART_T::FIFO: RFITL Position */ +#define UART_FIFO_RFITL_Msk (0xful << UART_FIFO_RFITL_Pos) /*!< UART_T::FIFO: RFITL Mask */ + +#define UART_FIFO_RXOFF_Pos (8) /*!< UART_T::FIFO: RXOFF Position */ +#define UART_FIFO_RXOFF_Msk (0x1ul << UART_FIFO_RXOFF_Pos) /*!< UART_T::FIFO: RXOFF Mask */ + +#define UART_FIFO_RTSTRGLV_Pos (16) /*!< UART_T::FIFO: RTSTRGLV Position */ +#define UART_FIFO_RTSTRGLV_Msk (0xful << UART_FIFO_RTSTRGLV_Pos) /*!< UART_T::FIFO: RTSTRGLV Mask */ + +#define UART_LINE_WLS_Pos (0) /*!< UART_T::LINE: WLS Position */ +#define UART_LINE_WLS_Msk (0x3ul << UART_LINE_WLS_Pos) /*!< UART_T::LINE: WLS Mask */ + +#define UART_LINE_NSB_Pos (2) /*!< UART_T::LINE: NSB Position */ +#define UART_LINE_NSB_Msk (0x1ul << UART_LINE_NSB_Pos) /*!< UART_T::LINE: NSB Mask */ + +#define UART_LINE_PBE_Pos (3) /*!< UART_T::LINE: PBE Position */ +#define UART_LINE_PBE_Msk (0x1ul << UART_LINE_PBE_Pos) /*!< UART_T::LINE: PBE Mask */ + +#define UART_LINE_EPE_Pos (4) /*!< UART_T::LINE: EPE Position */ +#define UART_LINE_EPE_Msk (0x1ul << UART_LINE_EPE_Pos) /*!< UART_T::LINE: EPE Mask */ + +#define UART_LINE_SPE_Pos (5) /*!< UART_T::LINE: SPE Position */ +#define UART_LINE_SPE_Msk (0x1ul << UART_LINE_SPE_Pos) /*!< UART_T::LINE: SPE Mask */ + +#define UART_LINE_BCB_Pos (6) /*!< UART_T::LINE: BCB Position */ +#define UART_LINE_BCB_Msk (0x1ul << UART_LINE_BCB_Pos) /*!< UART_T::LINE: BCB Mask */ + +#define UART_LINE_PSS_Pos (7) /*!< UART_T::LINE: PSS Position */ +#define UART_LINE_PSS_Msk (0x1ul << UART_LINE_PSS_Pos) /*!< UART_T::LINE: PSS Mask */ + +#define UART_LINE_TXDINV_Pos (8) /*!< UART_T::LINE: TXDINV Position */ +#define UART_LINE_TXDINV_Msk (0x1ul << UART_LINE_TXDINV_Pos) /*!< UART_T::LINE: TXDINV Mask */ + +#define UART_LINE_RXDINV_Pos (9) /*!< UART_T::LINE: RXDINV Position */ +#define UART_LINE_RXDINV_Msk (0x1ul << UART_LINE_RXDINV_Pos) /*!< UART_T::LINE: RXDINV Mask */ + +#define UART_MODEM_RTS_Pos (1) /*!< UART_T::MODEM: RTS Position */ +#define UART_MODEM_RTS_Msk (0x1ul << UART_MODEM_RTS_Pos) /*!< UART_T::MODEM: RTS Mask */ + +#define UART_MODEM_RTSACTLV_Pos (9) /*!< UART_T::MODEM: RTSACTLV Position */ +#define UART_MODEM_RTSACTLV_Msk (0x1ul << UART_MODEM_RTSACTLV_Pos) /*!< UART_T::MODEM: RTSACTLV Mask */ + +#define UART_MODEM_RTSSTS_Pos (13) /*!< UART_T::MODEM: RTSSTS Position */ +#define UART_MODEM_RTSSTS_Msk (0x1ul << UART_MODEM_RTSSTS_Pos) /*!< UART_T::MODEM: RTSSTS Mask */ + +#define UART_MODEMSTS_CTSDETF_Pos (0) /*!< UART_T::MODEMSTS: CTSDETF Position */ +#define UART_MODEMSTS_CTSDETF_Msk (0x1ul << UART_MODEMSTS_CTSDETF_Pos) /*!< UART_T::MODEMSTS: CTSDETF Mask */ + +#define UART_MODEMSTS_CTSSTS_Pos (4) /*!< UART_T::MODEMSTS: CTSSTS Position */ +#define UART_MODEMSTS_CTSSTS_Msk (0x1ul << UART_MODEMSTS_CTSSTS_Pos) /*!< UART_T::MODEMSTS: CTSSTS Mask */ + +#define UART_MODEMSTS_CTSACTLV_Pos (8) /*!< UART_T::MODEMSTS: CTSACTLV Position */ +#define UART_MODEMSTS_CTSACTLV_Msk (0x1ul << UART_MODEMSTS_CTSACTLV_Pos) /*!< UART_T::MODEMSTS: CTSACTLV Mask */ + +#define UART_FIFOSTS_RXOVIF_Pos (0) /*!< UART_T::FIFOSTS: RXOVIF Position */ +#define UART_FIFOSTS_RXOVIF_Msk (0x1ul << UART_FIFOSTS_RXOVIF_Pos) /*!< UART_T::FIFOSTS: RXOVIF Mask */ + +#define UART_FIFOSTS_ABRDIF_Pos (1) /*!< UART_T::FIFOSTS: ABRDIF Position */ +#define UART_FIFOSTS_ABRDIF_Msk (0x1ul << UART_FIFOSTS_ABRDIF_Pos) /*!< UART_T::FIFOSTS: ABRDIF Mask */ + +#define UART_FIFOSTS_ABRDTOIF_Pos (2) /*!< UART_T::FIFOSTS: ABRDTOIF Position */ +#define UART_FIFOSTS_ABRDTOIF_Msk (0x1ul << UART_FIFOSTS_ABRDTOIF_Pos) /*!< UART_T::FIFOSTS: ABRDTOIF Mask */ + +#define UART_FIFOSTS_ADDRDETF_Pos (3) /*!< UART_T::FIFOSTS: ADDRDETF Position */ +#define UART_FIFOSTS_ADDRDETF_Msk (0x1ul << UART_FIFOSTS_ADDRDETF_Pos) /*!< UART_T::FIFOSTS: ADDRDETF Mask */ + +#define UART_FIFOSTS_PEF_Pos (4) /*!< UART_T::FIFOSTS: PEF Position */ +#define UART_FIFOSTS_PEF_Msk (0x1ul << UART_FIFOSTS_PEF_Pos) /*!< UART_T::FIFOSTS: PEF Mask */ + +#define UART_FIFOSTS_FEF_Pos (5) /*!< UART_T::FIFOSTS: FEF Position */ +#define UART_FIFOSTS_FEF_Msk (0x1ul << UART_FIFOSTS_FEF_Pos) /*!< UART_T::FIFOSTS: FEF Mask */ + +#define UART_FIFOSTS_BIF_Pos (6) /*!< UART_T::FIFOSTS: BIF Position */ +#define UART_FIFOSTS_BIF_Msk (0x1ul << UART_FIFOSTS_BIF_Pos) /*!< UART_T::FIFOSTS: BIF Mask */ + +#define UART_FIFOSTS_RXPTR_Pos (8) /*!< UART_T::FIFOSTS: RXPTR Position */ +#define UART_FIFOSTS_RXPTR_Msk (0x3ful << UART_FIFOSTS_RXPTR_Pos) /*!< UART_T::FIFOSTS: RXPTR Mask */ + +#define UART_FIFOSTS_RXEMPTY_Pos (14) /*!< UART_T::FIFOSTS: RXEMPTY Position */ +#define UART_FIFOSTS_RXEMPTY_Msk (0x1ul << UART_FIFOSTS_RXEMPTY_Pos) /*!< UART_T::FIFOSTS: RXEMPTY Mask */ + +#define UART_FIFOSTS_RXFULL_Pos (15) /*!< UART_T::FIFOSTS: RXFULL Position */ +#define UART_FIFOSTS_RXFULL_Msk (0x1ul << UART_FIFOSTS_RXFULL_Pos) /*!< UART_T::FIFOSTS: RXFULL Mask */ + +#define UART_FIFOSTS_TXPTR_Pos (16) /*!< UART_T::FIFOSTS: TXPTR Position */ +#define UART_FIFOSTS_TXPTR_Msk (0x3ful << UART_FIFOSTS_TXPTR_Pos) /*!< UART_T::FIFOSTS: TXPTR Mask */ + +#define UART_FIFOSTS_TXEMPTY_Pos (22) /*!< UART_T::FIFOSTS: TXEMPTY Position */ +#define UART_FIFOSTS_TXEMPTY_Msk (0x1ul << UART_FIFOSTS_TXEMPTY_Pos) /*!< UART_T::FIFOSTS: TXEMPTY Mask */ + +#define UART_FIFOSTS_TXFULL_Pos (23) /*!< UART_T::FIFOSTS: TXFULL Position */ +#define UART_FIFOSTS_TXFULL_Msk (0x1ul << UART_FIFOSTS_TXFULL_Pos) /*!< UART_T::FIFOSTS: TXFULL Mask */ + +#define UART_FIFOSTS_TXOVIF_Pos (24) /*!< UART_T::FIFOSTS: TXOVIF Position */ +#define UART_FIFOSTS_TXOVIF_Msk (0x1ul << UART_FIFOSTS_TXOVIF_Pos) /*!< UART_T::FIFOSTS: TXOVIF Mask */ + +#define UART_FIFOSTS_TXEMPTYF_Pos (28) /*!< UART_T::FIFOSTS: TXEMPTYF Position */ +#define UART_FIFOSTS_TXEMPTYF_Msk (0x1ul << UART_FIFOSTS_TXEMPTYF_Pos) /*!< UART_T::FIFOSTS: TXEMPTYF Mask */ + +#define UART_FIFOSTS_RXIDLE_Pos (29) /*!< UART_T::FIFOSTS: RXIDLE Position */ +#define UART_FIFOSTS_RXIDLE_Msk (0x1ul << UART_FIFOSTS_RXIDLE_Pos) /*!< UART_T::FIFOSTS: RXIDLE Mask */ + +#define UART_FIFOSTS_TXRXACT_Pos (31) /*!< UART_T::FIFOSTS: TXRXACT Position */ +#define UART_FIFOSTS_TXRXACT_Msk (0x1ul << UART_FIFOSTS_TXRXACT_Pos) /*!< UART_T::FIFOSTS: TXRXACT Mask */ + +#define UART_INTSTS_RDAIF_Pos (0) /*!< UART_T::INTSTS: RDAIF Position */ +#define UART_INTSTS_RDAIF_Msk (0x1ul << UART_INTSTS_RDAIF_Pos) /*!< UART_T::INTSTS: RDAIF Mask */ + +#define UART_INTSTS_THREIF_Pos (1) /*!< UART_T::INTSTS: THREIF Position */ +#define UART_INTSTS_THREIF_Msk (0x1ul << UART_INTSTS_THREIF_Pos) /*!< UART_T::INTSTS: THREIF Mask */ + +#define UART_INTSTS_RLSIF_Pos (2) /*!< UART_T::INTSTS: RLSIF Position */ +#define UART_INTSTS_RLSIF_Msk (0x1ul << UART_INTSTS_RLSIF_Pos) /*!< UART_T::INTSTS: RLSIF Mask */ + +#define UART_INTSTS_MODEMIF_Pos (3) /*!< UART_T::INTSTS: MODEMIF Position */ +#define UART_INTSTS_MODEMIF_Msk (0x1ul << UART_INTSTS_MODEMIF_Pos) /*!< UART_T::INTSTS: MODEMIF Mask */ + +#define UART_INTSTS_RXTOIF_Pos (4) /*!< UART_T::INTSTS: RXTOIF Position */ +#define UART_INTSTS_RXTOIF_Msk (0x1ul << UART_INTSTS_RXTOIF_Pos) /*!< UART_T::INTSTS: RXTOIF Mask */ + +#define UART_INTSTS_BUFERRIF_Pos (5) /*!< UART_T::INTSTS: BUFERRIF Position */ +#define UART_INTSTS_BUFERRIF_Msk (0x1ul << UART_INTSTS_BUFERRIF_Pos) /*!< UART_T::INTSTS: BUFERRIF Mask */ + +#define UART_INTSTS_WKIF_Pos (6) /*!< UART_T::INTSTS: WKIF Position */ +#define UART_INTSTS_WKIF_Msk (0x1ul << UART_INTSTS_WKIF_Pos) /*!< UART_T::INTSTS: WKIF Mask */ + +#define UART_INTSTS_LINIF_Pos (7) /*!< UART_T::INTSTS: LINIF Position */ +#define UART_INTSTS_LINIF_Msk (0x1ul << UART_INTSTS_LINIF_Pos) /*!< UART_T::INTSTS: LINIF Mask */ + +#define UART_INTSTS_RDAINT_Pos (8) /*!< UART_T::INTSTS: RDAINT Position */ +#define UART_INTSTS_RDAINT_Msk (0x1ul << UART_INTSTS_RDAINT_Pos) /*!< UART_T::INTSTS: RDAINT Mask */ + +#define UART_INTSTS_THREINT_Pos (9) /*!< UART_T::INTSTS: THREINT Position */ +#define UART_INTSTS_THREINT_Msk (0x1ul << UART_INTSTS_THREINT_Pos) /*!< UART_T::INTSTS: THREINT Mask */ + +#define UART_INTSTS_RLSINT_Pos (10) /*!< UART_T::INTSTS: RLSINT Position */ +#define UART_INTSTS_RLSINT_Msk (0x1ul << UART_INTSTS_RLSINT_Pos) /*!< UART_T::INTSTS: RLSINT Mask */ + +#define UART_INTSTS_MODEMINT_Pos (11) /*!< UART_T::INTSTS: MODEMINT Position */ +#define UART_INTSTS_MODEMINT_Msk (0x1ul << UART_INTSTS_MODEMINT_Pos) /*!< UART_T::INTSTS: MODEMINT Mask */ + +#define UART_INTSTS_RXTOINT_Pos (12) /*!< UART_T::INTSTS: RXTOINT Position */ +#define UART_INTSTS_RXTOINT_Msk (0x1ul << UART_INTSTS_RXTOINT_Pos) /*!< UART_T::INTSTS: RXTOINT Mask */ + +#define UART_INTSTS_BUFERRINT_Pos (13) /*!< UART_T::INTSTS: BUFERRINT Position */ +#define UART_INTSTS_BUFERRINT_Msk (0x1ul << UART_INTSTS_BUFERRINT_Pos) /*!< UART_T::INTSTS: BUFERRINT Mask */ + +#define UART_INTSTS_WKINT_Pos (14) /*!< UART_T::INTSTS: WKINT Position */ +#define UART_INTSTS_WKINT_Msk (0x1ul << UART_INTSTS_WKINT_Pos) /*!< UART_T::INTSTS: WKINT Mask */ + +#define UART_INTSTS_LININT_Pos (15) /*!< UART_T::INTSTS: LININT Position */ +#define UART_INTSTS_LININT_Msk (0x1ul << UART_INTSTS_LININT_Pos) /*!< UART_T::INTSTS: LININT Mask */ + +#define UART_INTSTS_SWBEIF_Pos (16) /*!< UART_T::INTSTS: SWBEIF Position */ +#define UART_INTSTS_SWBEIF_Msk (0x1ul << UART_INTSTS_SWBEIF_Pos) /*!< UART_T::INTSTS: SWBEIF Mask */ + +#define UART_INTSTS_HWRLSIF_Pos (18) /*!< UART_T::INTSTS: HWRLSIF Position */ +#define UART_INTSTS_HWRLSIF_Msk (0x1ul << UART_INTSTS_HWRLSIF_Pos) /*!< UART_T::INTSTS: HWRLSIF Mask */ + +#define UART_INTSTS_HWMODIF_Pos (19) /*!< UART_T::INTSTS: HWMODIF Position */ +#define UART_INTSTS_HWMODIF_Msk (0x1ul << UART_INTSTS_HWMODIF_Pos) /*!< UART_T::INTSTS: HWMODIF Mask */ + +#define UART_INTSTS_HWTOIF_Pos (20) /*!< UART_T::INTSTS: HWTOIF Position */ +#define UART_INTSTS_HWTOIF_Msk (0x1ul << UART_INTSTS_HWTOIF_Pos) /*!< UART_T::INTSTS: HWTOIF Mask */ + +#define UART_INTSTS_HWBUFEIF_Pos (21) /*!< UART_T::INTSTS: HWBUFEIF Position */ +#define UART_INTSTS_HWBUFEIF_Msk (0x1ul << UART_INTSTS_HWBUFEIF_Pos) /*!< UART_T::INTSTS: HWBUFEIF Mask */ + +#define UART_INTSTS_TXENDIF_Pos (22) /*!< UART_T::INTSTS: TXENDIF Position */ +#define UART_INTSTS_TXENDIF_Msk (0x1ul << UART_INTSTS_TXENDIF_Pos) /*!< UART_T::INTSTS: TXENDIF Mask */ + +#define UART_INTSTS_SWBEINT_Pos (24) /*!< UART_T::INTSTS: SWBEINT Position */ +#define UART_INTSTS_SWBEINT_Msk (0x1ul << UART_INTSTS_SWBEINT_Pos) /*!< UART_T::INTSTS: SWBEINT Mask */ + +#define UART_INTSTS_HWRLSINT_Pos (26) /*!< UART_T::INTSTS: HWRLSINT Position */ +#define UART_INTSTS_HWRLSINT_Msk (0x1ul << UART_INTSTS_HWRLSINT_Pos) /*!< UART_T::INTSTS: HWRLSINT Mask */ + +#define UART_INTSTS_HWMODINT_Pos (27) /*!< UART_T::INTSTS: HWMODINT Position */ +#define UART_INTSTS_HWMODINT_Msk (0x1ul << UART_INTSTS_HWMODINT_Pos) /*!< UART_T::INTSTS: HWMODINT Mask */ + +#define UART_INTSTS_HWTOINT_Pos (28) /*!< UART_T::INTSTS: HWTOINT Position */ +#define UART_INTSTS_HWTOINT_Msk (0x1ul << UART_INTSTS_HWTOINT_Pos) /*!< UART_T::INTSTS: HWTOINT Mask */ + +#define UART_INTSTS_HWBUFEINT_Pos (29) /*!< UART_T::INTSTS: HWBUFEINT Position */ +#define UART_INTSTS_HWBUFEINT_Msk (0x1ul << UART_INTSTS_HWBUFEINT_Pos) /*!< UART_T::INTSTS: HWBUFEINT Mask */ + +#define UART_INTSTS_TXENDINT_Pos (30) /*!< UART_T::INTSTS: TXENDINT Position */ +#define UART_INTSTS_TXENDINT_Msk (0x1ul << UART_INTSTS_TXENDINT_Pos) /*!< UART_T::INTSTS: TXENDINT Mask */ + +#define UART_INTSTS_ABRINT_Pos (31) /*!< UART_T::INTSTS: ABRINT Position */ +#define UART_INTSTS_ABRINT_Msk (0x1ul << UART_INTSTS_ABRINT_Pos) /*!< UART_T::INTSTS: ABRINT Mask */ + +#define UART_TOUT_TOIC_Pos (0) /*!< UART_T::TOUT: TOIC Position */ +#define UART_TOUT_TOIC_Msk (0xfful << UART_TOUT_TOIC_Pos) /*!< UART_T::TOUT: TOIC Mask */ + +#define UART_TOUT_DLY_Pos (8) /*!< UART_T::TOUT: DLY Position */ +#define UART_TOUT_DLY_Msk (0xfful << UART_TOUT_DLY_Pos) /*!< UART_T::TOUT: DLY Mask */ + +#define UART_BAUD_BRD_Pos (0) /*!< UART_T::BAUD: BRD Position */ +#define UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos) /*!< UART_T::BAUD: BRD Mask */ + +#define UART_BAUD_EDIVM1_Pos (24) /*!< UART_T::BAUD: EDIVM1 Position */ +#define UART_BAUD_EDIVM1_Msk (0xful << UART_BAUD_EDIVM1_Pos) /*!< UART_T::BAUD: EDIVM1 Mask */ + +#define UART_BAUD_BAUDM0_Pos (28) /*!< UART_T::BAUD: BAUDM0 Position */ +#define UART_BAUD_BAUDM0_Msk (0x1ul << UART_BAUD_BAUDM0_Pos) /*!< UART_T::BAUD: BAUDM0 Mask */ + +#define UART_BAUD_BAUDM1_Pos (29) /*!< UART_T::BAUD: BAUDM1 Position */ +#define UART_BAUD_BAUDM1_Msk (0x1ul << UART_BAUD_BAUDM1_Pos) /*!< UART_T::BAUD: BAUDM1 Mask */ + +#define UART_IRDA_TXEN_Pos (1) /*!< UART_T::IRDA: TXEN Position */ +#define UART_IRDA_TXEN_Msk (0x1ul << UART_IRDA_TXEN_Pos) /*!< UART_T::IRDA: TXEN Mask */ + +#define UART_IRDA_TXINV_Pos (5) /*!< UART_T::IRDA: TXINV Position */ +#define UART_IRDA_TXINV_Msk (0x1ul << UART_IRDA_TXINV_Pos) /*!< UART_T::IRDA: TXINV Mask */ + +#define UART_IRDA_RXINV_Pos (6) /*!< UART_T::IRDA: RXINV Position */ +#define UART_IRDA_RXINV_Msk (0x1ul << UART_IRDA_RXINV_Pos) /*!< UART_T::IRDA: RXINV Mask */ + +#define UART_ALTCTL_BRKFL_Pos (0) /*!< UART_T::ALTCTL: BRKFL Position */ +#define UART_ALTCTL_BRKFL_Msk (0xful << UART_ALTCTL_BRKFL_Pos) /*!< UART_T::ALTCTL: BRKFL Mask */ + +#define UART_ALTCTL_LINRXEN_Pos (6) /*!< UART_T::ALTCTL: LINRXEN Position */ +#define UART_ALTCTL_LINRXEN_Msk (0x1ul << UART_ALTCTL_LINRXEN_Pos) /*!< UART_T::ALTCTL: LINRXEN Mask */ + +#define UART_ALTCTL_LINTXEN_Pos (7) /*!< UART_T::ALTCTL: LINTXEN Position */ +#define UART_ALTCTL_LINTXEN_Msk (0x1ul << UART_ALTCTL_LINTXEN_Pos) /*!< UART_T::ALTCTL: LINTXEN Mask */ + +#define UART_ALTCTL_RS485NMM_Pos (8) /*!< UART_T::ALTCTL: RS485NMM Position */ +#define UART_ALTCTL_RS485NMM_Msk (0x1ul << UART_ALTCTL_RS485NMM_Pos) /*!< UART_T::ALTCTL: RS485NMM Mask */ + +#define UART_ALTCTL_RS485AAD_Pos (9) /*!< UART_T::ALTCTL: RS485AAD Position */ +#define UART_ALTCTL_RS485AAD_Msk (0x1ul << UART_ALTCTL_RS485AAD_Pos) /*!< UART_T::ALTCTL: RS485AAD Mask */ + +#define UART_ALTCTL_RS485AUD_Pos (10) /*!< UART_T::ALTCTL: RS485AUD Position */ +#define UART_ALTCTL_RS485AUD_Msk (0x1ul << UART_ALTCTL_RS485AUD_Pos) /*!< UART_T::ALTCTL: RS485AUD Mask */ + +#define UART_ALTCTL_ADDRDEN_Pos (15) /*!< UART_T::ALTCTL: ADDRDEN Position */ +#define UART_ALTCTL_ADDRDEN_Msk (0x1ul << UART_ALTCTL_ADDRDEN_Pos) /*!< UART_T::ALTCTL: ADDRDEN Mask */ + +#define UART_ALTCTL_ABRIF_Pos (17) /*!< UART_T::ALTCTL: ABRIF Position */ +#define UART_ALTCTL_ABRIF_Msk (0x1ul << UART_ALTCTL_ABRIF_Pos) /*!< UART_T::ALTCTL: ABRIF Mask */ + +#define UART_ALTCTL_ABRDEN_Pos (18) /*!< UART_T::ALTCTL: ABRDEN Position */ +#define UART_ALTCTL_ABRDEN_Msk (0x1ul << UART_ALTCTL_ABRDEN_Pos) /*!< UART_T::ALTCTL: ABRDEN Mask */ + +#define UART_ALTCTL_ABRDBITS_Pos (19) /*!< UART_T::ALTCTL: ABRDBITS Position */ +#define UART_ALTCTL_ABRDBITS_Msk (0x3ul << UART_ALTCTL_ABRDBITS_Pos) /*!< UART_T::ALTCTL: ABRDBITS Mask */ + +#define UART_ALTCTL_ADDRMV_Pos (24) /*!< UART_T::ALTCTL: ADDRMV Position */ +#define UART_ALTCTL_ADDRMV_Msk (0xfful << UART_ALTCTL_ADDRMV_Pos) /*!< UART_T::ALTCTL: ADDRMV Mask */ + +#define UART_FUNCSEL_FUNCSEL_Pos (0) /*!< UART_T::FUNCSEL: FUNCSEL Position */ +#define UART_FUNCSEL_FUNCSEL_Msk (0x7ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_T::FUNCSEL: FUNCSEL Mask */ + +#define UART_FUNCSEL_TXRXDIS_Pos (3) /*!< UART_T::FUNCSEL: TXRXDIS Position */ +#define UART_FUNCSEL_TXRXDIS_Msk (0x1ul << UART_FUNCSEL_TXRXDIS_Pos) /*!< UART_T::FUNCSEL: TXRXDIS Mask */ + +#define UART_LINCTL_SLVEN_Pos (0) /*!< UART_T::LINCTL: SLVEN Position */ +#define UART_LINCTL_SLVEN_Msk (0x1ul << UART_LINCTL_SLVEN_Pos) /*!< UART_T::LINCTL: SLVEN Mask */ + +#define UART_LINCTL_SLVHDEN_Pos (1) /*!< UART_T::LINCTL: SLVHDEN Position */ +#define UART_LINCTL_SLVHDEN_Msk (0x1ul << UART_LINCTL_SLVHDEN_Pos) /*!< UART_T::LINCTL: SLVHDEN Mask */ + +#define UART_LINCTL_SLVAREN_Pos (2) /*!< UART_T::LINCTL: SLVAREN Position */ +#define UART_LINCTL_SLVAREN_Msk (0x1ul << UART_LINCTL_SLVAREN_Pos) /*!< UART_T::LINCTL: SLVAREN Mask */ + +#define UART_LINCTL_SLVDUEN_Pos (3) /*!< UART_T::LINCTL: SLVDUEN Position */ +#define UART_LINCTL_SLVDUEN_Msk (0x1ul << UART_LINCTL_SLVDUEN_Pos) /*!< UART_T::LINCTL: SLVDUEN Mask */ + +#define UART_LINCTL_MUTE_Pos (4) /*!< UART_T::LINCTL: MUTE Position */ +#define UART_LINCTL_MUTE_Msk (0x1ul << UART_LINCTL_MUTE_Pos) /*!< UART_T::LINCTL: MUTE Mask */ + +#define UART_LINCTL_SENDH_Pos (8) /*!< UART_T::LINCTL: SENDH Position */ +#define UART_LINCTL_SENDH_Msk (0x1ul << UART_LINCTL_SENDH_Pos) /*!< UART_T::LINCTL: SENDH Mask */ + +#define UART_LINCTL_IDPEN_Pos (9) /*!< UART_T::LINCTL: IDPEN Position */ +#define UART_LINCTL_IDPEN_Msk (0x1ul << UART_LINCTL_IDPEN_Pos) /*!< UART_T::LINCTL: IDPEN Mask */ + +#define UART_LINCTL_BRKDETEN_Pos (10) /*!< UART_T::LINCTL: BRKDETEN Position */ +#define UART_LINCTL_BRKDETEN_Msk (0x1ul << UART_LINCTL_BRKDETEN_Pos) /*!< UART_T::LINCTL: BRKDETEN Mask */ + +#define UART_LINCTL_LINRXOFF_Pos (11) /*!< UART_T::LINCTL: LINRXOFF Position */ +#define UART_LINCTL_LINRXOFF_Msk (0x1ul << UART_LINCTL_LINRXOFF_Pos) /*!< UART_T::LINCTL: LINRXOFF Mask */ + +#define UART_LINCTL_BITERREN_Pos (12) /*!< UART_T::LINCTL: BITERREN Position */ +#define UART_LINCTL_BITERREN_Msk (0x1ul << UART_LINCTL_BITERREN_Pos) /*!< UART_T::LINCTL: BITERREN Mask */ + +#define UART_LINCTL_BRKFL_Pos (16) /*!< UART_T::LINCTL: BRKFL Position */ +#define UART_LINCTL_BRKFL_Msk (0xful << UART_LINCTL_BRKFL_Pos) /*!< UART_T::LINCTL: BRKFL Mask */ + +#define UART_LINCTL_BSL_Pos (20) /*!< UART_T::LINCTL: BSL Position */ +#define UART_LINCTL_BSL_Msk (0x3ul << UART_LINCTL_BSL_Pos) /*!< UART_T::LINCTL: BSL Mask */ + +#define UART_LINCTL_HSEL_Pos (22) /*!< UART_T::LINCTL: HSEL Position */ +#define UART_LINCTL_HSEL_Msk (0x3ul << UART_LINCTL_HSEL_Pos) /*!< UART_T::LINCTL: HSEL Mask */ + +#define UART_LINCTL_PID_Pos (24) /*!< UART_T::LINCTL: PID Position */ +#define UART_LINCTL_PID_Msk (0xfful << UART_LINCTL_PID_Pos) /*!< UART_T::LINCTL: PID Mask */ + +#define UART_LINSTS_SLVHDETF_Pos (0) /*!< UART_T::LINSTS: SLVHDETF Position */ +#define UART_LINSTS_SLVHDETF_Msk (0x1ul << UART_LINSTS_SLVHDETF_Pos) /*!< UART_T::LINSTS: SLVHDETF Mask */ + +#define UART_LINSTS_SLVHEF_Pos (1) /*!< UART_T::LINSTS: SLVHEF Position */ +#define UART_LINSTS_SLVHEF_Msk (0x1ul << UART_LINSTS_SLVHEF_Pos) /*!< UART_T::LINSTS: SLVHEF Mask */ + +#define UART_LINSTS_SLVIDPEF_Pos (2) /*!< UART_T::LINSTS: SLVIDPEF Position */ +#define UART_LINSTS_SLVIDPEF_Msk (0x1ul << UART_LINSTS_SLVIDPEF_Pos) /*!< UART_T::LINSTS: SLVIDPEF Mask */ + +#define UART_LINSTS_SLVSYNCF_Pos (3) /*!< UART_T::LINSTS: SLVSYNCF Position */ +#define UART_LINSTS_SLVSYNCF_Msk (0x1ul << UART_LINSTS_SLVSYNCF_Pos) /*!< UART_T::LINSTS: SLVSYNCF Mask */ + +#define UART_LINSTS_BRKDETF_Pos (8) /*!< UART_T::LINSTS: BRKDETF Position */ +#define UART_LINSTS_BRKDETF_Msk (0x1ul << UART_LINSTS_BRKDETF_Pos) /*!< UART_T::LINSTS: BRKDETF Mask */ + +#define UART_LINSTS_BITEF_Pos (9) /*!< UART_T::LINSTS: BITEF Position */ +#define UART_LINSTS_BITEF_Msk (0x1ul << UART_LINSTS_BITEF_Pos) /*!< UART_T::LINSTS: BITEF Mask */ + +#define UART_BRCOMP_BRCOMP_Pos (0) /*!< UART_T::BRCOMP: BRCOMP Position */ +#define UART_BRCOMP_BRCOMP_Msk (0x1fful << UART_BRCOMP_BRCOMP_Pos) /*!< UART_T::BRCOMP: BRCOMP Mask */ + +#define UART_BRCOMP_BRCOMPDEC_Pos (31) /*!< UART_T::BRCOMP: BRCOMPDEC Position */ +#define UART_BRCOMP_BRCOMPDEC_Msk (0x1ul << UART_BRCOMP_BRCOMPDEC_Pos) /*!< UART_T::BRCOMP: BRCOMPDEC Mask */ + +#define UART_WKCTL_WKCTSEN_Pos (0) /*!< UART_T::WKCTL: WKCTSEN Position */ +#define UART_WKCTL_WKCTSEN_Msk (0x1ul << UART_WKCTL_WKCTSEN_Pos) /*!< UART_T::WKCTL: WKCTSEN Mask */ + +#define UART_WKCTL_WKDATEN_Pos (1) /*!< UART_T::WKCTL: WKDATEN Position */ +#define UART_WKCTL_WKDATEN_Msk (0x1ul << UART_WKCTL_WKDATEN_Pos) /*!< UART_T::WKCTL: WKDATEN Mask */ + +#define UART_WKCTL_WKRFRTEN_Pos (2) /*!< UART_T::WKCTL: WKRFRTEN Position */ +#define UART_WKCTL_WKRFRTEN_Msk (0x1ul << UART_WKCTL_WKRFRTEN_Pos) /*!< UART_T::WKCTL: WKRFRTEN Mask */ + +#define UART_WKCTL_WKRS485EN_Pos (3) /*!< UART_T::WKCTL: WKRS485EN Position */ +#define UART_WKCTL_WKRS485EN_Msk (0x1ul << UART_WKCTL_WKRS485EN_Pos) /*!< UART_T::WKCTL: WKRS485EN Mask */ + +#define UART_WKCTL_WKTOUTEN_Pos (4) /*!< UART_T::WKCTL: WKTOUTEN Position */ +#define UART_WKCTL_WKTOUTEN_Msk (0x1ul << UART_WKCTL_WKTOUTEN_Pos) /*!< UART_T::WKCTL: WKTOUTEN Mask */ + +#define UART_WKSTS_CTSWKF_Pos (0) /*!< UART_T::WKSTS: CTSWKF Position */ +#define UART_WKSTS_CTSWKF_Msk (0x1ul << UART_WKSTS_CTSWKF_Pos) /*!< UART_T::WKSTS: CTSWKF Mask */ + +#define UART_WKSTS_DATWKF_Pos (1) /*!< UART_T::WKSTS: DATWKF Position */ +#define UART_WKSTS_DATWKF_Msk (0x1ul << UART_WKSTS_DATWKF_Pos) /*!< UART_T::WKSTS: DATWKF Mask */ + +#define UART_WKSTS_RFRTWKF_Pos (2) /*!< UART_T::WKSTS: RFRTWKF Position */ +#define UART_WKSTS_RFRTWKF_Msk (0x1ul << UART_WKSTS_RFRTWKF_Pos) /*!< UART_T::WKSTS: RFRTWKF Mask */ + +#define UART_WKSTS_RS485WKF_Pos (3) /*!< UART_T::WKSTS: RS485WKF Position */ +#define UART_WKSTS_RS485WKF_Msk (0x1ul << UART_WKSTS_RS485WKF_Pos) /*!< UART_T::WKSTS: RS485WKF Mask */ + +#define UART_WKSTS_TOUTWKF_Pos (4) /*!< UART_T::WKSTS: TOUTWKF Position */ +#define UART_WKSTS_TOUTWKF_Msk (0x1ul << UART_WKSTS_TOUTWKF_Pos) /*!< UART_T::WKSTS: TOUTWKF Mask */ + +#define UART_DWKCOMP_STCOMP_Pos (0) /*!< UART_T::DWKCOMP: STCOMP Position */ +#define UART_DWKCOMP_STCOMP_Msk (0xfffful << UART_DWKCOMP_STCOMP_Pos) /*!< UART_T::DWKCOMP: STCOMP Mask */ + + +/**@}*/ /* UART_CONST */ +/**@}*/ /* end of UART register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __UART_REG_H__ */ \ No newline at end of file diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/ui2c_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/ui2c_reg.h new file mode 100644 index 00000000000..a3cca104977 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/ui2c_reg.h @@ -0,0 +1,576 @@ +/**************************************************************************//** + * @file ui2c_reg.h + * @version V1.00 + * @brief UI2C register definition header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __UI2C_REG_H__ +#define __UI2C_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup UI2C I2C Mode of USCI Controller (UI2C) + Memory Mapped Structure for UI2C Controller +@{ */ + +typedef struct +{ + + + /** + * @var UI2C_T::CTL + * Offset: 0x00 USCI Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |FUNMODE |Function Mode + * | | |This bit field selects the protocol for this USCI controller + * | | |Selecting a protocol that is not available or a reserved combination disables the USCI + * | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol + * | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE. + * | | |000 = The USCI is disabled. All protocol related state machines are set to idle state. + * | | |001 = The SPI protocol is selected. + * | | |010 = The UART protocol is selected. + * | | |100 = The I2C protocol is selected. + * | | |Note: Other bit combinations are reserved. + * @var UI2C_T::BRGEN + * Offset: 0x08 USCI Baud Rate Generator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RCLKSEL |Reference Clock Source Selection + * | | |This bit selects the source signal of reference clock (fREF_CLK). + * | | |0 = Peripheral device clock fPCLK. + * | | |1 = Reserved. + * |[1] |PTCLKSEL |Protocol Clock Source Selection + * | | |This bit selects the source signal of protocol clock (fPROT_CLK). + * | | |0 = Reference clock fREF_CLK. + * | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK). + * |[3:2] |SPCLKSEL |Sample Clock Source Selection + * | | |This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor. + * | | |00 = fSAMP_CLK = fDIV_CLK. + * | | |01 = fSAMP_CLK = fPROT_CLK. + * | | |10 = fSAMP_CLK = fSCLK. + * | | |11 = fSAMP_CLK = fREF_CLK. + * |[4] |TMCNTEN |Time Measurement Counter Enable Bit + * | | |This bit enables the 10-bit timing measurement counter. + * | | |0 = Time measurement counter is Disabled. + * | | |1 = Time measurement counter is Enabled. + * |[5] |TMCNTSRC |Time Measurement Counter Clock Source Selection + * | | |0 = Time measurement counter with fPROT_CLK. + * | | |1 = Time measurement counter with fDIV_CLK. + * |[9:8] |PDSCNT |Pre-divider for Sample Counter + * | | |This bit field defines the divide ratio of the clock division from sample clock fSAMP_CLK + * | | |The divided frequency fPDS_CNT = fSAMP_CLK / (PDSCNT+1). + * |[14:10] |DSCNT |Denominator for Sample Counter + * | | |This bit field defines the divide ratio of the sample clock fSAMP_CLK. + * | | |The divided frequency fDS_CNT = fPDS_CNT / (DSCNT+1). + * | | |Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value + * |[25:16] |CLKDIV |Clock Divider + * | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ). + * | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UI2C_PROTCTL[6])) is enabled + * | | |The revised value is the average bit time between bit 5 and bit 6 + * | | |The user can use revised CLKDIV and new BRDETITV (UI2C_PROTCTL[24:16]) to calculate the precise baud rate. + * @var UI2C_T::LINECTL + * Offset: 0x2C USCI Line Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LSB |LSB First Transmission Selection + * | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first. + * | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first. + * |[11:8] |DWIDTH |Word Length of Transmission + * | | |This bit field defines the data word length (amount of bits) for reception and transmission + * | | |The data word is always right-aligned in the data buffer + * | | |USCI support word length from 4 to 16 bits. + * | | |0x0: The data word contains 16 bits located at bit positions [15:0]. + * | | |0x1: Reserved. + * | | |0x2: Reserved. + * | | |0x3: Reserved. + * | | |0x4: The data word contains 4 bits located at bit positions [3:0]. + * | | |0x5: The data word contains 5 bits located at bit positions [4:0]. + * | | |... + * | | |0xF: The data word contains 15 bits located at bit positions [14:0]. + * | | |Note: In UART protocol, the length can be configured as 6~13 bits + * | | |And in I2C protocol, the length fixed as 8 bits. + * @var UI2C_T::TXDAT + * Offset: 0x30 USCI Transmit Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TXDAT |Transmit Data + * | | |Software can use this bit field to write 16-bit transmit data for transmission. + * @var UI2C_T::RXDAT + * Offset: 0x34 USCI Receive Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RXDAT |Received Data + * | | |This bit field monitors the received data which stored in receive data buffer. + * | | |Note 1: In I2C protocol, RXDAT[12:8] indicate the different transmission conditions which defined in I2C. + * | | |Note 2: In UART protocol, RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (UI2C_PROTSTS[7:5]). + * @var UI2C_T::DEVADDR0 + * Offset: 0x44 USCI Device Address Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |DEVADDR |Device Address + * | | |In I2C protocol, this bit field contains the programmed slave address + * | | |If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit + * | | |Then the second address byte is also compared to DEVADDR[7:0]. + * | | |Note 1: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode. + * | | |Note 2: When software set 10'h000, the address can not be used. + * @var UI2C_T::DEVADDR1 + * Offset: 0x48 USCI Device Address Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |DEVADDR |Device Address + * | | |In I2C protocol, this bit field contains the programmed slave address + * | | |If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit + * | | |Then the second address byte is also compared to DEVADDR[7:0]. + * | | |Note 1: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode. + * | | |Note 2: When software set 10'h000, the address can not be used. + * @var UI2C_T::ADDRMSK0 + * Offset: 0x4C USCI Device Address Mask Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |ADDRMSK |USCI Device Address Mask + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |USCI support multiple address recognition with two address mask register + * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care + * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. + * | | |Note: The wake-up function can not use address mask. + * @var UI2C_T::ADDRMSK1 + * Offset: 0x50 USCI Device Address Mask Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |ADDRMSK |USCI Device Address Mask + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |USCI support multiple address recognition with two address mask register + * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care + * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. + * | | |Note: The wake-up function can not use address mask. + * @var UI2C_T::WKCTL + * Offset: 0x54 USCI Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Wake-up Enable Bit + * | | |0 = Wake-up function Disabled. + * | | |1 = Wake-up function Enabled. + * |[1] |WKADDREN |Wake-up Address Match Enable Bit + * | | |0 = The chip is woken up according data toggle. + * | | |1 = The chip is woken up according address match. + * @var UI2C_T::WKSTS + * Offset: 0x58 USCI Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKF |Wake-up Flag + * | | |When chip is woken up from Power-down mode, this bit is set to 1 + * | | |Software can write 1 to clear this bit. + * @var UI2C_T::PROTCTL + * Offset: 0x5C USCI Protocol Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GCFUNC |General Call Function + * | | |0 = General Call Function Disabled. + * | | |1 = General Call Function Enabled. + * |[1] |AA |Assert Acknowledge Control + * | | |When AA =1 prior to address or data received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter + * | | |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line. + * |[2] |STO |I2C STOP Control + * | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically + * | | |In a slave mode, setting STO resets I2C hardware to the defined "not addressed" slave mode when bus error (UI2C_PROTSTS.ERRIF = 1). + * |[3] |STA |I2C START Control + * | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. + * |[4] |ADDR10EN |Address 10-bit Function Enable Bit + * | | |0 = Address match 10 bit function is disabled. + * | | |1 = Address match 10 bit function is enabled. + * |[5] |PTRG |I2C Protocol Trigger (Write Only) + * | | |When a new state is present in the UI2C_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested + * | | |It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTEN is disabled. + * | | |0 = I2C's stretch disabled and the I2C protocol function will go ahead. + * | | |1 = I2C's stretch active. + * |[8] |SCLOUTEN |SCL Output Enable Bit + * | | |This bit enables monitor pulling SCL to low + * | | |This monitor will pull SCL to low until it has had time to respond to an I2C interrupt. + * | | |0 = SCL output will be forced high due to open drain mechanism. + * | | |1 = I2C module may act as a slave peripheral just like in normal operation, the I2C holds the clock line low until it has had time to clear I2C interrupt. + * |[9] |MONEN |Monitor Mode Enable Bit + * | | |This bit enables monitor mode + * | | |In monitor mode the SDA output will be put in high impedance mode + * | | |This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. + * | | |0 = The monitor mode is disabled. + * | | |1 = The monitor mode is enabled. + * | | |Note: Depending on the state of the SCLOUTEN bit, the SCL output may be also forced high, preventing the module from having control over the I2C clock line. + * |[25:16] |TOCNT |Time-out Clock Cycle + * | | |This bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear + * | | |The time-out is enable when TOCNT bigger than 0. + * | | |Note: The TMCNTSRC (UI2C_BRGEN [5]) must be set zero on I2C mode. + * |[31] |PROTEN |I2C Protocol Enable Bit + * | | |0 = I2C Protocol disable. + * | | |1 = I2C Protocol enable. + * @var UI2C_T::PROTIEN + * Offset: 0x60 USCI Protocol Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TOIEN |Time-out Interrupt Enable Control + * | | |In I2C protocol, this bit enables the interrupt generation in case of a time-out event. + * | | |0 = The time-out interrupt is disabled. + * | | |1 = The time-out interrupt is enabled. + * |[1] |STARIEN |Start Condition Received Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if a start condition is detected. + * | | |0 = The start condition interrupt is disabled. + * | | |1 = The start condition interrupt is enabled. + * |[2] |STORIEN |Stop Condition Received Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if a stop condition is detected. + * | | |0 = The stop condition interrupt is disabled. + * | | |1 = The stop condition interrupt is enabled. + * |[3] |NACKIEN |Non - Acknowledge Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if a non - acknowledge is detected by a master. + * | | |0 = The non - acknowledge interrupt is disabled. + * | | |1 = The non - acknowledge interrupt is enabled. + * |[4] |ARBLOIEN |Arbitration Lost Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if an arbitration lost event is detected. + * | | |0 = The arbitration lost interrupt is disabled. + * | | |1 = The arbitration lost interrupt is enabled. + * |[5] |ERRIEN |Error Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (UI2C_PROTSTS [16])). + * | | |0 = The error interrupt is disabled. + * | | |1 = The error interrupt is enabled. + * |[6] |ACKIEN |Acknowledge Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if an acknowledge is detected by a master. + * | | |0 = The acknowledge interrupt is disabled. + * | | |1 = The acknowledge interrupt is enabled. + * @var UI2C_T::PROTSTS + * Offset: 0x64 USCI Protocol Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5] |TOIF |Time-out Interrupt Flag + * | | |0 = A time-out interrupt status has not occurred. + * | | |1 = A time-out interrupt status has occurred. + * | | |Note: It is cleared by software writing one into this bit + * |[6] |ONBUSY |On Bus Busy + * | | |Indicates that a communication is in progress on the bus + * | | |It is set by hardware when a START condition is detected + * | | |It is cleared by hardware when a STOP condition is detected + * | | |0 = The bus is IDLE (both SCLK and SDA High). + * | | |1 = The bus is busy. + * |[8] |STARIF |Start Condition Received Interrupt Flag + * | | |This bit indicates that a start condition or repeated start condition has been detected on master mode + * | | |However, this bit also indicates that a repeated start condition has been detected on slave mode. + * | | |A protocol interrupt can be generated if UI2C_PROTCTL.STARIEN = 1. + * | | |0 = A start condition has not yet been detected. + * | | |1 = A start condition has been detected. + * | | |It is cleared by software writing one into this bit + * |[9] |STORIF |Stop Condition Received Interrupt Flag + * | | |This bit indicates that a stop condition has been detected on the I2C bus lines + * | | |A protocol interrupt can be generated if UI2C_PROTCTL.STORIEN = 1. + * | | |0 = A stop condition has not yet been detected. + * | | |1 = A stop condition has been detected. + * | | |It is cleared by software writing one into this bit + * | | |Note: This bit is set when slave RX mode. + * |[10] |NACKIF |Non - Acknowledge Received Interrupt Flag + * | | |This bit indicates that a non - acknowledge has been received in master mode + * | | |A protocol interrupt can be generated if UI2C_PROTCTL.NACKIEN = 1. + * | | |0 = A non - acknowledge has not been received. + * | | |1 = A non - acknowledge has been received. + * | | |It is cleared by software writing one into this bit + * |[11] |ARBLOIF |Arbitration Lost Interrupt Flag + * | | |This bit indicates that an arbitration has been lost + * | | |A protocol interrupt can be generated if UI2C_PROTCTL.ARBLOIEN = 1. + * | | |0 = An arbitration has not been lost. + * | | |1 = An arbitration has been lost. + * | | |It is cleared by software writing one into this bit + * |[12] |ERRIF |Error Interrupt Flag + * | | |This bit indicates that a Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame + * | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit + * | | |A protocol interrupt can be generated if UI2C_PROTCTL.ERRIEN = 1. + * | | |0 = An I2C error has not been detected. + * | | |1 = An I2C error has been detected. + * | | |It is cleared by software writing one into this bit + * | | |Note: This bit is set when slave mode, user must write one into STO register to the defined "not addressed" slave mode. + * |[13] |ACKIF |Acknowledge Received Interrupt Flag + * | | |This bit indicates that an acknowledge has been received in master mode + * | | |A protocol interrupt can be generated if UI2C_PROTCTL.ACKIEN = 1. + * | | |0 = An acknowledge has not been received. + * | | |1 = An acknowledge has been received. + * | | |It is cleared by software writing one into this bit + * |[14] |SLASEL |Slave Select Status + * | | |This bit indicates that this device has been selected as slave. + * | | |0 = The device is not selected as slave. + * | | |1 = The device is selected as slave. + * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware. + * |[15] |SLAREAD |Slave Read Request Status + * | | |This bit indicates that a slave read request has been detected. + * | | |0 = A slave R/W bit is 1 has not been detected. + * | | |1 = A slave R/W bit is 1 has been detected. + * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware. + * |[16] |WKAKDONE |Wakeup Address Frame Acknowledge Bit Done + * | | |0 = The ACK bit cycle of address match frame isn't done. + * | | |1 = The ACK bit cycle of address match frame is done in power-down. + * | | |Note: This bit can't release when WKUPIF is set. + * |[17] |WRSTSWK |Read/Write Status Bit in Address Wakeup Frame + * | | |0 = Write command be record on the address match wakeup frame. + * | | |1 = Read command be record on the address match wakeup frame. + * |[18] |BUSHANG |Bus Hang-up + * | | |This bit indicates bus hang-up status + * | | |There is 4-bit counter count when SCL hold high and refer fSAMP_CLK + * | | |The hang-up counter will count to overflow and set this bit when SDA is low + * | | |The counter will be reset by falling edge of SCL signal. + * | | |0 = The bus is normal status for transmission. + * | | |1 = The bus is hang-up status for transmission. + * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present. + * |[19] |ERRARBLO |Error Arbitration Lost + * | | |This bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor + * | | |The I2C can send start condition when ERRARBLO is set + * | | |Thus this bit doesn't be cared on slave mode. + * | | |0 = The bus is normal status for transmission. + * | | |1 = The bus is error arbitration lost status for transmission. + * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present. + * @var UI2C_T::ADMAT + * Offset: 0x88 I2C Slave Match Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADMAT0 |USCI Address 0 Match Status Register + * | | |When address 0 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * |[1] |ADMAT1 |USCI Address 1 Match Status Register + * | | |When address 1 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * @var UI2C_T::TMCTL + * Offset: 0x8C I2C Timing Configure Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |STCTL |Setup Time Configure Control Register + * | | |This field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode.. + * | | |The delay setup time is numbers of peripheral clock = STCTL x fPCLK. + * |[24:16] |HTCTL |Hold Time Configure Control Register + * | | |This field is used to generate the delay timing between SCL falling edge SDA edge in + * | | |transmission mode. + * | | |The delay hold time is numbers of peripheral clock = HTCTL x fPCLK. + */ + __IO uint32_t CTL; /*!< [0x0000] USCI Control Register */ + __I uint32_t RESERVE0[1]; + __IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */ + __I uint32_t RESERVE1[8]; + __IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */ + __O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */ + __I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */ + __I uint32_t RESERVE2[3]; + __IO uint32_t DEVADDR0; /*!< [0x0044] USCI Device Address Register 0 */ + __IO uint32_t DEVADDR1; /*!< [0x0048] USCI Device Address Register 1 */ + __IO uint32_t ADDRMSK0; /*!< [0x004c] USCI Device Address Mask Register 0 */ + __IO uint32_t ADDRMSK1; /*!< [0x0050] USCI Device Address Mask Register 1 */ + __IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */ + __IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */ + __IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */ + __IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */ + __IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */ + __I uint32_t RESERVE3[8]; + __IO uint32_t ADMAT; /*!< [0x0088] I2C Slave Match Address Register */ + __IO uint32_t TMCTL; /*!< [0x008c] I2C Timing Configure Control Register */ + +} UI2C_T; + +/** + @addtogroup UI2C_CONST UI2C Bit Field Definition + Constant Definitions for UI2C Controller +@{ */ + +#define UI2C_CTL_FUNMODE_Pos (0) /*!< UI2C_T::CTL: FUNMODE Position */ +#define UI2C_CTL_FUNMODE_Msk (0x7ul << UI2C_CTL_FUNMODE_Pos) /*!< UI2C_T::CTL: FUNMODE Mask */ + +#define UI2C_BRGEN_RCLKSEL_Pos (0) /*!< UI2C_T::BRGEN: RCLKSEL Position */ +#define UI2C_BRGEN_RCLKSEL_Msk (0x1ul << UI2C_BRGEN_RCLKSEL_Pos) /*!< UI2C_T::BRGEN: RCLKSEL Mask */ + +#define UI2C_BRGEN_PTCLKSEL_Pos (1) /*!< UI2C_T::BRGEN: PTCLKSEL Position */ +#define UI2C_BRGEN_PTCLKSEL_Msk (0x1ul << UI2C_BRGEN_PTCLKSEL_Pos) /*!< UI2C_T::BRGEN: PTCLKSEL Mask */ + +#define UI2C_BRGEN_SPCLKSEL_Pos (2) /*!< UI2C_T::BRGEN: SPCLKSEL Position */ +#define UI2C_BRGEN_SPCLKSEL_Msk (0x3ul << UI2C_BRGEN_SPCLKSEL_Pos) /*!< UI2C_T::BRGEN: SPCLKSEL Mask */ + +#define UI2C_BRGEN_TMCNTEN_Pos (4) /*!< UI2C_T::BRGEN: TMCNTEN Position */ +#define UI2C_BRGEN_TMCNTEN_Msk (0x1ul << UI2C_BRGEN_TMCNTEN_Pos) /*!< UI2C_T::BRGEN: TMCNTEN Mask */ + +#define UI2C_BRGEN_TMCNTSRC_Pos (5) /*!< UI2C_T::BRGEN: TMCNTSRC Position */ +#define UI2C_BRGEN_TMCNTSRC_Msk (0x1ul << UI2C_BRGEN_TMCNTSRC_Pos) /*!< UI2C_T::BRGEN: TMCNTSRC Mask */ + +#define UI2C_BRGEN_PDSCNT_Pos (8) /*!< UI2C_T::BRGEN: PDSCNT Position */ +#define UI2C_BRGEN_PDSCNT_Msk (0x3ul << UI2C_BRGEN_PDSCNT_Pos) /*!< UI2C_T::BRGEN: PDSCNT Mask */ + +#define UI2C_BRGEN_DSCNT_Pos (10) /*!< UI2C_T::BRGEN: DSCNT Position */ +#define UI2C_BRGEN_DSCNT_Msk (0x1ful << UI2C_BRGEN_DSCNT_Pos) /*!< UI2C_T::BRGEN: DSCNT Mask */ + +#define UI2C_BRGEN_CLKDIV_Pos (16) /*!< UI2C_T::BRGEN: CLKDIV Position */ +#define UI2C_BRGEN_CLKDIV_Msk (0x3fful << UI2C_BRGEN_CLKDIV_Pos) /*!< UI2C_T::BRGEN: CLKDIV Mask */ + +#define UI2C_LINECTL_LSB_Pos (0) /*!< UI2C_T::LINECTL: LSB Position */ +#define UI2C_LINECTL_LSB_Msk (0x1ul << UI2C_LINECTL_LSB_Pos) /*!< UI2C_T::LINECTL: LSB Mask */ + +#define UI2C_LINECTL_DWIDTH_Pos (8) /*!< UI2C_T::LINECTL: DWIDTH Position */ +#define UI2C_LINECTL_DWIDTH_Msk (0xful << UI2C_LINECTL_DWIDTH_Pos) /*!< UI2C_T::LINECTL: DWIDTH Mask */ + +#define UI2C_TXDAT_TXDAT_Pos (0) /*!< UI2C_T::TXDAT: TXDAT Position */ +#define UI2C_TXDAT_TXDAT_Msk (0xfffful << UI2C_TXDAT_TXDAT_Pos) /*!< UI2C_T::TXDAT: TXDAT Mask */ + +#define UI2C_RXDAT_RXDAT_Pos (0) /*!< UI2C_T::RXDAT: RXDAT Position */ +#define UI2C_RXDAT_RXDAT_Msk (0xfffful << UI2C_RXDAT_RXDAT_Pos) /*!< UI2C_T::RXDAT: RXDAT Mask */ + +#define UI2C_DEVADDR0_DEVADDR_Pos (0) /*!< UI2C_T::DEVADDR0: DEVADDR Position */ +#define UI2C_DEVADDR0_DEVADDR_Msk (0x3fful << UI2C_DEVADDR0_DEVADDR_Pos) /*!< UI2C_T::DEVADDR0: DEVADDR Mask */ + +#define UI2C_DEVADDR1_DEVADDR_Pos (0) /*!< UI2C_T::DEVADDR1: DEVADDR Position */ +#define UI2C_DEVADDR1_DEVADDR_Msk (0x3fful << UI2C_DEVADDR1_DEVADDR_Pos) /*!< UI2C_T::DEVADDR1: DEVADDR Mask */ + +#define UI2C_ADDRMSK0_ADDRMSK_Pos (0) /*!< UI2C_T::ADDRMSK0: ADDRMSK Position */ +#define UI2C_ADDRMSK0_ADDRMSK_Msk (0x3fful << UI2C_ADDRMSK0_ADDRMSK_Pos) /*!< UI2C_T::ADDRMSK0: ADDRMSK Mask */ + +#define UI2C_ADDRMSK1_ADDRMSK_Pos (0) /*!< UI2C_T::ADDRMSK1: ADDRMSK Position */ +#define UI2C_ADDRMSK1_ADDRMSK_Msk (0x3fful << UI2C_ADDRMSK1_ADDRMSK_Pos) /*!< UI2C_T::ADDRMSK1: ADDRMSK Mask */ + +#define UI2C_WKCTL_WKEN_Pos (0) /*!< UI2C_T::WKCTL: WKEN Position */ +#define UI2C_WKCTL_WKEN_Msk (0x1ul << UI2C_WKCTL_WKEN_Pos) /*!< UI2C_T::WKCTL: WKEN Mask */ + +#define UI2C_WKCTL_WKADDREN_Pos (1) /*!< UI2C_T::WKCTL: WKADDREN Position */ +#define UI2C_WKCTL_WKADDREN_Msk (0x1ul << UI2C_WKCTL_WKADDREN_Pos) /*!< UI2C_T::WKCTL: WKADDREN Mask */ + +#define UI2C_WKSTS_WKF_Pos (0) /*!< UI2C_T::WKSTS: WKF Position */ +#define UI2C_WKSTS_WKF_Msk (0x1ul << UI2C_WKSTS_WKF_Pos) /*!< UI2C_T::WKSTS: WKF Mask */ + +#define UI2C_PROTCTL_GCFUNC_Pos (0) /*!< UI2C_T::PROTCTL: GCFUNC Position */ +#define UI2C_PROTCTL_GCFUNC_Msk (0x1ul << UI2C_PROTCTL_GCFUNC_Pos) /*!< UI2C_T::PROTCTL: GCFUNC Mask */ + +#define UI2C_PROTCTL_AA_Pos (1) /*!< UI2C_T::PROTCTL: AA Position */ +#define UI2C_PROTCTL_AA_Msk (0x1ul << UI2C_PROTCTL_AA_Pos) /*!< UI2C_T::PROTCTL: AA Mask */ + +#define UI2C_PROTCTL_STO_Pos (2) /*!< UI2C_T::PROTCTL: STO Position */ +#define UI2C_PROTCTL_STO_Msk (0x1ul << UI2C_PROTCTL_STO_Pos) /*!< UI2C_T::PROTCTL: STO Mask */ + +#define UI2C_PROTCTL_STA_Pos (3) /*!< UI2C_T::PROTCTL: STA Position */ +#define UI2C_PROTCTL_STA_Msk (0x1ul << UI2C_PROTCTL_STA_Pos) /*!< UI2C_T::PROTCTL: STA Mask */ + +#define UI2C_PROTCTL_ADDR10EN_Pos (4) /*!< UI2C_T::PROTCTL: ADDR10EN Position */ +#define UI2C_PROTCTL_ADDR10EN_Msk (0x1ul << UI2C_PROTCTL_ADDR10EN_Pos) /*!< UI2C_T::PROTCTL: ADDR10EN Mask */ + +#define UI2C_PROTCTL_PTRG_Pos (5) /*!< UI2C_T::PROTCTL: PTRG Position */ +#define UI2C_PROTCTL_PTRG_Msk (0x1ul << UI2C_PROTCTL_PTRG_Pos) /*!< UI2C_T::PROTCTL: PTRG Mask */ + +#define UI2C_PROTCTL_SCLOUTEN_Pos (8) /*!< UI2C_T::PROTCTL: SCLOUTEN Position */ +#define UI2C_PROTCTL_SCLOUTEN_Msk (0x1ul << UI2C_PROTCTL_SCLOUTEN_Pos) /*!< UI2C_T::PROTCTL: SCLOUTEN Mask */ + +#define UI2C_PROTCTL_MONEN_Pos (9) /*!< UI2C_T::PROTCTL: MONEN Position */ +#define UI2C_PROTCTL_MONEN_Msk (0x1ul << UI2C_PROTCTL_MONEN_Pos) /*!< UI2C_T::PROTCTL: MONEN Mask */ + +#define UI2C_PROTCTL_TOCNT_Pos (16) /*!< UI2C_T::PROTCTL: TOCNT Position */ +#define UI2C_PROTCTL_TOCNT_Msk (0x3fful << UI2C_PROTCTL_TOCNT_Pos) /*!< UI2C_T::PROTCTL: TOCNT Mask */ + +#define UI2C_PROTCTL_PROTEN_Pos (31) /*!< UI2C_T::PROTCTL: PROTEN Position */ +#define UI2C_PROTCTL_PROTEN_Msk (0x1ul << UI2C_PROTCTL_PROTEN_Pos) /*!< UI2C_T::PROTCTL: PROTEN Mask */ + +#define UI2C_PROTIEN_TOIEN_Pos (0) /*!< UI2C_T::PROTIEN: TOIEN Position */ +#define UI2C_PROTIEN_TOIEN_Msk (0x1ul << UI2C_PROTIEN_TOIEN_Pos) /*!< UI2C_T::PROTIEN: TOIEN Mask */ + +#define UI2C_PROTIEN_STARIEN_Pos (1) /*!< UI2C_T::PROTIEN: STARIEN Position */ +#define UI2C_PROTIEN_STARIEN_Msk (0x1ul << UI2C_PROTIEN_STARIEN_Pos) /*!< UI2C_T::PROTIEN: STARIEN Mask */ + +#define UI2C_PROTIEN_STORIEN_Pos (2) /*!< UI2C_T::PROTIEN: STORIEN Position */ +#define UI2C_PROTIEN_STORIEN_Msk (0x1ul << UI2C_PROTIEN_STORIEN_Pos) /*!< UI2C_T::PROTIEN: STORIEN Mask */ + +#define UI2C_PROTIEN_NACKIEN_Pos (3) /*!< UI2C_T::PROTIEN: NACKIEN Position */ +#define UI2C_PROTIEN_NACKIEN_Msk (0x1ul << UI2C_PROTIEN_NACKIEN_Pos) /*!< UI2C_T::PROTIEN: NACKIEN Mask */ + +#define UI2C_PROTIEN_ARBLOIEN_Pos (4) /*!< UI2C_T::PROTIEN: ARBLOIEN Position */ +#define UI2C_PROTIEN_ARBLOIEN_Msk (0x1ul << UI2C_PROTIEN_ARBLOIEN_Pos) /*!< UI2C_T::PROTIEN: ARBLOIEN Mask */ + +#define UI2C_PROTIEN_ERRIEN_Pos (5) /*!< UI2C_T::PROTIEN: ERRIEN Position */ +#define UI2C_PROTIEN_ERRIEN_Msk (0x1ul << UI2C_PROTIEN_ERRIEN_Pos) /*!< UI2C_T::PROTIEN: ERRIEN Mask */ + +#define UI2C_PROTIEN_ACKIEN_Pos (6) /*!< UI2C_T::PROTIEN: ACKIEN Position */ +#define UI2C_PROTIEN_ACKIEN_Msk (0x1ul << UI2C_PROTIEN_ACKIEN_Pos) /*!< UI2C_T::PROTIEN: ACKIEN Mask */ + +#define UI2C_PROTSTS_TOIF_Pos (5) /*!< UI2C_T::PROTSTS: TOIF Position */ +#define UI2C_PROTSTS_TOIF_Msk (0x1ul << UI2C_PROTSTS_TOIF_Pos) /*!< UI2C_T::PROTSTS: TOIF Mask */ + +#define UI2C_PROTSTS_ONBUSY_Pos (6) /*!< UI2C_T::PROTSTS: ONBUSY Position */ +#define UI2C_PROTSTS_ONBUSY_Msk (0x1ul << UI2C_PROTSTS_ONBUSY_Pos) /*!< UI2C_T::PROTSTS: ONBUSY Mask */ + +#define UI2C_PROTSTS_STARIF_Pos (8) /*!< UI2C_T::PROTSTS: STARIF Position */ +#define UI2C_PROTSTS_STARIF_Msk (0x1ul << UI2C_PROTSTS_STARIF_Pos) /*!< UI2C_T::PROTSTS: STARIF Mask */ + +#define UI2C_PROTSTS_STORIF_Pos (9) /*!< UI2C_T::PROTSTS: STORIF Position */ +#define UI2C_PROTSTS_STORIF_Msk (0x1ul << UI2C_PROTSTS_STORIF_Pos) /*!< UI2C_T::PROTSTS: STORIF Mask */ + +#define UI2C_PROTSTS_NACKIF_Pos (10) /*!< UI2C_T::PROTSTS: NACKIF Position */ +#define UI2C_PROTSTS_NACKIF_Msk (0x1ul << UI2C_PROTSTS_NACKIF_Pos) /*!< UI2C_T::PROTSTS: NACKIF Mask */ + +#define UI2C_PROTSTS_ARBLOIF_Pos (11) /*!< UI2C_T::PROTSTS: ARBLOIF Position */ +#define UI2C_PROTSTS_ARBLOIF_Msk (0x1ul << UI2C_PROTSTS_ARBLOIF_Pos) /*!< UI2C_T::PROTSTS: ARBLOIF Mask */ + +#define UI2C_PROTSTS_ERRIF_Pos (12) /*!< UI2C_T::PROTSTS: ERRIF Position */ +#define UI2C_PROTSTS_ERRIF_Msk (0x1ul << UI2C_PROTSTS_ERRIF_Pos) /*!< UI2C_T::PROTSTS: ERRIF Mask */ + +#define UI2C_PROTSTS_ACKIF_Pos (13) /*!< UI2C_T::PROTSTS: ACKIF Position */ +#define UI2C_PROTSTS_ACKIF_Msk (0x1ul << UI2C_PROTSTS_ACKIF_Pos) /*!< UI2C_T::PROTSTS: ACKIF Mask */ + +#define UI2C_PROTSTS_SLASEL_Pos (14) /*!< UI2C_T::PROTSTS: SLASEL Position */ +#define UI2C_PROTSTS_SLASEL_Msk (0x1ul << UI2C_PROTSTS_SLASEL_Pos) /*!< UI2C_T::PROTSTS: SLASEL Mask */ + +#define UI2C_PROTSTS_SLAREAD_Pos (15) /*!< UI2C_T::PROTSTS: SLAREAD Position */ +#define UI2C_PROTSTS_SLAREAD_Msk (0x1ul << UI2C_PROTSTS_SLAREAD_Pos) /*!< UI2C_T::PROTSTS: SLAREAD Mask */ + +#define UI2C_PROTSTS_WKAKDONE_Pos (16) /*!< UI2C_T::PROTSTS: WKAKDONE Position */ +#define UI2C_PROTSTS_WKAKDONE_Msk (0x1ul << UI2C_PROTSTS_WKAKDONE_Pos) /*!< UI2C_T::PROTSTS: WKAKDONE Mask */ + +#define UI2C_PROTSTS_WRSTSWK_Pos (17) /*!< UI2C_T::PROTSTS: WRSTSWK Position */ +#define UI2C_PROTSTS_WRSTSWK_Msk (0x1ul << UI2C_PROTSTS_WRSTSWK_Pos) /*!< UI2C_T::PROTSTS: WRSTSWK Mask */ + +#define UI2C_PROTSTS_BUSHANG_Pos (18) /*!< UI2C_T::PROTSTS: BUSHANG Position */ +#define UI2C_PROTSTS_BUSHANG_Msk (0x1ul << UI2C_PROTSTS_BUSHANG_Pos) /*!< UI2C_T::PROTSTS: BUSHANG Mask */ + +#define UI2C_PROTSTS_ERRARBLO_Pos (19) /*!< UI2C_T::PROTSTS: ERRARBLO Position */ +#define UI2C_PROTSTS_ERRARBLO_Msk (0x1ul << UI2C_PROTSTS_ERRARBLO_Pos) /*!< UI2C_T::PROTSTS: ERRARBLO Mask */ + +#define UI2C_ADMAT_ADMAT0_Pos (0) /*!< UI2C_T::ADMAT: ADMAT0 Position */ +#define UI2C_ADMAT_ADMAT0_Msk (0x1ul << UI2C_ADMAT_ADMAT0_Pos) /*!< UI2C_T::ADMAT: ADMAT0 Mask */ + +#define UI2C_ADMAT_ADMAT1_Pos (1) /*!< UI2C_T::ADMAT: ADMAT1 Position */ +#define UI2C_ADMAT_ADMAT1_Msk (0x1ul << UI2C_ADMAT_ADMAT1_Pos) /*!< UI2C_T::ADMAT: ADMAT1 Mask */ + +#define UI2C_TMCTL_STCTL_Pos (0) /*!< UI2C_T::TMCTL: STCTL Position */ +#define UI2C_TMCTL_STCTL_Msk (0x1fful << UI2C_TMCTL_STCTL_Pos) /*!< UI2C_T::TMCTL: STCTL Mask */ + +#define UI2C_TMCTL_HTCTL_Pos (16) /*!< UI2C_T::TMCTL: HTCTL Position */ +#define UI2C_TMCTL_HTCTL_Msk (0x1fful << UI2C_TMCTL_HTCTL_Pos) /*!< UI2C_T::TMCTL: HTCTL Mask */ + +/**@}*/ /* UI2C_CONST */ +/**@}*/ /* end of UI2C register group */ + + +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __UI2C_REG_H__ */ \ No newline at end of file diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/usbd_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/usbd_reg.h new file mode 100644 index 00000000000..49f925e652f --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/usbd_reg.h @@ -0,0 +1,650 @@ +/**************************************************************************//** + * @file usbd_reg.h + * @version V1.00 + * @brief USBD register definition header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __USBD_REG_H__ +#define __USBD_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup USBD USB Device Controller (USBD) + Memory Mapped Structure for USBD Controller +@{ */ + +typedef struct +{ + /** + * @var USBD_EP_T::BUFSEG + * Offset: 0x000 Endpoint n Buffer Segmentation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:3] |BUFSEG |Endpoint Buffer Segmentation + * | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is + * | | |USBD_SRAM address + { BUFSEG, 3'b000} + * | | |Where the USBD_SRAM address = USBD_BA+0x100h. + * | | |Refer to the section 1.1.5.7 for the endpoint SRAM structure and its description. + * @var USBD_EP_T::MXPLD + * Offset: 0x004 Endpoint n Maximal Payload Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |MXPLD |Maximal Payload + * | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token) + * | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token. + * | | |(1) When the register is written by CPU, + * | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready. + * | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host. + * | | |(2) When the register is read by CPU, + * | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host + * | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host. + * | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived. + * @var USBD_EP_T::CFG + * Offset: 0x008 Endpoint n Configuration Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |EPNUM |Endpoint Number + * | | |These bits are used to define the endpoint number of the current endpoint + * |[4] |ISOCH |Isochronous Endpoint + * | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake. + * | | |0 = No Isochronous endpoint. + * | | |1 = Isochronous endpoint. + * |[6:5] |STATE |Endpoint STATE + * | | |00 = Endpoint is Disabled. + * | | |01 = Out endpoint. + * | | |10 = IN endpoint. + * | | |11 = Undefined. + * |[7] |DSQSYNC |Data Sequence Synchronization + * | | |0 = DATA0 PID. + * | | |1 = DATA1 PID. + * | | |Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction + * | | |hardware will toggle automatically in IN token base on the bit. + * |[9] |CSTALL |Clear STALL Response + * | | |0 = Disable the device to clear the STALL handshake in setup stage. + * | | |1 = Clear the device to response STALL handshake in setup stage. + * @var USBD_EP_T::CFGP + * Offset: 0x00C Endpoint n Set Stall and Clear In/Out Ready Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CLRRDY |Clear Ready + * | | |When the USBD_MXPLDx register is set by user, it means that the endpoint is ready to transmit or receive data + * | | |If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is auto clear to 0. + * | | |For IN token, write '1' to clear the IN token had ready to transmit the data to USB. + * | | |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB. + * | | |This bit is write 1 only and is always 0 when it is read back. + * |[1] |SSTALL |Set STALL + * | | |0 = Disable the device to response STALL. + * | | |1 = Set the device to respond STALL automatically. + */ + __IO uint32_t BUFSEG; /*!< [0x0000] Endpoint n Buffer Segmentation Register */ + __IO uint32_t MXPLD; /*!< [0x0004] Endpoint n Maximal Payload Register */ + __IO uint32_t CFG; /*!< [0x0008] Endpoint n Configuration Register */ + __IO uint32_t CFGP; /*!< [0x000c] Endpoint n Set Stall and Clear In/Out Ready Control Register */ + +} USBD_EP_T; + +typedef struct +{ + + + /** + * @var USBD_T::INTEN + * Offset: 0x00 USB Device Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSIEN |Bus Event Interrupt Enable Bit + * | | |0 = BUS event interrupt Disabled. + * | | |1 = BUS event interrupt Enabled. + * |[1] |USBIEN |USB Event Interrupt Enable Bit + * | | |0 = USB event interrupt Disabled. + * | | |1 = USB event interrupt Enabled. + * |[2] |VBDETIEN |VBUS Detection Interrupt Enable Bit + * | | |0 = VBUS detection Interrupt Disabled. + * | | |1 = VBUS detection Interrupt Enabled. + * |[3] |NEVWKIEN |USB No-event-wake-up Interrupt Enable Bit + * | | |0 = No-event-wake-up Interrupt Disabled. + * | | |1 = No-event-wake-up Interrupt Enabled. + * |[4] |SOFIEN |Start of Frame Interrupt Enable Bit + * | | |0 = SOF Interrupt Disabled. + * | | |1 = SOF Interrupt Enabled. + * |[8] |WKEN |Wake-up Function Enable Bit + * | | |0 = USB wake-up function Disabled. + * | | |1 = USB wake-up function Enabled. + * |[15] |INNAKEN |Active NAK Function and Its Status in IN Token + * | | |0 = When device responds NAK after receiving IN token, IN NAK status will not be updated to USBD_EPSTS0 and USBD_EPSTS1register, so that the USB interrupt event will not be asserted. + * | | |1 = IN NAK status will be updated to USBD_EPSTS0 and USBD_EPSTS1 register and the USB interrupt event will be asserted, when the device responds NAK after receiving IN token. + * @var USBD_T::INTSTS + * Offset: 0x04 USB Device Interrupt Event Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSIF |BUS Interrupt Status + * | | |The BUS event means that there is one of the suspense or the resume function in the bus. + * | | |0 = No BUS event occurred. + * | | |1 = Bus event occurred; check USBD_ATTR[3:0] to know which kind of bus event was occurred, cleared by write 1 to USBD_INTSTS[0]. + * |[1] |USBIF |USB Event Interrupt Status + * | | |The USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus. + * | | |0 = No USB event occurred. + * | | |1 = USB event occurred, check EPSTS0~11[3:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[1] or EPSTS0~11 and SETUP (USBD_INTSTS[31]). + * |[2] |VBDETIF |VBUS Detection Interrupt Status + * | | |0 = There is not attached/detached event in the USB. + * | | |1 = There is attached/detached event in the USB bus and it is cleared by write 1 to USBD_INTSTS[2]. + * |[3] |NEVWKIF |No-event-wake-up Interrupt Status + * | | |0 = NEVWK event does not occur. + * | | |1 = No-event-wake-up event occurred, cleared by write 1 to USBD_INTSTS[3]. + * |[4] |SOFIF |Start of Frame Interrupt Status + * | | |0 = SOF event does not occur. + * | | |1 = SOF event occurred, cleared by write 1 to USBD_INTSTS[4]. + * |[16] |EPEVT0 |Endpoint 0's USB Event Status + * | | |0 = No event occurred in endpoint 0. + * | | |1 = USB event occurred on Endpoint 0, check USBD_EPSTS0[3:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[16] or USBD_INTSTS[1]. + * |[17] |EPEVT1 |Endpoint 1's USB Event Status + * | | |0 = No event occurred in endpoint 1. + * | | |1 = USB event occurred on Endpoint 1, check USBD_EPSTS0[7:4] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[17] or USBD_INTSTS[1]. + * |[18] |EPEVT2 |Endpoint 2's USB Event Status + * | | |0 = No event occurred in endpoint 2. + * | | |1 = USB event occurred on Endpoint 2, check USBD_EPSTS0[11:8] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[18] or USBD_INTSTS[1]. + * |[19] |EPEVT3 |Endpoint 3's USB Event Status + * | | |0 = No event occurred in endpoint 3. + * | | |1 = USB event occurred on Endpoint 3, check USBD_EPSTS0[15:12] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[19] or USBD_INTSTS[1]. + * |[20] |EPEVT4 |Endpoint 4's USB Event Status + * | | |0 = No event occurred in endpoint 4. + * | | |1 = USB event occurred on Endpoint 4, check USBD_EPSTS0[19:16] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[20] or USBD_INTSTS[1]. + * |[21] |EPEVT5 |Endpoint 5's USB Event Status + * | | |0 = No event occurred in endpoint 5. + * | | |1 = USB event occurred on Endpoint 5, check USBD_EPSTS0[23:20] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[21] or USBD_INTSTS[1]. + * |[22] |EPEVT6 |Endpoint 6's USB Event Status + * | | |0 = No event occurred in endpoint 6. + * | | |1 = USB event occurred on Endpoint 6, check USBD_EPSTS0[27:24] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[22] or USBD_INTSTS[1]. + * |[23] |EPEVT7 |Endpoint 7's USB Event Status + * | | |0 = No event occurred in endpoint 7. + * | | |1 = USB event occurred on Endpoint 7, check USBD_EPSTS0[31:28] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[23] or USBD_INTSTS[1]. + * |[24] |EPEVT8 |Endpoint 8's USB Event Status + * | | |0 = No event occurred in endpoint 8. + * | | |1 = USB event occurred on Endpoint 8, check USBD_EPSTS1[3 :0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[24] or USBD_INTSTS[1]. + * |[25] |EPEVT9 |Endpoint 9's USB Event Status + * | | |0 = No event occurred in endpoint 9. + * | | |1 = USB event occurred on Endpoint 9, check USBD_EPSTS1[7 :4] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[25] or USBD_INTSTS[1]. + * |[26] |EPEVT10 |Endpoint 10's USB Event Status + * | | |0 = No event occurred in endpoint 10. + * | | |1 = USB event occurred on Endpoint 10, check USBD_EPSTS1[11 :8] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[26] or USBD_INTSTS[1]. + * |[27] |EPEVT11 |Endpoint 11's USB Event Status + * | | |0 = No event occurred in endpoint 11. + * | | |1 = USB event occurred on Endpoint 11, check USBD_EPSTS1[ 15:12] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[27] or USBD_INTSTS[1]. + * |[31] |SETUP |Setup Event Status + * | | |0 = No Setup event. + * | | |1 = Setup event occurred, cleared by write 1 to USBD_INTSTS[31]. + * @var USBD_T::FADDR + * Offset: 0x08 USB Device Function Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |FADDR |USB Device Function Address + * @var USBD_T::EPSTS + * Offset: 0x0C USB Device Endpoint Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7] |OV |Overrun + * | | |It indicates that the received data is over the maximum payload number or not. + * | | |0 = No overrun. + * | | |1 = Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 Bytes. + * @var USBD_T::ATTR + * Offset: 0x10 USB Device Bus Status and Attribution Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |USBRST |USB Reset Status + * | | |0 = Bus no reset. + * | | |1 = Bus reset when SE0 (single-ended 0) more than 2.5us. + * | | |Note: This bit is read only. + * |[1] |SUSPEND |Suspend Status + * | | |0 = Bus no suspend. + * | | |1 = Bus idle more than 3ms, either cable is plugged off or host is sleeping. + * | | |Note: This bit is read only. + * |[2] |RESUME |Resume Status + * | | |0 = No bus resume. + * | | |1 = Resume from suspend. + * | | |Note: This bit is read only. + * |[3] |TOUT |Time-out Status + * | | |0 = No time-out. + * | | |1 = No Bus response more than 18 bits time (1 / 12MHz * 18 = 1.5 us). + * | | |Note: This bit is read only. + * |[4] |PHYEN |PHY Transceiver Function Enable Bit + * | | |0 = PHY transceiver function Disabled. + * | | |1 = PHY transceiver function Enabled. + * |[5] |RWAKEUP |Remote Wake-up + * | | |0 = Release the USB bus from K state. + * | | |1 = Force USB bus to K (USB_D+ low, USB_D-: high) state, used for remote wake-up. + * |[7] |USBEN |USB Controller Enable Bit + * | | |0 = USB Controller Disabled. + * | | |1 = USB Controller Enabled. + * |[8] |DPPUEN |Pull-up Resistor on USB_DP Enable Bit + * | | |0 = Pull-up resistor in USB_D+ bus Disabled. + * | | |1 = Pull-up resistor in USB_D+ bus Active. + * |[9] |PWRDN |Power-down PHY Transceiver, Low Active + * | | |0 = Power-down related circuit of PHY transceiver. + * | | |1 = Turn-on related circuit of PHY transceiver. + * |[10] |BYTEM |CPU Access USB SRAM Size Mode Selection + * | | |0 = Word mode: The size of the transfer from CPU to USB SRAM can be Word only. + * | | |1 = Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only. + * |[11] |LPMACK |LPM Token Acknowledge Enable Bit + * | | |The NYET/ACK will be returned only on a successful LPM transaction if no errors in both the EXT token and the LPM token and a valid bLinkState = 0001 (L1) is received, else ERROR and STALL will be returned automatically, respectively. + * | | |0= the valid LPM Token will be NYET. + * | | |1= the valid LPM Token will be ACK. + * |[12] |L1SUSPEND |LPM L1 Suspend + * | | |0 = Bus no L1 state suspend. + * | | |1 = This bit is set by the hardware when LPM command to enter the L1 state is successfully received and acknowledged. + * | | |Note: This bit is read only. + * |[13] |L1RESUME |LPM L1 Resume + * | | |0 = Bus no LPM L1 state resume. + * | | |1 = LPM L1 state Resume from LPM L1 state suspend. + * | | |Note: This bit is read only. + * @var USBD_T::VBUSDET + * Offset: 0x14 USB Device VBUS Detection Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |VBUSDET |Device VBUS Detection + * | | |0 = Controller is not attached to the USB host. + * | | |1 = Controller is attached to the USB host. + * @var USBD_T::STBUFSEG + * Offset: 0x18 SETUP Token Buffer Segmentation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:3] |STBUFSEG |SETUP Token Buffer Segmentation + * | | |It is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is + * | | |USBD_SRAM address + {STBUFSEG, 3'b000} + * | | |Where the USBD_SRAM address = USBD_BA+0x100h. + * | | |Note: It is used for SETUP token only. + * @var USBD_T::EPSTS0 + * Offset: 0x20 USB Device Endpoint Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[03:00] |EPSTS0 |Endpoint 0 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[07:04] |EPSTS1 |Endpoint 1 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[11:08] |EPSTS2 |Endpoint 2 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[15:12] |EPSTS3 |Endpoint 3 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[19:16] |EPSTS4 |Endpoint 4 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[23:20] |EPSTS5 |Endpoint 5 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[27:24] |EPSTS6 |Endpoint 6 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[31:28] |EPSTS7 |Endpoint 7 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * @var USBD_T::EPSTS1 + * Offset: 0x24 USB Device Endpoint Status Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |EPSTS8 |Endpoint 8 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[7:4] |EPSTS9 |Endpoint 9 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[11:8] |EPSTS10 |Endpoint 10 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[15:12] |EPSTS11 |Endpoint 11 Status + * | | |These bits are used to indicate the current status of this endpoint + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0011 = Setup ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * @var USBD_T::LPMATTR + * Offset: 0x88 USB LPM Attribution Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |LPMLINKSTS|LPM Link State + * | | |These bits contain the bLinkState received with last ACK LPM Token + * |[7:4] |LPMBESL |LPM Best Effort Service Latency + * | | |These bits contain the BESL value received with last ACK LPM Token + * |[8] |LPMRWAKUP |LPM Remote Wakeup + * | | |This bit contains the bRemoteWake value received with last ACK LPM Token + * @var USBD_T::FN + * Offset: 0x8C USB Frame number Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |FN |Frame Number + * | | |These bits contain the 11-bits frame number in the last received SOF packet. + * @var USBD_T::SE0 + * Offset: 0x90 USB Device Drive SE0 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SE0 |Drive Single Ended Zero in USB Bus + * | | |The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low. + * | | |0 = Normal operation. + * | | |1 = Force USB PHY transceiver to drive SE0. + */ + __IO uint32_t INTEN; /*!< [0x0000] USB Device Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x0004] USB Device Interrupt Event Status Register */ + __IO uint32_t FADDR; /*!< [0x0008] USB Device Function Address Register */ + __I uint32_t EPSTS; /*!< [0x000c] USB Device Endpoint Status Register */ + __IO uint32_t ATTR; /*!< [0x0010] USB Device Bus Status and Attribution Register */ + __I uint32_t VBUSDET; /*!< [0x0014] USB Device VBUS Detection Register */ + __IO uint32_t STBUFSEG; /*!< [0x0018] SETUP Token Buffer Segmentation Register */ + /* @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE0[1]; + /* @endcond //HIDDEN_SYMBOLS */ + __I uint32_t EPSTS0; /*!< [0x0020] USB Device Endpoint Status Register 0 */ + __I uint32_t EPSTS1; /*!< [0x0024] USB Device Endpoint Status Register 1 */ + /* @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE1[24]; + /* @endcond //HIDDEN_SYMBOLS */ + __I uint32_t LPMATTR; /*!< [0x0088] USB LPM Attribution Register */ + __I uint32_t FN; /*!< [0x008c] USB Frame number Register */ + __IO uint32_t SE0; /*!< [0x0090] USB Device Drive SE0 Control Register */ + /* @cond HIDDEN_SYMBOLS */ + __I uint32_t RESERVE2[283]; + /* @endcond //HIDDEN_SYMBOLS */ + USBD_EP_T EP[12]; /*!< [0x0500~0x5BC] USB Device Endpoints(0~11) */ +} USBD_T; + +/** + @addtogroup USBD_CONST USBD Bit Field Definition + Constant Definitions for USBD Controller +@{ */ + +#define USBD_INTEN_BUSIEN_Pos (0) /*!< USBD_T::INTEN: BUSIEN Position */ +#define USBD_INTEN_BUSIEN_Msk (0x1ul << USBD_INTEN_BUSIEN_Pos) /*!< USBD_T::INTEN: BUSIEN Mask */ + +#define USBD_INTEN_USBIEN_Pos (1) /*!< USBD_T::INTEN: USBIEN Position */ +#define USBD_INTEN_USBIEN_Msk (0x1ul << USBD_INTEN_USBIEN_Pos) /*!< USBD_T::INTEN: USBIEN Mask */ + +#define USBD_INTEN_VBDETIEN_Pos (2) /*!< USBD_T::INTEN: VBDETIEN Position */ +#define USBD_INTEN_VBDETIEN_Msk (0x1ul << USBD_INTEN_VBDETIEN_Pos) /*!< USBD_T::INTEN: VBDETIEN Mask */ + +#define USBD_INTEN_NEVWKIEN_Pos (3) /*!< USBD_T::INTEN: NEVWKIEN Position */ +#define USBD_INTEN_NEVWKIEN_Msk (0x1ul << USBD_INTEN_NEVWKIEN_Pos) /*!< USBD_T::INTEN: NEVWKIEN Mask */ + +#define USBD_INTEN_SOFIEN_Pos (4) /*!< USBD_T::INTEN: SOFIEN Position */ +#define USBD_INTEN_SOFIEN_Msk (0x1ul << USBD_INTEN_SOFIEN_Pos) /*!< USBD_T::INTEN: SOFIEN Mask */ + +#define USBD_INTEN_WKEN_Pos (8) /*!< USBD_T::INTEN: WKEN Position */ +#define USBD_INTEN_WKEN_Msk (0x1ul << USBD_INTEN_WKEN_Pos) /*!< USBD_T::INTEN: WKEN Mask */ + +#define USBD_INTEN_INNAKEN_Pos (15) /*!< USBD_T::INTEN: INNAKEN Position */ +#define USBD_INTEN_INNAKEN_Msk (0x1ul << USBD_INTEN_INNAKEN_Pos) /*!< USBD_T::INTEN: INNAKEN Mask */ + +#define USBD_INTSTS_BUSIF_Pos (0) /*!< USBD_T::INTSTS: BUSIF Position */ +#define USBD_INTSTS_BUSIF_Msk (0x1ul << USBD_INTSTS_BUSIF_Pos) /*!< USBD_T::INTSTS: BUSIF Mask */ + +#define USBD_INTSTS_USBIF_Pos (1) /*!< USBD_T::INTSTS: USBIF Position */ +#define USBD_INTSTS_USBIF_Msk (0x1ul << USBD_INTSTS_USBIF_Pos) /*!< USBD_T::INTSTS: USBIF Mask */ + +#define USBD_INTSTS_VBDETIF_Pos (2) /*!< USBD_T::INTSTS: VBDETIF Position */ +#define USBD_INTSTS_VBDETIF_Msk (0x1ul << USBD_INTSTS_VBDETIF_Pos) /*!< USBD_T::INTSTS: VBDETIF Mask */ + +#define USBD_INTSTS_NEVWKIF_Pos (3) /*!< USBD_T::INTSTS: NEVWKIF Position */ +#define USBD_INTSTS_NEVWKIF_Msk (0x1ul << USBD_INTSTS_NEVWKIF_Pos) /*!< USBD_T::INTSTS: NEVWKIF Mask */ + +#define USBD_INTSTS_SOFIF_Pos (4) /*!< USBD_T::INTSTS: SOFIF Position */ +#define USBD_INTSTS_SOFIF_Msk (0x1ul << USBD_INTSTS_SOFIF_Pos) /*!< USBD_T::INTSTS: SOFIF Mask */ + +#define USBD_INTSTS_EPEVT0_Pos (16) /*!< USBD_T::INTSTS: EPEVT0 Position */ +#define USBD_INTSTS_EPEVT0_Msk (0x1ul << USBD_INTSTS_EPEVT0_Pos) /*!< USBD_T::INTSTS: EPEVT0 Mask */ + +#define USBD_INTSTS_EPEVT1_Pos (17) /*!< USBD_T::INTSTS: EPEVT1 Position */ +#define USBD_INTSTS_EPEVT1_Msk (0x1ul << USBD_INTSTS_EPEVT1_Pos) /*!< USBD_T::INTSTS: EPEVT1 Mask */ + +#define USBD_INTSTS_EPEVT2_Pos (18) /*!< USBD_T::INTSTS: EPEVT2 Position */ +#define USBD_INTSTS_EPEVT2_Msk (0x1ul << USBD_INTSTS_EPEVT2_Pos) /*!< USBD_T::INTSTS: EPEVT2 Mask */ + +#define USBD_INTSTS_EPEVT3_Pos (19) /*!< USBD_T::INTSTS: EPEVT3 Position */ +#define USBD_INTSTS_EPEVT3_Msk (0x1ul << USBD_INTSTS_EPEVT3_Pos) /*!< USBD_T::INTSTS: EPEVT3 Mask */ + +#define USBD_INTSTS_EPEVT4_Pos (20) /*!< USBD_T::INTSTS: EPEVT4 Position */ +#define USBD_INTSTS_EPEVT4_Msk (0x1ul << USBD_INTSTS_EPEVT4_Pos) /*!< USBD_T::INTSTS: EPEVT4 Mask */ + +#define USBD_INTSTS_EPEVT5_Pos (21) /*!< USBD_T::INTSTS: EPEVT5 Position */ +#define USBD_INTSTS_EPEVT5_Msk (0x1ul << USBD_INTSTS_EPEVT5_Pos) /*!< USBD_T::INTSTS: EPEVT5 Mask */ + +#define USBD_INTSTS_EPEVT6_Pos (22) /*!< USBD_T::INTSTS: EPEVT6 Position */ +#define USBD_INTSTS_EPEVT6_Msk (0x1ul << USBD_INTSTS_EPEVT6_Pos) /*!< USBD_T::INTSTS: EPEVT6 Mask */ + +#define USBD_INTSTS_EPEVT7_Pos (23) /*!< USBD_T::INTSTS: EPEVT7 Position */ +#define USBD_INTSTS_EPEVT7_Msk (0x1ul << USBD_INTSTS_EPEVT7_Pos) /*!< USBD_T::INTSTS: EPEVT7 Mask */ + +#define USBD_INTSTS_EPEVT8_Pos (24) /*!< USBD_T::INTSTS: EPEVT8 Position */ +#define USBD_INTSTS_EPEVT8_Msk (0x1ul << USBD_INTSTS_EPEVT8_Pos) /*!< USBD_T::INTSTS: EPEVT8 Mask */ + +#define USBD_INTSTS_EPEVT9_Pos (25) /*!< USBD_T::INTSTS: EPEVT9 Position */ +#define USBD_INTSTS_EPEVT9_Msk (0x1ul << USBD_INTSTS_EPEVT9_Pos) /*!< USBD_T::INTSTS: EPEVT9 Mask */ + +#define USBD_INTSTS_EPEVT10_Pos (26) /*!< USBD_T::INTSTS: EPEVT10 Position */ +#define USBD_INTSTS_EPEVT10_Msk (0x1ul << USBD_INTSTS_EPEVT10_Pos) /*!< USBD_T::INTSTS: EPEVT10 Mask */ + +#define USBD_INTSTS_EPEVT11_Pos (27) /*!< USBD_T::INTSTS: EPEVT11 Position */ +#define USBD_INTSTS_EPEVT11_Msk (0x1ul << USBD_INTSTS_EPEVT11_Pos) /*!< USBD_T::INTSTS: EPEVT11 Mask */ + +#define USBD_INTSTS_SETUP_Pos (31) /*!< USBD_T::INTSTS: SETUP Position */ +#define USBD_INTSTS_SETUP_Msk (0x1ul << USBD_INTSTS_SETUP_Pos) /*!< USBD_T::INTSTS: SETUP Mask */ + +#define USBD_FADDR_FADDR_Pos (0) /*!< USBD_T::FADDR: FADDR Position */ +#define USBD_FADDR_FADDR_Msk (0x7ful << USBD_FADDR_FADDR_Pos) /*!< USBD_T::FADDR: FADDR Mask */ + +#define USBD_EPSTS_OV_Pos (7) /*!< USBD_T::EPSTS: OV Position */ +#define USBD_EPSTS_OV_Msk (0x1ul << USBD_EPSTS_OV_Pos) /*!< USBD_T::EPSTS: OV Mask */ + +#define USBD_ATTR_USBRST_Pos (0) /*!< USBD_T::ATTR: USBRST Position */ +#define USBD_ATTR_USBRST_Msk (0x1ul << USBD_ATTR_USBRST_Pos) /*!< USBD_T::ATTR: USBRST Mask */ + +#define USBD_ATTR_SUSPEND_Pos (1) /*!< USBD_T::ATTR: SUSPEND Position */ +#define USBD_ATTR_SUSPEND_Msk (0x1ul << USBD_ATTR_SUSPEND_Pos) /*!< USBD_T::ATTR: SUSPEND Mask */ + +#define USBD_ATTR_RESUME_Pos (2) /*!< USBD_T::ATTR: RESUME Position */ +#define USBD_ATTR_RESUME_Msk (0x1ul << USBD_ATTR_RESUME_Pos) /*!< USBD_T::ATTR: RESUME Mask */ + +#define USBD_ATTR_TOUT_Pos (3) /*!< USBD_T::ATTR: TOUT Position */ +#define USBD_ATTR_TOUT_Msk (0x1ul << USBD_ATTR_TOUT_Pos) /*!< USBD_T::ATTR: TOUT Mask */ + +#define USBD_ATTR_PHYEN_Pos (4) /*!< USBD_T::ATTR: PHYEN Position */ +#define USBD_ATTR_PHYEN_Msk (0x1ul << USBD_ATTR_PHYEN_Pos) /*!< USBD_T::ATTR: PHYEN Mask */ + +#define USBD_ATTR_RWAKEUP_Pos (5) /*!< USBD_T::ATTR: RWAKEUP Position */ +#define USBD_ATTR_RWAKEUP_Msk (0x1ul << USBD_ATTR_RWAKEUP_Pos) /*!< USBD_T::ATTR: RWAKEUP Mask */ + +#define USBD_ATTR_USBEN_Pos (7) /*!< USBD_T::ATTR: USBEN Position */ +#define USBD_ATTR_USBEN_Msk (0x1ul << USBD_ATTR_USBEN_Pos) /*!< USBD_T::ATTR: USBEN Mask */ + +#define USBD_ATTR_DPPUEN_Pos (8) /*!< USBD_T::ATTR: DPPUEN Position */ +#define USBD_ATTR_DPPUEN_Msk (0x1ul << USBD_ATTR_DPPUEN_Pos) /*!< USBD_T::ATTR: DPPUEN Mask */ + +#define USBD_ATTR_PWRDN_Pos (9) /*!< USBD_T::ATTR: PWRDN Position */ +#define USBD_ATTR_PWRDN_Msk (0x1ul << USBD_ATTR_PWRDN_Pos) /*!< USBD_T::ATTR: PWRDN Mask */ + +#define USBD_ATTR_BYTEM_Pos (10) /*!< USBD_T::ATTR: BYTEM Position */ +#define USBD_ATTR_BYTEM_Msk (0x1ul << USBD_ATTR_BYTEM_Pos) /*!< USBD_T::ATTR: BYTEM Mask */ + +#define USBD_ATTR_LPMACK_Pos (11) /*!< USBD_T::ATTR: LPMACK Position */ +#define USBD_ATTR_LPMACK_Msk (0x1ul << USBD_ATTR_LPMACK_Pos) /*!< USBD_T::ATTR: LPMACK Mask */ + +#define USBD_ATTR_L1SUSPEND_Pos (12) /*!< USBD_T::ATTR: L1SUSPEND Position */ +#define USBD_ATTR_L1SUSPEND_Msk (0x1ul << USBD_ATTR_L1SUSPEND_Pos) /*!< USBD_T::ATTR: L1SUSPEND Mask */ + +#define USBD_ATTR_L1RESUME_Pos (13) /*!< USBD_T::ATTR: L1RESUME Position */ +#define USBD_ATTR_L1RESUME_Msk (0x1ul << USBD_ATTR_L1RESUME_Pos) /*!< USBD_T::ATTR: L1RESUME Mask */ + +#define USBD_VBUSDET_VBUSDET_Pos (0) /*!< USBD_T::VBUSDET: VBUSDET Position */ +#define USBD_VBUSDET_VBUSDET_Msk (0x1ul << USBD_VBUSDET_VBUSDET_Pos) /*!< USBD_T::VBUSDET: VBUSDET Mask */ + +#define USBD_STBUFSEG_STBUFSEG_Pos (3) /*!< USBD_T::STBUFSEG: STBUFSEG Position */ +#define USBD_STBUFSEG_STBUFSEG_Msk (0x3ful << USBD_STBUFSEG_STBUFSEG_Pos) /*!< USBD_T::STBUFSEG: STBUFSEG Mask */ + +#define USBD_EPSTS0_EPSTS0_Pos (0) /*!< USBD_T::EPSTS0: EPSTS0 Position */ +#define USBD_EPSTS0_EPSTS0_Msk (0xful << USBD_EPSTS0_EPSTS0_Pos) /*!< USBD_T::EPSTS0: EPSTS0 Mask */ + +#define USBD_EPSTS0_EPSTS1_Pos (4) /*!< USBD_T::EPSTS0: EPSTS1 Position */ +#define USBD_EPSTS0_EPSTS1_Msk (0xful << USBD_EPSTS0_EPSTS1_Pos) /*!< USBD_T::EPSTS0: EPSTS1 Mask */ + +#define USBD_EPSTS0_EPSTS2_Pos (8) /*!< USBD_T::EPSTS0: EPSTS2 Position */ +#define USBD_EPSTS0_EPSTS2_Msk (0xful << USBD_EPSTS0_EPSTS2_Pos) /*!< USBD_T::EPSTS0: EPSTS2 Mask */ + +#define USBD_EPSTS0_EPSTS3_Pos (12) /*!< USBD_T::EPSTS0: EPSTS3 Position */ +#define USBD_EPSTS0_EPSTS3_Msk (0xful << USBD_EPSTS0_EPSTS3_Pos) /*!< USBD_T::EPSTS0: EPSTS3 Mask */ + +#define USBD_EPSTS0_EPSTS4_Pos (16) /*!< USBD_T::EPSTS0: EPSTS4 Position */ +#define USBD_EPSTS0_EPSTS4_Msk (0xful << USBD_EPSTS0_EPSTS4_Pos) /*!< USBD_T::EPSTS0: EPSTS4 Mask */ + +#define USBD_EPSTS0_EPSTS5_Pos (20) /*!< USBD_T::EPSTS0: EPSTS5 Position */ +#define USBD_EPSTS0_EPSTS5_Msk (0xful << USBD_EPSTS0_EPSTS5_Pos) /*!< USBD_T::EPSTS0: EPSTS5 Mask */ + +#define USBD_EPSTS0_EPSTS6_Pos (24) /*!< USBD_T::EPSTS0: EPSTS6 Position */ +#define USBD_EPSTS0_EPSTS6_Msk (0xful << USBD_EPSTS0_EPSTS6_Pos) /*!< USBD_T::EPSTS0: EPSTS6 Mask */ + +#define USBD_EPSTS0_EPSTS7_Pos (28) /*!< USBD_T::EPSTS0: EPSTS7 Position */ +#define USBD_EPSTS0_EPSTS7_Msk (0xful << USBD_EPSTS0_EPSTS7_Pos) /*!< USBD_T::EPSTS0: EPSTS7 Mask */ + +#define USBD_EPSTS1_EPSTS8_Pos (0) /*!< USBD_T::EPSTS1: EPSTS8 Position */ +#define USBD_EPSTS1_EPSTS8_Msk (0xful << USBD_EPSTS1_EPSTS8_Pos) /*!< USBD_T::EPSTS1: EPSTS8 Mask */ + +#define USBD_EPSTS1_EPSTS9_Pos (4) /*!< USBD_T::EPSTS1: EPSTS9 Position */ +#define USBD_EPSTS1_EPSTS9_Msk (0xful << USBD_EPSTS1_EPSTS9_Pos) /*!< USBD_T::EPSTS1: EPSTS9 Mask */ + +#define USBD_EPSTS1_EPSTS10_Pos (8) /*!< USBD_T::EPSTS1: EPSTS10 Position */ +#define USBD_EPSTS1_EPSTS10_Msk (0xful << USBD_EPSTS1_EPSTS10_Pos) /*!< USBD_T::EPSTS1: EPSTS10 Mask */ + +#define USBD_EPSTS1_EPSTS11_Pos (12) /*!< USBD_T::EPSTS1: EPSTS11 Position */ +#define USBD_EPSTS1_EPSTS11_Msk (0xful << USBD_EPSTS1_EPSTS11_Pos) /*!< USBD_T::EPSTS1: EPSTS11 Mask */ + +#define USBD_LPMATTR_LPMLINKSTS_Pos (0) /*!< USBD_T::LPMATTR: LPMLINKSTS Position */ +#define USBD_LPMATTR_LPMLINKSTS_Msk (0xful << USBD_LPMATTR_LPMLINKSTS_Pos) /*!< USBD_T::LPMATTR: LPMLINKSTS Mask */ + +#define USBD_LPMATTR_LPMBESL_Pos (4) /*!< USBD_T::LPMATTR: LPMBESL Position */ +#define USBD_LPMATTR_LPMBESL_Msk (0xful << USBD_LPMATTR_LPMBESL_Pos) /*!< USBD_T::LPMATTR: LPMBESL Mask */ + +#define USBD_LPMATTR_LPMRWAKUP_Pos (8) /*!< USBD_T::LPMATTR: LPMRWAKUP Position */ +#define USBD_LPMATTR_LPMRWAKUP_Msk (0x1ul << USBD_LPMATTR_LPMRWAKUP_Pos) /*!< USBD_T::LPMATTR: LPMRWAKUP Mask */ + +#define USBD_FN_FN_Pos (0) /*!< USBD_T::FN: FN Position */ +#define USBD_FN_FN_Msk (0x7fful << USBD_FN_FN_Pos) /*!< USBD_T::FN: FN Mask */ + +#define USBD_SE0_SE0_Pos (0) /*!< USBD_T::SE0: SE0 Position */ +#define USBD_SE0_SE0_Msk (0x1ul << USBD_SE0_SE0_Pos) /*!< USBD_T::SE0: SE0 Mask */ + +#define USBD_BUFSEG_BUFSEG_Pos (3) /*!< USBD_EP_T::BUFSEG: BUFSEG Position */ +#define USBD_BUFSEG_BUFSEG_Msk (0x3ful << USBD_BUFSEG_BUFSEG_Pos) /*!< USBD_EP_T::BUFSEG: BUFSEG Mask */ + +#define USBD_MXPLD_MXPLD_Pos (0) /*!< USBD_EP_T::MXPLD: MXPLD Position */ +#define USBD_MXPLD_MXPLD_Msk (0x1fful << USBD_MXPLD_MXPLD_Pos) /*!< USBD_EP_T::MXPLD: MXPLD Mask */ + +#define USBD_CFG_EPNUM_Pos (0) /*!< USBD_EP_T::CFG: EPNUM Position */ +#define USBD_CFG_EPNUM_Msk (0xful << USBD_CFG_EPNUM_Pos) /*!< USBD_EP_T::CFG: EPNUM Mask */ + +#define USBD_CFG_ISOCH_Pos (4) /*!< USBD_EP_T::CFG: ISOCH Position */ +#define USBD_CFG_ISOCH_Msk (0x1ul << USBD_CFG_ISOCH_Pos) /*!< USBD_EP_T::CFG: ISOCH Mask */ + +#define USBD_CFG_STATE_Pos (5) /*!< USBD_EP_T::CFG: STATE Position */ +#define USBD_CFG_STATE_Msk (0x3ul << USBD_CFG_STATE_Pos) /*!< USBD_EP_T::CFG: STATE Mask */ + +#define USBD_CFG_DSQSYNC_Pos (7) /*!< USBD_EP_T::CFG: DSQSYNC Position */ +#define USBD_CFG_DSQSYNC_Msk (0x1ul << USBD_CFG_DSQSYNC_Pos) /*!< USBD_EP_T::CFG: DSQSYNC Mask */ + +#define USBD_CFG_CSTALL_Pos (9) /*!< USBD_EP_T::CFG: CSTALL Position */ +#define USBD_CFG_CSTALL_Msk (0x1ul << USBD_CFG_CSTALL_Pos) /*!< USBD_EP_T::CFG: CSTALL Mask */ + +#define USBD_CFGP_CLRRDY_Pos (0) /*!< USBD_EP_T::CFGP: CLRRDY Position */ +#define USBD_CFGP_CLRRDY_Msk (0x1ul << USBD_CFGP_CLRRDY_Pos) /*!< USBD_EP_T::CFGP: CLRRDY Mask */ + +#define USBD_CFGP_SSTALL_Pos (1) /*!< USBD_EP_T::CFGP: SSTALL Position */ +#define USBD_CFGP_SSTALL_Msk (0x1ul << USBD_CFGP_SSTALL_Pos) /*!< USBD_EP_T::CFGP: SSTALL Mask */ + +/**@}*/ /* USBD_CONST */ +/**@}*/ /* end of USBD register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __USBD_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/uspi_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/uspi_reg.h new file mode 100644 index 00000000000..ac38c23acf7 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/uspi_reg.h @@ -0,0 +1,676 @@ +/**************************************************************************//** + * @file uspi_reg.h + * @version V1.00 + * @brief USPI register definition header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __USPI_REG_H__ +#define __USPI_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup USPI SPI Mode of USCI Controller (USPI) + Memory Mapped Structure for USPI Controller +@{ */ + +typedef struct +{ + + + /** + * @var USPI_T::CTL + * Offset: 0x00 USCI Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |FUNMODE |Function Mode + * | | |This bit field selects the protocol for this USCI controller + * | | |Selecting a protocol that is not available or a reserved combination disables the USCI + * | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol + * | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE. + * | | |000 = The USCI is disabled. All protocol related state machines are set to idle state. + * | | |001 = The SPI protocol is selected. + * | | |010 = The UART protocol is selected. + * | | |100 = The I2C protocol is selected. + * | | |Note: Other bit combinations are reserved. + * @var USPI_T::INTEN + * Offset: 0x04 USCI Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TXSTIEN |Transmit Start Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a transmit start event. + * | | |0 = The transmit start interrupt is disabled. + * | | |1 = The transmit start interrupt is enabled. + * |[2] |TXENDIEN |Transmit End Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a transmit finish event. + * | | |0 = The transmit finish interrupt is disabled. + * | | |1 = The transmit finish interrupt is enabled. + * |[3] |RXSTIEN |Receive Start Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a receive start event. + * | | |0 = The receive start interrupt is disabled. + * | | |1 = The receive start interrupt is enabled. + * |[4] |RXENDIEN |Receive End Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a receive finish event. + * | | |0 = The receive end interrupt is disabled. + * | | |1 = The receive end interrupt is enabled. + * @var USPI_T::BRGEN + * Offset: 0x08 USCI Baud Rate Generator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RCLKSEL |Reference Clock Source Selection + * | | |This bit selects the source of reference clock (fREF_CLK). + * | | |0 = Peripheral device clock fPCLK. + * | | |1 = Reserved. + * |[1] |PTCLKSEL |Protocol Clock Source Selection + * | | |This bit selects the source of protocol clock (fPROT_CLK). + * | | |0 = Reference clock fREF_CLK. + * | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK). + * |[3:2] |SPCLKSEL |Sample Clock Source Selection + * | | |This bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor. + * | | |00 = fDIV_CLK. + * | | |01 = fPROT_CLK. + * | | |10 = fSCLK. + * | | |11 = fREF_CLK. + * |[4] |TMCNTEN |Time Measurement Counter Enable Bit + * | | |This bit enables the 10-bit timing measurement counter. + * | | |0 = Time measurement counter is Disabled. + * | | |1 = Time measurement counter is Enabled. + * |[5] |TMCNTSRC |Time Measurement Counter Clock Source Selection + * | | |0 = Time measurement counter with fPROT_CLK. + * | | |1 = Time measurement counter with fDIV_CLK. + * |[25:16] |CLKDIV |Clock Divider + * | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ). + * | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(USPI_PROTCTL[6])) is enabled + * | | |The revised value is the average bit time between bit 5 and bit 6 + * | | |The user can use revised CLKDIV and new BRDETITV (USPI_PROTCTL[24:16]) to calculate the precise baud rate. + * @var USPI_T::DATIN0 + * Offset: 0x10 USCI Input Data Signal Configuration Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Signal Synchronization Selection + * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * | | |Note: In SPI protocol, we suggest this bit should be set as 0. + * |[2] |ININV |Input Signal Inverse Selection + * | | |This bit defines the inverter enable of the input asynchronous signal. + * | | |0 = The un-synchronized input signal will not be inverted. + * | | |1 = The un-synchronized input signal will be inverted. + * | | |Note: In SPI protocol, we suggest this bit should be set as 0. + * @var USPI_T::CTLIN0 + * Offset: 0x20 USCI Input Control Signal Configuration Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Synchronization Signal Selection + * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * | | |Note: In SPI protocol, we suggest this bit should be set as 0. + * |[2] |ININV |Input Signal Inverse Selection + * | | |This bit defines the inverter enable of the input asynchronous signal. + * | | |0 = The un-synchronized input signal will not be inverted. + * | | |1 = The un-synchronized input signal will be inverted. + * @var USPI_T::CLKIN + * Offset: 0x28 USCI Input Clock Signal Configuration Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Synchronization Signal Selection + * | | |This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * | | |Note: In SPI protocol, we suggest this bit should be set as 0. + * @var USPI_T::LINECTL + * Offset: 0x2C USCI Line Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LSB |LSB First Transmission Selection + * | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first. + * | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first. + * |[5] |DATOINV |Data Output Inverse Selection + * | | |This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin. + * | | |0 = Data output level is not inverted. + * | | |1 = Data output level is inverted. + * |[7] |CTLOINV |Control Signal Output Inverse Selection + * | | |This bit defines the relation between the internal control signal and the output control signal. + * | | |0 = No effect. + * | | |1 = The control signal will be inverted before its output. + * | | |Note: The control signal has different definitions in different protocol + * | | |In SPI protocol, the control signal means slave select signal + * | | |In UART protocol, the control signal means RTS signal. + * |[11:8] |DWIDTH |Word Length of Transmission + * | | |This bit field defines the data word length (amount of bits) for reception and transmission + * | | |The data word is always right-aligned in the data buffer + * | | |USCI support word length from 4 to 16 bits. + * | | |0x0: The data word contains 16 bits located at bit positions [15:0]. + * | | |0x1: Reserved. + * | | |0x2: Reserved. + * | | |0x3: Reserved. + * | | |0x4: The data word contains 4 bits located at bit positions [3:0]. + * | | |0x5: The data word contains 5 bits located at bit positions [4:0]. + * | | |... + * | | |0xF: The data word contains 15 bits located at bit positions [14:0]. + * | | |Note: In UART protocol, the length can be configured as 6~13 bits. + * @var USPI_T::TXDAT + * Offset: 0x30 USCI Transmit Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TXDAT |Transmit Data + * | | |Software can use this bit field to write 16-bit transmit data for transmission + * | | |In order to avoid overwriting the transmit data, user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field. + * |[16] |PORTDIR |Port Direction Control + * | | |This bit field is only available while USCI operates in SPI protocol (FUNMODE = 0x1) with half-duplex transfer + * | | |It is used to define the direction of the data port pin + * | | |When software writes USPI_TXDAT register, the transmit data and its port direction are settled simultaneously. + * | | |0 = The data pin is configured as output mode. + * | | |1 = The data pin is configured as input mode. + * @var USPI_T::RXDAT + * Offset: 0x34 USCI Receive Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RXDAT |Received Data + * | | |This bit field monitors the received data which stored in receive data buffer. + * @var USPI_T::BUFCTL + * Offset: 0x38 USCI Transmit/Receive Buffer Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6] |TXUDRIEN |Slave Transmit Under Run Interrupt Enable Bit + * | | |0 = Transmit under-run interrupt Disabled. + * | | |1 = Transmit under-run interrupt Enabled. + * |[7] |TXCLR |Clear Transmit Buffer + * | | |0 = No effect. + * | | |1 = The transmit buffer is cleared + * | | |Should only be used while the buffer is not taking part in data traffic. + * | | |Note: It is cleared automatically after one PCLK cycle. + * |[14] |RXOVIEN |Receive Buffer Overrun Interrupt Enable Bit + * | | |0 = Receive overrun interrupt Disabled. + * | | |1 = Receive overrun interrupt Enabled. + * |[15] |RXCLR |Clear Receive Buffer + * | | |0 = No effect. + * | | |1 = The receive buffer is cleared + * | | |Should only be used while the buffer is not taking part in data traffic. + * | | |Note: It is cleared automatically after one PCLK cycle. + * |[16] |TXRST |Transmit Reset + * | | |0 = No effect. + * | | |1 = Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer. + * | | |Note1: It is cleared automatically after one PCLK cycle. + * | | |Note2: Write 1 to this bit will set the output data pin to zero if USPI_BUFCTL[5]=0. + * |[17] |RXRST |Receive Reset + * | | |0 = No effect. + * | | |1 = Reset the receive-related counters, state machine, and the content of receive shift register and data buffer. + * | | |Note: It is cleared automatically after one PCLK cycle. + * @var USPI_T::BUFSTS + * Offset: 0x3C USCI Transmit/Receive Buffer Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXEMPTY |Receive Buffer Empty Indicator + * | | |0 = Receive buffer is not empty. + * | | |1 = Receive buffer is empty. + * |[1] |RXFULL |Receive Buffer Full Indicator + * | | |0 = Receive buffer is not full. + * | | |1 = Receive buffer is full. + * |[3] |RXOVIF |Receive Buffer Over-run Interrupt Status + * | | |This bit indicates that a receive buffer overrun event has been detected + * | | |If RXOVIEN (USPI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated + * | | |It is cleared by software writes 1 to this bit. + * | | |0 = A receive buffer overrun event has not been detected. + * | | |1 = A receive buffer overrun event has been detected. + * |[8] |TXEMPTY |Transmit Buffer Empty Indicator + * | | |0 = Transmit buffer is not empty. + * | | |1 = Transmit buffer is empty and available for the next transmission datum. + * |[9] |TXFULL |Transmit Buffer Full Indicator + * | | |0 = Transmit buffer is not full. + * | | |1 = Transmit buffer is full. + * |[11] |TXUDRIF |Transmit Buffer Under-run Interrupt Status + * | | |This bit indicates that a transmit buffer under-run event has been detected + * | | |If enabled by TXUDRIEN (USPI_BUFCTL[6]), the corresponding interrupt request is activated + * | | |It is cleared by software writes 1 to this bit + * | | |0 = A transmit buffer under-run event has not been detected. + * | | |1 = A transmit buffer under-run event has been detected. + * @var USPI_T::PDMACTL + * Offset: 0x40 USCI PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PDMARST |PDMA Reset + * | | |0 = No effect. + * | | |1 = Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically. + * |[1] |TXPDMAEN |PDMA Transmit Channel Available + * | | |0 = Transmit PDMA function Disabled. + * | | |1 = Transmit PDMA function Enabled. + * |[2] |RXPDMAEN |PDMA Receive Channel Available + * | | |0 = Receive PDMA function Disabled. + * | | |1 = Receive PDMA function Enabled. + * |[3] |PDMAEN |PDMA Mode Enable Bit + * | | |0 = PDMA function Disabled. + * | | |1 = PDMA function Enabled. + * | | |Notice: The I2C is not supporting PDMA function. + * @var USPI_T::WKCTL + * Offset: 0x54 USCI Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Wake-up Enable Bit + * | | |0 = Wake-up function Disabled. + * | | |1 = Wake-up function Enabled. + * |[1] |WKADDREN |Wake-up Address Match Enable Bit + * | | |0 = The chip is woken up according data toggle. + * | | |1 = The chip is woken up according address match. + * |[2] |PDBOPT |Power Down Blocking Option + * | | |0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately. + * | | |1 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately. + * @var USPI_T::WKSTS + * Offset: 0x58 USCI Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKF |Wake-up Flag + * | | |When chip is woken up from Power-down mode, this bit is set to 1 + * | | |Software can write 1 to clear this bit. + * @var USPI_T::PROTCTL + * Offset: 0x5C USCI Protocol Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SLAVE |Slave Mode Selection + * | | |0 = Master mode. + * | | |1 = Slave mode. + * |[1] |SLV3WIRE |Slave 3-wire Mode Selection (Slave Only) + * | | |The SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode. + * | | |0 = 4-wire bi-direction interface. + * | | |1 = 3-wire bi-direction interface. + * |[2] |SS |Slave Select Control (Master Only) + * | | |If AUTOSS bit is cleared, setting this bit to 1 will set the slave select signal to active state, and setting this bit to 0 will set the slave select back to inactive state. + * | | |If the AUTOSS function is enabled (AUTOSS = 1), the setting value of this bit will not affect the current state of slave select signal. + * | | |Note: In SPI protocol, the internal slave select signal is active high. + * |[3] |AUTOSS |Automatic Slave Select Function Enable (Master Only) + * | | |0 = Slave select signal will be controlled by the setting value of SS (USPI_PROTCTL[2]) bit. + * | | |1 = Slave select signal will be generated automatically + * | | |The slave select signal will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished. + * |[7:6] |SCLKMODE |Serial Bus Clock Mode + * | | |This bit field defines the SCLK idle status, data transmit, and data receive edge. + * | | |MODE0 = The idle state of SPI clock is low level + * | | |Data is transmitted with falling edge and received with rising edge. + * | | |MODE1 = The idle state of SPI clock is low level + * | | |Data is transmitted with rising edge and received with falling edge. + * | | |MODE2 = The idle state of SPI clock is high level + * | | |Data is transmitted with rising edge and received with falling edge. + * | | |MODE3 = The idle state of SPI clock is high level + * | | |Data is transmitted with falling edge and received with rising edge. + * |[11:8] |SUSPITV |Suspend Interval (Master Only) + * | | |This bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer + * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word + * | | |The default value is 0x3 + * | | |The period of the suspend interval is obtained according to the following equation. + * | | |(SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle + * | | |Example: + * | | |SUSPITV = 0x0 u2026 0.5 SPI_CLK clock cycle. + * | | |SUSPITV = 0x1 u2026 1.5 SPI_CLK clock cycle. + * | | |u2026u2026 + * | | |SUSPITV = 0xE u2026 14.5 SPI_CLK clock cycle. + * | | |SUSPITV = 0xF u2026 15.5 SPI_CLK clock cycle. + * |[14:12] |TSMSEL |Transmit Data Mode Selection + * | | |This bit field describes how receive and transmit data is shifted in and out. + * | | |TSMSEL = 000b: Full-duplex SPI. + * | | |TSMSEL = 100b: Half-duplex SPI. + * | | |Other values are reserved. + * | | |Note: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically. + * |[25:16] |SLVTOCNT |Slave Mode Time-out Period (Slave Only) + * | | |In Slave mode, this bit field is used for Slave time-out period + * | | |This bit field indicates how many clock periods (selected by TMCNTSRC, USPI_BRGEN[5]) between the two edges of input SCLK will assert the Slave time-out event + * | | |Writing 0x0 into this bit field will disable the Slave time-out function. + * | | |Example: Assume SLVTOCNT is 0x0A and TMCNTSRC (USPI_BRGEN[5]) is 1, it means the time-out event will occur if the state of SPI bus clock pin is not changed more than (10+1) periods of fDIV_CLK. + * |[28] |TXUDRPOL |Transmit Under-run Data Polarity (for Slave) + * | | |This bit defines the transmitting data level when no data is available for transferring. + * | | |0 = The output data level is 0 if TX under run event occurs. + * | | |1 = The output data level is 1 if TX under run event occurs. + * |[31] |PROTEN |SPI Protocol Enable Bit + * | | |0 = SPI Protocol Disabled. + * | | |1 = SPI Protocol Enabled. + * @var USPI_T::PROTIEN + * Offset: 0x60 USCI Protocol Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SSINAIEN |Slave Select Inactive Interrupt Enable Control + * | | |This bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive. + * | | |0 = Slave select inactive interrupt generation Disabled. + * | | |1 = Slave select inactive interrupt generation Enabled. + * |[1] |SSACTIEN |Slave Select Active Interrupt Enable Control + * | | |This bit enables/disables the generation of a slave select interrupt if the slave select changes to active. + * | | |0 = Slave select active interrupt generation Disabled. + * | | |1 = Slave select active interrupt generation Enabled. + * |[2] |SLVTOIEN |Slave Time-out Interrupt Enable Control + * | | |In SPI protocol, this bit enables the interrupt generation in case of a Slave time-out event. + * | | |0 = The Slave time-out interrupt Disabled. + * | | |1 = The Slave time-out interrupt Enabled. + * |[3] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Control + * | | |If data transfer is terminated by slave time-out or slave select inactive event in Slave mode, so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]) + * | | |Bit count error event occurs. + * | | |0 = The Slave mode bit count error interrupt Disabled. + * | | |1 = The Slave mode bit count error interrupt Enabled. + * @var USPI_T::PROTSTS + * Offset: 0x64 USCI Protocol Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TXSTIF |Transmit Start Interrupt Flag + * | | |0 = Transmit start event does not occur. + * | | |1 = Transmit start event occurs. + * | | |Note: It is cleared by software writes 1 to this bit + * |[2] |TXENDIF |Transmit End Interrupt Flag + * | | |0 = Transmit end event does not occur. + * | | |1 = Transmit end event occurs. + * | | |Note: It is cleared by software writes 1 to this bit + * |[3] |RXSTIF |Receive Start Interrupt Flag + * | | |0 = Receive start event does not occur. + * | | |1 = Receive start event occurs. + * | | |Note: It is cleared by software writes 1 to this bit + * |[4] |RXENDIF |Receive End Interrupt Flag + * | | |0 = Receive end event does not occur. + * | | |1 = Receive end event occurs. + * | | |Note: It is cleared by software writes 1 to this bit + * |[5] |SLVTOIF |Slave Time-out Interrupt Flag (for Slave Only) + * | | |0 = Slave time-out event does not occur. + * | | |1 = Slave time-out event occurs. + * | | |Note: It is cleared by software writes 1 to this bit + * |[6] |SLVBEIF |Slave Bit Count Error Interrupt Flag (for Slave Only) + * | | |0 = Slave bit count error event does not occur. + * | | |1 = Slave bit count error event occurs. + * | | |Note: It is cleared by software writes 1 to this bit. + * |[8] |SSINAIF |Slave Select Inactive Interrupt Flag (for Slave Only) + * | | |This bit indicates that the internal slave select signal has changed to inactive + * | | |It is cleared by software writes 1 to this bit + * | | |0 = The slave select signal has not changed to inactive. + * | | |1 = The slave select signal has changed to inactive. + * | | |Note: The internal slave select signal is active high. + * |[9] |SSACTIF |Slave Select Active Interrupt Flag (for Slave Only) + * | | |This bit indicates that the internal slave select signal has changed to active + * | | |It is cleared by software writes one to this bit + * | | |0 = The slave select signal has not changed to active. + * | | |1 = The slave select signal has changed to active. + * | | |Note: The internal slave select signal is active high. + * |[16] |SSLINE |Slave Select Line Bus Status (Read Only) + * | | |This bit is only available in Slave mode + * | | |It used to monitor the current status of the input slave select signal on the bus. + * | | |0 = The slave select line status is 0. + * | | |1 = The slave select line status is 1. + * |[17] |BUSY |Busy Status (Read Only) + * | | |0 = SPI is in idle state. + * | | |1 = SPI is in busy state. + * | | |The following listing are the bus busy conditions: + * | | |a. USPI_PROTCTL[31] = 1 and the TXEMPTY = 0. + * | | |b. For SPI Master mode, the TXEMPTY = 1 but the current transaction is not finished yet. + * | | |c + * | | |For SPI Slave mode, the USPI_PROTCTL[31] = 1 and there is serial clock input into the SPI core logic when slave select is active. + * | | |d + * | | |For SPI Slave mode, the USPI_PROTCTL[31] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive. + * |[18] |SLVUDR |Slave Mode Transmit Under-run Status (Read Only) + * | | |In Slave mode, if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock, this status flag will be set to 1 + * | | |This bit indicates whether the current shift-out data of word transmission is switched to TXUDRPOL (USPI_PROTCTL[28]) or not. + * | | |0 = Slave transmit under run event does not occur. + * | | |1 = Slave transmit under run event occurs. + */ + __IO uint32_t CTL; /*!< [0x0000] USCI Control Register */ + __IO uint32_t INTEN; /*!< [0x0004] USCI Interrupt Enable Register */ + __IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */ + __I uint32_t RESERVE0[1]; + __IO uint32_t DATIN0; /*!< [0x0010] USCI Input Data Signal Configuration Register 0 */ + __I uint32_t RESERVE1[3]; + __IO uint32_t CTLIN0; /*!< [0x0020] USCI Input Control Signal Configuration Register 0 */ + __I uint32_t RESERVE2[1]; + __IO uint32_t CLKIN; /*!< [0x0028] USCI Input Clock Signal Configuration Register */ + __IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */ + __O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */ + __I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */ + __IO uint32_t BUFCTL; /*!< [0x0038] USCI Transmit/Receive Buffer Control Register */ + __IO uint32_t BUFSTS; /*!< [0x003c] USCI Transmit/Receive Buffer Status Register */ + __IO uint32_t PDMACTL; /*!< [0x0040] USCI PDMA Control Register */ + __I uint32_t RESERVE3[4]; + __IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */ + __IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */ + __IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */ + __IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */ + __IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */ + __I uint32_t RESERVE4[998]; + +} USPI_T; + +/** + @addtogroup USPI_CONST USPI Bit Field Definition + Constant Definitions for USPI Controller +@{ */ + +#define USPI_CTL_FUNMODE_Pos (0) /*!< USPI_T::CTL: FUNMODE Position */ +#define USPI_CTL_FUNMODE_Msk (0x7ul << USPI_CTL_FUNMODE_Pos) /*!< USPI_T::CTL: FUNMODE Mask */ + +#define USPI_INTEN_TXSTIEN_Pos (1) /*!< USPI_T::INTEN: TXSTIEN Position */ +#define USPI_INTEN_TXSTIEN_Msk (0x1ul << USPI_INTEN_TXSTIEN_Pos) /*!< USPI_T::INTEN: TXSTIEN Mask */ + +#define USPI_INTEN_TXENDIEN_Pos (2) /*!< USPI_T::INTEN: TXENDIEN Position */ +#define USPI_INTEN_TXENDIEN_Msk (0x1ul << USPI_INTEN_TXENDIEN_Pos) /*!< USPI_T::INTEN: TXENDIEN Mask */ + +#define USPI_INTEN_RXSTIEN_Pos (3) /*!< USPI_T::INTEN: RXSTIEN Position */ +#define USPI_INTEN_RXSTIEN_Msk (0x1ul << USPI_INTEN_RXSTIEN_Pos) /*!< USPI_T::INTEN: RXSTIEN Mask */ + +#define USPI_INTEN_RXENDIEN_Pos (4) /*!< USPI_T::INTEN: RXENDIEN Position */ +#define USPI_INTEN_RXENDIEN_Msk (0x1ul << USPI_INTEN_RXENDIEN_Pos) /*!< USPI_T::INTEN: RXENDIEN Mask */ + +#define USPI_BRGEN_RCLKSEL_Pos (0) /*!< USPI_T::BRGEN: RCLKSEL Position */ +#define USPI_BRGEN_RCLKSEL_Msk (0x1ul << USPI_BRGEN_RCLKSEL_Pos) /*!< USPI_T::BRGEN: RCLKSEL Mask */ + +#define USPI_BRGEN_PTCLKSEL_Pos (1) /*!< USPI_T::BRGEN: PTCLKSEL Position */ +#define USPI_BRGEN_PTCLKSEL_Msk (0x1ul << USPI_BRGEN_PTCLKSEL_Pos) /*!< USPI_T::BRGEN: PTCLKSEL Mask */ + +#define USPI_BRGEN_SPCLKSEL_Pos (2) /*!< USPI_T::BRGEN: SPCLKSEL Position */ +#define USPI_BRGEN_SPCLKSEL_Msk (0x3ul << USPI_BRGEN_SPCLKSEL_Pos) /*!< USPI_T::BRGEN: SPCLKSEL Mask */ + +#define USPI_BRGEN_TMCNTEN_Pos (4) /*!< USPI_T::BRGEN: TMCNTEN Position */ +#define USPI_BRGEN_TMCNTEN_Msk (0x1ul << USPI_BRGEN_TMCNTEN_Pos) /*!< USPI_T::BRGEN: TMCNTEN Mask */ + +#define USPI_BRGEN_TMCNTSRC_Pos (5) /*!< USPI_T::BRGEN: TMCNTSRC Position */ +#define USPI_BRGEN_TMCNTSRC_Msk (0x1ul << USPI_BRGEN_TMCNTSRC_Pos) /*!< USPI_T::BRGEN: TMCNTSRC Mask */ + +#define USPI_BRGEN_CLKDIV_Pos (16) /*!< USPI_T::BRGEN: CLKDIV Position */ +#define USPI_BRGEN_CLKDIV_Msk (0x3fful << USPI_BRGEN_CLKDIV_Pos) /*!< USPI_T::BRGEN: CLKDIV Mask */ + +#define USPI_DATIN0_SYNCSEL_Pos (0) /*!< USPI_T::DATIN0: SYNCSEL Position */ +#define USPI_DATIN0_SYNCSEL_Msk (0x1ul << USPI_DATIN0_SYNCSEL_Pos) /*!< USPI_T::DATIN0: SYNCSEL Mask */ + +#define USPI_DATIN0_ININV_Pos (2) /*!< USPI_T::DATIN0: ININV Position */ +#define USPI_DATIN0_ININV_Msk (0x1ul << USPI_DATIN0_ININV_Pos) /*!< USPI_T::DATIN0: ININV Mask */ + +#define USPI_CTLIN0_SYNCSEL_Pos (0) /*!< USPI_T::CTLIN0: SYNCSEL Position */ +#define USPI_CTLIN0_SYNCSEL_Msk (0x1ul << USPI_CTLIN0_SYNCSEL_Pos) /*!< USPI_T::CTLIN0: SYNCSEL Mask */ + +#define USPI_CTLIN0_ININV_Pos (2) /*!< USPI_T::CTLIN0: ININV Position */ +#define USPI_CTLIN0_ININV_Msk (0x1ul << USPI_CTLIN0_ININV_Pos) /*!< USPI_T::CTLIN0: ININV Mask */ + +#define USPI_CLKIN_SYNCSEL_Pos (0) /*!< USPI_T::CLKIN: SYNCSEL Position */ +#define USPI_CLKIN_SYNCSEL_Msk (0x1ul << USPI_CLKIN_SYNCSEL_Pos) /*!< USPI_T::CLKIN: SYNCSEL Mask */ + +#define USPI_LINECTL_LSB_Pos (0) /*!< USPI_T::LINECTL: LSB Position */ +#define USPI_LINECTL_LSB_Msk (0x1ul << USPI_LINECTL_LSB_Pos) /*!< USPI_T::LINECTL: LSB Mask */ + +#define USPI_LINECTL_DATOINV_Pos (5) /*!< USPI_T::LINECTL: DATOINV Position */ +#define USPI_LINECTL_DATOINV_Msk (0x1ul << USPI_LINECTL_DATOINV_Pos) /*!< USPI_T::LINECTL: DATOINV Mask */ + +#define USPI_LINECTL_CTLOINV_Pos (7) /*!< USPI_T::LINECTL: CTLOINV Position */ +#define USPI_LINECTL_CTLOINV_Msk (0x1ul << USPI_LINECTL_CTLOINV_Pos) /*!< USPI_T::LINECTL: CTLOINV Mask */ + +#define USPI_LINECTL_DWIDTH_Pos (8) /*!< USPI_T::LINECTL: DWIDTH Position */ +#define USPI_LINECTL_DWIDTH_Msk (0xful << USPI_LINECTL_DWIDTH_Pos) /*!< USPI_T::LINECTL: DWIDTH Mask */ + +#define USPI_TXDAT_TXDAT_Pos (0) /*!< USPI_T::TXDAT: TXDAT Position */ +#define USPI_TXDAT_TXDAT_Msk (0xfffful << USPI_TXDAT_TXDAT_Pos) /*!< USPI_T::TXDAT: TXDAT Mask */ + +#define USPI_TXDAT_PORTDIR_Pos (16) /*!< USPI_T::TXDAT: PORTDIR Position */ +#define USPI_TXDAT_PORTDIR_Msk (0x1ul << USPI_TXDAT_PORTDIR_Pos) /*!< USPI_T::TXDAT: PORTDIR Mask */ + +#define USPI_RXDAT_RXDAT_Pos (0) /*!< USPI_T::RXDAT: RXDAT Position */ +#define USPI_RXDAT_RXDAT_Msk (0xfffful << USPI_RXDAT_RXDAT_Pos) /*!< USPI_T::RXDAT: RXDAT Mask */ + +#define USPI_BUFCTL_TXUDRIEN_Pos (6) /*!< USPI_T::BUFCTL: TXUDRIEN Position */ +#define USPI_BUFCTL_TXUDRIEN_Msk (0x1ul << USPI_BUFCTL_TXUDRIEN_Pos) /*!< USPI_T::BUFCTL: TXUDRIEN Mask */ + +#define USPI_BUFCTL_TXCLR_Pos (7) /*!< USPI_T::BUFCTL: TXCLR Position */ +#define USPI_BUFCTL_TXCLR_Msk (0x1ul << USPI_BUFCTL_TXCLR_Pos) /*!< USPI_T::BUFCTL: TXCLR Mask */ + +#define USPI_BUFCTL_RXOVIEN_Pos (14) /*!< USPI_T::BUFCTL: RXOVIEN Position */ +#define USPI_BUFCTL_RXOVIEN_Msk (0x1ul << USPI_BUFCTL_RXOVIEN_Pos) /*!< USPI_T::BUFCTL: RXOVIEN Mask */ + +#define USPI_BUFCTL_RXCLR_Pos (15) /*!< USPI_T::BUFCTL: RXCLR Position */ +#define USPI_BUFCTL_RXCLR_Msk (0x1ul << USPI_BUFCTL_RXCLR_Pos) /*!< USPI_T::BUFCTL: RXCLR Mask */ + +#define USPI_BUFCTL_TXRST_Pos (16) /*!< USPI_T::BUFCTL: TXRST Position */ +#define USPI_BUFCTL_TXRST_Msk (0x1ul << USPI_BUFCTL_TXRST_Pos) /*!< USPI_T::BUFCTL: TXRST Mask */ + +#define USPI_BUFCTL_RXRST_Pos (17) /*!< USPI_T::BUFCTL: RXRST Position */ +#define USPI_BUFCTL_RXRST_Msk (0x1ul << USPI_BUFCTL_RXRST_Pos) /*!< USPI_T::BUFCTL: RXRST Mask */ + +#define USPI_BUFSTS_RXEMPTY_Pos (0) /*!< USPI_T::BUFSTS: RXEMPTY Position */ +#define USPI_BUFSTS_RXEMPTY_Msk (0x1ul << USPI_BUFSTS_RXEMPTY_Pos) /*!< USPI_T::BUFSTS: RXEMPTY Mask */ + +#define USPI_BUFSTS_RXFULL_Pos (1) /*!< USPI_T::BUFSTS: RXFULL Position */ +#define USPI_BUFSTS_RXFULL_Msk (0x1ul << USPI_BUFSTS_RXFULL_Pos) /*!< USPI_T::BUFSTS: RXFULL Mask */ + +#define USPI_BUFSTS_RXOVIF_Pos (3) /*!< USPI_T::BUFSTS: RXOVIF Position */ +#define USPI_BUFSTS_RXOVIF_Msk (0x1ul << USPI_BUFSTS_RXOVIF_Pos) /*!< USPI_T::BUFSTS: RXOVIF Mask */ + +#define USPI_BUFSTS_TXEMPTY_Pos (8) /*!< USPI_T::BUFSTS: TXEMPTY Position */ +#define USPI_BUFSTS_TXEMPTY_Msk (0x1ul << USPI_BUFSTS_TXEMPTY_Pos) /*!< USPI_T::BUFSTS: TXEMPTY Mask */ + +#define USPI_BUFSTS_TXFULL_Pos (9) /*!< USPI_T::BUFSTS: TXFULL Position */ +#define USPI_BUFSTS_TXFULL_Msk (0x1ul << USPI_BUFSTS_TXFULL_Pos) /*!< USPI_T::BUFSTS: TXFULL Mask */ + +#define USPI_BUFSTS_TXUDRIF_Pos (11) /*!< USPI_T::BUFSTS: TXUDRIF Position */ +#define USPI_BUFSTS_TXUDRIF_Msk (0x1ul << USPI_BUFSTS_TXUDRIF_Pos) /*!< USPI_T::BUFSTS: TXUDRIF Mask */ + +#define USPI_PDMACTL_PDMARST_Pos (0) /*!< USPI_T::PDMACTL: PDMARST Position */ +#define USPI_PDMACTL_PDMARST_Msk (0x1ul << USPI_PDMACTL_PDMARST_Pos) /*!< USPI_T::PDMACTL: PDMARST Mask */ + +#define USPI_PDMACTL_TXPDMAEN_Pos (1) /*!< USPI_T::PDMACTL: TXPDMAEN Position */ +#define USPI_PDMACTL_TXPDMAEN_Msk (0x1ul << USPI_PDMACTL_TXPDMAEN_Pos) /*!< USPI_T::PDMACTL: TXPDMAEN Mask */ + +#define USPI_PDMACTL_RXPDMAEN_Pos (2) /*!< USPI_T::PDMACTL: RXPDMAEN Position */ +#define USPI_PDMACTL_RXPDMAEN_Msk (0x1ul << USPI_PDMACTL_RXPDMAEN_Pos) /*!< USPI_T::PDMACTL: RXPDMAEN Mask */ + +#define USPI_PDMACTL_PDMAEN_Pos (3) /*!< USPI_T::PDMACTL: PDMAEN Position */ +#define USPI_PDMACTL_PDMAEN_Msk (0x1ul << USPI_PDMACTL_PDMAEN_Pos) /*!< USPI_T::PDMACTL: PDMAEN Mask */ + +#define USPI_WKCTL_WKEN_Pos (0) /*!< USPI_T::WKCTL: WKEN Position */ +#define USPI_WKCTL_WKEN_Msk (0x1ul << USPI_WKCTL_WKEN_Pos) /*!< USPI_T::WKCTL: WKEN Mask */ + +#define USPI_WKCTL_WKADDREN_Pos (1) /*!< USPI_T::WKCTL: WKADDREN Position */ +#define USPI_WKCTL_WKADDREN_Msk (0x1ul << USPI_WKCTL_WKADDREN_Pos) /*!< USPI_T::WKCTL: WKADDREN Mask */ + +#define USPI_WKCTL_PDBOPT_Pos (2) /*!< USPI_T::WKCTL: PDBOPT Position */ +#define USPI_WKCTL_PDBOPT_Msk (0x1ul << USPI_WKCTL_PDBOPT_Pos) /*!< USPI_T::WKCTL: PDBOPT Mask */ + +#define USPI_WKSTS_WKF_Pos (0) /*!< USPI_T::WKSTS: WKF Position */ +#define USPI_WKSTS_WKF_Msk (0x1ul << USPI_WKSTS_WKF_Pos) /*!< USPI_T::WKSTS: WKF Mask */ + +#define USPI_PROTCTL_SLAVE_Pos (0) /*!< USPI_T::PROTCTL: SLAVE Position */ +#define USPI_PROTCTL_SLAVE_Msk (0x1ul << USPI_PROTCTL_SLAVE_Pos) /*!< USPI_T::PROTCTL: SLAVE Mask */ + +#define USPI_PROTCTL_SLV3WIRE_Pos (1) /*!< USPI_T::PROTCTL: SLV3WIRE Position */ +#define USPI_PROTCTL_SLV3WIRE_Msk (0x1ul << USPI_PROTCTL_SLV3WIRE_Pos) /*!< USPI_T::PROTCTL: SLV3WIRE Mask */ + +#define USPI_PROTCTL_SS_Pos (2) /*!< USPI_T::PROTCTL: SS Position */ +#define USPI_PROTCTL_SS_Msk (0x1ul << USPI_PROTCTL_SS_Pos) /*!< USPI_T::PROTCTL: SS Mask */ + +#define USPI_PROTCTL_AUTOSS_Pos (3) /*!< USPI_T::PROTCTL: AUTOSS Position */ +#define USPI_PROTCTL_AUTOSS_Msk (0x1ul << USPI_PROTCTL_AUTOSS_Pos) /*!< USPI_T::PROTCTL: AUTOSS Mask */ + +#define USPI_PROTCTL_SCLKMODE_Pos (6) /*!< USPI_T::PROTCTL: SCLKMODE Position */ +#define USPI_PROTCTL_SCLKMODE_Msk (0x3ul << USPI_PROTCTL_SCLKMODE_Pos) /*!< USPI_T::PROTCTL: SCLKMODE Mask */ + +#define USPI_PROTCTL_SUSPITV_Pos (8) /*!< USPI_T::PROTCTL: SUSPITV Position */ +#define USPI_PROTCTL_SUSPITV_Msk (0xful << USPI_PROTCTL_SUSPITV_Pos) /*!< USPI_T::PROTCTL: SUSPITV Mask */ + +#define USPI_PROTCTL_TSMSEL_Pos (12) /*!< USPI_T::PROTCTL: TSMSEL Position */ +#define USPI_PROTCTL_TSMSEL_Msk (0x7ul << USPI_PROTCTL_TSMSEL_Pos) /*!< USPI_T::PROTCTL: TSMSEL Mask */ + +#define USPI_PROTCTL_SLVTOCNT_Pos (16) /*!< USPI_T::PROTCTL: SLVTOCNT Position */ +#define USPI_PROTCTL_SLVTOCNT_Msk (0x3fful << USPI_PROTCTL_SLVTOCNT_Pos) /*!< USPI_T::PROTCTL: SLVTOCNT Mask */ + +#define USPI_PROTCTL_TXUDRPOL_Pos (28) /*!< USPI_T::PROTCTL: TXUDRPOL Position */ +#define USPI_PROTCTL_TXUDRPOL_Msk (0x1ul << USPI_PROTCTL_TXUDRPOL_Pos) /*!< USPI_T::PROTCTL: TXUDRPOL Mask */ + +#define USPI_PROTCTL_PROTEN_Pos (31) /*!< USPI_T::PROTCTL: PROTEN Position */ +#define USPI_PROTCTL_PROTEN_Msk (0x1ul << USPI_PROTCTL_PROTEN_Pos) /*!< USPI_T::PROTCTL: PROTEN Mask */ + +#define USPI_PROTIEN_SSINAIEN_Pos (0) /*!< USPI_T::PROTIEN: SSINAIEN Position */ +#define USPI_PROTIEN_SSINAIEN_Msk (0x1ul << USPI_PROTIEN_SSINAIEN_Pos) /*!< USPI_T::PROTIEN: SSINAIEN Mask */ + +#define USPI_PROTIEN_SSACTIEN_Pos (1) /*!< USPI_T::PROTIEN: SSACTIEN Position */ +#define USPI_PROTIEN_SSACTIEN_Msk (0x1ul << USPI_PROTIEN_SSACTIEN_Pos) /*!< USPI_T::PROTIEN: SSACTIEN Mask */ + +#define USPI_PROTIEN_SLVTOIEN_Pos (2) /*!< USPI_T::PROTIEN: SLVTOIEN Position */ +#define USPI_PROTIEN_SLVTOIEN_Msk (0x1ul << USPI_PROTIEN_SLVTOIEN_Pos) /*!< USPI_T::PROTIEN: SLVTOIEN Mask */ + +#define USPI_PROTIEN_SLVBEIEN_Pos (3) /*!< USPI_T::PROTIEN: SLVBEIEN Position */ +#define USPI_PROTIEN_SLVBEIEN_Msk (0x1ul << USPI_PROTIEN_SLVBEIEN_Pos) /*!< USPI_T::PROTIEN: SLVBEIEN Mask */ + +#define USPI_PROTSTS_TXSTIF_Pos (1) /*!< USPI_T::PROTSTS: TXSTIF Position */ +#define USPI_PROTSTS_TXSTIF_Msk (0x1ul << USPI_PROTSTS_TXSTIF_Pos) /*!< USPI_T::PROTSTS: TXSTIF Mask */ + +#define USPI_PROTSTS_TXENDIF_Pos (2) /*!< USPI_T::PROTSTS: TXENDIF Position */ +#define USPI_PROTSTS_TXENDIF_Msk (0x1ul << USPI_PROTSTS_TXENDIF_Pos) /*!< USPI_T::PROTSTS: TXENDIF Mask */ + +#define USPI_PROTSTS_RXSTIF_Pos (3) /*!< USPI_T::PROTSTS: RXSTIF Position */ +#define USPI_PROTSTS_RXSTIF_Msk (0x1ul << USPI_PROTSTS_RXSTIF_Pos) /*!< USPI_T::PROTSTS: RXSTIF Mask */ + +#define USPI_PROTSTS_RXENDIF_Pos (4) /*!< USPI_T::PROTSTS: RXENDIF Position */ +#define USPI_PROTSTS_RXENDIF_Msk (0x1ul << USPI_PROTSTS_RXENDIF_Pos) /*!< USPI_T::PROTSTS: RXENDIF Mask */ + +#define USPI_PROTSTS_SLVTOIF_Pos (5) /*!< USPI_T::PROTSTS: SLVTOIF Position */ +#define USPI_PROTSTS_SLVTOIF_Msk (0x1ul << USPI_PROTSTS_SLVTOIF_Pos) /*!< USPI_T::PROTSTS: SLVTOIF Mask */ + +#define USPI_PROTSTS_SLVBEIF_Pos (6) /*!< USPI_T::PROTSTS: SLVBEIF Position */ +#define USPI_PROTSTS_SLVBEIF_Msk (0x1ul << USPI_PROTSTS_SLVBEIF_Pos) /*!< USPI_T::PROTSTS: SLVBEIF Mask */ + +#define USPI_PROTSTS_SSINAIF_Pos (8) /*!< USPI_T::PROTSTS: SSINAIF Position */ +#define USPI_PROTSTS_SSINAIF_Msk (0x1ul << USPI_PROTSTS_SSINAIF_Pos) /*!< USPI_T::PROTSTS: SSINAIF Mask */ + +#define USPI_PROTSTS_SSACTIF_Pos (9) /*!< USPI_T::PROTSTS: SSACTIF Position */ +#define USPI_PROTSTS_SSACTIF_Msk (0x1ul << USPI_PROTSTS_SSACTIF_Pos) /*!< USPI_T::PROTSTS: SSACTIF Mask */ + +#define USPI_PROTSTS_SSLINE_Pos (16) /*!< USPI_T::PROTSTS: SSLINE Position */ +#define USPI_PROTSTS_SSLINE_Msk (0x1ul << USPI_PROTSTS_SSLINE_Pos) /*!< USPI_T::PROTSTS: SSLINE Mask */ + +#define USPI_PROTSTS_BUSY_Pos (17) /*!< USPI_T::PROTSTS: BUSY Position */ +#define USPI_PROTSTS_BUSY_Msk (0x1ul << USPI_PROTSTS_BUSY_Pos) /*!< USPI_T::PROTSTS: BUSY Mask */ + +#define USPI_PROTSTS_SLVUDR_Pos (18) /*!< USPI_T::PROTSTS: SLVUDR Position */ +#define USPI_PROTSTS_SLVUDR_Msk (0x1ul << USPI_PROTSTS_SLVUDR_Pos) /*!< USPI_T::PROTSTS: SLVUDR Mask */ + +/**@}*/ /* USPI_CONST */ +/**@}*/ /* end of USPI register group */ + + +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __USPI_REG_H__ */ \ No newline at end of file diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/uuart_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/uuart_reg.h new file mode 100644 index 00000000000..9a714a8abf8 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/uuart_reg.h @@ -0,0 +1,675 @@ +/**************************************************************************//** + * @file uuart_reg.h + * @version V1.00 + * @brief UUART register definition header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __UUART_REG_H__ +#define __UUART_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup UUART UART Mode of USCI Controller (UUART) + Memory Mapped Structure for UUART Controller +@{ */ + +typedef struct +{ + + + /** + * @var UUART_T::CTL + * Offset: 0x00 USCI Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |FUNMODE |Function Mode + * | | |This bit field selects the protocol for this USCI controller + * | | |Selecting a protocol that is not available or a reserved combination disables the USCI + * | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol + * | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE. + * | | |000 = The USCI is disabled. All protocol related state machines are set to idle state. + * | | |001 = The SPI protocol is selected. + * | | |010 = The UART protocol is selected. + * | | |100 = The I2C protocol is selected. + * | | |Note: Other bit combinations are reserved. + * @var UUART_T::INTEN + * Offset: 0x04 USCI Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TXSTIEN |Transmit Start Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a transmit start event. + * | | |0 = The transmit start interrupt is disabled. + * | | |1 = The transmit start interrupt is enabled. + * |[2] |TXENDIEN |Transmit End Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a transmit finish event. + * | | |0 = The transmit finish interrupt is disabled. + * | | |1 = The transmit finish interrupt is enabled. + * |[3] |RXSTIEN |Receive Start Interrupt Enable BIt + * | | |This bit enables the interrupt generation in case of a receive start event. + * | | |0 = The receive start interrupt is disabled. + * | | |1 = The receive start interrupt is enabled. + * |[4] |RXENDIEN |Receive End Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a receive finish event. + * | | |0 = The receive end interrupt is disabled. + * | | |1 = The receive end interrupt is enabled. + * @var UUART_T::BRGEN + * Offset: 0x08 USCI Baud Rate Generator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RCLKSEL |Reference Clock Source Selection + * | | |This bit selects the source signal of reference clock (fREF_CLK). + * | | |0 = Peripheral device clock fPCLK. + * | | |1 = Reserved. + * |[1] |PTCLKSEL |Protocol Clock Source Selection + * | | |This bit selects the source signal of protocol clock (fPROT_CLK). + * | | |0 = Reference clock fREF_CLK. + * | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK). + * |[3:2] |SPCLKSEL |Sample Clock Source Selection + * | | |This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor. + * | | |00 = fSAMP_CLK = fDIV_CLK. + * | | |01 = fSAMP_CLK = fPROT_CLK. + * | | |10 = fSAMP_CLK = fSCLK. + * | | |11 = fSAMP_CLK = fREF_CLK. + * |[4] |TMCNTEN |Timing Measurement Counter Enable Bit + * | | |This bit enables the 10-bit timing measurement counter. + * | | |0 = Timing measurement counter is Disabled. + * | | |1 = Timing measurement counter is Enabled. + * |[5] |TMCNTSRC |Timing Measurement Counter Clock Source Selection + * | | |0 = Timing measurement counter with fPROT_CLK. + * | | |1 = Timing measurement counter with fDIV_CLK. + * |[9:8] |PDSCNT |Pre-divider for Sample Counter + * | | |This bit field defines the divide ratio of the clock division from sample clock fSAMP_CLK + * | | |The divided frequency fPDS_CNT = fSAMP_CLK / (PDSCNT+1). + * |[14:10] |DSCNT |Denominator for Sample Counter + * | | |This bit field defines the divide ratio of the sample clock fSAMP_CLK. + * | | |The divided frequency fDS_CNT = fPDS_CNT / (DSCNT+1). + * | | |Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value + * |[25:16] |CLKDIV |Clock Divider + * | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ). + * | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled + * | | |The revised value is the average bit time between bit 5 and bit 6 + * | | |The user can use revised CLKDIV and new BRDETITV (UUART_PROTCTL[24:16]) to calculate the precise baud rate. + * @var UUART_T::DATIN0 + * Offset: 0x10 USCI Input Data Signal Configuration Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Signal Synchronization Selection + * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * |[2] |ININV |Input Signal Inverse Selection + * | | |This bit defines the inverter enable of the input asynchronous signal. + * | | |0 = The un-synchronized input signal will not be inverted. + * | | |1 = The un-synchronized input signal will be inverted. + * |[4:3] |EDGEDET |Input Signal Edge Detection Mode + * | | |This bit field selects which edge actives the trigger event of input data signal. + * | | |00 = The trigger event activation is disabled. + * | | |01 = A rising edge activates the trigger event of input data signal. + * | | |10 = A falling edge activates the trigger event of input data signal. + * | | |11 = Both edges activate the trigger event of input data signal. + * | | |Note: In UART function mode, it is suggested to set this bit field as 10. + * @var UUART_T::CTLIN0 + * Offset: 0x20 USCI Input Control Signal Configuration Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Synchronization Signal Selection + * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * |[2] |ININV |Input Signal Inverse Selection + * | | |This bit defines the inverter enable of the input asynchronous signal. + * | | |0 = The un-synchronized input signal will not be inverted. + * | | |1 = The un-synchronized input signal will be inverted. + * @var UUART_T::CLKIN + * Offset: 0x28 USCI Input Clock Signal Configuration Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Synchronization Signal Selection + * | | |This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * @var UUART_T::LINECTL + * Offset: 0x2C USCI Line Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LSB |LSB First Transmission Selection + * | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first. + * | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first. + * |[5] |DATOINV |Data Output Inverse Selection + * | | |This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin. + * | | |0 = The value of USCIx_DAT1 is equal to the data shift register. + * | | |1 = The value of USCIx_DAT1 is the inversion of data shift register. + * |[7] |CTLOINV |Control Signal Output Inverse Selection + * | | |This bit defines the relation between the internal control signal and the output control signal. + * | | |0 = No effect. + * | | |1 = The control signal will be inverted before its output. + * | | |Note: In UART protocol, the control signal means nRTS signal. + * |[11:8] |DWIDTH |Word Length of Transmission + * | | |This bit field defines the data word length (amount of bits) for reception and transmission + * | | |The data word is always right-aligned in the data buffer + * | | |USCI support word length from 4 to 16 bits. + * | | |0x0: The data word contains 16 bits located at bit positions [15:0]. + * | | |0x1: Reserved. + * | | |0x2: Reserved. + * | | |0x3: Reserved. + * | | |0x4: The data word contains 4 bits located at bit positions [3:0]. + * | | |0x5: The data word contains 5 bits located at bit positions [4:0]. + * | | |... + * | | |0xF: The data word contains 15 bits located at bit positions [14:0]. + * | | |Note: In UART protocol, the length can be configured as 6~13 bits. + * @var UUART_T::TXDAT + * Offset: 0x30 USCI Transmit Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TXDAT |Transmit Data + * | | |Software can use this bit field to write 16-bit transmit data for transmission. + * @var UUART_T::RXDAT + * Offset: 0x34 USCI Receive Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RXDAT |Received Data + * | | |This bit field monitors the received data which stored in receive data buffer. + * | | |Note: RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (UUART_PROTSTS[7:5]). + * @var UUART_T::BUFCTL + * Offset: 0x38 USCI Transmit/Receive Buffer Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7] |TXCLR |Clear Transmit Buffer + * | | |0 = No effect. + * | | |1 = The transmit buffer is cleared (filling level is cleared and output pointer is set to input pointer value) + * | | |Should only be used while the buffer is not taking part in data traffic. + * | | |Note: It is cleared automatically after one PCLK cycle. + * |[14] |RXOVIEN |Receive Buffer Overrun Error Interrupt Enable Control + * | | |0 = Receive overrun interrupt Disabled. + * | | |1 = Receive overrun interrupt Enabled. + * |[15] |RXCLR |Clear Receive Buffer + * | | |0 = No effect. + * | | |1 = The receive buffer is cleared (filling level is cleared and output pointer is set to input pointer value) + * | | |Should only be used while the buffer is not taking part in data traffic. + * | | |Note: It is cleared automatically after one PCLK cycle. + * |[16] |TXRST |Transmit Reset + * | | |0 = No effect. + * | | |1 = Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer. + * | | |Note: It is cleared automatically after one PCLK cycle. + * |[17] |RXRST |Receive Reset + * | | |0 = No effect. + * | | |1 = Reset the receive-related counters, state machine, and the content of receive shift register and data buffer. + * | | |Note1: It is cleared automatically after one PCLK cycle. + * | | |Note2: It is suggest to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1. + * @var UUART_T::BUFSTS + * Offset: 0x3C USCI Transmit/Receive Buffer Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXEMPTY |Receive Buffer Empty Indicator + * | | |0 = Receive buffer is not empty. + * | | |1 = Receive buffer is empty. + * |[1] |RXFULL |Receive Buffer Full Indicator + * | | |0 = Receive buffer is not full. + * | | |1 = Receive buffer is full. + * |[3] |RXOVIF |Receive Buffer Over-run Error Interrupt Status + * | | |This bit indicates that a receive buffer overrun error event has been detected + * | | |If RXOVIEN (UUART_BUFCTL[14]) is enabled, the corresponding interrupt request is activated + * | | |It is cleared by software writes 1 to this bit. + * | | |0 = A receive buffer overrun error event has not been detected. + * | | |1 = A receive buffer overrun error event has been detected. + * |[8] |TXEMPTY |Transmit Buffer Empty Indicator + * | | |0 = Transmit buffer is not empty. + * | | |1 = Transmit buffer is empty. + * |[9] |TXFULL |Transmit Buffer Full Indicator + * | | |0 = Transmit buffer is not full. + * | | |1 = Transmit buffer is full. + * |[11] |TXUDRIF |Transmit Buffer Under-run Error Interrupt Status + * | | |This bit indicates that a transmit buffer under-run error event has been detected + * | | |If enabled by TXUDRIEN (UUART_BUFCTL[6]), the corresponding interrupt request is activated + * | | |It is cleared by software writes 1 to this bit + * | | |0 = A transmit buffer under-run error event has not been detected. + * | | |1 = A transmit buffer under-run error event has been detected. + * @var UUART_T::PDMACTL + * Offset: 0x40 USCI PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PDMARST |PDMA Reset + * | | |0 = No effect. + * | | |1 = Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically. + * |[1] |TXPDMAEN |PDMA Transmit Channel Available + * | | |0 = Transmit PDMA function Disabled. + * | | |1 = Transmit PDMA function Enabled. + * |[2] |RXPDMAEN |PDMA Receive Channel Available + * | | |0 = Receive PDMA function Disabled. + * | | |1 = Receive PDMA function Enabled. + * |[3] |PDMAEN |PDMA Mode Enable Bit + * | | |0 = PDMA function Disabled. + * | | |1 = PDMA function Enabled. + * @var UUART_T::WKCTL + * Offset: 0x54 USCI Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Wake-up Enable Bit + * | | |0 = Wake-up function Disabled. + * | | |1 = Wake-up function Enabled. + * |[2] |PDBOPT |Power Down Blocking Option + * | | |0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately. + * | | |1 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately. + * @var UUART_T::WKSTS + * Offset: 0x58 USCI Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKF |Wake-up Flag + * | | |When chip is woken up from Power-down mode, this bit is set to 1 + * | | |Software can write 1 to clear this bit. + * @var UUART_T::PROTCTL + * Offset: 0x5C USCI Protocol Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |STOPB |Stop Bits + * | | |This bit defines the number of stop bits in an UART frame. + * | | |0 = The number of stop bits is 1. + * | | |1 = The number of stop bits is 2. + * |[1] |PARITYEN |Parity Enable Bit + * | | |This bit defines the parity bit is enabled in an UART frame. + * | | |0 = The parity bit Disabled. + * | | |1 = The parity bit Enabled. + * |[2] |EVENPARITY|Even Parity Enable Bit + * | | |0 = Odd number of logic 1 is transmitted and checked in each word. + * | | |1 = Even number of logic 1 is transmitted and checked in each word. + * | | |Note: This bit has effect only when PARITYEN is set. + * |[3] |RTSAUTOEN |nRTS Auto-flow Control Enable Bit + * | | |When nRTS auto-flow is enabled, if the receiver buffer is full (RXFULL (UUART_BUFSTS[1] =1), the UART will de-assert nRTS signal. + * | | |0 = nRTS auto-flow control Disabled. + * | | |1 = nRTS auto-flow control Enabled. + * | | |Note: This bit has effect only when the RTSAUDIREN is not set. + * |[4] |CTSAUTOEN |nCTS Auto-flow Control Enable Bit + * | | |When nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted). + * | | |0 = nCTS auto-flow control Disabled. + * | | |1 = nCTS auto-flow control Enabled. + * |[5] |RTSAUDIREN|nRTS Auto Direction Enable Bit + * | | |When nRTS auto direction is enabled, if the transmitted bytes in the TX buffer is empty, the UART asserted nRTS signal automatically. + * | | |0 = nRTS auto direction control Disabled. + * | | |1 = nRTS auto direction control Enabled. + * | | |Note 1: This bit is used for nRTS auto direction control for RS485. + * | | |Note 2: This bit has effect only when the RTSAUTOEN is not set. + * |[6] |ABREN |Auto-baud Rate Detect Enable Bit + * | | |0 = Auto-baud rate detect function Disabled. + * | | |1 = Auto-baud rate detect function Enabled. + * | | |Note: When the auto - baud rate detect operation finishes, hardware will clear this bit + * | | |The associated interrupt ABRDETIF (UUART_PROTST[9]) will be generated (If ARBIEN (UUART_PROTIEN [1]) is enabled). + * |[9] |DATWKEN |Data Wake-up Mode Enable Bit + * | | |0 = Data wake-up mode Disabled. + * | | |1 = Data wake-up mode Enabled. + * |[10] |CTSWKEN |nCTS Wake-up Mode Enable Bit + * | | |0 = nCTS wake-up mode Disabled. + * | | |1 = nCTS wake-up mode Enabled. + * |[14:11] |WAKECNT |Wake-up Counter + * | | |These bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is wake-up from Power-down mode. + * |[24:16] |BRDETITV |Baud Rate Detection Interval + * | | |This bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits + * | | |The order of the bus shall be 1 and 0 step by step (e.g + * | | |the input data pattern shall be 0x55) + * | | |The user can read the value to know the current input baud rate of the bus whenever the ABRDETIF (UUART_PROTCTL[9]) is set. + * | | |Note: This bit can be cleared to 0 by software writing 1 to the BRDETITV. + * |[26] |STICKEN |Stick Parity Enable Bit + * | | |0 = Stick parity Disabled. + * | | |1 = Stick parity Enabled. + * | | |Note: Refer to RS-485 Support section for detail information. + * |[29] |BCEN |Transmit Break Control Enable Bit + * | | |0 = Transmit Break Control Disabled. + * | | |1 = Transmit Break Control Enabled. + * | | |Note: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0) + * | | |This bit acts only on TX line and has no effect on the transmitter logic. + * |[31] |PROTEN |UART Protocol Enable Bit + * | | |0 = UART Protocol Disabled. + * | | |1 = UART Protocol Enabled. + * @var UUART_T::PROTIEN + * Offset: 0x60 USCI Protocol Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |ABRIEN |Auto-baud Rate Interrupt Enable Bit + * | | |0 = Auto-baud rate interrupt Disabled. + * | | |1 = Auto-baud rate interrupt Enabled. + * |[2] |RLSIEN |Receive Line Status Interrupt Enable Bit + * | | |0 = Receive line status interrupt Disabled. + * | | |1 = Receive line status interrupt Enabled. + * | | |Note: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt. + * @var UUART_T::PROTSTS + * Offset: 0x64 USCI Protocol Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TXSTIF |Transmit Start Interrupt Flag + * | | |0 = A transmit start interrupt status has not occurred. + * | | |1 = A transmit start interrupt status has occurred. + * | | |Note 1: It is cleared by software writing one into this bit. + * | | |Note 2: Used for user to load next transmit data when there is no data in transmit buffer. + * |[2] |TXENDIF |Transmit End Interrupt Flag + * | | |0 = A transmit end interrupt status has not occurred. + * | | |1 = A transmit end interrupt status has occurred. + * | | |Note: It is cleared by software writing one into this bit. + * |[3] |RXSTIF |Receive Start Interrupt Flag + * | | |0 = A receive start interrupt status has not occurred. + * | | |1 = A receive start interrupt status has occurred. + * | | |Note: It is cleared by software writing one into this bit. + * |[4] |RXENDIF |Receive End Interrupt Flag + * | | |0 = A receive finish interrupt status has not occurred. + * | | |1 = A receive finish interrupt status has occurred. + * | | |Note: It is cleared by software writing one into this bit. + * |[5] |PARITYERR |Parity Error Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid "parity bit". + * | | |0 = No parity error is generated. + * | | |1 = Parity error is generated. + * | | |Note: This bit can be cleared by write 1 among the BREAK, FRMERR and PARITYERR bits. + * |[6] |FRMERR |Framing Error Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as logic 0). + * | | |0 = No framing error is generated. + * | | |1 = Framing error is generated. + * | | |Note: This bit can be cleared by write 1 among the BREAK, FRMERR and PARITYERR bits. + * |[7] |BREAK |Break Flag + * | | |This bit is set to logic 1 whenever the received data input (RX) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits). + * | | |0 = No Break is generated. + * | | |1 = Break is generated in the receiver bus. + * | | |Note: This bit can be cleared by write 1 among the BREAK, FRMERR and PARITYERR bits. + * |[9] |ABRDETIF |Auto-baud Rate Interrupt Flag + * | | |This bit is set when auto-baud rate detection is done among the falling edge of the input data + * | | |If the ABRIEN (UUART_PROTCTL[6]) is set, the auto-baud rate interrupt will be generated + * | | |This bit can be set 4 times when the input data pattern is 0x55 and it is cleared before the next falling edge of the input bus. + * | | |0 = Auto-baud rate detect function is not done. + * | | |1 = One Bit auto-baud rate detect function is done. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[10] |RXBUSY |RX Bus Status Flag (Read Only) + * | | |This bit indicates the busy status of the receiver. + * | | |0 = The receiver is Idle. + * | | |1 = The receiver is BUSY. + * |[11] |ABERRSTS |Auto-baud Rate Error Status + * | | |This bit is set when auto-baud rate detection counter overrun + * | | |When the auto-baud rate counter overrun, the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the correct baud rate again. + * | | |0 = Auto-baud rate detect counter is not overrun. + * | | |1 = Auto-baud rate detect counter is overrun. + * | | |Note 1: This bit is set at the same time of ABRDETIF. + * | | |Note 2: This bit can be cleared by writing 1 to ABRDETIF or ABERRSTS. + * |[16] |CTSSYNCLV |nCTS Synchronized Level Status (Read Only) + * | | |This bit used to indicate the current status of the internal synchronized nCTS signal. + * | | |0 = The internal synchronized nCTS is low. + * | | |1 = The internal synchronized nCTS is high. + * |[17] |CTSLV |nCTS Pin Status (Read Only) + * | | |This bit used to monitor the current status of nCTS pin input. + * | | |0 = nCTS pin input is low level voltage logic state. + * | | |1 = nCTS pin input is high level voltage logic state. + */ + __IO uint32_t CTL; /*!< [0x0000] USCI Control Register */ + __IO uint32_t INTEN; /*!< [0x0004] USCI Interrupt Enable Register */ + __IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */ + __I uint32_t RESERVE0[1]; + __IO uint32_t DATIN0; /*!< [0x0010] USCI Input Data Signal Configuration Register 0 */ + __I uint32_t RESERVE1[3]; + __IO uint32_t CTLIN0; /*!< [0x0020] USCI Input Control Signal Configuration Register 0 */ + __I uint32_t RESERVE2[1]; + __IO uint32_t CLKIN; /*!< [0x0028] USCI Input Clock Signal Configuration Register */ + __IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */ + __O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */ + __I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */ + __IO uint32_t BUFCTL; /*!< [0x0038] USCI Transmit/Receive Buffer Control Register */ + __IO uint32_t BUFSTS; /*!< [0x003c] USCI Transmit/Receive Buffer Status Register */ + __IO uint32_t PDMACTL; /*!< [0x0040] USCI PDMA Control Register */ + __I uint32_t RESERVE3[4]; + __IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */ + __IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */ + __IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */ + __IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */ + __IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */ + __I uint32_t RESERVE4[998]; + +} UUART_T; + +/** + @addtogroup UUART_CONST UUART Bit Field Definition + Constant Definitions for UUART Controller +@{ */ + +#define UUART_CTL_FUNMODE_Pos (0) /*!< UUART_T::CTL: FUNMODE Position */ +#define UUART_CTL_FUNMODE_Msk (0x7ul << UUART_CTL_FUNMODE_Pos) /*!< UUART_T::CTL: FUNMODE Mask */ + +#define UUART_INTEN_TXSTIEN_Pos (1) /*!< UUART_T::INTEN: TXSTIEN Position */ +#define UUART_INTEN_TXSTIEN_Msk (0x1ul << UUART_INTEN_TXSTIEN_Pos) /*!< UUART_T::INTEN: TXSTIEN Mask */ + +#define UUART_INTEN_TXENDIEN_Pos (2) /*!< UUART_T::INTEN: TXENDIEN Position */ +#define UUART_INTEN_TXENDIEN_Msk (0x1ul << UUART_INTEN_TXENDIEN_Pos) /*!< UUART_T::INTEN: TXENDIEN Mask */ + +#define UUART_INTEN_RXSTIEN_Pos (3) /*!< UUART_T::INTEN: RXSTIEN Position */ +#define UUART_INTEN_RXSTIEN_Msk (0x1ul << UUART_INTEN_RXSTIEN_Pos) /*!< UUART_T::INTEN: RXSTIEN Mask */ + +#define UUART_INTEN_RXENDIEN_Pos (4) /*!< UUART_T::INTEN: RXENDIEN Position */ +#define UUART_INTEN_RXENDIEN_Msk (0x1ul << UUART_INTEN_RXENDIEN_Pos) /*!< UUART_T::INTEN: RXENDIEN Mask */ + +#define UUART_BRGEN_RCLKSEL_Pos (0) /*!< UUART_T::BRGEN: RCLKSEL Position */ +#define UUART_BRGEN_RCLKSEL_Msk (0x1ul << UUART_BRGEN_RCLKSEL_Pos) /*!< UUART_T::BRGEN: RCLKSEL Mask */ + +#define UUART_BRGEN_PTCLKSEL_Pos (1) /*!< UUART_T::BRGEN: PTCLKSEL Position */ +#define UUART_BRGEN_PTCLKSEL_Msk (0x1ul << UUART_BRGEN_PTCLKSEL_Pos) /*!< UUART_T::BRGEN: PTCLKSEL Mask */ + +#define UUART_BRGEN_SPCLKSEL_Pos (2) /*!< UUART_T::BRGEN: SPCLKSEL Position */ +#define UUART_BRGEN_SPCLKSEL_Msk (0x3ul << UUART_BRGEN_SPCLKSEL_Pos) /*!< UUART_T::BRGEN: SPCLKSEL Mask */ + +#define UUART_BRGEN_TMCNTEN_Pos (4) /*!< UUART_T::BRGEN: TMCNTEN Position */ +#define UUART_BRGEN_TMCNTEN_Msk (0x1ul << UUART_BRGEN_TMCNTEN_Pos) /*!< UUART_T::BRGEN: TMCNTEN Mask */ + +#define UUART_BRGEN_TMCNTSRC_Pos (5) /*!< UUART_T::BRGEN: TMCNTSRC Position */ +#define UUART_BRGEN_TMCNTSRC_Msk (0x1ul << UUART_BRGEN_TMCNTSRC_Pos) /*!< UUART_T::BRGEN: TMCNTSRC Mask */ + +#define UUART_BRGEN_PDSCNT_Pos (8) /*!< UUART_T::BRGEN: PDSCNT Position */ +#define UUART_BRGEN_PDSCNT_Msk (0x3ul << UUART_BRGEN_PDSCNT_Pos) /*!< UUART_T::BRGEN: PDSCNT Mask */ + +#define UUART_BRGEN_DSCNT_Pos (10) /*!< UUART_T::BRGEN: DSCNT Position */ +#define UUART_BRGEN_DSCNT_Msk (0x1ful << UUART_BRGEN_DSCNT_Pos) /*!< UUART_T::BRGEN: DSCNT Mask */ + +#define UUART_BRGEN_CLKDIV_Pos (16) /*!< UUART_T::BRGEN: CLKDIV Position */ +#define UUART_BRGEN_CLKDIV_Msk (0x3fful << UUART_BRGEN_CLKDIV_Pos) /*!< UUART_T::BRGEN: CLKDIV Mask */ + +#define UUART_DATIN0_SYNCSEL_Pos (0) /*!< UUART_T::DATIN0: SYNCSEL Position */ +#define UUART_DATIN0_SYNCSEL_Msk (0x1ul << UUART_DATIN0_SYNCSEL_Pos) /*!< UUART_T::DATIN0: SYNCSEL Mask */ + +#define UUART_DATIN0_ININV_Pos (2) /*!< UUART_T::DATIN0: ININV Position */ +#define UUART_DATIN0_ININV_Msk (0x1ul << UUART_DATIN0_ININV_Pos) /*!< UUART_T::DATIN0: ININV Mask */ + +#define UUART_DATIN0_EDGEDET_Pos (3) /*!< UUART_T::DATIN0: EDGEDET Position */ +#define UUART_DATIN0_EDGEDET_Msk (0x3ul << UUART_DATIN0_EDGEDET_Pos) /*!< UUART_T::DATIN0: EDGEDET Mask */ + +#define UUART_CTLIN0_SYNCSEL_Pos (0) /*!< UUART_T::CTLIN0: SYNCSEL Position */ +#define UUART_CTLIN0_SYNCSEL_Msk (0x1ul << UUART_CTLIN0_SYNCSEL_Pos) /*!< UUART_T::CTLIN0: SYNCSEL Mask */ + +#define UUART_CTLIN0_ININV_Pos (2) /*!< UUART_T::CTLIN0: ININV Position */ +#define UUART_CTLIN0_ININV_Msk (0x1ul << UUART_CTLIN0_ININV_Pos) /*!< UUART_T::CTLIN0: ININV Mask */ + +#define UUART_CLKIN_SYNCSEL_Pos (0) /*!< UUART_T::CLKIN: SYNCSEL Position */ +#define UUART_CLKIN_SYNCSEL_Msk (0x1ul << UUART_CLKIN_SYNCSEL_Pos) /*!< UUART_T::CLKIN: SYNCSEL Mask */ + +#define UUART_LINECTL_LSB_Pos (0) /*!< UUART_T::LINECTL: LSB Position */ +#define UUART_LINECTL_LSB_Msk (0x1ul << UUART_LINECTL_LSB_Pos) /*!< UUART_T::LINECTL: LSB Mask */ + +#define UUART_LINECTL_DATOINV_Pos (5) /*!< UUART_T::LINECTL: DATOINV Position */ +#define UUART_LINECTL_DATOINV_Msk (0x1ul << UUART_LINECTL_DATOINV_Pos) /*!< UUART_T::LINECTL: DATOINV Mask */ + +#define UUART_LINECTL_CTLOINV_Pos (7) /*!< UUART_T::LINECTL: CTLOINV Position */ +#define UUART_LINECTL_CTLOINV_Msk (0x1ul << UUART_LINECTL_CTLOINV_Pos) /*!< UUART_T::LINECTL: CTLOINV Mask */ + +#define UUART_LINECTL_DWIDTH_Pos (8) /*!< UUART_T::LINECTL: DWIDTH Position */ +#define UUART_LINECTL_DWIDTH_Msk (0xful << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_T::LINECTL: DWIDTH Mask */ + +#define UUART_TXDAT_TXDAT_Pos (0) /*!< UUART_T::TXDAT: TXDAT Position */ +#define UUART_TXDAT_TXDAT_Msk (0xfffful << UUART_TXDAT_TXDAT_Pos) /*!< UUART_T::TXDAT: TXDAT Mask */ + +#define UUART_RXDAT_RXDAT_Pos (0) /*!< UUART_T::RXDAT: RXDAT Position */ +#define UUART_RXDAT_RXDAT_Msk (0xfffful << UUART_RXDAT_RXDAT_Pos) /*!< UUART_T::RXDAT: RXDAT Mask */ + +#define UUART_BUFCTL_TXCLR_Pos (7) /*!< UUART_T::BUFCTL: TXCLR Position */ +#define UUART_BUFCTL_TXCLR_Msk (0x1ul << UUART_BUFCTL_TXCLR_Pos) /*!< UUART_T::BUFCTL: TXCLR Mask */ + +#define UUART_BUFCTL_RXOVIEN_Pos (14) /*!< UUART_T::BUFCTL: RXOVIEN Position */ +#define UUART_BUFCTL_RXOVIEN_Msk (0x1ul << UUART_BUFCTL_RXOVIEN_Pos) /*!< UUART_T::BUFCTL: RXOVIEN Mask */ + +#define UUART_BUFCTL_RXCLR_Pos (15) /*!< UUART_T::BUFCTL: RXCLR Position */ +#define UUART_BUFCTL_RXCLR_Msk (0x1ul << UUART_BUFCTL_RXCLR_Pos) /*!< UUART_T::BUFCTL: RXCLR Mask */ + +#define UUART_BUFCTL_TXRST_Pos (16) /*!< UUART_T::BUFCTL: TXRST Position */ +#define UUART_BUFCTL_TXRST_Msk (0x1ul << UUART_BUFCTL_TXRST_Pos) /*!< UUART_T::BUFCTL: TXRST Mask */ + +#define UUART_BUFCTL_RXRST_Pos (17) /*!< UUART_T::BUFCTL: RXRST Position */ +#define UUART_BUFCTL_RXRST_Msk (0x1ul << UUART_BUFCTL_RXRST_Pos) /*!< UUART_T::BUFCTL: RXRST Mask */ + +#define UUART_BUFSTS_RXEMPTY_Pos (0) /*!< UUART_T::BUFSTS: RXEMPTY Position */ +#define UUART_BUFSTS_RXEMPTY_Msk (0x1ul << UUART_BUFSTS_RXEMPTY_Pos) /*!< UUART_T::BUFSTS: RXEMPTY Mask */ + +#define UUART_BUFSTS_RXFULL_Pos (1) /*!< UUART_T::BUFSTS: RXFULL Position */ +#define UUART_BUFSTS_RXFULL_Msk (0x1ul << UUART_BUFSTS_RXFULL_Pos) /*!< UUART_T::BUFSTS: RXFULL Mask */ + +#define UUART_BUFSTS_RXOVIF_Pos (3) /*!< UUART_T::BUFSTS: RXOVIF Position */ +#define UUART_BUFSTS_RXOVIF_Msk (0x1ul << UUART_BUFSTS_RXOVIF_Pos) /*!< UUART_T::BUFSTS: RXOVIF Mask */ + +#define UUART_BUFSTS_TXEMPTY_Pos (8) /*!< UUART_T::BUFSTS: TXEMPTY Position */ +#define UUART_BUFSTS_TXEMPTY_Msk (0x1ul << UUART_BUFSTS_TXEMPTY_Pos) /*!< UUART_T::BUFSTS: TXEMPTY Mask */ + +#define UUART_BUFSTS_TXFULL_Pos (9) /*!< UUART_T::BUFSTS: TXFULL Position */ +#define UUART_BUFSTS_TXFULL_Msk (0x1ul << UUART_BUFSTS_TXFULL_Pos) /*!< UUART_T::BUFSTS: TXFULL Mask */ + +#define UUART_BUFSTS_TXUDRIF_Pos (11) /*!< UUART_T::BUFSTS: TXUDRIF Position */ +#define UUART_BUFSTS_TXUDRIF_Msk (0x1ul << UUART_BUFSTS_TXUDRIF_Pos) /*!< UUART_T::BUFSTS: TXUDRIF Mask */ + +#define UUART_PDMACTL_PDMARST_Pos (0) /*!< UUART_T::PDMACTL: PDMARST Position */ +#define UUART_PDMACTL_PDMARST_Msk (0x1ul << UUART_PDMACTL_PDMARST_Pos) /*!< UUART_T::PDMACTL: PDMARST Mask */ + +#define UUART_PDMACTL_TXPDMAEN_Pos (1) /*!< UUART_T::PDMACTL: TXPDMAEN Position */ +#define UUART_PDMACTL_TXPDMAEN_Msk (0x1ul << UUART_PDMACTL_TXPDMAEN_Pos) /*!< UUART_T::PDMACTL: TXPDMAEN Mask */ + +#define UUART_PDMACTL_RXPDMAEN_Pos (2) /*!< UUART_T::PDMACTL: RXPDMAEN Position */ +#define UUART_PDMACTL_RXPDMAEN_Msk (0x1ul << UUART_PDMACTL_RXPDMAEN_Pos) /*!< UUART_T::PDMACTL: RXPDMAEN Mask */ + +#define UUART_PDMACTL_PDMAEN_Pos (3) /*!< UUART_T::PDMACTL: PDMAEN Position */ +#define UUART_PDMACTL_PDMAEN_Msk (0x1ul << UUART_PDMACTL_PDMAEN_Pos) /*!< UUART_T::PDMACTL: PDMAEN Mask */ + +#define UUART_WKCTL_WKEN_Pos (0) /*!< UUART_T::WKCTL: WKEN Position */ +#define UUART_WKCTL_WKEN_Msk (0x1ul << UUART_WKCTL_WKEN_Pos) /*!< UUART_T::WKCTL: WKEN Mask */ + +#define UUART_WKCTL_PDBOPT_Pos (2) /*!< UUART_T::WKCTL: PDBOPT Position */ +#define UUART_WKCTL_PDBOPT_Msk (0x1ul << UUART_WKCTL_PDBOPT_Pos) /*!< UUART_T::WKCTL: PDBOPT Mask */ + +#define UUART_WKSTS_WKF_Pos (0) /*!< UUART_T::WKSTS: WKF Position */ +#define UUART_WKSTS_WKF_Msk (0x1ul << UUART_WKSTS_WKF_Pos) /*!< UUART_T::WKSTS: WKF Mask */ + +#define UUART_PROTCTL_STOPB_Pos (0) /*!< UUART_T::PROTCTL: STOPB Position */ +#define UUART_PROTCTL_STOPB_Msk (0x1ul << UUART_PROTCTL_STOPB_Pos) /*!< UUART_T::PROTCTL: STOPB Mask */ + +#define UUART_PROTCTL_PARITYEN_Pos (1) /*!< UUART_T::PROTCTL: PARITYEN Position */ +#define UUART_PROTCTL_PARITYEN_Msk (0x1ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_T::PROTCTL: PARITYEN Mask */ + +#define UUART_PROTCTL_EVENPARITY_Pos (2) /*!< UUART_T::PROTCTL: EVENPARITY Position */ +#define UUART_PROTCTL_EVENPARITY_Msk (0x1ul << UUART_PROTCTL_EVENPARITY_Pos) /*!< UUART_T::PROTCTL: EVENPARITY Mask */ + +#define UUART_PROTCTL_RTSAUTOEN_Pos (3) /*!< UUART_T::PROTCTL: RTSAUTOEN Position */ +#define UUART_PROTCTL_RTSAUTOEN_Msk (0x1ul << UUART_PROTCTL_RTSAUTOEN_Pos) /*!< UUART_T::PROTCTL: RTSAUTOEN Mask */ + +#define UUART_PROTCTL_CTSAUTOEN_Pos (4) /*!< UUART_T::PROTCTL: CTSAUTOEN Position */ +#define UUART_PROTCTL_CTSAUTOEN_Msk (0x1ul << UUART_PROTCTL_CTSAUTOEN_Pos) /*!< UUART_T::PROTCTL: CTSAUTOEN Mask */ + +#define UUART_PROTCTL_RTSAUDIREN_Pos (5) /*!< UUART_T::PROTCTL: RTSAUDIREN Position */ +#define UUART_PROTCTL_RTSAUDIREN_Msk (0x1ul << UUART_PROTCTL_RTSAUDIREN_Pos) /*!< UUART_T::PROTCTL: RTSAUDIREN Mask */ + +#define UUART_PROTCTL_ABREN_Pos (6) /*!< UUART_T::PROTCTL: ABREN Position */ +#define UUART_PROTCTL_ABREN_Msk (0x1ul << UUART_PROTCTL_ABREN_Pos) /*!< UUART_T::PROTCTL: ABREN Mask */ + +#define UUART_PROTCTL_DATWKEN_Pos (9) /*!< UUART_T::PROTCTL: DATWKEN Position */ +#define UUART_PROTCTL_DATWKEN_Msk (0x1ul << UUART_PROTCTL_DATWKEN_Pos) /*!< UUART_T::PROTCTL: DATWKEN Mask */ + +#define UUART_PROTCTL_CTSWKEN_Pos (10) /*!< UUART_T::PROTCTL: CTSWKEN Position */ +#define UUART_PROTCTL_CTSWKEN_Msk (0x1ul << UUART_PROTCTL_CTSWKEN_Pos) /*!< UUART_T::PROTCTL: CTSWKEN Mask */ + +#define UUART_PROTCTL_WAKECNT_Pos (11) /*!< UUART_T::PROTCTL: WAKECNT Position */ +#define UUART_PROTCTL_WAKECNT_Msk (0xful << UUART_PROTCTL_WAKECNT_Pos) /*!< UUART_T::PROTCTL: WAKECNT Mask */ + +#define UUART_PROTCTL_BRDETITV_Pos (16) /*!< UUART_T::PROTCTL: BRDETITV Position */ +#define UUART_PROTCTL_BRDETITV_Msk (0x1fful << UUART_PROTCTL_BRDETITV_Pos) /*!< UUART_T::PROTCTL: BRDETITV Mask */ + +#define UUART_PROTCTL_STICKEN_Pos (26) /*!< UUART_T::PROTCTL: STICKEN Position */ +#define UUART_PROTCTL_STICKEN_Msk (0x1ul << UUART_PROTCTL_STICKEN_Pos) /*!< UUART_T::PROTCTL: STICKEN Mask */ + +#define UUART_PROTCTL_BCEN_Pos (29) /*!< UUART_T::PROTCTL: BCEN Position */ +#define UUART_PROTCTL_BCEN_Msk (0x1ul << UUART_PROTCTL_BCEN_Pos) /*!< UUART_T::PROTCTL: BCEN Mask */ + +#define UUART_PROTCTL_PROTEN_Pos (31) /*!< UUART_T::PROTCTL: PROTEN Position */ +#define UUART_PROTCTL_PROTEN_Msk (0x1ul << UUART_PROTCTL_PROTEN_Pos) /*!< UUART_T::PROTCTL: PROTEN Mask */ + +#define UUART_PROTIEN_ABRIEN_Pos (1) /*!< UUART_T::PROTIEN: ABRIEN Position */ +#define UUART_PROTIEN_ABRIEN_Msk (0x1ul << UUART_PROTIEN_ABRIEN_Pos) /*!< UUART_T::PROTIEN: ABRIEN Mask */ + +#define UUART_PROTIEN_RLSIEN_Pos (2) /*!< UUART_T::PROTIEN: RLSIEN Position */ +#define UUART_PROTIEN_RLSIEN_Msk (0x1ul << UUART_PROTIEN_RLSIEN_Pos) /*!< UUART_T::PROTIEN: RLSIEN Mask */ + +#define UUART_PROTSTS_TXSTIF_Pos (1) /*!< UUART_T::PROTSTS: TXSTIF Position */ +#define UUART_PROTSTS_TXSTIF_Msk (0x1ul << UUART_PROTSTS_TXSTIF_Pos) /*!< UUART_T::PROTSTS: TXSTIF Mask */ + +#define UUART_PROTSTS_TXENDIF_Pos (2) /*!< UUART_T::PROTSTS: TXENDIF Position */ +#define UUART_PROTSTS_TXENDIF_Msk (0x1ul << UUART_PROTSTS_TXENDIF_Pos) /*!< UUART_T::PROTSTS: TXENDIF Mask */ + +#define UUART_PROTSTS_RXSTIF_Pos (3) /*!< UUART_T::PROTSTS: RXSTIF Position */ +#define UUART_PROTSTS_RXSTIF_Msk (0x1ul << UUART_PROTSTS_RXSTIF_Pos) /*!< UUART_T::PROTSTS: RXSTIF Mask */ + +#define UUART_PROTSTS_RXENDIF_Pos (4) /*!< UUART_T::PROTSTS: RXENDIF Position */ +#define UUART_PROTSTS_RXENDIF_Msk (0x1ul << UUART_PROTSTS_RXENDIF_Pos) /*!< UUART_T::PROTSTS: RXENDIF Mask */ + +#define UUART_PROTSTS_PARITYERR_Pos (5) /*!< UUART_T::PROTSTS: PARITYERR Position */ +#define UUART_PROTSTS_PARITYERR_Msk (0x1ul << UUART_PROTSTS_PARITYERR_Pos) /*!< UUART_T::PROTSTS: PARITYERR Mask */ + +#define UUART_PROTSTS_FRMERR_Pos (6) /*!< UUART_T::PROTSTS: FRMERR Position */ +#define UUART_PROTSTS_FRMERR_Msk (0x1ul << UUART_PROTSTS_FRMERR_Pos) /*!< UUART_T::PROTSTS: FRMERR Mask */ + +#define UUART_PROTSTS_BREAK_Pos (7) /*!< UUART_T::PROTSTS: BREAK Position */ +#define UUART_PROTSTS_BREAK_Msk (0x1ul << UUART_PROTSTS_BREAK_Pos) /*!< UUART_T::PROTSTS: BREAK Mask */ + +#define UUART_PROTSTS_ABRDETIF_Pos (9) /*!< UUART_T::PROTSTS: ABRDETIF Position */ +#define UUART_PROTSTS_ABRDETIF_Msk (0x1ul << UUART_PROTSTS_ABRDETIF_Pos) /*!< UUART_T::PROTSTS: ABRDETIF Mask */ + +#define UUART_PROTSTS_RXBUSY_Pos (10) /*!< UUART_T::PROTSTS: RXBUSY Position */ +#define UUART_PROTSTS_RXBUSY_Msk (0x1ul << UUART_PROTSTS_RXBUSY_Pos) /*!< UUART_T::PROTSTS: RXBUSY Mask */ + +#define UUART_PROTSTS_ABERRSTS_Pos (11) /*!< UUART_T::PROTSTS: ABERRSTS Position */ +#define UUART_PROTSTS_ABERRSTS_Msk (0x1ul << UUART_PROTSTS_ABERRSTS_Pos) /*!< UUART_T::PROTSTS: ABERRSTS Mask */ + +#define UUART_PROTSTS_CTSSYNCLV_Pos (16) /*!< UUART_T::PROTSTS: CTSSYNCLV Position */ +#define UUART_PROTSTS_CTSSYNCLV_Msk (0x1ul << UUART_PROTSTS_CTSSYNCLV_Pos) /*!< UUART_T::PROTSTS: CTSSYNCLV Mask */ + +#define UUART_PROTSTS_CTSLV_Pos (17) /*!< UUART_T::PROTSTS: CTSLV Position */ +#define UUART_PROTSTS_CTSLV_Msk (0x1ul << UUART_PROTSTS_CTSLV_Pos) /*!< UUART_T::PROTSTS: CTSLV Mask */ + +/**@}*/ /* UUART_CONST */ +/**@}*/ /* end of UUART register group */ + + +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __UUART_REG_H__ */ \ No newline at end of file diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/wdt_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/wdt_reg.h new file mode 100644 index 00000000000..319e925a531 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/wdt_reg.h @@ -0,0 +1,169 @@ +/**************************************************************************//** + * @file wdt_reg.h + * @version V1.00 + * @brief WDT register definition header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __WDT_REG_H__ +#define __WDT_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup WDT Watch Dog Timer Controller (WDT) + Memory Mapped Structure for WDT Controller +@{ */ + +typedef struct +{ + + + /** + * @var WDT_T::CTL + * Offset: 0x00 WDT Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |RSTEN |WDT Time-out Reset Enable Bit (Write Protect) + * | | |Setting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires. + * | | |0 = WDT time-out reset function Disabled. + * | | |1 = WDT time-out reset function Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[2] |RSTF |WDT Time-out Reset Flag + * | | |This bit indicates the system has been reset by WDT time-out reset or not. + * | | |0 = WDT time-out reset did not occur. + * | | |1 = WDT time-out reset occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * |[3] |IF |WDT Time-out Interrupt Flag + * | | |This bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval + * | | |0 = WDT time-out interrupt did not occur. + * | | |1 = WDT time-out interrupt occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * |[4] |WKEN |WDT Time-out Wake-up Function Control (Write Protect) + * | | |If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip. + * | | |0 = Wake-up trigger event Disabled if WDT time-out interrupt signal generated. + * | | |1 = Wake-up trigger event Enabled if WDT time-out interrupt signal generated. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: Chip can be woken up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz internal low speed RC oscillator (LIRC) or LXT. + * |[5] |WKF |WDT Time-out Wake-up Flag (Write Protect) + * | | |This bit indicates the interrupt wake-up flag status of WDT + * | | |0 = WDT does not cause chip wake-up. + * | | |1 = Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: This bit is cleared by writing 1 to it. + * |[6] |INTEN |WDT Time-out Interrupt Enable Bit (Write Protect) + * | | |If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU. + * | | |0 = WDT time-out interrupt Disabled. + * | | |1 = WDT time-out interrupt Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[7] |WDTEN |WDT Enable Bit (Write Protect) + * | | |0 = WDT Disabled (This action will reset the internal up counter value). + * | | |1 = WDT Enabled. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configured to 111, this bit is forced as 1 and user cannot change this bit to 0. + * |[11:8] |TOUTSEL |WDT Time-out Interval Selection (Write Protect) + * | | |These four bits select the time-out interval period for the WDT. + * | | |0000 = 2^4 * WDT_CLK. + * | | |0001 = 2^6 * WDT_CLK. + * | | |0010 = 2^8 * WDT_CLK. + * | | |0011 = 2^10 * WDT_CLK. + * | | |0100 = 2^12 * WDT_CLK. + * | | |0101 = 2^14 * WDT_CLK. + * | | |0110 = 2^16 * WDT_CLK. + * | | |0111 = 2^18 * WDT_CLK. + * | | |1000 = 2^20 * WDT_CLK. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[30] |SYNC |WDT Enable Control SYNC Flag Indicator (Read Only) + * | | |If user executes enable/disable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is completed or not. + * | | |0 = Set WDTEN bit is completed. + * | | |1 = Set WDTEN bit is synchronizing and not become active yet. + * | | |Note: Performing enable or disable WDTEN bit needs 2 * WDT_CLK period to become active. + * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Bit (Write Protect) + * | | |0 = ICE debug mode acknowledgement affects WDT counting. + * | | |WDT up counter will be held while CPU is held by ICE. + * | | |1 = ICE debug mode acknowledgement Disabled. + * | | |WDT up counter will keep going no matter CPU is held by ICE or not. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var WDT_T::ALTCTL + * Offset: 0x04 WDT Alternative Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |RSTDSEL |WDT Reset Delay Selection (Write Protect) + * | | |When WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by writing 0x00005aa5 to RSTCNT (WDT_RSTCNT[31:0]) to prevent WDT time-out reset happened. + * | | |User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period. + * | | |00 = WDT Reset Delay Period is 1026 * WDT_CLK. + * | | |01 = WDT Reset Delay Period is 130 * WDT_CLK. + * | | |10 = WDT Reset Delay Period is 18 * WDT_CLK. + * | | |11 = WDT Reset Delay Period is 3 * WDT_CLK. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: This register will be reset to 0 if WDT time-out reset happened. + * @var WDT_T::RSTCNT + * Offset: 0x08 WDT Reset Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RSTCNT |WDT Reset Counter Register + * | | |Writing 0x00005AA5 to this field will reset the internal 18-bit WDT up counter value to 0. + * | | |Note1: Performing RSTCNT to reset counter needs 2 * WDT_CLK period to become active. + */ + __IO uint32_t CTL; /*!< [0x0000] WDT Control Register */ + __IO uint32_t ALTCTL; /*!< [0x0004] WDT Alternative Control Register */ + __O uint32_t RSTCNT; /*!< [0x0008] WDT Reset Counter Register */ +} WDT_T; + +/** + @addtogroup WDT_CONST WDT Bit Field Definition + Constant Definitions for WDT Controller +@{ */ + +#define WDT_CTL_RSTEN_Pos (1) /*!< WDT_T::CTL: RSTEN Position */ +#define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos) /*!< WDT_T::CTL: RSTEN Mask */ + +#define WDT_CTL_RSTF_Pos (2) /*!< WDT_T::CTL: RSTF Position */ +#define WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos) /*!< WDT_T::CTL: RSTF Mask */ + +#define WDT_CTL_IF_Pos (3) /*!< WDT_T::CTL: IF Position */ +#define WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos) /*!< WDT_T::CTL: IF Mask */ + +#define WDT_CTL_WKEN_Pos (4) /*!< WDT_T::CTL: WKEN Position */ +#define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos) /*!< WDT_T::CTL: WKEN Mask */ + +#define WDT_CTL_WKF_Pos (5) /*!< WDT_T::CTL: WKF Position */ +#define WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos) /*!< WDT_T::CTL: WKF Mask */ + +#define WDT_CTL_INTEN_Pos (6) /*!< WDT_T::CTL: INTEN Position */ +#define WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos) /*!< WDT_T::CTL: INTEN Mask */ + +#define WDT_CTL_WDTEN_Pos (7) /*!< WDT_T::CTL: WDTEN Position */ +#define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos) /*!< WDT_T::CTL: WDTEN Mask */ + +#define WDT_CTL_TOUTSEL_Pos (8) /*!< WDT_T::CTL: TOUTSEL Position */ +#define WDT_CTL_TOUTSEL_Msk (0xful << WDT_CTL_TOUTSEL_Pos) /*!< WDT_T::CTL: TOUTSEL Mask */ + +#define WDT_CTL_SYNC_Pos (30) /*!< WDT_T::CTL: SYNC Position */ +#define WDT_CTL_SYNC_Msk (0x1ul << WDT_CTL_SYNC_Pos) /*!< WDT_T::CTL: SYNC Mask */ + +#define WDT_CTL_ICEDEBUG_Pos (31) /*!< WDT_T::CTL: ICEDEBUG Position */ +#define WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos) /*!< WDT_T::CTL: ICEDEBUG Mask */ + +#define WDT_ALTCTL_RSTDSEL_Pos (0) /*!< WDT_T::ALTCTL: RSTDSEL Position */ +#define WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT_T::ALTCTL: RSTDSEL Mask */ + +/**@}*/ /* WDT_CONST */ +/**@}*/ /* end of WDT register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __WDT_REG_H__ */ \ No newline at end of file diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/wwdt_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/wwdt_reg.h new file mode 100644 index 00000000000..8f3ab94477b --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/wwdt_reg.h @@ -0,0 +1,146 @@ +/**************************************************************************//** + * @file wwdt_reg.h + * @version V1.00 + * @brief WWDT register definition header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __WWDT_REG_H__ +#define __WWDT_REG_H__ + +#if defined ( __CC_ARM ) + #pragma anon_unions +#endif + +/** + @addtogroup REGISTER Control Register + @{ +*/ + +/** + @addtogroup WWDT Window Watchdog Timer (WWDT) + Memory Mapped Structure for WWDT Controller +@{ */ + +typedef struct +{ + + + /** + * @var WWDT_T::RLDCNT + * Offset: 0x00 WWDT Reload Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RLDCNT |WWDT Reload Counter Register + * | | |Writing 0x00005AA5 to this register will reload the WWDT counter value to 0x3F. + * | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT (WWDT_CTL[21:16]) + * | | |If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT, WWDT reset signal will be generated immediately. + * @var WWDT_T::CTL + * Offset: 0x04 WWDT Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WWDTEN |WWDT Enable Bit + * | | |0 = WWDT counter is stopped. + * | | |1 = WWDT counter starts counting. + * |[1] |INTEN |WWDT Interrupt Enable Bit + * | | |If this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU. + * | | |0 = WWDT counter compare match interrupt Disabled. + * | | |1 = WWDT counter compare match interrupt Enabled. + * |[11:8] |PSCSEL |WWDT Counter Prescale Period Selection + * | | |0000 = Pre-scale is 1; Max time-out period is 1 * 64 * WWDT_CLK. + * | | |0001 = Pre-scale is 2; Max time-out period is 2 * 64 * WWDT_CLK. + * | | |0010 = Pre-scale is 4; Max time-out period is 4 * 64 * WWDT_CLK. + * | | |0011 = Pre-scale is 8; Max time-out period is 8 * 64 * WWDT_CLK. + * | | |0100 = Pre-scale is 16; Max time-out period is 16 * 64 * WWDT_CLK. + * | | |0101 = Pre-scale is 32; Max time-out period is 32 * 64 * WWDT_CLK. + * | | |0110 = Pre-scale is 64; Max time-out period is 64 * 64 * WWDT_CLK. + * | | |0111 = Pre-scale is 128; Max time-out period is 128 * 64 * WWDT_CLK. + * | | |1000 = Pre-scale is 192; Max time-out period is 192 * 64 * WWDT_CLK. + * | | |1001 = Pre-scale is 256; Max time-out period is 256 * 64 * WWDT_CLK. + * | | |1010 = Pre-scale is 384; Max time-out period is 384 * 64 * WWDT_CLK. + * | | |1011 = Pre-scale is 512; Max time-out period is 512 * 64 * WWDT_CLK. + * | | |1100 = Pre-scale is 768; Max time-out period is 768 * 64 * WWDT_CLK. + * | | |1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * WWDT_CLK. + * | | |1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * WWDT_CLK. + * | | |1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * WWDT_CLK. + * |[21:16] |CMPDAT |WWDT Window Compare Register + * | | |Set this register to adjust the valid reload window. + * | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT + * | | |If user writes WWDT_RLDCNT register when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate immediately. + * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Bit + * | | |0 = ICE debug mode acknowledgement effects WWDT counting. + * | | |WWDT down counter will be held while CPU is held by ICE. + * | | |1 = ICE debug mode acknowledgement Disabled. + * | | |Note: WWDT down counter will keep going no matter CPU is held by ICE or not. + * @var WWDT_T::STATUS + * Offset: 0x08 WWDT Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WWDTIF |WWDT Compare Match Interrupt Flag + * | | |This bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]). + * | | |0 = No effect. + * | | |1 = WWDT counter value matches CMPDAT. + * | | |Note: This bit is cleared by writing 1 to it. + * |[1] |WWDTRF |WWDT Timer-out Reset Flag + * | | |This bit indicates the system has been reset by WWDT time-out reset or not. + * | | |0 = WWDT time-out reset did not occur. + * | | |1 = WWDT time-out reset occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * @var WWDT_T::CNT + * Offset: 0x0C WWDT Counter Value Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |CNTDAT |WWDT Counter Value + * | | |CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value. + */ + __O uint32_t RLDCNT; /*!< [0x0000] WWDT Reload Counter Register */ + __IO uint32_t CTL; /*!< [0x0004] WWDT Control Register */ + __IO uint32_t STATUS; /*!< [0x0008] WWDT Status Register */ + __I uint32_t CNT; /*!< [0x000c] WWDT Counter Value Register */ +} WWDT_T; + +/** + @addtogroup WWDT_CONST WWDT Bit Field Definition + Constant Definitions for WWDT Controller +@{ */ + +#define WWDT_RLDCNT_RLDCNT_Pos (0) /*!< WWDT_T::RLDCNT: RLDCNT Position */ +#define WWDT_RLDCNT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_RLDCNT_Pos) /*!< WWDT_T::RLDCNT: RLDCNT Mask */ + +#define WWDT_CTL_WWDTEN_Pos (0) /*!< WWDT_T::CTL: WWDTEN Position */ +#define WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos) /*!< WWDT_T::CTL: WWDTEN Mask */ + +#define WWDT_CTL_INTEN_Pos (1) /*!< WWDT_T::CTL: INTEN Position */ +#define WWDT_CTL_INTEN_Msk (0x1ul << WWDT_CTL_INTEN_Pos) /*!< WWDT_T::CTL: INTEN Mask */ + +#define WWDT_CTL_PSCSEL_Pos (8) /*!< WWDT_T::CTL: PSCSEL Position */ +#define WWDT_CTL_PSCSEL_Msk (0xful << WWDT_CTL_PSCSEL_Pos) /*!< WWDT_T::CTL: PSCSEL Mask */ + +#define WWDT_CTL_CMPDAT_Pos (16) /*!< WWDT_T::CTL: CMPDAT Position */ +#define WWDT_CTL_CMPDAT_Msk (0x3ful << WWDT_CTL_CMPDAT_Pos) /*!< WWDT_T::CTL: CMPDAT Mask */ + +#define WWDT_CTL_ICEDEBUG_Pos (31) /*!< WWDT_T::CTL: ICEDEBUG Position */ +#define WWDT_CTL_ICEDEBUG_Msk (0x1ul << WWDT_CTL_ICEDEBUG_Pos) /*!< WWDT_T::CTL: ICEDEBUG Mask */ + +#define WWDT_STATUS_WWDTIF_Pos (0) /*!< WWDT_T::STATUS: WWDTIF Position */ +#define WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos) /*!< WWDT_T::STATUS: WWDTIF Mask */ + +#define WWDT_STATUS_WWDTRF_Pos (1) /*!< WWDT_T::STATUS: WWDTRF Position */ +#define WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos) /*!< WWDT_T::STATUS: WWDTRF Mask */ + +#define WWDT_CNT_CNTDAT_Pos (0) /*!< WWDT_T::CNT: CNTDAT Position */ +#define WWDT_CNT_CNTDAT_Msk (0x3ful << WWDT_CNT_CNTDAT_Pos) /*!< WWDT_T::CNT: CNTDAT Mask */ + +/**@}*/ /* WWDT_CONST */ +/**@}*/ /* end of WWDT register group */ +/**@}*/ /* end of REGISTER group */ + +#if defined ( __CC_ARM ) + #pragma no_anon_unions +#endif + +#endif /* __WWDT_REG_H__ */ \ No newline at end of file diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_acmp.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_acmp.h new file mode 100644 index 00000000000..9fbdd163c98 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_acmp.h @@ -0,0 +1,414 @@ +/**************************************************************************//** + * @file ACMP.h + * @version V1.00 + * @brief M251 series ACMP Driver Header File + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __ACMP_H__ +#define __ACMP_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + + +/** @addtogroup ACMP_Driver ACMP Driver + @{ +*/ + + +/** @addtogroup ACMP_EXPORTED_CONSTANTS ACMP Exported Constants + @{ +*/ + + + +/*---------------------------------------------------------------------------------------------------------*/ +/* ACMP_CTL constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define ACMP_CTL_FILTSEL_OFF (0UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for filter function disabled. \hideinitializer */ +#define ACMP_CTL_FILTSEL_1PCLK (1UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 1 PCLK filter count. \hideinitializer */ +#define ACMP_CTL_FILTSEL_2PCLK (2UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 2 PCLKs filter count. \hideinitializer */ +#define ACMP_CTL_FILTSEL_4PCLK (3UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 4 PCLKs filter count. \hideinitializer */ +#define ACMP_CTL_FILTSEL_8PCLK (4UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 8 PCLKs filter count. \hideinitializer */ +#define ACMP_CTL_FILTSEL_16PCLK (5UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 16 PCLKs filter count. \hideinitializer */ +#define ACMP_CTL_FILTSEL_32PCLK (6UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 32 PCLKs filter count. \hideinitializer */ +#define ACMP_CTL_FILTSEL_64PCLK (7UL << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_CTL setting for 64 PCLKs filter count. \hideinitializer */ +#define ACMP_CTL_INTPOL_RF (0UL << ACMP_CTL_INTPOL_Pos) /*!< ACMP_CTL setting for selecting rising edge and falling edge as interrupt condition. \hideinitializer */ +#define ACMP_CTL_INTPOL_R (1UL << ACMP_CTL_INTPOL_Pos) /*!< ACMP_CTL setting for selecting rising edge as interrupt condition. \hideinitializer */ +#define ACMP_CTL_INTPOL_F (2UL << ACMP_CTL_INTPOL_Pos) /*!< ACMP_CTL setting for selecting falling edge as interrupt condition. \hideinitializer */ +#define ACMP_CTL_POSSEL_P0 (0UL << ACMP_CTL_POSSEL_Pos) /*!< ACMP_CTL setting for selecting ACMPx_P0 pin as the source of ACMP V+. \hideinitializer */ +#define ACMP_CTL_POSSEL_P1 (1UL << ACMP_CTL_POSSEL_Pos) /*!< ACMP_CTL setting for selecting ACMPx_P1 pin as the source of ACMP V+. \hideinitializer */ +#define ACMP_CTL_POSSEL_P2 (2UL << ACMP_CTL_POSSEL_Pos) /*!< ACMP_CTL setting for selecting ACMPx_P2 pin as the source of ACMP V+. \hideinitializer */ +#define ACMP_CTL_POSSEL_P3 (3UL << ACMP_CTL_POSSEL_Pos) /*!< ACMP_CTL setting for selecting ACMPx_P3 pin as the source of ACMP V+. \hideinitializer */ +#define ACMP_CTL_NEGSEL_PIN (0UL << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_CTL setting for selecting the voltage of ACMP negative input pin as the source of ACMP V-. \hideinitializer */ +#define ACMP_CTL_NEGSEL_CRV (1UL << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_CTL setting for selecting internal comparator reference voltage as the source of ACMP V-. \hideinitializer */ +#define ACMP_CTL_NEGSEL_VBG (2UL << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_CTL setting for selecting internal Band-gap voltage as the source of ACMP V-. \hideinitializer */ +#define ACMP_CTL_NEGSEL_DAC (3UL << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_CTL setting for selecting DAC output voltage as the source of ACMP V-. \hideinitializer */ +#define ACMP_CTL_HYSTERESIS_30MV (3UL << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_CTL setting for enabling the hysteresis function at 30mV. \hideinitializer */ +#define ACMP_CTL_HYSTERESIS_20MV (2UL << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_CTL setting for enabling the hysteresis function at 20mV. \hideinitializer */ +#define ACMP_CTL_HYSTERESIS_10MV (1UL << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_CTL setting for enabling the hysteresis function at 10mV. \hideinitializer */ +#define ACMP_CTL_HYSTERESIS_DISABLE (0UL << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_CTL setting for disabling the hysteresis function. \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* ACMP_VREF constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define ACMP_VREF_CRVSSEL_AVDD (0UL << ACMP_VREF_CRVSSEL_Pos) /*!< ACMP_VREF setting for selecting analog supply voltage AVDD as the CRV source voltage \hideinitializer */ +#define ACMP_VREF_CRVSSEL_INTVREF (1UL << ACMP_VREF_CRVSSEL_Pos) /*!< ACMP_VREF setting for selecting internal reference voltage as the CRV source voltage \hideinitializer */ + + +/*@}*/ /* end of group ACMP_EXPORTED_CONSTANTS */ + + +/** @addtogroup ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Macros and functions */ +/*---------------------------------------------------------------------------------------------------------*/ + + +/** + * @brief This macro is used to enable output inverse function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set ACMPOINV bit of ACMP_CTL register to enable output inverse function. + * \hideinitializer + */ +#define ACMP_ENABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPOINV_Msk) + +/** + * @brief This macro is used to disable output inverse function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear ACMPOINV bit of ACMP_CTL register to disable output inverse function. + * \hideinitializer + */ +#define ACMP_DISABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPOINV_Msk) + +/** + * @brief This macro is used to select ACMP negative input source + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32Src is comparator negative input selection. Including: + * - \ref ACMP_CTL_NEGSEL_PIN + * - \ref ACMP_CTL_NEGSEL_CRV + * - \ref ACMP_CTL_NEGSEL_VBG + * - \ref ACMP_CTL_NEGSEL_DAC + * @return None + * @details This macro will set NEGSEL (ACMP_CTL[5:4]) to determine the source of negative input. + * \hideinitializer + */ +#define ACMP_SET_NEG_SRC(acmp, u32ChNum, u32Src) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_NEGSEL_Msk) | (u32Src)) + +/** + * @brief This macro is used to enable hysteresis function and set hysteresis to 30mV + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * \hideinitializer + */ +#define ACMP_ENABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_HYSTERESIS_30MV) + +/** + * @brief This macro is used to disable hysteresis function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear HYSEL bits of ACMP_CTL register to disable hysteresis function. + * \hideinitializer + */ +#define ACMP_DISABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_HYSSEL_Msk) + +/** + * @brief This macro is used to select hysteresis level + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32HysSel The hysteresis function option. Including: + * - \ref ACMP_CTL_HYSTERESIS_30MV + * - \ref ACMP_CTL_HYSTERESIS_20MV + * - \ref ACMP_CTL_HYSTERESIS_10MV + * - \ref ACMP_CTL_HYSTERESIS_DISABLE + * \hideinitializer + * @return None + */ +#define ACMP_CONFIG_HYSTERESIS(acmp, u32ChNum, u32HysSel) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_HYSSEL_Msk) | (u32HysSel)) + +/** + * @brief This macro is used to enable interrupt + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set ACMPIE bit of ACMP_CTL register to enable interrupt function. + * If wake-up function is enabled, the wake-up interrupt will be enabled as well. + * \hideinitializer + */ +#define ACMP_ENABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPIE_Msk) + +/** + * @brief This macro is used to disable interrupt + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear ACMPIE bit of ACMP_CTL register to disable interrupt function. + * \hideinitializer + */ +#define ACMP_DISABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPIE_Msk) + +/** + * @brief This macro is used to enable ACMP + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set ACMPEN bit of ACMP_CTL register to enable analog comparator. + * \hideinitializer + */ +#define ACMP_ENABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPEN_Msk) + +/** + * @brief This macro is used to disable ACMP + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear ACMPEN bit of ACMP_CTL register to disable analog comparator. + * \hideinitializer + */ +#define ACMP_DISABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPEN_Msk) + +/** + * @brief This macro is used to get ACMP output value + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return ACMP output value + * @details This macro will return the ACMP output value. + * \hideinitializer + */ +#define ACMP_GET_OUTPUT(acmp, u32ChNum) (((acmp)->STATUS & (ACMP_STATUS_ACMPO0_Msk<<((u32ChNum))))?1:0) + +/** + * @brief This macro is used to get ACMP interrupt flag + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return ACMP interrupt occurred (1) or not (0) + * @details This macro will return the ACMP interrupt flag. + * \hideinitializer + */ +#define ACMP_GET_INT_FLAG(acmp, u32ChNum) (((acmp)->STATUS & (ACMP_STATUS_ACMPIF0_Msk<<((u32ChNum))))?1:0) + +/** + * @brief This macro is used to clear ACMP interrupt flag + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will write 1 to ACMPIFn bit of ACMP_STATUS register to clear interrupt flag. + * \hideinitializer + */ +#define ACMP_CLR_INT_FLAG(acmp, u32ChNum) ((acmp)->STATUS = (ACMP_STATUS_ACMPIF0_Msk<<((u32ChNum)))) + +/** + * @brief This macro is used to clear ACMP wake-up interrupt flag + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will write 1 to WKIFn bit of ACMP_STATUS register to clear interrupt flag. + * \hideinitializer + */ +#define ACMP_CLR_WAKEUP_INT_FLAG(acmp, u32ChNum) ((acmp)->STATUS = (ACMP_STATUS_WKIF0_Msk<<((u32ChNum)))) + +/** + * @brief This macro is used to enable ACMP wake-up function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set WKEN (ACMP_CTL[16]) to enable ACMP wake-up function. + * \hideinitializer + */ +#define ACMP_ENABLE_WAKEUP(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WKEN_Msk) + +/** + * @brief This macro is used to disable ACMP wake-up function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear WKEN (ACMP_CTL[16]) to disable ACMP wake-up function. + * \hideinitializer + */ +#define ACMP_DISABLE_WAKEUP(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WKEN_Msk) + +/** + * @brief This macro is used to select ACMP positive input pin + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32Pin Comparator positive pin selection. Including: + * - \ref ACMP_CTL_POSSEL_P0 + * - \ref ACMP_CTL_POSSEL_P1 + * - \ref ACMP_CTL_POSSEL_P2 + * - \ref ACMP_CTL_POSSEL_P3 + * @return None + * @details This macro will set POSSEL (ACMP_CTL[7:6]) to determine the comparator positive input pin. + * \hideinitializer + */ +#define ACMP_SELECT_P(acmp, u32ChNum, u32Pin) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_POSSEL_Msk) | (u32Pin)) + +/** + * @brief This macro is used to enable ACMP filter function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set OUTSEL (ACMP_CTL[12]) to enable output filter function. + * \hideinitializer + */ +#define ACMP_ENABLE_FILTER(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_OUTSEL_Msk) + +/** + * @brief This macro is used to disable ACMP filter function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear OUTSEL (ACMP_CTL[12]) to disable output filter function. + * \hideinitializer + */ +#define ACMP_DISABLE_FILTER(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_OUTSEL_Msk) + +/** + * @brief This macro is used to set ACMP filter function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32Cnt is comparator filter count setting. + * - \ref ACMP_CTL_FILTSEL_OFF + * - \ref ACMP_CTL_FILTSEL_1PCLK + * - \ref ACMP_CTL_FILTSEL_2PCLK + * - \ref ACMP_CTL_FILTSEL_4PCLK + * - \ref ACMP_CTL_FILTSEL_8PCLK + * - \ref ACMP_CTL_FILTSEL_16PCLK + * - \ref ACMP_CTL_FILTSEL_32PCLK + * - \ref ACMP_CTL_FILTSEL_64PCLK + * @return None + * @details When ACMP output filter function is enabled, the output sampling count is determined by FILTSEL (ACMP_CTL[15:13]). + * \hideinitializer + */ +#define ACMP_SET_FILTER(acmp, u32ChNum, u32Cnt) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_FILTSEL_Msk) | (u32Cnt)) + +/** + * @brief This macro is used to select comparator reference voltage + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32Level The comparator reference voltage setting. + * The formula is: + * comparator reference voltage = CRV source voltage x (1/6 + u32Level/24) + * The range of u32Level is 0 ~ 15. + * @return None + * @details When CRV is selected as ACMP negative input source, the CRV level is determined by CRVCTL (ACMP_VREF[3:0]). + * \hideinitializer + */ +#define ACMP_CRV_SEL(acmp, u32Level) ((acmp)->VREF = ((acmp)->VREF & ~ACMP_VREF_CRVCTL_Msk) | ((u32Level)<VREF = ((acmp)->VREF & ~ACMP_VREF_CRVSSEL_Msk) | (u32Src)) + +/** + * @brief This macro is used to select ACMP interrupt condition + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32Cond Comparator interrupt condition selection. Including: + * - \ref ACMP_CTL_INTPOL_RF + * - \ref ACMP_CTL_INTPOL_R + * - \ref ACMP_CTL_INTPOL_F + * @return None + * @details The ACMP output interrupt condition can be rising edge, falling edge or any edge. + * \hideinitializer + */ +#define ACMP_SELECT_INT_COND(acmp, u32ChNum, u32Cond) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_INTPOL_Msk) | (u32Cond)) + +/** + * @brief This macro is used to enable ACMP window latch mode + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set WLATEN (ACMP_CTL[17]) to enable ACMP window latch mode. + * When ACMP0/1_WLAT pin is at high level, ACMPO0/1 passes through window latch + * block; when ACMP0/1_WLAT pin is at low level, the output of window latch block, + * WLATOUT, is frozen. + * \hideinitializer + */ +#define ACMP_ENABLE_WINDOW_LATCH(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WLATEN_Msk) + +/** + * @brief This macro is used to disable ACMP window latch mode + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear WLATEN (ACMP_CTL[17]) to disable ACMP window latch mode. + * \hideinitializer + */ +#define ACMP_DISABLE_WINDOW_LATCH(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WLATEN_Msk) + +/** + * @brief This macro is used to enable ACMP window compare mode + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set WCMPSEL (ACMP_CTL[18]) to enable ACMP window compare mode. + * When window compare mode is enabled, user can connect the specific analog voltage + * source to either the positive inputs of both comparators or the negative inputs of + * both comparators. The upper bound and lower bound of the designated range are + * determined by the voltages applied to the other inputs of both comparators. If the + * output of a comparator is low and the other comparator outputs high, which means two + * comparators implies the upper and lower bound. User can directly monitor a specific + * analog voltage source via ACMPWO (ACMP_STATUS[16]). + * \hideinitializer + */ +#define ACMP_ENABLE_WINDOW_COMPARE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WCMPSEL_Msk) + +/** + * @brief This macro is used to disable ACMP window compare mode + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear WCMPSEL (ACMP_CTL[18]) to disable ACMP window compare mode. + * \hideinitializer + */ +#define ACMP_DISABLE_WINDOW_COMPARE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WCMPSEL_Msk) + + + + +/* Function prototype declaration */ +void ACMP_Open(ACMP_T *acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysSel); +void ACMP_Close(ACMP_T *acmp, uint32_t u32ChNum); + + + +/*@}*/ /* end of group ACMP_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group ACMP_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __ACMP_H__ */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_bpwm.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_bpwm.h new file mode 100644 index 00000000000..39f736e301f --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_bpwm.h @@ -0,0 +1,376 @@ +/****************************************************************************** + * @file bpwm.h + * @version V0.10 + * @brief M251 series BPWM driver header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __BPWM_H__ +#define __BPWM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup BPWM_Driver BPWM Driver + @{ +*/ + + +/** @addtogroup BPWM_EXPORTED_CONSTANTS BPWM Exported Constants + @{ +*/ +#define BPWM_CHANNEL_NUM (6UL) /*!< BPWM channel number */ +#define BPWM_CH_0_MASK (0x1UL) /*!< BPWM channel 0 mask */ +#define BPWM_CH_1_MASK (0x2UL) /*!< BPWM channel 1 mask */ +#define BPWM_CH_2_MASK (0x4UL) /*!< BPWM channel 2 mask */ +#define BPWM_CH_3_MASK (0x8UL) /*!< BPWM channel 3 mask */ +#define BPWM_CH_4_MASK (0x10UL) /*!< BPWM channel 4 mask */ +#define BPWM_CH_5_MASK (0x20UL) /*!< BPWM channel 5 mask */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define BPWM_UP_COUNTER (0UL) /*!< Up counter type */ +#define BPWM_DOWN_COUNTER (1UL) /*!< Down counter type */ +#define BPWM_UP_DOWN_COUNTER (2UL) /*!< Up-Down counter type */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Aligned Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define BPWM_EDGE_ALIGNED (1UL) /*!< BPWM working in edge aligned type(down count) */ +#define BPWM_CENTER_ALIGNED (2UL) /*!< BPWM working in center aligned type */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Output Level Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define BPWM_OUTPUT_NOTHING (0UL) /*!< BPWM output nothing */ +#define BPWM_OUTPUT_LOW (1UL) /*!< BPWM output low */ +#define BPWM_OUTPUT_HIGH (2UL) /*!< BPWM output high */ +#define BPWM_OUTPUT_TOGGLE (3UL) /*!< BPWM output toggle */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Synchronous Start Function Control Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define BPWM_SSCTL_SSRC_PWM0 (0UL<SSCTL = ((bpwm)->SSCTL & ~BPWM_SSCTL_SSRC_Msk) | (u32SyncSrc) | BPWM_SSCTL_SSEN0_Msk) + +/** + * @brief Disable timer synchronous start counting function of specified channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @return None + * @details This macro is used to disable timer synchronous start counting function of specified channel(s). + * @note All channels share channel 0's setting. + * \hideinitializer + */ +#define BPWM_DISABLE_TIMER_SYNC(bpwm, u32ChannelMask) ((bpwm)->SSCTL &= ~BPWM_SSCTL_SSEN0_Msk) + +/** + * @brief This macro enable BPWM counter synchronous start counting function. + * @param[in] bpwm The pointer of the specified BPWM module + * @return None + * @details This macro is used to make selected BPWM0 and BPWM1 channel(s) start counting at the same time. + * To configure synchronous start counting channel(s) by BPWM_ENABLE_TIMER_SYNC() and BPWM_DISABLE_TIMER_SYNC(). + * \hideinitializer + */ +#define BPWM_TRIGGER_SYNC_START(bpwm) ((bpwm)->SSTRG = BPWM_SSTRG_CNTSEN_Msk) + +/** + * @brief This macro enable output inverter of specified channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * \hideinitializer + */ +#define BPWM_ENABLE_OUTPUT_INVERTER(bpwm, u32ChannelMask) ((bpwm)->POLCTL = (u32ChannelMask)) + +/** + * @brief This macro get captured rising data + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return None + * \hideinitializer + */ +#define BPWM_GET_CAPTURE_RISING_DATA(bpwm, u32ChannelNum) ((bpwm)->CAPDAT[(u32ChannelNum)].RCAPDAT) + +/** + * @brief This macro get captured falling data + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return None + * \hideinitializer + */ +#define BPWM_GET_CAPTURE_FALLING_DATA(bpwm, u32ChannelNum) ((bpwm)->CAPDAT[(u32ChannelNum)].FCAPDAT) + +/** + * @brief This macro mask output logic to high or low + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32LevelMask Output logic to high or low + * @return None + * @details This macro is used to mask output logic to high or low of specified channel(s). + * @note If u32ChannelMask parameter is 0, then mask function will be disabled. + * \hideinitializer + */ +#define BPWM_MASK_OUTPUT(bpwm, u32ChannelMask, u32LevelMask) \ + { \ + (bpwm)->MSKEN = (u32ChannelMask); \ + (bpwm)->MSK = (u32LevelMask); \ + } + +/** + * @brief This macro set the prescaler of all channels + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFFF + * @return None + * \hideinitializer + */ +#define BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u32Prescaler) ((bpwm)->CLKPSC = (u32Prescaler)) + +/** +* @brief This macro get the prescaler of the selected channel +* @param[in] bpwm The pointer of the specified BPWM module +* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5. This parameter is not used. +* @return Return Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF +* @details This macro is used to get the prescaler of specified channel. +* @note All channels share channel 0's setting. +* The clock of BPWM counter is divided by (u32Prescaler + 1). +* \hideinitializer +*/ +#define BPWM_GET_PRESCALER(bpwm, u32ChannelNum) (bpwm)->CLKPSC + +/** + * @brief This macro set the duty of the selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32CMR Duty of specified channel. Valid values are between 0~0xFFFF + * @return None + * @note This new setting will take effect on next BPWM period + * \hideinitializer + */ +#define BPWM_SET_CMR(bpwm, u32ChannelNum, u32CMR) ((bpwm)->CMPDAT[(u32ChannelNum)] = (u32CMR)) + +/** + * @brief This macro get the duty of the selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return Return the duty of specified channel. Valid values are between 0~0xFFFF + * @details This macro is used to get the duty of specified channel. + * \hideinitializer + */ +#define BPWM_GET_CMR(bpwm, u32ChannelNum) ((bpwm)->CMPDAT[(u32ChannelNum)]) + +/** + * @brief This macro set the period of all channels + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF + * @return None + * @note This new setting will take effect on next BPWM period + * @note BPWM counter will stop if period length set to 0 + * \hideinitializer + */ +#define BPWM_SET_CNR(bpwm, u32ChannelNum, u32CNR) ((bpwm)->PERIOD = (u32CNR)) + +/** + * @brief This macro get the period of all channels + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return Return the period of specified channel. + * @details This macro is used to get the period of specified channel. + * \hideinitializer + */ +#define BPWM_GET_CNR(bpwm, u32ChannelNum) ((bpwm)->PERIOD) + +/** + * @brief This macro set the BPWM aligned type + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @param[in] u32AlignedType BPWM aligned type, valid values are: + * - \ref BPWM_UP_COUNTER + * - \ref BPWM_DOWN_COUNTER + * - \ref BPWM_UP_DOWN_COUNTER + * @return None + * @note All channels share channel 0's setting. + * \hideinitializer + */ +#define BPWM_SET_ALIGNED_TYPE(bpwm, u32ChannelMask, u32AlignedType) ((bpwm)->CTL1 = (u32AlignedType)) + +/** + * @brief Clear counter of channel 0 + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @return None + * @details This macro is used to clear counter of channel 0 + * \hideinitializer + */ +#define BPWM_CLR_COUNTER(bpwm, u32ChannelMask) ((bpwm)->CNTCLR = (BPWM_CNTCLR_CNTCLR0_Msk)) + +/** + * @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32ZeroLevel output level at zero point, valid values are: + * - \ref BPWM_OUTPUT_NOTHING + * - \ref BPWM_OUTPUT_LOW + * - \ref BPWM_OUTPUT_HIGH + * - \ref BPWM_OUTPUT_TOGGLE + * @param[in] u32CmpUpLevel output level at compare up point, valid values are: + * - \ref BPWM_OUTPUT_NOTHING + * - \ref BPWM_OUTPUT_LOW + * - \ref BPWM_OUTPUT_HIGH + * - \ref BPWM_OUTPUT_TOGGLE + * @param[in] u32PeriodLevel output level at period(center) point, valid values are: + * - \ref BPWM_OUTPUT_NOTHING + * - \ref BPWM_OUTPUT_LOW + * - \ref BPWM_OUTPUT_HIGH + * - \ref BPWM_OUTPUT_TOGGLE + * @param[in] u32CmpDownLevel output level at compare down point, valid values are: + * - \ref BPWM_OUTPUT_NOTHING + * - \ref BPWM_OUTPUT_LOW + * - \ref BPWM_OUTPUT_HIGH + * - \ref BPWM_OUTPUT_TOGGLE + * @return None + * @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s) + * \hideinitializer + */ +#define BPWM_SET_OUTPUT_LEVEL(bpwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \ + do{ \ + uint32_t i; \ + for(i = 0UL; i < 6UL; i++) { \ + if((u32ChannelMask) & (1UL << i)) { \ + (bpwm)->WGCTL0 = (((bpwm)->WGCTL0 & ~(3UL << (i << 1UL))) | ((u32ZeroLevel) << (i << 1UL))); \ + (bpwm)->WGCTL0 = (((bpwm)->WGCTL0 & ~(3UL << (BPWM_WGCTL0_PRDPCTL0_Pos + (i << 1UL)))) | ((u32PeriodLevel) << (BPWM_WGCTL0_PRDPCTL0_Pos + (i << 1UL)))); \ + (bpwm)->WGCTL1 = (((bpwm)->WGCTL1 & ~(3UL << (i << 1UL))) | ((u32CmpUpLevel) << (i << 1UL))); \ + (bpwm)->WGCTL1 = (((bpwm)->WGCTL1 & ~(3UL << (BPWM_WGCTL1_CMPDCTL0_Pos + (i << 1UL)))) | ((u32CmpDownLevel) << (BPWM_WGCTL1_CMPDCTL0_Pos + (i << 1UL)))); \ + } \ + } \ + }while(0) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define BPWM functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +uint32_t BPWM_ConfigCaptureChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge); +uint32_t BPWM_ConfigOutputChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle); +void BPWM_Start(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_Stop(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_ForceStop(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_EnableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition); +void BPWM_DisableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_ClearADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition); +uint32_t BPWM_GetADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_EnableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_DisableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_EnableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_DisableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_EnableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge); +void BPWM_DisableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge); +void BPWM_ClearCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge); +uint32_t BPWM_GetCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_EnableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType); +void BPWM_DisableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_ClearDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +uint32_t BPWM_GetDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_EnablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType); +void BPWM_DisablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_ClearPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +uint32_t BPWM_GetPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_EnableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_DisableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_ClearZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +uint32_t BPWM_GetZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_EnableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); +void BPWM_DisableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); +void BPWM_SetClockSource(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel); +uint32_t BPWM_GetWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_ClearWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); + + +/*@}*/ /* end of group BPWM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group BPWM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __BPWM_H__ */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_clk.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_clk.h new file mode 100644 index 00000000000..ec30b022166 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_clk.h @@ -0,0 +1,627 @@ +/**************************************************************************** + * @file clk.h + * @version V1.10 + * @brief M251 series CLK driver source file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __CLK_H__ +#define __CLK_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CLK_Driver CLK Driver + @{ +*/ + +/** @addtogroup CLK_EXPORTED_CONSTANTS CLK Exported Constants + @{ +*/ + +#define FREQ_4MHZ 4000000UL +#define FREQ_8MHZ 8000000UL +#define FREQ_16MHZ 16000000UL +#define FREQ_25MHZ 25000000UL +#define FREQ_32MHZ 32000000UL +#define FREQ_48MHZ 48000000UL +#define FREQ_50MHZ 50000000UL +#define FREQ_64MHZ 64000000UL +#define FREQ_72MHZ 72000000UL +#define FREQ_96MHZ 96000000UL +#define FREQ_100MHZ 100000000UL + +/*---------------------------------------------------------------------------------------------------------*/ +/* CLKSEL0 constant definitions. (Write-protection) */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_CLKSEL0_HCLKSEL_HXT (0x00UL<>30) & 0x3) /*!< Calculate AHBCLK/APBCLK offset on MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 */ +#define MODULE_CLKSEL(x) (((x) >>28) & 0x3) /*!< Calculate CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 */ +#define MODULE_CLKSEL_Msk(x) (((x) >>25) & 0x7) /*!< Calculate CLKSEL mask offset on MODULE index */ +#define MODULE_CLKSEL_Pos(x) (((x) >>20) & 0x1f) /*!< Calculate CLKSEL position offset on MODULE index */ +#define MODULE_CLKDIV(x) (((x) >>18) & 0x3) /*!< Calculate APBCLK CLKDIV on MODULE index, 0x0:CLKDIV, 0x1:CLKDIV1, 0x2:CLKDIV3, 0x3:CLKDIV4 */ +#define MODULE_CLKDIV_Msk(x) (((x) >>10) & 0xff) /*!< Calculate CLKDIV mask offset on MODULE index */ +#define MODULE_CLKDIV_Pos(x) (((x) >>5 ) & 0x1f) /*!< Calculate CLKDIV position offset on MODULE index */ +#define MODULE_IP_EN_Pos(x) (((x) >>0 ) & 0x1f) /*!< Calculate APBCLK offset on MODULE index */ +#define MODULE_NoMsk 0x0 /*!< Not mask on MODULE index */ +#define NA MODULE_NoMsk /*!< Not Available */ + +#define MODULE_APBCLK_ENC(x) (((x) & 0x03) << 30) /*!< MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 */ +#define MODULE_CLKSEL_ENC(x) (((x) & 0x03) << 28) /*!< CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 */ +#define MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x07) << 25) /*!< CLKSEL mask offset on MODULE index */ +#define MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1f) << 20) /*!< CLKSEL position offset on MODULE index */ +#define MODULE_CLKDIV_ENC(x) (((x) & 0x03) << 18) /*!< APBCLK CLKDIV on MODULE index, 0x0:CLKDIV, 0x1:CLKDIV1, 0x2:CLKDIV3, 0x3:CLKDIV4*/ +#define MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xff) << 10) /*!< CLKDIV mask offset on MODULE index */ +#define MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1f) << 5) /*!< CLKDIV position offset on MODULE index */ +#define MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1f) << 0) /*!< AHBCLK/APBCLK offset on MODULE index */ + + +//AHBCLK +#define PDMA_MODULE (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_PDMACKEN_Pos)|\ + MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< PDMA Module */ + +#define ISP_MODULE (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_ISPCKEN_Pos)|\ + MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ISP Module */ + +#define CRC_MODULE (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_CRCCKEN_Pos)|\ + MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CRC Module */ + +#define EBI_MODULE (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_EBICKEN_Pos)|\ + MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EBI Module */ + +#define CRPT_MODULE (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_CRPTCKEN_Pos)|\ + MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CRPT Module */ + +#define FMCIDLE_MODULE (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_FMCIDLE_Pos)|\ + MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< FMCIDLE Module */ + +//APBCLK0 +#define WDT_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_WDTCKEN_Pos)|\ + MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC( 0)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< WDT Module */ + +#define WWDT_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_WDTCKEN_Pos)|\ + MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC( 2)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< WWDT Module */ + +#define CLKO_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_CLKOCKEN_Pos) |\ + MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC( 4)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CLKO Module */ + +#define TMR0_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_TMR0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC( 8)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TMR0 Module */ + +#define TMR1_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_TMR1CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC(12)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TMR1 Module */ + +#define TMR2_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_TMR2CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC(16)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TMR2 Module */ + +#define TMR3_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_TMR3CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC(20)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TMR3 Module */ + +#define UART0_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_UART0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC(24)|\ + MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC( 8)) /*!< UART0 Module */ + +#define UART1_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_UART1CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC(28)|\ + MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC( 12)) /*!< UART1 Module */ + +#define UART2_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_UART2CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 3)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC(24)|\ + MODULE_CLKDIV_ENC( 3)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC( 0)) /*!< UART2 Module */ + +#define I2C0_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_I2C0CKEN_Pos) |\ + MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2C0 Module */ + +#define I2C1_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_I2C1CKEN_Pos) |\ + MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2C1 Module */ + +#define QSPI0_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_QSPI0CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC( 2)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< QSPI0 Module */ + +#define SPI0_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_SPI0CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC( 4)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI0 Module */ + +#define RTC_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_RTCCKEN_Pos)|\ + MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< RTC Module */ + +#define EADC_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_EADCCKEN_Pos)|\ + MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0xFF)|MODULE_CLKDIV_Pos_ENC(16)) /*!< ADC Module */ + +#define ACMP01_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_ACMP01CKEN_Pos)|\ + MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ACMP Module */ + +#define USBD_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_USBDCKEN_Pos)|\ + MODULE_CLKSEL_ENC( 0)|MODULE_CLKSEL_Msk_ENC(1)|MODULE_CLKSEL_Pos_ENC(8)|\ + MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC(4)) /*!< USBD Module */ + +//APBCLK1 +#define PWM0_MODULE (MODULE_APBCLK_ENC( 2)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_PWM0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 1)|MODULE_CLKSEL_Pos_ENC( 0)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< PWM0 Module */ + +#define PWM1_MODULE (MODULE_APBCLK_ENC( 2)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_PWM1CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 1)|MODULE_CLKSEL_Pos_ENC( 1)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< PWM1 Module */ + +#define DAC_MODULE (MODULE_APBCLK_ENC( 2)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_DACCKEN_Pos)|\ + MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< DAC Module */ + +#define OPA_MODULE (MODULE_APBCLK_ENC( 2)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_OPACKEN_Pos)|\ + MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< OPA Module */ + +#define USCI0_MODULE (MODULE_APBCLK_ENC( 2)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_USCI0CKEN_Pos)|\ + MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< USCI0 Module */ + +#define USCI1_MODULE (MODULE_APBCLK_ENC( 2)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_USCI1CKEN_Pos)|\ + MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< USCI1 Module */ + +#define USCI2_MODULE (MODULE_APBCLK_ENC( 2)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_USCI2CKEN_Pos)|\ + MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< USCI2 Module */ + +#define SC0_MODULE (MODULE_APBCLK_ENC( 2)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_SC0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 3)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC( 0)|\ + MODULE_CLKDIV_ENC( 1)|MODULE_CLKDIV_Msk_ENC(0xFF)|MODULE_CLKDIV_Pos_ENC( 0)) /*!< SC0 Module */ + +#define BPWM0_MODULE (MODULE_APBCLK_ENC( 2)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_BPWM0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 1)|MODULE_CLKSEL_Pos_ENC( 8)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< BPWM0 Module */ + +#define BPWM1_MODULE (MODULE_APBCLK_ENC( 2)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_BPWM1CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 1)|MODULE_CLKSEL_Pos_ENC( 9)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< BPWM0 Module */ + +#define PSIO_MODULE (MODULE_APBCLK_ENC( 2)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_PSIOCKEN_Pos)|\ + MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC( 28)|\ + MODULE_CLKDIV_ENC( 1)|MODULE_CLKDIV_Msk_ENC(0xFF)|MODULE_CLKDIV_Pos_ENC( 24)) /*!< PSIO Module */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* PDMSEL constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_PMUCTL_PDMSEL_PD (0x0UL<PMUCTL &= ~CLK_PMUCTL_WKTMREN_Msk) /*!< Disable Wake-up timer at Standby or Deep Power-down mode */ +#define CLK_ENABLE_WKTMR(void) (CLK->PMUCTL |= CLK_PMUCTL_WKTMREN_Msk) /*!< Enable Wake-up timer at Standby or Deep Power-down mode */ +#define CLK_DISABLE_DPDWKPIN0(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN0_Msk) /*!< Disable Wake-up pin0 (GPC.0) at Deep Power-down mode */ +#define CLK_DISABLE_DPDWKPIN1(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN1_Msk) /*!< Disable Wake-up pin1 (GPB.0) at Deep Power-down mode */ +#define CLK_DISABLE_DPDWKPIN2(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN2_Msk) /*!< Disable Wake-up pin2 (GPB.2) at Deep Power-down mode */ +#define CLK_DISABLE_DPDWKPIN3(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN3_Msk) /*!< Disable Wake-up pin3 (GPB.12) at Deep Power-down mode */ +#define CLK_DISABLE_DPDWKPIN4(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN4_Msk) /*!< Disable Wake-up pin4 (GPF.6) at Deep Power-down mode */ +#define CLK_DISABLE_WKPINDB(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINDBEN_Msk) /*!< Disable Wake-up pin De-bounce function */ +#define CLK_ENABLE_WKPINDB(void) (CLK->PMUCTL |= CLK_PMUCTL_WKPINDBEN_Msk) /*!< Enable Wake-up pin De-bounce function */ +#define CLK_DISABLE_RTCWK(void) (CLK->PMUCTL &= ~CLK_PMUCTL_RTCWKEN_Msk) /*!< Disable RTC Wake-up at Standby or Deep Power-down mode \hideinitializer */ +#define CLK_ENABLE_RTCWK(void) (CLK->PMUCTL |= CLK_PMUCTL_RTCWKEN_Msk) /*!< Enable RTC Wake-up at Standby or Deep Power-down mode \hideinitializer */ + +/** + * @brief Set Wake-up Timer Time-out Interval + * + * @param[in] u32Interval The de-bounce sampling cycle selection. It could be + * - \ref CLK_PMUCTL_WKTMRIS_128 + * - \ref CLK_PMUCTL_WKTMRIS_256 + * - \ref CLK_PMUCTL_WKTMRIS_512 + * - \ref CLK_PMUCTL_WKTMRIS_1024 + * - \ref CLK_PMUCTL_WKTMRIS_4096 + * - \ref CLK_PMUCTL_WKTMRIS_8192 + * - \ref CLK_PMUCTL_WKTMRIS_16384 + * - \ref CLK_PMUCTL_WKTMRIS_32768 + * + * @return None + * + * @details This function set Wake-up Timer Time-out Interval. + * + * + */ +#define CLK_SET_WKTMR_INTERVAL(u32Interval) (CLK->PMUCTL |= (u32Interval)) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* static inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void CLK_SysTickDelay(uint32_t u32USec); +__STATIC_INLINE void CLK_SysTickLongDelay(uint32_t u32USec); + +/** + * @brief This function execute delay function. + * @param[in] u32USec Delay time. The Max value is 2^24 / CPU Clock(MHz). Ex: + * 50MHz => 335544us, 48MHz => 349525us, 28MHz => 699050us ... + * @return None + * @details Use the SysTick to generate the delay time and the UNIT is in us. + * The SysTick clock source is from HCLK, i.e the same as system core clock. + * User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function. + */ +__STATIC_INLINE void CLK_SysTickDelay(uint32_t u32USec) +{ + SysTick->LOAD = u32USec * CyclesPerUs; + SysTick->VAL = (0x0u); + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; + + /* Waiting for down-count to zero */ + while ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0u) + { + } + + /* Disable SysTick counter */ + SysTick->CTRL = 0u; +} + +/** + * @brief This function execute long delay function. + * @param[in] u32USec Delay time. + * @return None + * @details Use the SysTick to generate the long delay time and the UNIT is in us. + * The SysTick clock source is from HCLK, i.e the same as system core clock. + * User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function. + */ +__STATIC_INLINE void CLK_SysTickLongDelay(uint32_t u32USec) +{ + uint32_t u32Delay; + + /* It should <= 349525us for each delay loop */ + u32Delay = 349525UL; + + do + { + if (u32USec > u32Delay) + { + u32USec -= u32Delay; + } + else + { + u32Delay = u32USec; + u32USec = 0UL; + } + + SysTick->LOAD = u32Delay * CyclesPerUs; + SysTick->VAL = (0x0UL); + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; + + /* Waiting for down-count to zero */ + while ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL) + { + } + + /* Disable SysTick counter */ + SysTick->CTRL = 0UL; + + } + while (u32USec > 0UL); + +} + +void CLK_DisableCKO(void); +void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En); +void CLK_PowerDown(void); +void CLK_Idle(void); +uint32_t CLK_GetHXTFreq(void); +uint32_t CLK_GetLXTFreq(void); +uint32_t CLK_GetPCLK0Freq(void); +uint32_t CLK_GetPCLK1Freq(void); +uint32_t CLK_GetHCLKFreq(void); +uint32_t CLK_GetCPUFreq(void); +uint32_t CLK_GetPLLClockFreq(void); +void CLK_DisablePLL(void); +uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq); +void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv); +uint32_t CLK_SetCoreClock(uint32_t u32Hclk); +void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv); +void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc); +void CLK_EnableXtalRC(uint32_t u32ClkMask); +void CLK_DisableXtalRC(uint32_t u32ClkMask); +void CLK_EnableModuleClock(uint32_t u32ModuleIdx); +void CLK_DisableModuleClock(uint32_t u32ModuleIdx); +uint32_t CLK_WaitClockReady(uint32_t u32ClkMask); +void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count); +void CLK_DisableSysTick(void); +void CLK_SetPowerDownMode(uint32_t u32PDMode); +void CLK_EnableDPDWKPin(uint32_t u32Pin, uint32_t u32TriggerType); +void CLK_EnableDPDWKPin0(uint32_t u32TriggerType); +void CLK_EnableDPDWKPin1(uint32_t u32TriggerType); +void CLK_EnableDPDWKPin2(uint32_t u32TriggerType); +void CLK_EnableDPDWKPin3(uint32_t u32TriggerType); +void CLK_EnableDPDWKPin4(uint32_t u32TriggerType); +uint32_t CLK_GetPMUWKSrc(void); +uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx); +uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx); + +/*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CLK_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CLK_H__ */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_crc.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_crc.h new file mode 100644 index 00000000000..174df2f1627 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_crc.h @@ -0,0 +1,109 @@ +/**************************************************************************//** + * @file crc.h + * @version V0.10 + * @brief M251 series Cyclic Redundancy Check(CRC) driver header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __CRC_H__ +#define __CRC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CRC_Driver CRC Driver + @{ +*/ + +/** @addtogroup CRC_EXPORTED_CONSTANTS CRC Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* CRC Polynomial Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CRC_CCITT (0UL << CRC_CTL_CRCMODE_Pos) /*!SEED = (u32Seed); CRC->CTL |= CRC_CTL_CHKSINIT_Msk; }while(0) + +/** + * @brief Get CRC Seed Value + * + * @param None + * + * @return CRC seed value + * + * @details This macro gets the current CRC seed value. + */ +#define CRC_GET_SEED() (CRC->SEED) + +/** + * @brief CRC Write Data + * + * @param[in] u32Data Write data + * + * @return None + * + * @details User can write data directly to CRC Write Data Register(CRC_DAT) by this macro to perform CRC operation. + */ +#define CRC_WRITE_DATA(u32Data) (CRC->DAT = (u32Data)) + +void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen); +uint32_t CRC_GetChecksum(void); + +/*@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CRC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CRC_H__ */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_crypto.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_crypto.h new file mode 100644 index 00000000000..54001442c06 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_crypto.h @@ -0,0 +1,188 @@ +/**************************************************************************//** + * @file crypto.h + * @version V1.10 + * @brief Cryptographic Accelerator driver header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __CRYPTO_H__ +#define __CRYPTO_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CRYPTO_Driver CRYPTO Driver + @{ +*/ + + +/** @addtogroup CRYPTO_EXPORTED_CONSTANTS CRYPTO Exported Constants + @{ +*/ + +#define PRNG_KEY_SIZE_64 0UL /*!< Select to generate 64-bit random key \hideinitializer */ +#define PRNG_KEY_SIZE_128 1UL /*!< Select to generate 128-bit random key \hideinitializer */ +#define PRNG_KEY_SIZE_192 2UL /*!< Select to generate 192-bit random key \hideinitializer */ +#define PRNG_KEY_SIZE_256 3UL /*!< Select to generate 256-bit random key \hideinitializer */ + +#define PRNG_SEED_CONT 0UL /*!< PRNG using current seed \hideinitializer */ +#define PRNG_SEED_RELOAD 1UL /*!< PRNG reload new seed \hideinitializer */ + +#define AES_KEY_SIZE_128 0UL /*!< AES select 128-bit key length \hideinitializer */ +#define AES_KEY_SIZE_192 1UL /*!< AES select 192-bit key length \hideinitializer */ +#define AES_KEY_SIZE_256 2UL /*!< AES select 256-bit key length \hideinitializer */ + +#define AES_MODE_ECB 0UL /*!< AES select ECB mode \hideinitializer */ +#define AES_MODE_CBC 1UL /*!< AES select CBC mode \hideinitializer */ +#define AES_MODE_CFB 2UL /*!< AES select CFB mode \hideinitializer */ +#define AES_MODE_OFB 3UL /*!< AES select OFB mode \hideinitializer */ +#define AES_MODE_CTR 4UL /*!< AES select CTR mode \hideinitializer */ +#define AES_MODE_CBC_CS1 0x10UL /*!< AES select CBC CS1 mode \hideinitializer */ +#define AES_MODE_CBC_CS2 0x11UL /*!< AES select CBC CS2 mode \hideinitializer */ +#define AES_MODE_CBC_CS3 0x12UL /*!< AES select CBC CS3 mode \hideinitializer */ + +#define AES_NO_SWAP 0UL /*!< AES do not swap input and output data \hideinitializer */ +#define AES_OUT_SWAP 1UL /*!< AES swap output data \hideinitializer */ +#define AES_IN_SWAP 2UL /*!< AES swap input data \hideinitializer */ +#define AES_IN_OUT_SWAP 3UL /*!< AES swap both input and output data \hideinitializer */ + +#define CRYPTO_DMA_FIRST 0x4UL /*!< Do first encrypt/decrypt in DMA cascade \hideinitializer */ +#define CRYPTO_DMA_ONE_SHOT 0x5UL /*!< Do one shot encrypt/decrypt with DMA \hideinitializer */ +#define CRYPTO_DMA_CONTINUE 0x6UL /*!< Do continuous encrypt/decrypt in DMA cascade \hideinitializer */ +#define CRYPTO_DMA_LAST 0x7UL /*!< Do last encrypt/decrypt in DMA cascade \hideinitializer */ + + +/*@}*/ /* end of group CRYPTO_EXPORTED_CONSTANTS */ + + +/** @addtogroup CRYPTO_EXPORTED_MACROS CRYPTO Exported Macros + @{ +*/ + +/*----------------------------------------------------------------------------------------------*/ +/* Macros */ +/*----------------------------------------------------------------------------------------------*/ + +/** + * @brief This macro enables PRNG interrupt. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define PRNG_ENABLE_INT(crpt) ((crpt)->INTEN |= CRPT_INTEN_PRNGIEN_Msk) + +/** + * @brief This macro disables PRNG interrupt. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define PRNG_DISABLE_INT(crpt) ((crpt)->INTEN &= ~CRPT_INTEN_PRNGIEN_Msk) + +/** + * @brief This macro gets PRNG interrupt flag. + * @param crpt Specified cripto module + * @return PRNG interrupt flag. + * \hideinitializer + */ +#define PRNG_GET_INT_FLAG(crpt) ((crpt)->INTSTS & CRPT_INTSTS_PRNGIF_Msk) + +/** + * @brief This macro clears PRNG interrupt flag. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define PRNG_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = CRPT_INTSTS_PRNGIF_Msk) + +/** + * @brief This macro enables AES interrupt. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define AES_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_AESIEN_Msk|CRPT_INTEN_AESEIEN_Msk)) + +/** + * @brief This macro disables AES interrupt. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define AES_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_AESIEN_Msk|CRPT_INTEN_AESEIEN_Msk)) + +/** + * @brief This macro gets AES interrupt flag. + * @param crpt Specified cripto module + * @return AES interrupt flag. + * \hideinitializer + */ +#define AES_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_AESIF_Msk|CRPT_INTSTS_AESEIF_Msk)) + +/** + * @brief This macro clears AES interrupt flag. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define AES_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_AESIF_Msk|CRPT_INTSTS_AESEIF_Msk)) + +/** + * @brief This macro enables AES key protection. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define AES_ENABLE_KEY_PROTECT(crpt) ((crpt)->AES_CTL |= CRPT_AES_CTL_KEYPRT_Msk) + +/** + * @brief This macro disables AES key protection. + * @param crpt Specified cripto module + * @return None + * \hideinitializer + */ +#define AES_DISABLE_KEY_PROTECT(crpt) ((crpt)->AES_CTL = ((crpt)->AES_CTL & ~CRPT_AES_CTL_KEYPRT_Msk) | (0x16UL<AES_CTL &= ~CRPT_AES_CTL_KEYPRT_Msk) + +/*@}*/ /* end of group CRYPTO_EXPORTED_MACROS */ + + + +/** @addtogroup CRYPTO_EXPORTED_FUNCTIONS CRYPTO Exported Functions + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Functions */ +/*---------------------------------------------------------------------------------------------------------*/ + +void PRNG_Open(CRPT_T *crpt, uint32_t u32KeySize, uint32_t u32SeedReload, uint32_t u32Seed); +void PRNG_Start(CRPT_T *crpt); +void PRNG_Read(CRPT_T *crpt, uint32_t au32RandKey[]); +void AES_Open(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32EncDec, uint32_t u32OpMode, uint32_t u32KeySize, uint32_t u32SwapType); +void AES_Start(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32DMAMode); +void AES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize); +void AES_SetInitVect(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32IV[]); +void AES_SetDMATransfer(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt); + + +/*@}*/ /* end of group CRYPTO_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CRYPTO_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CRYPTO_H__ */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ + diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_dac.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_dac.h new file mode 100644 index 00000000000..90a539781c3 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_dac.h @@ -0,0 +1,249 @@ +/**************************************************************************//** + * @file dac.h + * @version V0.10 + * @brief M251 series DAC driver header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __DAC_H__ +#define __DAC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup DAC_Driver DAC Driver + @{ +*/ + + +/** @addtogroup DAC_EXPORTED_CONSTANTS DAC Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* DAC_CTL Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define DAC_CTL_LALIGN_RIGHT_ALIGN (0UL<SWTRG = DAC_SWTRG_SWTRG_Msk) + +/** + * @brief Enable DAC data left-aligned. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details User has to load data into DAC_DAT[15:4] bits. DAC_DAT[31:16] and DAC_DAT[3:0] are ignored in DAC conversion. + * \hideinitializer + */ +#define DAC_ENABLE_LEFT_ALIGN(dac) ((dac)->CTL |= DAC_CTL_LALIGN_Msk) + +/** + * @brief Enable DAC data right-aligned. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details User has to load data into DAC_DAT[11:0] bits, DAC_DAT[31:12] are ignored in DAC conversion. + * \hideinitializer + */ +#define DAC_ENABLE_RIGHT_ALIGN(dac) ((dac)->CTL &= ~DAC_CTL_LALIGN_Msk) + +/** + * @brief Enable output voltage buffer. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details The DAC integrates a voltage output buffer that can be used to reduce output impedance and + * drive external loads directly without having to add an external operational amplifier. + * \hideinitializer + */ +#define DAC_ENABLE_BYPASS_BUFFER(dac) ((dac)->CTL |= DAC_CTL_BYPASS_Msk) + +/** + * @brief Disable output voltage buffer. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details This macro is used to disable output voltage buffer. + * \hideinitializer + */ +#define DAC_DISABLE_BYPASS_BUFFER(dac) ((dac)->CTL &= ~DAC_CTL_BYPASS_Msk) + +/** + * @brief Enable the interrupt. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used in M251 DAC. + * @return None + * @details This macro is used to enable DAC interrupt. + * \hideinitializer + */ +#define DAC_ENABLE_INT(dac, u32Ch) ((dac)->CTL |= DAC_CTL_DACIEN_Msk) + +/** + * @brief Disable the interrupt. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used in M251 DAC. + * @return None + * @details This macro is used to disable DAC interrupt. + * \hideinitializer + */ +#define DAC_DISABLE_INT(dac, u32Ch) ((dac)->CTL &= ~DAC_CTL_DACIEN_Msk) + +/** + * @brief Enable DMA under-run interrupt. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details This macro is used to enable DMA under-run interrupt. + * \hideinitializer + */ +#define DAC_ENABLE_DMAUDR_INT(dac) ((dac)->CTL |= DAC_CTL_DMAURIEN_Msk) + +/** + * @brief Disable DMA under-run interrupt. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details This macro is used to disable DMA under-run interrupt. + * \hideinitializer + */ +#define DAC_DISABLE_DMAUDR_INT(dac) ((dac)->CTL &= ~DAC_CTL_DMAURIEN_Msk) + +/** + * @brief Enable PDMA mode. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details DAC DMA request is generated when a hardware trigger event occurs while DMAEN (DAC_CTL[2]) is set. + * \hideinitializer + */ +#define DAC_ENABLE_PDMA(dac) ((dac)->CTL |= DAC_CTL_DMAEN_Msk) + +/** + * @brief Disable PDMA mode. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details This macro is used to disable DMA mode. + * \hideinitializer + */ +#define DAC_DISABLE_PDMA(dac) ((dac)->CTL &= ~DAC_CTL_DMAEN_Msk) + +/** + * @brief Write data for conversion. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used in M251 DAC. + * @param[in] u32Data Decides the data for conversion, valid range are between 0~0xFFF. + * @return None + * @details 12 bit left alignment: user has to load data into DAC_DAT[15:4] bits. + * 12 bit right alignment: user has to load data into DAC_DAT[11:0] bits. + * \hideinitializer + */ +#define DAC_WRITE_DATA(dac, u32Ch, u32Data) ((dac)->DAT = (u32Data)) + +/** + * @brief Read DAC 12-bit holding data. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used in M251 DAC. + * @return Return DAC 12-bit holding data. + * @details This macro is used to read DAC_DAT register. + * \hideinitializer + */ +#define DAC_READ_DATA(dac, u32Ch) ((dac)->DAT) + +/** + * @brief Get the busy state of DAC. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used in M251 DAC. + * @retval 0 Idle state. + * @retval 1 Busy state. + * @details This macro is used to read BUSY bit (DAC_STATUS[8]) to get busy state. + * \hideinitializer + */ +#define DAC_IS_BUSY(dac, u32Ch) (((dac)->STATUS & DAC_STATUS_BUSY_Msk) >> DAC_STATUS_BUSY_Pos) + +/** + * @brief Get the interrupt flag. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used in M251 DAC. + * @retval 0 DAC is in conversion state. + * @retval 1 DAC conversion finish. + * @details This macro is used to read FINISH bit (DAC_STATUS[0]) to get DAC conversion complete finish flag. + * \hideinitializer + */ +#define DAC_GET_INT_FLAG(dac, u32Ch) ((dac)->STATUS & DAC_STATUS_FINISH_Msk) + +/** + * @brief Get the DMA under-run flag. + * @param[in] dac The pointer of the specified DAC module. + * @retval 0 No DMA under-run error condition occurred. + * @retval 1 DMA under-run error condition occurred. + * @details This macro is used to read DMAUDR bit (DAC_STATUS[1]) to get DMA under-run state. + * \hideinitializer + */ +#define DAC_GET_DMAUDR_FLAG(dac) (((dac)->STATUS & DAC_STATUS_DMAUDR_Msk) >> DAC_STATUS_DMAUDR_Pos) + +/** + * @brief This macro clear the interrupt status bit. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used in M251 DAC. + * @return None + * @details User writes FINISH bit (DAC_STATUS[0]) to clear DAC conversion complete finish flag. + * \hideinitializer + */ +#define DAC_CLR_INT_FLAG(dac, u32Ch) ((dac)->STATUS = DAC_STATUS_FINISH_Msk) + +/** + * @brief This macro clear the DMA under-run flag. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details User writes DMAUDR bit (DAC_STATUS[1]) to clear DMA under-run flag. + * \hideinitializer + */ +#define DAC_CLR_DMAUDR_FLAG(dac) ((dac)->STATUS = DAC_STATUS_DMAUDR_Msk) + +void DAC_Open(DAC_T *dac, uint32_t u32Ch, uint32_t u32TrgSrc); +void DAC_Close(DAC_T *dac, uint32_t u32Ch); +uint32_t DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay); + +/*@}*/ /* end of group DAC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group DAC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __DAC_H__ */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_eadc.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_eadc.h new file mode 100644 index 00000000000..42d994d3317 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_eadc.h @@ -0,0 +1,723 @@ +/****************************************************************************//** + * @file eadc.h + * @version V0.10 + * @brief M251 series EADC driver header file + * + * @note + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __EADC_H__ +#define __EADC_H__ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Include related headers */ +/*---------------------------------------------------------------------------------------------------------*/ +#include "M251.h" + + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EADC_Driver EADC Driver + @{ +*/ + +/** @addtogroup EADC_EXPORTED_CONSTANTS EADC Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* EADC_SCTLn Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EADC_SCTL_CHSEL(x) ((x) << EADC_SCTL_CHSEL_Pos) /*!< A/D sample module channel selection */ +#define EADC_SCTL_TRGDLYDIV(x) ((x) << EADC_SCTL_TRGDLYDIV_Pos) /*!< A/D sample module start of conversion trigger delay clock divider selection */ +#define EADC_SCTL_TRGDLYCNT(x) ((x) << EADC_SCTL_TRGDLYCNT_Pos) /*!< A/D sample module start of conversion trigger delay time */ + +#define EADC_SOFTWARE_TRIGGER (0UL<CTL |= EADC_CTL_ADCRST_Msk) + + +/** + * @brief Enable PDMA transfer. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. + * @return None + * @details When A/D conversion is completed, the converted data is loaded into EADC_DATn (n=0~15) register, + * user can enable this bit to generate a PDMA data transfer request. + */ +#define EADC_ENABLE_PDMA(eadc, u32ModuleNum) (eadc)->PDMACTL |= (0x1 << u32ModuleNum) + + +/** + * @brief Disable PDMA transfer. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. + * @return None + * @details This macro is used to disable PDMA transfer. + */ +#define EADC_DISABLE_PDMA(eadc, u32ModuleNum) (eadc)->PDMACTL &= ~(0x1 << u32ModuleNum) + + +/** + * @brief Set ADIFn at A/D start of conversion. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. + * @return None + * @details The A/D converter generates ADIFn (EADC_STATUS2[n], n=0~3) at the start of conversion. + */ +#define EADC_ENABLE_INT_POSITION(eadc, u32ModuleNum) ((((eadc)->SCTL[(u32ModuleNum)])) |= EADC_SCTL_INTPOS_Msk) + + +/** + * @brief Set ADIFn at A/D end of conversion. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. + * @return None + * @details The A/D converter generates ADIFn (EADC_STATUS2[n], n=0~3) at the end of conversion. + */ +#define EADC_DISABLE_INT_POSITION(eadc, u32ModuleNum) ((((eadc)->SCTL[(u32ModuleNum)])) &= (~EADC_SCTL_INTPOS_Msk)) + + +/** + * @brief Enable the interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status. + * This parameter decides which interrupts will be enabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3. + * @return None + * @details The A/D converter generates a conversion end ADIFn (EADC_STATUS2[n], n=0~3) upon the end of specific sample module A/D conversion. + * If ADCIENn bit (EADC_CTL[n+2]) is set then conversion end interrupt request ADINTn is generated (n=0~3). + */ +#define EADC_ENABLE_INT(eadc, u32Mask) ((eadc)->CTL |= ((u32Mask) << EADC_CTL_ADCIEN0_Pos)) + + +/** + * @brief Disable the interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status. + * This parameter decides which interrupts will be disabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3. + * @return None + * @details Specific sample module A/D ADINT0 interrupt function disabled. + */ +#define EADC_DISABLE_INT(eadc, u32Mask) ((eadc)->CTL &= (~((u32Mask) << EADC_CTL_ADCIEN0_Pos))) + + +/** + * @brief Enable the sample module interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3. + * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. + * This parameter decides which sample module interrupts will be enabled, valid range are between 1~0x7FFFF. + * @return None + * @details There are 4 EADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address. + */ +#define EADC_ENABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((((eadc)->INTSRC[(u32IntSel)])) |= (u32ModuleMask)) + + +/** + * @brief Disable the sample module interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3. + * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. + * This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF. + * @return None + * @details There are 4 EADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address. + */ +#define EADC_DISABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((((eadc)->INTSRC[(u32IntSel)])) &= (~(u32ModuleMask))) + + +/** + * @brief Start the A/D conversion. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module. + * This parameter decides which sample module will be converted, valid range are between 1~0x7FFFF. + * Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module 18. + * @return None + * @details After write EADC_SWTRG register to start EADC conversion, the EADC_PENDSTS register will show which sample module will conversion. + */ +#define EADC_START_CONV(eadc, u32ModuleMask) ((eadc)->SWTRG = (u32ModuleMask)) + + +/** + * @brief Cancel the conversion for sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module. + * This parameter decides which sample module will stop the conversion, valid range are between 1~0x7FFFF. + * Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module18. + * @return None + * @details If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it. + */ +#define EADC_STOP_CONV(eadc, u32ModuleMask) ((eadc)->PENDSTS = (u32ModuleMask)) + + +/** + * @brief Get the conversion pending flag. + * @param[in] eadc The pointer of the specified EADC module. + * @return Return the conversion pending sample module. + * @details This STPFn (EADC_PENDSTS[n], n=0~18) bit remains 1 during pending state, when the respective EADC conversion is end, + * the STPFn (EADC_PENDSTS[n], n=0~18) bit is automatically cleared to 0. + */ +#define EADC_GET_PENDING_CONV(eadc) ((eadc)->PENDSTS) + + +/** + * @brief Get the conversion data of the user-specified sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18. + * @return Return the conversion data of the user-specified sample module. + * @details This macro is used to read RESULT bit (EADC_DATn[15:0], n=0~18) field to get conversion data. + */ +#define EADC_GET_CONV_DATA(eadc, u32ModuleNum) ((((eadc)->DAT[(u32ModuleNum)])) & EADC_DAT_RESULT_Msk) + + +/** + * @brief Get the data overrun flag of the user-specified sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of data overrun status bits. Each bit corresponds to a data overrun status, valid range are between 1~0x7FFFF. + * @return Return the data overrun flag of the user-specified sample module. + * @details This macro is used to read OV bit (EADC_STATUS0[31:16], EADC_STATUS1[18:16]) field to get data overrun status. + */ +#define EADC_GET_DATA_OVERRUN_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 >> EADC_STATUS0_OV_Pos) | ((eadc)->STATUS1 & EADC_STATUS1_OV_Msk)) & (u32ModuleMask)) + + +/** + * @brief Get the data valid flag of the user-specified sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of data valid status bits. Each bit corresponds to a data valid status, valid range are between 1~0x7FFFF. + * @return Return the data valid flag of the user-specified sample module. + * @details This macro is used to read VALID bit (EADC_STATUS0[15:0], EADC_STATUS1[2:0]) field to get data overrun status. + */ +#define EADC_GET_DATA_VALID_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 & EADC_STATUS0_VALID_Msk) | (((eadc)->STATUS1 & EADC_STATUS1_VALID_Msk) << 16)) & (u32ModuleMask)) + + +/** + * @brief Get the user-specified interrupt flags. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Mask The combination of interrupt status bits. Each bit corresponds to a interrupt status. + * Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3. + * Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3. + * Or use combination of following pre-define mask: + * - \ref EADC_STATUS2_ADIF0_Msk : ADIF0 mask + * - \ref EADC_STATUS2_ADIF1_Msk : ADIF1 mask + * - \ref EADC_STATUS2_ADIF2_Msk : ADIF2 mask + * - \ref EADC_STATUS2_ADIF3_Msk : ADIF3 mask + * - \ref EADC_STATUS2_ADCMPF0_Msk : ADCMPF0 mask + * - \ref EADC_STATUS2_ADCMPF1_Msk : ADCMPF1 mask + * - \ref EADC_STATUS2_ADCMPF2_Msk : ADCMPF2 mask + * - \ref EADC_STATUS2_ADCMPF3_Msk : ADCMPF3 mask + * @return Return the user-specified interrupt flags. + * @details This macro is used to get the user-specified interrupt flags. + */ +#define EADC_GET_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 & (u32Mask)) + + +/** + * @brief Get the user-specified sample module overrun flags. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status, valid range are between 1~0x7FFFF. + * @return Return the user-specified sample module overrun flags. + * @details This macro is used to get the user-specified sample module overrun flags. + */ +#define EADC_GET_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS & (u32ModuleMask)) + + +/** + * @brief Clear the selected interrupt status bits. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Mask The combination of compare interrupt status bits. Each bit corresponds to a compare interrupt status. + * Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3. + * Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3. + * Or use combination of following pre-define mask: + * - \ref EADC_STATUS2_ADIF0_Msk : ADIF0 mask + * - \ref EADC_STATUS2_ADIF1_Msk : ADIF1 mask + * - \ref EADC_STATUS2_ADIF2_Msk : ADIF2 mask + * - \ref EADC_STATUS2_ADIF3_Msk : ADIF3 mask + * - \ref EADC_STATUS2_ADCMPF0_Msk : ADCMPF0 mask + * - \ref EADC_STATUS2_ADCMPF1_Msk : ADCMPF1 mask + * - \ref EADC_STATUS2_ADCMPF2_Msk : ADCMPF2 mask + * - \ref EADC_STATUS2_ADCMPF3_Msk : ADCMPF3 mask + * @return None + * @details This macro is used to clear clear the selected interrupt status bits. + */ +#define EADC_CLR_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 = (u32Mask)) + + +/** + * @brief Clear the selected sample module overrun status bits. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status. + * Bit 0 is SPOVF0, bit 1 is SPOVF1..., bit 18 is SPOVF18. + * @return None + * @details This macro is used to clear the selected sample module overrun status bits. + */ +#define EADC_CLR_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS = (u32ModuleMask)) + + +/** + * @brief Check all sample module A/D result data register overrun flags. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 None of sample module data register overrun flag is set to 1. + * @retval 1 Any one of sample module data register overrun flag is set to 1. + * @details The AOV bit (EADC_STATUS2[27]) will keep 1 when any one of sample module data register overrun flag OVn (EADC_DATn[16], n=0~18) is set to 1. + */ +#define EADC_IS_DATA_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AOV_Msk) >> EADC_STATUS2_AOV_Pos) + + +/** + * @brief Check all sample module A/D result data register valid flags. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 None of sample module data register valid flag is set to 1. + * @retval 1 Any one of sample module data register valid flag is set to 1. + * @details The AVALID bit (EADC_STATUS2[26]) will keep 1 when any one of sample module data register valid flag VALIDn (EADC_DATn[17], n=0~18) is set to 1. + */ +#define EADC_IS_DATA_VALID(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AVALID_Msk) >> EADC_STATUS2_AVALID_Pos) + + +/** + * @brief Check all A/D sample module start of conversion overrun flags. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 None of sample module event overrun flag is set to 1. + * @retval 1 Any one of sample module event overrun flag is set to 1. + * @details The STOVF bit (EADC_STATUS2[25]) will keep 1 when any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n], n=0~18) is set to 1. + */ +#define EADC_IS_SAMPLE_MODULE_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_STOVF_Msk) >> EADC_STATUS2_STOVF_Pos) + + +/** + * @brief Check all A/D interrupt flag overrun bits. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 None of ADINT interrupt flag is overwritten to 1. + * @retval 1 Any one of ADINT interrupt flag is overwritten to 1. + * @details The ADOVIF bit (EADC_STATUS2[24]) will keep 1 when any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[n+8], n=0~3) is overwritten to 1. + */ +#define EADC_IS_INT_FLAG_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_ADOVIF_Msk) >> EADC_STATUS2_ADOVIF_Pos) + + +/** + * @brief Get the busy state of EADC. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 Idle state. + * @retval 1 Busy state. + * @details This macro is used to read BUSY bit (EADC_STATUS2[23]) to get busy state. + */ +#define EADC_IS_BUSY(eadc) (((eadc)->STATUS2 & EADC_STATUS2_BUSY_Msk) >> EADC_STATUS2_BUSY_Pos) + + +/** + * @brief Configure the comparator 0 and enable it. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum specifies the compare sample module, valid values are from 0 to 18. + * @param[in] u32Condition specifies the compare condition. Valid values are: + * - \ref EADC_CMP_CMPCOND_LESS_THAN : The compare condition is "less than the compare value" + * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL : The compare condition is "greater than or equal to the compare value" + * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. + * @param[in] u32MatchCount specifies the match count setting, valid range are between 1~0xF. + * @return None + * @details For example, EADC_ENABLE_CMP0(EADC, 5, EADC_CMP_CMPCOND_GREATER_OR_EQUAL, 0x800, 10); + * Means EADC will assert comparator 0 flag if sample module 5 conversion result is greater or + * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. + */ +#define EADC_ENABLE_CMP0(eadc,\ + u32ModuleNum,\ + u32Condition,\ + u16CMPData,\ + u32MatchCount) ((eadc)->CMP[0] = (((u32ModuleNum) << EADC_CMP_CMPSPL_Pos) |\ + (u32Condition) |\ + ((u16CMPData) << EADC_CMP_CMPDAT_Pos) |\ + (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos) |\ + EADC_CMP_ADCMPEN_Msk)) + + +/** + * @brief Configure the comparator 1 and enable it. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. + * @param[in] u32Condition specifies the compare condition. Valid values are: + * - \ref EADC_CMP_CMPCOND_LESS_THAN : The compare condition is "less than the compare value" + * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL : The compare condition s "greater than or equal to the compare value" + * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. + * @param[in] u32MatchCount specifies the match count setting, valid range are between 1~0xF. + * @return None + * @details For example, EADC_ENABLE_CMP1(EADC, 5, EADC_CMP_CMPCOND_GREATER_OR_EQUAL, 0x800, 10); + * Means EADC will assert comparator 1 flag if sample module 5 conversion result is greater or + * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. + */ +#define EADC_ENABLE_CMP1(eadc,\ + u32ModuleNum,\ + u32Condition,\ + u16CMPData,\ + u32MatchCount) ((eadc)->CMP[1] = (((u32ModuleNum) << EADC_CMP_CMPSPL_Pos) |\ + (u32Condition) |\ + ((u16CMPData) << EADC_CMP_CMPDAT_Pos) |\ + (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos) |\ + EADC_CMP_ADCMPEN_Msk)) + + +/** + * @brief Configure the comparator 2 and enable it. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. + * @param[in] u32Condition specifies the compare condition. Valid values are: + * - \ref EADC_CMP_CMPCOND_LESS_THAN : The compare condition is "less than the compare value" + * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL : The compare condition is "greater than or equal to the compare value" + * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. + * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF. + * @return None + * @details For example, EADC_ENABLE_CMP2(EADC, 5, EADC_CMP_CMPCOND_GREATER_OR_EQUAL, 0x800, 10); + * Means EADC will assert comparator 2 flag if sample module 5 conversion result is greater or + * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. + */ +#define EADC_ENABLE_CMP2(eadc,\ + u32ModuleNum,\ + u32Condition,\ + u16CMPData,\ + u32MatchCount) ((eadc)->CMP[2] = (((u32ModuleNum) << EADC_CMP_CMPSPL_Pos) |\ + (u32Condition) |\ + ((u16CMPData) << EADC_CMP_CMPDAT_Pos) |\ + (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos) |\ + EADC_CMP_ADCMPEN_Msk)) + + +/** + * @brief Configure the comparator 3 and enable it. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. + * @param[in] u32Condition specifies the compare condition. Valid values are: + * - \ref EADC_CMP_CMPCOND_LESS_THAN : The compare condition is "less than the compare value" + * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL : The compare condition is "greater than or equal to the compare value" + * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. + * @param[in] u32MatchCount specifies the match count setting, valid range are between 1~0xF. + * @return None + * @details For example, EADC_ENABLE_CMP3(EADC, 5, EADC_CMP_CMPCOND_GREATER_OR_EQUAL, 0x800, 10); + * Means EADC will assert comparator 3 flag if sample module 5 conversion result is greater or + * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. + */ +#define EADC_ENABLE_CMP3(eadc,\ + u32ModuleNum,\ + u32Condition,\ + u16CMPData,\ + u32MatchCount) ((eadc)->CMP[3] = (((u32ModuleNum) << EADC_CMP_CMPSPL_Pos) |\ + (u32Condition) |\ + ((u16CMPData) << EADC_CMP_CMPDAT_Pos) |\ + (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos) |\ + EADC_CMP_ADCMPEN_Msk)) + + +/** + * @brief Enable the compare window mode. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32CMP Specifies the compare register, valid values are 0 and 2. + * @return None + * @details ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched. + * ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched. + */ +#define EADC_ENABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((((eadc)->CMP[(u32CMP)])) |= EADC_CMP_CMPWEN_Msk) + + +/** + * @brief Disable the compare window mode. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32CMP Specifies the compare register, valid values are 0 and 2. + * @return None + * @details ADCMPF0 (EADC_STATUS2[4]) will be set when EADC_CMP0 compared condition matched. + * ADCMPF2 (EADC_STATUS2[6]) will be set when EADC_CMP2 compared condition matched. + */ +#define EADC_DISABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((((eadc)->CMP[(u32CMP)])) &= (~EADC_CMP_CMPWEN_Msk)) + + +/** + * @brief Enable the compare interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32CMP Specifies the compare register, valid values are from 0 to 3. + * @return None + * @details If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) + * and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[n+4], n=0~3) will be asserted, in the meanwhile, + * if ADCMPIE (EADC_CMPn[1], n=0~3) is set to 1, a compare interrupt request is generated. + */ +#define EADC_ENABLE_CMP_INT(eadc, u32CMP) ((((eadc)->CMP[(u32CMP)])) |= EADC_CMP_ADCMPIE_Msk) + + +/** + * @brief Disable the compare interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3. + * @return None + * @details This macro is used to disable the compare interrupt. + */ +#define EADC_DISABLE_CMP_INT(eadc, u32CMP) ((((eadc)->CMP[(u32CMP)])) &= (~EADC_CMP_ADCMPIE_Msk)) + + +/** + * @brief Disable comparator 0. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable comparator 0. + */ +#define EADC_DISABLE_CMP0(eadc) ((eadc)->CMP[0] &= (~EADC_CMP_ADCMPEN_Msk)) + + +/** + * @brief Disable comparator 1. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable comparator 1. + */ +#define EADC_DISABLE_CMP1(eadc) ((eadc)->CMP[1] &= (~EADC_CMP_ADCMPEN_Msk)) + + +/** + * @brief Disable comparator 2. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable comparator 2. + */ +#define EADC_DISABLE_CMP2(eadc) ((eadc)->CMP[2] &= (~EADC_CMP_ADCMPEN_Msk)) + + +/** + * @brief Disable comparator 3. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable comparator 3. + */ +#define EADC_DISABLE_CMP3(eadc) ((eadc)->CMP[3] &= (~EADC_CMP_ADCMPEN_Msk)) + + +/** + * @brief Enable conversion result left alignment. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. + * @return None + * @details The 12-bit conversion result will be left aligned and stored in EADC_DATn[15:4] (n=0~15). + */ +#define EADC_ENABLE_LEFT_ALIGN(eadc, u32ModuleNum) ((((eadc)->MCTL1[(u32ModuleNum)])) |= EADC_MCTL1_ALIGN_Msk) + + +/** + * @brief Disable conversion result left alignment. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. + * @return None + * @details The 12-bit conversion result will be right aligned and stored in EADC_DATn[11:0] (n=0~15). + */ +#define EADC_DISABLE_LEFT_ALIGN(eadc, u32ModuleNum) ((((eadc)->MCTL1[(u32ModuleNum)])) &= (~EADC_MCTL1_ALIGN_Msk)) + + +/** + * @brief Enable average mode. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. + * @return None + * @details Conversion results in data register will be averaged. + * @note This average mode needs to work with accumulated mode that configured by ACU (EADC_MnCTL1[7:4], n=0~15) bit field. + */ +#define EADC_ENABLE_AVG(eadc, u32ModuleNum) ((((eadc)->MCTL1[(u32ModuleNum)])) |= EADC_MCTL1_AVG_Msk) + + +/** + * @brief Disable average mode. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. + * @return None + * @details Conversion results in data register will not be averaged. + */ +#define EADC_DISABLE_AVG(eadc, u32ModuleNum) ((((eadc)->MCTL1[(u32ModuleNum)])) &= (~EADC_MCTL1_AVG_Msk)) + + +/** + * @brief Configure the Accumulation feature and enable it. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 15. + * @param[in] u16ACUNum specifies the number of accumulation, valid values are + * - \ref EADC_MCTL1_ACU_1 : 1 conversion result will be accumulated. + * - \ref EADC_MCTL1_ACU_2 : 2 conversion result will be accumulated. + * - \ref EADC_MCTL1_ACU_4 : 4 conversion result will be accumulated. + * - \ref EADC_MCTL1_ACU_8 : 8 conversion result will be accumulated. + * - \ref EADC_MCTL1_ACU_16 : 16 conversion result will be accumulated. + * - \ref EADC_MCTL1_ACU_32 : 32 conversion result will be accumulated. The result is right shift 1 bit to fit within the available 16-bit register size. + * - \ref EADC_MCTL1_ACU_64 : 64 conversion result will be accumulated. The result is right shift 2 bits to fit within the available 16-bit register size. + * - \ref EADC_MCTL1_ACU_128 : 128 conversion result will be accumulated. The result is right shift 3 bits to fit within the available 16-bit register size. + * - \ref EADC_MCTL1_ACU_256 : 256 conversion result will be accumulated. The result is right shift 4 bits to fit within the available 16-bit register size. + * @return None + * @details When accumulating more than 16 samples, the result will be too large to match the + * 16-bit RESULT register size (EADC_DATn[15:0]. To avoid overflow, the result is + * right shifted automatically to fit within the available 16-bit register size. + * The number of automatic right shifts is specified in parameter list above. + * + */ +#define EADC_ENABLE_ACU(eadc,\ + u32ModuleNum,\ + u16ACUNum) ((((eadc)->MCTL1[(u32ModuleNum)])) = (((((eadc)->MCTL1[(u32ModuleNum)])) & (~EADC_MCTL1_ACU_Msk)) |\ + (u16ACUNum))) + + +/** + * @brief Disable the Accumulation feature. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 15. + * @return None + */ +#define EADC_DISABLE_ACU(eadc, u32ModuleNum) ((((eadc)->MCTL1[(u32ModuleNum)])) &= (~EADC_MCTL1_ACU_Msk)) + + +/** + * @brief Configure the Auto Power On/Off mode and enable it. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32PowerOffThreshold specifies the auto power off threshold time. Valid values are: + * - \ref EADC_PWRCTL_AUTOPDTHT_8 : Auto Power Off Threshold Time 8 EADC clocks + * - \ref EADC_PWRCTL_AUTOPDTHT_16 : Auto Power Off Threshold Time 16 EADC clocks + * - \ref EADC_PWRCTL_AUTOPDTHT_32 : Auto Power Off Threshold Time 32 EADC clocks + * - \ref EADC_PWRCTL_AUTOPDTHT_64 : Auto Power Off Threshold Time 64 EADC clocks + * - \ref EADC_PWRCTL_AUTOPDTHT_128 : Auto Power Off Threshold Time 128 EADC clocks + * - \ref EADC_PWRCTL_AUTOPDTHT_256 : Auto Power Off Threshold Time 256 EADC clocks + * @param[in] u32PowerOnTime specifies the auto power on start-up time, valid range are between 0~0xFFF. + * @return None + * @details If the interval of time in idle state is longer than u32PowerOffThreshold, EADC will + * auto power off A/D converter analog circuit to reduce power consumption. + * EADC will automatically wakes-up when a conversion is started by software or hardware trigger. + * A start-up time is automatically inserted between the trigger event and the sampling time of the EADC. + * The start-up time = ((1/EADC_CLK) * u32PowerOnTime) and must be longer than 10us. + * @note The ADCEN bit (EADC_CTL[0]) will be set to 0 when EADC power off and set to 1 when EADC be wake-up. + */ +#define EADC_ENABLE_AUTOFF(eadc,\ + u32PowerOffThreshold,\ + u32PowerOnTime) ((eadc)->PWRCTL = ((u32PowerOffThreshold) |\ + ((u32PowerOnTime) << EADC_PWRCTL_STUPT_Pos) |\ + EADC_PWRCTL_AUTOFF_Msk)) + + +/** + * @brief Disable the Auto Power On/Off mode. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + */ +#define EADC_DISABLE_AUTOFF(eadc) ((eadc)->PWRCTL &= (~EADC_PWRCTL_AUTOFF_Msk)) + + +/** + * @brief Configure the Offset Cancellation feature and enable it. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] i16OffsetCancel specifies the signed value of offset cancellation, valid values are -16 to 15. + * @return None + * @details When i16OffsetCancel is set to 0, the offset cancellation trim bits have no effect to A/D result. + */ +#define EADC_ENABLE_OFFSETCANCEL(eadc,\ + i16OffsetCancel) {(eadc)->CTL |= EADC_CTL_CALEN_Msk;\ + (eadc)->OFFSETCAL = (i16OffsetCancel & EADC_OFFSETCAL_OFFSETCANCEL_Msk);} + + +/** + * @brief Disable the Offset Cancellation feature. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + */ +#define EADC_DISABLE_OFFSETCANCEL(eadc) {(eadc)->OFFSETCAL = 0;\ + (eadc)->CTL &= (~EADC_CTL_CALEN_Msk);} + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define EADC functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +void EADC_Open(EADC_T *eadc, uint32_t u32InputMode); +void EADC_Close(EADC_T *eadc); +void EADC_ConfigSampleModule(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerSource, uint32_t u32Channel); +void EADC_SetTriggerDelayTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerDelayTime, uint32_t u32DelayClockDivider); +void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime); + +/*@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EADC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __EADC_H__ */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_ebi.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_ebi.h new file mode 100644 index 00000000000..9ce465b6cad --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_ebi.h @@ -0,0 +1,350 @@ +/**************************************************************************//** +* @file ebi.h +* @version V0.10 +* @brief M251 series EBI driver source file +* +* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. +****************************************************************************/ +#ifndef __EBI_H__ +#define __EBI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EBI_Driver EBI Driver + @{ +*/ + +/** @addtogroup EBI_EXPORTED_FUNCTIONS EBI Exported Functions + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* Miscellaneous Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_BANK0_BASE_ADDR 0x60000000UL /*!< EBI bank0 base address \hideinitializer */ +#define EBI_BANK1_BASE_ADDR 0x60100000UL /*!< EBI bank1 base address \hideinitializer */ +#define EBI_BANK2_BASE_ADDR 0x60200000UL /*!< EBI bank2 base address \hideinitializer */ +#define EBI_MAX_SIZE 0x00100000UL /*!< Maximum EBI size for each bank is 1 MB \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Constants for EBI bank number */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_BANK0 0UL /*!< EBI bank 0 \hideinitializer */ +#define EBI_BANK1 1UL /*!< EBI bank 1 \hideinitializer */ +#define EBI_BANK2 2UL /*!< EBI bank 2 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Constants for EBI data bus width */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_BUSWIDTH_8BIT 8UL /*!< EBI bus width is 8-bit \hideinitializer */ +#define EBI_BUSWIDTH_16BIT 16UL /*!< EBI bus width is 16-bit \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Constants for EBI CS Active Level */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_CS_ACTIVE_LOW 0UL /*!< EBI CS active level is low \hideinitializer */ +#define EBI_CS_ACTIVE_HIGH 1UL /*!< EBI CS active level is high \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Constants for EBI MCLK divider and Timing */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_MCLKDIV_1 0x0UL /*!< EBI output clock(MCLK) is HCLK/1 \hideinitializer */ +#define EBI_MCLKDIV_2 0x1UL /*!< EBI output clock(MCLK) is HCLK/2 \hideinitializer */ +#define EBI_MCLKDIV_4 0x2UL /*!< EBI output clock(MCLK) is HCLK/4 \hideinitializer */ +#define EBI_MCLKDIV_8 0x3UL /*!< EBI output clock(MCLK) is HCLK/8 \hideinitializer */ +#define EBI_MCLKDIV_16 0x4UL /*!< EBI output clock(MCLK) is HCLK/16 \hideinitializer */ +#define EBI_MCLKDIV_32 0x5UL /*!< EBI output clock(MCLK) is HCLK/32 \hideinitializer */ +#define EBI_MCLKDIV_64 0x6UL /*!< EBI output clock(MCLK) is HCLK/64 \hideinitializer */ +#define EBI_MCLKDIV_128 0x7UL /*!< EBI output clock(MCLK) is HCLK/128 \hideinitializer */ + +#define EBI_TIMING_FASTEST 0x0UL /*!< EBI timing is the fastest \hideinitializer */ +#define EBI_TIMING_VERYFAST 0x1UL /*!< EBI timing is very fast \hideinitializer */ +#define EBI_TIMING_FAST 0x2UL /*!< EBI timing is fast \hideinitializer */ +#define EBI_TIMING_NORMAL 0x3UL /*!< EBI timing is normal \hideinitializer */ +#define EBI_TIMING_SLOW 0x4UL /*!< EBI timing is slow \hideinitializer */ +#define EBI_TIMING_VERYSLOW 0x5UL /*!< EBI timing is very slow \hideinitializer */ +#define EBI_TIMING_SLOWEST 0x6UL /*!< EBI timing is the slowest \hideinitializer */ + +#define EBI_OPMODE_NORMAL 0x0UL /*!< EBI bus operate in normal mode \hideinitializer */ +#define EBI_OPMODE_CACCESS (EBI_CTL_CACCESS_Msk) /*!< EBI bus operate in Continuous Data Access mode \hideinitializer */ + +/*@}*/ /* end of group EBI_EXPORTED_CONSTANTS */ + + +/** @addtogroup M251_EBI_EXPORTED_FUNCTIONS EBI Exported Functions + @{ +*/ + +/** + * @brief Read 8-bit data on EBI bank0 + * + * @param[in] u32Addr The data address on EBI bank0. + * + * @return 8-bit Data + * + * @details This macro is used to read 8-bit data from specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BANK0_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 8-bit data to EBI bank0 + * + * @param[in] u32Addr The data address on EBI bank0. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 8-bit data to specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 16-bit data on EBI bank0 + * + * @param[in] u32Addr The data address on EBI bank0. + * + * @return 16-bit Data + * + * @details This macro is used to read 16-bit data from specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BANK0_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 16-bit data to EBI bank0 + * + * @param[in] u32Addr The data address on EBI bank0. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 16-bit data to specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 32-bit data on EBI bank0 + * + * @param[in] u32Addr The data address on EBI bank0. + * + * @return 32-bit Data + * + * @details This macro is used to read 32-bit data from specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BANK0_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 32-bit data to EBI bank0 + * + * @param[in] u32Addr The data address on EBI bank0. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 32-bit data to specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 8-bit data on EBI bank1 + * + * @param[in] u32Addr The data address on EBI bank1. + * + * @return 8-bit Data + * + * @details This macro is used to read 8-bit data from specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BANK1_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 8-bit data to EBI bank1 + * + * @param[in] u32Addr The data address on EBI bank1. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 8-bit data to specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 16-bit data on EBI bank1 + * + * @param[in] u32Addr The data address on EBI bank1. + * + * @return 16-bit Data + * + * @details This macro is used to read 16-bit data from specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BANK1_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 16-bit data to EBI bank1 + * + * @param[in] u32Addr The data address on EBI bank1. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 16-bit data to specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 32-bit data on EBI bank1 + * + * @param[in] u32Addr The data address on EBI bank1. + * + * @return 32-bit Data + * + * @details This macro is used to read 32-bit data from specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BANK1_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 32-bit data to EBI bank1 + * + * @param[in] u32Addr The data address on EBI bank1. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 32-bit data to specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 8-bit data on EBI bank2 + * + * @param[in] u32Addr The data address on EBI bank2. + * + * @return 8-bit Data + * + * @details This macro is used to read 8-bit data from specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BANK2_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 8-bit data to EBI bank2 + * + * @param[in] u32Addr The data address on EBI bank2. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 8-bit data to specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK2_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 16-bit data on EBI bank2 + * + * @param[in] u32Addr The data address on EBI bank2. + * + * @return 16-bit Data + * + * @details This macro is used to read 16-bit data from specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BANK2_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 16-bit data to EBI bank2 + * + * @param[in] u32Addr The data address on EBI bank2. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 16-bit data to specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK2_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Read 32-bit data on EBI bank2 + * + * @param[in] u32Addr The data address on EBI bank2. + * + * @return 32-bit Data + * + * @details This macro is used to read 32-bit data from specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BANK2_BASE_ADDR+(u32Addr)))) + +/** + * @brief Write 32-bit data to EBI bank2 + * + * @param[in] u32Addr The data address on EBI bank2. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 32-bit data to specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK2_BASE_ADDR+(u32Addr))) = (u32Data)) + +/** + * @brief Enable EBI Write Buffer + * + * @param None + * + * @return None + * + * @details This macro is used to improve EBI write operation for EBI bank0 and bank1. + * \hideinitializer + */ +#define EBI_ENABLE_WRITE_BUFFER() (EBI->CTL0 |= EBI_CTL_WBUFEN_Msk); + +/** + * @brief Disable EBI Write Buffer + * + * @param None + * + * @return None + * + * @details This macro is used to disable EBI write buffer function. + * \hideinitializer + */ +#define EBI_DISABLE_WRITE_BUFFER() (EBI->CTL0 &= ~EBI_CTL_WBUFEN_Msk); + +void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel); +void EBI_Close(uint32_t u32Bank); +void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv); + +/*@}*/ /* end of group EBI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EBI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __EBI_H__ */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_fmc.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_fmc.h new file mode 100644 index 00000000000..5a16f9a03d5 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_fmc.h @@ -0,0 +1,697 @@ +/**************************************************************************//** + * @file fmc.h + * @version V3.0 + * @brief M251 Series Flash Memory Controller(FMC) driver header file + * + * @note + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ +#ifndef __FMC_H__ +#define __FMC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup FMC_Driver FMC Driver + @{ +*/ + +/** @addtogroup FMC_EXPORTED_CONSTANTS FMC Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Global constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define ISBEN 0 + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Base Address */ +/*---------------------------------------------------------------------------------------------------------*/ +#define FMC_APROM_BASE 0x00000000UL /*!< APROM Base Address */ +#define FMC_APROM_END 0x00040000UL /*!< APROM end address */ +#define FMC_LDROM_BASE 0x00100000UL /*!< LDROM Base Address */ +#define FMC_LDROM_END 0x00101000UL /*!< LDROM end address */ +#define FMC_XOM_BASE 0x00200000UL /*!< XOM Base Address */ +#define FMC_CONFIG_BASE 0x00300000UL /*!< CONFIG Base Address */ + +#define FMC_CONFIG0_ADDR (FMC_CONFIG_BASE) /*!< CONFIG 0 Address */ +#define FMC_CONFIG1_ADDR (FMC_CONFIG_BASE + 0x4UL) /*!< CONFIG 1 Address */ +#define FMC_CONFIG2_ADDR (FMC_CONFIG_BASE + 0x8UL) /*!< CONFIG 2 Address */ + +#define FMC_XOMR0BASE_ADDR (FMC_XOM_BASE) /*!< XOMR 0 Base Address */ + +#define FMC_APROM_SIZE FMC_APROM_END /*!< APROM Size */ +#define FMC_LDROM_SIZE 0x1000UL /*!< LDROM Size (4 Kbytes) */ + +#define FMC_FLASH_PAGE_SIZE 0x200UL /*!< Flash Page Size (512 Bytes) */ +#define FMC_PAGE_ADDR_MASK 0xFFFFFE00UL /*!< Flash page address mask */ +/*---------------------------------------------------------------------------------------------------------*/ +/* ISPCTL constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define FMC_ISPCTL_BS_LDROM 0x1UL /*!< ISPCTL setting to select to boot from LDROM */ +#define FMC_ISPCTL_BS_APROM 0x0UL /*!< ISPCTL setting to select to boot from APROM */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* ISPCMD constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define FMC_ISPCMD_READ 0x00UL /*!< ISP Command: Read Flash */ +#define FMC_ISPCMD_READ_UID 0x04UL /*!< ISP Command: Read Unique ID */ +#define FMC_ISPCMD_READ_ALL1 0x08UL /*!< ISP Command: Read all-one result */ +#define FMC_ISPCMD_READ_CID 0x0BUL /*!< ISP Command: Read Company ID */ +#define FMC_ISPCMD_READ_PID 0x0CUL /*!< ISP Command: Read Device ID */ +#define FMC_ISPCMD_CHECKSUM 0x0DUL /*!< ISP Command: Read Checksum */ +#define FMC_ISPCMD_PROGRAM 0x21UL /*!< ISP Command: 32-bit Program Flash */ +#define FMC_ISPCMD_PAGE_ERASE 0x22UL /*!< ISP Command: Page Erase Flash */ +#define FMC_ISPCMD_MULTI_PROG 0x27UL /*!< ISP Command: Flash Multi-Word Program */ +#define FMC_ISPCMD_RUN_ALL1 0x28UL /*!< ISP Command: Run all-one verification*/ +#define FMC_ISPCMD_CAL_CHECKSUM 0x2DUL /*!< ISP Command: Run Check Calculation */ +#define FMC_ISPCMD_VECMAP 0x2EUL /*!< ISP Command: Set vector mapping */ + +#define READ_ALLONE_YES 0xA11FFFFFUL /*!< Check-all-one result is all one. */ +#define READ_ALLONE_NOT 0xA1100000UL /*!< Check-all-one result is not all one. */ +#define READ_ALLONE_CMD_FAIL 0xFFFFFFFFUL /*!< Check-all-one command failed. */ + +/*@}*/ /* end of group FMC_EXPORTED_CONSTANTS */ + +/** @addtogroup FMC_EXPORTED_FUNCTIONS FMC Exported Functions + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* FMC Macro Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +/** + * @brief Enable ISP Function + * + * @param None + * + * @return None + * + * @details This function will set ISPEN bit of ISPCTL control register to enable ISP function. + * + */ +#define FMC_ENABLE_ISP() (FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk) /*!< Enable ISP Function */ + +/** + * @brief Disable ISP Function + * + * @param None + * + * @return None + * + * @details This function will clear ISPEN bit of ISPCTL control register to disable ISP function. + * + */ +#define FMC_DISABLE_ISP() (FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk) /*!< Disable ISP Function */ + +/** + * @brief Enable LDROM Update Function + * + * @param None + * + * @return None + * + * @details This function will set LDUEN bit of ISPCTL control register to enable LDROM update function. + * User needs to set LDUEN bit before they can update LDROM. + * + */ +#define FMC_ENABLE_LD_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_LDUEN_Msk) /*!< Enable LDROM Update Function */ + +/** + * @brief Disable LDROM Update Function + * + * @param None + * + * @return None + * + * @details This function will set ISPEN bit of ISPCTL control register to disable LDROM update function. + * + */ +#define FMC_DISABLE_LD_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_LDUEN_Msk) /*!< Disable LDROM Update Function */ + +/** + * @brief Enable User Configuration Update Function + * + * @param None + * + * @return None + * + * @details This function will set CFGUEN bit of ISPCTL control register to enable User Configuration update function. + * User needs to set CFGUEN bit before they can update User Configuration area. + * + */ +#define FMC_ENABLE_CFG_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_CFGUEN_Msk) /*!< Enable CONFIG Update Function */ + +/** + * @brief Disable User Configuration Update Function + * + * @param None + * + * @return None + * + * @details This function will clear CFGUEN bit of ISPCTL control register to disable User Configuration update function. + * + */ +#define FMC_DISABLE_CFG_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_CFGUEN_Msk) /*!< Disable CONFIG Update Function */ + + +/** + * @brief Enable APROM Update Function + * + * @param None + * + * @return None + * + * @details This function will set APUEN bit of ISPCTL control register to enable APROM update function. + * User needs to set APUEN bit before they can update APROM in APROM boot mode. + * + */ +#define FMC_ENABLE_AP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_APUEN_Msk) /*!< Enable APROM Update Function */ + +/** + * @brief Disable APROM Update Function + * + * @param None + * + * @return None + * + * @details This function will clear APUEN bit of ISPCTL control register to disable APROM update function. + * + */ +#define FMC_DISABLE_AP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_APUEN_Msk) /*!< Disable APROM Update Function */ + +/** + * @brief Next Booting Selection function + * + * @param[in] x Booting from APROM(0)/LDROM(1) + * + * @return None + * + * @details This function will set MCU next booting from LDROM/APROM. + * + * @note When use this macro, the Boot Loader booting selection MBS(CONFIG0[5]) must be set. + * + */ +#define FMC_SELECT_NEXT_BOOT(x) (FMC->ISPCTL = (FMC->ISPCTL & ~FMC_ISPCTL_BS_Msk) | ((x) << FMC_ISPCTL_BS_Pos)) /*!< Select Next Booting, x = 0 or 1 */ + +/** + * @brief Get MCU Booting Status + * + * @param None + * + * @return None + * + * @details This function will get status of chip next booting from LDROM/APROM. + * + */ +#define FMC_GET_BOOT_STATUS() ((FMC->ISPCTL & FMC_ISPCTL_BS_Msk)?1:0) /*!< Get MCU Booting Status */ + +/** + * @brief Get ISP fail flag + * + * @param None + * + * @return None + * + * @details This function will get the status of ISP falil flag + * + */ +#define FMC_GET_FAIL_FLAG() ((FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) ? 1UL : 0UL) /*!< Get ISP fail flag */ + +/** + * @brief Clear ISP fail flag + * + * @param None + * + * @return None + * + * @details This function will clear the status of ISP falil flag + * + */ +#define FMC_CLR_FAIL_FLAG() (FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk) /*!< Clear ISP fail flag */ + +/** + * @brief Disable APROM update function + * + * @param None + * + * @return None + * + * @details Disable APROM update function will forbid APROM programming when boot form APROM. + * APROM update is default to be disable. + * + */ +#define FMC_DisableAPUpdate() (FMC->ISPCTL &= ~FMC_ISPCTL_APUEN_Msk) /*!< Disable AP update */ + +/** + * @brief Disable User Configuration update function + * + * @param None + * + * @return None + * + * @details Disable User Configuration update function will forbid User Configuration programming. + * User Configuration update is default to be disable. + */ +#define FMC_DisableConfigUpdate() (FMC->ISPCTL &= ~FMC_ISPCTL_CFGUEN_Msk) /*!< Disable config update */ + +/** + * @brief Disable LDROM update function + * + * @param None + * + * @return None + + * @details Disable LDROM update function will forbid LDROM programming. + * LDROM update is default to be disable. + */ +#define FMC_DisableLDUpdate() (FMC->ISPCTL &= ~FMC_ISPCTL_LDUEN_Msk) /*!< Disable LD update */ + +/** + * @brief Enable APROM update function + * + * @param None + * + * @return None + * + * @details Enable APROM to be able to program when boot from APROM. + * + */ +#define FMC_EnableAPUpdate() (FMC->ISPCTL |= FMC_ISPCTL_APUEN_Msk) /*!< Enable AP update */ + +/** + * @brief Enable User Configuration update function + * + * @param None + * + * @return None + * + * @details Enable User Configuration to be able to program. + * + */ +#define FMC_EnableConfigUpdate() (FMC->ISPCTL |= FMC_ISPCTL_CFGUEN_Msk) /*!< Enable config update */ + +/** + * @brief Enable LDROM update function + * + * @param None + * + * @return None + * + * @details Enable LDROM to be able to program. + * + */ +#define FMC_EnableLDUpdate() (FMC->ISPCTL |= FMC_ISPCTL_LDUEN_Msk) /*!< Enable LD update */ + + + +/*---------------------------------------------------------------------------------------------------------*/ +/* inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +static __INLINE uint32_t FMC_ReadUID(uint8_t u8Index); +static __INLINE uint32_t FMC_ReadCID(void); +static __INLINE uint32_t FMC_ReadPID(void); +static __INLINE uint32_t FMC_ReadUCID(uint32_t u32Index); +static __INLINE uint32_t FMC_ReadVBGCode(void); +static __INLINE uint32_t FMC_ReadVTEMPCode(void); +static __INLINE uint32_t FMC_ReadADCOffset(void); +static __INLINE void FMC_SetVectorPageAddr(uint32_t u32PageAddr); +static __INLINE uint32_t FMC_GetVECMAP(void); +static __INLINE uint32_t FMC_GetCheckSum(uint32_t u32Addr, int32_t i32Size); +static __INLINE void FMC_Write128(uint32_t u32Addr, uint32_t pu32Buf[]); + + +/** + * @brief Read Unique ID + * + * @param[in] u8Index UID index. 0 = UID[31:0], 1 = UID[63:32], 2 = UID[95:64] + * + * @return The 32-bit unique ID data of specified UID index. + * + * @details To read out 96-bit Unique ID. + * + */ +static __INLINE uint32_t FMC_ReadUID(uint8_t u8Index) +{ + FMC->ISPCMD = FMC_ISPCMD_READ_UID; + FMC->ISPADDR = ((uint32_t)u8Index << 2u); + FMC->ISPDAT = 0u; + FMC->ISPTRG = 0x1u; +#if ISBEN + __ISB(); +#endif + + while (FMC->ISPTRG) {} + + return FMC->ISPDAT; +} + +/** + * @brief Read company ID + * + * @param None + * + * @return The company ID (32-bit) + * + * @details The company ID of Nuvoton is fixed to be 0xDA + * + */ +static __INLINE uint32_t FMC_ReadCID(void) +{ + FMC->ISPCMD = FMC_ISPCMD_READ_CID; /* Set ISP Command Code */ + FMC->ISPADDR = 0x0u; /* Must keep 0x0 when read CID */ + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */ +#if ISBEN + __ISB(); +#endif /* To make sure ISP/CPU be Synchronized */ + + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */ + + return FMC->ISPDAT; +} + +/** + * @brief Read product ID + * + * @param None + * + * @return The product ID (32-bit) + * + * @details This function is used to read product ID. + * + */ +static __INLINE uint32_t FMC_ReadPID(void) +{ + FMC->ISPCMD = FMC_ISPCMD_READ_PID; /* Set ISP Command Code */ + FMC->ISPADDR = 0x04u; /* Must keep 0x4 when read PID */ + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */ +#if ISBEN + __ISB(); +#endif /* To make sure ISP/CPU be Synchronized */ + + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */ + + return FMC->ISPDAT; +} + +/** + * @brief To read UCID + * + * @param[in] u32Index Index of the UCID to read. u32Index must be 0, 1, 2, or 3. + * + * @return The UCID of specified index + * + * @details This function is used to read unique chip ID (UCID). + * + */ +static __INLINE uint32_t FMC_ReadUCID(uint32_t u32Index) +{ + FMC->ISPCMD = FMC_ISPCMD_READ_UID; /* Set ISP Command Code */ + FMC->ISPADDR = (0x04u * u32Index) + 0x10u; /* The UCID is at offset 0x10 with word alignment. */ + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */ +#if ISBEN + __ISB(); +#endif /* To make sure ISP/CPU be Synchronized */ + + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */ + + return FMC->ISPDAT; +} + +/** + * @brief To read bang-gap voltage code + * + * @param[in] None + * + * @return The bang-gap voltage code + * + * @details This function is used to read bang-gap voltage code + * + */ +static __INLINE uint32_t FMC_ReadVBGCode(void) +{ + FMC->ISPCMD = FMC_ISPCMD_READ_UID; /* Set ISP Command Code */ + FMC->ISPADDR = 0x70; /* The VBG is at offset 0x70 with word alignment. */ + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */ +#if ISBEN + __ISB(); +#endif /* To make sure ISP/CPU be Synchronized */ + + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */ + + return FMC->ISPDAT; +} + +/** + * @brief To read the temperature sensor ADC code + * + * @param[in] None + * + * @return The temperature sensor ADC code + * + * @details This function is used to read temperature sensor ADC code + * + */ +static __INLINE uint32_t FMC_ReadVTEMPCode(void) +{ + FMC->ISPCMD = FMC_ISPCMD_READ_UID; /* Set ISP Command Code */ + FMC->ISPADDR = 0x74; /* The VTEMP code is at offset 0x74 with word alignment */ + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */ +#if ISBEN + __ISB(); +#endif /* To make sure ISP/CPU be Synchronized */ + + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */ + + return FMC->ISPDAT; +} + +/** + * @brief To read the calibration value for ADC offset + * + * @param[in] None + * + * @return The calibration value for ADC offset + * + * @details This function is used to read the calibration value for ADC offset + * + */ +static __INLINE uint32_t FMC_ReadADCOffset(void) +{ + FMC->ISPCMD = FMC_ISPCMD_READ_UID; /* Set ISP Command Code */ + FMC->ISPADDR = 0x78; /* The calibration value for ADC offset is at offset 0x78 with word alignment */ + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */ +#if ISBEN + __ISB(); +#endif /* To make sure ISP/CPU be Synchronized */ + + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */ + + return FMC->ISPDAT; +} + +/** + * @brief Set vector mapping address + * + * @param[in] u32PageAddr The page address to remap to address 0x0. The address must be page alignment. + * + * @return To set VECMAP to remap specified page address to 0x0. + * + * @details This function is used to set VECMAP to map specified page to vector page (0x0). + * + * @note + * VECMAP only valid when new IAP function is enabled. (CBS = 10'b or 00'b) + * + */ +static __INLINE void FMC_SetVectorPageAddr(uint32_t u32PageAddr) +{ + FMC->ISPCMD = FMC_ISPCMD_VECMAP; /* Set ISP Command Code */ + FMC->ISPADDR = u32PageAddr; /* The address of specified page which will be map to address 0x0. It must be page alignment. */ + FMC->ISPTRG = 0x1u; /* Trigger to start ISP procedure */ +#if ISBEN + __ISB(); +#endif /* To make sure ISP/CPU be Synchronized */ + + while (FMC->ISPTRG) {} /* Waiting for ISP Done */ +} + +/** + * @brief Get current vector mapping address. + * + * @param None + * + * @return The current vector mapping address. + * + * @details To get VECMAP value which is the page address for remapping to vector page (0x0). + * + * @note + * VECMAP only valid when new IAP function is enabled. (CBS = 10'b or 00'b) + * + */ +static __INLINE uint32_t FMC_GetVECMAP(void) +{ + return (FMC->ISPSTS & FMC_ISPSTS_VECMAP_Msk); +} + +/** + * @brief Get Flash Checksum + * + * @param[in] u32Addr Specific flash start address + * @param[in] i32Size Specific a size of Flash area + * + * @return A checksum value of a flash block. + * + * @details To get VECMAP value which is the page address for remapping to vector page (0x0). + * + */ +static __INLINE uint32_t FMC_GetCheckSum(uint32_t u32Addr, int32_t i32Size) +{ + FMC->ISPCMD = FMC_ISPCMD_CAL_CHECKSUM; + FMC->ISPADDR = u32Addr; + FMC->ISPDAT = (uint32_t)i32Size; + FMC->ISPTRG = 0x1u; +#if ISBEN + __ISB(); +#endif + + while (FMC->ISPTRG) {} + + FMC->ISPCMD = FMC_ISPCMD_CHECKSUM; + FMC->ISPTRG = 0x1u; + + while (FMC->ISPTRG) {} + + return FMC->ISPDAT; +} + +/** + * @brief Program Multi-Word data into specified address of flash + * + * @param[in] u32Addr Flash address include APROM, LDROM, Data Flash, and CONFIG + * @param[in] pu32Buf A data pointer is point to a data buffer start address; + * + * @return None + * + * @details To program multi-words data into Flash include APROM, LDROM, and CONFIG. + * + */ +static __INLINE void FMC_Write128(uint32_t u32Addr, uint32_t pu32Buf[]) +{ + + uint32_t i, idx, u32OnProg; + int32_t err; + + idx = 0u; + FMC->ISPCMD = FMC_ISPCMD_MULTI_PROG; + FMC->ISPADDR = u32Addr; + + do + { + err = 0; + u32OnProg = 1u; + FMC->MPDAT0 = pu32Buf[idx + 0u]; + FMC->MPDAT1 = pu32Buf[idx + 1u]; + FMC->MPDAT2 = pu32Buf[idx + 2u]; + FMC->MPDAT3 = pu32Buf[idx + 3u]; + FMC->ISPTRG = 0x1u; + idx += 4u; + + for (i = idx; i < 128u / 4u; i += 4u) /* Max data length is 128 bytes (128/4 words)*/ + { + __set_PRIMASK(1u); /* Mask interrupt to avoid status check coherence error*/ + + do + { + if ((FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk) == 0u) + { + __set_PRIMASK(0u); + + FMC->ISPADDR = FMC->MPADDR & (~0xful); + idx = (FMC->ISPADDR - u32Addr) / 4u; + err = -1; + } + } + while ((FMC->MPSTS & (3u << FMC_MPSTS_D0_Pos)) && (err == 0)); + + if (err == 0) + { + /* Update new data for D0 */ + FMC->MPDAT0 = pu32Buf[i]; + FMC->MPDAT1 = pu32Buf[i + 1u]; + + do + { + if ((FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk) == 0u) + { + __set_PRIMASK(0u); + FMC->ISPADDR = FMC->MPADDR & (~0xful); + idx = (FMC->ISPADDR - u32Addr) / 4u; + err = -1; + } + } + while ((FMC->MPSTS & (3u << FMC_MPSTS_D2_Pos)) && (err == 0)); + + if (err == 0) + { + /* Update new data for D2*/ + FMC->MPDAT2 = pu32Buf[i + 2u]; + FMC->MPDAT3 = pu32Buf[i + 3u]; + __set_PRIMASK(0u); + } + } + + if (err < 0) + { + break; + } + } + + if (err == 0) + { + u32OnProg = 0u; + + while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) {} + } + } + while (u32OnProg); +} + +void FMC_Open(void); +void FMC_Close(void); +int32_t FMC_ReadConfig(uint32_t u32Config[], uint32_t u32Count); +int32_t FMC_WriteConfig(uint32_t u32Config[], uint32_t u32Count); +void FMC_SetBootSource(int32_t i32BootSrc); +int32_t FMC_GetBootSource(void); +uint32_t FMC_CheckAllOne(uint32_t u32addr, uint32_t u32count); +uint32_t FMC_GetChkSum(uint32_t u32addr, uint32_t u32count); +int32_t FMC_Is_XOM_Actived(uint32_t xom_num); +int32_t FMC_Erase_XOM(uint32_t xom_num); +int32_t FMC_Erase(uint32_t u32Addr); +int32_t FMC_Config_XOM(uint32_t xom_num, uint32_t xom_base, uint8_t xom_page); +uint32_t FMC_Read(uint32_t u32Addr); +void FMC_Write(uint32_t u32Addr, uint32_t u32Data); + + +/*@}*/ /* end of group FMC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group FMC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FMC_H__ */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ + diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_gpio.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_gpio.h new file mode 100644 index 00000000000..1d0fb529dc5 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_gpio.h @@ -0,0 +1,473 @@ +/**************************************************************************//** + * @file crc.h + * @version V0.10 + * @brief M251 series GPIO driver header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __GPIO_H__ +#define __GPIO_H__ + + + + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup GPIO_Driver GPIO Driver + @{ +*/ + +/** @addtogroup GPIO_EXPORTED_CONSTANTS GPIO Exported Constants + @{ +*/ + +#define GPIO_PIN_MAX 16UL /*!< Specify Maximum Pins of Each GPIO Port */ + + +/* Define GPIO Pin Data Input/Output. It could be used to control each I/O pin by pin address mapping. + Example 1: + + PA0 = 1; + + It is used to set GPIO PA.0 to high; + + Example 2: + + if (PA0) + PA0 = 0; + + If GPIO PA.0 pin status is high, then set GPIO PA.0 data output to low. + */ +#define GPIO_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2)))) +#define PA0 GPIO_PIN_DATA(0, 0 ) /*!< Specify PA.0 Pin Data Input/Output */ +#define PA1 GPIO_PIN_DATA(0, 1 ) /*!< Specify PA.1 Pin Data Input/Output */ +#define PA2 GPIO_PIN_DATA(0, 2 ) /*!< Specify PA.2 Pin Data Input/Output */ +#define PA3 GPIO_PIN_DATA(0, 3 ) /*!< Specify PA.3 Pin Data Input/Output */ +#define PA4 GPIO_PIN_DATA(0, 4 ) /*!< Specify PA.4 Pin Data Input/Output */ +#define PA5 GPIO_PIN_DATA(0, 5 ) /*!< Specify PA.5 Pin Data Input/Output */ +#define PA6 GPIO_PIN_DATA(0, 6 ) /*!< Specify PA.6 Pin Data Input/Output */ +#define PA7 GPIO_PIN_DATA(0, 7 ) /*!< Specify PA.7 Pin Data Input/Output */ +#define PA8 GPIO_PIN_DATA(0, 8 ) /*!< Specify PA.8 Pin Data Input/Output */ +#define PA9 GPIO_PIN_DATA(0, 9 ) /*!< Specify PA.9 Pin Data Input/Output */ +#define PA10 GPIO_PIN_DATA(0, 10) /*!< Specify PA.10 Pin Data Input/Output */ +#define PA11 GPIO_PIN_DATA(0, 11) /*!< Specify PA.11 Pin Data Input/Output */ +#define PA12 GPIO_PIN_DATA(0, 12) /*!< Specify PA.12 Pin Data Input/Output */ +#define PA13 GPIO_PIN_DATA(0, 13) /*!< Specify PA.13 Pin Data Input/Output */ +#define PA14 GPIO_PIN_DATA(0, 14) /*!< Specify PA.14 Pin Data Input/Output */ +#define PA15 GPIO_PIN_DATA(0, 15) /*!< Specify PA.15 Pin Data Input/Output */ +#define PB0 GPIO_PIN_DATA(1, 0 ) /*!< Specify PB.0 Pin Data Input/Output */ +#define PB1 GPIO_PIN_DATA(1, 1 ) /*!< Specify PB.1 Pin Data Input/Output */ +#define PB2 GPIO_PIN_DATA(1, 2 ) /*!< Specify PB.2 Pin Data Input/Output */ +#define PB3 GPIO_PIN_DATA(1, 3 ) /*!< Specify PB.3 Pin Data Input/Output */ +#define PB4 GPIO_PIN_DATA(1, 4 ) /*!< Specify PB.4 Pin Data Input/Output */ +#define PB5 GPIO_PIN_DATA(1, 5 ) /*!< Specify PB.5 Pin Data Input/Output */ +#define PB6 GPIO_PIN_DATA(1, 6 ) /*!< Specify PB.6 Pin Data Input/Output */ +#define PB7 GPIO_PIN_DATA(1, 7 ) /*!< Specify PB.7 Pin Data Input/Output */ +#define PB8 GPIO_PIN_DATA(1, 8 ) /*!< Specify PB.8 Pin Data Input/Output */ +#define PB9 GPIO_PIN_DATA(1, 9 ) /*!< Specify PB.9 Pin Data Input/Output */ +#define PB10 GPIO_PIN_DATA(1, 10) /*!< Specify PB.10 Pin Data Input/Output */ +#define PB11 GPIO_PIN_DATA(1, 11) /*!< Specify PB.11 Pin Data Input/Output */ +#define PB12 GPIO_PIN_DATA(1, 12) /*!< Specify PB.12 Pin Data Input/Output */ +#define PB13 GPIO_PIN_DATA(1, 13) /*!< Specify PB.13 Pin Data Input/Output */ +#define PB14 GPIO_PIN_DATA(1, 14) /*!< Specify PB.14 Pin Data Input/Output */ +#define PB15 GPIO_PIN_DATA(1, 15) /*!< Specify PB.15 Pin Data Input/Output */ +#define PC0 GPIO_PIN_DATA(2, 0 ) /*!< Specify PC.0 Pin Data Input/Output */ +#define PC1 GPIO_PIN_DATA(2, 1 ) /*!< Specify PC.1 Pin Data Input/Output */ +#define PC2 GPIO_PIN_DATA(2, 2 ) /*!< Specify PC.2 Pin Data Input/Output */ +#define PC3 GPIO_PIN_DATA(2, 3 ) /*!< Specify PC.3 Pin Data Input/Output */ +#define PC4 GPIO_PIN_DATA(2, 4 ) /*!< Specify PC.4 Pin Data Input/Output */ +#define PC5 GPIO_PIN_DATA(2, 5 ) /*!< Specify PC.5 Pin Data Input/Output */ +#define PC6 GPIO_PIN_DATA(2, 6 ) /*!< Specify PC.6 Pin Data Input/Output */ +#define PC7 GPIO_PIN_DATA(2, 7 ) /*!< Specify PC.7 Pin Data Input/Output */ +#define PC8 GPIO_PIN_DATA(2, 8 ) /*!< Specify PC.8 Pin Data Input/Output */ +#define PC9 GPIO_PIN_DATA(2, 9 ) /*!< Specify PC.9 Pin Data Input/Output */ +#define PC10 GPIO_PIN_DATA(2, 10) /*!< Specify PC.10 Pin Data Input/Output */ +#define PC11 GPIO_PIN_DATA(2, 11) /*!< Specify PC.11 Pin Data Input/Output */ +#define PC12 GPIO_PIN_DATA(2, 12) /*!< Specify PC.12 Pin Data Input/Output */ +#define PC14 GPIO_PIN_DATA(2, 14) /*!< Specify PC.14 Pin Data Input/Output */ +#define PD0 GPIO_PIN_DATA(3, 0 ) /*!< Specify PD.0 Pin Data Input/Output */ +#define PD1 GPIO_PIN_DATA(3, 1 ) /*!< Specify PD.1 Pin Data Input/Output */ +#define PD2 GPIO_PIN_DATA(3, 2 ) /*!< Specify PD.2 Pin Data Input/Output */ +#define PD3 GPIO_PIN_DATA(3, 3 ) /*!< Specify PD.3 Pin Data Input/Output */ +#define PD4 GPIO_PIN_DATA(3, 4 ) /*!< Specify PD.4 Pin Data Input/Output */ +#define PD5 GPIO_PIN_DATA(3, 5 ) /*!< Specify PD.5 Pin Data Input/Output */ +#define PD6 GPIO_PIN_DATA(3, 6 ) /*!< Specify PD.6 Pin Data Input/Output */ +#define PD7 GPIO_PIN_DATA(3, 7 ) /*!< Specify PD.7 Pin Data Input/Output */ +#define PD8 GPIO_PIN_DATA(3, 8 ) /*!< Specify PD.8 Pin Data Input/Output */ +#define PD9 GPIO_PIN_DATA(3, 9 ) /*!< Specify PD.9 Pin Data Input/Output */ +#define PD10 GPIO_PIN_DATA(3, 10) /*!< Specify PD.10 Pin Data Input/Output */ +#define PD11 GPIO_PIN_DATA(3, 11) /*!< Specify PD.11 Pin Data Input/Output */ +#define PD12 GPIO_PIN_DATA(3, 12) /*!< Specify PD.12 Pin Data Input/Output */ +#define PD13 GPIO_PIN_DATA(3, 13) /*!< Specify PD.13 Pin Data Input/Output */ +#define PD15 GPIO_PIN_DATA(3, 15) /*!< Specify PD.15 Pin Data Input/Output */ +#define PE0 GPIO_PIN_DATA(4, 0 ) /*!< Specify PE.0 Pin Data Input/Output */ +#define PE1 GPIO_PIN_DATA(4, 1 ) /*!< Specify PE.1 Pin Data Input/Output */ +#define PE2 GPIO_PIN_DATA(4, 2 ) /*!< Specify PE.2 Pin Data Input/Output */ +#define PE3 GPIO_PIN_DATA(4, 3 ) /*!< Specify PE.3 Pin Data Input/Output */ +#define PE4 GPIO_PIN_DATA(4, 4 ) /*!< Specify PE.4 Pin Data Input/Output */ +#define PE5 GPIO_PIN_DATA(4, 5 ) /*!< Specify PE.5 Pin Data Input/Output */ +#define PE6 GPIO_PIN_DATA(4, 6 ) /*!< Specify PE.6 Pin Data Input/Output */ +#define PE7 GPIO_PIN_DATA(4, 7 ) /*!< Specify PE.7 Pin Data Input/Output */ +#define PE8 GPIO_PIN_DATA(4, 8 ) /*!< Specify PE.8 Pin Data Input/Output */ +#define PE9 GPIO_PIN_DATA(4, 9 ) /*!< Specify PE.9 Pin Data Input/Output */ +#define PE10 GPIO_PIN_DATA(4, 10) /*!< Specify PE.10 Pin Data Input/Output */ +#define PE11 GPIO_PIN_DATA(4, 11) /*!< Specify PE.11 Pin Data Input/Output */ +#define PE12 GPIO_PIN_DATA(4, 12) /*!< Specify PE.12 Pin Data Input/Output */ +#define PE13 GPIO_PIN_DATA(4, 13) /*!< Specify PE.13 Pin Data Input/Output */ +#define PE14 GPIO_PIN_DATA(4, 14) /*!< Specify PE.14 Pin Data Input/Output */ +#define PE15 GPIO_PIN_DATA(4, 15) /*!< Specify PE.15 Pin Data Input/Output */ +#define PF0 GPIO_PIN_DATA(5, 0 ) /*!< Specify PF.0 Pin Data Input/Output */ +#define PF1 GPIO_PIN_DATA(5, 1 ) /*!< Specify PF.1 Pin Data Input/Output */ +#define PF2 GPIO_PIN_DATA(5, 2 ) /*!< Specify PF.2 Pin Data Input/Output */ +#define PF3 GPIO_PIN_DATA(5, 3 ) /*!< Specify PF.3 Pin Data Input/Output */ +#define PF4 GPIO_PIN_DATA(5, 4 ) /*!< Specify PF.4 Pin Data Input/Output */ +#define PF5 GPIO_PIN_DATA(5, 5 ) /*!< Specify PF.5 Pin Data Input/Output */ +#define PF6 GPIO_PIN_DATA(5, 6 ) /*!< Specify PF.6 Pin Data Input/Output */ +#define PF7 GPIO_PIN_DATA(5, 7 ) /*!< Specify PF.7 Pin Data Input/Output */ +#define PF14 GPIO_PIN_DATA(5, 14) /*!< Specify PF.14 Pin Data Input/Output */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* PMD Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_MODE_INPUT 0x0UL /*!< Input Mode */ +#define GPIO_MODE_OUTPUT 0x1UL /*!< Output Mode */ +#define GPIO_MODE_OPEN_DRAIN 0x2UL /*!< Open-Drain Mode */ +#define GPIO_MODE_QUASI 0x3UL /*!< Quasi-bidirectional Mode */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO Interrupt Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_INT_RISING 0x00010000UL /*!< Interrupt enable by Input Rising Edge */ +#define GPIO_INT_FALLING 0x00000001UL /*!< Interrupt enable by Input Falling Edge */ +#define GPIO_INT_BOTH_EDGE 0x00010001UL /*!< Interrupt enable by both Rising Edge and Falling Edge */ +#define GPIO_INT_HIGH 0x01010000UL /*!< Interrupt enable by Level-High */ +#define GPIO_INT_LOW 0x01000001UL /*!< Interrupt enable by Level-Level */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO_INTTYPE Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_INTTYPE_EDGE 0UL /*!< GPIO_INTTYPE Setting for Edge Trigger Mode */ +#define GPIO_INTTYPE_LEVEL 1UL /*!< GPIO_INTTYPE Setting for Edge Level Mode */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO Slew Rate Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_SLEWCTL_NORMAL 0x0UL /*!< GPIO slew setting for nornal Mode */ +#define GPIO_SLEWCTL_HIGH 0x1UL /*!< GPIO slew setting for high Mode */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO Pull-up And Pull-down Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_PUSEL_DISABLE 0x0UL /*!< GPIO PUSEL setting for Disable Mode */ +#define GPIO_PUSEL_PULL_UP 0x1UL /*!< GPIO PUSEL setting for Pull-up Mode */ +#define GPIO_PUSEL_PULL_DOWN 0x2UL /*!< GPIO PUSEL setting for Pull-down Mode */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO_DBCTL Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_DBCTL_ICLK_ON 0x003F0000UL /*!< GPIO_DBCTL setting for all IO pins edge detection circuit is always active after reset */ +#define GPIO_DBCTL_ICLK_OFF 0x00000000UL /*!< GPIO_DBCTL setting for edge detection circuit is active only if IO pin corresponding GPIOx_IEN bit is set to 1 */ + +#define GPIO_DBCTL_DBCLKSRC_LIRC 0x00000010UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the internal 32k Hz */ +#define GPIO_DBCTL_DBCLKSRC_HCLK 0x00000000UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the HCLK */ + +#define GPIO_DBCTL_DBCLKSEL_1 0x00000000UL /*!< GPIO_DBCTL setting for sampling cycle = 1 clocks */ +#define GPIO_DBCTL_DBCLKSEL_2 0x00000001UL /*!< GPIO_DBCTL setting for sampling cycle = 2 clocks */ +#define GPIO_DBCTL_DBCLKSEL_4 0x00000002UL /*!< GPIO_DBCTL setting for sampling cycle = 4 clocks */ +#define GPIO_DBCTL_DBCLKSEL_8 0x00000003UL /*!< GPIO_DBCTL setting for sampling cycle = 8 clocks */ +#define GPIO_DBCTL_DBCLKSEL_16 0x00000004UL /*!< GPIO_DBCTL setting for sampling cycle = 16 clocks */ +#define GPIO_DBCTL_DBCLKSEL_32 0x00000005UL /*!< GPIO_DBCTL setting for sampling cycle = 32 clocks */ +#define GPIO_DBCTL_DBCLKSEL_64 0x00000006UL /*!< GPIO_DBCTL setting for sampling cycle = 64 clocks */ +#define GPIO_DBCTL_DBCLKSEL_128 0x00000007UL /*!< GPIO_DBCTL setting for sampling cycle = 128 clocks */ +#define GPIO_DBCTL_DBCLKSEL_256 0x00000008UL /*!< GPIO_DBCTL setting for sampling cycle = 256 clocks */ +#define GPIO_DBCTL_DBCLKSEL_512 0x00000009UL /*!< GPIO_DBCTL setting for sampling cycle = 512 clocks */ +#define GPIO_DBCTL_DBCLKSEL_1024 0x0000000AUL /*!< GPIO_DBCTL setting for sampling cycle = 1024 clocks */ +#define GPIO_DBCTL_DBCLKSEL_2048 0x0000000BUL /*!< GPIO_DBCTL setting for sampling cycle = 2048 clocks */ +#define GPIO_DBCTL_DBCLKSEL_4096 0x0000000CUL /*!< GPIO_DBCTL setting for sampling cycle = 4096 clocks */ +#define GPIO_DBCTL_DBCLKSEL_8192 0x0000000DUL /*!< GPIO_DBCTL setting for sampling cycle = 8192 clocks */ +#define GPIO_DBCTL_DBCLKSEL_16384 0x0000000EUL /*!< GPIO_DBCTL setting for sampling cycle = 16384 clocks */ +#define GPIO_DBCTL_DBCLKSEL_32768 0x0000000FUL /*!< GPIO_DBCTL setting for sampling cycle = 32768 clocks */ + + +/** + * @brief Clear GPIO Pin Interrupt Flag + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, and PE. + * It could be BIT0 ~ BIT12, and BIT14 ~ BIT15 for PC. + * It could be BIT0 ~ BIT13, and BIT15 for PD. + * It could be BIT0 ~ BIT7 for PF. + * + * @return None + * + * @details Clear the interrupt status of specified GPIO pin. + */ +#define GPIO_CLR_INT_FLAG(port, u32PinMask) ((port)->INTSRC = (u32PinMask)) + +/** + * @brief Disable Pin De-bounce Function + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, and PE. + * It could be BIT0 ~ BIT12, and BIT14 ~ BIT15 for PC. + * It could be BIT0 ~ BIT13, and BIT15 for PD. + * It could be BIT0 ~ BIT7 for PF. + * + * @return None + * + * @details Disable the interrupt de-bounce function of specified GPIO pin. + */ +#define GPIO_DISABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN &= ~(u32PinMask)) + +/** + * @brief Enable Pin De-bounce Function + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, and PE. + * It could be BIT0 ~ BIT12, and BIT14 ~ BIT15 for PC. + * It could be BIT0 ~ BIT13, and BIT15 for PD. + * It could be BIT0 ~ BIT7 for PF. + * + * @return None + * + * @details Enable the interrupt de-bounce function of specified GPIO pin. + */ +#define GPIO_ENABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN |= (u32PinMask)) + +/** + * @brief Disable I/O Digital Input Path + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, and PE. + * It could be BIT0 ~ BIT12, and BIT14 ~ BIT15 for PC. + * It could be BIT0 ~ BIT13, and BIT15 for PD. + * It could be BIT0 ~ BIT7 for PF. + * + * @return None + * + * @details Disable I/O digital input path of specified GPIO pin. + */ +#define GPIO_DISABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF |= ((u32PinMask)<<16)) + +/** + * @brief Enable I/O Digital Input Path + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, and PE. + * It could be BIT0 ~ BIT12, and BIT14 ~ BIT15 for PC. + * It could be BIT0 ~ BIT13, and BIT15 for PD. + * It could be BIT0 ~ BIT7 for PF. + * + * @return None + * + * @details Enable I/O digital input path of specified GPIO pin. + */ +#define GPIO_ENABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF &= ~((u32PinMask)<<16)) + +/** + * @brief Disable I/O DOUT mask + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, and PE. + * It could be BIT0 ~ BIT12, and BIT14 ~ BIT15 for PC. + * It could be BIT0 ~ BIT13, and BIT15 for PD. + * It could be BIT0 ~ BIT7 for PF. + * + * @return None + * + * @details Disable I/O DOUT mask of specified GPIO pin. + */ +#define GPIO_DISABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK &= ~(u32PinMask)) + +/** + * @brief Enable I/O DOUT mask + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, and PE. + * It could be BIT0 ~ BIT12, and BIT14 ~ BIT15 for PC. + * It could be BIT0 ~ BIT13, and BIT15 for PD. + * It could be BIT0 ~ BIT7 for PF. + * + * @return None + * + * @details Enable I/O DOUT mask of specified GPIO pin. + */ +#define GPIO_ENABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK |= (u32PinMask)) + +/** + * @brief Get GPIO Pin Interrupt Flag + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, and PE. + * It could be BIT0 ~ BIT12, and BIT14 ~ BIT15 for PC. + * It could be BIT0 ~ BIT13, and BIT15 for PD. + * It could be BIT0 ~ BIT7 for PF. + * + * @retval 0 No interrupt at specified GPIO pin + * @retval 1 The specified GPIO pin generate an interrupt + * + * @details Get the interrupt status of specified GPIO pin. + */ +#define GPIO_GET_INT_FLAG(port, u32PinMask) ((port)->INTSRC & (u32PinMask)) + +/** + * @brief Set De-bounce Sampling Cycle Time + * + * @param[in] u32ClkSrc The de-bounce counter clock source. It could be GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC. + * @param[in] u32ClkSel The de-bounce sampling cycle selection. It could be + * - \ref GPIO_DBCTL_DBCLKSEL_1 + * - \ref GPIO_DBCTL_DBCLKSEL_2 + * - \ref GPIO_DBCTL_DBCLKSEL_4 + * - \ref GPIO_DBCTL_DBCLKSEL_8 + * - \ref GPIO_DBCTL_DBCLKSEL_16 + * - \ref GPIO_DBCTL_DBCLKSEL_32 + * - \ref GPIO_DBCTL_DBCLKSEL_64 + * - \ref GPIO_DBCTL_DBCLKSEL_128 + * - \ref GPIO_DBCTL_DBCLKSEL_256 + * - \ref GPIO_DBCTL_DBCLKSEL_512 + * - \ref GPIO_DBCTL_DBCLKSEL_1024 + * - \ref GPIO_DBCTL_DBCLKSEL_2048 + * - \ref GPIO_DBCTL_DBCLKSEL_4096 + * - \ref GPIO_DBCTL_DBCLKSEL_8192 + * - \ref GPIO_DBCTL_DBCLKSEL_16384 + * - \ref GPIO_DBCTL_DBCLKSEL_32768 + * + * @return None + * + * @details Set the interrupt de-bounce sampling cycle time based on the debounce counter clock source. \n + * Example: GPIO_SET_DEBOUNCE_TIME(GPIO_DBCTL_DBCLKSRC_LIRC, GPIO_DBCTL_DBCLKSEL_4). \n + * It's meaning the debounce counter clock source is internal 38.4 KHz and sampling cycle selection is 4. \n + * Then the target de-bounce sampling cycle time is (4)*(1/(38.4*1000)) s = 1.04*0.0001 s = 104 us, + * and system will sampling interrupt input once per 104 us. + * Note: all GPIO ports use the same debounce source clock and de-bounce sampling cycle, but each port can close + * its clock source for power saving by setting ICLKONx bit to 0. + */ +#define GPIO_SET_DEBOUNCE_TIME(u32ClkSrc, u32ClkSel) (GPIO->DBCTL = ((GPIO_DBCTL_ICLK_ON) | (u32ClkSrc) | (u32ClkSel) )) + +/** + * @brief Set GPIO Interrupt Clock on bit + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. + * + * @return None + * + * @details Set the I/O pins edge detection circuit always active after reset for specified port. + */ +#define GPIO_SET_DEBOUNCE_ICLKON(port) (GPIO->DBCTL |= ((0x1UL << ((((uint32_t)port - (uint32_t)GPIO_BASE) / 0x40) + 16)))) + +/** + * @brief Clear GPIO Interrupt Clock on bit + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. + * + * @return None + * + * @details Set edge detection circuit active only if I/O pin edge interrupt enabled for specified port + */ +#define GPIO_CLR_DEBOUNCE_ICLKON(port) (GPIO->DBCTL &= ~((0x1UL << ((((uint32_t)port - (uint32_t)GPIO_BASE) / 0x40) + 16)))) + +/** + * @brief Get GPIO Port IN Data + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. + * + * @return The specified port data + * + * @details Get the PIN register of specified GPIO port. + */ +#define GPIO_GET_IN_DATA(port) ((port)->PIN) + +/** + * @brief Set GPIO Port OUT Data + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. + * @param[in] u32Data GPIO port data. + * + * @return None + * + * @details Set the Data into specified GPIO port. + */ +#define GPIO_SET_OUT_DATA(port, u32Data) ((port)->DOUT = (u32Data)) + +/** + * @brief Toggle Specified GPIO pin + * + * @param[in] u32Pin Pxy + * + * @return None + * + * @details Toggle the specified GPIO pint. + */ +#define GPIO_TOGGLE(u32Pin) ((u32Pin) ^= 1) + + +/** +* @brief Enable External GPIO interrupt +* +* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. +* @param[in] u32Pin The pin of specified GPIO port. +* It could be BIT0 ~ BIT15 for PA, PB, and PE. +* It could be BIT0 ~ BIT12, and BIT14 ~ BIT15 for PC. +* It could be BIT0 ~ BIT13, and BIT15 for PD. +* It could be BIT0 ~ BIT7 for PF. +* +* @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n +* GPIO_INT_RISING, GPIO_INT_FALLING, GPIO_INT_BOTH_EDGE, GPIO_INT_HIGH, GPIO_INT_LOW. +* +* @return None +* +* @details This function is used to enable specified GPIO pin interrupt. +*/ +#define GPIO_EnableEINT GPIO_EnableInt + +/** +* @brief Disable External GPIO interrupt +* +* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. +* @param[in] u32Pin The pin of specified GPIO port. +* It could be BIT0 ~ BIT15 for PA, PB, and PE. +* It could be BIT0 ~ BIT12, and BIT14 ~ BIT15 for PC. +* It could be BIT0 ~ BIT13, and BIT15 for PD. +* It could be BIT0 ~ BIT7 for PF. +* +* @return None +* +* @details This function is used to enable specified GPIO pin interrupt. +*/ +#define GPIO_DisableEINT GPIO_DisableInt + + +void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode); +void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs); +void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin); +void GPIO_SetSlewCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode); +void GPIO_SetPullCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode); +/*@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group GPIO_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __GPIO_H__ */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_i2c.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_i2c.h new file mode 100644 index 00000000000..db05e875309 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_i2c.h @@ -0,0 +1,488 @@ +/**************************************************************************//** + * @file I2C.h + * @version V0.10 + * @brief M251 Series I2C Driver Header File + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __I2C_H__ +#define __I2C_H__ + + + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup I2C_Driver I2C Driver + @{ +*/ + +/** @addtogroup I2C_EXPORTED_CONSTANTS I2C Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* I2C_CTL constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define I2C_CTL_STA_SI 0x28UL /*!< I2C_CTL setting for I2C control bits. It would set STA and SI bits */ +#define I2C_CTL_STA_SI_AA 0x2CUL /*!< I2C_CTL setting for I2C control bits. It would set STA, SI and AA bits */ +#define I2C_CTL_STO_SI 0x18UL /*!< I2C_CTL setting for I2C control bits. It would set STO and SI bits */ +#define I2C_CTL_STO_SI_AA 0x1CUL /*!< I2C_CTL setting for I2C control bits. It would set STO, SI and AA bits */ +#define I2C_CTL_SI 0x08UL /*!< I2C_CTL setting for I2C control bits. It would set SI bit */ +#define I2C_CTL_SI_AA 0x0CUL /*!< I2C_CTL setting for I2C control bits. It would set SI and AA bits */ +#define I2C_CTL_STA 0x20UL /*!< I2C_CTL setting for I2C control bits. It would set STA bit */ +#define I2C_CTL_STO 0x10UL /*!< I2C_CTL setting for I2C control bits. It would set STO bit */ +#define I2C_CTL_AA 0x04UL /*!< I2C_CTL setting for I2C control bits. It would set AA bit */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* I2C GCMode constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define I2C_GCMODE_ENABLE 1 /*!< Enable I2C GC Mode */ +#define I2C_GCMODE_DISABLE 0 /*!< Disable I2C GC Mode */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* I2C SMBUS constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define I2C_SMBH_ENABLE 1 /*!< Enable SMBus Host Mode enable */ +#define I2C_SMBD_ENABLE 0 /*!< Enable SMBus Device Mode enable */ +#define I2C_PECTX_ENABLE 1 /*!< Enable SMBus Packet Error Check Transmit function */ +#define I2C_PECTX_DISABLE 0 /*!< Disable SMBus Packet Error Check Transmit function */ + +/*@}*/ /* end of group I2C_EXPORTED_CONSTANTS */ + +/** @addtogroup I2C_EXPORTED_FUNCTIONS I2C Exported Functions + @{ +*/ +/** + * @brief The macro is used to set I2C bus condition at One Time + * + * @param[in] i2c Specify I2C port + * @param[in] u8Ctrl A byte writes to I2C control register + * + * @return None + * + * @details Set I2C_CTL register to control I2C bus conditions of START, STOP, SI, ACK. + */ +#define I2C_SET_CONTROL_REG(i2c, u8Ctrl) ((i2c)->CTL0 = ((i2c)->CTL0 & ~0x3c) | (u8Ctrl)) + +/** + * @brief The macro is used to set START condition of I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Set the I2C bus START condition in I2C_CTL register. + */ +#define I2C_START(i2c) ((i2c)->CTL0 = ((i2c)->CTL0 & ~I2C_CTL0_SI_Msk) | I2C_CTL0_STA_Msk) + +/** + * @brief The macro is used to wait I2C bus status get ready + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details When a new status is presented of I2C bus, the SI flag will be set in I2C_CTL register. + */ +#define I2C_WAIT_READY(i2c) while(!((i2c)->CTL0 & I2C_CTL0_SI_Msk)) + +/** + * @brief The macro is used to Read I2C Bus Data Register + * + * @param[in] i2c Specify I2C port + * + * @return A byte of I2C data register + * + * @details I2C controller read data from bus and save it in I2CDAT register. + */ +#define I2C_GET_DATA(i2c) ((i2c)->DAT) + +/** + * @brief Write a Data to I2C Data Register + * + * @param[in] i2c Specify I2C port + * @param[in] u8Data A byte that writes to data register + * + * @return None + * + * @details When write a data to I2C_DAT register, the I2C controller will shift it to I2C bus. + */ +#define I2C_SET_DATA(i2c, u8Data) ((i2c)->DAT = (u8Data)) + +/** + * @brief Get I2C Bus status code + * + * @param[in] i2c Specify I2C port + * + * @return I2C status code + * + * @details To get this status code to monitor I2C bus event. + */ +#define I2C_GET_STATUS(i2c) ((i2c)->STATUS0) + +/** + * @brief Get Time-out flag from I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @retval 0 I2C Bus time-out is not happened + * @retval 1 I2C Bus time-out is happened + * + * @details When I2C bus occurs time-out event, the time-out flag will be set. + */ +#define I2C_GET_TIMEOUT_FLAG(i2c) ( ((i2c)->TOCTL & I2C_TOCTL_TOIF_Msk) == I2C_TOCTL_TOIF_Msk ? 1:0 ) + +/** + * @brief To get wake-up flag from I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @retval 0 Chip is not woken-up from power-down mode + * @retval 1 Chip is woken-up from power-down mode + * + * @details I2C bus occurs wake-up event, wake-up flag will be set. + */ +#define I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WKIF_Msk) == I2C_WKSTS_WKIF_Msk ? 1:0 ) + +/** + * @brief To clear wake-up flag + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details If wake-up flag is set, use this macro to clear it. + */ +#define I2C_CLEAR_WAKEUP_FLAG(i2c) ((i2c)->WKSTS = I2C_WKSTS_WKIF_Msk) + +/** + * @brief To get SMBus Status + * + * @param[in] i2c Specify I2C port + * + * @return SMBus status + * + * @details To get the Bus Management status of I2C_BUSSTS register + * + */ +#define I2C_SMBUS_GET_STATUS(i2c) ((i2c)->BUSSTS) + +/** + * @brief Get SMBus CRC value + * + * @param[in] i2c Specify I2C port + * + * @return Packet error check byte value + * + * @details The CRC check value after a transmission or a reception by count by using CRC8 + * + */ +#define I2C_SMBUS_GET_PEC_VALUE(i2c) ((i2c)->PKTCRC) + +/** + * @brief Set SMBus Bytes number of Transmission or reception + * + * @param[in] i2c Specify I2C port + * @param[in] u32PktSize Transmit / Receive bytes + * + * @return None + * + * @details The transmission or receive byte number in one transaction when PECEN is set. The maximum is 255 bytes. + * + */ +#define I2C_SMBUS_SET_PACKET_BYTE_COUNT(i2c, u32PktSize) ((i2c)->PKTSIZE = (u32PktSize)) + +/** + * @brief Enable SMBus Alert function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin will pull lo, and reply ACK when get ARP from host + * Host Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin is supported to receive alert state(Lo trigger) + * + */ +#define I2C_SMBUS_ENABLE_ALERT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ALERTEN_Msk) + +/** + * @brief Disable SMBus Alert pin function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin will pull hi, and reply NACK when get ARP from host + * Host Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin is not supported to receive alert state(Lo trigger) + * + */ +#define I2C_SMBUS_DISABLE_ALERT(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ALERTEN_Msk) + +/** + * @brief Set SMBus SUSCON pin is output mode + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output mode. + * + * + */ +#define I2C_SMBUS_SET_SUSCON_OUT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOEN_Msk) + +/** + * @brief Set SMBus SUSCON pin is input mode + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is input mode. + * + * + */ +#define I2C_SMBUS_SET_SUSCON_IN(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOEN_Msk) + +/** + * @brief Set SMBus SUSCON pin output high state + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output hi state. + * + */ +#define I2C_SMBUS_SET_SUSCON_HIGH(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOSTS_Msk) + + +/** + * @brief Set SMBus SUSCON pin output low state + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output lo state. + * + */ +#define I2C_SMBUS_SET_SUSCON_LOW(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOSTS_Msk) + +/** + * @brief Enable SMBus Acknowledge control by manual + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details The 9th bit can response the ACK or NACK according the received data by user. When the byte is received, SCLK line stretching to low between the 8th and 9th SCLK pulse. + * + */ +#define I2C_SMBUS_ACK_MANUAL(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ACKMEN_Msk) + +/** + * @brief Disable SMBus Acknowledge control by manual + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Disable acknowledge response control by user. + * + */ +#define I2C_SMBUS_ACK_AUTO(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKMEN_Msk) + +/** + * @brief Enable SMBus Acknowledge manual interrupt + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function is used to enable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1 + * + */ +#define I2C_SMBUS_9THBIT_INT_ENABLE(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ACKM9SI_Msk) + +/** + * @brief Disable SMBus Acknowledge manual interrupt + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function is used to disable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1 + * + */ +#define I2C_SMBUS_9THBIT_INT_DISABLE(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKM9SI_Msk) + +/** + * @brief Enable SMBus PEC clear at REPEAT START + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function is used to enable the condition of REAEAT START can clear the PEC calculation. + * + */ +#define I2C_SMBUS_RST_PEC_AT_START_ENABLE(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_PECCLR_Msk) + +/** + * @brief Disable SMBus PEC clear at Repeat START + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function is used to disable the condition of Repeat START can clear the PEC calculation. + * + */ +#define I2C_SMBUS_RST_PEC_AT_START_DISABLE(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_PECCLR_Msk) +/** + * @brief Enable RX PDMA function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Set RXPDMAEN bit of I2C_CTL1 register to enable RX PDMA transfer function. + * \hideinitializer + */ +#define I2C_ENABLE_RX_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_RXPDMAEN_Msk) + +/** + * @brief Enable TX PDMA function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Set TXPDMAEN bit of I2C_CTL1 register to enable TX PDMA transfer function. + * \hideinitializer + */ +#define I2C_ENABLE_TX_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_TXPDMAEN_Msk) + +/** + * @brief Disable RX PDMA transfer. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Clear RXPDMAEN bit of I2C_CTL1 register to disable RX PDMA transfer function. + * \hideinitializer + */ +#define I2C_DISABLE_RX_PDMA(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_RXPDMAEN_Msk) + +/** + * @brief Disable TX PDMA transfer. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Clear TXPDMAEN bit of I2C_CTL1 register to disable TX PDMA transfer function. + * \hideinitializer + */ +#define I2C_DISABLE_TX_PDMA(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_TXPDMAEN_Msk) + +/** + * @brief Enable PDMA stretch function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Enable this function is to stretch bus by hardware after PDMA transfer is done if SI is not cleared. + * \hideinitializer + */ +#define I2C_ENABLE_PDMA_STRETCH(i2c) ((i2c)->CTL1 |= I2C_CTL1_PDMASTR_Msk) + +/** + * @brief Disable PDMA stretch function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details I2C will send STOP after PDMA transfers done automatically. + * \hideinitializer + */ +#define I2C_DISABLE_PDMA_STRETCH(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_PDMASTR_Msk) + +/** + * @brief Reset PDMA function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details I2C PDMA engine will be reset after this function is called. + * \hideinitializer + */ +#define I2C_DISABLE_RST_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_PDMARST_Msk) +/*---------------------------------------------------------------------------------------------------------*/ +/* inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void I2C_STOP(I2C_T *i2c); + +/** + * @brief The macro is used to set STOP condition of I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Set the I2C bus STOP condition in I2C_CTL register. + */ +__STATIC_INLINE void I2C_STOP(I2C_T *i2c) +{ + + (i2c)->CTL0 |= (I2C_CTL0_SI_Msk | I2C_CTL0_STO_Msk); + + while (i2c->CTL0 & I2C_CTL0_STO_Msk) + { + } +} + +void I2C_ClearTimeoutFlag(I2C_T *i2c); +void I2C_Close(I2C_T *i2c); +void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack); +void I2C_DisableInt(I2C_T *i2c); +void I2C_EnableInt(I2C_T *i2c); +uint32_t I2C_GetBusClockFreq(I2C_T *i2c); +uint32_t I2C_GetIntFlag(I2C_T *i2c); +uint32_t I2C_GetStatus(I2C_T *i2c); +uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock); +uint8_t I2C_GetData(I2C_T *i2c); +void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddr, uint8_t u8GCMode); +void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddrMask); +uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock); +void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout); +void I2C_DisableTimeout(I2C_T *i2c); +void I2C_EnableWakeup(I2C_T *i2c); +void I2C_DisableWakeup(I2C_T *i2c); +void I2C_SetData(I2C_T *i2c, uint8_t u8Data); +uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data); +uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data[], uint32_t u32wLen); +uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data); +uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data[], uint32_t u32wLen); +uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data); +uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data[], uint32_t u32wLen); +uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr); +uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t rdata[], uint32_t u32rLen); +uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr); +uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t rdata[], uint32_t u32rLen); +uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr); +uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t rdata[], uint32_t u32rLen); + +uint32_t I2C_SMBusGetStatus(I2C_T *i2c); +void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8ClrSMBusIntFlag); +void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize); +void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice); +void I2C_SMBusClose(I2C_T *i2c); +void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn); +uint8_t I2C_SMBusGetPECValue(I2C_T *i2c); +void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t us, uint32_t u32Hclk); +void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk); +void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk); +/*@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group I2C_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif +#endif /* __I2C_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_opa.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_opa.h new file mode 100644 index 00000000000..e79574efe32 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_opa.h @@ -0,0 +1,201 @@ +/**************************************************************************//** + * @file opa.h + * @version V1.00 + * @brief M251 series OPA driver header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __OPA_H__ +#define __OPA_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup OPA_Driver OPA Driver + @{ +*/ + +/** @addtogroup OPA_EXPORTED_CONSTANTS OPA Exported Constants + @{ +*/ +#define OPA_CALIBRATION_CLK_1K (0UL) /*!< OPA calibration clock select 1 KHz \hideinitializer */ +#define OPA_CALIBRATION_RV_1_2_AVDD (0UL) /*!< OPA calibration reference voltage select 1/2 AVDD \hideinitializer */ +#define OPA_CALIBRATION_RV_H_L_VCM (1UL) /*!< OPA calibration reference voltage select from high vcm to low vcm \hideinitializer */ + +/*@}*/ /* end of group OPA_EXPORTED_CONSTANTS */ + +/** @addtogroup OPA_EXPORTED_FUNCTIONS OPA Exported Functions + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define OPA functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ + +__STATIC_INLINE int32_t OPA_Calibration(OPA_T *opa, uint32_t u32OpaNum, uint32_t u32ClockSel, uint32_t u32RefVol); + +/** + * @brief This macro is used to power on the OPA circuit + * @param[in] opa The pointer of the specified OPA module + * @param[in] u32OpaNum The OPA number. 0 for OPA0. + * @return None + * @details This macro will set OPENx (x=0) bit of OPA_CTL register to power on the OPA circuit. + * \hideinitializer + */ +#define OPA_POWER_ON(opa, u32OpaNum) ((opa)->CTL |= (1UL<<(OPA_CTL_OPEN0_Pos+(u32OpaNum)))) + +/** + * @brief This macro is used to power down the OPA circuit + * @param[in] opa The pointer of the specified OPA module + * @param[in] u32OpaNum The OPA number. 0 for OPA0. + * @return None + * @details This macro will clear OPENx (x=0) bit of OPA_CTL register to power down the OPA circuit. + * \hideinitializer + */ +#define OPA_POWER_DOWN(opa, u32OpaNum) ((opa)->CTL &= ~(1UL<<(OPA_CTL_OPEN0_Pos+(u32OpaNum)))) + +/** + * @brief This macro is used to enable the OPA Schmitt trigger buffer + * @param[in] opa The pointer of the specified OPA module + * @param[in] u32OpaNum The OPA number. 0 for OPA0. + * @return None + * @details This macro will set OPDOENx (x=0) bit of OPA_CTL register to enable the OPA Schmitt trigger buffer. + * \hideinitializer + */ +#define OPA_ENABLE_SCH_TRIGGER(opa, u32OpaNum) ((opa)->CTL |= (1UL<<(OPA_CTL_OPDOEN0_Pos+(u32OpaNum)))) + +/** + * @brief This macro is used to disable the OPA Schmitt trigger buffer + * @param[in] opa The pointer of the specified OPA module + * @param[in] u32OpaNum The OPA number. 0 for OPA0. + * @return None + * @details This macro will clear OPDOENx (x=0) bit of OPA_CTL register to disable the OPA Schmitt trigger buffer. + * \hideinitializer + */ +#define OPA_DISABLE_SCH_TRIGGER(opa, u32OpaNum) ((opa)->CTL &= ~(1UL<<(OPA_CTL_OPDOEN0_Pos+(u32OpaNum)))) + +/** + * @brief This macro is used to enable OPA Schmitt trigger digital output interrupt + * @param[in] opa The pointer of the specified OPA module + * @param[in] u32OpaNum The OPA number. 0 for OPA0. + * @return None + * @details This macro will set OPDOIENx (x=0) bit of OPA_CTL register to enable the OPA Schmitt trigger digital output interrupt. + * \hideinitializer + */ +#define OPA_ENABLE_INT(opa, u32OpaNum) ((opa)->CTL |= (1UL<<(OPA_CTL_OPDOIEN0_Pos+(u32OpaNum)))) + +/** + * @brief This macro is used to disable OPA Schmitt trigger digital output interrupt + * @param[in] opa The pointer of the specified OPA module + * @param[in] u32OpaNum The OPA number. 0 for OPA0. + * @return None + * @details This macro will clear OPDOIENx (x=0) bit of OPA_CTL register to disable the OPA Schmitt trigger digital output interrupt. + * \hideinitializer + */ +#define OPA_DISABLE_INT(opa, u32OpaNum) ((opa)->CTL &= ~(1UL<<(OPA_CTL_OPDOIEN0_Pos+(u32OpaNum)))) + +/** + * @brief This macro is used to get OPA digital output state + * @param[in] opa The pointer of the specified OPA module + * @param[in] u32OpaNum The OPA number. 0 for OPA0. + * @return OPA digital output state + * @details This macro will return the OPA digital output value. + * \hideinitializer + */ +#define OPA_GET_DIGITAL_OUTPUT(opa, u32OpaNum) (((opa)->STATUS & (OPA_STATUS_OPDO0_Msk<<(u32OpaNum)))?1UL:0UL) + +/** + * @brief This macro is used to get OPA interrupt flag + * @param[in] opa The pointer of the specified OPA module + * @param[in] u32OpaNum The OPA number. 0 for OPA0. + * @retval 0 OPA interrupt does not occur. + * @retval 1 OPA interrupt occurs. + * @details This macro will return the OPA interrupt flag. + * \hideinitializer + */ +#define OPA_GET_INT_FLAG(opa, u32OpaNum) (((opa)->STATUS & (OPA_STATUS_OPDOIF0_Msk<<(u32OpaNum)))?1UL:0UL) + +/** + * @brief This macro is used to clear OPA interrupt flag + * @param[in] opa The pointer of the specified OPA module + * @param[in] u32OpaNum The OPA number. 0 for OPA0. + * @return None + * @details This macro will write 1 to OPDOIFx (x=0) bit of OPA_STATUS register to clear interrupt flag. + * \hideinitializer + */ +#define OPA_CLR_INT_FLAG(opa, u32OpaNum) ((opa)->STATUS = (OPA_STATUS_OPDOIF0_Msk<<(u32OpaNum))) + + +/** + * @brief This function is used to configure and start OPA calibration + * @param[in] opa The pointer of the specified OPA module + * @param[in] u32OpaNum The OPA number. 0 for OPA0. + * @param[in] u32ClockSel Select OPA calibration clock + * - \ref OPA_CALIBRATION_CLK_1K + * @param[in] u32RefVol Select OPA reference voltage + * - \ref OPA_CALIBRATION_RV_1_2_AVDD + * - \ref OPA_CALIBRATION_RV_H_L_VCM + * @retval 0 PMOS and NMOS calibration successfully. + * @retval -1 only PMOS calibration failed. + * @retval -2 only NMOS calibration failed. + * @retval -3 PMOS and NMOS calibration failed. + */ +__STATIC_INLINE int32_t OPA_Calibration(OPA_T *opa, uint32_t u32OpaNum, uint32_t u32ClockSel, uint32_t u32RefVol) +{ + uint32_t u32CALResult; + int32_t i32Ret = 0L; + + (opa)->CALCTL = (((opa)->CALCTL) & ~(0x30ul << (u32OpaNum << 1))) | (((u32ClockSel) << 4) << (u32OpaNum << 1)); + (opa)->CALCTL = (((opa)->CALCTL) & ~(OPA_CALCTL_CALRVS0_Msk << (u32OpaNum))) | (((u32RefVol) << OPA_CALCTL_CALRVS0_Pos) << (u32OpaNum)); + (opa)->CALCTL |= (OPA_CALCTL_CALTRG0_Msk << (u32OpaNum)); + + while ((opa)->CALCTL & (OPA_CALCTL_CALTRG0_Msk << (u32OpaNum))) {} + + u32CALResult = ((opa)->CALST >> ((u32OpaNum) * 4U)) & (OPA_CALST_CALNS0_Msk | OPA_CALST_CALPS0_Msk); + + if (u32CALResult == 0ul) + { + i32Ret = 0L; + } + else if (u32CALResult == OPA_CALST_CALNS0_Msk) + { + i32Ret = -2L; + } + else if (u32CALResult == OPA_CALST_CALPS0_Msk) + { + i32Ret = -1L; + } + else if (u32CALResult == (uint32_t)(OPA_CALST_CALNS0_Msk | OPA_CALST_CALPS0_Msk)) + { + i32Ret = -3L; + } + else + { + + } + + return i32Ret; +} + + + +/*@}*/ /* end of group OPA_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group OPA_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __OPA_H__ */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_pdma.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_pdma.h new file mode 100644 index 00000000000..4db0fbb3521 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_pdma.h @@ -0,0 +1,353 @@ +/**************************************************************************//** + * @file pdma.h + * @version V3.00 + * @brief M251 series PDMA driver header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __PDMA_H__ +#define __PDMA_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup PDMA_Driver PDMA Driver + @{ +*/ + +/** @addtogroup PDMA_EXPORTED_CONSTANTS PDMA Exported Constants + @{ +*/ +#define PDMA_CH_MAX 8UL /*!< Specify Maximum Channels of PDMA \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Operation Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define PDMA_OP_STOP 0x00000000UL /*!INTSTS)) + +/** + * @brief Get Transfer Done Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @return None + * + * @details Get the transfer done Interrupt status. + * \hideinitializer + */ +#define PDMA_GET_TD_STS(pdma) ((uint32_t)(pdma->TDSTS)) + +/** + * @brief Clear Transfer Done Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Mask The channel mask + * + * @return None + * + * @details Clear the transfer done Interrupt status. + * \hideinitializer + */ +#define PDMA_CLR_TD_FLAG(pdma, u32Mask) ((uint32_t)(pdma->TDSTS = (u32Mask))) + +/** + * @brief Get Target Abort Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @return None + * + * @details Get the target abort Interrupt status. + * \hideinitializer + */ +#define PDMA_GET_ABORT_STS(pdma) ((uint32_t)(pdma->ABTSTS)) + +/** + * @brief Clear Target Abort Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Mask The channel mask + * + * @return None + * + * @details Clear the target abort Interrupt status. + * \hideinitializer + */ +#define PDMA_CLR_ABORT_FLAG(pdma, u32Mask) ((uint32_t)(pdma->ABTSTS = (u32Mask))) + +/** + * @brief Get Alignment Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @return None + * + * @details Get Alignment Interrupt status. + * \hideinitializer + */ +#define PDMA_GET_ALIGN_STS(pdma) ((uint32_t)(PDMA->ALIGN)) + +/** + * @brief Clear Alignment Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Mask The channel mask + * + * @return None + * + * @details Clear the Alignment Interrupt status. + * \hideinitializer + */ +#define PDMA_CLR_ALIGN_FLAG(pdma,u32Mask) ((uint32_t)(pdma->ALIGN = (u32Mask))) + +/** + * @brief Clear Timeout Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details Clear the selected channel timeout interrupt status. + * \hideinitializer + */ +#define PDMA_CLR_TMOUT_FLAG(pdma, u32Ch) ((uint32_t)(pdma->INTSTS = (1 << ((u32Ch) + 8)))) + +/** + * @brief Check Channel Status + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * + * @retval 0 Idle state + * @retval 1 Busy state + * + * @details Check the selected channel is busy or not. + * \hideinitializer + */ +#define PDMA_IS_CH_BUSY(pdma, u32Ch) ((uint32_t)(pdma->TRGSTS & (1 << (u32Ch)))? 1 : 0) + +/** + * @brief Set Source Address + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Addr The selected address + * + * @return None + * + * @details This macro set the selected channel source address. + * \hideinitializer + */ +#define PDMA_SET_SRC_ADDR(pdma, u32Ch, u32Addr) ((uint32_t)(pdma->DSCT[(u32Ch)].SA = (u32Addr))) + +/** + * @brief Set Destination Address + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Addr The selected address + * + * @return None + * + * @details This macro set the selected channel destination address. + * \hideinitializer + */ +#define PDMA_SET_DST_ADDR(pdma, u32Ch, u32Addr) ((uint32_t)(pdma->DSCT[(u32Ch)].DA = (u32Addr))) + +/** + * @brief Set Transfer Count + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32TransCount Transfer Count + * + * @return None + * + * @details This macro set the selected channel transfer count. + * \hideinitializer + */ +#define PDMA_SET_TRANS_CNT(pdma, u32Ch, u32TransCount) ((uint32_t)(pdma->DSCT[(u32Ch)].CTL=(pdma->DSCT[(u32Ch)].CTL&~PDMA_DSCT_CTL_TXCNT_Msk)|(((u32TransCount)-1) << PDMA_DSCT_CTL_TXCNT_Pos))) + +/** + * @brief Set Scatter-gather descriptor Address + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Addr The descriptor address + * + * @return None + * + * @details This macro set the selected channel scatter-gather descriptor address. + * \hideinitializer + */ +#define PDMA_SET_SCATTER_DESC(pdma, u32Ch, u32Addr) ((uint32_t)(pdma->DSCT[(u32Ch)].NEXT = (u32Addr) - (pdma->SCATBA))) + +/** + * @brief Stop the channel + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details This macro stop the selected channel. + * \hideinitializer + */ +#define PDMA_STOP(pdma, u32Ch) ((uint32_t)(pdma->PAUSE = (1 << (u32Ch)))) + +/** + * @brief Pause the channel + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details This macro pause the selected channel. + * \hideinitializer + */ +#define PDMA_PAUSE(pdma, u32Ch) ((uint32_t)(pdma->PAUSE = (1 << (u32Ch)))) + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define PDMA functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +void PDMA_Open(PDMA_T *pdma, uint32_t u32Mask); +void PDMA_Close(PDMA_T *pdma); +void PDMA_SetTransferCnt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount); +void PDMA_SetTransferAddr(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl); +void PDMA_SetTransferMode(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr); +void PDMA_SetBurstType(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize); +void PDMA_EnableTimeout(PDMA_T *pdma, uint32_t u32Mask); +void PDMA_DisableTimeout(PDMA_T *pdma, uint32_t u32Mask); +void PDMA_SetTimeOut(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt); +void PDMA_Trigger(PDMA_T *pdma, uint32_t u32Ch); +void PDMA_EnableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask); +void PDMA_DisableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask); +void PDMA_SetStride(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32DestLen, uint32_t u32SrcLen, uint32_t u32TransCount); + + +/*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group PDMA_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PDMA_H__ */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_psio.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_psio.h new file mode 100644 index 00000000000..04b88fdb72c --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_psio.h @@ -0,0 +1,1190 @@ +/**************************************************************************//** + * @file psio.h + * @version V1.00 + * @brief M251 series psio driver header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +#ifndef __PSIO_H__ +#define __PSIO_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup PSIO_Driver PSIO Driver + @{ +*/ + +/** @addtogroup PSIO_EXPORTED_CONSTANTS PSIO Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Operation Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define PSIO_SC0 0x00000000UL /*!INTEN |= (u32IntSel)) + +/** + * @brief Disable specified PSIO interrupt + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32IntSel Interrupt type select + * - \ref PSIO_INTEN_CON0IE_Msk + * - \ref PSIO_INTEN_CON1IE_Msk + * - \ref PSIO_INTEN_MISMATIE_Msk + * - \ref PSIO_INTEN_TERRIE_Msk + * - \ref PSIO_INTEN_SC0IE_Msk + * - \ref PSIO_INTEN_SC1IE_Msk + * - \ref PSIO_INTEN_SC2IE_Msk + * - \ref PSIO_INTEN_SC3IE_Msk + * + * @return None + * + * @details This macro disable specified PSIO interrupt. + * \hideinitializer + */ +#define PSIO_DISABLE_INT(psio, u32IntSel) ((psio)->INTEN &= ~(u32IntSel)) + +/** + * @brief Get specified interrupt flag/status + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32IntTypeFlag Interrupt Type Flag, Valid values are + * - \ref PSIO_INTSTS_CON0IF_Msk + * - \ref PSIO_INTSTS_CON1IF_Msk + * - \ref PSIO_INTSTS_MISMATIF_Msk + * - \ref PSIO_INTSTS_TERRIF_Msk + * - \ref PSIO_INTSTS_SC0IF_Msk + * - \ref PSIO_INTSTS_SC1IF_Msk + * - \ref PSIO_INTSTS_SC2IF_Msk + * - \ref PSIO_INTSTS_SC3IF_Msk + * + * @return 0 The specified interrupt is not happened. + * 1 The specified interrupt is happened. + * + * @details This macro get specified interrupt flag or interrupt indicator status. + * \hideinitializer + */ +#define PSIO_GET_INT_FLAG(psio, u32IntTypeFlag) (((psio)->INTSTS & (u32IntTypeFlag))?1:0) + +/** + * @brief Clear specified interrupt flag/status + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32IntTypeFlag Interrupt Type Flag, Valid values are + * - \ref PSIO_INTSTS_CON0IF_Msk + * - \ref PSIO_INTSTS_CON1IF_Msk + * - \ref PSIO_INTSTS_MISMATIF_Msk + * - \ref PSIO_INTSTS_TERRIF_Msk + * - \ref PSIO_INTSTS_SC0IF_Msk + * - \ref PSIO_INTSTS_SC1IF_Msk + * - \ref PSIO_INTSTS_SC2IF_Msk + * - \ref PSIO_INTSTS_SC3IF_Msk + * + * @return None + * + * @details This macro Clear specified interrupt flag or interrupt indicator status. + * \hideinitializer + */ +#define PSIO_CLEAR_INT_FLAG(psio, u32IntTypeFlag) ((psio)->INTSTS = u32IntTypeFlag) + +/** + * @brief Get specified transfer status + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32Status Transfer status, Valid values are + * - \ref PSIO_TRANSTS_INFULL0_Msk + * - \ref PSIO_TRANSTS_INOVER0_Msk + * - \ref PSIO_TRANSTS_OUTEPY0_Msk + * - \ref PSIO_TRANSTS_OUTUF0_Msk + * - \ref PSIO_TRANSTS_INFULL1_Msk + * - \ref PSIO_TRANSTS_INOVER1_Msk + * - \ref PSIO_TRANSTS_OUTEPY1_Msk + * - \ref PSIO_TRANSTS_OUTUF1_Msk + * - \ref PSIO_TRANSTS_INFULL2_Msk + * - \ref PSIO_TRANSTS_INOVER2_Msk + * - \ref PSIO_TRANSTS_OUTEPY2_Msk + * - \ref PSIO_TRANSTS_OUTUF2_Msk + * - \ref PSIO_TRANSTS_INFULL3_Msk + * - \ref PSIO_TRANSTS_INOVER3_Msk + * - \ref PSIO_TRANSTS_OUTEPY3_Msk + * - \ref PSIO_TRANSTS_OUTUF3_Msk + * - \ref PSIO_TRANSTS_INFULL4_Msk + * - \ref PSIO_TRANSTS_INOVER4_Msk + * - \ref PSIO_TRANSTS_OUTEPY4_Msk + * - \ref PSIO_TRANSTS_OUTUF4_Msk + * - \ref PSIO_TRANSTS_INFULL5_Msk + * - \ref PSIO_TRANSTS_INOVER5_Msk + * - \ref PSIO_TRANSTS_OUTEPY5_Msk + * - \ref PSIO_TRANSTS_OUTUF5_Msk + * - \ref PSIO_TRANSTS_INFULL6_Msk + * - \ref PSIO_TRANSTS_INOVER6_Msk + * - \ref PSIO_TRANSTS_OUTEPY6_Msk + * - \ref PSIO_TRANSTS_OUTUF6_Msk + * - \ref PSIO_TRANSTS_INFULL7_Msk + * - \ref PSIO_TRANSTS_INOVER7_Msk + * - \ref PSIO_TRANSTS_OUTEPY7_Msk + * - \ref PSIO_TRANSTS_OUTUF7_Msk + * + * @return 0 The specified status is not happened. + * 1 The specified status is happened. + * + * @details This macro get specified transfer status. + * \hideinitializer + */ +#define PSIO_GET_TRANSFER_STATUS(psio, u32Status) (((psio)->TRANSTS & (u32Status))?1:0) + +/** + * @brief Clear specified transfer status + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32Status Transfer status, Valid values are + * - \ref PSIO_TRANSTS_INOVER0_Msk + * - \ref PSIO_TRANSTS_OUTUF0_Msk + * - \ref PSIO_TRANSTS_INOVER1_Msk + * - \ref PSIO_TRANSTS_OUTUF1_Msk + * - \ref PSIO_TRANSTS_INOVER2_Msk + * - \ref PSIO_TRANSTS_OUTUF2_Msk + * - \ref PSIO_TRANSTS_INOVER3_Msk + * - \ref PSIO_TRANSTS_OUTUF3_Msk + * - \ref PSIO_TRANSTS_INOVER4_Msk + * - \ref PSIO_TRANSTS_OUTUF4_Msk + * - \ref PSIO_TRANSTS_INOVER5_Msk + * - \ref PSIO_TRANSTS_OUTUF5_Msk + * - \ref PSIO_TRANSTS_INOVER6_Msk + * - \ref PSIO_TRANSTS_OUTUF6_Msk + * - \ref PSIO_TRANSTS_INOVER7_Msk + * - \ref PSIO_TRANSTS_OUTUF7_Msk + * + * @return None + * + * @details This macro clear specified transfer status. + * \hideinitializer + */ +#define PSIO_CLEAR_TRANSFER_STATUS(psio, u32Status) ((psio)->TRANSTS = u32Status) + +/** + * @brief Get specified input status state + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32Status Transfer input status state, Valid values are + * - \ref PSIO_ISSTS_VALID0_Msk + * - \ref PSIO_ISSTS_INSTSOV0_Msk + * - \ref PSIO_ISSTS_VALID1_Msk + * - \ref PSIO_ISSTS_INSTSOV1_Msk + * - \ref PSIO_ISSTS_VALID2_Msk + * - \ref PSIO_ISSTS_INSTSOV2_Msk + * - \ref PSIO_ISSTS_VALID3_Msk + * - \ref PSIO_ISSTS_INSTSOV3_Msk + * - \ref PSIO_ISSTS_VALID4_Msk + * - \ref PSIO_ISSTS_INSTSOV4_Msk + * - \ref PSIO_ISSTS_VALID5_Msk + * - \ref PSIO_ISSTS_INSTSOV5_Msk + * - \ref PSIO_ISSTS_VALID6_Msk + * - \ref PSIO_ISSTS_INSTSOV6_Msk + * - \ref PSIO_ISSTS_VALID7_Msk + * - \ref PSIO_ISSTS_INSTSOV7_Msk + * + * @return 0 The specified status is not happened. + * 1 The specified status is happened. + * + * @details This macro get input status state. + * \hideinitializer + */ +#define PSIO_GET_INPUT_STATUS_STATE(psio, u32Status) (((psio)->ISSTS & (u32Status))?1:0) + +/** + * @brief Clear specified input status state + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32Status Transfer input status state, Valid values are + * - \ref PSIO_ISSTS_INSTSOV0_Msk + * - \ref PSIO_ISSTS_INSTSOV1_Msk + * - \ref PSIO_ISSTS_INSTSOV2_Msk + * - \ref PSIO_ISSTS_INSTSOV3_Msk + * - \ref PSIO_ISSTS_INSTSOV4_Msk + * - \ref PSIO_ISSTS_INSTSOV5_Msk + * - \ref PSIO_ISSTS_INSTSOV6_Msk + * - \ref PSIO_ISSTS_INSTSOV7_Msk + * + * @return None + * + * @details This macro clear input status state. + * \hideinitializer + */ +#define PSIO_CLEAR_INPUT_STATUS_STATE(psio, u32Status) ((psio)->ISSTS = u32Status) + +/** + * @brief Set PSIO PDMA control input + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32SC The selected slot controller. Valid values are + * - \ref PSIO_SC0 + * - \ref PSIO_SC1 + * - \ref PSIO_SC2 + * - \ref PSIO_SC3 + * @param[in] u32InPin The selected input pin + * - \ref PSIO_PDMACTL_IPIN0EN_Msk + * - \ref PSIO_PDMACTL_IPIN1EN_Msk + * - \ref PSIO_PDMACTL_IPIN2EN_Msk + * - \ref PSIO_PDMACTL_IPIN3EN_Msk + * - \ref PSIO_PDMACTL_IPIN4EN_Msk + * - \ref PSIO_PDMACTL_IPIN5EN_Msk + * - \ref PSIO_PDMACTL_IPIN6EN_Msk + * - \ref PSIO_PDMACTL_IPIN7EN_Msk + * + * @return None + * + * @details This macro set PSIO input with PDMA. + * \hideinitializer + */ +#define PSIO_SET_PDMA_INPUT(psio, u32SC, u32InPin) ((psio)->PDMACTL = ((psio)->PDMACTL & ~PSIO_PDMACTL_INSCSEL_Msk) \ + |((u32SC)<PDMACTL = (psio)->PDMACTL & ~PSIO_PDMACTL_INSCSEL_Msk & ~(u32InPin)) + +/** + * @brief Set PSIO PDMA control output + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32SC The selected slot controller. Valid values are + * - \ref PSIO_SC0 + * - \ref PSIO_SC1 + * - \ref PSIO_SC2 + * - \ref PSIO_SC3 + * @param[in] u32OutPin The selected output pin + * - \ref PSIO_PDMACTL_OPIN0EN_Msk + * - \ref PSIO_PDMACTL_OPIN1EN_Msk + * - \ref PSIO_PDMACTL_OPIN2EN_Msk + * - \ref PSIO_PDMACTL_OPIN3EN_Msk + * - \ref PSIO_PDMACTL_OPIN4EN_Msk + * - \ref PSIO_PDMACTL_OPIN5EN_Msk + * - \ref PSIO_PDMACTL_OPIN6EN_Msk + * - \ref PSIO_PDMACTL_OPIN7EN_Msk + * + * @return None + * + * @details This macro set PSIO output with PDMA. + * \hideinitializer + */ +#define PSIO_SET_PDMA_OUTPUT(psio, u32SC, u32OutPin) ((psio)->PDMACTL = ((psio)->PDMACTL & ~PSIO_PDMACTL_OUTSCSEL_Msk) \ + |((u32SC)<PDMACTL = (psio)->PDMACTL & ~PSIO_PDMACTL_OUTSCSEL_Msk & ~(u32OutPin)) + +/** + * @brief Set slot controller trigger source + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32SC The selected slot controller. Valid values are + * - \ref PSIO_SC0 + * - \ref PSIO_SC1 + * - \ref PSIO_SC2 + * - \ref PSIO_SC3 + * @param[in] u32SrcType The selected trigger source type + * - \ref PSIO_SW_TRIGGER + * - \ref PSIO_FALLING_TRIGGER + * - \ref PSIO_RISING_TRIGGER + * - \ref PSIO_BOTH_EDGE_TRIGGER + * + * @return None + * + * @details This macro set slot controller trigger source. + * \hideinitializer + */ +#define PSIO_SET_TRIGSRC(psio, u32SC, u32SrcType) ((psio)->SCCT[(u32SC)].SCCTL=((psio)->SCCT[(u32SC)].SCCTL & ~PSIO_SCCT_SCCTL_TRIGSRC_Msk)|(u32SrcType)) + +/** + * @brief Start PSIO slot controller + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32SC The selected slot controller. Valid values are + * - \ref PSIO_SC0 + * - \ref PSIO_SC1 + * - \ref PSIO_SC2 + * - \ref PSIO_SC3 + * + * @return None + * + * @details This macro start PSIO slot controller. + * \hideinitializer + */ +#define PSIO_START_SC(psio, u32SC) ((psio)->SCCT[(u32SC)].SCCTL |= PSIO_SCCT_SCCTL_START_Msk) + +/** + * @brief Stop PSIO slot controller + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32SC The selected slot controller. Valid values are + * - \ref PSIO_SC0 + * - \ref PSIO_SC1 + * - \ref PSIO_SC2 + * - \ref PSIO_SC3 + * + * @return None + * + * @details This macro stop PSIO slot controller. + * \hideinitializer + */ +#define PSIO_STOP_SC(psio, u32SC) ((psio)->SCCT[(u32SC)].SCCTL |= PSIO_SCCT_SCCTL_STOP_Msk) + +/** + * @brief Get PSIO busy flag + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32SC The selected slot controller. Valid values are + * - \ref PSIO_SC0 + * - \ref PSIO_SC1 + * - \ref PSIO_SC2 + * - \ref PSIO_SC3 + * + * @return 0 The busy flag is not happened. + * 1 The busy flag is happened. + * + * @details This macro get PSIO busy flag. + * \hideinitializer + */ +#define PSIO_GET_BUSY_FLAG(psio, u32SC) (((psio)->SCCT[(u32SC)].SCCTL & PSIO_SCCT_SCCTL_BUSY_Msk)?1:0) + +/** + * @brief Get PSIO idle flag + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32SC The selected slot controller. Valid values are + * - \ref PSIO_SC0 + * - \ref PSIO_SC1 + * - \ref PSIO_SC2 + * - \ref PSIO_SC3 + * + * @return 0 The idle flag is not happened. + * 1 The idle flag is happened. + * + * @details This macro get PSIO idle flag. + * \hideinitializer + */ +#define PSIO_GET_IDLE_FLAG(psio, u32SC) (((psio)->SCCT[(u32SC)].SCCTL & PSIO_SCCT_SCCTL_IDLE_Msk)?1:0) + +/** +* @brief Clear PSIO idle flag +* +* @param[in] psio The pointer of the specified PSIO module +* @param[in] u32SC The selected slot controller. Valid values are +* - \ref PSIO_SC0 +* - \ref PSIO_SC1 +* - \ref PSIO_SC2 +* - \ref PSIO_SC3 +* +* @return None +* +* @details This macro clear PSIO idle flag. +* \hideinitializer +*/ +#define PSIO_SET_IDLE_FLAG(psio, u32SC) ((psio)->SCCT[(u32SC)].SCCTL |= PSIO_SCCT_SCCTL_IDLE_Msk) + +/** +* @brief Set PSIO slot tick count +* +* @param[in] psio The pointer of the specified PSIO module +* @param[in] u32SC The selected slot controller. Valid values are +* - \ref PSIO_SC0 +* - \ref PSIO_SC1 +* - \ref PSIO_SC2 +* - \ref PSIO_SC3 +* @param[in] u32Slot The selected slot. Valid values are +* - \ref PSIO_SLOT0 +* - \ref PSIO_SLOT1 +* - \ref PSIO_SLOT2 +* - \ref PSIO_SLOT3 +* - \ref PSIO_SLOT4 +* - \ref PSIO_SLOT5 +* - \ref PSIO_SLOT6 +* - \ref PSIO_SLOT7 +* @param[in] u32Cnt The slot tick count. Valid values are 0x0~0xF +* +* @return None +* +* @details This macro set PSIO slot tick count. +* \hideinitializer +*/ +#define PSIO_SCSLOT_SET_SLOT(psio, u32SC, u32Slot, u32Cnt) ((psio)->SCCT[(u32SC)].SCSLOT= \ + ((psio)->SCCT[(u32SC)].SCSLOT & ~(PSIO_SCCT_SCSLOT_SLOT0CNT_Msk<<((u32Slot-1)*PSIO_SCCT_SCSLOT_SLOT1CNT_Pos)))|((u32Cnt&0xF)<<((u32Slot-1)*PSIO_SCCT_SCSLOT_SLOT1CNT_Pos))) + +/** + * @brief Set PSIO all slot tick count + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32SC The selected slot controller. Valid values are + * - \ref PSIO_SC0 + * - \ref PSIO_SC1 + * - \ref PSIO_SC2 + * - \ref PSIO_SC3 + * @param[in] u32Cnt The slot tick count. Valid values are 0x0~0xF + * + * @return None + * + * @details This macro set PSIO all slot tick count. + * \hideinitializer + */ +#define PSIO_SCSLOT_SET_ALL_SLOT(psio, u32SC, u32Cnt) ((psio)->SCCT[(u32SC)].SCSLOT= \ + ((u32Cnt&0xF)<GNCT[(u32Pin)].GENCTL = \ + ((psio)->GNCT[(u32Pin)].GENCTL & ~PSIO_GNCT_GENCTL_PINEN_Msk)|PSIO_GNCT_GENCTL_PINEN_Msk) + +/** + * @brief Disable Pin function + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32Pin The selected Pin. Valid values are + * - \ref PSIO_PIN0 + * - \ref PSIO_PIN1 + * - \ref PSIO_PIN2 + * - \ref PSIO_PIN3 + * - \ref PSIO_PIN4 + * - \ref PSIO_PIN5 + * - \ref PSIO_PIN6 + * - \ref PSIO_PIN7 + * + * @return None + * + * @details This function is used to disable this Pin. + * \hideinitializer + */ +#define PSIO_DISABLE_PIN(psio, u32Pin) ((psio)->GNCT[(u32Pin)].GENCTL = \ + ((psio)->GNCT[(u32Pin)].GENCTL & ~PSIO_GNCT_GENCTL_PINEN_Msk)) + +/** + * @brief Set specified pin data width + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32Pin The selected Pin. Valid values are + * - \ref PSIO_PIN0 + * - \ref PSIO_PIN1 + * - \ref PSIO_PIN2 + * - \ref PSIO_PIN3 + * - \ref PSIO_PIN4 + * - \ref PSIO_PIN5 + * - \ref PSIO_PIN6 + * - \ref PSIO_PIN7 + * @param[in] u32InWidth The input data width. Valid values are 0~32 + * @param[in] u32OutWidth The output data width. Valid values are 0~32 + * + * @return None + * + * @details This macro set in/out data width. + * \hideinitializer + */ +#define PSIO_SET_WIDTH(psio, u32Pin, u32InWidth, u32OutWidth) (((psio)->GNCT[(u32Pin)].DATCTL)= \ + ((psio)->GNCT[(u32Pin)].DATCTL & ~PSIO_GNCT_DATCTL_INDATWD_Msk & ~PSIO_GNCT_DATCTL_OUTDATWD_Msk) \ + |((u32InWidth==0?0:(u32InWidth-1))<GNCT[(u32Pin)].DATCTL)= \ + (PSIO->GNCT[(u32Pin)].DATCTL & ~PSIO_GNCT_DATCTL_ORDER_Msk)|(u32Order)) + +/** + * @brief Set specified pin output data depth + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32Pin The selected Pin. Valid values are + * - \ref PSIO_PIN0 + * - \ref PSIO_PIN1 + * - \ref PSIO_PIN2 + * - \ref PSIO_PIN3 + * - \ref PSIO_PIN4 + * - \ref PSIO_PIN5 + * - \ref PSIO_PIN6 + * - \ref PSIO_PIN7 + * @param[in] u32Depth The data depth. Valid values are + * - \ref PSIO_DEPTH1 + * - \ref PSIO_DEPTH2 + * - \ref PSIO_DEPTH3 + * - \ref PSIO_DEPTH4 + * + * @return None + * + * @details This macro set output data order. + * \hideinitializer + */ +#define PSIO_SET_OUTPUT_DEPTH(psio, u32Pin, u32Depth) ((psio)->GNCT[(u32Pin)].DATCTL= \ + (PSIO->GNCT[(u32Pin)].DATCTL & ~PSIO_GNCT_DATCTL_OUTDEPTH_Msk)|((u32Depth)<GNCT[(u32Pin)].DATCTL= \ + (PSIO->GNCT[(u32Pin)].DATCTL & ~PSIO_GNCT_DATCTL_INDEPTH_Msk)|((u32Depth)<GNCT[u32Pin].INSTS&0xFF) + +/** + * @brief Get specified pin input data + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32Pin The selected Pin. Valid values are + * - \ref PSIO_PIN0 + * - \ref PSIO_PIN1 + * - \ref PSIO_PIN2 + * - \ref PSIO_PIN3 + * - \ref PSIO_PIN4 + * - \ref PSIO_PIN5 + * - \ref PSIO_PIN6 + * - \ref PSIO_PIN7 + * + * @return The specified pin input data + * + * @details This macro get specified pin input data. + * \hideinitializer + */ +#define PSIO_GET_INPUT_DATA(psio, u32Pin) (psio->GNCT[u32Pin].INDAT) + +/** +* @brief Set specified pin output data +* +* @param[in] psio The pointer of the specified PSIO module +* @param[in] u32Pin The selected Pin. Valid values are +* - \ref PSIO_PIN0 +* - \ref PSIO_PIN1 +* - \ref PSIO_PIN2 +* - \ref PSIO_PIN3 +* - \ref PSIO_PIN4 +* - \ref PSIO_PIN5 +* - \ref PSIO_PIN6 +* - \ref PSIO_PIN7 +* @param[in] u32Data The output data +* +* @return None +* +* @details This macro set specified pin output data. +* \hideinitializer +*/ +#define PSIO_SET_OUTPUT_DATA(psio, u32Pin, u32Data) (psio->GNCT[u32Pin].OUTDAT = (u32Data)) + +/** +* @brief Set specified pin check point and slot link +* +* @param[in] psio The pointer of the specified PSIO module +* @param[in] u32Pin The selected Pin. Valid values are +* - \ref PSIO_PIN0 +* - \ref PSIO_PIN1 +* - \ref PSIO_PIN2 +* - \ref PSIO_PIN3 +* - \ref PSIO_PIN4 +* - \ref PSIO_PIN5 +* - \ref PSIO_PIN6 +* - \ref PSIO_PIN7 +* @param[in] u32CheckPoint The selected check point. Valid values are +* - \ref PSIO_CP0 +* - \ref PSIO_CP1 +* - \ref PSIO_CP2 +* - \ref PSIO_CP3 +* - \ref PSIO_CP4 +* - \ref PSIO_CP5 +* - \ref PSIO_CP6 +* - \ref PSIO_CP7 +* @param[in] u32Slot The selected slot. Valid values are +* - \ref PSIO_SLOT0 +* - \ref PSIO_SLOT1 +* - \ref PSIO_SLOT2 +* - \ref PSIO_SLOT3 +* - \ref PSIO_SLOT4 +* - \ref PSIO_SLOT5 +* - \ref PSIO_SLOT6 +* - \ref PSIO_SLOT7 +* +* @return None +* +* @details This macro used to link check point and slot. +* \hideinitializer +*/ +#define PSIO_SET_CHECKPOINT(psio, u32Pin, u32CheckPoint, u32Slot) (psio->GNCT[(u32Pin)].CPCTL0= \ + (psio->GNCT[(u32Pin)].CPCTL0 & ~(PSIO_GNCT_CPCTL0_CKPT0_Msk<<((u32CheckPoint)*PSIO_GNCT_CPCTL0_CKPT1_Pos))) \ + |((u32Slot)<<((u32CheckPoint)*PSIO_GNCT_CPCTL0_CKPT1_Pos))) + +/** + * @brief Clear specified pin check point and slot link + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32Pin The selected Pin. Valid values are + * - \ref PSIO_PIN0 + * - \ref PSIO_PIN1 + * - \ref PSIO_PIN2 + * - \ref PSIO_PIN3 + * - \ref PSIO_PIN4 + * - \ref PSIO_PIN5 + * - \ref PSIO_PIN6 + * - \ref PSIO_PIN7 + * @param[in] u32CheckPoint The selected check point. Valid values are + * - \ref PSIO_CP0 + * - \ref PSIO_CP1 + * - \ref PSIO_CP2 + * - \ref PSIO_CP3 + * - \ref PSIO_CP4 + * - \ref PSIO_CP5 + * - \ref PSIO_CP6 + * - \ref PSIO_CP7 + * + * @return None + * + * @details This macro used to clear the link of check point and slot. + * \hideinitializer + */ +#define PSIO_CLEAR_CHECKPOINT(psio, u32Pin, u32CheckPoint) (psio->GNCT[(u32Pin)].CPCTL0= \ + psio->GNCT[(u32Pin)].CPCTL0 & ~(PSIO_GNCT_CPCTL0_CKPT0_Msk<<((u32CheckPoint)*PSIO_GNCT_CPCTL0_CKPT1_Pos))) + +/** + * @brief Set specified pin action of check point + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32Pin The selected Pin. Valid values are + * - \ref PSIO_PIN0 + * - \ref PSIO_PIN1 + * - \ref PSIO_PIN2 + * - \ref PSIO_PIN3 + * - \ref PSIO_PIN4 + * - \ref PSIO_PIN5 + * - \ref PSIO_PIN6 + * - \ref PSIO_PIN7 + * @param[in] u32CheckPoint The selected check point. Valid values are + * - \ref PSIO_CP0 + * - \ref PSIO_CP1 + * - \ref PSIO_CP2 + * - \ref PSIO_CP3 + * - \ref PSIO_CP4 + * - \ref PSIO_CP5 + * - \ref PSIO_CP6 + * - \ref PSIO_CP7 + * @param[in] u32Action The selected action. Valid values are + * - \ref PSIO_OUT_LOW + * - \ref PSIO_OUT_HIGH + * - \ref PSIO_OUT_BUFFER + * - \ref PSIO_OUT_TOGGLE + * - \ref PSIO_IN_BUFFER + * - \ref PSIO_IN_STATUS + * - \ref PSIO_IN_STATUS_UPDATE + * + * @return None + * + * @details This macro used to set specified pin action of check point. + * \hideinitializer + */ +#define PSIO_SET_ACTION(psio, u32Pin, u32CheckPoint, u32Action) (psio->GNCT[(u32Pin)].CPCTL1= \ + (psio->GNCT[(u32Pin)].CPCTL1 & ~(PSIO_GNCT_CPCTL1_CKPT0ACT_Msk<<((u32CheckPoint)*PSIO_GNCT_CPCTL1_CKPT1ACT_Pos))) \ + |((u32Action)<<((u32CheckPoint)*PSIO_GNCT_CPCTL1_CKPT1ACT_Pos))) + +/*---------------------------------------------------------------------------------------------------------*/ +/* inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/** + * @brief Set interrupt control + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32SC The selected slot controller + * @param[in] u32Int The interrupt type. Valid values are + * - \ref PSIO_INT0 + * - \ref PSIO_INT1 + * @param[in] u32Slot The selected slot. Valid values are + * - \ref PSIO_SLOT0 + * - \ref PSIO_SLOT1 + * - \ref PSIO_SLOT2 + * - \ref PSIO_SLOT3 + * - \ref PSIO_SLOT4 + * - \ref PSIO_SLOT5 + * - \ref PSIO_SLOT6 + * - \ref PSIO_SLOT7 + * + * @return None + * + * @details This function is used to set the selected slot controller, interrupt type and slot. + * \hideinitializer + */ +__STATIC_INLINE void PSIO_SET_INTCTL(PSIO_T *psio, uint32_t u32SC, uint32_t u32Int, uint32_t u32Slot) +{ + if (u32Int == PSIO_INT0) + { + (psio)->INTCTL = (((psio)->INTCTL & ~PSIO_INTCTL_CONI0SS_Msk & ~PSIO_INTCTL_CONI0SCS_Msk) + | ((u32SC) << PSIO_INTCTL_CONI0SCS_Pos) + | ((u32Slot) << PSIO_INTCTL_CONI0SS_Pos)); + } + else if (u32Int == PSIO_INT1) + { + (psio)->INTCTL = (((psio)->INTCTL & ~PSIO_INTCTL_CONI1SS_Msk & ~PSIO_INTCTL_CONI1SCS_Msk) + | ((u32SC) << PSIO_INTCTL_CONI1SCS_Pos) + | ((u32Slot) << PSIO_INTCTL_CONI1SS_Pos)); + } +} + +/** + * @brief Clear interrupt control setting + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32Int The interrupt type. Valid values are + * - \ref PSIO_INT0 + * - \ref PSIO_INT1 + * + * @return None + * + * @details This function is used to clear the selected slot controller, interrupt type and slot. + * \hideinitializer + */ +__STATIC_INLINE void PSIO_CLEAR_INTCTL(PSIO_T *psio, uint32_t u32Int) +{ + if (u32Int == PSIO_INT0) + { + (psio)->INTCTL = ((psio)->INTCTL & ~PSIO_INTCTL_CONI0SS_Msk & ~PSIO_INTCTL_CONI0SCS_Msk); + } + else if (u32Int == PSIO_INT1) + { + (psio)->INTCTL = ((psio)->INTCTL & ~PSIO_INTCTL_CONI1SS_Msk & ~PSIO_INTCTL_CONI1SCS_Msk); + } +} + +/** + * @brief Set Slot controller control + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32SC The selected slot controller + * @param[in] u32InitSlot The selected initial slot of the repeat period. Valid values are + * - \ref PSIO_SLOT0 + * - \ref PSIO_SLOT1 + * - \ref PSIO_SLOT2 + * - \ref PSIO_SLOT3 + * - \ref PSIO_SLOT4 + * - \ref PSIO_SLOT5 + * - \ref PSIO_SLOT6 + * - \ref PSIO_SLOT7 + * @param[in] u32EndSlot The selected end slot of the repeat period. Valid values are + * - \ref PSIO_SLOT0 + * - \ref PSIO_SLOT1 + * - \ref PSIO_SLOT2 + * - \ref PSIO_SLOT3 + * - \ref PSIO_SLOT4 + * - \ref PSIO_SLOT5 + * - \ref PSIO_SLOT6 + * - \ref PSIO_SLOT7 + * @param[in] u32LoopCnt The slot period loop count. Valid values are + * - 0x0 : Disable + * - 0x1~0x3E : Repeat slot 0x2~0x3F times + * - 0x3F : Loop until stop PSIO slot controller + * @param[in] u32Repeat Repeat mode Enable/Disable. Valid values are + * - \ref PSIO_REPEAT_ENABLE + * - \ref PSIO_REPEAT_DISABLE + * + * @return None + * + * @details This function is used to set the slot controller loop and repeat configuration. + * \hideinitializer + */ +__STATIC_INLINE void PSIO_SET_SCCTL(PSIO_T *psio, uint32_t u32SC, uint32_t u32InitSlot, uint32_t u32EndSlot, uint32_t u32LoopCnt, uint32_t u32Repeat) +{ + (psio)->SCCT[u32SC].SCCTL = ((psio)->SCCT[u32SC].SCCTL & ~PSIO_SCCT_SCCTL_INISLOT_Msk & ~PSIO_SCCT_SCCTL_ENDSLOT_Msk & ~PSIO_SCCT_SCCTL_SPLCNT_Msk) + | ((u32InitSlot) << PSIO_SCCT_SCCTL_INISLOT_Pos) + | ((u32EndSlot) << PSIO_SCCT_SCCTL_ENDSLOT_Pos) + | ((u32LoopCnt & 0x3F) << PSIO_SCCT_SCCTL_SPLCNT_Pos); + + if (u32Repeat == PSIO_REPEAT_ENABLE) + (psio)->SCCT[u32SC].SCCTL |= PSIO_SCCT_SCCTL_REPEAT_Msk; + else if (u32Repeat == PSIO_REPEAT_DISABLE) + (psio)->SCCT[u32SC].SCCTL &= ~PSIO_SCCT_SCCTL_REPEAT_Msk; +} + +/** + * @brief Set Pin general control + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32Pin The selected Pin. Valid values are + * - \ref PSIO_PIN0 + * - \ref PSIO_PIN1 + * - \ref PSIO_PIN2 + * - \ref PSIO_PIN3 + * - \ref PSIO_PIN4 + * - \ref PSIO_PIN5 + * - \ref PSIO_PIN6 + * - \ref PSIO_PIN7 + * @param[in] u32PinEn The selected Pin enable/disable. Valid values are + * - \ref PSIO_PIN_ENABLE + * - \ref PSIO_PIN_DISABLE + * @param[in] u32SC The selected slot controller for check point. Valid values are + * - \ref PSIO_SC0 + * - \ref PSIO_SC1 + * - \ref PSIO_SC2 + * - \ref PSIO_SC3 + * @param[in] u32IOMode The pin I/O mode. Valid values are + * - \ref PSIO_INPUT_MODE + * - \ref PSIO_OUTPUT_MODE + * - \ref PSIO_OPENDRAIN_MODE + * - \ref PSIO_QUASI_MODE + * @param[in] u32PinInit The pin initial status. Valid values are + * - \ref PSIO_LOW_LEVEL + * - \ref PSIO_HIGH_LEVEL + * - \ref PSIO_LAST_OUTPUT + * - \ref PSIO_Toggle + * @param[in] u32PinInterval The pin interval status. Valid values are + * - \ref PSIO_LOW_LEVEL + * - \ref PSIO_HIGH_LEVEL + * - \ref PSIO_LAST_OUTPUT + * - \ref PSIO_Toggle + * + * @return None + * + * @details This function is used to set the general control. + * \hideinitializer + */ +__STATIC_INLINE void PSIO_SET_GENCTL(PSIO_T *psio, uint32_t u32Pin, uint32_t u32PinEn, uint32_t u32SC, uint32_t u32IOMode, uint32_t u32PinInit, uint32_t u32PinInterval) +{ + (psio)->GNCT[u32Pin].GENCTL = ((psio)->GNCT[u32Pin].GENCTL & ~PSIO_GNCT_GENCTL_SCSEL_Msk & ~PSIO_GNCT_GENCTL_IOMODE_Msk + & ~PSIO_GNCT_GENCTL_INITIAL_Msk & ~PSIO_GNCT_GENCTL_INTERVAL_Msk) + | ((u32SC) << PSIO_GNCT_GENCTL_SCSEL_Pos) | ((u32IOMode) << PSIO_GNCT_GENCTL_IOMODE_Pos) + | ((u32PinInit) << PSIO_GNCT_GENCTL_INITIAL_Pos) | ((u32PinInterval) << PSIO_GNCT_GENCTL_INTERVAL_Pos); + + if (u32PinEn == PSIO_PIN_ENABLE) + (psio)->GNCT[u32Pin].GENCTL |= PSIO_GNCT_GENCTL_PINEN_Msk; + else if (u32PinEn == PSIO_PIN_DISABLE) + (psio)->GNCT[u32Pin].GENCTL &= ~PSIO_GNCT_GENCTL_PINEN_Msk; +} + +/** + * @brief Set Pin mode switch + * + * @param[in] psio The pointer of the specified PSIO module + * @param[in] u32Pin The selected Pin. Valid values are + * - \ref PSIO_PIN0 + * - \ref PSIO_PIN1 + * - \ref PSIO_PIN2 + * - \ref PSIO_PIN3 + * - \ref PSIO_PIN4 + * - \ref PSIO_PIN5 + * - \ref PSIO_PIN6 + * - \ref PSIO_PIN7 + * @param[in] u32SwPoint The switch point. Valid values are + * - \ref PSIO_SWITCH_P0 + * - \ref PSIO_SWITCH_P1 + * @param[in] u32SwMode The switch mode. Valid values are + * - \ref PSIO_INPUT_MODE + * - \ref PSIO_OUTPUT_MODE + * - \ref PSIO_OPENDRAIN_MODE + * - \ref PSIO_QUASI_MODE + * @param[in] u32SwCP The switch I/O mode at which point. Valid values are + * - \ref PSIO_CP0 + * - \ref PSIO_CP1 + * - \ref PSIO_CP2 + * - \ref PSIO_CP3 + * - \ref PSIO_CP4 + * - \ref PSIO_CP5 + * - \ref PSIO_CP6 + * - \ref PSIO_CP7 + * @return None + * + * @details This function is used to set the pin mode switch. + * \hideinitializer + */ +__STATIC_INLINE void PSIO_SWITCH_MODE(PSIO_T *psio, uint32_t u32Pin, uint32_t u32SwPoint, uint32_t u32SwMode, uint32_t u32SwCP) +{ + if (u32SwPoint == PSIO_SWITCH_P0) + { + (psio)->GNCT[u32Pin].GENCTL = ((psio)->GNCT[u32Pin].GENCTL & ~PSIO_GNCT_GENCTL_MODESW0_Msk & ~PSIO_GNCT_GENCTL_SW0CP_Msk) + | ((u32SwMode) << PSIO_GNCT_GENCTL_MODESW0_Pos) | ((u32SwCP + 1) << PSIO_GNCT_GENCTL_SW0CP_Pos); + } + else if (u32SwPoint == PSIO_SWITCH_P1) + { + (psio)->GNCT[u32Pin].GENCTL = ((psio)->GNCT[u32Pin].GENCTL & ~PSIO_GNCT_GENCTL_MODESW1_Msk & ~PSIO_GNCT_GENCTL_SW1CP_Msk) + | ((u32SwMode) << PSIO_GNCT_GENCTL_MODESW1_Pos) | ((u32SwCP + 1) << PSIO_GNCT_GENCTL_SW1CP_Pos); + } +} + +/** +* @brief Set specified pin check point and slot link, and pin action of check point +* +* @param[in] psio The pointer of the specified PSIO module +* @param[in] u32Pin The selected Pin. Valid values are +* - \ref PSIO_PIN0 +* - \ref PSIO_PIN1 +* - \ref PSIO_PIN2 +* - \ref PSIO_PIN3 +* - \ref PSIO_PIN4 +* - \ref PSIO_PIN5 +* - \ref PSIO_PIN6 +* - \ref PSIO_PIN7 +* @param[in] sConfig The selected check point configurations. +* +* @return None +* +* @details This macro used to link check point and slot, and set pin action of check point. +* \hideinitializer +*/ +__STATIC_INLINE void PSIO_SET_CP_CONFIG(PSIO_T *psio, uint32_t u32Pin, const S_PSIO_CP_CONFIG *sConfig) +{ + psio->GNCT[u32Pin].CPCTL0 = *(uint32_t*)sConfig; + psio->GNCT[u32Pin].CPCTL1 = *((uint32_t*)sConfig+1); +} + +/*@}*/ /* end of group PSIO_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group PSIO_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PSIO_H__ */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_pwm.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_pwm.h new file mode 100644 index 00000000000..fbbc24f90f4 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_pwm.h @@ -0,0 +1,515 @@ +/****************************************************************************** + * @file pwm.h + * @version V0.10 + * @brief M251 series PWM driver header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __PWM_H__ +#define __PWM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup PWM_Driver PWM Driver + @{ +*/ + +/** @addtogroup PWM_EXPORTED_CONSTANTS PWM Exported Constants + @{ +*/ +#define PWM_CHANNEL_NUM (6UL) /*!< PWM channel number */ +#define PWM_CH_0_MASK (0x1UL) /*!< PWM channel 0 mask */ +#define PWM_CH_1_MASK (0x2UL) /*!< PWM channel 1 mask */ +#define PWM_CH_2_MASK (0x4UL) /*!< PWM channel 2 mask */ +#define PWM_CH_3_MASK (0x8UL) /*!< PWM channel 3 mask */ +#define PWM_CH_4_MASK (0x10UL) /*!< PWM channel 4 mask */ +#define PWM_CH_5_MASK (0x20UL) /*!< PWM channel 5 mask */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define PWM_UP_COUNTER (0UL) /*!< Up counter type */ +#define PWM_DOWN_COUNTER (1UL) /*!< Down counter type */ +#define PWM_UP_DOWN_COUNTER (2UL) /*!< Up-Down counter type */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Aligned Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define PWM_EDGE_ALIGNED (1UL) /*!< PWM working in edge aligned type(down count) */ +#define PWM_CENTER_ALIGNED (2UL) /*!< PWM working in center aligned type */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Output Level Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define PWM_OUTPUT_NOTHING (0UL) /*!< PWM output nothing */ +#define PWM_OUTPUT_LOW (1UL) /*!< PWM output low */ +#define PWM_OUTPUT_HIGH (2UL) /*!< PWM output high */ +#define PWM_OUTPUT_TOGGLE (3UL) /*!< PWM output toggle */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Synchronous Start Function Control Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define PWM_SSCTL_SSRC_PWM0 (0UL<CTL1 = (pwm)->CTL1 | PWM_CTL1_OUTMODE0_Msk | PWM_CTL1_OUTMODE2_Msk | PWM_CTL1_OUTMODE4_Msk) + +/** + * @brief This macro disable complementary mode, and enable independent mode. + * @param[in] pwm The pointer of the specified PWM module + * @return None + * @details This macro is used to disable complementary mode of PWM module. + * \hideinitializer + */ +#define PWM_DISABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL1 = (pwm)->CTL1 & ~PWM_CTL1_OUTMODE0_Msk & ~PWM_CTL1_OUTMODE2_Msk & ~PWM_CTL1_OUTMODE4_Msk) + +/** + * @brief Enable timer synchronous start counting function of specified channel(s) + * @param[in] pwm The pointer of the specified PWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32SyncSrc Synchronous start source selection, valid values are: + * - \ref PWM_SSCTL_SSRC_PWM0 + * - \ref PWM_SSCTL_SSRC_PWM1 + * - \ref PWM_SSCTL_SSRC_BPWM0 + * - \ref PWM_SSCTL_SSRC_BPWM1 + * @return None + * @details This macro is used to enable timer synchronous start counting function of specified channel(s). + * @note Every two channels share the same setting. + * \hideinitializer + */ +#define PWM_ENABLE_TIMER_SYNC(pwm, u32ChannelMask, u32SyncSrc) \ + do{ \ + uint32_t i;\ + (pwm)->SSCTL = ((pwm)->SSCTL & ~PWM_SSCTL_SSRC_Msk) | (u32SyncSrc) ; \ + for(i = 0UL; i < 6UL; i++) { \ + if((u32ChannelMask) & (1UL << i)) \ + (pwm)->SSCTL |= (1UL << ((i >> 1UL) << 1UL)); \ + } \ + }while(0) + +/** + * @brief Disable timer synchronous start counting function of specified channel(s) + * @param[in] pwm The pointer of the specified PWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * @details This macro is used to disable timer synchronous start counting function of specified channel(s). + * @note Every two channels share the same setting. + * \hideinitializer + */ +#define PWM_DISABLE_TIMER_SYNC(pwm, u32ChannelMask) \ + do{ \ + uint32_t i;\ + for(i = 0UL; i < 6UL; i++) { \ + if((u32ChannelMask) & (1UL << i)) \ + (pwm)->SSCTL &= ~(1UL << ((i >> 1UL) << 1UL)); \ + } \ + }while(0) + +/** + * @brief This macro enable PWM counter synchronous start counting function. + * @param[in] pwm The pointer of the specified PWM module + * @return None + * @details This macro is used to make selected PWM0 and PWM1 channel(s) start counting at the same time. + * To configure synchronous start counting channel(s) by PWM_ENABLE_TIMER_SYNC() and PWM_DISABLE_TIMER_SYNC(). + * \hideinitializer + */ +#define PWM_TRIGGER_SYNC_START(pwm) ((pwm)->SSTRG = PWM_SSTRG_CNTSEN_Msk) + +/** + * @brief This macro enable output inverter of specified channel(s) + * @param[in] pwm The pointer of the specified PWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * @details This macro is used to enable output inverter of specified channel(s). + * \hideinitializer + */ +#define PWM_ENABLE_OUTPUT_INVERTER(pwm, u32ChannelMask) ((pwm)->POLCTL = (u32ChannelMask)) + +/** + * @brief This macro get captured rising data + * @param[in] pwm The pointer of the specified PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @return None + * @details This macro is used to get captured rising data of specified channel. + * \hideinitializer + */ +#define PWM_GET_CAPTURE_RISING_DATA(pwm, u32ChannelNum) ((pwm)->CAPDAT[(u32ChannelNum)].RCAPDAT) + +/** + * @brief This macro get captured falling data + * @param[in] pwm The pointer of the specified PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @return None + * @details This macro is used to get captured falling data of specified channel. + * \hideinitializer + */ +#define PWM_GET_CAPTURE_FALLING_DATA(pwm, u32ChannelNum) ((pwm)->CAPDAT[(u32ChannelNum)].FCAPDAT) + +/** + * @brief This macro mask output logic to high or low + * @param[in] pwm The pointer of the specified PWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32LevelMask Output logic to high or low + * @return None + * @details This macro is used to mask output logic to high or low of specified channel(s). + * @note If u32ChannelMask parameter is 0, then mask function will be disabled. + * \hideinitializer + */ +#define PWM_MASK_OUTPUT(pwm, u32ChannelMask, u32LevelMask) \ + do{ \ + (pwm)->MSKEN = (u32ChannelMask); \ + (pwm)->MSK = (u32LevelMask); \ + }while(0) + +/** + * @brief This macro set the prescaler of the selected channel + * @param[in] pwm The pointer of the specified PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFFF + * @return None + * @details This macro is used to set the prescaler of specified channel. + * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, + * channel 1 will also be affected. The clock of PWM counter is divided by (u32Prescaler + 1). + * \hideinitializer + */ +#define PWM_SET_PRESCALER(pwm, u32ChannelNum, u32Prescaler) ((pwm)->CLKPSC[(u32ChannelNum) >> 1UL] = (u32Prescaler)) + +/** + * @brief This macro get the prescaler of the selected channel + * @param[in] pwm The pointer of the specified PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @return Return Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF + * @details This macro is used to get the prescaler of specified channel. + * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, channel 1 will also be affected. + * The clock of PWM counter is divided by (u32Prescaler + 1). + * \hideinitializer + */ +#define PWM_GET_PRESCALER(pwm, u32ChannelNum) ((pwm)->CLKPSC[(u32ChannelNum) >> 1UL]) + +/** + * @brief This macro set the comparator of the selected channel + * @param[in] pwm The pointer of the specified PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @param[in] u32CMR Comparator of specified channel. Valid values are between 0~0xFFFF + * @return None + * @details This macro is used to set the comparator of specified channel. + * @note This new setting will take effect on next PWM period. + * \hideinitializer + */ +#define PWM_SET_CMR(pwm, u32ChannelNum, u32CMR) ((pwm)->CMPDAT[(u32ChannelNum)] = (u32CMR)) + +/** + * @brief This macro get the comparator of the selected channel + * @param[in] pwm The pointer of the specified PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @return Return the comparator of specified channel. Valid values are between 0~0xFFFF + * @details This macro is used to get the comparator of specified channel. + * \hideinitializer + */ +#define PWM_GET_CMR(pwm, u32ChannelNum) ((pwm)->CMPDAT[(u32ChannelNum)]) + +/** + * @brief This macro set the period of the selected channel + * @param[in] pwm The pointer of the specified PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0, 2, 4. Every two channels share the same setting. + * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF + * @return None + * @details This macro is used to set the period of specified channel. + * @note This new setting will take effect on next PWM period. + * @note PWM counter will stop if period length set to 0. + * \hideinitializer + */ +#define PWM_SET_CNR(pwm, u32ChannelNum, u32CNR) ((pwm)->PERIOD[(((u32ChannelNum) >> 1UL) << 1UL)] = (u32CNR)) + +/** + * @brief This macro get the period of the selected channel + * @param[in] pwm The pointer of the specified PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @return Return the period of specified channel. Valid values are between 0~0xFFFF + * @details This macro is used to get the period of specified channel. + * \hideinitializer + */ +#define PWM_GET_CNR(pwm, u32ChannelNum) ((pwm)->PERIOD[(((u32ChannelNum) >> 1UL) << 1UL)]) + +/** + * @brief This macro set the PWM aligned type + * @param[in] pwm The pointer of the specified PWM module + * @param[in] u32ChannelMask Combination of enabled channels. Every two channels share the same setting. + * @param[in] u32AlignedType PWM aligned type, valid values are: + * - \ref PWM_UP_COUNTER + * - \ref PWM_DOWN_COUNTER + * - \ref PWM_UP_DOWN_COUNTER + * @return None + * @details This macro is used to set the PWM aligned type of specified channel(s). + * \hideinitializer + */ +#define PWM_SET_ALIGNED_TYPE(pwm, u32ChannelMask, u32AlignedType) \ + do{ \ + uint32_t i; \ + for(i = 0UL; i < 6UL; i++) { \ + if((u32ChannelMask) & (1UL << i)) \ + (pwm)->CTL1 = (((pwm)->CTL1 & ~(3UL << ((i >> 1UL) << 2UL))) | ((u32AlignedType) << ((i >> 1UL) << 2UL))); \ + } \ + }while(0) + +/** + * @brief Clear counter of specified channel(s) + * @param[in] pwm The pointer of the specified PWM module + * @param[in] u32ChannelMask Combination of enabled channels. Every two channels share the same setting. + * @return None + * @details This macro is used to clear counter of specified channel(s). + * \hideinitializer + */ +#define PWM_CLR_COUNTER(pwm, u32ChannelMask) \ + do{ \ + uint32_t i; \ + for(i = 0UL; i < 6UL; i++) { \ + if((u32ChannelMask) & (1UL << i)) \ + ((pwm)->CNTCLR |= (1UL << ((i >> 1UL) << 1UL))); \ + } \ + }while(0) + +/** + * @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s) + * @param[in] pwm The pointer of the specified PWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32ZeroLevel output level at zero point, valid values are: + * - \ref PWM_OUTPUT_NOTHING + * - \ref PWM_OUTPUT_LOW + * - \ref PWM_OUTPUT_HIGH + * - \ref PWM_OUTPUT_TOGGLE + * @param[in] u32CmpUpLevel output level at compare up point, valid values are: + * - \ref PWM_OUTPUT_NOTHING + * - \ref PWM_OUTPUT_LOW + * - \ref PWM_OUTPUT_HIGH + * - \ref PWM_OUTPUT_TOGGLE + * @param[in] u32PeriodLevel output level at period(center) point, valid values are: + * - \ref PWM_OUTPUT_NOTHING + * - \ref PWM_OUTPUT_LOW + * - \ref PWM_OUTPUT_HIGH + * - \ref PWM_OUTPUT_TOGGLE + * @param[in] u32CmpDownLevel output level at compare down point, valid values are: + * - \ref PWM_OUTPUT_NOTHING + * - \ref PWM_OUTPUT_LOW + * - \ref PWM_OUTPUT_HIGH + * - \ref PWM_OUTPUT_TOGGLE + * @return None + * @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s). + * \hideinitializer + */ +#define PWM_SET_OUTPUT_LEVEL(pwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \ + do{ \ + uint32_t i; \ + for(i = 0UL; i < 6UL; i++) { \ + if((u32ChannelMask) & (1UL << i)) { \ + (pwm)->WGCTL0 = (((pwm)->WGCTL0 & ~(3UL << (i << 1UL))) | ((u32ZeroLevel) << (i << 1UL))); \ + (pwm)->WGCTL0 = (((pwm)->WGCTL0 & ~(3UL << (PWM_WGCTL0_PRDPCTL0_Pos + (i << 1UL)))) | ((u32PeriodLevel) << (PWM_WGCTL0_PRDPCTL0_Pos + (i << 1UL)))); \ + (pwm)->WGCTL1 = (((pwm)->WGCTL1 & ~(3UL << (i << 1UL))) | ((u32CmpUpLevel) << (i << 1UL))); \ + (pwm)->WGCTL1 = (((pwm)->WGCTL1 & ~(3UL << (PWM_WGCTL1_CMPDCTL0_Pos + (i << 1UL)))) | ((u32CmpDownLevel) << (PWM_WGCTL1_CMPDCTL0_Pos + (i << 1UL)))); \ + } \ + } \ + }while(0) + +/** + * @brief Trigger brake event from specified channel(s) by using sw trigger + * @param[in] pwm The pointer of the specified PWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4 + * @param[in] u32BrakeType Type of brake trigger. It supports PWM_FB_EDGE and PWM_FB_LEVEL. + * - \ref PWM_FB_EDGE + * - \ref PWM_FB_LEVEL + * @return None + * @details This macro is used to trigger brake event from specified channel(s) by using sw trigger. + * \hideinitializer + */ +#define PWM_TRIGGER_BRAKE(pwm, u32ChannelMask, u32BrakeType) ((pwm)->SWBRK |= ((u32ChannelMask) << (u32BrakeType))) + +/** + * @brief Set Dead zone clock source + * @param[in] pwm The pointer of the specified PWM module + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @param[in] u32AfterPrescaler Dead zone clock source is from prescaler output. Valid values are TRUE (after prescaler) or FALSE (before prescaler). + * @return None + * @details This macro is used to set Dead zone clock source. Every two channels share the same setting. + * @note The write-protection function should be disabled before using this function. + * \hideinitializer + */ +#define PWM_SET_DEADZONE_CLK_SRC(pwm, u32ChannelNum, u32AfterPrescaler) \ + (((pwm)->DTCTL[(u32ChannelNum) >> 1UL]) = ((pwm)->DTCTL[(u32ChannelNum) >> 1UL] & ~PWM_DTCTL0_1_DTCKSEL_Msk) | \ + ((u32AfterPrescaler) << PWM_DTCTL0_1_DTCKSEL_Pos)) + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define PWM functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +uint32_t PWM_ConfigCaptureChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge); +uint32_t PWM_ConfigOutputChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle); +uint32_t PWM_ConfigOutputChannel2(PWM_T *epwm, + uint32_t u32ChannelNum, + uint32_t u32Frequency, + uint32_t u32DutyCycle, + uint32_t u32Frequency2); +void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask); +void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask); +void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask); +void PWM_EnableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition); +void PWM_DisableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum); +void PWM_ClearADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition); +uint32_t PWM_GetADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum); +void PWM_EnableFaultBrake(PWM_T *pwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource); +void PWM_EnableCapture(PWM_T *pwm, uint32_t u32ChannelMask); +void PWM_DisableCapture(PWM_T *pwm, uint32_t u32ChannelMask); +void PWM_EnableOutput(PWM_T *pwm, uint32_t u32ChannelMask); +void PWM_DisableOutput(PWM_T *pwm, uint32_t u32ChannelMask); +void PWM_EnableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration); +void PWM_DisableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum); +void PWM_EnableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge); +void PWM_DisableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge); +void PWM_ClearCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge); +uint32_t PWM_GetCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum); +void PWM_EnableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType); +void PWM_DisableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum); +void PWM_ClearDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum); +uint32_t PWM_GetDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum); +void PWM_EnableLoadMode(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); +void PWM_DisableLoadMode(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); +void PWM_EnableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource); +void PWM_DisableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource); +void PWM_ClearFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource); +uint32_t PWM_GetFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource); +void PWM_EnablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType); +void PWM_DisablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum); +void PWM_ClearPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum); +uint32_t PWM_GetPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum); +void PWM_EnableZeroInt(PWM_T *pwm, uint32_t u32ChannelNum); +void PWM_DisableZeroInt(PWM_T *pwm, uint32_t u32ChannelNum); +void PWM_ClearZeroIntFlag(PWM_T *pwm, uint32_t u32ChannelNum); +uint32_t PWM_GetZeroIntFlag(PWM_T *pwm, uint32_t u32ChannelNum); +void PWM_SetClockSource(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel); +void PWM_EnableBrakeNoiseFilter(PWM_T *pwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel); +void PWM_DisableBrakeNoiseFilter(PWM_T *pwm, uint32_t u32BrakePinNum); +void PWM_EnableBrakePinInverse(PWM_T *pwm, uint32_t u32BrakePinNum); +void PWM_DisableBrakePinInverse(PWM_T *pwm, uint32_t u32BrakePinNum); +void PWM_SetBrakePinSource(PWM_T *pwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule); +uint32_t PWM_GetWrapAroundFlag(PWM_T *pwm, uint32_t u32ChannelNum); +void PWM_ClearWrapAroundFlag(PWM_T *pwm, uint32_t u32ChannelNum); +void PWM_EnablePDMA(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode); +void PWM_DisablePDMA(PWM_T *pwm, uint32_t u32ChannelNum); + +/*@}*/ /* end of group PWM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group PWM_Driver */ + +/*@}*/ /* end of group Standard_Driver*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __PWM_H__ */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_qspi.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_qspi.h new file mode 100644 index 00000000000..cb2901791f0 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_qspi.h @@ -0,0 +1,389 @@ +/**************************************************************************//** + * @file qspi.h + * @version V0.10 + * @brief M251 series QSPI driver header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __QSPI_H__ +#define __QSPI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup QSPI_Driver QSPI Driver + @{ +*/ + +/** @addtogroup QSPI_EXPORTED_CONSTANTS QSPI Exported Constants + @{ +*/ + +#define QSPI_MODE_0 (QSPI_CTL_TXNEG_Msk) /*!< CLKPOL=0; RXNEG=0; TXNEG=1 \hideinitializer */ +#define QSPI_MODE_1 (QSPI_CTL_RXNEG_Msk) /*!< CLKPOL=0; RXNEG=1; TXNEG=0 \hideinitializer */ +#define QSPI_MODE_2 (QSPI_CTL_CLKPOL_Msk | QSPI_CTL_RXNEG_Msk) /*!< CLKPOL=1; RXNEG=1; TXNEG=0 \hideinitializer */ +#define QSPI_MODE_3 (QSPI_CTL_CLKPOL_Msk | QSPI_CTL_TXNEG_Msk) /*!< CLKPOL=1; RXNEG=0; TXNEG=1 \hideinitializer */ + +#define QSPI_SLAVE (QSPI_CTL_SLAVE_Msk) /*!< Set as slave \hideinitializer */ +#define QSPI_MASTER (0x0UL) /*!< Set as master \hideinitializer */ + +#define QSPI_SS (QSPI_SSCTL_SS_Msk) /*!< Set SS \hideinitializer */ +#define QSPI_SS_ACTIVE_HIGH (QSPI_SSCTL_SSACTPOL_Msk) /*!< SS active high \hideinitializer */ +#define QSPI_SS_ACTIVE_LOW (0x0UL) /*!< SS active low \hideinitializer */ + +/* QSPI Interrupt Mask */ +#define QSPI_UNIT_INT_MASK (0x001UL) /*!< Unit transfer interrupt mask \hideinitializer */ +#define QSPI_SSACT_INT_MASK (0x002UL) /*!< Slave selection signal active interrupt mask \hideinitializer */ +#define QSPI_SSINACT_INT_MASK (0x004UL) /*!< Slave selection signal inactive interrupt mask \hideinitializer */ +#define QSPI_SLVUR_INT_MASK (0x008UL) /*!< Slave under run interrupt mask \hideinitializer */ +#define QSPI_SLVBE_INT_MASK (0x010UL) /*!< Slave bit count error interrupt mask \hideinitializer */ +#define QSPI_SLVTO_INT_MASK (0x020UL) /*!< Slave Mode Time-out interrupt mask \hideinitializer */ +#define QSPI_TXUF_INT_MASK (0x040UL) /*!< Slave TX underflow interrupt mask \hideinitializer */ +#define QSPI_FIFO_TXTH_INT_MASK (0x080UL) /*!< FIFO TX threshold interrupt mask \hideinitializer */ +#define QSPI_FIFO_RXTH_INT_MASK (0x100UL) /*!< FIFO RX threshold interrupt mask \hideinitializer */ +#define QSPI_FIFO_RXOV_INT_MASK (0x200UL) /*!< FIFO RX overrun interrupt mask \hideinitializer */ +#define QSPI_FIFO_RXTO_INT_MASK (0x400UL) /*!< FIFO RX time-out interrupt mask \hideinitializer */ + +/* QSPI Status Mask */ +#define QSPI_BUSY_MASK (0x01UL) /*!< Busy status mask \hideinitializer */ +#define QSPI_RX_EMPTY_MASK (0x02UL) /*!< RX empty status mask \hideinitializer */ +#define QSPI_RX_FULL_MASK (0x04UL) /*!< RX full status mask \hideinitializer */ +#define QSPI_TX_EMPTY_MASK (0x08UL) /*!< TX empty status mask \hideinitializer */ +#define QSPI_TX_FULL_MASK (0x10UL) /*!< TX full status mask \hideinitializer */ +#define QSPI_TXRX_RESET_MASK (0x20UL) /*!< TX or RX reset status mask \hideinitializer */ +#define QSPI_QSPIEN_STS_MASK (0x40UL) /*!< QSPIEN status mask \hideinitializer */ +#define QSPI_SSLINE_STS_MASK (0x80UL) /*!< QSPIx_SS line status mask \hideinitializer */ + +/*@}*/ /* end of group QSPI_EXPORTED_CONSTANTS */ + + +/** @addtogroup QSPI_EXPORTED_FUNCTIONS QSPI Exported Functions + @{ +*/ + +/** + * @brief Clear the unit transfer interrupt flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Write 1 to UNITIF bit of QSPI_STATUS register to clear the unit transfer interrupt flag. + * \hideinitializer + */ +#define QSPI_CLR_UNIT_TRANS_INT_FLAG(qspi) ((qspi)->STATUS = QSPI_STATUS_UNITIF_Msk) + +/** + * @brief Trigger RX PDMA function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set RXPDMAEN bit of QSPI_PDMACTL register to enable RX PDMA transfer function. + * \hideinitializer + */ +#define QSPI_TRIGGER_RX_PDMA(qspi) ((qspi)->PDMACTL |= QSPI_PDMACTL_RXPDMAEN_Msk) + +/** + * @brief Trigger TX PDMA function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set TXPDMAEN bit of QSPI_PDMACTL register to enable TX PDMA transfer function. + * \hideinitializer + */ +#define QSPI_TRIGGER_TX_PDMA(qspi) ((qspi)->PDMACTL |= QSPI_PDMACTL_TXPDMAEN_Msk) + +/** + * @brief Disable RX PDMA transfer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear RXPDMAEN bit of QSPI_PDMACTL register to disable RX PDMA transfer function. + * \hideinitializer + */ +#define QSPI_DISABLE_RX_PDMA(qspi) ( (qspi)->PDMACTL &= ~QSPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Disable TX PDMA transfer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear TXPDMAEN bit of QSPI_PDMACTL register to disable TX PDMA transfer function. + * \hideinitializer + */ +#define QSPI_DISABLE_TX_PDMA(qspi) ( (qspi)->PDMACTL &= ~QSPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Get the count of available data in RX FIFO. + * @param[in] qspi The pointer of the specified QSPI module. + * @return The count of available data in RX FIFO. + * @details Read RXCNT (QSPI_STATUS[27:24]) to get the count of available data in RX FIFO. + * \hideinitializer + */ +#define QSPI_GET_RX_FIFO_COUNT(qspi) (((qspi)->STATUS & QSPI_STATUS_RXCNT_Msk) >> QSPI_STATUS_RXCNT_Pos) + +/** + * @brief Get the RX FIFO empty flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @retval 0 RX FIFO is not empty. + * @retval 1 RX FIFO is empty. + * @details Read RXEMPTY bit of QSPI_STATUS register to get the RX FIFO empty flag. + * \hideinitializer + */ +#define QSPI_GET_RX_FIFO_EMPTY_FLAG(qspi) (((qspi)->STATUS & QSPI_STATUS_RXEMPTY_Msk)>>QSPI_STATUS_RXEMPTY_Pos) + +/** + * @brief Get the TX FIFO empty flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @retval 0 TX FIFO is not empty. + * @retval 1 TX FIFO is empty. + * @details Read TXEMPTY bit of QSPI_STATUS register to get the TX FIFO empty flag. + * \hideinitializer + */ +#define QSPI_GET_TX_FIFO_EMPTY_FLAG(qspi) (((qspi)->STATUS & QSPI_STATUS_TXEMPTY_Msk)>>QSPI_STATUS_TXEMPTY_Pos) + +/** + * @brief Get the TX FIFO full flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @retval 0 TX FIFO is not full. + * @retval 1 TX FIFO is full. + * @details Read TXFULL bit of QSPI_STATUS register to get the TX FIFO full flag. + * \hideinitializer + */ +#define QSPI_GET_TX_FIFO_FULL_FLAG(qspi) (((qspi)->STATUS & QSPI_STATUS_TXFULL_Msk)>>QSPI_STATUS_TXFULL_Pos) + +/** + * @brief Get the datum read from RX register. + * @param[in] qspi The pointer of the specified QSPI module. + * @return Data in RX register. + * @details Read QSPI_RX register to get the received datum. + * \hideinitializer + */ +#define QSPI_READ_RX(qspi) ((qspi)->RX) + +/** + * @brief Write datum to TX register. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32TxData The datum which user attempt to transfer through QSPI bus. + * @return None. + * @details Write u32TxData to QSPI_TX register. + * \hideinitializer + */ +#define QSPI_WRITE_TX(qspi, u32TxData) ((qspi)->TX = (u32TxData)) + +/** + * @brief Set QSPIx_SS pin to high state. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Disable automatic slave selection function and set QSPIx_SS pin to high state. + * \hideinitializer + */ +#define QSPI_SET_SS_HIGH(qspi) ((qspi)->SSCTL = ((qspi)->SSCTL & (~QSPI_SSCTL_AUTOSS_Msk)) | (QSPI_SSCTL_SSACTPOL_Msk | QSPI_SSCTL_SS_Msk)) + +/** + * @brief Set QSPIx_SS pin to low state. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Disable automatic slave selection function and set QSPIx_SS pin to low state. + * \hideinitializer + */ +#define QSPI_SET_SS_LOW(qspi) ((qspi)->SSCTL = ((qspi)->SSCTL & (~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SSACTPOL_Msk))) | QSPI_SSCTL_SS_Msk) + +/** + * @brief Enable Byte Reorder function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (QSPI_CTL[7:4]). + * \hideinitializer + */ +#define QSPI_ENABLE_BYTE_REORDER(qspi) ((qspi)->CTL |= QSPI_CTL_REORDER_Msk) + +/** + * @brief Disable Byte Reorder function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear REORDER bit field of QSPI_CTL register to disable Byte Reorder function. + * \hideinitializer + */ +#define QSPI_DISABLE_BYTE_REORDER(qspi) ((qspi)->CTL &= ~QSPI_CTL_REORDER_Msk) + +/** + * @brief Set the length of suspend interval. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15. + * @return None. + * @details Set the length of suspend interval according to u32SuspCycle. + * The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one QSPI bus clock cycle). + * \hideinitializer + */ +#define QSPI_SET_SUSPEND_CYCLE(qspi, u32SuspCycle) ((qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << QSPI_CTL_SUSPITV_Pos)) + +/** + * @brief Set the QSPI transfer sequence with LSB first. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set LSB bit of QSPI_CTL register to set the QSPI transfer sequence with LSB first. + * \hideinitializer + */ +#define QSPI_SET_LSB_FIRST(qspi) ((qspi)->CTL |= QSPI_CTL_LSB_Msk) + +/** + * @brief Set the QSPI transfer sequence with MSB first. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear LSB bit of QSPI_CTL register to set the QSPI transfer sequence with MSB first. + * \hideinitializer + */ +#define QSPI_SET_MSB_FIRST(qspi) ((qspi)->CTL &= ~QSPI_CTL_LSB_Msk) + +/** + * @brief Set the data width of a QSPI transaction. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Width The bit width of one transaction. + * @return None. + * @details The data width can be 8 ~ 32 bits. + * \hideinitializer + */ +#define QSPI_SET_DATA_WIDTH(qspi, u32Width) ((qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DWIDTH_Msk) | (((u32Width)&0x1F) << QSPI_CTL_DWIDTH_Pos)) + +/** + * @brief Get the QSPI busy state. + * @param[in] qspi The pointer of the specified QSPI module. + * @retval 0 QSPI controller is not busy. + * @retval 1 QSPI controller is busy. + * @details This macro will return the busy state of QSPI controller. + * \hideinitializer + */ +#define QSPI_IS_BUSY(qspi) ( ((qspi)->STATUS & QSPI_STATUS_BUSY_Msk)>>QSPI_STATUS_BUSY_Pos ) + +/** + * @brief Enable QSPI controller. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set QSPIEN (QSPI_CTL[0]) to enable QSPI controller. + * \hideinitializer + */ +#define QSPI_ENABLE(qspi) ((qspi)->CTL |= QSPI_CTL_QSPIEN_Msk) + +/** + * @brief Disable QSPI controller. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear QSPIEN (QSPI_CTL[0]) to disable QSPI controller. + * \hideinitializer + */ +#define QSPI_DISABLE(qspi) ((qspi)->CTL &= ~QSPI_CTL_QSPIEN_Msk) + +/** + * @brief Disable 2-bit Transfer mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear TWOBIT bit of QSPI_CTL register to disable 2-bit Transfer mode. + */ +#define QSPI_DISABLE_2BIT_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_TWOBIT_Msk ) + +/** + * @brief Enable 2-bit Transfer mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set TWOBIT bit of QSPI_CTL register to enable 2-bit Transfer mode. + */ +#define QSPI_ENABLE_2BIT_MODE(qspi) ( (qspi)->CTL |= QSPI_CTL_TWOBIT_Msk ) + +/** + * @brief Disable Slave 3-wire mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear SLV3WIRE bit of QSPI_SSCTL register to disable Slave 3-wire mode. + */ +#define QSPI_DISABLE_3WIRE_MODE(qspi) ( (qspi)->SSCTL &= ~QSPI_SSCTL_SLV3WIRE_Msk ) + +/** + * @brief Enable Slave 3-wire mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set SLV3WIRE bit of QSPI_SSCTL register to enable Slave 3-wire mode. + */ +#define QSPI_ENABLE_3WIRE_MODE(qspi) ( (qspi)->SSCTL |= QSPI_SSCTL_SLV3WIRE_Msk ) + +/** + * @brief Disable QSPI Dual IO function. + * @param[in] qspi is the base address of QSPI module. + * @return none + * \hideinitializer + */ +#define QSPI_DISABLE_DUAL_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_DUALIOEN_Msk ) + +/** + * @brief Enable Dual IO function and set QSPI Dual IO direction to input. + * @param[in] qspi is the base address of QSPI module. + * @return none + * \hideinitializer + */ +#define QSPI_ENABLE_DUAL_INPUT_MODE(qspi) ( (qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DATDIR_Msk) | QSPI_CTL_DUALIOEN_Msk ) + +/** + * @brief Enable Dual IO function and set QSPI Dual IO direction to output. + * @param[in] qspi is the base address of QSPI module. + * @return none + * \hideinitializer + */ +#define QSPI_ENABLE_DUAL_OUTPUT_MODE(qspi) ( (qspi)->CTL |= QSPI_CTL_DATDIR_Msk | QSPI_CTL_DUALIOEN_Msk ) + +/** + * @brief Disable QSPI Dual IO function. + * @param[in] qspi is the base address of QSPI module. + * @return none + * \hideinitializer + */ +#define QSPI_DISABLE_QUAD_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_QUADIOEN_Msk ) + +/** + * @brief Set QSPI Quad IO direction to input. + * @param[in] qspi is the base address of QSPI module. + * @return none + * \hideinitializer + */ +#define QSPI_ENABLE_QUAD_INPUT_MODE(qspi) ( (qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DATDIR_Msk) | QSPI_CTL_QUADIOEN_Msk ) + +/** + * @brief Set QSPI Quad IO direction to output. + * @param[in] qspi is the base address of QSPI module. + * @return none + * \hideinitializer + */ +#define QSPI_ENABLE_QUAD_OUTPUT_MODE(qspi) ( (qspi)->CTL |= QSPI_CTL_DATDIR_Msk | QSPI_CTL_QUADIOEN_Msk ) + + + + +/* Function prototype declaration */ +uint32_t QSPI_Open(QSPI_T *qspi, uint32_t u32MasterSlave, uint32_t u32QSPIMode, uint32_t u32DataWidth, uint32_t u32BusClock); +void QSPI_Close(QSPI_T *qspi); +void QSPI_ClearRxFIFO(QSPI_T *qspi); +void QSPI_ClearTxFIFO(QSPI_T *qspi); +void QSPI_DisableAutoSS(QSPI_T *qspi); +void QSPI_EnableAutoSS(QSPI_T *qspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel); +uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock); +void QSPI_SetFIFO(QSPI_T *qspi, uint32_t u32TxThreshold, uint32_t u32RxThreshold); +uint32_t QSPI_GetBusClock(QSPI_T *qspi); +void QSPI_EnableInt(QSPI_T *qspi, uint32_t u32Mask); +void QSPI_DisableInt(QSPI_T *qspi, uint32_t u32Mask); +uint32_t QSPI_GetIntFlag(QSPI_T *qspi, uint32_t u32Mask); +void QSPI_ClearIntFlag(QSPI_T *qspi, uint32_t u32Mask); +uint32_t QSPI_GetStatus(QSPI_T *qspi, uint32_t u32Mask); + + +/*@}*/ /* end of group QSPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group QSPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __QSPI_H__ */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_rtc.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_rtc.h new file mode 100644 index 00000000000..74b2a5fd877 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_rtc.h @@ -0,0 +1,377 @@ +/**************************************************************************//** + * @file rtc.h + * @version V1.00 + * @brief M251 series RTC driver header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __RTC_H__ +#define __RTC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup RTC_Driver RTC Driver + @{ +*/ + +/** @addtogroup RTC_EXPORTED_CONSTANTS RTC Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Initial Keyword Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_INIT_KEY 0xA5EB1357UL /*!< RTC Initiation Key to make RTC leaving reset state \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Frequency Compensation Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_INTEGER_32752 (0x0ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32752HZ \hideinitializer */ +#define RTC_INTEGER_32753 (0x1ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32753HZ \hideinitializer */ +#define RTC_INTEGER_32754 (0x2ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32754HZ \hideinitializer */ +#define RTC_INTEGER_32755 (0x3ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32755HZ \hideinitializer */ +#define RTC_INTEGER_32756 (0x4ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32756HZ \hideinitializer */ +#define RTC_INTEGER_32757 (0x5ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32757HZ \hideinitializer */ +#define RTC_INTEGER_32758 (0x6ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32758HZ \hideinitializer */ +#define RTC_INTEGER_32759 (0x7ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32759HZ \hideinitializer */ +#define RTC_INTEGER_32760 (0x8ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32760HZ \hideinitializer */ +#define RTC_INTEGER_32761 (0x9ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32761HZ \hideinitializer */ +#define RTC_INTEGER_32762 (0xaul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32762HZ \hideinitializer */ +#define RTC_INTEGER_32763 (0xbul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32763HZ \hideinitializer */ +#define RTC_INTEGER_32764 (0xcul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32764HZ \hideinitializer */ +#define RTC_INTEGER_32765 (0xdul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32765HZ \hideinitializer */ +#define RTC_INTEGER_32766 (0xeul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32766HZ \hideinitializer */ +#define RTC_INTEGER_32767 (0xful << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32767HZ \hideinitializer */ +#define RTC_INTEGER_32768 (0x10ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32768HZ \hideinitializer */ +#define RTC_INTEGER_32769 (0x11ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32769HZ \hideinitializer */ +#define RTC_INTEGER_32770 (0x12ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32770HZ \hideinitializer */ +#define RTC_INTEGER_32771 (0x13ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32771HZ \hideinitializer */ +#define RTC_INTEGER_32772 (0x14ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32772HZ \hideinitializer */ +#define RTC_INTEGER_32773 (0x15ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32773HZ \hideinitializer */ +#define RTC_INTEGER_32774 (0x16ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32774HZ \hideinitializer */ +#define RTC_INTEGER_32775 (0x17ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32775HZ \hideinitializer */ +#define RTC_INTEGER_32776 (0x18ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32776HZ \hideinitializer */ +#define RTC_INTEGER_32777 (0x19ul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32777HZ \hideinitializer */ +#define RTC_INTEGER_32778 (0x1aul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32778HZ \hideinitializer */ +#define RTC_INTEGER_32779 (0x1bul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32779HZ \hideinitializer */ +#define RTC_INTEGER_32780 (0x1cul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32780HZ \hideinitializer */ +#define RTC_INTEGER_32781 (0x1dul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32781HZ \hideinitializer */ +#define RTC_INTEGER_32782 (0x1eul << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32782HZ \hideinitializer */ +#define RTC_INTEGER_32783 (0x1ful << RTC_FREQADJ_INTEGER_Pos ) /*!< RTC Frequency is 32783HZ \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Time Attribute Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_CLOCK_12 0UL /*!< RTC as 12-hour time scale with AM and PM indication \hideinitializer */ +#define RTC_CLOCK_24 1UL /*!< RTC as 24-hour time scale \hideinitializer */ +#define RTC_AM 1UL /*!< RTC as AM indication \hideinitializer */ +#define RTC_PM 2UL /*!< RTC as PM indication \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Tick Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_TICK_1_SEC 0x0UL /*!< RTC time tick period is 1 second \hideinitializer */ +#define RTC_TICK_1_2_SEC 0x1UL /*!< RTC time tick period is 1/2 second \hideinitializer */ +#define RTC_TICK_1_4_SEC 0x2UL /*!< RTC time tick period is 1/4 second \hideinitializer */ +#define RTC_TICK_1_8_SEC 0x3UL /*!< RTC time tick period is 1/8 second \hideinitializer */ +#define RTC_TICK_1_16_SEC 0x4UL /*!< RTC time tick period is 1/16 second \hideinitializer */ +#define RTC_TICK_1_32_SEC 0x5UL /*!< RTC time tick period is 1/32 second \hideinitializer */ +#define RTC_TICK_1_64_SEC 0x6UL /*!< RTC time tick period is 1/64 second \hideinitializer */ +#define RTC_TICK_1_128_SEC 0x7UL /*!< RTC time tick period is 1/128 second \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Day of Week Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_SUNDAY 0x0UL /*!< Day of the Week is Sunday \hideinitializer */ +#define RTC_MONDAY 0x1UL /*!< Day of the Week is Monday \hideinitializer */ +#define RTC_TUESDAY 0x2UL /*!< Day of the Week is Tuesday \hideinitializer */ +#define RTC_WEDNESDAY 0x3UL /*!< Day of the Week is Wednesday \hideinitializer */ +#define RTC_THURSDAY 0x4UL /*!< Day of the Week is Thursday \hideinitializer */ +#define RTC_FRIDAY 0x5UL /*!< Day of the Week is Friday \hideinitializer */ +#define RTC_SATURDAY 0x6UL /*!< Day of the Week is Saturday \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Miscellaneous Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_WAIT_COUNT 0xFFFFFFFFUL /*!< Initial Time-out Value \hideinitializer */ +#define RTC_YEAR2000 2000UL /*!< RTC Reference for compute year data \hideinitializer */ +#define RTC_FCR_REFERENCE 32761UL /*!< RTC Reference for frequency compensation \hideinitializer */ + + +#define RTC_TAMPER0_SELECT (0x1ul << 0) /*!< Select Tamper 0 \hideinitializer */ +#define MAX_TAMPER_PIN_NUM 1ul /*!< Tamper Pin number \hideinitializer */ + +#define RTC_TAMPER_HIGH_LEVEL_DETECT 0ul /*!< Tamper pin detect voltage level is High \hideinitializer */ +#define RTC_TAMPER_LOW_LEVEL_DETECT 1ul /*!< Tamper pin detect voltage level is low \hideinitializer */ + +#define RTC_TAMPER_DEBOUNCE_ENABLE 1ul /*!< Enable RTC tamper pin de-bounce function \hideinitializer */ +#define RTC_TAMPER_DEBOUNCE_DISABLE 0ul /*!< Disable RTC tamper pin de-bounce function \hideinitializer */ + + +/*@}*/ /* end of group RTC_EXPORTED_CONSTANTS */ + + +/** @addtogroup RTC_EXPORTED_STRUCTS RTC Exported Structs + @{ +*/ +/** + * @details RTC define Time Data Struct + */ +typedef struct +{ + uint32_t u32Year; /*!< Year value */ + uint32_t u32Month; /*!< Month value */ + uint32_t u32Day; /*!< Day value */ + uint32_t u32DayOfWeek; /*!< Day of week value */ + uint32_t u32Hour; /*!< Hour value */ + uint32_t u32Minute; /*!< Minute value */ + uint32_t u32Second; /*!< Second value */ + uint32_t u32TimeScale; /*!< 12-Hour, 24-Hour */ + uint32_t u32AmPm; /*!< Only Time Scale select 12-hr used */ +} S_RTC_TIME_DATA_T; + +/*@}*/ /* end of group RTC_EXPORTED_STRUCTS */ + + +/** @addtogroup RTC_EXPORTED_FUNCTIONS RTC Exported Functions + @{ +*/ + +/** + * @brief Indicate is Leap Year or not + * + * @param None + * + * @retval 0 This year is not a leap year + * @retval 1 This year is a leap year + * + * @details According to current date, return this year is leap year or not. + * \hideinitializer + */ +#define RTC_IS_LEAP_YEAR() (RTC->LEAPYEAR & RTC_LEAPYEAR_LEAPYEAR_Msk ? 1:0) + +/** + * @brief Clear RTC Alarm Interrupt Flag + * + * @param None + * + * @return None + * + * @details This macro is used to clear RTC alarm interrupt flag. + * \hideinitializer + */ +#define RTC_CLEAR_ALARM_INT_FLAG() (RTC->INTSTS = RTC_INTSTS_ALMIF_Msk) + +/** + * @brief Clear RTC Tick Interrupt Flag + * + * @param None + * + * @return None + * + * @details This macro is used to clear RTC tick interrupt flag. + * \hideinitializer + */ +#define RTC_CLEAR_TICK_INT_FLAG() (RTC->INTSTS = RTC_INTSTS_TICKIF_Msk) + +/** + * @brief Clear RTC Tamper Interrupt Flag + * + * @param u32TamperFlag Tamper interrupt flag. It consists of: \n + * - \ref RTC_INTSTS_TAMP0IF_Msk + * + * @return None + * + * @details This macro is used to clear RTC snooper pin interrupt flag. + * \hideinitializer + */ +#define RTC_CLEAR_TAMPER_INT_FLAG(u32TamperFlag) (RTC->INTSTS = (u32TamperFlag)) + +/** + * @brief Get RTC Alarm Interrupt Flag + * + * @param None + * + * @retval 0 RTC alarm interrupt did not occur + * @retval 1 RTC alarm interrupt occurred + * + * @details This macro indicates RTC alarm interrupt occurred or not. + * \hideinitializer + */ +#define RTC_GET_ALARM_INT_FLAG() ((RTC->INTSTS & RTC_INTSTS_ALMIF_Msk)? 1:0) + +/** + * @brief Get RTC Time Tick Interrupt Flag + * + * @param None + * + * @retval 0 RTC time tick interrupt did not occur + * @retval 1 RTC time tick interrupt occurred + * + * @details This macro indicates RTC time tick interrupt occurred or not. + * \hideinitializer + */ +#define RTC_GET_TICK_INT_FLAG() ((RTC->INTSTS & RTC_INTSTS_TICKIF_Msk)? 1:0) + +/** + * @brief Get RTC Tamper Interrupt Flag + * + * @param None + * + * @retval 0 RTC snooper pin interrupt did not occur + * @retval 1 RTC snooper pin interrupt occurred + * + * @details This macro indicates RTC snooper pin interrupt occurred or not. + * \hideinitializer + */ +#define RTC_GET_TAMPER_INT_FLAG() ((RTC->INTSTS & (0x0100))? 1:0) + +/** + * @brief Get RTC TAMPER Interrupt Status + * + * @param None + * + * @retval RTC_INTSTS_TAMP0IF_Msk Tamper 0 interrupt flag is generated + * + * @details This macro indicates RTC snooper pin interrupt occurred or not. + * \hideinitializer + */ +#define RTC_GET_TAMPER_INT_STATUS() ((RTC->INTSTS & (0x0100))) + +/** + * @brief Enable RTC Tick Wake-up Function + * + * @param None + * + * @return None + * + * @details This macro is used to enable RTC tick interrupt wake-up function. + * \hideinitializer + */ +#define RTC_ENABLE_TICK_WAKEUP() ((RTC->INTEN |= RTC_INTEN_TICKIEN_Msk)) + +/** + * @brief Disable RTC Tick Wake-up Function + * + * @param None + * + * @return None + * + * @details This macro is used to disable RTC tick interrupt wake-up function. + * \hideinitializer + */ +#define RTC_DISABLE_TICK_WAKEUP() ((RTC->INTEN &= ~RTC_INTEN_TICKIEN_Msk)); + +/** + * @brief Enable RTC Alarm Wake-up Function + * + * @param None + * + * @return None + * + * @details This macro is used to enable RTC Alarm interrupt wake-up function. + * \hideinitializer + */ +#define RTC_ENABLE_ALARM_WAKEUP() ((RTC->INTEN |= RTC_INTEN_ALMIEN_Msk)) + +/** + * @brief Disable RTC Alarm Wake-up Function + * + * @param None + * + * @return None + * + * @details This macro is used to disable RTC Alarm interrupt wake-up function. + * \hideinitializer + */ +#define RTC_DISABLE_ALARM_WAKEUP() ((RTC->INTEN &= ~RTC_INTEN_ALMIEN_Msk)); + +/** + * @brief Read Spare Register + * + * @param[in] u32RegNum The spare register number, 0~4. + * + * @return Spare register content + * + * @details Read the specify spare register content. + * @note The returned value is valid only when SPRRWEN(SPRCTL[2] RTC Spare Function control register) bit is set. \n + * And its controlled by RTC Spare Function control register(RTC_SPRCTL). + * \hideinitializer + */ +#define RTC_READ_SPARE_REGISTER(u32RegNum) (RTC->SPR[(u32RegNum)]) + +/** + * @brief Write Spare Register + * + * @param[in] u32RegNum The spare register number, 0~4. + * @param[in] u32RegValue The spare register value. + * + * @return None + * + * @details Write specify data to spare register. + * @note This macro is effect only when SPRRWEN(SPRCTL[2] RTC Spare Function control register) bit is set. \n + * And its controlled by RTC Spare Function control register(RTC_SPRCTL). + * \hideinitializer + */ +#define RTC_WRITE_SPARE_REGISTER(u32RegNum, u32RegValue) (RTC->SPR[(u32RegNum)] = (u32RegValue)) + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +static __INLINE void RTC_WaitAccessEnable(void); + +/** + * @brief Wait RTC Access Enable + * + * @param None + * + * @return None + * + * @details This function is used to enable the maximum RTC read/write accessible time. + */ +static __INLINE void RTC_WaitAccessEnable(void) +{ + /* Dummy for M251/M252 */ +} + +void RTC_Open(S_RTC_TIME_DATA_T *psPt); +void RTC_Close(void); +void RTC_32KCalibration(int32_t i32FrequencyX10000); +void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *psPt); +void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *psPt); +void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *psPt); +void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *psPt); +void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek); +void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm); +void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day); +void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm); +void RTC_SetAlarmDateMask(uint8_t u8IsTenYMsk, uint8_t u8IsYMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenDMsk, uint8_t u8IsDMsk); +void RTC_SetAlarmTimeMask(uint8_t u8IsTenHMsk, uint8_t u8IsHMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenSMsk, uint8_t u8IsSMsk); +uint32_t RTC_GetDayOfWeek(void); +void RTC_SetTickPeriod(uint32_t u32TickSelection); +void RTC_EnableInt(uint32_t u32IntFlagMask); +void RTC_DisableInt(uint32_t u32IntFlagMask); +void RTC_EnableSpareAccess(void); +void RTC_DisableSpareRegister(void); +void RTC_StaticTamperEnable(uint32_t u32TamperSelect, uint32_t u32DetecLevel, uint32_t u32DebounceEn); +void RTC_StaticTamperDisable(uint32_t u32TamperSelect); + + +/*@}*/ /* end of group RTC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group RTC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __RTC_H__ */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_sc.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_sc.h new file mode 100644 index 00000000000..7d664a8bda0 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_sc.h @@ -0,0 +1,383 @@ +/**************************************************************************//** + * @file sc.h + * @version V3.00 + * @brief Smart Card(SC) driver header file + * + * @note + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SC_H__ +#define __SC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SC_Driver SC Driver + @{ +*/ + +/** @addtogroup SC_EXPORTED_CONSTANTS SC Exported Constants + @{ +*/ +#define SC_INTERFACE_NUM (1ul) /*!< Smartcard interface numbers \hideinitializer */ +#define SC_PIN_STATE_HIGH (1ul) /*!< Smartcard pin status high \hideinitializer */ +#define SC_PIN_STATE_LOW (0ul) /*!< Smartcard pin status low \hideinitializer */ +#define SC_PIN_STATE_IGNORE (0xFFFFFFFFul) /*!< Ignore pin status \hideinitializer */ +#define SC_CLK_ON (1ul) /*!< Smartcard clock on \hideinitializer */ +#define SC_CLK_OFF (0ul) /*!< Smartcard clock off \hideinitializer */ + +#define SC_TMR_MODE_0 (0ul << SC_TMRCTL0_OPMODE_Pos) /*!INTEN |= (u32Mask)) + +/** + * @brief Disable Smartcard Interrupt + * + * @param[in] psSC The pointer of smartcard module. + * @param[in] u32Mask Interrupt mask to be disabled. A combination of + * - \ref SC_INTEN_ACERRIEN_Msk + * - \ref SC_INTEN_RXTOIEN_Msk + * - \ref SC_INTEN_INITIEN_Msk + * - \ref SC_INTEN_CDIEN_Msk + * - \ref SC_INTEN_BGTIEN_Msk + * - \ref SC_INTEN_TMR2IEN_Msk + * - \ref SC_INTEN_TMR1IEN_Msk + * - \ref SC_INTEN_TMR0IEN_Msk + * - \ref SC_INTEN_TERRIEN_Msk + * - \ref SC_INTEN_TBEIEN_Msk + * - \ref SC_INTEN_RDAIEN_Msk + * + * @return None + * + * @details The macro is used to disable Auto-convention error interrupt, Receiver buffer time-out interrupt, Initial end interrupt, + * Card detect interrupt, Block guard time interrupt, Timer2 interrupt, Timer1 interrupt, Timer0 interrupt, + * Transfer error interrupt, Transmit buffer empty interrupt or Receive data reach trigger level interrupt. + * \hideinitializer + */ +#define SC_DISABLE_INT(psSC, u32Mask) ((psSC)->INTEN &= ~(u32Mask)) + +/** + * @brief Check Smartcard Interrupt Status Flag + * + * @param[in] psSC The pointer of smartcard module. + * @param[in] u32Mask Interrupt mask to be disabled. A combination of + * - \ref SC_INTSTS_ACERRIF_Msk + * - \ref SC_INTSTS_RXTOIF_Msk + * - \ref SC_INTSTS_INITIF_Msk + * - \ref SC_INTSTS_CDIF_Msk + * - \ref SC_INTSTS_BGTIF_Msk + * - \ref SC_INTSTS_TMR2IF_Msk + * - \ref SC_INTSTS_TMR1IF_Msk + * - \ref SC_INTSTS_TMR0IF_Msk + * - \ref SC_INTSTS_TERRIF_Msk + * - \ref SC_INTSTS_TBEIF_Msk + * - \ref SC_INTSTS_RDAIF_Msk + * + * @return None + * + * @details The macro is used to check Auto-convention error interrupt, Receiver buffer time-out interrupt, Initial end interrupt, + * Card detect interrupt, Block guard time interrupt, Timer2 interrupt, Timer1 interrupt, Timer0 interrupt, + * Transfer error interrupt, Transmit buffer empty interrupt or Receive data reach trigger level interrupt. + * \hideinitializer + */ +#define SC_CHECK_INTSTS(psSC, u32Mask) ((psSC)->INTSTS &= u32Mask) + +/** + * @brief Clear Smartcard Interrupt Status Flag + * + * @param[in] psSC The pointer of smartcard module. + * @param[in] u32Mask Interrupt mask to be disabled. A combination of + * - \ref SC_INTSTS_ACERRIF_Msk + * - \ref SC_INTSTS_RXTOIF_Msk + * - \ref SC_INTSTS_INITIF_Msk + * - \ref SC_INTSTS_CDIF_Msk + * - \ref SC_INTSTS_BGTIF_Msk + * - \ref SC_INTSTS_TMR2IF_Msk + * - \ref SC_INTSTS_TMR1IF_Msk + * - \ref SC_INTSTS_TMR0IF_Msk + * - \ref SC_INTSTS_TERRIF_Msk + * - \ref SC_INTSTS_TBEIF_Msk + * - \ref SC_INTSTS_RDAIF_Msk + * + * @return None + * + * @details The macro is used to check Auto-convention error interrupt, Receiver buffer time-out interrupt, Initial end interrupt, + * Card detect interrupt, Block guard time interrupt, Timer2 interrupt, Timer1 interrupt, Timer0 interrupt, + * Transfer error interrupt, Transmit buffer empty interrupt or Receive data reach trigger level interrupt. + * \hideinitializer + */ +#define SC_CLEAR_INTSTS(psSC, u32Mask) ((psSC)->INTSTS = u32Mask) + +/** + * @brief Set ETU Divider + * + * @param[in] psSC The pointer of smartcard module. + * @param[in] u32Mask ETU divider value + * + * @return None + * + * @details The macro is used to give ETU divider. Its value must be given more than 4. + * \hideinitializer + */ +#define SC_SET_ETUDIV(psSC, u32Mask) ((psSC)->ETUCTL = (((psSC)->ETUCTL&(~SC_ETUCTL_ETURDIV_Msk)) | (u32Mask <PINCTL & SC_PINCTL_SYNC_Msk);\ + if(u32State)\ + (psSC)->PINCTL |= SC_PINCTL_PWREN_Msk;\ + else\ + (psSC)->PINCTL &= ~SC_PINCTL_PWREN_Msk;\ + }while(0) + + +/** + * @brief Set Smartcard Clock Status + * + * @param[in] psSC The pointer of smartcard module. + * @param[in] u32OnOff Set clock on or off for selected smartcard module, valid values are: + * - \ref SC_CLK_ON + * - \ref SC_CLK_OFF + * + * @return None + * + * @details User can set CLKKEEP (SC_PINCTL[6]) to decide SC_CLK pin always keeps free running or not. + * \hideinitializer + */ +#define SC_SET_CLK_PIN(psSC, u32OnOff)\ + do {\ + while((psSC)->PINCTL & SC_PINCTL_SYNC_Msk);\ + if(u32OnOff)\ + (psSC)->PINCTL |= SC_PINCTL_CLKKEEP_Msk;\ + else\ + (psSC)->PINCTL &= ~(SC_PINCTL_CLKKEEP_Msk);\ + }while(0) + +/** + * @brief Set Smartcard I/O Pin State + * + * @param[in] psSC The pointer of smartcard module. + * @param[in] u32State Set pin state of I/O pin, valid parameters are: + * - \ref SC_PIN_STATE_HIGH + * - \ref SC_PIN_STATE_LOW + * + * @return None + * + * @details User can set SCDATA (SC_PINCTL[9]) to decide SC_DATA pin to high or low. + * \hideinitializer + */ +#define SC_SET_IO_PIN(psSC, u32State)\ + do {\ + while((psSC)->PINCTL & SC_PINCTL_SYNC_Msk);\ + if(u32State)\ + (psSC)->PINCTL |= SC_PINCTL_SCDATA_Msk;\ + else\ + (psSC)->PINCTL &= ~SC_PINCTL_SCDATA_Msk;\ + }while(0) + +/** + * @brief Set Smartcard Reset Pin State + * + * @param[in] psSC The pointer of smartcard module. + * @param[in] u32State Set pin state of reset pin, valid parameters are: + * - \ref SC_PIN_STATE_HIGH + * - \ref SC_PIN_STATE_LOW + * + * @return None + * + * @details User can set SCRST (SC_PINCTL[1]) to decide SC_RST pin to high or low. + * \hideinitializer + */ +#define SC_SET_RST_PIN(psSC, u32State)\ + do {\ + while((psSC)->PINCTL & SC_PINCTL_SYNC_Msk);\ + if(u32State)\ + (psSC)->PINCTL |= SC_PINCTL_RSTEN_Msk;\ + else\ + (psSC)->PINCTL &= ~SC_PINCTL_RSTEN_Msk;\ + }while(0) + +/** + * @brief Read One Byte Data + * + * @param[in] psSC The pointer of smartcard module. + * + * @return One byte read from receive FIFO + * + * @details By reading DAT register, the SC will return an 8-bit received data. + * \hideinitializer + */ +#define SC_READ(psSC) ((char)((psSC)->DAT)) + +/** + * @brief Write One Byte Data + * + * @param[in] psSC The pointer of smartcard module. + * @param[in] u8Data Data to write to transmit FIFO. + * + * @return None + * + * @details By writing data to DAT register, the SC will send out an 8-bit data. + * \hideinitializer + */ +#define SC_WRITE(psSC, u8Data) ((psSC)->DAT = (u8Data)) + +/** + * @brief Set Smartcard Stop Bit Length + * + * @param[in] psSC The pointer of smartcard module. + * @param[in] u32Len Stop bit length, ether 1 or 2. + * + * @return None + * + * @details Stop bit length must be 1 for T = 1 protocol and 2 for T = 0 protocol. + * \hideinitializer + */ +#define SC_SET_STOP_BIT_LEN(psSC, u32Len) ((psSC)->CTL = ((psSC)->CTL & ~SC_CTL_NSB_Msk) | (((u32Len) == 1)? SC_CTL_NSB_Msk : 0)) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* static inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void SC_SetTxRetry(SC_T *psSC, uint32_t u32Count); +__STATIC_INLINE void SC_SetRxRetry(SC_T *psSC, uint32_t u32Count); + + +/** + * @brief Set Tx Error Retry Count + * + * @param[in] psSC The pointer of smartcard module. + * @param[in] u32Count The number of Tx error retry count, between 0~8 and 0 means disable Tx error retry function. + * + * @return None + * + * @details This function is used to enable/disable transmitter retry function when parity error has occurred, and set error retry count. + * @note Set error retry count to 0 will disable Tx error retry function. + */ +__STATIC_INLINE void SC_SetTxRetry(SC_T *psSC, uint32_t u32Count) +{ + while ((psSC)->CTL & SC_CTL_SYNC_Msk) {} + + /* Retry count must set while enable bit disabled, so disable it first */ + (psSC)->CTL &= ~(SC_CTL_TXRTY_Msk | SC_CTL_TXRTYEN_Msk); + + if ((u32Count) != 0UL) + { + while ((psSC)->CTL & SC_CTL_SYNC_Msk) {} + + (psSC)->CTL |= (((u32Count) - 1UL) << SC_CTL_TXRTY_Pos) | SC_CTL_TXRTYEN_Msk; + } +} + +/** + * @brief Set Rx Error Retry Count + * + * @param[in] psSC The pointer of smartcard module. + * @param[in] u32Count The number of Rx error retry count, between 0~8 and 0 means disable Rx error retry function. + * + * @return None + * + * @details This function is used to enable/disable receiver retry function when parity error has occurred, and set error retry count. + * @note Set error retry count to 0 will disable Rx error retry function. + */ +__STATIC_INLINE void SC_SetRxRetry(SC_T *psSC, uint32_t u32Count) +{ + while ((psSC)->CTL & SC_CTL_SYNC_Msk) {} + + /* Retry count must set while enable bit disabled, so disable it first */ + (psSC)->CTL &= ~(SC_CTL_RXRTY_Msk | SC_CTL_RXRTYEN_Msk); + + if ((u32Count) != 0UL) + { + while ((psSC)->CTL & SC_CTL_SYNC_Msk) {} + + (psSC)->CTL |= (((u32Count) - 1UL) << SC_CTL_RXRTY_Pos) | SC_CTL_RXRTYEN_Msk; + } +} + + +uint32_t SC_IsCardInserted(SC_T *psSC); +void SC_ClearFIFO(SC_T *psSC); +void SC_Close(SC_T *psSC); +void SC_Open(SC_T *psSC, uint32_t u32CardDet, uint32_t u32PWR); +void SC_ResetReader(SC_T *psSC); +void SC_SetBlockGuardTime(SC_T *psSC, uint32_t u32BGT); +void SC_SetCharGuardTime(SC_T *psSC, uint32_t u32CGT); +void SC_StopAllTimer(SC_T *psSC); +void SC_StartTimer(SC_T *psSC, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount); +void SC_StopTimer(SC_T *psSC, uint32_t u32TimerNum); +uint32_t SC_GetInterfaceClock(SC_T *psSC); +/*@}*/ /* end of group SC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SC_H__ */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_scuart.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_scuart.h new file mode 100644 index 00000000000..bff24a7e3c7 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_scuart.h @@ -0,0 +1,266 @@ +/**************************************************************************//** + * @file scuart.h + * @version V1.00 + * @brief M251 Smartcard UART mode (SCUART) driver header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SCUART_H__ +#define __SCUART_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SCUART_Driver SCUART Driver + @{ +*/ + +/** @addtogroup SCUART_EXPORTED_CONSTANTS SCUART Exported Constants + @{ +*/ +#define SCUART_CHAR_LEN_5 (0x3ul << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 5 bits \hideinitializer */ +#define SCUART_CHAR_LEN_6 (0x2ul << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 6 bits \hideinitializer */ +#define SCUART_CHAR_LEN_7 (0x1ul << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 7 bits \hideinitializer */ +#define SCUART_CHAR_LEN_8 (0UL) /*!< Set SCUART word length to 8 bits \hideinitializer */ + +#define SCUART_PARITY_NONE (SC_UARTCTL_PBOFF_Msk) /*!< Set SCUART transfer with no parity \hideinitializer */ +#define SCUART_PARITY_ODD (SC_UARTCTL_OPE_Msk) /*!< Set SCUART transfer with odd parity \hideinitializer */ +#define SCUART_PARITY_EVEN (0UL) /*!< Set SCUART transfer with even parity \hideinitializer */ + +#define SCUART_STOP_BIT_1 (SC_CTL_NSB_Msk) /*!< Set SCUART transfer with one stop bit \hideinitializer */ +#define SCUART_STOP_BIT_2 (0UL) /*!< Set SCUART transfer with two stop bits \hideinitializer */ + + +/*@}*/ /* end of group SCUART_EXPORTED_CONSTANTS */ + + +/** @addtogroup SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions + @{ +*/ + +/* TX Macros */ +/** + * @brief Write Data to Tx data register + * @param[in] psSC The base address of smartcard module. + * @param[in] u8Data Data byte to transmit + * @return None + * \hideinitializer + */ +#define SCUART_WRITE(psSC, u8Data) ((psSC)->DAT = (u8Data)) + +/** + * @brief Get TX FIFO empty flag status from register + * @param[in] psSC The base address of smartcard module + * @return Transmit FIFO empty status + * @retval 0 Transmit FIFO is not empty + * @retval SC_STATUS_TXEMPTY_Msk Transmit FIFO is empty + * \hideinitializer + */ +#define SCUART_GET_TX_EMPTY(psSC) ((psSC)->STATUS & SC_STATUS_TXEMPTY_Msk) + +/** + * @brief Get TX FIFO full flag status from register + * @param[in] psSC The base address of smartcard module + * @return Transmit FIFO full status + * @retval 0 Transmit FIFO is not full + * @retval SC_STATUS_TXFULL_Msk Transmit FIFO is full + * \hideinitializer + */ +#define SCUART_GET_TX_FULL(psSC) ((psSC)->STATUS & SC_STATUS_TXFULL_Msk) + +/** + * @brief Wait specified smartcard port transmission complete + * @param[in] psSC The base address of smartcard module + * @return None + * @note This Macro blocks until transmit complete. + * \hideinitializer + */ +#define SCUART_WAIT_TX_EMPTY(psSC) while((psSC)->STATUS & SC_STATUS_TXACT_Msk) + +/** + * @brief Check specified smartcard port transmit FIFO is full or not + * @param[in] psSC The base address of smartcard module + * @return Transmit FIFO full status + * @retval 0 Transmit FIFO is not full + * @retval 1 Transmit FIFO is full + * \hideinitializer + */ +#define SCUART_IS_TX_FULL(psSC) ((psSC)->STATUS & SC_STATUS_TXFULL_Msk ? 1 : 0) + +/** + * @brief Check specified smartcard port transmission is over + * @param[in] psSC The base address of smartcard module + * @return Transmit complete status + * @retval 0 Transmit is not complete + * @retval 1 Transmit complete + * \hideinitializer + */ +#define SCUART_IS_TX_EMPTY(psSC) ((psSC)->STATUS & SC_STATUS_TXACT_Msk ? 0 : 1) + +/** + * @brief Check specified Smartcard port Transmission Status + * @param[in] psSC The pointer of smartcard module. + * @retval 0 Transmit is completed + * @retval 1 Transmit is active + * @details TXACT (SC_STATUS[31]) is set by hardware when Tx transfer is in active and the STOP bit of the last byte has been transmitted. + * \hideinitializer + */ +#define SCUART_IS_TX_ACTIVE(psSC) (((psSC)->STATUS & SC_STATUS_TXACT_Msk)? 1 : 0) + +/* RX Macros */ + +/** + * @brief Read Rx data register + * @param[in] psSC The base address of smartcard module + * @return The oldest data byte in RX FIFO + * \hideinitializer + */ +#define SCUART_READ(psSC) ((psSC)->DAT) + +/** + * @brief Get RX FIFO empty flag status from register + * @param[in] psSC The base address of smartcard module + * @return Receive FIFO empty status + * @retval 0 Receive FIFO is not empty + * @retval SC_STATUS_RXEMPTY_Msk Receive FIFO is empty + * \hideinitializer + */ +#define SCUART_GET_RX_EMPTY(psSC) ((psSC)->STATUS & SC_STATUS_RXEMPTY_Msk) + + +/** + * @brief Get RX FIFO full flag status from register + * @param[in] psSC The base address of smartcard module + * @return Receive FIFO full status + * @retval 0 Receive FIFO is not full + * @retval SC_STATUS_RXFULLF_Msk Receive FIFO is full + * \hideinitializer + */ +#define SCUART_GET_RX_FULL(psSC) ((psSC)->STATUS & SC_STATUS_RXFULL_Msk) + +/** + * @brief Check if receive data number in FIFO reach FIFO trigger level or not + * @param[in] psSC The base address of smartcard module + * @return Receive FIFO data status + * @retval 0 The number of bytes in receive FIFO is less than trigger level + * @retval 1 The number of bytes in receive FIFO equals or larger than trigger level + * @note If receive trigger level is \b not 1 byte, this macro return 0 does not necessary indicates there is \b no data in FIFO + * \hideinitializer + */ +#define SCUART_IS_RX_READY(psSC) ((psSC)->INTSTS & SC_INTSTS_RDAIF_Msk ? 1 : 0) + +/** + * @brief Check specified smartcard port receive FIFO is full or not + * @param[in] psSC The base address of smartcard module + * @return Receive FIFO full status + * @retval 0 Receive FIFO is not full + * @retval 1 Receive FIFO is full + * \hideinitializer + */ +#define SCUART_IS_RX_FULL(psSC) ((psSC)->STATUS & SC_STATUS_RXFULL_Msk ? 1 : 0) + +/* Interrupt Macros */ + +/** + * @brief Enable specified interrupts + * @param[in] psSC The base address of smartcard module + * @param[in] u32Mask Interrupt masks to enable, a combination of following bits + * - \ref SC_INTEN_RXTOIEN_Msk + * - \ref SC_INTEN_TERRIEN_Msk + * - \ref SC_INTEN_TBEIEN_Msk + * - \ref SC_INTEN_RDAIEN_Msk + * @return None + * \hideinitializer + */ +#define SCUART_ENABLE_INT(psSC, u32Mask) ((psSC)->INTEN |= (u32Mask)) + +/** + * @brief Disable specified interrupts + * @param[in] psSC The base address of smartcard module + * @param[in] u32Mask Interrupt masks to disable, a combination of following bits + * - \ref SC_INTEN_RXTOIEN_Msk + * - \ref SC_INTEN_TERRIEN_Msk + * - \ref SC_INTEN_TBEIEN_Msk + * - \ref SC_INTEN_RDAIEN_Msk + * @return None + * \hideinitializer + */ +#define SCUART_DISABLE_INT(psSC, u32Mask) ((psSC)->INTEN &= ~(u32Mask)) + +/** + * @brief Get specified interrupt flag/status + * @param[in] psSC The base address of smartcard module + * @param[in] u32Type Interrupt flag/status to check, could be one of following value + * - \ref SC_INTSTS_RXTOIF_Msk + * - \ref SC_INTSTS_TERRIF_Msk + * - \ref SC_INTSTS_TBEIF_Msk + * - \ref SC_INTSTS_RDAIF_Msk + * @return The status of specified interrupt + * @retval 0 Specified interrupt does not happened + * @retval 1 Specified interrupt happened + * \hideinitializer + */ +#define SCUART_GET_INT_FLAG(psSC, u32Type) ((psSC)->INTSTS & (u32Type) ? 1 : 0) + +/** + * @brief Clear specified interrupt flag/status + * @param[in] psSC The base address of smartcard module + * @param[in] u32Type Interrupt flag/status to clear, could be the combination of following values + * - \ref SC_INTSTS_RXTOIF_Msk + * - \ref SC_INTSTS_TERRIF_Msk + * - \ref SC_INTSTS_TBEIF_Msk + * @return None + * \hideinitializer + */ +#define SCUART_CLR_INT_FLAG(psSC, u32Type) ((psSC)->INTSTS = (u32Type)) + +/** + * @brief Get receive error flag/status + * @param[in] psSC The base address of smartcard module + * @return Current receive error status, could one of following errors: + * @retval SC_STATUS_PEF_Msk Parity error + * @retval SC_STATUS_FEF_Msk Frame error + * @retval SC_STATUS_BEF_Msk Break error + * \hideinitializer + */ +#define SCUART_GET_ERR_FLAG(psSC) ((psSC)->STATUS & (SC_STATUS_PEF_Msk | SC_STATUS_FEF_Msk | SC_STATUS_BEF_Msk)) + +/** + * @brief Clear specified receive error flag/status + * @param[in] psSC The base address of smartcard module + * @param[in] u32Mask Receive error flag/status to clear, combination following values + * - \ref SC_STATUS_PEF_Msk + * - \ref SC_STATUS_FEF_Msk + * - \ref SC_STATUS_BEF_Msk + * @return None + * \hideinitializer + */ +#define SCUART_CLR_ERR_FLAG(psSC, u32Mask) ((psSC)->STATUS = (u32Mask)) + +void SCUART_Close(SC_T *psSC); +uint32_t SCUART_Open(SC_T *psSC, uint32_t u32baudrate); +uint32_t SCUART_Read(SC_T *psSC, uint8_t pu8RxBuf[], uint32_t u32ReadBytes); +uint32_t SCUART_SetLineConfig(SC_T *psSC, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits); +void SCUART_SetTimeoutCnt(SC_T *psSC, uint32_t u32TOC); +void SCUART_Write(SC_T *psSC, uint8_t pu8TxBuf[], uint32_t u32WriteBytes); + +/*@}*/ /* end of group SCUART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SCUART_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SCUART_H__ */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_spi.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_spi.h new file mode 100644 index 00000000000..18414f374d8 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_spi.h @@ -0,0 +1,595 @@ +/**************************************************************************//** + * @file spi.h + * @version V0.10 + * @brief M251 series SPI driver header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __SPI_H__ +#define __SPI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SPI_Driver SPI Driver + @{ +*/ + +/** @addtogroup SPI_EXPORTED_CONSTANTS SPI Exported Constants + @{ +*/ + +#define SPI_MODE_0 (SPI_CTL_TXNEG_Msk) /*!< CLKPOL=0; RXNEG=0; TXNEG=1 \hideinitializer */ +#define SPI_MODE_1 (SPI_CTL_RXNEG_Msk) /*!< CLKPOL=0; RXNEG=1; TXNEG=0 \hideinitializer */ +#define SPI_MODE_2 (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk) /*!< CLKPOL=1; RXNEG=1; TXNEG=0 \hideinitializer */ +#define SPI_MODE_3 (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk) /*!< CLKPOL=1; RXNEG=0; TXNEG=1 \hideinitializer */ + +#define SPI_SLAVE (SPI_CTL_SLAVE_Msk) /*!< Set as slave \hideinitializer */ +#define SPI_MASTER (0x0UL) /*!< Set as master \hideinitializer */ + +#define SPI_SS (SPI_SSCTL_SS_Msk) /*!< Set SS \hideinitializer */ +#define SPI_SS_ACTIVE_HIGH (SPI_SSCTL_SSACTPOL_Msk) /*!< SS active high \hideinitializer */ +#define SPI_SS_ACTIVE_LOW (0x0UL) /*!< SS active low \hideinitializer */ + +/* SPI Interrupt Mask */ +#define SPI_UNIT_INT_MASK (0x001UL) /*!< Unit transfer interrupt mask \hideinitializer */ +#define SPI_SSACT_INT_MASK (0x002UL) /*!< Slave selection signal active interrupt mask \hideinitializer */ +#define SPI_SSINACT_INT_MASK (0x004UL) /*!< Slave selection signal inactive interrupt mask \hideinitializer */ +#define SPI_SLVUR_INT_MASK (0x008UL) /*!< Slave under run interrupt mask \hideinitializer */ +#define SPI_SLVBE_INT_MASK (0x010UL) /*!< Slave bit count error interrupt mask \hideinitializer */ +#define SPI_TXUF_INT_MASK (0x040UL) /*!< Slave TX underflow interrupt mask \hideinitializer */ +#define SPI_FIFO_TXTH_INT_MASK (0x080UL) /*!< FIFO TX threshold interrupt mask \hideinitializer */ +#define SPI_FIFO_RXTH_INT_MASK (0x100UL) /*!< FIFO RX threshold interrupt mask \hideinitializer */ +#define SPI_FIFO_RXOV_INT_MASK (0x200UL) /*!< FIFO RX overrun interrupt mask \hideinitializer */ +#define SPI_FIFO_RXTO_INT_MASK (0x400UL) /*!< FIFO RX time-out interrupt mask \hideinitializer */ + +/* SPI Status Mask */ +#define SPI_BUSY_MASK (0x01UL) /*!< Busy status mask \hideinitializer */ +#define SPI_RX_EMPTY_MASK (0x02UL) /*!< RX empty status mask \hideinitializer */ +#define SPI_RX_FULL_MASK (0x04UL) /*!< RX full status mask \hideinitializer */ +#define SPI_TX_EMPTY_MASK (0x08UL) /*!< TX empty status mask \hideinitializer */ +#define SPI_TX_FULL_MASK (0x10UL) /*!< TX full status mask \hideinitializer */ +#define SPI_TXRX_RESET_MASK (0x20UL) /*!< TX or RX reset status mask \hideinitializer */ +#define SPI_SPIEN_STS_MASK (0x40UL) /*!< SPIEN status mask \hideinitializer */ +#define SPI_SSLINE_STS_MASK (0x80UL) /*!< SPIx_SS line status mask \hideinitializer */ + + +/* I2S Data Width */ +#define SPII2S_DATABIT_8 (0UL << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 8-bit \hideinitializer */ +#define SPII2S_DATABIT_16 (1UL << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 16-bit \hideinitializer */ +#define SPII2S_DATABIT_24 (2UL << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 24-bit \hideinitializer */ +#define SPII2S_DATABIT_32 (3UL << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 32-bit \hideinitializer */ + +/* I2S Audio Format */ +#define SPII2S_MONO SPI_I2SCTL_MONO_Msk /*!< Monaural channel \hideinitializer */ +#define SPII2S_STEREO (0UL) /*!< Stereo channel \hideinitializer */ + +/* I2S Data Format */ +#define SPII2S_FORMAT_I2S (0UL<STATUS = SPI_STATUS_UNITIF_Msk) + +/** + * @brief Trigger RX PDMA function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set RXPDMAEN bit of SPI_PDMACTL register to enable RX PDMA transfer function. + * \hideinitializer + */ +#define SPI_TRIGGER_RX_PDMA(spi) ((spi)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk) + +/** + * @brief Trigger TX PDMA function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set TXPDMAEN bit of SPI_PDMACTL register to enable TX PDMA transfer function. + * \hideinitializer + */ +#define SPI_TRIGGER_TX_PDMA(spi) ((spi)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk) + +/** + * @brief Disable RX PDMA transfer. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear RXPDMAEN bit of SPI_PDMACTL register to disable RX PDMA transfer function. + * \hideinitializer + */ +#define SPI_DISABLE_RX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Disable TX PDMA transfer. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear TXPDMAEN bit of SPI_PDMACTL register to disable TX PDMA transfer function. + * \hideinitializer + */ +#define SPI_DISABLE_TX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Get the count of available data in RX FIFO. + * @param[in] spi The pointer of the specified SPI module. + * @return The count of available data in RX FIFO. + * @details Read RXCNT (SPI_STATUS[27:24]) to get the count of available data in RX FIFO. + * \hideinitializer + */ +#define SPI_GET_RX_FIFO_COUNT(spi) (((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos) + +/** + * @brief Get the RX FIFO empty flag. + * @param[in] spi The pointer of the specified SPI module. + * @retval 0 RX FIFO is not empty. + * @retval 1 RX FIFO is empty. + * @details Read RXEMPTY bit of SPI_STATUS register to get the RX FIFO empty flag. + * \hideinitializer + */ +#define SPI_GET_RX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk)>>SPI_STATUS_RXEMPTY_Pos) + +/** + * @brief Get the TX FIFO empty flag. + * @param[in] spi The pointer of the specified SPI module. + * @retval 0 TX FIFO is not empty. + * @retval 1 TX FIFO is empty. + * @details Read TXEMPTY bit of SPI_STATUS register to get the TX FIFO empty flag. + * \hideinitializer + */ +#define SPI_GET_TX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk)>>SPI_STATUS_TXEMPTY_Pos) + +/** + * @brief Get the TX FIFO full flag. + * @param[in] spi The pointer of the specified SPI module. + * @retval 0 TX FIFO is not full. + * @retval 1 TX FIFO is full. + * @details Read TXFULL bit of SPI_STATUS register to get the TX FIFO full flag. + * \hideinitializer + */ +#define SPI_GET_TX_FIFO_FULL_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TXFULL_Msk)>>SPI_STATUS_TXFULL_Pos) + +/** + * @brief Get the datum read from RX register. + * @param[in] spi The pointer of the specified SPI module. + * @return Data in RX register. + * @details Read SPI_RX register to get the received datum. + * \hideinitializer + */ +#define SPI_READ_RX(spi) ((spi)->RX) + +/** + * @brief Write datum to TX register. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32TxData The datum which user attempt to transfer through SPI bus. + * @return None. + * @details Write u32TxData to SPI_TX register. + * \hideinitializer + */ +#define SPI_WRITE_TX(spi, u32TxData) ((spi)->TX = (u32TxData)) + +/** + * @brief Set SPIx_SS pin to high state. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Disable automatic slave selection function and set SPIx_SS pin to high state. + * \hideinitializer + */ +#define SPI_SET_SS_HIGH(spi) ((spi)->SSCTL = ((spi)->SSCTL & (~SPI_SSCTL_AUTOSS_Msk)) | (SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk)) + +/** + * @brief Set SPIx_SS pin to low state. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Disable automatic slave selection function and set SPIx_SS pin to low state. + * \hideinitializer + */ +#define SPI_SET_SS_LOW(spi) ((spi)->SSCTL = ((spi)->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk))) | SPI_SSCTL_SS_Msk) + +/** + * @brief Enable Byte Reorder function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (SPI_CTL[7:4]). + * \hideinitializer + */ +#define SPI_ENABLE_BYTE_REORDER(spi) ((spi)->CTL |= SPI_CTL_REORDER_Msk) + +/** + * @brief Disable Byte Reorder function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear REORDER bit field of SPI_CTL register to disable Byte Reorder function. + * \hideinitializer + */ +#define SPI_DISABLE_BYTE_REORDER(spi) ((spi)->CTL &= ~SPI_CTL_REORDER_Msk) + +/** + * @brief Set the length of suspend interval. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15. + * @return None. + * @details Set the length of suspend interval according to u32SuspCycle. + * The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one SPI bus clock cycle). + * \hideinitializer + */ +#define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << SPI_CTL_SUSPITV_Pos)) + +/** + * @brief Set the SPI transfer sequence with LSB first. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set LSB bit of SPI_CTL register to set the SPI transfer sequence with LSB first. + * \hideinitializer + */ +#define SPI_SET_LSB_FIRST(spi) ((spi)->CTL |= SPI_CTL_LSB_Msk) + +/** + * @brief Set the SPI transfer sequence with MSB first. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear LSB bit of SPI_CTL register to set the SPI transfer sequence with MSB first. + * \hideinitializer + */ +#define SPI_SET_MSB_FIRST(spi) ((spi)->CTL &= ~SPI_CTL_LSB_Msk) + +/** + * @brief Set the data width of a SPI transaction. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Width The bit width of one transaction. + * @return None. + * @details The data width can be 8 ~ 32 bits. + * \hideinitializer + */ +#define SPI_SET_DATA_WIDTH(spi, u32Width) ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_DWIDTH_Msk) | (((u32Width)&0x1F) << SPI_CTL_DWIDTH_Pos)) + +/** + * @brief Get the SPI busy state. + * @param[in] spi The pointer of the specified SPI module. + * @retval 0 SPI controller is not busy. + * @retval 1 SPI controller is busy. + * @details This macro will return the busy state of SPI controller. + * \hideinitializer + */ +#define SPI_IS_BUSY(spi) ( ((spi)->STATUS & SPI_STATUS_BUSY_Msk)>>SPI_STATUS_BUSY_Pos ) + +/** + * @brief Enable SPI controller. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set SPIEN (SPI_CTL[0]) to enable SPI controller. + * \hideinitializer + */ +#define SPI_ENABLE(spi) ((spi)->CTL |= SPI_CTL_SPIEN_Msk) + +/** + * @brief Disable SPI controller. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear SPIEN (SPI_CTL[0]) to disable SPI controller. + * \hideinitializer + */ +#define SPI_DISABLE(spi) ((spi)->CTL &= ~SPI_CTL_SPIEN_Msk) + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask); +__STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask); +__STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch); + +/** + * @brief Enable zero cross detection function. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32ChMask The mask for left or right channel. Valid values are: + * - \ref SPII2S_RIGHT + * - \ref SPII2S_LEFT + * @return None + * @details This function will set RZCEN or LZCEN bit of SPI_I2SCTL register to enable zero cross detection function. + */ +__STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask) +{ + if (u32ChMask == SPII2S_RIGHT) + { + i2s->I2SCTL |= SPI_I2SCTL_RZCEN_Msk; + } + else + { + i2s->I2SCTL |= SPI_I2SCTL_LZCEN_Msk; + } +} + +/** + * @brief Disable zero cross detection function. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32ChMask The mask for left or right channel. Valid values are: + * - \ref SPII2S_RIGHT + * - \ref SPII2S_LEFT + * @return None + * @details This function will clear RZCEN or LZCEN bit of SPI_I2SCTL register to disable zero cross detection function. + */ +__STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask) +{ + if (u32ChMask == SPII2S_RIGHT) + { + i2s->I2SCTL &= ~SPI_I2SCTL_RZCEN_Msk; + } + else + { + i2s->I2SCTL &= ~SPI_I2SCTL_LZCEN_Msk; + } +} + +/** + * @brief Enable I2S TX DMA function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set TXPDMAEN bit of SPI_PDMACTL register to transmit data with PDMA. + * \hideinitializer + */ +#define SPII2S_ENABLE_TXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Disable I2S TX DMA function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear TXPDMAEN bit of SPI_PDMACTL register to disable TX DMA function. + * \hideinitializer + */ +#define SPII2S_DISABLE_TXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Enable I2S RX DMA function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set RXPDMAEN bit of SPI_PDMACTL register to receive data with PDMA. + * \hideinitializer + */ +#define SPII2S_ENABLE_RXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Disable I2S RX DMA function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear RXPDMAEN bit of SPI_PDMACTL register to disable RX DMA function. + * \hideinitializer + */ +#define SPII2S_DISABLE_RXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Enable I2S TX function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set TXEN bit of SPI_I2SCTL register to enable I2S TX function. + * \hideinitializer + */ +#define SPII2S_ENABLE_TX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_TXEN_Msk ) + +/** + * @brief Disable I2S TX function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear TXEN bit of SPI_I2SCTL register to disable I2S TX function. + * \hideinitializer + */ +#define SPII2S_DISABLE_TX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_TXEN_Msk ) + +/** + * @brief Enable I2S RX function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set RXEN bit of SPI_I2SCTL register to enable I2S RX function. + * \hideinitializer + */ +#define SPII2S_ENABLE_RX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_RXEN_Msk ) + +/** + * @brief Disable I2S RX function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear RXEN bit of SPI_I2SCTL register to disable I2S RX function. + * \hideinitializer + */ +#define SPII2S_DISABLE_RX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_RXEN_Msk ) + +/** + * @brief Enable TX Mute function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set MUTE bit of SPI_I2SCTL register to enable I2S TX mute function. + * \hideinitializer + */ +#define SPII2S_ENABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_MUTE_Msk ) + +/** + * @brief Disable TX Mute function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear MUTE bit of SPI_I2SCTL register to disable I2S TX mute function. + * \hideinitializer + */ +#define SPII2S_DISABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_MUTE_Msk ) + +/** + * @brief Clear TX FIFO. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear TX FIFO. The internal TX FIFO pointer will be reset to FIFO start point. + * \hideinitializer + */ +#define SPII2S_CLR_TX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk ) + +/** + * @brief Clear RX FIFO. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear RX FIFO. The internal RX FIFO pointer will be reset to FIFO start point. + * \hideinitializer + */ +#define SPII2S_CLR_RX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk ) + +/** + * @brief This function sets the recording source channel when mono mode is used. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Ch left or right channel. Valid values are: + * - \ref SPII2S_MONO_LEFT + * - \ref SPII2S_MONO_RIGHT + * @return None + * @details This function selects the recording source channel of monaural mode. + * \hideinitializer + */ +__STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch) +{ + u32Ch == SPII2S_MONO_LEFT ? + (i2s->I2SCTL |= SPI_I2SCTL_RXLCH_Msk) : + (i2s->I2SCTL &= ~SPI_I2SCTL_RXLCH_Msk); +} + +/** + * @brief Write data to I2S TX FIFO. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Data The value written to TX FIFO. + * @return None + * @details This macro will write a value to TX FIFO. + * \hideinitializer + */ +#define SPII2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TX = (u32Data) ) + +/** + * @brief Read RX FIFO. + * @param[in] i2s The pointer of the specified I2S module. + * @return The value read from RX FIFO. + * @details This function will return a value read from RX FIFO. + * \hideinitializer + */ +#define SPII2S_READ_RX_FIFO(i2s) ( (i2s)->RX ) + +/** + * @brief Get the interrupt flag. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Mask The mask value for all interrupt flags. + * @return The interrupt flags specified by the u32mask parameter. + * @details This macro will return the combination interrupt flags of SPI_I2SSTS register. The flags are specified by the u32mask parameter. + * \hideinitializer + */ +#define SPII2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS & (u32Mask) ) + +/** + * @brief Clear the interrupt flag. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Mask The mask value for all interrupt flags. + * @return None + * @details This macro will clear the interrupt flags specified by the u32mask parameter. + * @note Except TX and RX FIFO threshold interrupt flags, the other interrupt flags can be cleared by writing 1 to itself. + * \hideinitializer + */ +#define SPII2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS = (u32Mask) ) + +/** + * @brief Get transmit FIFO level + * @param[in] i2s The pointer of the specified I2S module. + * @return TX FIFO level + * @details This macro will return the number of available words in TX FIFO. + * \hideinitializer + */ +#define SPII2S_GET_TX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_TXCNT_Msk) >> SPI_I2SSTS_TXCNT_Pos ) + +/** + * @brief Get receive FIFO level + * @param[in] i2s The pointer of the specified I2S module. + * @return RX FIFO level + * @details This macro will return the number of available words in RX FIFO. + * \hideinitializer + */ +#define SPII2S_GET_RX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_RXCNT_Msk) >> SPI_I2SSTS_RXCNT_Pos ) + + + +/* Function prototype declaration */ +uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock); +void SPI_Close(SPI_T *spi); +void SPI_ClearRxFIFO(SPI_T *spi); +void SPI_ClearTxFIFO(SPI_T *spi); +void SPI_DisableAutoSS(SPI_T *spi); +void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel); +uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock); +void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold); +uint32_t SPI_GetBusClock(SPI_T *spi); +void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask); +void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask); +uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask); +void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask); +uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask); + +uint32_t SPII2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat); +void SPII2S_Close(SPI_T *i2s); +void SPII2S_EnableInt(SPI_T *i2s, uint32_t u32Mask); +void SPII2S_DisableInt(SPI_T *i2s, uint32_t u32Mask); +uint32_t SPII2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock); +void SPII2S_DisableMCLK(SPI_T *i2s); +void SPII2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold); + + +/*@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_sys.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_sys.h new file mode 100644 index 00000000000..595a7769688 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_sys.h @@ -0,0 +1,1231 @@ +/**************************************************************************** + * @file sys.h + * @version V1.10 + * @brief M251 series SYS driver source file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SYS_H__ +#define __SYS_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SYS_Driver SYS Driver + @{ +*/ + +/** @addtogroup SYS_EXPORTED_CONSTANTS SYS Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Module Reset Control Resister constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ + +#define PDMA_RST ((0x0<<24)|SYS_IPRST0_PDMARST_Pos) /*!< PDMA reset is one of the SYS_ResetModule parameter */ +#define EBI_RST ((0x0<<24)|SYS_IPRST0_EBIRST_Pos) /*!< EBI reset is one of the SYS_ResetModule parameter */ +#define CRC_RST ((0x0<<24)|SYS_IPRST0_CRCRST_Pos) /*!< CRC reset is one of the SYS_ResetModule parameter */ +#define CRPT_RST ((0x0<<24)|SYS_IPRST0_CRYPTRST_Pos) /*!< CRYPTO reset is one of the SYS_ResetModule parameter */ + +#define GPIO_RST ((0x4<<24)|SYS_IPRST1_GPIORST_Pos) /*!< GPIO reset is one of the SYS_ResetModule parameter */ +#define TMR0_RST ((0x4<<24)|SYS_IPRST1_TMR0RST_Pos) /*!< TMR0 reset is one of the SYS_ResetModule parameter */ +#define TMR1_RST ((0x4<<24)|SYS_IPRST1_TMR1RST_Pos) /*!< TMR1 reset is one of the SYS_ResetModule parameter */ +#define TMR2_RST ((0x4<<24)|SYS_IPRST1_TMR2RST_Pos) /*!< TMR2 reset is one of the SYS_ResetModule parameter */ +#define TMR3_RST ((0x4<<24)|SYS_IPRST1_TMR3RST_Pos) /*!< TMR3 reset is one of the SYS_ResetModule parameter */ +#define ACMP01_RST ((0x4<<24)|SYS_IPRST1_ACMP01RST_Pos) /*!< ACMP reset is one of the SYS_ResetModule parameter */ +#define I2C0_RST ((0x4<<24)|SYS_IPRST1_I2C0RST_Pos) /*!< I2C0 reset is one of the SYS_ResetModule parameter */ +#define I2C1_RST ((0x4<<24)|SYS_IPRST1_I2C1RST_Pos) /*!< I2C1 reset is one of the SYS_ResetModule parameter */ +#define QSPI0_RST ((0x4<<24)|SYS_IPRST1_QSPI0RST_Pos) /*!< QSPI0 reset is one of the SYS_ResetModule parameter */ +#define SPI0_RST ((0x4<<24)|SYS_IPRST1_SPI0RST_Pos) /*!< SPI0 reset is one of the SYS_ResetModule parameter */ +#define UART0_RST ((0x4<<24)|SYS_IPRST1_UART0RST_Pos) /*!< UART0 reset is one of the SYS_ResetModule parameter */ +#define UART1_RST ((0x4<<24)|SYS_IPRST1_UART1RST_Pos) /*!< UART1 reset is one of the SYS_ResetModule parameter */ +#define UART2_RST ((0x4<<24)|SYS_IPRST1_UART2RST_Pos) /*!< UART2 reset is one of the SYS_ResetModule parameter */ +#define USBD_RST ((0x4<<24)|SYS_IPRST1_USBDRST_Pos) /*!< USBD reset is one of the SYS_ResetModule parameter */ +#define EADC_RST ((0x4<<24)|SYS_IPRST1_EADCRST_Pos) /*!< ADC reset is one of the SYS_ResetModule parameter */ + +#define SC0_RST ((0x8<<24)|SYS_IPRST2_SC0RST_Pos) /*!< SC0 reset is one of the SYS_ResetModule parameter */ +#define USCI0_RST ((0x8<<24)|SYS_IPRST2_USCI0RST_Pos) /*!< USCI0 reset is one of the SYS_ResetModule parameter */ +#define USCI1_RST ((0x8<<24)|SYS_IPRST2_USCI1RST_Pos) /*!< USCI1 reset is one of the SYS_ResetModule parameter */ +#define USCI2_RST ((0x8<<24)|SYS_IPRST2_USCI2RST_Pos) /*!< USCI2 reset is one of the SYS_ResetModule parameter */ +#define DAC_RST ((0x8<<24)|SYS_IPRST2_DACRST_Pos) /*!< DAC reset is one of the SYS_ResetModule parameter */ +#define PWM0_RST ((0x8<<24)|SYS_IPRST2_PWM0RST_Pos) /*!< PWM0 reset is one of the SYS_ResetModule parameter */ +#define PWM1_RST ((0x8<<24)|SYS_IPRST2_PWM1RST_Pos) /*!< PWM1 reset is one of the SYS_ResetModule parameter */ +#define BPWM0_RST ((0x8<<24)|SYS_IPRST2_BPWM0RST_Pos) /*!< BPWM0 reset is one of the SYS_ResetModule parameter */ +#define BPWM1_RST ((0x8<<24)|SYS_IPRST2_BPWM1RST_Pos) /*!< BPWM0 reset is one of the SYS_ResetModule parameter */ +#define OPA_RST ((0x8<<24)|SYS_IPRST2_OPARST_Pos) /*!< OPA reset is one of the SYS_ResetModule parameter */ +#define PSIO_RST ((0x8<<24)|SYS_IPRST2_PSIORST_Pos) /*!< PSIO reset is one of the SYS_ResetModule parameter */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Brown Out Detector Threshold Voltage Selection constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define SYS_BODCTL_BOD_RST_EN (1UL<GPD_MFPL = (SYS->GPD_MFPL & ~SYS_GPD_MFPL_PD2MFP_Msk) | SYS_GPD_MFPL_PD2MFP_UART0_RXD; + SYS->GPD_MFPL = (SYS->GPD_MFPL & ~SYS_GPD_MFPL_PD3MFP_Msk) | SYS_GPD_MFPL_PD3MFP_UART0_TXD; +*/ +/* PA.0 MFP */ +#define SYS_GPA_MFPL_PA0MFP_GPIO (0x00UL<BODCTL |= SYS_BODCTL_BODIF_Msk) + +/** + * @brief Set Brown-out detector function to normal mode + * @param None + * @return None + * @details This macro set Brown-out detector to normal mode. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_CLEAR_BOD_LPM() (SYS->BODCTL &= ~SYS_BODCTL_BODLPM_Msk) + +/** + * @brief Disable Brown-out detector function + * @param None + * @return None + * @details This macro disable Brown-out detector function. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_DISABLE_BOD() (SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk) + +/** + * @brief Enable Brown-out detector function + * @param None + * @return None + * @details This macro enable Brown-out detector function. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_ENABLE_BOD() (SYS->BODCTL |= SYS_BODCTL_BODEN_Msk) + +/** + * @brief Get Brown-out detector interrupt flag + * @param None + * @retval 0 Brown-out detect interrupt flag is not set. + * @retval >=1 Brown-out detect interrupt flag is set. + * @details This macro get Brown-out detector interrupt flag. + * \hideinitializer + */ +#define SYS_GET_BOD_INT_FLAG() (SYS->BODCTL & SYS_BODCTL_BODIF_Msk) + +/** + * @brief Get Brown-out detector status + * @param None + * @retval 0 System voltage is higher than BOD threshold voltage setting or BOD function is disabled. + * @retval >=1 System voltage is lower than BOD threshold voltage setting. + * @details This macro get Brown-out detector output status. + * If the BOD function is disabled, this function always return 0. + * \hideinitializer + */ +#define SYS_GET_BOD_OUTPUT() (SYS->BODCTL & SYS_BODCTL_BODOUT_Msk) + +/** + * @brief Disable Brown-out detector interrupt function + * @param None + * @return None + * @details This macro disable Brown-out detector interrupt function. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_DISABLE_BOD_RST() (SYS->BODCTL &= ~SYS_BODCTL_BODRSTEN_Msk) + +/** + * @brief Enable Brown-out detector reset function + * @param None + * @return None + * @details This macro enable Brown-out detect reset function. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_ENABLE_BOD_RST() (SYS->BODCTL |= SYS_BODCTL_BODRSTEN_Msk) + +/** + * @brief Set Brown-out detector function low power mode + * @param None + * @return None + * @details This macro set Brown-out detector to low power mode. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_SET_BOD_LPM() (SYS->BODCTL |= SYS_BODCTL_BODLPM_Msk) + +/** + * @brief Set Brown-out detector voltage level + * @param[in] u32Level is Brown-out voltage level. Including : + * - \ref SYS_BODCTL_BODVL_4_4V + * - \ref SYS_BODCTL_BODVL_3_7V + * - \ref SYS_BODCTL_BODVL_3_0V + * - \ref SYS_BODCTL_BODVL_2_7V + * - \ref SYS_BODCTL_BODVL_2_4V + * - \ref SYS_BODCTL_BODVL_2_0V + * - \ref SYS_BODCTL_BODVL_1_8V + * @return None + * @details This macro set Brown-out detector voltage level. + * The write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_SET_BOD_LEVEL(u32Level) (SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | (u32Level)) + +/** + * @brief Get reset source is from Brown-out detector reset + * @param None + * @retval 0 Previous reset source is not from Brown-out detector reset + * @retval >=1 Previous reset source is from Brown-out detector reset + * @details This macro get previous reset source is from Brown-out detect reset or not. + * \hideinitializer + */ +#define SYS_IS_BOD_RST() (SYS->RSTSTS & SYS_RSTSTS_BODRF_Msk) + +/** + * @brief Get reset source is from VBAT LVR + * @param None + * @retval 0 Previous reset source is not from VBAT LVR + * @retval >=1 Previous reset source is from VBAT LVR + * @details This macro get previous reset source is from VBAT LVR or not. + * \hideinitializer + */ +#define SYS_IS_VBATLVR_RST() (SYS->RSTSTS & SYS_RSTSTS_VBATLVRF_Msk) + +/** + * @brief Get reset source is from CPU Lockup reset + * @param None + * @retval 0 Previous reset source is not from CPU Lockup reset + * @retval >=1 Previous reset source is from CPU Lockup reset + * @details This macro get previous reset source is from CPU Lockup reset or not. + * \hideinitializer + */ +#define SYS_IS_CPULK_RST() (SYS->RSTSTS & SYS_RSTSTS_CPULKRF_Msk) + +/** + * @brief Get reset source is from CPU reset + * @param None + * @retval 0 Previous reset source is not from CPU reset + * @retval >=1 Previous reset source is from CPU reset + * @details This macro get previous reset source is from CPU reset. + * \hideinitializer + */ +#define SYS_IS_CPU_RST() (SYS->RSTSTS & SYS_RSTSTS_CPURF_Msk) + +/** + * @brief Get reset source is from LVR Reset + * @param None + * @retval 0 Previous reset source is not from Low-Voltage-Reset + * @retval >=1 Previous reset source is from Low-Voltage-Reset + * @details This macro get previous reset source is from Low-Voltage-Reset. + * \hideinitializer + */ +#define SYS_IS_LVR_RST() (SYS->RSTSTS & SYS_RSTSTS_LVRF_Msk) + +/** + * @brief Get reset source is from Power-on Reset + * @param None + * @retval 0 Previous reset source is not from Power-on Reset + * @retval >=1 Previous reset source is from Power-on Reset + * @details This macro get previous reset source is from Power-on Reset. + * \hideinitializer + */ +#define SYS_IS_POR_RST() (SYS->RSTSTS & SYS_RSTSTS_PORF_Msk) + +/** + * @brief Get reset source is from reset pin reset + * @param None + * @retval 0 Previous reset source is not from reset pin reset + * @retval >=1 Previous reset source is from reset pin reset + * @details This macro get previous reset source is from reset pin reset. + * \hideinitializer + */ +#define SYS_IS_RSTPIN_RST() (SYS->RSTSTS & SYS_RSTSTS_PINRF_Msk) + +/** + * @brief Get reset source is from system reset + * @param None + * @retval 0 Previous reset source is not from system reset + * @retval >=1 Previous reset source is from system reset + * @details This macro get previous reset source is from system reset. + * \hideinitializer + */ +#define SYS_IS_SYSTEM_RST() (SYS->RSTSTS & SYS_RSTSTS_SYSRF_Msk) + +/** + * @brief Get reset source is from window watch dog reset + * @param None + * @retval 0 Previous reset source is not from window watch dog reset + * @retval >=1 Previous reset source is from window watch dog reset + * @details This macro get previous reset source is from window watch dog reset. + * \hideinitializer + */ +#define SYS_IS_WDT_RST() (SYS->RSTSTS & SYS_RSTSTS_WDTRF_Msk) + +/** + * @brief Disable Low-Voltage-Reset function + * @param None + * @return None + * @details This macro disable Low-Voltage-Reset function. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_DISABLE_LVR() (SYS->BODCTL &= ~SYS_BODCTL_LVREN_Msk) + +/** + * @brief Enable Low-Voltage-Reset function + * @param None + * @return None + * @details This macro enable Low-Voltage-Reset function. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_ENABLE_LVR() (SYS->BODCTL |= SYS_BODCTL_LVREN_Msk) + +/** + * @brief Disable Power-on Reset function + * @param None + * @return None + * @details This macro disable Power-on Reset function. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_DISABLE_POR() (SYS->PORCTL0 = 0x5AA5) + +/** + * @brief Enable Power-on Reset function + * @param None + * @return None + * @details This macro enable Power-on Reset function. + * The register write-protection function should be disabled before using this macro. + * \hideinitializer + */ +#define SYS_ENABLE_POR() (SYS->PORCTL0 = 0) + +/** + * @brief Clear reset source flag + * @param[in] u32RstSrc is reset source. Including : + * - \ref SYS_RSTSTS_PORF_Msk + * - \ref SYS_RSTSTS_PINRF_Msk + * - \ref SYS_RSTSTS_WDTRF_Msk + * - \ref SYS_RSTSTS_LVRF_Msk + * - \ref SYS_RSTSTS_BODRF_Msk + * - \ref SYS_RSTSTS_SYSRF_Msk + * - \ref SYS_RSTSTS_CPURF_Msk + * - \ref SYS_RSTSTS_CPULKRF_Msk + * - \ref SYS_RSTSTS_VBATLVRF_Msk + * @return None + * @details This macro clear reset source flag. + * \hideinitializer + */ +#define SYS_CLEAR_RST_SOURCE(u32RstSrc) ((SYS->RSTSTS) = (u32RstSrc) ) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* static inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void SYS_UnlockReg(void); +__STATIC_INLINE void SYS_LockReg(void); + +/** + * @brief Disable register write-protection function + * @param None + * @return None + * @details This function disable register write-protection function. + * To unlock the protected register to allow write access. + */ +__STATIC_INLINE void SYS_UnlockReg(void) +{ + do + { + SYS->REGLCTL = 0x59UL; + SYS->REGLCTL = 0x16UL; + SYS->REGLCTL = 0x88UL; + } + while (SYS->REGLCTL == 0UL); +} + +/** + * @brief Enable register write-protection function + * @param None + * @return None + * @details This function is used to enable register write-protection function. + * To lock the protected register to forbid write access. + */ +__STATIC_INLINE void SYS_LockReg(void) +{ + SYS->REGLCTL = 0x0UL; +} + + +void SYS_ClearResetSrc(uint32_t u32Src); +uint32_t SYS_GetBODStatus(void); +uint32_t SYS_GetResetSrc(void); +uint32_t SYS_IsRegLocked(void); +uint32_t SYS_ReadPDID(void); +void SYS_ResetChip(void); +void SYS_ResetCPU(void); +void SYS_ResetModule(uint32_t u32ModuleIndex); +void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel); +void SYS_DisableBOD(void); +void SYS_SetPowerLevel(uint32_t u32PowerLevel); + + +/*@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SYS_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __SYS_H__ */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_timer.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_timer.h new file mode 100644 index 00000000000..f4d51d80e91 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_timer.h @@ -0,0 +1,529 @@ +/**************************************************************************//** + * @file timer.h + * @version V1.01 + * @brief M251 series Timer driver header file + * + * @note + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __TIMER_H__ +#define __TIMER_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup TIMER_Driver TIMER Driver + @{ +*/ + +/** @addtogroup TIMER_EXPORTED_CONSTANTS TIMER Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* TIMER Operation Mode, External Counter and Capture Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TIMER_ONESHOT_MODE (0UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in one-shot mode */ +#define TIMER_PERIODIC_MODE (1UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in periodic mode */ +#define TIMER_TOGGLE_MODE (2UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in toggle-output mode */ +#define TIMER_CONTINUOUS_MODE (3UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in continuous counting mode */ + +#define TIMER_TOUT_PIN_FROM_TX (0UL << TIMER_CTL_TGLPINSEL_Pos) /*!< Timer toggle-output pin is from Tx pin */ +#define TIMER_TOUT_PIN_FROM_TX_EXT (1UL << TIMER_CTL_TGLPINSEL_Pos) /*!< Timer toggle-output pin is from Tx_EXT pin */ + +#define TIMER_CAPTURE_FREE_COUNTING_MODE (0UL << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< Timer capture event to get timer counter value */ +#define TIMER_CAPTURE_COUNTER_RESET_MODE (1UL << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< Timer capture event to reset timer counter */ + +#define TIMER_COUNTER_EVENT_FALLING (0UL << TIMER_EXTCTL_CNTPHASE_Pos) /*!< Counter increase on falling edge detection */ +#define TIMER_COUNTER_EVENT_RISING (1UL << TIMER_EXTCTL_CNTPHASE_Pos) /*!< Counter increase on rising edge detection */ + +#define TIMER_CAPTURE_EVENT_FALLING (0UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Falling edge detection to trigger capture event */ +#define TIMER_CAPTURE_EVENT_RISING (1UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Rising edge detection to trigger capture event */ +#define TIMER_CAPTURE_EVENT_FALLING_RISING (2UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Both falling and rising edge detection to trigger capture event, and first event at falling edge */ +#define TIMER_CAPTURE_EVENT_RISING_FALLING (3UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Both rising and falling edge detection to trigger capture event, and first event at rising edge */ +#define TIMER_CAPTURE_EVENT_GET_LOW_PERIOD (6UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< First capture event is at falling edge, follows are at at rising edge */ +#define TIMER_CAPTURE_EVENT_GET_HIGH_PERIOD (7UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< First capture event is at rising edge, follows are at at falling edge */ + +/* For new Trigger Source Selection */ +#define TIMER_TRGSEL_TIMEOUT_EVENT (0UL << TIMER_TRGCTL_TRGSSEL_Pos) +#define TIMER_TRGSEL_CAPTURE_EVENT (1UL << TIMER_TRGCTL_TRGSSEL_Pos) +#define TIMER_TRG_TO_PWM (TIMER_TRGCTL_TRGPWM_Msk) +#define TIMER_TRG_TO_EADC (TIMER_TRGCTL_TRGEADC_Msk) +#define TIMER_TRG_TO_PDMA (TIMER_TRGCTL_TRGPDMA_Msk) +#define TIMER_TRG_TO_DAC (TIMER_TRGCTL_TRGDAC_Msk) + +/* Capture Sourdce Selection */ +#define TIMER_CAPTURE_FROM_EXTERNAL (0UL << TIMER_CTL_CAPSRC_Pos) +#define TIMER_CAPTURE_FROM_INTERNAL (1UL << TIMER_CTL_CAPSRC_Pos) + +/* Capture Sourdce Divider */ +#define TIMER_CAPTURE_SRCDIV_1 (0UL << TIMER_EXTCTL_CAPDIVSCL_Pos) +#define TIMER_CAPTURE_SRCDIV_2 (1UL << TIMER_EXTCTL_CAPDIVSCL_Pos) +#define TIMER_CAPTURE_SRCDIV_4 (2UL << TIMER_EXTCTL_CAPDIVSCL_Pos) +#define TIMER_CAPTURE_SRCDIV_8 (3UL << TIMER_EXTCTL_CAPDIVSCL_Pos) +#define TIMER_CAPTURE_SRCDIV_16 (4UL << TIMER_EXTCTL_CAPDIVSCL_Pos) +#define TIMER_CAPTURE_SRCDIV_32 (5UL << TIMER_EXTCTL_CAPDIVSCL_Pos) +#define TIMER_CAPTURE_SRCDIV_64 (6UL << TIMER_EXTCTL_CAPDIVSCL_Pos) +#define TIMER_CAPTURE_SRCDIV_128 (7UL << TIMER_EXTCTL_CAPDIVSCL_Pos) +#define TIMER_CAPTURE_SRCDIV_256 (8UL << TIMER_EXTCTL_CAPDIVSCL_Pos) + +/* Internal Capture Sourdce Selection */ +#define TIMER_INTER_CAPTURE_FROM_ACMP0 (0UL << TIMER_EXTCTL_INTERCAPSEL_Pos) +#define TIMER_INTER_CAPTURE_FROM_ACMP1 (1UL << TIMER_EXTCTL_INTERCAPSEL_Pos) +#define TIMER_INTER_CAPTURE_FROM_HXT (2UL << TIMER_EXTCTL_INTERCAPSEL_Pos) +#define TIMER_INTER_CAPTURE_FROM_LXT (3UL << TIMER_EXTCTL_INTERCAPSEL_Pos) +#define TIMER_INTER_CAPTURE_FROM_HIRC (4UL << TIMER_EXTCTL_INTERCAPSEL_Pos) +#define TIMER_INTER_CAPTURE_FROM_LIRC (5UL << TIMER_EXTCTL_INTERCAPSEL_Pos) +#define TIMER_INTER_CAPTURE_FROM_MIRC (6UL << TIMER_EXTCTL_INTERCAPSEL_Pos) + +/*@}*/ /* end of group TIMER_EXPORTED_CONSTANTS */ + + +/** @addtogroup TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions + @{ +*/ + +/** + * @brief Set Timer Compared Value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Value Timer compare value. Valid values are between 2 to 0xFFFFFF. + * + * @return None + * + * @details This macro is used to set timer compared value to adjust timer time-out interval. + * @note 1. Never write 0x0 or 0x1 in this field, or the core will run into unknown state. \n + * 2. If update timer compared value in continuous counting mode, timer counter value will keep counting continuously. \n + * But if timer is operating at other modes, the timer up counter will restart counting and start from 0. + */ +#define TIMER_SET_CMP_VALUE(timer, u32Value) ((timer)->CMP = (u32Value)) + +/** + * @brief Set Timer Prescale Value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Value Timer prescale value. Valid values are between 0 to 0xFF. + * + * @return None + * + * @details This macro is used to set timer prescale value and timer source clock will be divided by (prescale + 1) \n + * before it is fed into timer. + */ +#define TIMER_SET_PRESCALE_VALUE(timer, u32Value) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_PSC_Msk) | (u32Value)) + + +/** + * @brief Check specify Timer Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Timer 24-bit up counter is inactive + * @retval 1 Timer 24-bit up counter is active + * + * @details This macro is used to check if specify Timer counter is inactive or active. + */ +#define TIMER_IS_ACTIVE(timer) (((timer)->CTL & TIMER_CTL_ACTSTS_Msk)? 1 : 0) + +/** + * @brief Select Toggle-output Pin + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32ToutSel Toggle-output pin selection, valid values are: + * - \ref TIMER_TOUT_PIN_FROM_TX + * - \ref TIMER_TOUT_PIN_FROM_TX_EXT + * + * @return None + * + * @details This macro is used to select timer toggle-output pin is output on Tx or Tx_EXT pin. + */ +#define TIMER_SELECT_TOUT_PIN(timer, u32ToutSel) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_TGLPINSEL_Msk) | (u32ToutSel)) + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void TIMER_Start(TIMER_T *timer); +__STATIC_INLINE void TIMER_Stop(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableWakeup(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableWakeup(TIMER_T *timer); +__STATIC_INLINE void TIMER_StartCapture(TIMER_T *timer); +__STATIC_INLINE void TIMER_StopCapture(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableInt(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableInt(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableCaptureInt(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableCaptureInt(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer); +__STATIC_INLINE void TIMER_ClearIntFlag(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer); +__STATIC_INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer); +__STATIC_INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetCounter(TIMER_T *timer); +__STATIC_INLINE void TIMER_ResetCounter(TIMER_T *timer); + +/** + * @brief Start Timer Counting + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to start Timer counting. + */ +__STATIC_INLINE void TIMER_Start(TIMER_T *timer) +{ + timer->CTL |= TIMER_CTL_CNTEN_Msk; +} + +/** + * @brief Stop Timer Counting + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to stop/suspend Timer counting. + */ +__STATIC_INLINE void TIMER_Stop(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_CNTEN_Msk; +} + +/** + * @brief Enable Timer Interrupt Wake-up Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the timer interrupt wake-up function and interrupt source could be time-out interrupt. + * @note To wake the system from Power-down mode, timer clock source must be ether LXT or LIRC. + */ +__STATIC_INLINE void TIMER_EnableWakeup(TIMER_T *timer) +{ + timer->CTL |= TIMER_CTL_WKEN_Msk; +} + +/** + * @brief Disable Timer Wake-up Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the timer interrupt wake-up function. + */ +__STATIC_INLINE void TIMER_DisableWakeup(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_WKEN_Msk; +} + +/** + * @brief Start Timer Capture Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to start Timer capture function. + */ +__STATIC_INLINE void TIMER_StartCapture(TIMER_T *timer) +{ + timer->EXTCTL |= TIMER_EXTCTL_CAPEN_Msk; +} + +/** + * @brief Stop Timer Capture Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to stop Timer capture function. + */ +__STATIC_INLINE void TIMER_StopCapture(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CAPEN_Msk; +} + +/** + * @brief Enable Capture Pin De-bounce + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the detect de-bounce function of capture pin. + */ +__STATIC_INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer) +{ + timer->EXTCTL |= TIMER_EXTCTL_CAPDBEN_Msk; +} + +/** + * @brief Disable Capture Pin De-bounce + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the detect de-bounce function of capture pin. + */ +__STATIC_INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CAPDBEN_Msk; +} + +/** + * @brief Enable Counter Pin De-bounce + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the detect de-bounce function of counter pin. + */ +__STATIC_INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer) +{ + timer->EXTCTL |= TIMER_EXTCTL_CNTDBEN_Msk; +} + +/** + * @brief Disable Counter Pin De-bounce + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the detect de-bounce function of counter pin. + */ +__STATIC_INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CNTDBEN_Msk; +} + +/** + * @brief Enable Timer Time-out Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the timer time-out interrupt function. + */ +__STATIC_INLINE void TIMER_EnableInt(TIMER_T *timer) +{ + timer->CTL |= TIMER_CTL_INTEN_Msk; +} + +/** + * @brief Disable Timer Time-out Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the timer time-out interrupt function. + */ +__STATIC_INLINE void TIMER_DisableInt(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_INTEN_Msk; +} + +/** + * @brief Enable Capture Trigger Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the timer capture trigger interrupt function. + */ +__STATIC_INLINE void TIMER_EnableCaptureInt(TIMER_T *timer) +{ + timer->EXTCTL |= TIMER_EXTCTL_CAPIEN_Msk; +} + +/** + * @brief Disable Capture Trigger Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the timer capture trigger interrupt function. + */ +__STATIC_INLINE void TIMER_DisableCaptureInt(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CAPIEN_Msk; +} + +/** + * @brief Get Timer Time-out Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Timer time-out interrupt did not occur + * @retval 1 Timer time-out interrupt occurred + * + * @details This function indicates timer time-out interrupt occurred or not. + */ +__STATIC_INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer) +{ + return ((timer->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1 : 0); +} + +/** + * @brief Clear Timer Time-out Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function clears timer time-out interrupt flag to 0. + */ +__STATIC_INLINE void TIMER_ClearIntFlag(TIMER_T *timer) +{ + timer->INTSTS = TIMER_INTSTS_TIF_Msk; +} + +/** + * @brief Get Timer Capture Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Timer capture interrupt did not occur + * @retval 1 Timer capture interrupt occurred + * + * @details This function indicates timer capture trigger interrupt occurred or not. + */ +__STATIC_INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer) +{ + return timer->EINTSTS; +} + +/** + * @brief Clear Timer Capture Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function clears timer capture trigger interrupt flag to 0. + */ +__STATIC_INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer) +{ + timer->EINTSTS = TIMER_EINTSTS_CAPIF_Msk; +} + +/** + * @brief Get Timer Wake-up Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Timer does not cause CPU wake-up + * @retval 1 Timer interrupt event cause CPU wake-up + * + * @details This function indicates timer interrupt event has waked up system or not. + */ +__STATIC_INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer) +{ + return (timer->INTSTS & TIMER_INTSTS_TWKF_Msk ? 1 : 0); +} + +/** + * @brief Clear Timer Wake-up Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function clears the timer wake-up system flag to 0. + */ +__STATIC_INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer) +{ + timer->INTSTS = TIMER_INTSTS_TWKF_Msk; +} + +/** + * @brief Get Capture value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return 24-bit Capture Value + * + * @details This function reports the current 24-bit timer capture value. + */ +__STATIC_INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer) +{ + return timer->CAP; +} + +/** + * @brief Get Counter value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return 24-bit Counter Value + * + * @details This function reports the current 24-bit timer counter value. + */ +__STATIC_INLINE uint32_t TIMER_GetCounter(TIMER_T *timer) +{ + return timer->CNT; +} + +/** + * @brief Reset Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to reset current counter value and internal prescale counter value. + */ +__STATIC_INLINE void TIMER_ResetCounter(TIMER_T *timer) +{ + timer->CNT = 0UL; + + while ((timer->CNT & TIMER_CNT_RSTACT_Msk) == TIMER_CNT_RSTACT_Msk) + { + ; + } +} + +uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq); +void TIMER_Close(TIMER_T *timer); +void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec); +void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge); +void TIMER_CaptureSelect(TIMER_T *timer, uint32_t u32Src); +void TIMER_DisableCapture(TIMER_T *timer); +void TIMER_SetTriggerSource(TIMER_T *timer, uint32_t u32Src); +void TIMER_SetTriggerTarget(TIMER_T *timer, uint32_t u32Mask); +void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge); +void TIMER_DisableEventCounter(TIMER_T *timer); +uint32_t TIMER_GetModuleClock(TIMER_T *timer); +void TIMER_EnableFreqCounter(TIMER_T *timer, uint32_t u32DropCount, uint32_t u32Timeout, uint32_t u32EnableInt); +void TIMER_DisableFreqCounter(TIMER_T *timer); + +/*@}*/ /* end of group TIMER_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group TIMER_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TIMER_H__ */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_timer_pwm.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_timer_pwm.h new file mode 100644 index 00000000000..5ee5ca7634f --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_timer_pwm.h @@ -0,0 +1,606 @@ +/**************************************************************************//** + * @file timer_pwm.h + * @version V1.01 + * @brief M251 series Timer PWM Controller(Timer PWM) driver header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __TIMER_PWM_H__ +#define __TIMER_PWM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup TIMER_PWM_Driver TIMER PWM Driver + @{ +*/ + +/** @addtogroup TIMER_PWM_EXPORTED_CONSTANTS TIMER PWM Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* TPWM Output Channel Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_CH0 (BIT0) /*!< Indicate PWMx_CH0 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* TPWM Output Channel Selection Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_TOUT_PIN_FROM_TX (BIT0) /*!< Indicate PWMx output to Tx pins \hideinitializer */ +#define TPWM_TOUT_PIN_FROM_TX_EXT (BIT8) /*!< Indicate PWMx output to Tx_ext pins \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* TPWM Counter Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_AUTO_RELOAD_MODE (0UL) /*!< Auto-reload mode \hideinitializer */ +#define TPWM_ONE_SHOT_MODE (1UL) /*!< One-shot mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* TPWM Trigger ADC/DAC/PDMA Source Select Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_TRIGGER_AT_PERIOD_POINT (0UL) /*!< Timer PWM trigger EADC while counter period point event occurred \hideinitializer */ +#define TPWM_TRIGGER_AT_COMPARE_POINT (1UL) /*!< Timer PWM trigger EADC while counter compare point event occurred \hideinitializer */ +#define TPWM_TRIGGER_AT_PERIOD_OR_COMPARE_POINT (2UL) /*!< Timer PWM trigger EADC while counter period or compare point event occurred \hideinitializer */ + +/*@}*/ /* end of group TIMER_PWM_EXPORTED_CONSTANTS */ + + +/** @addtogroup TIMER_PWM_EXPORTED_FUNCTIONS TIMER PWM Exported Functions + @{ +*/ + +/** + * @brief Enable TPWM Counter Mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable specified Timer channel as PWM counter mode, then timer counter mode is invalid. + * @note All registers about time counter function will be cleared to 0 and timer clock source will be changed to PCLKx automatically after executing this macro. + * \hideinitializer + */ +#define TPWM_ENABLE_PWM_MODE(timer) ((timer)->CTL |= TIMER_CTL_FUNCSEL_Msk) + +/** + * @brief Disable TPWM Counter Mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to disable specified Timer channel as PWM counter mode, then timer counter mode is available. + * @note All registers about TPWM counter function will be cleared to 0 after executing this macro. + * \hideinitializer + */ +#define TPWM_DISABLE_PWM_MODE(timer) ((timer)->CTL &= ~TIMER_CTL_FUNCSEL_Msk) + +/** + * @brief Start TPWM Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable TPWM generator and start counter counting. + * \hideinitializer + */ +#define TPWM_START_COUNTER(timer) ((timer)->PWMCTL |= TIMER_PWMCTL_CNTEN_Msk) + +/** + * @brief Stop TPWM Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to stop TPWM counter after current period is completed. + * \hideinitializer + */ +#define TPWM_STOP_COUNTER(timer) ((timer)->PWMPERIOD = 0x0UL) + +/** + * @brief Set Counter Clock Prescaler + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 0x0~0xFF. + * + * @return None + * + * @details This macro is used to set the prescaler of specified TIMER PWM. + * @note If prescaler is 0, then there is no scaling in counter clock source. + * \hideinitializer + */ +#define TPWM_SET_PRESCALER(timer, u32Prescaler) ((timer)->PWMCLKPSC = (u32Prescaler)) + +/** + * @brief Get Counter Clock Prescaler + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return Target prescaler setting, CLKPSC (TIMERx_PWMCLKPSC[7:0]) + * + * @details Get the prescaler setting, the target counter clock divider is (CLKPSC + 1). + * \hideinitializer + */ +#define TPWM_GET_PRESCALER(timer) ((timer)->PWMCLKPSC) + +/** + * @brief Set Counter Period + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] u32Period Period of specified channel. Valid values are between 0x0~0xFFFF. + * + * @return None + * + * @details This macro is used to set the period of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_SET_PERIOD(timer, u32Period) ((timer)->PWMPERIOD = (u32Period)) + +/** + * @brief Get Counter Period + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return Target period setting, PERIOD (TIMERx_PWMPERIOD[15:0]) + * + * @details This macro is used to get the period of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_GET_PERIOD(timer) ((timer)->PWMPERIOD) + +/** + * @brief Set Comparator Value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] u32Cmp Comparator of specified channel. Valid values are between 0x0~0xFFFF. + * + * @return None + * + * @details This macro is used to set the comparator value of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_SET_CMPDAT(timer, u32Cmp) ((timer)->PWMCMPDAT = (u32Cmp)) + +/** + * @brief Get Comparator Value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return Target comparator setting, CMPDAT (TIMERx_PWMCMPDAT[15:0]) + * + * @details This macro is used to get the comparator value of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_GET_CMPDAT(timer) ((timer)->PWMCMPDAT) + +/** + * @brief Clear Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to clear counter of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_CLEAR_COUNTER(timer) ((timer)->PWMCNTCLR = TIMER_PWMCNTCLR_CNTCLR_Msk) + +/** + * @brief Enable Output Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] u32Channel Enable specified channel output function. Valid values are: + * - \ref TPWM_CH0 + * + * @return None + * + * @details This macro is used to enable output function of specified output pins. + * @note If the corresponding bit in u32ChMask parameter is 0, then output function will be disabled in this channel. + * \hideinitializer + */ +#define TPWM_ENABLE_OUTPUT(timer, u32Channel) ((timer)->PWMPOCTL = (u32Channel)) + +/** + * @brief Select Toggle-output Pin + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32ToutSel Toggle-output pin selection, valid values are: + * - \ref TPWM_TOUT_PIN_FROM_TX + * - \ref TPWM_TOUT_PIN_FROM_TX_EXT + * + * @return None + * + * @details This macro is used to select TPWM toggle-output pin is output on Tx or Tx_EXT pin. + */ +#define TPWM_SELECT_TOUT_PIN(timer, u32ToutSel) ((timer)->PWMPOCTL = ((timer)->PWMPOCTL & ~TIMER_PWMPOCTL_POSEL_Msk) | (u32ToutSel)) + +/** + * @brief Set Output Inverse + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] u32Channel Set specified channel output is inversed or not. Valid values are: + * - \ref TPWM_CH0 + * + * @return None + * + * @details This macro is used to enable output inverse of specified output pins. + * @note If u32ChMask parameter is 0, then output inverse function will be disabled. + * \hideinitializer + */ +#define TPWM_SET_OUTPUT_INVERSE(timer, u32Channel) ((timer)->PWMPOLCTL = (u32Channel)) + +/** + * @brief Enable Period Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable the period event interrupt function. + * \hideinitializer + */ +#define TPWM_ENABLE_PERIOD_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_PIEN_Msk) + +/** + * @brief Disable Period Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to disable the period event interrupt function. + * \hideinitializer + */ +#define TPWM_DISABLE_PERIOD_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_PIEN_Msk) + +/** + * @brief Get Period Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Period event interrupt did not occur + * @retval 1 Period event interrupt occurred + * + * @details This macro indicates period event occurred or not. + * \hideinitializer + */ +#define TPWM_GET_PERIOD_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_PIF_Msk)? 1 : 0) + +/** + * @brief Clear Period Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro clears period event interrupt flag. + * \hideinitializer + */ +#define TPWM_CLEAR_PERIOD_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_PIF_Msk) + +/** + * @brief Enable Compare Up Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable the compare up event interrupt function. + * \hideinitializer + */ +#define TPWM_ENABLE_CMP_UP_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_CMPUIEN_Msk) + +/** + * @brief Disable Compare Up Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to disable the compare up event interrupt function. + * \hideinitializer + */ +#define TPWM_DISABLE_CMP_UP_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_CMPUIEN_Msk) + +/** + * @brief Get Compare Up Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Compare up event interrupt did not occur + * @retval 1 Compare up event interrupt occurred + * + * @details This macro indicates compare up event occurred or not. + * \hideinitializer + */ +#define TPWM_GET_CMP_UP_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_CMPUIF_Msk)? 1 : 0) + +/** + * @brief Clear Compare Up Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro clears compare up event interrupt flag. + * \hideinitializer + */ +#define TPWM_CLEAR_CMP_UP_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_CMPUIF_Msk) + +/** + * @brief Get Counter Reach Maximum Count Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Timer PWM counter never counts to maximum value + * @retval 1 Timer PWM counter counts to maximum value, 0xFFFF + * + * @details This macro indicates Timer PWM counter has count to 0xFFFF or not. + * \hideinitializer + */ +#define TPWM_GET_REACH_MAX_CNT_STATUS(timer) (((timer)->PWMSTATUS & TIMER_PWMSTATUS_CNTMAXF_Msk)? 1 : 0) + +/** + * @brief Clear Counter Reach Maximum Count Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro clears reach maximum count status. + * \hideinitializer + */ +#define TPWM_CLEAR_REACH_MAX_CNT_STATUS(timer) ((timer)->PWMSTATUS = TIMER_PWMSTATUS_CNTMAXF_Msk) + +/** + * @brief Get Trigger ADC Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Trigger ADC start conversion is not occur + * @retval 1 Specified counter event has trigger ADC start conversion + * + * @details This macro is used to indicate TPWM counter event has triggered ADC start conversion. + * \hideinitializer + */ +#define TPWM_GET_TRG_ADC_STATUS(timer) (((timer)->PWMSTATUS & TIMER_PWMSTATUS_EADCTRGF_Msk)? 1 : 0) + +/** + * @brief Clear Trigger ADC Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to clear TPWM counter event trigger ADC status. + * \hideinitializer + */ +#define TPWM_CLEAR_TRG_ADC_STATUS(timer) ((timer)->PWMSTATUS = TIMER_PWMSTATUS_EADCTRGF_Msk) + +/** + * @brief Get Trigger DAC Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Trigger DAC start conversion is not occur + * @retval 1 Specified counter event has trigger DAC start conversion + * + * @details This macro is used to indicate TPWM counter event has triggered DAC start conversion. + * \hideinitializer + */ +#define TPWM_GET_TRG_DAC_STATUS(timer) (((timer)->PWMSTATUS & TIMER_PWMSTATUS_DACTRGF_Msk)? 1 : 0) + +/** + * @brief Clear Trigger DAC Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to clear TPWM counter event trigger DAC status. + * \hideinitializer + */ +#define TPWM_CLEAR_TRG_DAC_STATUS(timer) ((timer)->PWMSTATUS = TIMER_PWMSTATUS_DACTRGF_Msk) + +/** + * @brief Get Trigger PDMA Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Trigger PDMA start conversion is not occur + * @retval 1 Specified counter event has trigger PDMA start conversion + * + * @details This macro is used to indicate TPWM counter event has triggered PDMA start conversion. + * \hideinitializer + */ +#define TPWM_GET_TRG_PDMA_STATUS(timer) (((timer)->PWMSTATUS & TIMER_PWMSTATUS_PDMATRGF_Msk)? 1 : 0) + +/** + * @brief Clear Trigger PDMA Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to clear TPWM counter event trigger PDMA status. + * \hideinitializer + */ +#define TPWM_CLEAR_TRG_PDMA_STATUS(timer) ((timer)->PWMSTATUS = TIMER_PWMSTATUS_PDMATRGF_Msk) + +uint32_t TPWM_ConfigOutputFreqAndDuty(TIMER_T *timer, uint32_t u32Frequency, uint32_t u32DutyCycle); +void TPWM_EnableCounter(TIMER_T *timer); +void TPWM_DisableCounter(TIMER_T *timer); +void TPWM_EnableTrigger(TIMER_T *timer, uint32_t u32TargetMask, uint32_t u32Condition); +void TPWM_DisableTrigger(TIMER_T *timer, uint32_t u32TargetMask); + +/** + * @brief Enable Trigger ADC + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Condition The condition to trigger ADC. It could be one of following conditions: + * - \ref TPWM_TRIGGER_AT_PERIOD_POINT + * - \ref TPWM_TRIGGER_AT_COMPARE_POINT + * - \ref TPWM_TRIGGER_AT_PERIOD_OR_COMPARE_POINT + * @return None + * + * @details This function is used to enable specified counter compare event to trigger ADC. + */ +#define TPWM_EnableTriggerADC(timer, u32Condition) TPWM_EnableTrigger(timer, TIMER_PWMTRGCTL_PWMTRGEADC_Msk, u32Condition) + +/** + * @brief Disable Trigger ADC + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable counter compare event to trigger ADC. + */ +#define TPWM_DisableTriggerADC(timer) TPWM_DisableTrigger(timer, TIMER_PWMTRGCTL_PWMTRGEADC_Msk) + +/** + * @brief Enable Trigger DAC + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Condition The condition to trigger DAC. It could be one of following conditions: + * - \ref TPWM_TRIGGER_AT_PERIOD_POINT + * - \ref TPWM_TRIGGER_AT_COMPARE_POINT + * - \ref TPWM_TRIGGER_AT_PERIOD_OR_COMPARE_POINT + * @return None + * + * @details This function is used to enable specified counter compare event to trigger DAC. + */ +#define TPWM_EnableTriggerDAC(timer, u32Condition) TPWM_EnableTrigger(timer, TIMER_PWMTRGCTL_PWMTRGDAC_Msk, u32Condition) + +/** + * @brief Disable Trigger DAC + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable counter compare event to trigger DAC. + */ +#define TPWM_DisableTriggerDAC(timer) TPWM_DisableTrigger(timer, TIMER_PWMTRGCTL_PWMTRGDAC_Msk) + +/** + * @brief Enable Trigger PDMA + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Condition The condition to trigger PDMA. It could be one of following conditions: + * - \ref TPWM_TRIGGER_AT_PERIOD_POINT + * - \ref TPWM_TRIGGER_AT_COMPARE_POINT + * - \ref TPWM_TRIGGER_AT_PERIOD_OR_COMPARE_POINT + * @return None + * + * @details This function is used to enable specified counter compare event to trigger PDMA. + */ +#define TPWM_EnableTriggerPDMA(timer, u32Condition) TPWM_EnableTrigger(timer, TIMER_PWMTRGCTL_PWMTRGPDMA_Msk, u32Condition) + +/** + * @brief Disable Trigger PDMA + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable counter compare event to trigger PDMA. + */ +#define TPWM_DisableTriggerPDMA(timer) TPWM_DisableTrigger(timer, TIMER_PWMTRGCTL_PWMTRGPDMA_Msk) + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void TPWM_EnableWakeup(TIMER_T *timer); +__STATIC_INLINE void TPWM_DisableWakeup(TIMER_T *timer); +__STATIC_INLINE uint32_t TPWM_GetWakeupFlag(TIMER_T *timer); +__STATIC_INLINE void TPWM_ClearWakeupFlag(TIMER_T *timer); + +/** + * @brief Enable TPWM Interrupt Wake-up Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the TPWM interrupt Wake-up function and interrupt source could be period interrupt, \n + * or compare interrupt. + * @note To wake the system from Power-down mode, PCLKx source must be ether LXT or LIRC. + * \hideinitializer + */ +__STATIC_INLINE void TPWM_EnableWakeup(TIMER_T *timer) +{ + timer->PWMCTL |= TIMER_PWMCTL_PWMINTWKEN_Msk; +} + +/** + * @brief Disable TPWM Interrupt Wake-up Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the TPWM interrupt Wake-up function. + * \hideinitializer + */ +__STATIC_INLINE void TPWM_DisableWakeup(TIMER_T *timer) +{ + timer->PWMCTL &= ~TIMER_PWMCTL_PWMINTWKEN_Msk; +} + +/** + * @brief Get TPWM Wake-up Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 TPWM does not cause CPU wake-up + * @retval 1 TPWM interrupt event cause CPU wake-up + * + * @details This function indicates TPWM interrupt event has waked up system or not. + * \hideinitializer + */ +__STATIC_INLINE uint32_t TPWM_GetWakeupFlag(TIMER_T *timer) +{ + return ((timer->PWMSTATUS & TIMER_PWMSTATUS_PWMINTWKF_Msk)? 1 : 0); +} + +/** + * @brief Clear TPWM Wake-up Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function clears TPWM Wake-up flag. + * \hideinitializer + */ +__STATIC_INLINE void TPWM_ClearWakeupFlag(TIMER_T *timer) +{ + timer->PWMSTATUS = TIMER_PWMSTATUS_PWMINTWKF_Msk; +} + +/*@}*/ /* end of group TIMER_PWM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group TIMER_PWM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TIMER_PWM_H__ */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_uart.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_uart.h new file mode 100644 index 00000000000..a983567d9a3 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_uart.h @@ -0,0 +1,500 @@ +/**************************************************************************** + * @file uart.h + * @version V1.00 + * @brief M251 series UART driver source file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __UART_H__ +#define __UART_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup UART_Driver UART Driver + @{ +*/ + +/** @addtogroup UART_EXPORTED_CONSTANTS UART Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* UART FIFO size constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ + +#define UART0_FIFO_SIZE 16ul /*!< UART0 supports separated receive/transmit 16/16 bytes entry FIFO \hideinitializer */ +#define UART1_FIFO_SIZE 16ul /*!< UART1 supports separated receive/transmit 16/16 bytes entry FIFO \hideinitializer */ +#define UART2_FIFO_SIZE 16ul /*!< UART2 supports separated receive/transmit 16/16 bytes entry FIFO \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* UART_FIFO constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ + +#define UART_FIFO_RFITL_1BYTE (0x0ul << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 1 byte \hideinitializer */ +#define UART_FIFO_RFITL_4BYTES (0x1ul << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 4 bytes \hideinitializer */ +#define UART_FIFO_RFITL_8BYTES (0x2ul << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 8 bytes \hideinitializer */ +#define UART_FIFO_RFITL_14BYTES (0x3ul << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 14 bytes \hideinitializer */ + +#define UART_FIFO_RTSTRGLV_1BYTE (0x0ul << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 1 byte \hideinitializer */ +#define UART_FIFO_RTSTRGLV_4BYTES (0x1ul << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 4 bytes \hideinitializer */ +#define UART_FIFO_RTSTRGLV_8BYTES (0x2ul << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 8 bytes \hideinitializer */ +#define UART_FIFO_RTSTRGLV_14BYTES (0x3ul << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 14 bytes \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* UART_LINE constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UART_WORD_LEN_5 (0ul) /*!< UART_LINE setting to set UART word length to 5 bits \hideinitializer */ +#define UART_WORD_LEN_6 (1ul) /*!< UART_LINE setting to set UART word length to 6 bits \hideinitializer */ +#define UART_WORD_LEN_7 (2ul) /*!< UART_LINE setting to set UART word length to 7 bits \hideinitializer */ +#define UART_WORD_LEN_8 (3ul) /*!< UART_LINE setting to set UART word length to 8 bits \hideinitializer */ + +#define UART_PARITY_NONE (0x0ul << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as no parity \hideinitializer */ +#define UART_PARITY_ODD (0x1ul << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as odd parity \hideinitializer */ +#define UART_PARITY_EVEN (0x3ul << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as even parity \hideinitializer */ +#define UART_PARITY_MARK (0x5ul << UART_LINE_PBE_Pos) /*!< UART_LINE setting to keep parity bit as '1' \hideinitializer */ +#define UART_PARITY_SPACE (0x7ul << UART_LINE_PBE_Pos) /*!< UART_LINE setting to keep parity bit as '0' \hideinitializer */ + +#define UART_STOP_BIT_1 (0x0ul << UART_LINE_NSB_Pos) /*!< UART_LINE setting for one stop bit \hideinitializer */ +#define UART_STOP_BIT_1_5 (0x1ul << UART_LINE_NSB_Pos) /*!< UART_LINE setting for 1.5 stop bit when 5-bit word length \hideinitializer */ +#define UART_STOP_BIT_2 (0x1ul << UART_LINE_NSB_Pos) /*!< UART_LINE setting for two stop bit when 6, 7, 8-bit word length \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* UART RTS ACTIVE LEVEL constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UART_RTS_IS_LOW_LEV_ACTIVE (0x1ul << UART_MODEM_RTSACTLV_Pos) /*!< Set RTS is Low Level Active \hideinitializer */ +#define UART_RTS_IS_HIGH_LEV_ACTIVE (0x0ul << UART_MODEM_RTSACTLV_Pos) /*!< Set RTS is High Level Active \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* UART_IRDA constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UART_IRDA_TXEN (0x1ul << UART_IRDA_TXEN_Pos) /*!< Set IrDA function Tx mode \hideinitializer */ +#define UART_IRDA_RXEN (0x0ul << UART_IRDA_TXEN_Pos) /*!< Set IrDA function Rx mode \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* UART_FUNCSEL constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UART_FUNCSEL_UART (0x0ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set UART Function (Default) \hideinitializer */ +#define UART_FUNCSEL_LIN (0x1ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set LIN Function \hideinitializer */ +#define UART_FUNCSEL_IrDA (0x2ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set IrDA Function \hideinitializer */ +#define UART_FUNCSEL_RS485 (0x3ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set RS485 Function \hideinitializer */ +#define UART_FUNCSEL_SINGLE_WIRE (0x4ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set Single Wire Function \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* UART_LINCTL constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UART_LINCTL_BRKFL(x) (((x)-1) << UART_LINCTL_BRKFL_Pos) /*!< UART_LINCTL setting to set LIN Break Field Length, x = 10 ~ 15, default value is 12 \hideinitializer */ +#define UART_LINCTL_BSL(x) (((x)-1) << UART_LINCTL_BSL_Pos) /*!< UART_LINCTL setting to set LIN Break/Sync Delimiter Length, x = 1 ~ 4 \hideinitializer */ +#define UART_LINCTL_HSEL_BREAK (0x0UL << UART_LINCTL_HSEL_Pos) /*!< UART_LINCTL setting to set LIN Header Select to break field \hideinitializer */ +#define UART_LINCTL_HSEL_BREAK_SYNC (0x1UL << UART_LINCTL_HSEL_Pos) /*!< UART_LINCTL setting to set LIN Header Select to break field and sync field \hideinitializer */ +#define UART_LINCTL_HSEL_BREAK_SYNC_ID (0x2UL << UART_LINCTL_HSEL_Pos) /*!< UART_LINCTL setting to set LIN Header Select to break field, sync field and ID field \hideinitializer */ +#define UART_LINCTL_PID(x) ((x) << UART_LINCTL_PID_Pos) /*!< UART_LINCTL setting to set LIN PID value \hideinitializer */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* UART BAUDRATE MODE constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UART_BAUD_MODE0 (0ul) /*!< Set UART Baudrate Mode is Mode0 \hideinitializer */ +#define UART_BAUD_MODE2 (UART_BAUD_BAUDM1_Msk | UART_BAUD_BAUDM0_Msk) /*!< Set UART Baudrate Mode is Mode2 \hideinitializer */ + + +/*@}*/ /* end of group UART_EXPORTED_CONSTANTS */ + + +/** @addtogroup UART_EXPORTED_FUNCTIONS UART Exported Functions + @{ +*/ + + +/** + * @brief Calculate UART baudrate mode0 divider + * + * @param[in] u32SrcFreq UART clock frequency + * @param[in] u32BaudRate Baudrate of UART module + * + * @return UART baudrate mode0 divider + * + * @details This macro calculate UART baudrate mode0 divider. + * \hideinitializer + */ +#define UART_BAUD_MODE0_DIVIDER(u32SrcFreq, u32BaudRate) ((((u32SrcFreq) + ((u32BaudRate)*8ul)) / (u32BaudRate) >> 4ul)-2ul) + + +/** + * @brief Calculate UART baudrate mode2 divider + * + * @param[in] u32SrcFreq UART clock frequency + * @param[in] u32BaudRate Baudrate of UART module + * + * @return UART baudrate mode2 divider + * + * @details This macro calculate UART baudrate mode2 divider. + * \hideinitializer + */ +#define UART_BAUD_MODE2_DIVIDER(u32SrcFreq, u32BaudRate) ((((u32SrcFreq) + ((u32BaudRate)/2ul)) / (u32BaudRate))-2ul) + + +/** + * @brief Write UART data + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u8Data Data byte to transmit. + * + * @return None + * + * @details This macro write Data to Tx data register. + * \hideinitializer + */ +#define UART_WRITE(uart, u8Data) ((uart)->DAT = (u8Data)) + + +/** + * @brief Read UART data + * + * @param[in] uart The pointer of the specified UART module + * + * @return The oldest data byte in RX FIFO. + * + * @details This macro read Rx data register. + * \hideinitializer + */ +#define UART_READ(uart) ((uart)->DAT) + + +/** + * @brief Get Tx empty + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Tx FIFO is not empty + * @retval >=1 Tx FIFO is empty + * + * @details This macro get Transmitter FIFO empty register value. + * \hideinitializer + */ +#define UART_GET_TX_EMPTY(uart) ((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTY_Msk) + + +/** + * @brief Get Rx empty + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Rx FIFO is not empty + * @retval >=1 Rx FIFO is empty + * + * @details This macro get Receiver FIFO empty register value. + * \hideinitializer + */ +#define UART_GET_RX_EMPTY(uart) ((uart)->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) + + +/** + * @brief Check specified UART port transmission is over. + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Tx transmission is not over + * @retval 1 Tx transmission is over + * + * @details This macro return Transmitter Empty Flag register bit value. + * It indicates if specified UART port transmission is over nor not. + * \hideinitializer + */ +#define UART_IS_TX_EMPTY(uart) (((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos) + + +/** + * @brief Wait specified UART port transmission is over + * + * @param[in] uart The pointer of the specified UART module + * + * @return None + * + * @details This macro wait specified UART port transmission is over. + * \hideinitializer + */ +#define UART_WAIT_TX_EMPTY(uart) while(!((((uart)->FIFOSTS) & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos)) + + +/** + * @brief Check RX is ready or not + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 The number of bytes in the RX FIFO is less than the RFITL + * @retval 1 The number of bytes in the RX FIFO equals or larger than RFITL + * + * @details This macro check receive data available interrupt flag is set or not. + * \hideinitializer + */ +#define UART_IS_RX_READY(uart) (((uart)->INTSTS & UART_INTSTS_RDAIF_Msk)>>UART_INTSTS_RDAIF_Pos) + + +/** + * @brief Check TX FIFO is full or not + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 1 TX FIFO is full + * @retval 0 TX FIFO is not full + * + * @details This macro check TX FIFO is full or not. + * \hideinitializer + */ +#define UART_IS_TX_FULL(uart) (((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)>>UART_FIFOSTS_TXFULL_Pos) + + +/** + * @brief Check RX FIFO is full or not + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 1 RX FIFO is full + * @retval 0 RX FIFO is not full + * + * @details This macro check RX FIFO is full or not. + * \hideinitializer + */ +#define UART_IS_RX_FULL(uart) (((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)>>UART_FIFOSTS_RXFULL_Pos) + + +/** + * @brief Get Tx full register value + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Tx FIFO is not full. + * @retval >=1 Tx FIFO is full. + * + * @details This macro get Tx full register value. + * \hideinitializer + */ +#define UART_GET_TX_FULL(uart) ((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) + + +/** + * @brief Get Rx full register value + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Rx FIFO is not full. + * @retval >=1 Rx FIFO is full. + * + * @details This macro get Rx full register value. + * \hideinitializer + */ +#define UART_GET_RX_FULL(uart) ((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk) + +/** + * @brief Rx Idel Status register value + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Rx is busy. + * @retval 1 Rx is Idel(Default) + * + * @details This macro get Rx Idel Status register value. + * \hideinitializer + */ +#define UART_RX_IDEL(uart) (((uart)->FIFOSTS & UART_FIFOSTS_RXIDLE_Msk )>> UART_FIFOSTS_RXIDLE_Pos) + + +/** + * @brief Enable specified UART interrupt + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UART_INTEN_TXENDIEN_Msk : Transmitter Empty interrupt + * - \ref UART_INTEN_ABRIEN_Msk : Auto baud rate interrupt + * - \ref UART_INTEN_SWBEIEN_Msk : Single-wire bit error detection interrupt + * - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt + * - \ref UART_INTEN_WKIEN_Msk : Wakeup interrupt + * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt + * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt + * - \ref UART_INTEN_MODEMIEN_Msk : Modem interrupt + * - \ref UART_INTEN_RLSIEN_Msk : Rx Line status interrupt + * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt + * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt + * + * @return None + * + * @details This macro enable specified UART interrupt. + * \hideinitializer + */ +#define UART_ENABLE_INT(uart, u32IntSel) ((uart)->INTEN |= (u32IntSel)) + + +/** + * @brief Disable specified UART interrupt + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UART_INTEN_TXENDIEN_Msk : Transmitter Empty interrupt + * - \ref UART_INTEN_ABRIEN_Msk : Auto baud rate interrupt + * - \ref UART_INTEN_SWBEIEN_Msk : Single-wire bit error detection interrupt + * - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt + * - \ref UART_INTEN_WKIEN_Msk : Wakeup interrupt + * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt + * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt + * - \ref UART_INTEN_MODEMIEN_Msk : Modem status interrupt + * - \ref UART_INTEN_RLSIEN_Msk : Receive Line status interrupt + * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt + * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt + * + * @return None + * + * @details This macro enable specified UART interrupt. + * \hideinitializer + */ +#define UART_DISABLE_INT(uart, u32IntSel) ((uart)->INTEN &= ~ (u32IntSel)) + + +/** + * @brief Get specified interrupt flag/status + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref UART_INTSTS_ABRINT_Msk : Auto-baud Rate Interrupt Indicator + * - \ref UART_INTSTS_TXENDINT_Msk : Transmitter Empty Interrupt Indicator + * - \ref UART_INTSTS_HWBUFEINT_Msk : In PDMA Mode, Buffer Error Interrupt Indicator + * - \ref UART_INTSTS_HWTOINT_Msk : In PDMA Mode, Time-out Interrupt Indicator + * - \ref UART_INTSTS_HWMODINT_Msk : In PDMA Mode, MODEM Status Interrupt Indicator + * - \ref UART_INTSTS_HWRLSINT_Msk : In PDMA Mode, Receive Line Status Interrupt Indicator + * - \ref UART_INTSTS_SWBEINT_Msk : In Single-wire Mode, Bit Error Detect Interrupt Indicator + * - \ref UART_INTSTS_TXENDIF_Msk : Transmitter Empty Interrupt Flag + * - \ref UART_INTSTS_HWBUFEIF_Msk : In PDMA Mode, Buffer Error Interrupt Flag + * - \ref UART_INTSTS_HWTOIF_Msk : In PDMA Mode, Time-out Interrupt Flag + * - \ref UART_INTSTS_HWMODIF_Msk : In PDMA Mode, MODEM Interrupt Flag + * - \ref UART_INTSTS_HWRLSIF_Msk : In PDMA Mode, Receive Line Status Flag + * - \ref UART_INTSTS_SWBEIF_Msk : In Single-wire Mode, Bit Error Detection Interrupt Flag + * - \ref UART_INTSTS_LININT_Msk : LIN Bus Interrupt Indicator + * - \ref UART_INTSTS_WKINT_Msk : Wake-up Interrupt Indicator + * - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error Interrupt Indicator + * - \ref UART_INTSTS_RXTOINT_Msk : Time-out Interrupt Indicator + * - \ref UART_INTSTS_MODEMINT_Msk : Modem Status Interrupt Indicator + * - \ref UART_INTSTS_RLSINT_Msk : Receive Line Status Interrupt Indicator + * - \ref UART_INTSTS_THREINT_Msk : Transmit Holding Register Empty Interrupt Indicator + * - \ref UART_INTSTS_RDAINT_Msk : Receive Data Available Interrupt Indicator + * - \ref UART_INTSTS_LINIF_Msk : LIN Bus Flag + * - \ref UART_INTSTS_WKIF_Msk : Wake-up Interrupt Flag + * - \ref UART_INTSTS_BUFERRIF_Msk : Buffer Error Interrupt Flag + * - \ref UART_INTSTS_RXTOIF_Msk : Rx Time-out Interrupt Flag + * - \ref UART_INTSTS_MODEMIF_Msk : Modem Interrupt Flag + * - \ref UART_INTSTS_RLSIF_Msk : Receive Line Status Interrupt Flag + * - \ref UART_INTSTS_THREIF_Msk : Tx Empty Interrupt Flag + * - \ref UART_INTSTS_RDAIF_Msk : Rx Ready Interrupt Flag + * + * @retval 0 The specified interrupt is not happened. + * 1 The specified interrupt is happened. + * + * @details This macro get specified interrupt flag or interrupt indicator status. + * \hideinitializer + */ +#define UART_GET_INT_FLAG(uart,u32IntTypeFlag) (((uart)->INTSTS & (u32IntTypeFlag))?1:0) + + +/** + * @brief Clear RS-485 Address Byte Detection Flag + * + * @param[in] uart The pointer of the specified UART module + * + * @return None + * + * @details This macro clear RS-485 address byte detection flag. + * \hideinitializer + */ +#define UART_RS485_CLEAR_ADDR_FLAG(uart) ((uart)->FIFOSTS = UART_FIFOSTS_ADDRDETF_Msk) + + +/** + * @brief Get RS-485 Address Byte Detection Flag + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Receiver detects a data that is not an address bit. + * @retval 1 Receiver detects a data that is an address bit. + * + * @details This macro get RS-485 address byte detection flag. + * \hideinitializer + */ +#define UART_RS485_GET_ADDR_FLAG(uart) (((uart)->FIFOSTS & UART_FIFOSTS_ADDRDETF_Msk) >> UART_FIFOSTS_ADDRDETF_Pos) + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void UART_CLEAR_RTS(UART_T *uart); +__STATIC_INLINE void UART_SET_RTS(UART_T *uart); + + +/** + * @brief Set RTS pin to low + * + * @param[in] uart The pointer of the specified UART module + * + * @return None + * + * @details This macro set RTS pin to low. + */ +__STATIC_INLINE void UART_CLEAR_RTS(UART_T *uart) +{ + uart->MODEM |= UART_MODEM_RTSACTLV_Msk; + uart->MODEM &= ~UART_MODEM_RTS_Msk; +} + + +/** + * @brief Set RTS pin to high + * + * @param[in] uart The pointer of the specified UART module + * + * @return None + * + * @details This macro set RTS pin to high. + */ +__STATIC_INLINE void UART_SET_RTS(UART_T *uart) +{ + uart->MODEM |= UART_MODEM_RTSACTLV_Msk | UART_MODEM_RTS_Msk; +} + + +void UART_ClearIntFlag(UART_T *uart, uint32_t u32InterruptFlag); +void UART_Close(UART_T *uart); +void UART_DisableFlowCtrl(UART_T *uart); +void UART_DisableInt(UART_T *uart, uint32_t u32InterruptFlag); +void UART_EnableFlowCtrl(UART_T *uart); +void UART_EnableInt(UART_T *uart, uint32_t u32InterruptFlag); +void UART_Open(UART_T *uart, uint32_t u32BaudRate); +uint32_t UART_Read(UART_T *uart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes); +void UART_SetLine_Config(UART_T *uart, uint32_t u32BaudRate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits); +void UART_SetTimeoutCnt(UART_T *uart, uint32_t u32TOC); +void UART_SelectIrDAMode(UART_T *uart, uint32_t u32BuadRate, uint32_t u32Direction); +void UART_SelectRS485Mode(UART_T *uart, uint32_t u32Mode, uint32_t u32Addr); +void UART_SelectLINMode(UART_T *uart, uint32_t u32Mode, uint32_t u32BreakLength); +uint32_t UART_Write(UART_T *uart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes); +void UART_SelectSingleWireMode(UART_T *uart); + + + +/*@}*/ /* end of group UART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group UART_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /*__UART_H__*/ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_usbd.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_usbd.h new file mode 100644 index 00000000000..e4379de1d16 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_usbd.h @@ -0,0 +1,700 @@ +/****************************************************************************** + * @file usbd.h + * @version V0.10 + * @brief M251 series USB driver header file + * + * @copyrightt (C) 2017 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __USBD_H__ +#define __USBD_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/*!< Definition for enabling Link Power Management(LPM) function. + LPM related handler will raise after LPM event happen. + if bcdUSB >= 0x0201, USB version is equal or higher than 2.1, + OS(Windows) will issue "get BOS descriptor" request to check the support of LPM. + + Notice: + If bcdUSB >= 0x0201, where USB version is equal or higher than 2.1, + WIN8 ~ WIN10 will fail to enumerate the device if device stalls the "get BOS descriptor" request. + WIN7 can still enumerate this device even though the "get BOS descriptor" request been stalled. + +*/ +//#define SUPPORT_LPM + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USBD_Driver USBD Driver + @{ +*/ + +/** @addtogroup USBD_EXPORTED_STRUCTS USBD Exported Structs + @{ +*/ +typedef struct s_usbd_info +{ + uint8_t *gu8DevDesc; /*!< Pointer for USB Device Descriptor */ + uint8_t *gu8ConfigDesc; /*!< Pointer for USB Configuration Descriptor */ + uint8_t **gu8StringDesc; /*!< Pointer for USB String Descriptor pointers */ + uint8_t **gu8HidReportDesc; /*!< Pointer for USB HID Report Descriptor */ + uint8_t *gu8BosDesc; /*!< Pointer for USB BOS Descriptor */ + uint32_t *gu32HidReportSize; /*!< Pointer for HID Report descriptor Size */ + uint32_t *gu32ConfigHidDescIdx; /*!< Pointer for HID Descriptor start index */ +} S_USBD_INFO_T; /*!< Device description structure */ + +extern const S_USBD_INFO_T gsInfo; + +/*@}*/ /* end of group USBD_EXPORTED_STRUCTS */ + + + + +/** @addtogroup USBD_EXPORTED_CONSTANTS USBD Exported Constants + @{ +*/ +#define USBD_BUF_BASE (USBD_BASE+0x100ul) /*!< USBD buffer base address \hideinitializer */ +#define USBD_MAX_EP 12ul /*!< Total EP number \hideinitializer */ + +#define EP0 0ul /*!< Endpoint 0 \hideinitializer */ +#define EP1 1ul /*!< Endpoint 1 \hideinitializer */ +#define EP2 2ul /*!< Endpoint 2 \hideinitializer */ +#define EP3 3ul /*!< Endpoint 3 \hideinitializer */ +#define EP4 4ul /*!< Endpoint 4 \hideinitializer */ +#define EP5 5ul /*!< Endpoint 5 \hideinitializer */ +#define EP6 6ul /*!< Endpoint 6 \hideinitializer */ +#define EP7 7ul /*!< Endpoint 7 \hideinitializer */ +#define EP8 8ul /*!< Endpoint 8 \hideinitializer */ +#define EP9 9ul /*!< Endpoint 9 \hideinitializer */ +#define EP10 10ul /*!< Endpoint 10 \hideinitializer */ +#define EP11 11ul /*!< Endpoint 11 \hideinitializer */ + +/*! b, then return a. Otherwise, return b. + */ +#define USBD_Maximum(a,b) ((a)>(b) ? (a) : (b)) + + +/** + * @brief Compare two input numbers and return minimum one + * + * @param[in] a First number to be compared + * @param[in] b Second number to be compared + * + * @return Minimum value between a and b + * + * @details If a < b, then return a. Otherwise, return b. + */ +#define USBD_Minimum(a,b) ((a)<(b) ? (a) : (b)) + + +/** + * @brief Enable USB + * + * @param None + * + * @return None + * + * @details To set USB ATTR control register to enable USB and PHY. + * + */ +#define USBD_ENABLE_USB() ((uint32_t)(USBD->ATTR |= 0x7D0)) + +/** + * @brief Disable USB + * + * @param None + * + * @return None + * + * @details To set USB ATTR control register to disable USB. + * + */ +#define USBD_DISABLE_USB() ((uint32_t)(USBD->ATTR &= ~USBD_USB_EN)) + +/** + * @brief Enable USB PHY + * + * @param None + * + * @return None + * + * @details To set USB ATTR control register to enable USB PHY. + * + */ +#define USBD_ENABLE_PHY() ((uint32_t)(USBD->ATTR |= USBD_PHY_EN)) + +/** + * @brief Disable USB PHY + * + * @param None + * + * @return None + * + * @details To set USB ATTR control register to disable USB PHY. + * + */ +#define USBD_DISABLE_PHY() ((uint32_t)(USBD->ATTR &= ~USBD_PHY_EN)) + +/** + * @brief Enable SE0. Force USB PHY transceiver to drive SE0. + * + * @param None + * + * @return None + * + * @details Set DRVSE0 bit of USB_DRVSE0 register to enable software-disconnect function. Force USB PHY transceiver to drive SE0 to bus. + * + */ +#define USBD_SET_SE0() ((uint32_t)(USBD->SE0 |= USBD_DRVSE0)) + +/** + * @brief Disable SE0 + * + * @param None + * + * @return None + * + * @details Clear DRVSE0 bit of USB_DRVSE0 register to disable software-disconnect function. + * + */ +#define USBD_CLR_SE0() ((uint32_t)(USBD->SE0 &= ~USBD_DRVSE0)) + +/** + * @brief Set USB device address + * + * @param[in] addr The USB device address. + * + * @return None + * + * @details Write USB device address to USB_FADDR register. + * + */ +#define USBD_SET_ADDR(addr) (USBD->FADDR = (addr)) + +/** + * @brief Get USB device address + * + * @param None + * + * @return USB device address + * + * @details Read USB_FADDR register to get USB device address. + * + */ +#define USBD_GET_ADDR() ((uint32_t)(USBD->FADDR)) + +/** + * @brief Enable USB interrupt function + * + * @param[in] intr The combination of the specified interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be enabled. + * (USBD_INT_WAKEUP, USBD_INT_FLDET, USBD_INT_USB, USBD_INT_BUS) + * + * @return None + * + * @details Enable USB related interrupt functions specified by intr parameter. + * + */ +#define USBD_ENABLE_INT(intr) (USBD->INTEN |= (intr)) + +/** + * @brief Get interrupt status + * + * @param None + * + * @return The value of USB_INTSTS register + * + * @details Return all interrupt flags of USB_INTSTS register. + * + */ +#define USBD_GET_INT_FLAG() ((uint32_t)(USBD->INTSTS)) + +/** + * @brief Clear USB interrupt flag + * + * @param[in] flag The combination of the specified interrupt flags. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. + * (USBD_INTSTS_WAKEUP, USBD_INTSTS_FLDET, USBD_INTSTS_BUS, USBD_INTSTS_USB) + * + * @return None + * + * @details Clear USB related interrupt flags specified by flag parameter. + * + */ +#define USBD_CLR_INT_FLAG(flag) (USBD->INTSTS = (flag)) + +/** + * @brief Get endpoint status + * + * @param None + * + * @return The value of USB_EPSTS register. + * + * @details Return all endpoint status. + * + */ +#define USBD_GET_EP_FLAG() ((uint32_t)(USBD->EPSTS)) + +/** + * @brief Get USB bus state + * + * @param None + * + * @return The value of USB_ATTR[3:0] and USB_ATTR[13:12]. + * Bit 0 indicates USB bus reset status. + * Bit 1 indicates USB bus suspend status. + * Bit 2 indicates USB bus resume status. + * Bit 3 indicates USB bus time-out status. + * Bit 12 indicates USB bus LPM L1 suspend status. + * Bit 13 indicates USB bus LPM L1 resume status. + * + * @details Return USB_ATTR[3:0] and USB_ATTR[13:12] for USB bus events. + * + * \hideinitializer + */ +#define USBD_GET_BUS_STATE() ((uint32_t)(USBD->ATTR & 0x300f)) + + +/** + * @brief Check cable connection state + * + * @param None + * + * @retval 0 USB cable is not attached. + * @retval 1 USB cable is attached. + * + * @details Check the connection state by FLDET bit of USB_FLDET register. + * + */ +#define USBD_IS_ATTACHED() ((uint32_t)(USBD->VBUSDET & USBD_VBUSDET_VBUSDET_Msk)) + +/** + * @brief Stop USB transaction of the specified endpoint ID + * + * @param[in] ep The USB endpoint ID. M251 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Write 1 to CLRRDY bit of USB_CFGPx register to stop USB transaction of the specified endpoint ID. + * + */ +#define USBD_STOP_TRANSACTION(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_CLRRDY_Msk) + +/** + * @brief Set USB DATA1 PID for the specified endpoint ID + * + * @param[in] ep The USB endpoint ID. M251 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Set DSQ_SYNC bit of USB_CFGx register to specify the DATA1 PID for the following IN token transaction. + * Base on this setting, hardware will toggle PID between DATA0 and DATA1 automatically for IN token transactions. + * + */ +#define USBD_SET_DATA1(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DSQSYNC_Msk) + +/** + * @brief Set USB DATA0 PID for the specified endpoint ID + * + * @param[in] ep The USB endpoint ID. M251 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Clear DSQ_SYNC bit of USB_CFGx register to specify the DATA0 PID for the following IN token transaction. + * Base on this setting, hardware will toggle PID between DATA0 and DATA1 automatically for IN token transactions. + * + */ +#define USBD_SET_DATA0(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DSQSYNC_Msk)) + +/** + * @brief Set USB payload size (IN data) + * + * @param[in] ep The USB endpoint ID. M251 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @param[in] size The transfer length. + * + * @return None + * + * @details This macro will write the transfer length to USB_MXPLDx register for IN data transaction. + * + */ +#define USBD_SET_PAYLOAD_LEN(ep, size) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4))) = (size)) + +/** + * @brief Get USB payload size (OUT data) + * + * @param[in] ep The USB endpoint ID. M251 Series supports 12 endpoint ID. This parameter could be 0 ~ 11. + * + * @return The value of USB_MXPLDx register. + * + * @details Get the data length of OUT data transaction by reading USB_MXPLDx register. + * + */ +#define USBD_GET_PAYLOAD_LEN(ep) ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4)))) + +/** + * @brief Configure endpoint + * + * @param[in] ep The USB endpoint ID. M251 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @param[in] config The USB configuration. + * + * @return None + * + * @details This macro will write config parameter to USB_CFGx register of specified endpoint ID. + * + */ +#define USBD_CONFIG_EP(ep, config) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) = (config)) + +/** + * @brief Set USB endpoint buffer + * + * @param[in] ep The USB endpoint ID. M251 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @param[in] offset The SRAM offset. + * + * @return None + * + * @details This macro will set the SRAM offset for the specified endpoint ID. + * + */ +#define USBD_SET_EP_BUF_ADDR(ep, offset) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4))) = (offset)) + +/** + * @brief Get the offset of the specified USB endpoint buffer + * + @param[in] ep The USB endpoint ID. M251 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return The offset of the specified endpoint buffer. + * + * @details This macro will return the SRAM offset of the specified endpoint ID. + * + */ +#define USBD_GET_EP_BUF_ADDR(ep) ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4)))) + +/** + * @brief Set USB endpoint stall state + * + * @param[in] ep The USB endpoint ID. M251 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Set USB endpoint stall state for the specified endpoint ID. Endpoint will respond STALL token automatically. + * + */ +#define USBD_SET_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_SSTALL_Msk) + +/** + * @brief Clear USB endpoint stall state + * + * @param[in] ep The USB endpoint ID. M251 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Clear USB endpoint stall state for the specified endpoint ID. Endpoint will respond ACK/NAK token. + */ +#define USBD_CLR_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) &= ~USBD_CFGP_SSTALL_Msk) + +/** + * @brief Get USB endpoint stall state + * + * @param[in] ep The USB endpoint ID. M251 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @retval 0 USB endpoint is not stalled. + * @retval Others USB endpoint is stalled. + * + * @details Get USB endpoint stall state of the specified endpoint ID. + * + */ +#define USBD_GET_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) & USBD_CFGP_SSTALL_Msk) + +/** + * @brief To support byte access between USB SRAM and system SRAM + * + * @param[in] dest Destination pointer. + * + * @param[in] src Source pointer. + * + * @param[in] size Byte count. + * + * @return None + * + * @details This function will copy the number of data specified by size and src parameters to the address specified by dest parameter. + * + */ +__STATIC_INLINE void USBD_MemCopy(uint8_t *dest, uint8_t *src, uint32_t size) +{ + while (size--) *dest++ = *src++; +} + + +/** + * @brief Set USB endpoint stall state + * + * @param[in] epnum USB endpoint number + * + * @return None + * + * @details Set USB endpoint stall state. Endpoint will respond STALL token automatically. + * + */ +__STATIC_INLINE void USBD_SetStall(uint8_t epnum) +{ + uint32_t u32CfgAddr; + uint32_t u32Cfg; + uint32_t i; + + for (i = 0ul; i < USBD_MAX_EP; i++) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + if ((u32Cfg & 0xful) == epnum) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + *((__IO uint32_t *)(u32CfgAddr)) = (u32Cfg | USBD_CFGP_SSTALL); + break; + } + } +} + +/** + * @brief Clear USB endpoint stall state + * + * @param[in] epnum USB endpoint number + * + * @return None + * + * @details Clear USB endpoint stall state. Endpoint will respond ACK/NAK token. + */ +__STATIC_INLINE void USBD_ClearStall(uint8_t epnum) +{ + uint32_t u32CfgAddr; + uint32_t u32Cfg; + uint32_t i; + + for (i = 0ul; i < USBD_MAX_EP; i++) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + if ((u32Cfg & 0xful) == epnum) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + *((__IO uint32_t *)(u32CfgAddr)) = (u32Cfg & ~USBD_CFGP_SSTALL); + break; + } + } +} + +/** + * @brief Get USB endpoint stall state + * + * @param[in] epnum USB endpoint number + * + * @retval 0 USB endpoint is not stalled. + * @retval Others USB endpoint is stalled. + * + * @details Get USB endpoint stall state. + * + */ +__STATIC_INLINE uint32_t USBD_GetStall(uint8_t epnum) +{ + uint32_t u32CfgAddr; + uint32_t u32Cfg; + uint32_t i; + + for (i = 0ul; i < USBD_MAX_EP; i++) + { + u32CfgAddr = (uint32_t)(i << 4ul) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + if ((u32Cfg & 0xful) == epnum) + { + u32CfgAddr = (uint32_t)(i << 4ul) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */ + break; + } + } + + return ((*((__IO uint32_t *)(u32CfgAddr))) & USBD_CFGP_SSTALL); +} + + +extern volatile uint8_t g_USBD_u8RemoteWakeupEn; + + +typedef void (*VENDOR_REQ)(void); /*!< Functional pointer type definition for Vendor class */ +typedef void (*CLASS_REQ)(void); /*!< Functional pointer type declaration for USB class request callback handler */ +typedef void (*SET_INTERFACE_REQ)(void); /*!< Functional pointer type declaration for USB set interface request callback handler */ +typedef void (*SET_CONFIG_CB)(void); /*!< Functional pointer type declaration for USB set configuration request callback handler */ + + +/*--------------------------------------------------------------------*/ +void USBD_Open(const S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface); +void USBD_Start(void); +void USBD_GetSetupPacket(uint8_t *buf); +void USBD_ProcessSetupPacket(void); +void USBD_StandardRequest(void); +void USBD_PrepareCtrlIn(uint8_t pu8Buf[], uint32_t u32Size); +void USBD_CtrlIn(void); +void USBD_PrepareCtrlOut(uint8_t *pu8Buf, uint32_t u32Size); +void USBD_CtrlOut(void); +void USBD_SwReset(void); +void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq); +void USBD_SetConfigCallback(SET_CONFIG_CB pfnSetConfigCallback); +void USBD_LockEpStall(uint32_t u32EpBitmap); + +/*@}*/ /* end of group USBD_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USBD_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBD_H__ */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_usci_i2c.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_usci_i2c.h new file mode 100644 index 00000000000..3d797f66b62 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_usci_i2c.h @@ -0,0 +1,331 @@ +/**************************************************************************//** + * @file usci_i2c.h + * @version V0.10 + * @brief M251 series USCI I2C(UI2C) driver header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __USCI_I2C_H__ +#define __USCI_I2C_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_I2C_Driver USCI_I2C Driver + @{ +*/ + +/** @addtogroup USCI_I2C_EXPORTED_CONSTANTS USCI_I2C Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_I2C master event definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +enum UI2C_MASTER_EVENT +{ + MASTER_SEND_ADDRESS = 10, /*!< Master send address to Slave */ + MASTER_SEND_H_WR_ADDRESS, /*!< Master send High address to Slave */ + MASTER_SEND_H_RD_ADDRESS, /*!< Master send address to Slave (Read ADDR) */ + MASTER_SEND_L_ADDRESS, /*!< Master send Low address to Slave */ + MASTER_SEND_DATA, /*!< Master Send Data to Slave */ + MASTER_SEND_REPEAT_START, /*!< Master send repeat start to Slave */ + MASTER_READ_DATA, /*!< Master Get Data from Slave */ + MASTER_STOP, /*!< Master send stop to Slave */ + MASTER_SEND_START /*!< Master send start to Slave */ +}; + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_I2C slave event definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +enum UI2C_SLAVE_EVENT +{ + SLAVE_ADDRESS_ACK = 100, /*!< Slave send address ACK */ + SLAVE_H_WR_ADDRESS_ACK, /*!< Slave send High address ACK */ + SLAVE_L_WR_ADDRESS_ACK, /*!< Slave send Low address ACK */ + SLAVE_GET_DATA, /*!< Slave Get Data from Master (Write CMD) */ + SLAVE_SEND_DATA, /*!< Slave Send Data to Master (Read CMD) */ + SLAVE_H_RD_ADDRESS_ACK, /*!< Slave send High address ACK */ + SLAVE_L_RD_ADDRESS_ACK /*!< Slave send Low address ACK */ +}; + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_CTL constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UI2C_CTL_PTRG 0x20UL /*!< USCI_CTL setting for I2C control bits. It would set PTRG bit \hideinitializer */ +#define UI2C_CTL_STA 0x08UL /*!< USCI_CTL setting for I2C control bits. It would set STA bit \hideinitializer */ +#define UI2C_CTL_STO 0x04UL /*!< USCI_CTL setting for I2C control bits. It would set STO bit \hideinitializer */ +#define UI2C_CTL_AA 0x02UL /*!< USCI_CTL setting for I2C control bits. It would set AA bit \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_I2C GCMode constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UI2C_GCMODE_ENABLE (1U) /*!< Enable USCI_I2C GC Mode \hideinitializer */ +#define UI2C_GCMODE_DISABLE (0U) /*!< Disable USCI_I2C GC Mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_I2C Wakeup Mode constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UI2C_DATA_TOGGLE_WK (0x0U << UI2C_WKCTL_WKADDREN_Pos) /*!< Wakeup according data toggle \hideinitializer */ +#define UI2C_ADDR_MATCH_WK (0x1U << UI2C_WKCTL_WKADDREN_Pos) /*!< Wakeup according address match \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_I2C interrupt mask definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UI2C_TO_INT_MASK (0x001U) /*!< Time-out interrupt mask \hideinitializer */ +#define UI2C_STAR_INT_MASK (0x002U) /*!< Start condition received interrupt mask \hideinitializer */ +#define UI2C_STOR_INT_MASK (0x004U) /*!< Stop condition received interrupt mask \hideinitializer */ +#define UI2C_NACK_INT_MASK (0x008U) /*!< Non-acknowledge interrupt mask \hideinitializer */ +#define UI2C_ARBLO_INT_MASK (0x010U) /*!< Arbitration lost interrupt mask \hideinitializer */ +#define UI2C_ERR_INT_MASK (0x020U) /*!< Error interrupt mask \hideinitializer */ +#define UI2C_ACK_INT_MASK (0x040U) /*!< Acknowledge interrupt mask \hideinitializer */ + +/*@}*/ /* end of group USCI_I2C_EXPORTED_CONSTANTS */ + + +/** @addtogroup USCI_I2C_EXPORTED_FUNCTIONS USCI_I2C Exported Functions + @{ +*/ + +/** + * @brief This macro sets the USCI_I2C protocol control register at one time + * + * @param[in] psUI2C The pointer of the specified USCI_I2C module. + * @param[in] u8Ctrl Set the register value of USCI_I2C control register. + * + * @return None + * + * @details Set UI2C_PROTCTL register to control USCI_I2C bus conditions of START, STOP, SI, ACK. + * \hideinitializer + */ +#define UI2C_SET_CONTROL_REG(psUI2C, u8Ctrl) ((psUI2C)->PROTCTL = ((psUI2C)->PROTCTL & ~0x2EU) | (u8Ctrl)) + +/** + * @brief This macro only set START bit to protocol control register of USCI_I2C module. + * + * @param[in] psUI2C The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details Set the USCI_I2C bus START condition in UI2C_PROTCTL register. + * \hideinitializer + */ +#define UI2C_START(psUI2C) ((psUI2C)->PROTCTL = ((psUI2C)->PROTCTL & ~UI2C_PROTCTL_PTRG_Msk) | UI2C_PROTCTL_STA_Msk) + +/** + * @brief This macro only set STOP bit to the control register of USCI_I2C module + * + * @param[in] psUI2C The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details Set the USCI_I2C bus STOP condition in UI2C_PROTCTL register. + * \hideinitializer + */ +#define UI2C_STOP(psUI2C) ((psUI2C)->PROTCTL = ((psUI2C)->PROTCTL & ~0x2E) | (UI2C_PROTCTL_PTRG_Msk | UI2C_PROTCTL_STO_Msk)) + +/** + * @brief This macro returns the data stored in data register of USCI_I2C module + * + * @param[in] psUI2C The pointer of the specified USCI_I2C module. + * + * @return Data + * + * @details Read a byte data value of UI2C_RXDAT register from USCI_I2C bus + * \hideinitializer + */ +#define UI2C_GET_DATA(psUI2C) ((psUI2C)->RXDAT) + +/** + * @brief This macro writes the data to data register of USCI_I2C module + * + * @param[in] psUI2C The pointer of the specified USCI_I2C module. + * @param[in] u8Data The data which will be written to data register of USCI_I2C module. + * + * @return None + * + * @details Write a byte data value of UI2C_TXDAT register, then sends address or data to USCI I2C bus + * \hideinitializer + */ +#define UI2C_SET_DATA(psUI2C, u8Data) ((psUI2C)->TXDAT = (u8Data)) + +/** + * @brief This macro returns time-out flag + * + * @param[in] psUI2C The pointer of the specified USCI_I2C module. + * + * @retval 0 USCI_I2C bus time-out is not happened + * @retval 1 USCI_I2C bus time-out is happened + * + * @details USCI_I2C bus occurs time-out event, the time-out flag will be set. If not occurs time-out event, this bit is cleared. + * \hideinitializer + */ +#define UI2C_GET_TIMEOUT_FLAG(psUI2C) (((psUI2C)->PROTSTS & UI2C_PROTSTS_TOIF_Msk) == UI2C_PROTSTS_TOIF_Msk ? 1:0) + +/** + * @brief This macro returns wake-up flag + * + * @param[in] psUI2C The pointer of the specified USCI_I2C module. + * + * @retval 0 Chip is not woken-up from power-down mode + * @retval 1 Chip is woken-up from power-down mode + * + * @details USCI_I2C controller wake-up flag will be set when USCI_I2C bus occurs wake-up from deep-sleep. + * \hideinitializer + */ +#define UI2C_GET_WAKEUP_FLAG(psUI2C) (((psUI2C)->WKSTS & UI2C_WKSTS_WKF_Msk) == UI2C_WKSTS_WKF_Msk ? 1:0) + +/** + * @brief This macro is used to clear USCI_I2C wake-up flag + * + * @param[in] psUI2C The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details If USCI_I2C wake-up flag is set, use this macro to clear it. + * \hideinitializer + */ +#define UI2C_CLR_WAKEUP_FLAG(psUI2C) ((psUI2C)->WKSTS = UI2C_WKSTS_WKF_Msk) + +/** + * @brief This macro disables the USCI_I2C 10-bit address mode + * + * @param[in] psUI2C The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details The UI2C_I2C is 7-bit address mode, when disable USCI_I2C 10-bit address match function. + * \hideinitializer + */ +#define UI2C_DISABLE_10BIT_ADDR_MODE(psUI2C) ((psUI2C)->PROTCTL &= ~(UI2C_PROTCTL_ADDR10EN_Msk)) + +/** + * @brief This macro enables the 10-bit address mode + * + * @param[in] psUI2C The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details To enable USCI_I2C 10-bit address match function. + * \hideinitializer + */ +#define UI2C_ENABLE_10BIT_ADDR_MODE(psUI2C) ((psUI2C)->PROTCTL |= UI2C_PROTCTL_ADDR10EN_Msk) + +/** + * @brief This macro gets USCI_I2C protocol interrupt flag or bus status + * + * @param[in] psUI2C The pointer of the specified USCI_I2C module. + * + * @return A word data of USCI_I2C_PROTSTS register + * + * @details Read a word data of USCI_I2C PROTSTS register to get USCI_I2C bus Interrupt flags or status. + * \hideinitializer + */ +#define UI2C_GET_PROT_STATUS(psUI2C) ((psUI2C)->PROTSTS) + +/** + * @brief This macro clears specified protocol interrupt flag + * @param[in] psUI2C The pointer of the specified USCI_I2C module. + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref UI2C_PROTSTS_ACKIF_Msk + * - \ref UI2C_PROTSTS_ERRIF_Msk + * - \ref UI2C_PROTSTS_ARBLOIF_Msk + * - \ref UI2C_PROTSTS_NACKIF_Msk + * - \ref UI2C_PROTSTS_STORIF_Msk + * - \ref UI2C_PROTSTS_STARIF_Msk + * - \ref UI2C_PROTSTS_TOIF_Msk + * @return None + * + * @details To clear interrupt flag when USCI_I2C occurs interrupt and set interrupt flag. + * \hideinitializer + */ +#define UI2C_CLR_PROT_INT_FLAG(psUI2C,u32IntTypeFlag) ((psUI2C)->PROTSTS = (u32IntTypeFlag)) + +/** + * @brief This macro enables specified protocol interrupt + * @param[in] psUI2C The pointer of the specified USCI_I2C module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref UI2C_PROTIEN_ACKIEN_Msk + * - \ref UI2C_PROTIEN_ERRIEN_Msk + * - \ref UI2C_PROTIEN_ARBLOIEN_Msk + * - \ref UI2C_PROTIEN_NACKIEN_Msk + * - \ref UI2C_PROTIEN_STORIEN_Msk + * - \ref UI2C_PROTIEN_STARIEN_Msk + * - \ref UI2C_PROTIEN_TOIEN_Msk + * @return None + * + * @details Set specified USCI_I2C protocol interrupt bits to enable interrupt function. + * \hideinitializer + */ +#define UI2C_ENABLE_PROT_INT(psUI2C, u32IntSel) ((psUI2C)->PROTIEN |= (u32IntSel)) + +/** + * @brief This macro disables specified protocol interrupt + * @param[in] psUI2C The pointer of the specified USCI_I2C module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref UI2C_PROTIEN_ACKIEN_Msk + * - \ref UI2C_PROTIEN_ERRIEN_Msk + * - \ref UI2C_PROTIEN_ARBLOIEN_Msk + * - \ref UI2C_PROTIEN_NACKIEN_Msk + * - \ref UI2C_PROTIEN_STORIEN_Msk + * - \ref UI2C_PROTIEN_STARIEN_Msk + * - \ref UI2C_PROTIEN_TOIEN_Msk + * @return None + * + * @details Clear specified USCI_I2C protocol interrupt bits to disable interrupt function. + * \hideinitializer + */ +#define UI2C_DISABLE_PROT_INT(psUI2C, u32IntSel) ((psUI2C)->PROTIEN &= ~ (u32IntSel)) + + +uint32_t UI2C_Open(UI2C_T *psUI2C, uint32_t u32BusClock); +void UI2C_Close(UI2C_T *psUI2C); +void UI2C_ClearTimeoutFlag(UI2C_T *psUI2C); +void UI2C_Trigger(UI2C_T *psUI2C, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Ptrg, uint8_t u8Ack); +void UI2C_DisableInt(UI2C_T *psUI2C, uint32_t u32Mask); +void UI2C_EnableInt(UI2C_T *psUI2C, uint32_t u32Mask); +uint32_t UI2C_GetBusClockFreq(UI2C_T *psUI2C); +uint32_t UI2C_SetBusClockFreq(UI2C_T *psUI2C, uint32_t u32BusClock); +uint32_t UI2C_GetIntFlag(UI2C_T *psUI2C, uint32_t u32Mask); +void UI2C_ClearIntFlag(UI2C_T *psUI2C, uint32_t u32Mask); +uint32_t UI2C_GetData(UI2C_T *psUI2C); +void UI2C_SetData(UI2C_T *psUI2C, uint8_t u8Data); +void UI2C_SetSlaveAddr(UI2C_T *psUI2C, uint8_t u8SlaveNo, uint16_t u16SlaveAddr, uint8_t u8GCMode); +void UI2C_SetSlaveAddrMask(UI2C_T *psUI2C, uint8_t u8SlaveNo, uint16_t u16SlaveAddrMask); +void UI2C_EnableTimeout(UI2C_T *psUI2C, uint32_t u32TimeoutCnt); +void UI2C_DisableTimeout(UI2C_T *psUI2C); +void UI2C_EnableWakeup(UI2C_T *psUI2C, uint8_t u8WakeupMode); +void UI2C_DisableWakeup(UI2C_T *psUI2C); +uint8_t UI2C_WriteByte(UI2C_T *psUI2C, uint8_t u8SlaveAddr, const uint8_t u8Data); +uint32_t UI2C_WriteMultiBytes(UI2C_T *psUI2C, uint8_t u8SlaveAddr, const uint8_t *pu8Data, uint32_t u32WLen); +uint8_t UI2C_WriteByteOneReg(UI2C_T *psUI2C, uint8_t u8SlaveAddr, uint8_t u8DataAddr, const uint8_t u8Data); +uint32_t UI2C_WriteMultiBytesOneReg(UI2C_T *psUI2C, uint8_t u8SlaveAddr, uint8_t u8DataAddr, const uint8_t *pu8Data, uint32_t u32WLen); +uint8_t UI2C_WriteByteTwoRegs(UI2C_T *psUI2C, uint8_t u8SlaveAddr, uint16_t u16DataAddr, const uint8_t u8Data); +uint32_t UI2C_WriteMultiBytesTwoRegs(UI2C_T *psUI2C, uint8_t u8SlaveAddr, uint16_t u16DataAddr, const uint8_t *pu8Data, uint32_t u32WLen); +uint8_t UI2C_ReadByte(UI2C_T *psUI2C, uint8_t u8SlaveAddr); +uint32_t UI2C_ReadMultiBytes(UI2C_T *psUI2C, uint8_t u8SlaveAddr, uint8_t *pu8RData, uint32_t u32RLen); +uint8_t UI2C_ReadByteOneReg(UI2C_T *psUI2C, uint8_t u8SlaveAddr, uint8_t u8DataAddr); +uint32_t UI2C_ReadMultiBytesOneReg(UI2C_T *psUI2C, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t *pu8RData, uint32_t u32RLen); +uint8_t UI2C_ReadByteTwoRegs(UI2C_T *psUI2C, uint8_t u8SlaveAddr, uint16_t u16DataAddr); +uint32_t UI2C_ReadMultiBytesTwoRegs(UI2C_T *psUI2C, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t *pu8RData, uint32_t u32RLen); + +/*@}*/ /* end of group USCI_I2C_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USCI_I2C_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USCI_I2C_H__ */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_usci_spi.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_usci_spi.h new file mode 100644 index 00000000000..22cd40e2816 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_usci_spi.h @@ -0,0 +1,410 @@ +/****************************************************************************//** + * @file usci_spi.h + * @version V0.10 + * @brief M251 series USCI_SPI driver header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __USCI_SPI_H__ +#define __USCI_SPI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_SPI_Driver USCI_SPI Driver + @{ +*/ + +/** @addtogroup USCI_SPI_EXPORTED_CONSTANTS USCI_SPI Exported Constants + @{ +*/ + +#define USPI_MODE_0 (0x0 << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle low; data transmit with falling edge and receive with rising edge \hideinitializer */ +#define USPI_MODE_1 (0x1 << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle low; data transmit with rising edge and receive with falling edge \hideinitializer */ +#define USPI_MODE_2 (0x2 << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle high; data transmit with rising edge and receive with falling edge \hideinitializer */ +#define USPI_MODE_3 (0x3 << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle high; data transmit with falling edge and receive with rising edge \hideinitializer */ + +#define USPI_SLAVE (USPI_PROTCTL_SLAVE_Msk) /*!< Set as slave \hideinitializer */ +#define USPI_MASTER (0x0ul) /*!< Set as master \hideinitializer */ + +#define USPI_SS (USPI_PROTCTL_SS_Msk) /*!< Set SS \hideinitializer */ +#define USPI_SS_ACTIVE_HIGH (0x0ul) /*!< SS active high \hideinitializer */ +#define USPI_SS_ACTIVE_LOW (USPI_LINECTL_CTLOINV_Msk) /*!< SS active low \hideinitializer */ + +/* USCI_SPI Interrupt Mask */ +#define USPI_SSINACT_INT_MASK (0x001ul) /*!< Slave Slave Inactive interrupt mask \hideinitializer */ +#define USPI_SSACT_INT_MASK (0x002ul) /*!< Slave Slave Active interrupt mask \hideinitializer */ +#define USPI_SLVTO_INT_MASK (0x004ul) /*!< Slave Mode Time-out interrupt mask \hideinitializer */ +#define USPI_SLVBE_INT_MASK (0x008ul) /*!< Slave Mode Bit Count Error interrupt mask \hideinitializer */ +#define USPI_TXUDR_INT_MASK (0x010ul) /*!< Slave Transmit Under Run interrupt mask \hideinitializer */ +#define USPI_RXOV_INT_MASK (0x020ul) /*!< Receive Buffer Overrun interrupt mask \hideinitializer */ +#define USPI_TXST_INT_MASK (0x040ul) /*!< Transmit Start interrupt mask \hideinitializer */ +#define USPI_TXEND_INT_MASK (0x080ul) /*!< Transmit End interrupt mask \hideinitializer */ +#define USPI_RXST_INT_MASK (0x100ul) /*!< Receive Start interrupt mask \hideinitializer */ +#define USPI_RXEND_INT_MASK (0x200ul) /*!< Receive End interrupt mask \hideinitializer */ + +/* USCI_SPI Status Mask */ +#define USPI_BUSY_MASK (0x01ul) /*!< Busy status mask \hideinitializer */ +#define USPI_RX_EMPTY_MASK (0x02ul) /*!< RX empty status mask \hideinitializer */ +#define USPI_RX_FULL_MASK (0x04ul) /*!< RX full status mask \hideinitializer */ +#define USPI_TX_EMPTY_MASK (0x08ul) /*!< TX empty status mask \hideinitializer */ +#define USPI_TX_FULL_MASK (0x10ul) /*!< TX full status mask \hideinitializer */ +#define USPI_SSLINE_STS_MASK (0x20ul) /*!< USCI_SPI_SS line status mask \hideinitializer */ + +/*@}*/ /* end of group USCI_SPI_EXPORTED_CONSTANTS */ + + +/** @addtogroup USCI_SPI_EXPORTED_FUNCTIONS USCI_SPI Exported Functions + @{ +*/ + +/** + * @brief Disable slave 3-wire mode. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @return None + * \hideinitializer + */ +#define USPI_DISABLE_3WIRE_MODE(psUSPI) ( (psUSPI)->PROTCTL &= ~USPI_PROTCTL_SLV3WIRE_Msk ) + +/** + * @brief Enable slave 3-wire mode. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @return None + * \hideinitializer + */ +#define USPI_ENABLE_3WIRE_MODE(psUSPI) ( (psUSPI)->PROTCTL |= USPI_PROTCTL_SLV3WIRE_Msk ) + +/** + * @brief Get the Rx buffer empty flag. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @return Rx buffer flag + * @retval 0: Rx buffer is not empty + * @retval 1: Rx buffer is empty + * \hideinitializer + */ +#define USPI_GET_RX_EMPTY_FLAG(psUSPI) ( ((psUSPI)->BUFSTS & USPI_BUFSTS_RXEMPTY_Msk) == USPI_BUFSTS_RXEMPTY_Msk ? 1:0 ) + +/** + * @brief Get the Tx buffer empty flag. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @return Tx buffer flag + * @retval 0: Tx buffer is not empty + * @retval 1: Tx buffer is empty + * \hideinitializer + */ +#define USPI_GET_TX_EMPTY_FLAG(psUSPI) ( ((psUSPI)->BUFSTS & USPI_BUFSTS_TXEMPTY_Msk) == USPI_BUFSTS_TXEMPTY_Msk ? 1:0 ) + +/** + * @brief Get the Tx buffer full flag. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @return Tx buffer flag + * @retval 0: Tx buffer is not full + * @retval 1: Tx buffer is full + * \hideinitializer + */ +#define USPI_GET_TX_FULL_FLAG(psUSPI) ( ((psUSPI)->BUFSTS & USPI_BUFSTS_TXFULL_Msk) == USPI_BUFSTS_TXFULL_Msk ? 1:0 ) + +/** + * @brief Get the datum read from RX register. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @return data in Rx register + * \hideinitializer + */ +#define USPI_READ_RX(psUSPI) ((psUSPI)->RXDAT) + +/** + * @brief Write datum to TX register. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @param[in] u32TxData The datum which user attempt to transfer through USCI_SPI bus. + * @return None + * \hideinitializer + */ +#define USPI_WRITE_TX(psUSPI, u32TxData) ( (psUSPI)->TXDAT = (u32TxData) ) + +/** + * @brief Set USCI_SPI_SS pin to high state. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @return None. + * @details Disable automatic slave selection function and set USCI_SPI_SS pin to high state. Only available in Master mode. + * \hideinitializer + */ +#define USPI_SET_SS_HIGH(psUSPI) \ + do{ \ + (psUSPI)->LINECTL |= (USPI_LINECTL_CTLOINV_Msk); \ + (psUSPI)->PROTCTL = ((psUSPI)->PROTCTL & ~(USPI_PROTCTL_AUTOSS_Msk | USPI_PROTCTL_SS_Msk)); \ + }while(0) + +/** + * @brief Set USCI_SPI_SS pin to low state. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @return None. + * @details Disable automatic slave selection function and set USCI_SPI_SS pin to low state. Only available in Master mode. + * \hideinitializer + */ +#define USPI_SET_SS_LOW(psUSPI) \ + do{ \ + (psUSPI)->LINECTL |= (USPI_LINECTL_CTLOINV_Msk); \ + (psUSPI)->PROTCTL = (((psUSPI)->PROTCTL & ~USPI_PROTCTL_AUTOSS_Msk) | USPI_PROTCTL_SS_Msk); \ + }while(0) + +/** + * @brief Set the length of suspend interval. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @param[in] u32SuspCycle Decide the length of suspend interval. + * @return None + * \hideinitializer + */ +#define USPI_SET_SUSPEND_CYCLE(psUSPI, u32SuspCycle) ( (psUSPI)->PROTCTL = ((psUSPI)->PROTCTL & ~USPI_PROTCTL_SUSPITV_Msk) | ((u32SuspCycle) << USPI_PROTCTL_SUSPITV_Pos) ) + +/** + * @brief Set the USCI_SPI transfer sequence with LSB first. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @return None + * \hideinitializer + */ +#define USPI_SET_LSB_FIRST(psUSPI) ( (psUSPI)->LINECTL |= USPI_LINECTL_LSB_Msk ) + +/** + * @brief Set the USCI_SPI transfer sequence with MSB first. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @return None + * \hideinitializer + */ +#define USPI_SET_MSB_FIRST(psUSPI) ( (psUSPI)->LINECTL &= ~USPI_LINECTL_LSB_Msk ) + +/** + * @brief Set the data width of a USCI_SPI transaction. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @param[in] u32Width The data width + * @return None + * \hideinitializer + */ +#define USPI_SET_DATA_WIDTH(psUSPI,u32Width) \ + do{ \ + if((u32Width) == 16ul){ \ + (psUSPI)->LINECTL = ((psUSPI)->LINECTL & ~USPI_LINECTL_DWIDTH_Msk) | (0 << USPI_LINECTL_DWIDTH_Pos); \ + }else { \ + (psUSPI)->LINECTL = ((psUSPI)->LINECTL & ~USPI_LINECTL_DWIDTH_Msk) | ((u32Width) << USPI_LINECTL_DWIDTH_Pos); \ + } \ + }while(0) + +/** + * @brief Get the USCI_SPI busy state. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @return USCI_SPI busy status + * @retval 0: USCI_SPI module is not busy + * @retval 1: USCI_SPI module is busy + * \hideinitializer + */ +#define USPI_IS_BUSY(psUSPI) ( ((psUSPI)->PROTSTS & USPI_PROTSTS_BUSY_Msk) == USPI_PROTSTS_BUSY_Msk ? 1:0 ) + +/** + * @brief Get the USCI_SPI wakeup flag. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @return Wakeup status. + * @retval 0 Flag is not set. + * @retval 1 Flag is set. + * \hideinitializer + */ +#define USPI_GET_WAKEUP_FLAG(psUSPI) ( ((psUSPI)->WKSTS & USPI_WKSTS_WKF_Msk) == USPI_WKSTS_WKF_Msk ? 1:0) + +/** + * @brief Clear the USCI_SPI wakeup flag. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @return None + * \hideinitializer + */ +#define USPI_CLR_WAKEUP_FLAG(psUSPI) ( (psUSPI)->WKSTS |= USPI_WKSTS_WKF_Msk) + +/** + * @brief Get protocol interrupt flag/status. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @return The interrupt flag/status of protocol status register. + * \hideinitializer + */ +#define USPI_GET_PROT_STATUS(psUSPI) ( (psUSPI)->PROTSTS) + +/** + * @brief Clear specified protocol interrupt flag. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref USPI_PROTSTS_SSACTIF_Msk + * - \ref USPI_PROTSTS_SSINAIF_Msk + * - \ref USPI_PROTSTS_SLVBEIF_Msk + * - \ref USPI_PROTSTS_SLVTOIF_Msk + * - \ref USPI_PROTSTS_RXENDIF_Msk + * - \ref USPI_PROTSTS_RXSTIF_Msk + * - \ref USPI_PROTSTS_TXENDIF_Msk + * - \ref USPI_PROTSTS_TXSTIF_Msk + * @return None + * \hideinitializer + */ +#define USPI_CLR_PROT_INT_FLAG(psUSPI,u32IntTypeFlag) ( (psUSPI)->PROTSTS = (u32IntTypeFlag)) + +/** + * @brief Get buffer interrupt flag/status. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @return The interrupt flag/status of buffer status register. + * \hideinitializer + */ +#define USPI_GET_BUF_STATUS(psUSPI) ( (psUSPI)->BUFSTS) + +/** + * @brief Clear specified buffer interrupt flag. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref USPI_BUFSTS_TXUDRIF_Msk + * - \ref USPI_BUFSTS_RXOVIF_Msk + * @return None + * \hideinitializer + */ +#define USPI_CLR_BUF_INT_FLAG(psUSPI,u32IntTypeFlag) ( (psUSPI)->BUFSTS = (u32IntTypeFlag)) + +/** + * @brief Enable specified protocol interrupt. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_PROTIEN_SLVBEIEN_Msk + * - \ref USPI_PROTIEN_SLVTOIEN_Msk + * - \ref USPI_PROTIEN_SSACTIEN_Msk + * - \ref USPI_PROTIEN_SSINAIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_ENABLE_PROT_INT(psUSPI, u32IntSel) ((psUSPI)->PROTIEN |= (u32IntSel)) + +/** + * @brief Disable specified protocol interrupt. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_PROTIEN_SLVBEIEN_Msk + * - \ref USPI_PROTIEN_SLVTOIEN_Msk + * - \ref USPI_PROTIEN_SSACTIEN_Msk + * - \ref USPI_PROTIEN_SSINAIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_DISABLE_PROT_INT(psUSPI, u32IntSel) ((psUSPI)->PROTIEN &= ~ (u32IntSel)) + +/** + * @brief Enable specified buffer interrupt. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_BUFCTL_RXOVIEN_Msk + * - \ref USPI_BUFCTL_TXUDRIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_ENABLE_BUF_INT(psUSPI, u32IntSel) ((psUSPI)->BUFCTL |= (u32IntSel)) + +/** + * @brief Disable specified buffer interrupt. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_BUFCTL_RXOVIEN_Msk + * - \ref USPI_BUFCTL_TXUDRIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_DISABLE_BUF_INT(psUSPI, u32IntSel) ((psUSPI)->BUFCTL &= ~ (u32IntSel)) + +/** + * @brief Enable specified transfer interrupt. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_INTEN_RXENDIEN_Msk + * - \ref USPI_INTEN_RXSTIEN_Msk + * - \ref USPI_INTEN_TXENDIEN_Msk + * - \ref USPI_INTEN_TXSTIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_ENABLE_TRANS_INT(psUSPI, u32IntSel) ((psUSPI)->INTEN |= (u32IntSel)) + +/** + * @brief Disable specified transfer interrupt. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_INTEN_RXENDIEN_Msk + * - \ref USPI_INTEN_RXSTIEN_Msk + * - \ref USPI_INTEN_TXENDIEN_Msk + * - \ref USPI_INTEN_TXSTIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_DISABLE_TRANS_INT(psUSPI, u32IntSel) ((psUSPI)->INTEN &= ~ (u32IntSel)) + + +/** + * @brief Trigger RX PDMA function. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @return None. + * @details Set RXPDMAEN bit of USPI_PDMACTL register to enable RX PDMA transfer function. + * \hideinitializer + */ +#define USPI_TRIGGER_RX_PDMA(psUSPI) ((psUSPI)->PDMACTL |= USPI_PDMACTL_RXPDMAEN_Msk|USPI_PDMACTL_PDMAEN_Msk) + +/** + * @brief Trigger TX PDMA function. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @return None. + * @details Set TXPDMAEN bit of USPI_PDMACTL register to enable TX PDMA transfer function. + * \hideinitializer + */ +#define USPI_TRIGGER_TX_PDMA(psUSPI) ((psUSPI)->PDMACTL |= USPI_PDMACTL_TXPDMAEN_Msk|USPI_PDMACTL_PDMAEN_Msk) + +/** + * @brief Disable RX PDMA transfer. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @return None. + * @details Clear RXPDMAEN bit of USPI_PDMACTL register to disable RX PDMA transfer function. + * \hideinitializer + */ +#define USPI_DISABLE_RX_PDMA(psUSPI) ( (psUSPI)->PDMACTL &= ~USPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Disable TX PDMA transfer. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @return None. + * @details Clear TXPDMAEN bit of USPI_PDMACTL register to disable TX PDMA transfer function. + * \hideinitializer + */ +#define USPI_DISABLE_TX_PDMA(psUSPI) ( (psUSPI)->PDMACTL &= ~USPI_PDMACTL_TXPDMAEN_Msk ) + +uint32_t USPI_Open(USPI_T *psUSPI, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock); +void USPI_Close(USPI_T *psUSPI); +void USPI_ClearRxBuf(USPI_T *psUSPI); +void USPI_ClearTxBuf(USPI_T *psUSPI); +void USPI_DisableAutoSS(USPI_T *psUSPI); +void USPI_EnableAutoSS(USPI_T *psUSPI, uint32_t u32SSPinMask, uint32_t u32ActiveLevel); +uint32_t USPI_SetBusClock(USPI_T *psUSPI, uint32_t u32BusClock); +uint32_t USPI_GetBusClock(USPI_T *psUSPI); +void USPI_EnableInt(USPI_T *psUSPI, uint32_t u32Mask); +void USPI_DisableInt(USPI_T *psUSPI, uint32_t u32Mask); +uint32_t USPI_GetIntFlag(USPI_T *psUSPI, uint32_t u32Mask); +void USPI_ClearIntFlag(USPI_T *psUSPI, uint32_t u32Mask); +uint32_t USPI_GetStatus(USPI_T *psUSPI, uint32_t u32Mask); +void USPI_EnableWakeup(USPI_T *psUSPI); +void USPI_DisableWakeup(USPI_T *psUSPI); + + +/*@}*/ /* end of group USCI_SPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USCI_SPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USCI_SPI_H__ */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_usci_uart.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_usci_uart.h new file mode 100644 index 00000000000..b5cf4cda103 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_usci_uart.h @@ -0,0 +1,490 @@ +/**************************************************************************//** + * @file usci_uart.h + * @version V0.10 + * @brief M251 series USCI UART (UUART) driver header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __USCI_UART_H__ +#define __USCI_UART_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_UART_Driver USCI_UART Driver + @{ +*/ + +/** @addtogroup USCI_UART_EXPORTED_CONSTANTS USCI_UART Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* UUART_LINECTL constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UUART_WORD_LEN_6 (6ul << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 6 bits \hideinitializer */ +#define UUART_WORD_LEN_7 (7ul << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 7 bits \hideinitializer */ +#define UUART_WORD_LEN_8 (8ul << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 8 bits \hideinitializer */ +#define UUART_WORD_LEN_9 (9ul << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 9 bits \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* UUART_PROTCTL constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UUART_PARITY_NONE (0x0ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_PROTCTL setting to set UART as no parity \hideinitializer */ +#define UUART_PARITY_ODD (0x1ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_PROTCTL setting to set UART as odd parity \hideinitializer */ +#define UUART_PARITY_EVEN (0x3ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_PROTCTL setting to set UART as even parity \hideinitializer */ + +#define UUART_STOP_BIT_1 (0x0ul) /*!< UUART_PROTCTL setting for one stop bit \hideinitializer */ +#define UUART_STOP_BIT_2 (0x1ul) /*!< UUART_PROTCTL setting for two stop bit \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI UART interrupt mask definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UUART_ABR_INT_MASK (0x002ul) /*!< Auto-baud rate interrupt mask \hideinitializer */ +#define UUART_RLS_INT_MASK (0x004ul) /*!< Receive line status interrupt mask \hideinitializer */ +#define UUART_BUF_RXOV_INT_MASK (0x008ul) /*!< Buffer RX overrun interrupt mask \hideinitializer */ +#define UUART_TXST_INT_MASK (0x010ul) /*!< TX start interrupt mask \hideinitializer */ +#define UUART_TXEND_INT_MASK (0x020ul) /*!< Tx end interrupt mask \hideinitializer */ +#define UUART_RXST_INT_MASK (0x040ul) /*!< RX start interrupt mask \hideinitializer */ +#define UUART_RXEND_INT_MASK (0x080ul) /*!< RX end interrupt mask \hideinitializer */ + + +/*@}*/ /* end of group USCI_UART_EXPORTED_CONSTANTS */ + + +/** @addtogroup USCI_UART_EXPORTED_FUNCTIONS USCI_UART Exported Functions + @{ +*/ + + +/** + * @brief Write USCI_UART data + * + * @param[in] psUUART The pointer of the specified USCI_UART module + * @param[in] u8Data Data byte to transmit. + * + * @return None + * + * @details This macro write Data to Tx data register. + * \hideinitializer + */ +#define UUART_WRITE(psUUART, u8Data) ((psUUART)->TXDAT = (u8Data)) + + +/** + * @brief Read USCI_UART data + * + * @param[in] psUUART The pointer of the specified USCI_UART module + * + * @return The oldest data byte in RX buffer. + * + * @details This macro read Rx data register. + * \hideinitializer + */ +#define UUART_READ(psUUART) ((psUUART)->RXDAT) + + +/** + * @brief Get Tx empty + * + * @param[in] psUUART The pointer of the specified USCI_UART module + * + * @retval 0 Tx buffer is not empty + * @retval >=1 Tx buffer is empty + * + * @details This macro get Transmitter buffer empty register value. + * \hideinitializer + */ +#define UUART_GET_TX_EMPTY(psUUART) ((psUUART)->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk) + + +/** + * @brief Get Rx empty + * + * @param[in] psUUART The pointer of the specified USCI_UART module + * + * @retval 0 Rx buffer is not empty + * @retval >=1 Rx buffer is empty + * + * @details This macro get Receiver buffer empty register value. + * \hideinitializer + */ +#define UUART_GET_RX_EMPTY(psUUART) ((psUUART)->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk) + + +/** + * @brief Check specified usci_uart port transmission is over. + * + * @param[in] psUUART The pointer of the specified USCI_UART module + * + * @retval 0 Tx transmission is not over + * @retval 1 Tx transmission is over + * + * @details This macro return Transmitter Empty Flag register bit value. \n + * It indicates if specified usci_uart port transmission is over nor not. + * \hideinitializer + */ +#define UUART_IS_TX_EMPTY(psUUART) (((psUUART)->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk) >> UUART_BUFSTS_TXEMPTY_Pos) + + +/** + * @brief Check specified usci_uart port receiver is empty. + * + * @param[in] psUUART The pointer of the specified USCI_UART module + * + * @retval 0 Rx receiver is not empty + * @retval 1 Rx receiver is empty + * + * @details This macro return Receive Empty Flag register bit value. \n + * It indicates if specified usci_uart port receiver is empty nor not. + * \hideinitializer + */ +#define UUART_IS_RX_EMPTY(psUUART) (((psUUART)->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk) >> UUART_BUFSTS_RXEMPTY_Pos) + + +/** + * @brief Wait specified usci_uart port transmission is over + * + * @param[in] psUUART The pointer of the specified USCI_UART module + * + * @return None + * + * @details This macro wait specified usci_uart port transmission is over. + * \hideinitializer + */ +#define UUART_WAIT_TX_EMPTY(psUUART) while(!((((psUUART)->BUFSTS) & UUART_BUFSTS_TXEMPTY_Msk) >> UUART_BUFSTS_TXEMPTY_Pos)) + + +/** + * @brief Check TX buffer is full or not + * + * @param[in] psUUART The pointer of the specified USCI_UART module + * + * @retval 1 TX buffer is full + * @retval 0 TX buffer is not full + * + * @details This macro check TX buffer is full or not. + * \hideinitializer + */ +#define UUART_IS_TX_FULL(psUUART) (((psUUART)->BUFSTS & UUART_BUFSTS_TXFULL_Msk)>>UUART_BUFSTS_TXFULL_Pos) + + +/** + * @brief Check RX buffer is full or not + * + * @param[in] psUUART The pointer of the specified USCI_UART module + * + * @retval 1 RX buffer is full + * @retval 0 RX buffer is not full + * + * @details This macro check RX buffer is full or not. + * \hideinitializer + */ +#define UUART_IS_RX_FULL(psUUART) (((psUUART)->BUFSTS & UUART_BUFSTS_RXFULL_Msk)>>UUART_BUFSTS_RXFULL_Pos) + + +/** + * @brief Get Tx full register value + * + * @param[in] psUUART The pointer of the specified USCI_UART module + * + * @retval 0 Tx buffer is not full. + * @retval >=1 Tx buffer is full. + * + * @details This macro get Tx full register value. + * \hideinitializer + */ +#define UUART_GET_TX_FULL(psUUART) ((psUUART)->BUFSTS & UUART_BUFSTS_TXFULL_Msk) + + +/** + * @brief Get Rx full register value + * + * @param[in] psUUART The pointer of the specified USCI_UART module + * + * @retval 0 Rx buffer is not full. + * @retval >=1 Rx buffer is full. + * + * @details This macro get Rx full register value. + * \hideinitializer + */ +#define UUART_GET_RX_FULL(psUUART) ((psUUART)->BUFSTS & UUART_BUFSTS_RXFULL_Msk) + + +/** + * @brief Enable specified USCI_UART protocol interrupt + * + * @param[in] psUUART The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_PROTIEN_RLSIEN_Msk : Rx Line status interrupt + * - \ref UUART_PROTIEN_ABRIEN_Msk : Auto-baud rate interrupt + * + * @return None + * + * @details This macro enable specified USCI_UART protocol interrupt. + * \hideinitializer + */ +#define UUART_ENABLE_PROT_INT(psUUART, u32IntSel) ((psUUART)->PROTIEN |= (u32IntSel)) + + +/** + * @brief Disable specified USCI_UART protocol interrupt + * + * @param[in] psUUART The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_PROTIEN_RLSIEN_Msk : Rx Line status interrupt + * - \ref UUART_PROTIEN_ABRIEN_Msk : Auto-baud rate interrupt + * + * @return None + * + * @details This macro disable specified USCI_UART protocol interrupt. + * \hideinitializer + */ +#define UUART_DISABLE_PROT_INT(psUUART, u32IntSel) ((psUUART)->PROTIEN &= ~(u32IntSel)) + + +/** + * @brief Enable specified USCI_UART buffer interrupt + * + * @param[in] psUUART The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_BUFCTL_RXOVIEN_Msk : Receive buffer overrun error interrupt + * + * @return None + * + * @details This macro enable specified USCI_UART buffer interrupt. + * \hideinitializer + */ +#define UUART_ENABLE_BUF_INT(psUUART, u32IntSel) ((psUUART)->BUFCTL |= (u32IntSel)) + + +/** + * @brief Disable specified USCI_UART buffer interrupt + * + * @param[in] psUUART The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_BUFCTL_RXOVIEN_Msk : Receive buffer overrun error interrupt + * + * @return None + * + * @details This macro disable specified USCI_UART buffer interrupt. + * \hideinitializer + */ +#define UUART_DISABLE_BUF_INT(psUUART, u32IntSel) ((psUUART)->BUFCTL &= ~ (u32IntSel)) + + +/** + * @brief Enable specified USCI_UART transfer interrupt + * + * @param[in] psUUART The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_INTEN_RXENDIEN_Msk : Receive end interrupt + * - \ref UUART_INTEN_RXSTIEN_Msk : Receive start interrupt + * - \ref UUART_INTEN_TXENDIEN_Msk : Transmit end interrupt + * - \ref UUART_INTEN_TXSTIEN_Msk : Transmit start interrupt + * + * @return None + * + * @details This macro enable specified USCI_UART transfer interrupt. + * \hideinitializer + */ +#define UUART_ENABLE_TRANS_INT(psUUART, u32IntSel) ((psUUART)->INTEN |= (u32IntSel)) + + +/** + * @brief Disable specified USCI_UART transfer interrupt + * + * @param[in] psUUART The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_INTEN_RXENDIEN_Msk : Receive end interrupt + * - \ref UUART_INTEN_RXSTIEN_Msk : Receive start interrupt + * - \ref UUART_INTEN_TXENDIEN_Msk : Transmit end interrupt + * - \ref UUART_INTEN_TXSTIEN_Msk : Transmit start interrupt + * + * @return None + * + * @details This macro disable specified USCI_UART transfer interrupt. + * \hideinitializer + */ +#define UUART_DISABLE_TRANS_INT(psUUART, u32IntSel) ((psUUART)->INTEN &= ~(u32IntSel)) + + +/** + * @brief Get protocol interrupt flag/status + * + * @param[in] psUUART The pointer of the specified USCI_UART module + * + * @return The interrupt flag/status of protocol status register. + * + * @details This macro get protocol status register value. + * \hideinitializer + */ +#define UUART_GET_PROT_STATUS(psUUART) ((psUUART)->PROTSTS) + + +/** + * @brief Clear specified protocol interrupt flag + * + * @param[in] psUUART The pointer of the specified USCI_UART module + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref UUART_PROTSTS_ABERRSTS_Msk : Auto-baud Rate Error Interrupt Indicator + * - \ref UUART_PROTSTS_ABRDETIF_Msk : Auto-baud Rate Detected Interrupt Flag + * - \ref UUART_PROTSTS_BREAK_Msk : Break Flag + * - \ref UUART_PROTSTS_FRMERR_Msk : Framing Error Flag + * - \ref UUART_PROTSTS_PARITYERR_Msk : Parity Error Flag + * - \ref UUART_PROTSTS_RXENDIF_Msk : Receive End Interrupt Flag + * - \ref UUART_PROTSTS_RXSTIF_Msk : Receive Start Interrupt Flag + * - \ref UUART_PROTSTS_TXENDIF_Msk : Transmit End Interrupt Flag + * - \ref UUART_PROTSTS_TXSTIF_Msk : Transmit Start Interrupt Flag + * + * @return None + * + * @details This macro clear specified protocol interrupt flag. + * \hideinitializer + */ +#define UUART_CLR_PROT_INT_FLAG(psUUART,u32IntTypeFlag) ((psUUART)->PROTSTS = (u32IntTypeFlag)) + + +/** + * @brief Get transmit/receive buffer interrupt flag/status + * + * @param[in] psUUART The pointer of the specified USCI_UART module + * + * @return The interrupt flag/status of buffer status register. + * + * @details This macro get buffer status register value. + * \hideinitializer + */ +#define UUART_GET_BUF_STATUS(psUUART) ((psUUART)->BUFSTS) + + +/** + * @brief Clear specified buffer interrupt flag + * + * @param[in] psUUART The pointer of the specified USCI_UART module + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref UUART_BUFSTS_RXOVIF_Msk : Receive Buffer Over-run Error Interrupt Indicator + * + * @return None + * + * @details This macro clear specified buffer interrupt flag. + * \hideinitializer + */ +#define UUART_CLR_BUF_INT_FLAG(psUUART,u32IntTypeFlag) ((psUUART)->BUFSTS = (u32IntTypeFlag)) + + +/** + * @brief Get wakeup flag + * + * @param[in] psUUART The pointer of the specified USCI_UART module + * + * @retval 0 Chip did not wake up from power-down mode. + * @retval 1 Chip waked up from power-down mode. + * + * @details This macro get wakeup flag. + * \hideinitializer + */ +#define UUART_GET_WAKEUP_FLAG(psUUART) ((psUUART)->WKSTS & UUART_WKSTS_WKF_Msk ? 1: 0 ) + + +/** + * @brief Clear wakeup flag + * + * @param[in] psUUART The pointer of the specified USCI_UART module + * + * @return None + * + * @details This macro clear wakeup flag. + * \hideinitializer + */ +#define UUART_CLR_WAKEUP_FLAG(psUUART) ((psUUART)->WKSTS = UUART_WKSTS_WKF_Msk) + + +/** + * @brief Trigger RX PDMA function. + * + * @param[in] psUUART The pointer of the specified USCI_UART module. + * + * @return None. + * + * @details Set RXPDMAEN bit of UUART_PDMACTL register to enable RX PDMA transfer function. + * \hideinitializer + */ +#define UUART_TRIGGER_RX_PDMA(psUUART) ((psUUART)->PDMACTL |= UUART_PDMACTL_RXPDMAEN_Msk|UUART_PDMACTL_PDMAEN_Msk) + + +/** + * @brief Trigger TX PDMA function. + * + * @param[in] psUUART The pointer of the specified USCI_UART module. + * + * @return None. + * + * @details Set TXPDMAEN bit of UUART_PDMACTL register to enable TX PDMA transfer function. + * \hideinitializer + */ +#define UUART_TRIGGER_TX_PDMA(psUUART) ((psUUART)->PDMACTL |= UUART_PDMACTL_TXPDMAEN_Msk|UUART_PDMACTL_PDMAEN_Msk) + + +/** + * @brief Disable RX PDMA transfer. + * + * @param[in] psUUART The pointer of the specified USCI_UART module. + * + * @return None. + * + * @details Clear RXPDMAEN bit of UUART_PDMACTL register to disable RX PDMA transfer function. + * \hideinitializer + */ +#define UUART_DISABLE_RX_PDMA(psUUART) ( (psUUART)->PDMACTL &= ~UUART_PDMACTL_RXPDMAEN_Msk ) + + +/** + * @brief Disable TX PDMA transfer. + * + * @param[in] psUUART The pointer of the specified USCI_UART module. + * + * @return None. + * + * @details Clear TXPDMAEN bit of UUART_PDMACTL register to disable TX PDMA transfer function. + * \hideinitializer + */ +#define UUART_DISABLE_TX_PDMA(psUUART) ( (psUUART)->PDMACTL &= ~UUART_PDMACTL_TXPDMAEN_Msk ) + + +void UUART_ClearIntFlag(UUART_T *psUUART, uint32_t u32Mask); +uint32_t UUART_GetIntFlag(UUART_T *psUUART, uint32_t u32Mask); +void UUART_Close(UUART_T *psUUART); +void UUART_DisableInt(UUART_T *psUUART, uint32_t u32Mask); +void UUART_EnableInt(UUART_T *psUUART, uint32_t u32Mask); +uint32_t UUART_Open(UUART_T *psUUART, uint32_t u32Baudrate); +uint32_t UUART_Read(UUART_T *psUUART, uint8_t pu8RxBuf[], uint32_t u32ReadBytes); +uint32_t UUART_SetLine_Config(UUART_T *psUUART, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits); +uint32_t UUART_Write(UUART_T *psUUART, uint8_t pu8TxBuf[], uint32_t u32WriteBytes); +void UUART_EnableWakeup(UUART_T *psUUART, uint32_t u32WakeupMode); +void UUART_DisableWakeup(UUART_T *psUUART); +void UUART_EnableFlowCtrl(UUART_T *psUUART); +void UUART_DisableFlowCtrl(UUART_T *psUUART); + + +/*@}*/ /* end of group USCI_UART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USCI_UART_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USCI_UART_H__ */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_wdt.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_wdt.h new file mode 100644 index 00000000000..b73a5465c4b --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_wdt.h @@ -0,0 +1,222 @@ +/**************************************************************************//** + * @file wdt.h + * @version V0.10 + * @brief M251 series WDT driver header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __WDT_H__ +#define __WDT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup WDT_Driver WDT Driver + @{ +*/ + +/** @addtogroup WDT_EXPORTED_CONSTANTS WDT Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* WDT Time-out Interval Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WDT_TIMEOUT_2POW4 (0UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^4 * WDT clocks */ +#define WDT_TIMEOUT_2POW6 (1UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^6 * WDT clocks */ +#define WDT_TIMEOUT_2POW8 (2UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^8 * WDT clocks */ +#define WDT_TIMEOUT_2POW10 (3UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^10 * WDT clocks */ +#define WDT_TIMEOUT_2POW12 (4UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^12 * WDT clocks */ +#define WDT_TIMEOUT_2POW14 (5UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^14 * WDT clocks */ +#define WDT_TIMEOUT_2POW16 (6UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^16 * WDT clocks */ +#define WDT_TIMEOUT_2POW18 (7UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^18 * WDT clocks */ +#define WDT_TIMEOUT_2POW20 (8UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^20 * WDT clocks */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* WDT Reset Delay Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WDT_RESET_DELAY_1026CLK (0UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 1026 * WDT clocks */ +#define WDT_RESET_DELAY_130CLK (1UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 130 * WDT clocks */ +#define WDT_RESET_DELAY_18CLK (2UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 18 * WDT clocks */ +#define WDT_RESET_DELAY_3CLK (3UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 3 * WDT clocks */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* WDT Free Reset Counter Keyword Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WDT_FREE_RESET_COUNTER_KEY (0x00005AA5) /*!< Fill this value to WDT_RSTCNT register to free reset WDT counter */ + +/*@}*/ /* end of group WDT_EXPORTED_CONSTANTS */ + + +/** @addtogroup WDT_EXPORTED_FUNCTIONS WDT Exported Functions + @{ +*/ + +/** + * @brief Clear WDT Reset System Flag + * + * @param None + * + * @return None + * + * @details This macro clears WDT time-out reset system flag. + * + * \hideinitializer + */ +#define WDT_CLEAR_RESET_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_RSTF_Msk) + +/** + * @brief Clear WDT Time-out Interrupt Flag + * + * @param None + * + * @return None + * + * @details This macro clears WDT time-out interrupt flag. + * + * \hideinitializer + */ +#define WDT_CLEAR_TIMEOUT_INT_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_IF_Msk) + +/** + * @brief Clear WDT Wake-up Flag + * + * @param None + * + * @return None + * + * @details This macro clears WDT time-out wake-up system flag. + * + * \hideinitializer + */ +#define WDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk)) | WDT_CTL_WKF_Msk) + +/** + * @brief Get WDT Time-out Reset Flag + * + * @param None + * + * @retval 0 WDT time-out reset system did not occur + * @retval 1 WDT time-out reset system occurred + * + * @details This macro indicates system has been reset by WDT time-out reset or not. + * + * \hideinitializer + */ +#define WDT_GET_RESET_FLAG() ((WDT->CTL & WDT_CTL_RSTF_Msk)? 1UL : 0UL) + +/** + * @brief Get WDT Time-out Interrupt Flag + * + * @param None + * + * @retval 0 WDT time-out interrupt did not occur + * @retval 1 WDT time-out interrupt occurred + * + * @details This macro indicates WDT time-out interrupt occurred or not. + * + * \hideinitializer + */ +#define WDT_GET_TIMEOUT_INT_FLAG() ((WDT->CTL & WDT_CTL_IF_Msk)? 1UL : 0UL) + +/** + * @brief Get WDT Time-out Wake-up Flag + * + * @param None + * + * @retval 0 WDT time-out interrupt does not cause CPU wake-up + * @retval 1 WDT time-out interrupt event cause CPU wake-up + * + * @details This macro indicates WDT time-out interrupt event has waked up system or not. + * + * \hideinitializer + */ +#define WDT_GET_TIMEOUT_WAKEUP_FLAG() ((WDT->CTL & WDT_CTL_WKF_Msk)? 1UL : 0UL) + +/** + * @brief Reset WDT Counter + * + * @param None + * + * @return None + * + * @details This macro is used to reset the internal 18-bit WDT up counter value. + * @note If WDT is activated and time-out reset system function is enabled also, user should \n + * reset the 18-bit WDT up counter value to avoid generate WDT time-out reset signal to \n + * reset system before the WDT time-out reset delay period expires. + * + * \hideinitializer + */ +#define WDT_RESET_COUNTER() (WDT->RSTCNT = WDT_FREE_RESET_COUNTER_KEY) +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void WDT_Close(void); +__STATIC_INLINE void WDT_EnableInt(void); +__STATIC_INLINE void WDT_DisableInt(void); + +/** + * @brief Stop WDT Counting + * + * @param None + * + * @return None + * + * @details This function will stop WDT counting and disable WDT module. + */ +__STATIC_INLINE void WDT_Close(void) +{ + WDT->CTL = 0UL; + return; +} + +/** + * @brief Enable WDT Time-out Interrupt + * + * @param None + * + * @return None + * + * @details This function will enable the WDT time-out interrupt function. + */ +__STATIC_INLINE void WDT_EnableInt(void) +{ + WDT->CTL |= WDT_CTL_INTEN_Msk; + return; +} + +/** + * @brief Disable WDT Time-out Interrupt + * + * @param None + * + * @return None + * + * @details This function will disable the WDT time-out interrupt function. + */ +__STATIC_INLINE void WDT_DisableInt(void) +{ + /* Do not touch another write 1 clear bits */ + WDT->CTL &= ~(WDT_CTL_INTEN_Msk | WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk); + return; +} + +void WDT_Open(uint32_t u32TimeoutInterval, uint32_t u32ResetDelay, uint32_t u32EnableReset, uint32_t u32EnableWakeup); + +/*@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group WDT_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __WDT_H__ */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_wwdt.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_wwdt.h new file mode 100644 index 00000000000..48eb82caee2 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_wwdt.h @@ -0,0 +1,157 @@ +/**************************************************************************//** + * @file wwdt.h + * @version V0.10 + * @brief M251 series WWDT driver header file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __WWDT_H__ +#define __WWDT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup WWDT_Driver WWDT Driver + @{ +*/ + +/** @addtogroup WWDT_EXPORTED_CONSTANTS WWDT Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* WWDT Prescale Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WWDT_PRESCALER_1 (0 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1 * (64*WWDT_CLK) */ +#define WWDT_PRESCALER_2 (1 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2 * (64*WWDT_CLK) */ +#define WWDT_PRESCALER_4 (2 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 4 * (64*WWDT_CLK) */ +#define WWDT_PRESCALER_8 (3 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 8 * (64*WWDT_CLK) */ +#define WWDT_PRESCALER_16 (4 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 16 * (64*WWDT_CLK) */ +#define WWDT_PRESCALER_32 (5 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 32 * (64*WWDT_CLK) */ +#define WWDT_PRESCALER_64 (6 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 64 * (64*WWDT_CLK) */ +#define WWDT_PRESCALER_128 (7 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 128 * (64*WWDT_CLK) */ +#define WWDT_PRESCALER_192 (8 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 192 * (64*WWDT_CLK) */ +#define WWDT_PRESCALER_256 (9 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 256 * (64*WWDT_CLK) */ +#define WWDT_PRESCALER_384 (10 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 384 * (64*WWDT_CLK) */ +#define WWDT_PRESCALER_512 (11 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 512 * (64*WWDT_CLK) */ +#define WWDT_PRESCALER_768 (12 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 768 * (64*WWDT_CLK) */ +#define WWDT_PRESCALER_1024 (13 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1024 * (64*WWDT_CLK) */ +#define WWDT_PRESCALER_1536 (14 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1536 * (64*WWDT_CLK) */ +#define WWDT_PRESCALER_2048 (15 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2048 * (64*WWDT_CLK) */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* WWDT Reload Counter Keyword Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WWDT_RELOAD_WORD (0x00005AA5) /*!< Fill this value to WWDT_RLDCNT register to reload WWDT counter */ + +/*@}*/ /* end of group WWDT_EXPORTED_CONSTANTS */ + + +/** @addtogroup WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions + @{ +*/ + +/** + * @brief Clear WWDT Reset System Flag + * + * @param None + * + * @return None + * + * @details This macro is used to clear WWDT time-out reset system flag. + * + * \hideinitializer + */ +#define WWDT_CLEAR_RESET_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTRF_Msk) + +/** + * @brief Clear WWDT Compared Match Interrupt Flag + * + * @param None + * + * @return None + * + * @details This macro is used to clear WWDT compared match interrupt flag. + * + * \hideinitializer + */ +#define WWDT_CLEAR_INT_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTIF_Msk) + +/** + * @brief Get WWDT Reset System Flag + * + * @param None + * + * @retval 0 WWDT time-out reset system did not occur + * @retval 1 WWDT time-out reset system occurred + * + * @details This macro is used to indicate system has been reset by WWDT time-out reset or not. + * + * \hideinitializer + */ +#define WWDT_GET_RESET_FLAG() ((WWDT->STATUS & WWDT_STATUS_WWDTRF_Msk)? 1 : 0) + +/** + * @brief Get WWDT Compared Match Interrupt Flag + * + * @param None + * + * @retval 0 WWDT compare match interrupt did not occur + * @retval 1 WWDT compare match interrupt occurred + * + * @details This macro is used to indicate WWDT counter value matches CMPDAT value or not. + * + * \hideinitializer + */ +#define WWDT_GET_INT_FLAG() ((WWDT->STATUS & WWDT_STATUS_WWDTIF_Msk)? 1 : 0) + +/** + * @brief Get WWDT Counter + * + * @param None + * + * @return WWDT Counter Value + * + * @details This macro reflects the current WWDT counter value. + * + * \hideinitializer + */ +#define WWDT_GET_COUNTER() (WWDT->CNT) + +/** + * @brief Reload WWDT Counter + * + * @param None + * + * @return None + * + * @details This macro is used to reload the WWDT counter value to 0x3F. + * @note User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value \n + * between 0 and CMPDAT value. If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT, \n + * WWDT reset signal will generate immediately to reset system. + * + * \hideinitializer + */ +#define WWDT_RELOAD_COUNTER() (WWDT->RLDCNT = WWDT_RELOAD_WORD) + +void WWDT_Open(uint32_t u32PreScale, uint32_t u32CmpValue, uint32_t u32EnableInt); + +/*@}*/ /* end of group WWDT_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group WWDT_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __WWDT_H__ */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_acmp.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_acmp.c new file mode 100644 index 00000000000..32cc38ca7d1 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_acmp.c @@ -0,0 +1,73 @@ +/**************************************************************************//** + * @file acmp.c + * @version V1.00 + * @brief M251 series Analog Comparator(ACMP) driver source file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup ACMP_Driver ACMP Driver + @{ +*/ + + +/** @addtogroup ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions + @{ +*/ + + +/** + * @brief Configure the specified ACMP module + * + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum Comparator number. + * @param[in] u32NegSrc Comparator negative input selection. Including: + * - \ref ACMP_CTL_NEGSEL_PIN + * - \ref ACMP_CTL_NEGSEL_CRV + * - \ref ACMP_CTL_NEGSEL_VBG + * - \ref ACMP_CTL_NEGSEL_DAC + * @param[in] u32HysSel The hysteresis function option. Including: + * - \ref ACMP_CTL_HYSTERESIS_30MV + * - \ref ACMP_CTL_HYSTERESIS_20MV + * - \ref ACMP_CTL_HYSTERESIS_10MV + * - \ref ACMP_CTL_HYSTERESIS_DISABLE + * + * @return None + * + * @details Configure hysteresis function, select the source of negative input and enable analog comparator. + */ +void ACMP_Open(ACMP_T *acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysSel) +{ + acmp->CTL[u32ChNum] = (acmp->CTL[u32ChNum] & (~(ACMP_CTL_NEGSEL_Msk | ACMP_CTL_HYSSEL_Msk))) | (u32NegSrc | u32HysSel | ACMP_CTL_ACMPEN_Msk); +} + +/** + * @brief Close analog comparator + * + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum Comparator number. + * + * @return None + * + * @details This function will clear ACMPEN bit of ACMP_CTL register to disable analog comparator. + */ +void ACMP_Close(ACMP_T *acmp, uint32_t u32ChNum) +{ + acmp->CTL[u32ChNum] &= (~ACMP_CTL_ACMPEN_Msk); +} + + + +/*@}*/ /* end of group ACMP_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group ACMP_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ + diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_bpwm.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_bpwm.c new file mode 100644 index 00000000000..879c1c2f237 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_bpwm.c @@ -0,0 +1,748 @@ +/**************************************************************************//** + * @file bpwm.c + * @version V0.10 + * @brief M251 series BPWM driver source file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup BPWM_Driver BPWM Driver + @{ +*/ + + +/** @addtogroup BPWM_EXPORTED_FUNCTIONS BPWM Exported Functions + @{ +*/ + +/** + * @brief Configure BPWM capture and get the nearest unit time. + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32UnitTimeNsec The unit time of counter + * @param[in] u32CaptureEdge The condition to latch the counter. This parameter is not used + * @return The nearest unit time in nano second. + * @details This function is used to Configure BPWM capture and get the nearest unit time. + */ +uint32_t BPWM_ConfigCaptureChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge) +{ + uint32_t u32Src; + uint32_t u32BPWMClockSrc; + uint32_t u32NearestUnitTimeNsec; + uint16_t u16Prescale = 1UL, u16CNR = 0xFFFFUL; + uint8_t u8BreakLoop = 0UL; + + if (bpwm == BPWM0) + { + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM0SEL_Msk; + } + else /* (bpwm == BPWM1) */ + { + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM1SEL_Msk; + } + + if (u32Src == 0UL) + { + //clock source is from PLL clock + u32BPWMClockSrc = CLK_GetPLLClockFreq(); + } + else + { + //clock source is from PCLK + SystemCoreClockUpdate(); + + if (bpwm == BPWM0) + { + u32BPWMClockSrc = CLK_GetPCLK0Freq(); + } + else /* (bpwm == BPWM1) */ + { + u32BPWMClockSrc = CLK_GetPCLK1Freq(); + } + } + + u32BPWMClockSrc /= 1000UL; + + for (u16Prescale = 1UL; u16Prescale <= 0x1000UL; u16Prescale++) + { + u32NearestUnitTimeNsec = (1000000UL * u16Prescale) / u32BPWMClockSrc; + + if (u32NearestUnitTimeNsec < u32UnitTimeNsec) + { + if (u16Prescale == 0x1000UL) + { + /* limit to the maximum unit time(nano second) */ + u8BreakLoop = 1UL; + } + + if (!((1000000UL * (u16Prescale + 1UL) > (u32NearestUnitTimeNsec * u32BPWMClockSrc)))) + { + u8BreakLoop = 1UL; + } + } + else + { + u8BreakLoop = 1UL; + } + + if (u8BreakLoop) + { + break; + } + } + + // convert to real register value + u16Prescale = u16Prescale - 1UL; + // all channels share a prescaler + BPWM_SET_PRESCALER(bpwm, u32ChannelNum, (uint32_t)u16Prescale); + + // set BPWM to down count type(edge aligned) + (bpwm)->CTL1 = BPWM_DOWN_COUNTER; + + BPWM_SET_CNR(bpwm, u32ChannelNum, u16CNR); + + return (u32NearestUnitTimeNsec); +} + +/** + * @brief This function Configure BPWM generator and get the nearest frequency in edge aligned(down countertype) auto-reload mode + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Frequency Target generator frequency + * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%... + * @return Nearest frequency clock in nano second + * @note Since all channels shares a prescaler. Call this API to configure BPWM frequency may affect + * existing frequency of other channel. + */ +uint32_t BPWM_ConfigOutputChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle) +{ + uint32_t u32Src; + uint32_t u32BPWMClockSrc; + uint32_t i; + uint16_t u16Prescale = 1UL, u16CNR = 0xFFFFUL; + + if (bpwm == BPWM0) + { + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM0SEL_Msk; + } + else /* (bpwm == BPWM1) */ + { + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_BPWM1SEL_Msk; + } + + if (u32Src == 0UL) + { + //clock source is from PLL clock + u32BPWMClockSrc = CLK_GetPLLClockFreq(); + } + else + { + //clock source is from PCLK + SystemCoreClockUpdate(); + + if (bpwm == BPWM0) + { + u32BPWMClockSrc = CLK_GetPCLK0Freq(); + } + else /* (bpwm == BPWM1) */ + { + u32BPWMClockSrc = CLK_GetPCLK1Freq(); + } + } + + for (u16Prescale = 1UL; u16Prescale < 0xFFFUL; u16Prescale++) //prescale could be 0~0xFFF + { + i = (u32BPWMClockSrc / u32Frequency) / u16Prescale; + + // If target value is larger than CNR, need to use a larger prescaler + if (i <= (0x10000UL)) + { + u16CNR = (uint16_t)i; + break; + } + } + + // Store return value here 'cos we're gonna change u16Prescale & u16CNR to the real value to fill into register + i = u32BPWMClockSrc / ((uint32_t)u16Prescale * (uint32_t)u16CNR); + + // convert to real register value + u16Prescale = u16Prescale - 1UL; + // all channels share a prescaler + BPWM_SET_PRESCALER(bpwm, u32ChannelNum, (uint32_t)u16Prescale); + // set BPWM to down count type + (bpwm)->CTL1 = BPWM_DOWN_COUNTER; + + u16CNR = u16CNR - 1UL; + BPWM_SET_CNR(bpwm, u32ChannelNum, u16CNR); + + if (u32DutyCycle) + { + if (u32DutyCycle >= 100UL) + BPWM_SET_CMR(bpwm, u32ChannelNum, u16CNR); + else + BPWM_SET_CMR(bpwm, u32ChannelNum, u32DutyCycle * (u16CNR + 1UL) / 100UL); + + (bpwm)->WGCTL0 &= ~((BPWM_WGCTL0_PRDPCTL0_Msk | BPWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum << 1UL)); + (bpwm)->WGCTL0 |= (BPWM_OUTPUT_LOW << ((u32ChannelNum << 1UL) + BPWM_WGCTL0_PRDPCTL0_Pos)); + (bpwm)->WGCTL1 &= ~((BPWM_WGCTL1_CMPDCTL0_Msk | BPWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum << 1UL)); + (bpwm)->WGCTL1 |= (BPWM_OUTPUT_HIGH << ((u32ChannelNum << 1UL) + BPWM_WGCTL1_CMPDCTL0_Pos)); + } + else + { + BPWM_SET_CMR(bpwm, u32ChannelNum, 0UL); + (bpwm)->WGCTL0 &= ~((BPWM_WGCTL0_PRDPCTL0_Msk | BPWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum << 1UL)); + (bpwm)->WGCTL0 |= (BPWM_OUTPUT_LOW << ((u32ChannelNum << 1UL) + BPWM_WGCTL0_ZPCTL0_Pos)); + (bpwm)->WGCTL1 &= ~((BPWM_WGCTL1_CMPDCTL0_Msk | BPWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum << 1UL)); + (bpwm)->WGCTL1 |= (BPWM_OUTPUT_HIGH << ((u32ChannelNum << 1UL) + BPWM_WGCTL1_CMPDCTL0_Pos)); + } + + return (i); +} + +/** + * @brief Start BPWM module + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @return None + * @details This function is used to start BPWM module. + * @note All channels share one counter. + */ +void BPWM_Start(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (bpwm)->CNTEN = BPWM_CNTEN_CNTEN0_Msk; +} + +/** + * @brief Stop BPWM module + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @return None + * @details This function is used to stop BPWM module. + * @note All channels share one period. + */ +void BPWM_Stop(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (bpwm)->PERIOD = 0UL; +} + +/** + * @brief Stop BPWM generation immediately by clear channel enable bit + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @return None + * @details This function is used to stop BPWM generation immediately by clear channel enable bit. + * @note All channels share one counter. + */ +void BPWM_ForceStop(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (bpwm)->CNTEN &= ~BPWM_CNTEN_CNTEN0_Msk; +} + +/** + * @brief Enable selected channel to trigger ADC + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Condition The condition to trigger ADC. Combination of following conditions: + * - \ref BPWM_TRIGGER_ADC_EVEN_ZERO_POINT + * - \ref BPWM_TRIGGER_ADC_EVEN_PERIOD_POINT + * - \ref BPWM_TRIGGER_ADC_EVEN_ZERO_OR_PERIOD_POINT + * - \ref BPWM_TRIGGER_ADC_EVEN_CMP_UP_COUNT_POINT + * - \ref BPWM_TRIGGER_ADC_EVEN_CMP_DOWN_COUNT_POINT + * - \ref BPWM_TRIGGER_ADC_ODD_CMP_UP_COUNT_POINT + * - \ref BPWM_TRIGGER_ADC_ODD_CMP_DOWN_COUNT_POINT + * @return None + * @details This function is used to enable selected channel to trigger ADC + */ +void BPWM_EnableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + if (u32ChannelNum < 4UL) + { + (bpwm)->EADCTS0 &= ~((BPWM_EADCTS0_TRGSEL0_Msk) << (u32ChannelNum << 3UL)); + (bpwm)->EADCTS0 |= ((BPWM_EADCTS0_TRGEN0_Msk | u32Condition) << (u32ChannelNum << 3UL)); + } + else + { + (bpwm)->EADCTS1 &= ~((BPWM_EADCTS1_TRGSEL4_Msk) << ((u32ChannelNum - 4UL) << 3UL)); + (bpwm)->EADCTS1 |= ((BPWM_EADCTS1_TRGEN4_Msk | u32Condition) << ((u32ChannelNum - 4UL) << 3UL)); + } +} + +/** + * @brief Disable selected channel to trigger ADC + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable selected channel to trigger ADC + */ +void BPWM_DisableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + if (u32ChannelNum < 4UL) + { + (bpwm)->EADCTS0 &= ~(BPWM_EADCTS0_TRGEN0_Msk << (u32ChannelNum << 3UL)); + } + else + { + (bpwm)->EADCTS1 &= ~(BPWM_EADCTS1_TRGEN4_Msk << ((u32ChannelNum - 4UL) << 3UL)); + } +} + +/** + * @brief Clear selected channel trigger ADC flag + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Condition This parameter is not used + * @return None + * @details This function is used to clear selected channel trigger ADC flag + */ +void BPWM_ClearADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + (bpwm)->STATUS = (BPWM_STATUS_EADCTRG0_Msk << u32ChannelNum); +} + +/** + * @brief Get selected channel trigger ADC flag + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @retval 0 The specified channel trigger ADC to start of conversion flag is not set + * @retval 1 The specified channel trigger ADC to start of conversion flag is set + * @details This function is used to get BPWM trigger ADC to start of conversion flag for specified channel + */ +uint32_t BPWM_GetADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + return (((bpwm)->STATUS & (BPWM_STATUS_EADCTRG0_Msk << u32ChannelNum)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture of selected channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to enable capture of selected channel(s) + */ +void BPWM_EnableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (bpwm)->CAPINEN |= u32ChannelMask; + (bpwm)->CAPCTL |= u32ChannelMask; +} + +/** + * @brief Disable capture of selected channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to disable capture of selected channel(s) + */ +void BPWM_DisableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (bpwm)->CAPINEN &= ~u32ChannelMask; + (bpwm)->CAPCTL &= ~u32ChannelMask; +} + +/** + * @brief Enables BPWM output generation of selected channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output... + * @return None + * @details This function is used to enables BPWM output generation of selected channel(s) + */ +void BPWM_EnableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (bpwm)->POEN |= u32ChannelMask; +} + +/** + * @brief Disables BPWM output generation of selected channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Set bit 0 to 1 disables channel 0 output, set bit 1 to 1 disables channel 1 output... + * @return None + * @details This function is used to disables BPWM output generation of selected channel(s) + */ +void BPWM_DisableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (bpwm)->POEN &= ~u32ChannelMask; +} + +/** + * @brief Enable capture interrupt of selected channel. + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref BPWM_CAPTURE_INT_RISING_LATCH + * - \ref BPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to enable capture interrupt of selected channel. + */ +void BPWM_EnableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (bpwm)->CAPIEN |= (u32Edge << u32ChannelNum); +} + +/** + * @brief Disable capture interrupt of selected channel. + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref BPWM_CAPTURE_INT_RISING_LATCH + * - \ref BPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to disable capture interrupt of selected channel. + */ +void BPWM_DisableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (bpwm)->CAPIEN &= ~(u32Edge << u32ChannelNum); +} + +/** + * @brief Clear capture interrupt of selected channel. + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref BPWM_CAPTURE_INT_RISING_LATCH + * - \ref BPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to clear capture interrupt of selected channel. + */ +void BPWM_ClearCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (bpwm)->CAPIF = (u32Edge << u32ChannelNum); +} + +/** + * @brief Get capture interrupt of selected channel. + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @retval 0 No capture interrupt + * @retval 1 Rising edge latch interrupt + * @retval 2 Falling edge latch interrupt + * @retval 3 Rising and falling latch interrupt + * @details This function is used to get capture interrupt of selected channel. + */ +uint32_t BPWM_GetCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + return (((((bpwm)->CAPIF & (BPWM_CAPIF_CAPFIF0_Msk << u32ChannelNum)) ? 1UL : 0UL) << 1UL) | \ + (((bpwm)->CAPIF & (BPWM_CAPIF_CAPRIF0_Msk << u32ChannelNum)) ? 1UL : 0UL)); +} +/** + * @brief Enable duty interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32IntDutyType Duty interrupt type, could be either + * - \ref BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP + * - \ref BPWM_DUTY_INT_UP_COUNT_MATCH_CMP + * @return None + * @details This function is used to enable duty interrupt of selected channel. + */ +void BPWM_EnableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType) +{ + (bpwm)->INTEN |= (u32IntDutyType << u32ChannelNum); +} + +/** + * @brief Disable duty interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable duty interrupt of selected channel + */ +void BPWM_DisableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (bpwm)->INTEN &= ~((uint32_t)(BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP | BPWM_DUTY_INT_UP_COUNT_MATCH_CMP) << u32ChannelNum); +} + +/** + * @brief Clear duty interrupt flag of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear duty interrupt flag of selected channel + */ +void BPWM_ClearDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (bpwm)->INTSTS = (BPWM_INTSTS_CMPUIF0_Msk | BPWM_INTSTS_CMPDIF0_Msk) << u32ChannelNum; +} + +/** + * @brief Get duty interrupt flag of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return Duty interrupt flag of specified channel + * @retval 0 Duty interrupt did not occur + * @retval 1 Duty interrupt occurred + * @details This function is used to get duty interrupt flag of selected channel + */ +uint32_t BPWM_GetDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + return ((((bpwm)->INTSTS & ((BPWM_INTSTS_CMPDIF0_Msk | BPWM_INTSTS_CMPUIF0_Msk) << u32ChannelNum))) ? 1UL : 0UL); +} + +/** + * @brief Enable period interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @param[in] u32IntPeriodType Period interrupt type. This parameter is not used. + * @return None + * @details This function is used to enable period interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_EnablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType) +{ + (bpwm)->INTEN |= BPWM_INTEN_PIEN0_Msk; +} + +/** + * @brief Disable period interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to disable period interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_DisablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (bpwm)->INTEN &= ~BPWM_INTEN_PIEN0_Msk; +} + +/** + * @brief Clear period interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to clear period interrupt of selected channel + * @note All channels share channel 0's setting. + */ +void BPWM_ClearPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (bpwm)->INTSTS = BPWM_INTSTS_PIF0_Msk; +} + +/** + * @brief Get period interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return Period interrupt flag of specified channel + * @retval 0 Period interrupt did not occur + * @retval 1 Period interrupt occurred + * @details This function is used to get period interrupt of selected channel + * @note All channels share channel 0's setting. + */ +uint32_t BPWM_GetPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + return (((bpwm)->INTSTS & BPWM_INTSTS_PIF0_Msk) ? 1UL : 0UL); +} + +/** + * @brief Enable zero interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to enable zero interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_EnableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (bpwm)->INTEN |= BPWM_INTEN_ZIEN0_Msk; +} + +/** + * @brief Disable zero interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to disable zero interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_DisableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (bpwm)->INTEN &= ~BPWM_INTEN_ZIEN0_Msk; +} + +/** + * @brief Clear zero interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to clear zero interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_ClearZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (bpwm)->INTSTS = BPWM_INTSTS_ZIF0_Msk; +} + +/** + * @brief Get zero interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return zero interrupt flag of specified channel + * @retval 0 zero interrupt did not occur + * @retval 1 zero interrupt occurred + * @details This function is used to get zero interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +uint32_t BPWM_GetZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + return (((bpwm)->INTSTS & BPWM_INTSTS_ZIF0_Msk) ? 1UL : 0UL); +} + +/** + * @brief Enable load mode of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32LoadMode BPWM counter loading mode. + * - \ref BPWM_LOAD_MODE_IMMEDIATE + * - \ref BPWM_LOAD_MODE_CENTER + * @return None + * @details This function is used to enable load mode of selected channel. + */ +void BPWM_EnableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode) +{ + (bpwm)->CTL0 |= (u32LoadMode << u32ChannelNum); +} + +/** + * @brief Disable load mode of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32LoadMode BPWM counter loading mode. + * - \ref BPWM_LOAD_MODE_IMMEDIATE + * - \ref BPWM_LOAD_MODE_CENTER + * @return None + * @details This function is used to disable load mode of selected channel. + */ +void BPWM_DisableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode) +{ + (bpwm)->CTL0 &= ~(u32LoadMode << u32ChannelNum); +} + +/** + * @brief Set BPWM clock source + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @param[in] u32ClkSrcSel BPWM external clock source. + * - \ref BPWM_CLKSRC_BPWM_CLK + * - \ref BPWM_CLKSRC_TIMER0 + * - \ref BPWM_CLKSRC_TIMER1 + * - \ref BPWM_CLKSRC_TIMER2 + * - \ref BPWM_CLKSRC_TIMER3 + * @return None + * @details This function is used to set BPWM clock source. + * @note All channels share channel 0's setting. + */ +void BPWM_SetClockSource(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel) +{ + (bpwm)->CLKSRC = (u32ClkSrcSel); +} + +/** + * @brief Get the time-base counter reached its maximum value flag of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return Count to max interrupt flag of specified channel + * @retval 0 Count to max interrupt did not occur + * @retval 1 Count to max interrupt occurred + * @details This function is used to get the time-base counter reached its maximum value flag of selected channel. + * @note All channels share channel 0's setting. + */ +uint32_t BPWM_GetWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + return (((bpwm)->STATUS & BPWM_STATUS_CNTMAX0_Msk) ? 1UL : 0UL); +} + +/** + * @brief Clear the time-base counter reached its maximum value flag of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to clear the time-base counter reached its maximum value flag of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_ClearWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (bpwm)->STATUS = BPWM_STATUS_CNTMAX0_Msk; +} + + +/*@}*/ /* end of group BPWM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group BPWM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_clk.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_clk.c new file mode 100644 index 00000000000..cb5f2fa8ff9 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_clk.c @@ -0,0 +1,1185 @@ +/**************************************************************************** + * @file clk.c + * @version V1.10 + * @brief M251 series CLK driver source file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CLK_Driver CLK Driver + @{ +*/ + +/** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions + @{ +*/ + +/** + * @brief Disable frequency output function + * @param None + * @return None + * @details This function disable frequency output function. + */ +void CLK_DisableCKO(void) +{ + /* Disable CKO clock source */ + CLK->APBCLK0 &= (~CLK_APBCLK0_CLKOCKEN_Msk); +} + +/** + * @brief This function enable frequency divider module clock. + * enable frequency divider clock function and configure frequency divider. + * @param[in] u32ClkSrc is frequency divider function clock source. Including : + * - \ref CLK_CLKSEL1_CLKOSEL_HXT + * - \ref CLK_CLKSEL1_CLKOSEL_LXT + * - \ref CLK_CLKSEL1_CLKOSEL_HCLK + * - \ref CLK_CLKSEL1_CLKOSEL_HIRC + * - \ref CLK_CLKSEL1_CLKOSEL_LIRC + * - \ref CLK_CLKSEL1_CLKOSEL_MIRC + * - \ref CLK_CLKSEL1_CLKOSEL_PLL + * - \ref CLK_CLKSEL1_CLKOSEL_SOF + * @param[in] u32ClkDiv is divider output frequency selection. + * @param[in] u32ClkDivBy1En is frequency divided by one enable. + * @return None + * + * @details Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv. + * The formula is: + * CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1) + * This function is just used to set CKO clock. + * User must enable I/O for CKO clock output pin by themselves. + */ +void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En) +{ + /* CKO = clock source / 2^(u32ClkDiv + 1) */ + CLK->CLKOCTL = CLK_CLKOCTL_CLKOEN_Msk | u32ClkDiv | (u32ClkDivBy1En << CLK_CLKOCTL_DIV1EN_Pos); + + /* Enable CKO clock source */ + CLK->APBCLK0 |= CLK_APBCLK0_CLKOCKEN_Msk; + + /* Select CKO clock source */ + CLK->CLKSEL1 = (CLK->CLKSEL1 & (~CLK_CLKSEL1_CLKOSEL_Msk)) | (u32ClkSrc); +} + +/** + * @brief Enter to Power-down mode + * @param None + * @return None + * @details This function is used to let system enter to Power-down mode. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_PowerDown(void) +{ + uint32_t u32HIRCTRIMCTL, u32MIRCTRIMCTL; + + /* Set the processor uses deep sleep as its low power mode */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Set system Power-down enabled */ + CLK->PWRCTL |= (CLK_PWRCTL_PDEN_Msk); + + /* Store HIRC/MIRC control register */ + u32HIRCTRIMCTL = SYS->HIRCTRIMCTL; + u32MIRCTRIMCTL = SYS->MIRCTRIMCTL; + + /* Disable HIRC/MIRC auto trim */ + SYS->HIRCTRIMCTL &= (~SYS_HIRCTRIMCTL_FREQSEL_Msk); + SYS->MIRCTRIMCTL &= (~SYS_MIRCTRIMCTL_FREQSEL_Msk); + + /* Chip enter Power-down mode after CPU run WFI instruction */ + __WFI(); + + /* Restore HIRC/MIRC control register */ + SYS->HIRCTRIMCTL = u32HIRCTRIMCTL; + SYS->MIRCTRIMCTL = u32MIRCTRIMCTL; +} + +/** + * @brief Enter to Idle mode + * @param None + * @return None + * @details This function let system enter to Idle mode. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_Idle(void) +{ + /* Set the processor uses sleep as its low power mode */ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + + /* Set chip in idle mode because of WFI command */ + CLK->PWRCTL &= ~CLK_PWRCTL_PDEN_Msk; + + /* Chip enter idle mode after CPU run WFI instruction */ + __WFI(); +} + +/** + * @brief Get external high speed crystal clock frequency + * @param None + * @return External high speed crystal frequency + * @details This function get external high speed crystal frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetHXTFreq(void) +{ + if (CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk) + return __HXT; + else + return 0UL; +} + +/** + * @brief Get external low speed crystal clock frequency + * @param None + * @return External low speed crystal clock frequency + * @details This function get external low frequency crystal frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetLXTFreq(void) +{ + if (CLK->PWRCTL & CLK_PWRCTL_LXTEN_Msk) + return __LXT; + else + return 0UL; +} + +/** + * @brief Get PCLK0 frequency + * @param None + * @return PCLK0 frequency + * @details This function get PCLK0 frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetPCLK0Freq(void) +{ + SystemCoreClockUpdate(); + + switch (CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) + { + case (CLK_PCLKDIV_APB0DIV_DIV1): + return SystemCoreClock; + + case (CLK_PCLKDIV_APB0DIV_DIV2): + return SystemCoreClock >> 1; + + case (CLK_PCLKDIV_APB0DIV_DIV4): + return SystemCoreClock >> 2; + + case (CLK_PCLKDIV_APB0DIV_DIV8): + return SystemCoreClock >> 3; + + case (CLK_PCLKDIV_APB0DIV_DIV16): + return SystemCoreClock >> 4; + + case (CLK_PCLKDIV_APB0DIV_DIV32): + return SystemCoreClock >> 5; + + default: + return 0UL; + } +} + +/** + * @brief Get PCLK1 frequency + * @param None + * @return PCLK1 frequency + * @details This function get PCLK1 frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetPCLK1Freq(void) +{ + SystemCoreClockUpdate(); + + switch (CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) + { + case (CLK_PCLKDIV_APB1DIV_DIV1): + return SystemCoreClock; + + case (CLK_PCLKDIV_APB1DIV_DIV2): + return SystemCoreClock >> 1; + + case (CLK_PCLKDIV_APB1DIV_DIV4): + return SystemCoreClock >> 2; + + case (CLK_PCLKDIV_APB1DIV_DIV8): + return SystemCoreClock >> 3; + + case (CLK_PCLKDIV_APB1DIV_DIV16): + return SystemCoreClock >> 4; + + case (CLK_PCLKDIV_APB1DIV_DIV32): + return SystemCoreClock >> 5; + + default: + return 0UL; + } +} + +/** + * @brief Get HCLK frequency + * @param None + * @return HCLK frequency + * @details This function get HCLK frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetHCLKFreq(void) +{ + SystemCoreClockUpdate(); + return SystemCoreClock; +} + +/** + * @brief Get CPU frequency + * @param None + * @return CPU frequency + * @details This function get CPU frequency. The frequency unit is Hz. + */ +uint32_t CLK_GetCPUFreq(void) +{ + SystemCoreClockUpdate(); + return SystemCoreClock; +} + +/** + * @brief Get PLL Clock Output Frequency + * + * @param None + * + * @return PLL clock output frequency + * + * @details To get actual PLL clock output frequency. The clock uint is in Hz. + */ +uint32_t CLK_GetPLLClockFreq(void) +{ + uint32_t u32PllFreq; + uint32_t u32FIN, u32NF, u32NR, u32NO; + uint8_t au8NoTbl[4] = {1u, 2u, 4u, 4u}; /* OUT_DV :DEF: {1, 2, 4, 4} */ + uint32_t u32Reg; + + u32PllFreq = 0UL; + u32Reg = CLK->PLLCTL; + + if ((u32Reg & (CLK_PLLCTL_PD_Msk | CLK_PLLCTL_OE_Msk)) == 0) + { + /* PLL is enabled and output enabled */ + if (u32Reg & CLK_PLLCTL_PLLSRC_Msk) + { + if ((u32Reg & CLK_PLLCTL_PLLSRC_Msk) == CLK_PLLCTL_PLLSRC_MIRC) + u32FIN = __MIRC; + else + u32FIN = (__HIRC >> 2); + } + else + u32FIN = __HXT; + + if (u32Reg & CLK_PLLCTL_BP_Msk) + { + /* PLL is in bypass mode */ + u32PllFreq = u32FIN; + } + else + { + /* PLL is in normal work mode */ + u32NO = au8NoTbl[((u32Reg & CLK_PLLCTL_OUTDIV_Msk) >> CLK_PLLCTL_OUTDIV_Pos)]; + u32NF = ((u32Reg & CLK_PLLCTL_FBDIV_Msk) >> CLK_PLLCTL_FBDIV_Pos); + u32NR = ((u32Reg & CLK_PLLCTL_INDIV_Msk) >> CLK_PLLCTL_INDIV_Pos); + /* u32FIN is shifted 2 bits to avoid overflow */ + u32PllFreq = (((u32FIN >> 2) * u32NF) / (u32NR * u32NO) << 2); + } + } + + return u32PllFreq; +} + +/** + * @brief Disable PLL + * @param None + * @return None + * @details This function set PLL in Power-down mode. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_DisablePLL(void) +{ + CLK->PLLCTL |= CLK_PLLCTL_PD_Msk; +} + +/** + * @brief Set PLL frequency + * @param[in] u32PllClkSrc is PLL clock source. Including : + * - \ref CLK_PLLCTL_PLLSRC_HXT + * - \ref CLK_PLLCTL_PLLSRC_HIRC_DIV4 + * - \ref CLK_PLLCTL_PLLSRC_MIRC + * @param[in] u32PllFreq is PLL frequency. + * @return PLL frequency + * @details This function is used to configure PLLCTL register to set specified PLL frequency. \n + * The register write-protection function should be disabled before using this function. + * The PLL output is least 16MHz at least if BP(CLK_PLLCTL[17]) is not set. + */ +uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq) +{ + uint32_t u32PllSrcClk, u32NR, u32NF, u32NO, u32ClkSrc; + uint32_t u32Tmp, u32Tmp2, u32Tmp3, u32Min, u32MinNF, u32MinNR, u32MinNO, u32PllBassFreq; + + /* Disable PLL first to avoid unstable when setting PLL */ + CLK_DisablePLL(); + + /* PLL source clock is from HXT */ + if (u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT) + { + /* Enable HXT clock */ + CLK->PWRCTL = (CLK->PWRCTL & ~CLK_PWRCTL_HXTEN_Msk) | CLK_PWRCTL_HXTEN_Msk; + + /* Wait for HXT clock ready */ + CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk); + + /* Select PLL source clock from HXT */ + u32ClkSrc = CLK_PLLCTL_PLLSRC_HXT; + u32PllSrcClk = __HXT;//12 MHz + } + /* PLL source clock is from HIRC_DIV4 */ + else if (u32PllClkSrc == CLK_PLLCTL_PLLSRC_HIRC_DIV4) + { + /* Enable HIRC clock */ + CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk; + /* Enable MIRC clock */ + CLK->PWRCTL |= CLK_PWRCTL_MIRCEN_Msk; + + /* Wait for HIRC clock ready */ + CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); + /* Wait for MIRC clock ready */ + CLK_WaitClockReady(CLK_STATUS_MIRCSTB_Msk); + + /* Select PLL source clock from HIRC_DIV4 */ + u32ClkSrc = CLK_PLLCTL_PLLSRC_HIRC_DIV4; + u32PllSrcClk = (__HIRC >> 2); //12 MHz + } + else + { + /* Enable MIRC clock */ + CLK->PWRCTL |= CLK_PWRCTL_MIRCEN_Msk; + /* Enable HIRC clock */ + CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk; + + /* Wait for MIRC clock ready */ + CLK_WaitClockReady(CLK_STATUS_MIRCSTB_Msk); + /* Wait for HIRC clock ready */ + CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); + + /* Select PLL source clock from MIRC */ + u32ClkSrc = CLK_PLLCTL_PLLSRC_MIRC; + u32PllSrcClk = __MIRC;//4 MHz + } + + if ((u32PllFreq <= FREQ_100MHZ) && (u32PllFreq >= FREQ_16MHZ)) + { + /* Find best solution */ + u32Min = (uint32_t) - 1UL; + u32MinNR = 0UL; + u32MinNF = 0UL; + u32MinNO = 0UL; + u32PllBassFreq = u32PllFreq; + + for (u32NO = 0UL; u32NO <= 3UL; u32NO++) + { + /* Break when get good results */ + if (u32Min == 0UL) + break; + + if (u32NO != 2UL) + { + if (u32NO == 3UL) + { + u32PllFreq = u32PllBassFreq << 2; + } + else if (u32NO == 1UL) + { + u32PllFreq = u32PllBassFreq << 1; + } + else + { + } + + for (u32NR = 1UL; u32NR <= 6UL; u32NR++) //u32PllSrcClk: MIRC:4M, HIRC_DIV4:12M, HXT:4~24M, 4 MHz <= u32Tmp + { + u32Tmp = u32PllSrcClk / u32NR; + + if (u32Tmp >= FREQ_4MHZ && u32Tmp <= FREQ_8MHZ) //4 MHz <= u32Tmp <= 8 MHz + { + for (u32NF = 8UL; u32NF <= 25UL; u32NF++) //4 MHz <= u32Tmp, u32Tmp2 <= FREQ_100MHZ + { + u32Tmp2 = u32Tmp * u32NF; + + if ((u32Tmp2 >= FREQ_64MHZ) && (u32Tmp2 <= FREQ_100MHZ)) + { + u32Tmp3 = (u32Tmp2 > u32PllFreq) ? (u32Tmp2 - u32PllFreq) : (u32PllFreq - u32Tmp2); + + if (u32NO == 3UL) + { + u32Tmp3 = u32Tmp3 >> 2; + } + else if (u32NO == 1UL) + { + u32Tmp3 = u32Tmp3 >> 1; + } + else + { + } + + if (u32Tmp3 < u32Min) + { + u32Min = u32Tmp3; + u32MinNR = u32NR; + u32MinNF = u32NF; + u32MinNO = u32NO; + + /* Break when get good results */ + if (u32Min == 0UL) + break; + } + } + } + } + } + } + } + } + else + { + /* Wrong frequency request. Just return default setting. */ + goto lexit; + } + + /* Enable and apply new PLL setting. */ + CLK->PLLCTL = u32ClkSrc | (u32MinNO << 14) | ((u32MinNR) << 9) | (u32MinNF); + //printf("\n u32ClkSrc %x, u32PllSrcClk %d, u32MinNO %d, u32MinNR %d, u32MinNF %d",u32ClkSrc,u32PllSrcClk,u32MinNO,u32MinNR,u32MinNF); + /* Wait for PLL clock stable */ + CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk); + //printf("\n u32PllSrcClk %d u32MinNO %d u32MinNR %d u32MinNF %d",u32PllSrcClk,u32MinNO,u32MinNR,u32MinNF); + /* Return actual PLL output clock frequency */ + return u32PllSrcClk / ((u32MinNO + 1UL) * u32MinNR) * u32MinNF; + +lexit: + + /* Apply PLL setting and return */ + if (u32PllFreq < FREQ_16MHZ) + { + if (u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT) + CLK->PLLCTL = CLK_PLLCTL_16MHz_HXT; + else if (u32PllClkSrc == CLK_PLLCTL_PLLSRC_HIRC_DIV4) + CLK->PLLCTL = CLK_PLLCTL_16MHz_HIRC_DIV4; + else + CLK->PLLCTL = CLK_PLLCTL_16MHz_MIRC; + } + else + { + if (u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT) + CLK->PLLCTL = CLK_PLLCTL_100MHz_HXT; + else if (u32PllClkSrc == CLK_PLLCTL_PLLSRC_HIRC_DIV4) + CLK->PLLCTL = CLK_PLLCTL_100MHz_HIRC_DIV4; + else + CLK->PLLCTL = CLK_PLLCTL_100MHz_MIRC; + } + + /* Wait for PLL clock stable */ + CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk); + + return CLK_GetPLLClockFreq(); + +} + +/** + * @brief Set HCLK clock source and HCLK clock divider + * @param[in] u32ClkSrc is HCLK clock source. Including : + * - \ref CLK_CLKSEL0_HCLKSEL_HXT + * - \ref CLK_CLKSEL0_HCLKSEL_LXT + * - \ref CLK_CLKSEL0_HCLKSEL_PLL + * - \ref CLK_CLKSEL0_HCLKSEL_LIRC + * - \ref CLK_CLKSEL0_HCLKSEL_MIRC + * - \ref CLK_CLKSEL0_HCLKSEL_HIRC + * @param[in] u32ClkDiv is HCLK clock divider. Including : + * - \ref CLK_CLKDIV0_HCLK(x) + * @return None + * @details This function set HCLK clock source and HCLK clock divider. + * The register write-protection function should be disabled before using this function. + * @note Must be care of flash access cycle control when using this function + */ +void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv) +{ + uint32_t u32HircStable; + + /* Read HIRC clock source stable flag */ + u32HircStable = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk; + + /* Switch to HIRC for Safe. Avoid HCLK too high when applying new divider. */ + CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk; + CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); + CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | CLK_CLKSEL0_HCLKSEL_HIRC; + + /* Apply new Divider */ + CLK->CLKDIV0 = (CLK->CLKDIV0 & (~CLK_CLKDIV0_HCLKDIV_Msk)) | u32ClkDiv; + + /* Switch HCLK to new HCLK source */ + CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | u32ClkSrc; + + /* Update System Core Clock */ + SystemCoreClockUpdate(); + + /* Disable HIRC if HIRC is disabled before switching HCLK source */ + if (u32HircStable == 0UL) + CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk; +} + +/** + * @brief Set HCLK frequency + * @param[in] u32Hclk is HCLK frequency. The range of u32Hclk is 25 MHz ~ 48 MHz. + * @return HCLK frequency + * @details This function is used to set HCLK frequency. The frequency unit is Hz. \n + * It would configure PLL frequency to 50MHz ~ 96MHz, + * set HCLK clock divider as 2 and switch HCLK clock source to PLL. \n + * The register write-protection function should be disabled before using this function. + */ +uint32_t CLK_SetCoreClock(uint32_t u32Hclk) +{ + uint32_t u32PllclkSet; + + /* The range of u32Hclk is 25 MHz ~ 48 MHz */ + if (u32Hclk > FREQ_48MHZ) + u32Hclk = FREQ_48MHZ; + + if (u32Hclk < FREQ_25MHZ) + u32Hclk = FREQ_25MHZ; + + /* Switch HCLK clock source to MIRC clock for safe */ + CLK->PWRCTL |= CLK_PWRCTL_MIRCEN_Msk; + CLK_WaitClockReady(CLK_STATUS_MIRCSTB_Msk); + CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_MIRC, CLK_CLKDIV0_HCLK(1)); + + u32PllclkSet = (u32Hclk << 1); + + /* Configure PLL setting if HXT clock is stable */ + if (CLK->STATUS & CLK_STATUS_HXTSTB_Msk) + u32PllclkSet = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HXT, u32PllclkSet); + + /* Configure PLL setting if HXT clock is not stable, MIRC & HIRC clock is stable */ + else if ((CLK->STATUS & CLK_STATUS_MIRCSTB_Msk) && (CLK->STATUS & CLK_STATUS_HIRCSTB_Msk)) + { + u32PllclkSet = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HIRC_DIV4, u32PllclkSet); + } + else + return 0UL; + + /* Select HCLK clock source to PLL, + Select HCLK clock source divider as 2 + and update system core clock + then Return actually HCLK frequency + */ + CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL, CLK_CLKDIV0_HCLK(2)); + return (u32PllclkSet >> 1); +} + +/** + * @brief This function set selected module clock source and module clock divider + * @param[in] u32ModuleIdx is module index. + * @param[in] u32ClkSrc is module clock source. + * @param[in] u32ClkDiv is module clock divider. + * @return None + * @details Valid parameter combinations listed in following table: + * + * |Module index |Clock source |Divider | + * | :---------------- | :----------------------------------- | :--------------------- | + * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 | x | + * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LXT | x | + * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LIRC | x | + * |\ref EADC_MODULE |x |\ref CLK_CLKDIV0_EADC(x)| + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HXT | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LXT | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_PCLK0 | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_EXT_TRG | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LIRC | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HIRC | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HXT | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LXT | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_PCLK0 | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_EXT_TRG | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LIRC | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HIRC | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HXT | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LXT | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_PCLK1 | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_EXT_TRG | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LIRC | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HIRC | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HXT | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LXT | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_PCLK1 | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_EXT_TRG | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LIRC | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HIRC | x | + * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_HXT |\ref CLK_CLKDIV0_UART0(x)| + * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_PLL |\ref CLK_CLKDIV0_UART0(x)| + * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_LXT |\ref CLK_CLKDIV0_UART0(x)| + * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_HIRC |\ref CLK_CLKDIV0_UART0(x)| + * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_PCLK0 |\ref CLK_CLKDIV0_UART0(x)| + * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_LIRC |\ref CLK_CLKDIV0_UART0(x)| + * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_HXT |\ref CLK_CLKDIV0_UART1(x)| + * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_PLL |\ref CLK_CLKDIV0_UART1(x)| + * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_LXT |\ref CLK_CLKDIV0_UART1(x)| + * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_HIRC |\ref CLK_CLKDIV0_UART1(x)| + * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_PCLK1 |\ref CLK_CLKDIV0_UART1(x)| + * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_LIRC |\ref CLK_CLKDIV0_UART1(x)| + * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_HXT |\ref CLK_CLKDIV4_UART2(x)| + * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_PLL |\ref CLK_CLKDIV4_UART2(x)| + * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_LXT |\ref CLK_CLKDIV4_UART2(x)| + * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_HIRC |\ref CLK_CLKDIV4_UART2(x)| + * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_PCLK0 |\ref CLK_CLKDIV4_UART2(x)| + * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_LIRC |\ref CLK_CLKDIV4_UART2(x)| + * |\ref BPWM0_MODULE |\ref CLK_CLKSEL2_BPWM0SEL_PLL | x | + * |\ref BPWM0_MODULE |\ref CLK_CLKSEL2_BPWM0SEL_PCLK0 | x | + * |\ref BPWM1_MODULE |\ref CLK_CLKSEL2_BPWM1SEL_PLL | x | + * |\ref BPWM1_MODULE |\ref CLK_CLKSEL2_BPWM1SEL_PCLK1 | x | + * |\ref PWM0_MODULE |\ref CLK_CLKSEL2_PWM0SEL_PLL | x | + * |\ref PWM0_MODULE |\ref CLK_CLKSEL2_PWM0SEL_PCLK0 | x | + * |\ref PWM1_MODULE |\ref CLK_CLKSEL2_PWM1SEL_PLL | x | + * |\ref PWM1_MODULE |\ref CLK_CLKSEL2_PWM1SEL_PCLK1 | x | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HXT | x | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_LXT | x | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HCLK | x | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HIRC | x | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_LIRC | x | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_MIRC | x | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_PLL | x | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_SOF | x | + * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 | x | + * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_LIRC | x | + * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_HXT | x | + * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_PLL | x | + * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_PCLK0 | x | + * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_HIRC | x | + * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_HXT | x | + * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_PLL | x | + * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_PCLK1 | x | + * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_HIRC | x | + * |\ref USBD_MODULE |\ref CLK_CLKSEL0_USBDSEL_HIRC |\ref CLK_CLKDIV0_USB(x) | + * |\ref USBD_MODULE |\ref CLK_CLKSEL0_USBDSEL_PLL |\ref CLK_CLKDIV0_USB(x) | + * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HXT |\ref CLK_CLKDIV1_SC0(x) | + * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PLL |\ref CLK_CLKDIV1_SC0(x) | + * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PCLK0 |\ref CLK_CLKDIV1_SC0(x) | + * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HIRC |\ref CLK_CLKDIV1_SC0(x) | + * |\ref PSIO_MODULE |\ref CLK_CLKSEL2_PSIOSEL_HXT |\ref CLK_CLKDIV1_PSIO(x)| + * |\ref PSIO_MODULE |\ref CLK_CLKSEL2_PSIOSEL_LXT |\ref CLK_CLKDIV1_PSIO(x)| + * |\ref PSIO_MODULE |\ref CLK_CLKSEL2_PSIOSEL_PCLK1 |\ref CLK_CLKDIV1_PSIO(x)| + * |\ref PSIO_MODULE |\ref CLK_CLKSEL2_PSIOSEL_PLL |\ref CLK_CLKDIV1_PSIO(x)| + * |\ref PSIO_MODULE |\ref CLK_CLKSEL2_PSIOSEL_LIRC |\ref CLK_CLKDIV1_PSIO(x)| + * |\ref PSIO_MODULE |\ref CLK_CLKSEL2_PSIOSEL_HIRC |\ref CLK_CLKDIV1_PSIO(x)| + */ +void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv) +{ + uint32_t u32Sel = 0UL, u32Div = 0UL; + uint32_t au32SelTbl[] = {0x0UL, 0x4UL, 0x8UL, 0xCUL}; + uint32_t au32DivTbl[] = {0x0UL, 0x4UL, 0xCUL, 0x10UL}; + + if (MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk) + { + /* Get clock divider control register address */ + u32Div = (uint32_t)&CLK->CLKDIV0 + (au32DivTbl[MODULE_CLKDIV(u32ModuleIdx)]); + /* Apply new divider */ + M32(u32Div) = (M32(u32Div) & (~(MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx)))) | u32ClkDiv; + } + + if (MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk) + { + /* Get clock select control register address */ + u32Sel = (uint32_t)&CLK->CLKSEL0 + (au32SelTbl[MODULE_CLKSEL(u32ModuleIdx)]); + /* Set new clock selection setting */ + M32(u32Sel) = (M32(u32Sel) & (~(MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx)))) | u32ClkSrc; + } +} + +/** + * @brief Set SysTick clock source + * @param[in] u32ClkSrc is module clock source. Including: + * - \ref CLK_CLKSEL0_STCLKSEL_HXT + * - \ref CLK_CLKSEL0_STCLKSEL_LXT + * - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2 + * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 + * - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 + * @return None + * @details This function set SysTick clock source. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc) +{ + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc; +} + +/** + * @brief Enable clock source + * @param[in] u32ClkMask is clock source mask. Including : + * - \ref CLK_PWRCTL_HXTEN_Msk + * - \ref CLK_PWRCTL_LXTEN_Msk + * - \ref CLK_PWRCTL_HIRCEN_Msk + * - \ref CLK_PWRCTL_LIRCEN_Msk + * - \ref CLK_PWRCTL_MIRCEN_Msk + * @return None + * @details This function enable clock source. \n + * The register write-protection function should be disabled before using this function. + * Notice that HXT and LXT are using commmon pin, + * that is the two clock(HXT, LXT) sources are mutual exclusive. + * So parameters, CLK_PWRCTL_HXTEN and CLK_PWRCTL_LXTEN, can not be applied at the same time. + * In other word, user should make sure that LXT is disabled if user want to enable HXT. + * user should disable HXT if user want to enable LXT. + */ +void CLK_EnableXtalRC(uint32_t u32ClkMask) +{ + CLK->PWRCTL |= u32ClkMask; +} + +/** + * @brief Disable clock source + * @param[in] u32ClkMask is clock source mask. Including : + * - \ref CLK_PWRCTL_HXTEN_Msk + * - \ref CLK_PWRCTL_LXTEN_Msk + * - \ref CLK_PWRCTL_HIRCEN_Msk + * - \ref CLK_PWRCTL_LIRCEN_Msk + * - \ref CLK_PWRCTL_MIRCEN_Msk + * @return None + * @details This function disable clock source. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_DisableXtalRC(uint32_t u32ClkMask) +{ + CLK->PWRCTL &= ~u32ClkMask; + // M252_LIRC need 1/2 LIRC delay(1000000/38400/2=13us) + if(u32ClkMask == CLK_PWRCTL_LIRCEN_Msk){ + SystemCoreClockUpdate(); + CLK_SysTickDelay(13); + } +} + +/** + * @brief This function enable module clock + * @param[in] u32ModuleIdx is module index. Including : + * - \ref PDMA_MODULE + * - \ref ISP_MODULE + * - \ref CRC_MODULE + * - \ref EBI_MODULE + * - \ref CRPT_MODULE + * - \ref FMCIDLE_MODULE + * - \ref WDT_MODULE + * - \ref WWDT_MODULE + * - \ref RTC_MODULE + * - \ref TMR0_MODULE + * - \ref TMR1_MODULE + * - \ref TMR2_MODULE + * - \ref TMR3_MODULE + * - \ref CLKO_MODULE + * - \ref I2C0_MODULE + * - \ref I2C1_MODULE + * - \ref QSPI0_MODULE + * - \ref SPI0_MODULE + * - \ref UART0_MODULE + * - \ref UART1_MODULE + * - \ref UART2_MODULE + * - \ref ACMP01_MODULE + * - \ref EADC_MODULE + * - \ref USBD_MODULE + * - \ref USCI0_MODULE + * - \ref USCI1_MODULE + * - \ref USCI2_MODULE + * - \ref BPWM0_MODULE + * - \ref BPWM1_MODULE + * - \ref PWM0_MODULE + * - \ref PWM1_MODULE + * - \ref DAC_MODULE + * - \ref OPA_MODULE + * - \ref SC0_MODULE + * - \ref PSIO_MODULE + * @return None + * @details This function enable module clock. + */ +void CLK_EnableModuleClock(uint32_t u32ModuleIdx) +{ + uint32_t au32ClkTbl[3] = {0x0UL, 0x4UL, 0x8UL}; + + *(volatile uint32_t *)((uint32_t)&CLK->AHBCLK + (au32ClkTbl[MODULE_APBCLK(u32ModuleIdx)])) |= 1 << MODULE_IP_EN_Pos(u32ModuleIdx); +} + +/** + * @brief This function disable module clock + * @param[in] u32ModuleIdx is module index + * - \ref PDMA_MODULE + * - \ref ISP_MODULE + * - \ref CRC_MODULE + * - \ref EBI_MODULE + * - \ref CRPT_MODULE + * - \ref FMCIDLE_MODULE + * - \ref WDT_MODULE + * - \ref WWDT_MODULE + * - \ref RTC_MODULE + * - \ref TMR0_MODULE + * - \ref TMR1_MODULE + * - \ref TMR2_MODULE + * - \ref TMR3_MODULE + * - \ref CLKO_MODULE + * - \ref I2C0_MODULE + * - \ref I2C1_MODULE + * - \ref QSPI0_MODULE + * - \ref SPI0_MODULE + * - \ref UART0_MODULE + * - \ref UART1_MODULE + * - \ref UART2_MODULE + * - \ref ACMP01_MODULE + * - \ref EADC_MODULE + * - \ref USBD_MODULE + * - \ref USCI0_MODULE + * - \ref USCI1_MODULE + * - \ref USCI2_MODULE + * - \ref BPWM0_MODULE + * - \ref BPWM1_MODULE + * - \ref PWM0_MODULE + * - \ref PWM1_MODULE + * - \ref DAC_MODULE + * - \ref OPA_MODULE + * - \ref SC0_MODULE + * - \ref PSIO_MODULE + * @return None + * @details This function disable module clock. + */ +void CLK_DisableModuleClock(uint32_t u32ModuleIdx) +{ + uint32_t au32ClkTbl[3] = {0x0UL, 0x4UL, 0x8UL}; + + *(volatile uint32_t *)((uint32_t)&CLK->AHBCLK + (au32ClkTbl[MODULE_APBCLK(u32ModuleIdx)])) &= ~(1 << MODULE_IP_EN_Pos(u32ModuleIdx)); +} + +/** + * @brief This function check selected clock source status + * @param[in] u32ClkMask is selected clock source. Including : + * - \ref CLK_STATUS_HXTSTB_Msk + * - \ref CLK_STATUS_LXTSTB_Msk + * - \ref CLK_STATUS_HIRCSTB_Msk + * - \ref CLK_STATUS_LIRCSTB_Msk + * - \ref CLK_STATUS_MIRCSTB_Msk + * - \ref CLK_STATUS_PLLSTB_Msk + * @retval 0 clock is not stable + * @retval 1 clock is stable + * @details To wait for clock ready by specified clock source stable flag or timeout (~300ms) + */ +uint32_t CLK_WaitClockReady(uint32_t u32ClkMask) +{ + int32_t i32TimeOutCnt = 2160000; + + while ((CLK->STATUS & u32ClkMask) != u32ClkMask) + { + if (i32TimeOutCnt-- <= 0) + return 0UL; + } + + return 1UL; +} + +/** + * @brief Enable System Tick counter + * @param[in] u32ClkSrc is System Tick clock source. Including: + * - \ref CLK_CLKSEL0_STCLKSEL_HXT + * - \ref CLK_CLKSEL0_STCLKSEL_LXT + * - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2 + * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 + * - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 + * - \ref CLK_CLKSEL0_STCLKSEL_HCLK + * @param[in] u32Count is System Tick reload value. It could be 0~0xFFFFFF. + * @return None + * @details This function set System Tick clock source, reload value, enable System Tick counter and interrupt. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count) +{ + /* Set System Tick counter disabled */ + SysTick->CTRL = 0UL; + + /* Set System Tick clock source */ + if (u32ClkSrc == CLK_CLKSEL0_STCLKSEL_HCLK) + SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk; + else + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc; + + /* Set System Tick reload value */ + SysTick->LOAD = u32Count; + + /* Clear System Tick current value and counter flag */ + SysTick->VAL = 0UL; + + /* Set System Tick interrupt enabled and counter enabled */ + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; +} + +/** + * @brief Disable System Tick counter + * @param None + * @return None + * @details This function disable System Tick counter. + */ +void CLK_DisableSysTick(void) +{ + /* Set System Tick counter disabled */ + SysTick->CTRL = 0UL; +} + + +/** + * @brief Power-down mode selected + * @param[in] u32PDMode is power down mode index. Including : + * - \ref CLK_PMUCTL_PDMSEL_PD + * - \ref CLK_PMUCTL_PDMSEL_FWPD + * - \ref CLK_PMUCTL_PDMSEL_DPD + * @return None + * @details This function is used to set power-down mode. + */ + +void CLK_SetPowerDownMode(uint32_t u32PDMode) +{ + CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_PDMSEL_Msk)) | u32PDMode; +} + +/** + * @brief Set Wake-up pin trigger type at Deep Power down mode + * + * @param[in] u32Pin The pin of specified GPIO. + * CLK_DPDWKPIN_0:GPC.0, CLK_DPDWKPIN_1:GPB.0, CLK_DPDWKPIN_2:GPB.2, CLK_DPDWKPIN_3:GPB.12, CLK_DPDWKPIN_4:GPF.6 + * - \ref CLK_DPDWKPIN_0 + * - \ref CLK_DPDWKPIN_1 + * - \ref CLK_DPDWKPIN_2 + * - \ref CLK_DPDWKPIN_3 + * - \ref CLK_DPDWKPIN_4 + * @param[in] u32TriggerType + * - \ref CLK_DPDWKPIN_RISING + * - \ref CLK_DPDWKPIN_FALLING + * - \ref CLK_DPDWKPIN_BOTHEDGE + * @return None + * + * @details This function is used to enable Wake-up pin trigger type. + */ + +void CLK_EnableDPDWKPin(uint32_t u32Pin, uint32_t u32TriggerType) +{ + switch (u32Pin) + { + case CLK_DPDWKPIN_0: + CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN0_Msk)) | (u32TriggerType << CLK_PMUCTL_WKPINEN0_Pos); + break; + + case CLK_DPDWKPIN_1: + CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN1_Msk)) | (u32TriggerType << CLK_PMUCTL_WKPINEN1_Pos); + break; + + case CLK_DPDWKPIN_2: + CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN2_Msk)) | (u32TriggerType << CLK_PMUCTL_WKPINEN2_Pos); + break; + + case CLK_DPDWKPIN_3: + CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN3_Msk)) | (u32TriggerType << CLK_PMUCTL_WKPINEN3_Pos); + break; + + case CLK_DPDWKPIN_4: + CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN4_Msk)) | (u32TriggerType << CLK_PMUCTL_WKPINEN4_Pos); + break; + } +} + +/** + * @brief Set Wake-up pin0 (GPC.0) trigger type at Deep Power down mode + * + * @param[in] u32TriggerType + * - \ref CLK_DPDWKPIN0_RISING + * - \ref CLK_DPDWKPIN0_FALLING + * - \ref CLK_DPDWKPIN0_BOTHEDGE + * @return None + * + * @details This function is used to enable Wake-up pin0 (GPC.0) trigger type. + */ + +void CLK_EnableDPDWKPin0(uint32_t u32TriggerType) +{ + CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN0_Msk)) | u32TriggerType; +} + +/** + * @brief Set Wake-up pin1 (GPB.0) trigger type at Deep Power down mode + * + * @param[in] u32TriggerType + * - \ref CLK_DPDWKPIN1_RISING + * - \ref CLK_DPDWKPIN1_FALLING + * - \ref CLK_DPDWKPIN1_BOTHEDGE + * @return None + * + * @details This function is used to enable Wake-up pin1 (GPB.0) trigger type. + */ + +void CLK_EnableDPDWKPin1(uint32_t u32TriggerType) +{ + CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN1_Msk)) | u32TriggerType; +} + +/** + * @brief Set Wake-up pin2 (GPB.2) trigger type at Deep Power down mode + * + * @param[in] u32TriggerType + * - \ref CLK_DPDWKPIN2_RISING + * - \ref CLK_DPDWKPIN2_FALLING + * - \ref CLK_DPDWKPIN2_BOTHEDGE + * @return None + * + * @details This function is used to enable Wake-up pin2 (GPB.2) trigger type. + */ + +void CLK_EnableDPDWKPin2(uint32_t u32TriggerType) +{ + CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN2_Msk)) | u32TriggerType; +} + +/** + * @brief Set Wake-up pin3 (GPB.12) trigger type at Deep Power down mode + * + * @param[in] u32TriggerType + * - \ref CLK_DPDWKPIN3_RISING + * - \ref CLK_DPDWKPIN3_FALLING + * - \ref CLK_DPDWKPIN3_BOTHEDGE + * @return None + * + * @details This function is used to enable Wake-up pin3 (GPB.12) trigger type. + */ + +void CLK_EnableDPDWKPin3(uint32_t u32TriggerType) +{ + CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN3_Msk)) | u32TriggerType; +} + +/** + * @brief Set Wake-up pin4 (GPF.6) trigger type at Deep Power down mode + * + * @param[in] u32TriggerType + * - \ref CLK_DPDWKPIN4_RISING + * - \ref CLK_DPDWKPIN4_FALLING + * - \ref CLK_DPDWKPIN4_BOTHEDGE + * @return None + * + * @details This function is used to enable Wake-up pin4 (GPF.6) trigger type. + */ + +void CLK_EnableDPDWKPin4(uint32_t u32TriggerType) +{ + CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN4_Msk)) | u32TriggerType; +} + +/** + * @brief Get power manager wake up source + * + * @param[in] None + * @return Wake up source + * + * @details This function get power manager wake up source. + */ + +uint32_t CLK_GetPMUWKSrc(void) +{ + return (CLK->PMUSTS); +} + + +/** + * @brief Get selected module clock source + * @param[in] u32ModuleIdx is module index + * - \ref WDT_MODULE + * - \ref WWDT_MODULE + * - \ref TMR0_MODULE + * - \ref TMR1_MODULE + * - \ref TMR2_MODULE + * - \ref TMR3_MODULE + * - \ref CLKO_MODULE + * - \ref QSPI0_MODULE + * - \ref SPI0_MODULE + * - \ref UART0_MODULE + * - \ref UART1_MODULE + * - \ref UART2_MODULE + * - \ref USBD_MODULE + * - \ref BPWM0_MODULE + * - \ref BPWM1_MODULE + * - \ref PWM0_MODULE + * - \ref PWM1_MODULE + * - \ref SC0_MODULE + * - \ref PSIO_MODULE + * @return Selected module clock source setting + * @details This function get selected module clock source. + */ + +uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx) +{ + uint32_t u32TmpVal = 0UL, u32TmpAddr = 0UL; + uint32_t au32SelTbl[4] = {0x0UL, 0x4UL, 0x8UL, 0xCUL}; + + /* Get clock source selection setting */ + if (u32ModuleIdx == PWM0_MODULE) + { + u32TmpVal = ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM0SEL_Msk) >> CLK_CLKSEL2_PWM0SEL_Pos); + } + else if (u32ModuleIdx == PWM1_MODULE) + { + u32TmpVal = ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1SEL_Msk) >> CLK_CLKSEL2_PWM1SEL_Pos); + } + else if (u32ModuleIdx == BPWM0_MODULE) + { + u32TmpVal = ((CLK->CLKSEL2 & CLK_CLKSEL2_BPWM0SEL_Msk) >> CLK_CLKSEL2_BPWM0SEL_Pos); + } + else if (u32ModuleIdx == BPWM1_MODULE) + { + u32TmpVal = ((CLK->CLKSEL2 & CLK_CLKSEL2_BPWM1SEL_Msk) >> CLK_CLKSEL2_BPWM1SEL_Pos); + } + else if (MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk) + { + /* Get clock select control register address */ + u32TmpAddr = (uint32_t)&CLK->CLKSEL0 + (au32SelTbl[MODULE_CLKSEL(u32ModuleIdx)]); + + /* Get clock source selection setting */ + u32TmpVal = ((inpw((uint32_t *)u32TmpAddr) & (MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx))) >> MODULE_CLKSEL_Pos(u32ModuleIdx)); + } + + return u32TmpVal; +} + +/** + * @brief Get selected module clock divider number + * @param[in] u32ModuleIdx is module index. + * - \ref UART0_MODULE + * - \ref UART1_MODULE + * - \ref UART2_MODULE + * - \ref EADC_MODULE + * - \ref USBD_MODULE + * - \ref SC0_MODULE + * - \ref PSIO_MODULE + * @return Selected module clock divider number setting + * @details This function get selected module clock divider number. + */ + +uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx) +{ + uint32_t u32TmpVal = 0UL, u32TmpAddr = 0UL; + uint32_t au32DivTbl[4] = {0x0UL, 0x4UL, 0x8UL, 0x10UL}; + + if (MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk) + { + /* Get clock divider control register address */ + u32TmpAddr = (uint32_t)&CLK->CLKDIV0 + (au32DivTbl[MODULE_CLKDIV(u32ModuleIdx)]); + /* Get clock divider number setting */ + u32TmpVal = ((inpw((uint32_t *)u32TmpAddr) & (MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx))) >> MODULE_CLKDIV_Pos(u32ModuleIdx)); + } + + return u32TmpVal; +} + +/*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CLK_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_crc.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_crc.c new file mode 100644 index 00000000000..01c00d61d08 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_crc.c @@ -0,0 +1,97 @@ +/**************************************************************************//** + * @file crc.c + * @version V0.10 + * @brief M251 CRC driver source file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include "NuMicro.h" +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CRC_Driver CRC Driver + @{ +*/ + +/** @addtogroup CRC_EXPORTED_FUNCTIONS CRC Exported Functions + @{ +*/ + +/** + * @brief CRC Open + * + * @param[in] u32Mode CRC operation polynomial mode. Valid values are: + * - \ref CRC_CCITT + * - \ref CRC_8 + * - \ref CRC_16 + * - \ref CRC_32 + * @param[in] u32Attribute CRC operation data attribute. Valid values are combined with: + * - \ref CRC_CHECKSUM_COM + * - \ref CRC_CHECKSUM_RVS + * - \ref CRC_WDATA_COM + * - \ref CRC_WDATA_RVS + * @param[in] u32Seed Seed value. + * @param[in] u32DataLen CPU Write Data Length. Valid values are: + * - \ref CRC_CPU_WDATA_8 + * - \ref CRC_CPU_WDATA_16 + * - \ref CRC_CPU_WDATA_32 + * + * @return None + * + * @details This function will enable the CRC controller by specify CRC operation mode, attribute, initial seed and write data length. \n + * After that, user can start to perform CRC calculate by calling CRC_WRITE_DATA macro or CRC_DAT register directly. + */ +void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen) +{ + CRC->SEED = u32Seed; + CRC->CTL = u32Mode | u32Attribute | u32DataLen | CRC_CTL_CRCEN_Msk; + + /* Setting CHKSINIT bit will reload the initial seed value(CRC_SEED register) to CRC controller */ + CRC->CTL |= CRC_CTL_CHKSINIT_Msk; +} + +/** + * @brief Get CRC Checksum + * + * @param[in] None + * + * @return Checksum Result + * + * @details This function gets the CRC checksum result by current CRC polynomial mode. + */ +uint32_t CRC_GetChecksum(void) +{ + uint32_t ret; + + switch (CRC->CTL & CRC_CTL_CRCMODE_Msk) + { + case CRC_CCITT: + case CRC_16: + ret = (CRC->CHECKSUM & 0xFFFFU); + break; + + case CRC_32: + ret = (CRC->CHECKSUM); + break; + + case CRC_8: + ret = (CRC->CHECKSUM & 0xFFU); + break; + + default: + ret = 0U; + break; + } + + return ret; +} + +/*@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CRC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_crypto.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_crypto.c new file mode 100644 index 00000000000..75166a76549 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_crypto.c @@ -0,0 +1,229 @@ +/**************************************************************************//** + * @file crypto.c + * @version V1.10 + * @brief Cryptographic Accelerator driver source file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include +#include "NuMicro.h" + +#define ENABLE_DEBUG 0 + +#if ENABLE_DEBUG + #define CRPT_DBGMSG printf +#else + #define CRPT_DBGMSG(...) do { } while (0) /* disable debug */ +#endif + +#if defined(__ICCARM__) + #pragma diag_suppress=Pm073, Pm143 /* Misra C rule 14.7 */ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CRYPTO_Driver CRYPTO Driver + @{ +*/ + + +/** @addtogroup CRYPTO_EXPORTED_FUNCTIONS CRYPTO Exported Functions + @{ +*/ + +/* // @cond HIDDEN_SYMBOLS */ + +static uint32_t g_AES_au32CTL[1]; + +/* // @endcond HIDDEN_SYMBOLS */ + +/** + * @brief Open PRNG function + * @param[in] crpt Reference to Crypto module. + * @param[in] u32KeySize is PRNG key size, including: + * - \ref PRNG_KEY_SIZE_64 + * - \ref PRNG_KEY_SIZE_128 + * - \ref PRNG_KEY_SIZE_192 + * - \ref PRNG_KEY_SIZE_256 + * @param[in] u32SeedReload is PRNG seed reload or not, including: + * - \ref PRNG_SEED_CONT + * - \ref PRNG_SEED_RELOAD + * @param[in] u32Seed The new seed. Only valid when u32SeedReload is PRNG_SEED_RELOAD. + * @return None + */ +void PRNG_Open(CRPT_T *crpt, uint32_t u32KeySize, uint32_t u32SeedReload, uint32_t u32Seed) +{ + if (u32SeedReload) + { + crpt->PRNG_SEED = u32Seed; + } + + crpt->PRNG_CTL = (u32KeySize << CRPT_PRNG_CTL_KEYSZ_Pos) | + (u32SeedReload << CRPT_PRNG_CTL_SEEDRLD_Pos); +} + +/** + * @brief Start to generate one PRNG key. + * @param[in] crpt Reference to Crypto module. + * @return None + */ +void PRNG_Start(CRPT_T *crpt) +{ + crpt->PRNG_CTL |= CRPT_PRNG_CTL_START_Msk; +} + +/** + * @brief Read the PRNG key. + * @param[in] crpt Reference to Crypto module. + * @param[out] au32RandKey The key buffer to store newly generated PRNG key. + * @return None + */ +void PRNG_Read(CRPT_T *crpt, uint32_t au32RandKey[]) +{ + uint32_t u32Idx, u32Wcnt; + + u32Wcnt = (((crpt->PRNG_CTL & CRPT_PRNG_CTL_KEYSZ_Msk) >> CRPT_PRNG_CTL_KEYSZ_Pos) + 1U) * 2U; + + for (u32Idx = 0U; u32Idx < u32Wcnt; u32Idx++) + { + au32RandKey[u32Idx] = crpt->PRNG_KEY[u32Idx]; + } + + crpt->PRNG_CTL &= ~CRPT_PRNG_CTL_SEEDRLD_Msk; +} + + +/** + * @brief Open AES encrypt/decrypt function. + * @param[in] crpt Reference to Crypto module. + * @param[in] u32Channel AES channel. Must be 0. + * @param[in] u32EncDec 1: AES encode; 0: AES decode + * @param[in] u32OpMode AES operation mode, including: + * - \ref AES_MODE_ECB + * - \ref AES_MODE_CBC + * - \ref AES_MODE_CFB + * - \ref AES_MODE_OFB + * - \ref AES_MODE_CTR + * - \ref AES_MODE_CBC_CS1 + * - \ref AES_MODE_CBC_CS2 + * - \ref AES_MODE_CBC_CS3 + * @param[in] u32KeySize is AES key size, including: + * - \ref AES_KEY_SIZE_128 + * - \ref AES_KEY_SIZE_192 + * - \ref AES_KEY_SIZE_256 + * @param[in] u32SwapType is AES input/output data swap control, including: + * - \ref AES_NO_SWAP + * - \ref AES_OUT_SWAP + * - \ref AES_IN_SWAP + * - \ref AES_IN_OUT_SWAP + * @return None + */ +void AES_Open(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32EncDec, + uint32_t u32OpMode, uint32_t u32KeySize, uint32_t u32SwapType) +{ + crpt->AES_CTL = (u32EncDec << CRPT_AES_CTL_ENCRYPTO_Pos) | + (u32OpMode << CRPT_AES_CTL_OPMODE_Pos) | + (u32KeySize << CRPT_AES_CTL_KEYSZ_Pos) | + (u32SwapType << CRPT_AES_CTL_OUTSWAP_Pos); + g_AES_au32CTL[u32Channel] = crpt->AES_CTL; +} + +/** + * @brief Start AES encrypt/decrypt + * @param[in] crpt Reference to Crypto module. + * @param[in] u32Channel AES channel. Must be 0. + * @param[in] u32DMAMode AES DMA control, including: + * - \ref CRYPTO_DMA_FIRST Do first encrypt/decrypt in DMA cascade. + * - \ref CRYPTO_DMA_ONE_SHOT Do one shot encrypt/decrypt with DMA. + * - \ref CRYPTO_DMA_CONTINUE Do continuous encrypt/decrypt in DMA cascade. + * - \ref CRYPTO_DMA_LAST Do last encrypt/decrypt in DMA cascade. + * @return None + */ +void AES_Start(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32DMAMode) +{ + crpt->AES_CTL = g_AES_au32CTL[u32Channel]; + crpt->AES_CTL |= CRPT_AES_CTL_START_Msk | (u32DMAMode << CRPT_AES_CTL_DMALAST_Pos); +} + +/** + * @brief Set AES keys + * @param[in] crpt Reference to Crypto module. + * @param[in] u32Channel AES channel. Must be 0. + * @param[in] au32Keys An word array contains AES keys. + * @param[in] u32KeySize is AES key size, including: + * - \ref AES_KEY_SIZE_128 + * - \ref AES_KEY_SIZE_192 + * - \ref AES_KEY_SIZE_256 + * @return None + */ +void AES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize) +{ + uint32_t u32Idx, u32Wcnt, u32KeyRegAddr; + + u32KeyRegAddr = (uint32_t)&crpt->AES_KEY[0] + (u32Channel * 0x3CUL); + u32Wcnt = 4UL + u32KeySize * 2UL; + + for (u32Idx = 0U; u32Idx < u32Wcnt; u32Idx++) + { + outpw(u32KeyRegAddr, au32Keys[u32Idx]); + u32KeyRegAddr += 4UL; + } +} + +/** + * @brief Set AES initial vectors + * @param[in] crpt Reference to Crypto module. + * @param[in] u32Channel AES channel. Must be 0. + * @param[in] au32IV A four entry word array contains AES initial vectors. + * @return None + */ +void AES_SetInitVect(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32IV[]) +{ + uint32_t u32Idx, u32KeyRegAddr; + + u32KeyRegAddr = (uint32_t)&crpt->AES_IV[0] + (u32Channel * 0x3CUL); + + for (u32Idx = 0U; u32Idx < 4U; u32Idx++) + { + outpw(u32KeyRegAddr, au32IV[u32Idx]); + u32KeyRegAddr += 4UL; + } +} + +/** + * @brief Set AES DMA transfer configuration. + * @param[in] crpt Reference to Crypto module. + * @param[in] u32Channel AES channel. Must be 0. + * @param[in] u32SrcAddr AES DMA source address + * @param[in] u32DstAddr AES DMA destination address + * @param[in] u32TransCnt AES DMA transfer byte count + * @return None + */ +void AES_SetDMATransfer(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32SrcAddr, + uint32_t u32DstAddr, uint32_t u32TransCnt) +{ + uint32_t u32RegAddr; + + u32RegAddr = (uint32_t)&crpt->AES_SADDR + (u32Channel * 0x3CUL); + outpw(u32RegAddr, u32SrcAddr); + + u32RegAddr = (uint32_t)&crpt->AES_DADDR + (u32Channel * 0x3CUL); + outpw(u32RegAddr, u32DstAddr); + + u32RegAddr = (uint32_t)&crpt->AES_CNT + (u32Channel * 0x3CUL); + outpw(u32RegAddr, u32TransCnt); +} + +/*@}*/ /* end of group CRYPTO_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CRYPTO_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ + diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_dac.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_dac.c new file mode 100644 index 00000000000..4c67b17a0b2 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_dac.c @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file dac.c + * @version V0.10 + * @brief M251 series DAC driver source file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup DAC_Driver DAC Driver + @{ +*/ + +/** @addtogroup DAC_EXPORTED_FUNCTIONS DAC Exported Functions + @{ +*/ + +/** + * @brief This function make DAC module be ready to convert. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used in M251 DAC. + * @param[in] u32TrgSrc Decides the trigger source. Valid values are: + * - \ref DAC_WRITE_DAT_TRIGGER :Write DAC_DAT trigger + * - \ref DAC_SOFTWARE_TRIGGER :Software trigger + * - \ref DAC_LOW_LEVEL_TRIGGER :STDAC pin low level trigger + * - \ref DAC_HIGH_LEVEL_TRIGGER :STDAC pin high level trigger + * - \ref DAC_FALLING_EDGE_TRIGGER :STDAC pin falling edge trigger + * - \ref DAC_RISING_EDGE_TRIGGER :STDAC pin rising edge trigger + * - \ref DAC_TIMER0_TRIGGER :Timer 0 trigger + * - \ref DAC_TIMER1_TRIGGER :Timer 1 trigger + * - \ref DAC_TIMER2_TRIGGER :Timer 2 trigger + * - \ref DAC_TIMER3_TRIGGER :Timer 3 trigger + * @return None + * @details The DAC conversion can be started by writing DAC_DAT, software trigger or hardware trigger. + * When TRGEN (DAC_CTL[4]) is 0, the data conversion is started by writing DAC_DAT register. + * When TRGEN (DAC_CTL[4]) is 1, the data conversion is started by SWTRG (DAC_SWTRG[0]) is set to 1, + * external STDAC pin, or timer event. + */ +void DAC_Open(DAC_T *dac, + uint32_t u32Ch, + uint32_t u32TrgSrc) +{ + dac->CTL &= ~(DAC_CTL_ETRGSEL_Msk | DAC_CTL_TRGSEL_Msk | DAC_CTL_TRGEN_Msk); + dac->CTL |= (u32TrgSrc | DAC_CTL_DACEN_Msk); +} + +/** + * @brief Disable DAC analog power. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used in M251 DAC. + * @return None + * @details Disable DAC analog power for saving power consumption. + */ +void DAC_Close(DAC_T *dac, uint32_t u32Ch) +{ + dac->CTL &= (~DAC_CTL_DACEN_Msk); +} + +/** + * @brief Set delay time for DAC to become stable. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Delay Decides the DAC conversion settling time, the range is from 0~(1023/PCLK1*1000000) micro seconds. + * @return Real DAC conversion settling time (micro second). + * @details For example, DAC controller clock speed is 50MHz and DAC conversion setting time is 1 us, SETTLET (DAC_TCTL[9:0]) value must be greater than 0x32. + * @note User needs to write appropriate value to meet DAC conversion settling time base on PCLK (APB clock) speed. + */ +uint32_t DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay) +{ + + dac->TCTL = ((CLK_GetPCLK1Freq() * u32Delay / 1000000UL) & 0x3FFUL); + + return ((dac->TCTL) * 1000000UL / CLK_GetPCLK1Freq()); +} + + + +/*@}*/ /* end of group DAC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group DAC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_eadc.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_eadc.c new file mode 100644 index 00000000000..04ac082c3b1 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_eadc.c @@ -0,0 +1,152 @@ +/**************************************************************************//** + * @file eadc.c + * @version V0.10 + * @brief M251 series EADC driver source file + * + * @note + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EADC_Driver EADC Driver + @{ +*/ + +/** @addtogroup EADC_EXPORTED_FUNCTIONS EADC Exported Functions + @{ +*/ + +/** + * @brief This function make EADC_module be ready to convert. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32InputMode Decides the input mode. M251 don't support this feature. + * - \ref NULL :Always NULL. + * @return None + * @details This function is used to set analog input mode and enable A/D Converter. + * Before starting A/D conversion function, ADCEN bit (EADC_CTL[0]) should be set to 1. + * @note + */ +void EADC_Open(EADC_T *eadc, uint32_t u32InputMode) +{ + eadc->CTL |= EADC_CTL_ADCEN_Msk; + + /* Wait for EADC start up completely and ready for conversion */ + while ((eadc->PWRCTL & EADC_PWRCTL_READY_Msk) == 0); + +} + + +/** + * @brief Disable EADC_module. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details Clear ADCEN bit (EADC_CTL[0]) to disable A/D converter analog circuit power consumption. + */ +void EADC_Close(EADC_T *eadc) +{ + eadc->CTL &= (~EADC_CTL_ADCEN_Msk); +} + + +/** + * @brief Configure the sample control logic module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. + * @param[in] u32TriggerSrc Decides the trigger source. Valid values are: + * - \ref EADC_SOFTWARE_TRIGGER : Disable trigger + * - \ref EADC_FALLING_EDGE_TRIGGER : STADC pin falling edge trigger + * - \ref EADC_RISING_EDGE_TRIGGER : STADC pin rising edge trigger + * - \ref EADC_FALLING_RISING_EDGE_TRIGGER : STADC pin both falling and rising edge trigger + * - \ref EADC_ADINT0_TRIGGER : EADC ADINT0 interrupt EOC pulse trigger + * - \ref EADC_ADINT1_TRIGGER : EADC ADINT1 interrupt EOC pulse trigger + * - \ref EADC_TIMER0_TRIGGER : Timer0 overflow pulse trigger + * - \ref EADC_TIMER1_TRIGGER : Timer1 overflow pulse trigger + * - \ref EADC_TIMER2_TRIGGER : Timer2 overflow pulse trigger + * - \ref EADC_TIMER3_TRIGGER : Timer3 overflow pulse trigger + * - \ref EADC_PWM0TG0_TRIGGER : PWM0TG0 trigger + * - \ref EADC_PWM0TG1_TRIGGER : PWM0TG1 trigger + * - \ref EADC_PWM0TG2_TRIGGER : PWM0TG2 trigger + * - \ref EADC_PWM0TG3_TRIGGER : PWM0TG3 trigger + * - \ref EADC_PWM0TG4_TRIGGER : PWM0TG4 trigger + * - \ref EADC_PWM0TG5_TRIGGER : PWM0TG5 trigger + * - \ref EADC_PWM1TG0_TRIGGER : PWM1TG0 trigger + * - \ref EADC_PWM1TG1_TRIGGER : PWM1TG1 trigger + * - \ref EADC_PWM1TG2_TRIGGER : PWM1TG2 trigger + * - \ref EADC_PWM1TG3_TRIGGER : PWM1TG3 trigger + * - \ref EADC_PWM1TG4_TRIGGER : PWM1TG4 trigger + * - \ref EADC_PWM1TG5_TRIGGER : PWM1TG5 trigger + * - \ref EADC_BPWM0TG_TRIGGER : BPWM0TG trigger + * @param[in] u32Channel Specifies the sample module channel, valid value are from 0 to 15. + * @return None + * @details Each of EADC control logic modules 0~15 which is configurable for EADC converter channel EADC_CH0~15 and trigger source. + * Sample module 16~18 is fixed for EADC channel 16, 17, 18 input sources as band-gap voltage, temperature sensor, and battery power (VBAT). + */ +void EADC_ConfigSampleModule(EADC_T *eadc, \ + uint32_t u32ModuleNum, \ + uint32_t u32TriggerSrc, \ + uint32_t u32Channel) +{ + ((eadc->SCTL[u32ModuleNum])) &= (~(EADC_SCTL_EXTFEN_Msk | EADC_SCTL_EXTREN_Msk | EADC_SCTL_TRGSEL_Msk | EADC_SCTL_CHSEL_Msk)); + ((eadc->SCTL[u32ModuleNum])) |= (u32TriggerSrc | u32Channel); +} + + +/** + * @brief Set trigger delay time. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid values are from 0 to 15. + * @param[in] u32TriggerDelayTime Decides the trigger delay time, valid range are between 0~255. + * @param[in] u32DelayClockDivider Decides the trigger delay clock divider. Valid values are: + * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_1 : Trigger delay clock frequency is EADC_CLK/1 + * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_2 : Trigger delay clock frequency is EADC_CLK/2 + * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_4 : Trigger delay clock frequency is EADC_CLK/4 + * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_16 : Trigger delay clock frequency is EADC_CLK/16 + * @return None + * @details User can configure the trigger delay time by setting TRGDLYCNT (EADC_SCTLn[15:8], n=0~15) and TRGDLYDIV (EADC_SCTLn[7:6], n=0~15). + * Trigger delay time = (u32TriggerDelayTime) x Trigger delay clock period. + */ +void EADC_SetTriggerDelayTime(EADC_T *eadc, \ + uint32_t u32ModuleNum, \ + uint32_t u32TriggerDelayTime, \ + uint32_t u32DelayClockDivider) +{ + ((eadc->SCTL[u32ModuleNum])) &= (~(EADC_SCTL_TRGDLYDIV_Msk | EADC_SCTL_TRGDLYCNT_Msk)); + ((eadc->SCTL[u32ModuleNum])) |= ((u32TriggerDelayTime << EADC_SCTL_TRGDLYCNT_Pos) | u32DelayClockDivider); +} + + +/** + * @brief Set EADC extend sample time. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid values are from 0 to 18. + * @param[in] u32ExtendSampleTime Decides the extend sampling time, the range is from 0~255 EADC clock. Valid value are from 0 to 255. + * @return None + * @details When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough + * if the analog channel has heavy loading to cause fully charge time is longer. + * User can extend A/D sampling time after trigger source is coming to get enough sampling time. + */ +void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime) +{ + if (u32ModuleNum < 16) + { + ((eadc->SCTL[u32ModuleNum])) &= (~EADC_SCTL_EXTSMPT_Msk); + ((eadc->SCTL[u32ModuleNum])) |= (u32ExtendSampleTime << EADC_SCTL_EXTSMPT_Pos); + } + else + { + ((eadc->SCTL0[u32ModuleNum - 16])) &= (~EADC_SCTL0_EXTSMPT_Msk); + ((eadc->SCTL0[u32ModuleNum - 16])) |= (u32ExtendSampleTime << EADC_SCTL0_EXTSMPT_Pos); + } +} + +/*@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EADC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_ebi.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_ebi.c new file mode 100644 index 00000000000..a6ec9bf5b27 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_ebi.c @@ -0,0 +1,194 @@ +/**************************************************************************//** +* @file ebi.c +* @version V0.10 +* @brief M251 series EBI driver source file +* +* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. +****************************************************************************/ + +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EBI_Driver EBI Driver + @{ +*/ + +/** @addtogroup EBI_EXPORTED_FUNCTIONS EBI Exported Functions + @{ +*/ + + +/** + * @brief Initialize EBI for specify Bank + * + * @param[in] u32Bank Bank number for EBI. Valid values are: + * - \ref EBI_BANK0 + * - \ref EBI_BANK1 + * - \ref EBI_BANK2 + * @param[in] u32DataWidth Data bus width. Valid values are: + * - \ref EBI_BUSWIDTH_8BIT + * - \ref EBI_BUSWIDTH_16BIT + * @param[in] u32TimingClass Default timing configuration. Valid values are: + * - \ref EBI_TIMING_FASTEST + * - \ref EBI_TIMING_VERYFAST + * - \ref EBI_TIMING_FAST + * - \ref EBI_TIMING_NORMAL + * - \ref EBI_TIMING_SLOW + * - \ref EBI_TIMING_VERYSLOW + * - \ref EBI_TIMING_SLOWEST + * @param[in] u32BusMode Set EBI bus operate mode. Valid values are: + * - \ref EBI_OPMODE_NORMAL + * - \ref EBI_OPMODE_CACCESS + * @param[in] u32CSActiveLevel CS is active High/Low. Valid values are: + * - \ref EBI_CS_ACTIVE_HIGH + * - \ref EBI_CS_ACTIVE_LOW + * + * @return None + * + * @details This function is used to open specify EBI bank with different bus width, timing setting and \n + * active level of CS pin to access EBI device. + * @note Write Buffer Enable(WBUFEN) and Extend Time Of ALE(TALE) are only available in EBI bank0 control register. + */ +void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel) +{ + uint32_t u32Index0 = (uint32_t)&EBI->CTL0 + (uint32_t)u32Bank * 0x10U; + uint32_t u32Index1 = (uint32_t)&EBI->TCTL0 + (uint32_t)u32Bank * 0x10U; + volatile uint32_t *pu32EBICTL = (uint32_t *)(u32Index0); + volatile uint32_t *pu32EBITCTL = (uint32_t *)(u32Index1); + + if (u32DataWidth == EBI_BUSWIDTH_8BIT) + { + *pu32EBICTL &= ~EBI_CTL_DW16_Msk; + } + else + { + *pu32EBICTL |= EBI_CTL_DW16_Msk; + } + + *pu32EBICTL |= u32BusMode; + + switch (u32TimingClass) + { + case EBI_TIMING_FASTEST: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_1 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk; + *pu32EBITCTL = 0x0U; + break; + + case EBI_TIMING_VERYFAST: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_1 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk | + (0x3U << EBI_CTL_TALE_Pos) ; + *pu32EBITCTL = 0x03003318U; + break; + + case EBI_TIMING_FAST: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk; + *pu32EBITCTL = 0x0U; + break; + + case EBI_TIMING_NORMAL: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk | + (0x3U << EBI_CTL_TALE_Pos) ; + *pu32EBITCTL = 0x03003318U; + break; + + case EBI_TIMING_SLOW: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk | + (0x7U << EBI_CTL_TALE_Pos) ; + *pu32EBITCTL = 0x07007738U; + break; + + case EBI_TIMING_VERYSLOW: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_4 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk | + (0x7U << EBI_CTL_TALE_Pos) ; + *pu32EBITCTL = 0x07007738U; + break; + + case EBI_TIMING_SLOWEST: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_8 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk | + (0x7U << EBI_CTL_TALE_Pos) ; + *pu32EBITCTL = 0x07007738U; + break; + + default: + *pu32EBICTL &= ~EBI_CTL_EN_Msk; + break; + } +} + +/** + * @brief Disable EBI on specify Bank + * + * @param[in] u32Bank Bank number for EBI. Valid values are: + * - \ref EBI_BANK0 + * - \ref EBI_BANK1 + * - \ref EBI_BANK2 + * + * @return None + * + * @details This function is used to close specify EBI function. + */ +void EBI_Close(uint32_t u32Bank) +{ + uint32_t u32Index = (uint32_t)&EBI->CTL0 + u32Bank * 0x10U; + volatile uint32_t *pu32EBICTL = (uint32_t *)(u32Index); + + *pu32EBICTL &= ~EBI_CTL_EN_Msk; +} + +/** + * @brief Set EBI Bus Timing for specify Bank + * + * @param[in] u32Bank Bank number for EBI. Valid values are: + * - \ref EBI_BANK0 + * - \ref EBI_BANK1 + * - \ref EBI_BANK2 + * @param[in] u32TimingConfig Configure EBI timing settings, includes TACC, TAHD, W2X and R2R setting. + * @param[in] u32MclkDiv Divider for MCLK. Valid values are: + * - \ref EBI_MCLKDIV_1 + * - \ref EBI_MCLKDIV_2 + * - \ref EBI_MCLKDIV_4 + * - \ref EBI_MCLKDIV_8 + * - \ref EBI_MCLKDIV_16 + * - \ref EBI_MCLKDIV_32 + * - \ref EBI_MCLKDIV_64 + * - \ref EBI_MCLKDIV_128 + * + * @return None + * + * @details This function is used to configure specify EBI bus timing for access EBI device. + */ +void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv) +{ + uint32_t u32Index0 = (uint32_t)&EBI->CTL0 + (uint32_t)u32Bank * 0x10U; + uint32_t u32Index1 = (uint32_t)&EBI->TCTL0 + (uint32_t)u32Bank * 0x10U; + volatile uint32_t *pu32EBICTL = (uint32_t *)(u32Index0); + volatile uint32_t *pu32EBITCTL = (uint32_t *)(u32Index1); + + *pu32EBICTL = (*pu32EBICTL & ~EBI_CTL_MCLKDIV_Msk) | (u32MclkDiv << EBI_CTL_MCLKDIV_Pos); + *pu32EBITCTL = u32TimingConfig; +} + +/*@}*/ /* end of group EBI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EBI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_fmc.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_fmc.c new file mode 100644 index 00000000000..9b35f46ef48 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_fmc.c @@ -0,0 +1,520 @@ +/**************************************************************************//** + * @file fmc.c + * @version V3.00 + * @brief M251 Series Flash Memory Controller(FMC) driver source file + * + * @note + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup FMC_Driver FMC Driver + @{ +*/ + +/** @addtogroup FMC_EXPORTED_FUNCTIONS FMC Exported Functions + @{ +*/ + +/** + * @brief Set boot source from LDROM or APROM after next software reset + * + * @param[in] i32BootSrc + * 1: Boot from LDROM + * 0: Boot from APROM + * + * @return None + * + * @details This function is used to switch APROM boot or LDROM boot. User need to call + * FMC_SetBootSource to select boot source first, then use CPU reset or + * System Reset Request to reset system. + * + */ +void FMC_SetBootSource(int32_t i32BootSrc) +{ + if (i32BootSrc) + { + FMC->ISPCTL |= FMC_ISPCTL_BS_Msk; /* Boot from LDROM */ + } + else + { + FMC->ISPCTL &= ~FMC_ISPCTL_BS_Msk;/* Boot from APROM */ + } +} + + +/** + * @brief Disable ISP Functions + * + * @param None + * + * @return None + * + * @details This function will clear ISPEN bit of ISPCON to disable ISP function + * + */ +void FMC_Close(void) +{ + FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk; +} + + +/** + * @brief Get the current boot source + * + * @param None + * + * @retval 0 This chip is currently booting from APROM + * @retval 1 This chip is currently booting from LDROM + * + * @note This function only show the boot source. + * User need to read ISPSTA register to know if IAP mode supported or not in relative boot. + */ +int32_t FMC_GetBootSource(void) +{ + int32_t ret = 0; + + if (FMC->ISPCTL & FMC_ISPCTL_BS_Msk) + { + ret = 1; + } + + return ret; +} + + +/** + * @brief Enable FMC ISP function + * + * @param None + * + * @return None + * + * @details ISPEN bit of ISPCON must be set before we can use ISP commands. + * Therefore, To use all FMC function APIs, user needs to call FMC_Open() first to enable ISP functions. + * + * @note ISP functions are write-protected. user also needs to unlock it by calling SYS_UnlockReg() before using all ISP functions. + * + */ +void FMC_Open(void) +{ + FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk; +} + + +/** + * @brief Read the User Configuration words. + * + * @param[out] u32Config The word buffer to store the User Configuration data. + * @param[in] u32Count The word count to be read. + * + * @retval 0 Success + * @retval -1 Failed + * + * @details This function is used to read the settings of user configuration. + * if u32Count = 1, Only CONFIG0 will be returned to the buffer specified by u32Config. + * if u32Count = 2, Both CONFIG0 and CONFIG1 will be returned. + */ +int32_t FMC_ReadConfig(uint32_t u32Config[], uint32_t u32Count) +{ + uint32_t i; + + for (i = 0u; i < u32Count; i++) + { + u32Config[i] = FMC_Read(FMC_CONFIG_BASE + i * 4u); + } + + return 0; +} + + +/** + * @brief Write User Configuration + * + * @param[in] u32Config The word buffer to store the User Configuration data. + * @param[in] u32Count The word count to program to User Configuration. + * + * @retval 0 Success + * @retval -1 Failed + * + * @details User must enable User Configuration update before writing it. + * User must erase User Configuration before writing it. + * User Configuration is also be page erase. User needs to backup necessary data + * before erase User Configuration. + */ +int32_t FMC_WriteConfig(uint32_t u32Config[], uint32_t u32Count) +{ + int32_t ret = 0; + uint32_t i; + + for (i = 0u; i < u32Count; i++) + { + FMC_Write(FMC_CONFIG_BASE + i * 4u, u32Config[i]); + + if (FMC_Read(FMC_CONFIG_BASE + i * 4u) != u32Config[i]) + { + ret = 1; + } + } + + return ret; +} + + +/** + * @brief Run CRC32 checksum calculation and get result. + * + * @param[in] u32addr Starting flash address. It must be a page aligned address. + * @param[in] u32count Byte count of flash to be calculated. It must be multiple of 512 bytes. + * + * @return Success or not. + * @retval 0 Success. + * @retval 0xFFFFFFFF Invalid parameter. + * + * details Run ISP checksum command to calculate specify area + */ +uint32_t FMC_GetChkSum(uint32_t u32addr, uint32_t u32count) +{ + uint32_t ret; + + if ((u32addr % 512UL) || (u32count % 512UL)) + { + ret = 0xFFFFFFFF; + } + else + { + FMC->ISPCMD = FMC_ISPCMD_CAL_CHECKSUM; + FMC->ISPADDR = u32addr; + FMC->ISPDAT = u32count; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { } + + FMC->ISPCMD = FMC_ISPCMD_CHECKSUM; + FMC->ISPADDR = u32addr; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { } + + ret = FMC->ISPDAT; + } + + return ret; +} + + +/** + * @brief Run flash all one verification and get result. + * + * @param[in] u32addr Starting flash address. It must be a page aligned address. + * @param[in] u32count Byte count of flash to be calculated. It must be multiple of 512 bytes. + * + * @retval READ_ALLONE_YES The contents of verified flash area are 0xFFFFFFFF. + * @retval READ_ALLONE_NOT Some contents of verified flash area are not 0xFFFFFFFF. + * @retval READ_ALLONE_CMD_FAIL Unexpected error occurred. + * + * @details Run ISP check all one command to check specify area is all one or not. + */ +uint32_t FMC_CheckAllOne(uint32_t u32addr, uint32_t u32count) +{ + uint32_t ret = READ_ALLONE_CMD_FAIL; + + FMC->ISPSTS = 0x80UL; /* clear check all one bit */ + + FMC->ISPCMD = FMC_ISPCMD_RUN_ALL1; + FMC->ISPADDR = u32addr; + FMC->ISPDAT = u32count; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { } + + do + { + FMC->ISPCMD = FMC_ISPCMD_READ_ALL1; + FMC->ISPADDR = u32addr; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { } + } + while (FMC->ISPDAT == 0UL); + + if (FMC->ISPDAT == READ_ALLONE_YES) + { + ret = FMC->ISPDAT; + } + + if (FMC->ISPDAT == READ_ALLONE_NOT) + { + ret = FMC->ISPDAT; + } + + return ret; +} + + +/** + * @brief Check the XOM is actived or not. + * + * @param[in] xom_num The XOM number. The value will always be 0 in M251 series. + * + * @retval 1 XOM is actived. + * @retval 0 XOM is not actived. + * @retval -2 Invalid XOM number. + * + * @details To get specify XOM active status + */ +int32_t FMC_Is_XOM_Actived(uint32_t xom_num) +{ + uint32_t u32act; + int32_t ret = 0; + + if (xom_num >= 1UL) + { + ret = -2; + } + + if (ret >= 0) + { + u32act = (((FMC->XOMSTS) & 0xful) & (1ul << xom_num)) >> xom_num; + ret = (int32_t)u32act; + } + + return ret; +} + + +/** + * @brief Config XOM Region + * @param[in] xom_num The XOM number. The value will always be 0 in M251 series. + * @param[in] xom_base The XOM region base address. + * @param[in] xom_page The XOM page number of region size. + * + * @retval 0 Success + * @retval 1 XOM is has already actived. + * @retval -1 Program failed. + * @retval -2 Invalid XOM number. + * + * @details Program XOM base address and XOM size(page) + */ +int32_t FMC_Config_XOM(uint32_t xom_num, uint32_t xom_base, uint8_t xom_page) +{ + int32_t ret = 0; + + if (xom_num >= 1UL) + { + ret = -2; + } + + if (ret == 0) + { + ret = FMC_Is_XOM_Actived(xom_num); + } + + if (ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC->ISPADDR = FMC_XOM_BASE + (xom_num * 0x10u); + FMC->ISPDAT = xom_base; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} + + if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + } + + if (ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC->ISPADDR = FMC_XOM_BASE + (xom_num * 0x10u + 0x04u); + FMC->ISPDAT = xom_page; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} + + if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + } + + if (ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC->ISPADDR = FMC_XOM_BASE + (xom_num * 0x10u + 0x08u); + FMC->ISPDAT = 0u; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} + + if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + } + + return ret; +} + + +/** + * @brief Execute Erase XOM Region + * + * @param[in] xom_num The XOM number. The value will always be 0 in M251 series. + * + * @return XOM erase success or not. + * @retval 0 Success + * @retval -1 Erase failed + * @retval -2 Invalid XOM number. + * + * @details Execute FMC_ISPCMD_PAGE_ERASE command to erase XOM. + */ +int32_t FMC_Erase_XOM(uint32_t xom_num) +{ + uint32_t u32Addr; + int32_t i32Active, err = 0; + + if (xom_num >= 1UL) + { + err = -2; + } + + i32Active = FMC_Is_XOM_Actived(xom_num); + + + if (i32Active) + { + u32Addr = FMC->XOMR0STS0; + FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE; + FMC->ISPADDR = u32Addr; + FMC->ISPDAT = 0x55aa03u; + FMC->ISPTRG = 0x1u; +#if ISBEN + __ISB(); +#endif + + while (FMC->ISPTRG) {} + + /* Check ISPFF flag to know whether erase OK or fail. */ + if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) + { + FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk; + err = -1; + } + } + else + { + err = -1; + } + + return err; +} + + +/** + * @brief Flash page erase + * + * @param[in] u32Addr Flash address including APROM, LDROM, Data Flash, and CONFIG + * + * @details To do flash page erase. The target address could be APROM, LDROM, Data Flash, or CONFIG. + * The page size is 512 bytes. + * + * @retval 0 Success + * @retval -1 Erase failed + * + */ +int32_t FMC_Erase(uint32_t u32Addr) +{ + int32_t ret = 0; + + FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE; + FMC->ISPADDR = u32Addr; + FMC->ISPTRG = 0x1u; +#if ISBEN + __ISB(); +#endif + + while (FMC->ISPTRG) {} + + /* Check ISPFF flag to know whether erase OK or fail. */ + if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) + { + FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk; + ret = -1; + } + + return ret; +} + + +/** + * @brief Read 32-bit Data from specified address of flash + * + * @param[in] u32Addr Flash address include APROM, LDROM, Data Flash, and CONFIG + * + * @return The data of specified address + * + * @details To read word data from Flash include APROM, LDROM, Data Flash, and CONFIG. + * + */ +uint32_t FMC_Read(uint32_t u32Addr) +{ + FMC->ISPCMD = FMC_ISPCMD_READ; + FMC->ISPADDR = u32Addr; + FMC->ISPDAT = 0u; + FMC->ISPTRG = 0x1u; +#if ISBEN + __ISB(); +#endif + + while (FMC->ISPTRG) {} + + return FMC->ISPDAT; +} + + + +/** + * @brief Program 32-bit data into specified address of flash + * + * @param[in] u32Addr Flash address include APROM, LDROM, Data Flash, and CONFIG + * @param[in] u32Data 32-bit Data to program + * + * @return None + * + * @details To program word data into Flash include APROM, LDROM, Data Flash, and CONFIG. + * The corresponding functions in CONFIG are listed in FMC section of Technical Reference Manual. + * + */ +void FMC_Write(uint32_t u32Addr, uint32_t u32Data) +{ + FMC->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC->ISPADDR = u32Addr; + FMC->ISPDAT = u32Data; + FMC->ISPTRG = 0x1u; +#if ISBEN + __ISB(); +#endif + + while (FMC->ISPTRG) {} +} + +/*@}*/ /* end of group FMC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group FMC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ + + diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_gpio.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_gpio.c new file mode 100644 index 00000000000..9f76941b387 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_gpio.c @@ -0,0 +1,163 @@ +/**************************************************************************//** + * @file gpio.c + * @version V0.10 + * @brief M251 GPIO driver source file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup GPIO_Driver GPIO Driver + @{ +*/ + +/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions + @{ +*/ + +/** + * @brief Set GPIO operation mode + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, and PE. + * It could be BIT0 ~ BIT12, and BIT14 ~ BIT15 for PC. + * It could be BIT0 ~ BIT13, and BIT15 for PD. + * It could be BIT0 ~ BIT7 for PF. + * @param[in] u32Mode Operation mode. It could be \n + * GPIO_MODE_INPUT, GPIO_MODE_OUTPUT, GPIO_MODE_OPEN_DRAIN, GPIO_MODE_QUASI. + * + * @return None + * + * @details This function is used to set specified GPIO operation mode. + */ +void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode) +{ + uint32_t i; + + for (i = 0ul; i < GPIO_PIN_MAX; i++) + { + if (u32PinMask & (1ul << i)) + { + port->MODE = (port->MODE & ~(0x3ul << (i << 1ul))) | (u32Mode << (i << 1ul)); + } + } +} + +/** + * @brief Enable GPIO interrupt + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. + * @param[in] u32Pin The pin of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, and PE. + * It could be BIT0 ~ BIT12, and BIT14 ~ BIT15 for PC. + * It could be BIT0 ~ BIT13, and BIT15 for PD. + * It could be BIT0 ~ BIT7 for PF. + * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n + * GPIO_INT_RISING, GPIO_INT_FALLING, GPIO_INT_BOTH_EDGE, GPIO_INT_HIGH, GPIO_INT_LOW. + * + * @return None + * + * @details This function is used to enable specified GPIO pin interrupt. + */ +void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs) +{ + port->INTTYPE |= (((u32IntAttribs >> 24UL) & 0xFFUL) << u32Pin); + port->INTEN |= ((u32IntAttribs & 0xFFFFFFUL) << u32Pin); +} + + +/** + * @brief Disable GPIO interrupt + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. + * @param[in] u32Pin The pin of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, and PE. + * It could be BIT0 ~ BIT12, and BIT14 ~ BIT15 for PC. + * It could be BIT0 ~ BIT13, and BIT15 for PD. + * It could be BIT0 ~ BIT7 for PF. + * @return None + * + * @details This function is used to enable specified GPIO pin interrupt. + */ +void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin) +{ + /* Configure interrupt mode of specified pin */ + port->INTTYPE &= ~(1UL << u32Pin); + /* Disable interrupt function of specified pin */ + port->INTEN &= ~((0x00010001UL) << u32Pin); +} + +/** + * @brief Set GPIO slew rate control + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE or PF. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, and PE. + * It could be BIT0 ~ BIT12, and BIT14 ~ BIT15 for PC. + * It could be BIT0 ~ BIT13, and BIT15 for PD. + * It could be BIT0 ~ BIT7 for PF. + * @param[in] u32Mode Slew rate mode. It could be + * - \ref GPIO_SLEWCTL_NORMAL (minimum 16 MHz at 2.7V) + * - \ref GPIO_SLEWCTL_HIGH (minimum 25 MHz at 2.7V) + * + * @return None + * + * @details This function is used to set specified GPIO operation mode. + */ +void GPIO_SetSlewCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode) +{ + uint32_t i; + + for (i = 0ul; i < GPIO_PIN_MAX; i++) + { + if (u32PinMask & (1ul << i)) + { + port->SLEWCTL = (port->SLEWCTL & ~(0x3ul << (i << 1ul))) | (u32Mode << (i << 1ul)); + } + } +} + + +/** + * @brief Set GPIO Pull-up and Pull-down control + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, or PF. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. + * It could be BIT0 ~ BIT15 for PA, PB, and PE. + * It could be BIT0 ~ BIT12, and BIT14 ~ BIT15 for PC. + * It could be BIT0 ~ BIT13, and BIT15 for PD. + * It could be BIT0 ~ BIT7 for PF. + * @param[in] u32Mode The pin mode of specified GPIO pin. It could be + * - \ref GPIO_PUSEL_DISABLE + * - \ref GPIO_PUSEL_PULL_UP + * - \ref GPIO_PUSEL_PULL_DOWN + * + * @return None + * + * @details Set the pin mode of specified GPIO pin. + */ +void GPIO_SetPullCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode) +{ + uint32_t i; + + for (i = 0ul; i < GPIO_PIN_MAX; i++) + { + if (u32PinMask & (1ul << i)) + { + port->PUSEL = (port->PUSEL & ~(0x3ul << (i << 1ul))) | (u32Mode << (i << 1ul)); + } + } +} +/*@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group GPIO_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_i2c.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_i2c.c new file mode 100644 index 00000000000..32f4b3381fb --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_i2c.c @@ -0,0 +1,1594 @@ +/**************************************************************************//** + * @file i2c.c + * @version V0.10 + * @brief M251 series I2C driver source file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup I2C_Driver I2C Driver + @{ +*/ + + +/** @addtogroup I2C_EXPORTED_FUNCTIONS I2C Exported Functions + @{ +*/ + +/** + * @brief Enable specify I2C Controller and set Clock Divider + * + * @param[in] i2c Specify I2C port + * @param[in] u32BusClock The target I2C bus clock in Hz + * + * @return Actual I2C bus clock frequency + * + * @details The function enable the specify I2C Controller and set proper Clock Divider + * in I2C CLOCK DIVIDED REGISTER (I2CLK) according to the target I2C Bus clock. + * I2C Bus clock = PCLK / (4*(divider+1). + * + */ +uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock) +{ + uint32_t u32Div; + uint32_t u32Pclk; + + if (i2c == I2C1) + { + u32Pclk = CLK_GetPCLK1Freq(); + } + else + { + u32Pclk = CLK_GetPCLK0Freq(); + } + + u32Div = (uint32_t)(((u32Pclk * 10U) / (u32BusClock * 4U) + 5U) / 10U - 1U); /* Compute proper divider for I2C clock */ + i2c->CLKDIV = u32Div; + + /* Enable I2C */ + i2c->CTL0 |= I2C_CTL0_I2CEN_Msk; + + return (u32Pclk / ((u32Div + 1U) << 2U)); +} + +/** + * @brief Disable specify I2C Controller + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Reset I2C Controller and disable specify I2C port. + * + */ + +void I2C_Close(I2C_T *i2c) +{ + /* Reset I2C Controller */ + if ((uint32_t)i2c == I2C0_BASE) + { + SYS->IPRST1 |= SYS_IPRST1_I2C0RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_I2C0RST_Msk; + } + else if ((uint32_t)i2c == I2C1_BASE) + { + SYS->IPRST1 |= SYS_IPRST1_I2C1RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_I2C1RST_Msk; + } + + /* Disable I2C */ + i2c->CTL0 &= ~I2C_CTL0_I2CEN_Msk; +} + +/** + * @brief Clear Time-out Counter flag + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details When Time-out flag will be set, use this function to clear I2C Bus Time-out counter flag . + * + */ +void I2C_ClearTimeoutFlag(I2C_T *i2c) +{ + i2c->TOCTL |= I2C_TOCTL_TOIF_Msk; +} + +/** + * @brief Set Control bit of I2C Controller + * + * @param[in] i2c Specify I2C port + * @param[in] u8Start Set I2C START condition + * @param[in] u8Stop Set I2C STOP condition + * @param[in] u8Si Clear SI flag + * @param[in] u8Ack Set I2C ACK bit + * + * @return None + * + * @details The function set I2C Control bit of I2C Bus protocol. + * + */ +void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack) +{ + uint32_t u32Reg = 0U; + + if (u8Start) + { + u32Reg |= I2C_CTL_STA; + } + + if (u8Stop) + { + u32Reg |= I2C_CTL_STO; + } + + if (u8Si) + { + u32Reg |= I2C_CTL_SI; + } + + if (u8Ack) + { + u32Reg |= I2C_CTL_AA; + } + + i2c->CTL0 = (i2c->CTL0 & ~0x3CU) | u32Reg; +} + +/** + * @brief Disable Interrupt of I2C Controller + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details The function is used for disable I2C interrupt + * + */ +void I2C_DisableInt(I2C_T *i2c) +{ + i2c->CTL0 &= ~I2C_CTL0_INTEN_Msk; +} + +/** + * @brief Enable Interrupt of I2C Controller + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details The function is used for enable I2C interrupt + * + */ +void I2C_EnableInt(I2C_T *i2c) +{ + i2c->CTL0 |= I2C_CTL0_INTEN_Msk; +} + +/** + * @brief Get I2C Bus Clock + * + * @param[in] i2c Specify I2C port + * + * @return The actual I2C Bus clock in Hz + * + * @details To get the actual I2C Bus Clock frequency. + */ +uint32_t I2C_GetBusClockFreq(I2C_T *i2c) +{ + uint32_t u32Divider = i2c->CLKDIV; + uint32_t u32Pclk; + + if (i2c == I2C1) + { + u32Pclk = CLK_GetPCLK1Freq(); + } + else + { + u32Pclk = CLK_GetPCLK0Freq(); + } + + return (u32Pclk / ((u32Divider + 1U) << 2U)); +} + +/** + * @brief Set I2C Bus Clock + * + * @param[in] i2c Specify I2C port + * @param[in] u32BusClock The target I2C Bus Clock in Hz + * + * @return The actual I2C Bus Clock in Hz + * + * @details To set the actual I2C Bus Clock frequency. + */ +uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock) +{ + uint32_t u32Div; + uint32_t u32Pclk; + + if (i2c == I2C1) + { + u32Pclk = CLK_GetPCLK1Freq(); + } + else + { + u32Pclk = CLK_GetPCLK0Freq(); + } + + u32Div = (uint32_t)(((u32Pclk * 10U) / (u32BusClock * 4U) + 5U) / 10U - 1U); /* Compute proper divider for I2C clock */ + i2c->CLKDIV = u32Div; + + return (u32Pclk / ((u32Div + 1U) << 2U)); +} + +/** + * @brief Get Interrupt Flag + * + * @param[in] i2c Specify I2C port + * + * @return I2C interrupt flag status + * + * @details To get I2C Bus interrupt flag. + */ +uint32_t I2C_GetIntFlag(I2C_T *i2c) +{ + return ((i2c->CTL0 & I2C_CTL0_SI_Msk) == I2C_CTL0_SI_Msk ? 1U : 0U); +} + +/** + * @brief Get I2C Bus Status Code + * + * @param[in] i2c Specify I2C port + * + * @return I2C Status Code + * + * @details To get I2C Bus Status Code. + */ +uint32_t I2C_GetStatus(I2C_T *i2c) +{ + return (i2c->STATUS0); +} + +/** + * @brief Read a Byte from I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @return I2C Data + * + * @details To read a bytes data from specify I2C port. + */ +uint8_t I2C_GetData(I2C_T *i2c) +{ + return (uint8_t)(i2c->DAT); +} + +/** + * @brief Send a byte to I2C Bus + * + * @param[in] i2c Specify I2C port + * @param[in] u8Data The data to send to I2C bus + * + * @return None + * + * @details This function is used to write a byte to specified I2C port + */ +void I2C_SetData(I2C_T *i2c, uint8_t u8Data) +{ + i2c->DAT = u8Data; +} + +/** + * @brief Set Slave Address and GC Mode + * + * @param[in] i2c Specify I2C port + * @param[in] u8SlaveNo Set the number of I2C address register (0~3) + * @param[in] u16SlaveAddr 7-bit or 10-bit slave address + * @param[in] u8GCMode Enable/Disable GC mode (I2C_GCMODE_ENABLE / I2C_GCMODE_DISABLE) + * + * @return None + * + * @details This function is used to set 7-bit or 10-bit slave addresses in I2C SLAVE ADDRESS REGISTER (I2CADDR0~3) + * and enable GC Mode. + * + */ +void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddr, uint8_t u8GCMode) +{ + switch (u8SlaveNo) + { + case 1: + i2c->ADDR1 = ((uint32_t)u16SlaveAddr << 1U) | u8GCMode; + break; + + case 2: + i2c->ADDR2 = ((uint32_t)u16SlaveAddr << 1U) | u8GCMode; + break; + + case 3: + i2c->ADDR3 = ((uint32_t)u16SlaveAddr << 1U) | u8GCMode; + break; + + case 0: + default: + i2c->ADDR0 = ((uint32_t)u16SlaveAddr << 1U) | u8GCMode; + break; + } +} + +/** + * @brief Configure the mask bits of 7-bit Slave Address + * + * @param[in] i2c Specify I2C port + * @param[in] u8SlaveNo Set the number of I2C address mask register (0~3) + * @param[in] u8SlaveAddrMask A byte for slave address mask + * + * @return None + * + * @details This function is used to set 7-bit slave addresses. + * + */ +void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddrMask) +{ + switch (u8SlaveNo) + { + case 1: + i2c->ADDRMSK1 = (uint32_t)u16SlaveAddrMask << 1U; + break; + + case 2: + i2c->ADDRMSK2 = (uint32_t)u16SlaveAddrMask << 1U; + break; + + case 3: + i2c->ADDRMSK3 = (uint32_t)u16SlaveAddrMask << 1U; + break; + + case 0: + default: + i2c->ADDRMSK0 = (uint32_t)u16SlaveAddrMask << 1U; + break; + } +} + +/** + * @brief Enable Time-out Counter Function and support Long Time-out + * + * @param[in] i2c Specify I2C port + * @param[in] u8LongTimeout Configure DIV4 to enable Long Time-out (0/1) + * + * @return None + * + * @details This function enable Time-out Counter function and configure DIV4 to support Long + * Time-out. + * + */ +void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout) +{ + if (u8LongTimeout) + { + i2c->TOCTL |= I2C_TOCTL_TOCDIV4_Msk; + } + else + { + i2c->TOCTL &= ~I2C_TOCTL_TOCDIV4_Msk; + } + + i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk; +} + +/** + * @brief Disable Time-out Counter Function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details To disable Time-out Counter function in I2CTOC register. + * + */ +void I2C_DisableTimeout(I2C_T *i2c) +{ + i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk; +} + +/** + * @brief Enable I2C Wake-up Function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details To enable Wake-up function of I2C Wake-up control register. + * + */ +void I2C_EnableWakeup(I2C_T *i2c) +{ + i2c->WKCTL |= I2C_WKCTL_WKEN_Msk; +} + +/** + * @brief Disable I2C Wake-up Function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details To disable Wake-up function of I2C Wake-up control register. + * + */ +void I2C_DisableWakeup(I2C_T *i2c) +{ + i2c->WKCTL &= ~I2C_WKCTL_WKEN_Msk; +} + +/** + * @brief To get SMBus Status + * + * @param[in] i2c Specify I2C port + * + * @return SMBus status + * + * @details To get the Bus Management status of I2C_BUSSTS register + * + */ +uint32_t I2C_SMBusGetStatus(I2C_T *i2c) +{ + return (i2c->BUSSTS); +} + +/** + * @brief Clear SMBus Interrupt Flag + * + * @param[in] i2c Specify I2C port + * @param[in] u8SMBusIntFlag Specify SMBus interrupt flag + * + * @return None + * + * @details To clear flags of I2C_BUSSTS status register if interrupt set. + * + */ +void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8SMBusIntFlag) +{ + i2c->BUSSTS = u8SMBusIntFlag; +} + +/** + * @brief Set SMBus Bytes Counts of Transmission or Reception + * + * @param[in] i2c Specify I2C port + * @param[in] u32PktSize Transmit / Receive bytes + * + * @return None + * + * @details The transmission or receive byte number in one transaction when PECEN is set. The maximum is 255 bytes. + * + */ +void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize) +{ + i2c->PKTSIZE = u32PktSize; +} + +/** + * @brief Init SMBus Host/Device Mode + * + * @param[in] i2c Specify I2C port + * @param[in] u8HostDevice Init SMBus port mode(I2C_SMBH_ENABLE(1)/I2C_SMBD_ENABLE(0)) + * + * @return None + * + * @details Using SMBus communication must specify the port is a Host or a Device. + * + */ +void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice) +{ + /* Clear BMHEN, BMDEN of BUSCTL Register */ + i2c->BUSCTL &= ~(I2C_BUSCTL_BMHEN_Msk | I2C_BUSCTL_BMDEN_Msk); + + /* Set SMBus Host/Device Mode, and enable Bus Management*/ + if (u8HostDevice == (uint8_t)I2C_SMBH_ENABLE) + { + i2c->BUSCTL |= (I2C_BUSCTL_BMHEN_Msk | I2C_BUSCTL_BUSEN_Msk); + } + else + { + i2c->BUSCTL |= (I2C_BUSCTL_BMDEN_Msk | I2C_BUSCTL_BUSEN_Msk); + } +} + +/** + * @brief Disable SMBus function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Disable all SMBus function include Bus disable, CRC check, Acknowledge by manual, Host/Device Mode. + * + */ +void I2C_SMBusClose(I2C_T *i2c) +{ + + i2c->BUSCTL = 0x00U; +} + +/** + * @brief Enable SMBus PEC Transmit Function + * + * @param[in] i2c Specify I2C port + * @param[in] u8PECTxEn CRC transmit enable(PECTX_ENABLE) or disable(PECTX_DISABLE) + * + * @return None + * + * @details When enable CRC check function, the Host or Device needs to transmit CRC byte. + * + */ +void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn) +{ + i2c->BUSCTL &= ~I2C_BUSCTL_PECTXEN_Msk; + + if (u8PECTxEn) + { + i2c->BUSCTL |= (I2C_BUSCTL_PECEN_Msk | I2C_BUSCTL_PECTXEN_Msk); + } + else + { + i2c->BUSCTL |= I2C_BUSCTL_PECEN_Msk; + } +} + +/** + * @brief Get SMBus CRC value + * + * @param[in] i2c Specify I2C port + * + * @return A byte is packet error check value + * + * @details The CRC check value after a transmission or a reception by count by using CRC8 + * + */ +uint8_t I2C_SMBusGetPECValue(I2C_T *i2c) +{ + return (uint8_t)i2c->PKTCRC; +} + +/** + * @brief Calculate Time-out of SMBus idle period + * + * @param[in] i2c Specify I2C port + * @param[in] us Time-out length(us) + * @param[in] u32Hclk I2C peripheral clock frequency + * + * @return None + * + * @details This function is used to set SMBus Time-out length when bus is in Idle state. + * + */ + +void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t us, uint32_t u32Hclk) +{ + uint32_t u32Div, u32Hclk_kHz; + + i2c->BUSCTL |= I2C_BUSCTL_TIDLE_Msk; + u32Hclk_kHz = u32Hclk / 1000U; + u32Div = (((us * u32Hclk_kHz) / 1000U) >> 2U) - 1U; + + if (u32Div > 255U) + { + i2c->BUSTOUT = 0xFFU; + } + else + { + i2c->BUSTOUT = u32Div; + } + +} + +/** + * @brief Calculate Time-out of SMBus active period + * + * @param[in] i2c Specify I2C port + * @param[in] ms Time-out length(ms) + * @param[in] u32Pclk peripheral clock frequency + * + * @return None + * + * @details This function is used to set SMBus Time-out length when bus is in active state. + * Time-out length is calculate the SCL line "one clock" pull low timing. + * + */ + +void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk) +{ + uint32_t u32Div, u32Pclk_kHz; + + i2c->BUSCTL &= ~I2C_BUSCTL_TIDLE_Msk; + + /* DIV4 disabled */ + i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk; + u32Pclk_kHz = u32Pclk / 1000U; + u32Div = ((ms * u32Pclk_kHz) / (16U * 1024U)) - 1U; + + if (u32Div <= 0xFFU) + { + i2c->BUSTOUT = u32Div; + } + else + { + /* DIV4 enabled */ + i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk; + i2c->BUSTOUT = (((ms * u32Pclk_kHz) / (16U * 1024U * 4U)) - 1U) & 0xFFU; /* The max value is 255 */ + } + +} + +/** + * @brief Calculate Cumulative Clock low Time-out of SMBus active period + * + * @param[in] i2c Specify I2C port + * @param[in] ms Time-out length(ms) + * @param[in] u32Pclk peripheral clock frequency + * + * @return None + * + * @details This function is used to set SMBus Time-out length when bus is in Active state. + * Time-out length is calculate the SCL line "clocks" low cumulative timing. + * + */ + +void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk) +{ + uint32_t u32Div, u32Pclk_kHz; + + i2c->BUSCTL &= ~I2C_BUSCTL_TIDLE_Msk; + + /* DIV4 disabled */ + i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk; + u32Pclk_kHz = u32Pclk / 1000U; + u32Div = ((ms * u32Pclk_kHz) / (16U * 1024U)) - 1U; + + if (u32Div <= 0xFFU) + { + i2c->CLKTOUT = u32Div; + } + else + { + /* DIV4 enabled */ + i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk; + i2c->CLKTOUT = (((ms * u32Pclk_kHz) / (16U * 1024U * 4U)) - 1U) & 0xFFU; /* The max value is 255 */ + } +} +/** + * @brief Write a byte to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] data Write a byte data to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for I2C Master write a byte data to Slave. + * + */ + +uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, u8Ctrl = 0U; + + I2C_START(i2c); + + while (u8Xfering && (u8Err == 0U)) + { + I2C_WAIT_READY(i2c) {} + + switch (I2C_GET_STATUS(i2c)) + { + case 0x08: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1U | 0x00U)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + + case 0x18: /* Slave Address ACK */ + I2C_SET_DATA(i2c, data); /* Write data to I2CDAT */ + break; + + case 0x20: /* Slave Address NACK */ + case 0x30: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1U; + break; + + case 0x28: + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0U; + break; + + case 0x38: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1U; + break; + } + + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + + return (u8Err | u8Xfering); /* return (Success)/(Fail) status */ +} + +/** + * @brief Write multi bytes to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] *data Pointer to array to write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for I2C Master write multi bytes data to Slave. + * + */ + +uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data[], uint32_t u32wLen) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, u8Ctrl = 0U; + uint32_t u32txLen = 0U; + + I2C_START(i2c); /* Send START */ + + while (u8Xfering && (u8Err == 0U)) + { + I2C_WAIT_READY(i2c) {} + + switch (I2C_GET_STATUS(i2c)) + { + case 0x08: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1U | 0x00U)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + + case 0x18: /* Slave Address ACK */ + case 0x28: + if (u32txLen < u32wLen) + I2C_SET_DATA(i2c, data[u32txLen++]); /* Write Data to I2CDAT */ + else + { + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0U; + } + + break; + + case 0x20: /* Slave Address NACK */ + case 0x30: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1U; + break; + + case 0x38: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1U; + break; + } + + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Specify a byte register address and write a byte to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 byte) of data write to + * @param[in] data A byte data to write it to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for I2C Master specify a address that data write to in Slave. + * + */ + +uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, u8Ctrl = 0U; + uint32_t u32txLen = 0U; + + I2C_START(i2c); /* Send START */ + + while (u8Xfering && (u8Err == 0U)) + { + I2C_WAIT_READY(i2c) {} + + switch (I2C_GET_STATUS(i2c)) + { + case 0x08: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1U | 0x00U)); /* Send Slave address with write bit */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + + case 0x18: /* Slave Address ACK */ + I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */ + break; + + case 0x20: /* Slave Address NACK */ + case 0x30: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1U; + break; + + case 0x28: + if (u32txLen < 1U) + { + I2C_SET_DATA(i2c, data); + u32txLen++; + } + else + { + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0U; + } + + break; + + case 0x38: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1U; + break; + } + + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + + return (u8Err | u8Xfering); /* return (Success)/(Fail) status */ +} + + +/** + * @brief Specify a byte register address and write multi bytes to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 byte) of data write to + * @param[in] *data Pointer to array to write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for I2C Master specify a byte address that multi data bytes write to in Slave. + * + */ + +uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data[], uint32_t u32wLen) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, u8Ctrl = 0U; + uint32_t u32txLen = 0U; + + I2C_START(i2c); /* Send START */ + + while (u8Xfering && (u8Err == 0U)) + { + I2C_WAIT_READY(i2c) {} + + switch (I2C_GET_STATUS(i2c)) + { + case 0x08: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1U | 0x00U)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; + break; + + case 0x18: /* Slave Address ACK */ + I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */ + break; + + case 0x20: /* Slave Address NACK */ + case 0x30: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1U; + break; + + case 0x28: + if (u32txLen < u32wLen) + I2C_SET_DATA(i2c, data[u32txLen++]); + else + { + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0U; + } + + break; + + case 0x38: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1U; + break; + } + + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Specify two bytes register address and Write a byte to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 byte) of data write to + * @param[in] data Write a byte data to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for I2C Master specify two bytes address that data write to in Slave. + * + */ + +uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, u8Addr = 1U, u8Ctrl = 0U; + uint32_t u32txLen = 0U; + + I2C_START(i2c); /* Send START */ + + while (u8Xfering && (u8Err == 0U)) + { + I2C_WAIT_READY(i2c) {} + + switch (I2C_GET_STATUS(i2c)) + { + case 0x08: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1U | 0x00U)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + + case 0x18: /* Slave Address ACK */ + I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00U) >> 8U)); /* Write Hi byte address of register */ + break; + + case 0x20: /* Slave Address NACK */ + case 0x30: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1; + break; + + case 0x28: + if (u8Addr) + { + I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFU)); /* Write Lo byte address of register */ + u8Addr = 0U; + } + else if ((u32txLen < 1U) && (u8Addr == 0U)) + { + I2C_SET_DATA(i2c, data); + u32txLen++; + } + else + { + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0U; + } + + break; + + case 0x38: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1U; + break; + } + + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + + return (u8Err | u8Xfering); /* return (Success)/(Fail) status */ +} + + +/** + * @brief Specify two bytes register address and write multi bytes to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 bytes) of data write to + * @param[in] data[] A data array for write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for I2C Master specify a byte address that multi data write to in Slave. + * + */ + +uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data[], uint32_t u32wLen) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, u8Addr = 1U, u8Ctrl = 0U; + uint32_t u32txLen = 0U; + + I2C_START(i2c); /* Send START */ + + while (u8Xfering && (u8Err == 0U)) + { + I2C_WAIT_READY(i2c) {} + + switch (I2C_GET_STATUS(i2c)) + { + case 0x08: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1U | 0x00U)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + + case 0x18: /* Slave Address ACK */ + I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00U) >> 8U)); /* Write Hi byte address of register */ + break; + + case 0x20: /* Slave Address NACK */ + case 0x30: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1U; + break; + + case 0x28: + if (u8Addr) + { + I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFU)); /* Write Lo byte address of register */ + u8Addr = 0U; + } + else if ((u32txLen < u32wLen) && (u8Addr == 0U)) + { + I2C_SET_DATA(i2c, data[u32txLen++]); /* Write data to Register I2CDAT*/ + } + else + { + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0U; + } + + break; + + case 0x38: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1U; + break; + } + + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Read a byte from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * + * @return Read a byte data from Slave + * + * @details The function is used for I2C Master to read a byte data from Slave. + * + */ +uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, rdata = 0U, u8Ctrl = 0U; + + I2C_START(i2c); /* Send START */ + + while (u8Xfering && (u8Err == 0U)) + { + I2C_WAIT_READY(i2c) {} + + switch (I2C_GET_STATUS(i2c)) + { + case 0x08: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1U) | 0x01U)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + + case 0x40: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + + case 0x48: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1U; + break; + + case 0x58: + rdata = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0U; + break; + + case 0x38: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1U; + break; + } + + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + + if (u8Err) + { + rdata = 0U; /* If occurs error, return 0 */ + } + return rdata; /* Return read data */ +} +/** + * @brief Read multi bytes from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[out] rdata[] A data array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for I2C Master to read multi data bytes from Slave. + * + * + */ +uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t rdata[], uint32_t u32rLen) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, u8Ctrl = 0U; + uint32_t u32rxLen = 0U; + + I2C_START(i2c); /* Send START */ + + while (u8Xfering && (u8Err == 0U)) + { + I2C_WAIT_READY(i2c) {} + + switch (I2C_GET_STATUS(i2c)) + { + case 0x08: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1U) | 0x01U)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + + case 0x40: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + break; + + case 0x48: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1; + break; + + case 0x50: + rdata[u32rxLen++] = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */ + + if (u32rxLen < (u32rLen - 1)) + { + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + } + else + { + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + } + + break; + + case 0x58: + rdata[u32rxLen++] = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0U; + break; + + case 0x38: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1U; + break; + } + + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + + return u32rxLen; /* Return bytes length that have been received */ +} + + +/** + * @brief Specify a byte register address and read a byte from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address(1 byte) of data read from + * + * @return Read a byte data from Slave + * + * @details The function is used for I2C Master specify a byte address that a data byte read from Slave. + * + * + */ +uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, rdata = 0U, u8Ctrl = 0U; + + I2C_START(i2c); /* Send START */ + + while (u8Xfering && (u8Err == 0U)) + { + I2C_WAIT_READY(i2c) {} + + switch (I2C_GET_STATUS(i2c)) + { + case 0x08: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1U | 0x00U)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + + case 0x18: /* Slave Address ACK */ + I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */ + break; + + case 0x20: /* Slave Address NACK */ + case 0x30: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1U; + break; + + case 0x28: + u8Ctrl = I2C_CTL_STA_SI; /* Send repeat START */ + break; + + case 0x10: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1U) | 0x01U)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + + case 0x40: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + + case 0x48: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1U; + break; + + case 0x58: + rdata = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0U; + break; + + case 0x38: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1U; + break; + } + + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + + if (u8Err) + { + rdata = 0U; /* If occurs error, return 0 */ + } + return rdata; /* Return read data */ +} + +/** + * @brief Specify a byte register address and read multi bytes from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 bytes) of data read from + * @param[out] rdata[] A data array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for I2C Master specify a byte address that multi data bytes read from Slave. + * + * + */ +uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t rdata[], uint32_t u32rLen) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, u8Ctrl = 0U; + uint32_t u32rxLen = 0U; + + I2C_START(i2c); /* Send START */ + + while (u8Xfering && (u8Err == 0U)) + { + I2C_WAIT_READY(i2c) {} + + switch (I2C_GET_STATUS(i2c)) + { + case 0x08: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1U | 0x00U)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + + case 0x18: /* Slave Address ACK */ + I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */ + break; + + case 0x20: /* Slave Address NACK */ + case 0x30: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1U; + break; + + case 0x28: + u8Ctrl = I2C_CTL_STA_SI; /* Send repeat START */ + break; + + case 0x10: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1U) | 0x01U)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + + case 0x40: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + break; + + case 0x48: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1U; + break; + + case 0x50: + rdata[u32rxLen++] = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */ + + if (u32rxLen < (u32rLen - 1U)) + { + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + } + else + { + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + } + break; + + case 0x58: + rdata[u32rxLen++] = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0U; + break; + + case 0x38: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1U; + break; + } + + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + + return u32rxLen; /* Return bytes length that have been received */ +} + +/** + * @brief Specify two bytes register address and read a byte from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify an address(2 bytes) of data read from + * + * @return Read a byte data from Slave + * + * @details The function is used for I2C Master specify two bytes address that a data byte read from Slave. + * + * + */ +uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, rdata = 0U, u8Addr = 1U, u8Ctrl = 0U; + + I2C_START(i2c); /* Send START */ + + while (u8Xfering && (u8Err == 0U)) + { + I2C_WAIT_READY(i2c) {} + + switch (I2C_GET_STATUS(i2c)) + { + case 0x08: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1U | 0x00U)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + + case 0x18: /* Slave Address ACK */ + I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00U) >> 8U));/* Write Hi byte address of register */ + break; + + case 0x20: /* Slave Address NACK */ + case 0x30: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1U; + break; + + case 0x28: + if (u8Addr) + { + I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFU)); /* Write Lo byte address of register */ + u8Addr = 0U; + } + else + { + u8Ctrl = I2C_CTL_STA_SI; /* Clear SI and send repeat START */ + } + break; + + case 0x10: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1U) | 0x01U)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + + case 0x40: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + + case 0x48: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1U; + break; + + case 0x58: + rdata = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0U; + break; + + case 0x38: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1U; + break; + } + + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + + if (u8Err) + { + rdata = 0U; /* If occurs error, return 0 */ + } + return rdata; /* Return read data */ +} + +/** + * @brief Specify two bytes register address and read multi bytes from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 bytes) of data read from + * @param[out] rdata[] A data array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for I2C Master specify two bytes address that multi data bytes read from Slave. + * + * + */ +uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t rdata[], uint32_t u32rLen) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, u8Addr = 1U, u8Ctrl = 0U; + uint32_t u32rxLen = 0U; + + I2C_START(i2c); /* Send START */ + + while (u8Xfering && (u8Err == 0U)) + { + I2C_WAIT_READY(i2c) {} + + switch (I2C_GET_STATUS(i2c)) + { + case 0x08: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1U | 0x00U)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + + case 0x18: /* Slave Address ACK */ + I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00U) >> 8U));/* Write Hi byte address of register */ + break; + + case 0x20: /* Slave Address NACK */ + case 0x30: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1U; + break; + + case 0x28: + if (u8Addr) + { + I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFU)); /* Write Lo byte address of register */ + u8Addr = 0U; + } + else + { + u8Ctrl = I2C_CTL_STA_SI; /* Clear SI and send repeat START */ + } + break; + + case 0x10: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1U) | 0x01U)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + + case 0x40: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + break; + + case 0x48: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1U; + break; + + case 0x50: + rdata[u32rxLen++] = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */ + + if (u32rxLen < (u32rLen - 1U)) + { + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + } + else + { + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + } + + break; + + case 0x58: + rdata[u32rxLen++] = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0U; + break; + + case 0x38: /* Arbitration Lost */ + default: /* Unknow status */ + I2C_SET_CONTROL_REG(i2c, I2C_CTL_STO_SI); /* Clear SI and send STOP */ + u8Ctrl = I2C_CTL_SI; + u8Err = 1U; + break; + } + + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + + return u32rxLen; /* Return bytes length that have been received */ +} + + +/*@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group I2C_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_pdma.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_pdma.c new file mode 100644 index 00000000000..f63b24f223f --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_pdma.c @@ -0,0 +1,423 @@ +/**************************************************************************//** + * @file pdma.c + * @version V1.00 + * @brief M251 series PDMA driver source file + * + * @note + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "M251.h" + + +static uint8_t u8ChSelect[PDMA_CH_MAX]; + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup PDMA_Driver PDMA Driver + @{ +*/ + + +/** @addtogroup PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions + @{ +*/ + +/** + * @brief PDMA Open + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Mask Channel enable bits. + * + * @return None + * + * @details This function enable the PDMA channels. + */ +void PDMA_Open(PDMA_T *pdma, uint32_t u32Mask) +{ + uint32_t i; + + for (i = 0UL; i < PDMA_CH_MAX; i++) + { + if ((1 << i) & u32Mask) + { + pdma->DSCT[i].CTL = 0UL; + u8ChSelect[i] = PDMA_MEM; + } + } + + pdma->CHCTL |= u32Mask; +} + +/** + * @brief PDMA Close + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @return None + * + * @details This function disable all PDMA channels. + */ +void PDMA_Close(PDMA_T *pdma) +{ + pdma->CHCTL = 0UL; +} + +/** + * @brief Set PDMA Transfer Count + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Width Data width. Valid values are + * - \ref PDMA_WIDTH_8 + * - \ref PDMA_WIDTH_16 + * - \ref PDMA_WIDTH_32 + * @param[in] u32TransCount Transfer count + * + * @return None + * + * @details This function set the selected channel data width and transfer count. + */ +void PDMA_SetTransferCnt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount) +{ + pdma->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXCNT_Msk | PDMA_DSCT_CTL_TXWIDTH_Msk); + pdma->DSCT[u32Ch].CTL |= (u32Width | ((u32TransCount - 1UL) << PDMA_DSCT_CTL_TXCNT_Pos)); +} + +/** + * @brief Set PDMA Stride Mode + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32DestLen Destination stride count + * @param[in] u32SrcLen Source stride count + * @param[in] u32TransCount Transfer count + * + * @return None + * + * @details This function set the selected stride mode. + */ +void PDMA_SetStride(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32DestLen, uint32_t u32SrcLen, uint32_t u32TransCount) +{ + pdma->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_STRIDE_EN_Msk; + pdma->STRIDE[u32Ch].ASOCR = (u32DestLen << 16) | u32SrcLen; + pdma->STRIDE[u32Ch].STC = u32TransCount; +} + +/** + * @brief Set PDMA Transfer Address + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32SrcAddr Source address + * @param[in] u32SrcCtrl Source control attribute. Valid values are + * - \ref PDMA_SAR_INC + * - \ref PDMA_SAR_FIX + * @param[in] u32DstAddr Destination address + * @param[in] u32DstCtrl Destination control attribute. Valid values are + * - \ref PDMA_DAR_INC + * - \ref PDMA_DAR_FIX + * + * @return None + * + * @details This function set the selected channel source/destination address and attribute. + */ +void PDMA_SetTransferAddr(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl) +{ + pdma->DSCT[u32Ch].SA = u32SrcAddr; + pdma->DSCT[u32Ch].DA = u32DstAddr; + pdma->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_SAINC_Msk | PDMA_DSCT_CTL_DAINC_Msk); + pdma->DSCT[u32Ch].CTL |= (u32SrcCtrl | u32DstCtrl); +} + +/** + * @brief Set PDMA Transfer Mode + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Peripheral The selected peripheral. Valid values are + * - \ref PDMA_MEM + * - \ref PDMA_UART0_TX + * - \ref PDMA_UART0_RX + * - \ref PDMA_UART1_TX + * - \ref PDMA_UART1_RX + * - \ref PDMA_UART2_TX + * - \ref PDMA_UART2_RX + * - \ref PDMA_USCI0_TX + * - \ref PDMA_USCI0_RX + * - \ref PDMA_USCI1_TX + * - \ref PDMA_USCI1_RX + * - \ref PDMA_QSPI0_TX + * - \ref PDMA_QSPI0_RX + * - \ref PDMA_SPI0_TX + * - \ref PDMA_SPI0_RX + * - \ref PDMA_PWM0_P1_RX + * - \ref PDMA_PWM0_P2_RX + * - \ref PDMA_PWM0_P3_RX + * - \ref PDMA_PWM1_P1_RX + * - \ref PDMA_PWM1_P2_RX + * - \ref PDMA_PWM1_P3_RX + * - \ref PDMA_I2C0_TX + * - \ref PDMA_I2C0_RX + * - \ref PDMA_I2C1_TX + * - \ref PDMA_I2C1_RX + * - \ref PDMA_TMR0 + * - \ref PDMA_TMR1 + * - \ref PDMA_TMR2 + * - \ref PDMA_TMR3 + * - \ref PDMA_EADC_RX + * - \ref PDMA_DAC0_TX + * - \ref PDMA_PSIO_TX + * - \ref PDMA_PSIO_RX + * - \ref PDMA_USCI2_TX + * - \ref PDMA_USCI2_RX + * @param[in] u32ScatterEn Scatter-gather mode enable + * @param[in] u32DescAddr Scatter-gather descriptor address + * + * @return None + * + * @details This function set the selected channel transfer mode. Include peripheral setting. + */ +void PDMA_SetTransferMode(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr) +{ + u8ChSelect[u32Ch] = u32Peripheral; + + switch (u32Ch) + { + case 0ul: + pdma->REQSEL0_3 = (pdma->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC0_Msk) | u32Peripheral; + break; + + case 1ul: + pdma->REQSEL0_3 = (pdma->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC1_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC1_Pos); + break; + + case 2ul: + pdma->REQSEL0_3 = (pdma->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC2_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC2_Pos); + break; + + case 3ul: + pdma->REQSEL0_3 = (pdma->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC3_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC3_Pos); + break; + + case 4ul: + pdma->REQSEL4_7 = (pdma->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC4_Msk) | u32Peripheral; + break; + + case 5ul: + pdma->REQSEL4_7 = (pdma->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC5_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC5_Pos); + break; + + case 6ul: + pdma->REQSEL4_7 = (pdma->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC6_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC6_Pos); + break; + + case 7ul: + pdma->REQSEL4_7 = (pdma->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC7_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC7_Pos); + break; + + default: + break; + } + + if (u32ScatterEn) + { + pdma->DSCT[u32Ch].CTL = (pdma->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_SCATTER; + pdma->DSCT[u32Ch].NEXT = u32DescAddr - (pdma->SCATBA); + } + else + { + pdma->DSCT[u32Ch].CTL = (pdma->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_BASIC; + } +} + +/** + * @brief Set PDMA Burst Type and Size + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32BurstType Burst mode or single mode. Valid values are + * - \ref PDMA_REQ_SINGLE + * - \ref PDMA_REQ_BURST + * @param[in] u32BurstSize Set the size of burst mode. Valid values are + * - \ref PDMA_BURST_128 + * - \ref PDMA_BURST_64 + * - \ref PDMA_BURST_32 + * - \ref PDMA_BURST_16 + * - \ref PDMA_BURST_8 + * - \ref PDMA_BURST_4 + * - \ref PDMA_BURST_2 + * - \ref PDMA_BURST_1 + * + * @return None + * + * @details This function set the selected channel burst type and size. + */ +void PDMA_SetBurstType(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize) +{ + pdma->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXTYPE_Msk | PDMA_DSCT_CTL_BURSIZE_Msk); + pdma->DSCT[u32Ch].CTL |= (u32BurstType | u32BurstSize); +} + +/** + * @brief Enable timeout function + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Mask Channel enable bits. + * + * @return None + * + * @details This function enable timeout function of the selected channel(s). + */ +void PDMA_EnableTimeout(PDMA_T *pdma, uint32_t u32Mask) +{ + pdma->TOUTEN |= u32Mask; +} + +/** + * @brief Disable timeout function + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Mask Channel enable bits. + * + * @return None + * + * @details This function disable timeout function of the selected channel(s). + */ +void PDMA_DisableTimeout(PDMA_T *pdma, uint32_t u32Mask) +{ + pdma->TOUTEN &= ~u32Mask; +} + +/** + * @brief Set PDMA Timeout Count + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32OnOff Enable/disable time out function + * @param[in] u32TimeOutCnt Timeout count + * + * @return None + * + * @details This function set the timeout count. + * @note M251 only supported channel 0/1. + */ +void PDMA_SetTimeOut(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt) +{ + switch (u32Ch) + { + case 0ul: + pdma->TOC0_1 = (pdma->TOC0_1 & ~PDMA_TOC0_1_TOC0_Msk) | u32TimeOutCnt; + break; + + case 1ul: + pdma->TOC0_1 = (pdma->TOC0_1 & ~PDMA_TOC0_1_TOC1_Msk) | (u32TimeOutCnt << PDMA_TOC0_1_TOC1_Pos); + break; + + default: + break; + } + + if (u32OnOff) + pdma->TOUTEN |= (1 << u32Ch); + else + pdma->TOUTEN &= ~(1 << u32Ch); +} + +/** + * @brief Trigger PDMA + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details This function trigger the selected channel. + */ +void PDMA_Trigger(PDMA_T *pdma, uint32_t u32Ch) +{ + if (u8ChSelect[u32Ch] == PDMA_MEM) + { + pdma->SWREQ = (1ul << u32Ch); + } + else {} +} + +/** + * @brief Enable Interrupt + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Mask The Interrupt Type. Valid values are + * - \ref PDMA_INT_TRANS_DONE + * - \ref PDMA_INT_TEMPTY + * - \ref PDMA_INT_TIMEOUT + * + * @return None + * + * @details This function enable the selected channel interrupt. + */ +void PDMA_EnableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask) +{ + switch (u32Mask) + { + case PDMA_INT_TRANS_DONE: + pdma->INTEN |= (1ul << u32Ch); + break; + + case PDMA_INT_TEMPTY: + pdma->DSCT[u32Ch].CTL &= ~PDMA_DSCT_CTL_TBINTDIS_Msk; + break; + + case PDMA_INT_TIMEOUT: + pdma->TOUTIEN |= (1ul << u32Ch); + break; + + default: + break; + } +} + +/** + * @brief Disable Interrupt + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Mask The Interrupt Type. Valid values are + * - \ref PDMA_INT_TRANS_DONE + * - \ref PDMA_INT_TEMPTY + * - \ref PDMA_INT_TIMEOUT + * + * @return None + * + * @details This function disable the selected channel interrupt. + */ +void PDMA_DisableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask) +{ + switch (u32Mask) + { + case PDMA_INT_TRANS_DONE: + pdma->INTEN &= ~(1ul << u32Ch); + break; + + case PDMA_INT_TEMPTY: + pdma->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_TBINTDIS_Msk; + break; + + case PDMA_INT_TIMEOUT: + pdma->TOUTIEN &= ~(1ul << u32Ch); + break; + + default: + break; + } +} + +/*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group PDMA_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_pwm.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_pwm.c new file mode 100644 index 00000000000..fda96fec3b6 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_pwm.c @@ -0,0 +1,1079 @@ +/**************************************************************************//** + * @file pwm.c + * @version V0.10 + * @brief M251 series PWM driver source file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup PWM_Driver PWM Driver + @{ +*/ + + +/** @addtogroup PWM_EXPORTED_FUNCTIONS PWM Exported Functions + @{ +*/ + +/** + * @brief Configure PWM capture and get the nearest unit time. + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @param[in] u32UnitTimeNsec The unit time of counter + * @param[in] u32CaptureEdge The condition to latch the counter. This parameter is not used + * @return The nearest unit time in nano second. + * @details This function is used to Configure PWM capture and get the nearest unit time. + */ +uint32_t PWM_ConfigCaptureChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge) +{ + uint32_t u32Src; + uint32_t u32PWMClockSrc; + uint32_t u32NearestUnitTimeNsec; + uint16_t u16Prescale = 1UL, u16CNR = 0xFFFFUL; + uint8_t u8BreakLoop = 0UL; + + if (pwm == PWM0) + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_PWM0SEL_Msk; + else//(pwm == PWM1) + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_PWM1SEL_Msk; + + if (u32Src == 0UL) + { + //clock source is from PLL clock + u32PWMClockSrc = CLK_GetPLLClockFreq(); + } + else + { + //clock source is from PCLK + SystemCoreClockUpdate(); + + if (pwm == PWM0) + { + u32PWMClockSrc = CLK_GetPCLK0Freq(); + } + else /* (pwm == PWM1) */ + { + u32PWMClockSrc = CLK_GetPCLK1Freq(); + } + } + + u32PWMClockSrc /= 1000UL; + + for (u16Prescale = 1UL; u16Prescale <= 0x1000UL; u16Prescale++) + { + u32NearestUnitTimeNsec = (1000000UL * u16Prescale) / u32PWMClockSrc; + + if (u32NearestUnitTimeNsec < u32UnitTimeNsec) + { + if (u16Prescale == 0x1000UL) + { + /* limit to the maximum unit time(nano second) */ + u8BreakLoop = 1UL; + } + + if (!((1000000UL * (u16Prescale + 1UL) > (u32NearestUnitTimeNsec * u32PWMClockSrc)))) + { + u8BreakLoop = 1UL; + } + } + else + { + u8BreakLoop = 1UL; + } + + if (u8BreakLoop) + { + break; + } + } + + // convert to real register value + u16Prescale = u16Prescale - 1UL; + // every two channels share a prescaler + PWM_SET_PRESCALER(pwm, u32ChannelNum, (uint32_t)u16Prescale); + + // set PWM to down count type(edge aligned) + (pwm)->CTL1 = ((pwm)->CTL1 & ~(PWM_CTL1_CNTTYPE0_Msk << ((u32ChannelNum >> 1UL) << 2UL))) | (1UL << ((u32ChannelNum >> 1UL) << 2UL)); + + PWM_SET_CNR(pwm, u32ChannelNum, u16CNR); + + return (u32NearestUnitTimeNsec); +} + +/** + * @brief This function Configure PWM generator and get the nearest frequency in edge aligned auto-reload mode + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @param[in] u32Frequency Target generator frequency + * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%... + * @return Nearest frequency clock in nano second + * @note Since every two channels, (0 & 1), (2 & 3), shares a prescaler. Call this API to configure PWM frequency may affect + * existing frequency of other channel. + */ +uint32_t PWM_ConfigOutputChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle) +{ + return PWM_ConfigOutputChannel2(pwm, u32ChannelNum, u32Frequency, u32DutyCycle, 1); +} + +/** + * @brief This function Configure PWM generator and get the nearest frequency in edge aligned auto-reload mode + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @param[in] u32Frequency Target generator frequency = u32Frequency / u32Frequency2 + * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%... + * @param[in] u32Frequency2 Target generator frequency = u32Frequency / u32Frequency2 + * @return Nearest frequency clock in nano second + * @note Since every two channels, (0 & 1), (2 & 3), shares a prescaler. Call this API to configure PWM frequency may affect + * existing frequency of other channel. + */ +uint32_t PWM_ConfigOutputChannel2(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle, uint32_t u32Frequency2) +{ + uint32_t u32Src; + uint32_t u32PWMClockSrc; + uint32_t i; + uint16_t u16Prescale = 1UL, u16CNR = 0xFFFFUL; + + if (pwm == PWM0) + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_PWM0SEL_Msk; + else//(pwm == PWM1) + u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_PWM1SEL_Msk; + + if (u32Src == 0UL) + { + //clock source is from PLL clock + u32PWMClockSrc = CLK_GetPLLClockFreq(); + } + else + { + //clock source is from PCLK + SystemCoreClockUpdate(); + + if (pwm == PWM0) + { + u32PWMClockSrc = CLK_GetPCLK0Freq(); + } + else /* (pwm == PWM1) */ + { + u32PWMClockSrc = CLK_GetPCLK1Freq(); + } + } + + for (u16Prescale = 1UL; u16Prescale < 0xFFFUL; u16Prescale++) //prescale could be 0~0xFFF + { + // Note: Support frequency < 1 + i = (uint64_t) u32PWMClockSrc * u32Frequency2 / u32Frequency / u16Prescale; + + // If target value is larger than CNR, need to use a larger prescaler + if (i <= (0x10000UL)) + { + u16CNR = (uint16_t)i; + break; + } + } + + // Store return value here 'cos we're gonna change u16Prescale & u16CNR to the real value to fill into register + i = u32PWMClockSrc / ((uint32_t)u16Prescale * (uint32_t)u16CNR); + + // convert to real register value + u16Prescale = u16Prescale - 1UL; + // every two channels share a prescaler + PWM_SET_PRESCALER(pwm, u32ChannelNum, (uint32_t)u16Prescale); + // set PWM to down count type(edge aligned) + (pwm)->CTL1 = ((pwm)->CTL1 & ~(PWM_CTL1_CNTTYPE0_Msk << ((u32ChannelNum >> 1UL) << 2UL))) | (1UL << ((u32ChannelNum >> 1UL) << 2UL)); + + u16CNR -= 1UL; + PWM_SET_CNR(pwm, u32ChannelNum, u16CNR); + + if (u32DutyCycle) + { + if (u32DutyCycle >= 100UL) + PWM_SET_CMR(pwm, u32ChannelNum, u16CNR); + else + PWM_SET_CMR(pwm, u32ChannelNum, u32DutyCycle * (u16CNR + 1UL) / 100UL); + + (pwm)->WGCTL0 &= ~((PWM_WGCTL0_PRDPCTL0_Msk | PWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum << 1UL)); + (pwm)->WGCTL0 |= (PWM_OUTPUT_LOW << ((u32ChannelNum << 1UL) + PWM_WGCTL0_PRDPCTL0_Pos)); + (pwm)->WGCTL1 &= ~((PWM_WGCTL1_CMPDCTL0_Msk | PWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum << 1UL)); + (pwm)->WGCTL1 |= (PWM_OUTPUT_HIGH << ((u32ChannelNum << 1UL) + PWM_WGCTL1_CMPDCTL0_Pos)); + } + else + { + PWM_SET_CMR(pwm, u32ChannelNum, 0UL); + (pwm)->WGCTL0 &= ~((PWM_WGCTL0_PRDPCTL0_Msk | PWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum << 1UL)); + (pwm)->WGCTL0 |= (PWM_OUTPUT_LOW << ((u32ChannelNum << 1UL) + PWM_WGCTL0_ZPCTL0_Pos)); + (pwm)->WGCTL1 &= ~((PWM_WGCTL1_CMPDCTL0_Msk | PWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum << 1UL)); + (pwm)->WGCTL1 |= (PWM_OUTPUT_HIGH << ((u32ChannelNum << 1UL) + PWM_WGCTL1_CMPDCTL0_Pos)); + } + + return (i); +} + +/** + * @brief Start PWM module + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to start PWM module. + * @note Every two channels share the same setting. + */ +void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask) +{ + uint32_t i; + + for (i = 0UL; i < PWM_CHANNEL_NUM; i ++) + { + if (u32ChannelMask & (1UL << i)) + { + (pwm)->CNTEN |= (1UL << ((i >> 1UL) << 1UL)); + } + } +} + +/** + * @brief Stop PWM module + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to stop PWM module. + * @note Every two channels share the same setting. + */ +void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask) +{ + uint32_t i; + + for (i = 0UL; i < PWM_CHANNEL_NUM; i ++) + { + if (u32ChannelMask & (1UL << i)) + { + (pwm)->PERIOD[((i >> 1UL) << 1UL)] = 0UL; + } + } +} + +/** + * @brief Stop PWM generation immediately by clear channel enable bit + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to stop PWM generation immediately by clear channel enable bit. + * @note Every two channels share the same setting. + */ +void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask) +{ + uint32_t i; + + for (i = 0UL; i < PWM_CHANNEL_NUM; i ++) + { + if (u32ChannelMask & (1UL << i)) + { + (pwm)->CNTEN &= ~(1UL << ((i >> 1UL) << 1UL)); + } + } +} + +/** + * @brief Enable selected channel to trigger ADC + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @param[in] u32Condition The condition to trigger ADC. Combination of following conditions: + * - \ref PWM_TRIGGER_ADC_EVEN_ZERO_POINT + * - \ref PWM_TRIGGER_ADC_EVEN_PERIOD_POINT + * - \ref PWM_TRIGGER_ADC_EVEN_ZERO_OR_PERIOD_POINT + * - \ref PWM_TRIGGER_ADC_EVEN_CMP_UP_COUNT_POINT + * - \ref PWM_TRIGGER_ADC_EVEN_CMP_DOWN_COUNT_POINT + * - \ref PWM_TRIGGER_ADC_ODD_CMP_UP_COUNT_POINT + * - \ref PWM_TRIGGER_ADC_ODD_CMP_DOWN_COUNT_POINT + * @return None + * @details This function is used to enable selected channel to trigger ADC. + */ +void PWM_EnableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + if (u32ChannelNum < 4UL) + { + (pwm)->EADCTS0 &= ~((PWM_EADCTS0_TRGSEL0_Msk) << (u32ChannelNum << 3UL)); + (pwm)->EADCTS0 |= ((PWM_EADCTS0_TRGEN0_Msk | u32Condition) << (u32ChannelNum << 3UL)); + } + else + { + (pwm)->EADCTS1 &= ~((PWM_EADCTS1_TRGSEL4_Msk) << ((u32ChannelNum - 4UL) << 3UL)); + (pwm)->EADCTS1 |= ((PWM_EADCTS1_TRGEN4_Msk | u32Condition) << ((u32ChannelNum - 4UL) << 3UL)); + } +} + +/** + * @brief Disable selected channel to trigger ADC + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable selected channel to trigger ADC. + */ +void PWM_DisableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum) +{ + if (u32ChannelNum < 4UL) + { + (pwm)->EADCTS0 &= ~(PWM_EADCTS0_TRGEN0_Msk << (u32ChannelNum << 3UL)); + } + else + { + (pwm)->EADCTS1 &= ~(PWM_EADCTS1_TRGEN4_Msk << ((u32ChannelNum - 4UL) << 3UL)); + } +} + +/** + * @brief Clear selected channel trigger ADC flag + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @param[in] u32Condition This parameter is not used + * @return None + * @details This function is used to clear selected channel trigger ADC flag. + */ +void PWM_ClearADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + (pwm)->STATUS = (PWM_STATUS_EADCTRG0_Msk << u32ChannelNum); +} + +/** + * @brief Get selected channel trigger ADC flag + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @retval 0 The specified channel trigger ADC to start of conversion flag is not set + * @retval 1 The specified channel trigger ADC to start of conversion flag is set + * @details This function is used to get PWM trigger ADC to start of conversion flag for specified channel. + */ +uint32_t PWM_GetADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum) +{ + return (((pwm)->STATUS & (PWM_STATUS_EADCTRG0_Msk << u32ChannelNum)) ? 1UL : 0UL); +} + +/** + * @brief This function enable fault brake of selected channel(s) + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * @param[in] u32LevelMask Output high or low while fault brake occurs, each bit represent the level of a channel + * while fault brake occurs. Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32BrakeSource Fault brake source, could be one of following source + * - \ref PWM_FB_EDGE_ACMP0 + * - \ref PWM_FB_EDGE_ACMP1 + * - \ref PWM_FB_EDGE_BKP0 + * - \ref PWM_FB_EDGE_BKP1 + * - \ref PWM_FB_EDGE_SYS_CSS + * - \ref PWM_FB_EDGE_SYS_BOD + * - \ref PWM_FB_EDGE_SYS_COR + * - \ref PWM_FB_LEVEL_ACMP0 + * - \ref PWM_FB_LEVEL_ACMP1 + * - \ref PWM_FB_LEVEL_BKP0 + * - \ref PWM_FB_LEVEL_BKP1 + * - \ref PWM_FB_LEVEL_SYS_CSS + * - \ref PWM_FB_LEVEL_SYS_BOD + * - \ref PWM_FB_LEVEL_SYS_COR + * @return None + * @details This function is used to enable fault brake of selected channel(s). + * The write-protection function should be disabled before using this function. + */ +void PWM_EnableFaultBrake(PWM_T *pwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource) +{ + uint32_t i; + + for (i = 0UL; i < PWM_CHANNEL_NUM; i ++) + { + if (u32ChannelMask & (1UL << i)) + { + if ((u32BrakeSource == PWM_FB_EDGE_SYS_CSS) || (u32BrakeSource == PWM_FB_EDGE_SYS_BOD) || \ + (u32BrakeSource == PWM_FB_EDGE_SYS_COR) || \ + (u32BrakeSource == PWM_FB_LEVEL_SYS_CSS) || (u32BrakeSource == PWM_FB_LEVEL_SYS_BOD) || \ + (u32BrakeSource == PWM_FB_LEVEL_SYS_COR)) + { + (pwm)->BRKCTL[i >> 1UL] |= (u32BrakeSource & (PWM_BRKCTL_SYSEBEN_Msk | PWM_BRKCTL_SYSLBEN_Msk)); + (pwm)->FAILBRK |= (u32BrakeSource & 0xBUL); + } + else + { + (pwm)->BRKCTL[i >> 1UL] |= u32BrakeSource; + } + } + + if (u32LevelMask & (1UL << i)) + { + if ((i & 0x1UL) == 0UL) + { + //set brake action as high level for even channel + (pwm)->BRKCTL[i >> 1UL] &= ~PWM_BRKCTL0_1_BRKAEVEN_Msk; + (pwm)->BRKCTL[i >> 1UL] |= ((3UL) << PWM_BRKCTL0_1_BRKAEVEN_Pos); + } + else + { + //set brake action as high level for odd channel + (pwm)->BRKCTL[i >> 1UL] &= ~PWM_BRKCTL0_1_BRKAODD_Msk; + (pwm)->BRKCTL[i >> 1UL] |= ((3UL) << PWM_BRKCTL0_1_BRKAODD_Pos); + } + } + else + { + if ((i & 0x1UL) == 0UL) + { + //set brake action as low level for even channel + (pwm)->BRKCTL[i >> 1UL] &= ~PWM_BRKCTL0_1_BRKAEVEN_Msk; + (pwm)->BRKCTL[i >> 1UL] |= ((2UL) << PWM_BRKCTL0_1_BRKAEVEN_Pos); + } + else + { + //set brake action as low level for odd channel + (pwm)->BRKCTL[i >> 1UL] &= ~PWM_BRKCTL0_1_BRKAODD_Msk; + (pwm)->BRKCTL[i >> 1UL] |= ((2UL) << PWM_BRKCTL0_1_BRKAODD_Pos); + } + } + } + +} + +/** + * @brief Enable capture of selected channel(s) + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to enable capture of selected channel(s). + */ +void PWM_EnableCapture(PWM_T *pwm, uint32_t u32ChannelMask) +{ + (pwm)->CAPINEN |= u32ChannelMask; + (pwm)->CAPCTL |= u32ChannelMask; +} + +/** + * @brief Disable capture of selected channel(s) + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to disable capture of selected channel(s). + */ +void PWM_DisableCapture(PWM_T *pwm, uint32_t u32ChannelMask) +{ + (pwm)->CAPINEN &= ~u32ChannelMask; + (pwm)->CAPCTL &= ~u32ChannelMask; +} + +/** + * @brief Enables PWM output generation of selected channel(s) + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output... + * @return None + * @details This function is used to enable PWM output generation of selected channel(s). + */ +void PWM_EnableOutput(PWM_T *pwm, uint32_t u32ChannelMask) +{ + (pwm)->POEN |= u32ChannelMask; +} + +/** + * @brief Disables PWM output generation of selected channel(s) + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Set bit 0 to 1 disables channel 0 output, set bit 1 to 1 disables channel 1 output... + * @return None + * @details This function is used to disable PWM output generation of selected channel(s). + */ +void PWM_DisableOutput(PWM_T *pwm, uint32_t u32ChannelMask) +{ + (pwm)->POEN &= ~u32ChannelMask; +} + +/** + * @brief Enable Dead zone of selected channel + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @param[in] u32Duration Dead zone length in PWM clock count, valid values are between 0~0xFFF, but 0 means there is no Dead zone. + * @return None + * @details This function is used to enable Dead zone of selected channel. + * The write-protection function should be disabled before using this function. + * @note Every two channels share the same setting. + */ +void PWM_EnableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration) +{ + // every two channels share the same setting + (pwm)->DTCTL[(u32ChannelNum) >> 1UL] &= ~PWM_DTCTL0_1_DTCNT_Msk; + (pwm)->DTCTL[(u32ChannelNum) >> 1UL] |= PWM_DTCTL0_1_DTEN_Msk | u32Duration; +} + +/** + * @brief Disable Dead zone of selected channel + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable Dead zone of selected channel. + * The write-protection function should be disabled before using this function. + */ +void PWM_DisableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum) +{ + // every two channels shares the same setting + (pwm)->DTCTL[(u32ChannelNum) >> 1UL] &= ~PWM_DTCTL0_1_DTEN_Msk; +} + +/** + * @brief Enable capture interrupt of selected channel. + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref PWM_CAPTURE_INT_RISING_LATCH + * - \ref PWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to enable capture interrupt of selected channel. + */ +void PWM_EnableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (pwm)->CAPIEN |= (u32Edge << u32ChannelNum); +} + +/** + * @brief Disable capture interrupt of selected channel. + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref PWM_CAPTURE_INT_RISING_LATCH + * - \ref PWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to disable capture interrupt of selected channel. + */ +void PWM_DisableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (pwm)->CAPIEN &= ~(u32Edge << u32ChannelNum); +} + +/** + * @brief Clear capture interrupt of selected channel. + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref PWM_CAPTURE_INT_RISING_LATCH + * - \ref PWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to clear capture interrupt of selected channel. + */ +void PWM_ClearCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (pwm)->CAPIF = (u32Edge << u32ChannelNum); +} + +/** + * @brief Get capture interrupt of selected channel. + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @retval 0 No capture interrupt + * @retval 1 Rising edge latch interrupt + * @retval 2 Falling edge latch interrupt + * @retval 3 Rising and falling latch interrupt + * @details This function is used to get capture interrupt of selected channel. + */ +uint32_t PWM_GetCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum) +{ + uint32_t u32CapFFlag, u32CapRFlag ; + u32CapFFlag = (((pwm)->CAPIF & (PWM_CAPIF_CFLIF0_Msk << u32ChannelNum)) ? 1UL : 0UL) ; + u32CapRFlag = (((pwm)->CAPIF & (PWM_CAPIF_CRLIF0_Msk << u32ChannelNum)) ? 1UL : 0UL) ; + return ((u32CapFFlag << 1UL) | u32CapRFlag); +} +/** + * @brief Enable duty interrupt of selected channel + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @param[in] u32IntDutyType Duty interrupt type, could be either + * - \ref PWM_DUTY_INT_DOWN_COUNT_MATCH_CMP + * - \ref PWM_DUTY_INT_UP_COUNT_MATCH_CMP + * @return None + * @details This function is used to enable duty interrupt of selected channel. + */ +void PWM_EnableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType) +{ + (pwm)->INTEN0 |= (u32IntDutyType << u32ChannelNum); +} + +/** + * @brief Disable duty interrupt of selected channel + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable duty interrupt of selected channel. + */ +void PWM_DisableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum) +{ + (pwm)->INTEN0 &= ~((PWM_DUTY_INT_DOWN_COUNT_MATCH_CMP | PWM_DUTY_INT_UP_COUNT_MATCH_CMP) << u32ChannelNum); +} + +/** + * @brief Clear duty interrupt flag of selected channel + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear duty interrupt flag of selected channel. + */ +void PWM_ClearDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum) +{ + (pwm)->INTSTS0 = (PWM_INTSTS0_CMPUIF0_Msk | PWM_INTSTS0_CMPDIF0_Msk) << u32ChannelNum; +} + +/** + * @brief Get duty interrupt flag of selected channel + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @return Duty interrupt flag of specified channel + * @retval 0 Duty interrupt did not occur + * @retval 1 Duty interrupt occurred + * @details This function is used to get duty interrupt flag of selected channel. + */ +uint32_t PWM_GetDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum) +{ + return ((((pwm)->INTSTS0 & ((PWM_INTSTS0_CMPDIF0_Msk | PWM_INTSTS0_CMPUIF0_Msk) << u32ChannelNum))) ? 1 : 0); +} + +/** + * @brief Enable load mode of selected channel + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @param[in] u32LoadMode PWM counter loading mode. + * - \ref PWM_LOAD_MODE_IMMEDIATE + * - \ref PWM_LOAD_MODE_CENTER + * @return None + * @details This function is used to enable load mode of selected channel. + */ +void PWM_EnableLoadMode(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32LoadMode) +{ + (pwm)->CTL0 |= (u32LoadMode << u32ChannelNum); +} + +/** + * @brief Disable load mode of selected channel + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @param[in] u32LoadMode PWM counter loading mode. + * - \ref PWM_LOAD_MODE_IMMEDIATE + * - \ref PWM_LOAD_MODE_CENTER + * @return None + * @details This function is used to disable load mode of selected channel. + */ +void PWM_DisableLoadMode(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32LoadMode) +{ + (pwm)->CTL0 &= ~(u32LoadMode << u32ChannelNum); +} + +/** + * @brief This function enable fault brake interrupt + * @param[in] pwm The pointer of the specified PWM module + * @param[in] u32BrakeSource Fault brake source. + * - \ref PWM_FB_EDGE + * - \ref PWM_FB_LEVEL + * @return None + * @details This function is used to enable fault brake interrupt. + * The write-protection function should be disabled before using this function. + * @note Every two channels share the same setting. + */ +void PWM_EnableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource) +{ + (pwm)->INTEN1 |= (0x7UL << u32BrakeSource); +} + +/** + * @brief This function disable fault brake interrupt + * @param[in] pwm The pointer of the specified PWM module + * @param[in] u32BrakeSource Fault brake source. + * - \ref PWM_FB_EDGE + * - \ref PWM_FB_LEVEL + * @return None + * @details This function is used to disable fault brake interrupt. + * The write-protection function should be disabled before using this function. + * @note Every two channels share the same setting. + */ +void PWM_DisableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource) +{ + (pwm)->INTEN1 &= ~(0x7UL << u32BrakeSource); +} + +/** + * @brief This function clear fault brake interrupt of selected source + * @param[in] pwm The pointer of the specified PWM module + * @param[in] u32BrakeSource Fault brake source. + * - \ref PWM_FB_EDGE + * - \ref PWM_FB_LEVEL + * @return None + * @details This function is used to clear fault brake interrupt of selected source. + * The write-protection function should be disabled before using this function. + */ +void PWM_ClearFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource) +{ + (pwm)->INTSTS1 = (0x3fUL << u32BrakeSource); +} + +/** + * @brief This function get fault brake interrupt flag of selected source + * @param[in] pwm The pointer of the specified PWM module + * @param[in] u32BrakeSource Fault brake source, could be either + * - \ref PWM_FB_EDGE + * - \ref PWM_FB_LEVEL + * @return Fault brake interrupt flag of specified source + * @retval 0 Fault brake interrupt did not occurred + * @retval 1 Fault brake interrupt occurred + * @details This function is used to get fault brake interrupt flag of selected source. + */ +uint32_t PWM_GetFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource) +{ + return (((pwm)->INTSTS1 & (0x3fUL << u32BrakeSource)) ? 1UL : 0UL); +} + +/** + * @brief Enable period interrupt of selected channel + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5. Every two channels share the same setting. + * @param[in] u32IntPeriodType Period interrupt type. This parameter is not used. + * @return None + * @details This function is used to enable period interrupt of selected channel. + */ +void PWM_EnablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType) +{ + (pwm)->INTEN0 |= (PWM_INTEN0_PIEN0_Msk << ((u32ChannelNum >> 1UL) << 1UL)); +} + +/** + * @brief Disable period interrupt of selected channel + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5. Every two channels share the same setting. + * @return None + * @details This function is used to disable period interrupt of selected channel. + */ +void PWM_DisablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum) +{ + (pwm)->INTEN0 &= ~(PWM_INTEN0_PIEN0_Msk << ((u32ChannelNum >> 1UL) << 1UL)); +} + +/** + * @brief Clear period interrupt of selected channel + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5. Every two channels share the same setting. + * @return None + * @details This function is used to clear period interrupt of selected channel. + */ +void PWM_ClearPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum) +{ + (pwm)->INTSTS0 = (PWM_INTSTS0_PIF0_Msk << ((u32ChannelNum >> 1UL) << 1UL)); +} + +/** + * @brief Get period interrupt of selected channel + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5. Every two channels share the same setting. + * @return Period interrupt flag of specified channel + * @retval 0 Period interrupt did not occur + * @retval 1 Period interrupt occurred + * @details This function is used to get period interrupt of selected channel. + */ +uint32_t PWM_GetPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum) +{ + return (((pwm)->INTSTS0 & (PWM_INTSTS0_PIF0_Msk << ((u32ChannelNum >> 1UL) << 1UL))) ? 1UL : 0UL); +} + +/** + * @brief Enable zero interrupt of selected channel + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5. Every two channels share the same setting. + * @return None + * @details This function is used to enable zero interrupt of selected channel. + */ +void PWM_EnableZeroInt(PWM_T *pwm, uint32_t u32ChannelNum) +{ + (pwm)->INTEN0 |= (PWM_INTEN0_ZIEN0_Msk << ((u32ChannelNum >> 1UL) << 1UL)); +} + +/** + * @brief Disable zero interrupt of selected channel + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5. Every two channels share the same setting. + * @return None + * @details This function is used to disable zero interrupt of selected channel. + */ +void PWM_DisableZeroInt(PWM_T *pwm, uint32_t u32ChannelNum) +{ + (pwm)->INTEN0 &= ~(PWM_INTEN0_ZIEN0_Msk << ((u32ChannelNum >> 1UL) << 1UL)); +} + +/** + * @brief Clear zero interrupt of selected channel + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5. Every two channels share the same setting. + * @return None + * @details This function is used to clear zero interrupt of selected channel. + */ +void PWM_ClearZeroIntFlag(PWM_T *pwm, uint32_t u32ChannelNum) +{ + (pwm)->INTSTS0 = (PWM_INTSTS0_ZIF0_Msk << ((u32ChannelNum >> 1UL) << 1UL)); +} + +/** + * @brief Get zero interrupt of selected channel + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5. Every two channels share the same setting. + * @return zero interrupt flag of specified channel + * @retval 0 zero interrupt did not occur + * @retval 1 zero interrupt occurred + * @details This function is used to get zero interrupt of selected channel. + */ +uint32_t PWM_GetZeroIntFlag(PWM_T *pwm, uint32_t u32ChannelNum) +{ + return (((pwm)->INTSTS0 & (PWM_INTSTS0_ZIF0_Msk << ((u32ChannelNum >> 1UL) << 1UL))) ? 1UL : 0UL); +} + +/** + * @brief Set PWM clock source + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 + * @param[in] u32ClkSrcSel PWM external clock source. + * - \ref PWM_CLKSRC_PWM_CLK + * - \ref PWM_CLKSRC_TIMER0 + * - \ref PWM_CLKSRC_TIMER1 + * - \ref PWM_CLKSRC_TIMER2 + * - \ref PWM_CLKSRC_TIMER3 + * @return None + * @details This function is used to set PWM clock source. + * @note Every two channels share the same setting. + */ +void PWM_SetClockSource(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel) +{ + (pwm)->CLKSRC = ((pwm)->CLKSRC & ~(PWM_CLKSRC_ECLKSRC0_Msk << ((u32ChannelNum >> 1UL) * PWM_CLKSRC_ECLKSRC2_Pos))) | \ + (u32ClkSrcSel << ((u32ChannelNum >> 1UL) * PWM_CLKSRC_ECLKSRC2_Pos)); +} + +/** + * @brief Enable PWM brake noise filter function + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1. + * @param[in] u32ClkCnt SYNC Edge Detector Filter Count. This controls the counter number of edge detector + * @param[in] u32ClkDivSel SYNC Edge Detector Filter Clock Selection. + * - \ref PWM_NF_CLK_DIV_1 + * - \ref PWM_NF_CLK_DIV_2 + * - \ref PWM_NF_CLK_DIV_4 + * - \ref PWM_NF_CLK_DIV_8 + * - \ref PWM_NF_CLK_DIV_16 + * - \ref PWM_NF_CLK_DIV_32 + * - \ref PWM_NF_CLK_DIV_64 + * - \ref PWM_NF_CLK_DIV_128 + * @return None + * @details This function is used to enable PWM brake noise filter function. + */ +void PWM_EnableBrakeNoiseFilter(PWM_T *pwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel) +{ + (pwm)->BNF = ((pwm)->BNF & ~((PWM_BNF_BRK0NFCNT_Msk | PWM_BNF_BRK0NFSEL_Msk) << (u32BrakePinNum * PWM_BNF_BRK1FEN_Pos))) | \ + (((u32ClkCnt << PWM_BNF_BRK0NFCNT_Pos) | (u32ClkDivSel << PWM_BNF_BRK0NFSEL_Pos) | PWM_BNF_BRK0FEN_Msk) << (u32BrakePinNum * PWM_BNF_BRK1FEN_Pos)); +} + +/** + * @brief Disable PWM brake noise filter function + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1. + * @return None + * @details This function is used to disable PWM brake noise filter function. + */ +void PWM_DisableBrakeNoiseFilter(PWM_T *pwm, uint32_t u32BrakePinNum) +{ + (pwm)->BNF &= ~(PWM_BNF_BRK0FEN_Msk << (u32BrakePinNum * PWM_BNF_BRK1FEN_Pos)); +} + +/** + * @brief Enable PWM brake pin inverse function + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1. + * @return None + * @details This function is used to enable PWM brake pin inverse function. + */ +void PWM_EnableBrakePinInverse(PWM_T *pwm, uint32_t u32BrakePinNum) +{ + (pwm)->BNF |= (PWM_BNF_BRK0PINV_Msk << (u32BrakePinNum * PWM_BNF_BRK1FEN_Pos)); +} + +/** + * @brief Disable PWM brake pin inverse function + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1. + * @return None + * @details This function is used to disable PWM brake pin inverse function. + */ +void PWM_DisableBrakePinInverse(PWM_T *pwm, uint32_t u32BrakePinNum) +{ + (pwm)->BNF &= ~(PWM_BNF_BRK0PINV_Msk << (u32BrakePinNum * PWM_BNF_BRK1FEN_Pos)); +} + +/** + * @brief Set PWM brake pin source + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1. + * @param[in] u32SelAnotherModule Select to another module. Valid values are TRUE or FALSE. + * @return None + * @details This function is used to set PWM brake pin source. + */ +void PWM_SetBrakePinSource(PWM_T *pwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule) +{ + (pwm)->BNF = ((pwm)->BNF & ~(PWM_BNF_BK0SRC_Msk << (u32BrakePinNum << 3UL))) | (u32SelAnotherModule << (PWM_BNF_BK0SRC_Pos + (u32BrakePinNum << 3UL))); +} + +/** + * @brief Get the time-base counter reached its maximum value flag of selected channel + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5. Every two channels share the same setting. + * @return Count to max interrupt flag of specified channel + * @retval 0 Count to max interrupt did not occur + * @retval 1 Count to max interrupt occurred + * @details This function is used to get the time-base counter reached its maximum value flag of selected channel. + */ +uint32_t PWM_GetWrapAroundFlag(PWM_T *pwm, uint32_t u32ChannelNum) +{ + return (((pwm)->STATUS & (PWM_STATUS_CNTMAX0_Msk << ((u32ChannelNum >> 1UL) << 1UL))) ? 1UL : 0UL); +} + +/** + * @brief Clear the time-base counter reached its maximum value flag of selected channel + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5. Every two channels share the same setting. + * @return None + * @details This function is used to clear the time-base counter reached its maximum value flag of selected channel. + */ +void PWM_ClearWrapAroundFlag(PWM_T *pwm, uint32_t u32ChannelNum) +{ + (pwm)->STATUS = (PWM_STATUS_CNTMAX0_Msk << ((u32ChannelNum >> 1UL) << 1UL)); +} + +/** + * @brief Enables PDMA transfer of selected channel for PWM capture + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32ChannelNum PWM channel number. + * @param[in] u32RisingFirst The capture order is rising, falling first. Every two channels share the same setting. Valid values are TRUE and FALSE. + * @param[in] u32Mode Captured data transferred by PDMA interrupt type. It could be either + * - \ref PWM_CAPTURE_PDMA_RISING_LATCH + * - \ref PWM_CAPTURE_PDMA_FALLING_LATCH + * - \ref PWM_CAPTURE_PDMA_RISING_FALLING_LATCH + * @return None + * @details This function is used to enable PDMA transfer of selected channel(s) for PWM capture. + * @note This function can only selects even or odd channel of pairs to do PDMA transfer. + */ +void PWM_EnablePDMA(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode) +{ + uint32_t u32IsOddCh; + u32IsOddCh = u32ChannelNum % 2UL; + (pwm)->PDMACTL = ((pwm)->PDMACTL & ~((PWM_PDMACTL_CHSEL0_1_Msk | PWM_PDMACTL_CAPORD0_1_Msk | PWM_PDMACTL_CAPMOD0_1_Msk) << ((u32ChannelNum >> 1UL) << 3UL))) | \ + (((u32IsOddCh << PWM_PDMACTL_CHSEL0_1_Pos) | (u32RisingFirst << PWM_PDMACTL_CAPORD0_1_Pos) | \ + u32Mode | PWM_PDMACTL_CHEN0_1_Msk) << ((u32ChannelNum >> 1UL) << 3UL)); +} + +/** + * @brief Disables PDMA transfer of selected channel for PWM capture + * @param[in] pwm The pointer of the specified PWM module + * - PWM0 : PWM Group 0 + * - PWM1 : PWM Group 1 + * @param[in] u32ChannelNum PWM channel number. + * @return None + * @details This function is used to enable PDMA transfer of selected channel(s) for PWM capture. + */ +void PWM_DisablePDMA(PWM_T *pwm, uint32_t u32ChannelNum) +{ + (pwm)->PDMACTL &= ~(PWM_PDMACTL_CHEN0_1_Msk << ((u32ChannelNum >> 1UL) << 3UL)); +} + +/*@}*/ /* end of group PWM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group PWM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_qspi.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_qspi.c new file mode 100644 index 00000000000..c7614285a3c --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_qspi.c @@ -0,0 +1,812 @@ +/**************************************************************************//** + * @file qspi.c + * @version V0.10 + * @brief M251 series QSPI driver source file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup QSPI_Driver QSPI Driver + @{ +*/ + + +/** @addtogroup QSPI_EXPORTED_FUNCTIONS QSPI Exported Functions + @{ +*/ + +/** + * @brief This function make QSPI module be ready to transfer. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32MasterSlave Decides the QSPI module is operating in master mode or in slave mode. (QSPI_SLAVE, QSPI_MASTER) + * @param[in] u32QSPIMode Decides the transfer timing. (QSPI_MODE_0, QSPI_MODE_1, QSPI_MODE_2, QSPI_MODE_3) + * @param[in] u32DataWidth Decides the data width of a QSPI transaction. + * @param[in] u32BusClock The expected frequency of QSPI bus clock in Hz. + * @return Actual frequency of QSPI peripheral clock. + * @details By default, the QSPI transfer sequence is MSB first, the slave selection signal is active low and the automatic + * slave selection function is disabled. + * In Slave mode, the u32BusClock shall be NULL and the QSPI clock divider setting will be 0. + * The actual clock rate may be different from the target QSPI clock rate. + * For example, if the QSPI source clock rate is 12 MHz and the target QSPI bus clock rate is 7 MHz, the + * actual QSPI clock rate will be 6MHz. + * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value. + * @note If u32BusClock >= system clock frequency, QSPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0. + * @note If u32BusClock >= QSPI peripheral clock source, DIVIDER will be set to 0. + * @note In slave mode, the QSPI peripheral clock rate will be equal to APB clock rate. + */ +uint32_t QSPI_Open(QSPI_T *qspi, + uint32_t u32MasterSlave, + uint32_t u32QSPIMode, + uint32_t u32DataWidth, + uint32_t u32BusClock) +{ + uint32_t u32ClkSrc = 0UL, u32Div, u32HCLKFreq, u32RetValue = 0UL; + + if (u32DataWidth == 32UL) + { + u32DataWidth = 0UL; + } + + /* Get system clock frequency */ + u32HCLKFreq = CLK_GetHCLKFreq(); + + if (u32MasterSlave == QSPI_MASTER) + { + /* Default setting: slave selection signal is active low; disable automatic slave selection function. */ + qspi->SSCTL = QSPI_SS_ACTIVE_LOW; + + /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */ + qspi->CTL = u32MasterSlave | (u32DataWidth << QSPI_CTL_DWIDTH_Pos) | (u32QSPIMode) | QSPI_CTL_QSPIEN_Msk; + + if (u32BusClock >= u32HCLKFreq) + { + /* Select PCLK as the clock source of QSPI */ + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0; + } + + /* Check clock source of QSPI */ + if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PCLK0) + { + /* Clock source is PCLK0 */ + u32ClkSrc = CLK_GetPCLK0Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + + if (u32BusClock >= u32HCLKFreq) + { + /* Set DIVIDER = 0 */ + qspi->CLKDIV = 0UL; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if (u32BusClock >= u32ClkSrc) + { + /* Set DIVIDER = 0 */ + qspi->CLKDIV = 0UL; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if (u32BusClock == 0UL) + { + /* Set DIVIDER to the maximum value 0x1FF. f_qspi = f_qspi_clk_src / (DIVIDER + 1) */ + qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL)); + } + else + { + u32Div = (((u32ClkSrc * 10UL) / u32BusClock + 5UL) / 10UL) - 1UL; /* Round to the nearest integer */ + + if (u32Div > 0x1FFUL) + { + u32Div = 0x1FFUL; + qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL)); + } + else + { + qspi->CLKDIV = (qspi->CLKDIV & (~QSPI_CLKDIV_DIVIDER_Msk)) | (u32Div << QSPI_CLKDIV_DIVIDER_Pos); + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (u32Div + 1UL)); + } + } + } + else /* For slave mode, force the QSPI peripheral clock rate to equal APB clock rate. */ + { + /* Default setting: slave selection signal is low level active. */ + qspi->SSCTL = QSPI_SS_ACTIVE_LOW; + + /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */ + qspi->CTL = u32MasterSlave | (u32DataWidth << QSPI_CTL_DWIDTH_Pos) | (u32QSPIMode) | QSPI_CTL_QSPIEN_Msk; + + /* Set DIVIDER = 0 */ + qspi->CLKDIV = 0UL; + + /* Select PCLK as the clock source of QSPI */ + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0; + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK0Freq(); + } + + return u32RetValue; +} + +/** + * @brief Disable QSPI controller. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None + * @details This function will reset QSPI controller. + */ +void QSPI_Close(QSPI_T *qspi) +{ + /* Reset QSPI */ + SYS->IPRST1 |= SYS_IPRST1_QSPI0RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_QSPI0RST_Msk; +} + +/** + * @brief Clear RX FIFO buffer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None + * @details This function will clear QSPI RX FIFO buffer. The RXEMPTY (QSPI_STATUS[8]) will be set to 1. + */ +void QSPI_ClearRxFIFO(QSPI_T *qspi) +{ + qspi->FIFOCTL |= QSPI_FIFOCTL_RXFBCLR_Msk; +} + +/** + * @brief Clear TX FIFO buffer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None + * @details This function will clear QSPI TX FIFO buffer. The TXEMPTY (QSPI_STATUS[16]) will be set to 1. + * @note The TX shift register will not be cleared. + */ +void QSPI_ClearTxFIFO(QSPI_T *qspi) +{ + qspi->FIFOCTL |= QSPI_FIFOCTL_TXFBCLR_Msk; +} + +/** + * @brief Disable the automatic slave selection function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None + * @details This function will disable the automatic slave selection function and set slave selection signal to inactive state. + */ +void QSPI_DisableAutoSS(QSPI_T *qspi) +{ + qspi->SSCTL &= ~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SS_Msk); +} + +/** + * @brief Enable the automatic slave selection function. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32SSPinMask Specifies slave selection pins. (QSPI_SS) + * @param[in] u32ActiveLevel Specifies the active level of slave selection signal. (QSPI_SS_ACTIVE_HIGH, QSPI_SS_ACTIVE_LOW) + * @return None + * @details This function will enable the automatic slave selection function. Only available in Master mode. + * The slave selection pin and the active level will be set in this function. + */ +void QSPI_EnableAutoSS(QSPI_T *qspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel) +{ + qspi->SSCTL = (qspi->SSCTL & (~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SSACTPOL_Msk | QSPI_SSCTL_SS_Msk))) | (u32SSPinMask | u32ActiveLevel | QSPI_SSCTL_AUTOSS_Msk); +} + +/** + * @brief Set the QSPI bus clock. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32BusClock The expected frequency of QSPI bus clock in Hz. + * @return Actual frequency of QSPI bus clock. + * @details This function is only available in Master mode. The actual clock rate may be different from the target QSPI bus clock rate. + * For example, if the QSPI source clock rate is 12 MHz and the target QSPI bus clock rate is 7 MHz, the actual QSPI bus clock + * rate will be 6 MHz. + * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value. + * @note If u32BusClock >= system clock frequency, QSPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0. + * @note If u32BusClock >= QSPI peripheral clock source, DIVIDER will be set to 0. + */ +uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock) +{ + uint32_t u32ClkSrc, u32HCLKFreq; + uint32_t u32Div, u32RetValue; + + /* Get system clock frequency */ + u32HCLKFreq = CLK_GetHCLKFreq(); + + if (u32BusClock >= u32HCLKFreq) + { + /* Select PCLK as the clock source of QSPI */ + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0; + } + + /* Check clock source of SPI */ + if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PCLK0) + { + /* Clock source is PCLK0 */ + u32ClkSrc = CLK_GetPCLK0Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + + if (u32BusClock >= u32HCLKFreq) + { + /* Set DIVIDER = 0 */ + qspi->CLKDIV = 0UL; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if (u32BusClock >= u32ClkSrc) + { + /* Set DIVIDER = 0 */ + qspi->CLKDIV = 0UL; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if (u32BusClock == 0UL) + { + /* Set DIVIDER to the maximum value 0x1FF. f_qspi = f_qspi_clk_src / (DIVIDER + 1) */ + qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL)); + } + else + { + u32Div = (((u32ClkSrc * 10UL) / u32BusClock + 5UL) / 10UL) - 1UL; /* Round to the nearest integer */ + + if (u32Div > 0x1FFUL) + { + u32Div = 0x1FFUL; + qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL)); + } + else + { + qspi->CLKDIV = (qspi->CLKDIV & (~QSPI_CLKDIV_DIVIDER_Msk)) | (u32Div << QSPI_CLKDIV_DIVIDER_Pos); + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (u32Div + 1UL)); + } + } + + return u32RetValue; +} + +/** + * @brief Configure FIFO threshold setting. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 3. + * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 3. + * @return None + * @details Set TX FIFO threshold and RX FIFO threshold configurations. + */ +void QSPI_SetFIFO(QSPI_T *qspi, uint32_t u32TxThreshold, uint32_t u32RxThreshold) +{ + qspi->FIFOCTL = (qspi->FIFOCTL & ~(QSPI_FIFOCTL_TXTH_Msk | QSPI_FIFOCTL_RXTH_Msk)) | + (u32TxThreshold << QSPI_FIFOCTL_TXTH_Pos) | + (u32RxThreshold << QSPI_FIFOCTL_RXTH_Pos); +} + +/** + * @brief Get the actual frequency of QSPI bus clock. Only available in Master mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return Actual QSPI bus clock frequency in Hz. + * @details This function will calculate the actual QSPI bus clock rate according to the QSPInSEL and DIVIDER settings. Only available in Master mode. + */ +uint32_t QSPI_GetBusClock(QSPI_T *qspi) +{ + uint32_t u32Div; + uint32_t u32ClkSrc; + + /* Get DIVIDER setting */ + u32Div = (qspi->CLKDIV & QSPI_CLKDIV_DIVIDER_Msk) >> QSPI_CLKDIV_DIVIDER_Pos; + + /* Check clock source of QSPI */ + if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if ((CLK->CLKSEL2 & CLK_CLKSEL2_QSPI0SEL_Msk) == CLK_CLKSEL2_QSPI0SEL_PCLK0) + { + /* Clock source is PCLK0 */ + u32ClkSrc = CLK_GetPCLK0Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + + /* Return QSPI bus clock rate */ + return (u32ClkSrc / (u32Div + 1UL)); +} + +/** + * @brief Enable interrupt function. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be enabled. It is combination of: + * - \ref QSPI_UNIT_INT_MASK + * - \ref QSPI_SSACT_INT_MASK + * - \ref QSPI_SSINACT_INT_MASK + * - \ref QSPI_SLVUR_INT_MASK + * - \ref QSPI_SLVBE_INT_MASK + * - \ref QSPI_SLVTO_INT_MASK + * - \ref QSPI_TXUF_INT_MASK + * - \ref QSPI_FIFO_TXTH_INT_MASK + * - \ref QSPI_FIFO_RXTH_INT_MASK + * - \ref QSPI_FIFO_RXOV_INT_MASK + * - \ref QSPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Enable QSPI related interrupts specified by u32Mask parameter. + */ +void QSPI_EnableInt(QSPI_T *qspi, uint32_t u32Mask) +{ + /* Enable unit transfer interrupt flag */ + if ((u32Mask & QSPI_UNIT_INT_MASK) == QSPI_UNIT_INT_MASK) + { + qspi->CTL |= QSPI_CTL_UNITIEN_Msk; + } + + /* Enable slave selection signal active interrupt flag */ + if ((u32Mask & QSPI_SSACT_INT_MASK) == QSPI_SSACT_INT_MASK) + { + qspi->SSCTL |= QSPI_SSCTL_SSACTIEN_Msk; + } + + /* Enable slave selection signal inactive interrupt flag */ + if ((u32Mask & QSPI_SSINACT_INT_MASK) == QSPI_SSINACT_INT_MASK) + { + qspi->SSCTL |= QSPI_SSCTL_SSINAIEN_Msk; + } + + /* Enable slave TX under run interrupt flag */ + if ((u32Mask & QSPI_SLVUR_INT_MASK) == QSPI_SLVUR_INT_MASK) + { + qspi->SSCTL |= QSPI_SSCTL_SLVURIEN_Msk; + } + + /* Enable slave bit count error interrupt flag */ + if ((u32Mask & QSPI_SLVBE_INT_MASK) == QSPI_SLVBE_INT_MASK) + { + qspi->SSCTL |= QSPI_SSCTL_SLVBEIEN_Msk; + } + + /* Enable slave mode time-out interrupt flag */ + if ((u32Mask & QSPI_SLVTO_INT_MASK) == QSPI_SLVTO_INT_MASK) + { + qspi->SSCTL |= QSPI_SSCTL_SLVTOIEN_Msk; + } + + /* Enable slave TX underflow interrupt flag */ + if ((u32Mask & QSPI_TXUF_INT_MASK) == QSPI_TXUF_INT_MASK) + { + qspi->FIFOCTL |= QSPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Enable TX threshold interrupt flag */ + if ((u32Mask & QSPI_FIFO_TXTH_INT_MASK) == QSPI_FIFO_TXTH_INT_MASK) + { + qspi->FIFOCTL |= QSPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Enable RX threshold interrupt flag */ + if ((u32Mask & QSPI_FIFO_RXTH_INT_MASK) == QSPI_FIFO_RXTH_INT_MASK) + { + qspi->FIFOCTL |= QSPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Enable RX overrun interrupt flag */ + if ((u32Mask & QSPI_FIFO_RXOV_INT_MASK) == QSPI_FIFO_RXOV_INT_MASK) + { + qspi->FIFOCTL |= QSPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Enable RX time-out interrupt flag */ + if ((u32Mask & QSPI_FIFO_RXTO_INT_MASK) == QSPI_FIFO_RXTO_INT_MASK) + { + qspi->FIFOCTL |= QSPI_FIFOCTL_RXTOIEN_Msk; + } +} + +/** + * @brief Disable interrupt function. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * This parameter decides which interrupts will be disabled. It is combination of: + * - \ref QSPI_UNIT_INT_MASK + * - \ref QSPI_SSACT_INT_MASK + * - \ref QSPI_SSINACT_INT_MASK + * - \ref QSPI_SLVUR_INT_MASK + * - \ref QSPI_SLVBE_INT_MASK + * - \ref QSPI_SLVTO_INT_MASK + * - \ref QSPI_TXUF_INT_MASK + * - \ref QSPI_FIFO_TXTH_INT_MASK + * - \ref QSPI_FIFO_RXTH_INT_MASK + * - \ref QSPI_FIFO_RXOV_INT_MASK + * - \ref QSPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Disable QSPI related interrupts specified by u32Mask parameter. + */ +void QSPI_DisableInt(QSPI_T *qspi, uint32_t u32Mask) +{ + /* Disable unit transfer interrupt flag */ + if ((u32Mask & QSPI_UNIT_INT_MASK) == QSPI_UNIT_INT_MASK) + { + qspi->CTL &= ~QSPI_CTL_UNITIEN_Msk; + } + + /* Disable slave selection signal active interrupt flag */ + if ((u32Mask & QSPI_SSACT_INT_MASK) == QSPI_SSACT_INT_MASK) + { + qspi->SSCTL &= ~QSPI_SSCTL_SSACTIEN_Msk; + } + + /* Disable slave selection signal inactive interrupt flag */ + if ((u32Mask & QSPI_SSINACT_INT_MASK) == QSPI_SSINACT_INT_MASK) + { + qspi->SSCTL &= ~QSPI_SSCTL_SSINAIEN_Msk; + } + + /* Disable slave TX under run interrupt flag */ + if ((u32Mask & QSPI_SLVUR_INT_MASK) == QSPI_SLVUR_INT_MASK) + { + qspi->SSCTL &= ~QSPI_SSCTL_SLVURIEN_Msk; + } + + /* Disable slave bit count error interrupt flag */ + if ((u32Mask & QSPI_SLVBE_INT_MASK) == QSPI_SLVBE_INT_MASK) + { + qspi->SSCTL &= ~QSPI_SSCTL_SLVBEIEN_Msk; + } + + /* Disable slave mode time-out interrupt flag */ + if ((u32Mask & QSPI_SLVTO_INT_MASK) == QSPI_SLVTO_INT_MASK) + { + qspi->SSCTL &= ~QSPI_SSCTL_SLVTOIEN_Msk; + } + + /* Disable slave TX underflow interrupt flag */ + if ((u32Mask & QSPI_TXUF_INT_MASK) == QSPI_TXUF_INT_MASK) + { + qspi->FIFOCTL &= ~QSPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Disable TX threshold interrupt flag */ + if ((u32Mask & QSPI_FIFO_TXTH_INT_MASK) == QSPI_FIFO_TXTH_INT_MASK) + { + qspi->FIFOCTL &= ~QSPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Disable RX threshold interrupt flag */ + if ((u32Mask & QSPI_FIFO_RXTH_INT_MASK) == QSPI_FIFO_RXTH_INT_MASK) + { + qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Disable RX overrun interrupt flag */ + if ((u32Mask & QSPI_FIFO_RXOV_INT_MASK) == QSPI_FIFO_RXOV_INT_MASK) + { + qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Disable RX time-out interrupt flag */ + if ((u32Mask & QSPI_FIFO_RXTO_INT_MASK) == QSPI_FIFO_RXTO_INT_MASK) + { + qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXTOIEN_Msk; + } +} + +/** + * @brief Get interrupt flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be read. It is combination of: + * - \ref QSPI_UNIT_INT_MASK + * - \ref QSPI_SSACT_INT_MASK + * - \ref QSPI_SSINACT_INT_MASK + * - \ref QSPI_SLVUR_INT_MASK + * - \ref QSPI_SLVBE_INT_MASK + * - \ref QSPI_SLVTO_INT_MASK + * - \ref QSPI_TXUF_INT_MASK + * - \ref QSPI_FIFO_TXTH_INT_MASK + * - \ref QSPI_FIFO_RXTH_INT_MASK + * - \ref QSPI_FIFO_RXOV_INT_MASK + * - \ref QSPI_FIFO_RXTO_INT_MASK + * + * @return Interrupt flags of selected sources. + * @details Get QSPI related interrupt flags specified by u32Mask parameter. + */ +uint32_t QSPI_GetIntFlag(QSPI_T *qspi, uint32_t u32Mask) +{ + uint32_t u32IntFlag = 0U, u32TmpVal; + + u32TmpVal = qspi->STATUS & QSPI_STATUS_UNITIF_Msk; + + /* Check unit transfer interrupt flag */ + if ((u32Mask & QSPI_UNIT_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_UNIT_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_SSACTIF_Msk; + + /* Check slave selection signal active interrupt flag */ + if ((u32Mask & QSPI_SSACT_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_SSACT_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_SSINAIF_Msk; + + /* Check slave selection signal inactive interrupt flag */ + if ((u32Mask & QSPI_SSINACT_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_SSINACT_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_SLVURIF_Msk; + + /* Check slave TX under run interrupt flag */ + if ((u32Mask & QSPI_SLVUR_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_SLVUR_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_SLVBEIF_Msk; + + /* Check slave bit count error interrupt flag */ + if ((u32Mask & QSPI_SLVBE_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_SLVBE_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_SLVTOIF_Msk; + + /* Check slave mode time-out interrupt flag */ + if ((u32Mask & QSPI_SLVTO_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_SLVTO_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_TXUFIF_Msk; + + /* Check slave TX underflow interrupt flag */ + if ((u32Mask & QSPI_TXUF_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_TXUF_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_TXTHIF_Msk; + + /* Check TX threshold interrupt flag */ + if ((u32Mask & QSPI_FIFO_TXTH_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_FIFO_TXTH_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_RXTHIF_Msk; + + /* Check RX threshold interrupt flag */ + if ((u32Mask & QSPI_FIFO_RXTH_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_FIFO_RXTH_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_RXOVIF_Msk; + + /* Check RX overrun interrupt flag */ + if ((u32Mask & QSPI_FIFO_RXOV_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_FIFO_RXOV_INT_MASK; + } + + u32TmpVal = qspi->STATUS & QSPI_STATUS_RXTOIF_Msk; + + /* Check RX time-out interrupt flag */ + if ((u32Mask & QSPI_FIFO_RXTO_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= QSPI_FIFO_RXTO_INT_MASK; + } + + return u32IntFlag; +} + +/** + * @brief Clear interrupt flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. It could be the combination of: + * - \ref QSPI_UNIT_INT_MASK + * - \ref QSPI_SSACT_INT_MASK + * - \ref QSPI_SSINACT_INT_MASK + * - \ref QSPI_SLVUR_INT_MASK + * - \ref QSPI_SLVBE_INT_MASK + * - \ref QSPI_SLVTO_INT_MASK + * - \ref QSPI_TXUF_INT_MASK + * - \ref QSPI_FIFO_RXOV_INT_MASK + * - \ref QSPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Clear QSPI related interrupt flags specified by u32Mask parameter. + */ +void QSPI_ClearIntFlag(QSPI_T *qspi, uint32_t u32Mask) +{ + if (u32Mask & QSPI_UNIT_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_UNITIF_Msk; /* Clear unit transfer interrupt flag */ + } + + if (u32Mask & QSPI_SSACT_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_SSACTIF_Msk; /* Clear slave selection signal active interrupt flag */ + } + + if (u32Mask & QSPI_SSINACT_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_SSINAIF_Msk; /* Clear slave selection signal inactive interrupt flag */ + } + + if (u32Mask & QSPI_SLVUR_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_SLVURIF_Msk; /* Clear slave TX under run interrupt flag */ + } + + if (u32Mask & QSPI_SLVBE_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_SLVBEIF_Msk; /* Clear slave bit count error interrupt flag */ + } + + if (u32Mask & QSPI_SLVTO_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_SLVTOIF_Msk; /* Clear slave mode time-out interrupt flag */ + } + + if (u32Mask & QSPI_TXUF_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_TXUFIF_Msk; /* Clear slave TX underflow interrupt flag */ + } + + if (u32Mask & QSPI_FIFO_RXOV_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_RXOVIF_Msk; /* Clear RX overrun interrupt flag */ + } + + if (u32Mask & QSPI_FIFO_RXTO_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_RXTOIF_Msk; /* Clear RX time-out interrupt flag */ + } +} + +/** + * @brief Get QSPI status. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related sources. + * Each bit corresponds to a source. + * This parameter decides which flags will be read. It is combination of: + * - \ref QSPI_BUSY_MASK + * - \ref QSPI_RX_EMPTY_MASK + * - \ref QSPI_RX_FULL_MASK + * - \ref QSPI_TX_EMPTY_MASK + * - \ref QSPI_TX_FULL_MASK + * - \ref QSPI_TXRX_RESET_MASK + * - \ref QSPI_QSPIEN_STS_MASK + * - \ref QSPI_SSLINE_STS_MASK + * + * @return Flags of selected sources. + * @details Get QSPI related status specified by u32Mask parameter. + */ +uint32_t QSPI_GetStatus(QSPI_T *qspi, uint32_t u32Mask) +{ + uint32_t u32Flag = 0UL, u32TmpValue; + + u32TmpValue = qspi->STATUS & QSPI_STATUS_BUSY_Msk; + + /* Check busy status */ + if ((u32Mask & QSPI_BUSY_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_BUSY_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_RXEMPTY_Msk; + + /* Check RX empty flag */ + if ((u32Mask & QSPI_RX_EMPTY_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_RX_EMPTY_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_RXFULL_Msk; + + /* Check RX full flag */ + if ((u32Mask & QSPI_RX_FULL_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_RX_FULL_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_TXEMPTY_Msk; + + /* Check TX empty flag */ + if ((u32Mask & QSPI_TX_EMPTY_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_TX_EMPTY_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_TXFULL_Msk; + + /* Check TX full flag */ + if ((u32Mask & QSPI_TX_FULL_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_TX_FULL_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_TXRXRST_Msk; + + /* Check TX/RX reset flag */ + if ((u32Mask & QSPI_TXRX_RESET_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_TXRX_RESET_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_QSPIENSTS_Msk; + + /* Check QSPIEN flag */ + if ((u32Mask & QSPI_QSPIEN_STS_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_QSPIEN_STS_MASK; + } + + u32TmpValue = qspi->STATUS & QSPI_STATUS_SSLINE_Msk; + + /* Check QSPIx_SS line status */ + if ((u32Mask & QSPI_SSLINE_STS_MASK) && (u32TmpValue)) + { + u32Flag |= QSPI_SSLINE_STS_MASK; + } + + return u32Flag; +} + + + +/*@}*/ /* end of group QSPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group QSPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_rtc.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_rtc.c new file mode 100644 index 00000000000..240639571ad --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_rtc.c @@ -0,0 +1,893 @@ +/**************************************************************************** + * @file rtc.c + * @version V1.00 + * @brief M251 series CLK driver source file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include "NuMicro.h" + + +/** @cond HIDDEN_SYMBOLS */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Macro, type and constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_GLOBALS + +/*---------------------------------------------------------------------------------------------------------*/ +/* Global file scope (static) variables */ +/*---------------------------------------------------------------------------------------------------------*/ +static volatile uint32_t g_u32HiYear, g_u32LoYear, g_u32HiMonth, g_u32LoMonth, g_u32HiDay, g_u32LoDay; +static volatile uint32_t g_u32HiHour, g_u32LoHour, g_u32HiMin, g_u32LoMin, g_u32HiSec, g_u32LoSec; + +/** @endcond HIDDEN_SYMBOLS */ + + + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup RTC_Driver RTC Driver + @{ +*/ + +/** @addtogroup RTC_EXPORTED_FUNCTIONS RTC Exported Functions + @{ +*/ + +/** + * @brief Initialize RTC module and start counting + * + * @param[in] psPt Specify the time property and current date and time. It includes: \n + * u32Year: Year value, range between 2000 ~ 2099. \n + * u32Month: Month value, range between 1 ~ 12. \n + * u32Day: Day value, range between 1 ~ 31. \n + * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY / + * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY / + * RTC_SATURDAY] \n + * u32Hour: Hour value, range between 0 ~ 23. \n + * u32Minute: Minute value, range between 0 ~ 59. \n + * u32Second: Second value, range between 0 ~ 59. \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This function is used to: \n + * 1. Write initial key to let RTC start count. \n + * 2. Input parameter indicates start date/time. \n + * 3. User has to make sure that parameters of RTC date/time are reasonable. \n + * @note Null pointer for using default starting date/time. + */ +void RTC_Open(S_RTC_TIME_DATA_T *psPt) +{ + RTC->INIT = RTC_INIT_KEY; + + if (RTC->INIT != RTC_INIT_ACTIVE_Msk) + { + RTC->INIT = RTC_INIT_KEY; + + while (RTC->INIT != RTC_INIT_ACTIVE_Msk) + { + } + } + + if (psPt == 0) + { + /* No RTC date/time data */ + } + else + { + /* Set RTC date and time */ + RTC_SetDateAndTime(psPt); + } +} + +/** + * @brief Disable RTC Clock + * + * @param None + * + * @return None + * + * @details This API will disable RTC peripheral clock and stops RTC counting. + */ +void RTC_Close(void) +{ + CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk; +} + +/** + * @brief Set Frequency Compensation Data + * + * @param[in] i32FrequencyX10000 Specify the RTC clock X 10000, ex: 327736512 means 32773.6512. + * + * @return None + * + */ +void RTC_32KCalibration(int32_t i32FrequencyX10000) +{ + + /* + Frequency counter measurement : 32773.6512 Hz + */ + uint32_t u32Index; + uint32_t u32Compensate; + + /* 327736512 %10000 = 6512 */ + u32Compensate = (uint32_t)(i32FrequencyX10000 % 10000); + /*Fraction Part: (6512 X 64)/10000 = 41.6768(0x2A) => RTC_FREQADJ[5:0]=0x2A*/ + u32Compensate = ((u32Compensate * 64) / 10000); + u32Compensate &= 0x3F; + /* + Formula for 32K compensation is + FREQADJ = 0~0x00001F00 (Frequency range : 32752Hz ~ 32783Hz) + */ + + if (i32FrequencyX10000 >= (uint32_t)327840000) + { + u32Compensate = 0x1F3F; + } + else if (i32FrequencyX10000 < (uint32_t)327520000) + { + u32Compensate = 0x0; + } + else + { + /* Integer Part: 32773 => RTC_FREQADJ[12:8] = 0x15 */ + for (u32Index = 0; u32Index < 0x20 ; u32Index++) + { + if ((i32FrequencyX10000 >= 327520000 + (u32Index * 10000)) && (i32FrequencyX10000 < 327520000 + ((u32Index + 1) * 10000))) + { + u32Compensate += (u32Index << RTC_FREQADJ_INTEGER_Pos); + break; + } + } + } + + + RTC->FREQADJ = (uint32_t)u32Compensate; +} + +/** + * @brief Get Current RTC Date and Time + * + * @param[out] psPt The returned pointer is specified the current RTC value. It includes: \n + * u32Year: Year value \n + * u32Month: Month value \n + * u32Day: Day value \n + * u32DayOfWeek: Day of week \n + * u32Hour: Hour value \n + * u32Minute: Minute value \n + * u32Second: Second value \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This API is used to get the current RTC date and time value. + */ +void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *psPt) +{ + uint32_t u32Tmp; + + psPt->u32TimeScale = RTC->CLKFMT & RTC_CLKFMT_24HEN_Msk; /* 12/24-hour */ + psPt->u32DayOfWeek = RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk; /* Day of the week */ + + /* Get [Date digit] data */ + g_u32HiYear = (RTC->CAL & RTC_CAL_TENYEAR_Msk) >> RTC_CAL_TENYEAR_Pos; + g_u32LoYear = (RTC->CAL & RTC_CAL_YEAR_Msk) >> RTC_CAL_YEAR_Pos; + g_u32HiMonth = (RTC->CAL & RTC_CAL_TENMON_Msk) >> RTC_CAL_TENMON_Pos; + g_u32LoMonth = (RTC->CAL & RTC_CAL_MON_Msk) >> RTC_CAL_MON_Pos; + g_u32HiDay = (RTC->CAL & RTC_CAL_TENDAY_Msk) >> RTC_CAL_TENDAY_Pos; + g_u32LoDay = (RTC->CAL & RTC_CAL_DAY_Msk) >> RTC_CAL_DAY_Pos; + + /* Get [Time digit] data */ + g_u32HiHour = (RTC->TIME & RTC_TIME_TENHR_Msk) >> RTC_TIME_TENHR_Pos; + g_u32LoHour = (RTC->TIME & RTC_TIME_HR_Msk) >> RTC_TIME_HR_Pos; + g_u32HiMin = (RTC->TIME & RTC_TIME_TENMIN_Msk) >> RTC_TIME_TENMIN_Pos; + g_u32LoMin = (RTC->TIME & RTC_TIME_MIN_Msk) >> RTC_TIME_MIN_Pos; + g_u32HiSec = (RTC->TIME & RTC_TIME_TENSEC_Msk) >> RTC_TIME_TENSEC_Pos; + g_u32LoSec = (RTC->TIME & RTC_TIME_SEC_Msk) >> RTC_TIME_SEC_Pos; + + /* Compute to 20XX year */ + u32Tmp = (g_u32HiYear * 10ul); + u32Tmp += g_u32LoYear; + psPt->u32Year = u32Tmp + RTC_YEAR2000; + + /* Compute 0~12 month */ + u32Tmp = (g_u32HiMonth * 10ul); + psPt->u32Month = u32Tmp + g_u32LoMonth; + + /* Compute 0~31 day */ + u32Tmp = (g_u32HiDay * 10ul); + psPt->u32Day = u32Tmp + g_u32LoDay; + + /* Compute 12/24 hour */ + if (psPt->u32TimeScale == RTC_CLOCK_12) + { + u32Tmp = (g_u32HiHour * 10ul); + u32Tmp += g_u32LoHour; + psPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */ + + if (psPt->u32Hour >= 21ul) + { + psPt->u32AmPm = RTC_PM; + psPt->u32Hour -= 20ul; + } + else + { + psPt->u32AmPm = RTC_AM; + } + + u32Tmp = (g_u32HiMin * 10ul); + u32Tmp += g_u32LoMin; + psPt->u32Minute = u32Tmp; + + u32Tmp = (g_u32HiSec * 10ul); + u32Tmp += g_u32LoSec; + psPt->u32Second = u32Tmp; + } + else + { + u32Tmp = (g_u32HiHour * 10ul); + u32Tmp += g_u32LoHour; + psPt->u32Hour = u32Tmp; + + u32Tmp = (g_u32HiMin * 10ul); + u32Tmp += g_u32LoMin; + psPt->u32Minute = u32Tmp; + + u32Tmp = (g_u32HiSec * 10ul); + u32Tmp += g_u32LoSec; + psPt->u32Second = u32Tmp; + } +} + +/** + * @brief Get RTC Alarm Date and Time + * + * @param[out] psPt The returned pointer is specified the RTC alarm value. It includes: \n + * u32Year: Year value \n + * u32Month: Month value \n + * u32Day: Day value \n + * u32DayOfWeek: Day of week \n + * u32Hour: Hour value \n + * u32Minute: Minute value \n + * u32Second: Second value \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This API is used to get the RTC alarm date and time setting. + */ +void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *psPt) +{ + uint32_t u32Tmp; + + psPt->u32TimeScale = RTC->CLKFMT & RTC_CLKFMT_24HEN_Msk; /* 12/24-hour */ + psPt->u32DayOfWeek = RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk; /* Day of the week */ + + /* Get alarm [Date digit] data */ + g_u32HiYear = (RTC->CALM & RTC_CALM_TENYEAR_Msk) >> RTC_CALM_TENYEAR_Pos; + g_u32LoYear = (RTC->CALM & RTC_CALM_YEAR_Msk) >> RTC_CALM_YEAR_Pos; + g_u32HiMonth = (RTC->CALM & RTC_CALM_TENMON_Msk) >> RTC_CALM_TENMON_Pos; + g_u32LoMonth = (RTC->CALM & RTC_CALM_MON_Msk) >> RTC_CALM_MON_Pos; + g_u32HiDay = (RTC->CALM & RTC_CALM_TENDAY_Msk) >> RTC_CALM_TENDAY_Pos; + g_u32LoDay = (RTC->CALM & RTC_CALM_DAY_Msk) >> RTC_CALM_DAY_Pos; + + /* Get alarm [Time digit] data */ + g_u32HiHour = (RTC->TALM & RTC_TALM_TENHR_Msk) >> RTC_TALM_TENHR_Pos; + g_u32LoHour = (RTC->TALM & RTC_TALM_HR_Msk) >> RTC_TALM_HR_Pos; + g_u32HiMin = (RTC->TALM & RTC_TALM_TENMIN_Msk) >> RTC_TALM_TENMIN_Pos; + g_u32LoMin = (RTC->TALM & RTC_TALM_MIN_Msk) >> RTC_TALM_MIN_Pos; + g_u32HiSec = (RTC->TALM & RTC_TALM_TENSEC_Msk) >> RTC_TALM_TENSEC_Pos; + g_u32LoSec = (RTC->TALM & RTC_TALM_SEC_Msk) >> RTC_TALM_SEC_Pos; + + /* Compute to 20XX year */ + u32Tmp = (g_u32HiYear * 10ul); + u32Tmp += g_u32LoYear; + psPt->u32Year = u32Tmp + RTC_YEAR2000; + + /* Compute 0~12 month */ + u32Tmp = (g_u32HiMonth * 10ul); + psPt->u32Month = u32Tmp + g_u32LoMonth; + + /* Compute 0~31 day */ + u32Tmp = (g_u32HiDay * 10ul); + psPt->u32Day = u32Tmp + g_u32LoDay; + + /* Compute 12/24 hour */ + if (psPt->u32TimeScale == RTC_CLOCK_12) + { + u32Tmp = (g_u32HiHour * 10ul); + u32Tmp += g_u32LoHour; + psPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */ + + if (psPt->u32Hour >= 21ul) + { + psPt->u32AmPm = RTC_PM; + psPt->u32Hour -= 20ul; + } + else + { + psPt->u32AmPm = RTC_AM; + } + + u32Tmp = (g_u32HiMin * 10ul); + u32Tmp += g_u32LoMin; + psPt->u32Minute = u32Tmp; + + u32Tmp = (g_u32HiSec * 10ul); + u32Tmp += g_u32LoSec; + psPt->u32Second = u32Tmp; + + } + else + { + u32Tmp = (g_u32HiHour * 10ul); + u32Tmp += g_u32LoHour; + psPt->u32Hour = u32Tmp; + + u32Tmp = (g_u32HiMin * 10ul); + u32Tmp += g_u32LoMin; + psPt->u32Minute = u32Tmp; + + u32Tmp = (g_u32HiSec * 10ul); + u32Tmp += g_u32LoSec; + psPt->u32Second = u32Tmp; + } +} + +/** + * @brief Update Current RTC Date and Time + * + * @param[in] psPt Specify the time property and current date and time. It includes: \n + * u32Year: Year value, range between 2000 ~ 2099. \n + * u32Month: Month value, range between 1 ~ 12. \n + * u32Day: Day value, range between 1 ~ 31. \n + * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY / + * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY / + * RTC_SATURDAY] \n + * u32Hour: Hour value, range between 0 ~ 23. \n + * u32Minute: Minute value, range between 0 ~ 59. \n + * u32Second: Second value, range between 0 ~ 59. \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This API is used to update current date and time to RTC. + */ +void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *psPt) +{ + uint32_t u32RegCAL, u32RegTIME; + + if (psPt == 0ul) + { + /* No RTC date/time data */ + } + else + { + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC 24/12 hour setting and Day of the Week */ + /*-----------------------------------------------------------------------------------------------------*/ + + if (psPt->u32TimeScale == RTC_CLOCK_12) + { + RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk; + + /*-------------------------------------------------------------------------------------------------*/ + /* Important, range of 12-hour PM mode is 21 up to 32 */ + /*-------------------------------------------------------------------------------------------------*/ + if (psPt->u32AmPm == RTC_PM) + { + psPt->u32Hour += 20ul; + } + } + else + { + RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk; + } + + /* Set Day of the Week */ + RTC->WEEKDAY = psPt->u32DayOfWeek; + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC Current Date and Time */ + /*-----------------------------------------------------------------------------------------------------*/ + u32RegCAL = ((psPt->u32Year - RTC_YEAR2000) / 10ul) << 20; + u32RegCAL |= (((psPt->u32Year - RTC_YEAR2000) % 10ul) << 16); + u32RegCAL |= ((psPt->u32Month / 10ul) << 12); + u32RegCAL |= ((psPt->u32Month % 10ul) << 8); + u32RegCAL |= ((psPt->u32Day / 10ul) << 4); + u32RegCAL |= (psPt->u32Day % 10ul); + + u32RegTIME = ((psPt->u32Hour / 10ul) << 20); + u32RegTIME |= ((psPt->u32Hour % 10ul) << 16); + u32RegTIME |= ((psPt->u32Minute / 10ul) << 12); + u32RegTIME |= ((psPt->u32Minute % 10ul) << 8); + u32RegTIME |= ((psPt->u32Second / 10ul) << 4); + u32RegTIME |= (psPt->u32Second % 10ul); + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC Calender and Time Loading */ + /*-----------------------------------------------------------------------------------------------------*/ + + RTC->CAL = (uint32_t)u32RegCAL; + RTC->TIME = (uint32_t)u32RegTIME; + } +} + +/** + * @brief Update RTC Alarm Date and Time + * + * @param[in] psPt Specify the time property and alarm date and time. It includes: \n + * u32Year: Year value, range between 2000 ~ 2099. \n + * u32Month: Month value, range between 1 ~ 12. \n + * u32Day: Day value, range between 1 ~ 31. \n + * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY / + * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY / + * RTC_SATURDAY] \n + * u32Hour: Hour value, range between 0 ~ 23. \n + * u32Minute: Minute value, range between 0 ~ 59. \n + * u32Second: Second value, range between 0 ~ 59. \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This API is used to update alarm date and time setting to RTC. + */ +void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *psPt) +{ + uint32_t u32RegCALM, u32RegTALM; + + if (psPt == 0) + { + /* No RTC date/time data */ + } + else + { + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC 24/12 hour setting and Day of the Week */ + /*-----------------------------------------------------------------------------------------------------*/ + + if (psPt->u32TimeScale == RTC_CLOCK_12) + { + RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk; + + /*-------------------------------------------------------------------------------------------------*/ + /* Important, range of 12-hour PM mode is 21 up to 32 */ + /*-------------------------------------------------------------------------------------------------*/ + if (psPt->u32AmPm == RTC_PM) + { + psPt->u32Hour += 20ul; + } + } + else + { + RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk; + } + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC Alarm Date and Time */ + /*-----------------------------------------------------------------------------------------------------*/ + u32RegCALM = ((psPt->u32Year - RTC_YEAR2000) / 10ul) << 20; + u32RegCALM |= (((psPt->u32Year - RTC_YEAR2000) % 10ul) << 16); + u32RegCALM |= ((psPt->u32Month / 10ul) << 12); + u32RegCALM |= ((psPt->u32Month % 10ul) << 8); + u32RegCALM |= ((psPt->u32Day / 10ul) << 4); + u32RegCALM |= (psPt->u32Day % 10ul); + + u32RegTALM = ((psPt->u32Hour / 10ul) << 20); + u32RegTALM |= ((psPt->u32Hour % 10ul) << 16); + u32RegTALM |= ((psPt->u32Minute / 10ul) << 12); + u32RegTALM |= ((psPt->u32Minute % 10ul) << 8); + u32RegTALM |= ((psPt->u32Second / 10ul) << 4); + u32RegTALM |= (psPt->u32Second % 10ul); + + + RTC->CALM = (uint32_t)u32RegCALM; + RTC->TALM = (uint32_t)u32RegTALM; + } +} + +/** + * @brief Update RTC Current Date + * + * @param[in] u32Year The year calendar digit of current RTC setting. + * @param[in] u32Month The month calendar digit of current RTC setting. + * @param[in] u32Day The day calendar digit of current RTC setting. + * @param[in] u32DayOfWeek The Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY / + * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY / + * RTC_SATURDAY] + * + * @return None + * + * @details This API is used to update current date to RTC. + */ +void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek) +{ + uint32_t u32RegCAL; + + u32RegCAL = ((u32Year - RTC_YEAR2000) / 10ul) << 20; + u32RegCAL |= (((u32Year - RTC_YEAR2000) % 10ul) << 16); + u32RegCAL |= ((u32Month / 10ul) << 12); + u32RegCAL |= ((u32Month % 10ul) << 8); + u32RegCAL |= ((u32Day / 10ul) << 4); + u32RegCAL |= (u32Day % 10ul); + + /* Set Day of the Week */ + RTC->WEEKDAY = u32DayOfWeek & RTC_WEEKDAY_WEEKDAY_Msk; + + /* Set RTC Calender Loading */ + RTC->CAL = (uint32_t)u32RegCAL; +} + +/** + * @brief Update RTC Current Time + * + * @param[in] u32Hour The hour time digit of current RTC setting. + * @param[in] u32Minute The minute time digit of current RTC setting. + * @param[in] u32Second The second time digit of current RTC setting. + * @param[in] u32TimeMode The 24-Hour / 12-Hour Time Scale Selection. [RTC_CLOCK_12 / RTC_CLOCK_24] + * @param[in] u32AmPm 12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [RTC_AM / RTC_PM] + * + * @return None + * + * @details This API is used to update current time to RTC. + */ +void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm) +{ + uint32_t u32RegTIME; + + /* Important, range of 12-hour PM mode is 21 up to 32 */ + if ((u32TimeMode == RTC_CLOCK_12) && (u32AmPm == RTC_PM)) + { + u32Hour += 20ul; + } + + u32RegTIME = ((u32Hour / 10ul) << 20); + u32RegTIME |= ((u32Hour % 10ul) << 16); + u32RegTIME |= ((u32Minute / 10ul) << 12); + u32RegTIME |= ((u32Minute % 10ul) << 8); + u32RegTIME |= ((u32Second / 10ul) << 4); + u32RegTIME |= (u32Second % 10ul); + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC 24/12 hour setting and Day of the Week */ + /*-----------------------------------------------------------------------------------------------------*/ + + if (u32TimeMode == RTC_CLOCK_12) + { + RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk; + } + else + { + RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk; + } + + RTC->TIME = (uint32_t)u32RegTIME; +} + +/** + * @brief Update RTC Alarm Date + * + * @param[in] u32Year The year calendar digit of RTC alarm setting. + * @param[in] u32Month The month calendar digit of RTC alarm setting. + * @param[in] u32Day The day calendar digit of RTC alarm setting. + * + * @return None + * + * @details This API is used to update alarm date setting to RTC. + */ +void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day) +{ + uint32_t u32RegCALM; + + u32RegCALM = ((u32Year - RTC_YEAR2000) / 10ul) << 20; + u32RegCALM |= (((u32Year - RTC_YEAR2000) % 10ul) << 16); + u32RegCALM |= ((u32Month / 10ul) << 12); + u32RegCALM |= ((u32Month % 10ul) << 8); + u32RegCALM |= ((u32Day / 10ul) << 4); + u32RegCALM |= (u32Day % 10ul); + + + /* Set RTC Alarm Date */ + RTC->CALM = (uint32_t)u32RegCALM; +} + +/** + * @brief Update RTC Alarm Time + * + * @param[in] u32Hour The hour time digit of RTC alarm setting. + * @param[in] u32Minute The minute time digit of RTC alarm setting. + * @param[in] u32Second The second time digit of RTC alarm setting. + * @param[in] u32TimeMode The 24-Hour / 12-Hour Time Scale Selection. [RTC_CLOCK_12 / RTC_CLOCK_24] + * @param[in] u32AmPm 12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [RTC_AM / RTC_PM] + * + * @return None + * + * @details This API is used to update alarm time setting to RTC. + */ +void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm) +{ + uint32_t u32RegTALM; + + /* Important, range of 12-hour PM mode is 21 up to 32 */ + if ((u32TimeMode == (uint32_t)RTC_CLOCK_12) && (u32AmPm == (uint32_t)RTC_PM)) + { + u32Hour += 20ul; + } + + u32RegTALM = ((u32Hour / 10ul) << 20); + u32RegTALM |= ((u32Hour % 10ul) << 16); + u32RegTALM |= ((u32Minute / 10ul) << 12); + u32RegTALM |= ((u32Minute % 10ul) << 8); + u32RegTALM |= ((u32Second / 10ul) << 4); + u32RegTALM |= (u32Second % 10ul); + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC 24/12 hour setting and Day of the Week */ + /*-----------------------------------------------------------------------------------------------------*/ + + if (u32TimeMode == (uint32_t)RTC_CLOCK_12) + { + RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk; + } + else + { + RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk; + } + + /* Set RTC Alarm Time */ + RTC->TALM = (uint32_t)u32RegTALM; +} + +/** + * @brief Set RTC Alarm Date Mask Function + * + * @param[in] u8IsTenYMsk 1: enable 10-Year digit alarm mask; 0: disabled. + * @param[in] u8IsYMsk 1: enable 1-Year digit alarm mask; 0: disabled. + * @param[in] u8IsTenMMsk 1: enable 10-Mon digit alarm mask; 0: disabled. + * @param[in] u8IsMMsk 1: enable 1-Mon digit alarm mask; 0: disabled. + * @param[in] u8IsTenDMsk 1: enable 10-Day digit alarm mask; 0: disabled. + * @param[in] u8IsDMsk 1: enable 1-Day digit alarm mask; 0: disabled. + * + * @return None + * + * @details This API is used to enable or disable RTC alarm date mask function. + */ +void RTC_SetAlarmDateMask(uint8_t u8IsTenYMsk, uint8_t u8IsYMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenDMsk, uint8_t u8IsDMsk) +{ + + RTC->CAMSK = ((uint32_t)u8IsTenYMsk << RTC_CAMSK_MTENYEAR_Pos) | + ((uint32_t)u8IsYMsk << RTC_CAMSK_MYEAR_Pos) | + ((uint32_t)u8IsTenMMsk << RTC_CAMSK_MTENMON_Pos) | + ((uint32_t)u8IsMMsk << RTC_CAMSK_MMON_Pos) | + ((uint32_t)u8IsTenDMsk << RTC_CAMSK_MTENDAY_Pos) | + ((uint32_t)u8IsDMsk << RTC_CAMSK_MDAY_Pos); +} + +/** + * @brief Set RTC Alarm Time Mask Function + * + * @param[in] u8IsTenHMsk 1: enable 10-Hour digit alarm mask; 0: disabled. + * @param[in] u8IsHMsk 1: enable 1-Hour digit alarm mask; 0: disabled. + * @param[in] u8IsTenMMsk 1: enable 10-Min digit alarm mask; 0: disabled. + * @param[in] u8IsMMsk 1: enable 1-Min digit alarm mask; 0: disabled. + * @param[in] u8IsTenSMsk 1: enable 10-Sec digit alarm mask; 0: disabled. + * @param[in] u8IsSMsk 1: enable 1-Sec digit alarm mask; 0: disabled. + * + * @return None + * + * @details This API is used to enable or disable RTC alarm time mask function. + */ +void RTC_SetAlarmTimeMask(uint8_t u8IsTenHMsk, uint8_t u8IsHMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenSMsk, uint8_t u8IsSMsk) +{ + + RTC->TAMSK = ((uint32_t)u8IsTenHMsk << RTC_TAMSK_MTENHR_Pos) | + ((uint32_t)u8IsHMsk << RTC_TAMSK_MHR_Pos) | + ((uint32_t)u8IsTenMMsk << RTC_TAMSK_MTENMIN_Pos) | + ((uint32_t)u8IsMMsk << RTC_TAMSK_MMIN_Pos) | + ((uint32_t)u8IsTenSMsk << RTC_TAMSK_MTENSEC_Pos) | + ((uint32_t)u8IsSMsk << RTC_TAMSK_MSEC_Pos); +} + +/** + * @brief Get Day of the Week + * + * @param None + * + * @retval 0 Sunday + * @retval 1 Monday + * @retval 2 Tuesday + * @retval 3 Wednesday + * @retval 4 Thursday + * @retval 5 Friday + * @retval 6 Saturday + * + * @details This API is used to get day of the week of current RTC date. + */ +uint32_t RTC_GetDayOfWeek(void) +{ + return (RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk); +} + +/** + * @brief Set RTC Tick Period Time + * + * @param[in] u32TickSelection It is used to set the RTC tick period time for Periodic Time Tick request. \n + * It consists of: + * - \ref RTC_TICK_1_SEC : Time tick is 1 second + * - \ref RTC_TICK_1_2_SEC : Time tick is 1/2 second + * - \ref RTC_TICK_1_4_SEC : Time tick is 1/4 second + * - \ref RTC_TICK_1_8_SEC : Time tick is 1/8 second + * - \ref RTC_TICK_1_16_SEC : Time tick is 1/16 second + * - \ref RTC_TICK_1_32_SEC : Time tick is 1/32 second + * - \ref RTC_TICK_1_64_SEC : Time tick is 1/64 second + * - \ref RTC_TICK_1_128_SEC : Time tick is 1/128 second + * + * @return None + * + * @details This API is used to set RTC tick period time for each tick interrupt. + */ +void RTC_SetTickPeriod(uint32_t u32TickSelection) +{ + + RTC->TICK = (RTC->TICK & ~RTC_TICK_TICK_Msk) | u32TickSelection; +} + +/** + * @brief Enable RTC Interrupt + * + * @param[in] u32IntFlagMask Specify the interrupt source. It consists of: + * - \ref RTC_INTEN_ALMIEN_Msk : Alarm interrupt + * - \ref RTC_INTEN_TICKIEN_Msk : Tick interrupt + * - \ref RTC_INTEN_TAMP0IEN_Msk : Tamper 0 Pin Event Detection interrupt + * + * @return None + * + * @details This API is used to enable the specify RTC interrupt function. + */ +void RTC_EnableInt(uint32_t u32IntFlagMask) +{ + RTC->INTEN |= u32IntFlagMask; +} + +/** + * @brief Disable RTC Interrupt + * + * @param[in] u32IntFlagMask Specify the interrupt source. It consists of: + * - \ref RTC_INTEN_ALMIEN_Msk : Alarm interrupt + * - \ref RTC_INTEN_TICKIEN_Msk : Tick interrupt + * - \ref RTC_INTEN_TAMP0IEN_Msk : Tamper 0 Pin Event Detection interrupt + * + * @return None + * + * @details This API is used to disable the specify RTC interrupt function. + */ +void RTC_DisableInt(uint32_t u32IntFlagMask) +{ + + RTC->INTEN &= ~u32IntFlagMask; + RTC->INTSTS = u32IntFlagMask; +} + +/** + * @brief Enable Spare Registers Access + * + * @param None + * + * @return None + * + * @details This API is used to enable the spare registers 0~4 can be accessed. + */ +void RTC_EnableSpareAccess(void) +{ + + RTC->SPRCTL |= RTC_SPRCTL_SPRRWEN_Msk; +} + +/** + * @brief Disable Spare Register + * + * @param None + * + * @return None + * + * @details This API is used to disable the spare register 0~4 cannot be accessed. + */ +void RTC_DisableSpareRegister(void) +{ + + RTC->SPRCTL &= ~RTC_SPRCTL_SPRRWEN_Msk; + +} + +/** + * @brief Static Tamper Detect + * + * @param[in] u32TamperSelect Tamper pin select. Possible options are + * - \ref RTC_TAMPER0_SELECT + * + * @param[in] u32DetecLevel Tamper pin detection level select. Possible options are + * - \ref RTC_TAMPER_HIGH_LEVEL_DETECT + * - \ref RTC_TAMPER_LOW_LEVEL_DETECT + * + * @param[in] u32DebounceEn Tamper pin de-bounce enable + * - \ref RTC_TAMPER_DEBOUNCE_ENABLE + * - \ref RTC_TAMPER_DEBOUNCE_DISABLE + * + * @return None + * + * @details This API is used to enable the tamper pin detect function with specify trigger condition. + */ +void RTC_StaticTamperEnable(uint32_t u32TamperSelect, uint32_t u32DetecLevel, uint32_t u32DebounceEn) +{ + uint32_t u32Loop; + uint32_t u32Reg; + uint32_t u32TmpReg; + + u32Reg = RTC->TAMPCTL; + + u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | (u32DetecLevel << RTC_TAMPCTL_TAMP0LV_Pos) | + (u32DebounceEn << RTC_TAMPCTL_TAMP0DBEN_Pos)); + + for (u32Loop = 0ul; u32Loop < MAX_TAMPER_PIN_NUM; u32Loop++) + { + if (u32TamperSelect & (0x1ul << u32Loop)) + { + u32Reg &= ~((RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP0LV_Msk | RTC_TAMPCTL_TAMP0DBEN_Msk) << (u32Loop * 4ul)); + u32Reg |= (u32TmpReg << (u32Loop * 4ul)); + } + } + + RTC->TAMPCTL = u32Reg; + +} + +/** + * @brief Static Tamper Disable + * + * @param[in] u32TamperSelect Tamper pin select. Possible options are + * - \ref RTC_TAMPER0_SELECT + * + * @return None + * + * @details This API is used to disable the static tamper pin detect. + */ +void RTC_StaticTamperDisable(uint32_t u32TamperSelect) +{ + uint32_t u32Loop; + uint32_t u32Reg; + uint32_t u32TmpReg; + + u32Reg = RTC->TAMPCTL; + + u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk); + + for (u32Loop = 0ul; u32Loop < MAX_TAMPER_PIN_NUM; u32Loop++) + { + if (u32TamperSelect & (0x1ul << u32Loop)) + { + u32Reg &= ~(u32TmpReg << (u32Loop * 4ul)); + } + } + + RTC->TAMPCTL = u32Reg; +} + + +/*@}*/ /* end of group RTC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group RTC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_sc.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_sc.c new file mode 100644 index 00000000000..cea50f42092 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_sc.c @@ -0,0 +1,463 @@ +/**************************************************************************//** + * @file sc.c + * @version V3.00 + * @brief Smart Card(SC) driver source file + * + * @note + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/* Below are variables used locally by SC driver and does not want to parse by doxygen unless HIDDEN_SYMBOLS is defined */ +/** @cond HIDDEN_SYMBOLS */ +static uint32_t u32CardStateIgnore[SC_INTERFACE_NUM] = {0UL}; + +/** @endcond HIDDEN_SYMBOLS */ + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SC_Driver SC Driver + @{ +*/ + +/** @addtogroup SC_EXPORTED_FUNCTIONS SC Exported Functions + @{ +*/ + +/** + * @brief Check Smartcard Slot Status + * + * @param[in] psSC The pointer of smartcard module. + * + * @retval TRUE Card insert + * @retval FALSE Card remove + * + * @details This function is used to check if specified smartcard slot is presented. + */ +uint32_t SC_IsCardInserted(SC_T *psSC) +{ + uint32_t ret; + + /* put conditions into two variable to remove IAR compilation warning */ + uint32_t cond1 = ((psSC->STATUS & SC_STATUS_CDPINSTS_Msk) >> SC_STATUS_CDPINSTS_Pos); + uint32_t cond2 = ((psSC->CTL & SC_CTL_CDLV_Msk) >> SC_CTL_CDLV_Pos); + + if ((psSC == SC0) && (u32CardStateIgnore[0] == 1UL)) + { + ret = (uint32_t)TRUE; + } + else if (cond1 != cond2) + { + ret = (uint32_t)FALSE; + } + else + { + ret = (uint32_t)TRUE; + } + + return ret; +} + +/* + * @brief Reset the Tx/Rx FIFO + * + * @param[in] psSC The pointer of smartcard module. + * + * @return None + * + * @details This function reset both transmit and receive FIFO of specified smartcard module. + */ +void SC_ClearFIFO(SC_T *psSC) +{ + while (psSC->ALTCTL & SC_ALTCTL_SYNC_Msk) + { + ; + } + + psSC->ALTCTL |= (SC_ALTCTL_TXRST_Msk | SC_ALTCTL_RXRST_Msk); +} + +/** + * @brief Disable specified Smartcard + * + * @param[in] psSC The pointer of smartcard module. + * + * @return None + * + * @details SC will force all transition to IDLE state. + */ +void SC_Close(SC_T *psSC) +{ + psSC->INTEN = 0UL; + + while (psSC->PINCTL & SC_PINCTL_SYNC_Msk) + { + ; + } + + psSC->PINCTL = 0UL; + psSC->ALTCTL = 0UL; + + while (psSC->CTL & SC_CTL_SYNC_Msk) + { + ; + } + + psSC->CTL = 0UL; +} + +/** + * @brief Initialized Smartcard + * + * @param[in] psSC The pointer of smartcard module. + * @param[in] u32CardDet Card detect polarity, select the SC_CD pin state which indicates card insert. Could be: + * -\ref SC_PIN_STATE_HIGH + * -\ref SC_PIN_STATE_LOW + * -\ref SC_PIN_STATE_IGNORE, no card detect pin, always assumes card present. + * @param[in] u32PWR Power on polarity, select the SC_PWR pin state which could set smartcard VCC to high level. Could be: + * -\ref SC_PIN_STATE_HIGH + * -\ref SC_PIN_STATE_LOW + * + * @return None + * + * @details Initialization process configures smartcard and enables engine clock. + */ +void SC_Open(SC_T *psSC, uint32_t u32CardDet, uint32_t u32PWR) +{ + uint32_t u32Reg = 0UL, u32Intf; + + if (psSC == SC0) + { + u32Intf = 0UL; + } + else + { + u32Intf = 2UL; + } + + if (u32CardDet != SC_PIN_STATE_IGNORE) + { + u32Reg = u32CardDet ? 0UL : SC_CTL_CDLV_Msk; + u32CardStateIgnore[u32Intf] = 0UL; + } + else + { + u32CardStateIgnore[u32Intf] = 1UL; + } + + psSC->PINCTL = u32PWR ? 0UL : SC_PINCTL_PWRINV_Msk; + + while (psSC->CTL & SC_CTL_SYNC_Msk) + { + ; + } + + psSC->CTL = SC_CTL_SCEN_Msk | u32Reg; +} + +/** + * @brief Reset specified Smartcard + * + * @param[in] psSC The pointer of smartcard module. + * + * @return None + * + * @details Reset the Tx/Rx FIFO, clock and initial default parameter. + */ +void SC_ResetReader(SC_T *psSC) +{ + uint32_t u32Intf; + + if (psSC == SC0) + { + u32Intf = 0UL; + } + else + { + u32Intf = 2UL; + } + + /* Reset FIFO, enable auto de-activation while card removal */ + psSC->ALTCTL |= (SC_ALTCTL_TXRST_Msk | SC_ALTCTL_RXRST_Msk | SC_ALTCTL_ADACEN_Msk); + + /* Set Rx trigger level to 1 character, longest card detect debounce period, disable error retry (EMV ATR does not use error retry) */ + while (psSC->CTL & SC_CTL_SYNC_Msk) + { + ; + } + + psSC->CTL &= ~(SC_CTL_RXTRGLV_Msk | + SC_CTL_CDDBSEL_Msk | + SC_CTL_TXRTY_Msk | + SC_CTL_TXRTYEN_Msk | + SC_CTL_RXRTY_Msk | + SC_CTL_RXRTYEN_Msk); + + while (psSC->CTL & SC_CTL_SYNC_Msk) + { + ; + } + + /* Enable auto convention, and all three smartcard internal timers */ + psSC->CTL |= SC_CTL_AUTOCEN_Msk | SC_CTL_TMRSEL_Msk; + /* Disable Rx timeout */ + psSC->RXTOUT = 0UL; + /* 372 clocks per ETU by default */ + psSC->ETUCTL = 371UL; + + /* Enable necessary interrupt for smartcard operation */ + if (u32CardStateIgnore[u32Intf]) /* Do not enable card detect interrupt if card present state ignore */ + { + psSC->INTEN = (SC_INTEN_RDAIEN_Msk | + SC_INTEN_TERRIEN_Msk | + SC_INTEN_TMR0IEN_Msk | + SC_INTEN_TMR1IEN_Msk | + SC_INTEN_TMR2IEN_Msk | + SC_INTEN_BGTIEN_Msk | + SC_INTEN_ACERRIEN_Msk); + } + else + { + psSC->INTEN = (SC_INTEN_RDAIEN_Msk | + SC_INTEN_TERRIEN_Msk | + SC_INTEN_TMR0IEN_Msk | + SC_INTEN_TMR1IEN_Msk | + SC_INTEN_TMR2IEN_Msk | + SC_INTEN_BGTIEN_Msk | + SC_INTEN_ACERRIEN_Msk | + SC_INTEN_CDIEN_Msk); + } + + return; +} + +/** + * @brief Set Block Guard Time + * + * @param[in] psSC The pointer of smartcard module. + * @param[in] u32BGT Block guard time using ETU as unit, valid range are between 1 ~ 32. + * + * @return None + * + * @details This function is used to configure block guard time (BGT) of specified smartcard module. + */ +void SC_SetBlockGuardTime(SC_T *psSC, uint32_t u32BGT) +{ + psSC->CTL = (psSC->CTL & ~SC_CTL_BGT_Msk) | ((u32BGT - 1UL) << SC_CTL_BGT_Pos); +} + +/** + * @brief Set Character Guard Time + * + * @param[in] psSC The pointer of smartcard module. + * @param[in] u32CGT Character guard time using ETU as unit, valid range are between 11 ~ 267. + * + * @return None + * + * @details This function is used to configure character guard time (CGT) of specified smartcard module. + * @note Before using this API, user should set the correct stop bit length first. + */ +void SC_SetCharGuardTime(SC_T *psSC, uint32_t u32CGT) +{ + /* CGT is "START bit" + "8-bits" + "Parity bit" + "STOP bit(s)" + "EGT counts" */ + u32CGT -= psSC->CTL & SC_CTL_NSB_Msk ? 11UL : 12UL; + psSC->EGT = u32CGT; +} + +/** + * @brief Stop all Timer Counting + * + * @param[in] psSC The pointer of smartcard module. + * + * @return None + * + * @details This function stop all smartcard timer of specified smartcard module. + * @note This function stop the timers within smartcard module, \b not timer module. + */ +void SC_StopAllTimer(SC_T *psSC) +{ + while (psSC->ALTCTL & SC_ALTCTL_SYNC_Msk) + { + ; + } + + psSC->ALTCTL &= ~(SC_ALTCTL_CNTEN0_Msk | SC_ALTCTL_CNTEN1_Msk | SC_ALTCTL_CNTEN2_Msk); +} + +/** + * @brief Configure and Start specified Timer + * + * @param[in] psSC The pointer of smartcard module. + * @param[in] u32TimerNum Specify time channel to start. Valid values are 0, 1, 2. + * @param[in] u32Mode Timer operating mode, valid values are: + * - \ref SC_TMR_MODE_0 + * - \ref SC_TMR_MODE_1 + * - \ref SC_TMR_MODE_2 + * - \ref SC_TMR_MODE_3 + * - \ref SC_TMR_MODE_4 + * - \ref SC_TMR_MODE_5 + * - \ref SC_TMR_MODE_6 + * - \ref SC_TMR_MODE_7 + * - \ref SC_TMR_MODE_8 + * - \ref SC_TMR_MODE_F + * @param[in] u32ETUCount Timer timeout duration, ETU based. For timer 0, valid range are between 1 ~ 0x1000000 ETUs. + * For timer 1 and timer 2, valid range are between 1 ~ 0x100 ETUs. + * + * @return None + * + * @details Enable Timer starting, counter will count when condition match. + * @note This function start the timer within smartcard module, \b not timer module. + * @note Depend on the timer operating mode, timer may not start counting immediately. + */ +void SC_StartTimer(SC_T *psSC, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount) +{ + uint32_t reg = u32Mode | (SC_TMRCTL0_CNT_Msk & (u32ETUCount - 1UL)); + + /* before to set CNTEN0/1/2 of reg. ALTCTL, SCEN bit must be enabled */ + if (u32TimerNum <= 2) + { + while (psSC->CTL & SC_CTL_SYNC_Msk) {}; + + psSC->CTL |= SC_CTL_TMRSEL_Msk | SC_CTL_SCEN_Msk; + + while (psSC->CTL & SC_CTL_SYNC_Msk) {}; + + while (psSC->ALTCTL & SC_ALTCTL_SYNC_Msk) {}; + } + + switch (u32TimerNum) + { + case 0UL: + while (psSC->TMRCTL0 & SC_TMRCTL0_SYNC_Msk) {}; + + psSC->TMRCTL0 = reg; + + psSC->ALTCTL |= SC_ALTCTL_CNTEN0_Msk; + + break; + + case 1UL: + while (psSC->TMRCTL1 & SC_TMRCTL1_SYNC_Msk) {}; + + psSC->TMRCTL1 = reg; + + psSC->ALTCTL |= SC_ALTCTL_CNTEN1_Msk; + + break; + + case 2UL: + while (psSC->TMRCTL2 & SC_TMRCTL2_SYNC_Msk) {}; + + psSC->TMRCTL2 = reg; + + psSC->ALTCTL |= SC_ALTCTL_CNTEN2_Msk; + + break; + + default: + break; + } +} + +/** + * @brief Stop specified Timer Counting + * + * @param[in] psSC The pointer of smartcard module. + * @param[in] u32TimerNum Specify timer channel to stop. Valid values are 0, 1, 2. + * + * @return None + * + * @details This function stop a smartcard timer of specified smartcard module. + * @note This function stop the timer within smartcard module, \b not timer module. + */ +void SC_StopTimer(SC_T *psSC, uint32_t u32TimerNum) +{ + while (psSC->ALTCTL & SC_ALTCTL_SYNC_Msk) {} + + if (u32TimerNum == 0UL) /* timer 0 */ + { + psSC->ALTCTL &= ~SC_ALTCTL_CNTEN0_Msk; + } + else if (u32TimerNum == 1UL) /* timer 1 */ + { + psSC->ALTCTL &= ~SC_ALTCTL_CNTEN1_Msk; + } + else /* timer 2 */ + { + psSC->ALTCTL &= ~SC_ALTCTL_CNTEN2_Msk; + } +} + +/** + * @brief Get specified Smartcard Clock Frequency + * + * @param[in] psSC The pointer of smartcard module. + * + * @return Smartcard frequency in kHZ + * + * @details This function is used to get specified smartcard module clock frequency in kHz. + */ +uint32_t SC_GetInterfaceClock(SC_T *psSC) +{ + uint32_t u32ClkSrc, u32Num, u32Clk = __HIRC, u32Div; + + /* Get smartcard module clock source and divider */ + if (psSC == SC0) + { + u32Num = 0UL; + u32ClkSrc = CLK_GetModuleClockSource(SC0_MODULE); + u32Div = CLK_GetModuleClockDivider(SC0_MODULE); + // u32ClkSrc = __HXT; + // u32Div = SC0->ETUCTL&SC_ETUCTL_ETURDIV_Msk; + } + else + { + u32Clk = 0UL; + } + + if (u32Clk == 0UL) + { + ; /* Invalid sc port */ + } + else + { + /* Get smartcard module clock */ + if (u32ClkSrc == 0UL) + { + u32Clk = __HXT; + } + else if (u32ClkSrc == 1UL) + { + u32Clk = CLK_GetPLLClockFreq(); + } + else if (u32ClkSrc == 2UL) + { + if (u32Num == 1UL) + { + u32Clk = CLK_GetPCLK1Freq(); + } + else + { + u32Clk = CLK_GetPCLK0Freq(); + } + } + else + { + u32Clk = __HIRC; + } + + u32Clk /= (u32Div + 1UL) * 1000UL; + } + + return u32Clk; +} + +/*@}*/ /* end of group SC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_scuart.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_scuart.c new file mode 100644 index 00000000000..9fa722b095c --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_scuart.c @@ -0,0 +1,239 @@ +/**************************************************************************//** + * @file scuart.c + * @brief M251 Smartcard UART mode (SCUART) driver source file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +static uint32_t SCUART_GetClock(SC_T *sc); + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SCUART_Driver SCUART Driver + @{ +*/ + + +/** @addtogroup SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions + @{ +*/ + +/** + * @brief The function is used to disable smartcard interface UART mode. + * @param sc The base address of smartcard module. + * @return None + */ +void SCUART_Close(SC_T *sc) +{ + sc->INTEN = 0UL; + sc->UARTCTL = 0UL; + sc->CTL = 0UL; + +} +/** @cond HIDDEN_SYMBOLS */ +/** + * @brief This function returns module clock of specified SC interface + * @param[in] sc The base address of smartcard module. + * @return Module clock of specified SC interface + */ +static uint32_t SCUART_GetClock(SC_T *sc) +{ + uint32_t u32ClkSrc, u32Num, u32Clk; + + if (sc == SC0) + { + u32Num = 0UL; + } + else + { + u32Num = 2UL; + } + + u32ClkSrc = (CLK->CLKSEL3 >> (2UL * u32Num)) & CLK_CLKSEL3_SC0SEL_Msk; + + /* Get smartcard module clock */ + if (u32ClkSrc == 0UL) + { + u32Clk = __HXT; + } + else if (u32ClkSrc == 1UL) + { + u32Clk = CLK_GetPLLClockFreq(); + } + else if (u32ClkSrc == 2UL) + { + if (u32Num == 1UL) + { + u32Clk = CLK_GetPCLK1Freq(); + } + else + { + u32Clk = CLK_GetPCLK0Freq(); + } + } + else + { + u32Clk = __HIRC; + } + + u32Clk /= (((CLK->CLKDIV1 >> (8UL * u32Num)) & CLK_CLKDIV1_SC0DIV_Msk) + 1UL); + + + return u32Clk; +} + +/** @endcond HIDDEN_SYMBOLS */ + +/** + * @brief This function use to enable smartcard module UART mode and set baudrate. + * @param[in] sc The base address of smartcard module. + * @param[in] u32baudrate Target baudrate of smartcard module. + * @return Actual baudrate of smartcard mode + * @details This function configures character width to 8 bits, 1 stop bit, and no parity. + * And can use \ref SCUART_SetLineConfig function to update these settings + * The baudrate clock source comes from SC_CLK/SC_DIV, where SC_CLK is controlled + * by SCxSEL in CLKSEL3 register, SC_DIV is controlled by SCxDIV in CLKDIV1 + * register. Since the baudrate divider is 12-bit wide and must be larger than 4, + * (clock source / baudrate) must be larger or equal to 5 and smaller or equal to + * 4096. Otherwise this function cannot configure SCUART to work with target baudrate. + */ +uint32_t SCUART_Open(SC_T *sc, uint32_t u32baudrate) +{ + uint32_t u32Clk = SCUART_GetClock(sc), u32Div; + + /* Calculate divider for target baudrate */ + u32Div = (u32Clk + (u32baudrate >> 1) - 1UL) / u32baudrate - 1UL; + + /* Enable smartcard interface and stop bit = 1 */ + sc->CTL = SC_CTL_SCEN_Msk | SC_CTL_NSB_Msk; + /* Enable UART mode, disable parity and 8 bit per character */ + sc->UARTCTL = SCUART_CHAR_LEN_8 | SCUART_PARITY_NONE | SC_UARTCTL_UARTEN_Msk; + sc->ETUCTL = u32Div; + + return (u32Clk / (u32Div + 1UL)); +} + +/** + * @brief The function is used to read Rx data from RX FIFO. + * @param[in] sc The base address of smartcard module. + * @param[in] pu8RxBuf The buffer to store receive the data + * @param[in] u32ReadBytes Target number of characters to receive + * @return Actual character number reads to buffer + * @note This function does not block and return immediately if there's no data available + */ +uint32_t SCUART_Read(SC_T *sc, uint8_t pu8RxBuf[], uint32_t u32ReadBytes) +{ + uint32_t u32Count; + + for (u32Count = 0UL; u32Count < u32ReadBytes; u32Count++) + { + if (SCUART_GET_RX_EMPTY(sc)) /* no data available */ + { + break; + } + + pu8RxBuf[u32Count] = (uint8_t)SCUART_READ(sc); /* get data from FIFO */ + } + + return u32Count; +} + +/** + * @brief This function use to configure smartcard UART mode line setting. + * @param[in] sc The base address of smartcard module. + * @param[in] u32Baudrate Target baudrate of smartcard module. If this value is 0, UART baudrate will not change. + * @param[in] u32DataWidth The data length, could be + * - \ref SCUART_CHAR_LEN_5 + * - \ref SCUART_CHAR_LEN_6 + * - \ref SCUART_CHAR_LEN_7 + * - \ref SCUART_CHAR_LEN_8 + * @param[in] u32Parity The parity setting, could be + * - \ref SCUART_PARITY_NONE + * - \ref SCUART_PARITY_ODD + * - \ref SCUART_PARITY_EVEN + * @param[in] u32StopBits The stop bit length, could be + * - \ref SCUART_STOP_BIT_1 + * - \ref SCUART_STOP_BIT_2 + * @return Actual baudrate of smartcard + * @details The baudrate clock source comes from SC_CLK/SC_DIV, where SC_CLK is controlled + * by SCxSEL in CLKSEL3 register, SC_DIV is controlled by SCxDIV in CLKDIV1 + * register. Since the baudrate divider is 12-bit wide and must be larger than 4, + * (clock source / baudrate) must be larger or equal to 5 and smaller or equal to + * 4096. Otherwise this function cannot configure SCUART to work with target baudrate. + */ +uint32_t SCUART_SetLineConfig(SC_T *sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits) +{ + + uint32_t u32Clk = SCUART_GetClock(sc), u32Div; + + if (u32Baudrate == 0UL) /* keep original baudrate setting */ + { + u32Div = sc->ETUCTL & SC_ETUCTL_ETURDIV_Msk; + } + else + { + /* Calculate divider for target baudrate */ + u32Div = (u32Clk + (u32Baudrate >> 1) - 1UL) / u32Baudrate - 1UL; + sc->ETUCTL = u32Div; + } + + /* Set stop bit */ + sc->CTL = u32StopBits | SC_CTL_SCEN_Msk; + /* Set character width and parity */ + sc->UARTCTL = u32Parity | u32DataWidth | SC_UARTCTL_UARTEN_Msk; + + return (u32Clk / (u32Div + 1UL)); +} + +/** + * @brief This function use to set receive timeout count. + * @param[in] sc The base address of smartcard module. + * @param[in] u32TOC Rx timeout counter, using baudrate as counter unit. Valid range are 0~0x1FF, + * set this value to 0 will disable timeout counter + * @return None + * @details The time-out counter resets and starts counting whenever the RX buffer received a + * new data word. Once the counter decrease to 1 and no new data is received or CPU + * does not read any data from FIFO, a receiver time-out interrupt will be generated. + */ +void SCUART_SetTimeoutCnt(SC_T *sc, uint32_t u32TOC) +{ + sc->RXTOUT = u32TOC; +} + + +/** + * @brief This function is to write data into transmit FIFO to send data out. + * @param[in] sc The base address of smartcard module. + * @param[in] pu8TxBuf The buffer containing data to send to transmit FIFO. + * @param[in] u32WriteBytes Number of data to send. + * @return None + * @note This function blocks until all data write into FIFO + */ +void SCUART_Write(SC_T *sc, uint8_t pu8TxBuf[], uint32_t u32WriteBytes) +{ + uint32_t u32Count; + + for (u32Count = 0UL; u32Count != u32WriteBytes; u32Count++) + { + /* Wait 'til FIFO not full */ + while (SCUART_GET_TX_FULL(sc)) + { + ; + } + + /* Write 1 byte to FIFO */ + sc->DAT = pu8TxBuf[u32Count]; + } +} + + +/*@}*/ /* end of group SCUART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SCUART_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_spi.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_spi.c new file mode 100644 index 00000000000..18873256104 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_spi.c @@ -0,0 +1,1141 @@ +/**************************************************************************//** + * @file spi.c + * @version V0.10 + * @brief M251 series SPI driver source file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ +/** @addtogroup SPI_Driver SPI Driver + @{ +*/ + + +/** @addtogroup SPI_EXPORTED_FUNCTIONS SPI Exported Functions + @{ +*/ +static uint32_t SPII2S_GetSourceClockFreq(SPI_T *i2s); + +/** + * @brief This function make SPI module be ready to transfer. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32MasterSlave Decides the SPI module is operating in master mode or in slave mode. (SPI_SLAVE, SPI_MASTER) + * @param[in] u32SPIMode Decides the transfer timing. (SPI_MODE_0, SPI_MODE_1, SPI_MODE_2, SPI_MODE_3) + * @param[in] u32DataWidth Decides the data width of a SPI transaction. + * @param[in] u32BusClock The expected frequency of SPI bus clock in Hz. + * @return Actual frequency of SPI peripheral clock. + * @details By default, the SPI transfer sequence is MSB first, the slave selection signal is active low and the automatic + * slave selection function is disabled. + * In Slave mode, the u32BusClock shall be NULL and the SPI clock divider setting will be 0. + * The actual clock rate may be different from the target SPI clock rate. + * For example, if the SPI source clock rate is 12 MHz and the target SPI bus clock rate is 7 MHz, the + * actual SPI clock rate will be 6MHz. + * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value. + * @note If u32BusClock >= system clock frequency, SPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0. + * @note If u32BusClock >= SPI peripheral clock source, DIVIDER will be set to 0. + * @note In slave mode, the SPI peripheral clock rate will be equal to APB clock rate. + */ +uint32_t SPI_Open(SPI_T *spi, + uint32_t u32MasterSlave, + uint32_t u32SPIMode, + uint32_t u32DataWidth, + uint32_t u32BusClock) +{ + uint32_t u32ClkSrc = 0UL, u32Div, u32HCLKFreq, u32RetValue = 0UL; + + /* Disable I2S mode */ + spi->I2SCTL &= ~SPI_I2SCTL_I2SEN_Msk; + + if (u32DataWidth == 32UL) + { + u32DataWidth = 0UL; + } + + /* Get system clock frequency */ + u32HCLKFreq = CLK_GetHCLKFreq(); + + if (u32MasterSlave == SPI_MASTER) + { + /* Default setting: slave selection signal is active low; disable automatic slave selection function. */ + spi->SSCTL = SPI_SS_ACTIVE_LOW; + + /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */ + spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode) | SPI_CTL_SPIEN_Msk; + + if (u32BusClock >= u32HCLKFreq) + { + /* Select PCLK as the clock source of SPI */ + if (spi == SPI0) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1; + } + } + + /* Check clock source of SPI */ + if (spi == SPI0) + { + if ((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if ((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if ((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK1) + { + /* Clock source is PCLK1 */ + u32ClkSrc = CLK_GetPCLK1Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + + if (u32BusClock >= u32HCLKFreq) + { + /* Set DIVIDER = 0 */ + spi->CLKDIV = 0UL; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if (u32BusClock >= u32ClkSrc) + { + /* Set DIVIDER = 0 */ + spi->CLKDIV = 0UL; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if (u32BusClock == 0UL) + { + /* Set DIVIDER to the maximum value 0x1FF. f_spi = f_spi_clk_src / (DIVIDER + 1) */ + spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0x1FFU + 1UL)); + } + else + { + u32Div = (((u32ClkSrc * 10UL) / u32BusClock + 5UL) / 10UL) - 1UL; /* Round to the nearest integer */ + + if (u32Div > 0x1FFUL) + { + u32Div = 0x1FFUL; + spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL)); + } + else + { + spi->CLKDIV = (spi->CLKDIV & (~SPI_CLKDIV_DIVIDER_Msk)) | (u32Div << SPI_CLKDIV_DIVIDER_Pos); + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (u32Div + 1UL)); + } + } + } + else /* For slave mode, force the SPI peripheral clock rate to equal APB clock rate. */ + { + /* Default setting: slave selection signal is low level active. */ + spi->SSCTL = SPI_SS_ACTIVE_LOW; + + /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */ + spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode) | SPI_CTL_SPIEN_Msk; + + /* Set DIVIDER = 0 */ + spi->CLKDIV = 0UL; + + /* Select PCLK as the clock source of SPI */ + if (spi == SPI0) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1; + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK1Freq(); + } + } + + return u32RetValue; +} + +/** + * @brief Disable SPI controller. + * @param[in] spi The pointer of the specified SPI module. + * @return None + * @details This function will reset SPI controller. + */ +void SPI_Close(SPI_T *spi) +{ + if (spi == SPI0) + { + /* Reset SPI */ + SYS->IPRST1 |= SYS_IPRST1_SPI0RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_SPI0RST_Msk; + } +} + +/** + * @brief Clear RX FIFO buffer. + * @param[in] spi The pointer of the specified SPI module. + * @return None + * @details This function will clear SPI RX FIFO buffer. The RXEMPTY (SPI_STATUS[8]) will be set to 1. + */ +void SPI_ClearRxFIFO(SPI_T *spi) +{ + spi->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk; +} + +/** + * @brief Clear TX FIFO buffer. + * @param[in] spi The pointer of the specified SPI module. + * @return None + * @details This function will clear SPI TX FIFO buffer. The TXEMPTY (SPI_STATUS[16]) will be set to 1. + * @note The TX shift register will not be cleared. + */ +void SPI_ClearTxFIFO(SPI_T *spi) +{ + spi->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk; +} + +/** + * @brief Disable the automatic slave selection function. + * @param[in] spi The pointer of the specified SPI module. + * @return None + * @details This function will disable the automatic slave selection function and set slave selection signal to inactive state. + */ +void SPI_DisableAutoSS(SPI_T *spi) +{ + spi->SSCTL &= ~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SS_Msk); +} + +/** + * @brief Enable the automatic slave selection function. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32SSPinMask Specifies slave selection pins. (SPI_SS) + * @param[in] u32ActiveLevel Specifies the active level of slave selection signal. (SPI_SS_ACTIVE_HIGH, SPI_SS_ACTIVE_LOW) + * @return None + * @details This function will enable the automatic slave selection function. Only available in Master mode. + * The slave selection pin and the active level will be set in this function. + */ +void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel) +{ + spi->SSCTL = (spi->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk))) | (u32SSPinMask | u32ActiveLevel | SPI_SSCTL_AUTOSS_Msk); +} + +/** + * @brief Set the SPI bus clock. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32BusClock The expected frequency of SPI bus clock in Hz. + * @return Actual frequency of SPI bus clock. + * @details This function is only available in Master mode. The actual clock rate may be different from the target SPI bus clock rate. + * For example, if the SPI source clock rate is 12 MHz and the target SPI bus clock rate is 7 MHz, the actual SPI bus clock + * rate will be 6 MHz. + * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value. + * @note If u32BusClock >= system clock frequency, SPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0. + * @note If u32BusClock >= SPI peripheral clock source, DIVIDER will be set to 0. + */ +uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock) +{ + uint32_t u32ClkSrc, u32HCLKFreq; + uint32_t u32Div, u32RetValue; + + /* Get system clock frequency */ + u32HCLKFreq = CLK_GetHCLKFreq(); + + if (u32BusClock >= u32HCLKFreq) + { + /* Select PCLK as the clock source of SPI */ + if (spi == SPI0) + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1; + } + + /* Check clock source of SPI */ + if (spi == SPI0) + { + if ((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if ((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if ((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK1) + { + /* Clock source is PCLK1 */ + u32ClkSrc = CLK_GetPCLK1Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + + if (u32BusClock >= u32HCLKFreq) + { + /* Set DIVIDER = 0 */ + spi->CLKDIV = 0UL; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if (u32BusClock >= u32ClkSrc) + { + /* Set DIVIDER = 0 */ + spi->CLKDIV = 0UL; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if (u32BusClock == 0UL) + { + /* Set DIVIDER to the maximum value 0x1FF. f_spi = f_spi_clk_src / (DIVIDER + 1) */ + spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0x1FFU + 1UL)); + } + else + { + u32Div = (((u32ClkSrc * 10UL) / u32BusClock + 5UL) / 10UL) - 1UL; /* Round to the nearest integer */ + + if (u32Div > 0x1FFUL) + { + u32Div = 0x1FFUL; + spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL)); + } + else + { + spi->CLKDIV = (spi->CLKDIV & (~SPI_CLKDIV_DIVIDER_Msk)) | (u32Div << SPI_CLKDIV_DIVIDER_Pos); + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (u32Div + 1UL)); + } + } + + return u32RetValue; +} + +/** + * @brief Configure FIFO threshold setting. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32TxThreshold Decides the TX FIFO threshold. + * @param[in] u32RxThreshold Decides the RX FIFO threshold. + * @return None + * @details Set TX FIFO threshold and RX FIFO threshold configurations. + */ +void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold) +{ + spi->FIFOCTL = (spi->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk | SPI_FIFOCTL_RXTH_Msk)) | + (u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) | + (u32RxThreshold << SPI_FIFOCTL_RXTH_Pos); +} + +/** + * @brief Get the actual frequency of SPI bus clock. Only available in Master mode. + * @param[in] spi The pointer of the specified SPI module. + * @return Actual SPI bus clock frequency in Hz. + * @details This function will calculate the actual SPI bus clock rate according to the SPInSEL and DIVIDER settings. Only available in Master mode. + */ +uint32_t SPI_GetBusClock(SPI_T *spi) +{ + uint32_t u32Div; + uint32_t u32ClkSrc; + + /* Get DIVIDER setting */ + u32Div = (spi->CLKDIV & SPI_CLKDIV_DIVIDER_Msk) >> SPI_CLKDIV_DIVIDER_Pos; + + /* Check clock source of SPI */ + if (spi == SPI0) + { + if ((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if ((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if ((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK1) + { + /* Clock source is PCLK1 */ + u32ClkSrc = CLK_GetPCLK1Freq(); + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + + /* Return SPI bus clock rate */ + return (u32ClkSrc / (u32Div + 1UL)); +} + +/** + * @brief Enable interrupt function. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be enabled. It is combination of: + * - \ref SPI_UNIT_INT_MASK + * - \ref SPI_SSACT_INT_MASK + * - \ref SPI_SSINACT_INT_MASK + * - \ref SPI_SLVUR_INT_MASK + * - \ref SPI_SLVBE_INT_MASK + * - \ref SPI_TXUF_INT_MASK + * - \ref SPI_FIFO_TXTH_INT_MASK + * - \ref SPI_FIFO_RXTH_INT_MASK + * - \ref SPI_FIFO_RXOV_INT_MASK + * - \ref SPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Enable SPI related interrupts specified by u32Mask parameter. + */ +void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask) +{ + /* Enable unit transfer interrupt flag */ + if ((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK) + { + spi->CTL |= SPI_CTL_UNITIEN_Msk; + } + + /* Enable slave selection signal active interrupt flag */ + if ((u32Mask & SPI_SSACT_INT_MASK) == SPI_SSACT_INT_MASK) + { + spi->SSCTL |= SPI_SSCTL_SSACTIEN_Msk; + } + + /* Enable slave selection signal inactive interrupt flag */ + if ((u32Mask & SPI_SSINACT_INT_MASK) == SPI_SSINACT_INT_MASK) + { + spi->SSCTL |= SPI_SSCTL_SSINAIEN_Msk; + } + + /* Enable slave TX under run interrupt flag */ + if ((u32Mask & SPI_SLVUR_INT_MASK) == SPI_SLVUR_INT_MASK) + { + spi->SSCTL |= SPI_SSCTL_SLVURIEN_Msk; + } + + /* Enable slave bit count error interrupt flag */ + if ((u32Mask & SPI_SLVBE_INT_MASK) == SPI_SLVBE_INT_MASK) + { + spi->SSCTL |= SPI_SSCTL_SLVBEIEN_Msk; + } + + /* Enable slave TX underflow interrupt flag */ + if ((u32Mask & SPI_TXUF_INT_MASK) == SPI_TXUF_INT_MASK) + { + spi->FIFOCTL |= SPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Enable TX threshold interrupt flag */ + if ((u32Mask & SPI_FIFO_TXTH_INT_MASK) == SPI_FIFO_TXTH_INT_MASK) + { + spi->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Enable RX threshold interrupt flag */ + if ((u32Mask & SPI_FIFO_RXTH_INT_MASK) == SPI_FIFO_RXTH_INT_MASK) + { + spi->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Enable RX overrun interrupt flag */ + if ((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK) + { + spi->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Enable RX time-out interrupt flag */ + if ((u32Mask & SPI_FIFO_RXTO_INT_MASK) == SPI_FIFO_RXTO_INT_MASK) + { + spi->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk; + } +} + +/** + * @brief Disable interrupt function. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * This parameter decides which interrupts will be disabled. It is combination of: + * - \ref SPI_UNIT_INT_MASK + * - \ref SPI_SSACT_INT_MASK + * - \ref SPI_SSINACT_INT_MASK + * - \ref SPI_SLVUR_INT_MASK + * - \ref SPI_SLVBE_INT_MASK + * - \ref SPI_TXUF_INT_MASK + * - \ref SPI_FIFO_TXTH_INT_MASK + * - \ref SPI_FIFO_RXTH_INT_MASK + * - \ref SPI_FIFO_RXOV_INT_MASK + * - \ref SPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Disable SPI related interrupts specified by u32Mask parameter. + */ +void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask) +{ + /* Disable unit transfer interrupt flag */ + if ((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK) + { + spi->CTL &= ~SPI_CTL_UNITIEN_Msk; + } + + /* Disable slave selection signal active interrupt flag */ + if ((u32Mask & SPI_SSACT_INT_MASK) == SPI_SSACT_INT_MASK) + { + spi->SSCTL &= ~SPI_SSCTL_SSACTIEN_Msk; + } + + /* Disable slave selection signal inactive interrupt flag */ + if ((u32Mask & SPI_SSINACT_INT_MASK) == SPI_SSINACT_INT_MASK) + { + spi->SSCTL &= ~SPI_SSCTL_SSINAIEN_Msk; + } + + /* Disable slave TX under run interrupt flag */ + if ((u32Mask & SPI_SLVUR_INT_MASK) == SPI_SLVUR_INT_MASK) + { + spi->SSCTL &= ~SPI_SSCTL_SLVURIEN_Msk; + } + + /* Disable slave bit count error interrupt flag */ + if ((u32Mask & SPI_SLVBE_INT_MASK) == SPI_SLVBE_INT_MASK) + { + spi->SSCTL &= ~SPI_SSCTL_SLVBEIEN_Msk; + } + + /* Disable slave TX underflow interrupt flag */ + if ((u32Mask & SPI_TXUF_INT_MASK) == SPI_TXUF_INT_MASK) + { + spi->FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Disable TX threshold interrupt flag */ + if ((u32Mask & SPI_FIFO_TXTH_INT_MASK) == SPI_FIFO_TXTH_INT_MASK) + { + spi->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Disable RX threshold interrupt flag */ + if ((u32Mask & SPI_FIFO_RXTH_INT_MASK) == SPI_FIFO_RXTH_INT_MASK) + { + spi->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Disable RX overrun interrupt flag */ + if ((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK) + { + spi->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Disable RX time-out interrupt flag */ + if ((u32Mask & SPI_FIFO_RXTO_INT_MASK) == SPI_FIFO_RXTO_INT_MASK) + { + spi->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk; + } +} + +/** + * @brief Get interrupt flag. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be read. It is combination of: + * - \ref SPI_UNIT_INT_MASK + * - \ref SPI_SSACT_INT_MASK + * - \ref SPI_SSINACT_INT_MASK + * - \ref SPI_SLVUR_INT_MASK + * - \ref SPI_SLVBE_INT_MASK + * - \ref SPI_TXUF_INT_MASK + * - \ref SPI_FIFO_TXTH_INT_MASK + * - \ref SPI_FIFO_RXTH_INT_MASK + * - \ref SPI_FIFO_RXOV_INT_MASK + * - \ref SPI_FIFO_RXTO_INT_MASK + * + * @return Interrupt flags of selected sources. + * @details Get SPI related interrupt flags specified by u32Mask parameter. + */ +uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask) +{ + uint32_t u32IntFlag = 0UL, u32TmpVal; + + u32TmpVal = spi->STATUS & SPI_STATUS_UNITIF_Msk; + + /* Check unit transfer interrupt flag */ + if ((u32Mask & SPI_UNIT_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_UNIT_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_SSACTIF_Msk; + + /* Check slave selection signal active interrupt flag */ + if ((u32Mask & SPI_SSACT_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_SSACT_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_SSINAIF_Msk; + + /* Check slave selection signal inactive interrupt flag */ + if ((u32Mask & SPI_SSINACT_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_SSINACT_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_SLVURIF_Msk; + + /* Check slave TX under run interrupt flag */ + if ((u32Mask & SPI_SLVUR_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_SLVUR_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_SLVBEIF_Msk; + + /* Check slave bit count error interrupt flag */ + if ((u32Mask & SPI_SLVBE_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_SLVBE_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_TXUFIF_Msk; + + /* Check slave TX underflow interrupt flag */ + if ((u32Mask & SPI_TXUF_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_TXUF_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_TXTHIF_Msk; + + /* Check TX threshold interrupt flag */ + if ((u32Mask & SPI_FIFO_TXTH_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_FIFO_TXTH_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_RXTHIF_Msk; + + /* Check RX threshold interrupt flag */ + if ((u32Mask & SPI_FIFO_RXTH_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_FIFO_RXTH_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_RXOVIF_Msk; + + /* Check RX overrun interrupt flag */ + if ((u32Mask & SPI_FIFO_RXOV_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_FIFO_RXOV_INT_MASK; + } + + u32TmpVal = spi->STATUS & SPI_STATUS_RXTOIF_Msk; + + /* Check RX time-out interrupt flag */ + if ((u32Mask & SPI_FIFO_RXTO_INT_MASK) && (u32TmpVal)) + { + u32IntFlag |= SPI_FIFO_RXTO_INT_MASK; + } + + return u32IntFlag; +} + +/** + * @brief Clear interrupt flag. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. It could be the combination of: + * - \ref SPI_UNIT_INT_MASK + * - \ref SPI_SSACT_INT_MASK + * - \ref SPI_SSINACT_INT_MASK + * - \ref SPI_SLVUR_INT_MASK + * - \ref SPI_SLVBE_INT_MASK + * - \ref SPI_TXUF_INT_MASK + * - \ref SPI_FIFO_RXOV_INT_MASK + * - \ref SPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Clear SPI related interrupt flags specified by u32Mask parameter. + */ +void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask) +{ + if (u32Mask & SPI_UNIT_INT_MASK) + { + spi->STATUS = SPI_STATUS_UNITIF_Msk; /* Clear unit transfer interrupt flag */ + } + + if (u32Mask & SPI_SSACT_INT_MASK) + { + spi->STATUS = SPI_STATUS_SSACTIF_Msk; /* Clear slave selection signal active interrupt flag */ + } + + if (u32Mask & SPI_SSINACT_INT_MASK) + { + spi->STATUS = SPI_STATUS_SSINAIF_Msk; /* Clear slave selection signal inactive interrupt flag */ + } + + if (u32Mask & SPI_SLVUR_INT_MASK) + { + spi->STATUS = SPI_STATUS_SLVURIF_Msk; /* Clear slave TX under run interrupt flag */ + } + + if (u32Mask & SPI_SLVBE_INT_MASK) + { + spi->STATUS = SPI_STATUS_SLVBEIF_Msk; /* Clear slave bit count error interrupt flag */ + } + + if (u32Mask & SPI_TXUF_INT_MASK) + { + spi->STATUS = SPI_STATUS_TXUFIF_Msk; /* Clear slave TX underflow interrupt flag */ + } + + if (u32Mask & SPI_FIFO_RXOV_INT_MASK) + { + spi->STATUS = SPI_STATUS_RXOVIF_Msk; /* Clear RX overrun interrupt flag */ + } + + if (u32Mask & SPI_FIFO_RXTO_INT_MASK) + { + spi->STATUS = SPI_STATUS_RXTOIF_Msk; /* Clear RX time-out interrupt flag */ + } +} + +/** + * @brief Get SPI status. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related sources. + * Each bit corresponds to a source. + * This parameter decides which flags will be read. It is combination of: + * - \ref SPI_BUSY_MASK + * - \ref SPI_RX_EMPTY_MASK + * - \ref SPI_RX_FULL_MASK + * - \ref SPI_TX_EMPTY_MASK + * - \ref SPI_TX_FULL_MASK + * - \ref SPI_TXRX_RESET_MASK + * - \ref SPI_SPIEN_STS_MASK + * - \ref SPI_SSLINE_STS_MASK + * + * @return Flags of selected sources. + * @details Get SPI related status specified by u32Mask parameter. + */ +uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask) +{ + uint32_t u32Flag = 0UL, u32TmpValue; + + u32TmpValue = spi->STATUS & SPI_STATUS_BUSY_Msk; + + /* Check busy status */ + if ((u32Mask & SPI_BUSY_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_BUSY_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_RXEMPTY_Msk; + + /* Check RX empty flag */ + if ((u32Mask & SPI_RX_EMPTY_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_RX_EMPTY_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_RXFULL_Msk; + + /* Check RX full flag */ + if ((u32Mask & SPI_RX_FULL_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_RX_FULL_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_TXEMPTY_Msk; + + /* Check TX empty flag */ + if ((u32Mask & SPI_TX_EMPTY_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_TX_EMPTY_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_TXFULL_Msk; + + /* Check TX full flag */ + if ((u32Mask & SPI_TX_FULL_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_TX_FULL_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_TXRXRST_Msk; + + /* Check TX/RX reset flag */ + if ((u32Mask & SPI_TXRX_RESET_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_TXRX_RESET_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_SPIENSTS_Msk; + + /* Check SPIEN flag */ + if ((u32Mask & SPI_SPIEN_STS_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_SPIEN_STS_MASK; + } + + u32TmpValue = spi->STATUS & SPI_STATUS_SSLINE_Msk; + + /* Check SPIx_SS line status */ + if ((u32Mask & SPI_SSLINE_STS_MASK) && (u32TmpValue)) + { + u32Flag |= SPI_SSLINE_STS_MASK; + } + + return u32Flag; +} + + +/** + * @brief This function is used to get I2S source clock frequency. + * @param[in] i2s The pointer of the specified I2S module. + * @return I2S source clock frequency (Hz). + * @details Return the source clock frequency according to the setting of SPI0SEL. + */ +static uint32_t SPII2S_GetSourceClockFreq(SPI_T *i2s) +{ + uint32_t u32Freq; + + if (i2s == SPI0) + { + if ((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_HXT) + { + u32Freq = __HXT; /* Clock source is HXT */ + } + else if ((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PLL) + { + u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if ((CLK->CLKSEL2 & CLK_CLKSEL2_SPI0SEL_Msk) == CLK_CLKSEL2_SPI0SEL_PCLK1) + { + /* Clock source is PCLK1 */ + u32Freq = CLK_GetPCLK1Freq(); + } + else + { + u32Freq = __HIRC; /* Clock source is HIRC */ + } + } + + return u32Freq; +} + +/** + * @brief This function configures some parameters of I2S interface for general purpose use. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32MasterSlave I2S operation mode. Valid values are listed below. + * - \ref SPII2S_MODE_MASTER + * - \ref SPII2S_MODE_SLAVE + * @param[in] u32SampleRate Sample rate + * @param[in] u32WordWidth Data length. Valid values are listed below. + * - \ref SPII2S_DATABIT_8 + * - \ref SPII2S_DATABIT_16 + * - \ref SPII2S_DATABIT_24 + * - \ref SPII2S_DATABIT_32 + * @param[in] u32Channels Audio format. Valid values are listed below. + * - \ref SPII2S_MONO + * - \ref SPII2S_STEREO + * @param[in] u32DataFormat Data format. Valid values are listed below. + * - \ref SPII2S_FORMAT_I2S + * - \ref SPII2S_FORMAT_MSB + * - \ref SPII2S_FORMAT_PCMA + * - \ref SPII2S_FORMAT_PCMB + * @return Real sample rate of master mode or peripheral clock rate of slave mode. + * @details This function will reset SPI/I2S controller and configure I2S controller according to the input parameters. + * Set TX FIFO threshold to 2 and RX FIFO threshold to 1. Both the TX and RX functions will be enabled. + * The actual sample rate may be different from the target sample rate. The real sample rate will be returned for reference. + * @note In slave mode, the SPI peripheral clock rate will be equal to APB clock rate. + */ +uint32_t SPII2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat) +{ + uint32_t u32Divider; + uint32_t u32BitRate, u32SrcClk, u32RetValue; + + /* Reset SPI/I2S */ + if (i2s == SPI0) + { + SYS->IPRST1 |= SYS_IPRST1_SPI0RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_SPI0RST_Msk; + } + + /* Configure I2S controller */ + i2s->I2SCTL = u32MasterSlave | u32WordWidth | u32Channels | u32DataFormat; + /* Set TX FIFO threshold to 2 and RX FIFO threshold to 1 */ + i2s->FIFOCTL = SPII2S_FIFO_TX_LEVEL_WORD_2 | SPII2S_FIFO_RX_LEVEL_WORD_2; + + if (u32MasterSlave == SPI_MASTER) + { + /* Get the source clock rate */ + u32SrcClk = SPII2S_GetSourceClockFreq(i2s); + + /* Calculate the bit clock rate */ + u32BitRate = u32SampleRate * ((u32WordWidth >> SPI_I2SCTL_WDWIDTH_Pos) + 1UL) * 16UL; + u32Divider = (((((u32SrcClk * 10UL / u32BitRate)) >> 1UL) + 5UL) / 10UL) - 1UL; + /* Set BCLKDIV setting */ + i2s->I2SCLK = (i2s->I2SCLK & ~SPI_I2SCLK_BCLKDIV_Msk) | (u32Divider << SPI_I2SCLK_BCLKDIV_Pos); + + /* Calculate bit clock rate */ + u32BitRate = u32SrcClk / ((u32Divider + 1UL) * 2UL); + /* Calculate real sample rate */ + u32SampleRate = u32BitRate / (((u32WordWidth >> SPI_I2SCTL_WDWIDTH_Pos) + 1UL) * 16UL); + + /* Enable TX function, RX function and I2S mode. */ + i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk); + + /* Return the real sample rate */ + u32RetValue = u32SampleRate; + } + else + { + /* Set BCLKDIV = 0 */ + i2s->I2SCLK &= ~SPI_I2SCLK_BCLKDIV_Msk; + + if (i2s == SPI0) + { + /* Set the peripheral clock rate to equal APB clock rate */ + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1; + /* Enable TX function, RX function and I2S mode. */ + i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk); + /* Return slave peripheral clock rate */ + u32RetValue = CLK_GetPCLK1Freq(); + } + } + + return u32RetValue; +} + +/** + * @brief Disable I2S function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details Disable I2S function. + */ +void SPII2S_Close(SPI_T *i2s) +{ + i2s->I2SCTL &= ~SPI_I2SCTL_I2SEN_Msk; +} + +/** + * @brief Enable interrupt function. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref SPII2S_FIFO_TXTH_INT_MASK + * - \ref SPII2S_FIFO_RXTH_INT_MASK + * - \ref SPII2S_FIFO_RXOV_INT_MASK + * - \ref SPII2S_FIFO_RXTO_INT_MASK + * - \ref SPII2S_TXUF_INT_MASK + * - \ref SPII2S_RIGHT_ZC_INT_MASK + * - \ref SPII2S_LEFT_ZC_INT_MASK + * - \ref SPII2S_SLV_CLKERR_INT_MASK + * @return None + * @details This function enables the interrupt according to the u32Mask parameter. + */ +void SPII2S_EnableInt(SPI_T *i2s, uint32_t u32Mask) +{ + /* Enable TX threshold interrupt flag */ + if ((u32Mask & SPII2S_FIFO_TXTH_INT_MASK) == SPII2S_FIFO_TXTH_INT_MASK) + { + i2s->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Enable RX threshold interrupt flag */ + if ((u32Mask & SPII2S_FIFO_RXTH_INT_MASK) == SPII2S_FIFO_RXTH_INT_MASK) + { + i2s->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Enable RX overrun interrupt flag */ + if ((u32Mask & SPII2S_FIFO_RXOV_INT_MASK) == SPII2S_FIFO_RXOV_INT_MASK) + { + i2s->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Enable RX time-out interrupt flag */ + if ((u32Mask & SPII2S_FIFO_RXTO_INT_MASK) == SPII2S_FIFO_RXTO_INT_MASK) + { + i2s->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk; + } + + /* Enable TX underflow interrupt flag */ + if ((u32Mask & SPII2S_TXUF_INT_MASK) == SPII2S_TXUF_INT_MASK) + { + i2s->FIFOCTL |= SPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Enable right channel zero cross interrupt flag */ + if ((u32Mask & SPII2S_RIGHT_ZC_INT_MASK) == SPII2S_RIGHT_ZC_INT_MASK) + { + i2s->I2SCTL |= SPI_I2SCTL_RZCIEN_Msk; + } + + /* Enable left channel zero cross interrupt flag */ + if ((u32Mask & SPII2S_LEFT_ZC_INT_MASK) == SPII2S_LEFT_ZC_INT_MASK) + { + i2s->I2SCTL |= SPI_I2SCTL_LZCIEN_Msk; + } + + /* Enable slave mode bit clock loss interrupt flag */ + if ((u32Mask & SPII2S_SLV_CLKERR_INT_MASK) == SPII2S_SLV_CLKERR_INT_MASK) + { + i2s->I2SCTL |= SPI_I2SCTL_SLVERRIEN_Msk; + } +} + +/** + * @brief Disable interrupt function. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref SPII2S_FIFO_TXTH_INT_MASK + * - \ref SPII2S_FIFO_RXTH_INT_MASK + * - \ref SPII2S_FIFO_RXOV_INT_MASK + * - \ref SPII2S_FIFO_RXTO_INT_MASK + * - \ref SPII2S_TXUF_INT_MASK + * - \ref SPII2S_RIGHT_ZC_INT_MASK + * - \ref SPII2S_LEFT_ZC_INT_MASK + * - \ref SPII2S_SLV_CLKERR_INT_MASK + * @return None + * @details This function disables the interrupt according to the u32Mask parameter. + */ +void SPII2S_DisableInt(SPI_T *i2s, uint32_t u32Mask) +{ + /* Disable TX threshold interrupt flag */ + if ((u32Mask & SPII2S_FIFO_TXTH_INT_MASK) == SPII2S_FIFO_TXTH_INT_MASK) + { + i2s->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Disable RX threshold interrupt flag */ + if ((u32Mask & SPII2S_FIFO_RXTH_INT_MASK) == SPII2S_FIFO_RXTH_INT_MASK) + { + i2s->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Disable RX overrun interrupt flag */ + if ((u32Mask & SPII2S_FIFO_RXOV_INT_MASK) == SPII2S_FIFO_RXOV_INT_MASK) + { + i2s->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Disable RX time-out interrupt flag */ + if ((u32Mask & SPII2S_FIFO_RXTO_INT_MASK) == SPII2S_FIFO_RXTO_INT_MASK) + { + i2s->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk; + } + + /* Disable TX underflow interrupt flag */ + if ((u32Mask & SPII2S_TXUF_INT_MASK) == SPII2S_TXUF_INT_MASK) + { + i2s->FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Disable right channel zero cross interrupt flag */ + if ((u32Mask & SPII2S_RIGHT_ZC_INT_MASK) == SPII2S_RIGHT_ZC_INT_MASK) + { + i2s->I2SCTL &= ~SPI_I2SCTL_RZCIEN_Msk; + } + + /* Disable left channel zero cross interrupt flag */ + if ((u32Mask & SPII2S_LEFT_ZC_INT_MASK) == SPII2S_LEFT_ZC_INT_MASK) + { + i2s->I2SCTL &= ~SPI_I2SCTL_LZCIEN_Msk; + } + + /* Disable slave mode bit clock loss interrupt flag */ + if ((u32Mask & SPII2S_SLV_CLKERR_INT_MASK) == SPII2S_SLV_CLKERR_INT_MASK) + { + i2s->I2SCTL &= ~SPI_I2SCTL_SLVERRIEN_Msk; + } +} + +/** + * @brief Enable master clock (MCLK). + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32BusClock The target MCLK clock rate. + * @return Actual MCLK clock rate + * @details Set the master clock rate according to u32BusClock parameter and enable master clock output. + * The actual master clock rate may be different from the target master clock rate. The real master clock rate will be returned for reference. + */ +uint32_t SPII2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock) +{ + uint32_t u32Divider; + uint32_t u32SrcClk, u32RetValue; + + u32SrcClk = SPII2S_GetSourceClockFreq(i2s); + + if (u32BusClock == u32SrcClk) + { + u32Divider = 0UL; + } + else + { + u32Divider = (u32SrcClk / u32BusClock) >> 1UL; + + /* MCLKDIV is a 7-bit width configuration. The maximum value is 0x7F. */ + if (u32Divider > 0x7FUL) + { + u32Divider = 0x7FUL; + } + } + + /* Write u32Divider to MCLKDIV (SPI_I2SCLK[6:0]) */ + i2s->I2SCLK = (i2s->I2SCLK & ~SPI_I2SCLK_MCLKDIV_Msk) | (u32Divider << SPI_I2SCLK_MCLKDIV_Pos); + + /* Enable MCLK output */ + i2s->I2SCTL |= SPI_I2SCTL_MCLKEN_Msk; + + if (u32Divider == 0UL) + { + u32RetValue = u32SrcClk; /* If MCLKDIV=0, master clock rate is equal to the source clock rate. */ + } + else + { + u32RetValue = ((u32SrcClk >> 1UL) / u32Divider); /* If MCLKDIV>0, master clock rate = source clock rate / (MCLKDIV * 2) */ + } + + return u32RetValue; +} + +/** + * @brief Disable master clock (MCLK). + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details Clear MCLKEN bit of SPI_I2SCTL register to disable master clock output. + */ +void SPII2S_DisableMCLK(SPI_T *i2s) +{ + i2s->I2SCTL &= ~SPI_I2SCTL_MCLKEN_Msk; +} + +/** + * @brief Configure FIFO threshold setting. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32TxThreshold Decides the TX FIFO threshold. + * @param[in] u32RxThreshold Decides the RX FIFO threshold. + * @return None + * @details Set TX FIFO threshold and RX FIFO threshold configurations. + */ +void SPII2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold) +{ + i2s->FIFOCTL = (i2s->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk | SPI_FIFOCTL_RXTH_Msk)) | + (u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) | + (u32RxThreshold << SPI_FIFOCTL_RXTH_Pos); +} + +/*@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_sys.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_sys.c new file mode 100644 index 00000000000..28688e66f96 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_sys.c @@ -0,0 +1,221 @@ +/**************************************************************************** + * @file sys.c + * @version V1.10 + * @brief M251 series SYS driver source file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include "NuMicro.h" +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SYS_Driver SYS Driver + @{ +*/ + + +/** @addtogroup SYS_EXPORTED_FUNCTIONS SYS Exported Functions + @{ +*/ + +/** + * @brief Clear reset source + * @param[in] u32Src is system reset source. Including : + * - \ref SYS_RSTSTS_VBATLVRF_Msk + * - \ref SYS_RSTSTS_CPULKRF_Msk + * - \ref SYS_RSTSTS_CPURF_Msk + * - \ref SYS_RSTSTS_PMURF_Msk + * - \ref SYS_RSTSTS_SYSRF_Msk + * - \ref SYS_RSTSTS_BODRF_Msk + * - \ref SYS_RSTSTS_LVRF_Msk + * - \ref SYS_RSTSTS_WDTRF_Msk + * - \ref SYS_RSTSTS_PINRF_Msk + * - \ref SYS_RSTSTS_PORF_Msk + * @return None + * @details This function clear the selected system reset source. + */ +void SYS_ClearResetSrc(uint32_t u32Src) +{ + SYS->RSTSTS |= u32Src; +} + +/** + * @brief Get Brown-out detector output status + * @param None + * @retval 0 System voltage is higher than BOD_VL setting or BOD_EN is 0. + * @retval 1 System voltage is lower than BOD_VL setting. + * @details This function get Brown-out detector output status. + */ +uint32_t SYS_GetBODStatus(void) +{ + return ((SYS->BODCTL & SYS_BODCTL_BODOUT_Msk) >> SYS_BODCTL_BODOUT_Pos); +} + +/** + * @brief Get reset status register value + * @param None + * @return Reset source + * @details This function get the system reset status register value. + */ +uint32_t SYS_GetResetSrc(void) +{ + return (SYS->RSTSTS); +} + +/** + * @brief Check if register is locked nor not + * @param None + * @retval 0 Write-protection function is disabled. + * 1 Write-protection function is enabled. + * @details This function check register write-protection bit setting. + */ +uint32_t SYS_IsRegLocked(void) +{ + return !(SYS->REGLCTL & 0x1UL); +} + +/** + * @brief Get product ID + * @param None + * @return Product ID + * @details This function get product ID. + */ +uint32_t SYS_ReadPDID(void) +{ + return SYS->PDID; +} + +/** + * @brief Reset chip with chip reset + * @param None + * @return None + * @details This function reset chip with chip reset. + * The register write-protection function should be disabled before using this function. + */ +void SYS_ResetChip(void) +{ + SYS->IPRST0 |= SYS_IPRST0_CHIPRST_Msk; +} + +/** + * @brief Reset chip with CPU reset + * @param None + * @return None + * @details This function reset CPU with CPU reset. + * The register write-protection function should be disabled before using this function. + */ +void SYS_ResetCPU(void) +{ + SYS->IPRST0 |= SYS_IPRST0_CPURST_Msk; +} + +/** + * @brief Reset selected module + * @param[in] u32ModuleIndex is module index. Including : + * - \ref PDMA_RST + * - \ref EBI_RST + * - \ref CRC_RST + * - \ref CRPT_RST + * - \ref GPIO_RST + * - \ref TMR0_RST + * - \ref TMR1_RST + * - \ref TMR2_RST + * - \ref TMR3_RST + * - \ref ACMP01_RST + * - \ref I2C0_RST + * - \ref I2C1_RST + * - \ref QSPI0_RST + * - \ref SPI0_RST + * - \ref UART0_RST + * - \ref UART1_RST + * - \ref UART2_RST + * - \ref USBD_RST + * - \ref EADC_RST + * - \ref SC0_RST + * - \ref USCI0_RST + * - \ref USCI1_RST + * - \ref USCI2_RST + * - \ref DAC_RST + * - \ref PWM0_RST + * - \ref PWM1_RST + * - \ref BPWM0_RST + * - \ref BPWM1_RST + * - \ref OPA_RST + * - \ref PSIO_RST + * @return None + * @details This function reset selected module. + */ +void SYS_ResetModule(uint32_t u32ModuleIndex) +{ + /* Generate reset signal to the corresponding module */ + *(volatile uint32_t *)((uint32_t)&SYS->IPRST0 + (u32ModuleIndex >> 24UL)) |= 1UL << (u32ModuleIndex & 0x00ffffffUL); + + /* Release corresponding module from reset state */ + *(volatile uint32_t *)((uint32_t)&SYS->IPRST0 + (u32ModuleIndex >> 24UL)) &= ~(1UL << (u32ModuleIndex & 0x00ffffffUL)); +} + + +/** + * @brief Enable and configure Brown-out detector function + * @param[in] i32Mode is reset or interrupt mode. Including : + * - \ref SYS_BODCTL_BOD_RST_EN + * - \ref SYS_BODCTL_BOD_INTERRUPT_EN + * @param[in] u32BODLevel is Brown-out voltage level. Including : + * - \ref SYS_BODCTL_BODVL_4_4V + * - \ref SYS_BODCTL_BODVL_3_7V + * - \ref SYS_BODCTL_BODVL_3_0V + * - \ref SYS_BODCTL_BODVL_2_7V + * - \ref SYS_BODCTL_BODVL_2_4V + * - \ref SYS_BODCTL_BODVL_2_0V + * - \ref SYS_BODCTL_BODVL_1_8V + * @return None + * @details This function configure Brown-out detector reset or interrupt mode, enable Brown-out function and set Brown-out voltage level. + * The register write-protection function should be disabled before using this function. + */ +void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel) +{ + /* Enable Brown-out Detector function */ + SYS->BODCTL |= SYS_BODCTL_BODEN_Msk; + + /* Enable Brown-out interrupt or reset function */ + SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODRSTEN_Msk) | i32Mode; + + /* Select Brown-out Detector threshold voltage */ + SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | u32BODLevel; +} + +/** + * @brief Disable Brown-out detector function + * @param None + * @return None + * @details This function disable Brown-out detector function. + * The register write-protection function should be disabled before using this function. + */ +void SYS_DisableBOD(void) +{ + SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk; +} + +/** + * @brief Set Power Level + * @param[in] u32PowerLevel is power level setting. Including : + * - \ref SYS_PLCTL_PLSEL_PL0 + * - \ref SYS_PLCTL_PLSEL_PL2 + * @return None + * @details This function select power level. + * The register write-protection function should be disabled before using this function. + */ +void SYS_SetPowerLevel(uint32_t u32PowerLevel) +{ + /* Set power voltage level */ + SYS->PLCTL = (SYS->PLCTL & (~SYS_PLCTL_PLSEL_Msk)) | (u32PowerLevel); +} + +/*@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SYS_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_timer.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_timer.c new file mode 100644 index 00000000000..7f97af8e189 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_timer.c @@ -0,0 +1,413 @@ +/**************************************************************************//** + * @file timer.c + * @version V3.01 + * @brief M251 series Timer Controller(Timer) driver source file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup TIMER_Driver TIMER Driver + @{ +*/ + +/** @addtogroup TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions + @{ +*/ + +/** + * @brief Open Timer with Operate Mode and Frequency + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Mode Operation mode. Possible options are + * - \ref TIMER_ONESHOT_MODE + * - \ref TIMER_PERIODIC_MODE + * - \ref TIMER_TOGGLE_MODE + * - \ref TIMER_CONTINUOUS_MODE + * @param[in] u32Freq Target working frequency + * + * @return Real timer working frequency + * + * @details This API is used to configure timer to operate in specified mode and frequency. + * If timer cannot work in target frequency, a closest frequency will be chose and returned. + * @note After calling this API, Timer is \b NOT running yet. But could start timer running be calling + * \ref TIMER_Start macro or program registers directly. + */ +uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq) +{ + uint32_t u32Clk = TIMER_GetModuleClock(timer); + uint32_t u32Cmpr = 0UL, u32Prescale = 0UL; + + // Fastest possible timer working freq is (u32Clk / 2). While cmpr = 2, pre-scale = 0. + if (u32Freq > (u32Clk / 2UL)) + { + u32Cmpr = 2UL; + } + else + { + if (u32Clk > 64000000UL) + { + u32Prescale = 7UL; // real prescaler value is 8 + u32Clk >>= 3; + } + else if (u32Clk > 32000000UL) + { + u32Prescale = 3UL; // real prescaler value is 4 + u32Clk >>= 2; + } + else if (u32Clk > 16000000UL) + { + u32Prescale = 1UL; // real prescaler value is 2 + u32Clk >>= 1; + } + + u32Cmpr = u32Clk / u32Freq; + } + + timer->CTL = u32Mode | u32Prescale; + timer->CMP = u32Cmpr; + + return (u32Clk / (u32Cmpr * (u32Prescale + 1UL))); +} + +/** + * @brief Stop Timer Counting + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This API stops timer counting and disable all timer interrupt function. + */ +void TIMER_Close(TIMER_T *timer) +{ + timer->CTL = 0UL; + timer->EXTCTL = 0UL; +} + +/** + * @brief Create a specify Delay Time + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Usec Delay period in micro seconds. Valid values are between 100~1000000 (100 micro second ~ 1 second). + * + * @return None + * + * @details This API is used to create a delay loop for u32usec micro seconds by using timer one-shot mode. + * @note This API overwrites the register setting of the timer used to count the delay time. + * @note This API use polling mode. So there is no need to enable interrupt for the timer module used to generate delay. + */ +void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec) +{ + uint32_t u32Clk = TIMER_GetModuleClock(timer); + uint32_t u32Prescale = 0UL, u32Delay = (SystemCoreClock / u32Clk) + 1UL; + uint32_t u32Cmpr, u32NsecPerTick; + + // Clear current timer configuration/ + timer->CTL = 0UL; + timer->EXTCTL = 0UL; + + if (u32Clk <= 1000000UL) // min delay is 1000 us if timer clock source is <= 1 MHz + { + if (u32Usec < 1000UL) + u32Usec = 1000UL; + + if (u32Usec > 1000000UL) + u32Usec = 1000000UL; + } + else + { + if (u32Usec < 100UL) + u32Usec = 100UL; + + if (u32Usec > 1000000UL) + u32Usec = 1000000UL; + } + + if (u32Clk <= 1000000UL) + { + u32Prescale = 0UL; + u32NsecPerTick = 1000000000UL / u32Clk; + u32Cmpr = (u32Usec * 1000UL) / u32NsecPerTick; + } + else + { + if (u32Clk > 64000000UL) + { + u32Prescale = 7UL; // real prescaler value is 8 + u32Clk >>= 3; + } + else if (u32Clk > 32000000UL) + { + u32Prescale = 3UL; // real prescaler value is 4 + u32Clk >>= 2; + } + else if (u32Clk > 16000000UL) + { + u32Prescale = 1UL; // real prescaler value is 2 + u32Clk >>= 1; + } + + if (u32Usec < 250UL) + { + u32Cmpr = (u32Usec * u32Clk) / 1000000UL; + } + else + { + u32NsecPerTick = 1000000000UL / u32Clk; + u32Cmpr = (u32Usec * 1000UL) / u32NsecPerTick; + } + } + + timer->CMP = u32Cmpr; + timer->CTL = TIMER_CTL_CNTEN_Msk | TIMER_ONESHOT_MODE | u32Prescale; + + // When system clock is faster than timer clock, it is possible timer active bit cannot set in time while we check it. + // And the while loop below return immediately, so put a tiny delay here allowing timer start counting and raise active flag. + for (; u32Delay > 0UL; u32Delay--) + { + __NOP(); + } + + while (timer->CTL & TIMER_CTL_ACTSTS_Msk) + { + } +} + +/** + * @brief Enable Timer Capture Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32CapMode Timer capture mode. Could be + * - \ref TIMER_CAPTURE_FREE_COUNTING_MODE + * - \ref TIMER_CAPTURE_COUNTER_RESET_MODE + * @param[in] u32Edge Timer capture trigger edge. Possible values are + * - \ref TIMER_CAPTURE_EVENT_FALLING + * - \ref TIMER_CAPTURE_EVENT_RISING + * - \ref TIMER_CAPTURE_EVENT_FALLING_RISING + * - \ref TIMER_CAPTURE_EVENT_RISING_FALLING + * - \ref TIMER_CAPTURE_EVENT_GET_LOW_PERIOD + * - \ref TIMER_CAPTURE_EVENT_GET_HIGH_PERIOD + * + * @return None + * + * @details This API is used to enable timer capture function with specify capture trigger edge \n + * to get current counter value or reset counter value to 0. + * @note Timer frequency should be configured separately by using \ref TIMER_Open API, or program registers directly. + */ +void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge) +{ + timer->EXTCTL = (timer->EXTCTL & ~(TIMER_EXTCTL_CAPFUNCS_Msk | TIMER_EXTCTL_CAPEDGE_Msk)) | + u32CapMode | u32Edge | TIMER_EXTCTL_CAPEN_Msk; +} + +/** + * @brief Select Timer Capture Source + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Src Timer capture source. Possible values are + * - \ref TIMER_CAPTURE_FROM_EXTERNAL + * - \ref TIMER_CAPTURE_FROM_INTERNAL + * + * @return None + * + * @details This API is used to select timer capture source from Tx_EXT or internal singal. + */ +void TIMER_CaptureSelect(TIMER_T *timer, uint32_t u32Src) +{ + timer->CTL = (timer->CTL & (~TIMER_CTL_CAPSRC_Msk)) | u32Src; +} + +/** + * @brief Disable Timer Capture Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This API is used to disable the timer capture function. + */ +void TIMER_DisableCapture(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CAPEN_Msk; +} + +/** + * @brief Set Timer Trigger Source + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Src Selects the interrupt source to trigger other modules. Could be: + * - \ref TIMER_TRGSEL_TIMEOUT_EVENT + * - \ref TIMER_TRGSEL_CAPTURE_EVENT + * + * @return None + * + * @details This function is used to set timer trigger source + */ +void TIMER_SetTriggerSource(TIMER_T *timer, uint32_t u32Src) +{ + timer->TRGCTL = (timer->TRGCTL & ~TIMER_TRGCTL_TRGSSEL_Msk) | u32Src; +} + +/** + * @brief Set Timer Trigger Target + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Mask The mask of modules (PWM/BPWM/DAC/EADC/PDMA) trigger by timer, the combination of + * - \ref TIMER_TRGCTL_TRGPWM_Msk, or + * - \ref TIMER_TRGCTL_TRGDAC_Msk, or + * - \ref TIMER_TRGCTL_TRGEADC_Msk, or + * - \ref TIMER_TRGCTL_TRGPDMA_Msk + * + * @return None + * + * @details This function is used to set timer trigger target + */ +void TIMER_SetTriggerTarget(TIMER_T *timer, uint32_t u32Mask) +{ + timer->TRGCTL = (timer->TRGCTL & ~(TIMER_TRGCTL_TRGPWM_Msk | TIMER_TRGCTL_TRGDAC_Msk | TIMER_TRGCTL_TRGEADC_Msk | TIMER_TRGCTL_TRGPDMA_Msk)) | u32Mask; +} + +/** + * @brief Enable Timer Counter Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Edge Detection edge of counter pin. Could be ether + * - \ref TIMER_COUNTER_EVENT_FALLING, or + * - \ref TIMER_COUNTER_EVENT_RISING + * + * @return None + * + * @details This function is used to enable the timer counter function with specify detection edge. + * @note Timer compare value should be configured separately by using \ref TIMER_SET_CMP_VALUE macro or program registers directly. + * @note While using event counter function, \ref TIMER_TOGGLE_MODE cannot set as timer operation mode. + */ +void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge) +{ + timer->EXTCTL = (timer->EXTCTL & ~TIMER_EXTCTL_CNTPHASE_Msk) | u32Edge; + timer->CTL |= TIMER_CTL_EXTCNTEN_Msk; +} + +/** + * @brief Disable Timer Counter Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This API is used to disable the timer event counter function. + */ +void TIMER_DisableEventCounter(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_EXTCNTEN_Msk; +} + +/** + * @brief Enable Timer Frequency Counter Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32DropCount This parameter has no effect in this BSP + * @param[in] u32Timeout This parameter has no effect in this BSP + * @param[in] u32EnableInt Enable interrupt assertion after capture complete or not. Valid values are TRUE and FALSE + * + * @return None + * + * @details This function is used to enable the Timer frequency counter function for + * calculate input event frequency. After enable this function, a pair of timers, + * TIMER0 and TIMER1, or TIMER2 and TIMER3 will be configured for this function. + * The mode used to calculate input event frequency is mentioned as + * "Inter Timer Trigger Mode" in Technical Reference Manual. + */ +void TIMER_EnableFreqCounter(TIMER_T *timer, + uint32_t u32DropCount, + uint32_t u32Timeout, + uint32_t u32EnableInt) +{ + TIMER_T *ptimerTmp; /* store the timer base to configure compare value */ + + if (timer == TIMER0) + { + ptimerTmp = TIMER1; + } + else if (timer == TIMER2) + { + ptimerTmp = TIMER3; + } + else + { + ptimerTmp = 0UL ; + } + + if (ptimerTmp != 0UL) + { + ptimerTmp->CMP = 0xFFFFFFUL; + ptimerTmp->EXTCTL = u32EnableInt ? TIMER_EXTCTL_CAPIEN_Msk : 0UL; + timer->CTL = TIMER_CTL_INTRGEN_Msk | TIMER_CTL_CNTEN_Msk; + } +} + +/** + * @brief Disable Timer Frequency Counter Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @brief This function is used to disable the Timer frequency counter function. + */ +void TIMER_DisableFreqCounter(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_INTRGEN_Msk; +} + +/** + * @brief Get Timer Clock Frequency + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return Timer clock frequency + * + * @details This API is used to get the timer clock frequency. + * @note This API cannot return correct clock rate if timer source is from external clock input. + */ +uint32_t TIMER_GetModuleClock(TIMER_T *timer) +{ + uint32_t u32Src; + const uint32_t au32Clk[] = {__HXT, __LXT, 0UL, 0UL, 0UL, __LIRC, 0UL, __HIRC}; + + if (timer == TIMER0) + u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR0SEL_Msk) >> CLK_CLKSEL1_TMR0SEL_Pos; + else if (timer == TIMER1) + u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR1SEL_Msk) >> CLK_CLKSEL1_TMR1SEL_Pos; + else if (timer == TIMER2) + u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR2SEL_Msk) >> CLK_CLKSEL1_TMR2SEL_Pos; + else // Timer 3 + u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR3SEL_Msk) >> CLK_CLKSEL1_TMR3SEL_Pos; + + if (u32Src == 2UL) + { + if((timer == TIMER0) || (timer == TIMER1)) + { + return CLK_GetPCLK0Freq(); + } + else + { + return CLK_GetPCLK1Freq(); + } + } + + return (au32Clk[u32Src]); +} + +/*@}*/ /* end of group TIMER_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group TIMER_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_timer_pwm.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_timer_pwm.c new file mode 100644 index 00000000000..fac1d98bf09 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_timer_pwm.c @@ -0,0 +1,159 @@ +/**************************************************************************//** + * @file timer.c + * @version V3.01 + * @brief Timer PWM Controller(Timer PWM) driver source file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup TIMER_PWM_Driver TIMER PWM Driver + @{ +*/ + +/** @addtogroup TIMER_PWM_EXPORTED_FUNCTIONS TIMER PWM Exported Functions + @{ +*/ + +/** + * @brief Configure TPWM Output Frequency and Duty Cycle + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Frequency Target generator frequency. + * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0~100. 10 means 10%, 20 means 20%... + * + * @return Nearest frequency clock in nano second + * + * @details This API is used to configure TPWM output frequency and duty cycle in up count type and auto-reload operation mode. + * @note This API is only available if Timer PWM counter clock source is from TMRx_CLK. + */ +uint32_t TPWM_ConfigOutputFreqAndDuty(TIMER_T *timer, uint32_t u32Frequency, uint32_t u32DutyCycle) +{ + uint32_t u32PWMClockFreq, u32TargetFreq; + uint32_t u32Prescaler = 0x100UL, u32Period, u32CMP; + + if((timer == TIMER0) || (timer == TIMER1)) + { + u32PWMClockFreq = CLK_GetPCLK0Freq(); + } + else + { + u32PWMClockFreq = CLK_GetPCLK1Freq(); + } + + /* Calculate u8PERIOD and u8PSC */ + for (u32Prescaler = 1; u32Prescaler <= 0x100UL; u32Prescaler++) + { + u32Period = (u32PWMClockFreq / u32Prescaler) / u32Frequency; + + /* If target u32Period is larger than 0x10000, need to use a larger prescaler */ + if (u32Period > 0x10000UL) + continue; + + break; + } + + /* Store return value here 'cos we're gonna change u32Prescaler & u32Period to the real value to fill into register */ + u32TargetFreq = (u32PWMClockFreq / u32Prescaler) / u32Period; + + /* Set PWM to auto-reload mode */ + timer->PWMCTL = (timer->PWMCTL & ~TIMER_PWMCTL_CNTMODE_Msk) | (TPWM_AUTO_RELOAD_MODE << TIMER_PWMCTL_CNTMODE_Pos); + + /* Convert to real register value */ + TPWM_SET_PRESCALER(timer, (u32Prescaler - 1UL)); + + TPWM_SET_PERIOD(timer, (u32Period - 1UL)); + + if (u32DutyCycle) + { + u32CMP = (u32DutyCycle * u32Period) / 100UL; + } + else + { + u32CMP = 0UL; + } + + TPWM_SET_CMPDAT(timer, u32CMP); + return (u32TargetFreq); +} + +/** + * @brief Enable TPWM Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable TPWM generator and start counter counting. + */ +void TPWM_EnableCounter(TIMER_T *timer) +{ + timer->PWMCTL |= TIMER_PWMCTL_CNTEN_Msk; +} + +/** + * @brief Disable TPWM Generator + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable TPWM counter immediately by clear CNTEN (TIMERx_PWMCTL[0]) bit. + */ +void TPWM_DisableCounter(TIMER_T *timer) +{ + timer->PWMCTL &= ~TIMER_PWMCTL_CNTEN_Msk; +} + +/** + * @brief Enable TPWM Trigger ADC/DAC/PDMA + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32TargetMask The mask of modules (DAC/EADC/PDMA) trigger by TPWM, the combination of: + * - \ref TIMER_PWMTRGCTL_PWMTRGDAC_Msk + * - \ref TIMER_PWMTRGCTL_PWMTRGEADC_Msk + * - \ref TIMER_PWMTRGCTL_PWMTRGPDMA_Msk + * @param[in] u32Condition The condition to trigger ADC/DAC/PDMA. It could be one of following conditions: + * - \ref TPWM_TRIGGER_AT_PERIOD_POINT + * - \ref TPWM_TRIGGER_AT_COMPARE_POINT + * - \ref TPWM_TRIGGER_AT_PERIOD_OR_COMPARE_POINT + * @return None + * + * @details This function is used to enable specified counter event to trigger ADC/DAC/PDMA. + */ +void TPWM_EnableTrigger(TIMER_T *timer, uint32_t u32TargetMask, uint32_t u32Condition) +{ + timer->PWMTRGCTL &= ~(TIMER_PWMTRGCTL_PWMTRGDAC_Msk | TIMER_PWMTRGCTL_PWMTRGEADC_Msk | TIMER_PWMTRGCTL_PWMTRGPDMA_Msk | TIMER_PWMTRGCTL_TRGSEL_Msk); + timer->PWMTRGCTL |= (u32TargetMask) | (u32Condition); +} + +/** + * @brief Disable Trigger ADC/DAC/PDMA + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32TargetMask The mask of modules (DAC/EADC/PDMA) trigger by TPWM, the combination of: + * - \ref TIMER_PWMTRGCTL_PWMTRGDAC_Msk + * - \ref TIMER_PWMTRGCTL_PWMTRGEADC_Msk + * - \ref TIMER_PWMTRGCTL_PWMTRGPDMA_Msk + * + * @return None + * + * @details This function is used to disable counter event to trigger ADC/DAC/PDMA. + */ +void TPWM_DisableTrigger(TIMER_T *timer, uint32_t u32TargetMask) +{ + timer->PWMTRGCTL &= ~(u32TargetMask); +} + +/*@}*/ /* end of group TIMER_PWM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group TIMER_PWM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_uart.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_uart.c new file mode 100644 index 00000000000..79c7d90b7d4 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_uart.c @@ -0,0 +1,659 @@ +/**************************************************************************** + * @file uart.c + * @version V1.00 + * @brief M251 series UART driver source file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ + +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup UART_Driver UART Driver + @{ +*/ + +/** @addtogroup UART_EXPORTED_FUNCTIONS UART Exported Functions + @{ +*/ + +/** + * @brief Clear UART specified interrupt flag + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32InterruptFlag The specified interrupt of UART module. + * - \ref UART_INTSTS_SWBEINT_Msk : Single-wire Bit Error Detect Interrupt + * - \ref UART_INTSTS_LININT_Msk : LIN bus interrupt + * - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt + * - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error interrupt + * - \ref UART_INTSTS_MODEMINT_Msk : Modem Status interrupt + * - \ref UART_INTSTS_RLSINT_Msk : Receive Line Status interrupt + * + * @return None + * + * @details The function is used to clear UART specified interrupt flag. + */ + +void UART_ClearIntFlag(UART_T *uart, uint32_t u32InterruptFlag) +{ + + + if (u32InterruptFlag & UART_INTSTS_SWBEINT_Msk) /* Clear Bit Error Detection Interrupt */ + { + uart->FIFOSTS = UART_INTSTS_SWBEIF_Msk; + } + + if (u32InterruptFlag & UART_INTSTS_RLSINT_Msk) /* Clear Receive Line Status Interrupt */ + { + uart->FIFOSTS = UART_FIFOSTS_BIF_Msk | UART_FIFOSTS_FEF_Msk | UART_FIFOSTS_FEF_Msk; + uart->FIFOSTS = UART_FIFOSTS_ADDRDETF_Msk; + } + + if (u32InterruptFlag & UART_INTSTS_MODEMINT_Msk) /* Clear Modem Status Interrupt */ + { + uart->MODEMSTS |= UART_MODEMSTS_CTSDETF_Msk; + } + + if (u32InterruptFlag & UART_INTSTS_BUFERRINT_Msk) /* Clear Buffer Error Interrupt */ + { + uart->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk | UART_FIFOSTS_TXOVIF_Msk; + } + + if (u32InterruptFlag & UART_INTSTS_WKINT_Msk) /* Clear Wake-up Interrupt */ + { + uart->WKSTS = UART_WKSTS_CTSWKF_Msk | UART_WKSTS_DATWKF_Msk | + UART_WKSTS_RFRTWKF_Msk | UART_WKSTS_RS485WKF_Msk | + UART_WKSTS_TOUTWKF_Msk; + } + + if (u32InterruptFlag & UART_INTSTS_LININT_Msk) /* Clear LIN Bus Interrupt */ + { + uart->INTSTS = UART_INTSTS_LINIF_Msk; + uart->LINSTS = UART_LINSTS_BITEF_Msk | UART_LINSTS_BRKDETF_Msk | + UART_LINSTS_SLVSYNCF_Msk | UART_LINSTS_SLVIDPEF_Msk | + UART_LINSTS_SLVHEF_Msk | UART_LINSTS_SLVHDETF_Msk ; + } +} + + +/** + * @brief Disable UART interrupt + * + * @param[in] uart The pointer of the specified UART module. + * + * @return None + * + * @details The function is used to disable UART interrupt. + */ +void UART_Close(UART_T *uart) +{ + uart->INTEN = 0ul; +} + + +/** + * @brief Disable UART auto flow control function + * + * @param[in] uart The pointer of the specified UART module. + * + * @return None + * + * @details The function is used to disable UART auto flow control. + */ +void UART_DisableFlowCtrl(UART_T *uart) +{ + uart->INTEN &= ~(UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk); +} + + +/** + * @brief Disable UART specified interrupt + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32InterruptFlag The specified interrupt of UART module. + * - \ref UART_INTSTS_SWBEINT_Msk : Single-wire Bit Error Detect Interrupt + * - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt + * - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt + * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt + * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt + * - \ref UART_INTEN_MODEMIEN_Msk : Modem status interrupt + * - \ref UART_INTEN_RLSIEN_Msk : Receive Line status interrupt + * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt + * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt * + * + * @return None + * + * @details The function is used to disable UART specified interrupt and disable NVIC UART IRQ. + */ +void UART_DisableInt(UART_T *uart, uint32_t u32InterruptFlag) +{ + /* Disable UART specified interrupt */ + UART_DISABLE_INT(uart, u32InterruptFlag); +} + + +/** + * @brief Enable UART auto flow control function + * + * @param[in] uart The pointer of the specified UART module. + * + * @return None + * + * @details The function is used to Enable UART auto flow control. + */ +void UART_EnableFlowCtrl(UART_T *uart) +{ + /* Set RTS pin output is low level active */ + uart->MODEM |= UART_MODEM_RTSACTLV_Msk; + + /* Set CTS pin input is low level active */ + uart->MODEMSTS |= UART_MODEMSTS_CTSACTLV_Msk; + + /* Set RTS and CTS auto flow control enable */ + uart->INTEN |= UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk; +} + + +/** + * @brief The function is used to enable UART specified interrupt and enable NVIC UART IRQ. + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32InterruptFlag The specified interrupt of UART module: + * - \ref UART_INTSTS_SWBEINT_Msk : Single-wire Bit Error Detect Interrupt + * - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt + * - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt + * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt + * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt + * - \ref UART_INTEN_MODEMIEN_Msk : Modem status interrupt + * - \ref UART_INTEN_RLSIEN_Msk : Receive Line status interrupt + * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt + * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt * + * + * @return None + * + * @details The function is used to enable UART specified interrupt and enable NVIC UART IRQ. + */ +void UART_EnableInt(UART_T *uart, uint32_t u32InterruptFlag) +{ + /* Enable UART specified interrupt */ + UART_ENABLE_INT(uart, u32InterruptFlag); +} + + +/** + * @brief Open and set UART function + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32BaudRate The baud rate of UART module. + * + * @return None + * + * @details This function use to enable UART function and set baud-rate. + */ +void UART_Open(UART_T *uart, uint32_t u32BaudRate) +{ + uint32_t u32UartClkSrcSel = 0ul, u32UartClkDivNum = 0ul; + uint32_t au32ClkTbl[6ul] = {__HXT, 0ul, __LXT, __HIRC, 0ul, __LIRC}; + uint32_t u32Baud_Div = 0ul; + + + if (uart == (UART_T *)UART0) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = ((uint32_t)(CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk)) >> CLK_CLKSEL1_UART0SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos; + } + else if (uart == (UART_T *)UART1) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos; + } + else if (uart == (UART_T *)UART2) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos; + } + else {} + + /* Select UART function */ + uart->FUNCSEL = UART_FUNCSEL_UART; + + /* Set UART line configuration */ + uart->LINE = UART_WORD_LEN_8 | UART_PARITY_NONE | UART_STOP_BIT_1; + + /* Set UART Rx and RTS trigger level */ + uart->FIFO &= ~(UART_FIFO_RFITL_Msk | UART_FIFO_RTSTRGLV_Msk); + + /* Get PLL clock frequency if UART clock source selection is PLL */ + if (u32UartClkSrcSel == 1ul) + { + au32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq(); + } + + /* Get PCLK clock frequency if UART clock source selection is PCLK */ + if (u32UartClkSrcSel == 4ul) + { + /* UART Port as UART0 or UART1 */ + if ((uart == (UART_T *)UART0) || (uart == (UART_T *)UART2)) + { + au32ClkTbl[u32UartClkSrcSel] = CLK_GetPCLK0Freq(); + } + else /* UART Port as UART1*/ + { + au32ClkTbl[u32UartClkSrcSel] = CLK_GetPCLK1Freq(); + } + + } + + /* Set UART baud rate */ + if (u32BaudRate != 0ul) + { + u32Baud_Div = UART_BAUD_MODE2_DIVIDER((au32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32BaudRate); + + if (u32Baud_Div > 0xFFFFul) + { + uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((au32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32BaudRate)); + } + else + { + uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div); + } + } +} + + +/** + * @brief Read UART data + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] pu8RxBuf The buffer to receive the data of receive FIFO. + * @param[in] u32ReadBytes The the read bytes number of data. + * + * @return u32Count Receive byte count + * + * @details The function is used to read Rx data from RX FIFO and the data will be stored in pu8RxBuf. + */ +uint32_t UART_Read(UART_T *uart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes) +{ + uint32_t u32Count, u32DelayNum; + uint32_t u32Exit = 0ul; + + for (u32Count = 0ul; u32Count < u32ReadBytes; u32Count++) + { + u32DelayNum = 0ul; + + while (uart->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) /* Check RX empty => failed */ + { + u32DelayNum++; + + if (u32DelayNum >= 0x40000000ul) + { + u32Exit = 1ul; + break; + } + else + { + } + } + + if (u32Exit == 1ul) + { + break; + } + else + { + pu8RxBuf[u32Count] = (uint8_t)uart->DAT; /* Get Data from UART RX */ + } + } + + return u32Count; + +} + + +/** + * @brief Set UART line configuration + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32BaudRate The register value of baudrate of UART module. + * If u32BaudRate = 0, UART baudrate will not change. + * @param[in] u32DataWidth The data length of UART module. + * - \ref UART_WORD_LEN_5 + * - \ref UART_WORD_LEN_6 + * - \ref UART_WORD_LEN_7 + * - \ref UART_WORD_LEN_8 + * @param[in] u32Parity The parity setting (none/odd/even/mark/space) of UART module. + * - \ref UART_PARITY_NONE + * - \ref UART_PARITY_ODD + * - \ref UART_PARITY_EVEN + * - \ref UART_PARITY_MARK + * - \ref UART_PARITY_SPACE + * @param[in] u32StopBits The stop bit length (1/1.5/2 bit) of UART module. + * - \ref UART_STOP_BIT_1 + * - \ref UART_STOP_BIT_1_5 + * - \ref UART_STOP_BIT_2 + * + * @return None + * + * @details This function use to config UART line setting. + */ +void UART_SetLine_Config(UART_T *uart, uint32_t u32BaudRate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits) +{ + uint32_t u32UartClkSrcSel = 0ul, u32UartClkDivNum = 0ul; + uint32_t au32ClkTbl[6ul] = {__HXT, 0ul, __LXT, __HIRC, 0, __LIRC}; + uint32_t u32Baud_Div = 0ul; + + + if (uart == (UART_T *)UART0) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk) >> CLK_CLKSEL1_UART0SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos; + } + else if (uart == (UART_T *)UART1) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos; + } + else if (uart == (UART_T *)UART2) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos; + } + else {} + + /* Get PLL clock frequency if UART clock source selection is PLL */ + if (u32UartClkSrcSel == 1ul) + { + au32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq(); + } + + /* Get PCLK clock frequency if UART clock source selection is PCLK */ + if (u32UartClkSrcSel == 4ul) + { + if ((uart == (UART_T *)UART0) || (uart == (UART_T *)UART2)) + { + au32ClkTbl[u32UartClkSrcSel] = CLK_GetPCLK0Freq(); + } + else /* UART Port as UART1*/ + { + au32ClkTbl[u32UartClkSrcSel] = CLK_GetPCLK1Freq(); + } + } + + + /* Set UART baud rate */ + if (u32BaudRate != 0ul) + { + u32Baud_Div = UART_BAUD_MODE2_DIVIDER((au32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32BaudRate); + + if (u32Baud_Div > 0xFFFFul) + { + uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((au32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32BaudRate)); + } + else + { + uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div); + } + } + + /* Set UART line configuration */ + uart->LINE = u32DataWidth | u32Parity | u32StopBits; +} + + +/** + * @brief Set Rx timeout count + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32TOC Rx timeout counter. + * + * @return None + * + * @details This function use to set Rx timeout count. + */ +void UART_SetTimeoutCnt(UART_T *uart, uint32_t u32TOC) +{ + /* Set time-out interrupt comparator */ + uart->TOUT = (uart->TOUT & ~UART_TOUT_TOIC_Msk) | (u32TOC); + + /* Set time-out counter enable */ + uart->INTEN |= UART_INTEN_TOCNTEN_Msk; +} + + +/** + * @brief Select and configure IrDA function + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32BuadRate The baud rate of UART module. + * @param[in] u32Direction The direction of UART module in IrDA mode: + * - \ref UART_IRDA_TXEN + * - \ref UART_IRDA_RXEN + * + * @return None + * + * @details The function is used to configure IrDA relative settings. It consists of TX or RX mode and baudrate. + */ +void UART_SelectIrDAMode(UART_T *uart, uint32_t u32BuadRate, uint32_t u32Direction) +{ + uint32_t u32UartClkSrcSel = 0ul, u32UartClkDivNum = 0ul; + uint32_t au32ClkTbl[6ul] = {__HXT, 0ul, __LXT, __HIRC, 0ul, __LIRC}; + uint32_t u32Baud_Div; + + /* Select IrDA function mode */ + uart->FUNCSEL = UART_FUNCSEL_IrDA; + + + if (uart == UART0) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk) >> CLK_CLKSEL1_UART0SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos; + } + else if (uart == UART1) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos; + } + else if (uart == UART2) + { + /* Get UART clock source selection */ + u32UartClkSrcSel = (CLK->CLKSEL3 & CLK_CLKSEL3_UART2SEL_Msk) >> CLK_CLKSEL3_UART2SEL_Pos; + /* Get UART clock divider number */ + u32UartClkDivNum = (CLK->CLKDIV4 & CLK_CLKDIV4_UART2DIV_Msk) >> CLK_CLKDIV4_UART2DIV_Pos; + } + else + { + } + + + /* Get PLL clock frequency if UART clock source selection is PLL */ + if (u32UartClkSrcSel == 1ul) + { + au32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq(); + } + + /* Get PCLK clock frequency if UART clock source selection is PCLK */ + if (u32UartClkSrcSel == 4ul) + { + if ((uart == (UART_T *)UART0) || (uart == (UART_T *)UART2)) + { + au32ClkTbl[u32UartClkSrcSel] = CLK_GetPCLK0Freq(); + } + else /* UART Port as UART1*/ + { + au32ClkTbl[u32UartClkSrcSel] = CLK_GetPCLK1Freq(); + } + } + + + /* Set UART IrDA baud rate in mode 0 */ + if (u32BuadRate != 0ul) + { + u32Baud_Div = UART_BAUD_MODE0_DIVIDER((au32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32BuadRate); + + if (u32Baud_Div < 0xFFFFul) + { + uart->BAUD = (UART_BAUD_MODE0 | u32Baud_Div); + } + else + { + } + } + + /* Configure IrDA relative settings */ + if (u32Direction == UART_IRDA_RXEN) + { + uart->IRDA |= UART_IRDA_RXINV_Msk; /*Rx signal is inverse*/ + uart->IRDA &= ~UART_IRDA_TXEN_Msk; + } + else + { + uart->IRDA &= ~UART_IRDA_TXINV_Msk; /*Tx signal is not inverse*/ + uart->IRDA |= UART_IRDA_TXEN_Msk; + } + +} + + +/** + * @brief Select and configure RS485 function + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32Mode The operation mode(NMM/AUD/AAD). + * - \ref UART_ALTCTL_RS485NMM_Msk + * - \ref UART_ALTCTL_RS485AUD_Msk + * - \ref UART_ALTCTL_RS485AAD_Msk + * @param[in] u32Addr The RS485 address. + * + * @return None + * + * @details The function is used to set RS485 relative setting. + */ +void UART_SelectRS485Mode(UART_T *uart, uint32_t u32Mode, uint32_t u32Addr) +{ + /* Select UART RS485 function mode */ + uart->FUNCSEL = UART_FUNCSEL_RS485; + + /* Set RS585 configuration */ + uart->ALTCTL &= ~(UART_ALTCTL_RS485NMM_Msk | UART_ALTCTL_RS485AUD_Msk | UART_ALTCTL_RS485AAD_Msk | UART_ALTCTL_ADDRMV_Msk); + uart->ALTCTL |= (u32Mode | (u32Addr << UART_ALTCTL_ADDRMV_Pos)); +} + + +/** + * @brief Select and configure LIN function + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32Mode The LIN direction : + * - \ref UART_ALTCTL_LINTXEN_Msk + * - \ref UART_ALTCTL_LINRXEN_Msk + * @param[in] u32BreakLength The break field length. + * + * @return None + * + * @details The function is used to set LIN relative setting. + */ +void UART_SelectLINMode(UART_T *uart, uint32_t u32Mode, uint32_t u32BreakLength) +{ + /* Select LIN function mode */ + uart->FUNCSEL = UART_FUNCSEL_LIN; + + /* Select LIN function setting : Tx enable, Rx enable and break field length */ + uart->ALTCTL &= ~(UART_ALTCTL_LINTXEN_Msk | UART_ALTCTL_LINRXEN_Msk | UART_ALTCTL_BRKFL_Msk); + uart->ALTCTL |= (u32Mode | (u32BreakLength << UART_ALTCTL_BRKFL_Pos)); +} + + +/** + * @brief Write UART data + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] pu8TxBuf The buffer to send the data to UART transmission FIFO. + * @param[out] u32WriteBytes The byte number of data. + * + * @return u32Count transfer byte count + * + * @details The function is to write data into TX buffer to transmit data by UART. + */ +uint32_t UART_Write(UART_T *uart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes) +{ + uint32_t u32Count, u32DelayNum; + uint32_t u32Exit = 0ul; + + for (u32Count = 0ul; u32Count != u32WriteBytes; u32Count++) + { + u32DelayNum = 0ul; + + while ((uart->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) == 0ul) /* Wait Tx empty and Time-out manner */ + { + u32DelayNum++; + + if (u32DelayNum >= 0x40000000ul) + { + u32Exit = 1ul; + break; + } + else + { + } + } + + if (u32Exit == 1ul) + { + break; + } + else + { + uart->DAT = pu8TxBuf[u32Count]; /* Send UART Data from buffer */ + } + } + + return u32Count; + +} +/** + * @brief Select Single Wire mode function + * + * @param[in] uart The pointer of the specified UART module. + * + * @return None + * + * @details The function is used to select Single Wire mode. + */ +void UART_SelectSingleWireMode(UART_T *uart) +{ + + /* Select UART SingleWire function mode */ + uart->FUNCSEL = ((uart->FUNCSEL & (~UART_FUNCSEL_FUNCSEL_Msk)) | UART_FUNCSEL_SINGLE_WIRE); + +} + + +/*@}*/ /* end of group UART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group UART_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ + + + diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_usbd.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_usbd.c new file mode 100644 index 00000000000..525c068cce3 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_usbd.c @@ -0,0 +1,784 @@ +/**************************************************************************//** + * @file usbd.c + * @version V0.10 + * @brief M251 series USBD driver source file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include "NuMicro.h" + +#if 0 + #define DBG_PRINTF printf +#else + #define DBG_PRINTF(...) +#endif + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USBD_Driver USBD Driver + @{ +*/ + + +/** @addtogroup USBD_EXPORTED_FUNCTIONS USBD Exported Functions + @{ +*/ + +/* Global variables for Control Pipe */ +uint8_t g_USBD_au8SetupPacket[8] = {0u}; /*!< Setup packet buffer */ +volatile uint8_t g_USBD_u8RemoteWakeupEn = 0u; /*!< Remote wake up function enable flag */ + +/** + * @cond HIDDEN_SYMBOLS + */ +static volatile uint8_t *s_USBD_pu8CtrlInPointer = 0ul; +static volatile uint8_t *s_USBD_pu8CtrlOutPointer = 0ul; +static volatile uint32_t s_USBD_u32CtrlInSize = 0ul; +static volatile uint32_t s_USBD_u32CtrlOutSize = 0ul; +static volatile uint32_t s_USBD_u32CtrlOutSizeLimit = 0ul; +static volatile uint32_t s_USBD_u32UsbAddr = 0ul; +static volatile uint32_t s_USBD_u32UsbConfig = 0ul; +static volatile uint32_t s_USBD_u32CtrlMaxPktSize = 8ul; +static volatile uint32_t s_USBD_u32UsbAltInterface = 0ul; +static volatile uint8_t s_USBD_u8CtrlInZeroFlag = 0ul; + +/** + * @endcond + */ + +const S_USBD_INFO_T *g_USBD_sINFO; /*!< A pointer for USB information structure */ + +VENDOR_REQ g_USBD_pfnVendorRequest = NULL; /*!< USB Vendor Request Functional Pointer */ +CLASS_REQ g_USBD_pfnClassRequest = NULL; /*!< USB Class Request Functional Pointer */ +SET_INTERFACE_REQ g_USBD_pfnSetInterface = NULL; /*!< USB Set Interface Functional Pointer */ +SET_CONFIG_CB g_USBD_pfnSetConfigCallback = NULL; /*!< USB Set configuration callback function pointer */ +uint32_t g_USBD_u32EpStallLock = 0ul; /*!< Bit map flag to lock specified EP when SET_FEATURE */ + +/** + * @brief This function makes USBD module to be ready to use + * + * @param[in] param The structure of USBD information. + * @param[in] pfnClassReq USB Class request callback function. + * @param[in] pfnSetInterface USB Set Interface request callback function. + * + * @return None + * + * @details This function will enable USB controller, USB PHY transceiver and pull-up resistor of USB_D+ pin. USB PHY will drive SE0 to bus. + */ +void USBD_Open(const S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface) +{ + g_USBD_sINFO = param; + g_USBD_pfnClassRequest = pfnClassReq; + g_USBD_pfnSetInterface = pfnSetInterface; + + /* get EP0 maximum packet size */ + s_USBD_u32CtrlMaxPktSize = g_USBD_sINFO->gu8DevDesc[7]; + + /* Initial USB engine */ +#ifdef SUPPORT_LPM + USBD->ATTR = 0x7D0UL | USBD_LPMACK; +#else + USBD->ATTR = 0x7D0UL; +#endif + /* Force SE0 */ + USBD_SET_SE0(); +} + +/** + * @brief This function makes USB host to recognize the device + * + * @param None + * + * @return None + * + * @details Enable WAKEUP, FLDET, USB and BUS interrupts. Disable software-disconnect function after 100ms delay with SysTick timer. + */ +void USBD_Start(void) +{ + /* Disable software-disconnect function */ + USBD_CLR_SE0(); + + /* Clear USB-related interrupts before enable interrupt */ + USBD_CLR_INT_FLAG(USBD_INT_BUS | USBD_INT_USB | USBD_INT_FLDET | USBD_INT_WAKEUP); + + /* Enable USB-related interrupts. */ + USBD_ENABLE_INT(USBD_INT_BUS | USBD_INT_USB | USBD_INT_FLDET | USBD_INT_WAKEUP); +} + +/** + * @brief Get the received SETUP packet + * + * @param[in] buf A buffer pointer used to store 8-byte SETUP packet. + * + * @return None + * + * @details Store SETUP packet to a user-specified buffer. + * + */ +void USBD_GetSetupPacket(uint8_t *buf) +{ + USBD_MemCopy(buf, g_USBD_au8SetupPacket, 8ul); +} + +/** + * @brief Process SETUP packet + * + * @param None + * + * @return None + * + * @details Parse SETUP packet and perform the corresponding action. + * + */ +void USBD_ProcessSetupPacket(void) +{ + /* Get SETUP packet from USB buffer */ + USBD_MemCopy(g_USBD_au8SetupPacket, (uint8_t *)USBD_BUF_BASE, 8ul); + + /* Check the request type */ + switch (g_USBD_au8SetupPacket[0] & 0x60ul) + { + case REQ_STANDARD: /* Standard */ + { + USBD_StandardRequest(); + break; + } + + case REQ_CLASS: /* Class */ + { + if (g_USBD_pfnClassRequest != NULL) + { + g_USBD_pfnClassRequest(); + } + + break; + } + + case REQ_VENDOR: /* Vendor */ + { + if (g_USBD_pfnVendorRequest != NULL) + { + g_USBD_pfnVendorRequest(); + } + + break; + } + + default: /* reserved */ + { + /* Setup error, stall the device */ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + break; + } + } +} + +/** + * @brief Process GetDescriptor request + * + * @param None + * + * @return None + * + * @details Parse GetDescriptor request and perform the corresponding action. + * + */ +void USBD_GetDescriptor(void) +{ + uint32_t u32Len; + + u32Len = 0ul; + u32Len = g_USBD_au8SetupPacket[7]; + u32Len <<= 8ul; + u32Len += g_USBD_au8SetupPacket[6]; + + switch (g_USBD_au8SetupPacket[3]) + { + /* Get Device Descriptor */ + case DESC_DEVICE: + { + u32Len = USBD_Minimum(u32Len, LEN_DEVICE); + DBG_PRINTF("Get device desc, %d\n", u32Len); + + USBD_PrepareCtrlIn((uint8_t *)g_USBD_sINFO->gu8DevDesc, u32Len); + + break; + } + + /* Get Configuration Descriptor */ + case DESC_CONFIG: + { + uint32_t u32TotalLen; + + DBG_PRINTF("Get config desc len %d, acture len %d\n", u32Len, u32TotalLen); + u32TotalLen = g_USBD_sINFO->gu8ConfigDesc[3]; + u32TotalLen = g_USBD_sINFO->gu8ConfigDesc[2] + (u32TotalLen << 8U); + + DBG_PRINTF("Get config desc len %d, acture len %d\n", u32Len, u32TotalLen); + u32Len = USBD_Minimum(u32Len, u32TotalLen); + DBG_PRINTF("Minimum len %d\n", u32Len); + + USBD_PrepareCtrlIn((uint8_t *)g_USBD_sINFO->gu8ConfigDesc, u32Len); + + break; + } + + + /* Get BOS Descriptor */ + case DESC_BOS: + { + uint32_t u32TotalLen; + + u32TotalLen = g_USBD_sINFO->gu8BosDesc[3]; + u32TotalLen = g_USBD_sINFO->gu8BosDesc[2] + (u32TotalLen << 8ul); + + DBG_PRINTF("Get BOS desc len %d, acture len %d\n", u32Len, u32TotalLen); + u32Len = USBD_Minimum(u32Len, u32TotalLen); + DBG_PRINTF("Minimum len %d\n", u32Len); + + USBD_PrepareCtrlIn((uint8_t *)g_USBD_sINFO->gu8BosDesc, u32Len); + break; + } + + /* Get HID Descriptor */ + case DESC_HID: + { + /* CV3.0 HID Class Descriptor Test, + Need to indicate index of the HID Descriptor within gu8ConfigDescriptor, specifically HID Composite device. */ + uint32_t u32ConfigDescOffset; /* u32ConfigDescOffset is configuration descriptor offset (HID descriptor start index) */ + u32Len = USBD_Minimum(u32Len, LEN_HID); + DBG_PRINTF("Get HID desc, %d\n", u32Len); + + u32ConfigDescOffset = g_USBD_sINFO->gu32ConfigHidDescIdx[g_USBD_au8SetupPacket[4]]; + USBD_PrepareCtrlIn((uint8_t *)&g_USBD_sINFO->gu8ConfigDesc[u32ConfigDescOffset], u32Len); + + break; + } + + /* Get Report Descriptor */ + case DESC_HID_RPT: + { + DBG_PRINTF("Get HID report, %d\n", u32Len); + + u32Len = USBD_Minimum(u32Len, g_USBD_sINFO->gu32HidReportSize[g_USBD_au8SetupPacket[4]]); + USBD_PrepareCtrlIn((uint8_t *)g_USBD_sINFO->gu8HidReportDesc[g_USBD_au8SetupPacket[4]], u32Len); + break; + } + + /* Get String Descriptor */ + case DESC_STRING: + { + /* Get String Descriptor */ + if (g_USBD_au8SetupPacket[2] < 4ul) + { + u32Len = USBD_Minimum(u32Len, g_USBD_sINFO->gu8StringDesc[g_USBD_au8SetupPacket[2]][0]); + DBG_PRINTF("Get string desc %d\n", u32Len); + + USBD_PrepareCtrlIn((uint8_t *)g_USBD_sINFO->gu8StringDesc[g_USBD_au8SetupPacket[2]], u32Len); + + + break; + } + else + { + /* Not support. Reply STALL. */ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + + DBG_PRINTF("Unsupported string desc (%d). Stall ctrl pipe.\n", g_USBD_au8SetupPacket[2]); + + break; + } + } + + default: + /* Not support. Reply STALL. */ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + + DBG_PRINTF("Unsupported get desc type. stall ctrl pipe\n"); + + break; + } +} + +/** + * @brief Process standard request + * + * @param None + * + * @return None + * + * @details Parse standard request and perform the corresponding action. + * + */ +void USBD_StandardRequest(void) +{ + DBG_PRINTF("USBD_StandardRequest\n"); + + /* clear global variables for new request */ + s_USBD_pu8CtrlInPointer = 0ul; + s_USBD_u32CtrlInSize = 0ul; + + if (g_USBD_au8SetupPacket[0] & 0x80ul) /* request data transfer direction */ + { + /* Device to host */ + switch (g_USBD_au8SetupPacket[1]) + { + case GET_CONFIGURATION: + { + /* Return current configuration setting */ + /* Data stage */ + M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)) = (uint8_t)s_USBD_u32UsbConfig; + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 1ul); + /* Status stage */ + USBD_PrepareCtrlOut(0, 0ul); + + DBG_PRINTF("Get configuration\n"); + + break; + } + + case GET_DESCRIPTOR: + { + USBD_GetDescriptor(); + USBD_PrepareCtrlOut(0, 0ul); /* For status stage */ + break; + } + + case GET_INTERFACE: + { + /* Return current interface setting */ + /* Data stage */ + M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)) = (uint8_t)s_USBD_u32UsbAltInterface; + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 1ul); + /* Status stage */ + USBD_PrepareCtrlOut(0, 0ul); + + DBG_PRINTF("Get interface\n"); + + break; + } + + case GET_STATUS: + { + /* Device */ + if (g_USBD_au8SetupPacket[0] == 0x80ul) + { + uint8_t u8Tmp; + + u8Tmp = (uint8_t)0ul; + + if (g_USBD_sINFO->gu8ConfigDesc[7] & 0x40ul) u8Tmp |= (uint8_t)1ul; /* Self-Powered/Bus-Powered. */ + + if (g_USBD_sINFO->gu8ConfigDesc[7] & 0x20) u8Tmp |= (uint8_t)(g_USBD_u8RemoteWakeupEn << 1ul); /* Remote wake up */ + + M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)) = u8Tmp; + + } + /* Interface */ + else if (g_USBD_au8SetupPacket[0] == 0x81ul) + M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)) = (uint8_t)0ul; + /* Endpoint */ + else if (g_USBD_au8SetupPacket[0] == 0x82ul) + { + uint8_t ep = (uint8_t)g_USBD_au8SetupPacket[4] & 0xFul; + M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0)) = (uint8_t)(USBD_GetStall(ep) ? 1ul : 0ul); + } + + M8(USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0) + 1) = (uint8_t)0ul; + /* Data stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 2ul); + /* Status stage */ + USBD_PrepareCtrlOut(0, 0ul); + + DBG_PRINTF("Get status\n"); + + break; + } + + default: + { + /* Setup error, stall the device */ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + + DBG_PRINTF("Unknown request. stall ctrl pipe.\n"); + + break; + } + } + } + else + { + /* Host to device */ + switch (g_USBD_au8SetupPacket[1]) + { + case CLEAR_FEATURE: + { + if (g_USBD_au8SetupPacket[2] == FEATURE_ENDPOINT_HALT) + { + uint32_t epNum, i; + + /* EP number stall is not allow to be clear in MSC class "Error Recovery Test". + a flag: g_USBD_u32EpStallLock is added to support it */ + epNum = (uint8_t)(g_USBD_au8SetupPacket[4] & 0xFul); + + for (i = 0ul; i < USBD_MAX_EP; i++) + { + if (((USBD->EP[i].CFG & 0xFul) == epNum) && ((g_USBD_u32EpStallLock & (1ul << i)) == 0ul)) + { + USBD->EP[i].CFGP &= ~USBD_CFGP_SSTALL_Msk; + USBD->EP[i].CFG &= ~USBD_CFG_DSQSYNC_Msk; + DBG_PRINTF("Clr stall ep%d %x\n", i, USBD->EP[i].CFGP); + } + } + } + else if (g_USBD_au8SetupPacket[2] == FEATURE_DEVICE_REMOTE_WAKEUP) + g_USBD_u8RemoteWakeupEn = (uint8_t)0; + + /* Status stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0ul); + + DBG_PRINTF("Clear feature op %d\n", g_USBD_au8SetupPacket[2]); + + break; + } + + case SET_ADDRESS: + { + s_USBD_u32UsbAddr = g_USBD_au8SetupPacket[2]; + DBG_PRINTF("Set addr to %d\n", s_USBD_u32UsbAddr); + + /* DATA IN for end of setup */ + /* Status Stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0ul); + + break; + } + + case SET_CONFIGURATION: + { + s_USBD_u32UsbConfig = g_USBD_au8SetupPacket[2]; + + if (g_USBD_pfnSetConfigCallback) + g_USBD_pfnSetConfigCallback(); + + /* Status stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0ul); + + DBG_PRINTF("Set config to %d\n", s_USBD_u32UsbConfig); + + break; + } + + case SET_FEATURE: + { + if (g_USBD_au8SetupPacket[2] == FEATURE_ENDPOINT_HALT) + { + USBD_SetStall((uint8_t)(g_USBD_au8SetupPacket[4] & 0xFul)); + DBG_PRINTF("Set feature. stall ep %d\n", g_USBD_au8SetupPacket[4] & 0xFul); + } + else if (g_USBD_au8SetupPacket[2] == FEATURE_DEVICE_REMOTE_WAKEUP) + { + g_USBD_u8RemoteWakeupEn = (uint8_t)1ul; + DBG_PRINTF("Set feature. enable remote wakeup\n"); + } + + /* Status stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0ul); + + break; + } + + case SET_INTERFACE: + { + s_USBD_u32UsbAltInterface = g_USBD_au8SetupPacket[2]; + + if (g_USBD_pfnSetInterface != NULL) + g_USBD_pfnSetInterface(); + + /* Status stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0ul); + + DBG_PRINTF("Set interface to %d\n", s_USBD_u32UsbAltInterface); + + break; + } + + default: + { + + /* Setup error, stall the device */ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + + DBG_PRINTF("Unsupported request. stall ctrl pipe.\n"); + + break; + } + } + } +} + +/** + * @brief Prepare the first Control IN pipe + * + * @param[in] pu8Buf The pointer of data sent to USB host. + * @param[in] u32Size The IN transfer size. + * + * @return None + * + * @details Prepare data for Control IN transfer. + * + */ +void USBD_PrepareCtrlIn(uint8_t pu8Buf[], uint32_t u32Size) +{ + DBG_PRINTF("Prepare Ctrl In %d\n", u32Size); + + if (u32Size > s_USBD_u32CtrlMaxPktSize) + { + // Data size > MXPLD + s_USBD_pu8CtrlInPointer = pu8Buf + s_USBD_u32CtrlMaxPktSize; + s_USBD_u32CtrlInSize = u32Size - s_USBD_u32CtrlMaxPktSize; + USBD_SET_DATA1(EP0); + USBD_MemCopy((uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0), pu8Buf, s_USBD_u32CtrlMaxPktSize); + USBD_SET_PAYLOAD_LEN(EP0, s_USBD_u32CtrlMaxPktSize); + } + else + { + // Data size <= MXPLD + s_USBD_pu8CtrlInPointer = 0ul; + s_USBD_u32CtrlInSize = 0ul; + + if (u32Size == s_USBD_u32CtrlMaxPktSize) + { + s_USBD_u8CtrlInZeroFlag = (uint8_t)1ul; + } + + USBD_SET_DATA1(EP0); + USBD_MemCopy((uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0), pu8Buf, u32Size); + USBD_SET_PAYLOAD_LEN(EP0, u32Size); + } +} + +/** + * @brief Repeat Control IN pipe + * + * @param None + * + * @return None + * + * @details This function processes the remained data of Control IN transfer. + * + */ +void USBD_CtrlIn(void) +{ + + DBG_PRINTF("Ctrl In Ack. residue %d\n", s_USBD_u32CtrlInSize); + + if (s_USBD_u32CtrlInSize) + { + // Process remained data + if (s_USBD_u32CtrlInSize > s_USBD_u32CtrlMaxPktSize) + { + // Data size > MXPLD + USBD_MemCopy((uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0), (uint8_t *)s_USBD_pu8CtrlInPointer, s_USBD_u32CtrlMaxPktSize); + USBD_SET_PAYLOAD_LEN(EP0, s_USBD_u32CtrlMaxPktSize); + s_USBD_pu8CtrlInPointer += s_USBD_u32CtrlMaxPktSize; + s_USBD_u32CtrlInSize -= s_USBD_u32CtrlMaxPktSize; + } + else + { + // Data size <= MXPLD + USBD_MemCopy((uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0), (uint8_t *)s_USBD_pu8CtrlInPointer, s_USBD_u32CtrlInSize); + USBD_SET_PAYLOAD_LEN(EP0, s_USBD_u32CtrlInSize); + + if (s_USBD_u32CtrlInSize == s_USBD_u32CtrlMaxPktSize) + { + s_USBD_u8CtrlInZeroFlag = (uint8_t)1ul; + } + + s_USBD_pu8CtrlInPointer = 0ul; + s_USBD_u32CtrlInSize = 0ul; + } + } + else // No more data for IN token + { + // In ACK for Set address + if ((g_USBD_au8SetupPacket[0] == REQ_STANDARD) && (g_USBD_au8SetupPacket[1] == SET_ADDRESS)) + { + if ((USBD_GET_ADDR() != s_USBD_u32UsbAddr) && (USBD_GET_ADDR() == 0ul)) + { + USBD_SET_ADDR(s_USBD_u32UsbAddr); + } + } + + /* For the case of data size is integral times maximum packet size */ + if (s_USBD_u8CtrlInZeroFlag) + { + USBD_SET_PAYLOAD_LEN(EP0, 0ul); + s_USBD_u8CtrlInZeroFlag = (uint8_t)0ul; + } + + DBG_PRINTF("Ctrl In done.\n"); + + } +} + +/** + * @brief Prepare the first Control OUT pipe + * + * @param[in] pu8Buf The pointer of data received from USB host. + * @param[in] u32Size The OUT transfer size. + * + * @return None + * + * @details This function is used to prepare the first Control OUT transfer. + * + */ +void USBD_PrepareCtrlOut(uint8_t *pu8Buf, uint32_t u32Size) +{ + s_USBD_pu8CtrlOutPointer = pu8Buf; + s_USBD_u32CtrlOutSize = 0ul; + s_USBD_u32CtrlOutSizeLimit = u32Size; + USBD_SET_PAYLOAD_LEN(EP1, s_USBD_u32CtrlMaxPktSize); +} + +/** + * @brief Repeat Control OUT pipe + * + * @param None + * + * @return None + * + * @details This function processes the successive Control OUT transfer. + * + */ +void USBD_CtrlOut(void) +{ + uint32_t u32Size; + + DBG_PRINTF("Ctrl Out Ack %d\n", s_USBD_u32CtrlOutSize); + + if (s_USBD_u32CtrlOutSize < s_USBD_u32CtrlOutSizeLimit) + { + u32Size = USBD_GET_PAYLOAD_LEN(EP1); + USBD_MemCopy((uint8_t *)s_USBD_pu8CtrlOutPointer, (uint8_t *)USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP1), u32Size); + s_USBD_pu8CtrlOutPointer += u32Size; + s_USBD_u32CtrlOutSize += u32Size; + + if (s_USBD_u32CtrlOutSize < s_USBD_u32CtrlOutSizeLimit) + USBD_SET_PAYLOAD_LEN(EP1, s_USBD_u32CtrlMaxPktSize); + + } +} + +/** + * @brief Reset software flags + * + * @param None + * + * @return None + * + * @details This function resets all variables for protocol and resets USB device address to 0. + * + */ +void USBD_SwReset(void) +{ + uint32_t i; + + // Reset all variables for protocol + s_USBD_pu8CtrlInPointer = 0ul; + s_USBD_u32CtrlInSize = 0ul; + s_USBD_pu8CtrlOutPointer = 0ul; + s_USBD_u32CtrlOutSize = 0ul; + s_USBD_u32CtrlOutSizeLimit = 0ul; + g_USBD_u32EpStallLock = 0ul; + memset(g_USBD_au8SetupPacket, 0, 8ul); + + /* Reset PID DATA0 */ + for (i = 0ul; i < USBD_MAX_EP; i++) + USBD->EP[i].CFG &= ~USBD_CFG_DSQSYNC_Msk; + + // Reset USB device address + USBD_SET_ADDR(0ul); +} + +/** + * @brief USBD Set Vendor Request + * + * @param[in] pfnVendorReq Vendor Request Callback Function + * + * @return None + * + * @details This function is used to set USBD vendor request callback function + */ +void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq) +{ + g_USBD_pfnVendorRequest = pfnVendorReq; +} + +/** + * @brief The callback function which called when get SET CONFIGURATION request + * + * @param[in] pfnSetConfigCallback Callback function pointer for SET CONFIGURATION request + * + * @return None + * + * @details This function is used to set the callback function which will be called at SET CONFIGURATION request. + */ +void USBD_SetConfigCallback(SET_CONFIG_CB pfnSetConfigCallback) +{ + g_USBD_pfnSetConfigCallback = pfnSetConfigCallback; +} + + +/** + * @brief EP stall lock function to avoid stall clear by USB SET FEATURE request. + * + * @param[in] u32EpBitmap Use bitmap to select which endpoints will be locked + * + * @return None + * + * @details This function is used to lock relative endpoint to avoid stall clear by SET FEATURE request. + * If ep stall locked, user needs to reset USB device or re-configure device to clear it. + */ +void USBD_LockEpStall(uint32_t u32EpBitmap) +{ + g_USBD_u32EpStallLock = u32EpBitmap; +} + + + + + +/*@}*/ /* end of group USBD_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USBD_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_usci_i2c.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_usci_i2c.c new file mode 100644 index 00000000000..540b2732f64 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_usci_i2c.c @@ -0,0 +1,1688 @@ +/**************************************************************************//** + * @file usci_i2c.c + * @version V0.10 + * @brief M251 series USCI I2C(UI2C) driver source file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_I2C_Driver USCI_I2C Driver + @{ +*/ + + +/** @addtogroup USCI_I2C_EXPORTED_FUNCTIONS USCI_I2C Exported Functions + @{ +*/ + +/** + * @brief This function makes USCI_I2C module be ready and set the wanted bus clock + * + * @param[in] psUI2C The pointer of the specified USCI_I2C module. + * @param[in] u32BusClock The target bus speed of USCI_I2C module. + * + * @return Actual USCI_I2C bus clock frequency. + * + * @details Enable USCI_I2C module and configure USCI_I2C module(bus clock, data format). + */ +uint32_t UI2C_Open(UI2C_T *psUI2C, uint32_t u32BusClock) +{ + uint32_t u32ClkDiv; + uint32_t u32Pclk; + + if ((psUI2C == UI2C0) || (psUI2C == UI2C2)) + { + u32Pclk = CLK_GetPCLK0Freq(); + } + else + { + u32Pclk = CLK_GetPCLK1Freq(); + } + + u32ClkDiv = (uint32_t)((((((u32Pclk / 2U) * 10U) / (u32BusClock)) + 5U) / 10U) - 1U); /* Compute proper divider for USCI_I2C clock */ + + /* Enable USCI_I2C protocol */ + psUI2C->CTL &= ~UI2C_CTL_FUNMODE_Msk; + psUI2C->CTL = 4U << UI2C_CTL_FUNMODE_Pos; + + /* Data format configuration */ + /* 8 bit data length */ + psUI2C->LINECTL &= ~UI2C_LINECTL_DWIDTH_Msk; + psUI2C->LINECTL |= 8U << UI2C_LINECTL_DWIDTH_Pos; + + /* MSB data format */ + psUI2C->LINECTL &= ~UI2C_LINECTL_LSB_Msk; + + /* Set USCI_I2C bus clock */ + psUI2C->BRGEN &= ~UI2C_BRGEN_CLKDIV_Msk; + psUI2C->BRGEN |= (u32ClkDiv << UI2C_BRGEN_CLKDIV_Pos); + psUI2C->PROTCTL |= UI2C_PROTCTL_PROTEN_Msk; + + return (u32Pclk / ((u32ClkDiv + 1U) << 1U)); +} + +/** + * @brief This function closes the USCI_I2C module + * + * @param[in] psUI2C The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details Close USCI_I2C protocol function. + */ +void UI2C_Close(UI2C_T *psUI2C) +{ + /* Disable USCI_I2C function */ + psUI2C->CTL &= ~UI2C_CTL_FUNMODE_Msk; +} + +/** + * @brief This function clears the time-out flag + * + * @param[in] psUI2C The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details Clear time-out flag when time-out flag is set. + */ +void UI2C_ClearTimeoutFlag(UI2C_T *psUI2C) +{ + psUI2C->PROTSTS = UI2C_PROTSTS_TOIF_Msk; +} + +/** + * @brief This function sets the control bit of the USCI_I2C module. + * + * @param[in] psUI2C The pointer of the specified USCI_I2C module. + * @param[in] u8Start Set START bit to USCI_I2C module. + * @param[in] u8Stop Set STOP bit to USCI_I2C module. + * @param[in] u8Ptrg Set PTRG bit to USCI_I2C module. + * @param[in] u8Ack Set ACK bit to USCI_I2C module. + * + * @return None + * + * @details The function set USCI_I2C control bit of USCI_I2C bus protocol. + */ +void UI2C_Trigger(UI2C_T *psUI2C, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Ptrg, uint8_t u8Ack) +{ + uint32_t u32Reg = 0U; + uint32_t u32Val = psUI2C->PROTCTL & ~(UI2C_PROTCTL_STA_Msk | UI2C_PROTCTL_STO_Msk | UI2C_PROTCTL_AA_Msk); + + if (u8Start) + { + u32Reg |= UI2C_PROTCTL_STA_Msk; + } + + if (u8Stop) + { + u32Reg |= UI2C_PROTCTL_STO_Msk; + } + + if (u8Ptrg) + { + u32Reg |= UI2C_PROTCTL_PTRG_Msk; + } + + if (u8Ack) + { + u32Reg |= UI2C_PROTCTL_AA_Msk; + } + + psUI2C->PROTCTL = u32Val | u32Reg; +} + +/** + * @brief This function disables the interrupt of USCI_I2C module + * + * @param[in] psUI2C The pointer of the specified USCI_I2C module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to an interrupt enable bit. + * This parameter decides which interrupts will be disabled. It is combination of: + * - \ref UI2C_TO_INT_MASK + * - \ref UI2C_STAR_INT_MASK + * - \ref UI2C_STOR_INT_MASK + * - \ref UI2C_NACK_INT_MASK + * - \ref UI2C_ARBLO_INT_MASK + * - \ref UI2C_ERR_INT_MASK + * - \ref UI2C_ACK_INT_MASK + * + * @return None + * + * @details The function is used to disable USCI_I2C bus interrupt events. + */ +void UI2C_DisableInt(UI2C_T *psUI2C, uint32_t u32Mask) +{ + /* Disable time-out interrupt flag */ + if ((u32Mask & UI2C_TO_INT_MASK) == UI2C_TO_INT_MASK) + { + psUI2C->PROTIEN &= ~UI2C_PROTIEN_TOIEN_Msk; + } + + /* Disable start condition received interrupt flag */ + if ((u32Mask & UI2C_STAR_INT_MASK) == UI2C_STAR_INT_MASK) + { + psUI2C->PROTIEN &= ~UI2C_PROTIEN_STARIEN_Msk; + } + + /* Disable stop condition received interrupt flag */ + if ((u32Mask & UI2C_STOR_INT_MASK) == UI2C_STOR_INT_MASK) + { + psUI2C->PROTIEN &= ~UI2C_PROTIEN_STORIEN_Msk; + } + + /* Disable non-acknowledge interrupt flag */ + if ((u32Mask & UI2C_NACK_INT_MASK) == UI2C_NACK_INT_MASK) + { + psUI2C->PROTIEN &= ~UI2C_PROTIEN_NACKIEN_Msk; + } + + /* Disable arbitration lost interrupt flag */ + if ((u32Mask & UI2C_ARBLO_INT_MASK) == UI2C_ARBLO_INT_MASK) + { + psUI2C->PROTIEN &= ~UI2C_PROTIEN_ARBLOIEN_Msk; + } + + /* Disable error interrupt flag */ + if ((u32Mask & UI2C_ERR_INT_MASK) == UI2C_ERR_INT_MASK) + { + psUI2C->PROTIEN &= ~UI2C_PROTIEN_ERRIEN_Msk; + } + + /* Disable acknowledge interrupt flag */ + if ((u32Mask & UI2C_ACK_INT_MASK) == UI2C_ACK_INT_MASK) + { + psUI2C->PROTIEN &= ~UI2C_PROTIEN_ACKIEN_Msk; + } +} + +/** + * @brief This function enables the interrupt of USCI_I2C module. + * @param[in] psUI2C The pointer of the specified USCI_I2C module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be enabled. It is combination of: + * - \ref UI2C_TO_INT_MASK + * - \ref UI2C_STAR_INT_MASK + * - \ref UI2C_STOR_INT_MASK + * - \ref UI2C_NACK_INT_MASK + * - \ref UI2C_ARBLO_INT_MASK + * - \ref UI2C_ERR_INT_MASK + * - \ref UI2C_ACK_INT_MASK + * @return None + * + * @details The function is used to enable USCI_I2C bus interrupt events. + */ +void UI2C_EnableInt(UI2C_T *psUI2C, uint32_t u32Mask) +{ + /* Enable time-out interrupt flag */ + if ((u32Mask & UI2C_TO_INT_MASK) == UI2C_TO_INT_MASK) + { + psUI2C->PROTIEN |= UI2C_PROTIEN_TOIEN_Msk; + } + + /* Enable start condition received interrupt flag */ + if ((u32Mask & UI2C_STAR_INT_MASK) == UI2C_STAR_INT_MASK) + { + psUI2C->PROTIEN |= UI2C_PROTIEN_STARIEN_Msk; + } + + /* Enable stop condition received interrupt flag */ + if ((u32Mask & UI2C_STOR_INT_MASK) == UI2C_STOR_INT_MASK) + { + psUI2C->PROTIEN |= UI2C_PROTIEN_STORIEN_Msk; + } + + /* Enable non-acknowledge interrupt flag */ + if ((u32Mask & UI2C_NACK_INT_MASK) == UI2C_NACK_INT_MASK) + { + psUI2C->PROTIEN |= UI2C_PROTIEN_NACKIEN_Msk; + } + + /* Enable arbitration lost interrupt flag */ + if ((u32Mask & UI2C_ARBLO_INT_MASK) == UI2C_ARBLO_INT_MASK) + { + psUI2C->PROTIEN |= UI2C_PROTIEN_ARBLOIEN_Msk; + } + + /* Enable error interrupt flag */ + if ((u32Mask & UI2C_ERR_INT_MASK) == UI2C_ERR_INT_MASK) + { + psUI2C->PROTIEN |= UI2C_PROTIEN_ERRIEN_Msk; + } + + /* Enable acknowledge interrupt flag */ + if ((u32Mask & UI2C_ACK_INT_MASK) == UI2C_ACK_INT_MASK) + { + psUI2C->PROTIEN |= UI2C_PROTIEN_ACKIEN_Msk; + } +} + +/** + * @brief This function returns the real bus clock of USCI_I2C module + * + * @param[in] psUI2C The pointer of the specified USCI_I2C module. + * + * @return Actual USCI_I2C bus clock frequency. + * + * @details The function returns the actual USCI_I2C module bus clock. + */ +uint32_t UI2C_GetBusClockFreq(UI2C_T *psUI2C) +{ + uint32_t u32Divider; + uint32_t u32Pclk; + + if ((psUI2C == UI2C0) || (psUI2C == UI2C2)) + { + u32Pclk = CLK_GetPCLK0Freq(); + } + else + { + u32Pclk = CLK_GetPCLK1Freq(); + } + + u32Divider = (psUI2C->BRGEN & UI2C_BRGEN_CLKDIV_Msk) >> UI2C_BRGEN_CLKDIV_Pos; + + return (u32Pclk / ((u32Divider + 1U) << 1U)); +} + +/** + * @brief This function sets bus clock frequency of USCI_I2C module + * + * @param[in] psUI2C The pointer of the specified USCI_I2C module. + * @param[in] u32BusClock The target bus speed of USCI_I2C module. + * + * @return Actual USCI_I2C bus clock frequency. + * + * @details Use this function set USCI_I2C bus clock frequency and return actual bus clock. + */ +uint32_t UI2C_SetBusClockFreq(UI2C_T *psUI2C, uint32_t u32BusClock) +{ + uint32_t u32ClkDiv; + uint32_t u32Pclk; + + if ((psUI2C == UI2C0) || (psUI2C == UI2C2)) + { + u32Pclk = CLK_GetPCLK0Freq(); + } + else + { + u32Pclk = CLK_GetPCLK1Freq(); + } + + u32ClkDiv = (uint32_t)((((((u32Pclk / 2U) * 10U) / (u32BusClock)) + 5U) / 10U) - 1U); /* Compute proper divider for USCI_I2C clock */ + + /* Set USCI_I2C bus clock */ + psUI2C->BRGEN &= ~UI2C_BRGEN_CLKDIV_Msk; + psUI2C->BRGEN |= (u32ClkDiv << UI2C_BRGEN_CLKDIV_Pos); + + return (u32Pclk / ((u32ClkDiv + 1U) << 1U)); +} + +/** + * @brief This function gets the interrupt flag of USCI_I2C module + * + * @param[in] psUI2C The pointer of the specified USCI_I2C module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be read. It is combination of: + * - \ref UI2C_TO_INT_MASK + * - \ref UI2C_STAR_INT_MASK + * - \ref UI2C_STOR_INT_MASK + * - \ref UI2C_NACK_INT_MASK + * - \ref UI2C_ARBLO_INT_MASK + * - \ref UI2C_ERR_INT_MASK + * - \ref UI2C_ACK_INT_MASK + * + * @return Interrupt flags of selected sources. + * + * @details Use this function to get USCI_I2C interrupt flag when module occurs interrupt event. + */ +uint32_t UI2C_GetIntFlag(UI2C_T *psUI2C, uint32_t u32Mask) +{ + uint32_t u32IntFlag = 0U; + uint32_t u32TmpValue; + + u32TmpValue = psUI2C->PROTSTS & UI2C_PROTSTS_TOIF_Msk; + + /* Check Time-out Interrupt Flag */ + if ((u32Mask & UI2C_TO_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_TO_INT_MASK; + } + + u32TmpValue = psUI2C->PROTSTS & UI2C_PROTSTS_STARIF_Msk; + + /* Check Start Condition Received Interrupt Flag */ + if ((u32Mask & UI2C_STAR_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_STAR_INT_MASK; + } + + u32TmpValue = psUI2C->PROTSTS & UI2C_PROTSTS_STORIF_Msk; + + /* Check Stop Condition Received Interrupt Flag */ + if ((u32Mask & UI2C_STOR_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_STOR_INT_MASK; + } + + u32TmpValue = psUI2C->PROTSTS & UI2C_PROTSTS_NACKIF_Msk; + + /* Check Non-Acknowledge Interrupt Flag */ + if ((u32Mask & UI2C_NACK_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_NACK_INT_MASK; + } + + u32TmpValue = psUI2C->PROTSTS & UI2C_PROTSTS_ARBLOIF_Msk; + + /* Check Arbitration Lost Interrupt Flag */ + if ((u32Mask & UI2C_ARBLO_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_ARBLO_INT_MASK; + } + + u32TmpValue = psUI2C->PROTSTS & UI2C_PROTSTS_ERRIF_Msk; + + /* Check Error Interrupt Flag */ + if ((u32Mask & UI2C_ERR_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_ERR_INT_MASK; + } + + u32TmpValue = psUI2C->PROTSTS & UI2C_PROTSTS_ACKIF_Msk; + + /* Check Acknowledge Interrupt Flag */ + if ((u32Mask & UI2C_ACK_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_ACK_INT_MASK; + } + + return u32IntFlag; +} + +/** + * @brief This function clears the interrupt flag of USCI_I2C module. + * @param[in] psUI2C The pointer of the specified USCI_I2C module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. It is combination of: + * - \ref UI2C_TO_INT_MASK + * - \ref UI2C_STAR_INT_MASK + * - \ref UI2C_STOR_INT_MASK + * - \ref UI2C_NACK_INT_MASK + * - \ref UI2C_ARBLO_INT_MASK + * - \ref UI2C_ERR_INT_MASK + * - \ref UI2C_ACK_INT_MASK + * + * @return None + * + * @details Use this function to clear USCI_I2C interrupt flag when module occurs interrupt event and set flag. + */ +void UI2C_ClearIntFlag(UI2C_T *psUI2C, uint32_t u32Mask) +{ + /* Clear Time-out Interrupt Flag */ + if (u32Mask & UI2C_TO_INT_MASK) + { + psUI2C->PROTSTS = UI2C_PROTSTS_TOIF_Msk; + } + + /* Clear Start Condition Received Interrupt Flag */ + if (u32Mask & UI2C_STAR_INT_MASK) + { + psUI2C->PROTSTS = UI2C_PROTSTS_STARIF_Msk; + } + + /* Clear Stop Condition Received Interrupt Flag */ + if (u32Mask & UI2C_STOR_INT_MASK) + { + psUI2C->PROTSTS = UI2C_PROTSTS_STORIF_Msk; + } + + /* Clear Non-Acknowledge Interrupt Flag */ + if (u32Mask & UI2C_NACK_INT_MASK) + { + psUI2C->PROTSTS = UI2C_PROTSTS_NACKIF_Msk; + } + + /* Clear Arbitration Lost Interrupt Flag */ + if (u32Mask & UI2C_ARBLO_INT_MASK) + { + psUI2C->PROTSTS = UI2C_PROTSTS_ARBLOIF_Msk; + } + + /* Clear Error Interrupt Flag */ + if (u32Mask & UI2C_ERR_INT_MASK) + { + psUI2C->PROTSTS = UI2C_PROTSTS_ERRIF_Msk; + } + + /* Clear Acknowledge Interrupt Flag */ + if (u32Mask & UI2C_ACK_INT_MASK) + { + psUI2C->PROTSTS = UI2C_PROTSTS_ACKIF_Msk; + } +} + +/** + * @brief This function returns the data stored in data register of USCI_I2C module. + * + * @param[in] psUI2C The pointer of the specified USCI_I2C module. + * + * @return USCI_I2C data. + * + * @details To read a byte data from USCI_I2C module receive data register. + */ +uint32_t UI2C_GetData(UI2C_T *psUI2C) +{ + return (psUI2C->RXDAT); +} + +/** + * @brief This function writes a byte data to data register of USCI_I2C module + * + * @param[in] psUI2C The pointer of the specified USCI_I2C module. + * @param[in] u8Data The data which will be written to data register of USCI_I2C module. + * + * @return None + * + * @details To write a byte data to transmit data register to transmit data. + */ +void UI2C_SetData(UI2C_T *psUI2C, uint8_t u8Data) +{ + psUI2C->TXDAT = u8Data; +} + +/** + * @brief Configure slave address and enable GC mode + * + * @param[in] psUI2C The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveNo Slave channel number [0/1] + * @param[in] u16SlaveAddr The slave address. + * @param[in] u8GCMode GC mode enable or not. Valid values are: + * - \ref UI2C_GCMODE_ENABLE + * - \ref UI2C_GCMODE_DISABLE + * + * @return None + * + * @details To configure USCI_I2C module slave address and GC mode. + */ +void UI2C_SetSlaveAddr(UI2C_T *psUI2C, uint8_t u8SlaveNo, uint16_t u16SlaveAddr, uint8_t u8GCMode) +{ + if (u8SlaveNo) + { + psUI2C->DEVADDR1 = u16SlaveAddr; + } + else + { + psUI2C->DEVADDR0 = u16SlaveAddr; + } + + psUI2C->PROTCTL = (psUI2C->PROTCTL & ~UI2C_PROTCTL_GCFUNC_Msk) | u8GCMode; +} + +/** + * @brief Configure the mask bit of slave address. + * + * @param[in] psUI2C The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveNo Slave channel number [0/1] + * @param[in] u16SlaveAddrMask The slave address mask. + * + * @return None + * + * @details To configure USCI_I2C module slave address mask bit. + * @note The corresponding address bit is "Don't Care". + */ +void UI2C_SetSlaveAddrMask(UI2C_T *psUI2C, uint8_t u8SlaveNo, uint16_t u16SlaveAddrMask) +{ + if (u8SlaveNo) + { + psUI2C->ADDRMSK1 = u16SlaveAddrMask; + } + else + { + psUI2C->ADDRMSK0 = u16SlaveAddrMask; + } +} + +/** + * @brief This function enables time-out function and configures timeout counter + * + * @param[in] psUI2C The pointer of the specified USCI_I2C module. + * @param[in] u32TimeoutCnt Timeout counter. Valid values are between 0~0x3FF + * + * @return None + * + * @details To enable USCI_I2C bus time-out function and set time-out counter. + */ +void UI2C_EnableTimeout(UI2C_T *psUI2C, uint32_t u32TimeoutCnt) +{ + psUI2C->PROTCTL = (psUI2C->PROTCTL & ~UI2C_PROTCTL_TOCNT_Msk) | (u32TimeoutCnt << UI2C_PROTCTL_TOCNT_Pos); + psUI2C->BRGEN = (psUI2C->BRGEN & ~UI2C_BRGEN_TMCNTSRC_Msk) | UI2C_BRGEN_TMCNTEN_Msk; +} + +/** + * @brief This function disables time-out function + * + * @param[in] psUI2C The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details To disable USCI_I2C bus time-out function. + */ +void UI2C_DisableTimeout(UI2C_T *psUI2C) +{ + psUI2C->PROTCTL &= ~UI2C_PROTCTL_TOCNT_Msk; + psUI2C->BRGEN &= ~UI2C_BRGEN_TMCNTEN_Msk; +} + +/** + * @brief This function enables the wakeup function of USCI_I2C module + * + * @param[in] psUI2C The pointer of the specified USCI_I2C module. + * @param[in] u8WakeupMode The wake-up mode selection. Valid values are: + * - \ref UI2C_DATA_TOGGLE_WK + * - \ref UI2C_ADDR_MATCH_WK + * + * @return None + * + * @details To enable USCI_I2C module wake-up function. + */ +void UI2C_EnableWakeup(UI2C_T *psUI2C, uint8_t u8WakeupMode) +{ + psUI2C->WKCTL = (psUI2C->WKCTL & ~UI2C_WKCTL_WKADDREN_Msk) | (u8WakeupMode | UI2C_WKCTL_WKEN_Msk); +} + +/** + * @brief This function disables the wakeup function of USCI_I2C module + * + * @param[in] psUI2C The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details To disable USCI_I2C module wake-up function. + */ +void UI2C_DisableWakeup(UI2C_T *psUI2C) +{ + psUI2C->WKCTL &= ~UI2C_WKCTL_WKEN_Msk; +} + +/** + * @brief Write a byte to Slave + * + * @param[in] *psUI2C The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8Data Write a byte data to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for USCI_I2C Master write a byte data to Slave. + * + */ + +uint8_t UI2C_WriteByte(UI2C_T *psUI2C, uint8_t u8SlaveAddr, const uint8_t u8Data) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, u8Ctrl = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(psUI2C); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(psUI2C) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(psUI2C) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(psUI2C, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(psUI2C, u8Data); /* Write data to UI2C_TXDAT */ + eEvent = MASTER_SEND_DATA; + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(psUI2C, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + return (u8Err | u8Xfering); /* return (Success)/(Fail) status */ +} + +/** + * @brief Write multi bytes to Slave + * + * @param[in] *psUI2C The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] *pu8Data Pointer to array to write data to Slave + * @param[in] u32WLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for USCI_I2C Master write multi bytes data to Slave. + * + */ + +uint32_t UI2C_WriteMultiBytes(UI2C_T *psUI2C, uint8_t u8SlaveAddr, const uint8_t *pu8Data, uint32_t u32WLen) +{ + uint8_t u8Xfering = 1U, u8Ctrl = 0U; + uint32_t u32TXLen = 0U; + + UI2C_START(psUI2C); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(psUI2C) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(psUI2C) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(psUI2C, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (u32TXLen < u32WLen) + UI2C_SET_DATA(psUI2C, pu8Data[u32TXLen++]); /* Write data to UI2C_TXDAT */ + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(psUI2C, u8Ctrl); /* Write controlbit to UI2C_CTL register */ + } + + return u32TXLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Specify a byte register address and write a byte to Slave + * + * @param[in] *psUI2C The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 byte) of data write to + * @param[in] u8Data A byte data to write it to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for USCI_I2C Master specify a address that data write to in Slave. + * + */ + +uint8_t UI2C_WriteByteOneReg(UI2C_T *psUI2C, uint8_t u8SlaveAddr, uint8_t u8DataAddr, const uint8_t u8Data) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, u8Ctrl = 0U; + uint32_t u32TXLen = 0U; + + UI2C_START(psUI2C); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(psUI2C) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(psUI2C) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(psUI2C, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (u32TXLen == 0U) + { + UI2C_SET_DATA(psUI2C, u8DataAddr); /* Write data address to UI2C_TXDAT */ + u32TXLen++; + } + else if (u32TXLen == 1U) + { + UI2C_SET_DATA(psUI2C, u8Data); /* Write data to UI2C_TXDAT */ + u32TXLen++; + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(psUI2C, u8Ctrl); /* Write controlbit to UI2C_CTL register */ + } + + return (u8Err | u8Xfering); /* return (Success)/(Fail) status */ +} + + +/** + * @brief Specify a byte register address and write multi bytes to Slave + * + * @param[in] *psUI2C The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 byte) of data write to + * @param[in] *pu8Data Pointer to array to write data to Slave + * @param[in] u32WLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for USCI_I2C Master specify a byte address that multi data bytes write to in Slave. + * + */ + +uint32_t UI2C_WriteMultiBytesOneReg(UI2C_T *psUI2C, uint8_t u8SlaveAddr, uint8_t u8DataAddr, const uint8_t *pu8Data, uint32_t u32WLen) +{ + uint8_t u8Xfering = 1U, u8Ctrl = 0U; + uint32_t u32TXLen = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(psUI2C); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(psUI2C) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(psUI2C) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(psUI2C, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(psUI2C, u8DataAddr); /* Write data address to UI2C_TXDAT */ + eEvent = MASTER_SEND_DATA; + } + else + { + if (u32TXLen < u32WLen) + UI2C_SET_DATA(psUI2C, pu8Data[u32TXLen++]); /* Write data to UI2C_TXDAT */ + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(psUI2C, u8Ctrl); /* Write controlbit to UI2C_CTL register */ + } + + return u32TXLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Specify two bytes register address and Write a byte to Slave + * + * @param[in] *psUI2C The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 byte) of data write to + * @param[in] u8Data Write a byte data to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for USCI_I2C Master specify two bytes address that data write to in Slave. + * + */ + +uint8_t UI2C_WriteByteTwoRegs(UI2C_T *psUI2C, uint8_t u8SlaveAddr, uint16_t u16DataAddr, const uint8_t u8Data) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, u8Ctrl = 0U; + uint32_t u32TXLen = 0U; + + UI2C_START(psUI2C); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(psUI2C) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(psUI2C) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(psUI2C, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (u32TXLen == 0U) + { + UI2C_SET_DATA(psUI2C, (uint8_t)(u16DataAddr & 0xFF00U) >> 8U); /* Write Hi byte data address to UI2C_TXDAT */ + u32TXLen++; + } + else if (u32TXLen == 1U) + { + UI2C_SET_DATA(psUI2C, (uint8_t)(u16DataAddr & 0xFFU)); /* Write Lo byte data address to UI2C_TXDAT */ + u32TXLen++; + } + else if (u32TXLen == 2U) + { + UI2C_SET_DATA(psUI2C, u8Data); /* Write data to UI2C_TXDAT */ + u32TXLen++; + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(psUI2C, u8Ctrl); /* Write controlbit to UI2C_CTL register */ + } + + return (u8Err | u8Xfering); +} + + +/** + * @brief Specify two bytes register address and write multi bytes to Slave + * + * @param[in] *psUI2C The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 bytes) of data write to + * @param[in] *pu8Data Pointer to array to write data to Slave + * @param[in] u32WLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for USCI_I2C Master specify a byte address that multi data write to in Slave. + * + */ + +uint32_t UI2C_WriteMultiBytesTwoRegs(UI2C_T *psUI2C, uint8_t u8SlaveAddr, uint16_t u16DataAddr, const uint8_t *pu8Data, uint32_t u32WLen) +{ + uint8_t u8Xfering = 1U, u8Addr = 1U, u8Ctrl = 0U; + uint32_t u32TXLen = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(psUI2C); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(psUI2C) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(psUI2C) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(psUI2C, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(psUI2C, (uint8_t)(u16DataAddr & 0xFF00U) >> 8U); /* Write Hi byte data address to UI2C_TXDAT */ + eEvent = MASTER_SEND_DATA; + } + else if (eEvent == MASTER_SEND_DATA) + { + if (u8Addr) + { + UI2C_SET_DATA(psUI2C, (uint8_t)(u16DataAddr & 0xFFU)); /* Write Lo byte data address to UI2C_TXDAT */ + u8Addr = 0; + } + else + { + if (u32TXLen < u32WLen) + { + UI2C_SET_DATA(psUI2C, pu8Data[u32TXLen++]); /* Write data to UI2C_TXDAT */ + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + } + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(psUI2C, u8Ctrl); /* Write controlbit to UI2C_CTL register */ + } + + return u32TXLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Read a byte from Slave + * + * @param[in] *psUI2C The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * + * @return Read a byte data from Slave + * + * @details The function is used for USCI_I2C Master to read a byte data from Slave. + * + */ +uint8_t UI2C_ReadByte(UI2C_T *psUI2C, uint8_t u8SlaveAddr) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, rdata = 0U, u8Ctrl = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(psUI2C); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(psUI2C) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(psUI2C) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(psUI2C, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + eEvent = MASTER_READ_DATA; + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if (eEvent == MASTER_SEND_H_RD_ADDRESS) + { + u8Err = 1U; + } + else + { + rdata = (unsigned char) UI2C_GET_DATA(psUI2C); /* Receive Data */ + } + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(psUI2C, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + if (u8Err) + rdata = 0U; + + return rdata; /* Return read data */ +} + + +/** + * @brief Read multi bytes from Slave + * + * @param[in] *psUI2C The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[out] *pu8Rdata Point to array to store data from Slave + * @param[in] u32RLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for USCI_I2C Master to read multi data bytes from Slave. + * + * + */ +uint32_t UI2C_ReadMultiBytes(UI2C_T *psUI2C, uint8_t u8SlaveAddr, uint8_t *pu8Rdata, uint32_t u32RLen) +{ + uint8_t u8Xfering = 1U, u8Ctrl = 0U; + uint32_t u32RXLen = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(psUI2C); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(psUI2C) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(psUI2C) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(psUI2C, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (eEvent == MASTER_SEND_H_RD_ADDRESS) + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + eEvent = MASTER_READ_DATA; + } + else + { + pu8Rdata[u32RXLen++] = (unsigned char) UI2C_GET_DATA(psUI2C); /* Receive Data */ + + if (u32RXLen < (u32RLen - 1U)) + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + else + u8Ctrl = UI2C_CTL_PTRG; + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if (eEvent == MASTER_READ_DATA) + pu8Rdata[u32RXLen++] = (unsigned char) UI2C_GET_DATA(psUI2C); /* Receive Data */ + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(psUI2C, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + return u32RXLen; /* Return bytes length that have been received */ +} + + +/** + * @brief Specify a byte register address and read a byte from Slave + * + * @param[in] *psUI2C The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address(1 byte) of data read from + * + * @return Read a byte data from Slave + * + * @details The function is used for USCI_I2C Master specify a byte address that a data byte read from Slave. + * + * + */ +uint8_t UI2C_ReadByteOneReg(UI2C_T *psUI2C, uint8_t u8SlaveAddr, uint8_t u8DataAddr) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, u8RData = 0U, u8Ctrl = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(psUI2C); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(psUI2C) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(psUI2C) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + + if (eEvent == MASTER_SEND_START) + { + UI2C_SET_DATA(psUI2C, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + } + else if (eEvent == MASTER_SEND_REPEAT_START) + { + UI2C_SET_DATA(psUI2C, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + } + + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(psUI2C, u8DataAddr); /* Write data address of register */ + u8Ctrl = UI2C_CTL_PTRG; + eEvent = MASTER_SEND_DATA; + } + else if (eEvent == MASTER_SEND_DATA) + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STA); /* Send repeat START signal */ + eEvent = MASTER_SEND_REPEAT_START; + } + else + { + /* SLA+R ACK */ + u8Ctrl = UI2C_CTL_PTRG; + eEvent = MASTER_READ_DATA; + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if (eEvent == MASTER_READ_DATA) + { + u8RData = (uint8_t) UI2C_GET_DATA(psUI2C); /* Receive Data */ + } + else + { + u8Err = 1U; + } + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(psUI2C, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + if (u8Err) + u8RData = 0U; /* If occurs error, return 0 */ + + return u8RData; /* Return read data */ +} + +/** + * @brief Specify a byte register address and read multi bytes from Slave + * + * @param[in] *psUI2C The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 bytes) of data read from + * @param[out] *pu8Rdata Point to array to store data from Slave + * @param[in] u32RLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for USCI_I2C Master specify a byte address that multi data bytes read from Slave. + * + * + */ +uint32_t UI2C_ReadMultiBytesOneReg(UI2C_T *psUI2C, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t *pu8Rdata, uint32_t u32RLen) +{ + uint8_t u8Xfering = 1U, u8Ctrl = 0U; + uint32_t u32RXLen = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(psUI2C); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(psUI2C) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(psUI2C) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + + if (eEvent == MASTER_SEND_START) + { + UI2C_SET_DATA(psUI2C, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + } + else if (eEvent == MASTER_SEND_REPEAT_START) + { + UI2C_SET_DATA(psUI2C, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + } + + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(psUI2C, u8DataAddr); /* Write data address of register */ + u8Ctrl = UI2C_CTL_PTRG; + eEvent = MASTER_SEND_DATA; + } + else if (eEvent == MASTER_SEND_DATA) + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STA); /* Send repeat START signal */ + eEvent = MASTER_SEND_REPEAT_START; + } + else if (eEvent == MASTER_SEND_H_RD_ADDRESS) + { + /* SLA+R ACK */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + eEvent = MASTER_READ_DATA; + } + else + { + pu8Rdata[u32RXLen++] = (uint8_t) UI2C_GET_DATA(psUI2C); /* Receive Data */ + + if (u32RXLen < u32RLen - 1U) + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + else + u8Ctrl = UI2C_CTL_PTRG; + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if (eEvent == MASTER_READ_DATA) + pu8Rdata[u32RXLen++] = (uint8_t) UI2C_GET_DATA(psUI2C); /* Receive Data */ + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(psUI2C, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + return u32RXLen; /* Return bytes length that have been received */ +} + +/** + * @brief Specify two bytes register address and read a byte from Slave + * + * @param[in] *psUI2C The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address(2 byte) of data read from + * + * @return Read a byte data from Slave + * + * @details The function is used for USCI_I2C Master specify two bytes address that a data byte read from Slave. + * + * + */ +uint8_t UI2C_ReadByteTwoRegs(UI2C_T *psUI2C, uint8_t u8SlaveAddr, uint16_t u16DataAddr) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, u8RData = 0U, u8Addr = 1U, u8Ctrl = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(psUI2C); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(psUI2C) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(psUI2C) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + + if (eEvent == MASTER_SEND_START) + { + UI2C_SET_DATA(psUI2C, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + } + else if (eEvent == MASTER_SEND_REPEAT_START) + { + UI2C_SET_DATA(psUI2C, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + } + + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(psUI2C, (uint8_t)(u16DataAddr & 0xFF00U) >> 8U); /* Write Hi byte address of register */ + eEvent = MASTER_SEND_DATA; + } + else if (eEvent == MASTER_SEND_DATA) + { + if (u8Addr) + { + UI2C_SET_DATA(psUI2C, (uint8_t)(u16DataAddr & 0xFFU)); /* Write Lo byte address of register */ + u8Addr = 0; + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STA); /* Send repeat START signal */ + eEvent = MASTER_SEND_REPEAT_START; + } + } + else + { + /* SLA+R ACK */ + u8Ctrl = UI2C_CTL_PTRG; + eEvent = MASTER_READ_DATA; + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if (eEvent == MASTER_READ_DATA) + { + u8RData = (uint8_t) UI2C_GET_DATA(psUI2C); /* Receive Data */ + } + else + { + u8Err = 1U; + } + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(psUI2C, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + if (u8Err) + u8RData = 0U; /* If occurs error, return 0 */ + + return u8RData; /* Return read data */ +} + +/** + * @brief Specify two bytes register address and read multi bytes from Slave + * + * @param[in] *psUI2C The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 bytes) of data read from + * @param[out] *pu8Rdata Point to array to store data from Slave + * @param[in] u32RLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for USCI_I2C Master specify two bytes address that multi data bytes read from Slave. + * + * + */ +uint32_t UI2C_ReadMultiBytesTwoRegs(UI2C_T *psUI2C, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t *pu8Rdata, uint32_t u32RLen) +{ + uint8_t u8Xfering = 1U, u8Addr = 1U, u8Ctrl = 0U; + uint32_t u32RXLen = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(psUI2C); /* Send START */ + + while (u8Xfering) + { + while (!(UI2C_GET_PROT_STATUS(psUI2C) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch (UI2C_GET_PROT_STATUS(psUI2C) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + + if (eEvent == MASTER_SEND_START) + { + UI2C_SET_DATA(psUI2C, (u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + } + else if (eEvent == MASTER_SEND_REPEAT_START) + { + UI2C_SET_DATA(psUI2C, (u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + } + + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if (eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(psUI2C, (uint8_t)(u16DataAddr & 0xFF00U) >> 8U); /* Write Hi byte address of register */ + eEvent = MASTER_SEND_DATA; + } + else if (eEvent == MASTER_SEND_DATA) + { + if (u8Addr) + { + UI2C_SET_DATA(psUI2C, (uint8_t)(u16DataAddr & 0xFFU)); /* Write Lo byte address of register */ + u8Addr = 0; + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STA); /* Send repeat START signal */ + eEvent = MASTER_SEND_REPEAT_START; + } + } + else if (eEvent == MASTER_SEND_H_RD_ADDRESS) + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + eEvent = MASTER_READ_DATA; + } + else + { + pu8Rdata[u32RXLen++] = (uint8_t) UI2C_GET_DATA(psUI2C); /* Receive Data */ + + if (u32RXLen < u32RLen - 1U) + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + else + u8Ctrl = UI2C_CTL_PTRG; + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if (eEvent == MASTER_READ_DATA) + pu8Rdata[u32RXLen++] = (uint8_t) UI2C_GET_DATA(psUI2C); /* Receive Data */ + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(psUI2C, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(psUI2C, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + return u32RXLen; /* Return bytes length that have been received */ +} + +/*@}*/ /* end of group USCI_I2C_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USCI_I2C_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_usci_spi.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_usci_spi.c new file mode 100644 index 00000000000..cf36b1bdcd7 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_usci_spi.c @@ -0,0 +1,708 @@ +/****************************************************************************//** + * @file usci_spi.c + * @version V0.10 + * @brief M251 series USCI_SPI driver source file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_SPI_Driver USCI_SPI Driver + @{ +*/ + + +/** @addtogroup USCI_SPI_EXPORTED_FUNCTIONS USCI_SPI Exported Functions + @{ +*/ + +/** + * @brief This function make USCI_SPI module be ready to transfer. + * By default, the USCI_SPI transfer sequence is MSB first, the slave selection + * signal is active low and the automatic slave select function is disabled. In + * Slave mode, the u32BusClock must be NULL and the USCI_SPI clock + * divider setting will be 0. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @param[in] u32MasterSlave Decide the USCI_SPI module is operating in master mode or in slave mode. Valid values are: + * - \ref USPI_SLAVE + * - \ref USPI_MASTER + * @param[in] u32SPIMode Decide the transfer timing. Valid values are: + * - \ref USPI_MODE_0 + * - \ref USPI_MODE_1 + * - \ref USPI_MODE_2 + * - \ref USPI_MODE_3 + * @param[in] u32DataWidth The data width of a USCI_SPI transaction. + * @param[in] u32BusClock The expected frequency of USCI_SPI bus clock in Hz. + * @return Actual frequency of USCI_SPI peripheral clock. + */ +uint32_t USPI_Open(USPI_T *psUSPI, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock) +{ + uint32_t u32ClkDiv = 0ul; + uint32_t u32Pclk; + uint32_t u32UspiClk = 0ul; + + if ((psUSPI == (USPI_T *)USPI0) || (psUSPI == (USPI_T *)USPI2)) + { + u32Pclk = CLK_GetPCLK0Freq(); + } + else + { + u32Pclk = CLK_GetPCLK1Freq(); + } + + if (u32BusClock != 0ul) + { + u32ClkDiv = (uint32_t)((((((u32Pclk / 2ul) * 10ul) / (u32BusClock)) + 5ul) / 10ul) - 1ul); /* Compute proper divider for USCI_SPI clock */ + } + else {} + + /* Enable USCI_SPI protocol */ + psUSPI->CTL &= ~USPI_CTL_FUNMODE_Msk; + psUSPI->CTL = 1ul << USPI_CTL_FUNMODE_Pos; + + /* Data format configuration */ + if (u32DataWidth == 16ul) + { + u32DataWidth = 0ul; + } + else {} + + psUSPI->LINECTL &= ~USPI_LINECTL_DWIDTH_Msk; + psUSPI->LINECTL |= (u32DataWidth << USPI_LINECTL_DWIDTH_Pos); + + /* MSB data format */ + psUSPI->LINECTL &= ~USPI_LINECTL_LSB_Msk; + + /* Set slave selection signal active low */ + if (u32MasterSlave == USPI_MASTER) + { + psUSPI->LINECTL |= USPI_LINECTL_CTLOINV_Msk; + } + else + { + psUSPI->CTLIN0 |= USPI_CTLIN0_ININV_Msk; + } + + /* Set operating mode and transfer timing */ + psUSPI->PROTCTL &= ~(USPI_PROTCTL_SCLKMODE_Msk | USPI_PROTCTL_AUTOSS_Msk | USPI_PROTCTL_SLAVE_Msk); + psUSPI->PROTCTL |= (u32MasterSlave | u32SPIMode); + + /* Set USCI_SPI bus clock */ + psUSPI->BRGEN &= ~USPI_BRGEN_CLKDIV_Msk; + psUSPI->BRGEN |= (u32ClkDiv << USPI_BRGEN_CLKDIV_Pos); + psUSPI->PROTCTL |= USPI_PROTCTL_PROTEN_Msk; + + if (u32BusClock != 0ul) + { + u32UspiClk = (uint32_t)(u32Pclk / ((u32ClkDiv + 1ul) << 1)); + } + else {} + + return u32UspiClk; +} + +/** + * @brief Disable USCI_SPI function mode. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_Close(USPI_T *psUSPI) +{ + psUSPI->CTL &= ~USPI_CTL_FUNMODE_Msk; +} + +/** + * @brief Clear Rx buffer. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_ClearRxBuf(USPI_T *psUSPI) +{ + psUSPI->BUFCTL |= USPI_BUFCTL_RXCLR_Msk; +} + +/** + * @brief Clear Tx buffer. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_ClearTxBuf(USPI_T *psUSPI) +{ + psUSPI->BUFCTL |= USPI_BUFCTL_TXCLR_Msk; +} + +/** + * @brief Disable the automatic slave select function. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_DisableAutoSS(USPI_T *psUSPI) +{ + psUSPI->PROTCTL &= ~(USPI_PROTCTL_AUTOSS_Msk | USPI_PROTCTL_SS_Msk); +} + +/** + * @brief Enable the automatic slave select function. Only available in Master mode. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @param[in] u32SSPinMask This parameter is not used. + * @param[in] u32ActiveLevel The active level of slave select signal. Valid values are: + * - \ref USPI_SS_ACTIVE_HIGH + * - \ref USPI_SS_ACTIVE_LOW + * @return None + */ +void USPI_EnableAutoSS(USPI_T *psUSPI, uint32_t u32SSPinMask, uint32_t u32ActiveLevel) +{ + psUSPI->LINECTL = (psUSPI->LINECTL & ~USPI_LINECTL_CTLOINV_Msk) | u32ActiveLevel; + psUSPI->PROTCTL |= USPI_PROTCTL_AUTOSS_Msk; +} + +/** + * @brief Set the USCI_SPI bus clock. Only available in Master mode. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @param[in] u32BusClock The expected frequency of USCI_SPI bus clock. + * @return Actual frequency of USCI_SPI peripheral clock. + */ +uint32_t USPI_SetBusClock(USPI_T *psUSPI, uint32_t u32BusClock) +{ + uint32_t u32ClkDiv; + uint32_t u32Pclk; + + if ((psUSPI == USPI0) || (psUSPI == USPI2)) + { + u32Pclk = CLK_GetPCLK0Freq(); + } + else + { + u32Pclk = CLK_GetPCLK1Freq(); + } + + u32ClkDiv = (uint32_t)((((((u32Pclk / 2ul) * 10ul) / (u32BusClock)) + 5ul) / 10ul) - 1ul); /* Compute proper divider for USCI_SPI clock */ + + /* Set USCI_SPI bus clock */ + psUSPI->BRGEN &= ~USPI_BRGEN_CLKDIV_Msk; + psUSPI->BRGEN |= (u32ClkDiv << USPI_BRGEN_CLKDIV_Pos); + + return (u32Pclk / ((u32ClkDiv + 1ul) << 1)); +} + +/** + * @brief Get the actual frequency of USCI_SPI bus clock. Only available in Master mode. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @return Actual USCI_SPI bus clock frequency. + */ +uint32_t USPI_GetBusClock(USPI_T *psUSPI) +{ + uint32_t u32BusClk; + uint32_t u32ClkDiv; + + u32ClkDiv = (psUSPI->BRGEN & USPI_BRGEN_CLKDIV_Msk) >> USPI_BRGEN_CLKDIV_Pos; + + if ((psUSPI == USPI0) || (psUSPI == USPI2)) + { + u32BusClk = (uint32_t)(CLK_GetPCLK0Freq() / ((u32ClkDiv + 1ul) << 1)); + } + else + { + u32BusClk = (uint32_t)(CLK_GetPCLK1Freq() / ((u32ClkDiv + 1ul) << 1)); + } + + return u32BusClk; +} + +/** + * @brief Enable related interrupts specified by u32Mask parameter. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * This parameter decides which interrupts will be enabled. Valid values are: + * - \ref USPI_SSINACT_INT_MASK + * - \ref USPI_SSACT_INT_MASK + * - \ref USPI_SLVTO_INT_MASK + * - \ref USPI_SLVBE_INT_MASK + * - \ref USPI_TXUDR_INT_MASK + * - \ref USPI_RXOV_INT_MASK + * - \ref USPI_TXST_INT_MASK + * - \ref USPI_TXEND_INT_MASK + * - \ref USPI_RXST_INT_MASK + * - \ref USPI_RXEND_INT_MASK + * @return None + */ +void USPI_EnableInt(USPI_T *psUSPI, uint32_t u32Mask) +{ + /* Enable slave selection signal inactive interrupt flag */ + if ((u32Mask & USPI_SSINACT_INT_MASK) == USPI_SSINACT_INT_MASK) + { + psUSPI->PROTIEN |= USPI_PROTIEN_SSINAIEN_Msk; + } + else {} + + /* Enable slave selection signal active interrupt flag */ + if ((u32Mask & USPI_SSACT_INT_MASK) == USPI_SSACT_INT_MASK) + { + psUSPI->PROTIEN |= USPI_PROTIEN_SSACTIEN_Msk; + } + else {} + + /* Enable slave time-out interrupt flag */ + if ((u32Mask & USPI_SLVTO_INT_MASK) == USPI_SLVTO_INT_MASK) + { + psUSPI->PROTIEN |= USPI_PROTIEN_SLVTOIEN_Msk; + } + else {} + + /* Enable slave bit count error interrupt flag */ + if ((u32Mask & USPI_SLVBE_INT_MASK) == USPI_SLVBE_INT_MASK) + { + psUSPI->PROTIEN |= USPI_PROTIEN_SLVBEIEN_Msk; + } + else {} + + /* Enable TX under run interrupt flag */ + if ((u32Mask & USPI_TXUDR_INT_MASK) == USPI_TXUDR_INT_MASK) + { + psUSPI->BUFCTL |= USPI_BUFCTL_TXUDRIEN_Msk; + } + else {} + + /* Enable RX overrun interrupt flag */ + if ((u32Mask & USPI_RXOV_INT_MASK) == USPI_RXOV_INT_MASK) + { + psUSPI->BUFCTL |= USPI_BUFCTL_RXOVIEN_Msk; + } + else {} + + /* Enable TX start interrupt flag */ + if ((u32Mask & USPI_TXST_INT_MASK) == USPI_TXST_INT_MASK) + { + psUSPI->INTEN |= USPI_INTEN_TXSTIEN_Msk; + } + else {} + + /* Enable TX end interrupt flag */ + if ((u32Mask & USPI_TXEND_INT_MASK) == USPI_TXEND_INT_MASK) + { + psUSPI->INTEN |= USPI_INTEN_TXENDIEN_Msk; + } + else {} + + /* Enable RX start interrupt flag */ + if ((u32Mask & USPI_RXST_INT_MASK) == USPI_RXST_INT_MASK) + { + psUSPI->INTEN |= USPI_INTEN_RXSTIEN_Msk; + } + else {} + + /* Enable RX end interrupt flag */ + if ((u32Mask & USPI_RXEND_INT_MASK) == USPI_RXEND_INT_MASK) + { + psUSPI->INTEN |= USPI_INTEN_RXENDIEN_Msk; + } + else {} +} + +/** + * @brief Disable related interrupts specified by u32Mask parameter. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * This parameter decides which interrupts will be disabled. Valid values are: + * - \ref USPI_SSINACT_INT_MASK + * - \ref USPI_SSACT_INT_MASK + * - \ref USPI_SLVTO_INT_MASK + * - \ref USPI_SLVBE_INT_MASK + * - \ref USPI_TXUDR_INT_MASK + * - \ref USPI_RXOV_INT_MASK + * - \ref USPI_TXST_INT_MASK + * - \ref USPI_TXEND_INT_MASK + * - \ref USPI_RXST_INT_MASK + * - \ref USPI_RXEND_INT_MASK + * @return None + */ +void USPI_DisableInt(USPI_T *psUSPI, uint32_t u32Mask) +{ + /* Disable slave selection signal inactive interrupt flag */ + if ((u32Mask & USPI_SSINACT_INT_MASK) == USPI_SSINACT_INT_MASK) + { + psUSPI->PROTIEN &= ~USPI_PROTIEN_SSINAIEN_Msk; + } + else {} + + /* Disable slave selection signal active interrupt flag */ + if ((u32Mask & USPI_SSACT_INT_MASK) == USPI_SSACT_INT_MASK) + { + psUSPI->PROTIEN &= ~USPI_PROTIEN_SSACTIEN_Msk; + } + else {} + + /* Disable slave time-out interrupt flag */ + if ((u32Mask & USPI_SLVTO_INT_MASK) == USPI_SLVTO_INT_MASK) + { + psUSPI->PROTIEN &= ~USPI_PROTIEN_SLVTOIEN_Msk; + } + else {} + + /* Disable slave bit count error interrupt flag */ + if ((u32Mask & USPI_SLVBE_INT_MASK) == USPI_SLVBE_INT_MASK) + { + psUSPI->PROTIEN &= ~USPI_PROTIEN_SLVBEIEN_Msk; + } + else {} + + /* Disable TX under run interrupt flag */ + if ((u32Mask & USPI_TXUDR_INT_MASK) == USPI_TXUDR_INT_MASK) + { + psUSPI->BUFCTL &= ~USPI_BUFCTL_TXUDRIEN_Msk; + } + else {} + + /* Disable RX overrun interrupt flag */ + if ((u32Mask & USPI_RXOV_INT_MASK) == USPI_RXOV_INT_MASK) + { + psUSPI->BUFCTL &= ~USPI_BUFCTL_RXOVIEN_Msk; + } + else {} + + /* Disable TX start interrupt flag */ + if ((u32Mask & USPI_TXST_INT_MASK) == USPI_TXST_INT_MASK) + { + psUSPI->INTEN &= ~USPI_INTEN_TXSTIEN_Msk; + } + else {} + + /* Disable TX end interrupt flag */ + if ((u32Mask & USPI_TXEND_INT_MASK) == USPI_TXEND_INT_MASK) + { + psUSPI->INTEN &= ~USPI_INTEN_TXENDIEN_Msk; + } + else {} + + /* Disable RX start interrupt flag */ + if ((u32Mask & USPI_RXST_INT_MASK) == USPI_RXST_INT_MASK) + { + psUSPI->INTEN &= ~USPI_INTEN_RXSTIEN_Msk; + } + else {} + + /* Disable RX end interrupt flag */ + if ((u32Mask & USPI_RXEND_INT_MASK) == USPI_RXEND_INT_MASK) + { + psUSPI->INTEN &= ~USPI_INTEN_RXENDIEN_Msk; + } + else {} +} + +/** + * @brief Get interrupt flag. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be read. It is combination of: + * - \ref USPI_SSINACT_INT_MASK + * - \ref USPI_SSACT_INT_MASK + * - \ref USPI_SLVTO_INT_MASK + * - \ref USPI_SLVBE_INT_MASK + * - \ref USPI_TXUDR_INT_MASK + * - \ref USPI_RXOV_INT_MASK + * - \ref USPI_TXST_INT_MASK + * - \ref USPI_TXEND_INT_MASK + * - \ref USPI_RXST_INT_MASK + * - \ref USPI_RXEND_INT_MASK + * @return Interrupt flags of selected sources. + */ +uint32_t USPI_GetIntFlag(USPI_T *psUSPI, uint32_t u32Mask) +{ + uint32_t u32TmpFlag; + uint32_t u32IntFlag = 0ul; + + /* Check slave selection signal inactive interrupt flag */ + u32TmpFlag = psUSPI->PROTSTS & USPI_PROTSTS_SSINAIF_Msk; + + if (((u32Mask & USPI_SSINACT_INT_MASK) == USPI_SSINACT_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_SSINAIF_Msk)) + { + u32IntFlag |= USPI_SSINACT_INT_MASK; + } + else {} + + /* Check slave selection signal active interrupt flag */ + + u32TmpFlag = psUSPI->PROTSTS & USPI_PROTSTS_SSACTIF_Msk; + + if (((u32Mask & USPI_SSACT_INT_MASK) == USPI_SSACT_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_SSACTIF_Msk)) + { + u32IntFlag |= USPI_SSACT_INT_MASK; + } + else {} + + /* Check slave time-out interrupt flag */ + u32TmpFlag = psUSPI->PROTSTS & USPI_PROTSTS_SLVTOIF_Msk; + + if (((u32Mask & USPI_SLVTO_INT_MASK) == USPI_SLVTO_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_SLVTOIF_Msk)) + { + u32IntFlag |= USPI_SLVTO_INT_MASK; + } + else {} + + /* Check slave bit count error interrupt flag */ + u32TmpFlag = psUSPI->PROTSTS & USPI_PROTSTS_SLVBEIF_Msk; + + if (((u32Mask & USPI_SLVBE_INT_MASK) == USPI_SLVBE_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_SLVBEIF_Msk)) + { + u32IntFlag |= USPI_SLVBE_INT_MASK; + } + else {} + + /* Check TX under run interrupt flag */ + u32TmpFlag = psUSPI->BUFSTS & USPI_BUFSTS_TXUDRIF_Msk; + + if (((u32Mask & USPI_TXUDR_INT_MASK) == USPI_TXUDR_INT_MASK) && (u32TmpFlag == USPI_BUFSTS_TXUDRIF_Msk)) + { + u32IntFlag |= USPI_TXUDR_INT_MASK; + } + else {} + + /* Check RX overrun interrupt flag */ + u32TmpFlag = psUSPI->BUFSTS & USPI_BUFSTS_RXOVIF_Msk; + + if (((u32Mask & USPI_RXOV_INT_MASK) == USPI_RXOV_INT_MASK) && (u32TmpFlag == USPI_BUFSTS_RXOVIF_Msk)) + { + u32IntFlag |= USPI_RXOV_INT_MASK; + } + else {} + + /* Check TX start interrupt flag */ + u32TmpFlag = psUSPI->PROTSTS & USPI_PROTSTS_TXSTIF_Msk; + + if (((u32Mask & USPI_TXST_INT_MASK) == USPI_TXST_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_TXSTIF_Msk)) + { + u32IntFlag |= USPI_TXST_INT_MASK; + } + else {} + + /* Check TX end interrupt flag */ + u32TmpFlag = psUSPI->PROTSTS & USPI_PROTSTS_TXENDIF_Msk; + + if (((u32Mask & USPI_TXEND_INT_MASK) == USPI_TXEND_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_TXENDIF_Msk)) + { + u32IntFlag |= USPI_TXEND_INT_MASK; + } + else {} + + /* Check RX start interrupt flag */ + u32TmpFlag = psUSPI->PROTSTS & USPI_PROTSTS_RXSTIF_Msk; + + if (((u32Mask & USPI_RXST_INT_MASK) == USPI_RXST_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_RXSTIF_Msk)) + { + u32IntFlag |= USPI_RXST_INT_MASK; + } + else {} + + /* Check RX end interrupt flag */ + u32TmpFlag = psUSPI->PROTSTS & USPI_PROTSTS_RXENDIF_Msk; + + if (((u32Mask & USPI_RXEND_INT_MASK) == USPI_RXEND_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_RXENDIF_Msk)) + { + u32IntFlag |= USPI_RXEND_INT_MASK; + } + else {} + + return u32IntFlag; +} + +/** + * @brief Clear interrupt flag. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. It could be the combination of: + * - \ref USPI_SSINACT_INT_MASK + * - \ref USPI_SSACT_INT_MASK + * - \ref USPI_SLVTO_INT_MASK + * - \ref USPI_SLVBE_INT_MASK + * - \ref USPI_TXUDR_INT_MASK + * - \ref USPI_RXOV_INT_MASK + * - \ref USPI_TXST_INT_MASK + * - \ref USPI_TXEND_INT_MASK + * - \ref USPI_RXST_INT_MASK + * - \ref USPI_RXEND_INT_MASK + * @return None + */ +void USPI_ClearIntFlag(USPI_T *psUSPI, uint32_t u32Mask) +{ + /* Clear slave selection signal inactive interrupt flag */ + if ((u32Mask & USPI_SSINACT_INT_MASK) == USPI_SSINACT_INT_MASK) + { + psUSPI->PROTSTS = USPI_PROTSTS_SSINAIF_Msk; + } + else {} + + /* Clear slave selection signal active interrupt flag */ + if ((u32Mask & USPI_SSACT_INT_MASK) == USPI_SSACT_INT_MASK) + { + psUSPI->PROTSTS = USPI_PROTSTS_SSACTIF_Msk; + } + else {} + + /* Clear slave time-out interrupt flag */ + if ((u32Mask & USPI_SLVTO_INT_MASK) == USPI_SLVTO_INT_MASK) + { + psUSPI->PROTSTS = USPI_PROTSTS_SLVTOIF_Msk; + } + else {} + + /* Clear slave bit count error interrupt flag */ + if ((u32Mask & USPI_SLVBE_INT_MASK) == USPI_SLVBE_INT_MASK) + { + psUSPI->PROTSTS = USPI_PROTSTS_SLVBEIF_Msk; + } + else {} + + /* Clear TX under run interrupt flag */ + if ((u32Mask & USPI_TXUDR_INT_MASK) == USPI_TXUDR_INT_MASK) + { + psUSPI->BUFSTS = USPI_BUFSTS_TXUDRIF_Msk; + } + else {} + + /* Clear RX overrun interrupt flag */ + if ((u32Mask & USPI_RXOV_INT_MASK) == USPI_RXOV_INT_MASK) + { + psUSPI->BUFSTS = USPI_BUFSTS_RXOVIF_Msk; + } + else {} + + /* Clear TX start interrupt flag */ + if ((u32Mask & USPI_TXST_INT_MASK) == USPI_TXST_INT_MASK) + { + psUSPI->PROTSTS = USPI_PROTSTS_TXSTIF_Msk; + } + else {} + + /* Clear TX end interrupt flag */ + if ((u32Mask & USPI_TXEND_INT_MASK) == USPI_TXEND_INT_MASK) + { + psUSPI->PROTSTS = USPI_PROTSTS_TXENDIF_Msk; + } + else {} + + /* Clear RX start interrupt flag */ + if ((u32Mask & USPI_RXST_INT_MASK) == USPI_RXST_INT_MASK) + { + psUSPI->PROTSTS = USPI_PROTSTS_RXSTIF_Msk; + } + else {} + + /* Clear RX end interrupt flag */ + if ((u32Mask & USPI_RXEND_INT_MASK) == USPI_RXEND_INT_MASK) + { + psUSPI->PROTSTS = USPI_PROTSTS_RXENDIF_Msk; + } + else {} +} + +/** + * @brief Get USCI_SPI status. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @param[in] u32Mask The combination of all related sources. + * Each bit corresponds to a source. + * This parameter decides which flags will be read. It is combination of: + * - \ref USPI_BUSY_MASK + * - \ref USPI_RX_EMPTY_MASK + * - \ref USPI_RX_FULL_MASK + * - \ref USPI_TX_EMPTY_MASK + * - \ref USPI_TX_FULL_MASK + * - \ref USPI_SSLINE_STS_MASK + * @return Flags of selected sources. + */ +uint32_t USPI_GetStatus(USPI_T *psUSPI, uint32_t u32Mask) +{ + uint32_t u32Flag = 0ul; + uint32_t u32TmpFlag; + + /* Check busy status */ + u32TmpFlag = psUSPI->PROTSTS & USPI_PROTSTS_BUSY_Msk; + + if (((u32Mask & USPI_BUSY_MASK) == USPI_BUSY_MASK) && (u32TmpFlag & USPI_PROTSTS_BUSY_Msk)) + { + u32Flag |= USPI_BUSY_MASK; + } + else {} + + /* Check RX empty flag */ + u32TmpFlag = psUSPI->BUFSTS & USPI_BUFSTS_RXEMPTY_Msk; + + if (((u32Mask & USPI_RX_EMPTY_MASK) == USPI_RX_EMPTY_MASK) && (u32TmpFlag == USPI_BUFSTS_RXEMPTY_Msk)) + { + u32Flag |= USPI_RX_EMPTY_MASK; + } + else {} + + /* Check RX full flag */ + u32TmpFlag = psUSPI->BUFSTS & USPI_BUFSTS_RXFULL_Msk; + + if (((u32Mask & USPI_RX_FULL_MASK) == USPI_RX_FULL_MASK) && (u32TmpFlag == USPI_BUFSTS_RXFULL_Msk)) + { + u32Flag |= USPI_RX_FULL_MASK; + } + else {} + + /* Check TX empty flag */ + u32TmpFlag = psUSPI->BUFSTS & USPI_BUFSTS_TXEMPTY_Msk; + + if (((u32Mask & USPI_TX_EMPTY_MASK) == USPI_TX_EMPTY_MASK) && (u32TmpFlag == USPI_BUFSTS_TXEMPTY_Msk)) + { + u32Flag |= USPI_TX_EMPTY_MASK; + } + else {} + + /* Check TX full flag */ + u32TmpFlag = psUSPI->BUFSTS & USPI_BUFSTS_TXFULL_Msk; + + if (((u32Mask & USPI_TX_FULL_MASK) == USPI_TX_FULL_MASK) && (u32TmpFlag == USPI_BUFSTS_TXFULL_Msk)) + { + u32Flag |= USPI_TX_FULL_MASK; + } + else {} + + /* Check USCI_SPI_SS line status */ + u32TmpFlag = psUSPI->PROTSTS & USPI_PROTSTS_SSLINE_Msk; + + if (((u32Mask & USPI_SSLINE_STS_MASK) == USPI_SSLINE_STS_MASK) && (u32TmpFlag & USPI_PROTSTS_SSLINE_Msk)) + { + u32Flag |= USPI_SSLINE_STS_MASK; + } + else {} + + return u32Flag; +} + +/** + * @brief Enable USCI_SPI Wake-up Function. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_EnableWakeup(USPI_T *psUSPI) +{ + psUSPI->WKCTL |= USPI_WKCTL_WKEN_Msk; +} + +/** + * @brief Disable USCI_SPI Wake-up Function. + * @param[in] psUSPI The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_DisableWakeup(USPI_T *psUSPI) +{ + psUSPI->WKCTL &= ~USPI_WKCTL_WKEN_Msk; +} + +/*@}*/ /* end of group USCI_SPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USCI_SPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_usci_uart.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_usci_uart.c new file mode 100644 index 00000000000..7f60da27ee3 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_usci_uart.c @@ -0,0 +1,748 @@ +/**************************************************************************//** + * @file usci_uart.c + * @version V0.10 + * @brief M251 series USCI UART (UUART) driver source file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_UART_Driver USCI_UART Driver + @{ +*/ + +/** @addtogroup USCI_UART_EXPORTED_FUNCTIONS USCI_UART Exported Functions + @{ +*/ + +/** + * @brief Clear USCI_UART specified interrupt flag + * + * @param[in] psUUART The pointer of the specified USCI_UART module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. It could be the combination of: + * - \ref UUART_ABR_INT_MASK + * - \ref UUART_RLS_INT_MASK + * - \ref UUART_BUF_RXOV_INT_MASK + * - \ref UUART_TXST_INT_MASK + * - \ref UUART_TXEND_INT_MASK + * - \ref UUART_RXST_INT_MASK + * - \ref UUART_RXEND_INT_MASK + * + * @return None + * + * @details The function is used to clear USCI_UART related interrupt flags specified by u32Mask parameter. + */ + +void UUART_ClearIntFlag(UUART_T *psUUART, uint32_t u32Mask) +{ + + if (u32Mask & UUART_ABR_INT_MASK) /* Clear Auto-baud Rate Interrupt */ + { + psUUART->PROTSTS = UUART_PROTSTS_ABRDETIF_Msk; + } + + if (u32Mask & UUART_RLS_INT_MASK) /* Clear Receive Line Status Interrupt */ + { + psUUART->PROTSTS = (UUART_PROTSTS_BREAK_Msk | UUART_PROTSTS_FRMERR_Msk | UUART_PROTSTS_PARITYERR_Msk); + } + + if (u32Mask & UUART_BUF_RXOV_INT_MASK) /* Clear Receive Buffer Over-run Error Interrupt */ + { + psUUART->BUFSTS = UUART_BUFSTS_RXOVIF_Msk; + } + + if (u32Mask & UUART_TXST_INT_MASK) /* Clear Transmit Start Interrupt */ + { + psUUART->PROTSTS = UUART_PROTSTS_TXSTIF_Msk; + } + + if (u32Mask & UUART_TXEND_INT_MASK) /* Clear Transmit End Interrupt */ + { + psUUART->PROTSTS = UUART_PROTSTS_TXENDIF_Msk; + } + + if (u32Mask & UUART_RXST_INT_MASK) /* Clear Receive Start Interrupt */ + { + psUUART->PROTSTS = UUART_PROTSTS_RXSTIF_Msk; + } + + if (u32Mask & UUART_RXEND_INT_MASK) /* Clear Receive End Interrupt */ + { + psUUART->PROTSTS = UUART_PROTSTS_RXENDIF_Msk; + } + +} + +/** + * @brief Get USCI_UART specified interrupt flag + * + * @param[in] psUUART The pointer of the specified USCI_UART module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be read. It is combination of: + * - \ref UUART_ABR_INT_MASK + * - \ref UUART_RLS_INT_MASK + * - \ref UUART_BUF_RXOV_INT_MASK + * - \ref UUART_TXST_INT_MASK + * - \ref UUART_TXEND_INT_MASK + * - \ref UUART_RXST_INT_MASK + * - \ref UUART_RXEND_INT_MASK + * + * @return Interrupt flags of selected sources. + * + * @details The function is used to get USCI_UART related interrupt flags specified by u32Mask parameter. + */ + +uint32_t UUART_GetIntFlag(UUART_T *psUUART, uint32_t u32Mask) +{ + uint32_t u32IntFlag = 0ul; + uint32_t u32Tmp1, u32Tmp2; + + /* Check Auto-baud Rate Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_ABR_INT_MASK); + u32Tmp2 = (psUUART->PROTSTS & UUART_PROTSTS_ABRDETIF_Msk); + + if (u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_ABR_INT_MASK; + } + + /* Check Receive Line Status Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_RLS_INT_MASK); + u32Tmp2 = (psUUART->PROTSTS & (UUART_PROTSTS_BREAK_Msk | UUART_PROTSTS_FRMERR_Msk | UUART_PROTSTS_PARITYERR_Msk)); + + if (u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_RLS_INT_MASK; + } + + /* Check Receive Buffer Over-run Error Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_BUF_RXOV_INT_MASK); + u32Tmp2 = (psUUART->BUFSTS & UUART_BUFSTS_RXOVIF_Msk); + + if (u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_BUF_RXOV_INT_MASK; + } + + /* Check Transmit Start Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_TXST_INT_MASK); + u32Tmp2 = (psUUART->PROTSTS & UUART_PROTSTS_TXSTIF_Msk); + + if (u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_TXST_INT_MASK; + } + + /* Check Transmit End Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_TXEND_INT_MASK); + u32Tmp2 = (psUUART->PROTSTS & UUART_PROTSTS_TXENDIF_Msk); + + if (u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_TXEND_INT_MASK; + } + + /* Check Receive Start Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_RXST_INT_MASK); + u32Tmp2 = (psUUART->PROTSTS & UUART_PROTSTS_RXSTIF_Msk); + + if (u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_RXST_INT_MASK; + } + + /* Check Receive End Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_RXEND_INT_MASK); + u32Tmp2 = (psUUART->PROTSTS & UUART_PROTSTS_RXENDIF_Msk); + + if (u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_RXEND_INT_MASK; + } + + return u32IntFlag; + +} + + +/** + * @brief Disable USCI_UART function mode + * + * @param[in] psUUART The pointer of the specified USCI_UART module. + * + * @return None + * + * @details The function is used to disable USCI_UART function mode. + */ +void UUART_Close(UUART_T *psUUART) +{ + psUUART->CTL = 0ul; +} + + +/** + * @brief Disable interrupt function. + * + * @param[in] psUUART The pointer of the specified USCI_UART module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be disabled. It is combination of: + * - \ref UUART_ABR_INT_MASK + * - \ref UUART_RLS_INT_MASK + * - \ref UUART_BUF_RXOV_INT_MASK + * - \ref UUART_TXST_INT_MASK + * - \ref UUART_TXEND_INT_MASK + * - \ref UUART_RXST_INT_MASK + * - \ref UUART_RXEND_INT_MASK + * + * @return None + * + * @details The function is used to disabled USCI_UART related interrupts specified by u32Mask parameter. + */ +void UUART_DisableInt(UUART_T *psUUART, uint32_t u32Mask) +{ + + /* Disable Auto-baud rate interrupt flag */ + if ((u32Mask & UUART_ABR_INT_MASK) == UUART_ABR_INT_MASK) + { + psUUART->PROTIEN &= ~UUART_PROTIEN_ABRIEN_Msk; + } + + /* Disable receive line status interrupt flag */ + if ((u32Mask & UUART_RLS_INT_MASK) == UUART_RLS_INT_MASK) + { + psUUART->PROTIEN &= ~UUART_PROTIEN_RLSIEN_Msk; + } + + /* Disable RX overrun interrupt flag */ + if ((u32Mask & UUART_BUF_RXOV_INT_MASK) == UUART_BUF_RXOV_INT_MASK) + { + psUUART->BUFCTL &= ~UUART_BUFCTL_RXOVIEN_Msk; + } + + /* Disable TX start interrupt flag */ + if ((u32Mask & UUART_TXST_INT_MASK) == UUART_TXST_INT_MASK) + { + psUUART->INTEN &= ~UUART_INTEN_TXSTIEN_Msk; + } + + /* Disable TX end interrupt flag */ + if ((u32Mask & UUART_TXEND_INT_MASK) == UUART_TXEND_INT_MASK) + { + psUUART->INTEN &= ~UUART_INTEN_TXENDIEN_Msk; + } + + /* Disable RX start interrupt flag */ + if ((u32Mask & UUART_RXST_INT_MASK) == UUART_RXST_INT_MASK) + { + psUUART->INTEN &= ~UUART_INTEN_RXSTIEN_Msk; + } + + /* Disable RX end interrupt flag */ + if ((u32Mask & UUART_RXEND_INT_MASK) == UUART_RXEND_INT_MASK) + { + psUUART->INTEN &= ~UUART_INTEN_RXENDIEN_Msk; + } +} + + +/** + * @brief Enable interrupt function. + * + * @param[in] psUUART The pointer of the specified USCI_UART module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be enabled. It is combination of: + * - \ref UUART_ABR_INT_MASK + * - \ref UUART_RLS_INT_MASK + * - \ref UUART_BUF_RXOV_INT_MASK + * - \ref UUART_TXST_INT_MASK + * - \ref UUART_TXEND_INT_MASK + * - \ref UUART_RXST_INT_MASK + * - \ref UUART_RXEND_INT_MASK + * + * @return None + * + * @details The function is used to enable USCI_UART related interrupts specified by u32Mask parameter. + */ +void UUART_EnableInt(UUART_T *psUUART, uint32_t u32Mask) +{ + /* Enable Auto-baud rate interrupt flag */ + if ((u32Mask & UUART_ABR_INT_MASK) == UUART_ABR_INT_MASK) + { + psUUART->PROTIEN |= UUART_PROTIEN_ABRIEN_Msk; + } + + /* Enable receive line status interrupt flag */ + if ((u32Mask & UUART_RLS_INT_MASK) == UUART_RLS_INT_MASK) + { + psUUART->PROTIEN |= UUART_PROTIEN_RLSIEN_Msk; + } + + /* Enable RX overrun interrupt flag */ + if ((u32Mask & UUART_BUF_RXOV_INT_MASK) == UUART_BUF_RXOV_INT_MASK) + { + psUUART->BUFCTL |= UUART_BUFCTL_RXOVIEN_Msk; + } + + /* Enable TX start interrupt flag */ + if ((u32Mask & UUART_TXST_INT_MASK) == UUART_TXST_INT_MASK) + { + psUUART->INTEN |= UUART_INTEN_TXSTIEN_Msk; + } + + /* Enable TX end interrupt flag */ + if ((u32Mask & UUART_TXEND_INT_MASK) == UUART_TXEND_INT_MASK) + { + psUUART->INTEN |= UUART_INTEN_TXENDIEN_Msk; + } + + /* Enable RX start interrupt flag */ + if ((u32Mask & UUART_RXST_INT_MASK) == UUART_RXST_INT_MASK) + { + psUUART->INTEN |= UUART_INTEN_RXSTIEN_Msk; + } + + /* Enable RX end interrupt flag */ + if ((u32Mask & UUART_RXEND_INT_MASK) == UUART_RXEND_INT_MASK) + { + psUUART->INTEN |= UUART_INTEN_RXENDIEN_Msk; + } +} + + +/** + * @brief Open and set USCI_UART function + * + * @param[in] psUUART The pointer of the specified USCI_UART module. + * @param[in] u32Baudrate The baud rate of USCI_UART module. + * + * @return Real baud rate of USCI_UART module. + * + * @details This function use to enable USCI_UART function and set baud-rate. + */ +uint32_t UUART_Open(UUART_T *psUUART, uint32_t u32Baudrate) +{ + uint32_t u32PCLKFreq, u32PDSCnt, u32DSCnt, u32ClkDiv; + uint32_t u32Tmp, u32Tmp2, u32Tmp3, u32Min, u32MinClkDiv, u32MinDSCnt; + + uint32_t u32Div; + + /* Get PCLK frequency */ + if ((psUUART == UUART0) || (psUUART == UUART2)) + { + u32PCLKFreq = CLK_GetPCLK0Freq(); + } + else + { + u32PCLKFreq = CLK_GetPCLK1Freq(); + } + + /* Find out divide value */ + u32Div = u32PCLKFreq / u32Baudrate; + + /* Avoid decimal of divider being discarded and find divider that are closest to the baud rate */ + u32Tmp = (u32PCLKFreq / u32Div) - u32Baudrate; + u32Tmp2 = u32Baudrate - (u32PCLKFreq / (u32Div + 1)); + + if (u32Tmp >= u32Tmp2) + { + u32Div = u32Div + 1; + } + + /* Divide value = CLKDIV(MAX. = 0x400) * DSCNT(MAX. = 0x10) * PDSCNT */ + u32Tmp = 0x400 * 0x10; + + /* Find out PDSCNT value */ + for (u32PDSCnt = 1; u32PDSCnt <= 0x04; u32PDSCnt++) + { + if (u32Div <= (u32Tmp * u32PDSCnt)) break; + } + + /* PDSCNT MAX.= 0x4 */ + if (u32PDSCnt > 0x4) u32PDSCnt = 0x4; + + /* Avoid decimal of PDSCNT being discarded */ + u32Tmp = u32Div / u32PDSCnt; + u32Tmp2 = (u32Div / u32Tmp) - u32PDSCnt; + u32Tmp3 = u32PDSCnt - (u32Div / (u32Tmp + 1)); + + if (u32Tmp2 >= u32Tmp3) + { + u32Div = u32Tmp + 1; + } + else u32Div = u32Tmp; + + /* Find best solution of DSCNT and CLKDIV*/ + u32Min = (uint32_t) - 1; + u32MinDSCnt = 0; + u32MinClkDiv = 0; + + u32Tmp = 0; + + for (u32DSCnt = 6; u32DSCnt <= 0x10; u32DSCnt++) /* DSCNT could be 0x5~0xF */ + { + + u32ClkDiv = u32Div / u32DSCnt; + + if (u32ClkDiv >= 0x400) + { + u32ClkDiv = 0x400; + u32Tmp = u32Tmp2 = abs((int)(u32PCLKFreq / (u32ClkDiv * u32DSCnt * u32PDSCnt)) - (int)u32Baudrate); + } + else /* Avoid decimal of PDSCNT being discarded */ + { + u32Tmp = abs((int)(u32PCLKFreq / (u32ClkDiv * u32DSCnt * u32PDSCnt)) - (int)u32Baudrate); + u32Tmp2 = abs((int)(u32PCLKFreq / ((u32ClkDiv + 1) * u32DSCnt * u32PDSCnt)) - (int)u32Baudrate); + } + + if (u32Tmp > u32Tmp2) + { + u32ClkDiv = u32ClkDiv + 1; + } + else u32Tmp2 = u32Tmp; + + /* Record the closest solution */ + if (u32Tmp2 < u32Min) + { + u32Min = u32Tmp2; + u32MinDSCnt = u32DSCnt; + u32MinClkDiv = u32ClkDiv; + + /* Break when get good results */ + if (u32Min == 0) + { + break; + } + } + } + + /* Enable USCI_UART protocol */ + psUUART->CTL &= ~UUART_CTL_FUNMODE_Msk; + psUUART->CTL = 2 << UUART_CTL_FUNMODE_Pos; + + /* Set USCI_UART line configuration */ + psUUART->LINECTL = UUART_WORD_LEN_8 | UUART_LINECTL_LSB_Msk; + psUUART->DATIN0 = (2 << UUART_DATIN0_EDGEDET_Pos); /* Set falling edge detection */ + + /* Set USCI_UART baud rate */ + psUUART->BRGEN = ((u32MinClkDiv - 1) << UUART_BRGEN_CLKDIV_Pos) | + ((u32MinDSCnt - 1) << UUART_BRGEN_DSCNT_Pos) | + ((u32PDSCnt - 1) << UUART_BRGEN_PDSCNT_Pos); + + psUUART->PROTCTL |= UUART_PROTCTL_PROTEN_Msk; + + return (u32PCLKFreq / u32PDSCnt / u32MinDSCnt / u32MinClkDiv); +} + + +/** + * @brief Read USCI_UART data + * + * @param[in] psUUART The pointer of the specified USCI_UART module. + * @param[in] pu8RxBuf The buffer to receive the data of receive buffer. + * @param[in] u32ReadBytes The read bytes number of data. + * + * @return Receive byte count + * + * @details The function is used to read Rx data from RX buffer and the data will be stored in pu8RxBuf. + */ +uint32_t UUART_Read(UUART_T *psUUART, uint8_t pu8RxBuf[], uint32_t u32ReadBytes) +{ + uint32_t u32Count, u32Delayno; + + for (u32Count = 0ul; u32Count < u32ReadBytes; u32Count++) + { + u32Delayno = 0ul; + + while (psUUART->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk) /* Check RX empty => failed */ + { + u32Delayno++; + + if (u32Delayno >= 0x40000000ul) + { + break; + } + } + + if (u32Delayno >= 0x40000000ul) + { + break; + } + + pu8RxBuf[u32Count] = (uint8_t)psUUART->RXDAT; /* Get Data from USCI RX */ + } + + return u32Count; + +} + + +/** + * @brief Set USCI_UART line configuration + * + * @param[in] psUUART The pointer of the specified USCI_UART module. + * @param[in] u32Baudrate The register value of baud rate of USCI_UART module. + * If u32Baudrate = 0, USCI_UART baud rate will not change. + * @param[in] u32DataWidth The data length of USCI_UART module. + * - \ref UUART_WORD_LEN_6 + * - \ref UUART_WORD_LEN_7 + * - \ref UUART_WORD_LEN_8 + * - \ref UUART_WORD_LEN_9 + * @param[in] u32Parity The parity setting (none/odd/even) of USCI_UART module. + * - \ref UUART_PARITY_NONE + * - \ref UUART_PARITY_ODD + * - \ref UUART_PARITY_EVEN + * @param[in] u32StopBits The stop bit length (1/2 bit) of USCI_UART module. + * - \ref UUART_STOP_BIT_1 + * - \ref UUART_STOP_BIT_2 + * + * @return Real baud rate of USCI_UART module. + * + * @details This function use to config USCI_UART line setting. + */ +uint32_t UUART_SetLine_Config(UUART_T *psUUART, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits) +{ + uint32_t u32PCLKFreq, u32PDSCnt, u32DSCnt, u32ClkDiv; + uint32_t u32Tmp, u32Tmp2, u32Tmp3, u32Min, u32MinClkDiv, u32MinDSCnt; + + uint32_t u32Div; + + /* Get PCLK frequency */ + if ((psUUART == UUART0) || (psUUART == UUART2)) + { + u32PCLKFreq = CLK_GetPCLK0Freq(); + } + else + { + u32PCLKFreq = CLK_GetPCLK1Freq(); + } + + if (u32Baudrate != 0) + { + u32Div = u32PCLKFreq / u32Baudrate; + u32Tmp = (u32PCLKFreq / u32Div) - u32Baudrate; + u32Tmp2 = u32Baudrate - (u32PCLKFreq / (u32Div + 1)); + + if (u32Tmp >= u32Tmp2) + { + u32Div = u32Div + 1; + } + + u32Tmp = 0x400 * 0x10; + + for (u32PDSCnt = 1; u32PDSCnt <= 0x04; u32PDSCnt++) + { + if (u32Div <= (u32Tmp * u32PDSCnt)) break; + } + + if (u32PDSCnt > 0x4) u32PDSCnt = 0x4; + + u32Tmp = u32Div / u32PDSCnt; + u32Tmp2 = (u32Div / u32Tmp) - u32PDSCnt; + u32Tmp3 = u32PDSCnt - (u32Div / (u32Tmp + 1)); + + if (u32Tmp2 >= u32Tmp3) + { + u32Div = u32Tmp + 1; + } + else u32Div = u32Tmp; + + /* Find best solution */ + u32Min = (uint32_t) - 1; + u32MinDSCnt = 0; + u32MinClkDiv = 0; + + u32Tmp = 0; + + for (u32DSCnt = 6; u32DSCnt <= 0x10; u32DSCnt++) /* DSCNT could be 0x5~0xF */ + { + + u32ClkDiv = u32Div / u32DSCnt; + + if (u32ClkDiv >= 0x400) + { + u32ClkDiv = 0x400; + u32Tmp = u32Tmp2 = abs((int)(u32PCLKFreq / (u32ClkDiv * u32DSCnt * u32PDSCnt)) - (int)u32Baudrate); + } + else + { + u32Tmp = abs((int)(u32PCLKFreq / (u32ClkDiv * u32DSCnt * u32PDSCnt)) - (int)u32Baudrate); + u32Tmp2 = abs((int)(u32PCLKFreq / ((u32ClkDiv + 1) * u32DSCnt * u32PDSCnt)) - (int)u32Baudrate); + } + + if (u32Tmp > u32Tmp2) + { + u32ClkDiv = u32ClkDiv + 1; + } + else u32Tmp2 = u32Tmp; + + if (u32Tmp2 < u32Min) + { + u32Min = u32Tmp2; + u32MinDSCnt = u32DSCnt; + u32MinClkDiv = u32ClkDiv; + + /* Break when get good results */ + if (u32Min == 0) + { + break; + } + } + } + + /* Set USCI_UART baud rate */ + psUUART->BRGEN = ((u32MinClkDiv - 1) << UUART_BRGEN_CLKDIV_Pos) | + ((u32MinDSCnt - 1) << UUART_BRGEN_DSCNT_Pos) | + ((u32PDSCnt - 1) << UUART_BRGEN_PDSCNT_Pos); + } + else + { + u32PDSCnt = ((psUUART->BRGEN & UUART_BRGEN_PDSCNT_Msk) >> UUART_BRGEN_PDSCNT_Pos) + 1; + u32MinDSCnt = ((psUUART->BRGEN & UUART_BRGEN_DSCNT_Msk) >> UUART_BRGEN_DSCNT_Pos) + 1; + u32MinClkDiv = ((psUUART->BRGEN & UUART_BRGEN_CLKDIV_Msk) >> UUART_BRGEN_CLKDIV_Pos) + 1; + } + + /* Set USCI_UART line configuration */ + psUUART->LINECTL = (psUUART->LINECTL & ~UUART_LINECTL_DWIDTH_Msk) | u32DataWidth; + psUUART->PROTCTL = (psUUART->PROTCTL & ~(UUART_PROTCTL_STICKEN_Msk | UUART_PROTCTL_EVENPARITY_Msk | + UUART_PROTCTL_PARITYEN_Msk)) | u32Parity; + psUUART->PROTCTL = (psUUART->PROTCTL & ~UUART_PROTCTL_STOPB_Msk) | u32StopBits; + + return (u32PCLKFreq / u32PDSCnt / u32MinDSCnt / u32MinClkDiv); +} + + +/** + * @brief Write USCI_UART data + * + * @param[in] psUUART The pointer of the specified USCI_UART module. + * @param[in] pu8TxBuf The buffer to send the data to USCI transmission buffer. + * @param[out] u32WriteBytes The byte number of data. + * + * @return Transfer byte count + * + * @details The function is to write data into TX buffer to transmit data by USCI_UART. + */ +uint32_t UUART_Write(UUART_T *psUUART, uint8_t pu8TxBuf[], uint32_t u32WriteBytes) +{ + uint32_t u32Count, u32Delayno; + + for (u32Count = 0ul; u32Count != u32WriteBytes; u32Count++) + { + u32Delayno = 0ul; + + while ((psUUART->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk) == 0ul) /* Wait Tx empty */ + { + u32Delayno++; + + if (u32Delayno >= 0x40000000ul) + { + break; + } + } + + if (u32Delayno >= 0x40000000ul) + { + break; + } + + psUUART->TXDAT = (uint8_t)pu8TxBuf[u32Count]; /* Send USCI_UART Data to buffer */ + } + + return u32Count; + +} + + +/** + * @brief Enable USCI_UART Wake-up Function + * + * @param[in] psUUART The pointer of the specified USCI_UART module. + * @param[in] u32WakeupMode The wakeup mode of USCI_UART module. + * - \ref UUART_PROTCTL_DATWKEN_Msk : Data wake-up Mode + * - \ref UUART_PROTCTL_CTSWKEN_Msk : nCTS wake-up Mode + * + * @return None + * + * @details The function is used to enable Wake-up function of USCI_UART. + */ +void UUART_EnableWakeup(UUART_T *psUUART, uint32_t u32WakeupMode) +{ + psUUART->PROTCTL |= u32WakeupMode; + psUUART->WKCTL |= UUART_WKCTL_WKEN_Msk; +} + + +/** + * @brief Disable USCI_UART Wake-up Function + * + * @param[in] psUUART The pointer of the specified USCI_UART module. + * + * @return None + * + * @details The function is used to disable Wake-up function of USCI_UART. + */ +void UUART_DisableWakeup(UUART_T *psUUART) +{ + psUUART->PROTCTL &= ~(UUART_PROTCTL_DATWKEN_Msk | UUART_PROTCTL_CTSWKEN_Msk); + psUUART->WKCTL &= ~UUART_WKCTL_WKEN_Msk; +} + +/** + * @brief Enable USCI_UART auto flow control + * + * @param[in] psUUART The pointer of the specified USCI_UART module. + * + * @return None + * + * @details The function is used to enable USCI_UART auto flow control. + */ +void UUART_EnableFlowCtrl(UUART_T *psUUART) +{ + /* Set RTS signal is low level active */ + psUUART->LINECTL &= ~UUART_LINECTL_CTLOINV_Msk; + + /* Set CTS signal is low level active */ + psUUART->CTLIN0 &= ~UUART_CTLIN0_ININV_Msk; + + /* Enable CTS and RTS auto flow control function */ + psUUART->PROTCTL |= UUART_PROTCTL_RTSAUTOEN_Msk | UUART_PROTCTL_CTSAUTOEN_Msk; +} + +/** + * @brief Disable USCI_UART auto flow control + * + * @param[in] psUUART The pointer of the specified USCI_UART module. + * + * @return None + * + * @details The function is used to disable USCI_UART auto flow control. + */ +void UUART_DisableFlowCtrl(UUART_T *psUUART) +{ + /* Disable CTS and RTS auto flow control function */ + psUUART->PROTCTL &= ~(UUART_PROTCTL_RTSAUTOEN_Msk | UUART_PROTCTL_CTSAUTOEN_Msk); +} + + + + +/*@}*/ /* end of group USCI_UART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USCI_UART_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ + diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_wdt.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_wdt.c new file mode 100644 index 00000000000..b7c29b38e44 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_wdt.c @@ -0,0 +1,69 @@ +/**************************************************************************//** + * @file wdt.c + * @version V0.10 + * @brief M251 series WDT driver source file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup WDT_Driver WDT Driver + @{ +*/ + +/** @addtogroup WDT_EXPORTED_FUNCTIONS WDT Exported Functions + @{ +*/ + +/** + * @brief Initialize WDT and start counting + * + * @param[in] u32TimeoutInterval Time-out interval period of WDT module. Valid values are: + * - \ref WDT_TIMEOUT_2POW4 + * - \ref WDT_TIMEOUT_2POW6 + * - \ref WDT_TIMEOUT_2POW8 + * - \ref WDT_TIMEOUT_2POW10 + * - \ref WDT_TIMEOUT_2POW12 + * - \ref WDT_TIMEOUT_2POW14 + * - \ref WDT_TIMEOUT_2POW16 + * - \ref WDT_TIMEOUT_2POW18 + * * \ref WDT_TIMEOUT_2POW20 + * @param[in] u32ResetDelay Configure WDT time-out reset delay period. Valid values are: + * - \ref WDT_RESET_DELAY_1026CLK + * - \ref WDT_RESET_DELAY_130CLK + * - \ref WDT_RESET_DELAY_18CLK + * - \ref WDT_RESET_DELAY_3CLK + * @param[in] u32EnableReset Enable WDT time-out reset system function. Valid values are TRUE and FALSE. + * @param[in] u32EnableWakeup Enable WDT time-out wake-up system function. Valid values are TRUE and FALSE. + * + * @return None + * + * @details This function makes WDT module start counting with different time-out interval, reset delay period and choose to \n + * enable or disable WDT time-out reset system or wake-up system. + * @note Please make sure that Register Write-Protection Function has been disabled before using this function. + */ +void WDT_Open(uint32_t u32TimeoutInterval, + uint32_t u32ResetDelay, + uint32_t u32EnableReset, + uint32_t u32EnableWakeup) +{ + WDT->ALTCTL = u32ResetDelay; + + WDT->CTL = u32TimeoutInterval | WDT_CTL_WDTEN_Msk | + (u32EnableReset << WDT_CTL_RSTEN_Pos) | + (u32EnableWakeup << WDT_CTL_WKEN_Pos); + return; +} + +/*@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group WDT_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_wwdt.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_wwdt.c new file mode 100644 index 00000000000..8d036b8933e --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_wwdt.c @@ -0,0 +1,68 @@ +/**************************************************************************//** + * @file wwdt.c + * @version V0.10 + * @brief M251 series WWDT driver source file + * + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup WWDT_Driver WWDT Driver + @{ +*/ + +/** @addtogroup WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions + @{ +*/ + +/** + * @brief Open WWDT function to start counting + * + * @param[in] u32PreScale Prescale period for the WWDT counter period. Valid values are: + * - \ref WWDT_PRESCALER_1 + * - \ref WWDT_PRESCALER_2 + * - \ref WWDT_PRESCALER_4 + * - \ref WWDT_PRESCALER_8 + * - \ref WWDT_PRESCALER_16 + * - \ref WWDT_PRESCALER_32 + * - \ref WWDT_PRESCALER_64 + * - \ref WWDT_PRESCALER_128 + * - \ref WWDT_PRESCALER_192 + * - \ref WWDT_PRESCALER_256 + * - \ref WWDT_PRESCALER_384 + * - \ref WWDT_PRESCALER_512 + * - \ref WWDT_PRESCALER_768 + * - \ref WWDT_PRESCALER_1024 + * - \ref WWDT_PRESCALER_1536 + * - \ref WWDT_PRESCALER_2048 + * @param[in] u32CmpValue Setting the window compared value. Valid values are between 0x0 to 0x3F. + * @param[in] u32EnableInt Enable WWDT interrupt function. Valid values are TRUE and FALSE. + * + * @return None + * + * @details This function makes WWDT module start counting with different counter period and compared window value. + * @note Application can call this function only once after boot up. + */ +void WWDT_Open(uint32_t u32PreScale, + uint32_t u32CmpValue, + uint32_t u32EnableInt) +{ + WWDT->CTL = u32PreScale | + (u32CmpValue << WWDT_CTL_CMPDAT_Pos) | + ((u32EnableInt == TRUE) ? WWDT_CTL_INTEN_Msk : 0U) | + WWDT_CTL_WWDTEN_Msk; + return; +} + +/*@}*/ /* end of group WWDT_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group WWDT_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/TOOLCHAIN_ARMC6/M251.sct b/targets/TARGET_NUVOTON/TARGET_M251/device/TOOLCHAIN_ARMC6/M251.sct new file mode 100644 index 00000000000..e6a67ed0b0d --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/TOOLCHAIN_ARMC6/M251.sct @@ -0,0 +1,75 @@ +#! armclang -E + +/* + * Copyright (c) 2019, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if !defined(MBED_APP_START) +#define MBED_APP_START 0x00000000 +#endif + +#if !defined(MBED_APP_SIZE) +#define MBED_APP_SIZE 0x00040000 +#endif + +#if !defined(MBED_RAM_APP_START) +#define MBED_RAM_APP_START 0x20000000 +#endif + +#if !defined(MBED_RAM_APP_SIZE) +#define MBED_RAM_APP_SIZE 0x8000 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) +#define MBED_BOOT_STACK_SIZE 0x400 +#endif + +LR_IROM1 MBED_APP_START +{ + /* load address = execution address */ + ER_IROM1 +0 + { + *(RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ARM_LIB_STACK MBED_RAM_APP_START EMPTY MBED_BOOT_STACK_SIZE + { + } + + /* Reserve for vectors + * + * Vector table base address is required to be 128-byte aligned at a minimum. + * A PE might impose further restrictions on it. */ + ER_IRAMVEC AlignExpr(+0, 128) EMPTY (4*(16 + 64)) + { + } + + /* 16 byte-aligned */ + RW_IRAM1 AlignExpr(+0, 16) + { + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_APP_START + MBED_RAM_APP_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) + { + } +} + +ScatterAssert(LoadLimit(LR_IROM1) <= (MBED_APP_START + MBED_APP_SIZE)) +ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= (MBED_RAM_APP_START + MBED_RAM_APP_SIZE)) diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/TOOLCHAIN_GCC_ARM/M251.ld b/targets/TARGET_NUVOTON/TARGET_M251/device/TOOLCHAIN_GCC_ARM/M251.ld new file mode 100644 index 00000000000..3085d9b5b38 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/TOOLCHAIN_GCC_ARM/M251.ld @@ -0,0 +1,222 @@ +/* + * Copyright (c) 2019, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* Nuvoton M251 GCC linker script file */ + +#if !defined(MBED_APP_START) +#define MBED_APP_START 0x00000000 +#endif + +#if !defined(MBED_APP_SIZE) +#define MBED_APP_SIZE 0x00040000 +#endif + +#if !defined(MBED_RAM_APP_START) +#define MBED_RAM_APP_START 0x20000000 +#endif + +#if !defined(MBED_RAM_APP_SIZE) +#define MBED_RAM_APP_SIZE 0x8000 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) +#define MBED_BOOT_STACK_SIZE 0x400 +#endif + +StackSize = MBED_BOOT_STACK_SIZE; + +MEMORY +{ + VECTORS (rx) : ORIGIN = MBED_APP_START, LENGTH = 0x00000400 + FLASH (rx) : ORIGIN = MBED_APP_START + 0x400, LENGTH = MBED_APP_SIZE - 0x400 + RAM_INTERN (rwx) : ORIGIN = MBED_RAM_APP_START, LENGTH = MBED_RAM_APP_SIZE +} + +/* Must match cmsis_nvic.h */ +__vector_size = 4 * (16 + 64); + + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .isr_vector : + { + __vector_table = .; + KEEP(*(.vector_table)) + . = ALIGN(8); + } > VECTORS + + .copy.table : ALIGN(4) + { + __copy_table_start__ = .; + LONG (LOADADDR(.data)) + LONG (ADDR(.data)) + LONG (SIZEOF(.data)) + __copy_table_end__ = .; + } > FLASH + + .zero.table : ALIGN(4) + { + __zero_table_start__ = .; + LONG (ADDR(.bss)) + LONG (SIZEOF(.bss)) + __zero_table_end__ = .; + } > FLASH + + .text : + { + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .stack (NOLOAD) : + { + . = ALIGN(8); + __StackLimit = .; + . += StackSize; + __StackTop = .; + } > RAM_INTERN + + PROVIDE(__stack = __StackTop); + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } > FLASH + + /* Relocate vector table in SRAM */ + .isr_vector.reloc (NOLOAD) : + { + . = ALIGN(1 << LOG2CEIL(__vector_size)); + PROVIDE(__start_vector_table__ = .); + . += __vector_size; + PROVIDE(__end_vector_table__ = .); + } > RAM_INTERN + + .data : + { + PROVIDE( __etext = LOADADDR(.data) ); + + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(8); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(8); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(8); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + /* All data end */ + . = ALIGN(32); + __data_end__ = .; + + } >RAM_INTERN AT>FLASH + + .bss (NOLOAD): + { + __bss_start__ = .; + *(.bss*) + *(COMMON) + __bss_end__ = .; + } > RAM_INTERN + + .heap (NOLOAD) : + { + . = ALIGN(8); + __end__ = .; + end = __end__; + *(.heap*); + . += (ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN) - .); + __HeapLimit = .; + } > RAM_INTERN + Image$$ARM_LIB_HEAP$$ZI$$Base = ADDR(.heap); + Image$$ARM_LIB_HEAP$$ZI$$Limit = ADDR(.heap) + SIZEOF(.heap); + + PROVIDE(__heap_size = SIZEOF(.heap)); + PROVIDE(__mbed_sbrk_start = ADDR(.heap)); + PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap)); +} diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/TOOLCHAIN_IAR/M251.icf b/targets/TARGET_NUVOTON/TARGET_M251/device/TOOLCHAIN_IAR/M251.icf new file mode 100644 index 00000000000..106e00493c3 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/TOOLCHAIN_IAR/M251.icf @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2019, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ + +if (! isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = 0x00000000; +} + +if (! isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = 0x00040000; +} + +if (! isdefinedsymbol(MBED_RAM_APP_START)) { + define symbol MBED_RAM_APP_START = 0x20000000; +} + + +if (! isdefinedsymbol(MBED_RAM_APP_SIZE)) { + define symbol MBED_RAM_APP_SIZE = 0x8000; +} + +if (! isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x400; +} + +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = MBED_APP_START; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; +define symbol __ICFEDIT_region_IRAM_start__ = MBED_RAM_APP_START; +define symbol __ICFEDIT_region_IRAM_end__ = MBED_RAM_APP_START + MBED_RAM_APP_SIZE - 1; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; +define symbol __ICFEDIT_size_heap__ = 0x4000; + + +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; +/* NOTE: Vector table base address is required to be 128-byte aligned at a minimum. + * A PE might impose further restrictions on it. */ +define block IRAMVEC with alignment = 1024, size = 4 * (16 + 64) { }; + + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem: __ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; + +place at start of IRAM_region { block CSTACK }; +place in IRAM_region { block IRAMVEC }; +place in IRAM_region { readwrite }; +place in IRAM_region { block HEAP }; diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/cmsis.h b/targets/TARGET_NUVOTON/TARGET_M251/device/cmsis.h new file mode 100644 index 00000000000..22fcd8cbe0f --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/cmsis.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2019, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "M251.h" +#include "cmsis_nvic.h" + +// Support linker-generated symbol as start of relocated vector table. +#if defined(__ARMCC_VERSION) +extern uint32_t Image$$ER_IRAMVEC$$ZI$$Base; +#elif defined(__ICCARM__) + +#elif defined(__GNUC__) +extern uint32_t __start_vector_table__; +#endif + + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/cmsis_nvic.h b/targets/TARGET_NUVOTON/TARGET_M251/device/cmsis_nvic.h new file mode 100644 index 00000000000..5707564e162 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/cmsis_nvic.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2019, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#include "cmsis.h" + +#define NVIC_USER_IRQ_OFFSET 16 +#define NVIC_USER_IRQ_NUMBER 64 +#define NVIC_NUM_VECTORS (NVIC_USER_IRQ_OFFSET + NVIC_USER_IRQ_NUMBER) + +#if defined(__ARMCC_VERSION) +# define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) &Image$$ER_IRAMVEC$$ZI$$Base) +#elif defined(__ICCARM__) +# pragma section = "IRAMVEC" +# define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) __section_begin("IRAMVEC")) +#elif defined(__GNUC__) +# define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) &__start_vector_table__) +#endif + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/startup_M251.c b/targets/TARGET_NUVOTON/TARGET_M251/device/startup_M251.c new file mode 100644 index 00000000000..a4e0c39ab0d --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/startup_M251.c @@ -0,0 +1,342 @@ +/* + * Copyright (c) 2019, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "M251.h" + +/* Suppress warning messages */ +#if defined(__CC_ARM) +// Suppress warning message: extended constant initializer used +#pragma diag_suppress 1296 +#elif defined(__ICCARM__) +#elif defined(__GNUC__) +#endif + +/* Macro Definitions */ +#if defined(__CC_ARM) +#define WEAK __attribute__ ((weak)) +#define ALIAS(f) __attribute__ ((weak, alias(#f))) + +#define WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) \ +void FUN(void) __attribute__ ((weak, alias(#FUN_ALIAS))); + +#elif defined(__ICCARM__) +//#define STRINGIFY(x) #x +//#define _STRINGIFY(x) STRINGIFY(x) +#define WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) \ +void FUN(void); \ +_Pragma(_STRINGIFY(_WEAK_ALIAS_FUNC(FUN, FUN_ALIAS))) +#define _WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) weak __WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) +#define __WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) FUN##=##FUN_ALIAS + +#elif defined(__GNUC__) +#define WEAK __attribute__ ((weak)) +#define ALIAS(f) __attribute__ ((weak, alias(#f))) + +#define WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) \ +void FUN(void) __attribute__ ((weak, alias(#FUN_ALIAS))); + +#endif + + +/* Initialize segments */ +#if defined(__ARMCC_VERSION) +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit; +extern void __main(void); +#elif defined(__ICCARM__) +void __iar_program_start(void); +#elif defined(__GNUC__) +extern uint32_t __StackTop; +extern uint32_t __copy_table_start__; +extern uint32_t __copy_table_end__; +extern uint32_t __zero_table_start__; +extern uint32_t __zero_table_end__; + +#if defined(TOOLCHAIN_GCC_ARM) +extern void _start(void); +#else +#error("For GCC toolchain, only support GNU ARM Embedded") +#endif +#endif + +/* Default empty handler */ +void Default_Handler(void); + +/* Reset handler */ +void Reset_Handler(void); + +/* Cortex-M23 core handlers */ +WEAK_ALIAS_FUNC(NMI_Handler, Default_Handler) // -14: Non Maskable Interrupt +WEAK_ALIAS_FUNC(HardFault_Handler, Default_Handler) // -13: Cortex-M23 Hard Fault Interrupt +WEAK_ALIAS_FUNC(SVC_Handler, Default_Handler) // -5: Cortex-M23 SV Call Interrupt + +WEAK_ALIAS_FUNC(PendSV_Handler, Default_Handler) // -2: Cortex-M23 Pend SV Interrupt +WEAK_ALIAS_FUNC(SysTick_Handler, Default_Handler) // -1: Cortex-M23 System Tick Interrupt + +/* Peripherals handlers */ +WEAK_ALIAS_FUNC(BOD_IRQHandler, Default_Handler) // 0: Brown-Out Low Voltage Detected Interrupt +WEAK_ALIAS_FUNC(IRCTRIM_IRQHandler, Default_Handler) // 1: Watch Dog Timer Interrupt +WEAK_ALIAS_FUNC(PWRWU_IRQHandler, Default_Handler) // 2: EINT0, EINT2 and EINT4 Interrupt + // 3: Reserved +WEAK_ALIAS_FUNC(CLKFAIL_IRQHandler, Default_Handler) // 4: Clock fail dector Interrupt + // 5: Reserved +WEAK_ALIAS_FUNC(RTC_IRQHandler, Default_Handler) // 6: Real Time Clock Interrupt +WEAK_ALIAS_FUNC(TAMPER_IRQHandler, Default_Handler) // 7: Tamper detection Interrupt +WEAK_ALIAS_FUNC(WDT_IRQHandler, Default_Handler) // 8: Watch Dog Timer Interrupt +WEAK_ALIAS_FUNC(WWDT_IRQHandler, Default_Handler) // 9: Window Watch Dog Timer Interrupt +WEAK_ALIAS_FUNC(EINT0_IRQHandler, Default_Handler) // 10: External Input 0 Interrupt +WEAK_ALIAS_FUNC(EINT1_IRQHandler, Default_Handler) // 11: External Input 1 Interrupt +WEAK_ALIAS_FUNC(EINT2_IRQHandler, Default_Handler) // 12: External Input 2 Interrupt +WEAK_ALIAS_FUNC(EINT3_IRQHandler, Default_Handler) // 13: External Input 3 Interrupt +WEAK_ALIAS_FUNC(EINT4_IRQHandler, Default_Handler) // 14: External Input 4 Interrupt +WEAK_ALIAS_FUNC(EINT5_IRQHandler, Default_Handler) // 15: External Input 5 Interrupt +WEAK_ALIAS_FUNC(GPA_IRQHandler, Default_Handler) // 16: GPIO PORT A Interrupt +WEAK_ALIAS_FUNC(GPB_IRQHandler, Default_Handler) // 17: GPIO PORT B Interrupt +WEAK_ALIAS_FUNC(GPC_IRQHandler, Default_Handler) // 18: GPIO PORT C Interrupt +WEAK_ALIAS_FUNC(GPD_IRQHandler, Default_Handler) // 19: GPIO PORT D Interrupt +WEAK_ALIAS_FUNC(GPE_IRQHandler, Default_Handler) // 20: GPIO PORT E Interrupt +WEAK_ALIAS_FUNC(GPF_IRQHandler, Default_Handler) // 21: GPIO PORT F Interrupt +WEAK_ALIAS_FUNC(QSPI0_IRQHandler, Default_Handler) // 22: QSPI0 Interrupt +WEAK_ALIAS_FUNC(SPI0_IRQHandler, Default_Handler) // 23: SPI0 Interrupt +WEAK_ALIAS_FUNC(BRAKE0_IRQHandler, Default_Handler) // 24: PWM Brake0 Interrupt +WEAK_ALIAS_FUNC(PWM0_P0_IRQHandler, Default_Handler) // 25: PWM0 P0 Interrupt +WEAK_ALIAS_FUNC(PWM0_P1_IRQHandler, Default_Handler) // 26: PWM0 P1 Interrupt +WEAK_ALIAS_FUNC(PWM0_P2_IRQHandler, Default_Handler) // 27: PWM0 P2 Interrupt +WEAK_ALIAS_FUNC(BRAKE1_IRQHandler, Default_Handler) // 28: PWM Brake1 Interrupt +WEAK_ALIAS_FUNC(PWM1_P0_IRQHandler, Default_Handler) // 29: PWM1 P0 Interrupt +WEAK_ALIAS_FUNC(PWM1_P1_IRQHandler, Default_Handler) // 30: PWM1 P1 Interrupt +WEAK_ALIAS_FUNC(PWM1_P2_IRQHandler, Default_Handler) // 31: PWM1 P2 Interrupt +WEAK_ALIAS_FUNC(TMR0_IRQHandler, Default_Handler) // 32: TIMER0 Interrupt +WEAK_ALIAS_FUNC(TMR1_IRQHandler, Default_Handler) // 33: TIMER1 Interrupt +WEAK_ALIAS_FUNC(TMR2_IRQHandler, Default_Handler) // 34: TIMER2 Interrupt +WEAK_ALIAS_FUNC(TMR3_IRQHandler, Default_Handler) // 35: TIMER3 Interrupt +WEAK_ALIAS_FUNC(UART0_IRQHandler, Default_Handler) // 36: UART0 Interrupt +WEAK_ALIAS_FUNC(UART1_IRQHandler, Default_Handler) // 37: UART1 Interrupt +WEAK_ALIAS_FUNC(I2C0_IRQHandler, Default_Handler) // 38: I2C0 Interrupt +WEAK_ALIAS_FUNC(I2C1_IRQHandler, Default_Handler) // 39: I2C1 Interrupt +WEAK_ALIAS_FUNC(PDMA_IRQHandler, Default_Handler) // 40: Peripheral DMA Interrupt +WEAK_ALIAS_FUNC(DAC_IRQHandler, Default_Handler) // 41: DAC Interrupt +WEAK_ALIAS_FUNC(EADC_INT0_IRQHandler, Default_Handler) // 42: Enhance ADC Interrupt 0 +WEAK_ALIAS_FUNC(EADC_INT1_IRQHandler, Default_Handler) // 43: Enhance ADC Interrupt 1 +WEAK_ALIAS_FUNC(ACMP01_IRQHandler, Default_Handler) // 44: ACMP0 Interrupt +WEAK_ALIAS_FUNC(BPWM0_IRQHandler, Default_Handler) // 45: BPWM0 Interrupt +WEAK_ALIAS_FUNC(EADC_INT2_IRQHandler, Default_Handler) // 46: Enhance EADC Interrupt 2 +WEAK_ALIAS_FUNC(EADC_INT3_IRQHandler, Default_Handler) // 47: Enhance EADC Interrupt 3 +WEAK_ALIAS_FUNC(UART2_IRQHandler, Default_Handler) // 48: UART2 Interrupt + // 49: Reserved +WEAK_ALIAS_FUNC(USCI0_IRQHandler, Default_Handler) // 50: USCI0 Interrupt + // 51: Reserved +WEAK_ALIAS_FUNC(USCI1_IRQHandler, Default_Handler) // 52: USCI1 Interrupt +WEAK_ALIAS_FUNC(USBD_IRQHandler, Default_Handler) // 53: USB Device Interrupt +WEAK_ALIAS_FUNC(BPWM1_IRQHandler, Default_Handler) // 54: BPWM1 Interrupt +WEAK_ALIAS_FUNC(PSIO_IRQHandler, Default_Handler) // 55: PSIO Interrupt + // 56: Reserved +WEAK_ALIAS_FUNC(CRPT_IRQHandler, Default_Handler) // 57: Cryption Interrupt +WEAK_ALIAS_FUNC(SC0_IRQHandler, Default_Handler) // 58: Smart Card0 Interrupt + // 59: Reserved +WEAK_ALIAS_FUNC(USCI2_IRQHandler, Default_Handler) // 60: USCI2 Interrupt + // 61: Reserved +WEAK_ALIAS_FUNC(OPA_IRQHandler, Default_Handler) // 62: OPA Interrupt + // 63: Reserved + +/* Vector table */ +#if defined(__ARMCC_VERSION) +__attribute__ ((section("RESET"))) +const uint32_t __vector_handlers[] = { +#elif defined(__ICCARM__) +extern uint32_t CSTACK$$Limit; +const uint32_t __vector_table[] @ ".intvec" = { +#elif defined(__GNUC__) +__attribute__ ((section(".vector_table"))) +const uint32_t __vector_handlers[] = { +#endif + + /* Configure Initial Stack Pointer, using linker-generated symbols */ +#if defined(__ARMCC_VERSION) + (uint32_t) &Image$$ARM_LIB_STACK$$ZI$$Limit, +#elif defined(__ICCARM__) + //(uint32_t) __sfe("CSTACK"), + (uint32_t) &CSTACK$$Limit, +#elif defined(__GNUC__) + (uint32_t) &__StackTop, +#endif + + (uint32_t) Reset_Handler, // Reset Handler + (uint32_t) NMI_Handler, // NMI Handler + (uint32_t) HardFault_Handler, // Hard Fault Handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + (uint32_t) SVC_Handler, // SVCall Handler + 0, // Reserved + 0, // Reserved + (uint32_t) PendSV_Handler, // PendSV Handler + (uint32_t) SysTick_Handler, // SysTick Handler + + /* External Interrupts */ + (uint32_t) BOD_IRQHandler, // 0: Brown-Out Low Voltage Detected Interrupt + (uint32_t) IRCTRIM_IRQHandler, // 1: Watch Dog Timer Interrupt + (uint32_t) PWRWU_IRQHandler, // 2: EINT0, EINT2 and EINT4 Interrupt + (uint32_t) Default_Handler, // 3: Reserved + (uint32_t) CLKFAIL_IRQHandler, // 4: Clock fail dector Interrupt + (uint32_t) Default_Handler, // 5: Reserved + (uint32_t) RTC_IRQHandler, // 6: Real Time Clock Interrupt + (uint32_t) TAMPER_IRQHandler, // 7: Tamper detection Interrupt + (uint32_t) WDT_IRQHandler, // 8: Watch Dog Timer Interrupt + (uint32_t) WWDT_IRQHandler, // 9: Window Watch Dog Timer Interrupt + (uint32_t) EINT0_IRQHandler, // 10: External Input 0 Interrupt + (uint32_t) EINT1_IRQHandler, // 11: External Input 1 Interrupt + (uint32_t) EINT2_IRQHandler, // 12: External Input 2 Interrupt + (uint32_t) EINT3_IRQHandler, // 13: External Input 3 Interrupt + (uint32_t) EINT4_IRQHandler, // 14: External Input 4 Interrupt + (uint32_t) EINT5_IRQHandler, // 15: External Input 5 Interrupt + (uint32_t) GPA_IRQHandler, // 16: GPIO PORT A Interrupt + (uint32_t) GPB_IRQHandler, // 17: GPIO PORT B Interrupt + (uint32_t) GPC_IRQHandler, // 18: GPIO PORT C Interrupt + (uint32_t) GPD_IRQHandler, // 19: GPIO PORT D Interrupt + (uint32_t) GPE_IRQHandler, // 20: GPIO PORT E Interrupt + (uint32_t) GPF_IRQHandler, // 21: GPIO PORT F Interrupt + (uint32_t) QSPI0_IRQHandler, // 22: QSPI0 Interrupt + (uint32_t) SPI0_IRQHandler, // 23: SPI0 Interrupt + (uint32_t) BRAKE0_IRQHandler, // 24: PWM Brake0 Interrupt + (uint32_t) PWM0_P0_IRQHandler, // 25: PWM0 P0 Interrupt + (uint32_t) PWM0_P1_IRQHandler, // 26: PWM0 P1 Interrupt + (uint32_t) PWM0_P2_IRQHandler, // 27: PWM0 P2 Interrupt + (uint32_t) BRAKE1_IRQHandler, // 28: PWM Brake1 Interrupt + (uint32_t) PWM1_P0_IRQHandler, // 29: PWM1 P0 Interrupt + (uint32_t) PWM1_P1_IRQHandler, // 30: PWM1 P1 Interrupt + (uint32_t) PWM1_P2_IRQHandler, // 31: PWM1 P2 Interrupt + (uint32_t) TMR0_IRQHandler, // 32: TIMER0 Interrupt + (uint32_t) TMR1_IRQHandler, // 33: TIMER1 Interrupt + (uint32_t) TMR2_IRQHandler, // 34: TIMER2 Interrupt + (uint32_t) TMR3_IRQHandler, // 35: TIMER3 Interrupt + (uint32_t) UART0_IRQHandler, // 36: UART0 Interrupt + (uint32_t) UART1_IRQHandler, // 37: UART1 Interrupt + (uint32_t) I2C0_IRQHandler, // 38: I2C0 Interrupt + (uint32_t) I2C1_IRQHandler, // 39: I2C1 Interrupt + (uint32_t) PDMA_IRQHandler, // 40: Peripheral DMA Interrupt + (uint32_t) DAC_IRQHandler, // 41: DAC Interrupt + (uint32_t) EADC_INT0_IRQHandler, // 42: Enhance ADC Interrupt 0 + (uint32_t) EADC_INT1_IRQHandler, // 43: Enhance ADC Interrupt 1 + (uint32_t) ACMP01_IRQHandler, // 44: ACMP0 Interrupt + (uint32_t) BPWM0_IRQHandler, // 45: BPWM0 Interrupt + (uint32_t) EADC_INT2_IRQHandler, // 46: Enhance EADC Interrupt 2 + (uint32_t) EADC_INT3_IRQHandler, // 47: Enhance EADC Interrupt 3 + (uint32_t) UART2_IRQHandler, // 48: UART2 Interrupt + (uint32_t) Default_Handler, // 49: Reserved + (uint32_t) USCI0_IRQHandler, // 50: USCI0 Interrupt + (uint32_t) Default_Handler, // 51: Reserved + (uint32_t) USCI1_IRQHandler, // 52: USCI1 Interrupt + (uint32_t) USBD_IRQHandler, // 53: USB Device Interrupt + (uint32_t) BPWM1_IRQHandler, // 54: BPWM1 Interrupt + (uint32_t) PSIO_IRQHandler, // 55: PSIO Interrupt + (uint32_t) Default_Handler, // 56: Reserved + (uint32_t) CRPT_IRQHandler, // 57: Cryption Interrupt + (uint32_t) SC0_IRQHandler, // 58: Smart Card0 Interrupt + (uint32_t) Default_Handler, // 59: Reserved + (uint32_t) USCI2_IRQHandler, // 60: USCI2 Interrupt + (uint32_t) Default_Handler, // 61: Reserved + (uint32_t) OPA_IRQHandler, // 62: OPA Interrupt + (uint32_t) Default_Handler, // 63: Reserved +}; + +void Reset_Handler(void) +{ + /* Disable register write-protection function */ + SYS_UnlockReg(); + + /* Disable Power-on Reset function */ + SYS_DISABLE_POR(); + /* After power-on, user can turn off internal analog POR circuit to save + * power by writing 0x5AA5 to this field. */ + SYS->PORCTL1 = 0x5AA5; + + /* SystemInit() must be called at the very start. */ + SystemInit(); + + /* Enable register write-protection function */ + SYS_LockReg(); + +#if defined(__ARMCC_VERSION) + __main(); + +#elif defined(__ICCARM__) + __iar_program_start(); + +#elif defined(__GNUC__) + /* Move (multiple) .data section(s) from ROM to RAM */ + { + /* Struct of copy table entry which must match linker script */ + typedef struct copy_table_entry_ { + uint32_t src; // Address to copy from + uint32_t dst; // Address to copy to + uint32_t size; // Copy size in bytes + } copy_table_entry; + + copy_table_entry *copy_table_ind = (copy_table_entry *) &__copy_table_start__; + copy_table_entry *copy_table_end = (copy_table_entry *) &__copy_table_end__; + + for (; copy_table_ind != copy_table_end; copy_table_ind ++) { + uint32_t *src_ind = (uint32_t *) copy_table_ind->src; + uint32_t *src_end = (uint32_t *) (copy_table_ind->src + copy_table_ind->size); + uint32_t *dst_ind = (uint32_t *) copy_table_ind->dst; + if (src_ind != dst_ind) { + for (; src_ind < src_end;) { + *dst_ind ++ = *src_ind ++; + } + } + } + } + + /* Initialize (multiple) .bss sections to zero */ + { + /* Struct of zero table entry which must match linker script */ + typedef struct zero_table_entry_ { + uint32_t start; // Address to start zero'ing + uint32_t size; // Zero size in bytes + } zero_table_entry; + + zero_table_entry *zero_table_ind = (zero_table_entry *) &__zero_table_start__; + zero_table_entry *zero_table_end = (zero_table_entry *) &__zero_table_end__; + + for (; zero_table_ind != zero_table_end; zero_table_ind ++) { + uint32_t *dst_ind = (uint32_t *) zero_table_ind->start; + uint32_t *dst_end = (uint32_t *) (zero_table_ind->start + zero_table_ind->size); + + for (; dst_ind < dst_end; ) { + *dst_ind ++ = 0; + } + } + } + + _start(); + +#endif + + /* Infinite loop */ + while (1); +} + +/* Default interrupt handler for unused IRQs. */ +void Default_Handler(void) +{ + while (1); +} diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/system_M251.c b/targets/TARGET_NUVOTON/TARGET_M251/device/system_M251.c new file mode 100644 index 00000000000..9335fe23703 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/system_M251.c @@ -0,0 +1,154 @@ +/**************************************************************************//** +* @file system_M251.c +* @version V0.10 +* @brief System Setting Source File +* +* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. +****************************************************************************/ + +#include +#include +#include +#include "M251.h" + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_M251.h" +#endif + + +#if defined(__ICCARM__) +extern void *__vector_table; /* see startup file */ +#else +extern void *__vector_handlers; /* see startup file */ +#endif + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __HSI; /*!< System Clock Frequency (Core Clock) */ +uint32_t CyclesPerUs = (__HSI / 1000000); /*!< Cycles per micro second */ +uint32_t PllClock = __HSI; /*!< PLL Output Clock Frequency */ +const uint32_t gau32ClkSrcTbl[8] = {__HXT, __LXT, 0UL, __LIRC, 0UL, __MIRC, 0UL, __HIRC}; + + +/** + * @brief Update the Variable SystemCoreClock + * + * @param None + * + * @return None + * + * @details This function is used to update the variable SystemCoreClock + * and must be called whenever the core clock is changed. + */ +void SystemCoreClockUpdate(void) +{ + uint32_t u32Freq, u32ClkSrc; + uint32_t u32HclkDiv; + + u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk; + + /* Update PLL Clock */ + PllClock = CLK_GetPLLClockFreq(); + + if (u32ClkSrc != CLK_CLKSEL0_HCLKSEL_PLL) + { + /* Use the clock sources directly */ + u32Freq = gau32ClkSrcTbl[u32ClkSrc]; + } + else + { + /* Use PLL clock */ + u32Freq = PllClock; + } + + u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1; + + /* Update System Core Clock */ + SystemCoreClock = u32Freq / u32HclkDiv; + + CyclesPerUs = (SystemCoreClock + 500000) / 1000000; +} + + + +/** + * @brief System Initialization + * + * @param None + * + * @return None + * + * @details The necessary initialization of system. Global variables are forbidden here. + */ +void SystemInit(void) +{ + /* Set access cycle for CPU @ 48MHz */ + FMC->CYCCTL = (FMC->CYCCTL & ~FMC_CYCCTL_CYCLE_Msk) | (3 << FMC_CYCCTL_CYCLE_Pos) | 0x100; + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +#if defined(__ICCARM__) + SCB->VTOR = (uint32_t) &__vector_table; +#else + SCB->VTOR = (uint32_t) &__vector_handlers; +#endif +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); + SCU_Setup(); + FMC_NSBA_Setup(); +#endif + +#ifdef INIT_SYSCLK_AT_BOOTING + +#endif + +} + + +#if USE_ASSERT + +/** + * @brief Assert Error Message + * + * @param[in] file the source file name + * @param[in] line line number + * + * @return None + * + * @details The function prints the source file name and line number where + * the ASSERT_PARAM() error occurs, and then stops in an infinite loop. + */ +void AssertError(uint8_t *file, uint32_t line) +{ + + printf("[%s] line %d : wrong parameters.\r\n", file, line); + + /* Infinite loop */ + while (1) ; +} +#endif + +/** + * @brief Set UART0 Default MPF + * + * @param None + * + * @return None + * + * @details The initialization of uart0 default multi function pin. + */ +#if defined( __ICCARM__ ) + __WEAK +#else + __attribute__((weak)) +#endif +void Uart0DefaultMPF(void) +{ + + /* Set GPB multi-function pins for UART0 RXD and TXD */ + SYS->GPB_MFPH = (SYS->GPB_MFPH & ~SYS_GPB_MFPH_PB12MFP_Msk) | SYS_GPB_MFPH_PB12MFP_UART0_RXD; + SYS->GPB_MFPH = (SYS->GPB_MFPH & ~SYS_GPB_MFPH_PB13MFP_Msk) | SYS_GPB_MFPH_PB13MFP_UART0_TXD; + +} diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/system_M251.h b/targets/TARGET_NUVOTON/TARGET_M251/device/system_M251.h new file mode 100644 index 00000000000..974e1cc7485 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/system_M251.h @@ -0,0 +1,75 @@ +/**************************************************************************//** +* @file system_M251.h +* @version V0.10 +* @brief System Setting Header File +* +* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. +****************************************************************************/ + +#ifndef __SYSTEM_M251_H__ +#define __SYSTEM_M251_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __HXT (12000000UL) /*!< External Crystal Clock Frequency */ +#define __LXT (32768UL) /*!< External Crystal Clock Frequency 32.768KHz */ +#define __LIRC (38400UL) /*!< Internal 38.4KHz RC Oscillator Frequency */ +#define __MIRC (4032000UL) /*!< Internal 4.032M RC Oscillator Frequency */ +#define __HIRC (48000000UL) /*!< Internal 48M RC Oscillator Frequency */ +#define __HSI (48000000UL) /*!< PLL default output is 48MHz */ +#define __SYS_OSC_CLK ( ___HSI) /*!< Main oscillator frequency */ + +#define __SYSTEM_CLOCK (1UL*__HXT) + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +extern uint32_t CyclesPerUs; /*!< Cycles per micro second */ +extern uint32_t PllClock; /*!< PLL Output Clock Frequency */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the micro controller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit(void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate(void); + +/** + * Set UART0 default multi function pin + * + * @param none + * @return none + * + * @brief The initialization of uart0 default multiple-function pin. + */ +extern void Uart0DefaultMPF(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_M251_H__ */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/dma.h b/targets/TARGET_NUVOTON/TARGET_M251/dma.h new file mode 100644 index 00000000000..ba554855b0d --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/dma.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2019, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_DMA_H +#define MBED_DMA_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define DMA_CAP_NONE (0 << 0) + +#define DMA_EVENT_ABORT (1 << 0) +#define DMA_EVENT_TRANSFER_DONE (1 << 1) +#define DMA_EVENT_TIMEOUT (1 << 2) +#define DMA_EVENT_ALL (DMA_EVENT_ABORT | DMA_EVENT_TRANSFER_DONE | DMA_EVENT_TIMEOUT) +#define DMA_EVENT_MASK DMA_EVENT_ALL + +void dma_set_handler(int channelid, uint32_t handler, uint32_t id, uint32_t event); +PDMA_T *dma_modbase(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M251/dma_api.c b/targets/TARGET_NUVOTON/TARGET_M251/dma_api.c new file mode 100644 index 00000000000..a8a23b0573d --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/dma_api.c @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2019, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dma_api.h" +#include "string.h" +#include "cmsis.h" +#include "mbed_assert.h" +#include "PeripheralNames.h" +#include "nu_modutil.h" +#include "nu_bitutil.h" +#include "dma.h" + +#define NU_PDMA_CH_MAX PDMA_CH_MAX /* Specify maximum channels of PDMA */ +#define NU_PDMA_CH_Pos 0 /* Specify first channel number of PDMA */ +#define NU_PDMA_CH_Msk (((1 << NU_PDMA_CH_MAX) - 1) << NU_PDMA_CH_Pos) + +struct nu_dma_chn_s { + void (*handler)(uint32_t, uint32_t); + uint32_t id; + uint32_t event; +}; + +static int dma_inited = 0; +static uint32_t dma_chn_mask = 0; +static struct nu_dma_chn_s dma_chn_arr[NU_PDMA_CH_MAX]; + +static void pdma_vec(void); +static const struct nu_modinit_s dma_modinit = {DMA_0, PDMA_MODULE, 0, 0, PDMA_RST, PDMA_IRQn, (void *) pdma_vec}; + +void dma_init(void) +{ + if (dma_inited) { + return; + } + + dma_inited = 1; + dma_chn_mask = ~NU_PDMA_CH_Msk; + memset(dma_chn_arr, 0x00, sizeof (dma_chn_arr)); + + /* Reset module */ + SYS_ResetModule(dma_modinit.rsetidx); + + /* Enable IP clock */ + CLK_EnableModuleClock(dma_modinit.clkidx); + + PDMA_T *pdma_base = dma_modbase(); + + PDMA_Open(pdma_base, 0); + + NVIC_SetVector(dma_modinit.irq_n, (uint32_t) dma_modinit.var); + NVIC_EnableIRQ(dma_modinit.irq_n); +} + +int dma_channel_allocate(uint32_t capabilities) +{ + if (! dma_inited) { + dma_init(); + } + + int i = nu_cto(dma_chn_mask); + if (i != 32) { + dma_chn_mask |= 1 << i; + memset(dma_chn_arr + i - NU_PDMA_CH_Pos, 0x00, sizeof (struct nu_dma_chn_s)); + return i; + } + + // No channel available + return DMA_ERROR_OUT_OF_CHANNELS; +} + +int dma_channel_free(int channelid) +{ + if (channelid != DMA_ERROR_OUT_OF_CHANNELS) { + dma_chn_mask &= ~(1 << channelid); + } + + return 0; +} + +void dma_set_handler(int channelid, uint32_t handler, uint32_t id, uint32_t event) +{ + MBED_ASSERT(dma_chn_mask & (1 << channelid)); + + dma_chn_arr[channelid - NU_PDMA_CH_Pos].handler = (void (*)(uint32_t, uint32_t)) handler; + dma_chn_arr[channelid - NU_PDMA_CH_Pos].id = id; + dma_chn_arr[channelid - NU_PDMA_CH_Pos].event = event; + + // Set interrupt vector if someone has removed it. + NVIC_SetVector(dma_modinit.irq_n, (uint32_t) dma_modinit.var); + NVIC_EnableIRQ(dma_modinit.irq_n); +} + +PDMA_T *dma_modbase(void) +{ + return (PDMA_T *) NU_MODBASE(dma_modinit.modname); +} + +static void pdma_vec(void) +{ + PDMA_T *pdma_base = (PDMA_T *) NU_MODBASE(dma_modinit.modname); + + uint32_t intsts = PDMA_GET_INT_STATUS(pdma_base); + + // Abort + if (intsts & PDMA_INTSTS_ABTIF_Msk) { + uint32_t abtsts = PDMA_GET_ABORT_STS(pdma_base); + // Clear all Abort flags + PDMA_CLR_ABORT_FLAG(pdma_base, abtsts); + + while (abtsts) { + int chn_id = nu_ctz(abtsts) - PDMA_ABTSTS_ABTIF0_Pos + NU_PDMA_CH_Pos; + if (dma_chn_mask & (1 << chn_id)) { + struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id - NU_PDMA_CH_Pos; + if (dma_chn->handler && (dma_chn->event & DMA_EVENT_ABORT)) { + dma_chn->handler(dma_chn->id, DMA_EVENT_ABORT); + } + } + abtsts &= ~(1 << (chn_id - NU_PDMA_CH_Pos + PDMA_ABTSTS_ABTIF0_Pos)); + } + } + + // Transfer done + if (intsts & PDMA_INTSTS_TDIF_Msk) { + uint32_t tdsts = PDMA_GET_TD_STS(pdma_base); + // Clear all transfer done flags + PDMA_CLR_TD_FLAG(pdma_base, tdsts); + + while (tdsts) { + int chn_id = nu_ctz(tdsts) - PDMA_TDSTS_TDIF0_Pos + NU_PDMA_CH_Pos; + if (dma_chn_mask & (1 << chn_id)) { + struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id - NU_PDMA_CH_Pos; + if (dma_chn->handler && (dma_chn->event & DMA_EVENT_TRANSFER_DONE)) { + dma_chn->handler(dma_chn->id, DMA_EVENT_TRANSFER_DONE); + } + } + tdsts &= ~(1 << (chn_id - NU_PDMA_CH_Pos + PDMA_TDSTS_TDIF0_Pos)); + } + } + + // Timeout + uint32_t reqto = intsts & (PDMA_INTSTS_REQTOF0_Msk | PDMA_INTSTS_REQTOF1_Msk); + if (reqto) { + // Clear all Timeout flags + pdma_base->INTSTS = reqto; + + while (reqto) { + int chn_id = nu_ctz(reqto) - PDMA_INTSTS_REQTOF0_Pos + NU_PDMA_CH_Pos; + if (dma_chn_mask & (1 << chn_id)) { + struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id - NU_PDMA_CH_Pos; + if (dma_chn->handler && (dma_chn->event & DMA_EVENT_TIMEOUT)) { + dma_chn->handler(dma_chn->id, DMA_EVENT_TIMEOUT); + } + } + reqto &= ~(1 << (chn_id - NU_PDMA_CH_Pos + PDMA_INTSTS_REQTOF0_Pos)); + } + } +} diff --git a/targets/TARGET_NUVOTON/TARGET_M251/flash_api.c b/targets/TARGET_NUVOTON/TARGET_M251/flash_api.c new file mode 100644 index 00000000000..aee985d597a --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/flash_api.c @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2019, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "flash_api.h" + +#if DEVICE_FLASH + +#include "flash_data.h" +#include "mbed_critical.h" + +// This is a flash algo binary blob. It is PIC (position independent code) that should be stored in RAM +// NOTE: On ARMv7-M/ARMv8-M, instruction fetches are always little-endian. +static uint32_t FLASH_ALGO[] = { + 0xb088b5b0, 0x460c4613, 0x90064605, 0x92049105, 0x90032064, 0x1000f240, 0x0000f2c4, 0x60012159, + 0x60012116, 0x60012188, 0x21016800, 0x93024208, 0x95009401, 0xe7ffd103, 0x90072001, 0xf240e038, + 0xf2c42000, 0x68010000, 0x43112204, 0xf2406001, 0xf2c42004, 0x68010000, 0x60014311, 0x9803e7ff, + 0x91031e41, 0xd0012800, 0xe7f8e7ff, 0x0000f24c, 0x0000f2c4, 0x222d6801, 0x60014311, 0x011cf24c, + 0x0100f2c4, 0x2301680a, 0x600a431a, 0x42186800, 0xe7ffd103, 0x90072001, 0xf24ce00a, 0xf2c40000, + 0x68010000, 0x43112240, 0x20006001, 0xe7ff9007, 0xb0089807, 0xb082bdb0, 0x90014601, 0xe7ff9100, + 0x0010f24c, 0x0000f2c4, 0x21016800, 0xd0014208, 0xe7f5e7ff, 0x0000f24c, 0x0000f2c4, 0x222d6801, + 0x60014391, 0x001cf24c, 0x0000f2c4, 0x22016801, 0x60014391, 0xb0022000, 0xb0834770, 0x90014601, + 0xe7ff9100, 0x0010f24c, 0x0000f2c4, 0x21016800, 0xd0014208, 0xe7f5e7ff, 0x0000f24c, 0x0000f2c4, + 0x22406801, 0x60014311, 0x000cf24c, 0x0000f2c4, 0x60012122, 0x21039801, 0xf24c4388, 0xf2c40104, + 0x60080100, 0x0010f24c, 0x0000f2c4, 0x60012101, 0x8f6ff3bf, 0xf24ce7ff, 0xf2c40010, 0x68000000, + 0x42082101, 0xe7ffd001, 0xf24ce7f5, 0xf2c40000, 0x68000000, 0x42082140, 0xe7ffd00b, 0x0000f24c, + 0x0000f2c4, 0x22406801, 0x60014311, 0x90022001, 0x2000e002, 0xe7ff9002, 0xb0039802, 0xb5804770, + 0x460ab088, 0x90064603, 0x20009105, 0x92029004, 0xe7ff9301, 0x99059804, 0xd2104288, 0x9806e7ff, + 0x1c4a9904, 0x00899204, 0xf7ff5840, 0x9003ff96, 0xd0032800, 0x9803e7ff, 0xe0039007, 0x2000e7ea, + 0xe7ff9007, 0xb0089807, 0xb5b0bd80, 0x4613b08a, 0x4605460c, 0x91079008, 0x20009206, 0x90039004, + 0x94019302, 0xe7ff9500, 0x0010f24c, 0x0000f2c4, 0x21016800, 0xd0014208, 0xe7f5e7ff, 0x0000f24c, + 0x0000f2c4, 0x22406801, 0x60014311, 0x1cc09807, 0x43882103, 0xe7ff9007, 0x28009807, 0xe7ffd04c, + 0x7800a808, 0x28000640, 0xe7ffd10f, 0x28809807, 0xe7ffd30b, 0x90052080, 0x99059808, 0x9b049a06, + 0xf00018d2, 0x9003f83f, 0xa808e022, 0x06407800, 0xd1112800, 0x9807e7ff, 0xd30d2810, 0x9807e7ff, + 0x4388210f, 0x98089005, 0x9a069905, 0x18d29b04, 0xf828f000, 0xe00a9003, 0x90059807, 0x99059808, + 0x9b049a06, 0xf00018d2, 0x9003f8de, 0xe7ffe7ff, 0x99089805, 0x90081808, 0x99049805, 0x90041808, + 0x99079805, 0x90071a08, 0x28009803, 0xe7ffd003, 0x90092001, 0xe7afe003, 0x90092000, 0x9809e7ff, + 0xbdb0b00a, 0xb088b5b0, 0x460c4613, 0x90074605, 0x92059106, 0x90049805, 0x300f9806, 0x4388210f, + 0x93039006, 0x95019402, 0xf24ce7ff, 0xf2c40010, 0x68000000, 0x42082101, 0xe7ffd001, 0xf24ce7f5, + 0xf2c40000, 0x68010000, 0x43112240, 0x98076001, 0x4388210f, 0x0104f24c, 0x0100f2c4, 0xf24c6008, + 0xf2c4000c, 0x21270000, 0x98046001, 0xf984f000, 0x0180f24c, 0x0100f2c4, 0x98046008, 0x90041d00, + 0xf0009804, 0xf24cf979, 0xf2c40184, 0x60080100, 0x1d009804, 0x98049004, 0xf96ef000, 0x0188f24c, + 0x0100f2c4, 0x98046008, 0x90041d00, 0xf0009804, 0xf24cf963, 0xf2c4018c, 0x60080100, 0x1d009804, + 0xf24c9004, 0xf2c40010, 0x21010000, 0x98066001, 0x90063810, 0x9806e7ff, 0xd0462800, 0xe7ffe7ff, + 0x00c0f24c, 0x0000f2c4, 0x21306800, 0xd0014208, 0xe7f5e7ff, 0xf0009804, 0xf24cf93f, 0xf2c40180, + 0x60080100, 0x1d009804, 0x98049004, 0xf934f000, 0x0184f24c, 0x0100f2c4, 0x98046008, 0x90041d00, + 0xf24ce7ff, 0xf2c400c0, 0x68000000, 0x420821c0, 0xe7ffd001, 0x9804e7f5, 0xf91ef000, 0x0188f24c, + 0x0100f2c4, 0x98046008, 0x90041d00, 0xf0009804, 0xf24cf913, 0xf2c4018c, 0x60080100, 0x1d009804, + 0x98069004, 0x90063810, 0xe7ffe7b5, 0x0010f24c, 0x0000f2c4, 0x21016800, 0xd0014208, 0xe7f5e7ff, + 0xb0082000, 0xb5b0bdb0, 0x4613b088, 0x4605460c, 0x91059006, 0x98059204, 0x21031cc0, 0x90054388, + 0x94029303, 0xe7ff9501, 0x0010f24c, 0x0000f2c4, 0x21016800, 0xd0014208, 0xe7f5e7ff, 0x0000f24c, + 0x0000f2c4, 0x22406801, 0x60014311, 0x000cf24c, 0x0000f2c4, 0x60012121, 0x9805e7ff, 0xd0412800, + 0x9806e7ff, 0x43882103, 0x0104f24c, 0x0100f2c4, 0x98046008, 0xf8c0f000, 0x0108f24c, 0x0100f2c4, + 0xf24c6008, 0xf2c40010, 0x21010000, 0xf3bf6001, 0xe7ff8f6f, 0x0010f24c, 0x0000f2c4, 0x21016800, + 0xd0014208, 0xe7f5e7ff, 0x0000f24c, 0x0000f2c4, 0x21406800, 0xd00b4208, 0xf24ce7ff, 0xf2c40000, + 0x68010000, 0x43112240, 0x20016001, 0xe00c9007, 0x1d009806, 0x98049006, 0x90041d00, 0x1f009805, + 0xe7ba9005, 0x90072000, 0x9807e7ff, 0xbdb0b008, 0xb088b5b0, 0x460c4613, 0x90064605, 0x92049105, + 0x1cc09805, 0x43882103, 0x93039005, 0x95019402, 0xf24ce7ff, 0xf2c40010, 0x68000000, 0x42082101, + 0xe7ffd001, 0xf24ce7f5, 0xf2c40000, 0x68010000, 0x43112240, 0xf24c6001, 0xf2c4000c, 0x21000000, + 0xe7ff6001, 0x28009805, 0xe7ffd050, 0x21039806, 0xf24c4388, 0xf2c40104, 0x60080100, 0x0008f24c, + 0x0000f2c4, 0x60012100, 0x0010f24c, 0x0000f2c4, 0x60012101, 0x8f6ff3bf, 0xf24ce7ff, 0xf2c40010, + 0x68000000, 0x42082101, 0xe7ffd001, 0xf24ce7f5, 0xf2c40000, 0x68000000, 0x42082140, 0xe7ffd00b, + 0x0000f24c, 0x0000f2c4, 0x22406801, 0x60014311, 0x90079806, 0xf24ce01d, 0xf2c40008, 0x68000000, + 0x90009904, 0xf0004608, 0x9900f817, 0xd0034281, 0x9806e7ff, 0xe00c9007, 0x1d009806, 0x98049006, + 0x90041d00, 0x1f009805, 0xe7ab9005, 0x90079806, 0x9807e7ff, 0xbdb0b008, 0x4601b083, 0x98029002, + 0x92021c42, 0x90017800, 0x1c429802, 0x78009202, 0x9a010200, 0x90011810, 0x1c429802, 0x78009202, + 0x9a010400, 0x90011810, 0x1c429802, 0x78009202, 0x9a010600, 0x90011810, 0x91009801, 0x4770b003, + 0x00000000, +}; + +static const flash_algo_t flash_algo_config = { + .init = 0x00000001, + .uninit = 0x000000b7, + .erase_sector = 0x000000fb, + .program_page = 0x000001eb, + .static_base = 0x000006a0, + .algo_blob = FLASH_ALGO +}; + +/* Secure flash */ +static const sector_info_t sectors_info[] = { + {0x0, 0x200}, // (start, sector size) +}; + +/* Secure flash */ +static const flash_target_config_t flash_target_config = { + .page_size = 4, // 4 bytes + // Here page_size is program unit, which is different + // than FMC definition. + .flash_start = 0x0, + .flash_size = 0x40000, + .sectors = sectors_info, + .sector_info_count = sizeof(sectors_info) / sizeof(sector_info_t) +}; + +void flash_set_target_config(flash_t *obj) +{ + obj->flash_algo = &flash_algo_config; + obj->target_config = &flash_target_config; +} +#endif // #if DEVICE_FLASH diff --git a/targets/TARGET_NUVOTON/TARGET_M251/gpio_api.c b/targets/TARGET_NUVOTON/TARGET_M251/gpio_api.c new file mode 100644 index 00000000000..da83e415f1b --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/gpio_api.c @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2019, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "gpio_api.h" +#include "mbed_assert.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "PeripheralPins.h" + +uint32_t gpio_set(PinName pin) +{ + if (pin == (PinName) NC) { + return 0; + } + + uint32_t pin_index = NU_PININDEX(pin); + +#if 1 + pin_function(pin, 0 << NU_MFP_POS(pin_index)); +#else + pinmap_pinout(pin, PinMap_GPIO); +#endif + + return (uint32_t)(1 << pin_index); // Return the pin mask +} + +int gpio_is_connected(const gpio_t *obj) +{ + return (obj->pin != (PinName) NC); +} + +void gpio_init(gpio_t *obj, PinName pin) +{ + obj->pin = pin; + + if (obj->pin == (PinName) NC) { + return; + } + + obj->mask = gpio_set(pin); + /* Default mode/direction */ + obj->mode = PullUp; + obj->direction = PIN_INPUT; +} + +void gpio_mode(gpio_t *obj, PinMode mode) +{ + if (obj->pin == (PinName) NC) { + return; + } + + switch (mode) { + case PullNone: + case PullDown: + case PullUp: + /* H/W doesn't support separate configuration for input pull mode/direction. + * We translate to input-only/push-pull output I/O mode dependent on direction. */ + obj->mode = (obj->direction == PIN_INPUT) ? InputOnly : PushPullOutput; + break; + + case QuasiBidirectional: + /* With quasi-bidirectional I/O mode, before digital input function is performed, + * the corresponding bit in GPIOx_DOUT must be set to 1. */ + obj->mode = QuasiBidirectional; + if (obj->direction == PIN_INPUT) { + gpio_write(obj, 1); + } + break; + + case InputOnly: + case PushPullOutput: + /* We may meet contradictory I/O mode/direction configuration. Favor I/O mode + * in the gpio_mode call here. */ + if (mode == InputOnly) { + obj->direction = PIN_INPUT; + obj->mode = InputOnly; + } else { + obj->direction = PIN_OUTPUT; + obj->mode = PushPullOutput; + } + break; + + default: + /* Allow for configuring other I/O modes directly */ + obj->mode = mode; + break; + } + + pin_mode(obj->pin, obj->mode); +} + +void gpio_dir(gpio_t *obj, PinDirection direction) +{ + if (obj->pin == (PinName) NC) { + return; + } + + obj->direction = direction; + + switch (obj->mode) { + case PullNone: + case PullDown: + case PullUp: + /* H/W doesn't support separate configuration for input pull mode/direction. + * We translate to input-only/push-pull output I/O mode dependent on direction. */ + obj->mode = (obj->direction == PIN_INPUT) ? InputOnly : PushPullOutput; + break; + + case QuasiBidirectional: + /* With quasi-bidirectional I/O mode, before digital input function is performed, + * the corresponding bit in GPIOx_DOUT must be set to 1. */ + if (obj->direction == PIN_INPUT) { + gpio_write(obj, 1); + } + break; + + case InputOnly: + case PushPullOutput: + /* We may meet contradictory I/O mode/direction configuration. Favor direction + * in the gpio_dir call here. */ + obj->mode = (obj->direction == PIN_INPUT) ? InputOnly : PushPullOutput; + break; + + default: + break; + } + + pin_mode(obj->pin, obj->mode); +} diff --git a/targets/TARGET_NUVOTON/TARGET_M251/gpio_irq_api.c b/targets/TARGET_NUVOTON/TARGET_M251/gpio_irq_api.c new file mode 100644 index 00000000000..df4611e018c --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/gpio_irq_api.c @@ -0,0 +1,256 @@ +/* + * Copyright (c) 2019, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "gpio_irq_api.h" + +#if DEVICE_INTERRUPTIN + +#include "gpio_api.h" +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralPins.h" +#include "nu_bitutil.h" + +#define NU_MAX_PIN_PER_PORT 16 + +struct nu_gpio_irq_var { + gpio_irq_t * obj_arr[NU_MAX_PIN_PER_PORT]; + IRQn_Type irq_n; + void (*vec)(void); + uint32_t port_index; +}; + +static void gpio_irq_0_vec(void); +static void gpio_irq_1_vec(void); +static void gpio_irq_2_vec(void); +static void gpio_irq_3_vec(void); +static void gpio_irq_4_vec(void); +static void gpio_irq_5_vec(void); +static void gpio_irq(struct nu_gpio_irq_var *var); + +//EINT0_IRQn +static struct nu_gpio_irq_var gpio_irq_var_arr[] = { + {{NULL}, GPA_IRQn, gpio_irq_0_vec, 0}, + {{NULL}, GPB_IRQn, gpio_irq_1_vec, 1}, + {{NULL}, GPC_IRQn, gpio_irq_2_vec, 2}, + {{NULL}, GPD_IRQn, gpio_irq_3_vec, 3}, + {{NULL}, GPE_IRQn, gpio_irq_4_vec, 4}, + {{NULL}, GPF_IRQn, gpio_irq_5_vec, 5}, +}; + +#define NU_MAX_PORT (sizeof (gpio_irq_var_arr) / sizeof (gpio_irq_var_arr[0])) + +#ifndef MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE +#define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE 0 +#endif + +#ifndef MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE_LIST +#define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE_LIST NC +#endif +static PinName gpio_irq_debounce_arr[] = { + MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE_LIST +}; + +#ifndef MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE +#define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE GPIO_DBCTL_DBCLKSRC_LIRC +#endif + +#ifndef MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE +#define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE GPIO_DBCTL_DBCLKSEL_16 +#endif + +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +{ + if (pin == NC) { + return -1; + } + + uint32_t pin_index = NU_PININDEX(pin); + uint32_t port_index = NU_PINPORT(pin); + if (pin_index >= NU_MAX_PIN_PER_PORT || port_index >= NU_MAX_PORT) { + return -1; + } + + obj->pin = pin; + obj->irq_handler = (uint32_t) handler; + obj->irq_id = id; + + GPIO_T *gpio_base = NU_PORT_BASE(port_index); + // NOTE: In InterruptIn constructor, gpio_irq_init() is called with gpio_init_in() which is responsible for multi-function pin setting. + // There is no need to call gpio_set() redundantly. + + { +#if MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE + // Suppress compiler warning + (void) gpio_irq_debounce_arr; + + // Configure de-bounce clock source and sampling cycle time + GPIO_SET_DEBOUNCE_TIME(MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE); + GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index); +#else + // Enable de-bounce if the pin is in the de-bounce enable list + + // De-bounce defaults to disabled. + GPIO_DISABLE_DEBOUNCE(gpio_base, 1 << pin_index); + + PinName *debounce_pos = gpio_irq_debounce_arr; + PinName *debounce_end = gpio_irq_debounce_arr + sizeof (gpio_irq_debounce_arr) / sizeof (gpio_irq_debounce_arr[0]); + for (; debounce_pos != debounce_end && *debounce_pos != NC; debounce_pos ++) { + uint32_t pin_index_debunce = NU_PININDEX(*debounce_pos); + uint32_t port_index_debounce = NU_PINPORT(*debounce_pos); + + if (pin_index == pin_index_debunce && + port_index == port_index_debounce) { + // Configure de-bounce clock source and sampling cycle time + GPIO_SET_DEBOUNCE_TIME(MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE); + GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index); + break; + } + } +#endif + } + + struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index; + + var->obj_arr[pin_index] = obj; + + // NOTE: InterruptIn requires IRQ enabled by default. + gpio_irq_enable(obj); + + return 0; +} + +void gpio_irq_free(gpio_irq_t *obj) +{ + uint32_t pin_index = NU_PININDEX(obj->pin); + uint32_t port_index = NU_PINPORT(obj->pin); + struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index; + + NVIC_DisableIRQ(var->irq_n); + NU_PORT_BASE(port_index)->INTEN = 0; + + MBED_ASSERT(pin_index < NU_MAX_PIN_PER_PORT); + var->obj_arr[pin_index] = NULL; +} + +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) +{ + uint32_t pin_index = NU_PININDEX(obj->pin); + uint32_t port_index = NU_PINPORT(obj->pin); + GPIO_T *gpio_base = NU_PORT_BASE(port_index); + + switch (event) { + case IRQ_RISE: + if (enable) { + GPIO_EnableInt(gpio_base, pin_index, GPIO_INT_RISING); + } else { + gpio_base->INTEN &= ~(GPIO_INT_RISING << pin_index); + } + break; + + case IRQ_FALL: + if (enable) { + GPIO_EnableInt(gpio_base, pin_index, GPIO_INT_FALLING); + } else { + gpio_base->INTEN &= ~(GPIO_INT_FALLING << pin_index); + } + break; + + case IRQ_NONE: + default: + break; + } +} + +void gpio_irq_enable(gpio_irq_t *obj) +{ + uint32_t port_index = NU_PINPORT(obj->pin); + struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index; + + NVIC_SetVector(var->irq_n, (uint32_t) var->vec); + NVIC_EnableIRQ(var->irq_n); +} + +void gpio_irq_disable(gpio_irq_t *obj) +{ + uint32_t port_index = NU_PINPORT(obj->pin); + struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index; + + NVIC_DisableIRQ(var->irq_n); +} + +static void gpio_irq_0_vec(void) +{ + gpio_irq(gpio_irq_var_arr + 0); +} +static void gpio_irq_1_vec(void) +{ + gpio_irq(gpio_irq_var_arr + 1); +} +static void gpio_irq_2_vec(void) +{ + gpio_irq(gpio_irq_var_arr + 2); +} +static void gpio_irq_3_vec(void) +{ + gpio_irq(gpio_irq_var_arr + 3); +} +static void gpio_irq_4_vec(void) +{ + gpio_irq(gpio_irq_var_arr + 4); +} +static void gpio_irq_5_vec(void) +{ + gpio_irq(gpio_irq_var_arr + 5); +} + +static void gpio_irq(struct nu_gpio_irq_var *var) +{ + // NOTE: GPA_IRQn, GPB_IRQn, ... are not arranged sequentially, so we cannot calculate out port_index through offset from GPA_IRQn. + // Instead, we add port_index into gpio_irq_var_arr table. + uint32_t port_index = var->port_index; + GPIO_T *gpio_base = NU_PORT_BASE(port_index); + + uint32_t intsrc = gpio_base->INTSRC; + uint32_t inten = gpio_base->INTEN; + while (intsrc) { + int pin_index = nu_ctz(intsrc); + gpio_irq_t *obj = var->obj_arr[pin_index]; + if (inten & (GPIO_INT_RISING << pin_index)) { + if (GPIO_PIN_DATA(port_index, pin_index)) { + if (obj->irq_handler) { + ((gpio_irq_handler) obj->irq_handler)(obj->irq_id, IRQ_RISE); + } + } + } + + if (inten & (GPIO_INT_FALLING << pin_index)) { + if (! GPIO_PIN_DATA(port_index, pin_index)) { + if (obj->irq_handler) { + ((gpio_irq_handler) obj->irq_handler)(obj->irq_id, IRQ_FALL); + } + } + } + + intsrc &= ~(1 << pin_index); + } + // Clear all interrupt flags + gpio_base->INTSRC = gpio_base->INTSRC; +} + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M251/gpio_object.h b/targets/TARGET_NUVOTON/TARGET_M251/gpio_object.h new file mode 100644 index 00000000000..aa1409ed893 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/gpio_object.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2019, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_GPIO_OBJECT_H +#define MBED_GPIO_OBJECT_H + +#include "mbed_assert.h" +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + PinName pin; + uint32_t mask; + PinDirection direction; + PinMode mode; +} gpio_t; + +static inline void gpio_write(gpio_t *obj, int value) +{ + MBED_ASSERT(obj->pin != (PinName)NC); + uint32_t pin_index = NU_PININDEX(obj->pin); + uint32_t port_index = NU_PINPORT(obj->pin); + + GPIO_PIN_DATA(port_index, pin_index) = value ? 1 : 0; +} + +static inline int gpio_read(gpio_t *obj) +{ + MBED_ASSERT(obj->pin != (PinName)NC); + uint32_t pin_index = NU_PININDEX(obj->pin); + uint32_t port_index = NU_PINPORT(obj->pin); + + return (GPIO_PIN_DATA(port_index, pin_index) ? 1 : 0); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M251/i2c_api.c b/targets/TARGET_NUVOTON/TARGET_M251/i2c_api.c new file mode 100644 index 00000000000..d91b77b35f9 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/i2c_api.c @@ -0,0 +1,927 @@ +/* + * Copyright (c) 2019, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "i2c_api.h" + +#if DEVICE_I2C + +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralPins.h" +#include "nu_modutil.h" +#include "nu_miscutil.h" +#include "nu_bitutil.h" +#include "mbed_critical.h" + +struct nu_i2c_var { + i2c_t * obj; + void (*vec)(void); +}; + +static void i2c0_vec(void); +static void i2c1_vec(void); +static void i2c_irq(i2c_t *obj); +static void i2c_fsm_reset(i2c_t *obj, uint32_t i2c_ctl); +static void i2c_fsm_tranfini(i2c_t *obj, int lastdatanaked); + +static struct nu_i2c_var i2c0_var = { + .obj = NULL, + .vec = i2c0_vec, +}; +static struct nu_i2c_var i2c1_var = { + .obj = NULL, + .vec = i2c1_vec, +}; + +static uint32_t i2c_modinit_mask = 0; + +static const struct nu_modinit_s i2c_modinit_tab[] = { + {I2C_0, I2C0_MODULE, 0, 0, I2C0_RST, I2C0_IRQn, &i2c0_var}, + {I2C_1, I2C1_MODULE, 0, 0, I2C1_RST, I2C1_IRQn, &i2c1_var}, + + {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL} +}; + +static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastdata); +static int i2c_do_trsn(i2c_t *obj, uint32_t i2c_ctl, int sync); +#define NU_I2C_TIMEOUT_STAT_INT 500000 +#define NU_I2C_TIMEOUT_STOP 500000 +static int i2c_poll_status_timeout(i2c_t *obj, int (*is_status)(i2c_t *obj), uint32_t timeout); +static int i2c_poll_tran_heatbeat_timeout(i2c_t *obj, uint32_t timeout); +static int i2c_is_trsn_done(i2c_t *obj); +static int i2c_is_tran_started(i2c_t *obj); +static int i2c_addr2data(int address, int read); +#if DEVICE_I2CSLAVE +// Convert mbed address to BSP address. +static int i2c_addr2bspaddr(int address); +#endif // #if DEVICE_I2CSLAVE +static void i2c_enable_int(i2c_t *obj); +static void i2c_disable_int(i2c_t *obj); +static int i2c_set_int(i2c_t *obj, int inten); + + +#if DEVICE_I2C_ASYNCH +static void i2c_buffer_set(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length); +static void i2c_enable_vector_interrupt(i2c_t *obj, uint32_t handler, int enable); +static void i2c_rollback_vector_interrupt(i2c_t *obj); +#endif + +#define TRANCTRL_STARTED (1) +#define TRANCTRL_NAKLASTDATA (1 << 1) +#define TRANCTRL_LASTDATANAKED (1 << 2) + +uint32_t us_ticker_read(void); + +void i2c_init(i2c_t *obj, PinName sda, PinName scl) +{ + uint32_t i2c_sda = pinmap_peripheral(sda, PinMap_I2C_SDA); + uint32_t i2c_scl = pinmap_peripheral(scl, PinMap_I2C_SCL); + obj->i2c.i2c = (I2CName) pinmap_merge(i2c_sda, i2c_scl); + MBED_ASSERT((int)obj->i2c.i2c != NC); + + const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->i2c.i2c); + + // Reset this module + SYS_ResetModule(modinit->rsetidx); + + // Enable IP clock + CLK_EnableModuleClock(modinit->clkidx); + + pinmap_pinout(sda, PinMap_I2C_SDA); + pinmap_pinout(scl, PinMap_I2C_SCL); + +#if DEVICE_I2C_ASYNCH + obj->i2c.dma_usage = DMA_USAGE_NEVER; + obj->i2c.event = 0; + obj->i2c.stop = 0; + obj->i2c.address = 0; +#endif + + // NOTE: Setting I2C bus clock to 100 KHz is required. See I2C::I2C in common/I2C.cpp. + I2C_Open((I2C_T *) NU_MODBASE(obj->i2c.i2c), 100000); + // NOTE: INTEN bit and FSM control bits (STA, STO, SI, AA) are packed in one register CTL0. We cannot control interrupt through + // INTEN bit without impacting FSM control bits. Use NVIC_EnableIRQ/NVIC_DisableIRQ instead for interrupt control. + I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c); + i2c_base->CTL0 |= (I2C_CTL0_INTEN_Msk | I2C_CTL0_I2CEN_Msk); + + // Enable sync-mode vector interrupt. + struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var; + var->obj = obj; + obj->i2c.tran_ctrl = 0; + obj->i2c.stop = 0; + i2c_enable_vector_interrupt(obj, (uint32_t) var->vec, 1); + + // Mark this module to be inited. + int i = modinit - i2c_modinit_tab; + i2c_modinit_mask |= 1 << i; +} + +int i2c_start(i2c_t *obj) +{ + return i2c_do_trsn(obj, I2C_CTL0_STA_Msk | I2C_CTL0_SI_Msk, 1); +} + +int i2c_stop(i2c_t *obj) +{ + return i2c_do_trsn(obj, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk, 1); +} + +void i2c_frequency(i2c_t *obj, int hz) +{ + I2C_SetBusClockFreq((I2C_T *) NU_MODBASE(obj->i2c.i2c), hz); +} + +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) +{ + if (i2c_start(obj)) { + i2c_stop(obj); + return I2C_ERROR_BUS_BUSY; + } + + if (i2c_byte_write(obj, i2c_addr2data(address, 1)) != 1) { + i2c_stop(obj); + return I2C_ERROR_NO_SLAVE; + } + + // Read in bytes + length = i2c_do_tran(obj, data, length, 1, 1); + + // If not repeated start, send stop. + if (stop) { + i2c_stop(obj); + } + + return length; +} + +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) +{ + if (i2c_start(obj)) { + i2c_stop(obj); + return I2C_ERROR_BUS_BUSY; + } + + if (i2c_byte_write(obj, i2c_addr2data(address, 0)) != 1) { + i2c_stop(obj); + return I2C_ERROR_NO_SLAVE; + } + + // Write out bytes + length = i2c_do_tran(obj, (char *) data, length, 0, 1); + + if (stop) { + i2c_stop(obj); + } + + return length; +} + +void i2c_reset(i2c_t *obj) +{ + i2c_stop(obj); +} + +int i2c_byte_read(i2c_t *obj, int last) +{ + char data = 0; + i2c_do_tran(obj, &data, 1, 1, last); + return data; +} + +int i2c_byte_write(i2c_t *obj, int data) +{ + char data_[1]; + data_[0] = data & 0xFF; + + if (i2c_do_tran(obj, data_, 1, 0, 0) == 1 && + ! (obj->i2c.tran_ctrl & TRANCTRL_LASTDATANAKED)) { + return 1; + } else { + return 0; + } +} + +const PinMap *i2c_master_sda_pinmap() +{ + return PinMap_I2C_SDA; +} + +const PinMap *i2c_master_scl_pinmap() +{ + return PinMap_I2C_SCL; +} + +const PinMap *i2c_slave_sda_pinmap() +{ + return PinMap_I2C_SDA; +} + +const PinMap *i2c_slave_scl_pinmap() +{ + return PinMap_I2C_SCL; +} + +#if DEVICE_I2CSLAVE + +// See I2CSlave.h +#define NoData 0 // the slave has not been addressed +#define ReadAddressed 1 // the master has requested a read from this slave (slave = transmitter) +#define WriteGeneral 2 // the master is writing to all slave +#define WriteAddressed 3 // the master is writing to this slave (slave = receiver) + +void i2c_slave_mode(i2c_t *obj, int enable_slave) +{ + I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c); + + i2c_disable_int(obj); + + obj->i2c.slaveaddr_state = NoData; + + // Switch to not addressed mode + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk); + + i2c_enable_int(obj); +} + +int i2c_slave_receive(i2c_t *obj) +{ + int slaveaddr_state; + + i2c_disable_int(obj); + slaveaddr_state = obj->i2c.slaveaddr_state; + i2c_enable_int(obj); + + return slaveaddr_state; +} + +int i2c_slave_read(i2c_t *obj, char *data, int length) +{ + return i2c_do_tran(obj, data, length, 1, 1); +} + +int i2c_slave_write(i2c_t *obj, const char *data, int length) +{ + return i2c_do_tran(obj, (char *) data, length, 0, 1); +} + +void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) +{ + I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c); + + i2c_disable_int(obj); + + // NOTE: On NUC472/M451, non-zero slave address can still work as GC mode is enabled. + // On M480, non-zero slave address won't work as GC mode is enabled. + I2C_SetSlaveAddr(i2c_base, 0, i2c_addr2bspaddr(address), I2C_GCMODE_DISABLE); + + i2c_enable_int(obj); +} + +static int i2c_addr2bspaddr(int address) +{ + return (address >> 1); +} + +#endif // #if DEVICE_I2CSLAVE + +static void i2c_enable_int(i2c_t *obj) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab); + + core_util_critical_section_enter(); + + // Enable I2C interrupt + NVIC_EnableIRQ(modinit->irq_n); + obj->i2c.inten = 1; + + core_util_critical_section_exit(); +} + +static void i2c_disable_int(i2c_t *obj) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab); + + core_util_critical_section_enter(); + + // Disable I2C interrupt + NVIC_DisableIRQ(modinit->irq_n); + obj->i2c.inten = 0; + + core_util_critical_section_exit(); +} + +static int i2c_set_int(i2c_t *obj, int inten) +{ + int inten_back; + + core_util_critical_section_enter(); + + inten_back = obj->i2c.inten; + + core_util_critical_section_exit(); + + if (inten) { + i2c_enable_int(obj); + } else { + i2c_disable_int(obj); + } + + return inten_back; +} + +static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastdata) +{ + if (! buf || ! length) { + return 0; + } + + int tran_len = 0; + + i2c_disable_int(obj); + obj->i2c.tran_ctrl = naklastdata ? (TRANCTRL_STARTED | TRANCTRL_NAKLASTDATA) : TRANCTRL_STARTED; + obj->i2c.tran_beg = buf; + obj->i2c.tran_pos = buf; + obj->i2c.tran_end = buf + length; + i2c_enable_int(obj); + + if (i2c_poll_tran_heatbeat_timeout(obj, NU_I2C_TIMEOUT_STAT_INT)) { + // N/A + } else { + i2c_disable_int(obj); + tran_len = obj->i2c.tran_pos - obj->i2c.tran_beg; + obj->i2c.tran_beg = NULL; + obj->i2c.tran_pos = NULL; + obj->i2c.tran_end = NULL; + i2c_enable_int(obj); + } + + return tran_len; +} + +static int i2c_do_trsn(i2c_t *obj, uint32_t i2c_ctl, int sync) +{ + I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c); + int err = 0; + + i2c_disable_int(obj); + + if (i2c_poll_status_timeout(obj, i2c_is_trsn_done, NU_I2C_TIMEOUT_STAT_INT)) { + err = I2C_ERROR_BUS_BUSY; + } else { + // NOTE: Avoid duplicate Start/Stop. Otherwise, we may meet strange error. + uint32_t status = I2C_GET_STATUS(i2c_base); + + switch (status) { + case 0x08: // Start + case 0x10: // Master Repeat Start + if (i2c_ctl & I2C_CTL0_STA_Msk) { + return 0; + } else { + break; + } + case 0xF8: // Bus Released + if ((i2c_ctl & (I2C_CTL0_STA_Msk | I2C_CTL0_STO_Msk)) == I2C_CTL0_STO_Msk) { + return 0; + } else { + break; + } + } + I2C_SET_CONTROL_REG(i2c_base, i2c_ctl); + if (sync && i2c_poll_status_timeout(obj, i2c_is_trsn_done, NU_I2C_TIMEOUT_STAT_INT)) { + err = I2C_ERROR_BUS_BUSY; + } + } + + i2c_enable_int(obj); + + return err; +} + +static int i2c_poll_status_timeout(i2c_t *obj, int (*is_status)(i2c_t *obj), uint32_t timeout) +{ + uint32_t t1, t2, elapsed = 0; + int status_assert = 0; + + t1 = us_ticker_read(); + while (1) { + status_assert = is_status(obj); + if (status_assert) { + break; + } + + t2 = us_ticker_read(); + elapsed = (t2 > t1) ? (t2 - t1) : ((uint64_t) t2 + 0xFFFFFFFF - t1 + 1); + if (elapsed >= timeout) { + break; + } + } + + return (elapsed >= timeout); +} + +static int i2c_poll_tran_heatbeat_timeout(i2c_t *obj, uint32_t timeout) +{ + uint32_t t1, t2, elapsed = 0; + int tran_started; + char *tran_pos = NULL; + char *tran_pos2 = NULL; + + i2c_disable_int(obj); + tran_pos = obj->i2c.tran_pos; + i2c_enable_int(obj); + t1 = us_ticker_read(); + while (1) { + i2c_disable_int(obj); + tran_started = i2c_is_tran_started(obj); + i2c_enable_int(obj); + if (! tran_started) { // Transfer completed or stopped + break; + } + + i2c_disable_int(obj); + tran_pos2 = obj->i2c.tran_pos; + i2c_enable_int(obj); + t2 = us_ticker_read(); + if (tran_pos2 != tran_pos) { // Transfer on-going + t1 = t2; + tran_pos = tran_pos2; + continue; + } + + elapsed = (t2 > t1) ? (t2 - t1) : ((uint64_t) t2 + 0xFFFFFFFF - t1 + 1); + if (elapsed >= timeout) { // Transfer idle + break; + } + } + + return (elapsed >= timeout); +} + +#if 0 +static int i2c_is_stat_int(i2c_t *obj) +{ + I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c); + + return !! (i2c_base->CTL0 & I2C_CTL0_SI_Msk); +} + +static int i2c_is_stop_det(i2c_t *obj) +{ + I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c); + + return ! (i2c_base->CTL0 & I2C_CTL0_STO_Msk); +} +#endif + +static int i2c_is_trsn_done(i2c_t *obj) +{ + I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c); + int i2c_int; + uint32_t status; + int inten_back; + + inten_back = i2c_set_int(obj, 0); + i2c_int = !! (i2c_base->CTL0 & I2C_CTL0_SI_Msk); + status = I2C_GET_STATUS(i2c_base); + i2c_set_int(obj, inten_back); + + return (i2c_int || status == 0xF8); +} + +static int i2c_is_tran_started(i2c_t *obj) +{ + int started; + int inten_back; + + inten_back = i2c_set_int(obj, 0); + started = !! (obj->i2c.tran_ctrl & TRANCTRL_STARTED); + i2c_set_int(obj, inten_back); + + return started; +} + +static int i2c_addr2data(int address, int read) +{ + return read ? (address | 1) : (address & 0xFE); +} + +static void i2c0_vec(void) +{ + i2c_irq(i2c0_var.obj); +} +static void i2c1_vec(void) +{ + i2c_irq(i2c1_var.obj); +} + +static void i2c_irq(i2c_t *obj) +{ + I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c); + uint32_t status; + + if (I2C_GET_TIMEOUT_FLAG(i2c_base)) { + I2C_ClearTimeoutFlag(i2c_base); + return; + } + + status = I2C_GET_STATUS(i2c_base); + + switch (status) { + // Master Transmit + case 0x28: // Master Transmit Data ACK + case 0x18: // Master Transmit Address ACK + case 0x08: // Start + case 0x10: // Master Repeat Start + if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) { + if (obj->i2c.tran_pos < obj->i2c.tran_end) { + I2C_SET_DATA(i2c_base, *obj->i2c.tran_pos ++); + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk); + } else { + i2c_fsm_tranfini(obj, 0); + } + } else { + i2c_disable_int(obj); + } + break; + + case 0x30: // Master Transmit Data NACK + i2c_fsm_tranfini(obj, 1); + break; + + case 0x20: // Master Transmit Address NACK + i2c_fsm_tranfini(obj, 1); + break; + + case 0x38: // Master Arbitration Lost + i2c_fsm_reset(obj, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk); + break; + + case 0x48: // Master Receive Address NACK + i2c_fsm_tranfini(obj, 1); + break; + + case 0x40: // Master Receive Address ACK + case 0x50: // Master Receive Data ACK + case 0x58: // Master Receive Data NACK + if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) { + if (obj->i2c.tran_pos < obj->i2c.tran_end) { + if (status == 0x50 || status == 0x58) { + *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base); + } + + if (status == 0x58) { + i2c_fsm_tranfini(obj, 1); + } else { + uint32_t i2c_ctl = I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk; + if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 && + obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) { + // Last data + i2c_ctl &= ~I2C_CTL0_AA_Msk; + } + I2C_SET_CONTROL_REG(i2c_base, i2c_ctl); + } + } else { + obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED; + i2c_disable_int(obj); + break; + } + } else { + i2c_disable_int(obj); + } + break; + + //case 0x00: // Bus error + + // Slave Transmit + case 0xB8: // Slave Transmit Data ACK + case 0xA8: // Slave Transmit Address ACK + case 0xB0: // Slave Transmit Arbitration Lost + if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) { + if (obj->i2c.tran_pos < obj->i2c.tran_end) { + uint32_t i2c_ctl = I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk; + + I2C_SET_DATA(i2c_base, *obj->i2c.tran_pos ++); + if (obj->i2c.tran_pos == obj->i2c.tran_end && + obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) { + // Last data + i2c_ctl &= ~I2C_CTL0_AA_Msk; + } + I2C_SET_CONTROL_REG(i2c_base, i2c_ctl); + } else { + obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED; + i2c_disable_int(obj); + break; + } + } else { + i2c_disable_int(obj); + } + obj->i2c.slaveaddr_state = ReadAddressed; + break; + //case 0xA0: // Slave Transmit Repeat Start or Stop + case 0xC0: // Slave Transmit Data NACK + case 0xC8: // Slave Transmit Last Data ACK + obj->i2c.slaveaddr_state = NoData; + i2c_fsm_reset(obj, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk); + break; + + // Slave Receive + case 0x80: // Slave Receive Data ACK + case 0x88: // Slave Receive Data NACK + case 0x60: // Slave Receive Address ACK + case 0x68: // Slave Receive Arbitration Lost + obj->i2c.slaveaddr_state = WriteAddressed; + if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) { + if (obj->i2c.tran_pos < obj->i2c.tran_end) { + if (status == 0x80 || status == 0x88) { + *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base); + } + + if (status == 0x88) { + obj->i2c.slaveaddr_state = NoData; + i2c_fsm_reset(obj, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk); + } else { + uint32_t i2c_ctl = I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk; + if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 && + obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) { + // Last data + i2c_ctl &= ~I2C_CTL0_AA_Msk; + } + I2C_SET_CONTROL_REG(i2c_base, i2c_ctl); + } + } else { + obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED; + i2c_disable_int(obj); + break; + } + } else { + i2c_disable_int(obj); + } + break; + //case 0xA0: // Slave Receive Repeat Start or Stop + + // GC mode + //case 0xA0: // GC mode Repeat Start or Stop + case 0x90: // GC mode Data ACK + case 0x98: // GC mode Data NACK + case 0x70: // GC mode Address ACK + case 0x78: // GC mode Arbitration Lost + obj->i2c.slaveaddr_state = WriteAddressed; + if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) { + if (obj->i2c.tran_pos < obj->i2c.tran_end) { + if (status == 0x90 || status == 0x98) { + *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base); + } + + if (status == 0x98) { + obj->i2c.slaveaddr_state = NoData; + i2c_fsm_reset(obj, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk); + } else { + uint32_t i2c_ctl = I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk; + if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 && + obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) { + // Last data + i2c_ctl &= ~I2C_CTL0_AA_Msk; + } + I2C_SET_CONTROL_REG(i2c_base, i2c_ctl); + } + } else { + obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED; + i2c_disable_int(obj); + break; + } + } else { + i2c_disable_int(obj); + } + break; + + case 0xF8: // Bus Released + break; + + default: + i2c_fsm_reset(obj, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk); + } +} + +static void i2c_fsm_reset(i2c_t *obj, uint32_t i2c_ctl) +{ + I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c); + + obj->i2c.stop = 0; + + obj->i2c.tran_ctrl = 0; + + I2C_SET_CONTROL_REG(i2c_base, i2c_ctl); + obj->i2c.slaveaddr_state = NoData; +} + +static void i2c_fsm_tranfini(i2c_t *obj, int lastdatanaked) +{ + if (lastdatanaked) { + obj->i2c.tran_ctrl |= TRANCTRL_LASTDATANAKED; + } + + obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED; + i2c_disable_int(obj); +} + +#if DEVICE_I2C_ASYNCH + +void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint) +{ + // NOTE: The mbed I2C address passed in is shifted left by 1 bit (7-bit addr << 1). + + // NOTE: First transmit and then receive. + + (void) hint; + obj->i2c.dma_usage = DMA_USAGE_NEVER; + obj->i2c.stop = stop; + obj->i2c.address = address; + obj->i2c.event = event; + i2c_buffer_set(obj, tx, tx_length, rx, rx_length); + + i2c_enable_vector_interrupt(obj, handler, 1); + i2c_start(obj); +} + +uint32_t i2c_irq_handler_asynch(i2c_t *obj) +{ + int event = 0; + + I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c); + uint32_t status = I2C_GET_STATUS(i2c_base); + switch (status) { + case 0x08: // Start + case 0x10: {// Master Repeat Start + if (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) { + I2C_SET_DATA(i2c_base, (i2c_addr2data(obj->i2c.address, 0))); + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk); + } else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) { + I2C_SET_DATA(i2c_base, (i2c_addr2data(obj->i2c.address, 1))); + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk); + } else { + event = I2C_EVENT_TRANSFER_COMPLETE; + if (obj->i2c.stop) { + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk); + } + } + break; + } + + case 0x18: // Master Transmit Address ACK + case 0x28: // Master Transmit Data ACK + if (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) { + uint8_t *tx = (uint8_t *)obj->tx_buff.buffer; + I2C_SET_DATA(i2c_base, tx[obj->tx_buff.pos ++]); + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk); + } else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) { + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STA_Msk | I2C_CTL0_SI_Msk); + } else { + event = I2C_EVENT_TRANSFER_COMPLETE; + if (obj->i2c.stop) { + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk); + } + } + break; + + case 0x20: // Master Transmit Address NACK + event = I2C_EVENT_ERROR_NO_SLAVE; + if (obj->i2c.stop) { + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk); + } + break; + + case 0x30: // Master Transmit Data NACK + if (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) { + event = I2C_EVENT_TRANSFER_EARLY_NACK; + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk); + } else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) { + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STA_Msk | I2C_CTL0_SI_Msk); + } else { + event = I2C_EVENT_TRANSFER_COMPLETE; + if (obj->i2c.stop) { + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk); + } + } + break; + + case 0x38: // Master Arbitration Lost + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk); // Enter not addressed SLV mode + event = I2C_EVENT_ERROR; + break; + + case 0x50: // Master Receive Data ACK + if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) { + uint8_t *rx = (uint8_t *) obj->rx_buff.buffer; + rx[obj->rx_buff.pos ++] = I2C_GET_DATA(((I2C_T *) NU_MODBASE(obj->i2c.i2c))); + } + case 0x40: // Master Receive Address ACK + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk | ((obj->rx_buff.pos != obj->rx_buff.length - 1) ? I2C_CTL0_AA_Msk : 0)); + break; + + case 0x48: // Master Receive Address NACK + event = I2C_EVENT_ERROR_NO_SLAVE; + if (obj->i2c.stop) { + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk); + } + break; + + case 0x58: // Master Receive Data NACK + if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) { + uint8_t *rx = (uint8_t *) obj->rx_buff.buffer; + rx[obj->rx_buff.pos ++] = I2C_GET_DATA(((I2C_T *) NU_MODBASE(obj->i2c.i2c))); + } + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STA_Msk | I2C_CTL0_SI_Msk); + break; + + case 0x00: // Bus error + event = I2C_EVENT_ERROR; + i2c_reset(obj); + break; + + default: + event = I2C_EVENT_ERROR; + if (obj->i2c.stop) { + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk); + } + } + + if (event) { + i2c_rollback_vector_interrupt(obj); + } + + return (event & obj->i2c.event); +} + +uint8_t i2c_active(i2c_t *obj) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->i2c.i2c); + + // Vector will be changed for async transfer. Use it to judge if async transfer is on-going. + uint32_t vec = NVIC_GetVector(modinit->irq_n); + struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var; + return (vec && vec != (uint32_t) var->vec); +} + +void i2c_abort_asynch(i2c_t *obj) +{ + i2c_rollback_vector_interrupt(obj); + i2c_stop(obj); +} + +static void i2c_buffer_set(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length) +{ + obj->tx_buff.buffer = (void *) tx; + obj->tx_buff.length = tx_length; + obj->tx_buff.pos = 0; + obj->rx_buff.buffer = rx; + obj->rx_buff.length = rx_length; + obj->rx_buff.pos = 0; +} + +static void i2c_enable_vector_interrupt(i2c_t *obj, uint32_t handler, int enable) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->i2c.i2c); + + if (enable) { + NVIC_SetVector(modinit->irq_n, handler); + i2c_enable_int(obj); + } else { + i2c_disable_int(obj); + } + +} + +static void i2c_rollback_vector_interrupt(i2c_t *obj) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->i2c.i2c); + + struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var; + i2c_enable_vector_interrupt(obj, (uint32_t) var->vec, 1); +} + +#endif + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M251/lp_ticker.c b/targets/TARGET_NUVOTON/TARGET_M251/lp_ticker.c new file mode 100644 index 00000000000..ffa7fb40375 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/lp_ticker.c @@ -0,0 +1,224 @@ +/* + * Copyright (c) 2019, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "lp_ticker_api.h" + +#if DEVICE_LPTICKER + +#include "sleep_api.h" +#include "mbed_assert.h" +#include "nu_modutil.h" +#include "nu_timer.h" +#include "nu_miscutil.h" + +/* Micro seconds per second */ +#define NU_US_PER_SEC 1000000 +/* Timer clock per lp_ticker tick */ +#define NU_TMRCLK_PER_TICK 1 +/* Timer clock per second */ +#define NU_TMRCLK_PER_SEC (__LXT) +/* Timer max counter bit size */ +#define NU_TMR_MAXCNT_BITSIZE 24 +/* Timer max counter */ +#define NU_TMR_MAXCNT ((1 << NU_TMR_MAXCNT_BITSIZE) - 1) + +static void tmr1_vec(void); + +/* NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC. */ +static const struct nu_modinit_s timer1_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_LXT, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec}; + +#define TIMER_MODINIT timer1_modinit + +/* Timer interrupt enable/disable + * + * Because Timer interrupt enable/disable (TIMER_EnableInt/TIMER_DisableInt) needs wait for lp_ticker, + * we call NVIC_DisableIRQ/NVIC_EnableIRQ instead. + */ + +/* Track ticker status */ +static volatile uint16_t ticker_inited = 0; + +#define TMR_CMP_MIN 2 +#define TMR_CMP_MAX 0xFFFFFFu + +/* Synchronization issue with LXT/LIRC-clocked Timer + * + * PCLK : typical HCLK/2 + * ECLK (engine clock) : LXT/LIRC for Timer used to implement lp_ticker + * + * When system clock is higher than Timer clock (LXT/LIRC), we need to add delay for ECLK + * domain to take effect: + * 1. Write : typical 1PCLK + 2ECLK + * Read-check doesn't work because it just checks PCLK domain and doesn't check into + * ECLK domain. + * 2. Clear interrupt flag : typical 2PCLK + * It is very rare that we would meet dummy interrupt and get stuck in ISR until + * 'clear interrupt flag' takes effect. The issue is ignorable because the pending + * time is very short (at most 1 dummy interrupt). We won't take special handling for it. + */ + +void lp_ticker_init(void) +{ + if (ticker_inited) { + /* By HAL spec, ticker_init allows the ticker to keep counting and disables the + * ticker interrupt. */ + lp_ticker_disable_interrupt(); + return; + } + ticker_inited = 1; + + // Reset module + SYS_ResetModule(TIMER_MODINIT.rsetidx); + + // Select IP clock source + CLK_SetModuleClock(TIMER_MODINIT.clkidx, TIMER_MODINIT.clksrc, TIMER_MODINIT.clkdiv); + + // Enable IP clock + CLK_EnableModuleClock(TIMER_MODINIT.clkidx); + + TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); + + // Configure clock + uint32_t clk_timer = TIMER_GetModuleClock(timer_base); + uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1; + MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127); + MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0); + uint32_t cmp_timer = TMR_CMP_MAX; + MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX); + // Continuous mode + // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480/M2351/M251. In M451/M480/M2351/M251, TIMER_CNT is updated continuously by default. + timer_base->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/; + nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3); + + timer_base->CMP = cmp_timer; + nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3); + + // Set vector + NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var); + + NVIC_DisableIRQ(TIMER_MODINIT.irq_n); + + TIMER_EnableInt(timer_base); + nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3); + + TIMER_EnableWakeup(timer_base); + nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3); + + TIMER_Start(timer_base); + nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3); + + /* Wait for timer to start counting and raise active flag */ + while(! (timer_base->CTL & TIMER_CTL_ACTSTS_Msk)); +} + +void lp_ticker_free(void) +{ + /* Disable interrupt */ + NVIC_DisableIRQ(TIMER_MODINIT.irq_n); + + /* Disable IP clock */ + CLK_DisableModuleClock(TIMER_MODINIT.clkidx); + + ticker_inited = 0; +} + +timestamp_t lp_ticker_read() +{ + if (! ticker_inited) { + lp_ticker_init(); + } + + TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); + + return (TIMER_GetCounter(timer_base) / NU_TMRCLK_PER_TICK); +} + +void lp_ticker_set_interrupt(timestamp_t timestamp) +{ + /* Clear any previously pending interrupts */ + lp_ticker_clear_interrupt(); + NVIC_ClearPendingIRQ(TIMER_MODINIT.irq_n); + + /* In continuous mode, counter will be reset to zero with the following sequence: + * 1. Stop counting + * 2. Configure new CMP value + * 3. Restart counting + * + * This behavior is not what we want. To fix it, we could configure new CMP value + * without stopping counting first. + */ + TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); + + /* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of + * (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */ + uint32_t cmp_timer = timestamp * NU_TMRCLK_PER_TICK; + cmp_timer = NU_CLAMP(cmp_timer, TMR_CMP_MIN, TMR_CMP_MAX); + + /* NOTE: Rely on LPTICKER_DELAY_TICKS to be non-blocking. */ + timer_base->CMP = cmp_timer; + + /* We can call ticker_irq_handler now. */ + NVIC_EnableIRQ(TIMER_MODINIT.irq_n); +} + +void lp_ticker_disable_interrupt(void) +{ + /* We cannot call ticker_irq_handler now. */ + NVIC_DisableIRQ(TIMER_MODINIT.irq_n); +} + +void lp_ticker_clear_interrupt(void) +{ + /* To avoid sync issue, we clear TIF/TWKF simultaneously rather than call separate + * driver API: + * + * TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); + * TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); + */ + TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); + timer_base->INTSTS = TIMER_INTSTS_TIF_Msk | TIMER_INTSTS_TWKF_Msk; +} + +void lp_ticker_fire_interrupt(void) +{ + // NOTE: This event was in the past. Set the interrupt as pending, but don't process it here. + // This prevents a recursive loop under heavy load which can lead to a stack overflow. + NVIC_SetPendingIRQ(TIMER_MODINIT.irq_n); + + /* We can call ticker_irq_handler now. */ + NVIC_EnableIRQ(TIMER_MODINIT.irq_n); +} + +const ticker_info_t* lp_ticker_get_info() +{ + static const ticker_info_t info = { + NU_TMRCLK_PER_SEC / NU_TMRCLK_PER_TICK, + NU_TMR_MAXCNT_BITSIZE + }; + return &info; +} + +static void tmr1_vec(void) +{ + lp_ticker_clear_interrupt(); + + // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler(); + lp_ticker_irq_handler(); +} + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M251/mbed_overrides.c b/targets/TARGET_NUVOTON/TARGET_M251/mbed_overrides.c new file mode 100644 index 00000000000..b7a0af10026 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/mbed_overrides.c @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2019, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "analogin_api.h" + +void mbed_sdk_init(void) +{ + // NOTE: Support singleton semantics to be called from other init functions + static int inited = 0; + if (inited) { + return; + } + inited = 1; + + /*---------------------------------------------------------------------------------------------------------*/ + /* Init System Clock */ + /*---------------------------------------------------------------------------------------------------------*/ + /* Unlock protected registers */ + SYS_UnlockReg(); + +#if defined(NU_HXT_ENABLE) && (NU_HXT_ENABLE == 1UL) + /* HXT Enable: Set XT1_OUT(PF.2) and XT1_IN(PF.3) to input mode */ + PF->MODE &= ~(GPIO_MODE_MODE2_Msk | GPIO_MODE_MODE3_Msk); +#endif + + /* LXT Enable: Set X32_OUT(PF.4) and X32_IN(PF.5) to input mode */ + PF->MODE &= ~(GPIO_MODE_MODE4_Msk | GPIO_MODE_MODE5_Msk); + + /* Enable HIRC clock (Internal RC 48MHz) */ + CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk); +#if defined(NU_HXT_ENABLE) && (NU_HXT_ENABLE == 1UL) + /* Enable HXT clock (external XTAL 12MHz) */ + CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk); +#endif + /* Enable LIRC for lp_ticker */ + CLK_EnableXtalRC(CLK_PWRCTL_LIRCEN_Msk); + /* Enable LXT for RTC */ + CLK_EnableXtalRC(CLK_PWRCTL_LXTEN_Msk); + + /* Wait for HIRC clock ready */ + CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); +#if defined(NU_HXT_ENABLE) && (NU_HXT_ENABLE == 1UL) + /* Wait for HXT clock ready */ + CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk); +#endif + /* Wait for LIRC clock ready */ + CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk); + /* Wait for LXT clock ready */ + CLK_WaitClockReady(CLK_STATUS_LXTSTB_Msk); + +#if defined(NU_HXT_ENABLE) && (NU_HXT_ENABLE == 1UL) + /* HXT Enable: Disable digital input path of analog pin XT1_OUT to prevent leakage */ + GPIO_DISABLE_DIGITAL_PATH(PF, (1ul << 2)); + /* HXT Enable: Disable digital input path of analog pin XT1_IN to prevent leakage */ + GPIO_DISABLE_DIGITAL_PATH(PF, (1ul << 3)); +#endif + + /* LXT Enable: Disable digital input path of analog pin X32_OUT to prevent leakage */ + GPIO_DISABLE_DIGITAL_PATH(PF, (1ul << 4)); + /* LXT Enable: Disable digital input path of analog pin XT32_IN to prevent leakage */ + GPIO_DISABLE_DIGITAL_PATH(PF, (1ul << 5)); + + /* Select HCLK clock source as HIRC and HCLK clock divider as 1 */ + CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1)); + + /* Set both PCLK0 and PCLK1 as HCLK/2 */ + CLK->PCLKDIV = CLK_PCLKDIV_APB0DIV_DIV2 | CLK_PCLKDIV_APB1DIV_DIV2; + + /* Update System Core Clock */ + /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */ + SystemCoreClockUpdate(); + + /* Lock protected registers */ + SYS_LockReg(); +} diff --git a/targets/TARGET_NUVOTON/TARGET_M251/objects.h b/targets/TARGET_NUVOTON/TARGET_M251/objects.h new file mode 100644 index 00000000000..50c0b95a8bc --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/objects.h @@ -0,0 +1,130 @@ +/* + * Copyright (c) 2019, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" +#include "dma_api.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct gpio_irq_s { + PinName pin; + uint32_t irq_handler; + uint32_t irq_id; + struct gpio_irq_s *next; +}; + +struct port_s { + PortName port; + uint32_t mask; + PinDirection direction; +}; + +struct analogin_s { + ADCName adc; +}; + +struct dac_s { + DACName dac; +}; + +struct serial_s { + UARTName uart; + + uint32_t baudrate; + uint32_t databits; + uint32_t parity; + uint32_t stopbits; + + void (*vec)(void); + uint32_t irq_handler; + uint32_t irq_id; + uint32_t irq_en; + uint32_t inten_msk; + + // Async transfer related fields + DMAUsage dma_usage_tx; + DMAUsage dma_usage_rx; + int dma_chn_id_tx; + int dma_chn_id_rx; + uint32_t event; + void (*irq_handler_tx_async)(void); + void (*irq_handler_rx_async)(void); +}; + +struct spi_s { + SPIName spi; + PinName pin_miso; + PinName pin_mosi; + PinName pin_sclk; + PinName pin_ssel; + + // Async transfer related fields + DMAUsage dma_usage; + int dma_chn_id_tx; + int dma_chn_id_rx; + uint32_t event; + uint32_t hdlr_async; +}; + +struct i2c_s { + I2CName i2c; + int slaveaddr_state; + + uint32_t tran_ctrl; + char * tran_beg; + char * tran_pos; + char * tran_end; + int inten; + + // Async transfer related fields + DMAUsage dma_usage; + uint32_t event; + int stop; + uint32_t address; + uint32_t hdlr_async; +}; + +struct pwmout_s { + PWMName pwm; + uint32_t period_us; + uint32_t pulsewidth_us; +}; + +struct sleep_s { + int powerdown; +}; + +struct trng_s { + uint8_t dummy; +}; + +#ifdef __cplusplus +} +#endif + +#include "gpio_object.h" + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M251/pinmap.c b/targets/TARGET_NUVOTON/TARGET_M251/pinmap.c new file mode 100644 index 00000000000..b058fa5d7f2 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/pinmap.c @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2019, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed_assert.h" +#include "pinmap.h" +#include "PortNames.h" +#include "mbed_error.h" + +/** + * Configure pin multi-function + */ +void pin_function(PinName pin, int data) +{ + MBED_ASSERT(pin != (PinName)NC); + uint32_t pin_index = NU_PININDEX(pin); + uint32_t port_index = NU_PINPORT(pin); + __IO uint32_t *GPx_MFPx = ((__IO uint32_t *) &SYS->GPA_MFPL) + port_index * 2 + (pin_index / 8); + uint32_t MFP_Msk = NU_MFP_MSK(pin_index); + + // E.g.: SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA0MFP_Msk) ) | SYS_GPA_MFPL_PA0MFP_SC0_CD ; + *GPx_MFPx = (*GPx_MFPx & (~MFP_Msk)) | data; +} + +/** + * Configure pin pull-up/pull-down + */ +void pin_mode(PinName pin, PinMode mode) +{ + MBED_ASSERT(pin != (PinName)NC); + uint32_t pin_index = NU_PININDEX(pin); + uint32_t port_index = NU_PINPORT(pin); + GPIO_T *gpio_base = NU_PORT_BASE(port_index); + + uint32_t mode_intern = GPIO_MODE_INPUT; + + switch (mode) { + case InputOnly: + mode_intern = GPIO_MODE_INPUT; + break; + + case PushPullOutput: + mode_intern = GPIO_MODE_OUTPUT; + break; + + case OpenDrain: + mode_intern = GPIO_MODE_OPEN_DRAIN; + break; + + case QuasiBidirectional: + mode_intern = GPIO_MODE_QUASI; + break; + + default: + /* H/W doesn't support separate configuration for input pull mode/direction. + * We expect upper layer would have translated input pull mode/direction + * to I/O mode */ + return; + } + + GPIO_SetMode(gpio_base, 1 << pin_index, mode_intern); + + /* Invalid combinations of PinMode/PinDirection + * + * We assume developer would avoid the following combinations of PinMode/PinDirection + * which are invalid: + * 1. InputOnly/PIN_OUTPUT + * 2. PushPullOutput/PIN_INPUT + */ +} diff --git a/targets/TARGET_NUVOTON/TARGET_M251/port_api.c b/targets/TARGET_NUVOTON/TARGET_M251/port_api.c new file mode 100644 index 00000000000..851289236fc --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/port_api.c @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2019, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "port_api.h" +#include "gpio_api.h" +#include "pinmap.h" +#include "mbed_error.h" + +#if DEVICE_PORTIN || DEVICE_PORTOUT || DEVICE_PORTINOUT + +PinName port_pin(PortName port, int pin_n) +{ + return (PinName) NU_PINNAME(port, pin_n); +} + +void port_init(port_t *obj, PortName port, int mask, PinDirection dir) +{ + obj->port = port; + obj->mask = mask; + obj->direction = dir; + + uint32_t i; + obj->direction = dir; + for (i = 0; i < GPIO_PIN_MAX; i++) { + if (obj->mask & (1 << i)) { + gpio_set(port_pin(port, i)); + } + } + + port_dir(obj, dir); +} + +void port_dir(port_t *obj, PinDirection dir) +{ + uint32_t i; + obj->direction = dir; + for (i = 0; i < GPIO_PIN_MAX; i++) { + if (obj->mask & (1 << i)) { + if (dir == PIN_OUTPUT) { + GPIO_SetMode(NU_PORT_BASE(obj->port), 1 << i, GPIO_MODE_OUTPUT); + } else { // PIN_INPUT + GPIO_SetMode(NU_PORT_BASE(obj->port), 1 << i, GPIO_MODE_INPUT); + } + } + } +} + +void port_mode(port_t *obj, PinMode mode) +{ + uint32_t i; + + for (i = 0; i < GPIO_PIN_MAX; i++) { + if (obj->mask & (1 << i)) { + pin_mode(port_pin(obj->port, i), mode); + } + } +} + +void port_write(port_t *obj, int value) +{ + uint32_t i; + uint32_t port_index = obj->port; + + for (i = 0; i < GPIO_PIN_MAX; i++) { + if (obj->mask & (1 << i)) { + GPIO_PIN_DATA(port_index, i) = (value & obj->mask) ? 1 : 0; + } + } +} + +int port_read(port_t *obj) +{ + uint32_t i; + uint32_t port_index = obj->port; + int value = 0; + + for (i = 0; i < GPIO_PIN_MAX; i++) { + if (obj->mask & (1 << i)) { + value = value | (GPIO_PIN_DATA(port_index, i) << i); + } + } + + return value; +} + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M251/pwmout_api.c b/targets/TARGET_NUVOTON/TARGET_M251/pwmout_api.c new file mode 100644 index 00000000000..da09a7ff3be --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/pwmout_api.c @@ -0,0 +1,201 @@ +/* + * Copyright (c) 2019, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "pwmout_api.h" + +#if DEVICE_PWMOUT + +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralPins.h" +#include "nu_modutil.h" +#include "nu_miscutil.h" +#include "nu_bitutil.h" + +struct nu_pwm_var { + uint32_t en_msk; +}; + +static struct nu_pwm_var pwm0_var = { + .en_msk = 0 +}; + +static struct nu_pwm_var pwm1_var = { + .en_msk = 0 +}; + +static uint32_t pwm_modinit_mask = 0; + +static const struct nu_modinit_s pwm_modinit_tab[] = { + {PWM_0_0, PWM0_MODULE, CLK_CLKSEL2_PWM0SEL_PCLK0, 0, PWM0_RST, PWM0_P0_IRQn, &pwm0_var}, + {PWM_0_1, PWM0_MODULE, CLK_CLKSEL2_PWM0SEL_PCLK0, 0, PWM0_RST, PWM0_P0_IRQn, &pwm0_var}, + {PWM_0_2, PWM0_MODULE, CLK_CLKSEL2_PWM0SEL_PCLK0, 0, PWM0_RST, PWM0_P1_IRQn, &pwm0_var}, + {PWM_0_3, PWM0_MODULE, CLK_CLKSEL2_PWM0SEL_PCLK0, 0, PWM0_RST, PWM0_P1_IRQn, &pwm0_var}, + {PWM_0_4, PWM0_MODULE, CLK_CLKSEL2_PWM0SEL_PCLK0, 0, PWM0_RST, PWM0_P2_IRQn, &pwm0_var}, + {PWM_0_5, PWM0_MODULE, CLK_CLKSEL2_PWM0SEL_PCLK0, 0, PWM0_RST, PWM0_P2_IRQn, &pwm0_var}, + + {PWM_1_0, PWM1_MODULE, CLK_CLKSEL2_PWM1SEL_PCLK1, 0, PWM1_RST, PWM1_P0_IRQn, &pwm1_var}, + {PWM_1_1, PWM1_MODULE, CLK_CLKSEL2_PWM1SEL_PCLK1, 0, PWM1_RST, PWM1_P0_IRQn, &pwm1_var}, + {PWM_1_2, PWM1_MODULE, CLK_CLKSEL2_PWM1SEL_PCLK1, 0, PWM1_RST, PWM1_P1_IRQn, &pwm1_var}, + {PWM_1_3, PWM1_MODULE, CLK_CLKSEL2_PWM1SEL_PCLK1, 0, PWM1_RST, PWM1_P1_IRQn, &pwm1_var}, + {PWM_1_4, PWM1_MODULE, CLK_CLKSEL2_PWM1SEL_PCLK1, 0, PWM1_RST, PWM1_P2_IRQn, &pwm1_var}, + {PWM_1_5, PWM1_MODULE, CLK_CLKSEL2_PWM1SEL_PCLK1, 0, PWM1_RST, PWM1_P2_IRQn, &pwm1_var}, + + {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL} +}; + +static void pwmout_config(pwmout_t* obj, int start); + +void pwmout_init(pwmout_t* obj, PinName pin) +{ + obj->pwm = (PWMName) pinmap_peripheral(pin, PinMap_PWM); + MBED_ASSERT((int) obj->pwm != NC); + + const struct nu_modinit_s *modinit = get_modinit(obj->pwm, pwm_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->pwm); + + // NOTE: All channels (identified by PWMName) share a PWM module. This reset will also affect other channels of the same PWM module. + if (! ((struct nu_pwm_var *) modinit->var)->en_msk) { + // Reset this module if no channel enabled + SYS_ResetModule(modinit->rsetidx); + } + + uint32_t chn = NU_MODSUBINDEX(obj->pwm); + + // NOTE: Channels 0/1/2/3/4/5 share a clock source. + if ((((struct nu_pwm_var *) modinit->var)->en_msk & 0x3F) == 0) { + // Select clock source of paired channels + CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv); + // Enable clock of paired channels + CLK_EnableModuleClock(modinit->clkidx); + } + + // Wire pinout + pinmap_pinout(pin, PinMap_PWM); + + // Default: period = 10 ms, pulse width = 0 ms + obj->period_us = 1000 * 10; + obj->pulsewidth_us = 0; + pwmout_config(obj, 0); + + ((struct nu_pwm_var *) modinit->var)->en_msk |= 1 << chn; + + // Mark this module to be inited. + int i = modinit - pwm_modinit_tab; + pwm_modinit_mask |= 1 << i; +} + +void pwmout_free(pwmout_t* obj) +{ + PWM_T *pwm_base = (PWM_T *) NU_MODBASE(obj->pwm); + uint32_t chn = NU_MODSUBINDEX(obj->pwm); + PWM_ForceStop(pwm_base, 1 << chn); + + const struct nu_modinit_s *modinit = get_modinit(obj->pwm, pwm_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->pwm); + ((struct nu_pwm_var *) modinit->var)->en_msk &= ~(1 << chn); + + + if ((((struct nu_pwm_var *) modinit->var)->en_msk & 0x3F) == 0) { + CLK_DisableModuleClock(modinit->clkidx); + } + + // Mark this module to be deinited. + int i = modinit - pwm_modinit_tab; + pwm_modinit_mask &= ~(1 << i); +} + +void pwmout_write(pwmout_t* obj, float value) +{ + obj->pulsewidth_us = NU_CLAMP((uint32_t) (value * obj->period_us), 0, obj->period_us); + pwmout_config(obj, 1); +} + +float pwmout_read(pwmout_t* obj) +{ + return NU_CLAMP((((float) obj->pulsewidth_us) / obj->period_us), 0.0f, 1.0f); +} + +void pwmout_period(pwmout_t* obj, float seconds) +{ + pwmout_period_us(obj, seconds * 1000000.0f); +} + +void pwmout_period_ms(pwmout_t* obj, int ms) +{ + pwmout_period_us(obj, ms * 1000); +} + +// Set the PWM period, keeping the duty cycle the same. +void pwmout_period_us(pwmout_t* obj, int us) +{ + uint32_t period_us_old = obj->period_us; + uint32_t pulsewidth_us_old = obj->pulsewidth_us; + obj->period_us = us; + obj->pulsewidth_us = NU_CLAMP(obj->period_us * pulsewidth_us_old / period_us_old, 0, obj->period_us); + pwmout_config(obj, 1); +} + +void pwmout_pulsewidth(pwmout_t* obj, float seconds) +{ + pwmout_pulsewidth_us(obj, seconds * 1000000.0f); +} + +void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) +{ + pwmout_pulsewidth_us(obj, ms * 1000); +} + +void pwmout_pulsewidth_us(pwmout_t* obj, int us) +{ + obj->pulsewidth_us = NU_CLAMP(us, 0, obj->period_us); + pwmout_config(obj, 1); +} + +static void pwmout_config(pwmout_t* obj, int start) +{ + PWM_T *pwm_base = (PWM_T *) NU_MODBASE(obj->pwm); + uint32_t chn = NU_MODSUBINDEX(obj->pwm); + + // To avoid abnormal pulse on (re-)configuration, follow the sequence: stop/configure(/re-start). + // NOTE: The issue is met in ARM mbed CI test tests-api-pwm on M487. + PWM_ForceStop(pwm_base, 1 << chn); + + // NOTE: Support period < 1s + // NOTE: ARM mbed CI test fails due to first PWM pulse error. Workaround by: + // 1. Inverse duty cycle (100 - duty) + // 2. Inverse PWM output polarity + // This trick is here to pass ARM mbed CI test. First PWM pulse error still remains. + PWM_ConfigOutputChannel2(pwm_base, chn, 1000 * 1000, 100 - obj->pulsewidth_us * 100 / obj->period_us, obj->period_us); + pwm_base->POLCTL |= 1 << (PWM_POLCTL_PINV0_Pos + chn); + + if (start) { + // Enable output of the specified PWM channel + PWM_EnableOutput(pwm_base, 1 << chn); + PWM_Start(pwm_base, 1 << chn); + } +} + +const PinMap *pwmout_pinmap() +{ + return PinMap_PWM; +} + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M251/rtc_api.c b/targets/TARGET_NUVOTON/TARGET_M251/rtc_api.c new file mode 100644 index 00000000000..fb9c8030d5f --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/rtc_api.c @@ -0,0 +1,215 @@ +/* + * Copyright (c) 2019, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "rtc_api.h" + +#if DEVICE_RTC + +#include "mbed_wait_api.h" +#include "mbed_error.h" +#include "nu_modutil.h" +#include "nu_miscutil.h" +#include "mbed_mktime.h" + +/* Micro seconds per second */ +#define NU_US_PER_SEC 1000000 +/* Timer clock per second + * + * NOTE: This dependents on real hardware. + */ +#define NU_RTCCLK_PER_SEC __LXT + +/* Strategy for implementation of RTC HAL + * + * H/W RTC just supports year range 2000~2099, which cannot fully cover POSIX time (starting since 2970) + * and date time of struct TM (starting since 1900). + * + * To conquer the difficulty, we don't use H/W RTC to keep real date time. Instead, we use it to keep + * elapsed time in seconds since one reference time point. The strategy would be: + * + * 1. Choose DATETIME_HWRTC_ORIGIN (00:00:00 UTC, Saturday, 1 January 2000) as reference time point of H/W RTC. + * 2. t_hwrtc_origin = DATETIME_HWRTC_ORIGIN in POSIX time + * 3. t_hwrtc_elapsed = t_hwrtc_origin + elapsed time since t_hwrtc_origin + * 4. t_write = POSIX time set by rtc_write(). + * 5. t_present = rtc_read() = t_write + (t_hwrtc_elapsed - t_hwrtc_origin) + * + * 1900 + * |---------------------------------------------------------------------------------| + * 1970 t_write t_present + * |---------|-------|-----------------|---------------------------------------------| + * + * 2000 + * |-----------------|---------------------------------------------------------------| + * t_hwrtc_origin t_hwrtc_elapsed + * + */ +/* Start year of struct TM*/ +#define NU_TM_YEAR0 1900 +/* Start year of POSIX time (set_time()/time()) */ +#define NU_POSIX_YEAR0 1970 +/* Start year of H/W RTC */ +#define NU_HWRTC_YEAR0 2000 + +/* RTC H/W origin time: 00:00:00 UTC, Saturday, 1 January 2000 */ +static const S_RTC_TIME_DATA_T DATETIME_HWRTC_ORIGIN = { + 2000, /* Year value, range between 2000 ~ 2099 */ + 1, /* Month value, range between 1 ~ 12 */ + 1, /* Day value, range between 1 ~ 31 */ + RTC_SATURDAY, /* Day of the week */ + 0, /* Hour value, range between 0 ~ 23 */ + 0, /* Minute value, range between 0 ~ 59 */ + 0, /* Second value, range between 0 ~ 59 */ + RTC_CLOCK_24, /* 12-Hour (RTC_CLOCK_12) / 24-Hour (RTC_CLOCK_24) */ + 0 /* RTC_AM / RTC_PM (used only for 12-Hour) */ +}; +/* t_hwrtc_origin initialized or not? */ +static bool t_hwrtc_origin_inited = 0; +/* POSIX time of DATETIME_HWRTC_ORIGIN (since 00:00:00 UTC, Thursday, 1 January 1970) */ +static time_t t_hwrtc_origin = 0; +/* POSIX time set by rtc_write() */ +static time_t t_write = 0; +/* Convert date time from H/W RTC to struct TM */ +static void rtc_convert_datetime_hwrtc_to_tm(struct tm *datetime_tm, const S_RTC_TIME_DATA_T *datetime_hwrtc); + +static const struct nu_modinit_s rtc_modinit = {RTC_0, RTC_MODULE, 0, 0, 0, RTC_IRQn, NULL}; + +void rtc_init(void) +{ + if (rtc_isenabled()) { + return; + } + + RTC_Open(NULL); + + /* POSIX time origin (00:00:00 UTC, Thursday, 1 January 1970) */ + rtc_write(0); +} + +void rtc_free(void) +{ + CLK_DisableModuleClock(rtc_modinit.clkidx); +} + +int rtc_isenabled(void) +{ + // NOTE: To access (RTC) registers, clock must be enabled first. + if (! (CLK->APBCLK0 & CLK_APBCLK0_RTCCKEN_Msk)) { + // Enable IP clock + CLK_EnableModuleClock(rtc_modinit.clkidx); + } + + RTC_T *rtc_base = (RTC_T *) NU_MODBASE(rtc_modinit.modname); + + // NOTE: Check RTC Init Active flag to support crossing reset cycle. + return !! (rtc_base->INIT & RTC_INIT_ACTIVE_Msk); +} + +time_t rtc_read(void) +{ + /* NOTE: After boot, RTC time registers are not synced immediately, about 1 sec latency. + * RTC time got (through RTC_GetDateAndTime()) in this sec would be last-synced and incorrect. + * NUC472/M453: Known issue + * M487: Fixed + */ + if (! rtc_isenabled()) { + rtc_init(); + } + + /* Used for intermediary between date time of H/W RTC and POSIX time */ + struct tm datetime_tm; + + if (! t_hwrtc_origin_inited) { + t_hwrtc_origin_inited = 1; + + /* Convert date time from H/W RTC to struct TM */ + rtc_convert_datetime_hwrtc_to_tm(&datetime_tm, &DATETIME_HWRTC_ORIGIN); + /* Convert date time of struct TM to POSIX time */ + if (! _rtc_maketime(&datetime_tm, &t_hwrtc_origin, RTC_FULL_LEAP_YEAR_SUPPORT)) { + return 0; + } + + /* Load t_write from RTC spare register to cross reset cycle */ + RTC_WaitAccessEnable(); + RTC_EnableSpareAccess(); + RTC_WaitAccessEnable(); + t_write = RTC_READ_SPARE_REGISTER(0); + } + + S_RTC_TIME_DATA_T hwrtc_datetime_2K_present; + RTC_WaitAccessEnable(); + RTC_GetDateAndTime(&hwrtc_datetime_2K_present); + /* Convert date time from H/W RTC to struct TM */ + rtc_convert_datetime_hwrtc_to_tm(&datetime_tm, &hwrtc_datetime_2K_present); + /* Convert date time of struct TM to POSIX time */ + time_t t_hwrtc_elapsed; + if (! _rtc_maketime(&datetime_tm, &t_hwrtc_elapsed, RTC_FULL_LEAP_YEAR_SUPPORT)) { + return 0; + } + + /* Present time in POSIX time */ + time_t t_present = t_write + (t_hwrtc_elapsed - t_hwrtc_origin); + return t_present; +} + +void rtc_write(time_t t) +{ + if (! rtc_isenabled()) { + rtc_init(); + } + + t_write = t; + + /* Store t_write to RTC spare register to cross reset cycle */ + RTC_WaitAccessEnable(); + RTC_EnableSpareAccess(); + RTC_WaitAccessEnable(); + RTC_WRITE_SPARE_REGISTER(0, t_write); + + RTC_WaitAccessEnable(); + RTC_SetDateAndTime((S_RTC_TIME_DATA_T *) &DATETIME_HWRTC_ORIGIN); + /* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */ + wait_us((NU_US_PER_SEC / NU_RTCCLK_PER_SEC) * 3); +} + +/* + struct tm + tm_sec seconds after the minute 0-61 + tm_min minutes after the hour 0-59 + tm_hour hours since midnight 0-23 + tm_mday day of the month 1-31 + tm_mon months since January 0-11 + tm_year years since 1900 + tm_wday days since Sunday 0-6 + tm_yday days since January 1 0-365 + tm_isdst Daylight Saving Time flag +*/ +static void rtc_convert_datetime_hwrtc_to_tm(struct tm *datetime_tm, const S_RTC_TIME_DATA_T *datetime_hwrtc) +{ + datetime_tm->tm_year = datetime_hwrtc->u32Year - NU_TM_YEAR0; + datetime_tm->tm_mon = datetime_hwrtc->u32Month - 1; + datetime_tm->tm_mday = datetime_hwrtc->u32Day; + datetime_tm->tm_wday = datetime_hwrtc->u32DayOfWeek; + datetime_tm->tm_hour = datetime_hwrtc->u32Hour; + if (datetime_hwrtc->u32TimeScale == RTC_CLOCK_12 && datetime_hwrtc->u32AmPm == RTC_PM) { + datetime_tm->tm_hour += 12; + } + datetime_tm->tm_min = datetime_hwrtc->u32Minute; + datetime_tm->tm_sec = datetime_hwrtc->u32Second; +} + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M251/serial_api.c b/targets/TARGET_NUVOTON/TARGET_M251/serial_api.c new file mode 100644 index 00000000000..fab0bf58505 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/serial_api.c @@ -0,0 +1,1153 @@ +/* + * Copyright (c) 2019, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "serial_api.h" + +#if DEVICE_SERIAL + +#include "cmsis.h" +#include "mbed_error.h" +#include "mbed_assert.h" +#include "PeripheralPins.h" +#include "nu_modutil.h" +#include "nu_bitutil.h" +#include +#include + +#if DEVICE_SERIAL_ASYNCH +#include "dma_api.h" +#include "dma.h" +#endif + +struct nu_uart_var { + uint32_t ref_cnt; // Reference count of the H/W module + serial_t * obj; + uint32_t fifo_size_tx; + uint32_t fifo_size_rx; + void (*vec)(void); +#if DEVICE_SERIAL_ASYNCH + void (*vec_async)(void); + uint8_t pdma_perp_tx; + uint8_t pdma_perp_rx; +#endif +}; + +static void uart0_vec(void); +static void uart1_vec(void); +static void uart2_vec(void); +static void uart_irq(serial_t *obj); + +#if DEVICE_SERIAL_ASYNCH +static void uart0_vec_async(void); +static void uart1_vec_async(void); +static void uart2_vec_async(void); +static void uart_irq_async(serial_t *obj); + +static void uart_dma_handler_tx(uint32_t id, uint32_t event); +static void uart_dma_handler_rx(uint32_t id, uint32_t event); + +static void serial_tx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable); +static void serial_rx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable); +static void serial_enable_interrupt(serial_t *obj, SerialIrq irq, uint32_t enable); +static void serial_rollback_interrupt(serial_t *obj, SerialIrq irq); +static int serial_write_async(serial_t *obj); +static int serial_read_async(serial_t *obj); + +static uint32_t serial_rx_event_check(serial_t *obj); +static uint32_t serial_tx_event_check(serial_t *obj); + +static int serial_is_tx_complete(serial_t *obj); +static void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable); + +static void serial_tx_buffer_set(serial_t *obj, const void *tx, size_t length, uint8_t width); +static void serial_rx_buffer_set(serial_t *obj, void *rx, size_t length, uint8_t width); +static void serial_rx_set_char_match(serial_t *obj, uint8_t char_match); +static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable); +static int serial_is_rx_complete(serial_t *obj); + +static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch); +static int serial_is_irq_en(serial_t *obj, SerialIrq irq); +#endif + +bool serial_can_deep_sleep(void); + +static struct nu_uart_var uart0_var = { + .ref_cnt = 0, + .obj = NULL, + .fifo_size_tx = 16, + .fifo_size_rx = 16, + .vec = uart0_vec, +#if DEVICE_SERIAL_ASYNCH + .vec_async = uart0_vec_async, + .pdma_perp_tx = PDMA_UART0_TX, + .pdma_perp_rx = PDMA_UART0_RX +#endif +}; +static struct nu_uart_var uart1_var = { + .ref_cnt = 0, + .obj = NULL, + .fifo_size_tx = 16, + .fifo_size_rx = 16, + .vec = uart1_vec, +#if DEVICE_SERIAL_ASYNCH + .vec_async = uart1_vec_async, + .pdma_perp_tx = PDMA_UART1_TX, + .pdma_perp_rx = PDMA_UART1_RX +#endif +}; +static struct nu_uart_var uart2_var = { + .ref_cnt = 0, + .obj = NULL, + .fifo_size_tx = 16, + .fifo_size_rx = 16, + .vec = uart2_vec, +#if DEVICE_SERIAL_ASYNCH + .vec_async = uart2_vec_async, + .pdma_perp_tx = PDMA_UART2_TX, + .pdma_perp_rx = PDMA_UART2_RX +#endif +}; + +int stdio_uart_inited = 0; +serial_t stdio_uart; +static uint32_t uart_modinit_mask = 0; + +static const struct nu_modinit_s uart_modinit_tab[] = { + {UART_0, UART0_MODULE, CLK_CLKSEL1_UART0SEL_HIRC, CLK_CLKDIV0_UART0(1), UART0_RST, UART0_IRQn, &uart0_var}, + {UART_1, UART1_MODULE, CLK_CLKSEL1_UART1SEL_HIRC, CLK_CLKDIV0_UART1(1), UART1_RST, UART1_IRQn, &uart1_var}, + {UART_2, UART2_MODULE, CLK_CLKSEL3_UART2SEL_HIRC, CLK_CLKDIV4_UART2(1), UART2_RST, UART2_IRQn, &uart2_var}, + + {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL} +}; + +extern void mbed_sdk_init(void); + +void serial_init(serial_t *obj, PinName tx, PinName rx) +{ + // NOTE: With armcc, serial_init() gets called from _sys_open() timing of which is before main()/mbed_sdk_init(). + mbed_sdk_init(); + + // Determine which UART_x the pins are used for + uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX); + uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX); + // Get the peripheral name (UART_x) from the pins and assign it to the object + obj->serial.uart = (UARTName) pinmap_merge(uart_tx, uart_rx); + MBED_ASSERT((int)obj->serial.uart != NC); + + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; + + if (! var->ref_cnt) { + // Reset this module + SYS_ResetModule(modinit->rsetidx); + + // Select IP clock source + CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv); + // Enable IP clock + CLK_EnableModuleClock(modinit->clkidx); + + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + + // Configure baudrate + int baudrate = 9600; + if (obj->serial.uart == STDIO_UART) { +#if MBED_CONF_PLATFORM_STDIO_BAUD_RATE + baudrate = MBED_CONF_PLATFORM_STDIO_BAUD_RATE; +#endif + } else { +#if MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE + baudrate = MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE; +#endif + } + serial_baud(obj, baudrate); + + // Configure data bits, parity, and stop bits + serial_format(obj, 8, ParityNone, 1); + } + var->ref_cnt ++; + + obj->serial.vec = var->vec; + obj->serial.irq_en = 0; + +#if DEVICE_SERIAL_ASYNCH + obj->serial.dma_usage_tx = DMA_USAGE_NEVER; + obj->serial.dma_usage_rx = DMA_USAGE_NEVER; + obj->serial.event = 0; + obj->serial.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS; + obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS; +#endif + + /* With support for checking H/W UART initialized or not, we allow serial_init(&stdio_uart) + * calls in even though H/W UART 'STDIO_UART' has initialized. When serial_init(&stdio_uart) + * calls in, we only need to set the 'stdio_uart_inited' flag. */ + if (((uintptr_t) obj) == ((uintptr_t) &stdio_uart)) { + MBED_ASSERT(obj->serial.uart == STDIO_UART); + stdio_uart_inited = 1; + } + + if (var->ref_cnt) { + // Mark this module to be inited. + int i = modinit - uart_modinit_tab; + uart_modinit_mask |= 1 << i; + } +} + +void serial_free(serial_t *obj) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; + + var->ref_cnt --; + if (! var->ref_cnt) { +#if DEVICE_SERIAL_ASYNCH + if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) { + dma_channel_free(obj->serial.dma_chn_id_tx); + obj->serial.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS; + } + if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) { + dma_channel_free(obj->serial.dma_chn_id_rx); + obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS; + } +#endif + + do { + UART_Close((UART_T *) NU_MODBASE(obj->serial.uart)); + + UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_THREIEN_Msk | UART_INTEN_RXTOIEN_Msk)); + NVIC_DisableIRQ(modinit->irq_n); + + // Disable IP clock + CLK_DisableModuleClock(modinit->clkidx); + } while (0); + } + + if (var->obj == obj) { + var->obj = NULL; + } + + /* Clear the 'stdio_uart_inited' flag when serial_free(&stdio_uart) calls in. */ + if (((uintptr_t) obj) == ((uintptr_t) &stdio_uart)) { + MBED_ASSERT(obj->serial.uart == STDIO_UART); + stdio_uart_inited = 0; + } + + if (! var->ref_cnt) { + // Mark this module to be deinited. + int i = modinit - uart_modinit_tab; + uart_modinit_mask &= ~(1 << i); + } +} + +void serial_baud(serial_t *obj, int baudrate) +{ + // Flush Tx FIFO. Otherwise, output data may get lost on this change. + while (! UART_IS_TX_EMPTY((UART_T *) NU_MODBASE(obj->serial.uart))); + + obj->serial.baudrate = baudrate; + UART_Open((UART_T *) NU_MODBASE(obj->serial.uart), baudrate); +} + +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) +{ + // Flush Tx FIFO. Otherwise, output data may get lost on this change. + while (! UART_IS_TX_EMPTY((UART_T *) NU_MODBASE(obj->serial.uart))); + + // Sanity check arguments + MBED_ASSERT((data_bits == 5) || (data_bits == 6) || (data_bits == 7) || (data_bits == 8)); + MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) || (parity == ParityForced1) || (parity == ParityForced0)); + MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); + + obj->serial.databits = data_bits; + obj->serial.parity = parity; + obj->serial.stopbits = stop_bits; + + uint32_t databits_intern = (data_bits == 5) ? UART_WORD_LEN_5 : + (data_bits == 6) ? UART_WORD_LEN_6 : + (data_bits == 7) ? UART_WORD_LEN_7 : + UART_WORD_LEN_8; + uint32_t parity_intern = (parity == ParityOdd || parity == ParityForced1) ? UART_PARITY_ODD : + (parity == ParityEven || parity == ParityForced0) ? UART_PARITY_EVEN : + UART_PARITY_NONE; + uint32_t stopbits_intern = (stop_bits == 2) ? UART_STOP_BIT_2 : UART_STOP_BIT_1; + UART_SetLine_Config((UART_T *) NU_MODBASE(obj->serial.uart), + 0, // Don't change baudrate + databits_intern, + parity_intern, + stopbits_intern); +} + +#if DEVICE_SERIAL_FC + +void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) +{ + UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart); + + if (rxflow != NC) { + // Check if RTS pin matches. + uint32_t uart_rts = pinmap_peripheral(rxflow, PinMap_UART_RTS); + MBED_ASSERT(uart_rts == obj->serial.uart); + // Enable the pin for RTS function + pinmap_pinout(rxflow, PinMap_UART_RTS); + + // NOTE: Added in M480/M2351/M251. Before configuring RTSACTLV, disable TX/RX. + uart_base->FUNCSEL |= UART_FUNCSEL_TXRXDIS_Msk; + while (uart_base->FIFOSTS & UART_FIFOSTS_TXRXACT_Msk); + // nRTS pin output is low level active + uart_base->MODEM |= UART_MODEM_RTSACTLV_Msk; + // NOTE: Added in M480/M2351/M251. After configuring RTSACTLV, re-enable TX/RX. + uart_base->FUNCSEL &= ~UART_FUNCSEL_TXRXDIS_Msk; + // Configure RTS trigger level to 8 bytes + uart_base->FIFO = (uart_base->FIFO & ~UART_FIFO_RTSTRGLV_Msk) | UART_FIFO_RTSTRGLV_8BYTES; + + if (type == FlowControlRTS || type == FlowControlRTSCTS) { + // Enable RTS + uart_base->INTEN |= UART_INTEN_ATORTSEN_Msk; + } else { + // Disable RTS + uart_base->INTEN &= ~UART_INTEN_ATORTSEN_Msk; + /* Drive nRTS pin output to low-active. Allow the peer to be able to send data + * even though its CTS is still enabled. */ + uart_base->MODEM &= ~UART_MODEM_RTS_Msk; + } + } + + /* If CTS is disabled, we don't need to configure CTS. But to be consistent with + * RTS code above, we still configure CTS. */ + if (txflow != NC) { + // Check if CTS pin matches. + uint32_t uart_cts = pinmap_peripheral(txflow, PinMap_UART_CTS); + MBED_ASSERT(uart_cts == obj->serial.uart); + // Enable the pin for CTS function + pinmap_pinout(txflow, PinMap_UART_CTS); + + // NOTE: Added in M480/M2351/M251. Before configuring CTSACTLV, disable TX/RX. + uart_base->FUNCSEL |= UART_FUNCSEL_TXRXDIS_Msk; + while (uart_base->FIFOSTS & UART_FIFOSTS_TXRXACT_Msk); + // nCTS pin input is low level active + uart_base->MODEMSTS |= UART_MODEMSTS_CTSACTLV_Msk; + // NOTE: Added in M480/M2351/M251. After configuring CTSACTLV, re-enable TX/RX. + uart_base->FUNCSEL &= ~UART_FUNCSEL_TXRXDIS_Msk; + + if (type == FlowControlCTS || type == FlowControlRTSCTS) { + // Enable CTS + uart_base->INTEN |= UART_INTEN_ATOCTSEN_Msk; + } else { + // Disable CTS + uart_base->INTEN &= ~UART_INTEN_ATOCTSEN_Msk; + } + } +} + +#endif //DEVICE_SERIAL_FC + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +{ + // Flush Tx FIFO. Otherwise, output data may get lost on this change. + while (! UART_IS_TX_EMPTY((UART_T *) NU_MODBASE(obj->serial.uart))); + + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + obj->serial.irq_handler = (uint32_t) handler; + obj->serial.irq_id = id; + + // Restore sync-mode vector + obj->serial.vec = ((struct nu_uart_var *) modinit->var)->vec; +} + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) +{ + obj->serial.irq_en = enable; + serial_enable_interrupt(obj, irq, enable); +} + +int serial_getc(serial_t *obj) +{ + // NOTE: Every byte access requires accompaniment of one interrupt. This has side effect of performance degradation. + while (! serial_readable(obj)); + int c = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart))); + + // NOTE: On Nuvoton targets, no H/W IRQ to match TxIrq/RxIrq. + // Simulation of TxIrq/RxIrq requires the call to Serial::putc()/Serial::getc() respectively. + if (obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) { + UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); + } + + return c; +} + +void serial_putc(serial_t *obj, int c) +{ + // NOTE: Every byte access requires accompaniment of one interrupt. This has side effect of performance degradation. + while (! serial_writable(obj)); + UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), c); + + // NOTE: On Nuvoton targets, no H/W IRQ to match TxIrq/RxIrq. + // Simulation of TxIrq/RxIrq requires the call to Serial::putc()/Serial::getc() respectively. + if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) { + UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk); + } +} + +int serial_readable(serial_t *obj) +{ + return ! UART_GET_RX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))); +} + +int serial_writable(serial_t *obj) +{ + return ! UART_IS_TX_FULL(((UART_T *) NU_MODBASE(obj->serial.uart))); +} + +void serial_pinout_tx(PinName tx) +{ + pinmap_pinout(tx, PinMap_UART_TX); +} + +void serial_break_set(serial_t *obj) +{ + ((UART_T *) NU_MODBASE(obj->serial.uart))->LINE |= UART_LINE_BCB_Msk; +} + +void serial_break_clear(serial_t *obj) +{ + ((UART_T *) NU_MODBASE(obj->serial.uart))->LINE &= ~UART_LINE_BCB_Msk; +} + +static void uart0_vec(void) +{ + uart_irq(uart0_var.obj); +} + +static void uart1_vec(void) +{ + uart_irq(uart1_var.obj); +} + +static void uart2_vec(void) +{ + uart_irq(uart2_var.obj); +} + +static void uart_irq(serial_t *obj) +{ + UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart); + + if (uart_base->INTSTS & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) { + // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next read. + UART_DISABLE_INT(uart_base, (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); + if (obj->serial.irq_handler) { + ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, RxIrq); + } + } + + if (uart_base->INTSTS & UART_INTSTS_THREINT_Msk) { + // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next write. + UART_DISABLE_INT(uart_base, UART_INTEN_THREIEN_Msk); + if (obj->serial.irq_handler) { + ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, TxIrq); + } + } + + // FIXME: Ignore all other interrupt flags. Clear them. Otherwise, program will get stuck in interrupt. + uart_base->INTSTS = uart_base->INTSTS; + uart_base->FIFOSTS = uart_base->FIFOSTS; +} + + +#if DEVICE_SERIAL_ASYNCH +int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint) +{ + MBED_ASSERT(tx_width == 8 || tx_width == 16 || tx_width == 32); + + obj->serial.dma_usage_tx = hint; + serial_check_dma_usage(&obj->serial.dma_usage_tx, &obj->serial.dma_chn_id_tx); + + // UART IRQ is necessary for both interrupt way and DMA way + serial_tx_enable_event(obj, event, 1); + serial_tx_buffer_set(obj, tx, tx_length, tx_width); + + int n_word = 0; + if (obj->serial.dma_usage_tx == DMA_USAGE_NEVER) { + // Interrupt way + n_word = serial_write_async(obj); + serial_tx_enable_interrupt(obj, handler, 1); + } else { + // DMA way + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + PDMA_T *pdma_base = dma_modbase(); + + pdma_base->CHCTL |= 1 << obj->serial.dma_chn_id_tx; // Enable this DMA channel + PDMA_SetTransferMode(pdma_base, + obj->serial.dma_chn_id_tx, + ((struct nu_uart_var *) modinit->var)->pdma_perp_tx, // Peripheral connected to this PDMA + 0, // Scatter-gather disabled + 0); // Scatter-gather descriptor address + PDMA_SetTransferCnt(pdma_base, + obj->serial.dma_chn_id_tx, + (tx_width == 8) ? PDMA_WIDTH_8 : (tx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32, + tx_length); + PDMA_SetTransferAddr(pdma_base, + obj->serial.dma_chn_id_tx, + (uint32_t) tx, // NOTE: + // NUC472: End of source address + // M451: Start of source address + // M480: Start of source address + // M2351: Start of source address + // M251: Start of source address + PDMA_SAR_INC, // Source address incremental + (uint32_t) NU_MODBASE(obj->serial.uart), // Destination address + PDMA_DAR_FIX); // Destination address fixed + PDMA_SetBurstType(pdma_base, + obj->serial.dma_chn_id_tx, + PDMA_REQ_SINGLE, // Single mode + 0); // Burst size + PDMA_EnableInt(pdma_base, + obj->serial.dma_chn_id_tx, + PDMA_INT_TRANS_DONE); // Interrupt type + // Register DMA event handler + dma_set_handler(obj->serial.dma_chn_id_tx, (uint32_t) uart_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL); + serial_tx_enable_interrupt(obj, handler, 1); + /* We needn't actually enable UART INT to go UART ISR -> handler. + * Instead, as PDMA INT is triggered, we will go PDMA ISR -> UART ISR -> handler + * with serial_tx/rx_enable_interrupt having set up this call path. */ + UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk); + + ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_TXPDMAEN_Msk; // Start DMA transfer + } + + return n_word; +} + +void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint) +{ + MBED_ASSERT(rx_width == 8 || rx_width == 16 || rx_width == 32); + + obj->serial.dma_usage_rx = hint; + serial_check_dma_usage(&obj->serial.dma_usage_rx, &obj->serial.dma_chn_id_rx); + // DMA doesn't support char match, so fall back to IRQ if it is requested. + if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER && + (event & SERIAL_EVENT_RX_CHARACTER_MATCH) && + char_match != SERIAL_RESERVED_CHAR_MATCH) { + obj->serial.dma_usage_rx = DMA_USAGE_NEVER; + dma_channel_free(obj->serial.dma_chn_id_rx); + obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS; + } + + // UART IRQ is necessary for both interrupt way and DMA way + serial_rx_enable_event(obj, event, 1); + serial_rx_buffer_set(obj, rx, rx_length, rx_width); + serial_rx_set_char_match(obj, char_match); + + if (obj->serial.dma_usage_rx == DMA_USAGE_NEVER) { + // Interrupt way + serial_rx_enable_interrupt(obj, handler, 1); + } else { + // DMA way + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + PDMA_T *pdma_base = dma_modbase(); + + pdma_base->CHCTL |= 1 << obj->serial.dma_chn_id_rx; // Enable this DMA channel + PDMA_SetTransferMode(pdma_base, + obj->serial.dma_chn_id_rx, + ((struct nu_uart_var *) modinit->var)->pdma_perp_rx, // Peripheral connected to this PDMA + 0, // Scatter-gather disabled + 0); // Scatter-gather descriptor address + PDMA_SetTransferCnt(pdma_base, + obj->serial.dma_chn_id_rx, + (rx_width == 8) ? PDMA_WIDTH_8 : (rx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32, + rx_length); + PDMA_SetTransferAddr(pdma_base, + obj->serial.dma_chn_id_rx, + (uint32_t) NU_MODBASE(obj->serial.uart), // Source address + PDMA_SAR_FIX, // Source address fixed + (uint32_t) rx, // NOTE: + // NUC472: End of destination address + // M451: Start of destination address + // M480: Start of destination address + // M2351: Start of destination address + // M251: Start of destination address + PDMA_DAR_INC); // Destination address incremental + PDMA_SetBurstType(pdma_base, + obj->serial.dma_chn_id_rx, + PDMA_REQ_SINGLE, // Single mode + 0); // Burst size + PDMA_EnableInt(pdma_base, + obj->serial.dma_chn_id_rx, + PDMA_INT_TRANS_DONE); // Interrupt type + // Register DMA event handler + dma_set_handler(obj->serial.dma_chn_id_rx, (uint32_t) uart_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL); + serial_rx_enable_interrupt(obj, handler, 1); + /* We needn't actually enable UART INT to go UART ISR -> handler. + * Instead, as PDMA INT is triggered, we will go PDMA ISR -> UART ISR -> handler + * with serial_tx/rx_enable_interrupt having set up this call path. */ + UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); + ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_RXPDMAEN_Msk; // Start DMA transfer + } +} + +void serial_tx_abort_asynch(serial_t *obj) +{ + // Flush Tx FIFO. Otherwise, output data may get lost on this change. + while (! UART_IS_TX_EMPTY((UART_T *) NU_MODBASE(obj->serial.uart))); + + if (obj->serial.dma_usage_tx != DMA_USAGE_NEVER) { + PDMA_T *pdma_base = dma_modbase(); + + if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) { + PDMA_DisableInt(pdma_base, obj->serial.dma_chn_id_tx, PDMA_INT_TRANS_DONE); + // NOTE: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown. + pdma_base->CHCTL &= ~(1 << obj->serial.dma_chn_id_tx); + } + UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_TXPDMAEN_Msk); + } + + // Necessary for both interrupt way and DMA way + serial_enable_interrupt(obj, TxIrq, 0); + serial_rollback_interrupt(obj, TxIrq); +} + +void serial_rx_abort_asynch(serial_t *obj) +{ + if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER) { + PDMA_T *pdma_base = dma_modbase(); + + if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) { + PDMA_DisableInt(pdma_base, obj->serial.dma_chn_id_rx, PDMA_INT_TRANS_DONE); + // NOTE: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown. + pdma_base->CHCTL &= ~(1 << obj->serial.dma_chn_id_rx); + } + UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RXPDMAEN_Msk); + } + + // Necessary for both interrupt way and DMA way + serial_enable_interrupt(obj, RxIrq, 0); + serial_rollback_interrupt(obj, RxIrq); +} + +uint8_t serial_tx_active(serial_t *obj) +{ + // NOTE: Judge by serial_is_irq_en(obj, TxIrq) doesn't work with sync/async modes interleaved. Change with TX FIFO empty flag. + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; + return (obj->serial.vec == var->vec_async); +} + +uint8_t serial_rx_active(serial_t *obj) +{ + // NOTE: Judge by serial_is_irq_en(obj, RxIrq) doesn't work with sync/async modes interleaved. Change with RX FIFO empty flag. + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; + return (obj->serial.vec == var->vec_async); +} + +int serial_irq_handler_asynch(serial_t *obj) +{ + int event_rx = 0; + int event_tx = 0; + + // Necessary for both interrupt way and DMA way + if (serial_is_irq_en(obj, RxIrq)) { + event_rx = serial_rx_event_check(obj); + if (event_rx) { + serial_rx_abort_asynch(obj); + } + } + + if (serial_is_irq_en(obj, TxIrq)) { + event_tx = serial_tx_event_check(obj); + if (event_tx) { + serial_tx_abort_asynch(obj); + } + } + + return (obj->serial.event & (event_rx | event_tx)); +} + +static void uart0_vec_async(void) +{ + uart_irq_async(uart0_var.obj); +} + +static void uart1_vec_async(void) +{ + uart_irq_async(uart1_var.obj); +} + +static void uart2_vec_async(void) +{ + uart_irq_async(uart2_var.obj); +} + +static void uart_irq_async(serial_t *obj) +{ + if (serial_is_irq_en(obj, RxIrq)) { + (*obj->serial.irq_handler_rx_async)(); + } + if (serial_is_irq_en(obj, TxIrq)) { + (*obj->serial.irq_handler_tx_async)(); + } +} + +static void serial_rx_set_char_match(serial_t *obj, uint8_t char_match) +{ + obj->char_match = char_match; + obj->char_found = 0; +} + +static void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable) +{ + obj->serial.event &= ~SERIAL_EVENT_TX_MASK; + obj->serial.event |= (event & SERIAL_EVENT_TX_MASK); + + if (event & SERIAL_EVENT_TX_COMPLETE) { + // N/A + } +} + +static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable) +{ + obj->serial.event &= ~SERIAL_EVENT_RX_MASK; + obj->serial.event |= (event & SERIAL_EVENT_RX_MASK); + + if (event & SERIAL_EVENT_RX_COMPLETE) { + // N/A + } + if (event & SERIAL_EVENT_RX_OVERRUN_ERROR) { + // N/A + } + if (event & SERIAL_EVENT_RX_FRAMING_ERROR) { + UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RLSIEN_Msk); + } + if (event & SERIAL_EVENT_RX_PARITY_ERROR) { + UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RLSIEN_Msk); + } + if (event & SERIAL_EVENT_RX_OVERFLOW) { + UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_BUFERRIEN_Msk); + } + if (event & SERIAL_EVENT_RX_CHARACTER_MATCH) { + // N/A + } +} + +static int serial_is_tx_complete(serial_t *obj) +{ + // NOTE: Exclude tx fifo empty check due to no such interrupt on DMA way + return (obj->tx_buff.pos == obj->tx_buff.length); +} + +static int serial_is_rx_complete(serial_t *obj) +{ + return (obj->rx_buff.pos == obj->rx_buff.length); +} + +static uint32_t serial_tx_event_check(serial_t *obj) +{ + UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart); + + if (uart_base->INTSTS & UART_INTSTS_THREINT_Msk) { + // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next write. + UART_DISABLE_INT(uart_base, UART_INTEN_THREIEN_Msk); + } + + uint32_t event = 0; + + if (obj->serial.dma_usage_tx == DMA_USAGE_NEVER) { + serial_write_async(obj); + } + + if (serial_is_tx_complete(obj)) { + event |= SERIAL_EVENT_TX_COMPLETE; + } + + return event; +} + +static uint32_t serial_rx_event_check(serial_t *obj) +{ + UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart); + + if (uart_base->INTSTS & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) { + // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next read. + UART_DISABLE_INT(uart_base, (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); + } + + uint32_t event = 0; + + if (uart_base->FIFOSTS & UART_FIFOSTS_BIF_Msk) { + uart_base->FIFOSTS = UART_FIFOSTS_BIF_Msk; + } + if (uart_base->FIFOSTS & UART_FIFOSTS_FEF_Msk) { + uart_base->FIFOSTS = UART_FIFOSTS_FEF_Msk; + event |= SERIAL_EVENT_RX_FRAMING_ERROR; + } + if (uart_base->FIFOSTS & UART_FIFOSTS_PEF_Msk) { + uart_base->FIFOSTS = UART_FIFOSTS_PEF_Msk; + event |= SERIAL_EVENT_RX_PARITY_ERROR; + } + + if (uart_base->FIFOSTS & UART_FIFOSTS_RXOVIF_Msk) { + uart_base->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk; + event |= SERIAL_EVENT_RX_OVERFLOW; + } + + if (obj->serial.dma_usage_rx == DMA_USAGE_NEVER) { + serial_read_async(obj); + } + + if (serial_is_rx_complete(obj)) { + event |= SERIAL_EVENT_RX_COMPLETE; + } + if ((obj->char_match != SERIAL_RESERVED_CHAR_MATCH) && obj->char_found) { + event |= SERIAL_EVENT_RX_CHARACTER_MATCH; + } + + return event; +} + +static void uart_dma_handler_tx(uint32_t id, uint32_t event_dma) +{ + serial_t *obj = (serial_t *) id; + + // FIXME: Pass this error to caller + if (event_dma & DMA_EVENT_ABORT) { + } + // Expect UART IRQ will catch this transfer done event + if (event_dma & DMA_EVENT_TRANSFER_DONE) { + obj->tx_buff.pos = obj->tx_buff.length; + } + // FIXME: Pass this error to caller + if (event_dma & DMA_EVENT_TIMEOUT) { + } + + uart_irq_async(obj); +} + +static void uart_dma_handler_rx(uint32_t id, uint32_t event_dma) +{ + serial_t *obj = (serial_t *) id; + + // FIXME: Pass this error to caller + if (event_dma & DMA_EVENT_ABORT) { + } + // Expect UART IRQ will catch this transfer done event + if (event_dma & DMA_EVENT_TRANSFER_DONE) { + obj->rx_buff.pos = obj->rx_buff.length; + } + // FIXME: Pass this error to caller + if (event_dma & DMA_EVENT_TIMEOUT) { + } + + uart_irq_async(obj); +} + +static int serial_write_async(serial_t *obj) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart); + + uint32_t tx_fifo_max = ((struct nu_uart_var *) modinit->var)->fifo_size_tx; + uint32_t tx_fifo_busy = (uart_base->FIFOSTS & UART_FIFOSTS_TXPTR_Msk) >> UART_FIFOSTS_TXPTR_Pos; + if (uart_base->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) { + tx_fifo_busy = tx_fifo_max; + } + uint32_t tx_fifo_free = tx_fifo_max - tx_fifo_busy; + if (tx_fifo_free == 0) { + // Simulate clear of the interrupt flag + if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) { + UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk); + } + return 0; + } + + uint32_t bytes_per_word = obj->tx_buff.width / 8; + + uint8_t *tx = (uint8_t *)(obj->tx_buff.buffer) + bytes_per_word * obj->tx_buff.pos; + int n_words = 0; + while (obj->tx_buff.pos < obj->tx_buff.length && tx_fifo_free >= bytes_per_word) { + switch (bytes_per_word) { + case 4: + UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++); + UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++); + case 2: + UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++); + case 1: + UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++); + } + + n_words ++; + tx_fifo_free -= bytes_per_word; + obj->tx_buff.pos ++; + } + + if (n_words) { + // Simulate clear of the interrupt flag + if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) { + UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk); + } + } + + return n_words; +} + +static int serial_read_async(serial_t *obj) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + uint32_t rx_fifo_busy = (((UART_T *) NU_MODBASE(obj->serial.uart))->FIFOSTS & UART_FIFOSTS_RXPTR_Msk) >> UART_FIFOSTS_RXPTR_Pos; + + uint32_t bytes_per_word = obj->rx_buff.width / 8; + + uint8_t *rx = (uint8_t *)(obj->rx_buff.buffer) + bytes_per_word * obj->rx_buff.pos; + int n_words = 0; + while (obj->rx_buff.pos < obj->rx_buff.length && rx_fifo_busy >= bytes_per_word) { + switch (bytes_per_word) { + case 4: + *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart))); + *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart))); + case 2: + *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart))); + case 1: + *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart))); + } + + n_words ++; + rx_fifo_busy -= bytes_per_word; + obj->rx_buff.pos ++; + + if ((obj->serial.event & SERIAL_EVENT_RX_CHARACTER_MATCH) && + obj->char_match != SERIAL_RESERVED_CHAR_MATCH) { + uint8_t *rx_cmp = rx; + switch (bytes_per_word) { + case 4: + rx_cmp -= 2; + case 2: + rx_cmp --; + case 1: + rx_cmp --; + } + if (*rx_cmp == obj->char_match) { + obj->char_found = 1; + break; + } + } + } + + if (n_words) { + // Simulate clear of the interrupt flag + if (obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) { + UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); + } + } + + return n_words; +} + +static void serial_tx_buffer_set(serial_t *obj, const void *tx, size_t length, uint8_t width) +{ + obj->tx_buff.buffer = (void *) tx; + obj->tx_buff.length = length; + obj->tx_buff.pos = 0; + obj->tx_buff.width = width; +} + +static void serial_rx_buffer_set(serial_t *obj, void *rx, size_t length, uint8_t width) +{ + obj->rx_buff.buffer = rx; + obj->rx_buff.length = length; + obj->rx_buff.pos = 0; + obj->rx_buff.width = width; +} + +static void serial_tx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t enable) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + // Necessary for both interrupt way and DMA way + struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; + // With our own async vector, tx/rx handlers can be different. + obj->serial.vec = var->vec_async; + obj->serial.irq_handler_tx_async = (void (*)(void)) handler; + serial_enable_interrupt(obj, TxIrq, enable); +} + +static void serial_rx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t enable) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + // Necessary for both interrupt way and DMA way + struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; + // With our own async vector, tx/rx handlers can be different. + obj->serial.vec = var->vec_async; + obj->serial.irq_handler_rx_async = (void (*) (void)) handler; + serial_enable_interrupt(obj, RxIrq, enable); +} + +static void serial_enable_interrupt(serial_t *obj, SerialIrq irq, uint32_t enable) +{ + if (enable) { + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + NVIC_SetVector(modinit->irq_n, (uint32_t) obj->serial.vec); + NVIC_EnableIRQ(modinit->irq_n); + + struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; + // Multiple serial S/W objects for single UART H/W module possibly. + // Bind serial S/W object to UART H/W module as interrupt is enabled. + var->obj = obj; + + switch (irq) { + // NOTE: Setting inten_msk first to avoid race condition + case RxIrq: + obj->serial.inten_msk = obj->serial.inten_msk | (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk); + UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); + break; + case TxIrq: + obj->serial.inten_msk = obj->serial.inten_msk | UART_INTEN_THREIEN_Msk; + UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk); + break; + } + } else { // disable + switch (irq) { + case RxIrq: + UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); + obj->serial.inten_msk = obj->serial.inten_msk & ~(UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk); + break; + case TxIrq: + UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk); + obj->serial.inten_msk = obj->serial.inten_msk & ~UART_INTEN_THREIEN_Msk; + break; + } + } +} + +static void serial_rollback_interrupt(serial_t *obj, SerialIrq irq) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; + + obj->serial.vec = var->vec; + serial_enable_interrupt(obj, irq, obj->serial.irq_en); +} + +static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch) +{ + if (*dma_usage != DMA_USAGE_NEVER) { + if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) { + *dma_ch = dma_channel_allocate(DMA_CAP_NONE); + } + if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) { + *dma_usage = DMA_USAGE_NEVER; + } + } else { + dma_channel_free(*dma_ch); + *dma_ch = DMA_ERROR_OUT_OF_CHANNELS; + } +} + +static int serial_is_irq_en(serial_t *obj, SerialIrq irq) +{ + int inten_msk = 0; + + switch (irq) { + case RxIrq: + inten_msk = obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk); + break; + case TxIrq: + inten_msk = obj->serial.inten_msk & UART_INTEN_THREIEN_Msk; + break; + } + + return !! inten_msk; +} + +#endif // #if DEVICE_SERIAL_ASYNCH + +bool serial_can_deep_sleep(void) +{ + bool sleep_allowed = 1; + const struct nu_modinit_s *modinit = uart_modinit_tab; + while (modinit->var != NULL) { + struct nu_uart_var *uart_var = (struct nu_uart_var *) modinit->var; + UART_T *uart_base = (UART_T *) NU_MODBASE(modinit->modname); + if (uart_var->ref_cnt > 0) { + if (!UART_IS_TX_EMPTY(uart_base)) { + sleep_allowed = 0; + break; + } + } + modinit++; + } + return sleep_allowed; +} + +const PinMap *serial_tx_pinmap() +{ + return PinMap_UART_TX; +} + +const PinMap *serial_rx_pinmap() +{ + return PinMap_UART_RX; +} + +const PinMap *serial_cts_pinmap() +{ + return PinMap_UART_CTS; +} + +const PinMap *serial_rts_pinmap() +{ + return PinMap_UART_RTS; +} + +#endif // #if DEVICE_SERIAL diff --git a/targets/TARGET_NUVOTON/TARGET_M251/sleep.c b/targets/TARGET_NUVOTON/TARGET_M251/sleep.c new file mode 100644 index 00000000000..11c564549f7 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/sleep.c @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2019, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "sleep_api.h" + +#if DEVICE_SLEEP + +#include "cmsis.h" +#include "device.h" +#include "objects.h" +#include "PeripheralPins.h" +#include + +#if DEVICE_SERIAL +bool serial_can_deep_sleep(void); +#endif + +/** + * Enter idle mode, in which just CPU is halted. + */ +void hal_sleep(void) +{ + SYS_UnlockReg(); + CLK_Idle(); + SYS_LockReg(); +} + +/** + * Enter power-down mode, in which HXT/HIRC are halted. + */ +void hal_deepsleep(void) +{ +#if DEVICE_SERIAL + if (!serial_can_deep_sleep()) { + return; + } +#endif + + SYS_UnlockReg(); + CLK_PowerDown(); + SYS_LockReg(); +} + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M251/spi_api.c b/targets/TARGET_NUVOTON/TARGET_M251/spi_api.c new file mode 100644 index 00000000000..0e5d5cad80b --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/spi_api.c @@ -0,0 +1,843 @@ +/* + * Copyright (c) 2019, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "spi_api.h" + +#if DEVICE_SPI + +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralPins.h" +#include "nu_modutil.h" +#include "nu_miscutil.h" +#include "nu_bitutil.h" + +#if DEVICE_SPI_ASYNCH +#include "dma_api.h" +#include "dma.h" +#endif + +#define NU_SPI_FRAME_MIN 8 +#define NU_SPI_FRAME_MAX 32 + +struct nu_spi_var { +#if DEVICE_SPI_ASYNCH + uint8_t pdma_perp_tx; + uint8_t pdma_perp_rx; +#endif +}; + +static struct nu_spi_var spi0_var = { +#if DEVICE_SPI_ASYNCH + .pdma_perp_tx = PDMA_SPI0_TX, + .pdma_perp_rx = PDMA_SPI0_RX +#endif +}; + +/* Synchronous version of SPI_ENABLE()/SPI_DISABLE() macros + * + * The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI + * control logic is enabled/disabled, this bit indicates the real status of SPI controller. + * + * NOTE: All configurations shall be ready before calling SPI_ENABLE_SYNC(). + * NOTE: Before changing the configurations of SPIx_CTL, SPIx_CLKDIV, SPIx_SSCTL and SPIx_FIFOCTL registers, + * user shall clear the SPIEN (SPIx_CTL[0]) and confirm the SPIENSTS (SPIx_STATUS[15]) is 0 + * (by SPI_DISABLE_SYNC here). + */ +__STATIC_INLINE void SPI_ENABLE_SYNC(SPI_T *spi_base) +{ + if (! (spi_base->CTL & SPI_CTL_SPIEN_Msk)) { + SPI_ENABLE(spi_base); + } + while (! (spi_base->STATUS & SPI_STATUS_SPIENSTS_Msk)); +} +__STATIC_INLINE void SPI_DISABLE_SYNC(SPI_T *spi_base) +{ + if (spi_base->CTL & SPI_CTL_SPIEN_Msk) { + // NOTE: SPI H/W may get out of state without the busy check. + while (SPI_IS_BUSY(spi_base)); + + SPI_DISABLE(spi_base); + } + while (spi_base->STATUS & SPI_STATUS_SPIENSTS_Msk); +} + +#if DEVICE_SPI_ASYNCH +static void spi_enable_vector_interrupt(spi_t *obj, uint32_t handler, uint8_t enable); +static void spi_master_enable_interrupt(spi_t *obj, uint8_t enable); +static uint32_t spi_master_write_asynch(spi_t *obj, uint32_t tx_limit); +static uint32_t spi_master_read_asynch(spi_t *obj); +static uint32_t spi_event_check(spi_t *obj); +static void spi_enable_event(spi_t *obj, uint32_t event, uint8_t enable); +static void spi_buffer_set(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length); +static void spi_check_dma_usage(DMAUsage *dma_usage, int *dma_ch_tx, int *dma_ch_rx); +static uint8_t spi_get_data_width(spi_t *obj); +static int spi_is_tx_complete(spi_t *obj); +static int spi_is_rx_complete(spi_t *obj); +static int spi_writeable(spi_t * obj); +static int spi_readable(spi_t * obj); +static void spi_dma_handler_tx(uint32_t id, uint32_t event_dma); +static void spi_dma_handler_rx(uint32_t id, uint32_t event_dma); +static uint32_t spi_fifo_depth(spi_t *obj); +#endif + +static uint32_t spi_modinit_mask = 0; + +static const struct nu_modinit_s spi_modinit_tab[] = { + {SPI_0, SPI0_MODULE, CLK_CLKSEL2_SPI0SEL_PCLK1, MODULE_NoMsk, SPI0_RST, SPI0_IRQn, &spi0_var}, + + {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL} +}; + +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) +{ + // Determine which SPI_x the pins are used for + uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI); + uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO); + uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK); + uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL); + uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso); + uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel); + obj->spi.spi = (SPIName) pinmap_merge(spi_data, spi_cntl); + MBED_ASSERT((int)obj->spi.spi != NC); + + const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->spi.spi); + + // Reset this module + SYS_ResetModule(modinit->rsetidx); + + // Select IP clock source + CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv); + // Enable IP clock + CLK_EnableModuleClock(modinit->clkidx); + + pinmap_pinout(mosi, PinMap_SPI_MOSI); + pinmap_pinout(miso, PinMap_SPI_MISO); + pinmap_pinout(sclk, PinMap_SPI_SCLK); + pinmap_pinout(ssel, PinMap_SPI_SSEL); + + obj->spi.pin_mosi = mosi; + obj->spi.pin_miso = miso; + obj->spi.pin_sclk = sclk; + obj->spi.pin_ssel = ssel; + + +#if DEVICE_SPI_ASYNCH + obj->spi.dma_usage = DMA_USAGE_NEVER; + obj->spi.event = 0; + obj->spi.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS; + obj->spi.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS; + + /* NOTE: We use vector to judge if asynchronous transfer is on-going (spi_active). + * At initial time, asynchronous transfer is not on-going and so vector must + * be cleared to zero for correct judgement. */ + NVIC_SetVector(modinit->irq_n, 0); +#endif + + // Mark this module to be inited. + int i = modinit - spi_modinit_tab; + spi_modinit_mask |= 1 << i; +} + +void spi_free(spi_t *obj) +{ +#if DEVICE_SPI_ASYNCH + if (obj->spi.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) { + dma_channel_free(obj->spi.dma_chn_id_tx); + obj->spi.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS; + } + if (obj->spi.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) { + dma_channel_free(obj->spi.dma_chn_id_rx); + obj->spi.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS; + } +#endif + + SPI_Close((SPI_T *) NU_MODBASE(obj->spi.spi)); + + const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->spi.spi); + + SPI_DisableInt(((SPI_T *) NU_MODBASE(obj->spi.spi)), (SPI_FIFO_RXOV_INT_MASK | SPI_FIFO_RXTH_INT_MASK | SPI_FIFO_TXTH_INT_MASK)); + NVIC_DisableIRQ(modinit->irq_n); + + // Disable IP clock + CLK_DisableModuleClock(modinit->clkidx); + + // Mark this module to be deinited. + int i = modinit - spi_modinit_tab; + spi_modinit_mask &= ~(1 << i); +} + +void spi_format(spi_t *obj, int bits, int mode, int slave) +{ + MBED_ASSERT(bits >= NU_SPI_FRAME_MIN && bits <= NU_SPI_FRAME_MAX); + + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + + SPI_DISABLE_SYNC(spi_base); + + SPI_Open(spi_base, + slave ? SPI_SLAVE : SPI_MASTER, + (mode == 0) ? SPI_MODE_0 : (mode == 1) ? SPI_MODE_1 : (mode == 2) ? SPI_MODE_2 : SPI_MODE_3, + bits, + SPI_GetBusClock(spi_base)); + // NOTE: Hardcode to be MSB first. + SPI_SET_MSB_FIRST(spi_base); + + if (! slave) { + // Master + if (obj->spi.pin_ssel != NC) { + // Configure SS as low active. + SPI_EnableAutoSS(spi_base, SPI_SS, SPI_SS_ACTIVE_LOW); + } else { + SPI_DisableAutoSS(spi_base); + } + } else { + // Slave + // Configure SS as low active. + spi_base->SSCTL &= ~SPI_SSCTL_SSACTPOL_Msk; + } + + /* NOTE: M451's/M480's/M2351's/M251's SPI_Open() will enable SPI transfer (SPI_CTL_SPIEN_Msk). + * We cannot use SPI_CTL_SPIEN_Msk for judgement of spi_active(). + * Judge with vector instead. */ +} + +void spi_frequency(spi_t *obj, int hz) +{ + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + + SPI_DISABLE_SYNC(spi_base); + + SPI_SetBusClock((SPI_T *) NU_MODBASE(obj->spi.spi), hz); +} + + +int spi_master_write(spi_t *obj, int value) +{ + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + + // NOTE: Data in receive FIFO can be read out via ICE. + SPI_ENABLE_SYNC(spi_base); + + // Wait for tx buffer empty + while(! spi_writeable(obj)); + SPI_WRITE_TX(spi_base, value); + + // Wait for rx buffer full + while (! spi_readable(obj)); + int value2 = SPI_READ_RX(spi_base); + + /* We don't call SPI_DISABLE_SYNC here for performance. */ + + return value2; +} + +int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, + char *rx_buffer, int rx_length, char write_fill) { + int total = (tx_length > rx_length) ? tx_length : rx_length; + + for (int i = 0; i < total; i++) { + char out = (i < tx_length) ? tx_buffer[i] : write_fill; + char in = spi_master_write(obj, out); + if (i < rx_length) { + rx_buffer[i] = in; + } + } + + return total; +} + +const PinMap *spi_master_mosi_pinmap() +{ + return PinMap_SPI_MOSI; +} + +const PinMap *spi_master_miso_pinmap() +{ + return PinMap_SPI_MISO; +} + +const PinMap *spi_master_clk_pinmap() +{ + return PinMap_SPI_SCLK; +} + +const PinMap *spi_master_cs_pinmap() +{ + return PinMap_SPI_SSEL; +} + +const PinMap *spi_slave_mosi_pinmap() +{ + return PinMap_SPI_MOSI; +} + +const PinMap *spi_slave_miso_pinmap() +{ + return PinMap_SPI_MISO; +} + +const PinMap *spi_slave_clk_pinmap() +{ + return PinMap_SPI_SCLK; +} + +const PinMap *spi_slave_cs_pinmap() +{ + return PinMap_SPI_SSEL; +} + +#if DEVICE_SPISLAVE +int spi_slave_receive(spi_t *obj) +{ + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + + SPI_ENABLE_SYNC(spi_base); + + return spi_readable(obj); +}; + +int spi_slave_read(spi_t *obj) +{ + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + + SPI_ENABLE_SYNC(spi_base); + + // Wait for rx buffer full + while (! spi_readable(obj)); + int value = SPI_READ_RX(spi_base); + return value; +} + +void spi_slave_write(spi_t *obj, int value) +{ + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + + SPI_ENABLE_SYNC(spi_base); + + // Wait for tx buffer empty + while(! spi_writeable(obj)); + SPI_WRITE_TX(spi_base, value); +} +#endif + +#if DEVICE_SPI_ASYNCH +void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint) +{ + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + SPI_SET_DATA_WIDTH(spi_base, bit_width); + + obj->spi.dma_usage = hint; + spi_check_dma_usage(&obj->spi.dma_usage, &obj->spi.dma_chn_id_tx, &obj->spi.dma_chn_id_rx); + uint32_t data_width = spi_get_data_width(obj); + // Conditions to go DMA way: + // (1) No DMA support for non-8 multiple data width. + // (2) tx length >= rx length. Otherwise, as tx DMA is done, no bus activity for remaining rx. + if ((data_width % 8) || + (tx_length < rx_length)) { + obj->spi.dma_usage = DMA_USAGE_NEVER; + dma_channel_free(obj->spi.dma_chn_id_tx); + obj->spi.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS; + dma_channel_free(obj->spi.dma_chn_id_rx); + obj->spi.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS; + } + + // SPI IRQ is necessary for both interrupt way and DMA way + spi_enable_event(obj, event, 1); + spi_buffer_set(obj, tx, tx_length, rx, rx_length); + + SPI_ENABLE_SYNC(spi_base); + + if (obj->spi.dma_usage == DMA_USAGE_NEVER) { + // Interrupt way + spi_master_write_asynch(obj, spi_fifo_depth(obj) / 2); + spi_enable_vector_interrupt(obj, handler, 1); + spi_master_enable_interrupt(obj, 1); + } else { + // DMA way + const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->spi.spi); + + PDMA_T *pdma_base = dma_modbase(); + + // Configure tx DMA + pdma_base->CHCTL |= 1 << obj->spi.dma_chn_id_tx; // Enable this DMA channel + PDMA_SetTransferMode(pdma_base, + obj->spi.dma_chn_id_tx, + ((struct nu_spi_var *) modinit->var)->pdma_perp_tx, // Peripheral connected to this PDMA + 0, // Scatter-gather disabled + 0); // Scatter-gather descriptor address + PDMA_SetTransferCnt(pdma_base, + obj->spi.dma_chn_id_tx, + (data_width == 8) ? PDMA_WIDTH_8 : (data_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32, + tx_length); + PDMA_SetTransferAddr(pdma_base, + obj->spi.dma_chn_id_tx, + (uint32_t) tx, // NOTE: + // NUC472: End of source address + // M451/M480/M2351/M251: Start of source address + PDMA_SAR_INC, // Source address incremental + (uint32_t) &spi_base->TX, // Destination address + PDMA_DAR_FIX); // Destination address fixed + PDMA_SetBurstType(pdma_base, + obj->spi.dma_chn_id_tx, + PDMA_REQ_SINGLE, // Single mode + 0); // Burst size + PDMA_EnableInt(pdma_base, + obj->spi.dma_chn_id_tx, + PDMA_INT_TRANS_DONE); // Interrupt type + // Register DMA event handler + dma_set_handler(obj->spi.dma_chn_id_tx, (uint32_t) spi_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL); + + // Configure rx DMA + pdma_base->CHCTL |= 1 << obj->spi.dma_chn_id_rx; // Enable this DMA channel + PDMA_SetTransferMode(pdma_base, + obj->spi.dma_chn_id_rx, + ((struct nu_spi_var *) modinit->var)->pdma_perp_rx, // Peripheral connected to this PDMA + 0, // Scatter-gather disabled + 0); // Scatter-gather descriptor address + PDMA_SetTransferCnt(pdma_base, + obj->spi.dma_chn_id_rx, + (data_width == 8) ? PDMA_WIDTH_8 : (data_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32, + rx_length); + PDMA_SetTransferAddr(pdma_base, + obj->spi.dma_chn_id_rx, + (uint32_t) &spi_base->RX, // Source address + PDMA_SAR_FIX, // Source address fixed + (uint32_t) rx, // NOTE: + // NUC472: End of destination address + // M451/M480/M2351/M251: Start of destination address + PDMA_DAR_INC); // Destination address incremental + PDMA_SetBurstType(pdma_base, + obj->spi.dma_chn_id_rx, + PDMA_REQ_SINGLE, // Single mode + 0); // Burst size + PDMA_EnableInt(pdma_base, + obj->spi.dma_chn_id_rx, + PDMA_INT_TRANS_DONE); // Interrupt type + // Register DMA event handler + dma_set_handler(obj->spi.dma_chn_id_rx, (uint32_t) spi_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL); + + /* Start tx/rx DMA transfer + * + * If we have both PDMA and SPI interrupts enabled and PDMA priority is lower than SPI priority, + * we would trap in SPI interrupt handler endlessly with the sequence: + * + * 1. PDMA TX transfer done interrupt occurs and is well handled. + * 2. SPI RX FIFO threshold interrupt occurs. Trap here because PDMA RX transfer done interrupt doesn't get handled. + * 3. PDMA RX transfer done interrupt occurs but it cannot be handled due to above. + * + * To fix it, we don't enable SPI TX/RX threshold interrupts but keep SPI vector handler set to be called + * in PDMA TX/RX transfer done interrupt handlers (spi_dma_handler_tx/spi_dma_handler_rx). + */ + NVIC_SetVector(modinit->irq_n, handler); + + /* Order to enable PDMA TX/RX functions + * + * H/W spec: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are + * enabled, RX PDMA function cannot be enabled prior to TX PDMA function. User can enable + * TX PDMA function firstly or enable both functions simultaneously. + * Per real test, it is safer to start RX PDMA first and then TX PDMA. Otherwise, receive FIFO is + * subject to overflow by TX DMA. + * + * With the above conflicts, we enable PDMA TX/RX functions simultaneously. + */ + spi_base->PDMACTL |= (SPI_PDMACTL_TXPDMAEN_Msk | SPI_PDMACTL_RXPDMAEN_Msk); + + /* Don't enable SPI TX/RX threshold interrupts as commented above */ + } +} + +/** + * Abort an SPI transfer + * This is a helper function for event handling. When any of the events listed occurs, the HAL will abort any ongoing + * transfers + * @param[in] obj The SPI peripheral to stop + */ +void spi_abort_asynch(spi_t *obj) +{ + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + PDMA_T *pdma_base = dma_modbase(); + + if (obj->spi.dma_usage != DMA_USAGE_NEVER) { + // Receive FIFO Overrun in case of tx length > rx length on DMA way + if (spi_base->STATUS & SPI_STATUS_RXOVIF_Msk) { + spi_base->STATUS = SPI_STATUS_RXOVIF_Msk; + } + + if (obj->spi.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) { + PDMA_DisableInt(pdma_base, obj->spi.dma_chn_id_tx, PDMA_INT_TRANS_DONE); + // NOTE: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown. + pdma_base->CHCTL &= ~(1 << obj->spi.dma_chn_id_tx); + } + SPI_DISABLE_TX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi))); + + if (obj->spi.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) { + PDMA_DisableInt(pdma_base, obj->spi.dma_chn_id_rx, PDMA_INT_TRANS_DONE); + // NOTE: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown. + pdma_base->CHCTL &= ~(1 << obj->spi.dma_chn_id_rx); + } + SPI_DISABLE_RX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi))); + } + + // Necessary for both interrupt way and DMA way + spi_enable_vector_interrupt(obj, 0, 0); + spi_master_enable_interrupt(obj, 0); + + /* Necessary for accessing FIFOCTL below */ + SPI_DISABLE_SYNC(spi_base); + + SPI_ClearRxFIFO(spi_base); + SPI_ClearTxFIFO(spi_base); +} + +/** + * Handle the SPI interrupt + * Read frames until the RX FIFO is empty. Write at most as many frames as were read. This way, + * it is unlikely that the RX FIFO will overflow. + * @param[in] obj The SPI peripheral that generated the interrupt + * @return + */ +uint32_t spi_irq_handler_asynch(spi_t *obj) +{ + // Check for SPI events + uint32_t event = spi_event_check(obj); + if (event) { + spi_abort_asynch(obj); + } + + return (obj->spi.event & event) | ((event & SPI_EVENT_COMPLETE) ? SPI_EVENT_INTERNAL_TRANSFER_COMPLETE : 0); +} + +uint8_t spi_active(spi_t *obj) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->spi.spi); + + /* Vector will be cleared when asynchronous transfer is finished or aborted. + Use it to judge if asynchronous transfer is on-going. */ + uint32_t vec = NVIC_GetVector(modinit->irq_n); + return vec ? 1 : 0; +} + +static int spi_writeable(spi_t * obj) +{ + // Receive FIFO must not be full to avoid receive FIFO overflow on next transmit/receive + return (! SPI_GET_TX_FIFO_FULL_FLAG(((SPI_T *) NU_MODBASE(obj->spi.spi)))); +} + +static int spi_readable(spi_t * obj) +{ + return ! SPI_GET_RX_FIFO_EMPTY_FLAG(((SPI_T *) NU_MODBASE(obj->spi.spi))); +} + +static void spi_enable_event(spi_t *obj, uint32_t event, uint8_t enable) +{ + obj->spi.event &= ~SPI_EVENT_ALL; + obj->spi.event |= (event & SPI_EVENT_ALL); + if (event & SPI_EVENT_RX_OVERFLOW) { + SPI_EnableInt((SPI_T *) NU_MODBASE(obj->spi.spi), SPI_FIFO_RXOV_INT_MASK); + } +} + +static void spi_enable_vector_interrupt(spi_t *obj, uint32_t handler, uint8_t enable) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->spi.spi); + + if (enable) { + NVIC_SetVector(modinit->irq_n, handler); + NVIC_EnableIRQ(modinit->irq_n); + } else { + NVIC_DisableIRQ(modinit->irq_n); + NVIC_SetVector(modinit->irq_n, 0); + } +} + +static void spi_master_enable_interrupt(spi_t *obj, uint8_t enable) +{ + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + + if (enable) { + uint32_t fifo_depth = spi_fifo_depth(obj); + SPI_SetFIFO(spi_base, fifo_depth / 2, fifo_depth / 2); + // Enable tx/rx FIFO threshold interrupt + SPI_EnableInt(spi_base, SPI_FIFO_RXTH_INT_MASK | SPI_FIFO_TXTH_INT_MASK); + } else { + SPI_DisableInt(spi_base, SPI_FIFO_RXTH_INT_MASK | SPI_FIFO_TXTH_INT_MASK); + } +} + +static uint32_t spi_event_check(spi_t *obj) +{ + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + uint32_t event = 0; + + if (obj->spi.dma_usage == DMA_USAGE_NEVER) { + uint32_t n_rec = spi_master_read_asynch(obj); + spi_master_write_asynch(obj, n_rec); + } + + if (spi_is_tx_complete(obj) && spi_is_rx_complete(obj)) { + event |= SPI_EVENT_COMPLETE; + } + + // Receive FIFO Overrun + if (spi_base->STATUS & SPI_STATUS_RXOVIF_Msk) { + spi_base->STATUS = SPI_STATUS_RXOVIF_Msk; + // In case of tx length > rx length on DMA way + if (obj->spi.dma_usage == DMA_USAGE_NEVER) { + event |= SPI_EVENT_RX_OVERFLOW; + } + } + + // Receive Time-Out + if (spi_base->STATUS & SPI_STATUS_RXTOIF_Msk) { + spi_base->STATUS = SPI_STATUS_RXTOIF_Msk; + // Not using this IF. Just clear it. + } + // Transmit FIFO Under-Run + if (spi_base->STATUS & SPI_STATUS_TXUFIF_Msk) { + spi_base->STATUS = SPI_STATUS_TXUFIF_Msk; + event |= SPI_EVENT_ERROR; + } + + return event; +} + +/** + * Send words from the SPI TX buffer until the send limit is reached or the TX FIFO is full + * tx_limit is provided to ensure that the number of SPI frames (words) in flight can be managed. + * @param[in] obj The SPI object on which to operate + * @param[in] tx_limit The maximum number of words to send + * @return The number of SPI words that have been transfered + */ +static uint32_t spi_master_write_asynch(spi_t *obj, uint32_t tx_limit) +{ + uint32_t n_words = 0; + uint32_t tx_rmn = obj->tx_buff.length - obj->tx_buff.pos; + uint32_t rx_rmn = obj->rx_buff.length - obj->rx_buff.pos; + uint32_t max_tx = NU_MAX(tx_rmn, rx_rmn); + max_tx = NU_MIN(max_tx, tx_limit); + uint8_t data_width = spi_get_data_width(obj); + uint8_t bytes_per_word = (data_width + 7) / 8; + uint8_t *tx = (uint8_t *)(obj->tx_buff.buffer) + bytes_per_word * obj->tx_buff.pos; + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + + while ((n_words < max_tx) && spi_writeable(obj)) { + if (spi_is_tx_complete(obj)) { + // Transmit dummy as transmit buffer is empty + SPI_WRITE_TX(spi_base, 0); + } else { + switch (bytes_per_word) { + case 4: + SPI_WRITE_TX(spi_base, nu_get32_le(tx)); + tx += 4; + break; + case 2: + SPI_WRITE_TX(spi_base, nu_get16_le(tx)); + tx += 2; + break; + case 1: + SPI_WRITE_TX(spi_base, *((uint8_t *) tx)); + tx += 1; + break; + } + + obj->tx_buff.pos ++; + } + n_words ++; + } + + //Return the number of words that have been sent + return n_words; +} + +/** + * Read SPI words out of the RX FIFO + * Continues reading words out of the RX FIFO until the following condition is met: + * o There are no more words in the FIFO + * OR BOTH OF: + * o At least as many words as the TX buffer have been received + * o At least as many words as the RX buffer have been received + * This way, RX overflows are not generated when the TX buffer size exceeds the RX buffer size + * @param[in] obj The SPI object on which to operate + * @return Returns the number of words extracted from the RX FIFO + */ +static uint32_t spi_master_read_asynch(spi_t *obj) +{ + uint32_t n_words = 0; + uint32_t tx_rmn = obj->tx_buff.length - obj->tx_buff.pos; + uint32_t rx_rmn = obj->rx_buff.length - obj->rx_buff.pos; + uint32_t max_rx = NU_MAX(tx_rmn, rx_rmn); + uint8_t data_width = spi_get_data_width(obj); + uint8_t bytes_per_word = (data_width + 7) / 8; + uint8_t *rx = (uint8_t *)(obj->rx_buff.buffer) + bytes_per_word * obj->rx_buff.pos; + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + + while ((n_words < max_rx) && spi_readable(obj)) { + if (spi_is_rx_complete(obj)) { + // Disregard as receive buffer is full + SPI_READ_RX(spi_base); + } else { + switch (bytes_per_word) { + case 4: { + uint32_t val = SPI_READ_RX(spi_base); + nu_set32_le(rx, val); + rx += 4; + break; + } + case 2: { + uint16_t val = SPI_READ_RX(spi_base); + nu_set16_le(rx, val); + rx += 2; + break; + } + case 1: + *rx ++ = SPI_READ_RX(spi_base); + break; + } + + obj->rx_buff.pos ++; + } + n_words ++; + } + + // Return the number of words received + return n_words; +} + +static void spi_buffer_set(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length) +{ + obj->tx_buff.buffer = (void *) tx; + obj->tx_buff.length = tx_length; + obj->tx_buff.pos = 0; + obj->tx_buff.width = spi_get_data_width(obj); + obj->rx_buff.buffer = rx; + obj->rx_buff.length = rx_length; + obj->rx_buff.pos = 0; + obj->rx_buff.width = spi_get_data_width(obj); +} + +static void spi_check_dma_usage(DMAUsage *dma_usage, int *dma_ch_tx, int *dma_ch_rx) +{ + if (*dma_usage != DMA_USAGE_NEVER) { + if (*dma_ch_tx == DMA_ERROR_OUT_OF_CHANNELS) { + *dma_ch_tx = dma_channel_allocate(DMA_CAP_NONE); + } + if (*dma_ch_rx == DMA_ERROR_OUT_OF_CHANNELS) { + *dma_ch_rx = dma_channel_allocate(DMA_CAP_NONE); + } + + if (*dma_ch_tx == DMA_ERROR_OUT_OF_CHANNELS || *dma_ch_rx == DMA_ERROR_OUT_OF_CHANNELS) { + *dma_usage = DMA_USAGE_NEVER; + } + } + + if (*dma_usage == DMA_USAGE_NEVER) { + dma_channel_free(*dma_ch_tx); + *dma_ch_tx = DMA_ERROR_OUT_OF_CHANNELS; + dma_channel_free(*dma_ch_rx); + *dma_ch_rx = DMA_ERROR_OUT_OF_CHANNELS; + } +} + +static uint8_t spi_get_data_width(spi_t *obj) +{ + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + + uint32_t data_width = ((spi_base->CTL & SPI_CTL_DWIDTH_Msk) >> SPI_CTL_DWIDTH_Pos); + if (data_width == 0) { + data_width = 32; + } + + return data_width; +} + +static int spi_is_tx_complete(spi_t *obj) +{ + return (obj->tx_buff.pos == obj->tx_buff.length); +} + +static int spi_is_rx_complete(spi_t *obj) +{ + return (obj->rx_buff.pos == obj->rx_buff.length); +} + +static void spi_dma_handler_tx(uint32_t id, uint32_t event_dma) +{ + spi_t *obj = (spi_t *) id; + + // FIXME: Pass this error to caller + if (event_dma & DMA_EVENT_ABORT) { + } + // Expect SPI IRQ will catch this transfer done event + if (event_dma & DMA_EVENT_TRANSFER_DONE) { + obj->tx_buff.pos = obj->tx_buff.length; + } + // FIXME: Pass this error to caller + if (event_dma & DMA_EVENT_TIMEOUT) { + } + + const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->spi.spi); + + void (*vec)(void) = (void (*)(void)) NVIC_GetVector(modinit->irq_n); + vec(); +} + +static void spi_dma_handler_rx(uint32_t id, uint32_t event_dma) +{ + spi_t *obj = (spi_t *) id; + + // FIXME: Pass this error to caller + if (event_dma & DMA_EVENT_ABORT) { + } + // Expect SPI IRQ will catch this transfer done event + if (event_dma & DMA_EVENT_TRANSFER_DONE) { + obj->rx_buff.pos = obj->rx_buff.length; + } + // FIXME: Pass this error to caller + if (event_dma & DMA_EVENT_TIMEOUT) { + } + + const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->spi.spi); + + void (*vec)(void) = (void (*)(void)) NVIC_GetVector(modinit->irq_n); + vec(); +} + +/* Return FIFO depth of the SPI peripheral */ +static uint32_t spi_fifo_depth(spi_t *obj) +{ + return 4; +} + +#endif + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M251/trng_api.c b/targets/TARGET_NUVOTON/TARGET_M251/trng_api.c new file mode 100644 index 00000000000..d67e563e409 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/trng_api.c @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2019, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if DEVICE_TRNG + +#include +#include +#include "cmsis.h" +#include "us_ticker_api.h" +#include "trng_api.h" +#include "crypto-misc.h" + +/* + * Get Random number generator. + */ + +#define PRNG_KEY_SIZE (0x20UL) + +static void trng_get(unsigned char *pConversionData) +{ + uint32_t *p32ConversionData; + + p32ConversionData = (uint32_t *)pConversionData; + + PRNG_Open(CRYPTO_MODBASE(), PRNG_KEY_SIZE_256, 1, us_ticker_read()); + crypto_prng_prestart(); + PRNG_Start(CRYPTO_MODBASE()); + crypto_prng_wait(); + + PRNG_Read(CRYPTO_MODBASE(), p32ConversionData); +} + +void trng_init(trng_t *obj) +{ + (void)obj; + + /* Init crypto module */ + crypto_init(); + + PRNG_ENABLE_INT(CRYPTO_MODBASE()); +} + +void trng_free(trng_t *obj) +{ + (void)obj; + + PRNG_DISABLE_INT(CRYPTO_MODBASE()); + + /* Uninit crypto module */ + crypto_uninit(); +} + +int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length) +{ + (void)obj; + unsigned char tmpBuff[PRNG_KEY_SIZE]; + size_t cur_length = 0; + + while (length >= sizeof(tmpBuff)) { + trng_get(output); + output += sizeof(tmpBuff); + cur_length += sizeof(tmpBuff); + length -= sizeof(tmpBuff); + } + if (length > 0) { + trng_get(tmpBuff); + memcpy(output, tmpBuff, length); + cur_length += length; + crypto_zeroize(tmpBuff, sizeof(tmpBuff)); + } + *output_length = cur_length; + return 0; +} + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M251/us_ticker.c b/targets/TARGET_NUVOTON/TARGET_M251/us_ticker.c new file mode 100644 index 00000000000..358fe2832dd --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/us_ticker.c @@ -0,0 +1,180 @@ +/* + * Copyright (c) 2019, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "us_ticker_api.h" + +#if DEVICE_USTICKER + +#include "sleep_api.h" +#include "mbed_assert.h" +#include "nu_modutil.h" +#include "nu_miscutil.h" + +/* Micro seconds per second */ +#define NU_US_PER_SEC 1000000 +/* Timer clock per us_ticker tick */ +#define NU_TMRCLK_PER_TICK 1 +/* Timer clock per second */ +#define NU_TMRCLK_PER_SEC (1000 * 1000) +/* Timer max counter bit size */ +#define NU_TMR_MAXCNT_BITSIZE 24 +/* Timer max counter */ +#define NU_TMR_MAXCNT ((1 << NU_TMR_MAXCNT_BITSIZE) - 1) + +static void tmr0_vec(void); + +static const struct nu_modinit_s timer0_modinit = {TIMER_0, TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_PCLK0, 0, TMR0_RST, TMR0_IRQn, (void *) tmr0_vec}; + +#define TIMER_MODINIT timer0_modinit + +/* Track ticker status */ +static volatile uint16_t ticker_inited = 0; + +#define TMR_CMP_MIN 2 +#define TMR_CMP_MAX 0xFFFFFFu + +void us_ticker_init(void) +{ + if (ticker_inited) { + /* By HAL spec, ticker_init allows the ticker to keep counting and disables the + * ticker interrupt. */ + us_ticker_disable_interrupt(); + return; + } + ticker_inited = 1; + + // Reset IP + SYS_ResetModule(TIMER_MODINIT.rsetidx); + + // Select IP clock source + CLK_SetModuleClock(TIMER_MODINIT.clkidx, TIMER_MODINIT.clksrc, TIMER_MODINIT.clkdiv); + + // Enable IP clock + CLK_EnableModuleClock(TIMER_MODINIT.clkidx); + + TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); + + // Timer for normal counter + uint32_t clk_timer = TIMER_GetModuleClock(timer_base); + uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1; + MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127); + MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0); + uint32_t cmp_timer = TMR_CMP_MAX; + MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX); + // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480/M2351/M251. In M451/M480/M2351/M251, TIMER_CNT is updated continuously by default. + timer_base->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/; + timer_base->CMP = cmp_timer; + + NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var); + + NVIC_DisableIRQ(TIMER_MODINIT.irq_n); + + TIMER_EnableInt(timer_base); + + TIMER_Start(timer_base); + /* Wait for timer to start counting and raise active flag */ + while(! (timer_base->CTL & TIMER_CTL_ACTSTS_Msk)); +} + +void us_ticker_free(void) +{ + /* Disable interrupt */ + NVIC_DisableIRQ(TIMER_MODINIT.irq_n); + + /* Disable IP clock */ + CLK_DisableModuleClock(TIMER_MODINIT.clkidx); + + ticker_inited = 0; +} + +uint32_t us_ticker_read() +{ + if (! ticker_inited) { + us_ticker_init(); + } + + TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); + + return (TIMER_GetCounter(timer_base) / NU_TMRCLK_PER_TICK); +} + +void us_ticker_set_interrupt(timestamp_t timestamp) +{ + /* Clear any previously pending interrupts */ + us_ticker_clear_interrupt(); + NVIC_ClearPendingIRQ(TIMER_MODINIT.irq_n); + + /* In continuous mode, counter will be reset to zero with the following sequence: + * 1. Stop counting + * 2. Configure new CMP value + * 3. Restart counting + * + * This behavior is not what we want. To fix it, we could configure new CMP value + * without stopping counting first. + */ + TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); + + /* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of + * (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */ + uint32_t cmp_timer = timestamp * NU_TMRCLK_PER_TICK; + cmp_timer = NU_CLAMP(cmp_timer, TMR_CMP_MIN, TMR_CMP_MAX); + timer_base->CMP = cmp_timer; + + /* We can call ticker_irq_handler now. */ + NVIC_EnableIRQ(TIMER_MODINIT.irq_n); +} + +void us_ticker_disable_interrupt(void) +{ + /* We cannot call ticker_irq_handler now. */ + NVIC_DisableIRQ(TIMER_MODINIT.irq_n); +} + +void us_ticker_clear_interrupt(void) +{ + TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); +} + +void us_ticker_fire_interrupt(void) +{ + // NOTE: This event was in the past. Set the interrupt as pending, but don't process it here. + // This prevents a recursive loop under heavy load which can lead to a stack overflow. + NVIC_SetPendingIRQ(TIMER_MODINIT.irq_n); + + /* We can call ticker_irq_handler now. */ + NVIC_EnableIRQ(TIMER_MODINIT.irq_n); +} + +const ticker_info_t* us_ticker_get_info() +{ + static const ticker_info_t info = { + NU_TMRCLK_PER_SEC / NU_TMRCLK_PER_TICK, + NU_TMR_MAXCNT_BITSIZE + }; + return &info; +} + +static void tmr0_vec(void) +{ + us_ticker_clear_interrupt(); + + // NOTE: us_ticker_set_interrupt() may get called in us_ticker_irq_handler(); + us_ticker_irq_handler(); +} + +#endif diff --git a/targets/targets.json b/targets/targets.json index dc258bb9f64..4266274b3c2 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -8828,6 +8828,81 @@ "mbed_ram_start" : "0x20000000", "mbed_ram_size" : "0x8000" }, + "NUMAKER_M252KG": { + "core": "Cortex-M23", + "trustzone": false, + "is_disk_virtual": true, + "default_toolchain": "ARMC6", + "extra_labels": [ + "NUVOTON", + "M251", + "M252KG6AE", + "FLASH_CMSIS_ALGO" + ], + "macros_add": [ + "MBED_FAULT_HANDLER_DISABLED", + "LPTICKER_DELAY_TICKS=3" + ], + "supported_toolchains": ["ARMC6", "GCC_ARM", "IAR"], + "config": { + "gpio-irq-debounce-enable": { + "help": "Enable GPIO IRQ debounce", + "value": 0 + }, + "gpio-irq-debounce-enable-list": { + "help": "Comma separated pin list to enable GPIO IRQ debounce", + "value": "NC" + }, + "gpio-irq-debounce-clock-source": { + "help": "Select GPIO IRQ debounce clock source: GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC", + "value": "GPIO_DBCTL_DBCLKSRC_LIRC" + }, + "gpio-irq-debounce-sample-rate": { + "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCTL_DBCLKSEL_1, GPIO_DBCTL_DBCLKSEL_2, GPIO_DBCTL_DBCLKSEL_4, ..., or GPIO_DBCTL_DBCLKSEL_32768", + "value": "GPIO_DBCTL_DBCLKSEL_16" + }, + "hxt-enable": { + "help": "Enable external high-speed crystal (HXT)", + "value": 0, + "macro_name": "NU_HXT_ENABLE" + } + }, + "overrides": { + "tickless-from-us-ticker": true + }, + "inherits": ["Target"], + "device_has": [ + "USTICKER", + "LPTICKER", + "RTC", + "ANALOGIN", + "ANALOGOUT", + "I2C", + "I2CSLAVE", + "I2C_ASYNCH", + "INTERRUPTIN", + "PORTIN", + "PORTINOUT", + "PORTOUT", + "PWMOUT", + "SERIAL", + "SERIAL_ASYNCH", + "SERIAL_FC", + "STDIO_MESSAGES", + "SLEEP", + "SPI", + "SPISLAVE", + "SPI_ASYNCH", + "TRNG", + "FLASH", + "MPU" + ], + "components_add": ["FLASHIAP"], + "detect_code": ["1309"], + "release_versions": ["2", "5"], + "device_name": "M252KG6AE", + "bootloader_supported": true + }, "TMPM3H6": { "inherits": ["Target"], "core": "Cortex-M3", From 9b6edba26c01ea71ef0a00f93253ff3e8a330b6f Mon Sep 17 00:00:00 2001 From: Chun-Chieh Li Date: Mon, 8 Jul 2019 15:55:50 +0800 Subject: [PATCH 191/227] Override mpu-rom-end to 0x1fffffff MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Without this override, mpu hal will require 5 mpu regions which exceed 4 mpu regions supported by M252 (see hal/mpu/mbed_mpu_v8m.c). In this scenario, we will hit assert error but we actually meet stack overrun first due to just 0x400 bytes for emitting error message. The issue doesn’t occur on other targets such as M487 because it has 8 mpu regions. --- targets/targets.json | 1 + 1 file changed, 1 insertion(+) diff --git a/targets/targets.json b/targets/targets.json index 4266274b3c2..b9fb26b12b1 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -8868,6 +8868,7 @@ } }, "overrides": { + "mpu-rom-end": "0x1fffffff", "tickless-from-us-ticker": true }, "inherits": ["Target"], From 7c48b44488c158a986ee94adb42ce01f5bac7202 Mon Sep 17 00:00:00 2001 From: Chun-Chieh Li Date: Mon, 8 Jul 2019 15:47:05 +0800 Subject: [PATCH 192/227] Enlarge required deep sleep latency This configuration is to pass wake-up from deep-sleep test such as mbedmicro-rtos-mbed-systimer. --- targets/targets.json | 1 + 1 file changed, 1 insertion(+) diff --git a/targets/targets.json b/targets/targets.json index b9fb26b12b1..02ef8dfb63b 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -8869,6 +8869,7 @@ }, "overrides": { "mpu-rom-end": "0x1fffffff", + "deep-sleep-latency": 1, "tickless-from-us-ticker": true }, "inherits": ["Target"], From b6a29934e8ee99c73843f1016dd397c7f8d957a9 Mon Sep 17 00:00:00 2001 From: Chun-Chieh Li Date: Tue, 9 Jul 2019 15:57:18 +0800 Subject: [PATCH 193/227] Enlarge LPTICKER_DELAY_TICKS for safe On Nuvoton targets, lp_ticker_set_interrupt(...) needs around 3 lp-ticker ticks to take effect. It may miss when current tick and match tick are very close (see hal/LowPowerTickerWrapper.cpp). Enlarge LPTICKER_DELAY_TICKS to 4 from 3 to address this boundary case. --- targets/targets.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/targets.json b/targets/targets.json index 02ef8dfb63b..381562ed761 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -8841,7 +8841,7 @@ ], "macros_add": [ "MBED_FAULT_HANDLER_DISABLED", - "LPTICKER_DELAY_TICKS=3" + "LPTICKER_DELAY_TICKS=4" ], "supported_toolchains": ["ARMC6", "GCC_ARM", "IAR"], "config": { From 7245474e403e0084964e51052dc63fcd41a24f3f Mon Sep 17 00:00:00 2001 From: Chun-Chieh Li Date: Thu, 8 Aug 2019 09:57:05 +0800 Subject: [PATCH 194/227] Add 'sectors' target configuration parameter --- targets/targets.json | 1 + 1 file changed, 1 insertion(+) diff --git a/targets/targets.json b/targets/targets.json index 381562ed761..0ad7cad1ad6 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -8903,6 +8903,7 @@ "detect_code": ["1309"], "release_versions": ["2", "5"], "device_name": "M252KG6AE", + "sectors": [[0,512]], "bootloader_supported": true }, "TMPM3H6": { From a56db3697dbb0588bfe94bd47095797e38db11e0 Mon Sep 17 00:00:00 2001 From: Chun-Chieh Li Date: Tue, 30 Jul 2019 13:12:46 +0800 Subject: [PATCH 195/227] Force enum PinName to 32-bit NU_PINNAME_BIND(...) requires enum PinName to be 32-bit to encode module binding information in it. --- targets/TARGET_NUVOTON/TARGET_M251/PinNames.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/targets/TARGET_NUVOTON/TARGET_M251/PinNames.h b/targets/TARGET_NUVOTON/TARGET_M251/PinNames.h index f7af3cf2d28..aa1d0f8470b 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/PinNames.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/PinNames.h @@ -126,6 +126,9 @@ typedef enum { LED4 = LED1, // No real LED. Just for passing ATS. /* Button naming */ + + /* Force PinName to 32-bit required by NU_PINNAME_BIND(...) */ + FORCE_ENUM_PINNAME_32BIT = 0x7FFFFFFF, } PinName; From 3cdf84d943bf9f42475104db8fb1d29ba2cf8d6e Mon Sep 17 00:00:00 2001 From: Chun-Chieh Li Date: Tue, 30 Jul 2019 13:17:27 +0800 Subject: [PATCH 196/227] Exclude USB UART from testing USB UART is dedicated to USB COM and so must exclude from FPGA CI testing. --- targets/TARGET_NUVOTON/TARGET_M251/pinmap.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/targets/TARGET_NUVOTON/TARGET_M251/pinmap.c b/targets/TARGET_NUVOTON/TARGET_M251/pinmap.c index b058fa5d7f2..f18e3913a04 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/pinmap.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/pinmap.c @@ -19,6 +19,7 @@ #include "mbed_assert.h" #include "pinmap.h" #include "PortNames.h" +#include "PeripheralNames.h" #include "mbed_error.h" /** @@ -82,3 +83,18 @@ void pin_mode(PinName pin, PinMode mode) * 2. PushPullOutput/PIN_INPUT */ } + +/* List of peripherals excluded from testing */ +const PeripheralList *pinmap_restricted_peripherals() +{ + static const int perifs[] = { + STDIO_UART // Dedicated to USB VCOM + }; + + static const PeripheralList peripheral_list = { + sizeof(perifs) / sizeof(perifs[0]), + perifs + }; + + return &peripheral_list; +} From a5b704866869b82aec6066bbb012eab0f91ba93c Mon Sep 17 00:00:00 2001 From: Chun-Chieh Li Date: Tue, 30 Jul 2019 13:37:44 +0800 Subject: [PATCH 197/227] Fix IP initialization sequence Better IP initialization sequence: 1. Configure IP pins 2. Select IP clock source and then enable it 3. Reset the IP (SYS_ResetModule) NOTE1: IP reset takes effect regardless of IP clock. So it doesn't matter if IP clock enable is before IP reset. NOTE2: Non-configured pins may disturb IP's state, so IP pinout first and then IP reset. NOTE3: IP reset at the end of IP initialization sequence can cover unexpected situation. --- targets/TARGET_NUVOTON/TARGET_M251/analogin_api.c | 12 ++++++------ targets/TARGET_NUVOTON/TARGET_M251/analogout_api.c | 14 +++++++------- targets/TARGET_NUVOTON/TARGET_M251/dma_api.c | 6 +++--- targets/TARGET_NUVOTON/TARGET_M251/i2c_api.c | 8 ++++---- targets/TARGET_NUVOTON/TARGET_M251/lp_ticker.c | 6 +++--- targets/TARGET_NUVOTON/TARGET_M251/pwmout_api.c | 14 +++++++------- targets/TARGET_NUVOTON/TARGET_M251/serial_api.c | 8 ++++---- targets/TARGET_NUVOTON/TARGET_M251/spi_api.c | 12 ++++++------ targets/TARGET_NUVOTON/TARGET_M251/us_ticker.c | 6 +++--- 9 files changed, 43 insertions(+), 43 deletions(-) diff --git a/targets/TARGET_NUVOTON/TARGET_M251/analogin_api.c b/targets/TARGET_NUVOTON/TARGET_M251/analogin_api.c index 087be9ab52c..256b8399725 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/analogin_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/analogin_api.c @@ -55,19 +55,22 @@ void analogin_init(analogin_t *obj, PinName pin) MBED_ASSERT(modinit != NULL); MBED_ASSERT(modinit->modname == (int) obj->adc); + // Wire pinout + pinmap_pinout(pin, PinMap_ADC); + EADC_T *eadc_base = (EADC_T *) NU_MODBASE(obj->adc); // NOTE: All channels (identified by ADCName) share a ADC module. This reset will also affect other channels of the same ADC module. if (! eadc_modinit_mask) { - // Reset this module if no channel enabled - SYS_ResetModule(modinit->rsetidx); - // Select clock source CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv); // Enable clock CLK_EnableModuleClock(modinit->clkidx); + // Reset this module if no channel enabled + SYS_ResetModule(modinit->rsetidx); + /* Configure EADC_module to be ready to convert * M251 doesn't support 'input mode' feature. Configure it to 0. */ EADC_Open(eadc_base, 0); @@ -75,9 +78,6 @@ void analogin_init(analogin_t *obj, PinName pin) uint32_t chn = NU_MODSUBINDEX(obj->adc); - // Wire pinout - pinmap_pinout(pin, PinMap_ADC); - // Configure the sample module Nmod for analog input channel Nch and software trigger source EADC_ConfigSampleModule(eadc_base, chn, EADC_SOFTWARE_TRIGGER, chn); diff --git a/targets/TARGET_NUVOTON/TARGET_M251/analogout_api.c b/targets/TARGET_NUVOTON/TARGET_M251/analogout_api.c index e80b020c336..b12775a9858 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/analogout_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/analogout_api.c @@ -53,20 +53,23 @@ void analogout_init(dac_t *obj, PinName pin) uint32_t chn = NU_MODSUBINDEX(obj->dac); MBED_ASSERT(chn < NU_DACCHN_MAXNUM); + /* Wire pinout */ + pinmap_pinout(pin, PinMap_DAC); + DAC_T *dac_base = (DAC_T *) NU_MODBASE(obj->dac); /* Module-level setup from here */ - if (! dac_modinit_mask[modidx]) { - /* Reset IP */ - SYS_ResetModule(modinit->rsetidx); - + if (! dac_modinit_mask[modidx]) { /* Select IP clock source and clock divider */ CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv); /* Enable IP clock */ CLK_EnableModuleClock(modinit->clkidx); + /* Reset IP */ + SYS_ResetModule(modinit->rsetidx); + /* The conversion settling time is 6us when 12-bit input code transition from * lowest code (0x000) to highest code (0xFFF). */ DAC_SetDelayTime(dac_base, 6); @@ -80,9 +83,6 @@ void analogout_init(dac_t *obj, PinName pin) /* Set the software trigger, enable DAC event trigger mode and enable D/A converter */ DAC_Open(dac_base, chn, DAC_SOFTWARE_TRIGGER); - - /* Wire pinout */ - pinmap_pinout(pin, PinMap_DAC); /* Mark channel allocated */ dac_modinit_mask[modidx] |= 1 << chn; diff --git a/targets/TARGET_NUVOTON/TARGET_M251/dma_api.c b/targets/TARGET_NUVOTON/TARGET_M251/dma_api.c index a8a23b0573d..84071180439 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/dma_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/dma_api.c @@ -52,12 +52,12 @@ void dma_init(void) dma_chn_mask = ~NU_PDMA_CH_Msk; memset(dma_chn_arr, 0x00, sizeof (dma_chn_arr)); - /* Reset module */ - SYS_ResetModule(dma_modinit.rsetidx); - /* Enable IP clock */ CLK_EnableModuleClock(dma_modinit.clkidx); + /* Reset module */ + SYS_ResetModule(dma_modinit.rsetidx); + PDMA_T *pdma_base = dma_modbase(); PDMA_Open(pdma_base, 0); diff --git a/targets/TARGET_NUVOTON/TARGET_M251/i2c_api.c b/targets/TARGET_NUVOTON/TARGET_M251/i2c_api.c index d91b77b35f9..bf82c12a6b7 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/i2c_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/i2c_api.c @@ -98,14 +98,14 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) MBED_ASSERT(modinit != NULL); MBED_ASSERT(modinit->modname == (int) obj->i2c.i2c); - // Reset this module - SYS_ResetModule(modinit->rsetidx); + pinmap_pinout(sda, PinMap_I2C_SDA); + pinmap_pinout(scl, PinMap_I2C_SCL); // Enable IP clock CLK_EnableModuleClock(modinit->clkidx); - pinmap_pinout(sda, PinMap_I2C_SDA); - pinmap_pinout(scl, PinMap_I2C_SCL); + // Reset this module + SYS_ResetModule(modinit->rsetidx); #if DEVICE_I2C_ASYNCH obj->i2c.dma_usage = DMA_USAGE_NEVER; diff --git a/targets/TARGET_NUVOTON/TARGET_M251/lp_ticker.c b/targets/TARGET_NUVOTON/TARGET_M251/lp_ticker.c index ffa7fb40375..c05d1054ba8 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/lp_ticker.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/lp_ticker.c @@ -82,15 +82,15 @@ void lp_ticker_init(void) } ticker_inited = 1; - // Reset module - SYS_ResetModule(TIMER_MODINIT.rsetidx); - // Select IP clock source CLK_SetModuleClock(TIMER_MODINIT.clkidx, TIMER_MODINIT.clksrc, TIMER_MODINIT.clkdiv); // Enable IP clock CLK_EnableModuleClock(TIMER_MODINIT.clkidx); + // Reset module + SYS_ResetModule(TIMER_MODINIT.rsetidx); + TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); // Configure clock diff --git a/targets/TARGET_NUVOTON/TARGET_M251/pwmout_api.c b/targets/TARGET_NUVOTON/TARGET_M251/pwmout_api.c index da09a7ff3be..0b489d1caa6 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/pwmout_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/pwmout_api.c @@ -70,11 +70,8 @@ void pwmout_init(pwmout_t* obj, PinName pin) MBED_ASSERT(modinit != NULL); MBED_ASSERT(modinit->modname == (int) obj->pwm); - // NOTE: All channels (identified by PWMName) share a PWM module. This reset will also affect other channels of the same PWM module. - if (! ((struct nu_pwm_var *) modinit->var)->en_msk) { - // Reset this module if no channel enabled - SYS_ResetModule(modinit->rsetidx); - } + // Wire pinout + pinmap_pinout(pin, PinMap_PWM); uint32_t chn = NU_MODSUBINDEX(obj->pwm); @@ -86,8 +83,11 @@ void pwmout_init(pwmout_t* obj, PinName pin) CLK_EnableModuleClock(modinit->clkidx); } - // Wire pinout - pinmap_pinout(pin, PinMap_PWM); + // NOTE: All channels (identified by PWMName) share a PWM module. This reset will also affect other channels of the same PWM module. + if (! ((struct nu_pwm_var *) modinit->var)->en_msk) { + // Reset this module if no channel enabled + SYS_ResetModule(modinit->rsetidx); + } // Default: period = 10 ms, pulse width = 0 ms obj->period_us = 1000 * 10; diff --git a/targets/TARGET_NUVOTON/TARGET_M251/serial_api.c b/targets/TARGET_NUVOTON/TARGET_M251/serial_api.c index fab0bf58505..971b2e61585 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/serial_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/serial_api.c @@ -156,16 +156,16 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; if (! var->ref_cnt) { - // Reset this module - SYS_ResetModule(modinit->rsetidx); + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); // Select IP clock source CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv); // Enable IP clock CLK_EnableModuleClock(modinit->clkidx); - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); + // Reset this module + SYS_ResetModule(modinit->rsetidx); // Configure baudrate int baudrate = 9600; diff --git a/targets/TARGET_NUVOTON/TARGET_M251/spi_api.c b/targets/TARGET_NUVOTON/TARGET_M251/spi_api.c index 0e5d5cad80b..a72ae85a822 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/spi_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/spi_api.c @@ -120,18 +120,18 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel MBED_ASSERT(modinit != NULL); MBED_ASSERT(modinit->modname == (int) obj->spi.spi); - // Reset this module - SYS_ResetModule(modinit->rsetidx); + pinmap_pinout(mosi, PinMap_SPI_MOSI); + pinmap_pinout(miso, PinMap_SPI_MISO); + pinmap_pinout(sclk, PinMap_SPI_SCLK); + pinmap_pinout(ssel, PinMap_SPI_SSEL); // Select IP clock source CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv); // Enable IP clock CLK_EnableModuleClock(modinit->clkidx); - pinmap_pinout(mosi, PinMap_SPI_MOSI); - pinmap_pinout(miso, PinMap_SPI_MISO); - pinmap_pinout(sclk, PinMap_SPI_SCLK); - pinmap_pinout(ssel, PinMap_SPI_SSEL); + // Reset this module + SYS_ResetModule(modinit->rsetidx); obj->spi.pin_mosi = mosi; obj->spi.pin_miso = miso; diff --git a/targets/TARGET_NUVOTON/TARGET_M251/us_ticker.c b/targets/TARGET_NUVOTON/TARGET_M251/us_ticker.c index 358fe2832dd..8aeca00bbea 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/us_ticker.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/us_ticker.c @@ -58,15 +58,15 @@ void us_ticker_init(void) } ticker_inited = 1; - // Reset IP - SYS_ResetModule(TIMER_MODINIT.rsetidx); - // Select IP clock source CLK_SetModuleClock(TIMER_MODINIT.clkidx, TIMER_MODINIT.clksrc, TIMER_MODINIT.clkdiv); // Enable IP clock CLK_EnableModuleClock(TIMER_MODINIT.clkidx); + // Reset IP + SYS_ResetModule(TIMER_MODINIT.rsetidx); + TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); // Timer for normal counter From 7f29545a57b4dfd46536aa8a33bb08b4e700da0f Mon Sep 17 00:00:00 2001 From: Chun-Chieh Li Date: Tue, 30 Jul 2019 13:50:51 +0800 Subject: [PATCH 198/227] Fix I2C NACK error Fix logic error on replying NACK at the end of transfer. This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-i2c/ i2c - test single byte read i2c API. --- targets/TARGET_NUVOTON/TARGET_M251/i2c_api.c | 34 ++++++++++++++++---- 1 file changed, 28 insertions(+), 6 deletions(-) diff --git a/targets/TARGET_NUVOTON/TARGET_M251/i2c_api.c b/targets/TARGET_NUVOTON/TARGET_M251/i2c_api.c index bf82c12a6b7..4f5a4d32149 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/i2c_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/i2c_api.c @@ -81,9 +81,10 @@ static void i2c_enable_vector_interrupt(i2c_t *obj, uint32_t handler, int enable static void i2c_rollback_vector_interrupt(i2c_t *obj); #endif -#define TRANCTRL_STARTED (1) -#define TRANCTRL_NAKLASTDATA (1 << 1) -#define TRANCTRL_LASTDATANAKED (1 << 2) +#define TRANCTRL_STARTED (1) // Guard I2C ISR from data transfer prematurely +#define TRANCTRL_NAKLASTDATA (1 << 1) // Request NACK on last data +#define TRANCTRL_LASTDATANAKED (1 << 2) // Last data NACKed +#define TRANCTRL_RECVDATA (1 << 3) // Receive data available uint32_t us_ticker_read(void); @@ -583,11 +584,17 @@ static void i2c_irq(i2c_t *obj) if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) { if (obj->i2c.tran_pos < obj->i2c.tran_end) { if (status == 0x50 || status == 0x58) { - *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base); + if (obj->i2c.tran_ctrl & TRANCTRL_RECVDATA) { + *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base); + obj->i2c.tran_ctrl &= ~TRANCTRL_RECVDATA; + } } if (status == 0x58) { i2c_fsm_tranfini(obj, 1); + } else if (obj->i2c.tran_pos == obj->i2c.tran_end) { + obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED; + i2c_disable_int(obj); } else { uint32_t i2c_ctl = I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk; if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 && @@ -596,6 +603,7 @@ static void i2c_irq(i2c_t *obj) i2c_ctl &= ~I2C_CTL0_AA_Msk; } I2C_SET_CONTROL_REG(i2c_base, i2c_ctl); + obj->i2c.tran_ctrl |= TRANCTRL_RECVDATA; } } else { obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED; @@ -650,12 +658,18 @@ static void i2c_irq(i2c_t *obj) if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) { if (obj->i2c.tran_pos < obj->i2c.tran_end) { if (status == 0x80 || status == 0x88) { - *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base); + if (obj->i2c.tran_ctrl & TRANCTRL_RECVDATA) { + *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base); + obj->i2c.tran_ctrl &= ~TRANCTRL_RECVDATA; + } } if (status == 0x88) { obj->i2c.slaveaddr_state = NoData; i2c_fsm_reset(obj, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk); + } else if (obj->i2c.tran_pos == obj->i2c.tran_end) { + obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED; + i2c_disable_int(obj); } else { uint32_t i2c_ctl = I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk; if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 && @@ -664,6 +678,7 @@ static void i2c_irq(i2c_t *obj) i2c_ctl &= ~I2C_CTL0_AA_Msk; } I2C_SET_CONTROL_REG(i2c_base, i2c_ctl); + obj->i2c.tran_ctrl |= TRANCTRL_RECVDATA; } } else { obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED; @@ -686,12 +701,18 @@ static void i2c_irq(i2c_t *obj) if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) { if (obj->i2c.tran_pos < obj->i2c.tran_end) { if (status == 0x90 || status == 0x98) { - *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base); + if (obj->i2c.tran_ctrl & TRANCTRL_RECVDATA) { + *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base); + obj->i2c.tran_ctrl &= ~TRANCTRL_RECVDATA; + } } if (status == 0x98) { obj->i2c.slaveaddr_state = NoData; i2c_fsm_reset(obj, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk); + } else if (obj->i2c.tran_pos == obj->i2c.tran_end) { + obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED; + i2c_disable_int(obj); } else { uint32_t i2c_ctl = I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk; if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 && @@ -700,6 +721,7 @@ static void i2c_irq(i2c_t *obj) i2c_ctl &= ~I2C_CTL0_AA_Msk; } I2C_SET_CONTROL_REG(i2c_base, i2c_ctl); + obj->i2c.tran_ctrl |= TRANCTRL_RECVDATA; } } else { obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED; From a3197f3ec9e73c58823c8cc8fa3f1e279eafad60 Mon Sep 17 00:00:00 2001 From: Chun-Chieh Li Date: Tue, 30 Jul 2019 14:03:53 +0800 Subject: [PATCH 199/227] Fix redundant SPI clock generation Fix SPI clocks are generated redundantly at the end of transfer. This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-spi/ SPI - async mode. --- targets/TARGET_NUVOTON/TARGET_M251/objects.h | 2 +- targets/TARGET_NUVOTON/TARGET_M251/spi_api.c | 15 ++++++--------- 2 files changed, 7 insertions(+), 10 deletions(-) diff --git a/targets/TARGET_NUVOTON/TARGET_M251/objects.h b/targets/TARGET_NUVOTON/TARGET_M251/objects.h index 50c0b95a8bc..aca28833f17 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/objects.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/objects.h @@ -86,7 +86,7 @@ struct spi_s { int dma_chn_id_tx; int dma_chn_id_rx; uint32_t event; - uint32_t hdlr_async; + uint32_t txrx_rmn; // Track tx/rx frames remaining in interrupt way }; struct i2c_s { diff --git a/targets/TARGET_NUVOTON/TARGET_M251/spi_api.c b/targets/TARGET_NUVOTON/TARGET_M251/spi_api.c index a72ae85a822..3004a649860 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/spi_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/spi_api.c @@ -367,6 +367,9 @@ void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, SPI_ENABLE_SYNC(spi_base); + // Initialize total SPI transfer frames + obj->spi.txrx_rmn = NU_MAX(tx_length, rx_length); + if (obj->spi.dma_usage == DMA_USAGE_NEVER) { // Interrupt way spi_master_write_asynch(obj, spi_fifo_depth(obj) / 2); @@ -637,16 +640,12 @@ static uint32_t spi_event_check(spi_t *obj) static uint32_t spi_master_write_asynch(spi_t *obj, uint32_t tx_limit) { uint32_t n_words = 0; - uint32_t tx_rmn = obj->tx_buff.length - obj->tx_buff.pos; - uint32_t rx_rmn = obj->rx_buff.length - obj->rx_buff.pos; - uint32_t max_tx = NU_MAX(tx_rmn, rx_rmn); - max_tx = NU_MIN(max_tx, tx_limit); uint8_t data_width = spi_get_data_width(obj); uint8_t bytes_per_word = (data_width + 7) / 8; uint8_t *tx = (uint8_t *)(obj->tx_buff.buffer) + bytes_per_word * obj->tx_buff.pos; SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); - while ((n_words < max_tx) && spi_writeable(obj)) { + while (obj->spi.txrx_rmn && spi_writeable(obj)) { if (spi_is_tx_complete(obj)) { // Transmit dummy as transmit buffer is empty SPI_WRITE_TX(spi_base, 0); @@ -669,6 +668,7 @@ static uint32_t spi_master_write_asynch(spi_t *obj, uint32_t tx_limit) obj->tx_buff.pos ++; } n_words ++; + obj->spi.txrx_rmn --; } //Return the number of words that have been sent @@ -689,15 +689,12 @@ static uint32_t spi_master_write_asynch(spi_t *obj, uint32_t tx_limit) static uint32_t spi_master_read_asynch(spi_t *obj) { uint32_t n_words = 0; - uint32_t tx_rmn = obj->tx_buff.length - obj->tx_buff.pos; - uint32_t rx_rmn = obj->rx_buff.length - obj->rx_buff.pos; - uint32_t max_rx = NU_MAX(tx_rmn, rx_rmn); uint8_t data_width = spi_get_data_width(obj); uint8_t bytes_per_word = (data_width + 7) / 8; uint8_t *rx = (uint8_t *)(obj->rx_buff.buffer) + bytes_per_word * obj->rx_buff.pos; SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); - while ((n_words < max_rx) && spi_readable(obj)) { + while (spi_readable(obj)) { if (spi_is_rx_complete(obj)) { // Disregard as receive buffer is full SPI_READ_RX(spi_base); From 07eb503cf1f970bf26ee62464ea2dcfdc69e4dcd Mon Sep 17 00:00:00 2001 From: Chun-Chieh Li Date: Tue, 30 Jul 2019 14:27:08 +0800 Subject: [PATCH 200/227] Fix redundant call to UART IRQ handler Honor RxIrq/TxIrq to avoid redundant call to UART IRQ handler. This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-uart. --- targets/TARGET_NUVOTON/TARGET_M251/serial_api.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/targets/TARGET_NUVOTON/TARGET_M251/serial_api.c b/targets/TARGET_NUVOTON/TARGET_M251/serial_api.c index 971b2e61585..89c0e0fbeb8 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/serial_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/serial_api.c @@ -81,9 +81,10 @@ static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable); static int serial_is_rx_complete(serial_t *obj); static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch); -static int serial_is_irq_en(serial_t *obj, SerialIrq irq); #endif +static int serial_is_irq_en(serial_t *obj, SerialIrq irq); + bool serial_can_deep_sleep(void); static struct nu_uart_var uart0_var = { @@ -459,7 +460,8 @@ static void uart_irq(serial_t *obj) if (uart_base->INTSTS & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) { // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next read. UART_DISABLE_INT(uart_base, (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); - if (obj->serial.irq_handler) { + if (obj->serial.irq_handler && serial_is_irq_en(obj, RxIrq)) { + // Call irq_handler() only when RxIrq is enabled ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, RxIrq); } } @@ -467,7 +469,8 @@ static void uart_irq(serial_t *obj) if (uart_base->INTSTS & UART_INTSTS_THREINT_Msk) { // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next write. UART_DISABLE_INT(uart_base, UART_INTEN_THREIEN_Msk); - if (obj->serial.irq_handler) { + if (obj->serial.irq_handler && serial_is_irq_en(obj, TxIrq)) { + // Call irq_handler() only when TxIrq is enabled ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, TxIrq); } } @@ -1094,6 +1097,8 @@ static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch) } } +#endif // #if DEVICE_SERIAL_ASYNCH + static int serial_is_irq_en(serial_t *obj, SerialIrq irq) { int inten_msk = 0; @@ -1110,8 +1115,6 @@ static int serial_is_irq_en(serial_t *obj, SerialIrq irq) return !! inten_msk; } -#endif // #if DEVICE_SERIAL_ASYNCH - bool serial_can_deep_sleep(void) { bool sleep_allowed = 1; From f761fe7eb15110b3639df460d86d152ee7e36845 Mon Sep 17 00:00:00 2001 From: Chun-Chieh Li Date: Tue, 30 Jul 2019 14:34:31 +0800 Subject: [PATCH 201/227] Support GPIO input pull-high/pull-low In Nuvoton, only new-design chips support GPIO input pull-high/pull-low modes. Targets not supporting this feature are listed below: - NUMAKER_PFM_NANO130 - NUMAKER_PFM_NUC472 - NUMAKER_PFM_M453 --- targets/TARGET_NUVOTON/TARGET_M251/gpio_api.c | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/targets/TARGET_NUVOTON/TARGET_M251/gpio_api.c b/targets/TARGET_NUVOTON/TARGET_M251/gpio_api.c index da83e415f1b..884f0259442 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/gpio_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/gpio_api.c @@ -64,10 +64,23 @@ void gpio_mode(gpio_t *obj, PinMode mode) return; } + uint32_t pin_index = NU_PININDEX(obj->pin); + uint32_t port_index = NU_PINPORT(obj->pin); + GPIO_T *gpio_base = NU_PORT_BASE(port_index); + switch (mode) { case PullNone: + if (mode == PullNone) { + GPIO_SetPullCtl(gpio_base, 1 << pin_index, GPIO_PUSEL_DISABLE); + } case PullDown: + if (mode == PullDown) { + GPIO_SetPullCtl(gpio_base, 1 << pin_index, GPIO_PUSEL_PULL_DOWN); + } case PullUp: + if (mode == PullUp) { + GPIO_SetPullCtl(gpio_base, 1 << pin_index, GPIO_PUSEL_PULL_UP); + } /* H/W doesn't support separate configuration for input pull mode/direction. * We translate to input-only/push-pull output I/O mode dependent on direction. */ obj->mode = (obj->direction == PIN_INPUT) ? InputOnly : PushPullOutput; @@ -112,10 +125,23 @@ void gpio_dir(gpio_t *obj, PinDirection direction) obj->direction = direction; + uint32_t pin_index = NU_PININDEX(obj->pin); + uint32_t port_index = NU_PINPORT(obj->pin); + GPIO_T *gpio_base = NU_PORT_BASE(port_index); + switch (obj->mode) { case PullNone: + if (obj->mode == PullNone) { + GPIO_SetPullCtl(gpio_base, 1 << pin_index, GPIO_PUSEL_DISABLE); + } case PullDown: + if (obj->mode == PullDown) { + GPIO_SetPullCtl(gpio_base, 1 << pin_index, GPIO_PUSEL_PULL_DOWN); + } case PullUp: + if (obj->mode == PullUp) { + GPIO_SetPullCtl(gpio_base, 1 << pin_index, GPIO_PUSEL_PULL_UP); + } /* H/W doesn't support separate configuration for input pull mode/direction. * We translate to input-only/push-pull output I/O mode dependent on direction. */ obj->mode = (obj->direction == PIN_INPUT) ? InputOnly : PushPullOutput; From 2136567b7ac7410d80182ff3ae35408997fa2433 Mon Sep 17 00:00:00 2001 From: Chun-Chieh Li Date: Thu, 1 Aug 2019 16:36:50 +0800 Subject: [PATCH 202/227] Free up peripheral pins in peripheral free-up HAL API Without free-up of peripheral pins, peripheral pins of the same peripheral may share by multiple ports after port iteration, and this peripheral may fail with pin interference. --- .../TARGET_NUVOTON/TARGET_M251/analogin_api.c | 2 ++ .../TARGET_M251/analogout_api.c | 6 ++++ targets/TARGET_NUVOTON/TARGET_M251/i2c_api.c | 3 ++ targets/TARGET_NUVOTON/TARGET_M251/objects.h | 9 ++++++ .../TARGET_NUVOTON/TARGET_M251/pwmout_api.c | 6 ++++ .../TARGET_NUVOTON/TARGET_M251/serial_api.c | 31 +++++++++++++++++-- targets/TARGET_NUVOTON/TARGET_M251/spi_api.c | 21 +++++++++---- 7 files changed, 69 insertions(+), 9 deletions(-) diff --git a/targets/TARGET_NUVOTON/TARGET_M251/analogin_api.c b/targets/TARGET_NUVOTON/TARGET_M251/analogin_api.c index 256b8399725..2833e41e0d1 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/analogin_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/analogin_api.c @@ -55,6 +55,8 @@ void analogin_init(analogin_t *obj, PinName pin) MBED_ASSERT(modinit != NULL); MBED_ASSERT(modinit->modname == (int) obj->adc); + obj->pin = pin; + // Wire pinout pinmap_pinout(pin, PinMap_ADC); diff --git a/targets/TARGET_NUVOTON/TARGET_M251/analogout_api.c b/targets/TARGET_NUVOTON/TARGET_M251/analogout_api.c index b12775a9858..96da2699db8 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/analogout_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/analogout_api.c @@ -53,6 +53,8 @@ void analogout_init(dac_t *obj, PinName pin) uint32_t chn = NU_MODSUBINDEX(obj->dac); MBED_ASSERT(chn < NU_DACCHN_MAXNUM); + obj->pin = pin; + /* Wire pinout */ pinmap_pinout(pin, PinMap_DAC); @@ -119,6 +121,10 @@ void analogout_free(dac_t *obj) /* Disable IP clock */ CLK_DisableModuleClock(modinit->clkidx); } + + // Free up pins + gpio_set(obj->pin); + obj->pin = NC; } void analogout_write(dac_t *obj, float value) diff --git a/targets/TARGET_NUVOTON/TARGET_M251/i2c_api.c b/targets/TARGET_NUVOTON/TARGET_M251/i2c_api.c index 4f5a4d32149..da70f4abb8e 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/i2c_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/i2c_api.c @@ -99,6 +99,9 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) MBED_ASSERT(modinit != NULL); MBED_ASSERT(modinit->modname == (int) obj->i2c.i2c); + obj->i2c.pin_sda = sda; + obj->i2c.pin_scl = scl; + pinmap_pinout(sda, PinMap_I2C_SDA); pinmap_pinout(scl, PinMap_I2C_SCL); diff --git a/targets/TARGET_NUVOTON/TARGET_M251/objects.h b/targets/TARGET_NUVOTON/TARGET_M251/objects.h index aca28833f17..fffc5017801 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/objects.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/objects.h @@ -44,14 +44,20 @@ struct port_s { struct analogin_s { ADCName adc; + PinName pin; }; struct dac_s { DACName dac; + PinName pin; }; struct serial_s { UARTName uart; + PinName pin_tx; + PinName pin_rx; + PinName pin_rts; + PinName pin_cts; uint32_t baudrate; uint32_t databits; @@ -91,6 +97,8 @@ struct spi_s { struct i2c_s { I2CName i2c; + PinName pin_sda; + PinName pin_scl; int slaveaddr_state; uint32_t tran_ctrl; @@ -109,6 +117,7 @@ struct i2c_s { struct pwmout_s { PWMName pwm; + PinName pin; uint32_t period_us; uint32_t pulsewidth_us; }; diff --git a/targets/TARGET_NUVOTON/TARGET_M251/pwmout_api.c b/targets/TARGET_NUVOTON/TARGET_M251/pwmout_api.c index 0b489d1caa6..eec6974f4f2 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/pwmout_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/pwmout_api.c @@ -70,6 +70,8 @@ void pwmout_init(pwmout_t* obj, PinName pin) MBED_ASSERT(modinit != NULL); MBED_ASSERT(modinit->modname == (int) obj->pwm); + obj->pin = pin; + // Wire pinout pinmap_pinout(pin, PinMap_PWM); @@ -120,6 +122,10 @@ void pwmout_free(pwmout_t* obj) // Mark this module to be deinited. int i = modinit - pwm_modinit_tab; pwm_modinit_mask &= ~(1 << i); + + // Free up pins + gpio_set(obj->pin); + obj->pin = NC; } void pwmout_write(pwmout_t* obj, float value) diff --git a/targets/TARGET_NUVOTON/TARGET_M251/serial_api.c b/targets/TARGET_NUVOTON/TARGET_M251/serial_api.c index 89c0e0fbeb8..aefd9673197 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/serial_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/serial_api.c @@ -156,10 +156,15 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; - if (! var->ref_cnt) { - pinmap_pinout(tx, PinMap_UART_TX); - pinmap_pinout(rx, PinMap_UART_RX); + obj->serial.pin_tx = tx; + obj->serial.pin_rx = rx; + obj->serial.pin_rts = NC; + obj->serial.pin_cts = NC; + + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + if (! var->ref_cnt) { // Select IP clock source CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv); // Enable IP clock @@ -259,6 +264,16 @@ void serial_free(serial_t *obj) int i = modinit - uart_modinit_tab; uart_modinit_mask &= ~(1 << i); } + + // Free up pins + gpio_set(obj->serial.pin_tx); + gpio_set(obj->serial.pin_rx); + gpio_set(obj->serial.pin_rts); + gpio_set(obj->serial.pin_cts); + obj->serial.pin_tx = NC; + obj->serial.pin_rx = NC; + obj->serial.pin_rts = NC; + obj->serial.pin_cts = NC; } void serial_baud(serial_t *obj, int baudrate) @@ -305,6 +320,16 @@ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, Pi { UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart); + // Free up old rts/cts pins when they are different from new ones + if (obj->serial.pin_rts != rxflow) { + gpio_set(obj->serial.pin_rts); + obj->serial.pin_rts = rxflow; + } + if (obj->serial.pin_cts != txflow) { + gpio_set(obj->serial.pin_cts); + obj->serial.pin_cts = txflow; + } + if (rxflow != NC) { // Check if RTS pin matches. uint32_t uart_rts = pinmap_peripheral(rxflow, PinMap_UART_RTS); diff --git a/targets/TARGET_NUVOTON/TARGET_M251/spi_api.c b/targets/TARGET_NUVOTON/TARGET_M251/spi_api.c index 3004a649860..7a3dea89abf 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/spi_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/spi_api.c @@ -120,6 +120,11 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel MBED_ASSERT(modinit != NULL); MBED_ASSERT(modinit->modname == (int) obj->spi.spi); + obj->spi.pin_mosi = mosi; + obj->spi.pin_miso = miso; + obj->spi.pin_sclk = sclk; + obj->spi.pin_ssel = ssel; + pinmap_pinout(mosi, PinMap_SPI_MOSI); pinmap_pinout(miso, PinMap_SPI_MISO); pinmap_pinout(sclk, PinMap_SPI_SCLK); @@ -133,12 +138,6 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel // Reset this module SYS_ResetModule(modinit->rsetidx); - obj->spi.pin_mosi = mosi; - obj->spi.pin_miso = miso; - obj->spi.pin_sclk = sclk; - obj->spi.pin_ssel = ssel; - - #if DEVICE_SPI_ASYNCH obj->spi.dma_usage = DMA_USAGE_NEVER; obj->spi.event = 0; @@ -184,6 +183,16 @@ void spi_free(spi_t *obj) // Mark this module to be deinited. int i = modinit - spi_modinit_tab; spi_modinit_mask &= ~(1 << i); + + // Free up pins + gpio_set(obj->spi.pin_mosi); + gpio_set(obj->spi.pin_miso); + gpio_set(obj->spi.pin_sclk); + gpio_set(obj->spi.pin_ssel); + obj->spi.pin_mosi = NC; + obj->spi.pin_miso = NC; + obj->spi.pin_sclk = NC; + obj->spi.pin_ssel = NC; } void spi_format(spi_t *obj, int bits, int mode, int slave) From 14e9683d4de2de7d2a054cc9b457d74b8d3cd5ea Mon Sep 17 00:00:00 2001 From: Chun-Chieh Li Date: Wed, 21 Aug 2019 17:54:08 +0800 Subject: [PATCH 203/227] Add BSD-3-Clause license for BSP files --- .../TARGET_NUVOTON/TARGET_M251/device/M251.h | 27 ++++++++++++-- .../TARGET_M251/device/Reg/NuMicro.h | 26 +++++++++++++- .../TARGET_M251/device/Reg/acmp_reg.h | 26 +++++++++++++- .../TARGET_M251/device/Reg/bpwm_reg.h | 26 +++++++++++++- .../TARGET_M251/device/Reg/clk_reg.h | 26 +++++++++++++- .../TARGET_M251/device/Reg/crc_reg.h | 26 +++++++++++++- .../TARGET_M251/device/Reg/crypto_reg.h | 26 +++++++++++++- .../TARGET_M251/device/Reg/dac_reg.h | 26 +++++++++++++- .../TARGET_M251/device/Reg/eadc_reg.h | 26 +++++++++++++- .../TARGET_M251/device/Reg/ebi_reg.h | 26 +++++++++++++- .../TARGET_M251/device/Reg/fmc_reg.h | 26 +++++++++++++- .../TARGET_M251/device/Reg/gpio_reg.h | 26 +++++++++++++- .../TARGET_M251/device/Reg/i2c_reg.h | 26 +++++++++++++- .../TARGET_M251/device/Reg/opa_reg.h | 26 +++++++++++++- .../TARGET_M251/device/Reg/pdma_reg.h | 26 +++++++++++++- .../TARGET_M251/device/Reg/psio_reg.h | 26 +++++++++++++- .../TARGET_M251/device/Reg/pwm_reg.h | 26 +++++++++++++- .../TARGET_M251/device/Reg/qspi_reg.h | 26 +++++++++++++- .../TARGET_M251/device/Reg/rtc_reg.h | 26 +++++++++++++- .../TARGET_M251/device/Reg/sc_reg.h | 26 +++++++++++++- .../TARGET_M251/device/Reg/spi_reg.h | 26 +++++++++++++- .../TARGET_M251/device/Reg/sys_reg.h | 26 +++++++++++++- .../TARGET_M251/device/Reg/timer_reg.h | 26 +++++++++++++- .../TARGET_M251/device/Reg/uart_reg.h | 26 +++++++++++++- .../TARGET_M251/device/Reg/ui2c_reg.h | 26 +++++++++++++- .../TARGET_M251/device/Reg/usbd_reg.h | 26 +++++++++++++- .../TARGET_M251/device/Reg/uspi_reg.h | 26 +++++++++++++- .../TARGET_M251/device/Reg/uuart_reg.h | 26 +++++++++++++- .../TARGET_M251/device/Reg/wdt_reg.h | 26 +++++++++++++- .../TARGET_M251/device/Reg/wwdt_reg.h | 26 +++++++++++++- .../device/StdDriver/inc/m251_acmp.h | 26 +++++++++++++- .../device/StdDriver/inc/m251_bpwm.h | 26 +++++++++++++- .../device/StdDriver/inc/m251_clk.h | 26 +++++++++++++- .../device/StdDriver/inc/m251_crc.h | 26 +++++++++++++- .../device/StdDriver/inc/m251_crypto.h | 26 +++++++++++++- .../device/StdDriver/inc/m251_dac.h | 26 +++++++++++++- .../device/StdDriver/inc/m251_eadc.h | 27 ++++++++++++-- .../device/StdDriver/inc/m251_ebi.h | 36 +++++++++++++++---- .../device/StdDriver/inc/m251_fmc.h | 27 ++++++++++++-- .../device/StdDriver/inc/m251_gpio.h | 26 +++++++++++++- .../device/StdDriver/inc/m251_i2c.h | 26 +++++++++++++- .../device/StdDriver/inc/m251_opa.h | 26 +++++++++++++- .../device/StdDriver/inc/m251_pdma.h | 26 +++++++++++++- .../device/StdDriver/inc/m251_psio.h | 26 +++++++++++++- .../device/StdDriver/inc/m251_pwm.h | 26 +++++++++++++- .../device/StdDriver/inc/m251_qspi.h | 26 +++++++++++++- .../device/StdDriver/inc/m251_rtc.h | 26 +++++++++++++- .../device/StdDriver/inc/m251_sc.h | 27 ++++++++++++-- .../device/StdDriver/inc/m251_scuart.h | 26 +++++++++++++- .../device/StdDriver/inc/m251_spi.h | 26 +++++++++++++- .../device/StdDriver/inc/m251_sys.h | 26 +++++++++++++- .../device/StdDriver/inc/m251_timer.h | 27 ++++++++++++-- .../device/StdDriver/inc/m251_timer_pwm.h | 26 +++++++++++++- .../device/StdDriver/inc/m251_uart.h | 26 +++++++++++++- .../device/StdDriver/inc/m251_usbd.h | 26 +++++++++++++- .../device/StdDriver/inc/m251_usci_i2c.h | 26 +++++++++++++- .../device/StdDriver/inc/m251_usci_spi.h | 26 +++++++++++++- .../device/StdDriver/inc/m251_usci_uart.h | 26 +++++++++++++- .../device/StdDriver/inc/m251_wdt.h | 26 +++++++++++++- .../device/StdDriver/inc/m251_wwdt.h | 26 +++++++++++++- .../device/StdDriver/src/m251_acmp.c | 26 +++++++++++++- .../device/StdDriver/src/m251_bpwm.c | 26 +++++++++++++- .../device/StdDriver/src/m251_clk.c | 26 +++++++++++++- .../device/StdDriver/src/m251_crc.c | 26 +++++++++++++- .../device/StdDriver/src/m251_crypto.c | 26 +++++++++++++- .../device/StdDriver/src/m251_dac.c | 26 +++++++++++++- .../device/StdDriver/src/m251_eadc.c | 27 ++++++++++++-- .../device/StdDriver/src/m251_ebi.c | 26 +++++++++++++- .../device/StdDriver/src/m251_fmc.c | 27 ++++++++++++-- .../device/StdDriver/src/m251_gpio.c | 26 +++++++++++++- .../device/StdDriver/src/m251_i2c.c | 26 +++++++++++++- .../device/StdDriver/src/m251_pdma.c | 27 ++++++++++++-- .../device/StdDriver/src/m251_pwm.c | 26 +++++++++++++- .../device/StdDriver/src/m251_qspi.c | 26 +++++++++++++- .../device/StdDriver/src/m251_rtc.c | 26 +++++++++++++- .../device/StdDriver/src/m251_sc.c | 27 ++++++++++++-- .../device/StdDriver/src/m251_scuart.c | 26 +++++++++++++- .../device/StdDriver/src/m251_spi.c | 26 +++++++++++++- .../device/StdDriver/src/m251_sys.c | 26 +++++++++++++- .../device/StdDriver/src/m251_timer.c | 26 +++++++++++++- .../device/StdDriver/src/m251_timer_pwm.c | 26 +++++++++++++- .../device/StdDriver/src/m251_uart.c | 26 +++++++++++++- .../device/StdDriver/src/m251_usbd.c | 26 +++++++++++++- .../device/StdDriver/src/m251_usci_i2c.c | 26 +++++++++++++- .../device/StdDriver/src/m251_usci_spi.c | 26 +++++++++++++- .../device/StdDriver/src/m251_usci_uart.c | 26 +++++++++++++- .../device/StdDriver/src/m251_wdt.c | 26 +++++++++++++- .../device/StdDriver/src/m251_wwdt.c | 26 +++++++++++++- .../TARGET_M251/device/system_M251.c | 34 +++++++++++++++--- .../TARGET_M251/device/system_M251.h | 34 +++++++++++++++--- 90 files changed, 2263 insertions(+), 112 deletions(-) diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/M251.h b/targets/TARGET_NUVOTON/TARGET_M251/device/M251.h index 42d7ec6c408..194364500e8 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/M251.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/M251.h @@ -3,8 +3,31 @@ * @version V1.0 * @brief Peripheral Access Layer Header File * - * @note - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************/ /** diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/NuMicro.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/NuMicro.h index 3bfe1658446..79aff799d47 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/NuMicro.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/NuMicro.h @@ -3,7 +3,31 @@ * @version V1.00 * @brief NuMicro peripheral access layer header file. * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __NUMICRO_H__ #define __NUMICRO_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/acmp_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/acmp_reg.h index 672695d3ee8..023b985b763 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/acmp_reg.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/acmp_reg.h @@ -3,7 +3,31 @@ * @version V1.00 * @brief ACMP register definition header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __ACMP_REG_H__ #define __ACMP_REG_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/bpwm_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/bpwm_reg.h index 4a3411e8a00..dd89a923c6d 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/bpwm_reg.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/bpwm_reg.h @@ -3,7 +3,31 @@ * @version V1.00 * @brief BPWM register definition header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __BPWM_REG_H__ #define __BPWM_REG_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/clk_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/clk_reg.h index 06a0251a7e4..51fe5581dbe 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/clk_reg.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/clk_reg.h @@ -3,7 +3,31 @@ * @version V1.00 * @brief CLK register definition header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __CLK_REG_H__ #define __CLK_REG_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/crc_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/crc_reg.h index 3b6ab0a9c5f..b8409beab5c 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/crc_reg.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/crc_reg.h @@ -3,7 +3,31 @@ * @version V1.00 * @brief CRC register definition header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __CRC_REG_H__ #define __CRC_REG_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/crypto_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/crypto_reg.h index cb934ec4a76..d61d5f07833 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/crypto_reg.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/crypto_reg.h @@ -3,7 +3,31 @@ * @version V1.00 * @brief CRYPTO register definition header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __CRYPTO_REG_H__ #define __CRYPTO_REG_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/dac_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/dac_reg.h index e3f21c9bdf8..269cede511d 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/dac_reg.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/dac_reg.h @@ -3,7 +3,31 @@ * @version V1.00 * @brief DAC register definition header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __DAC_REG_H__ #define __DAC_REG_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/eadc_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/eadc_reg.h index d06cd6934bd..5116245c4c2 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/eadc_reg.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/eadc_reg.h @@ -3,7 +3,31 @@ * @version V1.00 * @brief EADC register definition header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __EADC_REG_H__ #define __EADC_REG_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/ebi_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/ebi_reg.h index 07ccca8b9f0..27e832702b4 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/ebi_reg.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/ebi_reg.h @@ -3,7 +3,31 @@ * @version V1.00 * @brief EBI register definition header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __EBI_REG_H__ #define __EBI_REG_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/fmc_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/fmc_reg.h index 9c3448510ef..0e7cffa8c45 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/fmc_reg.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/fmc_reg.h @@ -3,7 +3,31 @@ * @version V1.00 * @brief FMC register definition header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __FMC_REG_H__ #define __FMC_REG_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/gpio_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/gpio_reg.h index eb25013b627..8f6964bc866 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/gpio_reg.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/gpio_reg.h @@ -3,7 +3,31 @@ * @version V1.00 * @brief GPIO register definition header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __GPIO_REG_H__ #define __GPIO_REG_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/i2c_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/i2c_reg.h index 0d172723250..ca1ce41304d 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/i2c_reg.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/i2c_reg.h @@ -3,7 +3,31 @@ * @version V1.00 * @brief I2C register definition header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __I2C_REG_H__ #define __I2C_REG_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/opa_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/opa_reg.h index c9616bc1628..3ceed150488 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/opa_reg.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/opa_reg.h @@ -3,7 +3,31 @@ * @version V1.00 * @brief OPA register definition header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __OPA_REG_H__ #define __OPA_REG_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/pdma_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/pdma_reg.h index b69eac1b652..a1c6072dda8 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/pdma_reg.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/pdma_reg.h @@ -3,7 +3,31 @@ * @version V1.00 * @brief PDMA register definition header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __PDMA_REG_H__ #define __PDMA_REG_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/psio_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/psio_reg.h index ac34f92d7a2..5790a7b9607 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/psio_reg.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/psio_reg.h @@ -3,7 +3,31 @@ * @version V1.00 * @brief PSIO register definition header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __PSIO_REG_H__ #define __PSIO_REG_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/pwm_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/pwm_reg.h index 99a266e4301..a6e9527e81c 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/pwm_reg.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/pwm_reg.h @@ -3,7 +3,31 @@ * @version V1.00 * @brief PWM register definition header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __PWM_REG_H__ #define __PWM_REG_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/qspi_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/qspi_reg.h index d8018672f66..0b473de2810 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/qspi_reg.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/qspi_reg.h @@ -3,7 +3,31 @@ * @version V1.00 * @brief QSPI register definition header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __QSPI_REG_H__ #define __QSPI_REG_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/rtc_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/rtc_reg.h index 4903da158d0..910d67d9263 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/rtc_reg.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/rtc_reg.h @@ -3,7 +3,31 @@ * @version V1.00 * @brief RTC register definition header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __RTC_REG_H__ #define __RTC_REG_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/sc_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/sc_reg.h index 1db5c43488a..03547444144 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/sc_reg.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/sc_reg.h @@ -3,7 +3,31 @@ * @version V1.00 * @brief SC register definition header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __SC_REG_H__ #define __SC_REG_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/spi_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/spi_reg.h index 67f7cecbf40..e67799d7975 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/spi_reg.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/spi_reg.h @@ -3,7 +3,31 @@ * @version V1.00 * @brief SPI register definition header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __SPI_REG_H__ #define __SPI_REG_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/sys_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/sys_reg.h index 7dc71f90498..dd17c229fbd 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/sys_reg.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/sys_reg.h @@ -3,7 +3,31 @@ * @version V1.00 * @brief SYS register definition header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __SYS_REG_H__ #define __SYS_REG_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/timer_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/timer_reg.h index 5ae5304b298..77c7c8de63e 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/timer_reg.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/timer_reg.h @@ -3,7 +3,31 @@ * @version V1.00 * @brief TIMER register definition header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __TIMER_REG_H__ #define __TIMER_REG_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/uart_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/uart_reg.h index 4666a126f54..17f661a07f3 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/uart_reg.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/uart_reg.h @@ -3,7 +3,31 @@ * @version V1.00 * @brief UART register definition header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __UART_REG_H__ #define __UART_REG_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/ui2c_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/ui2c_reg.h index a3cca104977..596e75a3c21 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/ui2c_reg.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/ui2c_reg.h @@ -3,7 +3,31 @@ * @version V1.00 * @brief UI2C register definition header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __UI2C_REG_H__ #define __UI2C_REG_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/usbd_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/usbd_reg.h index 49f925e652f..a439cf1bf76 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/usbd_reg.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/usbd_reg.h @@ -3,7 +3,31 @@ * @version V1.00 * @brief USBD register definition header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __USBD_REG_H__ #define __USBD_REG_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/uspi_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/uspi_reg.h index ac38c23acf7..55f449b05ee 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/uspi_reg.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/uspi_reg.h @@ -3,7 +3,31 @@ * @version V1.00 * @brief USPI register definition header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __USPI_REG_H__ #define __USPI_REG_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/uuart_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/uuart_reg.h index 9a714a8abf8..ab108621747 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/uuart_reg.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/uuart_reg.h @@ -3,7 +3,31 @@ * @version V1.00 * @brief UUART register definition header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __UUART_REG_H__ #define __UUART_REG_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/wdt_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/wdt_reg.h index 319e925a531..34da808dd38 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/wdt_reg.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/wdt_reg.h @@ -3,7 +3,31 @@ * @version V1.00 * @brief WDT register definition header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __WDT_REG_H__ #define __WDT_REG_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/wwdt_reg.h b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/wwdt_reg.h index 8f3ab94477b..1a4a054f16f 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/wwdt_reg.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/Reg/wwdt_reg.h @@ -3,7 +3,31 @@ * @version V1.00 * @brief WWDT register definition header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __WWDT_REG_H__ #define __WWDT_REG_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_acmp.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_acmp.h index 9fbdd163c98..31b28c045a4 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_acmp.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_acmp.h @@ -3,7 +3,31 @@ * @version V1.00 * @brief M251 series ACMP Driver Header File * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************/ #ifndef __ACMP_H__ #define __ACMP_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_bpwm.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_bpwm.h index 39f736e301f..e30e51906a8 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_bpwm.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_bpwm.h @@ -3,7 +3,31 @@ * @version V0.10 * @brief M251 series BPWM driver header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __BPWM_H__ #define __BPWM_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_clk.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_clk.h index ec30b022166..efffef89449 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_clk.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_clk.h @@ -3,7 +3,31 @@ * @version V1.10 * @brief M251 series CLK driver source file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __CLK_H__ #define __CLK_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_crc.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_crc.h index 174df2f1627..dc20cff964a 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_crc.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_crc.h @@ -3,7 +3,31 @@ * @version V0.10 * @brief M251 series Cyclic Redundancy Check(CRC) driver header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __CRC_H__ #define __CRC_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_crypto.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_crypto.h index 54001442c06..9ce41668551 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_crypto.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_crypto.h @@ -3,7 +3,31 @@ * @version V1.10 * @brief Cryptographic Accelerator driver header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************/ #ifndef __CRYPTO_H__ #define __CRYPTO_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_dac.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_dac.h index 90a539781c3..94485826a85 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_dac.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_dac.h @@ -3,7 +3,31 @@ * @version V0.10 * @brief M251 series DAC driver header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __DAC_H__ #define __DAC_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_eadc.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_eadc.h index 42d994d3317..e94947b36a9 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_eadc.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_eadc.h @@ -3,8 +3,31 @@ * @version V0.10 * @brief M251 series EADC driver header file * - * @note - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __EADC_H__ #define __EADC_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_ebi.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_ebi.h index 9ce465b6cad..9babd3cd419 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_ebi.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_ebi.h @@ -1,10 +1,34 @@ /**************************************************************************//** -* @file ebi.h -* @version V0.10 -* @brief M251 series EBI driver source file -* -* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. -****************************************************************************/ + * @file ebi.h + * @version V0.10 + * @brief M251 series EBI driver source file + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ #ifndef __EBI_H__ #define __EBI_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_fmc.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_fmc.h index 5a16f9a03d5..6b3a98d93c6 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_fmc.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_fmc.h @@ -3,8 +3,31 @@ * @version V3.0 * @brief M251 Series Flash Memory Controller(FMC) driver header file * - * @note - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ******************************************************************************/ #ifndef __FMC_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_gpio.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_gpio.h index 1d0fb529dc5..ff529a0a51b 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_gpio.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_gpio.h @@ -3,7 +3,31 @@ * @version V0.10 * @brief M251 series GPIO driver header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************/ #ifndef __GPIO_H__ #define __GPIO_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_i2c.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_i2c.h index db05e875309..3f90b8ad7d8 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_i2c.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_i2c.h @@ -3,7 +3,31 @@ * @version V0.10 * @brief M251 Series I2C Driver Header File * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************/ #ifndef __I2C_H__ #define __I2C_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_opa.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_opa.h index e79574efe32..6b75ffefe9a 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_opa.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_opa.h @@ -3,7 +3,31 @@ * @version V1.00 * @brief M251 series OPA driver header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __OPA_H__ #define __OPA_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_pdma.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_pdma.h index 4db0fbb3521..2148a8cf8c1 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_pdma.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_pdma.h @@ -3,7 +3,31 @@ * @version V3.00 * @brief M251 series PDMA driver header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __PDMA_H__ #define __PDMA_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_psio.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_psio.h index 04b88fdb72c..1e8d1339f05 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_psio.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_psio.h @@ -3,7 +3,31 @@ * @version V1.00 * @brief M251 series psio driver header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __PSIO_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_pwm.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_pwm.h index fbbc24f90f4..e5246ebdd3b 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_pwm.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_pwm.h @@ -3,7 +3,31 @@ * @version V0.10 * @brief M251 series PWM driver header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __PWM_H__ #define __PWM_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_qspi.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_qspi.h index cb2901791f0..2a7386b31b3 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_qspi.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_qspi.h @@ -3,7 +3,31 @@ * @version V0.10 * @brief M251 series QSPI driver header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __QSPI_H__ #define __QSPI_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_rtc.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_rtc.h index 74b2a5fd877..003e5d9e8a2 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_rtc.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_rtc.h @@ -3,7 +3,31 @@ * @version V1.00 * @brief M251 series RTC driver header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __RTC_H__ #define __RTC_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_sc.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_sc.h index 7d664a8bda0..ce4fe59ec48 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_sc.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_sc.h @@ -3,8 +3,31 @@ * @version V3.00 * @brief Smart Card(SC) driver header file * - * @note - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __SC_H__ #define __SC_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_scuart.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_scuart.h index bff24a7e3c7..c1f12373ad6 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_scuart.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_scuart.h @@ -3,7 +3,31 @@ * @version V1.00 * @brief M251 Smartcard UART mode (SCUART) driver header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __SCUART_H__ #define __SCUART_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_spi.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_spi.h index 18414f374d8..3fb3d2d1120 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_spi.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_spi.h @@ -3,7 +3,31 @@ * @version V0.10 * @brief M251 series SPI driver header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __SPI_H__ #define __SPI_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_sys.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_sys.h index 595a7769688..222af74f020 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_sys.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_sys.h @@ -3,7 +3,31 @@ * @version V1.10 * @brief M251 series SYS driver source file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __SYS_H__ #define __SYS_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_timer.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_timer.h index f4d51d80e91..28dc8cb0aa4 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_timer.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_timer.h @@ -3,8 +3,31 @@ * @version V1.01 * @brief M251 series Timer driver header file * - * @note - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __TIMER_H__ #define __TIMER_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_timer_pwm.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_timer_pwm.h index 5ee5ca7634f..e2758ee7ebb 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_timer_pwm.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_timer_pwm.h @@ -3,7 +3,31 @@ * @version V1.01 * @brief M251 series Timer PWM Controller(Timer PWM) driver header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __TIMER_PWM_H__ #define __TIMER_PWM_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_uart.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_uart.h index a983567d9a3..18afb191e40 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_uart.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_uart.h @@ -3,7 +3,31 @@ * @version V1.00 * @brief M251 series UART driver source file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __UART_H__ #define __UART_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_usbd.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_usbd.h index e4379de1d16..1dbb1717adc 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_usbd.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_usbd.h @@ -3,7 +3,31 @@ * @version V0.10 * @brief M251 series USB driver header file * - * @copyrightt (C) 2017 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************/ #ifndef __USBD_H__ #define __USBD_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_usci_i2c.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_usci_i2c.h index 3d797f66b62..a410759e101 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_usci_i2c.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_usci_i2c.h @@ -3,7 +3,31 @@ * @version V0.10 * @brief M251 series USCI I2C(UI2C) driver header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************/ #ifndef __USCI_I2C_H__ #define __USCI_I2C_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_usci_spi.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_usci_spi.h index 22cd40e2816..708ec7b3064 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_usci_spi.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_usci_spi.h @@ -3,7 +3,31 @@ * @version V0.10 * @brief M251 series USCI_SPI driver header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __USCI_SPI_H__ #define __USCI_SPI_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_usci_uart.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_usci_uart.h index b5cf4cda103..5f9eb841c85 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_usci_uart.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_usci_uart.h @@ -3,7 +3,31 @@ * @version V0.10 * @brief M251 series USCI UART (UUART) driver header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __USCI_UART_H__ #define __USCI_UART_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_wdt.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_wdt.h index b73a5465c4b..9ff7937a8b7 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_wdt.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_wdt.h @@ -3,7 +3,31 @@ * @version V0.10 * @brief M251 series WDT driver header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __WDT_H__ #define __WDT_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_wwdt.h b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_wwdt.h index 48eb82caee2..56c4eb37cb1 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_wwdt.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/inc/m251_wwdt.h @@ -3,7 +3,31 @@ * @version V0.10 * @brief M251 series WWDT driver header file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #ifndef __WWDT_H__ #define __WWDT_H__ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_acmp.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_acmp.c index 32cc38ca7d1..a7cd684ad7b 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_acmp.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_acmp.c @@ -3,7 +3,31 @@ * @version V1.00 * @brief M251 series Analog Comparator(ACMP) driver source file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #include "NuMicro.h" diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_bpwm.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_bpwm.c index 879c1c2f237..3ef08af5af1 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_bpwm.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_bpwm.c @@ -3,7 +3,31 @@ * @version V0.10 * @brief M251 series BPWM driver source file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #include "NuMicro.h" diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_clk.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_clk.c index cb5f2fa8ff9..3b91bd3c599 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_clk.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_clk.c @@ -3,7 +3,31 @@ * @version V1.10 * @brief M251 series CLK driver source file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #include "NuMicro.h" diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_crc.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_crc.c index 01c00d61d08..e863aea661e 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_crc.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_crc.c @@ -3,7 +3,31 @@ * @version V0.10 * @brief M251 CRC driver source file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #include "NuMicro.h" diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_crypto.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_crypto.c index 75166a76549..fc4ad0b4659 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_crypto.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_crypto.c @@ -3,7 +3,31 @@ * @version V1.10 * @brief Cryptographic Accelerator driver source file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #include diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_dac.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_dac.c index 4c67b17a0b2..1869f2040dd 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_dac.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_dac.c @@ -3,7 +3,31 @@ * @version V0.10 * @brief M251 series DAC driver source file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #include "NuMicro.h" diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_eadc.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_eadc.c index 04ac082c3b1..314cbc37d77 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_eadc.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_eadc.c @@ -3,8 +3,31 @@ * @version V0.10 * @brief M251 series EADC driver source file * - * @note - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #include "NuMicro.h" diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_ebi.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_ebi.c index a6ec9bf5b27..294cf7fdf44 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_ebi.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_ebi.c @@ -3,7 +3,31 @@ * @version V0.10 * @brief M251 series EBI driver source file * -* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. +* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ****************************************************************************/ #include "NuMicro.h" diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_fmc.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_fmc.c index 9b35f46ef48..3f719ccd0e0 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_fmc.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_fmc.c @@ -3,8 +3,31 @@ * @version V3.00 * @brief M251 Series Flash Memory Controller(FMC) driver source file * - * @note - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #include #include "NuMicro.h" diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_gpio.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_gpio.c index 9f76941b387..9efbd2a35d5 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_gpio.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_gpio.c @@ -3,7 +3,31 @@ * @version V0.10 * @brief M251 GPIO driver source file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #include "NuMicro.h" diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_i2c.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_i2c.c index 32f4b3381fb..27108a6d2d4 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_i2c.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_i2c.c @@ -3,7 +3,31 @@ * @version V0.10 * @brief M251 series I2C driver source file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #include "NuMicro.h" diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_pdma.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_pdma.c index f63b24f223f..7e5a04c75a3 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_pdma.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_pdma.c @@ -3,8 +3,31 @@ * @version V1.00 * @brief M251 series PDMA driver source file * - * @note - * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #include "M251.h" diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_pwm.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_pwm.c index fda96fec3b6..abb16e62266 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_pwm.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_pwm.c @@ -3,7 +3,31 @@ * @version V0.10 * @brief M251 series PWM driver source file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #include "NuMicro.h" diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_qspi.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_qspi.c index c7614285a3c..10ee27f9147 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_qspi.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_qspi.c @@ -3,7 +3,31 @@ * @version V0.10 * @brief M251 series QSPI driver source file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #include "NuMicro.h" diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_rtc.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_rtc.c index 240639571ad..11a83e7f532 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_rtc.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_rtc.c @@ -3,7 +3,31 @@ * @version V1.00 * @brief M251 series CLK driver source file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #include "NuMicro.h" diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_sc.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_sc.c index cea50f42092..2434f4af344 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_sc.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_sc.c @@ -3,8 +3,31 @@ * @version V3.00 * @brief Smart Card(SC) driver source file * - * @note - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #include "NuMicro.h" diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_scuart.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_scuart.c index 9fa722b095c..5e42ba1c653 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_scuart.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_scuart.c @@ -2,7 +2,31 @@ * @file scuart.c * @brief M251 Smartcard UART mode (SCUART) driver source file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #include "NuMicro.h" diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_spi.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_spi.c index 18873256104..8c9b9c9a55e 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_spi.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_spi.c @@ -3,7 +3,31 @@ * @version V0.10 * @brief M251 series SPI driver source file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #include "NuMicro.h" diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_sys.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_sys.c index 28688e66f96..90ae804144d 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_sys.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_sys.c @@ -3,7 +3,31 @@ * @version V1.10 * @brief M251 series SYS driver source file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #include "NuMicro.h" /** @addtogroup Standard_Driver Standard Driver diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_timer.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_timer.c index 7f97af8e189..7123a9cecff 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_timer.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_timer.c @@ -3,7 +3,31 @@ * @version V3.01 * @brief M251 series Timer Controller(Timer) driver source file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #include "NuMicro.h" diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_timer_pwm.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_timer_pwm.c index fac1d98bf09..97a85371814 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_timer_pwm.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_timer_pwm.c @@ -3,7 +3,31 @@ * @version V3.01 * @brief Timer PWM Controller(Timer PWM) driver source file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #include "NuMicro.h" diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_uart.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_uart.c index 79c7d90b7d4..7599b29bb03 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_uart.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_uart.c @@ -3,7 +3,31 @@ * @version V1.00 * @brief M251 series UART driver source file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #include "NuMicro.h" diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_usbd.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_usbd.c index 525c068cce3..b044279a471 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_usbd.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_usbd.c @@ -3,7 +3,31 @@ * @version V0.10 * @brief M251 series USBD driver source file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #include diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_usci_i2c.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_usci_i2c.c index 540b2732f64..4001bf6e60b 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_usci_i2c.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_usci_i2c.c @@ -3,7 +3,31 @@ * @version V0.10 * @brief M251 series USCI I2C(UI2C) driver source file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #include "NuMicro.h" diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_usci_spi.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_usci_spi.c index cf36b1bdcd7..8d04f50654f 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_usci_spi.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_usci_spi.c @@ -3,7 +3,31 @@ * @version V0.10 * @brief M251 series USCI_SPI driver source file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #include "NuMicro.h" diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_usci_uart.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_usci_uart.c index 7f60da27ee3..194d221c5db 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_usci_uart.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_usci_uart.c @@ -3,7 +3,31 @@ * @version V0.10 * @brief M251 series USCI UART (UUART) driver source file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #include diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_wdt.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_wdt.c index b7c29b38e44..62798864606 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_wdt.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_wdt.c @@ -3,7 +3,31 @@ * @version V0.10 * @brief M251 series WDT driver source file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #include "NuMicro.h" diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_wwdt.c b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_wwdt.c index 8d036b8933e..701f8ff8c38 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_wwdt.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/StdDriver/src/m251_wwdt.c @@ -3,7 +3,31 @@ * @version V0.10 * @brief M251 series WWDT driver source file * - * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *****************************************************************************/ #include "NuMicro.h" diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/system_M251.c b/targets/TARGET_NUVOTON/TARGET_M251/device/system_M251.c index 9335fe23703..4d04a7f8399 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/system_M251.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/system_M251.c @@ -1,9 +1,33 @@ /**************************************************************************//** -* @file system_M251.c -* @version V0.10 -* @brief System Setting Source File -* -* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * @file system_M251.c + * @version V0.10 + * @brief System Setting Source File + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ****************************************************************************/ #include diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/system_M251.h b/targets/TARGET_NUVOTON/TARGET_M251/device/system_M251.h index 974e1cc7485..f15db1a9e1d 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/system_M251.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/system_M251.h @@ -1,9 +1,33 @@ /**************************************************************************//** -* @file system_M251.h -* @version V0.10 -* @brief System Setting Header File -* -* @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + * @file system_M251.h + * @version V0.10 + * @brief System Setting Header File + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2019 Nuvoton Technology Corp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ****************************************************************************/ #ifndef __SYSTEM_M251_H__ From 7f921bc292e78608ccb00afd34fa3596c38d0728 Mon Sep 17 00:00:00 2001 From: Chun-Chieh Li Date: Fri, 23 Aug 2019 10:21:03 +0800 Subject: [PATCH 204/227] Add missing 'sectors' into arm_pack_manager/index.json --- tools/arm_pack_manager/index.json | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/tools/arm_pack_manager/index.json b/tools/arm_pack_manager/index.json index ab49324b74a..25ad4120c2a 100644 --- a/tools/arm_pack_manager/index.json +++ b/tools/arm_pack_manager/index.json @@ -169627,7 +169627,12 @@ "units": 1 } }, - "sectors": null, + "sectors": [ + [ + 0, + 512 + ] + ], "sub_family": "M251", "vendor": "Nuvoton:18" }, From 03affe94d8064bd542f265f113747161d427ba9e Mon Sep 17 00:00:00 2001 From: Chun-Chieh Li Date: Fri, 27 Sep 2019 17:50:48 +0800 Subject: [PATCH 205/227] Remove TRNG support Reasons to remove TRNG support: 1. M252 just has 32KiB SRAM and cannot afford mbedtls application. 2. Implementing TRNG HAL with PRNG H/W has security concern. --- .../TARGET_M251/crypto/crypto-misc.cpp | 274 ------------------ .../TARGET_M251/crypto/crypto-misc.h | 104 ------- targets/TARGET_NUVOTON/TARGET_M251/objects.h | 4 - targets/TARGET_NUVOTON/TARGET_M251/trng_api.c | 90 ------ targets/targets.json | 1 - 5 files changed, 473 deletions(-) delete mode 100644 targets/TARGET_NUVOTON/TARGET_M251/crypto/crypto-misc.cpp delete mode 100644 targets/TARGET_NUVOTON/TARGET_M251/crypto/crypto-misc.h delete mode 100644 targets/TARGET_NUVOTON/TARGET_M251/trng_api.c diff --git a/targets/TARGET_NUVOTON/TARGET_M251/crypto/crypto-misc.cpp b/targets/TARGET_NUVOTON/TARGET_M251/crypto/crypto-misc.cpp deleted file mode 100644 index 4da9836fa0c..00000000000 --- a/targets/TARGET_NUVOTON/TARGET_M251/crypto/crypto-misc.cpp +++ /dev/null @@ -1,274 +0,0 @@ -/* - * Copyright (c) 2019, Nuvoton Technology Corporation - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - -#include "cmsis.h" -#include "mbed_assert.h" -#include "mbed_atomic.h" -#include "mbed_critical.h" -#include "mbed_error.h" -#include -#include "nu_modutil.h" -#include "nu_bitutil.h" -#include "crypto-misc.h" -#include "platform/SingletonPtr.h" -#include "platform/PlatformMutex.h" - -#if DEVICE_TRNG || defined(MBEDTLS_CONFIG_HW_SUPPORT) - -/* Consideration for choosing proper synchronization mechanism - * - * 1. We choose mutex to synchronize access to crypto non-SHA AC. We can guarantee: - * (1) No deadlock - * We just lock mutex for a short sequence of operations rather than the whole lifetime - * of crypto context. - * (2) No priority inversion - * Mutex supports priority inheritance and it is enabled. - * 2. We choose atomic flag to synchronize access to crypto SHA AC. We can guarantee: - * (1) No deadlock - * With SHA AC not supporting context save & restore, we provide SHA S/W fallback when - * SHA AC is not available. - * (2) No biting CPU - * Same reason as above. - */ - -/* Mutex for crypto AES AC management */ -static SingletonPtr crypto_aes_mutex; - -/* Atomic flag for crypto SHA AC management */ -static core_util_atomic_flag crypto_sha_atomic_flag = CORE_UTIL_ATOMIC_FLAG_INIT; - - -/* Crypto (AES, DES, SHA, etc.) init counter. Crypto's keeps active as it is non-zero. */ -static uint16_t crypto_init_counter = 0U; - -/* Crypto done flags */ -#define CRYPTO_DONE_OK BIT0 /* Done with OK */ -#define CRYPTO_DONE_ERR BIT1 /* Done with error */ - -/* Track if PRNG H/W operation is done */ -static volatile uint16_t crypto_prng_done; -/* Track if AES H/W operation is done */ -static volatile uint16_t crypto_aes_done; - -static void crypto_submodule_prestart(volatile uint16_t *submodule_done); -static bool crypto_submodule_wait(volatile uint16_t *submodule_done); - -/* As crypto init counter changes from 0 to 1: - * - * 1. Enable crypto clock - * 2. Enable crypto interrupt - */ -void crypto_init(void) -{ - core_util_critical_section_enter(); - if (crypto_init_counter == USHRT_MAX) { - core_util_critical_section_exit(); - error("Crypto clock enable counter would overflow (> USHRT_MAX)"); - } - core_util_atomic_incr_u16(&crypto_init_counter, 1); - if (crypto_init_counter == 1) { - CLK_EnableModuleClock(CRPT_MODULE); - - NVIC_EnableIRQ(CRPT_IRQn); - } - core_util_critical_section_exit(); -} - -/* As crypto init counter changes from 1 to 0: - * - * 1. Disable crypto interrupt - * 2. Disable crypto clock - */ -void crypto_uninit(void) -{ - core_util_critical_section_enter(); - if (crypto_init_counter == 0) { - core_util_critical_section_exit(); - error("Crypto clock enable counter would underflow (< 0)"); - } - core_util_atomic_decr_u16(&crypto_init_counter, 1); - if (crypto_init_counter == 0) { - NVIC_DisableIRQ(CRPT_IRQn); - - CLK_DisableModuleClock(CRPT_MODULE); - } - core_util_critical_section_exit(); -} - -/* Implementation that should never be optimized out by the compiler */ -void crypto_zeroize(void *v, size_t n) -{ - volatile unsigned char *p = (volatile unsigned char*) v; - while (n--) { - *p++ = 0; - } -} - -/* Implementation that should never be optimized out by the compiler */ -void crypto_zeroize32(uint32_t *v, size_t n) -{ - volatile uint32_t *p = (volatile uint32_t*) v; - while (n--) { - *p++ = 0; - } -} - -void crypto_aes_acquire(void) -{ - /* Don't check return code of Mutex::lock(void) - * - * This function treats RTOS errors as fatal system errors, so it can only return osOK. - * Use of the return value is deprecated, as the return is expected to become void in - * the future. - */ - crypto_aes_mutex->lock(); -} - -void crypto_aes_release(void) -{ - crypto_aes_mutex->unlock(); -} - -bool crypto_sha_try_acquire(void) -{ - return !core_util_atomic_flag_test_and_set(&crypto_sha_atomic_flag); -} - -void crypto_sha_release(void) -{ - core_util_atomic_flag_clear(&crypto_sha_atomic_flag); -} - -void crypto_prng_prestart(void) -{ - crypto_submodule_prestart(&crypto_prng_done); -} - -bool crypto_prng_wait(void) -{ - return crypto_submodule_wait(&crypto_prng_done); -} - -void crypto_aes_prestart(void) -{ - crypto_submodule_prestart(&crypto_aes_done); -} - -bool crypto_aes_wait(void) -{ - return crypto_submodule_wait(&crypto_aes_done); -} - -bool crypto_dma_buff_compat(const void *buff, size_t buff_size, size_t size_aligned_to) -{ - uint32_t buff_ = (uint32_t) buff; - - return (((buff_ & 0x03) == 0) && /* Word-aligned buffer base address */ - ((buff_size & (size_aligned_to - 1)) == 0) && /* Crypto submodule dependent buffer size alignment */ - (((buff_ >> 28) == 0x2) && (buff_size <= (0x30000000 - buff_)))); /* 0x20000000-0x2FFFFFFF */ -} - -/* Overlap cases - * - * 1. in_buff in front of out_buff: - * - * in in_end - * | | - * |||||||||||||||| - * |||||||||||||||| - * | | - * out out_end - * - * 2. out_buff in front of in_buff: - * - * in in_end - * | | - * |||||||||||||||| - * |||||||||||||||| - * | | - * out out_end - */ -bool crypto_dma_buffs_overlap(const void *in_buff, size_t in_buff_size, const void *out_buff, size_t out_buff_size) -{ - uint32_t in = (uint32_t) in_buff; - uint32_t in_end = in + in_buff_size; - uint32_t out = (uint32_t) out_buff; - uint32_t out_end = out + out_buff_size; - - bool overlap = (in <= out && out < in_end) || (out <= in && in < out_end); - - return overlap; -} - -static void crypto_submodule_prestart(volatile uint16_t *submodule_done) -{ - *submodule_done = 0; - - /* Ensure memory accesses above are completed before DMA is started - * - * Replacing __DSB() with __DMB() is also OK in this case. - * - * Refer to "multi-master systems" section with DMA in: - * https://static.docs.arm.com/dai0321/a/DAI0321A_programming_guide_memory_barriers_for_m_profile.pdf - */ - __DSB(); -} - -static bool crypto_submodule_wait(volatile uint16_t *submodule_done) -{ - while (! *submodule_done); - - /* Ensure while loop above and subsequent code are not reordered */ - __DSB(); - - if ((*submodule_done & CRYPTO_DONE_OK)) { - /* Done with OK */ - return true; - } else if ((*submodule_done & CRYPTO_DONE_ERR)) { - /* Done with error */ - return false; - } - - return false; -} - -/* Crypto interrupt handler - * - * There's inconsistency in cryptography related naming, Crpt or Crypto. For example, - * cryptography IRQ handler could be CRPT_IRQHandler or CRYPTO_IRQHandler. To override - * default cryptography IRQ handler, see device/startup_{CHIP}.c for its correct name - * or call NVIC_SetVector() in crypto_init() regardless of its name. */ -extern "C" void CRPT_IRQHandler() -{ - uint32_t intsts; - - if ((intsts = PRNG_GET_INT_FLAG(CRYPTO_MODBASE())) != 0) { - /* Done with OK */ - crypto_prng_done |= CRYPTO_DONE_OK; - /* Clear interrupt flag */ - PRNG_CLR_INT_FLAG(CRYPTO_MODBASE()); - } else if ((intsts = AES_GET_INT_FLAG(CRYPTO_MODBASE())) != 0) { - /* Done with OK */ - crypto_aes_done |= CRYPTO_DONE_OK; - /* Clear interrupt flag */ - AES_CLR_INT_FLAG(CRYPTO_MODBASE()); - } -} - -#endif /* #if DEVICE_TRNG || defined(MBEDTLS_CONFIG_HW_SUPPORT) */ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/crypto/crypto-misc.h b/targets/TARGET_NUVOTON/TARGET_M251/crypto/crypto-misc.h deleted file mode 100644 index fa5a278d91f..00000000000 --- a/targets/TARGET_NUVOTON/TARGET_M251/crypto/crypto-misc.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright (c) 2019, Nuvoton Technology Corporation - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_CRYPTO_MISC_H -#define MBED_CRYPTO_MISC_H - -#include - -#if DEVICE_TRNG || defined(MBEDTLS_CONFIG_HW_SUPPORT) - -#ifdef __cplusplus -extern "C" { -#endif - -/* Get Crypto module base */ -__STATIC_INLINE CRPT_T *CRYPTO_MODBASE(void) -{ - return CRPT; -} - -/* Init/Uninit crypto module */ -void crypto_init(void); -void crypto_uninit(void); - -/* Clear buffer to zero - * Implementation that should never be optimized out by the compiler */ -void crypto_zeroize(void *v, size_t n); -void crypto_zeroize32(uint32_t *v, size_t n); - -/* Acquire/release ownership of crypto sub-module - * - * \note "acquire" is blocking until ownership is acquired - * - * \note "acquire"/"release" must be paired. - * - * \note Recursive "acquire" is allowed because the underlying synchronization - * primitive mutex supports it. - */ -void crypto_aes_acquire(void); -void crypto_aes_release(void); - -/* Acquire/release ownership of crypto sub-module - * - * \return false if crytpo sub-module is held by another thread or - * another mbedtls context. - * true if successful - * - * \note Successful "try_acquire" and "release" must be paired. - */ -bool crypto_sha_try_acquire(void); -void crypto_sha_release(void); - -/* Flow control between crypto/xxx start and crypto/xxx ISR - * - * crypto_xxx_prestart/crypto_xxx_wait encapsulate control flow between crypto/xxx start and crypto/xxx ISR. - * - * crypto_xxx_prestart will also address synchronization issue with memory barrier instruction. - * - * On finish, return of crypto_xxx_wait indicates success or not: - * true if successful - * false if failed - * - * Example: Start AES H/W and wait for its finish - * crypto_aes_prestart(); - * AES_Start(); - * crypto_aes_wait(); - */ -void crypto_prng_prestart(void); -bool crypto_prng_wait(void); -void crypto_aes_prestart(void); -bool crypto_aes_wait(void); - - -/* Check if buffer can be used for crypto DMA. It has the following requirements: - * (1) Word-aligned buffer base address - * (2) Crypto submodule (AES, DES, SHA, etc.) dependent buffer size alignment. Must be 2 power. - * (3) Located in 0x20000000-0x2FFFFFFF region - */ -bool crypto_dma_buff_compat(const void *buff, size_t buff_size, size_t size_aligned_to); - -/* Check if input/output buffers are overlapped */ -bool crypto_dma_buffs_overlap(const void *in_buff, size_t in_buff_size, const void *out_buff, size_t out_buff_size); - -#ifdef __cplusplus -} -#endif - -#endif -#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M251/objects.h b/targets/TARGET_NUVOTON/TARGET_M251/objects.h index fffc5017801..d0fc1df0d98 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/objects.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/objects.h @@ -126,10 +126,6 @@ struct sleep_s { int powerdown; }; -struct trng_s { - uint8_t dummy; -}; - #ifdef __cplusplus } #endif diff --git a/targets/TARGET_NUVOTON/TARGET_M251/trng_api.c b/targets/TARGET_NUVOTON/TARGET_M251/trng_api.c deleted file mode 100644 index d67e563e409..00000000000 --- a/targets/TARGET_NUVOTON/TARGET_M251/trng_api.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (c) 2019, Nuvoton Technology Corporation - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if DEVICE_TRNG - -#include -#include -#include "cmsis.h" -#include "us_ticker_api.h" -#include "trng_api.h" -#include "crypto-misc.h" - -/* - * Get Random number generator. - */ - -#define PRNG_KEY_SIZE (0x20UL) - -static void trng_get(unsigned char *pConversionData) -{ - uint32_t *p32ConversionData; - - p32ConversionData = (uint32_t *)pConversionData; - - PRNG_Open(CRYPTO_MODBASE(), PRNG_KEY_SIZE_256, 1, us_ticker_read()); - crypto_prng_prestart(); - PRNG_Start(CRYPTO_MODBASE()); - crypto_prng_wait(); - - PRNG_Read(CRYPTO_MODBASE(), p32ConversionData); -} - -void trng_init(trng_t *obj) -{ - (void)obj; - - /* Init crypto module */ - crypto_init(); - - PRNG_ENABLE_INT(CRYPTO_MODBASE()); -} - -void trng_free(trng_t *obj) -{ - (void)obj; - - PRNG_DISABLE_INT(CRYPTO_MODBASE()); - - /* Uninit crypto module */ - crypto_uninit(); -} - -int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length) -{ - (void)obj; - unsigned char tmpBuff[PRNG_KEY_SIZE]; - size_t cur_length = 0; - - while (length >= sizeof(tmpBuff)) { - trng_get(output); - output += sizeof(tmpBuff); - cur_length += sizeof(tmpBuff); - length -= sizeof(tmpBuff); - } - if (length > 0) { - trng_get(tmpBuff); - memcpy(output, tmpBuff, length); - cur_length += length; - crypto_zeroize(tmpBuff, sizeof(tmpBuff)); - } - *output_length = cur_length; - return 0; -} - -#endif diff --git a/targets/targets.json b/targets/targets.json index 0ad7cad1ad6..b8d58117454 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -8895,7 +8895,6 @@ "SPI", "SPISLAVE", "SPI_ASYNCH", - "TRNG", "FLASH", "MPU" ], From 08a2709993b4ad7b50467a6f11c6f260720e3046 Mon Sep 17 00:00:00 2001 From: Matthew Macovsky Date: Fri, 6 Sep 2019 18:09:21 +0100 Subject: [PATCH 206/227] Allow for arbitrary QSPI alt sizes The QSPI spec allows alt to be any size that is a multiple of the number of data lines. For example, Micron's N25Q128A uses only a single alt cycle for all read modes (1, 2, or 4 bits depending on how many data lines are in use). --- TESTS/mbed_hal/qspi/qspi_test_utils.h | 8 +- .../COMPONENT_QSPIF/QSPIFBlockDevice.cpp | 13 +- drivers/QSPI.h | 2 +- drivers/source/QSPI.cpp | 29 +++- .../direct_access_devicekey_test/main.cpp | 2 +- hal/qspi_api.h | 7 +- .../TARGET_Cypress/TARGET_PSOC6/cy_qspi_api.c | 17 +- .../psoc6csp/hal/include/cyhal_qspi.h | 11 +- .../psoc6csp/hal/src/cyhal_qspi.c | 123 +++++++++++--- targets/TARGET_STM/qspi_api.c | 154 +++++++++++++----- .../TARGET_EFM32/qspi_api.c | 6 +- 11 files changed, 266 insertions(+), 106 deletions(-) diff --git a/TESTS/mbed_hal/qspi/qspi_test_utils.h b/TESTS/mbed_hal/qspi/qspi_test_utils.h index 08f16f42c9f..0c29232e51e 100644 --- a/TESTS/mbed_hal/qspi/qspi_test_utils.h +++ b/TESTS/mbed_hal/qspi/qspi_test_utils.h @@ -102,10 +102,10 @@ struct Qspi { #define ADDR_SIZE_24 QSPI_CFG_ADDR_SIZE_24 #define ADDR_SIZE_32 QSPI_CFG_ADDR_SIZE_32 -#define ALT_SIZE_8 QSPI_CFG_ALT_SIZE_8 -#define ALT_SIZE_16 QSPI_CFG_ALT_SIZE_16 -#define ALT_SIZE_24 QSPI_CFG_ALT_SIZE_24 -#define ALT_SIZE_32 QSPI_CFG_ALT_SIZE_32 +#define ALT_SIZE_8 8u +#define ALT_SIZE_16 16u +#define ALT_SIZE_24 24u +#define ALT_SIZE_32 32u #define STATUS_REG QSPI_CMD_RDSR #define CONFIG_REG0 QSPI_CMD_RDCR0 diff --git a/components/storage/blockdevice/COMPONENT_QSPIF/QSPIFBlockDevice.cpp b/components/storage/blockdevice/COMPONENT_QSPIF/QSPIFBlockDevice.cpp index 7010b22cfbe..bc0d424188d 100644 --- a/components/storage/blockdevice/COMPONENT_QSPIF/QSPIFBlockDevice.cpp +++ b/components/storage/blockdevice/COMPONENT_QSPIF/QSPIFBlockDevice.cpp @@ -247,7 +247,7 @@ int QSPIFBlockDevice::init() // Configure BUS Mode to 1_1_1 for all commands other than Read _qspi_configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_SINGLE, - QSPI_CFG_ALT_SIZE_8, QSPI_CFG_BUS_SINGLE, 0); + 0, QSPI_CFG_BUS_SINGLE, 0); _is_initialized = true; @@ -303,7 +303,7 @@ int QSPIFBlockDevice::read(void *buffer, bd_addr_t addr, bd_size_t size) // Configure Bus for Reading _qspi_configure_format(_inst_width, _address_width, _address_size, QSPI_CFG_BUS_SINGLE, - QSPI_CFG_ALT_SIZE_8, _data_width, _dummy_and_mode_cycles); + 0, _data_width, _dummy_and_mode_cycles); if (QSPI_STATUS_OK != _qspi_send_read_command(_read_instruction, buffer, addr, size)) { status = QSPIF_BD_ERROR_DEVICE_ERROR; @@ -312,7 +312,7 @@ int QSPIFBlockDevice::read(void *buffer, bd_addr_t addr, bd_size_t size) // All commands other than Read use default 1-1-1 Bus mode (Program/Erase are constrained by flash memory performance less than that of the bus) _qspi_configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_SINGLE, - QSPI_CFG_ALT_SIZE_8, QSPI_CFG_BUS_SINGLE, 0); + 0, QSPI_CFG_BUS_SINGLE, 0); _mutex.unlock(); return status; @@ -718,7 +718,7 @@ int QSPIFBlockDevice::_sfdp_parse_sfdp_headers(uint32_t &basic_table_addr, size_ // Set 1-1-1 bus mode for SFDP header parsing _qspi_configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_SINGLE, - QSPI_CFG_ALT_SIZE_8, QSPI_CFG_BUS_SINGLE, 8); + 0, QSPI_CFG_BUS_SINGLE, 8); qspi_status_t status = _qspi_send_read_command(QSPIF_SFDP, (char *)sfdp_header, addr /*address*/, data_length); if (status != QSPI_STATUS_OK) { @@ -885,7 +885,7 @@ int QSPIFBlockDevice::_sfdp_set_quad_enabled(uint8_t *basic_param_table_ptr) // Configure BUS Mode to 1_1_1 for all commands other than Read _qspi_configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_SINGLE, - QSPI_CFG_ALT_SIZE_8, QSPI_CFG_BUS_SINGLE, 0); + 0, QSPI_CFG_BUS_SINGLE, 0); // Read Status Register if (QSPI_STATUS_OK == _qspi_send_general_command(_read_register_inst, QSPI_NO_ADDRESS_COMMAND, NULL, 0, @@ -1206,7 +1206,7 @@ int QSPIFBlockDevice::_enable_fast_mdoe() // Configure BUS Mode to 1_1_1 for all commands other than Read _qspi_configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_SINGLE, - QSPI_CFG_ALT_SIZE_8, QSPI_CFG_BUS_SINGLE, 0); + 0, QSPI_CFG_BUS_SINGLE, 0); // Read Status Register if (QSPI_STATUS_OK == _qspi_send_general_command(read_conf_register_inst, QSPI_NO_ADDRESS_COMMAND, NULL, 0, @@ -1306,7 +1306,6 @@ int QSPIFBlockDevice::_utils_iterate_next_largest_erase_type(uint8_t &bitfield, tr_error("No erase type was found for current region addr"); } return largest_erase_type; - } /***************************************************/ diff --git a/drivers/QSPI.h b/drivers/QSPI.h index 4ab356a0091..657be507260 100644 --- a/drivers/QSPI.h +++ b/drivers/QSPI.h @@ -106,7 +106,7 @@ class QSPI : private NonCopyable { * @param address_width Bus width used by address phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD) * @param address_size Size in bits used by address phase(Valid values are QSPI_CFG_ADDR_SIZE_8, QSPI_CFG_ADDR_SIZE_16, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_ADDR_SIZE_32) * @param alt_width Bus width used by alt phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD) - * @param alt_size Size in bits used by alt phase(Valid values are QSPI_CFG_ALT_SIZE_8, QSPI_CFG_ALT_SIZE_16, QSPI_CFG_ALT_SIZE_24, QSPI_CFG_ALT_SIZE_32) + * @param alt_size Size in bits used by alt phase (must be a multiple of the number of bus lines indicated in alt_width) * @param data_width Bus width used by data phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD) * @param dummy_cycles Number of dummy clock cycles to be used after alt phase * diff --git a/drivers/source/QSPI.cpp b/drivers/source/QSPI.cpp index c79c949e3b3..839c2f1e63c 100644 --- a/drivers/source/QSPI.cpp +++ b/drivers/source/QSPI.cpp @@ -26,6 +26,21 @@ namespace mbed { QSPI *QSPI::_owner = NULL; SingletonPtr QSPI::_mutex; +uint8_t convert_bus_width_to_line_count(qspi_bus_width_t width) +{ + switch (width) { + case QSPI_CFG_BUS_SINGLE: + return 1; + case QSPI_CFG_BUS_DUAL: + return 2; + case QSPI_CFG_BUS_QUAD: + return 4; + default: + // Unrecognized bus width + return 0; + } +} + QSPI::QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel, int mode) : _qspi() { _qspi_io0 = io0; @@ -38,7 +53,7 @@ QSPI::QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, Pin _address_width = QSPI_CFG_BUS_SINGLE; _address_size = QSPI_CFG_ADDR_SIZE_24; _alt_width = QSPI_CFG_BUS_SINGLE; - _alt_size = QSPI_CFG_ALT_SIZE_8; + _alt_size = 0; _data_width = QSPI_CFG_BUS_SINGLE; _num_dummy_cycles = 0; _mode = mode; @@ -52,7 +67,14 @@ QSPI::QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, Pin qspi_status_t QSPI::configure_format(qspi_bus_width_t inst_width, qspi_bus_width_t address_width, qspi_address_size_t address_size, qspi_bus_width_t alt_width, qspi_alt_size_t alt_size, qspi_bus_width_t data_width, int dummy_cycles) { - qspi_status_t ret_status = QSPI_STATUS_OK; + // Check that alt_size/alt_width are a valid combination + uint8_t alt_lines = convert_bus_width_to_line_count(alt_width); + if (alt_lines == 0) { + return QSPI_STATUS_ERROR; + } else if (alt_size % alt_lines != 0) { + // Invalid alt size/width combination (alt size is not a multiple of the number of bus lines used to transmit it) + return QSPI_STATUS_ERROR; + } lock(); _inst_width = inst_width; @@ -62,10 +84,9 @@ qspi_status_t QSPI::configure_format(qspi_bus_width_t inst_width, qspi_bus_width _alt_size = alt_size; _data_width = data_width; _num_dummy_cycles = dummy_cycles; - unlock(); - return ret_status; + return QSPI_STATUS_OK; } qspi_status_t QSPI::set_frequency(int hz) diff --git a/features/storage/TESTS/kvstore/direct_access_devicekey_test/main.cpp b/features/storage/TESTS/kvstore/direct_access_devicekey_test/main.cpp index ba3fb6bb631..cf6a60f9f81 100644 --- a/features/storage/TESTS/kvstore/direct_access_devicekey_test/main.cpp +++ b/features/storage/TESTS/kvstore/direct_access_devicekey_test/main.cpp @@ -255,7 +255,7 @@ void test_direct_access_to_device_inject_root() ret = devkey.device_inject_root_of_trust(key, DEVICE_KEY_16BYTE); TEST_ASSERT_EQUAL_INT(DEVICEKEY_SUCCESS, ret); - // Now use Direct Access To DeviceKey to retrieve it */ + // Now use Direct Access To DeviceKey to retrieve it uint32_t internal_start_address; uint32_t internal_rbp_size; bool is_conf_tdb_internal = false; diff --git a/hal/qspi_api.h b/hal/qspi_api.h index 8464c2d6b2c..8314c5bb7f9 100644 --- a/hal/qspi_api.h +++ b/hal/qspi_api.h @@ -60,12 +60,7 @@ typedef enum qspi_address_size { /** Alternative size in bits */ -typedef enum qspi_alt_size { - QSPI_CFG_ALT_SIZE_8, - QSPI_CFG_ALT_SIZE_16, - QSPI_CFG_ALT_SIZE_24, - QSPI_CFG_ALT_SIZE_32, -} qspi_alt_size_t; +typedef uint8_t qspi_alt_size_t; /** QSPI command * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/cy_qspi_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/cy_qspi_api.c index cd28b088441..3404dcc75d0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/cy_qspi_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/cy_qspi_api.c @@ -69,21 +69,6 @@ static inline cyhal_qspi_size_t cyhal_qspi_convert_addr_size(qspi_address_size_t } } -static inline cyhal_qspi_size_t cyhal_qspi_convert_alt_size(qspi_alt_size_t size) -{ - switch (size) { - case QSPI_CFG_ALT_SIZE_8: - return CYHAL_QSPI_CFG_SIZE_8; - case QSPI_CFG_ALT_SIZE_16: - return CYHAL_QSPI_CFG_SIZE_16; - case QSPI_CFG_ALT_SIZE_24: - return CYHAL_QSPI_CFG_SIZE_24; - default: // fallthrough - case QSPI_CFG_ALT_SIZE_32: - return CYHAL_QSPI_CFG_SIZE_32; - } -} - static void cyhal_qspi_convert_command(const qspi_command_t *from, cyhal_qspi_command_t *to) { to->instruction.bus_width = cyhal_qspi_convert_width(from->instruction.bus_width); @@ -94,7 +79,7 @@ static void cyhal_qspi_convert_command(const qspi_command_t *from, cyhal_qspi_co to->address.value = from->address.value; to->address.disabled = from->address.disabled; to->mode_bits.bus_width = cyhal_qspi_convert_width(from->alt.bus_width); - to->mode_bits.size = cyhal_qspi_convert_alt_size(from->alt.size); + to->mode_bits.size = from->alt.size; to->mode_bits.value = from->alt.value; to->mode_bits.disabled = from->alt.disabled; to->dummy_count = from->dummy_count; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_qspi.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_qspi.h index b3ba4d91233..bf67b384527 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_qspi.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_qspi.h @@ -71,9 +71,12 @@ typedef enum { } cyhal_qspi_event_t; #define CYHAL_QSPI_RSLT_ERR_BUS_WIDTH (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 0)) /**< Bus width Error. >*/ -#define CYHAL_QSPI_RSLT_ERR_PIN (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 1)) /**< Pin related Error. >*/ -#define CYHAL_QSPI_RSLT_ERR_DATA_SEL (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 2)) /**< Data select Error. >*/ -#define CYHAL_QSPI_RSLT_ERR_INSTANCE (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 3)) /**< QSPI instance related Error. >*/ +#define CYHAL_QSPI_RSLT_ERR_SIZE (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 1)) /**< Size Error. >*/ +#define CYHAL_QSPI_RSLT_ERR_PIN (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 2)) /**< Pin related Error. >*/ +#define CYHAL_QSPI_RSLT_ERR_DATA_SEL (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 3)) /**< Data select Error. >*/ +#define CYHAL_QSPI_RSLT_ERR_INSTANCE (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 4)) /**< QSPI instance related Error. >*/ +#define CYHAL_QSPI_RSLT_ERR_ALT_SIZE_WIDTH_MISMATCH (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 5)) /**< Provided alt size is incompatible with provided alt width. >*/ +#define CYHAL_QSPI_RSLT_ERR_ALT_SIZE_DUMMY_CYCLES_MISMATCH (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 6)) /**< Provided alt size is incompatible with provided number of dummy cycles (due to device-specific restrictions). >*/ /** @brief QSPI command settings */ typedef struct cyhal_qspi_command { @@ -90,7 +93,7 @@ typedef struct cyhal_qspi_command { } address; struct { cyhal_qspi_bus_width_t bus_width; /**< Bus width for mode bits >*/ - cyhal_qspi_size_t size; /**< Mode bits size >*/ + uint8_t size; /**< Mode bits size >*/ uint32_t value; /**< Mode bits value >*/ bool disabled; /**< Mode bits phase skipped if disabled is set to true >*/ } mode_bits; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_qspi.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_qspi.c index 2842e623470..5c4c852a6d6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_qspi.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_qspi.c @@ -292,16 +292,45 @@ static inline uint32_t get_size(cyhal_qspi_size_t hal_size) return ((uint32_t)hal_size >> 3); /* convert bits to bytes */ } +/* cyhal_qspi_bus_width_t to number of bus lines used */ +static uint8_t get_lines(cyhal_qspi_bus_width_t hal_width) +{ + uint8_t lines; + + switch (hal_width) + { + case CYHAL_QSPI_CFG_BUS_SINGLE: + lines = 1; + break; + case CYHAL_QSPI_CFG_BUS_DUAL: + lines = 2; + break; + case CYHAL_QSPI_CFG_BUS_QUAD: + lines = 4; + break; + case CYHAL_QSPI_CFG_BUS_OCTAL: + lines = 8; + break; + default: + lines = 0; + } + + return lines; +} + /* Sends QSPI command with certain set of data */ /* Address passed through 'command' is not used, instead the value in 'addr' is used. */ static cy_rslt_t qspi_command_transfer(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command, - uint32_t addr, bool endOfTransfer) + uint32_t addr, bool endOfTransfer, uint8_t *dummy_cycles) { /* max address size is 4 bytes and max mode bits size is 4 bytes */ uint8_t cmd_param[8] = {0}; uint32_t start_pos = 0; uint32_t addr_size = 0; - uint32_t mode_bits_size = 0; + uint32_t mode_size = 0; + uint8_t leftover_bits = 0; + uint8_t lines = 0; + uint8_t integrated_dummy_cycles = 0; cy_en_smif_txfr_width_t bus_width = CY_SMIF_WIDTH_SINGLE; cy_stc_smif_mem_cmd_t cyhal_cmd_config; cy_rslt_t result = CY_RSLT_SUCCESS; @@ -332,22 +361,67 @@ static cy_rslt_t qspi_command_transfer(cyhal_qspi_t *obj, const cyhal_qspi_comma if (!command->address.disabled) { addr_size = get_size(command->address.size); - uint32_to_byte_array(addr, cmd_param, start_pos, addr_size); - start_pos += addr_size; - bus_width = cyhal_cmd_config.addrWidth; + if (addr_size == 0) + { + result = CYHAL_QSPI_RSLT_ERR_SIZE; + } + else + { + uint32_to_byte_array(addr, cmd_param, start_pos, addr_size); + start_pos += addr_size; + bus_width = cyhal_cmd_config.addrWidth; + } } if (!command->mode_bits.disabled) { - mode_bits_size = get_size(command->mode_bits.size); - uint32_to_byte_array(cyhal_cmd_config.mode, cmd_param, start_pos, mode_bits_size); - bus_width = cyhal_cmd_config.modeWidth; + // Mode size must be a multiple of the number of bus lines used (i.e. a whole number of cycles) + lines = get_lines(command->mode_bits.bus_width); + if (lines == 0) + { + result = CYHAL_QSPI_RSLT_ERR_BUS_WIDTH; + } + else if (command->mode_bits.size % lines != 0) + { + result = CYHAL_QSPI_RSLT_ERR_ALT_SIZE_WIDTH_MISMATCH; + } + else + { + // Round mode size up to nearest byte - unused parts of byte act as dummy cycles + mode_size = get_size(command->mode_bits.size - 1) + 1; + + // Unused bits in most significant byte of mode + leftover_bits = (mode_size << 3) - command->mode_bits.size; + if (leftover_bits != 0) + { + // Account for dummy cycles that will be spent in the mode portion of the command + integrated_dummy_cycles = (8 - (command->mode_bits.size % 8)) / lines; + if (*dummy_cycles < integrated_dummy_cycles) + { + // Not enough dummy cycles to account for a short mode + result = CYHAL_QSPI_RSLT_ERR_ALT_SIZE_DUMMY_CYCLES_MISMATCH; + } + else + { + *dummy_cycles -= integrated_dummy_cycles; + } + + // Align mode value to the end of the most significant byte + cyhal_cmd_config.mode <<= leftover_bits; + } + + uint32_to_byte_array(cyhal_cmd_config.mode, cmd_param, start_pos, mode_size); + bus_width = cyhal_cmd_config.modeWidth; + } } - uint32_t cmpltTxfr = ((endOfTransfer) ? 1UL : 0UL); - result = (cy_rslt_t)Cy_SMIF_TransmitCommand(obj->base, cyhal_cmd_config.command, - cyhal_cmd_config.cmdWidth, cmd_param, (addr_size + mode_bits_size), - bus_width, obj->slave_select, cmpltTxfr, &obj->context); + if (CY_RSLT_SUCCESS == result) + { + uint32_t cmpltTxfr = ((endOfTransfer) ? 1UL : 0UL); + result = (cy_rslt_t)Cy_SMIF_TransmitCommand(obj->base, cyhal_cmd_config.command, + cyhal_cmd_config.cmdWidth, cmd_param, (addr_size + mode_size), + bus_width, obj->slave_select, cmpltTxfr, &obj->context); + } } return result; } @@ -810,6 +884,7 @@ cy_rslt_t cyhal_qspi_read(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command uint32_t chunk = 0; size_t read_bytes = *length; uint32_t addr = command->address.value; + uint8_t dummy_cycles = command->dummy_count; /* SMIF can read only up to 65536 bytes in one go. Split the larger read into multiple chunks */ while (read_bytes > 0) @@ -823,11 +898,11 @@ cy_rslt_t cyhal_qspi_read(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command * to create a copy of the command object. Instead of copying the object, the address is * passed separately. */ - status = qspi_command_transfer(obj, command, addr, false); + status = qspi_command_transfer(obj, command, addr, false, &dummy_cycles); if (CY_RSLT_SUCCESS == status) { - if (command->dummy_count > 0u) + if (dummy_cycles > 0u) { status = (cy_rslt_t)Cy_SMIF_SendDummyCycles(obj->base, command->dummy_count); } @@ -852,13 +927,15 @@ cy_rslt_t cyhal_qspi_read(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command cy_rslt_t cyhal_qspi_read_async(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command, void *data, size_t *length) { - cy_rslt_t status = qspi_command_transfer(obj, command, command->address.value, false); - + cy_rslt_t status = CY_RSLT_SUCCESS; + uint32_t addr = command->address.value; + uint8_t dummy_cycles = command->dummy_count; + status = qspi_command_transfer(obj, command, addr, false, &dummy_cycles); if (CY_RSLT_SUCCESS == status) { if (command->dummy_count > 0u) { - status = (cy_rslt_t)Cy_SMIF_SendDummyCycles(obj->base, command->dummy_count); + status = (cy_rslt_t)Cy_SMIF_SendDummyCycles(obj->base, dummy_cycles); } if (CY_RSLT_SUCCESS == status) @@ -873,13 +950,14 @@ cy_rslt_t cyhal_qspi_read_async(cyhal_qspi_t *obj, const cyhal_qspi_command_t *c /* length can be up to 65536. */ cy_rslt_t cyhal_qspi_write(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command, const void *data, size_t *length) { - cy_rslt_t status = qspi_command_transfer(obj, command, command->address.value, false); + uint8_t dummy_cycles = command->dummy_count; + cy_rslt_t status = qspi_command_transfer(obj, command, command->address.value, false, &dummy_cycles); if (CY_RSLT_SUCCESS == status) { if (command->dummy_count > 0u) { - status = (cy_rslt_t)Cy_SMIF_SendDummyCycles(obj->base, command->dummy_count); + status = (cy_rslt_t)Cy_SMIF_SendDummyCycles(obj->base, dummy_cycles); } if ((CY_SMIF_SUCCESS == status) && (*length > 0)) @@ -895,13 +973,14 @@ cy_rslt_t cyhal_qspi_write(cyhal_qspi_t *obj, const cyhal_qspi_command_t *comman /* length can be up to 65536. */ cy_rslt_t cyhal_qspi_write_async(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command, const void *data, size_t *length) { - cy_rslt_t status = qspi_command_transfer(obj, command, command->address.value, false); + uint8_t dummy_cycles = command->dummy_count; + cy_rslt_t status = qspi_command_transfer(obj, command, command->address.value, false, &dummy_cycles); if (CY_RSLT_SUCCESS == status) { if (command->dummy_count > 0u) { - status = (cy_rslt_t)Cy_SMIF_SendDummyCycles(obj->base, command->dummy_count); + status = (cy_rslt_t)Cy_SMIF_SendDummyCycles(obj->base, dummy_cycles); } if ((CY_SMIF_SUCCESS == status) && (*length > 0)) @@ -922,7 +1001,7 @@ cy_rslt_t cyhal_qspi_transfer( if ((tx_data == NULL || tx_size == 0) && (rx_data == NULL || rx_size == 0)) { /* only command, no rx or tx */ - status = qspi_command_transfer(obj, command, command->address.value, true); + status = qspi_command_transfer(obj, command, command->address.value, true, NULL); } else { diff --git a/targets/TARGET_STM/qspi_api.c b/targets/TARGET_STM/qspi_api.c index 789bdaba49c..e0e4fc759be 100644 --- a/targets/TARGET_STM/qspi_api.c +++ b/targets/TARGET_STM/qspi_api.c @@ -43,7 +43,7 @@ #define QSPI_FLASH_SIZE_DEFAULT 0x80000000 #if defined(OCTOSPI1) -void qspi_prepare_command(const qspi_command_t *command, OSPI_RegularCmdTypeDef *st_command) +qspi_status_t qspi_prepare_command(const qspi_command_t *command, OSPI_RegularCmdTypeDef *st_command) { debug_if(qspi_api_c_debug, "qspi_prepare_command In: instruction.value %x dummy_count %x address.bus_width %x address.disabled %x address.value %x address.size %x\n", command->instruction.value, command->dummy_count, command->address.bus_width, command->address.disabled, command->address.value, command->address.size); @@ -66,8 +66,8 @@ void qspi_prepare_command(const qspi_command_t *command, OSPI_RegularCmdTypeDef st_command->InstructionMode = HAL_OSPI_INSTRUCTION_4_LINES; break; default: - error("Command param error: wrong istruction format\n"); - break; + error("Command param error: wrong instruction format\n"); + return QSPI_STATUS_ERROR; } } @@ -99,7 +99,7 @@ void qspi_prepare_command(const qspi_command_t *command, OSPI_RegularCmdTypeDef break; default: error("Command param error: wrong address size\n"); - break; + return QSPI_STATUS_ERROR; } switch(command->address.size) { case QSPI_CFG_ADDR_SIZE_8: @@ -116,7 +116,7 @@ void qspi_prepare_command(const qspi_command_t *command, OSPI_RegularCmdTypeDef break; default: error("Command param error: wrong address size\n"); - break; + return QSPI_STATUS_ERROR; } } @@ -124,39 +124,62 @@ void qspi_prepare_command(const qspi_command_t *command, OSPI_RegularCmdTypeDef st_command->AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE; st_command->AlternateBytesSize = 0; } else { - st_command->AlternateBytes = command->alt.value; + uint8_t alt_lines = 0; switch (command->alt.bus_width) { case QSPI_CFG_BUS_SINGLE: st_command->AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_1_LINE; + alt_lines = 1; break; case QSPI_CFG_BUS_DUAL: st_command->AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_2_LINES; + alt_lines = 2; break; case QSPI_CFG_BUS_QUAD: st_command->AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_4_LINES; + alt_lines = 4; break; default: st_command->AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE; - break; + error("Command param error: invalid alt bytes mode\n"); + return QSPI_STATUS_ERROR; } - switch(command->alt.size) { - case QSPI_CFG_ALT_SIZE_8: - st_command->AlternateBytesSize = HAL_OSPI_ALTERNATE_BYTES_8_BITS; - break; - case QSPI_CFG_ALT_SIZE_16: - st_command->AlternateBytesSize = HAL_OSPI_ALTERNATE_BYTES_16_BITS; - break; - case QSPI_CFG_ALT_SIZE_24: - st_command->AlternateBytesSize = HAL_OSPI_ALTERNATE_BYTES_24_BITS; - break; - case QSPI_CFG_ALT_SIZE_32: - st_command->AlternateBytesSize = HAL_OSPI_ALTERNATE_BYTES_32_BITS; - break; - default: - st_command->AlternateBytesSize = 0; - printf("Command param error: wrong address size\n"); - break; + + // Alt size must be a multiple of the number of bus lines used (i.e. a whole number of cycles) + if (command->alt.size % alt_lines != 0) { + error("Command param error: incompatible alt size and alt bus width\n"); + return QSPI_STATUS_ERROR; } + + // Round up to nearest byte - unused parts of byte act as dummy cycles + uint32_t rounded_size = ((command->alt.size - 1) >> 3) + 1; + // Maximum of 4 alt bytes + if (rounded_size > 4) { + error("Command param error: alt size exceeds maximum of 32 bits\n"); + return QSPI_STATUS_ERROR; + } + + // Unused bits in most significant byte of alt + uint8_t leftover_bits = (rounded_size << 3) - command->alt.size; + if (leftover_bits != 0) { + // Account for dummy cycles that will be spent in the alt portion of the command + uint8_t integrated_dummy_cycles = leftover_bits / alt_lines; + if (st_command->DummyCycles < integrated_dummy_cycles) + { + // Not enough dummy cycles to account for a short alt + error("Command param error: not enough dummy cycles to make up for given alt size\n"); + return QSPI_STATUS_ERROR; + } + st_command->DummyCycles -= integrated_dummy_cycles; + + // Align alt value to the end of the most significant byte + st_command->AlternateBytes = command->alt.value << leftover_bits; + } else { + st_command->AlternateBytes = command->alt.value; + } + + /* command->AlternateBytesSize needs to be shifted by OCTOSPI_CCR_ABSIZE_Pos */ + // 0b00 = 1 byte, 0b01 = 2 bytes, 0b10 = 3 bytes, 0b11 = 4 bytes + st_command->AlternateBytesSize = ((rounded_size - 1) << OCTOSPI_CCR_ABSIZE_Pos) & OCTOSPI_CCR_ABSIZE_Msk; } switch (command->data.bus_width) { @@ -176,9 +199,11 @@ void qspi_prepare_command(const qspi_command_t *command, OSPI_RegularCmdTypeDef debug_if(qspi_api_c_debug, "qspi_prepare_command Out: InstructionMode %x Instruction %x AddressMode %x AddressSize %x Address %x DataMode %x\n", st_command->InstructionMode, st_command->Instruction, st_command->AddressMode, st_command->AddressSize, st_command->Address, st_command->DataMode); + + return QSPI_STATUS_OK; } #else /* OCTOSPI */ -void qspi_prepare_command(const qspi_command_t *command, QSPI_CommandTypeDef *st_command) +qspi_status_t qspi_prepare_command(const qspi_command_t *command, QSPI_CommandTypeDef *st_command) { debug_if(qspi_api_c_debug, "qspi_prepare_command In: instruction.value %x dummy_count %x address.bus_width %x address.disabled %x address.value %x address.size %x\n", command->instruction.value, command->dummy_count, command->address.bus_width, command->address.disabled, command->address.value, command->address.size); @@ -230,15 +255,19 @@ void qspi_prepare_command(const qspi_command_t *command, QSPI_CommandTypeDef *st st_command->AddressSize = (command->address.size << QUADSPI_CCR_ADSIZE_Pos) & QUADSPI_CCR_ADSIZE_Msk; } + uint8_t alt_lines = 0; switch (command->alt.bus_width) { case QSPI_CFG_BUS_SINGLE: st_command->AlternateByteMode = QSPI_ALTERNATE_BYTES_1_LINE; + alt_lines = 1; break; case QSPI_CFG_BUS_DUAL: st_command->AlternateByteMode = QSPI_ALTERNATE_BYTES_2_LINES; + alt_lines = 2; break; case QSPI_CFG_BUS_QUAD: st_command->AlternateByteMode = QSPI_ALTERNATE_BYTES_4_LINES; + alt_lines = 4; break; default: st_command->AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; @@ -249,10 +278,40 @@ void qspi_prepare_command(const qspi_command_t *command, QSPI_CommandTypeDef *st st_command->AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; st_command->AlternateBytesSize = 0; } else { - st_command->AlternateBytes = command->alt.value; + // Alt size must be a multiple of the number of bus lines used (i.e. a whole number of cycles) + if ((alt_lines == 0) || (command->alt.size % alt_lines != 0)) { + return QSPI_STATUS_ERROR; + } + + // Round up to nearest byte - unused parts of byte act as dummy cycles + uint32_t rounded_size = ((command->alt.size - 1) >> 3) + 1; + // Maximum of 4 alt bytes + if (rounded_size > 4) { + return QSPI_STATUS_ERROR; + } + + // Unused bits in most significant byte of alt + uint8_t leftover_bits = (rounded_size << 3) - command->alt.size; + if (leftover_bits != 0) { + // Account for dummy cycles that will be spent in the alt portion of the command + uint8_t integrated_dummy_cycles = leftover_bits / alt_lines; + if (st_command->DummyCycles < integrated_dummy_cycles) + { + // Not enough dummy cycles to account for a short alt + return QSPI_STATUS_ERROR; + } + st_command->DummyCycles -= integrated_dummy_cycles; + + // Align alt value to the end of the most significant byte + st_command->AlternateBytes = command->alt.value << leftover_bits; + } else { + rounded_size -= 1; + st_command->AlternateBytes = command->alt.value; + } + /* command->AlternateBytesSize needs to be shifted by QUADSPI_CCR_ABSIZE_Pos */ - st_command->AlternateBytesSize = (command->alt.size << QUADSPI_CCR_ABSIZE_Pos) & QUADSPI_CCR_ABSIZE_Msk; - st_command->AlternateBytesSize = command->alt.size; + // 0b00 = 1 byte, 0b01 = 2 bytes, 0b10 = 3 bytes, 0b11 = 4 bytes + st_command->AlternateBytesSize = ((rounded_size - 1) << QUADSPI_CCR_ABSIZE_Pos) & QUADSPI_CCR_ABSIZE_Msk; } switch (command->data.bus_width) { @@ -271,8 +330,11 @@ void qspi_prepare_command(const qspi_command_t *command, QSPI_CommandTypeDef *st } st_command->NbData = 0; + debug_if(qspi_api_c_debug, "qspi_prepare_command Out: InstructionMode %x Instruction %x AddressMode %x AddressSize %x Address %x DataMode %x\n", st_command->InstructionMode, st_command->Instruction, st_command->AddressMode, st_command->AddressSize, st_command->Address, st_command->DataMode); + + return QSPI_STATUS_OK; } #endif /* OCTOSPI */ @@ -586,10 +648,12 @@ qspi_status_t qspi_write(qspi_t *obj, const qspi_command_t *command, const void debug_if(qspi_api_c_debug, "qspi_write size %u\n", *length); OSPI_RegularCmdTypeDef st_command; - qspi_prepare_command(command, &st_command); + qspi_status_t status = qspi_prepare_command(command, &st_command); + if (status != QSPI_STATUS_OK) { + return status; + } st_command.NbData = *length; - qspi_status_t status = QSPI_STATUS_OK; if (HAL_OSPI_Command(&obj->handle, &st_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { debug_if(qspi_api_c_debug, "HAL_OSPI_Command error\n"); @@ -607,10 +671,12 @@ qspi_status_t qspi_write(qspi_t *obj, const qspi_command_t *command, const void qspi_status_t qspi_write(qspi_t *obj, const qspi_command_t *command, const void *data, size_t *length) { QSPI_CommandTypeDef st_command; - qspi_prepare_command(command, &st_command); + qspi_status_t status = qspi_prepare_command(command, &st_command); + if (status != QSPI_STATUS_OK) { + return status; + } st_command.NbData = *length; - qspi_status_t status = QSPI_STATUS_OK; if (HAL_QSPI_Command(&obj->handle, &st_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { status = QSPI_STATUS_ERROR; @@ -631,10 +697,12 @@ qspi_status_t qspi_write(qspi_t *obj, const qspi_command_t *command, const void qspi_status_t qspi_read(qspi_t *obj, const qspi_command_t *command, void *data, size_t *length) { OSPI_RegularCmdTypeDef st_command; - qspi_prepare_command(command, &st_command); + qspi_status_t status = qspi_prepare_command(command, &st_command); + if (status != QSPI_STATUS_OK) { + return status; + } st_command.NbData = *length; - qspi_status_t status = QSPI_STATUS_OK; if (HAL_OSPI_Command(&obj->handle, &st_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { debug_if(qspi_api_c_debug, "HAL_OSPI_Command error\n"); @@ -654,10 +722,12 @@ qspi_status_t qspi_read(qspi_t *obj, const qspi_command_t *command, void *data, qspi_status_t qspi_read(qspi_t *obj, const qspi_command_t *command, void *data, size_t *length) { QSPI_CommandTypeDef st_command; - qspi_prepare_command(command, &st_command); - + qspi_status_t status = qspi_prepare_command(command, &st_command); + if (status != QSPI_STATUS_OK) { + return status; + } + st_command.NbData = *length; - qspi_status_t status = QSPI_STATUS_OK; if (HAL_QSPI_Command(&obj->handle, &st_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) { status = QSPI_STATUS_ERROR; @@ -683,7 +753,10 @@ qspi_status_t qspi_command_transfer(qspi_t *obj, const qspi_command_t *command, if ((tx_data == NULL || tx_size == 0) && (rx_data == NULL || rx_size == 0)) { // only command, no rx or tx OSPI_RegularCmdTypeDef st_command; - qspi_prepare_command(command, &st_command); + status = qspi_prepare_command(command, &st_command); + if (status != QSPI_STATUS_OK) { + return status; + } st_command.NbData = 1; st_command.DataMode = HAL_OSPI_DATA_NONE; /* Instruction only */ @@ -720,7 +793,10 @@ qspi_status_t qspi_command_transfer(qspi_t *obj, const qspi_command_t *command, if ((tx_data == NULL || tx_size == 0) && (rx_data == NULL || rx_size == 0)) { // only command, no rx or tx QSPI_CommandTypeDef st_command; - qspi_prepare_command(command, &st_command); + status = qspi_prepare_command(command, &st_command); + if (status != QSPI_STATUS_OK) { + return status; + } st_command.NbData = 1; st_command.DataMode = QSPI_DATA_NONE; /* Instruction only */ diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/qspi_api.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/qspi_api.c index 1435751b1b1..75f988b6a48 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/qspi_api.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/qspi_api.c @@ -33,6 +33,8 @@ #include "PeripheralPins.h" #include "pinmap_function.h" +#define SUPPORTED_ALT_SIZE 8u + qspi_status_t qspi_init(qspi_t *obj, PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel, uint32_t hz, uint8_t mode) { @@ -268,7 +270,7 @@ qspi_status_t qspi_command_transfer(qspi_t *obj, const qspi_command_t *command, cfg.modeBitEnable = true; obj->instance->MODEBITCONFIG = command->alt.value & _QSPI_MODEBITCONFIG_MODE_MASK; - if(command->alt.size != QSPI_CFG_ALT_SIZE_8) { + if(command->alt.size != SUPPORTED_ALT_SIZE) { //do not support 'alt' bigger than 8 bit return QSPI_STATUS_INVALID_PARAMETER; } @@ -338,7 +340,7 @@ qspi_status_t qspi_read(qspi_t *obj, const qspi_command_t *command, void *data, obj->instance->DEVINSTRRDCONFIG |= QSPI_DEVINSTRRDCONFIG_MODEBITENABLE; obj->instance->MODEBITCONFIG = command->alt.value & _QSPI_MODEBITCONFIG_MODE_MASK; - if(command->alt.size != QSPI_CFG_ALT_SIZE_8) { + if(command->alt.size != SUPPORTED_ALT_SIZE) { // Do not support 'alt' bigger than 8 bit return QSPI_STATUS_INVALID_PARAMETER; } From 65e726eb9ea8ee39fcfdd67c03cb9a877004b36e Mon Sep 17 00:00:00 2001 From: Kyle Kearney Date: Mon, 30 Sep 2019 16:00:24 -0700 Subject: [PATCH 207/227] Fix possible negative QSPI alt count on STM Remove an extraneous decrement operation in cases where the alt bits size is a multiple of 8. --- targets/TARGET_STM/qspi_api.c | 1 - 1 file changed, 1 deletion(-) diff --git a/targets/TARGET_STM/qspi_api.c b/targets/TARGET_STM/qspi_api.c index e0e4fc759be..8528968c748 100644 --- a/targets/TARGET_STM/qspi_api.c +++ b/targets/TARGET_STM/qspi_api.c @@ -305,7 +305,6 @@ qspi_status_t qspi_prepare_command(const qspi_command_t *command, QSPI_CommandTy // Align alt value to the end of the most significant byte st_command->AlternateBytes = command->alt.value << leftover_bits; } else { - rounded_size -= 1; st_command->AlternateBytes = command->alt.value; } From 53352717a29c385b89b21bd7a242079c5da06356 Mon Sep 17 00:00:00 2001 From: Matthew Macovsky Date: Thu, 22 Aug 2019 18:13:58 -0500 Subject: [PATCH 208/227] Differentiate alt and dummy cycles in QSPIF Propagate separate alt cycle and dummy cycle counts from QSPIFBlockDevice down to the qspi driver, so that drivers which handle the two separately have enough information to do so. --- .../COMPONENT_QSPIF/QSPIFBlockDevice.cpp | 44 +++++++++++-------- .../COMPONENT_QSPIF/QSPIFBlockDevice.h | 6 ++- 2 files changed, 29 insertions(+), 21 deletions(-) diff --git a/components/storage/blockdevice/COMPONENT_QSPIF/QSPIFBlockDevice.cpp b/components/storage/blockdevice/COMPONENT_QSPIF/QSPIFBlockDevice.cpp index bc0d424188d..daebef73d40 100644 --- a/components/storage/blockdevice/COMPONENT_QSPIF/QSPIFBlockDevice.cpp +++ b/components/storage/blockdevice/COMPONENT_QSPIF/QSPIFBlockDevice.cpp @@ -36,6 +36,7 @@ using namespace mbed; #define UINT64_MAX -1 #endif #define QSPI_NO_ADDRESS_COMMAND UINT64_MAX +#define QSPI_ALT_DEFAULT_VALUE 0 // Status Register Bits #define QSPIF_STATUS_BIT_WIP 0x1 //Write In Progress #define QSPIF_STATUS_BIT_WEL 0x2 // Write Enable Latch @@ -168,12 +169,12 @@ int QSPIFBlockDevice::init() _inst_width = QSPI_CFG_BUS_SINGLE; _address_width = QSPI_CFG_BUS_SINGLE; _address_size = QSPI_CFG_ADDR_SIZE_24; + _alt_size = 0; + _dummy_cycles = 0; _data_width = QSPI_CFG_BUS_SINGLE; - _dummy_and_mode_cycles = 0; _write_register_inst = QSPIF_WRSR; _read_register_inst = QSPIF_RDSR; - if (QSPI_STATUS_OK != _qspi_set_frequency(_freq)) { tr_error("QSPI Set Frequency Failed"); status = QSPIF_BD_ERROR_DEVICE_ERROR; @@ -302,15 +303,15 @@ int QSPIFBlockDevice::read(void *buffer, bd_addr_t addr, bd_size_t size) _mutex.lock(); // Configure Bus for Reading - _qspi_configure_format(_inst_width, _address_width, _address_size, QSPI_CFG_BUS_SINGLE, - 0, _data_width, _dummy_and_mode_cycles); + _qspi_configure_format(_inst_width, _address_width, _address_size, _address_width, // Alt width == address width + _alt_size, _data_width, _dummy_cycles); if (QSPI_STATUS_OK != _qspi_send_read_command(_read_instruction, buffer, addr, size)) { status = QSPIF_BD_ERROR_DEVICE_ERROR; tr_error("Read Command failed"); } - // All commands other than Read use default 1-1-1 Bus mode (Program/Erase are constrained by flash memory performance less than that of the bus) + // All commands other than Read use default 1-1-1 Bus mode (Program/Erase are constrained by flash memory performance more than bus performance) _qspi_configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_SINGLE, 0, QSPI_CFG_BUS_SINGLE, 0); @@ -1024,8 +1025,9 @@ int QSPIFBlockDevice::_sfdp_detect_best_bus_read_mode(uint8_t *basic_param_table read_inst = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_444_READ_INST_BYTE]; set_quad_enable = true; is_qpi_mode = true; - _dummy_and_mode_cycles = (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_444_READ_INST_BYTE - 1] >> 5) - + (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_444_READ_INST_BYTE - 1] & 0x1F); + _dummy_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_444_READ_INST_BYTE - 1] & 0x1F; + uint8_t mode_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_444_READ_INST_BYTE - 1] >> 5; + _alt_size = mode_cycles * 4; tr_debug("Read Bus Mode set to 4-4-4, Instruction: 0x%xh", _read_instruction); //_inst_width = QSPI_CFG_BUS_QUAD; _address_width = QSPI_CFG_BUS_QUAD; @@ -1038,9 +1040,9 @@ int QSPIFBlockDevice::_sfdp_detect_best_bus_read_mode(uint8_t *basic_param_table // Fast Read 1-4-4 Supported read_inst = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_144_READ_INST_BYTE]; set_quad_enable = true; - // dummy cycles + mode cycles = Dummy Cycles - _dummy_and_mode_cycles = (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_144_READ_INST_BYTE - 1] >> 5) - + (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_144_READ_INST_BYTE - 1] & 0x1F); + _dummy_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_144_READ_INST_BYTE - 1] & 0x1F; + uint8_t mode_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_144_READ_INST_BYTE - 1] >> 5; + _alt_size = mode_cycles * 4; _address_width = QSPI_CFG_BUS_QUAD; _data_width = QSPI_CFG_BUS_QUAD; tr_debug("Read Bus Mode set to 1-4-4, Instruction: 0x%xh", _read_instruction); @@ -1051,8 +1053,9 @@ int QSPIFBlockDevice::_sfdp_detect_best_bus_read_mode(uint8_t *basic_param_table // Fast Read 1-1-4 Supported read_inst = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_114_READ_INST_BYTE]; set_quad_enable = true; - _dummy_and_mode_cycles = (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_114_READ_INST_BYTE - 1] >> 5) - + (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_114_READ_INST_BYTE - 1] & 0x1F); + _dummy_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_114_READ_INST_BYTE - 1] & 0x1F; + uint8_t mode_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_114_READ_INST_BYTE - 1] >> 5; + _alt_size = mode_cycles; _data_width = QSPI_CFG_BUS_QUAD; tr_debug("Read Bus Mode set to 1-1-4, Instruction: 0x%xh", _read_instruction); break; @@ -1061,8 +1064,9 @@ int QSPIFBlockDevice::_sfdp_detect_best_bus_read_mode(uint8_t *basic_param_table if (examined_byte & 0x01) { // Fast Read 2-2-2 Supported read_inst = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_222_READ_INST_BYTE]; - _dummy_and_mode_cycles = (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_222_READ_INST_BYTE - 1] >> 5) - + (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_222_READ_INST_BYTE - 1] & 0x1F); + _dummy_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_222_READ_INST_BYTE - 1] & 0x1F; + uint8_t mode_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_222_READ_INST_BYTE - 1] >> 5; + _alt_size = mode_cycles * 2; _address_width = QSPI_CFG_BUS_DUAL; _data_width = QSPI_CFG_BUS_DUAL; tr_debug("Read Bus Mode set to 2-2-2, Instruction: 0x%xh", _read_instruction); @@ -1073,8 +1077,9 @@ int QSPIFBlockDevice::_sfdp_detect_best_bus_read_mode(uint8_t *basic_param_table if (examined_byte & 0x10) { // Fast Read 1-2-2 Supported read_inst = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_122_READ_INST_BYTE]; - _dummy_and_mode_cycles = (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_122_READ_INST_BYTE - 1] >> 5) - + (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_122_READ_INST_BYTE - 1] & 0x1F); + _dummy_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_122_READ_INST_BYTE - 1] & 0x1F; + uint8_t mode_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_122_READ_INST_BYTE - 1] >> 5; + _alt_size = mode_cycles * 2; _address_width = QSPI_CFG_BUS_DUAL; _data_width = QSPI_CFG_BUS_DUAL; tr_debug("Read Bus Mode set to 1-2-2, Instruction: 0x%xh", _read_instruction); @@ -1083,8 +1088,9 @@ int QSPIFBlockDevice::_sfdp_detect_best_bus_read_mode(uint8_t *basic_param_table if (examined_byte & 0x01) { // Fast Read 1-1-2 Supported read_inst = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_112_READ_INST_BYTE]; - _dummy_and_mode_cycles = (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_112_READ_INST_BYTE - 1] >> 5) - + (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_112_READ_INST_BYTE - 1] & 0x1F); + _dummy_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_112_READ_INST_BYTE - 1] & 0x1F; + uint8_t mode_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_112_READ_INST_BYTE - 1] >> 5; + _alt_size = mode_cycles; _data_width = QSPI_CFG_BUS_DUAL; tr_debug("Read Bus Mode set to 1-1-2, Instruction: 0x%xh", _read_instruction); break; @@ -1322,7 +1328,7 @@ qspi_status_t QSPIFBlockDevice::_qspi_send_read_command(unsigned int read_inst, // Send Read command to device driver size_t buf_len = size; - if (_qspi.read(read_inst, -1, (unsigned int)addr, (char *)buffer, &buf_len) != QSPI_STATUS_OK) { + if (_qspi.read(read_inst, (_alt_size == 0) ? -1 : QSPI_ALT_DEFAULT_VALUE, (unsigned int)addr, (char *)buffer, &buf_len) != QSPI_STATUS_OK) { tr_error("Read failed"); return QSPI_STATUS_ERROR; } diff --git a/components/storage/blockdevice/COMPONENT_QSPIF/QSPIFBlockDevice.h b/components/storage/blockdevice/COMPONENT_QSPIF/QSPIFBlockDevice.h index b009bd97b22..5f78b0cafa8 100644 --- a/components/storage/blockdevice/COMPONENT_QSPIF/QSPIFBlockDevice.h +++ b/components/storage/blockdevice/COMPONENT_QSPIF/QSPIFBlockDevice.h @@ -357,9 +357,11 @@ class QSPIFBlockDevice : public mbed::BlockDevice { // Bus speed configuration qspi_bus_width_t _inst_width; //Bus width for Instruction phase qspi_bus_width_t _address_width; //Bus width for Address phase - qspi_address_size_t _address_size; // number of bytes for address + qspi_address_size_t _address_size; //Number of bits for address + qspi_alt_size_t _alt_size; //Number of bits for alt + bool _alt_enabled; //Whether alt is enabled + uint8_t _dummy_cycles; //Number of Dummy cycles required by Current Bus Mode qspi_bus_width_t _data_width; //Bus width for Data phase - int _dummy_and_mode_cycles; // Number of Dummy and Mode Bits required by Current Bus Mode uint32_t _init_ref_count; bool _is_initialized; From 1dc74090a7026ae12af22d2cee75e91715796d49 Mon Sep 17 00:00:00 2001 From: Kyle Kearney Date: Wed, 18 Sep 2019 17:01:43 -0700 Subject: [PATCH 209/227] Add target for CY8CPROTO-063-BLE --- .../GeneratedSource/cycfg.c | 34 + .../GeneratedSource/cycfg.h | 47 + .../GeneratedSource/cycfg.timestamp | 24 + .../GeneratedSource/cycfg_clocks.c | 45 + .../GeneratedSource/cycfg_clocks.h | 53 + .../GeneratedSource/cycfg_notices.h | 30 + .../GeneratedSource/cycfg_peripherals.c | 63 + .../GeneratedSource/cycfg_peripherals.h | 66 + .../GeneratedSource/cycfg_pins.c | 204 +++ .../GeneratedSource/cycfg_pins.h | 216 ++++ .../GeneratedSource/cycfg_routing.c | 29 + .../GeneratedSource/cycfg_routing.h | 47 + .../GeneratedSource/cycfg_system.c | 526 ++++++++ .../GeneratedSource/cycfg_system.h | 100 ++ .../cyreservedresources.list | 18 +- .../COMPONENT_BSP_DESIGN_MODUS/design.modus | 194 +++ .../PeripheralNames.h | 114 ++ .../TARGET_CY8CPROTO_063_BLE/PeripheralPins.c | 229 ++++ .../TARGET_CY8CPROTO_063_BLE/PinNames.h | 47 + .../TARGET_CY8CPROTO_063_BLE/cybsp.c | 118 ++ .../TARGET_CY8CPROTO_063_BLE/cybsp.h | 73 ++ .../TARGET_CY8CPROTO_063_BLE/cybsp_types.h | 124 ++ .../TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct | 313 +++++ .../TOOLCHAIN_ARM/startup_psoc6_01_cm4.S | 684 ++++++++++ .../TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld | 461 +++++++ .../TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S | 631 +++++++++ .../TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf | 286 +++++ .../TOOLCHAIN_IAR/startup_psoc6_01_cm4.S | 1141 +++++++++++++++++ .../device/system_psoc6.h | 680 ++++++++++ .../device/system_psoc6_cm4.c | 552 ++++++++ targets/targets.json | 17 + 31 files changed, 7150 insertions(+), 16 deletions(-) create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/design.modus create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/PeripheralNames.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/PeripheralPins.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/PinNames.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/cybsp.c create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/cybsp.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/cybsp_types.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/system_psoc6.h create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/system_psoc6_cm4.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c new file mode 100644 index 00000000000..cb430a41643 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c @@ -0,0 +1,34 @@ +/******************************************************************************* +* File Name: cycfg.c +* +* Description: +* Wrapper function to initialize all generated code. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg.h" + +void init_cycfg_all(void) +{ + init_cycfg_system(); + init_cycfg_clocks(); + init_cycfg_routing(); + init_cycfg_peripherals(); + init_cycfg_pins(); +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h new file mode 100644 index 00000000000..9abc7f0f4ab --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h @@ -0,0 +1,47 @@ +/******************************************************************************* +* File Name: cycfg.h +* +* Description: +* Simple wrapper header containing all generated files. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_H) +#define CYCFG_H + +#if defined(__cplusplus) +extern "C" { +#endif + +#include "cycfg_notices.h" +#include "cycfg_system.h" +#include "cycfg_clocks.h" +#include "cycfg_routing.h" +#include "cycfg_peripherals.h" +#include "cycfg_pins.h" + +void init_cycfg_all(void); + + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp new file mode 100644 index 00000000000..6911b5befd4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp @@ -0,0 +1,24 @@ +/******************************************************************************* +* File Name: cycfg.timestamp +* +* Description: +* Sentinel file for determining if generated source is up to date. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c new file mode 100644 index 00000000000..219facba434 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c @@ -0,0 +1,45 @@ +/******************************************************************************* +* File Name: cycfg_clocks.c +* +* Description: +* Clock configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_clocks.h" + +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_I2C_CLK_DIV_obj = + { + .type = CYHAL_RSC_CLOCK, + .block_num = CYBSP_I2C_CLK_DIV_HW, + .channel_num = CYBSP_I2C_CLK_DIV_NUM, + }; +#endif //defined (CY_USING_HAL) + + +void init_cycfg_clocks(void) +{ + Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U); + Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 3U); + Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_I2C_CLK_DIV_obj); +#endif //defined (CY_USING_HAL) +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h new file mode 100644 index 00000000000..8be433dd877 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h @@ -0,0 +1,53 @@ +/******************************************************************************* +* File Name: cycfg_clocks.h +* +* Description: +* Clock configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_CLOCKS_H) +#define CYCFG_CLOCKS_H + +#include "cycfg_notices.h" +#include "cy_sysclk.h" +#if defined (CY_USING_HAL) + #include "cyhal_hwmgr.h" +#endif //defined (CY_USING_HAL) + +#if defined(__cplusplus) +extern "C" { +#endif + +#define CYBSP_I2C_CLK_DIV_ENABLED 1U +#define CYBSP_I2C_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT +#define CYBSP_I2C_CLK_DIV_NUM 1U + +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_I2C_CLK_DIV_obj; +#endif //defined (CY_USING_HAL) + +void init_cycfg_clocks(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_CLOCKS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h new file mode 100644 index 00000000000..90f1013f8a7 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h @@ -0,0 +1,30 @@ +/******************************************************************************* +* File Name: cycfg_notices.h +* +* Description: +* Contains warnings and errors that occurred while generating code for the +* design. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_NOTICES_H) +#define CYCFG_NOTICES_H + + +#endif /* CYCFG_NOTICES_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c new file mode 100644 index 00000000000..c80943efb14 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c @@ -0,0 +1,63 @@ +/******************************************************************************* +* File Name: cycfg_peripherals.c +* +* Description: +* Peripheral Hardware Block configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_peripherals.h" + +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t bless_0_obj = + { + .type = CYHAL_RSC_BLESS, + .block_num = 0U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_scb_ezi2c_config_t CYBSP_I2C_config = +{ + .numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS, + .slaveAddress1 = 8U, + .slaveAddress2 = 0U, + .subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS, + .enableWakeFromSleep = false, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_I2C_obj = + { + .type = CYHAL_RSC_SCB, + .block_num = 8U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) + + +void init_cycfg_peripherals(void) +{ +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&bless_0_obj); +#endif //defined (CY_USING_HAL) + + Cy_SysClk_PeriphAssignDivider(PCLK_SCB8_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_I2C_obj); +#endif //defined (CY_USING_HAL) +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h new file mode 100644 index 00000000000..00f48a648d4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h @@ -0,0 +1,66 @@ +/******************************************************************************* +* File Name: cycfg_peripherals.h +* +* Description: +* Peripheral Hardware Block configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_PERIPHERALS_H) +#define CYCFG_PERIPHERALS_H + +#include "cycfg_notices.h" +#include "cy_scb_ezi2c.h" +#include "cy_sysclk.h" +#if defined (CY_USING_HAL) + #include "cyhal_hwmgr.h" +#endif //defined (CY_USING_HAL) + +#if defined(__cplusplus) +extern "C" { +#endif + +#define bless_0_ENABLED 1U +#define CY_BLE_CORE_CORTEX_M4 4U +#define CY_BLE_CORE_CORTEX_M0P 0U +#define CY_BLE_CORE_DUAL 255U +#ifndef CY_BLE_CORE + #define CY_BLE_CORE 4U +#endif +#define CY_BLE_IRQ bless_interrupt_IRQn +#define CYBSP_I2C_ENABLED 1U +#define CYBSP_I2C_HW SCB8 +#define CYBSP_I2C_IRQ scb_8_interrupt_IRQn + +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t bless_0_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_scb_ezi2c_config_t CYBSP_I2C_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_I2C_obj; +#endif //defined (CY_USING_HAL) + +void init_cycfg_peripherals(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_PERIPHERALS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c new file mode 100644 index 00000000000..62ce1aea996 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c @@ -0,0 +1,204 @@ +/******************************************************************************* +* File Name: cycfg_pins.c +* +* Description: +* Pin configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_pins.h" + +const cy_stc_gpio_pin_config_t WCO_IN_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = WCO_IN_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t WCO_IN_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = WCO_IN_PORT_NUM, + .channel_num = WCO_IN_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t WCO_OUT_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = WCO_OUT_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t WCO_OUT_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = WCO_OUT_PORT_NUM, + .channel_num = WCO_OUT_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_I2C_SCL_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_OD_DRIVESLOW, + .hsiom = CYBSP_I2C_SCL_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_I2C_SCL_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_I2C_SCL_PORT_NUM, + .channel_num = CYBSP_I2C_SCL_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_I2C_SDA_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_OD_DRIVESLOW, + .hsiom = CYBSP_I2C_SDA_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_I2C_SDA_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_I2C_SDA_PORT_NUM, + .channel_num = CYBSP_I2C_SDA_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t SWDIO_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_PULLUP, + .hsiom = SWDIO_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t SWDIO_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = SWDIO_PORT_NUM, + .channel_num = SWDIO_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t SWCLK_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_PULLDOWN, + .hsiom = SWCLK_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t SWCLK_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = SWCLK_PORT_NUM, + .channel_num = SWCLK_PIN, + }; +#endif //defined (CY_USING_HAL) + + +void init_cycfg_pins(void) +{ + Cy_GPIO_Pin_Init(WCO_IN_PORT, WCO_IN_PIN, &WCO_IN_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&WCO_IN_obj); +#endif //defined (CY_USING_HAL) + + Cy_GPIO_Pin_Init(WCO_OUT_PORT, WCO_OUT_PIN, &WCO_OUT_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&WCO_OUT_obj); +#endif //defined (CY_USING_HAL) + + Cy_GPIO_Pin_Init(CYBSP_I2C_SCL_PORT, CYBSP_I2C_SCL_PIN, &CYBSP_I2C_SCL_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_I2C_SCL_obj); +#endif //defined (CY_USING_HAL) + + Cy_GPIO_Pin_Init(CYBSP_I2C_SDA_PORT, CYBSP_I2C_SDA_PIN, &CYBSP_I2C_SDA_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_I2C_SDA_obj); +#endif //defined (CY_USING_HAL) + + Cy_GPIO_Pin_Init(SWDIO_PORT, SWDIO_PIN, &SWDIO_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&SWDIO_obj); +#endif //defined (CY_USING_HAL) + + Cy_GPIO_Pin_Init(SWCLK_PORT, SWCLK_PIN, &SWCLK_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&SWCLK_obj); +#endif //defined (CY_USING_HAL) +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h new file mode 100644 index 00000000000..471d2dd612f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h @@ -0,0 +1,216 @@ +/******************************************************************************* +* File Name: cycfg_pins.h +* +* Description: +* Pin configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_PINS_H) +#define CYCFG_PINS_H + +#include "cycfg_notices.h" +#include "cy_gpio.h" +#if defined (CY_USING_HAL) + #include "cyhal_hwmgr.h" +#endif //defined (CY_USING_HAL) +#include "cycfg_routing.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define WCO_IN_ENABLED 1U +#define WCO_IN_PORT GPIO_PRT0 +#define WCO_IN_PORT_NUM 0U +#define WCO_IN_PIN 0U +#define WCO_IN_NUM 0U +#define WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG +#define WCO_IN_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_0_pin_0_HSIOM + #define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO +#endif +#define WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM +#define WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn +#if defined (CY_USING_HAL) + #define WCO_IN_HAL_PORT_PIN P0_0 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG +#endif //defined (CY_USING_HAL) +#define WCO_OUT_ENABLED 1U +#define WCO_OUT_PORT GPIO_PRT0 +#define WCO_OUT_PORT_NUM 0U +#define WCO_OUT_PIN 1U +#define WCO_OUT_NUM 1U +#define WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG +#define WCO_OUT_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_0_pin_1_HSIOM + #define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM +#define WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn +#if defined (CY_USING_HAL) + #define WCO_OUT_HAL_PORT_PIN P0_1 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG +#endif //defined (CY_USING_HAL) +#define CYBSP_I2C_SCL_ENABLED 1U +#define CYBSP_I2C_SCL_PORT GPIO_PRT6 +#define CYBSP_I2C_SCL_PORT_NUM 6U +#define CYBSP_I2C_SCL_PIN 4U +#define CYBSP_I2C_SCL_NUM 4U +#define CYBSP_I2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW +#define CYBSP_I2C_SCL_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_4_HSIOM + #define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_I2C_SCL_HSIOM ioss_0_port_6_pin_4_HSIOM +#define CYBSP_I2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_I2C_SCL_HAL_PORT_PIN P6_4 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_I2C_SCL_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_I2C_SCL_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_I2C_SCL_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW +#endif //defined (CY_USING_HAL) +#define CYBSP_I2C_SDA_ENABLED 1U +#define CYBSP_I2C_SDA_PORT GPIO_PRT6 +#define CYBSP_I2C_SDA_PORT_NUM 6U +#define CYBSP_I2C_SDA_PIN 5U +#define CYBSP_I2C_SDA_NUM 5U +#define CYBSP_I2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW +#define CYBSP_I2C_SDA_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_5_HSIOM + #define ioss_0_port_6_pin_5_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_I2C_SDA_HSIOM ioss_0_port_6_pin_5_HSIOM +#define CYBSP_I2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_I2C_SDA_HAL_PORT_PIN P6_5 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_I2C_SDA_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_I2C_SDA_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_I2C_SDA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW +#endif //defined (CY_USING_HAL) +#define SWDIO_ENABLED 1U +#define SWDIO_PORT GPIO_PRT6 +#define SWDIO_PORT_NUM 6U +#define SWDIO_PIN 6U +#define SWDIO_NUM 6U +#define SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP +#define SWDIO_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_6_HSIOM + #define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM +#define SWDIO_IRQ ioss_interrupts_gpio_6_IRQn +#if defined (CY_USING_HAL) + #define SWDIO_HAL_PORT_PIN P6_6 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP +#endif //defined (CY_USING_HAL) +#define SWCLK_ENABLED 1U +#define SWCLK_PORT GPIO_PRT6 +#define SWCLK_PORT_NUM 6U +#define SWCLK_PIN 7U +#define SWCLK_NUM 7U +#define SWCLK_DRIVEMODE CY_GPIO_DM_PULLDOWN +#define SWCLK_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_7_HSIOM + #define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define SWCLK_HSIOM ioss_0_port_6_pin_7_HSIOM +#define SWCLK_IRQ ioss_interrupts_gpio_6_IRQn +#if defined (CY_USING_HAL) + #define SWCLK_HAL_PORT_PIN P6_7 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define SWCLK_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define SWCLK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define SWCLK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN +#endif //defined (CY_USING_HAL) + +extern const cy_stc_gpio_pin_config_t WCO_IN_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t WCO_IN_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t WCO_OUT_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t WCO_OUT_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_I2C_SCL_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_I2C_SCL_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_I2C_SDA_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_I2C_SDA_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t SWDIO_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t SWDIO_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t SWCLK_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t SWCLK_obj; +#endif //defined (CY_USING_HAL) + +void init_cycfg_pins(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_PINS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c new file mode 100644 index 00000000000..095e0b0b975 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c @@ -0,0 +1,29 @@ +/******************************************************************************* +* File Name: cycfg_routing.c +* +* Description: +* Establishes all necessary connections between hardware elements. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_routing.h" + +void init_cycfg_routing(void) +{ +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h new file mode 100644 index 00000000000..1b52354e2c7 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h @@ -0,0 +1,47 @@ +/******************************************************************************* +* File Name: cycfg_routing.h +* +* Description: +* Establishes all necessary connections between hardware elements. +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_ROUTING_H) +#define CYCFG_ROUTING_H + +#if defined(__cplusplus) +extern "C" { +#endif + +#include "cycfg_notices.h" +void init_cycfg_routing(void); +#define init_cycfg_connectivity() init_cycfg_routing() +#define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN +#define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT +#define ioss_0_port_6_pin_4_HSIOM P6_4_SCB8_I2C_SCL +#define ioss_0_port_6_pin_5_HSIOM P6_5_SCB8_I2C_SDA +#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS +#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_ROUTING_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c new file mode 100644 index 00000000000..9bf8d778906 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c @@ -0,0 +1,526 @@ +/******************************************************************************* +* File Name: cycfg_system.c +* +* Description: +* System configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_system.h" + +#define CY_CFG_SYSCLK_ECO_ERROR 1 +#define CY_CFG_SYSCLK_ALTHF_ERROR 2 +#define CY_CFG_SYSCLK_PLL_ERROR 3 +#define CY_CFG_SYSCLK_FLL_ERROR 4 +#define CY_CFG_SYSCLK_WCO_ERROR 5 +#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1 +#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1 +#define CY_CFG_SYSCLK_FLL_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1 +#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL +#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0 +#define CY_CFG_SYSCLK_ILO_ENABLED 1 +#define CY_CFG_SYSCLK_IMO_ENABLED 1 +#define CY_CFG_SYSCLK_CLKLF_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH3_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH3_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPATH4_ENABLED 1 +#define CY_CFG_SYSCLK_CLKPATH4_SOURCE CY_SYSCLK_CLKPATH_IN_IMO +#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1 +#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1 +#define CY_CFG_SYSCLK_WCO_ENABLED 1 +#define CY_CFG_PWR_ENABLED 1 +#define CY_CFG_PWR_INIT 1 +#define CY_CFG_PWR_USING_PMIC 0 +#define CY_CFG_PWR_VBACKUP_USING_VDDD 1 +#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP +#define CY_CFG_PWR_USING_ULP 0 + +static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = +{ + .fllMult = 500U, + .refDiv = 20U, + .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4, + .enableOutputDiv = true, + .lockTolerance = 10U, + .igain = 9U, + .pgain = 5U, + .settlingCount = 8U, + .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT, + .cco_Freq = 355U, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = + { + .type = CYHAL_RSC_CLKPATH, + .block_num = 0U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = + { + .type = CYHAL_RSC_CLKPATH, + .block_num = 1U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = + { + .type = CYHAL_RSC_CLKPATH, + .block_num = 2U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj = + { + .type = CYHAL_RSC_CLKPATH, + .block_num = 3U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj = + { + .type = CYHAL_RSC_CLKPATH, + .block_num = 4U, + .channel_num = 0U, + }; +#endif //defined (CY_USING_HAL) + +__WEAK void cycfg_ClockStartupError(uint32_t error) +{ + (void)error; /* Suppress the compiler warning */ + while(1); +} +__STATIC_INLINE void Cy_SysClk_ClkBakInit() +{ + Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO); +} +__STATIC_INLINE void Cy_SysClk_ClkFastInit() +{ + Cy_SysClk_ClkFastSetDivider(0U); +} +__STATIC_INLINE void Cy_SysClk_FllInit() +{ + if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); + } + if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR); + } +} +__STATIC_INLINE void Cy_SysClk_ClkHf0Init() +{ + Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH); + Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); +} +__STATIC_INLINE void Cy_SysClk_IloInit() +{ + /* The WDT is unlocked in the default startup code */ + Cy_SysClk_IloEnable(); + Cy_SysClk_IloHibernateOn(true); +} +__STATIC_INLINE void Cy_SysClk_ClkLfInit() +{ + /* The WDT is unlocked in the default startup code */ + Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO); +} +__STATIC_INLINE void Cy_SysClk_ClkPath0Init() +{ + Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPath1Init() +{ + Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPath2Init() +{ + Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPath3Init() +{ + Cy_SysClk_ClkPathSetSource(3U, CY_CFG_SYSCLK_CLKPATH3_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPath4Init() +{ + Cy_SysClk_ClkPathSetSource(4U, CY_CFG_SYSCLK_CLKPATH4_SOURCE); +} +__STATIC_INLINE void Cy_SysClk_ClkPeriInit() +{ + Cy_SysClk_ClkPeriSetDivider(1U); +} +__STATIC_INLINE void Cy_SysClk_ClkSlowInit() +{ + Cy_SysClk_ClkSlowSetDivider(0U); +} +__STATIC_INLINE void Cy_SysClk_WcoInit() +{ + (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO); + (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO); + if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL)) + { + cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR); + } +} +__STATIC_INLINE void init_cycfg_power(void) +{ + /* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */ + #if (CY_CFG_PWR_VBACKUP_USING_VDDD) + if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */) + { + Cy_SysLib_ResetBackupDomain(); + Cy_SysClk_IloDisable(); + Cy_SysClk_IloInit(); + } + #else /* Dedicated Supply */ + Cy_SysPm_BackupSetSupply(CY_SYSPM_VDDBACKUP_VBACKUP); + #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */ + + /* Configure core regulator */ + #if CY_CFG_PWR_USING_LDO + Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_LP); + Cy_SysPm_LdoSetMode(CY_SYSPM_LDO_MODE_NORMAL); + #else + Cy_SysPm_BuckEnable(CY_SYSPM_BUCK_OUT1_VOLTAGE_LP); + #endif /* CY_CFG_PWR_USING_LDO */ + /* Configure PMIC */ + Cy_SysPm_UnlockPmic(); + #if CY_CFG_PWR_USING_PMIC + Cy_SysPm_PmicEnableOutput(); + #else + Cy_SysPm_PmicDisableOutput(); + #endif /* CY_CFG_PWR_USING_PMIC */ +} + + +void init_cycfg_system(void) +{ + /* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */ + Cy_SysLib_SetWaitStates(false, 150UL); + #ifdef CY_CFG_PWR_ENABLED + #ifdef CY_CFG_PWR_INIT + init_cycfg_power(); + #else + #warning Power system will not be configured. Update power personality to v1.20 or later. + #endif /* CY_CFG_PWR_INIT */ + #endif /* CY_CFG_PWR_ENABLED */ + + /* Reset the core clock path to default and disable all the FLLs/PLLs */ + Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE); + Cy_SysClk_ClkFastSetDivider(0U); + Cy_SysClk_ClkPeriSetDivider(1U); + Cy_SysClk_ClkSlowSetDivider(0U); + for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */ + { + (void)Cy_SysClk_PllDisable(pll); + } + Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO); + + if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) && + (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0))) + { + Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1); + } + + Cy_SysClk_FllDisable(); + Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO); + Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0); + #ifdef CY_IP_MXBLESS + (void)Cy_BLE_EcoReset(); + #endif + + + /* Enable all source clocks */ + #ifdef CY_CFG_SYSCLK_PILO_ENABLED + Cy_SysClk_PiloInit(); + #endif + + #ifdef CY_CFG_SYSCLK_WCO_ENABLED + Cy_SysClk_WcoInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED + Cy_SysClk_ClkLfInit(); + #endif + + #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED + Cy_SysClk_AltHfInit(); + #endif + + #ifdef CY_CFG_SYSCLK_ECO_ENABLED + Cy_SysClk_EcoInit(); + #endif + + #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED + Cy_SysClk_ExtClkInit(); + #endif + + /* Configure CPU clock dividers */ + #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED + Cy_SysClk_ClkFastInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED + Cy_SysClk_ClkPeriInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED + Cy_SysClk_ClkSlowInit(); + #endif + + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) + /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */ + Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO); + Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1); + #else + #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED + Cy_SysClk_ClkPath1Init(); + #endif + #endif + + /* Configure Path Clocks */ + #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED + Cy_SysClk_ClkPath0Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED + Cy_SysClk_ClkPath2Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED + Cy_SysClk_ClkPath3Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED + Cy_SysClk_ClkPath4Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED + Cy_SysClk_ClkPath5Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED + Cy_SysClk_ClkPath6Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED + Cy_SysClk_ClkPath7Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED + Cy_SysClk_ClkPath8Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED + Cy_SysClk_ClkPath9Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED + Cy_SysClk_ClkPath10Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED + Cy_SysClk_ClkPath11Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED + Cy_SysClk_ClkPath12Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED + Cy_SysClk_ClkPath13Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED + Cy_SysClk_ClkPath14Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED + Cy_SysClk_ClkPath15Init(); + #endif + + /* Configure and enable FLL */ + #ifdef CY_CFG_SYSCLK_FLL_ENABLED + Cy_SysClk_FllInit(); + #endif + + Cy_SysClk_ClkHf0Init(); + + #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0)) + #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED + /* Apply the ClkPath1 user setting */ + Cy_SysClk_ClkPath1Init(); + #endif + #endif + + /* Configure and enable PLLs */ + #ifdef CY_CFG_SYSCLK_PLL0_ENABLED + Cy_SysClk_Pll0Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL1_ENABLED + Cy_SysClk_Pll1Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL2_ENABLED + Cy_SysClk_Pll2Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL3_ENABLED + Cy_SysClk_Pll3Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL4_ENABLED + Cy_SysClk_Pll4Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL5_ENABLED + Cy_SysClk_Pll5Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL6_ENABLED + Cy_SysClk_Pll6Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL7_ENABLED + Cy_SysClk_Pll7Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL8_ENABLED + Cy_SysClk_Pll8Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL9_ENABLED + Cy_SysClk_Pll9Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL10_ENABLED + Cy_SysClk_Pll10Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL11_ENABLED + Cy_SysClk_Pll11Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL12_ENABLED + Cy_SysClk_Pll12Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL13_ENABLED + Cy_SysClk_Pll13Init(); + #endif + #ifdef CY_CFG_SYSCLK_PLL14_ENABLED + Cy_SysClk_Pll14Init(); + #endif + + /* Configure HF clocks */ + #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED + Cy_SysClk_ClkHf1Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED + Cy_SysClk_ClkHf2Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED + Cy_SysClk_ClkHf3Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED + Cy_SysClk_ClkHf4Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED + Cy_SysClk_ClkHf5Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED + Cy_SysClk_ClkHf6Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED + Cy_SysClk_ClkHf7Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED + Cy_SysClk_ClkHf8Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED + Cy_SysClk_ClkHf9Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED + Cy_SysClk_ClkHf10Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED + Cy_SysClk_ClkHf11Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED + Cy_SysClk_ClkHf12Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED + Cy_SysClk_ClkHf13Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED + Cy_SysClk_ClkHf14Init(); + #endif + #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED + Cy_SysClk_ClkHf15Init(); + #endif + + /* Configure miscellaneous clocks */ + #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED + Cy_SysClk_ClkTimerInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED + Cy_SysClk_ClkAltSysTickInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED + Cy_SysClk_ClkPumpInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED + Cy_SysClk_ClkBakInit(); + #endif + + /* Configure default enabled clocks */ + #ifdef CY_CFG_SYSCLK_ILO_ENABLED + Cy_SysClk_IloInit(); + #else + Cy_SysClk_IloDisable(); + #endif + + #ifndef CY_CFG_SYSCLK_IMO_ENABLED + #error the IMO must be enabled for proper chip operation + #endif + + #ifdef CY_CFG_SYSCLK_MFO_ENABLED + Cy_SysClk_MfoInit(); + #endif + + #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED + Cy_SysClk_ClkMfInit(); + #endif + + /* Set accurate flash wait states */ + #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED)) + Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ); + #endif + + /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */ + SystemCoreClockUpdate(); + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj); +#endif //defined (CY_USING_HAL) + +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj); +#endif //defined (CY_USING_HAL) +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h new file mode 100644 index 00000000000..ef9fad341b6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h @@ -0,0 +1,100 @@ +/******************************************************************************* +* File Name: cycfg_system.h +* +* Description: +* System configuration +* This file was automatically generated and should not be modified. +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_SYSTEM_H) +#define CYCFG_SYSTEM_H + +#include "cycfg_notices.h" +#include "cy_sysclk.h" +#include "cy_ble_clk.h" +#if defined (CY_USING_HAL) + #include "cyhal_hwmgr.h" +#endif //defined (CY_USING_HAL) +#include "cy_gpio.h" +#include "cy_syspm.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define cpuss_0_dap_0_ENABLED 1U +#define srss_0_clock_0_ENABLED 1U +#define srss_0_clock_0_bakclk_0_ENABLED 1U +#define srss_0_clock_0_fastclk_0_ENABLED 1U +#define srss_0_clock_0_fll_0_ENABLED 1U +#define srss_0_clock_0_hfclk_0_ENABLED 1U +#define CY_CFG_SYSCLK_CLKHF0 0UL +#define srss_0_clock_0_ilo_0_ENABLED 1U +#define srss_0_clock_0_imo_0_ENABLED 1U +#define srss_0_clock_0_lfclk_0_ENABLED 1U +#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768 +#define srss_0_clock_0_pathmux_0_ENABLED 1U +#define srss_0_clock_0_pathmux_1_ENABLED 1U +#define srss_0_clock_0_pathmux_2_ENABLED 1U +#define srss_0_clock_0_pathmux_3_ENABLED 1U +#define srss_0_clock_0_pathmux_4_ENABLED 1U +#define srss_0_clock_0_periclk_0_ENABLED 1U +#define srss_0_clock_0_slowclk_0_ENABLED 1U +#define srss_0_clock_0_wco_0_ENABLED 1U +#define srss_0_power_0_ENABLED 1U +#define CY_CFG_PWR_MODE_LP 0x01UL +#define CY_CFG_PWR_MODE_ULP 0x02UL +#define CY_CFG_PWR_MODE_ACTIVE 0x04UL +#define CY_CFG_PWR_MODE_SLEEP 0x08UL +#define CY_CFG_PWR_MODE_DEEPSLEEP 0x10UL +#define CY_CFG_PWR_SYS_IDLE_MODE CY_CFG_PWR_MODE_DEEPSLEEP +#define CY_CFG_PWR_SYS_ACTIVE_MODE CY_CFG_PWR_MODE_LP +#define CY_CFG_PWR_DEEPSLEEP_LATENCY 0UL +#define CY_CFG_PWR_USING_LDO 1 +#define CY_CFG_PWR_VDDA_MV 3300 +#define CY_CFG_PWR_VDDD_MV 3300 +#define CY_CFG_PWR_VBACKUP_MV 3300 +#define CY_CFG_PWR_VDD_NS_MV 3300 +#define CY_CFG_PWR_VDDIO0_MV 3300 +#define CY_CFG_PWR_VDDIO1_MV 3300 + +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj; +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj; +#endif //defined (CY_USING_HAL) + +void init_cycfg_system(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_SYSTEM_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list index 73b81d459ae..22e48eac708 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list @@ -1,18 +1,4 @@ -[Device="CYBLE-416045-02"] +[Device=CYBLE-416045-02] [Blocks] -# User IO -# CYBSP_USER_LED1 -ioss[0].port[6].pin[3] -# CYBSP_USER_LED2 -ioss[0].port[7].pin[1] -# CYBSP_USER_BTN1 -ioss[0].port[0].pin[4] - -# Debug -# CYBSP_DEBUG_UART -scb[5] -# CYBSP_DEBUG_UART_RX -ioss[0].port[5].pin[0] -# CYBSP_DEBUG_UART_TX -ioss[0].port[5].pin[1] +# Nothing needs to be reserved for this board diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/design.modus new file mode 100644 index 00000000000..6a935554880 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/design.modus @@ -0,0 +1,194 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/PeripheralNames.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/PeripheralNames.h new file mode 100644 index 00000000000..c58cc2e1034 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/PeripheralNames.h @@ -0,0 +1,114 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2018 Future Electronics + * Copyright (c) 2019 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + UART_0 = (int)SCB0_BASE, + UART_1 = (int)SCB1_BASE, + UART_2 = (int)SCB2_BASE, + UART_3 = (int)SCB3_BASE, + UART_4 = (int)SCB4_BASE, + UART_5 = (int)SCB5_BASE, + UART_6 = (int)SCB6_BASE, + UART_7 = (int)SCB7_BASE, +} UARTName; + +#define DEVICE_SPI_COUNT CY_IP_MXSCB_INSTANCES + +typedef enum { + SPI_0 = (int)SCB0_BASE, + SPI_1 = (int)SCB1_BASE, + SPI_2 = (int)SCB2_BASE, + SPI_3 = (int)SCB3_BASE, + SPI_4 = (int)SCB4_BASE, + SPI_5 = (int)SCB5_BASE, + SPI_6 = (int)SCB6_BASE, + SPI_7 = (int)SCB7_BASE, + SPI_8 = (int)SCB8_BASE, +} SPIName; + +typedef enum { + I2C_0 = (int)SCB0_BASE, + I2C_1 = (int)SCB1_BASE, + I2C_2 = (int)SCB2_BASE, + I2C_3 = (int)SCB3_BASE, + I2C_4 = (int)SCB4_BASE, + I2C_5 = (int)SCB5_BASE, + I2C_6 = (int)SCB6_BASE, + I2C_7 = (int)SCB7_BASE, + I2C_8 = (int)SCB8_BASE, +} I2CName; + +typedef enum { + PWM_32b_0 = TCPWM0_BASE, + PWM_32b_1, + PWM_32b_2, + PWM_32b_3, + PWM_32b_4, + PWM_32b_5, + PWM_32b_6, + PWM_32b_7, + PWM_16b_0 = TCPWM1_BASE, + PWM_16b_1, + PWM_16b_2, + PWM_16b_3, + PWM_16b_4, + PWM_16b_5, + PWM_16b_6, + PWM_16b_7, + PWM_16b_8, + PWM_16b_9, + PWM_16b_10, + PWM_16b_11, + PWM_16b_12, + PWM_16b_13, + PWM_16b_14, + PWM_16b_15, + PWM_16b_16, + PWM_16b_17, + PWM_16b_18, + PWM_16b_19, + PWM_16b_20, + PWM_16b_21, + PWM_16b_22, + PWM_16b_23, +} PWMName; + +typedef enum { + ADC_0 = (int)SAR_BASE, +} ADCName; + +typedef enum { + DAC_0 = (int)CTDAC0_BASE, +} DACName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/PeripheralPins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/PeripheralPins.c new file mode 100644 index 00000000000..4b7bb9588cb --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/PeripheralPins.c @@ -0,0 +1,229 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2018 Future Electronics + * Copyright (c) 2019 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralNames.h" +#include "PeripheralPins.h" +#include "pinmap.h" + +#if DEVICE_SERIAL +//*** SERIAL *** +const PinMap PinMap_UART_RX[] = { + {P5_0, UART_5, CYHAL_PIN_IN_FUNCTION(P5_0_SCB5_UART_RX)}, + {P6_4, UART_6, CYHAL_PIN_IN_FUNCTION(P6_4_SCB6_UART_RX)}, + {P9_0, UART_2, CYHAL_PIN_IN_FUNCTION(P9_0_SCB2_UART_RX)}, + {P10_0, UART_1, CYHAL_PIN_IN_FUNCTION(P10_0_SCB1_UART_RX)}, + {NC, NC, 0} +}; +const PinMap PinMap_UART_TX[] = { + {P5_1, UART_5, CYHAL_PIN_OUT_FUNCTION(P5_1_SCB5_UART_TX)}, + {P6_5, UART_6, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB6_UART_TX)}, + {P7_1, UART_4, CYHAL_PIN_OUT_FUNCTION(P7_1_SCB4_UART_TX)}, + {P9_1, UART_2, CYHAL_PIN_OUT_FUNCTION(P9_1_SCB2_UART_TX)}, + {P10_1, UART_1, CYHAL_PIN_OUT_FUNCTION(P10_1_SCB1_UART_TX)}, + {NC, NC, 0} +}; +const PinMap PinMap_UART_RTS[] = { + {P0_4, UART_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_UART_RTS)}, + {P5_2, UART_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_UART_RTS)}, + {P6_2, UART_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_UART_RTS)}, + {P6_6, UART_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_UART_RTS)}, + {P7_2, UART_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_UART_RTS)}, + {P9_2, UART_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_UART_RTS)}, + {P10_2, UART_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_UART_RTS)}, + {NC, NC, 0} +}; +const PinMap PinMap_UART_CTS[] = { + {P0_5, UART_0, CYHAL_PIN_IN_FUNCTION(P0_5_SCB0_UART_CTS)}, + {P5_3, UART_5, CYHAL_PIN_IN_FUNCTION(P5_3_SCB5_UART_CTS)}, + {P6_3, UART_3, CYHAL_PIN_IN_FUNCTION(P6_3_SCB3_UART_CTS)}, + {P6_7, UART_6, CYHAL_PIN_IN_FUNCTION(P6_7_SCB6_UART_CTS)}, + {P9_3, UART_2, CYHAL_PIN_IN_FUNCTION(P9_3_SCB2_UART_CTS)}, + {P10_3, UART_1, CYHAL_PIN_IN_FUNCTION(P10_3_SCB1_UART_CTS)}, + {NC, NC, 0} +}; +#endif // DEVICE_SERIAL + + +#if DEVICE_I2C +//*** I2C *** +const PinMap PinMap_I2C_SCL[] = { + {P5_0, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_0_SCB5_I2C_SCL)}, + {P6_4, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_4_SCB6_I2C_SCL)}, + {P6_4, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_4_SCB8_I2C_SCL)}, + {P9_0, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_0_SCB2_I2C_SCL)}, + {P10_0, I2C_1, CYHAL_PIN_OD_FUNCTION(P10_0_SCB1_I2C_SCL)}, + {NC, NC, 0} +}; +const PinMap PinMap_I2C_SDA[] = { + {P5_1, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_1_SCB5_I2C_SDA)}, + {P6_5, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_5_SCB6_I2C_SDA)}, + {P6_5, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_5_SCB8_I2C_SDA)}, + {P7_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_1_SCB4_I2C_SDA)}, + {P9_1, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_1_SCB2_I2C_SDA)}, + {P10_1, I2C_1, CYHAL_PIN_OD_FUNCTION(P10_1_SCB1_I2C_SDA)}, + {NC, NC, 0} +}; +#endif // DEVICE_I2C + +#if DEVICE_SPI +//*** SPI *** +const PinMap PinMap_SPI_MOSI[] = { + {P5_0, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_0_SCB5_SPI_MOSI)}, + {P6_4, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB6_SPI_MOSI)}, + {P6_4, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB8_SPI_MOSI)}, + {P9_0, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_0_SCB2_SPI_MOSI)}, + {P10_0, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_0_SCB1_SPI_MOSI)}, + {NC, NC, 0} +}; +const PinMap PinMap_SPI_MISO[] = { + {P5_1, SPI_5, CYHAL_PIN_IN_FUNCTION(P5_1_SCB5_SPI_MISO)}, + {P6_5, SPI_6, CYHAL_PIN_IN_FUNCTION(P6_5_SCB6_SPI_MISO)}, + {P6_5, SPI_8, CYHAL_PIN_IN_FUNCTION(P6_5_SCB8_SPI_MISO)}, + {P7_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P7_1_SCB4_SPI_MISO)}, + {P9_1, SPI_2, CYHAL_PIN_IN_FUNCTION(P9_1_SCB2_SPI_MISO)}, + {P10_1, SPI_1, CYHAL_PIN_IN_FUNCTION(P10_1_SCB1_SPI_MISO)}, + {NC, NC, 0} +}; +const PinMap PinMap_SPI_SCLK[] = { + {P0_4, SPI_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_SPI_CLK)}, + {P5_2, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_SPI_CLK)}, + {P6_2, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_SPI_CLK)}, + {P6_2, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB8_SPI_CLK)}, + {P6_6, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_SPI_CLK)}, + {P6_6, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB8_SPI_CLK)}, + {P7_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_SPI_CLK)}, + {P9_2, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_SPI_CLK)}, + {P10_2, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_SPI_CLK)}, + {NC, NC, 0} +}; +const PinMap PinMap_SPI_SSEL[] = { + {P0_5, SPI_0, CYHAL_PIN_OUT_FUNCTION(P0_5_SCB0_SPI_SELECT0)}, + {P5_3, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_3_SCB5_SPI_SELECT0)}, + {P6_3, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB3_SPI_SELECT0)}, + {P6_3, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB8_SPI_SELECT0)}, + {P6_7, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB6_SPI_SELECT0)}, + {P6_7, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB8_SPI_SELECT0)}, + {P9_3, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_3_SCB2_SPI_SELECT0)}, + {P10_3, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_3_SCB1_SPI_SELECT0)}, + {NC, NC, 0} +}; +#endif // DEVICE_SPI + +#if DEVICE_PWMOUT +//*** PWM *** +const PinMap PinMap_PWM_OUT[] = { + // 16-bit PWM outputs + {P0_0, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM1_LINE0)}, + {P0_4, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM1_LINE2)}, + {P5_0, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM1_LINE4)}, + {P5_2, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM1_LINE5)}, + {P5_4, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM1_LINE6)}, + {P5_6, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM1_LINE7)}, + {P6_2, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM1_LINE9)}, + {P6_4, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM1_LINE10)}, + {P6_6, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM1_LINE11)}, + {P7_2, PWM_16b_13, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM1_LINE13)}, + {P9_0, PWM_16b_20, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM1_LINE20)}, + {P9_2, PWM_16b_21, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM1_LINE21)}, + {P9_4, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P9_4_TCPWM1_LINE0)}, + {P9_6, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P9_6_TCPWM1_LINE1)}, + {P10_0, PWM_16b_22, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM1_LINE22)}, + {P10_2, PWM_16b_23, CYHAL_PIN_OUT_FUNCTION(P10_2_TCPWM1_LINE23)}, + {P10_4, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM1_LINE0)}, + {P10_6, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P10_6_TCPWM1_LINE2)}, + {P12_6, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM1_LINE7)}, + // 16-bit PWM inverted outputs + {P0_1, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM1_LINE_COMPL0)}, + {P0_5, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM1_LINE_COMPL2)}, + {P5_1, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM1_LINE_COMPL4)}, + {P5_3, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM1_LINE_COMPL5)}, + {P5_5, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM1_LINE_COMPL6)}, + {P6_3, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM1_LINE_COMPL9)}, + {P6_5, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM1_LINE_COMPL10)}, + {P6_7, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM1_LINE_COMPL11)}, + {P7_1, PWM_16b_12, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM1_LINE_COMPL12)}, + {P7_7, PWM_16b_15, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM1_LINE_COMPL15)}, + {P9_1, PWM_16b_20, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM1_LINE_COMPL20)}, + {P9_3, PWM_16b_21, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM1_LINE_COMPL21)}, + {P9_5, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P9_5_TCPWM1_LINE_COMPL0)}, + {P10_1, PWM_16b_22, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM1_LINE_COMPL22)}, + {P10_3, PWM_16b_23, CYHAL_PIN_OUT_FUNCTION(P10_3_TCPWM1_LINE_COMPL23)}, + {P10_5, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM1_LINE_COMPL0)}, + {P12_7, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM1_LINE_COMPL7)}, + // 32-bit PWM outputs + {P0_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM0_LINE0)}, + {P0_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM0_LINE2)}, + {P5_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM0_LINE4)}, + {P5_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM0_LINE5)}, + {P5_4, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM0_LINE6)}, + {P5_6, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM0_LINE7)}, + {P6_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM0_LINE1)}, + {P6_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM0_LINE2)}, + {P6_6, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM0_LINE3)}, + {P7_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM0_LINE5)}, + {P9_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM0_LINE4)}, + {P9_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM0_LINE5)}, + {P9_4, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P9_4_TCPWM0_LINE7)}, + {P9_6, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P9_6_TCPWM0_LINE0)}, + {P10_0, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM0_LINE6)}, + {P10_2, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P10_2_TCPWM0_LINE7)}, + {P10_4, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM0_LINE0)}, + {P10_6, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P10_6_TCPWM0_LINE1)}, + {P12_6, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM0_LINE7)}, + // 32-bit PWM inverted outputs + {P0_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM0_LINE_COMPL0)}, + {P0_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM0_LINE_COMPL2)}, + {P5_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM0_LINE_COMPL4)}, + {P5_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM0_LINE_COMPL5)}, + {P5_5, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM0_LINE_COMPL6)}, + {P6_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM0_LINE_COMPL1)}, + {P6_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM0_LINE_COMPL2)}, + {P6_7, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM0_LINE_COMPL3)}, + {P7_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM0_LINE_COMPL4)}, + {P7_7, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM0_LINE_COMPL7)}, + {P9_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM0_LINE_COMPL4)}, + {P9_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM0_LINE_COMPL5)}, + {P9_5, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P9_5_TCPWM0_LINE_COMPL7)}, + {P10_1, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM0_LINE_COMPL6)}, + {P10_3, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P10_3_TCPWM0_LINE_COMPL7)}, + {P10_5, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM0_LINE_COMPL0)}, + {P12_7, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM0_LINE_COMPL7)}, + {NC, NC, 0} +}; +#endif // DEVICE_PWMOUT + +#if DEVICE_ANALOGIN +const PinMap PinMap_ADC[] = { + {P10_0, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, + {P10_1, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, + {P10_2, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, + {P10_3, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, + {P10_4, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, + {P10_5, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, + {P10_6, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, + {NC, NC, 0} +}; +#endif // DEVICE_ANALOGIN + +#if DEVICE_ANALOGOUT +const PinMap PinMap_DAC[] = { + {P9_6, DAC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, + {NC, NC, 0} +}; +#endif // DEVICE_ANALOGIN diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/PinNames.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/PinNames.h new file mode 100644 index 00000000000..ca7d623c93a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/PinNames.h @@ -0,0 +1,47 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2018 Future Electronics + * Copyright (c) 2019 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "PinNamesTypes.h" +#include "cyhal_pin_package.h" + +// Generic signal names +#define UART_RX P5_0 +#define UART_TX P5_1 + +#define I2C_SCL P6_4 +#define I2C_SDA P6_5 + +#define LED1 P6_3 +#define LED2 P7_1 + +#define SWITCH2 P0_4 +#define USER_BUTTON SWITCH2 +#define BUTTON1 USER_BUTTON + +// Standardized interfaces names +#define STDIO_UART_TX UART_TX +#define STDIO_UART_RX UART_RX + +#define USBTX UART_TX +#define USBRX UART_RX + +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/cybsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/cybsp.c new file mode 100644 index 00000000000..f460f83ac42 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/cybsp.c @@ -0,0 +1,118 @@ +/***************************************************************************//** +* \file cybsp.c +* +* Description: +* Provides initialization code for starting up the hardware contained on the +* Cypress board. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include +#include "cybsp.h" +#include "cyhal_utils.h" +#include "cycfg.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/* The sysclk deep sleep callback is recommended to be the last callback that +* is executed before entry into deep sleep mode and the first one upon +* exit the deep sleep mode. +* Doing so minimizes the time spent on low power mode entry and exit. +*/ +#ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER + #define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u) +#endif + +#if defined(CYBSP_WIFI_CAPABLE) +static cyhal_sdio_t sdio_obj; + +cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void) +{ + return &sdio_obj; +} +#endif + +/** + * Registers a power management callback that prepares the clock system + * for entering deep sleep mode and restore the clocks upon wakeup from deep sleep. + * NOTE: This is called automatically as part of \ref cybsp_init + */ +static cy_rslt_t cybsp_register_sysclk_pm_callback(void) +{ + cy_rslt_t result = CY_RSLT_SUCCESS; + static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = {NULL, NULL}; + static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback = { + .callback = &Cy_SysClk_DeepSleepCallback, + .type = CY_SYSPM_DEEPSLEEP, + .callbackParams = &cybsp_sysclk_pm_callback_param, + .order = CYBSP_SYSCLK_PM_CALLBACK_ORDER + }; + + if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback)) + { + result = CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK; + } + return result; +} + +cy_rslt_t cybsp_init(void) +{ + /* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */ + cy_rslt_t result = cyhal_hwmgr_init(); + init_cycfg_system(); + + if (CY_RSLT_SUCCESS == result) + { + result = cybsp_register_sysclk_pm_callback(); + } + +#if defined(CYBSP_WIFI_CAPABLE) + /* Initialize SDIO interface. This must be done before other HAL API calls as some SDIO implementations require + * specific peripheral instances. + * NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically + * done when starting up WiFi. + */ + if (CY_RSLT_SUCCESS == result) + { + /* Reserves: CYBSP_WIFI_SDIO, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3 + * CYBSP_WIFI_SDIO_CMD and CYBSP_WIFI_SDIO_CLK. + */ + result = cyhal_sdio_init( + &sdio_obj, + CYBSP_WIFI_SDIO_CMD, + CYBSP_WIFI_SDIO_CLK, + CYBSP_WIFI_SDIO_D0, + CYBSP_WIFI_SDIO_D1, + CYBSP_WIFI_SDIO_D2, + CYBSP_WIFI_SDIO_D3); + } +#endif /* defined(CYBSP_WIFI_CAPABLE) */ + + /* CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was reserved by + * user previously. Please review the Device Configurator (design.modus) and the BSP reservation list + * (cyreservedresources.list) to make sure no resources are reserved by both. + */ + return result; +} + +#if defined(__cplusplus) +} +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/cybsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/cybsp.h new file mode 100644 index 00000000000..bd930510eda --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/cybsp.h @@ -0,0 +1,73 @@ +/***************************************************************************//** +* \file cybsp.h +* +* \brief +* Basic API for setting up boards containing a Cypress MCU. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#pragma once + +#include "cy_result.h" +#include "cybsp_types.h" +#if defined(CYBSP_WIFI_CAPABLE) +#include "cyhal_sdio.h" +#endif + +#if defined(__cplusplus) +extern "C" { +#endif + +/** +* \addtogroup group_bsp_macros Macros +* \{ +*/ + +/** Failed to configure sysclk power management callback */ +#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0)) + +/** \} group_bsp_macros */ + +/** +* \addtogroup group_bsp_functions Functions +* \{ +*/ + +/** + * \brief Initialize all hardware on the board + * \returns CY_RSLT_SUCCESS if the board is sucessfully initialized, if there is + * a problem initializing any hardware it returns an error code specific + * to the hardware module that had a problem. + */ +cy_rslt_t cybsp_init(void); + +#if defined(CYBSP_WIFI_CAPABLE) +/** + * \brief Get the initialized sdio object used for communicating with the WiFi Chip. + * \note This function should only be called after cybsp_init(); + * \returns The initialized sdio object. + */ +cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void); +#endif /* defined(CYBSP_WIFI_CAPABLE) */ + +/** \} group_bsp_functions */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/cybsp_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/cybsp_types.h new file mode 100644 index 00000000000..ca97ff3ab1f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/cybsp_types.h @@ -0,0 +1,124 @@ +/***************************************************************************//** +* \file CY8CPROTO-063-BLE/cybsp_types.h +* +* Description: +* Provides APIs for interacting with the hardware contained on the Cypress +* CY8CPROTO-063-BLE kit. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#pragma once + +#include "cyhal_pin_package.h" + +#if defined(__cplusplus) +extern "C" { +#endif + + +/** +* \addtogroup group_bsp_pin_state Pin States +* \{ +*/ + +/** Pin state for the LED on. */ +#define CYBSP_LED_STATE_ON (0U) +/** Pin state for the LED off. */ +#define CYBSP_LED_STATE_OFF (1U) + +/** Pin state for when a button is pressed. */ +#define CYBSP_BTN_PRESSED (0U) +/** Pin state for when a button is released. */ +#define CYBSP_BTN_OFF (1U) + +/** \} group_bsp_pin_state */ + + +/** +* \addtogroup group_bsp_pins Pin Mappings +* \{ +*/ + +/** +* \addtogroup group_bsp_pins_led LED Pins +* \{ +*/ + +/** LED 3; User LED1 (red) */ +#define CYBSP_LED3 (P6_3) +/** LED 4; User LED2 (green) */ +#define CYBSP_LED4 (P7_1) + +/** LED 3; User LED1 (red) */ +#define CYBSP_USER_LED1 (CYBSP_LED3) +/** LED 4; User LED2 (green) */ +#define CYBSP_USER_LED2 (CYBSP_LED4) +/** LED 3; User LED1 (red) */ +#define CYBSP_USER_LED (CYBSP_USER_LED1) + +/** \} group_bsp_pins_led */ + +/** +* \addtogroup group_bsp_pins_btn Button Pins +* \{ +*/ + +/** Switch 2; User Button 1 */ +#define CYBSP_SW2 (P0_4) + +/** Switch 2; User Button 1 */ +#define CYBSP_USER_BTN1 (CYBSP_SW2) +/** Switch 2; User Button 1 */ +#define CYBSP_USER_BTN (CYBSP_USER_BTN1) + +/** \} group_bsp_pins_btn */ + + +/** +* \addtogroup group_bsp_pins_comm Communication Pins +* \{ +*/ + +/** Pin: UART RX */ +#define CYBSP_UART_RX P5_0 +/** Pin: UART TX */ +#define CYBSP_UART_TX P5_1 + +/** Pin: UART RX */ +#define CYBSP_DEBUG_UART_RX P5_0 +/** Pin: UART TX */ +#define CYBSP_DEBUG_UART_TX P5_1 + +/** Pin: I2C SCL */ +#define CYBSP_I2C_SCL P6_4 +/** Pin: I2C SDA */ +#define CYBSP_I2C_SDA P6_5 + +/** Pin: SWDIO */ +#define CYBSP_SWDIO P6_6 +/** Pin: SWDCK */ +#define CYBSP_SWDCK P6_7 + +/** \} group_bsp_pins_comm */ + +/** \} group_bsp_pins */ + +#if defined(__cplusplus) +} +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct new file mode 100644 index 00000000000..7ccd6c547dc --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct @@ -0,0 +1,313 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xx7_cm4_dual.sct +;* \version 2.60 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +; Size of the Cortex-M0+ application flash image +#define FLASH_CM0P_SIZE 0x2000 + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. In case if MBED_APP_START address is +;* customized by the bootloader config, the application image should not +;* include CM0p prebuilt image. +;* + +#if !defined(MBED_APP_START) + #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00100000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08002000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x00045800 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +; Size of the stack section at the end of CM4 SRAM +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + + +; Cortex-M0+ application flash image area +LR_IROM MBED_ROM_START FLASH_CM0P_SIZE +{ + .cy_m0p_image +0 FLASH_CM0P_SIZE + { + * (.cy_m0p_image) + } +} + +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 + { + * (HEAP) + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE + { + * (STACK) + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + .cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00100000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S new file mode 100644 index 00000000000..5bd22714385 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S @@ -0,0 +1,684 @@ +;/**************************************************************************//** +; * @file startup_psoc6_01_cm4.S +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + IF :DEF:__STACK_SIZE +Stack_Size EQU __STACK_SIZE + ELSE +Stack_Size EQU 0x00000400 + ENDIF + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + IF :DEF:__HEAP_SIZE +Heap_Size EQU __HEAP_SIZE + ELSE +Heap_Size EQU 0x00000400 + ENDIF + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + + DCD 0x0000000D ; NMI Handler located at ROM code + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External interrupts Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD pass_interrupt_ctbs_IRQHandler ; CTBm Interrupt (all CTBms) + DCD bless_interrupt_IRQHandler ; Bluetooth Radio interrupt + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 + DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 + DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 + DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 + DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 + DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 + DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 + DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 + DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 + DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 + DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 + DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 + DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 + DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 + DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 + DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 + DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 + DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 + DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 + DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 + DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 + DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 + DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 + DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 + DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 + DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 + DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 + DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 + DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 + DCD udb_interrupts_0_IRQHandler ; UDB Interrupt #0 + DCD udb_interrupts_1_IRQHandler ; UDB Interrupt #1 + DCD udb_interrupts_2_IRQHandler ; UDB Interrupt #2 + DCD udb_interrupts_3_IRQHandler ; UDB Interrupt #3 + DCD udb_interrupts_4_IRQHandler ; UDB Interrupt #4 + DCD udb_interrupts_5_IRQHandler ; UDB Interrupt #5 + DCD udb_interrupts_6_IRQHandler ; UDB Interrupt #6 + DCD udb_interrupts_7_IRQHandler ; UDB Interrupt #7 + DCD udb_interrupts_8_IRQHandler ; UDB Interrupt #8 + DCD udb_interrupts_9_IRQHandler ; UDB Interrupt #9 + DCD udb_interrupts_10_IRQHandler ; UDB Interrupt #10 + DCD udb_interrupts_11_IRQHandler ; UDB Interrupt #11 + DCD udb_interrupts_12_IRQHandler ; UDB Interrupt #12 + DCD udb_interrupts_13_IRQHandler ; UDB Interrupt #13 + DCD udb_interrupts_14_IRQHandler ; UDB Interrupt #14 + DCD udb_interrupts_15_IRQHandler ; UDB Interrupt #15 + DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt + DCD audioss_interrupt_i2s_IRQHandler ; I2S Audio interrupt + DCD audioss_interrupt_pdm_IRQHandler ; PDM/PCM Audio interrupt + DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD pass_interrupt_dacs_IRQHandler ; Consolidated interrrupt for all DACs + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + + AREA |.text|, CODE, READONLY + + +; Weak function for startup customization +; +; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +; because this function is executed as the first instruction in the ResetHandler. +; The PDL is also not initialized to use the proper register offsets. +; The user of this function is responsible for initializing the PDL and resources before using them. +; +Cy_OnResetUser PROC + EXPORT Cy_OnResetUser [WEAK] + BX LR + ENDP + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT Cy_SystemInitFpuEnable + IMPORT __main + + ; Define strong function for startup customization + BL Cy_OnResetUser + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__Vectors + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +Vectors_Copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE Vectors_Copy + + ; Update Vector Table Offset Register. */ + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb 0xF + + ; Enable the FPU if used + LDR R0, =Cy_SystemInitFpuEnable + BLX R0 + + LDR R0, =__main + BLX R0 + + ; Should never get here + B . + + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP +HardFault_Wrapper\ + PROC + EXPORT HardFault_Wrapper [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B HardFault_Wrapper + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT ioss_interrupts_gpio_0_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_1_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_2_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_3_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_4_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_5_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_6_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_7_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_8_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_9_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_10_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_11_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_12_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_13_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_14_IRQHandler [WEAK] + EXPORT ioss_interrupt_gpio_IRQHandler [WEAK] + EXPORT ioss_interrupt_vdd_IRQHandler [WEAK] + EXPORT lpcomp_interrupt_IRQHandler [WEAK] + EXPORT scb_8_interrupt_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_0_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_1_IRQHandler [WEAK] + EXPORT srss_interrupt_backup_IRQHandler [WEAK] + EXPORT srss_interrupt_IRQHandler [WEAK] + EXPORT pass_interrupt_ctbs_IRQHandler [WEAK] + EXPORT bless_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_15_IRQHandler [WEAK] + EXPORT scb_0_interrupt_IRQHandler [WEAK] + EXPORT scb_1_interrupt_IRQHandler [WEAK] + EXPORT scb_2_interrupt_IRQHandler [WEAK] + EXPORT scb_3_interrupt_IRQHandler [WEAK] + EXPORT scb_4_interrupt_IRQHandler [WEAK] + EXPORT scb_5_interrupt_IRQHandler [WEAK] + EXPORT scb_6_interrupt_IRQHandler [WEAK] + EXPORT scb_7_interrupt_IRQHandler [WEAK] + EXPORT csd_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_1_IRQHandler [WEAK] + EXPORT cpuss_interrupt_crypto_IRQHandler [WEAK] + EXPORT cpuss_interrupt_fm_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_4_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_5_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_6_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_7_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_4_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_5_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_6_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_7_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_8_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_9_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_10_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_11_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_12_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_13_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_14_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_15_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_16_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_17_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_18_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_19_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_20_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_21_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_22_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_23_IRQHandler [WEAK] + EXPORT udb_interrupts_0_IRQHandler [WEAK] + EXPORT udb_interrupts_1_IRQHandler [WEAK] + EXPORT udb_interrupts_2_IRQHandler [WEAK] + EXPORT udb_interrupts_3_IRQHandler [WEAK] + EXPORT udb_interrupts_4_IRQHandler [WEAK] + EXPORT udb_interrupts_5_IRQHandler [WEAK] + EXPORT udb_interrupts_6_IRQHandler [WEAK] + EXPORT udb_interrupts_7_IRQHandler [WEAK] + EXPORT udb_interrupts_8_IRQHandler [WEAK] + EXPORT udb_interrupts_9_IRQHandler [WEAK] + EXPORT udb_interrupts_10_IRQHandler [WEAK] + EXPORT udb_interrupts_11_IRQHandler [WEAK] + EXPORT udb_interrupts_12_IRQHandler [WEAK] + EXPORT udb_interrupts_13_IRQHandler [WEAK] + EXPORT udb_interrupts_14_IRQHandler [WEAK] + EXPORT udb_interrupts_15_IRQHandler [WEAK] + EXPORT pass_interrupt_sar_IRQHandler [WEAK] + EXPORT audioss_interrupt_i2s_IRQHandler [WEAK] + EXPORT audioss_interrupt_pdm_IRQHandler [WEAK] + EXPORT profile_interrupt_IRQHandler [WEAK] + EXPORT smif_interrupt_IRQHandler [WEAK] + EXPORT usb_interrupt_hi_IRQHandler [WEAK] + EXPORT usb_interrupt_med_IRQHandler [WEAK] + EXPORT usb_interrupt_lo_IRQHandler [WEAK] + EXPORT pass_interrupt_dacs_IRQHandler [WEAK] + +ioss_interrupts_gpio_0_IRQHandler +ioss_interrupts_gpio_1_IRQHandler +ioss_interrupts_gpio_2_IRQHandler +ioss_interrupts_gpio_3_IRQHandler +ioss_interrupts_gpio_4_IRQHandler +ioss_interrupts_gpio_5_IRQHandler +ioss_interrupts_gpio_6_IRQHandler +ioss_interrupts_gpio_7_IRQHandler +ioss_interrupts_gpio_8_IRQHandler +ioss_interrupts_gpio_9_IRQHandler +ioss_interrupts_gpio_10_IRQHandler +ioss_interrupts_gpio_11_IRQHandler +ioss_interrupts_gpio_12_IRQHandler +ioss_interrupts_gpio_13_IRQHandler +ioss_interrupts_gpio_14_IRQHandler +ioss_interrupt_gpio_IRQHandler +ioss_interrupt_vdd_IRQHandler +lpcomp_interrupt_IRQHandler +scb_8_interrupt_IRQHandler +srss_interrupt_mcwdt_0_IRQHandler +srss_interrupt_mcwdt_1_IRQHandler +srss_interrupt_backup_IRQHandler +srss_interrupt_IRQHandler +pass_interrupt_ctbs_IRQHandler +bless_interrupt_IRQHandler +cpuss_interrupts_ipc_0_IRQHandler +cpuss_interrupts_ipc_1_IRQHandler +cpuss_interrupts_ipc_2_IRQHandler +cpuss_interrupts_ipc_3_IRQHandler +cpuss_interrupts_ipc_4_IRQHandler +cpuss_interrupts_ipc_5_IRQHandler +cpuss_interrupts_ipc_6_IRQHandler +cpuss_interrupts_ipc_7_IRQHandler +cpuss_interrupts_ipc_8_IRQHandler +cpuss_interrupts_ipc_9_IRQHandler +cpuss_interrupts_ipc_10_IRQHandler +cpuss_interrupts_ipc_11_IRQHandler +cpuss_interrupts_ipc_12_IRQHandler +cpuss_interrupts_ipc_13_IRQHandler +cpuss_interrupts_ipc_14_IRQHandler +cpuss_interrupts_ipc_15_IRQHandler +scb_0_interrupt_IRQHandler +scb_1_interrupt_IRQHandler +scb_2_interrupt_IRQHandler +scb_3_interrupt_IRQHandler +scb_4_interrupt_IRQHandler +scb_5_interrupt_IRQHandler +scb_6_interrupt_IRQHandler +scb_7_interrupt_IRQHandler +csd_interrupt_IRQHandler +cpuss_interrupts_dw0_0_IRQHandler +cpuss_interrupts_dw0_1_IRQHandler +cpuss_interrupts_dw0_2_IRQHandler +cpuss_interrupts_dw0_3_IRQHandler +cpuss_interrupts_dw0_4_IRQHandler +cpuss_interrupts_dw0_5_IRQHandler +cpuss_interrupts_dw0_6_IRQHandler +cpuss_interrupts_dw0_7_IRQHandler +cpuss_interrupts_dw0_8_IRQHandler +cpuss_interrupts_dw0_9_IRQHandler +cpuss_interrupts_dw0_10_IRQHandler +cpuss_interrupts_dw0_11_IRQHandler +cpuss_interrupts_dw0_12_IRQHandler +cpuss_interrupts_dw0_13_IRQHandler +cpuss_interrupts_dw0_14_IRQHandler +cpuss_interrupts_dw0_15_IRQHandler +cpuss_interrupts_dw1_0_IRQHandler +cpuss_interrupts_dw1_1_IRQHandler +cpuss_interrupts_dw1_2_IRQHandler +cpuss_interrupts_dw1_3_IRQHandler +cpuss_interrupts_dw1_4_IRQHandler +cpuss_interrupts_dw1_5_IRQHandler +cpuss_interrupts_dw1_6_IRQHandler +cpuss_interrupts_dw1_7_IRQHandler +cpuss_interrupts_dw1_8_IRQHandler +cpuss_interrupts_dw1_9_IRQHandler +cpuss_interrupts_dw1_10_IRQHandler +cpuss_interrupts_dw1_11_IRQHandler +cpuss_interrupts_dw1_12_IRQHandler +cpuss_interrupts_dw1_13_IRQHandler +cpuss_interrupts_dw1_14_IRQHandler +cpuss_interrupts_dw1_15_IRQHandler +cpuss_interrupts_fault_0_IRQHandler +cpuss_interrupts_fault_1_IRQHandler +cpuss_interrupt_crypto_IRQHandler +cpuss_interrupt_fm_IRQHandler +cpuss_interrupts_cm0_cti_0_IRQHandler +cpuss_interrupts_cm0_cti_1_IRQHandler +cpuss_interrupts_cm4_cti_0_IRQHandler +cpuss_interrupts_cm4_cti_1_IRQHandler +tcpwm_0_interrupts_0_IRQHandler +tcpwm_0_interrupts_1_IRQHandler +tcpwm_0_interrupts_2_IRQHandler +tcpwm_0_interrupts_3_IRQHandler +tcpwm_0_interrupts_4_IRQHandler +tcpwm_0_interrupts_5_IRQHandler +tcpwm_0_interrupts_6_IRQHandler +tcpwm_0_interrupts_7_IRQHandler +tcpwm_1_interrupts_0_IRQHandler +tcpwm_1_interrupts_1_IRQHandler +tcpwm_1_interrupts_2_IRQHandler +tcpwm_1_interrupts_3_IRQHandler +tcpwm_1_interrupts_4_IRQHandler +tcpwm_1_interrupts_5_IRQHandler +tcpwm_1_interrupts_6_IRQHandler +tcpwm_1_interrupts_7_IRQHandler +tcpwm_1_interrupts_8_IRQHandler +tcpwm_1_interrupts_9_IRQHandler +tcpwm_1_interrupts_10_IRQHandler +tcpwm_1_interrupts_11_IRQHandler +tcpwm_1_interrupts_12_IRQHandler +tcpwm_1_interrupts_13_IRQHandler +tcpwm_1_interrupts_14_IRQHandler +tcpwm_1_interrupts_15_IRQHandler +tcpwm_1_interrupts_16_IRQHandler +tcpwm_1_interrupts_17_IRQHandler +tcpwm_1_interrupts_18_IRQHandler +tcpwm_1_interrupts_19_IRQHandler +tcpwm_1_interrupts_20_IRQHandler +tcpwm_1_interrupts_21_IRQHandler +tcpwm_1_interrupts_22_IRQHandler +tcpwm_1_interrupts_23_IRQHandler +udb_interrupts_0_IRQHandler +udb_interrupts_1_IRQHandler +udb_interrupts_2_IRQHandler +udb_interrupts_3_IRQHandler +udb_interrupts_4_IRQHandler +udb_interrupts_5_IRQHandler +udb_interrupts_6_IRQHandler +udb_interrupts_7_IRQHandler +udb_interrupts_8_IRQHandler +udb_interrupts_9_IRQHandler +udb_interrupts_10_IRQHandler +udb_interrupts_11_IRQHandler +udb_interrupts_12_IRQHandler +udb_interrupts_13_IRQHandler +udb_interrupts_14_IRQHandler +udb_interrupts_15_IRQHandler +pass_interrupt_sar_IRQHandler +audioss_interrupt_i2s_IRQHandler +audioss_interrupt_pdm_IRQHandler +profile_interrupt_IRQHandler +smif_interrupt_IRQHandler +usb_interrupt_hi_IRQHandler +usb_interrupt_med_IRQHandler +usb_interrupt_lo_IRQHandler +pass_interrupt_dacs_IRQHandler + + B . + ENDP + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + + ALIGN + + ENDIF + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld new file mode 100644 index 00000000000..e7c641ea4fe --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld @@ -0,0 +1,461 @@ +/***************************************************************************//** +* \file cy8c6xx7_cm4_dual.ld +* \version 2.60 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +/* Size of the Cortex-M0+ application image at the start of FLASH */ +FLASH_CM0P_SIZE = 0x2000; + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10000000 +#endif + +/* MBED_APP_START is being used by the bootloader build script and +* will be calculate by the system. In case if MBED_APP_START address is +* customized by the bootloader config, the application image should not +* include CM0p prebuilt image. +*/ +#if !defined(MBED_APP_START) + #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x00100000 +#endif + +/* MBED_APP_SIZE is being used by the bootloader build script and +* will be calculate by the system. +*/ +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE) +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08002000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x00045800 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +/* Size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = MBED_BOOT_STACK_SIZE; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'. + */ + ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE + cm0p_image (rx) : ORIGIN = MBED_ROM_START, LENGTH = FLASH_CM0P_SIZE + flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M0+ application flash image area */ + .cy_m0p_image ORIGIN(cm0p_image) : + { + . = ALIGN(4); + __cy_m0p_code_start = . ; + KEEP(*(.cy_m0p_image)) + __cy_m0p_code_end = . ; + } > cm0p_image + + /* Cortex-M4 application flash area */ + .text ORIGIN(flash) : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + .cy_xip : + { + KEEP(*(.cy_xip)) + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00100000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S new file mode 100644 index 00000000000..3c2f44d1e07 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S @@ -0,0 +1,631 @@ +/**************************************************************************//** + * @file startup_psoc6_01_cm4.S + * @brief CMSIS Core Device Startup File for + * ARMCM4 Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + /* Copy flash vectors and data section to RAM */ + #define __STARTUP_COPY_MULTIPLE + + /* Clear single BSS section */ + #define __STARTUP_CLEAR_BSS + + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + .long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + .long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + .long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + .long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + .long pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */ + .long bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */ + .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + .long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + .long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + .long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + .long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + .long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + .long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + .long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + .long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + .long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + .long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + .long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + .long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + .long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + .long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + .long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + .long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + .long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + .long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + .long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + .long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + .long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + .long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + .long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + .long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + .long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + .long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + .long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + .long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + .long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + .long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + .long udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */ + .long udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */ + .long udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */ + .long udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */ + .long udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */ + .long udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */ + .long udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */ + .long udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */ + .long udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */ + .long udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */ + .long udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */ + .long udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */ + .long udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */ + .long udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */ + .long udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */ + .long udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */ + .long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + .long audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */ + .long audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */ + .long profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + .long usb_interrupt_hi_IRQHandler /* USB Interrupt */ + .long usb_interrupt_med_IRQHandler /* USB Interrupt */ + .long usb_interrupt_lo_IRQHandler /* USB Interrupt */ + .long pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ + + + .size __Vectors, . - __Vectors + .equ __VectorsSize, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __VectorsSize + .size __ramVectors, . - __ramVectors + + + .text + .thumb + .thumb_func + .align 2 + + /* + * Device startup customization + * + * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) + * because this function is executed as the first instruction in the ResetHandler. + * The PDL is also not initialized to use the proper register offsets. + * The user of this function is responsible for initializing the PDL and resources before using them. + */ + .weak Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser + .type Cy_OnResetUser, %function + +Cy_OnResetUser: + bx lr + .size Cy_OnResetUser, . - Cy_OnResetUser + .endfunc + + /* Reset handler */ + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + /* Update Vector Table Offset Register. */ + ldr r0, =__ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + /* Enable the FPU if used */ + bl Cy_SystemInitFpuEnable + + bl _start + + /* Should never get here */ + b . + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function + +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + + + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function + +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + .type Fault_Handler, %function + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + +.macro def_fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + def_fault_Handler MemManage_Handler + def_fault_Handler BusFault_Handler + def_fault_Handler UsageFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + def_irq_handler pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */ + def_irq_handler bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */ + def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + def_irq_handler udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */ + def_irq_handler udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */ + def_irq_handler udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */ + def_irq_handler udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */ + def_irq_handler udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */ + def_irq_handler udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */ + def_irq_handler udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */ + def_irq_handler udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */ + def_irq_handler udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */ + def_irq_handler udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */ + def_irq_handler udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */ + def_irq_handler udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */ + def_irq_handler udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */ + def_irq_handler udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */ + def_irq_handler udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */ + def_irq_handler udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */ + def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + def_irq_handler audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */ + def_irq_handler audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */ + def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */ + def_irq_handler pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */ + + .end + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf new file mode 100644 index 00000000000..ae61379863e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf @@ -0,0 +1,286 @@ +/***************************************************************************//** +* \file cy8c6xx7_cm4_dual.icf +* \version 2.60 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +/* Size of the Cortex-M0+ application image */ +define symbol FLASH_CM0P_SIZE = 0x2000; + +if (!isdefinedsymbol(MBED_ROM_START)) { + define symbol MBED_ROM_START = 0x10000000; +} + +/* MBED_APP_START is being used by the bootloader build script and + * will be calculate by the system. In case if MBED_APP_START address is + * customized by the bootloader config, the application image should not + * include CM0p prebuilt image. + */ +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = (MBED_ROM_START + FLASH_CM0P_SIZE); +} + +if (!isdefinedsymbol(MBED_ROM_SIZE)) { + define symbol MBED_ROM_SIZE = 0x00100000; +} + +/* MBED_APP_SIZE is being used by the bootloader build script and + * will be calculate by the system. + */ +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = (MBED_ROM_SIZE - FLASH_CM0P_SIZE); +} + +if (!isdefinedsymbol(MBED_RAM_START)) { + define symbol MBED_RAM_START = 0x08002000; +} + +if (!isdefinedsymbol(MBED_RAM_SIZE)) { + define symbol MBED_RAM_SIZE = 0x00045800; +} + +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + + if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x0400; + } else { + define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE; + } +} + +define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +/* Flash */ +define symbol __ICFEDIT_region_IROM0_start__ = MBED_ROM_START; +define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE); + +define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region IROM0_region = mem:[from __ICFEDIT_region_IROM0_start__ to __ICFEDIT_region_IROM0_end__]; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block RAM_DATA {readwrite section .data}; +define block RAM_OTHER {readwrite section * }; +define block RAM_NOINIT {readwrite section .noinit}; +define block RAM_BSS {readwrite section .bss}; +define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; + +define block CM0P_RO with size = FLASH_CM0P_SIZE { readonly section .cy_m0p_image }; +define block RO {first section .intvec, readonly}; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M0+ application image */ +place at start of IROM0_region { block CM0P_RO }; + +/* Flash - Cortex-M4 application */ +place at start of IROM1_region { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { section .cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { block RAM}; +place in IRAM1_region { block HEAP}; +place at end of IRAM1_region { block CSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_m0p_image, + section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00100000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S new file mode 100644 index 00000000000..75747c4face --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S @@ -0,0 +1,1141 @@ +;/**************************************************************************//** +; * @file startup_psoc6_01_cm4.S +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 08. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec_ram:DATA:NOROOT(2) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN Cy_SystemInitFpuEnable + EXTERN __iar_data_init3 + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + PUBLIC __ramVectors + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD 0x0000000D ; NMI_Handler is defined in ROM code + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External interrupts Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD pass_interrupt_ctbs_IRQHandler ; CTBm Interrupt (all CTBms) + DCD bless_interrupt_IRQHandler ; Bluetooth Radio interrupt + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 + DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 + DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 + DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 + DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 + DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 + DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 + DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 + DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 + DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 + DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 + DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 + DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 + DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 + DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 + DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 + DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 + DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 + DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 + DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 + DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 + DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 + DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 + DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 + DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 + DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 + DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 + DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 + DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 + DCD udb_interrupts_0_IRQHandler ; UDB Interrupt #0 + DCD udb_interrupts_1_IRQHandler ; UDB Interrupt #1 + DCD udb_interrupts_2_IRQHandler ; UDB Interrupt #2 + DCD udb_interrupts_3_IRQHandler ; UDB Interrupt #3 + DCD udb_interrupts_4_IRQHandler ; UDB Interrupt #4 + DCD udb_interrupts_5_IRQHandler ; UDB Interrupt #5 + DCD udb_interrupts_6_IRQHandler ; UDB Interrupt #6 + DCD udb_interrupts_7_IRQHandler ; UDB Interrupt #7 + DCD udb_interrupts_8_IRQHandler ; UDB Interrupt #8 + DCD udb_interrupts_9_IRQHandler ; UDB Interrupt #9 + DCD udb_interrupts_10_IRQHandler ; UDB Interrupt #10 + DCD udb_interrupts_11_IRQHandler ; UDB Interrupt #11 + DCD udb_interrupts_12_IRQHandler ; UDB Interrupt #12 + DCD udb_interrupts_13_IRQHandler ; UDB Interrupt #13 + DCD udb_interrupts_14_IRQHandler ; UDB Interrupt #14 + DCD udb_interrupts_15_IRQHandler ; UDB Interrupt #15 + DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt + DCD audioss_interrupt_i2s_IRQHandler ; I2S Audio interrupt + DCD audioss_interrupt_pdm_IRQHandler ; PDM/PCM Audio interrupt + DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD pass_interrupt_dacs_IRQHandler ; Consolidated interrrupt for all DACs + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + SECTION .intvec_ram:DATA:REORDER:NOROOT(2) +__ramVectors + DS32 __Vectors_Size + + + THUMB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default handlers +;; + PUBWEAK Default_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Default_Handler + B Default_Handler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for startup customization +;; +;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +;; because this function is executed as the first instruction in the ResetHandler. +;; The PDL is also not initialized to use the proper register offsets. +;; The user of this function is responsible for initializing the PDL and resources before using them. +;; + PUBWEAK Cy_OnResetUser + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_OnResetUser + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Define strong version to return zero for +;; __iar_program_start to skip data sections +;; initialization. +;; + PUBLIC __low_level_init + SECTION .text:CODE:REORDER:NOROOT(2) +__low_level_init + MOVS R0, #0 + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + ; Define strong function for startup customization + LDR R0, =Cy_OnResetUser + BLX R0 + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__vector_table + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +intvec_copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE intvec_copy + + ; Update Vector Table Offset Register + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb + + ; Enable the FPU if used + LDR R0, =Cy_SystemInitFpuEnable + BLX R0 + + ; Initialize data sections + LDR R0, =__iar_data_init3 + BLX R0 + + LDR R0, =SystemInit + BLX R0 + + LDR R0, =__iar_program_start + BLX R0 + +; Should never get here +Cy_Main_Exited + B Cy_Main_Exited + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK Cy_SysLib_FaultHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Cy_SysLib_FaultHandler + B Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Wrapper + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Wrapper + IMPORT Cy_SysLib_FaultHandler + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + b L_API_call +L_MSP + mrs r0, MSP +L_API_call + ; Storing LR content for Creator call stack trace + push {LR} + bl Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Wrapper + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B HardFault_Wrapper + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B HardFault_Wrapper + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B HardFault_Wrapper + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + ; External interrupts + PUBWEAK ioss_interrupts_gpio_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_0_IRQHandler + B ioss_interrupts_gpio_0_IRQHandler + + PUBWEAK ioss_interrupts_gpio_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_1_IRQHandler + B ioss_interrupts_gpio_1_IRQHandler + + PUBWEAK ioss_interrupts_gpio_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_2_IRQHandler + B ioss_interrupts_gpio_2_IRQHandler + + PUBWEAK ioss_interrupts_gpio_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_3_IRQHandler + B ioss_interrupts_gpio_3_IRQHandler + + PUBWEAK ioss_interrupts_gpio_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_4_IRQHandler + B ioss_interrupts_gpio_4_IRQHandler + + PUBWEAK ioss_interrupts_gpio_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_5_IRQHandler + B ioss_interrupts_gpio_5_IRQHandler + + PUBWEAK ioss_interrupts_gpio_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_6_IRQHandler + B ioss_interrupts_gpio_6_IRQHandler + + PUBWEAK ioss_interrupts_gpio_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_7_IRQHandler + B ioss_interrupts_gpio_7_IRQHandler + + PUBWEAK ioss_interrupts_gpio_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_8_IRQHandler + B ioss_interrupts_gpio_8_IRQHandler + + PUBWEAK ioss_interrupts_gpio_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_9_IRQHandler + B ioss_interrupts_gpio_9_IRQHandler + + PUBWEAK ioss_interrupts_gpio_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_10_IRQHandler + B ioss_interrupts_gpio_10_IRQHandler + + PUBWEAK ioss_interrupts_gpio_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_11_IRQHandler + B ioss_interrupts_gpio_11_IRQHandler + + PUBWEAK ioss_interrupts_gpio_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_12_IRQHandler + B ioss_interrupts_gpio_12_IRQHandler + + PUBWEAK ioss_interrupts_gpio_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_13_IRQHandler + B ioss_interrupts_gpio_13_IRQHandler + + PUBWEAK ioss_interrupts_gpio_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_14_IRQHandler + B ioss_interrupts_gpio_14_IRQHandler + + PUBWEAK ioss_interrupt_gpio_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_gpio_IRQHandler + B ioss_interrupt_gpio_IRQHandler + + PUBWEAK ioss_interrupt_vdd_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_vdd_IRQHandler + B ioss_interrupt_vdd_IRQHandler + + PUBWEAK lpcomp_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +lpcomp_interrupt_IRQHandler + B lpcomp_interrupt_IRQHandler + + PUBWEAK scb_8_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_8_interrupt_IRQHandler + B scb_8_interrupt_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_0_IRQHandler + B srss_interrupt_mcwdt_0_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_1_IRQHandler + B srss_interrupt_mcwdt_1_IRQHandler + + PUBWEAK srss_interrupt_backup_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_backup_IRQHandler + B srss_interrupt_backup_IRQHandler + + PUBWEAK srss_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_IRQHandler + B srss_interrupt_IRQHandler + + PUBWEAK pass_interrupt_ctbs_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_ctbs_IRQHandler + B pass_interrupt_ctbs_IRQHandler + + PUBWEAK bless_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +bless_interrupt_IRQHandler + B bless_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_0_IRQHandler + B cpuss_interrupts_ipc_0_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_1_IRQHandler + B cpuss_interrupts_ipc_1_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_2_IRQHandler + B cpuss_interrupts_ipc_2_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_3_IRQHandler + B cpuss_interrupts_ipc_3_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_4_IRQHandler + B cpuss_interrupts_ipc_4_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_5_IRQHandler + B cpuss_interrupts_ipc_5_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_6_IRQHandler + B cpuss_interrupts_ipc_6_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_7_IRQHandler + B cpuss_interrupts_ipc_7_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_8_IRQHandler + B cpuss_interrupts_ipc_8_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_9_IRQHandler + B cpuss_interrupts_ipc_9_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_10_IRQHandler + B cpuss_interrupts_ipc_10_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_11_IRQHandler + B cpuss_interrupts_ipc_11_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_12_IRQHandler + B cpuss_interrupts_ipc_12_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_13_IRQHandler + B cpuss_interrupts_ipc_13_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_14_IRQHandler + B cpuss_interrupts_ipc_14_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_15_IRQHandler + B cpuss_interrupts_ipc_15_IRQHandler + + PUBWEAK scb_0_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_0_interrupt_IRQHandler + B scb_0_interrupt_IRQHandler + + PUBWEAK scb_1_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_1_interrupt_IRQHandler + B scb_1_interrupt_IRQHandler + + PUBWEAK scb_2_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_2_interrupt_IRQHandler + B scb_2_interrupt_IRQHandler + + PUBWEAK scb_3_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_3_interrupt_IRQHandler + B scb_3_interrupt_IRQHandler + + PUBWEAK scb_4_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_4_interrupt_IRQHandler + B scb_4_interrupt_IRQHandler + + PUBWEAK scb_5_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_5_interrupt_IRQHandler + B scb_5_interrupt_IRQHandler + + PUBWEAK scb_6_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_6_interrupt_IRQHandler + B scb_6_interrupt_IRQHandler + + PUBWEAK scb_7_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_7_interrupt_IRQHandler + B scb_7_interrupt_IRQHandler + + PUBWEAK csd_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +csd_interrupt_IRQHandler + B csd_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_0_IRQHandler + B cpuss_interrupts_dw0_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_1_IRQHandler + B cpuss_interrupts_dw0_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_2_IRQHandler + B cpuss_interrupts_dw0_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_3_IRQHandler + B cpuss_interrupts_dw0_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_4_IRQHandler + B cpuss_interrupts_dw0_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_5_IRQHandler + B cpuss_interrupts_dw0_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_6_IRQHandler + B cpuss_interrupts_dw0_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_7_IRQHandler + B cpuss_interrupts_dw0_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_8_IRQHandler + B cpuss_interrupts_dw0_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_9_IRQHandler + B cpuss_interrupts_dw0_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_10_IRQHandler + B cpuss_interrupts_dw0_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_11_IRQHandler + B cpuss_interrupts_dw0_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_12_IRQHandler + B cpuss_interrupts_dw0_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_13_IRQHandler + B cpuss_interrupts_dw0_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_14_IRQHandler + B cpuss_interrupts_dw0_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_15_IRQHandler + B cpuss_interrupts_dw0_15_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_0_IRQHandler + B cpuss_interrupts_dw1_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_1_IRQHandler + B cpuss_interrupts_dw1_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_2_IRQHandler + B cpuss_interrupts_dw1_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_3_IRQHandler + B cpuss_interrupts_dw1_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_4_IRQHandler + B cpuss_interrupts_dw1_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_5_IRQHandler + B cpuss_interrupts_dw1_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_6_IRQHandler + B cpuss_interrupts_dw1_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_7_IRQHandler + B cpuss_interrupts_dw1_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_8_IRQHandler + B cpuss_interrupts_dw1_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_9_IRQHandler + B cpuss_interrupts_dw1_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_10_IRQHandler + B cpuss_interrupts_dw1_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_11_IRQHandler + B cpuss_interrupts_dw1_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_12_IRQHandler + B cpuss_interrupts_dw1_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_13_IRQHandler + B cpuss_interrupts_dw1_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_14_IRQHandler + B cpuss_interrupts_dw1_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_15_IRQHandler + B cpuss_interrupts_dw1_15_IRQHandler + + PUBWEAK cpuss_interrupts_fault_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_0_IRQHandler + B cpuss_interrupts_fault_0_IRQHandler + + PUBWEAK cpuss_interrupts_fault_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_1_IRQHandler + B cpuss_interrupts_fault_1_IRQHandler + + PUBWEAK cpuss_interrupt_crypto_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_crypto_IRQHandler + B cpuss_interrupt_crypto_IRQHandler + + PUBWEAK cpuss_interrupt_fm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_fm_IRQHandler + B cpuss_interrupt_fm_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_0_IRQHandler + B cpuss_interrupts_cm0_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_1_IRQHandler + B cpuss_interrupts_cm0_cti_1_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_0_IRQHandler + B cpuss_interrupts_cm4_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_1_IRQHandler + B cpuss_interrupts_cm4_cti_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_0_IRQHandler + B tcpwm_0_interrupts_0_IRQHandler + + PUBWEAK tcpwm_0_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_1_IRQHandler + B tcpwm_0_interrupts_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_2_IRQHandler + B tcpwm_0_interrupts_2_IRQHandler + + PUBWEAK tcpwm_0_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_3_IRQHandler + B tcpwm_0_interrupts_3_IRQHandler + + PUBWEAK tcpwm_0_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_4_IRQHandler + B tcpwm_0_interrupts_4_IRQHandler + + PUBWEAK tcpwm_0_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_5_IRQHandler + B tcpwm_0_interrupts_5_IRQHandler + + PUBWEAK tcpwm_0_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_6_IRQHandler + B tcpwm_0_interrupts_6_IRQHandler + + PUBWEAK tcpwm_0_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_7_IRQHandler + B tcpwm_0_interrupts_7_IRQHandler + + PUBWEAK tcpwm_1_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_0_IRQHandler + B tcpwm_1_interrupts_0_IRQHandler + + PUBWEAK tcpwm_1_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_1_IRQHandler + B tcpwm_1_interrupts_1_IRQHandler + + PUBWEAK tcpwm_1_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_2_IRQHandler + B tcpwm_1_interrupts_2_IRQHandler + + PUBWEAK tcpwm_1_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_3_IRQHandler + B tcpwm_1_interrupts_3_IRQHandler + + PUBWEAK tcpwm_1_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_4_IRQHandler + B tcpwm_1_interrupts_4_IRQHandler + + PUBWEAK tcpwm_1_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_5_IRQHandler + B tcpwm_1_interrupts_5_IRQHandler + + PUBWEAK tcpwm_1_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_6_IRQHandler + B tcpwm_1_interrupts_6_IRQHandler + + PUBWEAK tcpwm_1_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_7_IRQHandler + B tcpwm_1_interrupts_7_IRQHandler + + PUBWEAK tcpwm_1_interrupts_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_8_IRQHandler + B tcpwm_1_interrupts_8_IRQHandler + + PUBWEAK tcpwm_1_interrupts_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_9_IRQHandler + B tcpwm_1_interrupts_9_IRQHandler + + PUBWEAK tcpwm_1_interrupts_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_10_IRQHandler + B tcpwm_1_interrupts_10_IRQHandler + + PUBWEAK tcpwm_1_interrupts_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_11_IRQHandler + B tcpwm_1_interrupts_11_IRQHandler + + PUBWEAK tcpwm_1_interrupts_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_12_IRQHandler + B tcpwm_1_interrupts_12_IRQHandler + + PUBWEAK tcpwm_1_interrupts_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_13_IRQHandler + B tcpwm_1_interrupts_13_IRQHandler + + PUBWEAK tcpwm_1_interrupts_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_14_IRQHandler + B tcpwm_1_interrupts_14_IRQHandler + + PUBWEAK tcpwm_1_interrupts_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_15_IRQHandler + B tcpwm_1_interrupts_15_IRQHandler + + PUBWEAK tcpwm_1_interrupts_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_16_IRQHandler + B tcpwm_1_interrupts_16_IRQHandler + + PUBWEAK tcpwm_1_interrupts_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_17_IRQHandler + B tcpwm_1_interrupts_17_IRQHandler + + PUBWEAK tcpwm_1_interrupts_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_18_IRQHandler + B tcpwm_1_interrupts_18_IRQHandler + + PUBWEAK tcpwm_1_interrupts_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_19_IRQHandler + B tcpwm_1_interrupts_19_IRQHandler + + PUBWEAK tcpwm_1_interrupts_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_20_IRQHandler + B tcpwm_1_interrupts_20_IRQHandler + + PUBWEAK tcpwm_1_interrupts_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_21_IRQHandler + B tcpwm_1_interrupts_21_IRQHandler + + PUBWEAK tcpwm_1_interrupts_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_22_IRQHandler + B tcpwm_1_interrupts_22_IRQHandler + + PUBWEAK tcpwm_1_interrupts_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_23_IRQHandler + B tcpwm_1_interrupts_23_IRQHandler + + PUBWEAK udb_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_0_IRQHandler + B udb_interrupts_0_IRQHandler + + PUBWEAK udb_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_1_IRQHandler + B udb_interrupts_1_IRQHandler + + PUBWEAK udb_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_2_IRQHandler + B udb_interrupts_2_IRQHandler + + PUBWEAK udb_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_3_IRQHandler + B udb_interrupts_3_IRQHandler + + PUBWEAK udb_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_4_IRQHandler + B udb_interrupts_4_IRQHandler + + PUBWEAK udb_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_5_IRQHandler + B udb_interrupts_5_IRQHandler + + PUBWEAK udb_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_6_IRQHandler + B udb_interrupts_6_IRQHandler + + PUBWEAK udb_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_7_IRQHandler + B udb_interrupts_7_IRQHandler + + PUBWEAK udb_interrupts_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_8_IRQHandler + B udb_interrupts_8_IRQHandler + + PUBWEAK udb_interrupts_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_9_IRQHandler + B udb_interrupts_9_IRQHandler + + PUBWEAK udb_interrupts_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_10_IRQHandler + B udb_interrupts_10_IRQHandler + + PUBWEAK udb_interrupts_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_11_IRQHandler + B udb_interrupts_11_IRQHandler + + PUBWEAK udb_interrupts_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_12_IRQHandler + B udb_interrupts_12_IRQHandler + + PUBWEAK udb_interrupts_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_13_IRQHandler + B udb_interrupts_13_IRQHandler + + PUBWEAK udb_interrupts_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_14_IRQHandler + B udb_interrupts_14_IRQHandler + + PUBWEAK udb_interrupts_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +udb_interrupts_15_IRQHandler + B udb_interrupts_15_IRQHandler + + PUBWEAK pass_interrupt_sar_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_sar_IRQHandler + B pass_interrupt_sar_IRQHandler + + PUBWEAK audioss_interrupt_i2s_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +audioss_interrupt_i2s_IRQHandler + B audioss_interrupt_i2s_IRQHandler + + PUBWEAK audioss_interrupt_pdm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +audioss_interrupt_pdm_IRQHandler + B audioss_interrupt_pdm_IRQHandler + + PUBWEAK profile_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +profile_interrupt_IRQHandler + B profile_interrupt_IRQHandler + + PUBWEAK smif_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +smif_interrupt_IRQHandler + B smif_interrupt_IRQHandler + + PUBWEAK usb_interrupt_hi_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_hi_IRQHandler + B usb_interrupt_hi_IRQHandler + + PUBWEAK usb_interrupt_med_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_med_IRQHandler + B usb_interrupt_med_IRQHandler + + PUBWEAK usb_interrupt_lo_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_lo_IRQHandler + B usb_interrupt_lo_IRQHandler + + PUBWEAK pass_interrupt_dacs_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_dacs_IRQHandler + B pass_interrupt_dacs_IRQHandler + + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/system_psoc6.h new file mode 100644 index 00000000000..423361f58ab --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/system_psoc6.h @@ -0,0 +1,680 @@ +/***************************************************************************//** +* \file system_psoc6.h +* \version 2.60 +* +* \brief Device system header file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + + +#ifndef _SYSTEM_PSOC6_H_ +#define _SYSTEM_PSOC6_H_ + +/** +* \addtogroup group_system_config +* \{ +* Provides device startup, system configuration, and linker script files. +* The system startup provides the followings features: +* - See \ref group_system_config_device_initialization for the: +* * \ref group_system_config_dual_core_device_initialization +* * \ref group_system_config_single_core_device_initialization +* - \ref group_system_config_device_memory_definition +* - \ref group_system_config_heap_stack_config +* - \ref group_system_config_merge_apps +* - \ref group_system_config_default_handlers +* - \ref group_system_config_device_vector_table +* - \ref group_system_config_cm4_functions +* +* \section group_system_config_configuration Configuration Considerations +* +* \subsection group_system_config_device_memory_definition Device Memory Definition +* The flash and RAM allocation for each CPU is defined by the linker scripts. +* For dual-core devices, the physical flash and RAM memory is shared between the CPU cores. +* 2 KB of RAM (allocated at the end of RAM) are reserved for system use. +* For Single-Core devices the system reserves additional 80 bytes of RAM. +* Using the reserved memory area for other purposes will lead to unexpected behavior. +* +* \note The linker files provided with the PDL are generic and handle all common +* use cases. Your project may not use every section defined in the linker files. +* In that case you may see warnings during the build process. To eliminate build +* warnings in your project, you can simply comment out or remove the relevant +* code in the linker file. +* +* ARM GCC\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example, +* 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the +* Cy_SysEnableCM4() function call. +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.ld', where 'xx' is the device group: +* \code +* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000 +* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000 +* \endcode +* - 'xx_cm4_dual.ld', where 'xx' is the device group: +* \code +* flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000 +* ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800 +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's +* value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this +* by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* +* ARM MDK\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example, +* 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref +* Cy_SysEnableCM4() function call. +* +* \note The linker files provided with the PDL are generic and handle all common +* use cases. Your project may not use every section defined in the linker files. +* In that case you may see the warnings during the build process: +* L6314W (no section matches pattern) and/or L6329W +* (pattern only matches removed unused sections). In your project, you can +* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +* the linker. You can also comment out or remove the relevant code in the linker +* file. +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.scat', where 'xx' is the device group: +* \code +* #define FLASH_START 0x10000000 +* #define FLASH_SIZE 0x00080000 +* #define RAM_START 0x08000000 +* #define RAM_SIZE 0x00024000 +* \endcode +* - 'xx_cm4_dual.scat', where 'xx' is the device group: +* \code +* #define FLASH_START 0x10080000 +* #define FLASH_SIZE 0x00080000 +* #define RAM_START 0x08024000 +* #define RAM_SIZE 0x00023800 +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START +* value in the 'xx_cm4_dual.scat' file, +* where 'xx' is the device group. Do this by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* +* IAR\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.icf', where 'xx' is the device group, and 'yy' is the target CPU; for example, +* 'cy8c6xx7_cm0plus.icf' and 'cy8c6xx7_cm4_dual.icf'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref +* Cy_SysEnableCM4() function call. +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.icf', where 'xx' is the device group: +* \code +* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000; +* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000; +* \endcode +* - 'xx_cm4_dual.icf', where 'xx' is the device group: +* \code +* define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000; +* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800; +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the +* __ICFEDIT_region_IROM1_start__ value in the 'xx_cm4_dual.icf' file, where 'xx' +* is the device group. Do this by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* +* \subsection group_system_config_device_initialization Device Initialization +* After a power-on-reset (POR), the boot process is handled by the boot code +* from the on-chip ROM that is always executed by the Cortex-M0+ core. The boot +* code passes the control to the Cortex-M0+ startup code located in flash. +* +* \subsubsection group_system_config_dual_core_device_initialization Dual-Core Devices +* The Cortex-M0+ startup code performs the device initialization by a call to +* SystemInit() and then calls the main() function. The Cortex-M4 core is disabled +* by default. Enable the core using the \ref Cy_SysEnableCM4() function. +* See \ref group_system_config_cm4_functions for more details. +* \note Startup code executes SystemInit() function for the both Cortex-M0+ and Cortex-M4 cores. +* The function has a separate implementation on each core. +* Both function implementations unlock and disable the WDT. +* Therefore enable the WDT after both cores have been initialized. +* +* \subsubsection group_system_config_single_core_device_initialization Single-Core Devices +* The Cortex-M0+ core is not user-accessible on these devices. In this case the +* Flash Boot handles setup of the CM0+ core and starts the Cortex-M4 core. +* +* \subsection group_system_config_heap_stack_config Heap and Stack Configuration +* There are two ways to adjust heap and stack configurations: +* -# Editing source code files +* -# Specifying via command line +* +* By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400. +* +* \subsubsection group_system_config_heap_stack_config_gcc ARM GCC +* - Editing source code files\n +* The heap and stack sizes are defined in the assembler startup files +* (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). +* Change the heap and stack sizes by modifying the following lines:\n +* \code .equ Stack_Size, 0x00001000 \endcode +* \code .equ Heap_Size, 0x00000400 \endcode +* +* - Specifying via command line\n +* Change the heap and stack sizes passing the following commands to the compiler:\n +* \code -D __STACK_SIZE=0x000000400 \endcode +* \code -D __HEAP_SIZE=0x000000100 \endcode +* +* \subsubsection group_system_config_heap_stack_config_mdk ARM MDK +* - Editing source code files\n +* The heap and stack sizes are defined in the assembler startup files +* (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). +* Change the heap and stack sizes by modifying the following lines:\n +* \code Stack_Size EQU 0x00001000 \endcode +* \code Heap_Size EQU 0x00000400 \endcode +* +* - Specifying via command line\n +* Change the heap and stack sizes passing the following commands to the assembler:\n +* \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode +* \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode +* +* \subsubsection group_system_config_heap_stack_config_iar IAR +* - Editing source code files\n +* The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. +* Change the heap and stack sizes by modifying the following lines:\n +* \code Stack_Size EQU 0x00001000 \endcode +* \code Heap_Size EQU 0x00000400 \endcode +* +* - Specifying via command line\n +* Change the heap and stack sizes passing the following commands to the +* linker (including quotation marks):\n +* \code --define_symbol __STACK_SIZE=0x000000400 \endcode +* \code --define_symbol __HEAP_SIZE=0x000000100 \endcode +* +* \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables +* The CM0+ project and linker script build the CM0+ application image. Similarly, +* the CM4 linker script builds the CM4 application image. Each specifies +* locations, sizes, and contents of sections in memory. See +* \ref group_system_config_device_memory_definition for the symbols and default +* values. +* +* The cymcuelftool is invoked by a post-build command. The precise project +* setting is IDE-specific. +* +* The cymcuelftool combines the two executables. The tool examines the +* executables to ensure that memory regions either do not overlap, or contain +* identical bytes (shared). If there are no problems, it creates a new ELF file +* with the merged image, without changing any of the addresses or data. +* +* \subsection group_system_config_default_handlers Default Interrupt Handlers Definition +* The default interrupt handler functions are defined as weak functions to a dummy +* handler in the startup file. The naming convention for the interrupt handler names +* is \_IRQHandler. A default interrupt handler can be overwritten in +* user code by defining the handler function using the same name. For example: +* \code +* void scb_0_interrupt_IRQHandler(void) +*{ +* ... +*} +* \endcode +* +* \subsection group_system_config_device_vector_table Vectors Table Copy from Flash to RAM +* This process uses memory sections defined in the linker script. The startup +* code actually defines the contents of the vector table and performs the copy. +* \subsubsection group_system_config_device_vector_table_gcc ARM GCC +* The linker script file is 'xx_yy.ld', where 'xx' is the device family, and +* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld. +* It defines sections and locations in memory.\n +* Copy interrupt vectors from flash to RAM: \n +* From: \code LONG (__Vectors) \endcode +* To: \code LONG (__ram_vectors_start__) \endcode +* Size: \code LONG (__Vectors_End - __Vectors) \endcode +* The vector table address (and the vector table itself) are defined in the +* assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). +* The code in these files copies the vector table from Flash to RAM. +* \subsubsection group_system_config_device_vector_table_mdk ARM MDK +* The linker script file is 'xx_yy.scat', where 'xx' is the device family, +* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and +* cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table +* (RESET_RAM) shall be first in the RAM section.\n +* RESET_RAM represents the vector table. It is defined in the assembler startup +* files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). +* The code in these files copies the vector table from Flash to RAM. +* +* \subsubsection group_system_config_device_vector_table_iar IAR +* The linker script file is 'xx_yy.icf', where 'xx' is the device family, and +* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. +* This file defines the .intvec_ram section and its location. +* \code place at start of IRAM1_region { readwrite section .intvec_ram}; \endcode +* The vector table address (and the vector table itself) are defined in the +* assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). +* The code in these files copies the vector table from Flash to RAM. +* +* \section group_system_config_more_information More Information +* Refer to the PDL User Guide for the +* more details. +* +* \section group_system_config_MISRA MISRA Compliance +* +*
VersionChangesReason for Change
4.40 +* Fixed \ref Cy_SysPm_LdoSetVoltage(), \ref Cy_SysPm_BuckEnable(), and +* \ref Cy_SysPm_BuckSetVoltage1() functions. Corrected the sequence for +* setting the RAM trim value. This behavior is applicable for all +* devices, except CY8C6xx6 and CY8C6xx7. +* +* For all devices, except CY8C6xx6 and CY8C6xx7, the trim +* sequence was setting incorrect trim values for RAM. +* This could cause a CPU hard fault. +*
4.30 * Corrected the \ref Cy_SysPm_CpuEnterDeepSleep() function. @@ -1209,7 +1223,7 @@ extern "C" { #define CY_SYSPM_DRV_VERSION_MAJOR 4 /** Driver minor version */ -#define CY_SYSPM_DRV_VERSION_MINOR 30 +#define CY_SYSPM_DRV_VERSION_MINOR 40 /** SysPm driver identifier */ #define CY_SYSPM_ID (CY_PDL_DRV_ID(0x10U)) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_canfd.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_canfd.c index 6b485495a50..4a8098fae67 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_canfd.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_canfd.c @@ -1,6 +1,6 @@ /******************************************************************************* * \file cy_canfd.c -* \version 1.0 +* \version 1.0.1 * * \brief * Provides an API implementation of the CAN FD driver. @@ -229,6 +229,7 @@ static uint32_t Cy_CANFD_CalcTxBufAdrs(CANFD_Type *base, uint32_t chan, * "Rx FIFO 1 New Message" and "Rx FIFO 0 New Message" interrupt events only. * Other interrupts can be configured with the Cy_CANFD_SetInterruptMask() function. * \note If the channel was disabled, call Cy_CANFD_Enable before calling Cy_CANFD_Init. +* \note Call this function only after all debug messages reception is completed. * * \param *base * The pointer to a CAN FD instance. @@ -512,8 +513,8 @@ cy_en_canfd_status_t Cy_CANFD_Init(CANFD_Type *base, uint32_t chan, * * De-initializes the CAN FD block, returns registers values to default. * -* \note -* Do not call Cy_CANFD_Disable before Cy_CANFD_DeInit. +* \note Do not call Cy_CANFD_Disable before Cy_CANFD_DeInit. +* \note Call this function only after all debug messages reception is completed. * * \param *base * The pointer to a CAN FD instance. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_device.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_device.c index 2a3d6e9a0fa..c89104a36d0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_device.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_device.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_device.c -* \version 2.0 +* \version 2.10 * * This file provides the definitions for core and peripheral block HW base * addresses, versions, and parameters. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_flash.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_flash.c index 26b5165d014..4c7b385806d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_flash.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_flash.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_flash.c -* \version 3.30.1 +* \version 3.30.2 * * \brief * Provides the public functions for the API for the PSoC 6 Flash Driver. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syspm.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syspm.c index 5949fcbcec9..7b1244edfe8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syspm.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syspm.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_syspm.c -* \version 4.30 +* \version 4.40 * * This driver provides the source code for API power management. * @@ -3110,7 +3110,7 @@ static void SetReadMarginTrimUlp(void) else { CPUSS_TRIM_RAM_CTL = (SFLASH_CPUSS_TRIM_RAM_CTL_HALF_ULP & ((uint32_t) ~CPUSS_TRIM_RAM_CTL_RA_MASK)) | - (CPUSS_TRIM_RAM_CTL | CPUSS_TRIM_RAM_CTL_RA_MASK); + (CPUSS_TRIM_RAM_CTL & CPUSS_TRIM_RAM_CTL_RA_MASK); CPUSS_TRIM_ROM_CTL = SFLASH_CPUSS_TRIM_ROM_CTL_HALF_ULP; } @@ -3139,8 +3139,8 @@ static void SetReadMarginTrimLp(void) } else { - CPUSS_TRIM_RAM_CTL = (SFLASH_CPUSS_TRIM_ROM_CTL_LP & ((uint32_t) ~CPUSS_TRIM_RAM_CTL_RA_MASK)) | - (CPUSS_TRIM_RAM_CTL | CPUSS_TRIM_RAM_CTL_RA_MASK); + CPUSS_TRIM_RAM_CTL = (SFLASH_CPUSS_TRIM_RAM_CTL_LP & ((uint32_t) ~CPUSS_TRIM_RAM_CTL_RA_MASK)) | + (CPUSS_TRIM_RAM_CTL & CPUSS_TRIM_RAM_CTL_RA_MASK); CPUSS_TRIM_ROM_CTL = SFLASH_CPUSS_TRIM_ROM_CTL_LP; } @@ -3166,8 +3166,8 @@ static void SetWriteAssistTrimUlp(void) } else { - CPUSS_TRIM_RAM_CTL = (SFLASH_CPUSS_TRIM_ROM_CTL_ULP & ((uint32_t) ~CPUSS_TRIM_RAM_CTL_RA_MASK)) | - (CPUSS_TRIM_RAM_CTL | CPUSS_TRIM_RAM_CTL_RA_MASK); + CPUSS_TRIM_RAM_CTL = (SFLASH_CPUSS_TRIM_RAM_CTL_ULP & ((uint32_t) ~CPUSS_TRIM_RAM_CTL_RA_MASK)) | + (CPUSS_TRIM_RAM_CTL & CPUSS_TRIM_RAM_CTL_RA_MASK); } } @@ -3191,8 +3191,8 @@ static void SetWriteAssistTrimLp(void) } else { - CPUSS_TRIM_RAM_CTL = (SFLASH_CPUSS_TRIM_ROM_CTL_HALF_LP & ((uint32_t) ~CPUSS_TRIM_RAM_CTL_RA_MASK)) | - (CPUSS_TRIM_RAM_CTL | CPUSS_TRIM_RAM_CTL_RA_MASK); + CPUSS_TRIM_RAM_CTL = (SFLASH_CPUSS_TRIM_RAM_CTL_HALF_LP & ((uint32_t) ~CPUSS_TRIM_RAM_CTL_RA_MASK)) | + (CPUSS_TRIM_RAM_CTL & CPUSS_TRIM_RAM_CTL_RA_MASK); CPUSS_TRIM_ROM_CTL = SFLASH_CPUSS_TRIM_ROM_CTL_HALF_LP; } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/version.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/version.xml index cef1ad789e3..7fa78eaf8e3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/version.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/version.xml @@ -1 +1 @@ -1.3.1.1474 +1.3.1.1499 From dd9f9e1cb5d22f378111e61a9dad13a4a0ae01a3 Mon Sep 17 00:00:00 2001 From: Vincent Veron Date: Thu, 22 Aug 2019 15:06:22 +0200 Subject: [PATCH 130/227] STM32H7 : use RAM instead of DTCMRAM (IAR toolchain) Keep vector table and crash data ram in 0x20000000 for tests-mbed_platform-crash_reporting test. Move the rest in RAM (0x24000000). This is needed for ethernet and allows user to use more RAM (512k). Signed-off-by: Vincent Veron --- .../device/TOOLCHAIN_IAR/stm32h743xI.icf | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/device/TOOLCHAIN_IAR/stm32h743xI.icf b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/device/TOOLCHAIN_IAR/stm32h743xI.icf index cd92feee9c1..f6eee32e677 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/device/TOOLCHAIN_IAR/stm32h743xI.icf +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/device/TOOLCHAIN_IAR/stm32h743xI.icf @@ -10,11 +10,11 @@ define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; // 512KB RAM (0x80000) // Vector table dynamic copy: 166 vectors = 664 bytes (0x298) reserved // Crash data area: 256 bytes (0x100) reserved -define symbol __NVIC_start__ = 0x24000000; -define symbol __NVIC_end__ = 0x24000297; -define symbol __region_CRASH_DATA_RAM_start__ = 0x24000298; // Aligned on 8 bytes -define symbol __region_CRASH_DATA_RAM_end__ = 0x24000397; -define symbol __region_RAM_start__ = 0x24000398; // Aligned on 8 bytes +define symbol __NVIC_start__ = 0x20000000; +define symbol __NVIC_end__ = 0x20000297; +define symbol __region_CRASH_DATA_RAM_start__ = 0x20000298; // Aligned on 8 bytes +define symbol __region_CRASH_DATA_RAM_end__ = 0x20000397; +define symbol __region_RAM_start__ = 0x24000000; // Aligned on 8 bytes define symbol __region_RAM_end__ = 0x24000000 + 0x80000 - 1; // Memory regions From 7561e770a328c058447c7ca0159ea5de24a74e9e Mon Sep 17 00:00:00 2001 From: Vincent Veron Date: Thu, 29 Aug 2019 14:36:15 +0200 Subject: [PATCH 131/227] STM32H7 : use RAM instead of DTCMRAM (ARM toolchain) --- .../device/TOOLCHAIN_ARM_STD/startup_stm32h743xx.S | 4 ++-- .../device/TOOLCHAIN_ARM_STD/stm32h743xI.sct | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/device/TOOLCHAIN_ARM_STD/startup_stm32h743xx.S b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/device/TOOLCHAIN_ARM_STD/startup_stm32h743xx.S index 6f26d2f969d..aadbff68357 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/device/TOOLCHAIN_ARM_STD/startup_stm32h743xx.S +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/device/TOOLCHAIN_ARM_STD/startup_stm32h743xx.S @@ -24,7 +24,7 @@ ;* ;****************************************************************************** -__initial_sp EQU 0x20020000 ; Top of RAM + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| PRESERVE8 THUMB @@ -36,7 +36,7 @@ __initial_sp EQU 0x20020000 ; Top of RAM EXPORT __Vectors_End EXPORT __Vectors_Size -__Vectors DCD __initial_sp ; Top of Stack +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/device/TOOLCHAIN_ARM_STD/stm32h743xI.sct b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/device/TOOLCHAIN_ARM_STD/stm32h743xI.sct index be31314ac49..90385094459 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/device/TOOLCHAIN_ARM_STD/stm32h743xI.sct +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/device/TOOLCHAIN_ARM_STD/stm32h743xI.sct @@ -44,12 +44,12 @@ #define MBED_RAM_START 0x24000000 #define MBED_RAM_SIZE 0x80000 -#define MBED_VECTTABLE_RAM_START (MBED_RAM_START) +#define MBED_VECTTABLE_RAM_START 0x20000000 #define MBED_VECTTABLE_RAM_SIZE 0x298 #define MBED_CRASH_REPORT_RAM_START (MBED_VECTTABLE_RAM_START + MBED_VECTTABLE_RAM_SIZE) #define MBED_CRASH_REPORT_RAM_SIZE 0x100 -#define MBED_RAM0_START (MBED_CRASH_REPORT_RAM_START + MBED_CRASH_REPORT_RAM_SIZE) -#define MBED_RAM0_SIZE (MBED_RAM_SIZE - MBED_VECTTABLE_RAM_SIZE - MBED_CRASH_REPORT_RAM_SIZE) +#define MBED_RAM0_START (MBED_RAM_START) +#define MBED_RAM0_SIZE (MBED_RAM_SIZE) LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region From 85757ce1983924b4f0371c6beb57c84e61f300de Mon Sep 17 00:00:00 2001 From: Vincent Veron Date: Thu, 29 Aug 2019 14:42:27 +0200 Subject: [PATCH 132/227] STM32H7 : use RAM instead of DTCMRAM (GCC_ARM toolchain) --- .../device/TOOLCHAIN_GCC_ARM/STM32H743xI.ld | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/device/TOOLCHAIN_GCC_ARM/STM32H743xI.ld b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/device/TOOLCHAIN_GCC_ARM/STM32H743xI.ld index 12dfa9020cc..9e06e3470a9 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/device/TOOLCHAIN_GCC_ARM/STM32H743xI.ld +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/device/TOOLCHAIN_GCC_ARM/STM32H743xI.ld @@ -19,8 +19,8 @@ M_CRASH_DATA_RAM_SIZE = 0x100; MEMORY { FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE - DTCMRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 128K - RAM (xrw) : ORIGIN = 0x24000298, LENGTH = 512K - 0x298 /* end = 0x24080000 */ + DTCMRAM (rwx) : ORIGIN = 0x20000298, LENGTH = 128K-0x298 + RAM (xrw) : ORIGIN = 0x24000000, LENGTH = 512K RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K @@ -108,7 +108,7 @@ SECTIONS . += M_CRASH_DATA_RAM_SIZE; . = ALIGN(8); __CRASH_DATA_RAM_END__ = .; /* Define a global symbol at data end */ - } > RAM + } > DTCMRAM .data : AT (__etext) { From 0a7a0d813435e5ea58513924dbb4104de051ea55 Mon Sep 17 00:00:00 2001 From: Hugues Kamba Date: Mon, 9 Sep 2019 09:04:07 +0100 Subject: [PATCH 133/227] Remove unreachable statements warnings The warnings are observed when building with the IAR toolchain. --- drivers/source/usb/USBDevice.cpp | 189 ++++++++++++++++++++++++++++--- hal/mbed_pinmap_common.c | 1 - hal/mbed_ticker_api.c | 23 +++- 3 files changed, 192 insertions(+), 21 deletions(-) diff --git a/drivers/source/usb/USBDevice.cpp b/drivers/source/usb/USBDevice.cpp index 945deb69ecf..40c3b0df932 100644 --- a/drivers/source/usb/USBDevice.cpp +++ b/drivers/source/usb/USBDevice.cpp @@ -22,6 +22,7 @@ #include "USBDescriptor.h" #include "usb_phy_api.h" #include "mbed_assert.h" +#include "platform/mbed_error.h" //#define DEBUG @@ -852,8 +853,17 @@ void USBDevice::ep0_setup() assert_locked(); if (_device.state < Default) { - MBED_ASSERT(0); +#if MBED_TRAP_ERRORS_ENABLED + MBED_ERROR( + MBED_MAKE_ERROR( + MBED_MODULE_DRIVER_USB, + MBED_ERROR_CODE_NOT_READY + ), + "Device state is \"Powered\" or \"Detached\"" + ); +#else return; +#endif // MBED_TRAP_ERRORS_ENABLED } _setup_ready = true; @@ -874,15 +884,33 @@ void USBDevice::ep0_out() assert_locked(); if (_device.state < Default) { - MBED_ASSERT(0); +#if MBED_TRAP_ERRORS_ENABLED + MBED_ERROR( + MBED_MAKE_ERROR( + MBED_MODULE_DRIVER_USB, + MBED_ERROR_CODE_NOT_READY + ), + "Device state is \"Powered\" or \"Detached\"" + ); +#else return; +#endif // MBED_TRAP_ERRORS_ENABLED } if (_transfer.user_callback != None) { /* EP0 OUT should not receive data if the stack is waiting on a user callback for the buffer to fill or status */ - MBED_ASSERT(0); +#if MBED_TRAP_ERRORS_ENABLED + MBED_ERROR( + MBED_MAKE_ERROR( + MBED_MODULE_DRIVER_USB, + MBED_ERROR_CODE_NOT_READY + ), + "The stack is waiting on a user callback for the buffer to fill or status." + ); +#else return; +#endif // MBED_TRAP_ERRORS_ENABLED } if (_transfer.stage == Status) { @@ -903,8 +931,17 @@ void USBDevice::ep0_in() assert_locked(); if (_device.state < Default) { - MBED_ASSERT(0); +#if MBED_TRAP_ERRORS_ENABLED + MBED_ERROR( + MBED_MAKE_ERROR( + MBED_MODULE_DRIVER_USB, + MBED_ERROR_CODE_NOT_READY + ), + "Device state is \"Powered\" or \"Detached\"" + ); +#else return; +#endif // MBED_TRAP_ERRORS_ENABLED } #ifdef DEBUG @@ -928,8 +965,17 @@ void USBDevice::out(usb_ep_t endpoint) assert_locked(); if (!EP_INDEXABLE(endpoint)) { - MBED_ASSERT(0); +#if MBED_TRAP_ERRORS_ENABLED + MBED_ERROR( + MBED_MAKE_ERROR( + MBED_MODULE_DRIVER_USB, + MBED_ERROR_CODE_INVALID_INDEX + ), + "The endpoint is not indexable." + ); +#else return; +#endif // MBED_TRAP_ERRORS_ENABLED } endpoint_info_t *info = &_endpoint_info[EP_TO_INDEX(endpoint)]; @@ -946,8 +992,17 @@ void USBDevice::in(usb_ep_t endpoint) assert_locked(); if (!EP_INDEXABLE(endpoint)) { - MBED_ASSERT(0); +#if MBED_TRAP_ERRORS_ENABLED + MBED_ERROR( + MBED_MAKE_ERROR( + MBED_MODULE_DRIVER_USB, + MBED_ERROR_CODE_INVALID_INDEX + ), + "The endpoint is not indexable." + ); +#else return; +#endif // MBED_TRAP_ERRORS_ENABLED } endpoint_info_t *info = &_endpoint_info[EP_TO_INDEX(endpoint)]; @@ -1056,9 +1111,18 @@ bool USBDevice::endpoint_add(usb_ep_t endpoint, uint32_t max_packet_size, usb_ep lock(); if (!EP_INDEXABLE(endpoint)) { - MBED_ASSERT(0); +#if MBED_TRAP_ERRORS_ENABLED + MBED_ERROR( + MBED_MAKE_ERROR( + MBED_MODULE_DRIVER_USB, + MBED_ERROR_CODE_INVALID_INDEX + ), + "The endpoint is not indexable." + ); +#else unlock(); return false; +#endif // MBED_TRAP_ERRORS_ENABLED } if (!_endpoint_add_remove_allowed) { @@ -1087,9 +1151,18 @@ void USBDevice::endpoint_remove(usb_ep_t endpoint) lock(); if (!EP_INDEXABLE(endpoint)) { - MBED_ASSERT(0); +#if MBED_TRAP_ERRORS_ENABLED + MBED_ERROR( + MBED_MAKE_ERROR( + MBED_MODULE_DRIVER_USB, + MBED_ERROR_CODE_INVALID_INDEX + ), + "The endpoint is not indexable." + ); +#else unlock(); return; +#endif // MBED_TRAP_ERRORS_ENABLED } if (!_endpoint_add_remove_allowed) { @@ -1133,9 +1206,18 @@ void USBDevice::endpoint_stall(usb_ep_t endpoint) lock(); if (!EP_INDEXABLE(endpoint)) { - MBED_ASSERT(0); +#if MBED_TRAP_ERRORS_ENABLED + MBED_ERROR( + MBED_MAKE_ERROR( + MBED_MODULE_DRIVER_USB, + MBED_ERROR_CODE_INVALID_INDEX + ), + "The endpoint is not indexable." + ); +#else unlock(); return; +#endif // MBED_TRAP_ERRORS_ENABLED } endpoint_info_t *info = &_endpoint_info[EP_TO_INDEX(endpoint)]; @@ -1161,9 +1243,18 @@ void USBDevice::endpoint_unstall(usb_ep_t endpoint) lock(); if (!EP_INDEXABLE(endpoint)) { - MBED_ASSERT(0); +#if MBED_TRAP_ERRORS_ENABLED + MBED_ERROR( + MBED_MAKE_ERROR( + MBED_MODULE_DRIVER_USB, + MBED_ERROR_CODE_INVALID_INDEX + ), + "The endpoint is not indexable." + ); +#else unlock(); return; +#endif // MBED_TRAP_ERRORS_ENABLED } endpoint_info_t *info = &_endpoint_info[EP_TO_INDEX(endpoint)]; @@ -1307,9 +1398,18 @@ void USBDevice::endpoint_abort(usb_ep_t endpoint) lock(); if (!EP_INDEXABLE(endpoint)) { - MBED_ASSERT(0); +#if MBED_TRAP_ERRORS_ENABLED + MBED_ERROR( + MBED_MAKE_ERROR( + MBED_MODULE_DRIVER_USB, + MBED_ERROR_CODE_INVALID_INDEX + ), + "The endpoint is not indexable." + ); +#else unlock(); return; +#endif // MBED_TRAP_ERRORS_ENABLED } endpoint_info_t *info = &_endpoint_info[EP_TO_INDEX(endpoint)]; @@ -1333,9 +1433,18 @@ bool USBDevice::read_start(usb_ep_t endpoint, uint8_t *buffer, uint32_t max_size lock(); if (!EP_INDEXABLE(endpoint)) { - MBED_ASSERT(0); +#if MBED_TRAP_ERRORS_ENABLED + MBED_ERROR( + MBED_MAKE_ERROR( + MBED_MODULE_DRIVER_USB, + MBED_ERROR_CODE_INVALID_INDEX + ), + "The endpoint is not indexable." + ); +#else unlock(); return false; +#endif // MBED_TRAP_ERRORS_ENABLED } endpoint_info_t *info = &_endpoint_info[EP_TO_INDEX(endpoint)]; @@ -1347,9 +1456,18 @@ bool USBDevice::read_start(usb_ep_t endpoint, uint8_t *buffer, uint32_t max_size } if (max_size < info->max_packet_size) { - MBED_ASSERT(0); +#if MBED_TRAP_ERRORS_ENABLED + MBED_ERROR( + MBED_MAKE_ERROR( + MBED_MODULE_DRIVER_USB, + MBED_ERROR_CODE_INVALID_SIZE + ), + "The size of the data to read is less than the max packet size for this endpoint." + ); +#else unlock(); return false; +#endif // MBED_TRAP_ERRORS_ENABLED } if (info->pending) { @@ -1373,9 +1491,18 @@ uint32_t USBDevice::read_finish(usb_ep_t endpoint) lock(); if (!EP_INDEXABLE(endpoint)) { - MBED_ASSERT(0); +#if MBED_TRAP_ERRORS_ENABLED + MBED_ERROR( + MBED_MAKE_ERROR( + MBED_MODULE_DRIVER_USB, + MBED_ERROR_CODE_INVALID_INDEX + ), + "The endpoint is not indexable." + ); +#else unlock(); return 0; +#endif // MBED_TRAP_ERRORS_ENABLED } endpoint_info_t *info = &_endpoint_info[EP_TO_INDEX(endpoint)]; @@ -1397,9 +1524,18 @@ bool USBDevice::write_start(usb_ep_t endpoint, uint8_t *buffer, uint32_t size) lock(); if (!EP_INDEXABLE(endpoint)) { - MBED_ASSERT(0); +#if MBED_TRAP_ERRORS_ENABLED + MBED_ERROR( + MBED_MAKE_ERROR( + MBED_MODULE_DRIVER_USB, + MBED_ERROR_CODE_INVALID_INDEX + ), + "The endpoint is not indexable" + ); +#else unlock(); return false; +#endif // MBED_TRAP_ERRORS_ENABLED } endpoint_info_t *info = &_endpoint_info[EP_TO_INDEX(endpoint)]; @@ -1411,10 +1547,18 @@ bool USBDevice::write_start(usb_ep_t endpoint, uint8_t *buffer, uint32_t size) } if (size > info->max_packet_size) { - // Size being written is too large - MBED_ASSERT(0); +#if MBED_TRAP_ERRORS_ENABLED + MBED_ERROR( + MBED_MAKE_ERROR( + MBED_MODULE_DRIVER_USB, + MBED_ERROR_CODE_INVALID_SIZE + ), + "Size being written is too large." + ); +#else unlock(); return false; +#endif // MBED_TRAP_ERRORS_ENABLED } if (info->pending) { @@ -1443,9 +1587,18 @@ uint32_t USBDevice::write_finish(usb_ep_t endpoint) lock(); if (!EP_INDEXABLE(endpoint)) { - MBED_ASSERT(0); +#if MBED_TRAP_ERRORS_ENABLED + MBED_ERROR( + MBED_MAKE_ERROR( + MBED_MODULE_DRIVER_USB, + MBED_ERROR_CODE_INVALID_INDEX + ), + "The endpoint is not indexable." + ); +#else unlock(); return 0; +#endif // MBED_TRAP_ERRORS_ENABLED } endpoint_info_t *info = &_endpoint_info[EP_TO_INDEX(endpoint)]; diff --git a/hal/mbed_pinmap_common.c b/hal/mbed_pinmap_common.c index 2c2643e0312..6903dca791d 100644 --- a/hal/mbed_pinmap_common.c +++ b/hal/mbed_pinmap_common.c @@ -52,7 +52,6 @@ uint32_t pinmap_merge(uint32_t a, uint32_t b) // mis-match error case MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_PINMAP_INVALID), "pinmap mis-match", a); - return (uint32_t)NC; } uint32_t pinmap_find_peripheral(PinName pin, const PinMap *map) diff --git a/hal/mbed_ticker_api.c b/hal/mbed_ticker_api.c index 5591b1485bf..55aeb7685c0 100644 --- a/hal/mbed_ticker_api.c +++ b/hal/mbed_ticker_api.c @@ -19,6 +19,7 @@ #include "hal/ticker_api.h" #include "platform/mbed_critical.h" #include "platform/mbed_assert.h" +#include "platform/mbed_error.h" static void schedule_interrupt(const ticker_data_t *const ticker); static void update_present_time(const ticker_data_t *const ticker); @@ -42,8 +43,17 @@ static void initialize(const ticker_data_t *ticker) const ticker_info_t *info = ticker->interface->get_info(); uint32_t frequency = info->frequency; if (info->frequency == 0) { - MBED_ASSERT(0); +#if MBED_TRAP_ERRORS_ENABLED + MBED_ERROR( + MBED_MAKE_ERROR( + MBED_MODULE_HAL, + MBED_ERROR_CODE_NOT_READY + ), + "Ticker frequency is zero" + ); +#else frequency = 1000000; +#endif // MBED_TRAP_ERRORS_ENABLED } uint8_t frequency_shifts = 0; @@ -56,8 +66,17 @@ static void initialize(const ticker_data_t *ticker) uint32_t bits = info->bits; if ((info->bits > 32) || (info->bits < 4)) { - MBED_ASSERT(0); +#if MBED_TRAP_ERRORS_ENABLED + MBED_ERROR( + MBED_MAKE_ERROR( + MBED_MODULE_HAL, + MBED_ERROR_CODE_INVALID_SIZE + ), + "Ticker number of bit is greater than 32 or less than 4 bits" + ); +#else bits = 32; +#endif // MBED_TRAP_ERRORS_ENABLED } uint32_t max_delta = 0x7 << (bits - 4); // 7/16th uint64_t max_delta_us = From 477f5636e2df1602a5829ece30d07bf3663e1e76 Mon Sep 17 00:00:00 2001 From: Kyle Kearney Date: Mon, 23 Sep 2019 14:25:25 -0700 Subject: [PATCH 134/227] Explicitly set tdb internal flash size for PSOC6 The default computation assumes that a flash sector is several times larger than a flash page. On PSoC 6 targets this is not the case (the two values are the same) so the computed size is too small. This is a similar change to 1b1f14d36b398831a3ae984db22c0c772b2e951a, but for devices which implement TDB in internal storage. --- features/storage/kvstore/conf/tdb_internal/mbed_lib.json | 3 +++ 1 file changed, 3 insertions(+) diff --git a/features/storage/kvstore/conf/tdb_internal/mbed_lib.json b/features/storage/kvstore/conf/tdb_internal/mbed_lib.json index 4ca583bcb8f..04e1f102edb 100644 --- a/features/storage/kvstore/conf/tdb_internal/mbed_lib.json +++ b/features/storage/kvstore/conf/tdb_internal/mbed_lib.json @@ -22,6 +22,9 @@ "FVP_MPS2": { "internal_size": "0x200000", "internal_base_address": "0x00200000" + }, + "MCU_PSOC6": { + "internal_size": "7168" } } } From 1d695010124ac345b7fb5f374cf13a3e73a27b75 Mon Sep 17 00:00:00 2001 From: Balaji Date: Wed, 18 Sep 2019 14:08:35 -0700 Subject: [PATCH 135/227] TCP Packet loss when TCP Receive mailbox is full. --- features/lwipstack/lwip-sys/arch/sys_arch.h | 2 +- features/lwipstack/lwipopts.h | 5 +++-- features/lwipstack/mbed_lib.json | 16 ++++++++++++++++ 3 files changed, 20 insertions(+), 3 deletions(-) diff --git a/features/lwipstack/lwip-sys/arch/sys_arch.h b/features/lwipstack/lwip-sys/arch/sys_arch.h index 6a968db966c..728da3ca9a6 100644 --- a/features/lwipstack/lwip-sys/arch/sys_arch.h +++ b/features/lwipstack/lwip-sys/arch/sys_arch.h @@ -46,7 +46,7 @@ typedef struct { } sys_mutex_t; // === MAIL BOX === -#define MB_SIZE 8 +#define MB_SIZE MBED_CONF_LWIP_MBOX_SIZE typedef struct { osEventFlagsId_t id; diff --git a/features/lwipstack/lwipopts.h b/features/lwipstack/lwipopts.h index fd2a4fab137..8146459e386 100644 --- a/features/lwipstack/lwipopts.h +++ b/features/lwipstack/lwipopts.h @@ -93,8 +93,9 @@ #define LWIP_RAW 0 #endif -#define TCPIP_MBOX_SIZE 8 -#define DEFAULT_TCP_RECVMBOX_SIZE 8 +#define MEMP_NUM_TCPIP_MSG_INPKT MBED_CONF_LWIP_MEMP_NUM_TCPIP_MSG_INPKT +#define TCPIP_MBOX_SIZE MBED_CONF_LWIP_TCPIP_MBOX_SIZE +#define DEFAULT_TCP_RECVMBOX_SIZE MBED_CONF_LWIP_DEFAULT_TCP_RECVMBOX_SIZE #define DEFAULT_UDP_RECVMBOX_SIZE 8 #define DEFAULT_RAW_RECVMBOX_SIZE 8 #define DEFAULT_ACCEPTMBOX_SIZE 8 diff --git a/features/lwipstack/mbed_lib.json b/features/lwipstack/mbed_lib.json index 5db1c5fc1be..402b5cac4f2 100644 --- a/features/lwipstack/mbed_lib.json +++ b/features/lwipstack/mbed_lib.json @@ -77,10 +77,26 @@ "help": "Number of simultaneously queued TCP segments. Current default (used if null here) is set to 16 in opt.h, unless overridden by target Ethernet drivers.", "value": null }, + "memp-num-tcpip-msg-inpkt": { + "help": "Number of simultaneously queued TCP messages that are received", + "value": 8 + }, "tcp-mss": { "help": "TCP Maximum segment size. Current default (used if null here) is set to 536 in opt.h, unless overridden by target Ethernet drivers.", "value": null }, + "tcpip-mbox-size": { + "help": "TCPIP mailbox size", + "value": 8 + }, + "default-tcp-recvmbox-size": { + "help": "Default TCPIP receive mailbox size", + "value": 8 + }, + "mbox-size": { + "help": "mailbox size", + "value": 8 + }, "tcp-snd-buf": { "help": "TCP sender buffer space (bytes). Current default (used if null here) is set to (2 * TCP_MSS) in opt.h, unless overridden by target Ethernet drivers.", "value": null From d932a4f6e0e158e364df441723285a64e4262e49 Mon Sep 17 00:00:00 2001 From: Juhani Puurula Date: Thu, 26 Sep 2019 12:14:56 +0300 Subject: [PATCH 136/227] Speed up unit test build with parallel jobs --- UNITTESTS/unit_test/test.py | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/UNITTESTS/unit_test/test.py b/UNITTESTS/unit_test/test.py index dbf515e4e0a..5df0fd1c5ef 100644 --- a/UNITTESTS/unit_test/test.py +++ b/UNITTESTS/unit_test/test.py @@ -21,6 +21,7 @@ import os import logging import sys +import psutil from shutil import copy from .utils import execute_program @@ -106,6 +107,11 @@ def build_tests(self): args = [self.make_program] + # Speed up compilation by running on more than one core + count = psutil.cpu_count() + args.append("-j{}".format(count+1)) + args.append("-l{}".format(count)) + if logging.getLogger().getEffectiveLevel() == logging.DEBUG: args.append("VERBOSE=1") From bd756ab906eb5a1b879d39855890342e65af8b7c Mon Sep 17 00:00:00 2001 From: int_szyk Date: Mon, 16 Sep 2019 13:35:28 +0200 Subject: [PATCH 137/227] Tweak equeue chain tests Changed the order of destroying queues because it is needed to destroy queues in specified order when they are chained. --- TESTS/events/equeue/main.cpp | 2 +- UNITTESTS/events/equeue/test_equeue.cpp | 2 +- events/source/tests/tests.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/TESTS/events/equeue/main.cpp b/TESTS/events/equeue/main.cpp index 98288859fbf..17edc3cc364 100644 --- a/TESTS/events/equeue/main.cpp +++ b/TESTS/events/equeue/main.cpp @@ -742,8 +742,8 @@ static void test_equeue_chain() TEST_ASSERT_EQUAL_UINT8(3, touched1); TEST_ASSERT_EQUAL_UINT8(3, touched2); - equeue_destroy(&q1); equeue_destroy(&q2); + equeue_destroy(&q1); } /** Test that unchaining equeues makes them work on their own. diff --git a/UNITTESTS/events/equeue/test_equeue.cpp b/UNITTESTS/events/equeue/test_equeue.cpp index cb93134b281..33eccca8155 100644 --- a/UNITTESTS/events/equeue/test_equeue.cpp +++ b/UNITTESTS/events/equeue/test_equeue.cpp @@ -765,8 +765,8 @@ TEST_F(TestEqueue, test_equeue_chain) EXPECT_EQ(3, touched1); EXPECT_EQ(3, touched2); - equeue_destroy(&q1); equeue_destroy(&q2); + equeue_destroy(&q1); } /** Test that unchaining equeues makes them work on their own. diff --git a/events/source/tests/tests.c b/events/source/tests/tests.c index d5c8e131008..6c4c22b6724 100644 --- a/events/source/tests/tests.c +++ b/events/source/tests/tests.c @@ -606,8 +606,8 @@ void chain_test(void) test_assert(touched == 6); - equeue_destroy(&q1); equeue_destroy(&q2); + equeue_destroy(&q1); } void unchain_test(void) From 0b272137854126859f82f22075d30f5f0eb76578 Mon Sep 17 00:00:00 2001 From: int_szyk Date: Mon, 16 Sep 2019 14:21:52 +0200 Subject: [PATCH 138/227] Expand documentation of equeue --- events/equeue.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/events/equeue.h b/events/equeue.h index 7c3dfbea54b..5d452fc5040 100644 --- a/events/equeue.h +++ b/events/equeue.h @@ -93,6 +93,9 @@ typedef struct equeue { // // If the event queue creation fails, equeue_create returns a negative, // platform-specific error code. +// +// If queues are chained, it is needed to unchain them first, before calling destroy, +// or call the destroy function on queues in order that chained queues are destroyed first. int equeue_create(equeue_t *queue, size_t size); int equeue_create_inplace(equeue_t *queue, size_t size, void *buffer); void equeue_destroy(equeue_t *queue); From 7aeb5c97dd7a21b80baee872e113629dabf18949 Mon Sep 17 00:00:00 2001 From: Filip Jagodzinski Date: Tue, 10 Sep 2019 17:37:13 +0200 Subject: [PATCH 139/227] Tests: USB: Use libusb0 backend on Windows libusb0 supports all features used for testing. A newer version (libusb1) does not have a complete implementation for Windows. --- TESTS/host_tests/pyusb_basic.py | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/TESTS/host_tests/pyusb_basic.py b/TESTS/host_tests/pyusb_basic.py index 2f39678fe29..54ecc265e4a 100644 --- a/TESTS/host_tests/pyusb_basic.py +++ b/TESTS/host_tests/pyusb_basic.py @@ -38,6 +38,14 @@ import struct +if sys.platform.startswith('win'): + # Use libusb0 on Windows. libusb1 implementation for Windows + # does not support all features necessary for testing. + import usb.backend.libusb0 + USB_BACKEND = usb.backend.libusb0.get_backend() +else: + # Use a default backend on other platforms. + USB_BACKEND = None def get_interface(dev, interface, alternate=0): intf = None @@ -314,11 +322,10 @@ def _callback_reset_support(self, key, value, timestamp): def find_device(self, serial_number): # to make it more reliable, 20 retries in 2[s] for _ in range(20): - dev = usb.core.find(custom_match=TestMatch(serial_number)) + dev = usb.core.find(custom_match=TestMatch(serial_number), backend=USB_BACKEND) if dev is not None: break time.sleep(0.1) - if dev is None: self.log("Device not found") self.send_kv("failed", "0") From 2c2a91ce877bccefa5838ff1d907bcc028e9208c Mon Sep 17 00:00:00 2001 From: Filip Jagodzinski Date: Wed, 11 Sep 2019 10:52:44 +0200 Subject: [PATCH 140/227] Tests: USBHID: Use libusb0 backend on Windows libusb0 supports all features used for testing. A newer version (libusb1) does not have a complete implementation for Windows. --- TESTS/host_tests/usb_device_hid.py | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/TESTS/host_tests/usb_device_hid.py b/TESTS/host_tests/usb_device_hid.py index 9a1c0f7142b..415718f6307 100644 --- a/TESTS/host_tests/usb_device_hid.py +++ b/TESTS/host_tests/usb_device_hid.py @@ -19,6 +19,7 @@ import time import threading import uuid +import sys import mbed_host_tests import usb.core from usb.util import ( @@ -31,6 +32,15 @@ DESC_TYPE_CONFIG, build_request_type) +if sys.platform.startswith('win'): + # Use libusb0 on Windows. libusb1 implementation for Windows + # does not support all features necessary for testing. + import usb.backend.libusb0 + USB_BACKEND = usb.backend.libusb0.get_backend() +else: + # Use a default backend on other platforms. + USB_BACKEND = None + try: import hid except ImportError: @@ -232,7 +242,7 @@ def get_usb_dev(usb_id_str): during test suite setup. Raises RuntimeError if the device is not found. """ - usb_dev = usb.core.find(custom_match=lambda d: d.serial_number == usb_id_str) + usb_dev = usb.core.find(custom_match=lambda d: d.serial_number == usb_id_str, backend=USB_BACKEND) if usb_dev is None: err_msg = 'USB device (SN={}) not found.' raise RuntimeError(err_msg.format(usb_id_str)) From a19d3693faaa47e21e2e200f21bfe3eb5c66c275 Mon Sep 17 00:00:00 2001 From: int_szyk Date: Fri, 13 Sep 2019 13:29:56 +0200 Subject: [PATCH 141/227] Change reset_reason timeout. Changed mbed_drivers-reset_reason and mbed_hal-reset_reason tests because sometimes for some devices it was a little bit to short. --- TESTS/mbed_drivers/reset_reason/main.cpp | 2 +- TESTS/mbed_hal/reset_reason/main.cpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/TESTS/mbed_drivers/reset_reason/main.cpp b/TESTS/mbed_drivers/reset_reason/main.cpp index f9c59d70958..f12a5a50fc0 100644 --- a/TESTS/mbed_drivers/reset_reason/main.cpp +++ b/TESTS/mbed_drivers/reset_reason/main.cpp @@ -137,7 +137,7 @@ void test_reset_reason() int main() { - GREENTEA_SETUP(60, "reset_reason"); + GREENTEA_SETUP(90, "reset_reason"); test_reset_reason(); // The result of this test suite is reported by the host side. GREENTEA_TESTSUITE_RESULT(0); // Fail on any error. } diff --git a/TESTS/mbed_hal/reset_reason/main.cpp b/TESTS/mbed_hal/reset_reason/main.cpp index 99f5d7ace12..b97b9074091 100644 --- a/TESTS/mbed_hal/reset_reason/main.cpp +++ b/TESTS/mbed_hal/reset_reason/main.cpp @@ -144,7 +144,7 @@ void test_reset_reason() int main() { - GREENTEA_SETUP(60, "reset_reason"); + GREENTEA_SETUP(90, "reset_reason"); test_reset_reason(); // The result of this test suite is reported by the host side. GREENTEA_TESTSUITE_RESULT(0); // Fail on any error. } From c62c7135f9a6432c46fbf6164e03dcf9b58ae6ae Mon Sep 17 00:00:00 2001 From: Ryan Morse Date: Thu, 26 Sep 2019 13:40:33 -0700 Subject: [PATCH 142/227] Moved TriggerMux initialization out of the HAL and into the BSP since that is what dictates what trigger muxes actually need to be used --- .../SDIO_HOST/SDIO_HOST.c | 1 + .../SDIO_HOST/SDIO_HOST_cfg.c | 14 ++++++++++++++ .../SDIO_HOST/SDIO_HOST_cfg.h | 2 ++ .../TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST.c | 1 + .../SDIO_HOST/SDIO_HOST_cfg.c | 14 ++++++++++++++ .../SDIO_HOST/SDIO_HOST_cfg.h | 2 ++ .../TARGET_PSOC6/psoc6csp/hal/src/cyhal_udb_sdio.c | 11 ----------- 7 files changed, 34 insertions(+), 11 deletions(-) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.c index dac8480d91f..6ccc0e7252e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.c @@ -141,6 +141,7 @@ void SDIO_Init(stc_sdio_irq_cb_t* pfuCb) if ( !udb_initialized ) { udb_initialized = 1; + SDIO_Host_Config_TriggerMuxes(); SDIO_Host_Config_UDBs(); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.c index 09799c3e9a3..94e533da700 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.c @@ -969,6 +969,20 @@ static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { {(void CYFAR *)(CYDEV_UDB_DSI11_BASE), BS_UDB_DSI11_VAL, 124u}, }; +void SDIO_Host_Config_TriggerMuxes(void) +{ + /* Connect UDB to DMA */ + Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT1, TRIG0_OUT_CPUSS_DW0_TR_IN1, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT4, TRIG0_OUT_CPUSS_DW0_TR_IN0, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT0, TRIG1_OUT_CPUSS_DW1_TR_IN1, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT5, TRIG1_OUT_CPUSS_DW1_TR_IN3, false, TRIGGER_TYPE_LEVEL); + + Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB0, TRIG14_OUT_TR_GROUP1_INPUT43, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB1, TRIG14_OUT_TR_GROUP0_INPUT44, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB3, TRIG14_OUT_TR_GROUP0_INPUT47, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB7, TRIG14_OUT_TR_GROUP1_INPUT48, false, TRIGGER_TYPE_LEVEL); +} + void SDIO_Host_Config_UDBs(void) { size_t i; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.h index baf79ccfa32..bed87f55bf0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.h @@ -892,6 +892,8 @@ extern cy_stc_dma_descriptor_t SDIO_HOST_Write_DMA_Write_DMA_Desc; /* The peripheral clock divider type */ #define SDIO_HOST_Internal_Clock_DIV_TYPE ((cy_en_divider_types_t)CY_SYSCLK_DIV_8_BIT) +/*Function for configuring TriggerMuxes*/ +void SDIO_Host_Config_TriggerMuxes(void); /*Function for configuring UDBs*/ void SDIO_Host_Config_UDBs(void); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST.c index dac8480d91f..6ccc0e7252e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST.c @@ -141,6 +141,7 @@ void SDIO_Init(stc_sdio_irq_cb_t* pfuCb) if ( !udb_initialized ) { udb_initialized = 1; + SDIO_Host_Config_TriggerMuxes(); SDIO_Host_Config_UDBs(); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST_cfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST_cfg.c index 09799c3e9a3..94e533da700 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST_cfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST_cfg.c @@ -969,6 +969,20 @@ static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { {(void CYFAR *)(CYDEV_UDB_DSI11_BASE), BS_UDB_DSI11_VAL, 124u}, }; +void SDIO_Host_Config_TriggerMuxes(void) +{ + /* Connect UDB to DMA */ + Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT1, TRIG0_OUT_CPUSS_DW0_TR_IN1, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT4, TRIG0_OUT_CPUSS_DW0_TR_IN0, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT0, TRIG1_OUT_CPUSS_DW1_TR_IN1, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT5, TRIG1_OUT_CPUSS_DW1_TR_IN3, false, TRIGGER_TYPE_LEVEL); + + Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB0, TRIG14_OUT_TR_GROUP1_INPUT43, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB1, TRIG14_OUT_TR_GROUP0_INPUT44, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB3, TRIG14_OUT_TR_GROUP0_INPUT47, false, TRIGGER_TYPE_LEVEL); + Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB7, TRIG14_OUT_TR_GROUP1_INPUT48, false, TRIGGER_TYPE_LEVEL); +} + void SDIO_Host_Config_UDBs(void) { size_t i; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST_cfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST_cfg.h index baf79ccfa32..bed87f55bf0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST_cfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST_cfg.h @@ -892,6 +892,8 @@ extern cy_stc_dma_descriptor_t SDIO_HOST_Write_DMA_Write_DMA_Desc; /* The peripheral clock divider type */ #define SDIO_HOST_Internal_Clock_DIV_TYPE ((cy_en_divider_types_t)CY_SYSCLK_DIV_8_BIT) +/*Function for configuring TriggerMuxes*/ +void SDIO_Host_Config_TriggerMuxes(void); /*Function for configuring UDBs*/ void SDIO_Host_Config_UDBs(void); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_udb_sdio.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_udb_sdio.c index f199cd1a834..5725c0c913b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_udb_sdio.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_udb_sdio.c @@ -462,17 +462,6 @@ cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk, Cy_SysInt_Init(&irqDma1_3, &SDIO_READ_DMA_IRQ); NVIC_EnableIRQ(cpuss_interrupts_dw1_3_IRQn); - /* Connect UDB to DMA */ - Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT1, TRIG0_OUT_CPUSS_DW0_TR_IN1, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT4, TRIG0_OUT_CPUSS_DW0_TR_IN0, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT0, TRIG1_OUT_CPUSS_DW1_TR_IN1, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT5, TRIG1_OUT_CPUSS_DW1_TR_IN3, false, TRIGGER_TYPE_LEVEL); - - Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB0, TRIG14_OUT_TR_GROUP1_INPUT43, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB1, TRIG14_OUT_TR_GROUP0_INPUT44, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB3, TRIG14_OUT_TR_GROUP0_INPUT47, false, TRIGGER_TYPE_LEVEL); - Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB7, TRIG14_OUT_TR_GROUP1_INPUT48, false, TRIGGER_TYPE_LEVEL); - stc_sdio_irq_cb_t irq_cbs; irq_cbs.pfnCardIntCb = cyhal_sdio_interrupts_dispatcher_IRQHandler; From b2e0a13730e903b6b9e2ceea584c202325fa86b1 Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Fri, 27 Sep 2019 10:41:43 +0200 Subject: [PATCH 143/227] STM32H7 ST CUBE V1.5.0 update --- .../TARGET_STM32H743xI/device/stm32h743xx.h | 208 +-- .../device/system_stm32h7xx.c | 76 +- .../TARGET_STM32H747xI/device/stm32h747xx.h | 244 +-- .../TARGET_STM32H7/device/stm32_hal_legacy.h | 147 +- .../TARGET_STM32H7/device/stm32h7xx.h | 4 +- .../TARGET_STM32H7/device/stm32h7xx_hal.c | 55 +- .../TARGET_STM32H7/device/stm32h7xx_hal.h | 40 + .../TARGET_STM32H7/device/stm32h7xx_hal_adc.c | 1490 +++++++++-------- .../TARGET_STM32H7/device/stm32h7xx_hal_adc.h | 232 ++- .../device/stm32h7xx_hal_adc_ex.c | 1105 ++++++------ .../device/stm32h7xx_hal_adc_ex.h | 218 +-- .../device/stm32h7xx_hal_conf.h | 12 +- .../device/stm32h7xx_hal_cryp.c | 149 +- .../device/stm32h7xx_hal_cryp_ex.c | 8 + .../device/stm32h7xx_hal_flash.c | 13 +- .../device/stm32h7xx_hal_flash.h | 4 +- .../device/stm32h7xx_hal_flash_ex.c | 3 +- .../device/stm32h7xx_hal_flash_ex.h | 15 +- .../device/stm32h7xx_hal_gpio.c | 9 +- .../TARGET_STM32H7/device/stm32h7xx_hal_hcd.c | 32 +- .../device/stm32h7xx_hal_hrtim.c | 29 +- .../device/stm32h7xx_hal_hrtim.h | 234 +-- .../device/stm32h7xx_hal_hsem.c | 4 + .../device/stm32h7xx_hal_irda.c | 115 +- .../device/stm32h7xx_hal_irda.h | 56 +- .../device/stm32h7xx_hal_irda_ex.h | 393 ++++- .../device/stm32h7xx_hal_iwdg.c | 24 +- .../device/stm32h7xx_hal_lptim.c | 496 +++++- .../device/stm32h7xx_hal_lptim.h | 11 +- .../TARGET_STM32H7/device/stm32h7xx_hal_mmc.c | 584 +++++-- .../TARGET_STM32H7/device/stm32h7xx_hal_mmc.h | 48 +- .../TARGET_STM32H7/device/stm32h7xx_hal_pcd.c | 10 +- .../device/stm32h7xx_hal_ramecc.c | 4 +- .../device/stm32h7xx_hal_ramecc.h | 2 +- .../TARGET_STM32H7/device/stm32h7xx_hal_rcc.c | 4 +- .../device/stm32h7xx_hal_rcc_ex.c | 27 + .../TARGET_STM32H7/device/stm32h7xx_hal_sd.c | 623 ++++--- .../TARGET_STM32H7/device/stm32h7xx_hal_sd.h | 87 +- .../device/stm32h7xx_hal_sd_ex.c | 3 +- .../device/stm32h7xx_hal_sd_ex.h | 6 +- .../device/stm32h7xx_hal_smartcard.c | 128 +- .../device/stm32h7xx_hal_smartcard.h | 244 ++- .../device/stm32h7xx_hal_smartcard_ex.c | 19 +- .../device/stm32h7xx_hal_smartcard_ex.h | 30 +- .../TARGET_STM32H7/device/stm32h7xx_hal_tim.c | 4 + .../TARGET_STM32H7/device/stm32h7xx_hal_tim.h | 85 +- .../device/stm32h7xx_hal_tim_ex.c | 32 +- .../device/stm32h7xx_hal_tim_ex.h | 37 +- .../device/stm32h7xx_hal_uart.c | 295 ++-- .../device/stm32h7xx_hal_uart.h | 78 +- .../device/stm32h7xx_hal_uart_ex.c | 8 +- .../device/stm32h7xx_hal_uart_ex.h | 390 ++++- .../device/stm32h7xx_hal_usart.c | 121 +- .../device/stm32h7xx_hal_usart.h | 177 +- .../device/stm32h7xx_hal_usart_ex.c | 6 + .../device/stm32h7xx_hal_usart_ex.h | 64 +- .../TARGET_STM32H7/device/stm32h7xx_ll_adc.c | 210 +-- .../TARGET_STM32H7/device/stm32h7xx_ll_adc.h | 165 +- .../TARGET_STM32H7/device/stm32h7xx_ll_gpio.h | 1 + .../device/stm32h7xx_ll_hrtim.c | 2 +- .../device/stm32h7xx_ll_hrtim.h | 952 ++++------- .../TARGET_STM32H7/device/stm32h7xx_ll_hsem.h | 16 + .../device/stm32h7xx_ll_lptim.c | 21 +- .../device/stm32h7xx_ll_lptim.h | 5 +- .../device/stm32h7xx_ll_lpuart.c | 48 +- .../device/stm32h7xx_ll_lpuart.h | 16 +- .../TARGET_STM32H7/device/stm32h7xx_ll_rcc.h | 26 +- .../device/stm32h7xx_ll_sdmmc.c | 22 +- .../device/stm32h7xx_ll_sdmmc.h | 183 +- .../TARGET_STM32H7/device/stm32h7xx_ll_spi.c | 2 +- .../device/stm32h7xx_ll_system.h | 63 + .../TARGET_STM32H7/device/stm32h7xx_ll_tim.c | 4 +- .../TARGET_STM32H7/device/stm32h7xx_ll_tim.h | 166 +- .../device/stm32h7xx_ll_usart.c | 106 +- .../device/stm32h7xx_ll_usart.h | 73 +- .../TARGET_STM32H7/device/stm32h7xx_ll_usb.c | 13 +- 76 files changed, 6468 insertions(+), 4168 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/device/stm32h743xx.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/device/stm32h743xx.h index acb04e85b29..383f514a49b 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/device/stm32h743xx.h +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/device/stm32h743xx.h @@ -298,6 +298,7 @@ __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode A } ADC_Common_TypeDef; + /** * @brief VREFBUF */ @@ -734,7 +735,7 @@ typedef struct uint32_t RESERVED15[14]; __IO uint32_t MMCTSCGPR; __IO uint32_t MMCTMCGPR; - int32_t RESERVED16[5]; + uint32_t RESERVED16[5]; __IO uint32_t MMCTPCGR; uint32_t RESERVED17[10]; __IO uint32_t MMCRCRCEPR; @@ -2033,7 +2034,6 @@ typedef struct #define ADC1_BASE (D2_AHB1PERIPH_BASE + 0x2000UL) #define ADC2_BASE (D2_AHB1PERIPH_BASE + 0x2100UL) #define ADC12_COMMON_BASE (D2_AHB1PERIPH_BASE + 0x2300UL) -#define ART_BASE (D2_AHB1PERIPH_BASE + 0x4400UL) #define ETH_BASE (D2_AHB1PERIPH_BASE + 0x8000UL) #define ETH_MAC_BASE (ETH_BASE) @@ -2382,7 +2382,6 @@ typedef struct #define EXTI ((EXTI_TypeDef *) EXTI_BASE) #define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE) #define EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE) -#define SDMMC ((SDMMC_TypeDef *) SDMMC_BASE) #define TIM1 ((TIM_TypeDef *) TIM1_BASE) #define SPI1 ((SPI_TypeDef *) SPI1_BASE) #define TIM8 ((TIM_TypeDef *) TIM8_BASE) @@ -2392,11 +2391,11 @@ typedef struct #define TIM16 ((TIM_TypeDef *) TIM16_BASE) #define TIM17 ((TIM_TypeDef *) TIM17_BASE) #define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE) -#define HRTIM1_TIMA ((HRTIM_TIM_TypeDef *) HRTIM1_TIMA_BASE) -#define HRTIM1_TIMB ((HRTIM_TIM_TypeDef *) HRTIM1_TIMB_BASE) -#define HRTIM1_TIMC ((HRTIM_TIM_TypeDef *) HRTIM1_TIMC_BASE) -#define HRTIM1_TIMD ((HRTIM_TIM_TypeDef *) HRTIM1_TIMD_BASE) -#define HRTIM1_TIME ((HRTIM_TIM_TypeDef *) HRTIM1_TIME_BASE) +#define HRTIM1_TIMA ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE) +#define HRTIM1_TIMB ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE) +#define HRTIM1_TIMC ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE) +#define HRTIM1_TIMD ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE) +#define HRTIM1_TIME ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE) #define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE) #define SAI1 ((SAI_TypeDef *) SAI1_BASE) #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) @@ -3890,6 +3889,7 @@ typedef struct #define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ #define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */ + /******************************************************************************/ /* */ /* VREFBUF */ @@ -10513,7 +10513,7 @@ typedef struct /******************* Bits definition for FLASH_ACR register **********************/ #define FLASH_ACR_LATENCY_Pos (0U) #define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ -#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */ #define FLASH_ACR_LATENCY_0WS (0x00000000UL) #define FLASH_ACR_LATENCY_1WS (0x00000001UL) #define FLASH_ACR_LATENCY_2WS (0x00000002UL) @@ -10532,318 +10532,318 @@ typedef struct #define FLASH_ACR_LATENCY_15WS (0x0000000FUL) #define FLASH_ACR_WRHIGHFREQ_Pos (4U) #define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ -#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ #define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ #define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ /******************* Bits definition for FLASH_CR register ***********************/ #define FLASH_CR_LOCK_Pos (0U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ -#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Configuration lock bit */ #define FLASH_CR_PG_Pos (1U) #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000002 */ -#define FLASH_CR_PG FLASH_CR_PG_Msk +#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Internal buffer control bit */ #define FLASH_CR_SER_Pos (2U) #define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000004 */ -#define FLASH_CR_SER FLASH_CR_SER_Msk +#define FLASH_CR_SER FLASH_CR_SER_Msk /*!< Sector erase request */ #define FLASH_CR_BER_Pos (3U) #define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) /*!< 0x00000008 */ -#define FLASH_CR_BER FLASH_CR_BER_Msk +#define FLASH_CR_BER FLASH_CR_BER_Msk /*!< Bank erase request */ #define FLASH_CR_PSIZE_Pos (4U) #define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000030 */ -#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk +#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk /*!< Program size */ #define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000010 */ #define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000020 */ #define FLASH_CR_FW_Pos (6U) #define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) /*!< 0x00000040 */ -#define FLASH_CR_FW FLASH_CR_FW_Msk +#define FLASH_CR_FW FLASH_CR_FW_Msk /*!< Write forcing control bit */ #define FLASH_CR_START_Pos (7U) #define FLASH_CR_START_Msk (0x1UL << FLASH_CR_START_Pos) /*!< 0x00000080 */ -#define FLASH_CR_START FLASH_CR_START_Msk +#define FLASH_CR_START FLASH_CR_START_Msk /*!< Erase start control bit */ #define FLASH_CR_SNB_Pos (8U) #define FLASH_CR_SNB_Msk (0x7UL << FLASH_CR_SNB_Pos) /*!< 0x00000700 */ -#define FLASH_CR_SNB FLASH_CR_SNB_Msk -#define FLASH_CR_SNB_0 (0x1UL << FLASH_CR_SNB_Pos) /*!< 0x00000100 */ -#define FLASH_CR_SNB_1 (0x2UL << FLASH_CR_SNB_Pos) /*!< 0x00000200 */ -#define FLASH_CR_SNB_2 (0x4UL << FLASH_CR_SNB_Pos) /*!< 0x00000400 */ +#define FLASH_CR_SNB FLASH_CR_SNB_Msk /*!< Sector erase selection number */ +#define FLASH_CR_SNB_0 (0x1UL << FLASH_CR_SNB_Pos) /*!< 0x00000100 */ +#define FLASH_CR_SNB_1 (0x2UL << FLASH_CR_SNB_Pos) /*!< 0x00000200 */ +#define FLASH_CR_SNB_2 (0x4UL << FLASH_CR_SNB_Pos) /*!< 0x00000400 */ #define FLASH_CR_CRC_EN_Pos (15U) #define FLASH_CR_CRC_EN_Msk (0x1UL << FLASH_CR_CRC_EN_Pos) /*!< 0x00008000 */ -#define FLASH_CR_CRC_EN FLASH_CR_CRC_EN_Msk +#define FLASH_CR_CRC_EN FLASH_CR_CRC_EN_Msk /*!< CRC control bit */ #define FLASH_CR_EOPIE_Pos (16U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00010000 */ -#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End-of-program interrupt control bit */ #define FLASH_CR_WRPERRIE_Pos (17U) #define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) /*!< 0x00020000 */ -#define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk +#define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk /*!< Write protection error interrupt enable bit */ #define FLASH_CR_PGSERRIE_Pos (18U) #define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) /*!< 0x00040000 */ -#define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk +#define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk /*!< Programming sequence error interrupt enable bit */ #define FLASH_CR_STRBERRIE_Pos (19U) #define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */ -#define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk +#define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk /*!< Strobe error interrupt enable bit */ #define FLASH_CR_INCERRIE_Pos (21U) #define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) /*!< 0x00200000 */ -#define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk +#define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk /*!< Inconsistency error interrupt enable bit */ #define FLASH_CR_OPERRIE_Pos (22U) #define FLASH_CR_OPERRIE_Msk (0x1UL << FLASH_CR_OPERRIE_Pos) /*!< 0x00400000 */ -#define FLASH_CR_OPERRIE FLASH_CR_OPERRIE_Msk +#define FLASH_CR_OPERRIE FLASH_CR_OPERRIE_Msk /*!< Write/erase error interrupt enable bit */ #define FLASH_CR_RDPERRIE_Pos (23U) #define FLASH_CR_RDPERRIE_Msk (0x1UL << FLASH_CR_RDPERRIE_Pos) /*!< 0x00800000 */ -#define FLASH_CR_RDPERRIE FLASH_CR_RDPERRIE_Msk +#define FLASH_CR_RDPERRIE FLASH_CR_RDPERRIE_Msk /*!< Read protection error interrupt enable bit */ #define FLASH_CR_RDSERRIE_Pos (24U) #define FLASH_CR_RDSERRIE_Msk (0x1UL << FLASH_CR_RDSERRIE_Pos) /*!< 0x01000000 */ -#define FLASH_CR_RDSERRIE FLASH_CR_RDSERRIE_Msk +#define FLASH_CR_RDSERRIE FLASH_CR_RDSERRIE_Msk /*!< Secure error interrupt enable bit */ #define FLASH_CR_SNECCERRIE_Pos (25U) #define FLASH_CR_SNECCERRIE_Msk (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */ -#define FLASH_CR_SNECCERRIE FLASH_CR_SNECCERRIE_Msk +#define FLASH_CR_SNECCERRIE FLASH_CR_SNECCERRIE_Msk /*!< ECC single correction error interrupt enable bit */ #define FLASH_CR_DBECCERRIE_Pos (26U) #define FLASH_CR_DBECCERRIE_Msk (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */ -#define FLASH_CR_DBECCERRIE FLASH_CR_DBECCERRIE_Msk +#define FLASH_CR_DBECCERRIE FLASH_CR_DBECCERRIE_Msk /*!< ECC double detection error interrupt enable bit */ #define FLASH_CR_CRCENDIE_Pos (27U) #define FLASH_CR_CRCENDIE_Msk (0x1UL << FLASH_CR_CRCENDIE_Pos) /*!< 0x08000000 */ -#define FLASH_CR_CRCENDIE FLASH_CR_CRCENDIE_Msk +#define FLASH_CR_CRCENDIE FLASH_CR_CRCENDIE_Msk /*!< CRC end of calculation interrupt enable bit */ #define FLASH_CR_CRCRDERRIE_Pos (28U) #define FLASH_CR_CRCRDERRIE_Msk (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */ -#define FLASH_CR_CRCRDERRIE FLASH_CR_CRCRDERRIE_Msk +#define FLASH_CR_CRCRDERRIE FLASH_CR_CRCRDERRIE_Msk /*!< CRC read error interrupt enable bit */ /******************* Bits definition for FLASH_SR register ***********************/ #define FLASH_SR_BSY_Pos (0U) #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ -#define FLASH_SR_BSY FLASH_SR_BSY_Msk +#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy flag */ #define FLASH_SR_WBNE_Pos (1U) #define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) /*!< 0x00000002 */ -#define FLASH_SR_WBNE FLASH_SR_WBNE_Msk +#define FLASH_SR_WBNE FLASH_SR_WBNE_Msk /*!< Write buffer not empty flag */ #define FLASH_SR_QW_Pos (2U) #define FLASH_SR_QW_Msk (0x1UL << FLASH_SR_QW_Pos) /*!< 0x00000004 */ -#define FLASH_SR_QW FLASH_SR_QW_Msk +#define FLASH_SR_QW FLASH_SR_QW_Msk /*!< Wait queue flag */ #define FLASH_SR_CRC_BUSY_Pos (3U) #define FLASH_SR_CRC_BUSY_Msk (0x1UL << FLASH_SR_CRC_BUSY_Pos) /*!< 0x00000008 */ -#define FLASH_SR_CRC_BUSY FLASH_SR_CRC_BUSY_Msk +#define FLASH_SR_CRC_BUSY FLASH_SR_CRC_BUSY_Msk /*!< CRC busy flag */ #define FLASH_SR_EOP_Pos (16U) #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00010000 */ -#define FLASH_SR_EOP FLASH_SR_EOP_Msk +#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End-of-program flag */ #define FLASH_SR_WRPERR_Pos (17U) #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00020000 */ -#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error flag */ #define FLASH_SR_PGSERR_Pos (18U) #define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00040000 */ -#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< Programming sequence error flag */ #define FLASH_SR_STRBERR_Pos (19U) #define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) /*!< 0x00080000 */ -#define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk +#define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk /*!< Strobe error flag */ #define FLASH_SR_INCERR_Pos (21U) #define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) /*!< 0x00200000 */ -#define FLASH_SR_INCERR FLASH_SR_INCERR_Msk +#define FLASH_SR_INCERR FLASH_SR_INCERR_Msk /*!< Inconsistency error flag */ #define FLASH_SR_OPERR_Pos (22U) #define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00400000 */ -#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk +#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk /*!< Write/erase error flag */ #define FLASH_SR_RDPERR_Pos (23U) #define FLASH_SR_RDPERR_Msk (0x1UL << FLASH_SR_RDPERR_Pos) /*!< 0x00800000 */ -#define FLASH_SR_RDPERR FLASH_SR_RDPERR_Msk +#define FLASH_SR_RDPERR FLASH_SR_RDPERR_Msk /*!< Read protection error flag */ #define FLASH_SR_RDSERR_Pos (24U) #define FLASH_SR_RDSERR_Msk (0x1UL << FLASH_SR_RDSERR_Pos) /*!< 0x01000000 */ -#define FLASH_SR_RDSERR FLASH_SR_RDSERR_Msk +#define FLASH_SR_RDSERR FLASH_SR_RDSERR_Msk /*!< Secure error flag */ #define FLASH_SR_SNECCERR_Pos (25U) #define FLASH_SR_SNECCERR_Msk (0x1UL << FLASH_SR_SNECCERR_Pos) /*!< 0x02000000 */ -#define FLASH_SR_SNECCERR FLASH_SR_SNECCERR_Msk +#define FLASH_SR_SNECCERR FLASH_SR_SNECCERR_Msk /*!< Single correction error flag */ #define FLASH_SR_DBECCERR_Pos (26U) #define FLASH_SR_DBECCERR_Msk (0x1UL << FLASH_SR_DBECCERR_Pos) /*!< 0x04000000 */ -#define FLASH_SR_DBECCERR FLASH_SR_DBECCERR_Msk +#define FLASH_SR_DBECCERR FLASH_SR_DBECCERR_Msk /*!< ECC double detection error flag */ #define FLASH_SR_CRCEND_Pos (27U) #define FLASH_SR_CRCEND_Msk (0x1UL << FLASH_SR_CRCEND_Pos) /*!< 0x08000000 */ -#define FLASH_SR_CRCEND FLASH_SR_CRCEND_Msk +#define FLASH_SR_CRCEND FLASH_SR_CRCEND_Msk /*!< CRC end of calculation flag */ #define FLASH_SR_CRCRDERR_Pos (28U) #define FLASH_SR_CRCRDERR_Msk (0x1UL << FLASH_SR_CRCRDERR_Pos) /*!< 0x10000000 */ -#define FLASH_SR_CRCRDERR FLASH_SR_CRCRDERR_Msk +#define FLASH_SR_CRCRDERR FLASH_SR_CRCRDERR_Msk /*!< CRC read error flag */ /******************* Bits definition for FLASH_CCR register *******************/ #define FLASH_CCR_CLR_EOP_Pos (16U) #define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) /*!< 0x00010000 */ -#define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk +#define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk /*!< EOP flag clear bit */ #define FLASH_CCR_CLR_WRPERR_Pos (17U) #define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */ -#define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk +#define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk /*!< WRPERR flag clear bit */ #define FLASH_CCR_CLR_PGSERR_Pos (18U) #define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */ -#define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk +#define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk /*!< PGSERR flag clear bit */ #define FLASH_CCR_CLR_STRBERR_Pos (19U) #define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */ -#define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk +#define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk /*!< STRBERR flag clear bit */ #define FLASH_CCR_CLR_INCERR_Pos (21U) #define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */ -#define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk +#define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk /*!< INCERR flag clear bit */ #define FLASH_CCR_CLR_OPERR_Pos (22U) #define FLASH_CCR_CLR_OPERR_Msk (0x1UL << FLASH_CCR_CLR_OPERR_Pos) /*!< 0x00400000 */ -#define FLASH_CCR_CLR_OPERR FLASH_CCR_CLR_OPERR_Msk +#define FLASH_CCR_CLR_OPERR FLASH_CCR_CLR_OPERR_Msk /*!< OPERR flag clear bit */ #define FLASH_CCR_CLR_RDPERR_Pos (23U) #define FLASH_CCR_CLR_RDPERR_Msk (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */ -#define FLASH_CCR_CLR_RDPERR FLASH_CCR_CLR_RDPERR_Msk +#define FLASH_CCR_CLR_RDPERR FLASH_CCR_CLR_RDPERR_Msk /*!< RDPERR flag clear bit */ #define FLASH_CCR_CLR_RDSERR_Pos (24U) #define FLASH_CCR_CLR_RDSERR_Msk (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */ -#define FLASH_CCR_CLR_RDSERR FLASH_CCR_CLR_RDSERR_Msk +#define FLASH_CCR_CLR_RDSERR FLASH_CCR_CLR_RDSERR_Msk /*!< RDSERR flag clear bit */ #define FLASH_CCR_CLR_SNECCERR_Pos (25U) #define FLASH_CCR_CLR_SNECCERR_Msk (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */ -#define FLASH_CCR_CLR_SNECCERR FLASH_CCR_CLR_SNECCERR_Msk +#define FLASH_CCR_CLR_SNECCERR FLASH_CCR_CLR_SNECCERR_Msk /*!< SNECCERR flag clear bit */ #define FLASH_CCR_CLR_DBECCERR_Pos (26U) #define FLASH_CCR_CLR_DBECCERR_Msk (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */ -#define FLASH_CCR_CLR_DBECCERR FLASH_CCR_CLR_DBECCERR_Msk +#define FLASH_CCR_CLR_DBECCERR FLASH_CCR_CLR_DBECCERR_Msk /*!< DBECCERR flag clear bit */ #define FLASH_CCR_CLR_CRCEND_Pos (27U) #define FLASH_CCR_CLR_CRCEND_Msk (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */ -#define FLASH_CCR_CLR_CRCEND FLASH_CCR_CLR_CRCEND_Msk +#define FLASH_CCR_CLR_CRCEND FLASH_CCR_CLR_CRCEND_Msk /*!< CRCEND flag clear bit */ #define FLASH_CCR_CLR_CRCRDERR_Pos (28U) #define FLASH_CCR_CLR_CRCRDERR_Msk (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */ -#define FLASH_CCR_CLR_CRCRDERR FLASH_CCR_CLR_CRCRDERR_Msk +#define FLASH_CCR_CLR_CRCRDERR FLASH_CCR_CLR_CRCRDERR_Msk /*!< CRCRDERR flag clear bit */ /******************* Bits definition for FLASH_OPTCR register *******************/ #define FLASH_OPTCR_OPTLOCK_Pos (0U) #define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */ -#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk +#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk /*!< FLASH_OPTCR lock option configuration bit */ #define FLASH_OPTCR_OPTSTART_Pos (1U) #define FLASH_OPTCR_OPTSTART_Msk (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */ -#define FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk +#define FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk /*!< Option byte start change option configuration bit */ #define FLASH_OPTCR_MER_Pos (4U) #define FLASH_OPTCR_MER_Msk (0x1UL << FLASH_OPTCR_MER_Pos) /*!< 0x00000010 */ -#define FLASH_OPTCR_MER FLASH_OPTCR_MER_Msk +#define FLASH_OPTCR_MER FLASH_OPTCR_MER_Msk /*!< Mass erase request */ #define FLASH_OPTCR_OPTCHANGEERRIE_Pos (30U) #define FLASH_OPTCR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */ -#define FLASH_OPTCR_OPTCHANGEERRIE FLASH_OPTCR_OPTCHANGEERRIE_Msk +#define FLASH_OPTCR_OPTCHANGEERRIE FLASH_OPTCR_OPTCHANGEERRIE_Msk /*!< Option byte change error interrupt enable bit */ #define FLASH_OPTCR_SWAP_BANK_Pos (31U) #define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */ -#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk +#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk /*!< Bank swapping option configuration bit */ /******************* Bits definition for FLASH_OPTSR register ***************/ #define FLASH_OPTSR_OPT_BUSY_Pos (0U) #define FLASH_OPTSR_OPT_BUSY_Msk (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */ -#define FLASH_OPTSR_OPT_BUSY FLASH_OPTSR_OPT_BUSY_Msk +#define FLASH_OPTSR_OPT_BUSY FLASH_OPTSR_OPT_BUSY_Msk /*!< Option byte change ongoing flag */ #define FLASH_OPTSR_BOR_LEV_Pos (2U) #define FLASH_OPTSR_BOR_LEV_Msk (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */ -#define FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk +#define FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk /*!< Brownout level option status bit */ #define FLASH_OPTSR_BOR_LEV_0 (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */ #define FLASH_OPTSR_BOR_LEV_1 (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */ #define FLASH_OPTSR_IWDG1_SW_Pos (4U) #define FLASH_OPTSR_IWDG1_SW_Msk (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */ -#define FLASH_OPTSR_IWDG1_SW FLASH_OPTSR_IWDG1_SW_Msk +#define FLASH_OPTSR_IWDG1_SW FLASH_OPTSR_IWDG1_SW_Msk /*!< IWDG1 control mode option status bit */ #define FLASH_OPTSR_NRST_STOP_D1_Pos (6U) #define FLASH_OPTSR_NRST_STOP_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */ -#define FLASH_OPTSR_NRST_STOP_D1 FLASH_OPTSR_NRST_STOP_D1_Msk +#define FLASH_OPTSR_NRST_STOP_D1 FLASH_OPTSR_NRST_STOP_D1_Msk /*!< D1 domain DStop entry reset option status bit */ #define FLASH_OPTSR_NRST_STBY_D1_Pos (7U) #define FLASH_OPTSR_NRST_STBY_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */ -#define FLASH_OPTSR_NRST_STBY_D1 FLASH_OPTSR_NRST_STBY_D1_Msk +#define FLASH_OPTSR_NRST_STBY_D1 FLASH_OPTSR_NRST_STBY_D1_Msk /*!< D1 domain DStandby entry reset option status bit */ #define FLASH_OPTSR_RDP_Pos (8U) #define FLASH_OPTSR_RDP_Msk (0xFFUL << FLASH_OPTSR_RDP_Pos) /*!< 0x0000FF00 */ -#define FLASH_OPTSR_RDP FLASH_OPTSR_RDP_Msk +#define FLASH_OPTSR_RDP FLASH_OPTSR_RDP_Msk /*!< Readout protection level option status byte */ #define FLASH_OPTSR_FZ_IWDG_STOP_Pos (17U) #define FLASH_OPTSR_FZ_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */ -#define FLASH_OPTSR_FZ_IWDG_STOP FLASH_OPTSR_FZ_IWDG_STOP_Msk +#define FLASH_OPTSR_FZ_IWDG_STOP FLASH_OPTSR_FZ_IWDG_STOP_Msk /*!< IWDG Stop mode freeze option status bit */ #define FLASH_OPTSR_FZ_IWDG_SDBY_Pos (18U) #define FLASH_OPTSR_FZ_IWDG_SDBY_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */ -#define FLASH_OPTSR_FZ_IWDG_SDBY FLASH_OPTSR_FZ_IWDG_SDBY_Msk +#define FLASH_OPTSR_FZ_IWDG_SDBY FLASH_OPTSR_FZ_IWDG_SDBY_Msk /*!< IWDG Standby mode freeze option status bit */ #define FLASH_OPTSR_ST_RAM_SIZE_Pos (19U) #define FLASH_OPTSR_ST_RAM_SIZE_Msk (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */ -#define FLASH_OPTSR_ST_RAM_SIZE FLASH_OPTSR_ST_RAM_SIZE_Msk +#define FLASH_OPTSR_ST_RAM_SIZE FLASH_OPTSR_ST_RAM_SIZE_Msk /*!< ST RAM size option status */ #define FLASH_OPTSR_ST_RAM_SIZE_0 (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */ #define FLASH_OPTSR_ST_RAM_SIZE_1 (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */ #define FLASH_OPTSR_SECURITY_Pos (21U) #define FLASH_OPTSR_SECURITY_Msk (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */ -#define FLASH_OPTSR_SECURITY FLASH_OPTSR_SECURITY_Msk +#define FLASH_OPTSR_SECURITY FLASH_OPTSR_SECURITY_Msk /*!< Security enable option status bit */ #define FLASH_OPTSR_IO_HSLV_Pos (29U) #define FLASH_OPTSR_IO_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */ -#define FLASH_OPTSR_IO_HSLV FLASH_OPTSR_IO_HSLV_Msk +#define FLASH_OPTSR_IO_HSLV FLASH_OPTSR_IO_HSLV_Msk /*!< I/O high-speed at low-voltage status bit */ #define FLASH_OPTSR_OPTCHANGEERR_Pos (30U) #define FLASH_OPTSR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */ -#define FLASH_OPTSR_OPTCHANGEERR FLASH_OPTSR_OPTCHANGEERR_Msk +#define FLASH_OPTSR_OPTCHANGEERR FLASH_OPTSR_OPTCHANGEERR_Msk /*!< Option byte change error flag */ #define FLASH_OPTSR_SWAP_BANK_OPT_Pos (31U) #define FLASH_OPTSR_SWAP_BANK_OPT_Msk (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */ -#define FLASH_OPTSR_SWAP_BANK_OPT FLASH_OPTSR_SWAP_BANK_OPT_Msk +#define FLASH_OPTSR_SWAP_BANK_OPT FLASH_OPTSR_SWAP_BANK_OPT_Msk /*!< Bank swapping option status bit */ /******************* Bits definition for FLASH_OPTCCR register *******************/ #define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos (30U) #define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */ -#define FLASH_OPTCCR_CLR_OPTCHANGEERR FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk +#define FLASH_OPTCCR_CLR_OPTCHANGEERR FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk /*!< OPTCHANGEERR reset bit */ /******************* Bits definition for FLASH_PRAR register *********************/ #define FLASH_PRAR_PROT_AREA_START_Pos (0U) #define FLASH_PRAR_PROT_AREA_START_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */ -#define FLASH_PRAR_PROT_AREA_START FLASH_PRAR_PROT_AREA_START_Msk +#define FLASH_PRAR_PROT_AREA_START FLASH_PRAR_PROT_AREA_START_Msk /*!< PCROP area start status bits */ #define FLASH_PRAR_PROT_AREA_END_Pos (16U) #define FLASH_PRAR_PROT_AREA_END_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */ -#define FLASH_PRAR_PROT_AREA_END FLASH_PRAR_PROT_AREA_END_Msk +#define FLASH_PRAR_PROT_AREA_END FLASH_PRAR_PROT_AREA_END_Msk /*!< PCROP area end status bits */ #define FLASH_PRAR_DMEP_Pos (31U) #define FLASH_PRAR_DMEP_Msk (0x1UL << FLASH_PRAR_DMEP_Pos) /*!< 0x80000000 */ -#define FLASH_PRAR_DMEP FLASH_PRAR_DMEP_Msk +#define FLASH_PRAR_DMEP FLASH_PRAR_DMEP_Msk /*!< PCROP protected erase enable option status bit */ /******************* Bits definition for FLASH_SCAR register *********************/ #define FLASH_SCAR_SEC_AREA_START_Pos (0U) #define FLASH_SCAR_SEC_AREA_START_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */ -#define FLASH_SCAR_SEC_AREA_START FLASH_SCAR_SEC_AREA_START_Msk +#define FLASH_SCAR_SEC_AREA_START FLASH_SCAR_SEC_AREA_START_Msk /*!< Secure-only area start status bits */ #define FLASH_SCAR_SEC_AREA_END_Pos (16U) #define FLASH_SCAR_SEC_AREA_END_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */ -#define FLASH_SCAR_SEC_AREA_END FLASH_SCAR_SEC_AREA_END_Msk +#define FLASH_SCAR_SEC_AREA_END FLASH_SCAR_SEC_AREA_END_Msk /*!< Secure-only area end status bits */ #define FLASH_SCAR_DMES_Pos (31U) #define FLASH_SCAR_DMES_Msk (0x1UL << FLASH_SCAR_DMES_Pos) /*!< 0x80000000 */ -#define FLASH_SCAR_DMES FLASH_SCAR_DMES_Msk +#define FLASH_SCAR_DMES FLASH_SCAR_DMES_Msk /*!< Secure access protected erase enable option status bit */ /******************* Bits definition for FLASH_WPSN register *********************/ #define FLASH_WPSN_WRPSN_Pos (0U) #define FLASH_WPSN_WRPSN_Msk (0xFFUL << FLASH_WPSN_WRPSN_Pos) /*!< 0x000000FF */ -#define FLASH_WPSN_WRPSN FLASH_WPSN_WRPSN_Msk +#define FLASH_WPSN_WRPSN FLASH_WPSN_WRPSN_Msk /*!< Sector write protection option status byte */ /******************* Bits definition for FLASH_BOOT_CUR register ****************/ #define FLASH_BOOT_ADD0_Pos (0U) #define FLASH_BOOT_ADD0_Msk (0xFFFFUL << FLASH_BOOT_ADD0_Pos) /*!< 0x0000FFFF */ -#define FLASH_BOOT_ADD0 FLASH_BOOT_ADD0_Msk +#define FLASH_BOOT_ADD0 FLASH_BOOT_ADD0_Msk /*!< Arm Cortex-M7 boot address 0 */ #define FLASH_BOOT_ADD1_Pos (16U) #define FLASH_BOOT_ADD1_Msk (0xFFFFUL << FLASH_BOOT_ADD1_Pos) /*!< 0xFFFF0000 */ -#define FLASH_BOOT_ADD1 FLASH_BOOT_ADD1_Msk +#define FLASH_BOOT_ADD1 FLASH_BOOT_ADD1_Msk /*!< Arm Cortex-M7 boot address 1 */ /******************* Bits definition for FLASH_CRCCR register ********************/ #define FLASH_CRCCR_CRC_SECT_Pos (0U) #define FLASH_CRCCR_CRC_SECT_Msk (0x7UL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x00000007 */ -#define FLASH_CRCCR_CRC_SECT FLASH_CRCCR_CRC_SECT_Msk +#define FLASH_CRCCR_CRC_SECT FLASH_CRCCR_CRC_SECT_Msk /*!< CRC sector number */ #define FLASH_CRCCR_CRC_BY_SECT_Pos (8U) #define FLASH_CRCCR_CRC_BY_SECT_Msk (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */ -#define FLASH_CRCCR_CRC_BY_SECT FLASH_CRCCR_CRC_BY_SECT_Msk +#define FLASH_CRCCR_CRC_BY_SECT FLASH_CRCCR_CRC_BY_SECT_Msk /*!< CRC sector mode select bit */ #define FLASH_CRCCR_ADD_SECT_Pos (9U) #define FLASH_CRCCR_ADD_SECT_Msk (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */ -#define FLASH_CRCCR_ADD_SECT FLASH_CRCCR_ADD_SECT_Msk +#define FLASH_CRCCR_ADD_SECT FLASH_CRCCR_ADD_SECT_Msk /*!< CRC sector select bit */ #define FLASH_CRCCR_CLEAN_SECT_Pos (10U) #define FLASH_CRCCR_CLEAN_SECT_Msk (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */ -#define FLASH_CRCCR_CLEAN_SECT FLASH_CRCCR_CLEAN_SECT_Msk +#define FLASH_CRCCR_CLEAN_SECT FLASH_CRCCR_CLEAN_SECT_Msk /*!< CRC sector list clear bit */ #define FLASH_CRCCR_START_CRC_Pos (16U) #define FLASH_CRCCR_START_CRC_Msk (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */ -#define FLASH_CRCCR_START_CRC FLASH_CRCCR_START_CRC_Msk +#define FLASH_CRCCR_START_CRC FLASH_CRCCR_START_CRC_Msk /*!< CRC start bit */ #define FLASH_CRCCR_CLEAN_CRC_Pos (17U) #define FLASH_CRCCR_CLEAN_CRC_Msk (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */ -#define FLASH_CRCCR_CLEAN_CRC FLASH_CRCCR_CLEAN_CRC_Msk +#define FLASH_CRCCR_CLEAN_CRC FLASH_CRCCR_CLEAN_CRC_Msk /*!< CRC clear bit */ #define FLASH_CRCCR_CRC_BURST_Pos (20U) #define FLASH_CRCCR_CRC_BURST_Msk (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */ -#define FLASH_CRCCR_CRC_BURST FLASH_CRCCR_CRC_BURST_Msk +#define FLASH_CRCCR_CRC_BURST FLASH_CRCCR_CRC_BURST_Msk /*!< CRC burst size */ #define FLASH_CRCCR_CRC_BURST_0 (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */ #define FLASH_CRCCR_CRC_BURST_1 (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */ #define FLASH_CRCCR_ALL_BANK_Pos (22U) #define FLASH_CRCCR_ALL_BANK_Msk (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */ -#define FLASH_CRCCR_ALL_BANK FLASH_CRCCR_ALL_BANK_Msk +#define FLASH_CRCCR_ALL_BANK FLASH_CRCCR_ALL_BANK_Msk /*!< CRC select bit */ /******************* Bits definition for FLASH_CRCSADD register ****************/ #define FLASH_CRCSADD_CRC_START_ADDR_Pos (0U) #define FLASH_CRCSADD_CRC_START_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */ -#define FLASH_CRCSADD_CRC_START_ADDR FLASH_CRCSADD_CRC_START_ADDR_Msk +#define FLASH_CRCSADD_CRC_START_ADDR FLASH_CRCSADD_CRC_START_ADDR_Msk /*!< CRC start address */ /******************* Bits definition for FLASH_CRCEADD register ****************/ #define FLASH_CRCEADD_CRC_END_ADDR_Pos (0U) #define FLASH_CRCEADD_CRC_END_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */ -#define FLASH_CRCEADD_CRC_END_ADDR FLASH_CRCEADD_CRC_END_ADDR_Msk +#define FLASH_CRCEADD_CRC_END_ADDR FLASH_CRCEADD_CRC_END_ADDR_Msk /*!< CRC end address */ /******************* Bits definition for FLASH_CRCDATA register ***************/ #define FLASH_CRCDATA_CRC_DATA_Pos (0U) #define FLASH_CRCDATA_CRC_DATA_Msk (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */ -#define FLASH_CRCDATA_CRC_DATA FLASH_CRCDATA_CRC_DATA_Msk +#define FLASH_CRCDATA_CRC_DATA FLASH_CRCDATA_CRC_DATA_Msk /*!< CRC result */ /******************* Bits definition for FLASH_ECC_FA register *******************/ #define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos (0U) #define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk (0x7FFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x00007FFF */ -#define FLASH_ECC_FA_FAIL_ECC_ADDR FLASH_ECC_FA_FAIL_ECC_ADDR_Msk +#define FLASH_ECC_FA_FAIL_ECC_ADDR FLASH_ECC_FA_FAIL_ECC_ADDR_Msk /*!< ECC error address */ /******************************************************************************/ /* */ @@ -19090,7 +19090,9 @@ typedef struct /* TIM */ /* */ /******************************************************************************/ -#define TIM_BREAK_INPUT_SUPPORT /*!CR |= RCC_CR_HSION; - + /* Reset CFGR register */ RCC->CFGR = 0x00000000; @@ -164,7 +164,7 @@ void SystemInit (void) /* Reset D2CFGR register */ RCC->D2CFGR = 0x00000000; - + /* Reset D3CFGR register */ RCC->D3CFGR = 0x00000000; @@ -182,14 +182,14 @@ void SystemInit (void) RCC->PLL2DIVR = 0x00000000; /* Reset PLL2FRACR register */ - + RCC->PLL2FRACR = 0x00000000; /* Reset PLL3DIVR register */ RCC->PLL3DIVR = 0x00000000; /* Reset PLL3FRACR register */ RCC->PLL3FRACR = 0x00000000; - + /* Reset HSEBYP bit */ RCC->CR &= 0xFFFBFFFFU; @@ -221,7 +221,7 @@ void SystemInit (void) if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) { /* if stm32h7 revY*/ - /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ + /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ *((__IO uint32_t*)0x51008108) = 0x000000001U; } @@ -230,7 +230,7 @@ void SystemInit (void) SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM */ #else SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ // MBED PATCH for Bootloader -#endif +#endif #endif /*DUAL_CORE && CORE_CM4*/ @@ -241,33 +241,33 @@ void SystemInit (void) * The SystemCoreClock variable contains the core clock , it can * be used by the user application to setup the SysTick timer or configure * other parameters. - * + * * @note Each time the core clock changes, this function must be called * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: - * - * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*) + * + * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*) * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) * - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*), * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. * * (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value * 4 MHz) but the real value may vary depending on the variations - * in voltage and temperature. + * in voltage and temperature. * (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value * 64 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * + * in voltage and temperature. + * * (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value * 25 MHz), user has to ensure that HSE_VALUE is same as the real * frequency of the crystal used. Otherwise, this function may * have wrong result. - * + * * - The result of this function could be not correct when using fractional * value for HSE crystal. * @param None @@ -283,7 +283,7 @@ void SystemCoreClockUpdate (void) switch (RCC->CFGR & RCC_CFGR_SWS) { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ - SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); + SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); break; case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ @@ -306,27 +306,27 @@ void SystemCoreClockUpdate (void) if (pllm != 0U) { - switch (pllsource) - { + switch (pllsource) + { case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */ - hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ; + hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ; pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); - break; + break; case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */ pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); - break; + break; case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */ pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); - break; + break; - default: + default: pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); - break; - } + break; + } pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; SystemCoreClock = (uint32_t)(float_t)(pllvco/(float_t)pllp); } @@ -340,7 +340,7 @@ void SystemCoreClockUpdate (void) SystemCoreClock = CSI_VALUE; break; } - + /* Compute SystemClock frequency --------------------------------------------------*/ tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]; @@ -351,7 +351,7 @@ void SystemCoreClockUpdate (void) SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); } - + /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/device/stm32h747xx.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/device/stm32h747xx.h index 280314f64cb..c8d0a9c5f97 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/device/stm32h747xx.h +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/device/stm32h747xx.h @@ -321,6 +321,15 @@ __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode A } ADC_Common_TypeDef; +/** + * @brief ART + */ + +typedef struct +{ + __IO uint32_t CTR; /*!< ART accelerator - control register */ +}ART_TypeDef; + /** * @brief VREFBUF */ @@ -839,7 +848,7 @@ typedef struct uint32_t RESERVED15[14]; __IO uint32_t MMCTSCGPR; __IO uint32_t MMCTMCGPR; - int32_t RESERVED16[5]; + uint32_t RESERVED16[5]; __IO uint32_t MMCTPCGR; uint32_t RESERVED17[10]; __IO uint32_t MMCRCRCEPR; @@ -2537,7 +2546,6 @@ typedef struct #define EXTI ((EXTI_TypeDef *) EXTI_BASE) #define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE) #define EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE) -#define SDMMC ((SDMMC_TypeDef *) SDMMC_BASE) #define TIM1 ((TIM_TypeDef *) TIM1_BASE) #define SPI1 ((SPI_TypeDef *) SPI1_BASE) #define TIM8 ((TIM_TypeDef *) TIM8_BASE) @@ -2547,11 +2555,11 @@ typedef struct #define TIM16 ((TIM_TypeDef *) TIM16_BASE) #define TIM17 ((TIM_TypeDef *) TIM17_BASE) #define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE) -#define HRTIM1_TIMA ((HRTIM_TIM_TypeDef *) HRTIM1_TIMA_BASE) -#define HRTIM1_TIMB ((HRTIM_TIM_TypeDef *) HRTIM1_TIMB_BASE) -#define HRTIM1_TIMC ((HRTIM_TIM_TypeDef *) HRTIM1_TIMC_BASE) -#define HRTIM1_TIMD ((HRTIM_TIM_TypeDef *) HRTIM1_TIMD_BASE) -#define HRTIM1_TIME ((HRTIM_TIM_TypeDef *) HRTIM1_TIME_BASE) +#define HRTIM1_TIMA ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE) +#define HRTIM1_TIMB ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE) +#define HRTIM1_TIMC ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE) +#define HRTIM1_TIMD ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE) +#define HRTIM1_TIME ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE) #define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE) #define SAI1 ((SAI_TypeDef *) SAI1_BASE) #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) @@ -2584,6 +2592,8 @@ typedef struct #define RCC ((RCC_TypeDef *) RCC_BASE) #define RCC_C1 ((RCC_Core_TypeDef *) RCC_C1_BASE) #define RCC_C2 ((RCC_Core_TypeDef *) RCC_C2_BASE) + +#define ART ((ART_TypeDef *) ART_BASE) #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) #define CRC ((CRC_TypeDef *) CRC_BASE) @@ -4052,6 +4062,20 @@ typedef struct #define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ #define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */ +/******************************************************************************/ +/* */ +/* ART accelerator */ +/* */ +/******************************************************************************/ +/******************* Bit definition for ART_CTR register ********************/ +#define ART_CTR_EN_Pos (0U) +#define ART_CTR_EN_Msk (0x1UL << ART_CTR_EN_Pos) /*!< 0x00000001 */ +#define ART_CTR_EN ART_CTR_EN_Msk /*!< Cache enable*/ + +#define ART_CTR_PCACHEADDR_Pos (8U) +#define ART_CTR_PCACHEADDR_Msk (0xFFFUL << ART_CTR_PCACHEADDR_Pos) /*!< 0x000FFF00 */ +#define ART_CTR_PCACHEADDR ART_CTR_PCACHEADDR_Msk /*!< Cacheable page index */ + /******************************************************************************/ /* */ /* VREFBUF */ @@ -13749,7 +13773,7 @@ typedef struct /******************* Bits definition for FLASH_ACR register **********************/ #define FLASH_ACR_LATENCY_Pos (0U) #define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ -#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */ #define FLASH_ACR_LATENCY_0WS (0x00000000UL) #define FLASH_ACR_LATENCY_1WS (0x00000001UL) #define FLASH_ACR_LATENCY_2WS (0x00000002UL) @@ -13768,340 +13792,340 @@ typedef struct #define FLASH_ACR_LATENCY_15WS (0x0000000FUL) #define FLASH_ACR_WRHIGHFREQ_Pos (4U) #define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ -#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ #define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ #define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ /******************* Bits definition for FLASH_CR register ***********************/ #define FLASH_CR_LOCK_Pos (0U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ -#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Configuration lock bit */ #define FLASH_CR_PG_Pos (1U) #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000002 */ -#define FLASH_CR_PG FLASH_CR_PG_Msk +#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Internal buffer control bit */ #define FLASH_CR_SER_Pos (2U) #define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000004 */ -#define FLASH_CR_SER FLASH_CR_SER_Msk +#define FLASH_CR_SER FLASH_CR_SER_Msk /*!< Sector erase request */ #define FLASH_CR_BER_Pos (3U) #define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) /*!< 0x00000008 */ -#define FLASH_CR_BER FLASH_CR_BER_Msk +#define FLASH_CR_BER FLASH_CR_BER_Msk /*!< Bank erase request */ #define FLASH_CR_PSIZE_Pos (4U) #define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000030 */ -#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk +#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk /*!< Program size */ #define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000010 */ #define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000020 */ #define FLASH_CR_FW_Pos (6U) #define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) /*!< 0x00000040 */ -#define FLASH_CR_FW FLASH_CR_FW_Msk +#define FLASH_CR_FW FLASH_CR_FW_Msk /*!< Write forcing control bit */ #define FLASH_CR_START_Pos (7U) #define FLASH_CR_START_Msk (0x1UL << FLASH_CR_START_Pos) /*!< 0x00000080 */ -#define FLASH_CR_START FLASH_CR_START_Msk +#define FLASH_CR_START FLASH_CR_START_Msk /*!< Erase start control bit */ #define FLASH_CR_SNB_Pos (8U) #define FLASH_CR_SNB_Msk (0x7UL << FLASH_CR_SNB_Pos) /*!< 0x00000700 */ -#define FLASH_CR_SNB FLASH_CR_SNB_Msk -#define FLASH_CR_SNB_0 (0x1UL << FLASH_CR_SNB_Pos) /*!< 0x00000100 */ -#define FLASH_CR_SNB_1 (0x2UL << FLASH_CR_SNB_Pos) /*!< 0x00000200 */ -#define FLASH_CR_SNB_2 (0x4UL << FLASH_CR_SNB_Pos) /*!< 0x00000400 */ +#define FLASH_CR_SNB FLASH_CR_SNB_Msk /*!< Sector erase selection number */ +#define FLASH_CR_SNB_0 (0x1UL << FLASH_CR_SNB_Pos) /*!< 0x00000100 */ +#define FLASH_CR_SNB_1 (0x2UL << FLASH_CR_SNB_Pos) /*!< 0x00000200 */ +#define FLASH_CR_SNB_2 (0x4UL << FLASH_CR_SNB_Pos) /*!< 0x00000400 */ #define FLASH_CR_CRC_EN_Pos (15U) #define FLASH_CR_CRC_EN_Msk (0x1UL << FLASH_CR_CRC_EN_Pos) /*!< 0x00008000 */ -#define FLASH_CR_CRC_EN FLASH_CR_CRC_EN_Msk +#define FLASH_CR_CRC_EN FLASH_CR_CRC_EN_Msk /*!< CRC control bit */ #define FLASH_CR_EOPIE_Pos (16U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00010000 */ -#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End-of-program interrupt control bit */ #define FLASH_CR_WRPERRIE_Pos (17U) #define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) /*!< 0x00020000 */ -#define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk +#define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk /*!< Write protection error interrupt enable bit */ #define FLASH_CR_PGSERRIE_Pos (18U) #define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) /*!< 0x00040000 */ -#define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk +#define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk /*!< Programming sequence error interrupt enable bit */ #define FLASH_CR_STRBERRIE_Pos (19U) #define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */ -#define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk +#define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk /*!< Strobe error interrupt enable bit */ #define FLASH_CR_INCERRIE_Pos (21U) #define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) /*!< 0x00200000 */ -#define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk +#define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk /*!< Inconsistency error interrupt enable bit */ #define FLASH_CR_OPERRIE_Pos (22U) #define FLASH_CR_OPERRIE_Msk (0x1UL << FLASH_CR_OPERRIE_Pos) /*!< 0x00400000 */ -#define FLASH_CR_OPERRIE FLASH_CR_OPERRIE_Msk +#define FLASH_CR_OPERRIE FLASH_CR_OPERRIE_Msk /*!< Write/erase error interrupt enable bit */ #define FLASH_CR_RDPERRIE_Pos (23U) #define FLASH_CR_RDPERRIE_Msk (0x1UL << FLASH_CR_RDPERRIE_Pos) /*!< 0x00800000 */ -#define FLASH_CR_RDPERRIE FLASH_CR_RDPERRIE_Msk +#define FLASH_CR_RDPERRIE FLASH_CR_RDPERRIE_Msk /*!< Read protection error interrupt enable bit */ #define FLASH_CR_RDSERRIE_Pos (24U) #define FLASH_CR_RDSERRIE_Msk (0x1UL << FLASH_CR_RDSERRIE_Pos) /*!< 0x01000000 */ -#define FLASH_CR_RDSERRIE FLASH_CR_RDSERRIE_Msk +#define FLASH_CR_RDSERRIE FLASH_CR_RDSERRIE_Msk /*!< Secure error interrupt enable bit */ #define FLASH_CR_SNECCERRIE_Pos (25U) #define FLASH_CR_SNECCERRIE_Msk (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */ -#define FLASH_CR_SNECCERRIE FLASH_CR_SNECCERRIE_Msk +#define FLASH_CR_SNECCERRIE FLASH_CR_SNECCERRIE_Msk /*!< ECC single correction error interrupt enable bit */ #define FLASH_CR_DBECCERRIE_Pos (26U) #define FLASH_CR_DBECCERRIE_Msk (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */ -#define FLASH_CR_DBECCERRIE FLASH_CR_DBECCERRIE_Msk +#define FLASH_CR_DBECCERRIE FLASH_CR_DBECCERRIE_Msk /*!< ECC double detection error interrupt enable bit */ #define FLASH_CR_CRCENDIE_Pos (27U) #define FLASH_CR_CRCENDIE_Msk (0x1UL << FLASH_CR_CRCENDIE_Pos) /*!< 0x08000000 */ -#define FLASH_CR_CRCENDIE FLASH_CR_CRCENDIE_Msk +#define FLASH_CR_CRCENDIE FLASH_CR_CRCENDIE_Msk /*!< CRC end of calculation interrupt enable bit */ #define FLASH_CR_CRCRDERRIE_Pos (28U) #define FLASH_CR_CRCRDERRIE_Msk (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */ -#define FLASH_CR_CRCRDERRIE FLASH_CR_CRCRDERRIE_Msk +#define FLASH_CR_CRCRDERRIE FLASH_CR_CRCRDERRIE_Msk /*!< CRC read error interrupt enable bit */ /******************* Bits definition for FLASH_SR register ***********************/ #define FLASH_SR_BSY_Pos (0U) #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ -#define FLASH_SR_BSY FLASH_SR_BSY_Msk +#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy flag */ #define FLASH_SR_WBNE_Pos (1U) #define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) /*!< 0x00000002 */ -#define FLASH_SR_WBNE FLASH_SR_WBNE_Msk +#define FLASH_SR_WBNE FLASH_SR_WBNE_Msk /*!< Write buffer not empty flag */ #define FLASH_SR_QW_Pos (2U) #define FLASH_SR_QW_Msk (0x1UL << FLASH_SR_QW_Pos) /*!< 0x00000004 */ -#define FLASH_SR_QW FLASH_SR_QW_Msk +#define FLASH_SR_QW FLASH_SR_QW_Msk /*!< Wait queue flag */ #define FLASH_SR_CRC_BUSY_Pos (3U) #define FLASH_SR_CRC_BUSY_Msk (0x1UL << FLASH_SR_CRC_BUSY_Pos) /*!< 0x00000008 */ -#define FLASH_SR_CRC_BUSY FLASH_SR_CRC_BUSY_Msk +#define FLASH_SR_CRC_BUSY FLASH_SR_CRC_BUSY_Msk /*!< CRC busy flag */ #define FLASH_SR_EOP_Pos (16U) #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00010000 */ -#define FLASH_SR_EOP FLASH_SR_EOP_Msk +#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End-of-program flag */ #define FLASH_SR_WRPERR_Pos (17U) #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00020000 */ -#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error flag */ #define FLASH_SR_PGSERR_Pos (18U) #define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00040000 */ -#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< Programming sequence error flag */ #define FLASH_SR_STRBERR_Pos (19U) #define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) /*!< 0x00080000 */ -#define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk +#define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk /*!< Strobe error flag */ #define FLASH_SR_INCERR_Pos (21U) #define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) /*!< 0x00200000 */ -#define FLASH_SR_INCERR FLASH_SR_INCERR_Msk +#define FLASH_SR_INCERR FLASH_SR_INCERR_Msk /*!< Inconsistency error flag */ #define FLASH_SR_OPERR_Pos (22U) #define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00400000 */ -#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk +#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk /*!< Write/erase error flag */ #define FLASH_SR_RDPERR_Pos (23U) #define FLASH_SR_RDPERR_Msk (0x1UL << FLASH_SR_RDPERR_Pos) /*!< 0x00800000 */ -#define FLASH_SR_RDPERR FLASH_SR_RDPERR_Msk +#define FLASH_SR_RDPERR FLASH_SR_RDPERR_Msk /*!< Read protection error flag */ #define FLASH_SR_RDSERR_Pos (24U) #define FLASH_SR_RDSERR_Msk (0x1UL << FLASH_SR_RDSERR_Pos) /*!< 0x01000000 */ -#define FLASH_SR_RDSERR FLASH_SR_RDSERR_Msk +#define FLASH_SR_RDSERR FLASH_SR_RDSERR_Msk /*!< Secure error flag */ #define FLASH_SR_SNECCERR_Pos (25U) #define FLASH_SR_SNECCERR_Msk (0x1UL << FLASH_SR_SNECCERR_Pos) /*!< 0x02000000 */ -#define FLASH_SR_SNECCERR FLASH_SR_SNECCERR_Msk +#define FLASH_SR_SNECCERR FLASH_SR_SNECCERR_Msk /*!< Single correction error flag */ #define FLASH_SR_DBECCERR_Pos (26U) #define FLASH_SR_DBECCERR_Msk (0x1UL << FLASH_SR_DBECCERR_Pos) /*!< 0x04000000 */ -#define FLASH_SR_DBECCERR FLASH_SR_DBECCERR_Msk +#define FLASH_SR_DBECCERR FLASH_SR_DBECCERR_Msk /*!< ECC double detection error flag */ #define FLASH_SR_CRCEND_Pos (27U) #define FLASH_SR_CRCEND_Msk (0x1UL << FLASH_SR_CRCEND_Pos) /*!< 0x08000000 */ -#define FLASH_SR_CRCEND FLASH_SR_CRCEND_Msk +#define FLASH_SR_CRCEND FLASH_SR_CRCEND_Msk /*!< CRC end of calculation flag */ #define FLASH_SR_CRCRDERR_Pos (28U) #define FLASH_SR_CRCRDERR_Msk (0x1UL << FLASH_SR_CRCRDERR_Pos) /*!< 0x10000000 */ -#define FLASH_SR_CRCRDERR FLASH_SR_CRCRDERR_Msk +#define FLASH_SR_CRCRDERR FLASH_SR_CRCRDERR_Msk /*!< CRC read error flag */ /******************* Bits definition for FLASH_CCR register *******************/ #define FLASH_CCR_CLR_EOP_Pos (16U) #define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) /*!< 0x00010000 */ -#define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk +#define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk /*!< EOP flag clear bit */ #define FLASH_CCR_CLR_WRPERR_Pos (17U) #define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */ -#define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk +#define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk /*!< WRPERR flag clear bit */ #define FLASH_CCR_CLR_PGSERR_Pos (18U) #define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */ -#define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk +#define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk /*!< PGSERR flag clear bit */ #define FLASH_CCR_CLR_STRBERR_Pos (19U) #define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */ -#define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk +#define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk /*!< STRBERR flag clear bit */ #define FLASH_CCR_CLR_INCERR_Pos (21U) #define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */ -#define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk +#define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk /*!< INCERR flag clear bit */ #define FLASH_CCR_CLR_OPERR_Pos (22U) #define FLASH_CCR_CLR_OPERR_Msk (0x1UL << FLASH_CCR_CLR_OPERR_Pos) /*!< 0x00400000 */ -#define FLASH_CCR_CLR_OPERR FLASH_CCR_CLR_OPERR_Msk +#define FLASH_CCR_CLR_OPERR FLASH_CCR_CLR_OPERR_Msk /*!< OPERR flag clear bit */ #define FLASH_CCR_CLR_RDPERR_Pos (23U) #define FLASH_CCR_CLR_RDPERR_Msk (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */ -#define FLASH_CCR_CLR_RDPERR FLASH_CCR_CLR_RDPERR_Msk +#define FLASH_CCR_CLR_RDPERR FLASH_CCR_CLR_RDPERR_Msk /*!< RDPERR flag clear bit */ #define FLASH_CCR_CLR_RDSERR_Pos (24U) #define FLASH_CCR_CLR_RDSERR_Msk (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */ -#define FLASH_CCR_CLR_RDSERR FLASH_CCR_CLR_RDSERR_Msk +#define FLASH_CCR_CLR_RDSERR FLASH_CCR_CLR_RDSERR_Msk /*!< RDSERR flag clear bit */ #define FLASH_CCR_CLR_SNECCERR_Pos (25U) #define FLASH_CCR_CLR_SNECCERR_Msk (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */ -#define FLASH_CCR_CLR_SNECCERR FLASH_CCR_CLR_SNECCERR_Msk +#define FLASH_CCR_CLR_SNECCERR FLASH_CCR_CLR_SNECCERR_Msk /*!< SNECCERR flag clear bit */ #define FLASH_CCR_CLR_DBECCERR_Pos (26U) #define FLASH_CCR_CLR_DBECCERR_Msk (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */ -#define FLASH_CCR_CLR_DBECCERR FLASH_CCR_CLR_DBECCERR_Msk +#define FLASH_CCR_CLR_DBECCERR FLASH_CCR_CLR_DBECCERR_Msk /*!< DBECCERR flag clear bit */ #define FLASH_CCR_CLR_CRCEND_Pos (27U) #define FLASH_CCR_CLR_CRCEND_Msk (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */ -#define FLASH_CCR_CLR_CRCEND FLASH_CCR_CLR_CRCEND_Msk +#define FLASH_CCR_CLR_CRCEND FLASH_CCR_CLR_CRCEND_Msk /*!< CRCEND flag clear bit */ #define FLASH_CCR_CLR_CRCRDERR_Pos (28U) #define FLASH_CCR_CLR_CRCRDERR_Msk (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */ -#define FLASH_CCR_CLR_CRCRDERR FLASH_CCR_CLR_CRCRDERR_Msk +#define FLASH_CCR_CLR_CRCRDERR FLASH_CCR_CLR_CRCRDERR_Msk /*!< CRCRDERR flag clear bit */ /******************* Bits definition for FLASH_OPTCR register *******************/ #define FLASH_OPTCR_OPTLOCK_Pos (0U) #define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */ -#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk +#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk /*!< FLASH_OPTCR lock option configuration bit */ #define FLASH_OPTCR_OPTSTART_Pos (1U) #define FLASH_OPTCR_OPTSTART_Msk (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */ -#define FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk +#define FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk /*!< Option byte start change option configuration bit */ #define FLASH_OPTCR_MER_Pos (4U) #define FLASH_OPTCR_MER_Msk (0x1UL << FLASH_OPTCR_MER_Pos) /*!< 0x00000010 */ -#define FLASH_OPTCR_MER FLASH_OPTCR_MER_Msk +#define FLASH_OPTCR_MER FLASH_OPTCR_MER_Msk /*!< Mass erase request */ #define FLASH_OPTCR_OPTCHANGEERRIE_Pos (30U) #define FLASH_OPTCR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */ -#define FLASH_OPTCR_OPTCHANGEERRIE FLASH_OPTCR_OPTCHANGEERRIE_Msk +#define FLASH_OPTCR_OPTCHANGEERRIE FLASH_OPTCR_OPTCHANGEERRIE_Msk /*!< Option byte change error interrupt enable bit */ #define FLASH_OPTCR_SWAP_BANK_Pos (31U) #define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */ -#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk +#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk /*!< Bank swapping option configuration bit */ /******************* Bits definition for FLASH_OPTSR register ***************/ #define FLASH_OPTSR_OPT_BUSY_Pos (0U) #define FLASH_OPTSR_OPT_BUSY_Msk (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */ -#define FLASH_OPTSR_OPT_BUSY FLASH_OPTSR_OPT_BUSY_Msk +#define FLASH_OPTSR_OPT_BUSY FLASH_OPTSR_OPT_BUSY_Msk /*!< Option byte change ongoing flag */ #define FLASH_OPTSR_BOR_LEV_Pos (2U) #define FLASH_OPTSR_BOR_LEV_Msk (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */ -#define FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk +#define FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk /*!< Brownout level option status bit */ #define FLASH_OPTSR_BOR_LEV_0 (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */ #define FLASH_OPTSR_BOR_LEV_1 (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */ #define FLASH_OPTSR_IWDG1_SW_Pos (4U) #define FLASH_OPTSR_IWDG1_SW_Msk (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */ -#define FLASH_OPTSR_IWDG1_SW FLASH_OPTSR_IWDG1_SW_Msk +#define FLASH_OPTSR_IWDG1_SW FLASH_OPTSR_IWDG1_SW_Msk /*!< IWDG1 control mode option status bit */ #define FLASH_OPTSR_IWDG2_SW_Pos (5U) #define FLASH_OPTSR_IWDG2_SW_Msk (0x1UL << FLASH_OPTSR_IWDG2_SW_Pos) /*!< 0x00000020 */ -#define FLASH_OPTSR_IWDG2_SW FLASH_OPTSR_IWDG2_SW_Msk +#define FLASH_OPTSR_IWDG2_SW FLASH_OPTSR_IWDG2_SW_Msk /*!< IWDG2 control mode option status bit */ #define FLASH_OPTSR_NRST_STOP_D1_Pos (6U) #define FLASH_OPTSR_NRST_STOP_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */ -#define FLASH_OPTSR_NRST_STOP_D1 FLASH_OPTSR_NRST_STOP_D1_Msk +#define FLASH_OPTSR_NRST_STOP_D1 FLASH_OPTSR_NRST_STOP_D1_Msk /*!< D1 domain DStop entry reset option status bit */ #define FLASH_OPTSR_NRST_STBY_D1_Pos (7U) #define FLASH_OPTSR_NRST_STBY_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */ -#define FLASH_OPTSR_NRST_STBY_D1 FLASH_OPTSR_NRST_STBY_D1_Msk +#define FLASH_OPTSR_NRST_STBY_D1 FLASH_OPTSR_NRST_STBY_D1_Msk /*!< D1 domain DStandby entry reset option status bit */ #define FLASH_OPTSR_RDP_Pos (8U) #define FLASH_OPTSR_RDP_Msk (0xFFUL << FLASH_OPTSR_RDP_Pos) /*!< 0x0000FF00 */ -#define FLASH_OPTSR_RDP FLASH_OPTSR_RDP_Msk +#define FLASH_OPTSR_RDP FLASH_OPTSR_RDP_Msk /*!< Readout protection level option status byte */ #define FLASH_OPTSR_FZ_IWDG_STOP_Pos (17U) #define FLASH_OPTSR_FZ_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */ -#define FLASH_OPTSR_FZ_IWDG_STOP FLASH_OPTSR_FZ_IWDG_STOP_Msk +#define FLASH_OPTSR_FZ_IWDG_STOP FLASH_OPTSR_FZ_IWDG_STOP_Msk /*!< IWDG Stop mode freeze option status bit */ #define FLASH_OPTSR_FZ_IWDG_SDBY_Pos (18U) #define FLASH_OPTSR_FZ_IWDG_SDBY_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */ -#define FLASH_OPTSR_FZ_IWDG_SDBY FLASH_OPTSR_FZ_IWDG_SDBY_Msk +#define FLASH_OPTSR_FZ_IWDG_SDBY FLASH_OPTSR_FZ_IWDG_SDBY_Msk /*!< IWDG Standby mode freeze option status bit */ #define FLASH_OPTSR_ST_RAM_SIZE_Pos (19U) #define FLASH_OPTSR_ST_RAM_SIZE_Msk (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */ -#define FLASH_OPTSR_ST_RAM_SIZE FLASH_OPTSR_ST_RAM_SIZE_Msk +#define FLASH_OPTSR_ST_RAM_SIZE FLASH_OPTSR_ST_RAM_SIZE_Msk /*!< ST RAM size option status */ #define FLASH_OPTSR_ST_RAM_SIZE_0 (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */ #define FLASH_OPTSR_ST_RAM_SIZE_1 (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */ #define FLASH_OPTSR_SECURITY_Pos (21U) #define FLASH_OPTSR_SECURITY_Msk (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */ -#define FLASH_OPTSR_SECURITY FLASH_OPTSR_SECURITY_Msk +#define FLASH_OPTSR_SECURITY FLASH_OPTSR_SECURITY_Msk /*!< Security enable option status bit */ #define FLASH_OPTSR_BCM4_Pos (22U) #define FLASH_OPTSR_BCM4_Msk (0x1UL << FLASH_OPTSR_BCM4_Pos) /*!< 0x00400000 */ -#define FLASH_OPTSR_BCM4 FLASH_OPTSR_BCM4_Msk +#define FLASH_OPTSR_BCM4 FLASH_OPTSR_BCM4_Msk /*!< Arm Cortex-M4 boot option status bit */ #define FLASH_OPTSR_BCM7_Pos (23U) #define FLASH_OPTSR_BCM7_Msk (0x1UL << FLASH_OPTSR_BCM7_Pos) /*!< 0x00800000 */ -#define FLASH_OPTSR_BCM7 FLASH_OPTSR_BCM7_Msk +#define FLASH_OPTSR_BCM7 FLASH_OPTSR_BCM7_Msk /*!< Arm Cortex-M7 boot option status bit */ #define FLASH_OPTSR_NRST_STOP_D2_Pos (24U) #define FLASH_OPTSR_NRST_STOP_D2_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_D2_Pos) /*!< 0x01000000 */ -#define FLASH_OPTSR_NRST_STOP_D2 FLASH_OPTSR_NRST_STOP_D2_Msk +#define FLASH_OPTSR_NRST_STOP_D2 FLASH_OPTSR_NRST_STOP_D2_Msk /*!< D2 domain DStop entry reset option status bit */ #define FLASH_OPTSR_NRST_STBY_D2_Pos (25U) #define FLASH_OPTSR_NRST_STBY_D2_Msk (0x1UL << FLASH_OPTSR_NRST_STBY_D2_Pos) /*!< 0x02000000 */ -#define FLASH_OPTSR_NRST_STBY_D2 FLASH_OPTSR_NRST_STBY_D2_Msk +#define FLASH_OPTSR_NRST_STBY_D2 FLASH_OPTSR_NRST_STBY_D2_Msk /*!< D2 domain DStandby entry reset option status bit */ #define FLASH_OPTSR_IO_HSLV_Pos (29U) #define FLASH_OPTSR_IO_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */ -#define FLASH_OPTSR_IO_HSLV FLASH_OPTSR_IO_HSLV_Msk +#define FLASH_OPTSR_IO_HSLV FLASH_OPTSR_IO_HSLV_Msk /*!< I/O high-speed at low-voltage status bit */ #define FLASH_OPTSR_OPTCHANGEERR_Pos (30U) #define FLASH_OPTSR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */ -#define FLASH_OPTSR_OPTCHANGEERR FLASH_OPTSR_OPTCHANGEERR_Msk +#define FLASH_OPTSR_OPTCHANGEERR FLASH_OPTSR_OPTCHANGEERR_Msk /*!< Option byte change error flag */ #define FLASH_OPTSR_SWAP_BANK_OPT_Pos (31U) #define FLASH_OPTSR_SWAP_BANK_OPT_Msk (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */ -#define FLASH_OPTSR_SWAP_BANK_OPT FLASH_OPTSR_SWAP_BANK_OPT_Msk +#define FLASH_OPTSR_SWAP_BANK_OPT FLASH_OPTSR_SWAP_BANK_OPT_Msk /*!< Bank swapping option status bit */ /******************* Bits definition for FLASH_OPTCCR register *******************/ #define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos (30U) #define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */ -#define FLASH_OPTCCR_CLR_OPTCHANGEERR FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk +#define FLASH_OPTCCR_CLR_OPTCHANGEERR FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk /*!< OPTCHANGEERR reset bit */ /******************* Bits definition for FLASH_PRAR register *********************/ #define FLASH_PRAR_PROT_AREA_START_Pos (0U) #define FLASH_PRAR_PROT_AREA_START_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */ -#define FLASH_PRAR_PROT_AREA_START FLASH_PRAR_PROT_AREA_START_Msk +#define FLASH_PRAR_PROT_AREA_START FLASH_PRAR_PROT_AREA_START_Msk /*!< PCROP area start status bits */ #define FLASH_PRAR_PROT_AREA_END_Pos (16U) #define FLASH_PRAR_PROT_AREA_END_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */ -#define FLASH_PRAR_PROT_AREA_END FLASH_PRAR_PROT_AREA_END_Msk +#define FLASH_PRAR_PROT_AREA_END FLASH_PRAR_PROT_AREA_END_Msk /*!< PCROP area end status bits */ #define FLASH_PRAR_DMEP_Pos (31U) #define FLASH_PRAR_DMEP_Msk (0x1UL << FLASH_PRAR_DMEP_Pos) /*!< 0x80000000 */ -#define FLASH_PRAR_DMEP FLASH_PRAR_DMEP_Msk +#define FLASH_PRAR_DMEP FLASH_PRAR_DMEP_Msk /*!< PCROP protected erase enable option status bit */ /******************* Bits definition for FLASH_SCAR register *********************/ #define FLASH_SCAR_SEC_AREA_START_Pos (0U) #define FLASH_SCAR_SEC_AREA_START_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */ -#define FLASH_SCAR_SEC_AREA_START FLASH_SCAR_SEC_AREA_START_Msk +#define FLASH_SCAR_SEC_AREA_START FLASH_SCAR_SEC_AREA_START_Msk /*!< Secure-only area start status bits */ #define FLASH_SCAR_SEC_AREA_END_Pos (16U) #define FLASH_SCAR_SEC_AREA_END_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */ -#define FLASH_SCAR_SEC_AREA_END FLASH_SCAR_SEC_AREA_END_Msk +#define FLASH_SCAR_SEC_AREA_END FLASH_SCAR_SEC_AREA_END_Msk /*!< Secure-only area end status bits */ #define FLASH_SCAR_DMES_Pos (31U) #define FLASH_SCAR_DMES_Msk (0x1UL << FLASH_SCAR_DMES_Pos) /*!< 0x80000000 */ -#define FLASH_SCAR_DMES FLASH_SCAR_DMES_Msk +#define FLASH_SCAR_DMES FLASH_SCAR_DMES_Msk /*!< Secure access protected erase enable option status bit */ /******************* Bits definition for FLASH_WPSN register *********************/ #define FLASH_WPSN_WRPSN_Pos (0U) #define FLASH_WPSN_WRPSN_Msk (0xFFUL << FLASH_WPSN_WRPSN_Pos) /*!< 0x000000FF */ -#define FLASH_WPSN_WRPSN FLASH_WPSN_WRPSN_Msk +#define FLASH_WPSN_WRPSN FLASH_WPSN_WRPSN_Msk /*!< Sector write protection option status byte */ /******************* Bits definition for FLASH_BOOT7_CUR register ****************/ #define FLASH_BOOT7_BCM7_ADD0_Pos (0U) #define FLASH_BOOT7_BCM7_ADD0_Msk (0xFFFFUL << FLASH_BOOT7_BCM7_ADD0_Pos) /*!< 0x0000FFFF */ -#define FLASH_BOOT7_BCM7_ADD0 FLASH_BOOT7_BCM7_ADD0_Msk +#define FLASH_BOOT7_BCM7_ADD0 FLASH_BOOT7_BCM7_ADD0_Msk /*!< Arm Cortex-M7 boot address 0 */ #define FLASH_BOOT7_BCM7_ADD1_Pos (16U) #define FLASH_BOOT7_BCM7_ADD1_Msk (0xFFFFUL << FLASH_BOOT7_BCM7_ADD1_Pos) /*!< 0xFFFF0000 */ -#define FLASH_BOOT7_BCM7_ADD1 FLASH_BOOT7_BCM7_ADD1_Msk +#define FLASH_BOOT7_BCM7_ADD1 FLASH_BOOT7_BCM7_ADD1_Msk /*!< Arm Cortex-M7 boot address 1 */ /******************* Bits definition for FLASH_BOOT4 register ********************/ #define FLASH_BOOT4_BCM4_ADD0_Pos (0U) #define FLASH_BOOT4_BCM4_ADD0_Msk (0xFFFFUL << FLASH_BOOT4_BCM4_ADD0_Pos) /*!< 0x0000FFFF */ -#define FLASH_BOOT4_BCM4_ADD0 FLASH_BOOT4_BCM4_ADD0_Msk +#define FLASH_BOOT4_BCM4_ADD0 FLASH_BOOT4_BCM4_ADD0_Msk /*!< Arm Cortex-M4 boot address 0 */ #define FLASH_BOOT4_BCM4_ADD1_Pos (16U) #define FLASH_BOOT4_BCM4_ADD1_Msk (0xFFFFUL << FLASH_BOOT4_BCM4_ADD1_Pos) /*!< 0xFFFF0000 */ -#define FLASH_BOOT4_BCM4_ADD1 FLASH_BOOT4_BCM4_ADD1_Msk +#define FLASH_BOOT4_BCM4_ADD1 FLASH_BOOT4_BCM4_ADD1_Msk /*!< Arm Cortex-M4 boot address 1 */ /******************* Bits definition for FLASH_CRCCR register ********************/ #define FLASH_CRCCR_CRC_SECT_Pos (0U) #define FLASH_CRCCR_CRC_SECT_Msk (0x7UL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x00000007 */ -#define FLASH_CRCCR_CRC_SECT FLASH_CRCCR_CRC_SECT_Msk +#define FLASH_CRCCR_CRC_SECT FLASH_CRCCR_CRC_SECT_Msk /*!< CRC sector number */ #define FLASH_CRCCR_CRC_BY_SECT_Pos (8U) #define FLASH_CRCCR_CRC_BY_SECT_Msk (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */ -#define FLASH_CRCCR_CRC_BY_SECT FLASH_CRCCR_CRC_BY_SECT_Msk +#define FLASH_CRCCR_CRC_BY_SECT FLASH_CRCCR_CRC_BY_SECT_Msk /*!< CRC sector mode select bit */ #define FLASH_CRCCR_ADD_SECT_Pos (9U) #define FLASH_CRCCR_ADD_SECT_Msk (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */ -#define FLASH_CRCCR_ADD_SECT FLASH_CRCCR_ADD_SECT_Msk +#define FLASH_CRCCR_ADD_SECT FLASH_CRCCR_ADD_SECT_Msk /*!< CRC sector select bit */ #define FLASH_CRCCR_CLEAN_SECT_Pos (10U) #define FLASH_CRCCR_CLEAN_SECT_Msk (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */ -#define FLASH_CRCCR_CLEAN_SECT FLASH_CRCCR_CLEAN_SECT_Msk +#define FLASH_CRCCR_CLEAN_SECT FLASH_CRCCR_CLEAN_SECT_Msk /*!< CRC sector list clear bit */ #define FLASH_CRCCR_START_CRC_Pos (16U) #define FLASH_CRCCR_START_CRC_Msk (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */ -#define FLASH_CRCCR_START_CRC FLASH_CRCCR_START_CRC_Msk +#define FLASH_CRCCR_START_CRC FLASH_CRCCR_START_CRC_Msk /*!< CRC start bit */ #define FLASH_CRCCR_CLEAN_CRC_Pos (17U) #define FLASH_CRCCR_CLEAN_CRC_Msk (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */ -#define FLASH_CRCCR_CLEAN_CRC FLASH_CRCCR_CLEAN_CRC_Msk +#define FLASH_CRCCR_CLEAN_CRC FLASH_CRCCR_CLEAN_CRC_Msk /*!< CRC clear bit */ #define FLASH_CRCCR_CRC_BURST_Pos (20U) #define FLASH_CRCCR_CRC_BURST_Msk (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */ -#define FLASH_CRCCR_CRC_BURST FLASH_CRCCR_CRC_BURST_Msk +#define FLASH_CRCCR_CRC_BURST FLASH_CRCCR_CRC_BURST_Msk /*!< CRC burst size */ #define FLASH_CRCCR_CRC_BURST_0 (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */ #define FLASH_CRCCR_CRC_BURST_1 (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */ #define FLASH_CRCCR_ALL_BANK_Pos (22U) #define FLASH_CRCCR_ALL_BANK_Msk (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */ -#define FLASH_CRCCR_ALL_BANK FLASH_CRCCR_ALL_BANK_Msk +#define FLASH_CRCCR_ALL_BANK FLASH_CRCCR_ALL_BANK_Msk /*!< CRC select bit */ /******************* Bits definition for FLASH_CRCSADD register ****************/ #define FLASH_CRCSADD_CRC_START_ADDR_Pos (0U) #define FLASH_CRCSADD_CRC_START_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */ -#define FLASH_CRCSADD_CRC_START_ADDR FLASH_CRCSADD_CRC_START_ADDR_Msk +#define FLASH_CRCSADD_CRC_START_ADDR FLASH_CRCSADD_CRC_START_ADDR_Msk /*!< CRC start address */ /******************* Bits definition for FLASH_CRCEADD register ****************/ #define FLASH_CRCEADD_CRC_END_ADDR_Pos (0U) #define FLASH_CRCEADD_CRC_END_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */ -#define FLASH_CRCEADD_CRC_END_ADDR FLASH_CRCEADD_CRC_END_ADDR_Msk +#define FLASH_CRCEADD_CRC_END_ADDR FLASH_CRCEADD_CRC_END_ADDR_Msk /*!< CRC end address */ /******************* Bits definition for FLASH_CRCDATA register ***************/ #define FLASH_CRCDATA_CRC_DATA_Pos (0U) #define FLASH_CRCDATA_CRC_DATA_Msk (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */ -#define FLASH_CRCDATA_CRC_DATA FLASH_CRCDATA_CRC_DATA_Msk +#define FLASH_CRCDATA_CRC_DATA FLASH_CRCDATA_CRC_DATA_Msk /*!< CRC result */ /******************* Bits definition for FLASH_ECC_FA register *******************/ #define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos (0U) #define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk (0x7FFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x00007FFF */ -#define FLASH_ECC_FA_FAIL_ECC_ADDR FLASH_ECC_FA_FAIL_ECC_ADDR_Msk +#define FLASH_ECC_FA_FAIL_ECC_ADDR FLASH_ECC_FA_FAIL_ECC_ADDR_Msk /*!< ECC error address */ /******************************************************************************/ /* */ @@ -22893,7 +22917,9 @@ typedef struct /* TIM */ /* */ /******************************************************************************/ -#define TIM_BREAK_INPUT_SUPPORT /*!
© Copyright (c) 2018 STMicroelectronics. + *

© Copyright (c) 2019 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, @@ -236,6 +236,11 @@ #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE +#if defined(STM32G4) +#define DAC_CHIPCONNECT_DISABLE (DAC_CHIPCONNECT_EXTERNAL | DAC_CHIPCONNECT_BOTH) +#define DAC_CHIPCONNECT_ENABLE (DAC_CHIPCONNECT_INTERNAL | DAC_CHIPCONNECT_BOTH) +#endif + #if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID @@ -491,7 +496,13 @@ #define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 #define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 #define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 +#if defined(STM32G4) +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD +#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD +#endif /* STM32G4 */ /** * @} */ @@ -500,7 +511,7 @@ /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose * @{ */ -#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) +#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 @@ -559,12 +570,12 @@ #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32H7) +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32H7*/ +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/ #if defined(STM32L1) #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW @@ -606,6 +617,124 @@ #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE +#if defined(STM32G4) +#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig +#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable +#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable +#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset +#endif /* STM32G4 */ + +#if defined(STM32H7) +#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 + +#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 +#endif /* STM32H7 */ /** * @} */ @@ -1280,7 +1409,7 @@ #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4) #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT @@ -2985,7 +3114,7 @@ #if defined(STM32L4) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE -#elif defined(STM32WB) || defined(STM32G0) +#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK #endif @@ -3113,7 +3242,7 @@ /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) +#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32G4) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3229,7 +3358,7 @@ #define SDIO_IRQHandler SDMMC1_IRQHandler #endif -#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) +#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) #define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef #define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef #define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef @@ -3476,7 +3605,7 @@ /** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose * @{ */ -#if defined (STM32H7) || defined (STM32F3) +#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) #define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT #define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA #define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx.h b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx.h index b1a7cf80518..c3e276b2119 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx.h +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx.h @@ -88,10 +88,10 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V1.5.0 + * @brief CMSIS Device version number V1.6.0 */ #define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */ +#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x06) /*!< [23:16] sub1 version */ #define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32H7xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\ diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal.c b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal.c index bf67d43d296..b1c84f1614f 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal.c +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal.c @@ -47,10 +47,10 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** - * @brief STM32H7xx HAL Driver version number V1.5.0 + * @brief STM32H7xx HAL Driver version number V1.6.0 */ #define __STM32H7xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */ -#define __STM32H7xx_HAL_VERSION_SUB1 (0x05UL) /*!< [23:16] sub1 version */ +#define __STM32H7xx_HAL_VERSION_SUB1 (0x06UL) /*!< [23:16] sub1 version */ #define __STM32H7xx_HAL_VERSION_SUB2 (0x00UL) /*!< [15:8] sub2 version */ #define __STM32H7xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */ #define __STM32H7xx_HAL_VERSION ((__STM32H7xx_HAL_VERSION_MAIN << 24)\ @@ -63,9 +63,17 @@ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ -static __IO uint32_t uwTick; -static uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ -static HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ +/* Exported variables --------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Variables HAL Exported Variables + * @{ + */ +__IO uint32_t uwTick; +uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ +HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ +/** + * @} + */ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ @@ -125,13 +133,21 @@ static HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ */ HAL_StatusTypeDef HAL_Init(void) { + +#if defined(DUAL_CORE) && defined(CORE_CM4) + /* Configure Cortex-M4 Instruction cache through ART accelerator */ + __HAL_RCC_ART_CLK_ENABLE(); /* Enable the Cortex-M4 ART Clock */ + __HAL_ART_CONFIG_BASE_ADDRESS(0x08100000UL); /* Configure the Cortex-M4 ART Base address to the Flash Bank 2 : */ + __HAL_ART_ENABLE(); /* Enable the Cortex-M4 ART */ +#endif /* DUAL_CORE && CORE_CM4 */ + /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); - /* Update the SystemD2Clock global variable */ + /* Update the SystemD2Clock global variable */ SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ @@ -453,6 +469,33 @@ uint32_t HAL_GetDEVID(void) return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); } +/** + * @brief Return the first word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw0(void) +{ + return(READ_REG(*((uint32_t *)UID_BASE))); +} + +/** + * @brief Return the second word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw1(void) +{ + return(READ_REG(*((uint32_t *)(UID_BASE + 4U)))); +} + +/** + * @brief Return the third word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw2(void) +{ + return(READ_REG(*((uint32_t *)(UID_BASE + 8U)))); +} + /** * @brief Configure the internal voltage reference buffer voltage scale. * @param VoltageScaling specifies the output voltage to achieve diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal.h b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal.h index f9473206c84..094f7bfe8ee 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal.h +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal.h @@ -624,6 +624,31 @@ typedef enum /* Exported macro ------------------------------------------------------------*/ +/** @defgroup ART_Exported_Macros ART Exported Macros + * @{ + */ +#if defined(DUAL_CORE) + +/** @brief ART Enable Macro. + * Enable the Cortex-M4 ART cache. + */ +#define __HAL_ART_ENABLE() SET_BIT(ART->CTR, ART_CTR_EN) + +/** @brief ART Disable Macro. + * Disable the Cortex-M4 ART cache. + */ +#define __HAL_ART_DISABLE() CLEAR_BIT(ART->CTR, ART_CTR_EN) + +/** @brief ART Cache BaseAddress Config. + * Configure the Cortex-M4 ART cache Base Address. + */ +#define __HAL_ART_CONFIG_BASE_ADDRESS(__BASE_ADDRESS__) MODIFY_REG(ART->CTR, ART_CTR_PCACHEADDR, (((__BASE_ADDRESS__) >> 12U) & 0x000FFF00UL)) + +#endif /* DUAL_CORE */ +/** + * @} + */ + /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros * @{ */ @@ -874,6 +899,18 @@ typedef enum * @} */ +/* Exported variables --------------------------------------------------------*/ + +/** @addtogroup HAL_Exported_Variables + * @{ + */ +extern __IO uint32_t uwTick; +extern uint32_t uwTickPrio; +extern HAL_TickFreqTypeDef uwTickFreq; +/** + * @} + */ + /* Exported functions --------------------------------------------------------*/ /* Initialization and de-initialization functions ******************************/ @@ -895,6 +932,9 @@ void HAL_ResumeTick(void); uint32_t HAL_GetHalVersion(void); uint32_t HAL_GetREVID(void); uint32_t HAL_GetDEVID(void); +uint32_t HAL_GetUIDw0(void); +uint32_t HAL_GetUIDw1(void); +uint32_t HAL_GetUIDw2(void); void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface); void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState ); void HAL_SYSCFG_EnableBOOST(void); diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_adc.c b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_adc.c index 5a8d69ba6df..3212fb819d2 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_adc.c +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_adc.c @@ -2,7 +2,7 @@ ****************************************************************************** * @file stm32h7xx_hal_adc.c * @author MCD Application Team - * @brief This file provides firmware functions to manage the following + * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) * peripheral: * + Initialization and de-initialization functions @@ -16,7 +16,7 @@ * + State functions * ++ ADC state machine management * ++ Interrupts and flags management - * Other functions (extended functions) are available in file + * Other functions (extended functions) are available in file * "stm32h7xx_hal_adc_ex.c". * @verbatim @@ -26,33 +26,33 @@ [..] (+) 16-bit, 14-bit, 12-bit, 10-bit or 8-bit configurable resolution. - (+) Interrupt generation at the end of regular conversion and in case of + (+) Interrupt generation at the end of regular conversion and in case of analog watchdog or overrun events. - + (+) Single and continuous conversion modes. - + (+) Scan mode for conversion of several channels sequentially. - + (+) Data alignment with in-built data coherency. - + (+) Programmable sampling time (channel wise) - + (+) External trigger (timer or EXTI) with configurable polarity - + (+) DMA request generation for transfer of conversions data of regular group. - + (+) Configurable delay between conversions in Dual interleaved mode. - + (+) ADC channels selectable single/differential input. - + (+) ADC offset shared on 4 offset instances. (+) ADC calibration - + (+) ADC conversion of regular group. - + (+) ADC supply requirements: 1.62 V to 3.6 V. - - (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to + + (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to Vdda or to an external voltage reference). @@ -67,7 +67,7 @@ (#) Enable the ADC interface (++) As prerequisite, ADC clock must be configured at RCC top level. - (++) Two clock settings are mandatory: + (++) Two clock settings are mandatory: (+++) ADC clock (core clock, also possibly conversion clock). (+++) ADC clock (conversions clock). @@ -97,8 +97,8 @@ (#) Optionally, in case of usage of ADC with interruptions: (++) Configure the NVIC for ADC using function HAL_NVIC_EnableIRQ(ADCx_IRQn) - (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() - into the function of corresponding ADC interruption vector + (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() + into the function of corresponding ADC interruption vector ADCx_IRQHandler(). (#) Optionally, in case of usage of DMA: @@ -106,8 +106,8 @@ using function HAL_DMA_Init(). (++) Configure the NVIC for DMA using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) - (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() - into the function of corresponding DMA interruption vector + (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() + into the function of corresponding DMA interruption vector DMAx_Channelx_IRQHandler(). *** Configuration of ADC, group regular, channels parameters *** @@ -118,7 +118,7 @@ and regular group parameters (conversion trigger, sequencer, ...) using function HAL_ADC_Init(). - (#) Configure the channels for regular group parameters (channel number, + (#) Configure the channels for regular group parameters (channel number, channel rank into sequencer, ..., into regular group) using function HAL_ADC_ConfigChannel(). @@ -140,22 +140,22 @@ (++) ADC conversion by polling: (+++) Activate the ADC peripheral and start conversions using function HAL_ADC_Start() - (+++) Wait for ADC conversion completion + (+++) Wait for ADC conversion completion using function HAL_ADC_PollForConversion() - (+++) Retrieve conversion results + (+++) Retrieve conversion results using function HAL_ADC_GetValue() - (+++) Stop conversion and disable the ADC peripheral + (+++) Stop conversion and disable the ADC peripheral using function HAL_ADC_Stop() - (++) ADC conversion by interruption: + (++) ADC conversion by interruption: (+++) Activate the ADC peripheral and start conversions using function HAL_ADC_Start_IT() (+++) Wait for ADC conversion completion by call of function HAL_ADC_ConvCpltCallback() (this function must be implemented in user program) - (+++) Retrieve conversion results + (+++) Retrieve conversion results using function HAL_ADC_GetValue() - (+++) Stop conversion and disable the ADC peripheral + (+++) Stop conversion and disable the ADC peripheral using function HAL_ADC_Stop_IT() (++) ADC conversion with transfer by DMA: @@ -166,7 +166,7 @@ (these functions must be implemented in user program) (+++) Conversion results are automatically transferred by DMA into destination variable address. - (+++) Stop conversion and disable the ADC peripheral + (+++) Stop conversion and disable the ADC peripheral using function HAL_ADC_Stop_DMA() [..] @@ -212,7 +212,7 @@ using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) [..] - + *** Callback registration *** ============================================= [..] @@ -285,7 +285,7 @@ When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks are set to the corresponding weak functions. - + @endverbatim ****************************************************************************** * @attention @@ -298,7 +298,7 @@ * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * - ****************************************************************************** + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -326,19 +326,19 @@ ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\ ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated when no regular conversion is on-going */ - + #define ADC_CFGR2_FIELDS ((uint32_t)(ADC_CFGR2_ROVSE | ADC_CFGR2_OVSR |\ ADC_CFGR2_OVSS | ADC_CFGR2_TROVS |\ ADC_CFGR2_ROVSM)) /*!< ADC_CFGR2 fields of parameters that can be updated when no conversion (neither regular nor injected) is on-going */ - + /* Timeout values for ADC operations (enable settling time, */ /* disable settling time, ...). */ /* Values defined to be higher than worst cases: low clock frequency, */ /* maximum prescalers. */ #define ADC_ENABLE_TIMEOUT (2UL) /*!< ADC enable time-out value */ #define ADC_DISABLE_TIMEOUT (2UL) /*!< ADC disable time-out value */ - + /* Timeout to wait for current conversion on going to be completed. */ /* Timeout fixed to worst case, for 1 channel. */ /* - maximum sampling time (830.5 adc_clk) */ @@ -364,19 +364,19 @@ /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions * @brief ADC Initialization and Configuration functions * -@verbatim +@verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to: - (+) Initialize and configure the ADC. + (+) Initialize and configure the ADC. (+) De-initialize the ADC. @endverbatim * @{ */ /** - * @brief Initialize the ADC peripheral and regular group according to + * @brief Initialize the ADC peripheral and regular group according to * parameters specified in structure "ADC_InitTypeDef". * @note As prerequisite, ADC clock must be configured at RCC top level * (refer to description of RCC configuration for ADC @@ -384,26 +384,26 @@ * @note Possibility to update parameters on the fly: * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when * coming from ADC state reset. Following calls to this function can - * be used to reconfigure some parameters of ADC_InitTypeDef - * structure on the fly, without modifying MSP configuration. If ADC + * be used to reconfigure some parameters of ADC_InitTypeDef + * structure on the fly, without modifying MSP configuration. If ADC * MSP has to be modified again, HAL_ADC_DeInit() must be called * before HAL_ADC_Init(). * The setting of these parameters is conditioned to ADC state. - * For parameters constraints, see comments of structure + * For parameters constraints, see comments of structure * "ADC_InitTypeDef". - * @note This function configures the ADC within 2 scopes: scope of entire - * ADC and scope of regular group. For parameters details, see comments + * @note This function configures the ADC within 2 scopes: scope of entire + * ADC and scope of regular group. For parameters details, see comments * of structure "ADC_InitTypeDef". - * @note Parameters related to common ADC registers (ADC clock mode) are set + * @note Parameters related to common ADC registers (ADC clock mode) are set * only if all ADCs are disabled. - * If this is not the case, these common parameters setting are + * If this is not the case, these common parameters setting are * bypassed without error reporting: it can be the intended behaviour in * case of update of a parameter of ADC_InitTypeDef on the fly, * without disabling the other ADCs. * @param hadc ADC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmpCFGR; @@ -411,13 +411,13 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) __IO uint32_t wait_loop_index = 0UL; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; - + /* Check ADC handle */ - if(hadc == NULL) + if (hadc == NULL) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); @@ -431,24 +431,24 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode)); - - if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) + + if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) { assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); - - if(hadc->Init.DiscontinuousConvMode == ENABLE) + + if (hadc->Init.DiscontinuousConvMode == ENABLE) { assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion)); } } - + /* DISCEN and CONT bits cannot be set at the same time */ assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE))); - + /* Actions performed only if ADC is coming from state reset: */ /* - Initialization of ADC MSP */ - if(hadc->State == HAL_ADC_STATE_RESET) + if (hadc->State == HAL_ADC_STATE_RESET) { #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) /* Init the ADC Callback settings */ @@ -461,83 +461,83 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; /* Legacy weak callback */ hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; /* Legacy weak callback */ hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; /* Legacy weak callback */ - + if (hadc->MspInitCallback == NULL) { hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ } - + /* Init the low level hardware */ hadc->MspInitCallback(hadc); #else /* Init the low level hardware */ HAL_ADC_MspInit(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - + /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); - + /* Initialize Lock */ hadc->Lock = HAL_UNLOCKED; } - + /* - Exit from deep-power-down mode and ADC voltage regulator enable */ - if(LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL) + if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL) { - /* Disable ADC deep power down mode */ + /* Disable ADC deep power down mode */ LL_ADC_DisableDeepPowerDown(hadc->Instance); - + /* System was in deep power down mode, calibration must - be relaunched or a previously saved calibration factor - re-applied once the ADC voltage regulator is enabled */ + be relaunched or a previously saved calibration factor + re-applied once the ADC voltage regulator is enabled */ } - - if(LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) + + if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) { /* Enable ADC internal voltage regulator */ LL_ADC_EnableInternalRegulator(hadc->Instance); - + /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); - while(wait_loop_index != 0UL) + while (wait_loop_index != 0UL) { wait_loop_index--; } } - + /* Verification that ADC voltage regulator is correctly enabled, whether */ /* or not ADC is coming from state reset (if any potential problem of */ /* clocking, voltage regulator would not be enabled). */ - if(LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) + if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - + /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - + tmp_hal_status = HAL_ERROR; } - - /* Configuration of ADC parameters if previous preliminary actions are */ + + /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed and if there is no conversion on going on regular */ /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */ /* called to update a parameter on the fly). */ tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance); - - if( ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) - && (tmp_adc_reg_is_conversion_on_going == 0UL) - ) + + if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) + && (tmp_adc_reg_is_conversion_on_going == 0UL) + ) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); - + /* Configuration of common ADC parameters */ - + /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - clock configuration */ @@ -565,7 +565,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler); } } - + /* Configuration of ADC: */ /* - resolution Init.Resolution */ /* - external trigger to start conversion Init.ExternalTrigConv */ @@ -589,12 +589,13 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) hadc->Init.Resolution | ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode) ); } - + + if (hadc->Init.DiscontinuousConvMode == ENABLE) { tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion); } - + /* Enable external trigger if trigger selection is different of software */ /* start. */ /* Note: This configuration keeps the hardware feature of parameter */ @@ -602,14 +603,14 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* software start. */ if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) { - tmpCFGR |= ( (hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) + tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) | hadc->Init.ExternalTrigConvEdge ); } - + /* Update Configuration Register CFGR */ - MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR); - + MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR); + /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular and injected groups: */ @@ -618,23 +619,23 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* - Oversampling parameters Init.Oversampling */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); - if ( (tmp_adc_is_conversion_on_going_regular == 0UL) + if ((tmp_adc_is_conversion_on_going_regular == 0UL) && (tmp_adc_is_conversion_on_going_injected == 0UL) ) { tmpCFGR = ( - ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | - ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement) ); - + ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | + ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement)); + MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR); - + if (hadc->Init.OversamplingMode == ENABLE) { assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio)); assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift)); assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode)); assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset)); - + if ((hadc->Init.ExternalTrigConv == ADC_SOFTWARE_START) || (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE)) { @@ -650,7 +651,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* - Oversampling mode (continued/resumed) */ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS, ADC_CFGR2_ROVSE | - (hadc->Init.Oversampling.Ratio << 16) | + ((hadc->Init.Oversampling.Ratio - 1UL) << ADC_CFGR2_OVSR_Pos) | hadc->Init.Oversampling.RightBitShift | hadc->Init.Oversampling.TriggeredMode | hadc->Init.Oversampling.OversamplingStopReset); @@ -661,14 +662,14 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* Disable ADC oversampling scope on ADC group regular */ CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE); } - + /* Set the LeftShift parameter: it is applied to the final result with or without oversampling */ MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_LSHIFT, hadc->Init.LeftBitShift); /* Configure the BOOST Mode */ ADC_ConfigureBoostMode(hadc); } - + /* Configuration of regular group sequencer: */ /* - if scan mode is disabled, regular channels sequence length is set to */ /* 0x00: 1 channel converted (channel on regular rank 1) */ @@ -687,7 +688,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L); } - + /* Initialize the ADC state */ /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); @@ -696,10 +697,10 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - + tmp_hal_status = HAL_ERROR; } - + /* Return function status */ return tmp_hal_status; } @@ -707,40 +708,40 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /** * @brief Deinitialize the ADC peripheral registers to their default reset * values, with deinitialization of the ADC MSP. - * @note For devices with several ADCs: reset of ADC common registers is done + * @note For devices with several ADCs: reset of ADC common registers is done * only if all ADCs sharing the same common group are disabled. * (function "HAL_ADC_MspDeInit()" is also called under the same conditions: * all ADC instances use the same core clock at RCC level, disabling * the core clock reset all ADC instances). - * If this is not the case, reset of these common parameters reset is + * If this is not the case, reset of these common parameters reset is * bypassed without error reporting: it can be the intended behavior in - * case of reset of a single ADC while the other ADCs sharing the same + * case of reset of a single ADC while the other ADCs sharing the same * common group is still running. * @note By default, HAL_ADC_DeInit() set ADC in mode deep power-down: - * this saves more power by reducing leakage currents + * this saves more power by reducing leakage currents * and is particularly interesting before entering MCU low-power modes. * @param hadc ADC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; - + /* Check ADC handle */ - if(hadc == NULL) + if (hadc == NULL) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); - + /* Stop potential conversion on going */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); - + /* Disable ADC peripheral if conversions are effectively stopped */ /* Flush register JSQR: reset the queue sequencer when injected */ /* queue sequencer is enabled and ADC disabled. */ @@ -748,13 +749,13 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) /* internally disabled just after the completion of the last valid */ /* injected sequence. */ SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM); - + /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { /* Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); - + /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { @@ -762,36 +763,36 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) hadc->State = HAL_ADC_STATE_READY; } } - + /* Note: HAL ADC deInit is done independently of ADC conversion stop */ /* and disable return status. In case of status fail, attempt to */ /* perform deinitialization anyway and it is up user code in */ /* in HAL_ADC_MspDeInit() to reset the ADC peripheral using */ /* system RCC hard reset. */ - + /* ========== Reset ADC registers ========== */ /* Reset register IER */ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 | ADC_IT_JQOVF | ADC_IT_OVR | ADC_IT_JEOS | ADC_IT_JEOC | ADC_IT_EOS | ADC_IT_EOC | - ADC_IT_EOSMP | ADC_IT_RDY ) ); - + ADC_IT_EOSMP | ADC_IT_RDY)); + /* Reset register ISR */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 | ADC_FLAG_JQOVF | ADC_FLAG_OVR | ADC_FLAG_JEOS | ADC_FLAG_JEOC | ADC_FLAG_EOS | ADC_FLAG_EOC | - ADC_FLAG_EOSMP | ADC_FLAG_RDY ) ); - + ADC_FLAG_EOSMP | ADC_FLAG_RDY)); + /* Reset register CR */ - /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, - ADC_CR_ADCAL, ADC_CR_ADDIS and ADC_CR_ADEN are in access mode "read-set": - no direct reset applicable. - Update CR register to reset value where doable by software */ + /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, + ADC_CR_ADCAL, ADC_CR_ADDIS and ADC_CR_ADEN are in access mode "read-set": + no direct reset applicable. + Update CR register to reset value where doable by software */ CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF); - SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD); - + SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD); + /* Reset register CFGR */ CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM | @@ -799,20 +800,20 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD | ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_RES | ADC_CFGR_DMNGT); - SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); - + SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); + /* Reset register CFGR2 */ - CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS | - ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE ); - + CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS | + ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE); + /* Reset register SMPR1 */ - CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_FIELDS); - + CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_FIELDS); + /* Reset register SMPR2 */ - CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 | - ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 | - ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10 ); - + CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 | + ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 | + ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10); + /* Reset register LTR1 and HTR1 */ CLEAR_BIT(hadc->Instance->LTR1, ADC_LTR_LT); CLEAR_BIT(hadc->Instance->HTR1, ADC_HTR_HT); @@ -824,27 +825,27 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) /* Reset register LTR3 and HTR3 */ CLEAR_BIT(hadc->Instance->LTR3, ADC_LTR_LT); CLEAR_BIT(hadc->Instance->HTR3, ADC_HTR_HT); - + /* Reset register SQR1 */ - CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 | - ADC_SQR1_SQ1 | ADC_SQR1_L); - + CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 | + ADC_SQR1_SQ1 | ADC_SQR1_L); + /* Reset register SQR2 */ - CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 | - ADC_SQR2_SQ6 | ADC_SQR2_SQ5); - + CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 | + ADC_SQR2_SQ6 | ADC_SQR2_SQ5); + /* Reset register SQR3 */ - CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 | - ADC_SQR3_SQ11 | ADC_SQR3_SQ10); - + CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 | + ADC_SQR3_SQ11 | ADC_SQR3_SQ10); + /* Reset register SQR4 */ - CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15); - + CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15); + /* Register JSQR was reset when the ADC was disabled */ - + /* Reset register DR */ /* bits in access mode read only, no direct reset applicable*/ - + /* Reset register OFR1 */ CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1); /* Reset register OFR2 */ @@ -853,25 +854,25 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3); /* Reset register OFR4 */ CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4); - + /* Reset registers JDR1, JDR2, JDR3, JDR4 */ /* bits in access mode read only, no direct reset applicable*/ - + /* Reset register AWD2CR */ CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH); - + /* Reset register AWD3CR */ CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH); - + /* Reset register DIFSEL */ CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL); - + /* Reset register CALFACT */ CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S); - - + + /* ========== Reset common ADC registers ========== */ - + /* Software is allowed to change common parameters only when all the other ADCs are disabled. */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) @@ -886,43 +887,43 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc); } - /* DeInit the low level hardware. - + /* DeInit the low level hardware. + For example: __HAL_RCC_ADC_FORCE_RESET(); __HAL_RCC_ADC_RELEASE_RESET(); __HAL_RCC_ADC_CLK_DISABLE(); - + Keep in mind that all ADCs use the same clock: disabling - the clock will reset all ADCs. - + the clock will reset all ADCs. + */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) if (hadc->MspDeInitCallback == NULL) { hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ } - + /* DeInit the low level hardware: RCC clock, NVIC */ hadc->MspDeInitCallback(hadc); #else /* DeInit the low level hardware: RCC clock, NVIC */ HAL_ADC_MspDeInit(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - + /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); - + /* Reset injected channel configuration parameters */ hadc->InjectionConfig.ContextQueue = 0; - hadc->InjectionConfig.ChannelCount = 0; - + hadc->InjectionConfig.ChannelCount = 0; + /* Set ADC state */ hadc->State = HAL_ADC_STATE_RESET; - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -932,14 +933,14 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) * @param hadc ADC handle * @retval None */ -__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) +__weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_MspInit must be implemented in the user file. - */ + */ } /** @@ -949,14 +950,14 @@ __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) * the core clock reset all ADC instances). * @retval None */ -__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) +__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADC_MspDeInit must be implemented in the user file. - */ + */ } #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) @@ -984,7 +985,7 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; - + if (pCallback == NULL) { /* Update the error code */ @@ -992,7 +993,7 @@ HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Call return HAL_ERROR; } - + if ((hadc->State & HAL_ADC_STATE_READY) != 0UL) { switch (CallbackID) @@ -1000,47 +1001,47 @@ HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Call case HAL_ADC_CONVERSION_COMPLETE_CB_ID : hadc->ConvCpltCallback = pCallback; break; - + case HAL_ADC_CONVERSION_HALF_CB_ID : hadc->ConvHalfCpltCallback = pCallback; break; - + case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : hadc->LevelOutOfWindowCallback = pCallback; break; - + case HAL_ADC_ERROR_CB_ID : hadc->ErrorCallback = pCallback; break; - + case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : hadc->InjectedConvCpltCallback = pCallback; break; - + case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID : hadc->InjectedQueueOverflowCallback = pCallback; break; - + case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID : hadc->LevelOutOfWindow2Callback = pCallback; break; - + case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID : hadc->LevelOutOfWindow3Callback = pCallback; break; - + case HAL_ADC_END_OF_SAMPLING_CB_ID : hadc->EndOfSamplingCallback = pCallback; break; - + case HAL_ADC_MSPINIT_CB_ID : hadc->MspInitCallback = pCallback; break; - + case HAL_ADC_MSPDEINIT_CB_ID : hadc->MspDeInitCallback = pCallback; break; - + default : /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; @@ -1057,15 +1058,15 @@ HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Call case HAL_ADC_MSPINIT_CB_ID : hadc->MspInitCallback = pCallback; break; - + case HAL_ADC_MSPDEINIT_CB_ID : hadc->MspDeInitCallback = pCallback; break; - + default : /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; - + /* Return error status */ status = HAL_ERROR; break; @@ -1075,11 +1076,11 @@ HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Call { /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; - + /* Return error status */ status = HAL_ERROR; } - + return status; } @@ -1106,7 +1107,7 @@ HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Call HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; - + if ((hadc->State & HAL_ADC_STATE_READY) != 0UL) { switch (CallbackID) @@ -1114,51 +1115,51 @@ HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Ca case HAL_ADC_CONVERSION_COMPLETE_CB_ID : hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; break; - + case HAL_ADC_CONVERSION_HALF_CB_ID : hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; break; - + case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; break; - + case HAL_ADC_ERROR_CB_ID : hadc->ErrorCallback = HAL_ADC_ErrorCallback; break; - + case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; break; - + case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID : hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback; break; - + case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID : hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; break; - + case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID : hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; break; - + case HAL_ADC_END_OF_SAMPLING_CB_ID : hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; break; - + case HAL_ADC_MSPINIT_CB_ID : hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ break; - + case HAL_ADC_MSPDEINIT_CB_ID : hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ break; - + default : /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; - + /* Return error status */ status = HAL_ERROR; break; @@ -1171,15 +1172,15 @@ HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Ca case HAL_ADC_MSPINIT_CB_ID : hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ break; - + case HAL_ADC_MSPDEINIT_CB_ID : hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ break; - + default : /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; - + /* Return error status */ status = HAL_ERROR; break; @@ -1189,11 +1190,11 @@ HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Ca { /* Update the error code */ hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; - + /* Return error status */ status = HAL_ERROR; } - + return status; } @@ -1204,9 +1205,9 @@ HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Ca */ /** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions - * @brief ADC IO operation functions - * -@verbatim + * @brief ADC IO operation functions + * +@verbatim =============================================================================== ##### IO operation functions ##### =============================================================================== @@ -1228,30 +1229,30 @@ HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Ca /** * @brief Enable ADC, start conversion of regular group. * @note Interruptions enabled in this function: None. - * @note Case of multimode enabled (when multimode feature is available): - * if ADC is Slave, ADC is enabled but conversion is not started, + * @note Case of multimode enabled (when multimode feature is available): + * if ADC is Slave, ADC is enabled but conversion is not started, * if ADC is master, ADC is enabled and multimode conversion is started. * @param hadc ADC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; const ADC_TypeDef *tmpADC_Master; uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Perform ADC enable and conversion start if no conversion is on going */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { /* Process locked */ __HAL_LOCK(hadc); - + /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); - + /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { @@ -1261,39 +1262,39 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_BUSY); - + /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - if ADC instance is master or if multimode feature is not available - if multimode setting is disabled (ADC instance slave in independent mode) */ - if ( (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) - || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) ) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } - + /* Set ADC error code */ /* Check if a conversion is on going on ADC group injected */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { /* Reset ADC error code fields related to regular conversions only */ - CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); } else - { + { /* Reset all ADC error code fields */ - ADC_CLEAR_ERRORCODE(hadc); + ADC_CLEAR_ERRORCODE(hadc); } - + /* Clear ADC group regular conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); - + /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); - + /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ @@ -1302,18 +1303,18 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) /* - if ADC is slave and dual regular conversions are enabled, ADC is */ /* enabled only (conversion is not started), */ /* - if ADC is master, ADC is enabled and conversion is started. */ - if ( (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) - || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) - || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) - || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) ) { /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL) { - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } - + /* Start ADC group regular conversion */ LL_ADC_REG_StartConversion(hadc->Instance); } @@ -1321,14 +1322,14 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) { /* ADC instance is a multimode slave instance with multimode regular conversions enabled */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); - /* if Master ADC JAUTO bit is set, update Slave State in setting + /* if Master ADC JAUTO bit is set, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */ tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } - + } } else @@ -1341,39 +1342,39 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) { tmp_hal_status = HAL_BUSY; } - + /* Return function status */ return tmp_hal_status; } /** - * @brief Stop ADC conversion of regular group (and injected channels in + * @brief Stop ADC conversion of regular group (and injected channels in * case of auto_injection mode), disable ADC peripheral. - * @note: ADC peripheral disable is forcing stop of potential + * @note: ADC peripheral disable is forcing stop of potential * conversion on injected group. If injected group is under use, it * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. * @param hadc ADC handle * @retval HAL status. */ -HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Process locked */ __HAL_LOCK(hadc); - + /* 1. Stop potential conversion on going, on ADC groups regular and injected */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); - + /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { /* 2. Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); - + /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { @@ -1383,10 +1384,10 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) HAL_ADC_STATE_READY); } } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -1395,31 +1396,31 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) * @brief Wait for regular group conversion to be completed. * @note ADC conversion flags EOS (end of sequence) and EOC (end of * conversion) are cleared by this function, with an exception: - * if low power feature "LowPowerAutoWait" is enabled, flags are + * if low power feature "LowPowerAutoWait" is enabled, flags are * not cleared to not interfere with this feature until data register * is read using function HAL_ADC_GetValue(). - * @note This function cannot be used in a particular setup: ADC configured + * @note This function cannot be used in a particular setup: ADC configured * in DMA mode and polling for end of each conversion (ADC init * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). * In this case, DMA resets the flag EOC and polling cannot be - * performed on each conversion. Nevertheless, polling can still + * performed on each conversion. Nevertheless, polling can still * be performed on the complete sequence (ADC init * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV). * @param hadc ADC handle * @param Timeout Timeout value in millisecond. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) +HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout) { uint32_t tickstart; uint32_t tmp_Flag_End; uint32_t tmp_cfgr; const ADC_TypeDef *tmpADC_Master; uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* If end of conversion selected to end of sequence conversions */ if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) { @@ -1434,9 +1435,9 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti /* several ranks and polling for end of each conversion. */ /* For code simplicity sake, this particular case is generalized to */ /* ADC configured in DMA mode and and polling for end of each conversion. */ - if ( (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) - || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) - || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) + if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) ) { /* Check DMNGT bit in handle ADC CFGR register */ @@ -1464,58 +1465,58 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti } } } - + /* Get tick count */ tickstart = HAL_GetTick(); - + /* Wait until End of unitary conversion or sequence conversions flag is raised */ - while((hadc->Instance->ISR & tmp_Flag_End) == 0UL) + while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) { /* Check if timeout is disabled (set to infinite wait) */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + return HAL_TIMEOUT; } } } - + /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); - + /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ - if( (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) - && (hadc->Init.ContinuousConvMode == DISABLE) - ) + if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) + && (hadc->Init.ContinuousConvMode == DISABLE) + ) { /* Check whether end of sequence is reached */ - if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS)) { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - + if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } } - + /* Get relevant register CFGR in ADC instance of ADC master or slave */ /* in function of multimode state (for devices with multimode */ /* available). */ - if ( (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) - || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) - || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) - || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) ) { /* Retrieve handle ADC CFGR register */ @@ -1527,11 +1528,11 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); tmp_cfgr = READ_REG(tmpADC_Master->CFGR); } - + /* Clear polled flag */ if (tmp_Flag_End == ADC_FLAG_EOS) { - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS); + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS); } else { @@ -1543,7 +1544,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); } } - + /* Return function status */ return HAL_OK; } @@ -1561,131 +1562,131 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti * @arg @ref ADC_JQOVF_EVENT ADC Injected context queue overflow event * @param Timeout Timeout value in millisecond. * @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR. - * Indeed, the latter is reset only if hadc->Init.Overrun field is set - * to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten + * Indeed, the latter is reset only if hadc->Init.Overrun field is set + * to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten * by a new converted data as soon as OVR is cleared. * To reset OVR flag once the preserved data is retrieved, the user can resort - * to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); + * to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) +HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout) { uint32_t tickstart; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_EVENT_TYPE(EventType)); - + /* Get tick count */ tickstart = HAL_GetTick(); - + /* Check selected event flag */ - while(__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL) + while (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL) { /* Check if timeout is disabled (set to infinite wait) */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + return HAL_TIMEOUT; } } } - - switch(EventType) + + switch (EventType) { - /* End Of Sampling event */ - case ADC_EOSMP_EVENT: - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP); - - /* Clear the End Of Sampling flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP); - - break; - - /* Analog watchdog (level out of window) event */ - /* Note: In case of several analog watchdog enabled, if needed to know */ - /* which one triggered and on which ADCx, test ADC state of analog watchdog */ - /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()". */ - /* For example: */ - /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " */ - /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD2) != 0UL) " */ - /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD3) != 0UL) " */ - - /* Check analog watchdog 1 flag */ - case ADC_AWD_EVENT: - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); - - /* Clear ADC analog watchdog flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1); - - break; - - /* Check analog watchdog 2 flag */ - case ADC_AWD2_EVENT: - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_AWD2); - - /* Clear ADC analog watchdog flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2); - - break; - - /* Check analog watchdog 3 flag */ - case ADC_AWD3_EVENT: - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_AWD3); - - /* Clear ADC analog watchdog flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3); - - break; - - /* Injected context queue overflow event */ - case ADC_JQOVF_EVENT: - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF); - - /* Set ADC error code to Injected context queue overflow */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); - - /* Clear ADC Injected context queue overflow flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF); - - break; - - /* Overrun event */ - default: /* Case ADC_OVR_EVENT */ - /* If overrun is set to overwrite previous data, overrun event is not */ - /* considered as an error. */ - /* (cf ref manual "Managing conversions without using the DMA and without */ - /* overrun ") */ - if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) - { + /* End Of Sampling event */ + case ADC_EOSMP_EVENT: /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); - - /* Set ADC error code to overrun */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); - } - else - { - /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN - otherwise, data register is potentially overwritten by new converted data as soon - as OVR is cleared. */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); - } - break; + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP); + + /* Clear the End Of Sampling flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP); + + break; + + /* Analog watchdog (level out of window) event */ + /* Note: In case of several analog watchdog enabled, if needed to know */ + /* which one triggered and on which ADCx, test ADC state of analog watchdog */ + /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()". */ + /* For example: */ + /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " */ + /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD2) != 0UL) " */ + /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD3) != 0UL) " */ + + /* Check analog watchdog 1 flag */ + case ADC_AWD_EVENT: + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1); + + break; + + /* Check analog watchdog 2 flag */ + case ADC_AWD2_EVENT: + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD2); + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2); + + break; + + /* Check analog watchdog 3 flag */ + case ADC_AWD3_EVENT: + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD3); + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3); + + break; + + /* Injected context queue overflow event */ + case ADC_JQOVF_EVENT: + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF); + + /* Set ADC error code to Injected context queue overflow */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); + + /* Clear ADC Injected context queue overflow flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF); + + break; + + /* Overrun event */ + default: /* Case ADC_OVR_EVENT */ + /* If overrun is set to overwrite previous data, overrun event is not */ + /* considered as an error. */ + /* (cf ref manual "Managing conversions without using the DMA and without */ + /* overrun ") */ + if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); + + /* Set ADC error code to overrun */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); + } + else + { + /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN + otherwise, data register is potentially overwritten by new converted data as soon + as OVR is cleared. */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); + } + break; } - + /* Return function status */ return HAL_OK; } @@ -1693,44 +1694,44 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy /** * @brief Enable ADC, start conversion of regular group with interruption. * @note Interruptions enabled in this function according to initialization - * setting : EOC (end of conversion), EOS (end of sequence), + * setting : EOC (end of conversion), EOS (end of sequence), * OVR overrun. * Each of these interruptions has its dedicated callback function. - * @note Case of multimode enabled (when multimode feature is available): + * @note Case of multimode enabled (when multimode feature is available): * HAL_ADC_Start_IT() must be called for ADC Slave first, then for * ADC Master. - * For ADC Slave, ADC is enabled only (conversion is not started). + * For ADC Slave, ADC is enabled only (conversion is not started). * For ADC Master, ADC is enabled and multimode conversion is started. * @note To guarantee a proper reset of all interruptions once all the needed - * conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure + * conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure * a correct stop of the IT-based conversions. - * @note By default, HAL_ADC_Start_IT() does not enable the End Of Sampling + * @note By default, HAL_ADC_Start_IT() does not enable the End Of Sampling * interruption. If required (e.g. in case of oversampling with trigger * mode), the user must: - * 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP) - * 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP) + * 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP) + * 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP) * before calling HAL_ADC_Start_IT(). * @param hadc ADC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; const ADC_TypeDef *tmpADC_Master; uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Perform ADC enable and conversion start if no conversion is on going */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { /* Process locked */ __HAL_LOCK(hadc); - + /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); - + /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { @@ -1740,44 +1741,44 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_BUSY); - + /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - if ADC instance is master or if multimode feature is not available - if multimode setting is disabled (ADC instance slave in independent mode) */ - if ( (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) - || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) ) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } - + /* Set ADC error code */ /* Check if a conversion is on going on ADC group injected */ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL) { /* Reset ADC error code fields related to regular conversions only */ - CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR|HAL_ADC_ERROR_DMA)); + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); } else { /* Reset all ADC error code fields */ - ADC_CLEAR_ERRORCODE(hadc); + ADC_CLEAR_ERRORCODE(hadc); } - + /* Clear ADC group regular conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); - + /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); - + /* Disable all interruptions before enabling the desired ones */ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); - + /* Enable ADC end of conversion interrupt */ - switch(hadc->Init.EOCSelection) + switch (hadc->Init.EOCSelection) { case ADC_EOC_SEQ_CONV: __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS); @@ -1787,53 +1788,53 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC); break; } - + /* Enable ADC overrun interrupt */ /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is ADC_IT_OVR enabled; otherwise data overwrite is considered as normal behavior and no CPU time is lost for a non-processed interruption */ if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) { - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); } - + /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ - /* Case of multimode enabled (when multimode feature is available): */ + /* Case of multimode enabled (when multimode feature is available): */ /* - if ADC is slave and dual regular conversions are enabled, ADC is */ /* enabled only (conversion is not started), */ /* - if ADC is master, ADC is enabled and conversion is started. */ - if ( (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) - || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) - || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) - || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) ) { /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */ if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); - - /* Enable as well injected interruptions in case + + /* Enable as well injected interruptions in case HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This allows to start regular and injected conversions when JAUTO is set with a single call to HAL_ADC_Start_IT() */ - switch(hadc->Init.EOCSelection) + switch (hadc->Init.EOCSelection) { - case ADC_EOC_SEQ_CONV: + case ADC_EOC_SEQ_CONV: __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS); - break; + break; /* case ADC_EOC_SINGLE_CONV */ default: - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); - break; + break; } } - + /* Start ADC group regular conversion */ LL_ADC_REG_StartConversion(hadc->Instance); } @@ -1846,21 +1847,21 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL) { - /* First, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit + /* First, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); /* Next, set Slave injected interruptions */ - switch(hadc->Init.EOCSelection) + switch (hadc->Init.EOCSelection) { case ADC_EOC_SEQ_CONV: __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS); - break; + break; /* case ADC_EOC_SINGLE_CONV */ default: __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); - break; + break; } } } @@ -1870,47 +1871,47 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) /* Process unlocked */ __HAL_UNLOCK(hadc); } - + } else { tmp_hal_status = HAL_BUSY; } - + /* Return function status */ return tmp_hal_status; } /** - * @brief Stop ADC conversion of regular group (and injected group in - * case of auto_injection mode), disable interrution of + * @brief Stop ADC conversion of regular group (and injected group in + * case of auto_injection mode), disable interrution of * end-of-conversion, disable ADC peripheral. * @param hadc ADC handle * @retval HAL status. */ -HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Process locked */ __HAL_LOCK(hadc); - + /* 1. Stop potential conversion on going, on ADC groups regular and injected */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); - + /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { /* Disable ADC end of conversion interrupt for regular group */ /* Disable ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); - + /* 2. Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); - + /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { @@ -1920,10 +1921,10 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) HAL_ADC_STATE_READY); } } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -1931,40 +1932,40 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) /** * @brief Enable ADC, start conversion of regular group and transfer result through DMA. * @note Interruptions enabled in this function: - * overrun (if applicable), DMA half transfer, DMA transfer complete. + * overrun (if applicable), DMA half transfer, DMA transfer complete. * Each of these interruptions has its dedicated callback function. - * @note Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_DMA() - * is designed for single-ADC mode only. For multimode, the dedicated + * @note Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_DMA() + * is designed for single-ADC mode only. For multimode, the dedicated * HAL_ADCEx_MultiModeStart_DMA() function must be used. * @param hadc ADC handle * @param pData Destination Buffer address. * @param Length Number of data to be transferred from ADC peripheral to memory * @retval HAL status. */ -HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) +HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) { HAL_StatusTypeDef tmp_hal_status; uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Perform ADC enable and conversion start if no conversion is on going */ if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { /* Process locked */ __HAL_LOCK(hadc); - + /* Ensure that multimode regular conversions are not enabled. */ /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used. */ - if ( (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) - || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) - || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) + if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) ) { /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); - + /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { @@ -1974,61 +1975,61 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, HAL_ADC_STATE_REG_BUSY); - + /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - if ADC instance is master or if multimode feature is not available - if multimode setting is disabled (ADC instance slave in independent mode) */ - if ( (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) - || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) ) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } - + /* Check if a conversion is on going on ADC group injected */ if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL) { /* Reset ADC error code fields related to regular conversions only */ - CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); } else - { + { /* Reset all ADC error code fields */ - ADC_CLEAR_ERRORCODE(hadc); + ADC_CLEAR_ERRORCODE(hadc); } - + /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; - + /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; - + /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; - - + + /* Manage ADC and DMA start: ADC overrun interruption, DMA start, */ /* ADC start (in case of SW start): */ - + /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC */ /* operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); - + /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); - - /* With DMA, overrun event is always considered as an error even if - hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore, + + /* With DMA, overrun event is always considered as an error even if + hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore, ADC_IT_OVR is enabled. */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); - - + + /* Start the DMA channel */ tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); - + /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ @@ -2041,7 +2042,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui /* Process unlocked */ __HAL_UNLOCK(hadc); } - + } else { @@ -2054,49 +2055,49 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui { tmp_hal_status = HAL_BUSY; } - + /* Return function status */ return tmp_hal_status; } /** - * @brief Stop ADC conversion of regular group (and injected group in - * case of auto_injection mode), disable ADC DMA transfer, disable + * @brief Stop ADC conversion of regular group (and injected group in + * case of auto_injection mode), disable ADC DMA transfer, disable * ADC peripheral. * @note: ADC peripheral disable is forcing stop of potential * conversion on ADC group injected. If ADC group injected is under use, it * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. - * @note Case of multimode enabled (when multimode feature is available): - * HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only. + * @note Case of multimode enabled (when multimode feature is available): + * HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only. * For multimode, the dedicated HAL_ADCEx_MultiModeStop_DMA() API must be used. * @param hadc ADC handle * @retval HAL status. */ -HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Process locked */ __HAL_LOCK(hadc); - + /* 1. Stop potential ADC group regular conversion on going */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); - + /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { /* Disable ADC DMA (ADC DMA configuration of continous requests is kept) */ MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_DMNGT_0 |ADC_CFGR_DMNGT_1, 0UL); - + /* Disable the DMA channel (in case of DMA in circular mode or stop */ /* while DMA transfer is on going) */ - if(hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY) + if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY) { tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); - + /* Check if DMA channel effectively disabled */ if (tmp_hal_status != HAL_OK) { @@ -2104,10 +2105,10 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); } } - + /* Disable ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); - + /* 2. Disable the ADC peripheral */ /* Update "tmp_hal_status" only if DMA channel disabling passed, */ /* to keep in memory a potential failing status. */ @@ -2128,12 +2129,12 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } - + } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -2142,7 +2143,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) * @brief Get ADC regular group conversion result. * @note Reading register DR automatically clears ADC flag EOC * (ADC group regular end of unitary conversion). - * @note This function does not clear ADC flag EOS + * @note This function does not clear ADC flag EOS * (ADC group regular end of sequence conversion). * Occurrence of flag EOS rising: * - If sequencer is composed of 1 rank, flag EOS is equivalent @@ -2157,15 +2158,15 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) * @param hadc ADC handle * @retval ADC group regular conversion data */ -uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) +uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Note: EOC flag is not cleared here by software because automatically */ /* cleared by hardware when reading register DR. */ - - /* Return ADC converted value */ + + /* Return ADC converted value */ return hadc->Instance->DR; } @@ -2174,7 +2175,7 @@ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) * @param hadc ADC handle * @retval None */ -void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) +void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) { uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */ uint32_t tmp_isr = hadc->Instance->ISR; @@ -2184,13 +2185,13 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) uint32_t tmp_cfgr; const ADC_TypeDef *tmpADC_Master; uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); - + /* ========== Check End of Sampling flag for ADC group regular ========== */ - if(((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP)) + if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP)) { /* Update state machine on end of sampling status if not in error state */ if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) @@ -2198,21 +2199,21 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP); } - + /* End Of Sampling callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->EndOfSamplingCallback(hadc); #else HAL_ADCEx_EndOfSamplingCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - + /* Clear regular group conversion flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP ); + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP); } - + /* ====== Check ADC group regular end of unitary conversion sequence conversions ===== */ - if((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) || - (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)) ) + if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) || + (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS))) { /* Update state machine on conversion status if not in error state */ if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) @@ -2220,19 +2221,19 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); } - + /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going */ /* to disable interruption. */ - if(LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) + if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) { /* Get relevant register CFGR in ADC instance of ADC master or slave */ /* in function of multimode state (for devices with multimode */ /* available). */ - if ( (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) - || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) - || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) - || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN) ) { /* check CONT bit directly in handle ADC CFGR register */ @@ -2244,12 +2245,12 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); tmp_cfgr = READ_REG(tmpADC_Master->CFGR); } - + /* Carry on if continuous mode is disabled */ - if (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT) + if (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT) { /* If End of Sequence is reached, disable interrupts */ - if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS)) { /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ /* ADSTART==0 (no conversion on going) */ @@ -2260,27 +2261,27 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* HAL_Start_IT(), but is not disabled here because can be used */ /* by overrun IRQ process below. */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); - + /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - + if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); - } + } } else { /* Change ADC state to error state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - + /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); } } } } - + /* Conversion complete callback */ /* Note: Into callback function "HAL_ADC_ConvCpltCallback()", */ /* to determine if conversion has been triggered from EOC or EOS, */ @@ -2291,18 +2292,18 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) #else HAL_ADC_ConvCpltCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - + /* Clear regular group conversion flag */ /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */ /* conversion flags clear induces the release of the preserved data.*/ /* Therefore, if the preserved data value is needed, it must be */ /* read preliminarily into HAL_ADC_ConvCpltCallback(). */ - __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) ); + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); } - + /* ====== Check ADC group injected end of unitary conversion sequence conversions ===== */ - if( (((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) || - (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)) ) + if ((((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) || + (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS))) { /* Update state machine on conversion status if not in error state */ if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) @@ -2310,17 +2311,17 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); } - + /* Retrieve ADC configuration */ tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance); tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance); /* Get relevant register CFGR in ADC instance of ADC master or slave */ /* in function of multimode state (for devices with multimode */ /* available). */ - if ( (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) - || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) - || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) - || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL) + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL) ) { tmp_cfgr = READ_REG(hadc->Instance->CFGR); @@ -2330,19 +2331,19 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); tmp_cfgr = READ_REG(tmpADC_Master->CFGR); } - + /* Disable interruption if no further conversion upcoming by injected */ /* external trigger or by automatic injected conversion with regular */ /* group having no further conversion upcoming (same conditions as */ /* regular group interruption disabling above), */ /* and if injected scan sequence is completed. */ - if((tmp_adc_inj_is_trigger_source_sw_start != 0UL) || - ((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) && - ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) && - (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == 0UL) ) ) ) + if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL) || + ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) && + ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) && + (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL)))) { /* If End of Sequence is reached, disable interrupts */ - if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) { /* Particular case if injected contexts queue is enabled: */ /* when the last context has been fully processed, JSQR is reset */ @@ -2350,7 +2351,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* (queue empty, triggers are ignored), it can start again */ /* immediately after setting a new context (JADSTART is still set). */ /* Therefore, state of HAL ADC injected group is kept to busy. */ - if(READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL) + if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL) { /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */ /* JADSTART==0 (no conversion on going) */ @@ -2358,12 +2359,12 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) { /* Disable ADC end of sequence conversion interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS); - + /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL) - { + { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } @@ -2371,83 +2372,83 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - + /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); } } } } - + /* Injected Conversion complete callback */ - /* Note: HAL_ADCEx_InjectedConvCpltCallback can resort to + /* Note: HAL_ADCEx_InjectedConvCpltCallback can resort to if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether - interruption has been triggered by end of conversion or end of - sequence. */ + interruption has been triggered by end of conversion or end of + sequence. */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->InjectedConvCpltCallback(hadc); #else HAL_ADCEx_InjectedConvCpltCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - + /* Clear injected group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS); } - + /* ========== Check Analog watchdog 1 flag ========== */ - if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1)) + if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1)) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); - + /* Level out of window 1 callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->LevelOutOfWindowCallback(hadc); #else HAL_ADC_LevelOutOfWindowCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - - /* Clear ADC analog watchdog flag */ + + /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1); } - + /* ========== Check analog watchdog 2 flag ========== */ - if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2)) + if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2)) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD2); - + /* Level out of window 2 callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->LevelOutOfWindow2Callback(hadc); #else HAL_ADCEx_LevelOutOfWindow2Callback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - - /* Clear ADC analog watchdog flag */ + + /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2); } - + /* ========== Check analog watchdog 3 flag ========== */ - if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3)) + if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3)) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD3); - + /* Level out of window 3 callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->LevelOutOfWindow3Callback(hadc); #else HAL_ADCEx_LevelOutOfWindow3Callback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - - /* Clear ADC analog watchdog flag */ + + /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3); } - + /* ========== Check Overrun flag ========== */ - if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR)) + if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR)) { /* If overrun is set to overwrite previous data (default setting), */ /* overrun event is not considered as an error. */ @@ -2464,7 +2465,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* Check DMA configuration */ if (tmp_multimode_config != LL_ADC_MULTI_INDEPENDENT) { - /* Multimode (when feature is available) is enabled, + /* Multimode (when feature is available) is enabled, Common Control Register MDMA bits must be checked. */ if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC) { @@ -2480,15 +2481,15 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) } } } - + if (overrun_error == 1UL) { /* Change ADC state to error state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); - + /* Set ADC error code to overrun */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); - + /* Error callback */ /* Note: In case of overrun, ADC conversion data is preserved until */ /* flag OVR is reset. */ @@ -2500,23 +2501,23 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) HAL_ADC_ErrorCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } - + /* Clear ADC overrun flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); } - + /* ========== Check Injected context queue overflow flag ========== */ - if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF)) + if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF)) { /* Change ADC state to overrun state */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF); - + /* Set ADC error code to Injected context queue overflow */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); - + /* Clear the Injected context queue overflow flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF); - + /* Injected context queue overflow callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->InjectedQueueOverflowCallback(hadc); @@ -2524,7 +2525,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) HAL_ADCEx_InjectedQueueOverflowCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } - + } /** @@ -2532,7 +2533,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) * @param hadc ADC handle * @retval None */ -__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) +__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); @@ -2547,7 +2548,7 @@ __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) * @param hadc ADC handle * @retval None */ -__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) +__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); @@ -2562,7 +2563,7 @@ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) * @param hadc ADC handle * @retval None */ -__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) +__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); @@ -2575,7 +2576,7 @@ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) /** * @brief ADC error callback in non-blocking mode * (ADC conversion with interruption or transfer by DMA). - * @note In case of error due to overrun when using ADC with DMA transfer + * @note In case of error due to overrun when using ADC with DMA transfer * (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"): * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()". * - If needed, restart a new ADC conversion using function @@ -2599,16 +2600,16 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) */ /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim + * @brief Peripheral Control functions + * +@verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Configure channels on regular group (+) Configure the analog watchdog - + @endverbatim * @{ */ @@ -2617,7 +2618,7 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) * @brief Configure a channel to be assigned to ADC group regular. * @note In case of usage of internal measurement channels: * Vbat/VrefInt/TempSensor. - * These internal paths can be disabled using function + * These internal paths can be disabled using function * HAL_ADC_DeInit(). * @note Possibility to update parameters on the fly: * This function initializes channel into ADC group regular, @@ -2630,7 +2631,7 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) * @param sConfig Structure of ADC channel assigned to ADC group regular. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmpOffsetShifted; @@ -2638,7 +2639,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf __IO uint32_t wait_loop_index = 0; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); @@ -2654,11 +2655,11 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf { assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset)); } - - /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is + + /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is ignored (considered as reset) */ - assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE))); - + assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE))); + /* Verification of channel number */ if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED) { @@ -2680,10 +2681,10 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf assert_param(IS_ADC3_DIFF_CHANNEL(sConfig->Channel)); } } - + /* Process locked */ __HAL_LOCK(hadc); - + /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ @@ -2693,10 +2694,10 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf { /* ADC channels preselection */ hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL)); - + /* Set ADC group regular sequence: channel on the selected scan sequence rank */ LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel); - + /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ @@ -2704,28 +2705,32 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf /* - Channel offset */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); - if ( (tmp_adc_is_conversion_on_going_regular == 0UL) + if ((tmp_adc_is_conversion_on_going_regular == 0UL) && (tmp_adc_is_conversion_on_going_injected == 0UL) ) { /* Set sampling time of the selected ADC channel */ LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime); - + /* Configure the offset: offset enable/disable, channel, offset value */ /* Shift the offset with respect to the selected ADC resolution. */ /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset); - - if(sConfig->OffsetNumber != ADC_OFFSET_NONE) + + if (sConfig->OffsetNumber != ADC_OFFSET_NONE) { /* Set ADC selected offset number */ LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted); - + assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetSignedSaturation)); /* Set ADC selected offset signed saturation */ LL_ADC_SetOffsetSignedSaturation(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); - + + assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetRightShift)); + /* Set ADC selected offset right shift */ + LL_ADC_SetDataRightShift(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetRightShift == ENABLE) ? LL_ADC_OFFSET_RSHIFT_ENABLE : LL_ADC_OFFSET_RSHIFT_DISABLE); + } else { @@ -2750,7 +2755,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf } } } - + /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - Single or differential mode */ @@ -2759,27 +2764,29 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf { /* Set mode single-ended or differential input of the selected ADC channel */ LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff); - + /* Configuration of differential mode */ if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED) { /* Set sampling time of the selected ADC channel */ /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */ - LL_ADC_SetChannelSamplingTime(hadc->Instance, (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), sConfig->SamplingTime); + LL_ADC_SetChannelSamplingTime(hadc->Instance, + (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)), + sConfig->SamplingTime); } - + /* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */ /* If internal channel selected, enable dedicated internal buffers and */ /* paths. */ /* Note: these internal measurement paths can be disabled using */ /* HAL_ADC_DeInit(). */ - + if(__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) { /* Configuration of common ADC parameters */ - + tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); - + /* Software is allowed to change common parameters only when all ADCs */ /* of the common group are disabled. */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) @@ -2791,7 +2798,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel); - + /* Delay for temperature sensor stabilization time */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ @@ -2826,17 +2833,17 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf /* If the requested internal measurement path has already been */ /* enabled and other ADC of the common group are enabled, internal */ /* measurement paths cannot be enabled. */ - else + else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - + tmp_hal_status = HAL_ERROR; } } } } - + /* If a conversion is on going on regular group, no update on regular */ /* channel could be done on neither of the channel configuration structure */ /* parameters. */ @@ -2844,13 +2851,13 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - + tmp_hal_status = HAL_ERROR; } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -2858,12 +2865,12 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf /** * @brief Configure the analog watchdog. * @note Possibility to update parameters on the fly: - * This function initializes the selected analog watchdog, successive - * calls to this function can be used to reconfigure some parameters - * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting + * This function initializes the selected analog watchdog, successive + * calls to this function can be used to reconfigure some parameters + * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting * the ADC. * The setting of these parameters is conditioned to ADC state. - * For parameters constraints, see comments of structure + * For parameters constraints, see comments of structure * "ADC_AnalogWDGConfTypeDef". * @note On this STM32 serie, analog watchdog thresholds cannot be modified * while ADC conversion is on going. @@ -2871,27 +2878,27 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf * @param AnalogWDGConfig Structure of ADC analog watchdog configuration * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmpAWDHighThresholdShifted; uint32_t tmpAWDLowThresholdShifted; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber)); assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode)); assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); - - if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) || - (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || - (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) ) + + if ((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) || + (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || + (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)) { assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); } - + /* Verify thresholds range */ if (hadc->Init.OversamplingMode == ENABLE) { @@ -2906,10 +2913,10 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold)); assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold)); } - + /* Process locked */ __HAL_LOCK(hadc); - + /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on ADC groups regular and injected: */ @@ -2917,68 +2924,71 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG /* - Analog watchdog thresholds */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); - if ( (tmp_adc_is_conversion_on_going_regular == 0UL) + if ((tmp_adc_is_conversion_on_going_regular == 0UL) && (tmp_adc_is_conversion_on_going_injected == 0UL) ) { /* Analog watchdog configuration */ - if(AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) + if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) { /* Configuration of analog watchdog: */ /* - Set the analog watchdog enable mode: one or overall group of */ /* channels, on groups regular and-or injected. */ - switch(AnalogWDGConfig->WatchdogMode) + switch (AnalogWDGConfig->WatchdogMode) { case ADC_ANALOGWATCHDOG_SINGLE_REG: - LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, LL_ADC_GROUP_REGULAR)); + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, + LL_ADC_GROUP_REGULAR)); break; - + case ADC_ANALOGWATCHDOG_SINGLE_INJEC: - LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, LL_ADC_GROUP_INJECTED)); + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, + LL_ADC_GROUP_INJECTED)); break; - + case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC: - LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, LL_ADC_GROUP_REGULAR_INJECTED)); + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, + LL_ADC_GROUP_REGULAR_INJECTED)); break; - + case ADC_ANALOGWATCHDOG_ALL_REG: LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG); break; - + case ADC_ANALOGWATCHDOG_ALL_INJEC: LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_INJ); break; - + case ADC_ANALOGWATCHDOG_ALL_REGINJEC: LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG_INJ); break; - + default: /* ADC_ANALOGWATCHDOG_NONE */ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_DISABLE); break; } - + /* Shift the offset in function of the selected ADC resolution: */ /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */ - /* are set to 0 */ + /* are set to 0 */ tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold); tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold); - + /* Set the high and low thresholds */ MODIFY_REG(hadc->Instance->LTR1, ADC_LTR_LT , tmpAWDLowThresholdShifted); MODIFY_REG(hadc->Instance->HTR1, ADC_HTR_HT , tmpAWDHighThresholdShifted); - + /* Update state, clear previous result related to AWD1 */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1); - + /* Clear flag ADC analog watchdog */ /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ /* (in case left enabled by previous ADC operations). */ LL_ADC_ClearFlag_AWD1(hadc->Instance); - + /* Configure ADC analog watchdog interrupt */ - if(AnalogWDGConfig->ITMode == ENABLE) + if (AnalogWDGConfig->ITMode == ENABLE) { LL_ADC_EnableIT_AWD1(hadc->Instance); } @@ -2990,7 +3000,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */ else { - switch(AnalogWDGConfig->WatchdogMode) + switch (AnalogWDGConfig->WatchdogMode) { case ADC_ANALOGWATCHDOG_SINGLE_REG: case ADC_ANALOGWATCHDOG_SINGLE_INJEC: @@ -3006,7 +3016,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG SET_BIT(hadc->Instance->AWD3CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL))); } break; - + case ADC_ANALOGWATCHDOG_ALL_REG: case ADC_ANALOGWATCHDOG_ALL_INJEC: case ADC_ANALOGWATCHDOG_ALL_REGINJEC: @@ -3021,17 +3031,17 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG SET_BIT(hadc->Instance->AWD3CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL))); } break; - + default: /* ADC_ANALOGWATCHDOG_NONE */ LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE); break; } - + /* Shift the thresholds in function of the selected ADC resolution */ /* have to be left-aligned on bit 15, the LSB (right bits) are set to 0 */ tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold); tmpAWDLowThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold); - + if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) { /* Set ADC analog watchdog thresholds value of both thresholds high and low */ @@ -3044,20 +3054,20 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG MODIFY_REG(hadc->Instance->LTR3, ADC_LTR_LT , tmpAWDLowThresholdShifted); MODIFY_REG(hadc->Instance->HTR3, ADC_HTR_HT , tmpAWDHighThresholdShifted); } - + if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) { /* Update state, clear previous result related to AWD2 */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2); - + /* Clear flag ADC analog watchdog */ /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ /* (in case left enabled by previous ADC operations). */ LL_ADC_ClearFlag_AWD2(hadc->Instance); - + /* Configure ADC analog watchdog interrupt */ - if(AnalogWDGConfig->ITMode == ENABLE) + if (AnalogWDGConfig->ITMode == ENABLE) { LL_ADC_EnableIT_AWD2(hadc->Instance); } @@ -3071,15 +3081,15 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG { /* Update state, clear previous result related to AWD3 */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3); - + /* Clear flag ADC analog watchdog */ /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ /* (in case left enabled by previous ADC operations). */ LL_ADC_ClearFlag_AWD3(hadc->Instance); - + /* Configure ADC analog watchdog interrupt */ - if(AnalogWDGConfig->ITMode == ENABLE) + if (AnalogWDGConfig->ITMode == ENABLE) { LL_ADC_EnableIT_AWD3(hadc->Instance); } @@ -3089,7 +3099,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG } } } - + } /* If a conversion is on going on ADC group regular or injected, no update */ /* could be done on neither of the AWD configuration structure parameters. */ @@ -3097,12 +3107,12 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - + tmp_hal_status = HAL_ERROR; } /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -3113,14 +3123,14 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG */ /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions - * @brief ADC Peripheral State functions - * + * @brief ADC Peripheral State functions + * @verbatim =============================================================================== ##### Peripheral state and errors functions ##### =============================================================================== [..] - This subsection provides functions to get in run-time the status of the + This subsection provides functions to get in run-time the status of the peripheral. (+) Check the ADC state (+) Check the ADC error code @@ -3131,19 +3141,19 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG /** * @brief Return the ADC handle state. - * @note ADC state machine is managed by bitfields, ADC status must be + * @note ADC state machine is managed by bitfields, ADC status must be * compared with states bits. - * For example: + * For example: * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " * @param hadc ADC handle * @retval ADC handle state (bitfield on 32 bits) */ -uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) +uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Return ADC handle state */ return hadc->State; } @@ -3157,7 +3167,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + return hadc->ErrorCode; } @@ -3183,7 +3193,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) * @arg @ref ADC_REGULAR_INJECTED_GROUP ADC regular and injected conversion type. * @retval HAL status. */ -HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup) +HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup) { uint32_t tickstart; uint32_t Conversion_Timeout_CPU_cycles = 0UL; @@ -3191,16 +3201,16 @@ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t Conversio uint32_t tmp_ADC_CR_ADSTART_JADSTART; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup)); - + /* Verification if ADC is not already stopped (on regular and injected */ /* groups) to bypass this function if not needed. */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); - if ( (tmp_adc_is_conversion_on_going_regular != 0UL) + if ((tmp_adc_is_conversion_on_going_regular != 0UL) || (tmp_adc_is_conversion_on_going_injected != 0UL) ) { @@ -3210,34 +3220,34 @@ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t Conversio /* injected group stop ADC_CR_JADSTP). */ /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1 */ /* (see reference manual). */ - if ( ((hadc->Instance->CFGR & ADC_CFGR_JAUTO) != 0UL) - && (hadc->Init.ContinuousConvMode == ENABLE) - && (hadc->Init.LowPowerAutoWait == ENABLE) + if (((hadc->Instance->CFGR & ADC_CFGR_JAUTO) != 0UL) + && (hadc->Init.ContinuousConvMode == ENABLE) + && (hadc->Init.LowPowerAutoWait == ENABLE) ) { /* Use stop of regular group */ conversion_group_reassigned = ADC_REGULAR_GROUP; - + /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */ - while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL) + while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL) { if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES * 4UL)) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - + /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - + return HAL_ERROR; } Conversion_Timeout_CPU_cycles ++; } - + /* Clear JEOS */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS); } - + /* Stop potential conversion on going on ADC group regular */ if (conversion_group_reassigned != ADC_INJECTED_GROUP) { @@ -3251,7 +3261,7 @@ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t Conversio } } } - + /* Stop potential conversion on going on ADC group injected */ if (conversion_group_reassigned != ADC_REGULAR_GROUP) { @@ -3265,41 +3275,41 @@ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t Conversio } } } - + /* Selection of start and stop bits with respect to the regular or injected group */ - switch(conversion_group_reassigned) + switch (conversion_group_reassigned) { - case ADC_REGULAR_INJECTED_GROUP: + case ADC_REGULAR_INJECTED_GROUP: tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART); break; - case ADC_INJECTED_GROUP: + case ADC_INJECTED_GROUP: tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART; break; - /* Case ADC_REGULAR_GROUP only*/ - default: + /* Case ADC_REGULAR_GROUP only*/ + default: tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART; break; } - + /* Wait for conversion effectively stopped */ tickstart = HAL_GetTick(); - - while((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL) + + while ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL) { - if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT) + if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - + /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - + return HAL_ERROR; } } - + } - + /* Return HAL status */ return HAL_OK; } @@ -3313,10 +3323,10 @@ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t Conversio * @param hadc ADC handle * @retval HAL status. */ -HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) { uint32_t tickstart; - + /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ @@ -3328,19 +3338,19 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - + /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - + return HAL_ERROR; } - + /* Enable the ADC peripheral */ LL_ADC_Enable(hadc->Instance); - + /* Wait for ADC effectively enabled */ tickstart = HAL_GetTick(); - + /* Poll for ADC ready flag raised except case of multimode enabled and ADC slave selected. */ uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); @@ -3350,8 +3360,8 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) { - /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit - has been cleared (after a calibration), ADEN bit is reset by the + /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit + has been cleared (after a calibration), ADEN bit is reset by the calibration logic. The workaround is to continue setting ADEN until ADRDY is becomes 1. Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this @@ -3362,21 +3372,21 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { LL_ADC_Enable(hadc->Instance); } - + if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - + /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - + return HAL_ERROR; } } } } - + /* Return HAL status */ return HAL_OK; } @@ -3388,20 +3398,20 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) * @param hadc ADC handle * @retval HAL status. */ -HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc) { uint32_t tickstart; const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance); - + /* Verification if ADC is not already disabled: */ /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ /* disabled. */ - if ( (LL_ADC_IsEnabled(hadc->Instance) != 0UL) + if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) && (tmp_adc_is_disable_on_going == 0UL) ) { /* Check if conditions to disable the ADC are fulfilled */ - if((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN) + if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN) { /* Disable the ADC peripheral */ LL_ADC_Disable(hadc->Instance); @@ -3411,52 +3421,52 @@ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - + /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - + return HAL_ERROR; } - + /* Wait for ADC effectively disabled */ /* Get tick count */ tickstart = HAL_GetTick(); - - while((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) + + while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) { - if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) + if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - + /* Set ADC error code to ADC peripheral internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - + return HAL_ERROR; } } } - + /* Return HAL status */ return HAL_OK; } /** - * @brief DMA transfer complete callback. + * @brief DMA transfer complete callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { /* Retrieve ADC handle corresponding to current DMA handle */ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - + ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* Update state machine on conversion status if not in error state */ - if((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL) + if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); - + /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going */ /* to disable interruption. */ @@ -3464,15 +3474,15 @@ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL) { /* Are conversions software-triggered ? */ - if(LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) + if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) { /* Is CONT bit set ? */ - if(READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL) + if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL) { /* CONT bit is not set, no more conversions expected */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - if((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) - { + if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) + { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } @@ -3482,17 +3492,17 @@ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { /* DMA End of Transfer interrupt was triggered but conversions sequence is not over. If DMACFG is set to 0, conversions are stopped. */ - if(READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMNGT) == 0UL) + if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMNGT) == 0UL) { /* DMACFG bit is not set, conversions are stopped. */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - if((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) - { + if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL) + { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } } - + /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); @@ -3520,15 +3530,15 @@ void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA half transfer complete callback. + * @brief DMA half transfer complete callback. * @param hdma pointer to DMA handle. * @retval None */ void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) { /* Retrieve ADC handle corresponding to current DMA handle */ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - + ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* Half conversion callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvHalfCpltCallback(hadc); @@ -3545,14 +3555,14 @@ void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) void ADC_DMAError(DMA_HandleTypeDef *hdma) { /* Retrieve ADC handle corresponding to current DMA handle */ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - + ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); - + /* Set ADC error code to DMA error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); - + /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); @@ -3631,21 +3641,23 @@ void ADC_ConfigureBoostMode(ADC_HandleTypeDef* hadc) CLEAR_BIT(hadc->Instance->CR, ADC_CR_BOOST_0); } } - else /* STM32H7 silicon Rev.B and above */ + else /* STM32H7 silicon Rev.V */ { + freq /= 2U; /* divider by 2 for Rev.V */ + if (freq <= 6250000UL) { MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, 0UL); } - else if((freq > 6250000UL) && (freq <= 12500000UL)) + else if((freq > 6250000UL) && (freq <= 12500000UL)) { MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_0); } - else if((freq > 12500000UL) && (freq <= 25000000UL)) + else if((freq > 12500000UL) && (freq <= 25000000UL)) { MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1); } - else /* if(freq > 25000000UL) */ + else /* if(freq > 25000000UL) */ { MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0); } diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_adc.h b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_adc.h index 22d7a21b885..d74c0e25235 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_adc.h +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_adc.h @@ -22,7 +22,7 @@ #define STM32H7xx_HAL_ADC_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -44,13 +44,13 @@ * @{ */ -/** +/** * @brief ADC group regular oversampling structure definition */ typedef struct { uint32_t Ratio; /*!< Configures the oversampling ratio. - This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ + This parameter can be a value between 1 and 1024 */ uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ @@ -66,7 +66,7 @@ typedef struct (the oversampling buffer is zeroed during injection sequence). This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */ -}ADC_OversamplingTypeDef; +} ADC_OversamplingTypeDef; /** * @brief Structure definition of ADC instance and ADC group regular. @@ -89,15 +89,15 @@ typedef struct uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler. This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE. Note: The ADC clock configuration is common to all ADC instances. - Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits, + Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits, AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits. Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only - if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC + if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details. Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level. Note: This parameter can be modified only if all ADC instances are disabled. */ - uint32_t Resolution; /*!< Configure the ADC resolution. + uint32_t Resolution; /*!< Configure the ADC resolution. This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */ uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected. @@ -130,7 +130,7 @@ typedef struct uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group sequencer. To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 16. - Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without + Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence @@ -147,7 +147,7 @@ typedef struct If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead. This parameter can be a value of @ref ADC_regular_external_trigger_source. Caution: external trigger source is common to all ADC instances. */ - + uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start. If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. This parameter can be a value of @ref ADC_regular_external_trigger_edge */ @@ -161,11 +161,11 @@ typedef struct uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default). This parameter applies to ADC group regular only. This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR. - Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear - end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function + Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear + end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear). Note: Error reporting with respect to the conversion mode: - - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data + - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case. - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */ @@ -178,7 +178,7 @@ typedef struct ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters. Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */ -}ADC_InitTypeDef; +} ADC_InitTypeDef; /** * @brief Structure definition of ADC channel for regular group @@ -233,7 +233,7 @@ typedef struct Offset value must be a positive number. Depending of ADC resolution selected (16, 14, 12, 10, 8 bits), this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF, 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively. - Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled + Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ FunctionalState OffsetRightShift; /*!< Define the Right-shift data after Offset correction. @@ -244,7 +244,7 @@ typedef struct This parameter is applied only for 16-bit or 8-bit resolution. This parameter can be set to ENABLE or DISABLE. */ -}ADC_ChannelConfTypeDef; +} ADC_ChannelConfTypeDef; /** * @brief Structure definition of ADC analog watchdog @@ -275,10 +275,10 @@ typedef struct uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value. Depending of ADC resolution selected (16, 14, 12, 10, 8 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFFF, 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively. - Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits + Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are - impacted: the comparison of analog watchdog thresholds is done + impacted: the comparison of analog watchdog thresholds is done on oversampling intermediate computation (after ratio, before shift application): intermediate register bitfield [32:7] (26 most significant bits). */ @@ -288,10 +288,10 @@ typedef struct Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are - impacted: the comparison of analog watchdog thresholds is done + impacted: the comparison of analog watchdog thresholds is done on oversampling intermediate computation (after ratio, before shift application): intermediate register bitfield [32:7] (26 most significant bits). */ -}ADC_AnalogWDGConfTypeDef; +} ADC_AnalogWDGConfTypeDef; /** * @brief ADC group injected contexts queue configuration @@ -299,12 +299,12 @@ typedef struct */ typedef struct { - uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each + uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each HAL_ADCEx_InjectedConfigChannel() call to finally initialize JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */ - + uint32_t ChannelCount; /*!< Number of channels in the injected sequence */ -}ADC_InjectionConfigTypeDef; +} ADC_InjectionConfigTypeDef; /** @defgroup ADC_States ADC States * @{ @@ -314,7 +314,7 @@ typedef struct * @brief HAL ADC state machine: ADC states definition (bitfields) * @note ADC state machine is managed by bitfields, state must be compared * with bit by bit. - * For example: + * For example: * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " */ @@ -383,7 +383,7 @@ typedef struct void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ -}ADC_HandleTypeDef; +} ADC_HandleTypeDef; #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) /** @@ -656,23 +656,6 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @} */ -/** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio - * @{ - */ -#define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define ADC_OVERSAMPLING_RATIO_512 (LL_ADC_OVS_RATIO_512) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define ADC_OVERSAMPLING_RATIO_1024 (LL_ADC_OVS_RATIO_1024) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -/** - * @} - */ - /** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift * @{ */ @@ -824,7 +807,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @param __HANDLE__ ADC handle * @retval None */ -#define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) +#define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) /** * @brief Verification of ADC state: enabled or disabled. @@ -866,7 +849,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** * @brief Verify that a given value is aligned with the ADC resolution range. * @param __RESOLUTION__ ADC resolution (16, 14, 12, 10 or 8 bits). - * @param __ADC_VALUE__ value checked against the resolution. + * @param __ADC_VALUE__ value checked against the resolution. * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__) */ #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ @@ -874,7 +857,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** * @brief Verify the length of the scheduled regular conversions group. - * @param __LENGTH__ number of programmed conversions. + * @param __LENGTH__ number of programmed conversions. * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large) */ #define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL))) @@ -882,7 +865,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** * @brief Verify the number of scheduled regular conversions in discontinuous mode. - * @param NUMBER number of scheduled regular conversions in discontinuous mode. + * @param NUMBER number of scheduled regular conversions in discontinuous mode. * @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) or RESET (NUMBER is null or too large) */ #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL))) @@ -907,7 +890,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32) || \ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64) || \ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128) || \ - ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) ) + ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) ) /** * @brief Verify the ADC resolution setting. @@ -1043,7 +1026,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /* Maximum conversion time is */ /* 827 / 0.35 MHz = 2.36 ms */ -#define ADC_STOP_CONVERSION_TIMEOUT ( 5UL) /*!< ADC stop time-out value */ +#define ADC_STOP_CONVERSION_TIMEOUT ( 5UL) /*!< ADC stop time-out value */ /* Delay for temperature sensor stabilization time. */ /* Maximum delay is 120us (refer device datasheet, parameter tSTART). */ @@ -1078,10 +1061,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ do{ \ - (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) + (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ ((__HANDLE__)->State = HAL_ADC_STATE_RESET) @@ -1102,7 +1085,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) - * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. + * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. * @retval None */ #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ @@ -1123,7 +1106,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) - * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. + * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. * @retval None */ #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ @@ -1143,28 +1126,28 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) - * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. + * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. * @retval State of interruption (SET or RESET) */ #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) - + /** * @brief Check whether the specified ADC flag is set or not. * @param __HANDLE__ ADC handle * @param __FLAG__ ADC flag * This parameter can be one of the following values: - * @arg @ref ADC_FLAG_RDY ADC Ready flag - * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag - * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag - * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag - * @arg @ref ADC_FLAG_OVR ADC overrun flag - * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag - * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag + * @arg @ref ADC_FLAG_RDY ADC Ready flag + * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag + * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag + * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag + * @arg @ref ADC_FLAG_OVR ADC overrun flag + * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag + * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) - * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. + * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. * @retval State of flag (TRUE or FALSE). */ #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ @@ -1175,17 +1158,17 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @param __HANDLE__ ADC handle * @param __FLAG__ ADC flag * This parameter can be one of the following values: - * @arg @ref ADC_FLAG_RDY ADC Ready flag - * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag - * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag - * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag - * @arg @ref ADC_FLAG_OVR ADC overrun flag - * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag - * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag + * @arg @ref ADC_FLAG_RDY ADC Ready flag + * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag + * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag + * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag + * @arg @ref ADC_FLAG_OVR ADC overrun flag + * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag + * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) - * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. + * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. * @retval None */ /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ @@ -1242,7 +1225,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @retval Value between Min_Data=0 and Max_Data=18 */ #define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ - __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__)) + __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__)) /** * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x @@ -1286,7 +1269,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ #define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ - __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__)) + __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__)) /** * @brief Helper macro to determine whether the selected channel @@ -1339,7 +1322,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. */ #define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ - __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__)) + __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__)) /** * @brief Helper macro to convert a channel defined from parameter @@ -1406,7 +1389,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @arg @ref ADC_CHANNEL_18 */ #define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ - __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__)) + __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__)) /** * @brief Helper macro to determine whether the internal channel @@ -1435,7 +1418,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * Value "1" if the internal channel selected is available on the ADC instance selected. */ #define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ - __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__)) + __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__)) /** * @brief Helper macro to get the ADC multimode conversion data of ADC master @@ -1451,7 +1434,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ #define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ - __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__)) + __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__)) /** * @brief Helper macro to select the ADC common instance @@ -1464,7 +1447,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @retval ADC common register instance */ #define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \ - __LL_ADC_COMMON_INSTANCE((__ADCx__)) + __LL_ADC_COMMON_INSTANCE((__ADCx__)) /** * @brief Helper macro to check if all ADC instances sharing the same @@ -1484,7 +1467,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * is enabled. */ #define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ - __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__)) + __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__)) /** * @brief Helper macro to define the ADC conversion data full-scale digital @@ -1501,12 +1484,12 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @retval ADC conversion data full-scale digital value */ #define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ - __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__)) + __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__)) /** * @brief Helper macro to convert the ADC conversion data from * a resolution to another resolution. - * @param __DATA__ ADC conversion data to be converted + * @param __DATA__ ADC conversion data to be converted * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted * This parameter can be one of the following values: * @arg @ref ADC_RESOLUTION_16B @@ -1526,9 +1509,9 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to #define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ __ADC_RESOLUTION_CURRENT__,\ __ADC_RESOLUTION_TARGET__) \ - __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\ - (__ADC_RESOLUTION_CURRENT__),\ - (__ADC_RESOLUTION_TARGET__)) + __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__), \ + (__ADC_RESOLUTION_CURRENT__), \ + (__ADC_RESOLUTION_TARGET__)) /** * @brief Helper macro to calculate the voltage (unit: mVolt) @@ -1550,9 +1533,9 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to #define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ __ADC_DATA__,\ __ADC_RESOLUTION__) \ - __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ - (__ADC_DATA__),\ - (__ADC_RESOLUTION__)) + __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__), \ + (__ADC_DATA__), \ + (__ADC_RESOLUTION__)) /** * @brief Helper macro to calculate analog reference voltage (Vref+) @@ -1582,8 +1565,8 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to */ #define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ __ADC_RESOLUTION__) \ - __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\ - (__ADC_RESOLUTION__)) + __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__), \ + (__ADC_RESOLUTION__)) /** * @brief Helper macro to calculate the temperature (unit: degree Celsius) @@ -1634,9 +1617,9 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to #define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ __TEMPSENSOR_ADC_DATA__,\ __ADC_RESOLUTION__) \ - __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\ - (__TEMPSENSOR_ADC_DATA__),\ - (__ADC_RESOLUTION__)) + __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__), \ + (__TEMPSENSOR_ADC_DATA__), \ + (__ADC_RESOLUTION__)) /** * @brief Helper macro to calculate the temperature (unit: degree Celsius) @@ -1689,12 +1672,12 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to __VREFANALOG_VOLTAGE__,\ __TEMPSENSOR_ADC_DATA__,\ __ADC_RESOLUTION__) \ - __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\ - (__TEMPSENSOR_TYP_CALX_V__),\ - (__TEMPSENSOR_CALX_TEMP__),\ - (__VREFANALOG_VOLTAGE__),\ - (__TEMPSENSOR_ADC_DATA__),\ - (__ADC_RESOLUTION__)) + __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__), \ + (__TEMPSENSOR_TYP_CALX_V__), \ + (__TEMPSENSOR_CALX_TEMP__), \ + (__VREFANALOG_VOLTAGE__), \ + (__TEMPSENSOR_ADC_DATA__), \ + (__ADC_RESOLUTION__)) /** * @} @@ -1717,14 +1700,15 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @{ */ /* Initialization and de-initialization functions ****************************/ -HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); -void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); -void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); +void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc); +void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc); #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) /* Callbacks Register/UnRegister functions ***********************************/ -HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, + pADC_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /** @@ -1738,39 +1722,39 @@ HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Ca /* IO operation functions *****************************************************/ /* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); -HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); +HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout); /* Non-blocking mode: Interruption */ -HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc); /* Non-blocking mode: DMA */ -HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); -HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); +HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); /* ADC retrieve conversion value intended to be used with polling or interruption */ -uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); +uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc); /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ -void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); -void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); -void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); -void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); +void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); +void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc); +void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc); +void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc); void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); /** * @} */ /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * @{ - */ + * @brief Peripheral Control functions + * @{ + */ /* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); -HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig); +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig); /** * @} @@ -1780,7 +1764,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_Ana /** @addtogroup ADC_Exported_Functions_Group4 * @{ */ -uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); +uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc); uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** @@ -1795,9 +1779,9 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** @addtogroup ADC_Private_Functions ADC Private Functions * @{ */ -HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup); -HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup); +HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc); void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); void ADC_DMAError(DMA_HandleTypeDef *hdma); diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_adc_ex.c b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_adc_ex.c index c701b47e36b..a89090edbbd 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_adc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_adc_ex.c @@ -20,7 +20,7 @@ * "stm32h7xx_hal_adc.c". * @verbatim - [..] + [..] (@) Sections "ADC peripheral features" and "How to use this driver" are available in file of generic functions "stm32h7xx_hal_adc.c". [..] @@ -64,16 +64,18 @@ ADC_JSQR_JSQ1 | ADC_JSQR_JSQ2 |\ ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime once the ADC is enabled */ - + /* Fixed timeout value for ADC calibration. */ -/* Values defined to be higher than worst cases: low clock frequency, */ -/* maximum prescalers. */ -/* Ex of profile low frequency : f_ADC at 4,577 Khz (minimum value */ -/* according to Data sheet), calibration_time MAX = 16384 / f_ADC */ -/* 16384 / 4577.63671875 = 3.58s */ -/* At maximum CPU speed (400 MHz), this means */ -/* 3.58 * 400 MHz = 1432000000 CPU cycles */ -#define ADC_CALIBRATION_TIMEOUT (1432000000U) /*!< ADC calibration time-out value */ +/* Fixed timeout value for ADC calibration. */ +/* Values defined to be higher than worst cases: low clock frequency, */ +/* maximum prescalers. */ +/* Ex of profile low frequency : f_ADC at 0.125 Mhz (minimum value */ +/* according to Data sheet), calibration_time MAX = 165010 / f_ADC */ +/* 165010 / 125000 = 1.32s */ +/* At maximum CPU speed (480 MHz), this means */ +/* 1.32 * 480 MHz = 633600000 CPU cycles */ +#define ADC_CALIBRATION_TIMEOUT (633600000U) /*!< ADC calibration time-out value */ + /** * @} @@ -96,7 +98,7 @@ ##### IO operation functions ##### =============================================================================== [..] This section provides functions allowing to: - + (+) Perform the ADC self-calibration for single or differential ending. (+) Get calibration factors for single or differential ending. (+) Set calibration factors for single or differential ending. @@ -107,7 +109,7 @@ (+) Get result of ADC group injected channel conversion. (+) Start conversion of ADC group injected and enable interruptions. (+) Stop conversion of ADC group injected and disable interruptions. - + (+) When multimode feature is available, start multimode and enable DMA transfer. (+) Stop multimode and disable ADC DMA transfer. (+) Get result of multimode conversion. @@ -121,7 +123,7 @@ * Calibration prerequisite: ADC must be disabled (execute this * function before HAL_ADC_Start() or after HAL_ADC_Stop() ). * @param hadc ADC handle -* @param CalibrationMode Selection of calibration offset or +* @param CalibrationMode Selection of calibration offset or * linear calibration offset. * @arg ADC_CALIB_OFFSET Channel in mode calibration offset * @arg ADC_CALIB_OFFSET_LINEARITY Channel in mode linear calibration offset @@ -131,36 +133,36 @@ * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t CalibrationMode, uint32_t SingleDiff) +HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff) { HAL_StatusTypeDef tmp_hal_status; __IO uint32_t wait_loop_index = 0UL; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); - + /* Process locked */ __HAL_LOCK(hadc); - + /* Calibration prerequisite: ADC must be disabled. */ - + /* Disable the ADC (if not already disabled) */ tmp_hal_status = ADC_Disable(hadc); - + /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); - + /* Start ADC calibration in mode single-ended or differential */ LL_ADC_StartCalibration(hadc->Instance , CalibrationMode, SingleDiff ); - + /* Wait for calibration completion */ - while(LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) + while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) { wait_loop_index++; if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT) @@ -169,14 +171,14 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL); - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + return HAL_ERROR; } } - + /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, @@ -185,14 +187,14 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t else { SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - + /* Note: No need to update variable "tmp_hal_status" here: already set */ /* to state "HAL_ERROR" by function disabling the ADC. */ } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -205,14 +207,14 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t * @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended * @retval Calibration value. */ -uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff) +uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); - + assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); + /* Return the selected ADC calibration value */ - return LL_ADC_GetCalibrationOffsetFactor(hadc->Instance, SingleDiff); + return LL_ADC_GetCalibrationOffsetFactor(hadc->Instance, SingleDiff); } /** @@ -234,9 +236,9 @@ HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef* hadc, if (tmp_hal_status == HAL_OK) { - for(cnt = 0UL; cnt < 6UL; cnt++) - { - LinearCalib_Buffer[cnt]=LL_ADC_GetCalibrationLinearFactor(hadc->Instance, ADC_CR_LINCALRDYW6 >> cnt); + for(cnt = ADC_LINEAR_CALIB_REG_COUNT; cnt > 0UL; cnt--) + { + LinearCalib_Buffer[cnt-1U]=LL_ADC_GetCalibrationLinearFactor(hadc->Instance, ADC_CR_LINCALRDYW6 >> (ADC_LINEAR_CALIB_REG_COUNT-cnt)); } } @@ -253,26 +255,26 @@ HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef* hadc, * @param CalibrationFactor Calibration factor (coded on 7 bits maximum) * @retval HAL state */ -HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff, uint32_t CalibrationFactor) +HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); assert_param(IS_ADC_CALFACT(CalibrationFactor)); - + /* Process locked */ __HAL_LOCK(hadc); - + /* Verification of hardware constraints before modifying the calibration */ /* factors register: ADC must be enabled, no conversion on going. */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); - - if ( (LL_ADC_IsEnabled(hadc->Instance) != 0UL) + + if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) && (tmp_adc_is_conversion_on_going_regular == 0UL) && (tmp_adc_is_conversion_on_going_injected == 0UL) ) @@ -286,14 +288,14 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); /* Update ADC error code */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - + /* Update ADC state machine to error */ tmp_hal_status = HAL_ERROR; } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -354,63 +356,102 @@ HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc, return HAL_ERROR; } +/* Enable the ADC peripheral */ + if (ADC_Enable(hadc) != HAL_OK) + { + return HAL_ERROR; + } + else + { + for(cnt = ADC_LINEAR_CALIB_REG_COUNT; cnt > 0UL ; cnt--) + { + LL_ADC_SetCalibrationLinearFactor(hadc->Instance, ADC_CR_LINCALRDYW6 >> (ADC_LINEAR_CALIB_REG_COUNT-cnt), LinearCalib_Buffer[cnt-1U]); + } + (void)ADC_Disable(hadc); + } + return HAL_OK; +} + - for(cnt = 0UL; cnt < 6UL; cnt++) +/** + * @brief Load the calibration factor from engi bytes + * @param hadc ADC handle + * @retval HAL state + */ +HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_FactorLoad(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + uint32_t cnt; + uint32_t LinearCalib_Buffer[ADC_LINEAR_CALIB_REG_COUNT]; + + /* Linearity calibration is retrieved from engi bytes + read values from registers and put them to the CALFACT2 register */ + /* If needed linearity calibration can be done in runtime using + LL_ADC_GetCalibrationLinearFactor() */ + + + for (cnt = 0UL; cnt < ADC_LINEAR_CALIB_REG_COUNT; cnt++) { - LL_ADC_SetCalibrationLinearFactor(hadc->Instance, ADC_CR_LINCALRDYW6 >> cnt, LinearCalib_Buffer[cnt]); + LinearCalib_Buffer[cnt] = *(uint32_t*)(ADC_LINEAR_CALIB_REG_1_ADDR + cnt); } - return HAL_OK; + if (HAL_ADCEx_LinearCalibration_SetValue(hadc,(uint32_t*)LinearCalib_Buffer) != HAL_OK) + { + tmp_hal_status = HAL_ERROR; + } + + return tmp_hal_status; } + /** * @brief Enable ADC, start conversion of injected group. * @note Interruptions enabled in this function: None. - * @note Case of multimode enabled when multimode feature is available: - * HAL_ADCEx_InjectedStart() API must be called for ADC slave first, - * then for ADC master. - * For ADC slave, ADC is enabled only (conversion is not started). + * @note Case of multimode enabled when multimode feature is available: + * HAL_ADCEx_InjectedStart() API must be called for ADC slave first, + * then for ADC master. + * For ADC slave, ADC is enabled only (conversion is not started). * For ADC master, ADC is enabled and multimode conversion is started. * @param hadc ADC handle. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; uint32_t tmp_config_injected_queue; uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL) { return HAL_BUSY; } else { - /* In case of software trigger detection enabled, JQDIS must be set + /* In case of software trigger detection enabled, JQDIS must be set (which can be done only if ADSTART and JADSTART are both cleared). If JQDIS is not set at that point, returns an error - since software trigger detection is disabled. User needs to - resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS. - - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means + resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS. + - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means the queue is empty */ tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); - - if ( (READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL) + + if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL) && (tmp_config_injected_queue == 0UL) ) { - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); return HAL_ERROR; } - + /* Process locked */ __HAL_LOCK(hadc); - + /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); - + /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { @@ -425,33 +466,33 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); } - + /* Set ADC state */ /* - Clear state bitfield related to injected group conversion results */ /* - Set state bitfield related to injected operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); - + /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - if ADC instance is master or if multimode feature is not available - if multimode setting is disabled (ADC instance slave in independent mode) */ - if ( (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) - || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) ) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } - + /* Clear ADC group injected group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS)); - + /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); - + /* Enable conversion of injected group, if automatic injected conversion */ /* is disabled. */ /* If software start has been selected, conversion starts immediately. */ @@ -464,14 +505,14 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) /* and conversion is started. */ /* If ADC is master or independent, */ /* - ADC is enabled and conversion is started. */ - if ( (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) - || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) - || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) - || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL) + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL) ) { /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */ - if(LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT) + if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT) { LL_ADC_INJ_StartConversion(hadc->Instance); } @@ -481,14 +522,14 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } - - } + + } else { /* Process unlocked */ - __HAL_UNLOCK(hadc); + __HAL_UNLOCK(hadc); } - + /* Return function status */ return tmp_hal_status; } @@ -497,32 +538,32 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) /** * @brief Stop conversion of injected channels. Disable ADC peripheral if * no regular conversion is on going. - * @note If ADC must be disabled and if conversion is on going on + * @note If ADC must be disabled and if conversion is on going on * regular group, function HAL_ADC_Stop must be used to stop both * injected and regular groups, and disable the ADC. * @note If injected group mode auto-injection is enabled, * function HAL_ADC_Stop must be used. - * @note In case of multimode enabled (when multimode feature is available), + * @note In case of multimode enabled (when multimode feature is available), * HAL_ADCEx_InjectedStop() must be called for ADC master first, then for ADC slave. - * For ADC master, conversion is stopped and ADC is disabled. + * For ADC master, conversion is stopped and ADC is disabled. * For ADC slave, ADC is disabled only (conversion stop of ADC master * has already stopped conversion of ADC slave). * @param hadc ADC handle. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Process locked */ __HAL_LOCK(hadc); - + /* 1. Stop potential conversion on going on injected group only. */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP); - + /* Disable ADC peripheral if injected conversions are effectively stopped */ /* and if no conversion on regular group is on-going */ if (tmp_hal_status == HAL_OK) @@ -531,7 +572,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) { /* 2. Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); - + /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { @@ -549,10 +590,10 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); } } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -565,7 +606,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) * checked and cleared depending on AUTDLY bit status. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) +HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout) { uint32_t tickstart; uint32_t tmp_Flag_End; @@ -574,7 +615,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u uint32_t tmp_cfgr; const ADC_TypeDef *tmpADC_Master; uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); @@ -587,39 +628,39 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u { tmp_Flag_End = ADC_FLAG_JEOC; } - + /* Get timeout */ tickstart = HAL_GetTick(); - - /* Wait until End of Conversion or Sequence flag is raised */ - while((hadc->Instance->ISR & tmp_Flag_End) == 0UL) + + /* Wait until End of Conversion or Sequence flag is raised */ + while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) { /* Check if timeout is disabled (set to infinite wait) */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + return HAL_TIMEOUT; } } } - + /* Retrieve ADC configuration */ tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance); tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance); /* Get relevant register CFGR in ADC instance of ADC master or slave */ /* in function of multimode state (for devices with multimode */ /* available). */ - if ( (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) - || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) - || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) - || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL) + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL) ) { tmp_cfgr = READ_REG(hadc->Instance->CFGR); @@ -629,20 +670,20 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance); tmp_cfgr = READ_REG(tmpADC_Master->CFGR); } - + /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); - + /* Determine whether any further conversion upcoming on group injected */ /* by external trigger or by automatic injected conversion */ /* from group regular. */ - if((tmp_adc_inj_is_trigger_source_sw_start != 0UL) || - ((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) && - ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) && - (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == 0UL) ) ) ) + if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL) || + ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) && + ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) && + (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL)))) { /* Check whether end of sequence is reached */ - if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) ) + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) { /* Particular case if injected contexts queue is enabled: */ /* when the last context has been fully processed, JSQR is reset */ @@ -650,19 +691,19 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u /* (queue empty, triggers are ignored), it can start again */ /* immediately after setting a new context (JADSTART is still set). */ /* Therefore, state of HAL ADC injected group is kept to busy. */ - if(READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL) + if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL) { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); - - if((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL) + + if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } } } - + /* Clear polled flag */ if (tmp_Flag_End == ADC_FLAG_JEOS) { @@ -670,7 +711,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u /* "LowPowerAutoWait " is disabled, to not interfere with this feature. */ /* For injected groups, no new conversion will start before JEOS is */ /* cleared. */ - if (READ_BIT (tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL) + if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL) { __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS)); } @@ -679,7 +720,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u { __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); } - + /* Return API HAL status */ return HAL_OK; } @@ -687,53 +728,53 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u /** * @brief Enable ADC, start conversion of injected group with interruption. * @note Interruptions enabled in this function according to initialization - * setting : JEOC (end of conversion) or JEOS (end of sequence) - * @note Case of multimode enabled (when multimode feature is enabled): - * HAL_ADCEx_InjectedStart_IT() API must be called for ADC slave first, - * then for ADC master. - * For ADC slave, ADC is enabled only (conversion is not started). + * setting : JEOC (end of conversion) or JEOS (end of sequence) + * @note Case of multimode enabled (when multimode feature is enabled): + * HAL_ADCEx_InjectedStart_IT() API must be called for ADC slave first, + * then for ADC master. + * For ADC slave, ADC is enabled only (conversion is not started). * For ADC master, ADC is enabled and multimode conversion is started. * @param hadc ADC handle. * @retval HAL status. */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; uint32_t tmp_config_injected_queue; uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL) { return HAL_BUSY; } else { - /* In case of software trigger detection enabled, JQDIS must be set + /* In case of software trigger detection enabled, JQDIS must be set (which can be done only if ADSTART and JADSTART are both cleared). If JQDIS is not set at that point, returns an error - since software trigger detection is disabled. User needs to - resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS. - - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means + resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS. + - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means the queue is empty */ tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); - - if ( (READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL) + + if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL) && (tmp_config_injected_queue == 0UL) ) { - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); return HAL_ERROR; } /* Process locked */ __HAL_LOCK(hadc); - + /* Enable the ADC peripheral */ tmp_hal_status = ADC_Enable(hadc); - + /* Start conversion if ADC is effectively enabled */ if (tmp_hal_status == HAL_OK) { @@ -741,61 +782,61 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL) { /* Reset ADC error code field related to injected conversions only */ - CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); + CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); } else { /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); } - + /* Set ADC state */ /* - Clear state bitfield related to injected group conversion results */ /* - Set state bitfield related to injected operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); - + /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit - if ADC instance is master or if multimode feature is not available - if multimode setting is disabled (ADC instance slave in independent mode) */ - if ( (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) - || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) ) { CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } - + /* Clear ADC group injected group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS)); - + /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); - + /* Enable ADC Injected context queue overflow interrupt if this feature */ /* is enabled. */ if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != 0UL) { __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF); } - + /* Enable ADC end of conversion interrupt */ - switch(hadc->Init.EOCSelection) + switch (hadc->Init.EOCSelection) { - case ADC_EOC_SEQ_CONV: + case ADC_EOC_SEQ_CONV: __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS); break; /* case ADC_EOC_SINGLE_CONV */ default: - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); break; } - + /* Enable conversion of injected group, if automatic injected conversion */ /* is disabled. */ /* If software start has been selected, conversion starts immediately. */ @@ -808,14 +849,14 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) /* and conversion is started. */ /* If ADC is master or independent, */ /* - ADC is enabled and conversion is started. */ - if ( (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) - || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) - || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) - || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL) + if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance) + || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT) + || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL) ) { /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */ - if(LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT) + if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT) { LL_ADC_INJ_StartConversion(hadc->Instance); } @@ -825,51 +866,51 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */ SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); } - + } else { /* Process unlocked */ __HAL_UNLOCK(hadc); } - + /* Return function status */ return tmp_hal_status; } } /** - * @brief Stop conversion of injected channels, disable interruption of + * @brief Stop conversion of injected channels, disable interruption of * end-of-conversion. Disable ADC peripheral if no regular conversion * is on going. - * @note If ADC must be disabled and if conversion is on going on + * @note If ADC must be disabled and if conversion is on going on * regular group, function HAL_ADC_Stop must be used to stop both * injected and regular groups, and disable the ADC. * @note If injected group mode auto-injection is enabled, * function HAL_ADC_Stop must be used. - * @note Case of multimode enabled (when multimode feature is available): - * HAL_ADCEx_InjectedStop_IT() API must be called for ADC master first, + * @note Case of multimode enabled (when multimode feature is available): + * HAL_ADCEx_InjectedStop_IT() API must be called for ADC master first, * then for ADC slave. - * For ADC master, conversion is stopped and ADC is disabled. + * For ADC master, conversion is stopped and ADC is disabled. * For ADC slave, ADC is disabled only (conversion stop of ADC master * has already stopped conversion of ADC slave). * @note In case of auto-injection mode, HAL_ADC_Stop() must be used. * @param hadc ADC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Process locked */ __HAL_LOCK(hadc); - + /* 1. Stop potential conversion on going on injected group only. */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP); - + /* Disable ADC peripheral if injected conversions are effectively stopped */ /* and if no conversion on the other group (regular group) is intended to */ /* continue. */ @@ -877,12 +918,12 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) { /* Disable ADC end of conversion interrupt for injected channels */ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_FLAG_JQOVF)); - + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) { /* 2. Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); - + /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { @@ -903,27 +944,27 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } /** * @brief Enable ADC, start MultiMode conversion and transfer regular results through DMA. - * @note Multimode must have been previously configured using + * @note Multimode must have been previously configured using * HAL_ADCEx_MultiModeConfigChannel() function. * Interruptions enabled in this function: - * overrun, DMA half transfer, DMA transfer complete. + * overrun, DMA half transfer, DMA transfer complete. * Each of these interruptions has its dedicated callback function. - * @note State field of Slave ADC handle is not updated in this configuration: - * user should not rely on it for information related to Slave regular - * conversions. + * @note State field of Slave ADC handle is not updated in this configuration: + * user should not rely on it for information related to Slave regular + * conversions. * @param hadc ADC handle of ADC master (handle of ADC slave must not be used) * @param pData Destination Buffer address. * @param Length Length of data to be transferred from ADC peripheral to memory (in bytes). * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) +HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) { HAL_StatusTypeDef tmp_hal_status; ADC_HandleTypeDef tmphadcSlave; @@ -933,7 +974,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); - + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL) { return HAL_BUSY; @@ -945,18 +986,18 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t /* Set a temporary handle of the ADC slave associated to the ADC master */ ADC_MULTI_SLAVE(hadc, &tmphadcSlave); - + if (tmphadcSlave.Instance == NULL) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + return HAL_ERROR; } - + /* Enable the ADC peripherals: master and slave (in case if not already */ /* enabled previously) */ tmp_hal_status = ADC_Enable(hadc); @@ -964,7 +1005,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t { tmp_hal_status = ADC_Enable(&tmphadcSlave); } - + /* Start multimode conversion of ADCs pair */ if (tmp_hal_status == HAL_OK) { @@ -972,40 +1013,40 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY); - + /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); - + /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; - + /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; - + /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ; - + /* Pointer to the common control register */ tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); - + /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ /* start (in case of SW start): */ - + /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); - + /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); - + /* Enable ADC overrun interrupt */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); - + /* Start the DMA channel */ tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length); - + /* Enable conversion of regular group. */ /* If software start has been selected, conversion starts immediately. */ /* If external trigger has been selected, conversion will start at next */ @@ -1018,7 +1059,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t /* Process unlocked */ __HAL_UNLOCK(hadc); } - + /* Return function status */ return tmp_hal_status; } @@ -1027,92 +1068,92 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t /** * @brief Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral. * @note Multimode is kept enabled after this function. MultiMode DMA bits - * (MDMA and DMACFG bits of common CCR register) are maintained. To disable - * Multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be + * (MDMA and DMACFG bits of common CCR register) are maintained. To disable + * Multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be * reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can * resort to HAL_ADCEx_DisableMultiMode() API. - * @note In case of DMA configured in circular mode, function + * @note In case of DMA configured in circular mode, function * HAL_ADC_Stop_DMA() must be called after this function with handle of * ADC slave, to properly disable the DMA channel. * @param hadc ADC handle of ADC master (handle of ADC slave must not be used) * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; uint32_t tickstart; ADC_HandleTypeDef tmphadcSlave; uint32_t tmphadcSlave_conversion_on_going; HAL_StatusTypeDef tmphadcSlave_disable_status; - + /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); - + /* Process locked */ __HAL_LOCK(hadc); - - + + /* 1. Stop potential multimode conversion on going, on regular and injected groups */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); - + /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) - { + { /* Set a temporary handle of the ADC slave associated to the ADC master */ ADC_MULTI_SLAVE(hadc, &tmphadcSlave); - + if (tmphadcSlave.Instance == NULL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + return HAL_ERROR; } - + /* Procedure to disable the ADC peripheral: wait for conversions */ /* effectively stopped (ADC master and ADC slave), then disable ADC */ - + /* 1. Wait for ADC conversion completion for ADC master and ADC slave */ - tickstart = HAL_GetTick(); - + tickstart = HAL_GetTick(); + tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); - while( (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) + while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) || (tmphadcSlave_conversion_on_going == 1UL) - ) + ) { - if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT) + if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + return HAL_ERROR; } - + tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); } - + /* Disable the DMA channel (in case of DMA in circular mode or stop */ /* while DMA transfer is on going) */ /* Note: DMA channel of ADC slave should be stopped after this function */ /* with HAL_ADC_Stop_DMA() API. */ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); - + /* Check if DMA channel effectively disabled */ if (tmp_hal_status == HAL_ERROR) { /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); } - + /* Disable ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); - + /* 2. Disable the ADC peripherals: master and slave */ /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */ /* memory a potential failing status. */ @@ -1120,7 +1161,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) { tmphadcSlave_disable_status = ADC_Disable(&tmphadcSlave); if ((ADC_Disable(hadc) == HAL_OK) && - (tmphadcSlave_disable_status == HAL_OK) ) + (tmphadcSlave_disable_status == HAL_OK)) { tmp_hal_status = HAL_OK; } @@ -1131,16 +1172,16 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) (void) ADC_Disable(hadc); (void) ADC_Disable(&tmphadcSlave); } - + /* Set ADC state (ADC master) */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -1150,20 +1191,20 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) * @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used) * @retval The converted data values. */ -uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) +uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc) { const ADC_Common_TypeDef *tmpADC_Common; - + /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); - + /* Prevent unused argument(s) compilation warning if no assert_param check */ /* and possible no usage in __LL_ADC_COMMON_INSTANCE() below */ UNUSED(hadc); - + /* Pointer to the common control register */ tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); - + /* Return the multi mode conversion value */ return tmpADC_Common->CDR; } @@ -1172,7 +1213,7 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) * @brief Get ADC injected group conversion result. * @note Reading register JDRx automatically clears ADC flag JEOC * (ADC group injected end of unitary conversion). - * @note This function does not clear ADC flag JEOS + * @note This function does not clear ADC flag JEOS * (ADC group injected end of sequence conversion) * Occurrence of flag JEOS rising: * - If sequencer is composed of 1 rank, flag JEOS is equivalent @@ -1183,9 +1224,9 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) * Flag JEOS must not be cleared by this function because * it would not be compliant with low power features * (feature low power auto-wait, not available on all STM32 families). - * To clear this flag, either use function: + * To clear this flag, either use function: * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming - * model polling: @ref HAL_ADCEx_InjectedPollForConversion() + * model polling: @ref HAL_ADCEx_InjectedPollForConversion() * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS). * @param hadc ADC handle * @param InjectedRank the converted ADC injected rank. @@ -1196,24 +1237,24 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) * @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4 * @retval ADC group injected conversion data */ -uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank) +uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank) { uint32_t tmp_jdr; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_INJECTED_RANK(InjectedRank)); - + /* Get ADC converted value */ - switch(InjectedRank) - { + switch (InjectedRank) + { case ADC_INJECTED_RANK_4: tmp_jdr = hadc->Instance->JDR4; break; - case ADC_INJECTED_RANK_3: + case ADC_INJECTED_RANK_3: tmp_jdr = hadc->Instance->JDR3; break; - case ADC_INJECTED_RANK_2: + case ADC_INJECTED_RANK_2: tmp_jdr = hadc->Instance->JDR2; break; case ADC_INJECTED_RANK_1: @@ -1221,8 +1262,8 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa tmp_jdr = hadc->Instance->JDR1; break; } - - /* Return ADC converted value */ + + /* Return ADC converted value */ return tmp_jdr; } @@ -1231,11 +1272,11 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa * @param hadc ADC handle * @retval None */ -__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) +__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); - + /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADCEx_InjectedConvCpltCallback must be implemented in the user file. */ @@ -1250,11 +1291,11 @@ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) * @param hadc ADC handle * @retval None */ -__weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc) +__weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); - + /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file. */ @@ -1265,11 +1306,11 @@ __weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc) * @param hadc ADC handle * @retval None */ -__weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc) +__weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); - + /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file. */ @@ -1280,11 +1321,11 @@ __weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc) * @param hadc ADC handle * @retval None */ -__weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc) +__weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); - + /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file. */ @@ -1296,48 +1337,48 @@ __weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc) * @param hadc ADC handle * @retval None */ -__weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc) +__weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); - + /* NOTE : This function should not be modified. When the callback is needed, function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file. */ } /** - * @brief Stop ADC conversion of regular group (and injected channels in - * case of auto_injection mode), disable ADC peripheral if no + * @brief Stop ADC conversion of regular group (and injected channels in + * case of auto_injection mode), disable ADC peripheral if no * conversion is on going on injected group. * @param hadc ADC handle * @retval HAL status. */ -HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Process locked */ __HAL_LOCK(hadc); - + /* 1. Stop potential regular conversion on going */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); - - /* Disable ADC peripheral if regular conversions are effectively stopped + + /* Disable ADC peripheral if regular conversions are effectively stopped and if no injected conversions are on-going */ if (tmp_hal_status == HAL_OK) { - /* Clear HAL_ADC_STATE_REG_BUSY bit */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - + /* Clear HAL_ADC_STATE_REG_BUSY bit */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) { /* 2. Disable the ADC peripheral */ tmp_hal_status = ADC_Disable(hadc); - + /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { @@ -1354,10 +1395,10 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc) SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); } } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -1371,32 +1412,32 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc) * @param hadc ADC handle * @retval HAL status. */ -HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Process locked */ __HAL_LOCK(hadc); - + /* 1. Stop potential regular conversion on going */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); - + /* Disable ADC peripheral if conversions are effectively stopped and if no injected conversion is on-going */ if (tmp_hal_status == HAL_OK) { - /* Clear HAL_ADC_STATE_REG_BUSY bit */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - + /* Clear HAL_ADC_STATE_REG_BUSY bit */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + /* Disable all regular-related interrupts */ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); - + /* 2. Disable ADC peripheral if no injected conversions are on-going */ if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) - { + { tmp_hal_status = ADC_Disable(hadc); /* if no issue reported */ if (tmp_hal_status == HAL_OK) @@ -1412,62 +1453,62 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc) SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); } } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } /** - * @brief Stop ADC conversion of regular group (and injected group in - * case of auto_injection mode), disable ADC DMA transfer, disable + * @brief Stop ADC conversion of regular group (and injected group in + * case of auto_injection mode), disable ADC DMA transfer, disable * ADC peripheral if no conversion is on going * on injected group. - * @note HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode only. - * For multimode (when multimode feature is available), + * @note HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode only. + * For multimode (when multimode feature is available), * HAL_ADCEx_RegularMultiModeStop_DMA() API must be used. * @param hadc ADC handle * @retval HAL status. */ -HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Process locked */ __HAL_LOCK(hadc); - + /* 1. Stop potential regular conversion on going */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); - - /* Disable ADC peripheral if conversions are effectively stopped + + /* Disable ADC peripheral if conversions are effectively stopped and if no injected conversion is on-going */ if (tmp_hal_status == HAL_OK) { /* Clear HAL_ADC_STATE_REG_BUSY bit */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - + /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */ MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_DMNGT_0 |ADC_CFGR_DMNGT_1, 0UL); - + /* Disable the DMA channel (in case of DMA in circular mode or stop while */ /* while DMA transfer is on going) */ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); - + /* Check if DMA channel effectively disabled */ if (tmp_hal_status != HAL_OK) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); } - + /* Disable ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); - + /* 2. Disable the ADC peripheral */ /* Update "tmp_hal_status" only if DMA channel disabling passed, */ /* to keep in memory a potential failing status. */ @@ -1481,7 +1522,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc) { (void)ADC_Disable(hadc); } - + /* Check if ADC is effectively disabled */ if (tmp_hal_status == HAL_OK) { @@ -1496,10 +1537,10 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc) SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); } } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -1507,129 +1548,129 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc) /** * @brief Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going. * @note Multimode is kept enabled after this function. Multimode DMA bits - * (MDMA and DMACFG bits of common CCR register) are maintained. To disable - * multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be + * (MDMA and DMACFG bits of common CCR register) are maintained. To disable + * multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be * reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can - * resort to HAL_ADCEx_DisableMultiMode() API. - * @note In case of DMA configured in circular mode, function + * resort to HAL_ADCEx_DisableMultiMode() API. + * @note In case of DMA configured in circular mode, function * HAL_ADCEx_RegularStop_DMA() must be called after this function with handle of * ADC slave, to properly disable the DMA channel. * @param hadc ADC handle of ADC master (handle of ADC slave must not be used) * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; uint32_t tickstart; ADC_HandleTypeDef tmphadcSlave; uint32_t tmphadcSlave_conversion_on_going; - + /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); - + /* Process locked */ __HAL_LOCK(hadc); - - + + /* 1. Stop potential multimode conversion on going, on regular groups */ tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); - + /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { /* Clear HAL_ADC_STATE_REG_BUSY bit */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - + /* Set a temporary handle of the ADC slave associated to the ADC master */ ADC_MULTI_SLAVE(hadc, &tmphadcSlave); - + if (tmphadcSlave.Instance == NULL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + return HAL_ERROR; } - + /* Procedure to disable the ADC peripheral: wait for conversions */ /* effectively stopped (ADC master and ADC slave), then disable ADC */ - + /* 1. Wait for ADC conversion completion for ADC master and ADC slave */ - tickstart = HAL_GetTick(); - + tickstart = HAL_GetTick(); + tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); - while( (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) + while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) || (tmphadcSlave_conversion_on_going == 1UL) - ) + ) { - if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT) + if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + return HAL_ERROR; } - + tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); } - + /* Disable the DMA channel (in case of DMA in circular mode or stop */ /* while DMA transfer is on going) */ /* Note: DMA channel of ADC slave should be stopped after this function */ /* with HAL_ADCEx_RegularStop_DMA() API. */ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); - + /* Check if DMA channel effectively disabled */ if (tmp_hal_status != HAL_OK) { /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); } - + /* Disable ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); - + /* 2. Disable the ADC peripherals: master and slave if no injected */ /* conversion is on-going. */ /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */ /* memory a potential failing status. */ if (tmp_hal_status == HAL_OK) { - if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) - { - tmp_hal_status = ADC_Disable(hadc); - if (tmp_hal_status == HAL_OK) - { - if (LL_ADC_INJ_IsConversionOngoing((&tmphadcSlave)->Instance) == 0UL) - { - tmp_hal_status = ADC_Disable(&tmphadcSlave); - } - } - } - - if (tmp_hal_status == HAL_OK) - { - /* Both Master and Slave ADC's could be disabled. Update Master State */ - /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */ - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); - } - else - { - /* injected (Master or Slave) conversions are still on-going, - no Master State change */ - } + if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) + { + tmp_hal_status = ADC_Disable(hadc); + if (tmp_hal_status == HAL_OK) + { + if (LL_ADC_INJ_IsConversionOngoing((&tmphadcSlave)->Instance) == 0UL) + { + tmp_hal_status = ADC_Disable(&tmphadcSlave); + } + } + } + + if (tmp_hal_status == HAL_OK) + { + /* Both Master and Slave ADC's could be disabled. Update Master State */ + /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */ + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); + } + else + { + /* injected (Master or Slave) conversions are still on-going, + no Master State change */ + } } } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -1641,7 +1682,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc) /** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions * @brief ADC Extended Peripheral Control functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral Control functions ##### =============================================================================== @@ -1651,7 +1692,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc) (+) Enable or Disable Injected Queue (+) Disable ADC voltage regulator (+) Enter ADC deep-power-down mode - + @endverbatim * @{ */ @@ -1659,38 +1700,38 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc) /** * @brief Configure a channel to be assigned to ADC group injected. * @note Possibility to update parameters on the fly: - * This function initializes injected group, following calls to this + * This function initializes injected group, following calls to this * function can be used to reconfigure some parameters of structure * "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC. * The setting of these parameters is conditioned to ADC state: * Refer to comments of structure "ADC_InjectionConfTypeDef". * @note In case of usage of internal measurement channels: * Vbat/VrefInt/TempSensor. - * These internal paths can be disabled using function + * These internal paths can be disabled using function * HAL_ADC_DeInit(). - * @note Caution: For Injected Context Queue use, a context must be fully - * defined before start of injected conversion. All channels are configured - * consecutively for the same ADC instance. Therefore, the number of calls to - * HAL_ADCEx_InjectedConfigChannel() must be equal to the value of parameter + * @note Caution: For Injected Context Queue use, a context must be fully + * defined before start of injected conversion. All channels are configured + * consecutively for the same ADC instance. Therefore, the number of calls to + * HAL_ADCEx_InjectedConfigChannel() must be equal to the value of parameter * InjectedNbrOfConversion for each context. - * - Example 1: If 1 context is intended to be used (or if there is no use of the - * Injected Queue Context feature) and if the context contains 3 injected ranks - * (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be - * called once for each channel (i.e. 3 times) before starting a conversion. - * This function must not be called to configure a 4th injected channel: + * - Example 1: If 1 context is intended to be used (or if there is no use of the + * Injected Queue Context feature) and if the context contains 3 injected ranks + * (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be + * called once for each channel (i.e. 3 times) before starting a conversion. + * This function must not be called to configure a 4th injected channel: * it would start a new context into context queue. - * - Example 2: If 2 contexts are intended to be used and each of them contains - * 3 injected ranks (InjectedNbrOfConversion = 3), - * HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and - * for each context (3 channels x 2 contexts = 6 calls). Conversion can - * start once the 1st context is set, that is after the first three + * - Example 2: If 2 contexts are intended to be used and each of them contains + * 3 injected ranks (InjectedNbrOfConversion = 3), + * HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and + * for each context (3 channels x 2 contexts = 6 calls). Conversion can + * start once the 1st context is set, that is after the first three * HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly. * @param hadc ADC handle * @param sConfigInjected Structure of ADC injected group and ADC channel for * injected group. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected) +HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmpOffsetShifted; @@ -1698,9 +1739,9 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; __IO uint32_t wait_loop_index = 0; - + uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0U; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime)); @@ -1712,14 +1753,14 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I assert_param(IS_ADC_OFFSET_NUMBER(sConfigInjected->InjectedOffsetNumber)); assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset)); assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjecOversamplingMode)); - - if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) + + if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) { assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank)); assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion)); assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode)); } - + /* Check offset range according to oversampling setting */ if (hadc->Init.OversamplingMode == ENABLE) { @@ -1729,17 +1770,17 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I { assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset)); } - + /* JDISCEN and JAUTO bits can't be set at the same time */ - assert_param(!((sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE))); - + assert_param(!((sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE))); + /* DISCEN and JAUTO bits can't be set at the same time */ - assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE))); - + assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE))); + /* Verification of channel number */ if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED) { - assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel)); + assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel)); } else { @@ -1756,10 +1797,10 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I assert_param(IS_ADC3_DIFF_CHANNEL(sConfigInjected->InjectedChannel)); } } - + /* Process locked */ __HAL_LOCK(hadc); - + /* Configuration of injected group sequencer: */ /* Hardware constraint: Must fully define injected context register JSQR */ /* before make it entering into injected sequencer queue. */ @@ -1780,9 +1821,9 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* injected ranks have been set. */ /* Note: Scan mode is not present by hardware on this device, but used */ /* by software for alignment over all STM32 devices. */ - + if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) || - (sConfigInjected->InjectedNbrOfConversion == 1U) ) + (sConfigInjected->InjectedNbrOfConversion == 1U)) { /* Configuration of context register JSQR: */ /* - number of ranks in injected group sequencer: fixed to 1st rank */ @@ -1790,7 +1831,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* - external trigger to start conversion */ /* - external trigger polarity */ /* - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */ - + if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1) { /* Enable external trigger if trigger selection is different of */ @@ -1800,20 +1841,20 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* software start. */ if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) { - tmp_JSQR_ContextQueueBeingBuilt = ( ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) - | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL) - | sConfigInjected->ExternalTrigInjecConvEdge - ); + tmp_JSQR_ContextQueueBeingBuilt = (ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) + | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL) + | sConfigInjected->ExternalTrigInjecConvEdge + ); } else { - tmp_JSQR_ContextQueueBeingBuilt = ( ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) ); + tmp_JSQR_ContextQueueBeingBuilt = (ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1)); } - - MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_JSQR_ContextQueueBeingBuilt); + + MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_JSQR_ContextQueueBeingBuilt); /* For debug and informative reasons, hadc handle saves JSQR setting */ hadc->InjectionConfig.ContextQueue = tmp_JSQR_ContextQueueBeingBuilt; - + } } else @@ -1825,10 +1866,10 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* calls of this function, for each injected channel rank: */ /* 1. Start new context and set parameters related to all injected */ /* channels: injected sequence length and trigger. */ - + /* if hadc->InjectionConfig.ChannelCount is equal to 0, this is the first */ /* call of the context under setting */ - if (hadc->InjectionConfig.ChannelCount == 0U) + if (hadc->InjectionConfig.ChannelCount == 0U) { /* Initialize number of channels that will be configured on the context */ /* being built */ @@ -1836,13 +1877,13 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* Handle hadc saves the context under build up over each HAL_ADCEx_InjectedConfigChannel() call, this context will be written in JSQR register at the last call. At this point, the context is merely reset */ - hadc->InjectionConfig.ContextQueue = 0x00000000U; - + hadc->InjectionConfig.ContextQueue = 0x00000000U; + /* Configuration of context register JSQR: */ /* - number of ranks in injected group sequencer */ /* - external trigger to start conversion */ /* - external trigger polarity */ - + /* Enable external trigger if trigger selection is different of */ /* software start. */ /* Note: This configuration keeps the hardware feature of parameter */ @@ -1850,39 +1891,39 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* software start. */ if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) { - tmp_JSQR_ContextQueueBeingBuilt = ( (sConfigInjected->InjectedNbrOfConversion - 1U) - | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL) - | sConfigInjected->ExternalTrigInjecConvEdge - ); + tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U) + | (sConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL) + | sConfigInjected->ExternalTrigInjecConvEdge + ); } else { - tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U) ); + tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - 1U)); } - + } - + /* 2. Continue setting of context under definition with parameter */ /* related to each channel: channel rank sequence */ /* Clear the old JSQx bits for the selected rank */ tmp_JSQR_ContextQueueBeingBuilt &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, sConfigInjected->InjectedRank); - + /* Set the JSQx bits for the selected rank */ tmp_JSQR_ContextQueueBeingBuilt |= ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank); - + /* Decrease channel count */ hadc->InjectionConfig.ChannelCount--; - + /* 3. tmp_JSQR_ContextQueueBeingBuilt is fully built for this HAL_ADCEx_InjectedConfigChannel() - call, aggregate the setting to those already built during the previous + call, aggregate the setting to those already built during the previous HAL_ADCEx_InjectedConfigChannel() calls (for the same context of course) */ hadc->InjectionConfig.ContextQueue |= tmp_JSQR_ContextQueueBeingBuilt; - + /* 4. End of context setting: if this is the last channel set, then write context into register JSQR and make it enter into queue */ if (hadc->InjectionConfig.ChannelCount == 0U) { - MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, hadc->InjectionConfig.ContextQueue); + MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, hadc->InjectionConfig.ContextQueue); } } @@ -1897,26 +1938,26 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I { /* ADC channels preselection */ hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel) & 0x1FUL)); - + /* If auto-injected mode is disabled: no constraint */ if (sConfigInjected->AutoInjectedConv == DISABLE) - { + { MODIFY_REG(hadc->Instance->CFGR, - ADC_CFGR_JQM | ADC_CFGR_JDISCEN, + ADC_CFGR_JQM | ADC_CFGR_JDISCEN, ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext) | - ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)sConfigInjected->InjectedDiscontinuousConvMode) ); + ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)sConfigInjected->InjectedDiscontinuousConvMode)); } /* If auto-injected mode is enabled: Injected discontinuous setting is */ /* discarded. */ else { MODIFY_REG(hadc->Instance->CFGR, - ADC_CFGR_JQM | ADC_CFGR_JDISCEN, - ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext) ); + ADC_CFGR_JQM | ADC_CFGR_JDISCEN, + ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)sConfigInjected->QueueInjectedContext)); } } - + /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular and injected groups: */ @@ -1926,24 +1967,24 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* - Channel offset */ tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); - - if ( (tmp_adc_is_conversion_on_going_regular == 0UL) + + if ((tmp_adc_is_conversion_on_going_regular == 0UL) && (tmp_adc_is_conversion_on_going_injected == 0UL) ) { /* If injected group external triggers are disabled (set to injected */ /* software start): no constraint */ if ((sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START) - || (sConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)) + || (sConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)) { - if (sConfigInjected->AutoInjectedConv == ENABLE) - { - SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO); - } - else - { - CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO); - } + if (sConfigInjected->AutoInjectedConv == ENABLE) + { + SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO); + } + else + { + CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO); + } } /* If Automatic injected conversion was intended to be set and could not */ /* due to injected group external triggers enabled, error is reported. */ @@ -1953,60 +1994,64 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - + tmp_hal_status = HAL_ERROR; } else { - CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO); + CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO); } } - + if (sConfigInjected->InjecOversamplingMode == ENABLE) { assert_param(IS_ADC_OVERSAMPLING_RATIO(sConfigInjected->InjecOversampling.Ratio)); assert_param(IS_ADC_RIGHT_BIT_SHIFT(sConfigInjected->InjecOversampling.RightBitShift)); - + /* JOVSE must be reset in case of triggered regular mode */ - assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE|ADC_CFGR2_TROVS) == (ADC_CFGR2_ROVSE|ADC_CFGR2_TROVS))); - + assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS) == (ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS))); + /* Configuration of Injected Oversampler: */ /* - Oversampling Ratio */ /* - Right bit shift */ - + /* Enable OverSampling mode */ - MODIFY_REG(hadc->Instance->CFGR2, - ADC_CFGR2_JOVSE | - ADC_CFGR2_OVSR | - ADC_CFGR2_OVSS, - ADC_CFGR2_JOVSE | - sConfigInjected->InjecOversampling.Ratio | - sConfigInjected->InjecOversampling.RightBitShift - ); + MODIFY_REG(hadc->Instance->CFGR2, + ADC_CFGR2_JOVSE | + ADC_CFGR2_OVSR | + ADC_CFGR2_OVSS, + ADC_CFGR2_JOVSE | + ((sConfigInjected->InjecOversampling.Ratio - 1UL) << ADC_CFGR2_OVSR_Pos) | + sConfigInjected->InjecOversampling.RightBitShift + ); } else { /* Disable Regular OverSampling */ - CLEAR_BIT( hadc->Instance->CFGR2, ADC_CFGR2_JOVSE); + CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_JOVSE); } - + /* Set sampling time of the selected ADC channel */ LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSamplingTime); - + /* Configure the offset: offset enable/disable, channel, offset value */ - + /* Shift the offset with respect to the selected ADC resolution. */ /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset); - - if(sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) + + if (sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) { /* Set ADC selected offset number */ - LL_ADC_SetOffset(hadc->Instance, sConfigInjected->InjectedOffsetNumber, sConfigInjected->InjectedChannel, tmpOffsetShifted); - + LL_ADC_SetOffset(hadc->Instance, sConfigInjected->InjectedOffsetNumber, sConfigInjected->InjectedChannel, + tmpOffsetShifted); + /* Set ADC selected offset signed saturation */ LL_ADC_SetOffsetSignedSaturation(hadc->Instance, sConfigInjected->InjectedOffsetNumber, (sConfigInjected->InjectedOffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); - + + /* Set ADC selected offset right shift */ + LL_ADC_SetDataRightShift(hadc->Instance, sConfigInjected->InjectedOffsetNumber, (sConfigInjected->InjectedOffsetRightShift == (uint32_t)ENABLE) ? LL_ADC_OFFSET_RSHIFT_ENABLE : LL_ADC_OFFSET_RSHIFT_DISABLE); + } else { @@ -2014,24 +2059,24 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* If this is the case, the corresponding offset number is disabled. */ if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) { - LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_1, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); + LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_1, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); } if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) { - LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_2, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); + LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_2, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); } if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) { - LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_4, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); + LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_4, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); } if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) { - LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_4, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); + LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_4, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE); } } - + } - + /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - Single or differential mode */ @@ -2040,7 +2085,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I { /* Set mode single-ended or differential input of the selected ADC channel */ LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSingleDiff); - + /* Configuration of differential mode */ /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */ if (sConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED) @@ -2048,13 +2093,13 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* Set sampling time of the selected ADC channel */ LL_ADC_SetChannelSamplingTime(hadc->Instance, (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfigInjected->InjectedChannel) + 1UL) & 0x1FUL)), sConfigInjected->InjectedSamplingTime); } - + /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */ /* internal measurement paths enable: If internal channel selected, */ /* enable dedicated internal buffers and path. */ /* Note: these internal measurement paths can be disabled using */ /* HAL_ADC_DeInit(). */ - + if(__LL_ADC_IS_CHANNEL_INTERNAL(sConfigInjected->InjectedChannel)) { /* Configuration of common ADC parameters (continuation) */ @@ -2063,7 +2108,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) { tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); - + /* If the requested internal measurement path has already been enabled, */ /* bypass the configuration processing. */ if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) @@ -2071,7 +2116,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel); - + /* Delay for temperature sensor stabilization time */ /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ @@ -2085,14 +2130,14 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I } } else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL)) - { + { if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel); } } else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) - { + { if (ADC_VREFINT_INSTANCE(hadc)) { LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel); @@ -2106,20 +2151,20 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* If the requested internal measurement path has already been enabled */ /* and other ADC of the common group are enabled, internal */ /* measurement paths cannot be enabled. */ - else + else { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - + tmp_hal_status = HAL_ERROR; } } - + } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -2127,12 +2172,12 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /** * @brief Enable ADC multimode and configure multimode parameters * @note Possibility to update parameters on the fly: - * This function initializes multimode parameters, following - * calls to this function can be used to reconfigure some parameters - * of structure "ADC_MultiModeTypeDef" on the fly, without resetting + * This function initializes multimode parameters, following + * calls to this function can be used to reconfigure some parameters + * of structure "ADC_MultiModeTypeDef" on the fly, without resetting * the ADCs. * The setting of these parameters is conditioned to ADC state. - * For parameters constraints, see comments of structure + * For parameters constraints, see comments of structure * "ADC_MultiModeTypeDef". * @note To move back configuration from multimode to single mode, ADC must * be reset (using function HAL_ADC_Init() ). @@ -2140,56 +2185,56 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I * @param multimode Structure of ADC multimode configuration * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode) +HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; ADC_Common_TypeDef *tmpADC_Common; ADC_HandleTypeDef tmphadcSlave; uint32_t tmphadcSlave_conversion_on_going; - + /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); assert_param(IS_ADC_MULTIMODE(multimode->Mode)); - if(multimode->Mode != ADC_MODE_INDEPENDENT) + if (multimode->Mode != ADC_MODE_INDEPENDENT) { assert_param(IS_ADC_DUAL_DATA_MODE(multimode->DualModeData)); assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay)); } - + /* Process locked */ __HAL_LOCK(hadc); - + ADC_MULTI_SLAVE(hadc, &tmphadcSlave); - + if (tmphadcSlave.Instance == NULL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + return HAL_ERROR; } - + /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated when ADC is disabled or enabled without */ /* conversion on going on regular group: */ /* - Multimode DATA Format configuration */ tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); - if ( (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) - && (tmphadcSlave_conversion_on_going == 0UL) ) + if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) + && (tmphadcSlave_conversion_on_going == 0UL)) { /* Pointer to the common control register */ tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance); - + /* If multimode is selected, configure all multimode parameters. */ /* Otherwise, reset multimode parameters (can be used in case of */ /* transition from multimode to independent mode). */ - if(multimode->Mode != ADC_MODE_INDEPENDENT) + if (multimode->Mode != ADC_MODE_INDEPENDENT) { MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DAMDF, multimode->DualModeData); - + /* Parameters that can be updated only when ADC is disabled: */ /* - Multimode mode selection */ /* - Multimode delay */ @@ -2200,21 +2245,21 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ /* from 1 to 6 clock cycles for 10 and 8 bits */ /* If a higher delay is selected, it will be clipped to maximum delay */ /* range */ - + if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL) { - MODIFY_REG(tmpADC_Common->CCR, - ADC_CCR_DUAL | - ADC_CCR_DELAY, - multimode->Mode | - multimode->TwoSamplingDelay - ); + MODIFY_REG(tmpADC_Common->CCR, + ADC_CCR_DUAL | + ADC_CCR_DELAY, + multimode->Mode | + multimode->TwoSamplingDelay + ); } } else /* ADC_MODE_INDEPENDENT */ { CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DAMDF); - + /* Parameters that can be updated only when ADC is disabled: */ /* - Multimode mode selection */ /* - Multimode delay */ @@ -2230,55 +2275,55 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - + tmp_hal_status = HAL_ERROR; } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; -} +} /** * @brief Enable Injected Queue * @note This function resets CFGR register JQDIS bit in order to enable the * Injected Queue. JQDIS can be written only when ADSTART and JDSTART - * are both equal to 0 to ensure that no regular nor injected - * conversion is ongoing. + * are both equal to 0 to ensure that no regular nor injected + * conversion is ongoing. * @param hadc ADC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); - + /* Parameter can be set only if no conversion is on-going */ - if ( (tmp_adc_is_conversion_on_going_regular == 0UL) + if ((tmp_adc_is_conversion_on_going_regular == 0UL) && (tmp_adc_is_conversion_on_going_injected == 0UL) ) { CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); - + /* Update state, clear previous result related to injected queue overflow */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF); - + tmp_hal_status = HAL_OK; } else { tmp_hal_status = HAL_ERROR; } - + return tmp_hal_status; } @@ -2286,25 +2331,25 @@ HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc) * @brief Disable Injected Queue * @note This function sets CFGR register JQDIS bit in order to disable the * Injected Queue. JQDIS can be written only when ADSTART and JDSTART - * are both equal to 0 to ensure that no regular nor injected - * conversion is ongoing. + * are both equal to 0 to ensure that no regular nor injected + * conversion is ongoing. * @param hadc ADC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance); - + /* Parameter can be set only if no conversion is on-going */ - if ( (tmp_adc_is_conversion_on_going_regular == 0UL) + if ((tmp_adc_is_conversion_on_going_regular == 0UL) && (tmp_adc_is_conversion_on_going_injected == 0UL) ) { @@ -2315,7 +2360,7 @@ HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc) { tmp_hal_status = HAL_ERROR; } - + return tmp_hal_status; } @@ -2323,18 +2368,18 @@ HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc) * @brief Disable ADC voltage regulator. * @note Disabling voltage regulator allows to save power. This operation can * be carried out only when ADC is disabled. - * @note To enable again the voltage regulator, the user is expected to + * @note To enable again the voltage regulator, the user is expected to * resort to HAL_ADC_Init() API. * @param hadc ADC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) { @@ -2345,33 +2390,33 @@ HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc) { tmp_hal_status = HAL_ERROR; } - + return tmp_hal_status; } /** * @brief Enter ADC deep-power-down mode - * @note This mode is achieved in setting DEEPPWD bit and allows to save power - * in reducing leakage currents. It is particularly interesting before + * @note This mode is achieved in setting DEEPPWD bit and allows to save power + * in reducing leakage currents. It is particularly interesting before * entering stop modes. * @note Setting DEEPPWD automatically clears ADVREGEN bit and disables the * ADC voltage regulator. This means that this API encompasses * HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal * calibration is lost. - * @note To exit the ADC deep-power-down mode, the user is expected to + * @note To exit the ADC deep-power-down mode, the user is expected to * resort to HAL_ADC_Init() API as well as to relaunch a calibration * with HAL_ADCEx_Calibration_Start() API or to re-apply a previously * saved calibration factor. * @param hadc ADC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */ if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) { @@ -2382,7 +2427,7 @@ HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef* hadc) { tmp_hal_status = HAL_ERROR; } - + return tmp_hal_status; } diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_adc_ex.h b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_adc_ex.h index d93cb41a5c2..7d727b0d23b 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_adc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_adc_ex.h @@ -22,7 +22,7 @@ #define STM32H7xx_HAL_ADC_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -47,13 +47,13 @@ typedef struct { uint32_t Ratio; /*!< Configures the oversampling ratio. - This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ - + This parameter can be a value between 1 and 1024 */ + uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ -}ADC_InjOversamplingTypeDef; +} ADC_InjOversamplingTypeDef; -/** +/** * @brief Structure definition of ADC group injected and ADC channel affected to ADC group injected * @note Parameters of this structure are shared within 2 scopes: * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset @@ -64,7 +64,7 @@ typedef struct * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff') * - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group. * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups. - * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going + * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going * on ADC groups regular and injected. * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). @@ -77,7 +77,7 @@ typedef struct uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer. This parameter must be a value of @ref ADC_INJ_SEQ_RANKS. - Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by + Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions adjusted) */ uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. @@ -100,7 +100,7 @@ typedef struct Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). - If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case + If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case of another parameter update on the fly) */ uint32_t InjectedOffsetNumber; /*!< Selects the offset number. @@ -111,7 +111,7 @@ typedef struct Offset value must be a positive number. Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. - Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled + Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ uint32_t InjectedOffsetRightShift; /*!< Specifies whether the 1 bit Right-shift feature is used or not. @@ -127,21 +127,21 @@ typedef struct uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer. To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 4. - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. - Discontinuous mode can be enabled only if continuous mode is disabled. + Discontinuous mode can be enabled only if continuous mode is disabled. This parameter can be set to ENABLE or DISABLE. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank). - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion after regular one - This parameter can be set to ENABLE or DISABLE. + This parameter can be set to ENABLE or DISABLE. Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START) Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. @@ -152,11 +152,11 @@ typedef struct FunctionalState QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled. This parameter can be set to ENABLE or DISABLE. If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a - new injected context is set when queue is full, error is triggered by interruption and through function + new injected context is set when queue is full, error is triggered by interruption and through function 'HAL_ADCEx_InjectedQueueOverflowCallback'. Caution: This feature request that the sequence is fully configured before injected conversion start. Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter. - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */ @@ -169,7 +169,7 @@ typedef struct uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. This parameter can be a value of @ref ADC_injected_external_trigger_edge. If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ FunctionalState InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled. @@ -177,18 +177,18 @@ typedef struct Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters. - Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled. + Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled. Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ -}ADC_InjectionConfTypeDef; +} ADC_InjectionConfTypeDef; -/** +/** * @brief Structure definition of ADC multimode * @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs). * Both Master and Slave ADCs must be disabled. */ typedef struct { - uint32_t Mode; /*!< Configures the ADC to operate in independent or multimode. + uint32_t Mode; /*!< Configures the ADC to operate in independent or multimode. This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */ uint32_t DualModeData; /*!< Configures the Dual ADC Mode Data Format: @@ -196,13 +196,13 @@ typedef struct uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. This parameter can be a value of @ref ADC_HAL_EC_MULTI_TWOSMP_DELAY. - Delay range depends on selected resolution: + Delay range depends on selected resolution: from 1 to 9 clock cycles for 16 bits, from 1 to 9 clock cycles for 14 bits from 1 to 8 clock cycles for 12 bits from 1 to 6 clock cycles for 10 bits from 1 to 6 clock cycles for 8 bits */ -}ADC_MultiModeTypeDef; +} ADC_MultiModeTypeDef; /** * @} @@ -247,10 +247,10 @@ typedef struct /** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected) * @{ */ -#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions hardware trigger detection disabled */ -#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */ -#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */ -#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */ +#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions hardware trigger detection disabled */ +#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */ +#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */ +#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */ /** * @} */ @@ -351,7 +351,7 @@ typedef struct /** * @} */ - + /** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields * @{ */ @@ -363,12 +363,12 @@ typedef struct * @} */ -/** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields +/** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields * @{ */ /* ADC_CFGR fields of parameters that can be updated when no conversion (neither regular nor injected) is on-going */ -#define ADC_CFGR_FIELDS_2 ((uint32_t)(ADC_CFGR_DMNGT | ADC_CFGR_AUTDLY)) +#define ADC_CFGR_FIELDS_2 ((uint32_t)(ADC_CFGR_DMNGT | ADC_CFGR_AUTDLY)) /** * @} */ @@ -401,9 +401,9 @@ typedef struct * @note Standard way of multimode configuration change is done from * HAL ADC handle of ADC master using function * "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )". - * Usage of this macro is not the Standard way of multimode - * configuration and can lead to have HAL ADC handles status - * misaligned. Usage of this macro must be limited to cases + * Usage of this macro is not the Standard way of multimode + * configuration and can lead to have HAL ADC handles status + * misaligned. Usage of this macro must be limited to cases * mentionned above. * @param __HANDLE__ ADC handle. * @retval None @@ -452,9 +452,10 @@ typedef struct /** * @brief Check whether or not ADC is independent. * @param __HANDLE__ ADC handle. - * @note When multimode feature is not available, the macro always returns SET. + * @note When multimode feature is not available, the macro always returns SET. * @retval SET (ADC is independent) or RESET (ADC is not). */ + #define ADC_IS_INDEPENDENT(__HANDLE__) \ ( ( ( ((__HANDLE__)->Instance) == ADC3) \ )? \ @@ -532,7 +533,7 @@ typedef struct * @param __CHANNEL__ ADC Channel. * @retval None */ -#define ADC_DIFSEL_CHANNEL(__CHANNEL__) (1UL << (__CHANNEL__)) +#define ADC_DIFSEL_CHANNEL(__CHANNEL__) (1UL << (__CHANNEL__)) /** * @brief Configure calibration factor in differential mode to be set into calibration register. @@ -606,7 +607,7 @@ typedef struct ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \ : \ ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \ - ) + ) /** * @brief Shift the AWD2 and AWD3 threshold in function of the selected ADC resolution. @@ -641,6 +642,7 @@ typedef struct * @retval Common control register */ #define ADC12_COMMON_REGISTER(__HANDLE__) (ADC12_COMMON) + /** * @brief Report common register to ADC3 * @param __HANDLE__: ADC handle @@ -707,7 +709,6 @@ typedef struct * @param __HANDLE__: ADC handle * @retval SET (Independent or Master, or Slave without dual regular conversions enabled) or RESET (Slave ADC with dual regular conversions enabled) */ - #define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) \ ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \ )? \ @@ -747,10 +748,10 @@ typedef struct * @param __HANDLE_SLAVE__ ADC slave handle. * @note if __HANDLE_MASTER__ is the handle of a slave ADC (ADC2) or an independent ADC, __HANDLE_SLAVE__ instance is set to NULL. * @retval None - */ + */ #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ ( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) ) - + /** * @brief Verify the ADC instance connected to the temperature sensor. @@ -775,7 +776,7 @@ typedef struct /** * @brief Verify the length of scheduled injected conversions group. - * @param __LENGTH__ number of programmed conversions. + * @param __LENGTH__ number of programmed conversions. * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large) */ #define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U))) @@ -790,7 +791,7 @@ typedef struct /** * @brief Verify the ADC channel setting. - * @param __CHANNEL__ programmed ADC channel. + * @param __CHANNEL__ programmed ADC channel. * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) */ #define IS_ADC_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_0) || \ @@ -868,7 +869,7 @@ typedef struct /** * @brief Verify the ADC single-ended input or differential mode setting. - * @param __SING_DIFF__ programmed channel setting. + * @param __SING_DIFF__ programmed channel setting. * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid) */ #define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \ @@ -876,24 +877,24 @@ typedef struct /** * @brief Verify the ADC offset management setting. - * @param __OFFSET_NUMBER__ ADC offset management. + * @param __OFFSET_NUMBER__ ADC offset management. * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid) */ #define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \ ((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \ ((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \ ((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \ - ((__OFFSET_NUMBER__) == ADC_OFFSET_4) ) + ((__OFFSET_NUMBER__) == ADC_OFFSET_4) ) /** * @brief Verify the ADC injected channel setting. - * @param __CHANNEL__ programmed ADC injected channel. + * @param __CHANNEL__ programmed ADC injected channel. * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) */ #define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \ ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \ ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \ - ((__CHANNEL__) == ADC_INJECTED_RANK_4) ) + ((__CHANNEL__) == ADC_INJECTED_RANK_4) ) /** * @brief Verify the ADC injected conversions external trigger. @@ -923,25 +924,25 @@ typedef struct * @brief Verify the ADC edge trigger setting for injected group. * @param __EDGE__ programmed ADC edge trigger setting. * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) - */ -#define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ - ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \ - ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ - ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) + */ +#define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ + ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \ + ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ + ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) /** * @brief Verify the ADC multimode setting. * @param __MODE__ programmed ADC multimode setting. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ -#define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \ - ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ - ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ - ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \ - ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \ - ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \ - ((__MODE__) == ADC_DUALMODE_INTERL) || \ - ((__MODE__) == ADC_DUALMODE_ALTERTRIG) ) + */ +#define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \ + ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ + ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ + ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \ + ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \ + ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \ + ((__MODE__) == ADC_DUALMODE_INTERL) || \ + ((__MODE__) == ADC_DUALMODE_ALTERTRIG) ) /** * @brief Verify the ADC dual data mode setting. @@ -974,7 +975,7 @@ typedef struct */ #define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \ ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \ - ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) ) + ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) ) /** * @brief Verify the ADC analog watchdog mode setting. @@ -987,38 +988,38 @@ typedef struct ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ - ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) + ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) /** * @brief Verify the ADC conversion (regular or injected or both). * @param __CONVERSION__ ADC conversion group. * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid) */ -#define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \ - ((__CONVERSION__) == ADC_INJECTED_GROUP) || \ - ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) ) +#define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \ + ((__CONVERSION__) == ADC_INJECTED_GROUP) || \ + ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) ) /** * @brief Verify the ADC event type. * @param __EVENT__ ADC event. * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid) */ -#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \ - ((__EVENT__) == ADC_AWD_EVENT) || \ - ((__EVENT__) == ADC_AWD2_EVENT) || \ - ((__EVENT__) == ADC_AWD3_EVENT) || \ - ((__EVENT__) == ADC_OVR_EVENT) || \ - ((__EVENT__) == ADC_JQOVF_EVENT) ) +#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \ + ((__EVENT__) == ADC_AWD_EVENT) || \ + ((__EVENT__) == ADC_AWD2_EVENT) || \ + ((__EVENT__) == ADC_AWD3_EVENT) || \ + ((__EVENT__) == ADC_OVR_EVENT) || \ + ((__EVENT__) == ADC_JQOVF_EVENT) ) /** - * @brief Verify the ADC oversampling ratio. + * @brief Verify the ADC oversampling ratio. * @param RATIO: programmed ADC oversampling ratio. * @retval SET (RATIO is a valid value) or RESET (RATIO is invalid) */ -#define IS_ADC_OVERSAMPLING_RATIO(RATIO) ((RATIO) < 1024UL) +#define IS_ADC_OVERSAMPLING_RATIO(RATIO) (((RATIO) >= 1UL) && ((RATIO) <= 1024UL)) /** - * @brief Verify the ADC oversampling shift. + * @brief Verify the ADC oversampling shift. * @param __SHIFT__ programmed ADC oversampling shift. * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid) */ @@ -1033,27 +1034,27 @@ typedef struct ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 )) /** - * @brief Verify the ADC oversampling triggered mode. - * @param __MODE__ programmed ADC oversampling triggered mode. + * @brief Verify the ADC oversampling triggered mode. + * @param __MODE__ programmed ADC oversampling triggered mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \ - ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) + ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) /** - * @brief Verify the ADC oversampling regular conversion resumed or continued mode. - * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode. + * @brief Verify the ADC oversampling regular conversion resumed or continued mode. + * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \ - ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) ) + ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) ) /** - * @brief Verify the DFSDM mode configuration. - * @param __HANDLE__ ADC handle. + * @brief Verify the DFSDM mode configuration. + * @param __HANDLE__ ADC handle. * @note When DMSDFM configuration is not supported, the macro systematically reports SET. For * this reason, the input parameter is the ADC handle and not the configuration parameter - * directly. + * directly. * @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid) */ #if defined(DFSDM1_Channel0) @@ -1065,15 +1066,15 @@ typedef struct /** * @brief Return the DFSDM configuration mode. - * @param __HANDLE__ ADC handle. - * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled). + * @param __HANDLE__ ADC handle. + * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled). * For this reason, the input parameter is the ADC handle and not the configuration parameter - * directly. + * directly. * @retval DFSDM configuration mode */ #if defined(DFSDM1_Channel0) #define ADC_CFGR_DFSDM(__HANDLE__) ((__HANDLE__)->Init.DFSDMConfig) -#else +#else #define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL) #endif @@ -1093,20 +1094,21 @@ typedef struct /* IO operation functions *****************************************************/ /* ADC calibration */ -HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t CalibrationMode, uint32_t SingleDiff); +HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff); uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff); -HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t* LinearCalib_Buffer); +HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t* LinearCalib_Buffer); HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor); HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t* LinearCalib_Buffer); +HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_FactorLoad(ADC_HandleTypeDef *hadc); /* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); +HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); /* Non-blocking mode: Interruption */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc); /* ADC multimode */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); @@ -1114,20 +1116,20 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc); /* ADC retrieve conversion value intended to be used with polling or interruption */ -uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank); +uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank); /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ -void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc); -void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc); -void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc); -void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc); -void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc); +void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc); +void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc); +void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc); +void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc); +void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc); /* ADC group regular conversions stop */ -HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc); /** * @} @@ -1137,12 +1139,12 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc); * @{ */ /* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected); +HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,ADC_InjectionConfTypeDef* sConfigInjected); HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode); -HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc); /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_conf.h b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_conf.h index 1fb15bd2bf0..5446926b96b 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_conf.h +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_conf.h @@ -121,15 +121,6 @@ #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/ -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ - /** * @brief External Low Speed oscillator (LSE) value. * This value is used by the UART, RTC HAL module to compute the system frequency @@ -144,7 +135,7 @@ #endif /* LSE_STARTUP_TIMEOUT */ #if !defined (LSI_VALUE) - #define LSI_VALUE ((uint32_t)32000) /*!< LSI Typical Value in Hz*/ + #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/ #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz The real value may vary depending on the variations in voltage and temperature.*/ @@ -169,6 +160,7 @@ #define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */ #define USE_RTOS 0 #define USE_SD_TRANSCEIVER 1U /*!< use uSD Transceiver */ +#define USE_SPI_CRC 1U /*!< use CRC in SPI */ #define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ #define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_cryp.c b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_cryp.c index 9510324c6d9..8e8da38cdfa 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_cryp.c +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_cryp.c @@ -139,13 +139,15 @@ (##) Final phase: IP generates the authenticated tag (T) using the last block of data. *** Callback registration *** - ============================================= + ============================= + [..] The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. Use Functions @ref HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback() to register an interrupt callback. + [..] Function @ref HAL_CRYP_RegisterCallback() allows to register following callbacks: (+) InCpltCallback : Input FIFO transfer completed callback. (+) OutCpltCallback : Output FIFO transfer completed callback. @@ -155,6 +157,7 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. + [..] Use function @ref HAL_CRYP_UnRegisterCallback() to reset a callback to the default weak function. @ref HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle, @@ -166,6 +169,7 @@ (+) MspInitCallback : CRYP MspInit. (+) MspDeInitCallback : CRYP MspDeInit. + [..] By default, after the @ref HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET all callbacks are set to the corresponding weak functions : examples @ref HAL_CRYP_InCpltCallback() , @ref HAL_CRYP_OutCpltCallback(). @@ -175,6 +179,7 @@ if not, MspInit or MspDeInit are not null, the @ref HAL_CRYP_Init() / @ref HAL_CRYP_DeInit() keep and use the user MspInit/MspDeInit functions (registered beforehand) + [..] Callbacks can be registered/unregistered in HAL_CRYP_STATE_READY state only. Exception done MspInit/MspDeInit callbacks that can be registered/unregistered in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state, @@ -183,6 +188,7 @@ using @ref HAL_CRYP_RegisterCallback() before calling @ref HAL_CRYP_DeInit() or @ref HAL_CRYP_Init() function. + [..] When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks are set to the corresponding weak functions. @@ -331,7 +337,9 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp); static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp); static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp); +#if !defined (CRYP_VER_2_2) static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); +#endif /*End of not defined CRYP_VER_2_2*/ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp); static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp); static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); @@ -440,9 +448,10 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) /* Set the key size(This bit field is ‘don’t care’ in the DES or TDES modes) data type and Algorithm */ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); - +#if !defined (CRYP_VER_2_2) /* Read Device ID to indicate CRYP1 IP Version */ hcryp->Version = HAL_GetREVID(); +#endif /*End of not defined CRYP_VER_2_2*/ /* Reset Error Code field */ hcryp->ErrorCode = HAL_CRYP_ERROR_NONE; @@ -1149,7 +1158,7 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, u HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output) { uint32_t algo; - HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status; if (hcryp->State == HAL_CRYP_STATE_READY) { @@ -1216,7 +1225,8 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input /* Enable CRYP to start DES/TDES process*/ __HAL_CRYP_ENABLE(hcryp); - + + status = HAL_OK; break; case CRYP_AES_ECB: @@ -2318,7 +2328,9 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) /* Compute the number of padding bytes in last block of payload */ npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size); +#if !defined (CRYP_VER_2_2) if (hcryp->Version >= REV_ID_B) +#endif /*End of not defined CRYP_VER_2_2*/ { /* Case of AES GCM payload encryption or AES CCM payload decryption to get right tag */ temp_cr_algodir = hcryp->Instance->CR & CRYP_CR_ALGODIR; @@ -2795,7 +2807,9 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t /* Disable the CRYP peripheral */ __HAL_CRYP_DISABLE(hcryp); +#if !defined (CRYP_VER_2_2) if (hcryp->Version >= REV_ID_B) +#endif /*End of not defined CRYP_VER_2_2*/ { /* Set to 0 the number of non-valid bytes using NPBLB register*/ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U); @@ -2849,7 +2863,9 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t if ((hcryp->Size % 16U) != 0U) { +#if !defined (CRYP_VER_2_2) if (hcryp->Version >= REV_ID_B) +#endif /*End of not defined CRYP_VER_2_2*/ { /* Compute the number of padding bytes in last block of payload */ npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size); @@ -2924,12 +2940,14 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t } } } +#if !defined (CRYP_VER_2_2) else /* Workaround to be used */ { /* Workaround 2 for STM32H7 below rev.B To generate correct TAG only when size of the last block of payload is inferior to 128 bits, in case of GCM encryption or CCM decryption*/ CRYP_Workaround(hcryp, Timeout); } /* end of NPBLB or Workaround*/ +#endif /*End of not defined CRYP_VER_2_2*/ } @@ -3070,7 +3088,9 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp) /* Disable the CRYP peripheral */ __HAL_CRYP_DISABLE(hcryp); +#if !defined (CRYP_VER_2_2) if (hcryp->Version >= REV_ID_B) +#endif /*End of not defined CRYP_VER_2_2*/ { /* Set to 0 the number of non-valid bytes using NPBLB register*/ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U); @@ -3103,7 +3123,9 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp) /* Compute the number of padding bytes in last block of payload */ npblb = 16U - (uint32_t)hcryp->Size; +#if !defined (CRYP_VER_2_2) if (hcryp->Version >= REV_ID_B) +#endif /*End of not defined CRYP_VER_2_2*/ { /* Set Npblb in case of AES GCM payload encryption to get right tag*/ if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT) @@ -3222,6 +3244,15 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t /* Enable the CRYP peripheral */ __HAL_CRYP_ENABLE(hcryp); +#if defined (CRYP_VER_2_2) + { + /* for STM32H7 rev.B and above Write B0 packet into CRYP_DR*/ + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2); + hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3); + } +#else if (hcryp->Version >= REV_ID_B) { /* for STM32H7 rev.B and above Write B0 packet into CRYP_DR*/ @@ -3261,6 +3292,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3); } } +#endif /* Get tick */ tickstart = HAL_GetTick(); @@ -3301,8 +3333,9 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t /* Disable the CRYP peripheral */ __HAL_CRYP_DISABLE(hcryp); - +#if !defined (CRYP_VER_2_2) if (hcryp->Version >= REV_ID_B) +#endif /*End of not defined CRYP_VER_2_2*/ { /* Set to 0 the number of non-valid bytes using NPBLB register*/ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U); @@ -3355,7 +3388,9 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t if ((hcryp->Size % 16U) != 0U) { +#if !defined (CRYP_VER_2_2) if (hcryp->Version >= REV_ID_B) +#endif /*End of not defined CRYP_VER_2_2*/ { /* Compute the number of padding bytes in last block of payload */ npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size); @@ -3430,6 +3465,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t } } } +#if !defined (CRYP_VER_2_2) else /* No NPBLB, Workaround to be used */ { /* CRYP Workaround : CRYP1 generates correct TAG during CCM decryption only when ciphertext blocks size is multiple of @@ -3437,6 +3473,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t is selected, then the TAG message will be wrong.*/ CRYP_Workaround(hcryp, Timeout); } +#endif /*End of not defined CRYP_VER_2_2*/ } /* Return function status */ @@ -3473,7 +3510,9 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) __HAL_CRYP_ENABLE(hcryp); /*Write the B0 packet into CRYP_DR*/ +#if !defined (CRYP_VER_2_2) if (hcryp->Version >= REV_ID_B) +#endif /*End of not defined CRYP_VER_2_2*/ { /* for STM32H7 rev.B and above data has not to be swapped */ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0); @@ -3481,6 +3520,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2); hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3); } +#if !defined (CRYP_VER_2_2) else /* data has to be swapped according to the DATATYPE */ { if (hcryp->Init.DataType == CRYP_DATATYPE_8B) @@ -3512,7 +3552,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3); } } - +#endif /*End of not defined CRYP_VER_2_2*/ /*Wait for the CRYPEN bit to be cleared*/ count = CRYP_TIMEOUT_GCMCCMINITPHASE; do @@ -3580,8 +3620,9 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) __HAL_CRYP_ENABLE(hcryp); /*Write the B0 packet into CRYP_DR*/ - +#if !defined (CRYP_VER_2_2) if (hcryp->Version >= REV_ID_B) +#endif /*End of not defined CRYP_VER_2_2*/ { /* for STM32H7 rev.B and above data has not to be swapped */ hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0); @@ -3589,6 +3630,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2); hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3); } +#if !defined (CRYP_VER_2_2) else /* data has to be swapped according to the DATATYPE */ { if (hcryp->Init.DataType == CRYP_DATATYPE_8B) @@ -3620,6 +3662,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3); } } +#endif /*End of not defined CRYP_VER_2_2*/ /*Wait for the CRYPEN bit to be cleared*/ count = CRYP_TIMEOUT_GCMCCMINITPHASE; do @@ -3654,8 +3697,9 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) /* Disable the CRYP peripheral */ __HAL_CRYP_DISABLE(hcryp); - +#if !defined (CRYP_VER_2_2) if (hcryp->Version >= REV_ID_B) +#endif /*End of not defined CRYP_VER_2_2*/ { /* Set to 0 the number of non-valid bytes using NPBLB register*/ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U); @@ -3686,7 +3730,9 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) /* Compute the number of padding bytes in last block of payload */ npblb = 16U - (uint32_t)(hcryp->Size); +#if !defined (CRYP_VER_2_2) if (hcryp->Version >= REV_ID_B) +#endif /*End of not defined CRYP_VER_2_2*/ { /* Set Npblb in case of AES CCM payload decryption to get right tag*/ if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT) @@ -3780,10 +3826,16 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) uint32_t temp; /* Temporary CrypOutBuff */ uint32_t lastwordsize; uint32_t npblb; - uint32_t temp_cr_algodir; - + uint32_t temp_cr_algodir; + uint8_t negative = 0U; + /***************************** Payload phase *******************************/ + if ((hcryp->Size / 4U) < hcryp->CrypInCount) + { + negative = 1U; + } + if (hcryp->Size == 0U) { /* Disable interrupts */ @@ -3796,7 +3848,8 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) hcryp->State = HAL_CRYP_STATE_READY; } - else if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U) + else if ((((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U) && + (negative == 0U)) { if ((hcryp->Instance->IMSCR & CRYP_IMSCR_INIM)!= 0x0U) { @@ -3876,7 +3929,9 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) /* Compute the number of padding bytes in last block of payload */ npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size); +#if !defined (CRYP_VER_2_2) if (hcryp->Version >= REV_ID_B) +#endif /*End of not defined CRYP_VER_2_2*/ { /* Set Npblb in case of AES GCM payload encryption and CCM decryption to get right tag */ temp_cr_algodir = hcryp->Instance->CR & CRYP_CR_ALGODIR; @@ -4252,7 +4307,9 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) /* Disable the CRYP peripheral */ __HAL_CRYP_DISABLE(hcryp); +#if !defined (CRYP_VER_2_2) if (hcryp->Version >= REV_ID_B) +#endif /*End of not defined CRYP_VER_2_2*/ { /* Set to 0 the number of non-valid bytes using NPBLB register*/ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U); @@ -4300,7 +4357,7 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) } } - +#if !defined (CRYP_VER_2_2) /** * @brief Workaround used for GCM/CCM mode. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains @@ -4341,9 +4398,8 @@ static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) /* Disable CRYP to start the final phase */ __HAL_CRYP_DISABLE(hcryp); - /*Load CRYP_IV1R register content in a temporary variable. Decrement the value - by 1 and reinsert the result in CRYP_IV1R register*/ - hcryp->Instance->IV1RR = 0x5U; + /*Update CRYP_IV1R register and ALGOMODE*/ + hcryp->Instance->IV1RR = ((hcryp->Instance->CSGCMCCM7R)-1U); MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR); /* Enable CRYP to start the final phase */ @@ -4406,6 +4462,67 @@ static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) /* configured final phase */ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL); + if ( (hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_32B) + { + if ((npblb %4U)==1U) + { + intermediate_data[lastwordsize-1U] &= 0xFFFFFF00U; + } + if ((npblb %4U)==2U) + { + intermediate_data[lastwordsize-1U] &= 0xFFFF0000U; + } + if ((npblb %4U)==3U) + { + intermediate_data[lastwordsize-1U] &= 0xFF000000U; + } + } + else if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_8B) + { + if ((npblb %4U)==1U) + { + intermediate_data[lastwordsize-1U] &= __REV(0xFFFFFF00U); + } + if ((npblb %4U)==2U) + { + intermediate_data[lastwordsize-1U] &= __REV(0xFFFF0000U); + } + if ((npblb %4U)==3U) + { + intermediate_data[lastwordsize-1U] &= __REV(0xFF000000U); + } + } + else if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_16B) + { + if ((npblb %4U)==1U) + { + intermediate_data[lastwordsize-1U] &= __ROR((0xFFFFFF00U), 16); + } + if ((npblb %4U)==2U) + { + intermediate_data[lastwordsize-1U] &= __ROR((0xFFFF0000U), 16); + } + if ((npblb %4U)==3U) + { + intermediate_data[lastwordsize-1U] &= __ROR((0xFF000000U), 16); + } + } + else /*CRYP_DATATYPE_1B*/ + { + if ((npblb %4U)==1U) + { + intermediate_data[lastwordsize-1U] &= __RBIT(0xFFFFFF00U); + } + if ((npblb %4U)==2U) + { + intermediate_data[lastwordsize-1U] &= __RBIT(0xFFFF0000U); + } + if ((npblb %4U)==3U) + { + intermediate_data[lastwordsize-1U] &= __RBIT(0xFF000000U); + } + } + for (index = 0U; index < lastwordsize ; index ++) { /*Write the intermediate_data in the IN FIFO */ @@ -4589,7 +4706,7 @@ static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) /* Process Unlocked */ __HAL_UNLOCK(hcryp); } - +#endif /*End of not defined CRYP_VER_2_2*/ /** * @brief Handle CRYP hardware block Timeout when waiting for IFEM flag to be raised. diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_cryp_ex.c b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_cryp_ex.c index 816b87eeb81..0a9b8b51889 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_cryp_ex.c +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_cryp_ex.c @@ -157,14 +157,17 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u /* Write the number of bits in header (64 bits) followed by the number of bits in the payload */ +#if !defined (CRYP_VER_2_2) /* STM32H7 rev.B and above : data has to be inserted normally (no swapping)*/ if (hcryp->Version >= REV_ID_B) +#endif /*End of not defined CRYP_VER_2_2*/ { hcryp->Instance->DIN = 0U; hcryp->Instance->DIN = (uint32_t)(headerlength); hcryp->Instance->DIN = 0U; hcryp->Instance->DIN = (uint32_t)(inputlength); } +#if !defined (CRYP_VER_2_2) else/* data has to be swapped according to the DATATYPE */ { if (hcryp->Init.DataType == CRYP_DATATYPE_1B) @@ -200,6 +203,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u /* Nothing to do */ } } +#endif /*End of not defined CRYP_VER_2_2*/ /* Wait for OFNE flag to be raised */ tickstart = HAL_GetTick(); while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE)) @@ -312,8 +316,10 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u ctr0[2] = hcryp->Init.B0[2]; ctr0[3] = hcryp->Init.B0[3] & CRYP_CCM_CTR0_3; +#if !defined (CRYP_VER_2_2) /*STM32H7 rev.B and above : data has to be inserted normally (no swapping)*/ if (hcryp->Version >= REV_ID_B) +#endif /*End of not defined CRYP_VER_2_2*/ { hcryp->Instance->DIN = *(uint32_t *)(ctr0addr); ctr0addr += 4U; @@ -323,6 +329,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u ctr0addr += 4U; hcryp->Instance->DIN = *(uint32_t *)(ctr0addr); } +#if !defined (CRYP_VER_2_2) else /* data has to be swapped according to the DATATYPE */ { if (hcryp->Init.DataType == CRYP_DATATYPE_8B) @@ -366,6 +373,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u hcryp->Instance->DIN = *(uint32_t *)(ctr0addr); } } +#endif /*End of not defined CRYP_VER_2_2*/ /* Wait for OFNE flag to be raised */ tickstart = HAL_GetTick(); while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE)) diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_flash.c b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_flash.c index f99e25a9169..46abf9e692e 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_flash.c +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_flash.c @@ -205,7 +205,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress, if(bank == FLASH_BANK_1) { - /* If the program operation is completed, disable the PG*/ + /* If the program operation is completed, disable the PG */ CLEAR_BIT(FLASH->CR1, FLASH_CR_PG); } else @@ -289,7 +289,7 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddre /* Set PG bit */ SET_BIT(FLASH->CR2, FLASH_CR_PG); - /* Enable End of Operation and Error interrupts for Bank2*/ + /* Enable End of Operation and Error interrupts for Bank2 */ __HAL_FLASH_ENABLE_IT_BANK2(FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK2 | FLASH_IT_PGSERR_BANK2 | \ FLASH_IT_STRBERR_BANK2 | FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK2); } @@ -328,10 +328,10 @@ void HAL_FLASH_IRQHandler(void) { if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE_BANK1) { - /*Nb of sector to erased can be decreased*/ + /* Nb of sector to erased can be decreased */ pFlash.NbSectorsToErase--; - /* Check if there are still sectors to erase*/ + /* Check if there are still sectors to erase */ if(pFlash.NbSectorsToErase != 0U) { /* Indicate user which sector has been erased */ @@ -340,7 +340,7 @@ void HAL_FLASH_IRQHandler(void) /* Clear bank 1 End of Operation pending bit */ __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_EOP_BANK1); - /*Increment sector number*/ + /* Increment sector number */ pFlash.Sector++; temp = pFlash.Sector; FLASH_Erase_Sector(temp, FLASH_BANK_1, pFlash.VoltageForErase); @@ -462,6 +462,7 @@ void HAL_FLASH_IRQHandler(void) /* Check FLASH Bank1 operation error flags */ errorflag = FLASH->SR1 & (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | FLASH_FLAG_STRBERR_BANK1 | \ FLASH_FLAG_INCERR_BANK1 | FLASH_FLAG_OPERR_BANK1); + if(errorflag != 0U) { /* Save the error code */ @@ -556,7 +557,7 @@ void HAL_FLASH_IRQHandler(void) * Mass Erase: Bank number which has been requested to erase * Sectors Erase: Sector which has been erased * (if 0xFFFFFFFF, it means that all the selected sectors have been erased) - * Program Address which was selected for data program + * Program: Address which was selected for data program * @retval None */ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_flash.h b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_flash.h index b92f26d220d..1d1232e9b62 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_flash.h +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_flash.h @@ -91,7 +91,7 @@ typedef struct * @brief FLASH Error Code * @{ */ -#define HAL_FLASH_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_FLASH_ERROR_NONE 0x00000000U /*!< No error */ #define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR /*!< Write Protection Error */ #define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR /*!< Program Sequence Error */ @@ -134,7 +134,7 @@ typedef struct /** @defgroup FLASH_Type_Program FLASH Type Program * @{ */ -#define FLASH_TYPEPROGRAM_FLASHWORD 0x03U /*!< Program a flash word (256-bit) at a specified address */ +#define FLASH_TYPEPROGRAM_FLASHWORD 0x01U /*!< Program a flash word (256-bit) at a specified address */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_flash_ex.c b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_flash_ex.c index c095e4ee25c..11dca39286c 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_flash_ex.c +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_flash_ex.c @@ -462,7 +462,8 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) FLASH_OB_BootAddConfig(pOBInit->BootConfig, pOBInit->BootAddr0, pOBInit->BootAddr1); } #endif /*DUAL_CORE*/ - /*Bank1 secure area configuration*/ + + /*Bank1 secure area configuration*/ if((pOBInit->OptionType & OPTIONBYTE_SECURE_AREA) == OPTIONBYTE_SECURE_AREA) { FLASH_OB_SecureAreaConfig(pOBInit->SecureAreaConfig, pOBInit->SecureAreaStartAddr, pOBInit->SecureAreaEndAddr,pOBInit->Banks); diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_flash_ex.h b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_flash_ex.h index 0d91e1723c4..c7a7d7d0d04 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_flash_ex.h +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_flash_ex.h @@ -130,7 +130,7 @@ typedef struct uint32_t SecureAreaStartAddr; /*!< Bank Secure area Start address. This parameter must be a value between begin address and end address of bank1 */ - uint32_t SecureAreaEndAddr; /*!< Bank Secure area End address . + uint32_t SecureAreaEndAddr; /*!< Bank Secure area End address. This parameter must be a value between Secure Area Start address and end address of a bank1 */ } FLASH_OBProgramInitTypeDef; @@ -514,7 +514,7 @@ typedef struct #define OB_USER_SECURITY 0x0040U /*!< security selection */ #define OB_USER_IOHSLV 0x0080U /*!< IO HSLV selection */ #define OB_USER_SWAP_BANK 0x0100U /*!< Bank swap selection */ -#if defined(DUAL_CORE) +#if defined (DUAL_CORE) #define OB_USER_IWDG2_SW 0x0200U /*!< Window watchdog selection */ #define OB_USER_BCM4 0x0400U /*!< CM4 boot selection */ #define OB_USER_BCM7 0x0800U /*!< CM7 boot selection */ @@ -715,16 +715,7 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_ ((LATENCY) == FLASH_LATENCY_14) || \ ((LATENCY) == FLASH_LATENCY_15)) -#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) || \ - (((ADDRESS) >= FLASH_OTP_BANK1_BASE) && ((ADDRESS) <= FLASH_OTP_BANK1_END)) || \ - (((ADDRESS) >= FLASH_OTP_BANK2_BASE) && ((ADDRESS) <= FLASH_OTP_BANK2_END))) - -#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0U) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL)) - -#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\ - ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\ - ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\ - ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7)) +#define IS_FLASH_SECTOR(SECTOR) ((SECTOR) < FLASH_SECTOR_TOTAL) #define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFFFFF00U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_gpio.c b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_gpio.c index 100f5021885..641c7e93424 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_gpio.c +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_gpio.c @@ -330,10 +330,10 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) /*------------------------- EXTI Mode Configuration --------------------*/ /* Clear the External Interrupt or Event for the current IO */ tmp = SYSCFG->EXTICR[position >> 2U]; - tmp &= (0x0FUL << (8U * (position & 0x03U))); - if (tmp == (GPIO_GET_INDEX(GPIOx) << (8U * (position & 0x03U)))) + tmp &= (0x0FUL << (4U * (position & 0x03U))); + if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) { - tmp = 0x0FUL << (8U * (position & 0x03U)); + tmp = 0x0FUL << (4U * (position & 0x03U)); SYSCFG->EXTICR[position >> 2U] &= ~tmp; /* Clear EXTI line configuration for Current CPU */ @@ -487,9 +487,10 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) GPIOx->LCKR = GPIO_Pin; /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ GPIOx->LCKR = tmp; - /* Read LCKK bit*/ + /* Read LCKK register. This read is mandatory to complete key lock sequence*/ tmp = GPIOx->LCKR; + /* read again in order to confirm lock is active */ if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00U) { return HAL_OK; diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_hcd.c b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_hcd.c index f7175fdcb30..5ae9674f197 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_hcd.c +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_hcd.c @@ -373,14 +373,13 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint16_t length, uint8_t do_ping) { - UNUSED(do_ping); - hhcd->hc[ch_num].ep_is_in = direction; hhcd->hc[ch_num].ep_type = ep_type; if (token == 0U) { hhcd->hc[ch_num].data_pid = HC_PID_SETUP; + hhcd->hc[ch_num].do_ping = do_ping; } else { @@ -534,20 +533,19 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) /* Handle Host Disconnect Interrupts */ if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT)) { + __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT); - /* Cleanup HPRT */ - USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \ - USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); - - /* Handle Host Port Disconnect Interrupt */ + if ((USBx_HPRT0 & USB_OTG_HPRT_PCSTS) == 0U) + { + /* Handle Host Port Disconnect Interrupt */ #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->DisconnectCallback(hhcd); + hhcd->DisconnectCallback(hhcd); #else - HAL_HCD_Disconnect_Callback(hhcd); + HAL_HCD_Disconnect_Callback(hhcd); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ - (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); - __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT); + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); + } } /* Handle Host Port Interrupts */ @@ -1009,6 +1007,7 @@ HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd) __HAL_HCD_ENABLE(hhcd); (void)USB_DriveVbus(hhcd->Instance, 1U); __HAL_UNLOCK(hhcd); + return HAL_OK; } @@ -1023,6 +1022,7 @@ HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd) __HAL_LOCK(hhcd); (void)USB_StopHost(hhcd->Instance); __HAL_UNLOCK(hhcd); + return HAL_OK; } @@ -1555,8 +1555,6 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) { if ((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS) { - USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT); - #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) hhcd->ConnectCallback(hhcd); #else @@ -1593,10 +1591,8 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) } #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) hhcd->PortEnabledCallback(hhcd); - hhcd->ConnectCallback(hhcd); #else HAL_HCD_PortEnabled_Callback(hhcd); - HAL_HCD_Connect_Callback(hhcd); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } @@ -1607,12 +1603,6 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) #else HAL_HCD_PortDisabled_Callback(hhcd); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ - - /* Cleanup HPRT */ - USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \ - USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); - - USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT); } } diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_hrtim.c b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_hrtim.c index 2d17c161ada..18d208c86c6 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_hrtim.c +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_hrtim.c @@ -274,6 +274,7 @@ Use Functions HAL_HRTIM_RegisterCallback() or HAL_HRTIM_TIMxRegisterCallback() to register an interrupt callback. + [..] Function HAL_HRTIM_RegisterCallback() allows to register following callbacks: (+) Fault1Callback : Fault 1 interrupt callback function (+) Fault2Callback : Fault 2 interrupt callback function @@ -287,6 +288,7 @@ (+) MspInitCallback : HRTIM MspInit callback function (+) MspDeInitCallback : HRTIM MspInit callback function + [..] Function HAL_HRTIM_TIMxRegisterCallback() allows to register following callbacks: (+) RegistersUpdateCallback : Timer x Update interrupt callback function (+) RepetitionEventCallback : Timer x Repetition interrupt callback function @@ -304,13 +306,16 @@ (+) Output2ResetCallback : Timer x output 2 reset interrupt callback function (+) BurstDMATransferCallback : Timer x Burst DMA completed interrupt callback function + [..] Both functions take as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. + [..] Use function HAL_HRTIM_UnRegisterCallback or HAL_HRTIM_TIMxUnRegisterCallback to reset a callback to the default weak function. Both functions take as parameters the HAL peripheral handle and the Callback ID. + [..] By default, after the HAL_HRTIM_Init() and when the state is HAL_HRTIM_STATE_RESET all callbacks are set to the corresponding weak functions (e.g HAL_HRTIM_Fault1Callback) Exception done for MspInit and MspDeInit functions that are reset to the legacy @@ -319,14 +324,16 @@ not null, the HAL_HRTIM_Init()/ HAL_HRTIM_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] Callbacks can be registered/unregistered in HAL_HRTIM_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered in HAL_HRTIM_STATE_READY or HAL_HRTIM_STATE_RESET states, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. Then, the user first registers the MspInit/MspDeInit user callbacks using HAL_HRTIM_RegisterCallback() before calling HAL_HRTIM_DeInit() - or @ref HAL_HRTIM_Init() function. + or HAL_HRTIM_Init() function. + [..] When the compilation flag USE_HAL_HRTIM_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks are set to the corresponding weak functions. @@ -1198,7 +1205,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg) { uint32_t CompareUnit = (uint32_t)RESET; - HRTIM_OutputCfgTypeDef OutputCfg = {0}; + HRTIM_OutputCfgTypeDef OutputCfg; /* Check parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel)); @@ -4655,8 +4662,13 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, } else { - /* nothing to do */ + /* nothing to do */ } + } + else + { + /* Clear HRTIM_TIMxCR.DELCMP2 bitfield */ + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP2, 0U); } break; } @@ -4695,8 +4707,13 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim, } else { - /* nothing to do */ + /* nothing to do */ } + } + else + { + /* Clear HRTIM_TIMxCR.DELCMP4 bitfield */ + MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP4, 0U); } break; } @@ -6415,7 +6432,7 @@ uint32_t HAL_HRTIM_GetIdlePushPullStatus(HRTIM_HandleTypeDef * hhrtim, * @brief This function handles HRTIM interrupt request. * @param hhrtim pointer to HAL HRTIM handle * @param TimerIdx Timer index - * This parameter can be any value of @ref HRTIM_Timer_Index + * This parameter can be any value of HRTIM_Timer_Index * @retval None */ void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef * hhrtim, @@ -7452,7 +7469,7 @@ HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, * @} */ -/** @addtogroup HRTIM_Private_Functions HRTIM Private Functions +/** @addtogroup HRTIM_Private_Functions * @{ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_hrtim.h b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_hrtim.h index 48e0e679fb7..4cf070c1f13 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_hrtim.h +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_hrtim.h @@ -961,90 +961,38 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @brief Constants defining the events that can be selected to configure the * set crossbar of a timer output */ -#define HRTIM_OUTPUTSET_NONE 0x00000000U /*!< Reset the output set crossbar */ -#define HRTIM_OUTPUTSET_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces the output to its active state */ -#define HRTIM_OUTPUTSET_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces the output to its active state */ -#define HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its active state */ -#define HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its active state */ -#define HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its active state */ -#define HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its active state */ -/* Timer Events mapping for Timer A */ -#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */ -/* Timer Events mapping for Timer B */ -#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */ -/* Timer Events mapping for Timer C */ -#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */ -/* Timer Events mapping for Timer D */ -#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */ -/* Timer Events mapping for Timer E */ -#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */ -/* Timer Events mapping for Timer F */ -#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */ -#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */ - -#define HRTIM_OUTPUTSET_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces the output to its active state */ -#define HRTIM_OUTPUTSET_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces the output to its active state */ -#define HRTIM_OUTPUTSET_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces the output to its active state */ -#define HRTIM_OUTPUTSET_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces the output to its active state */ -#define HRTIM_OUTPUTSET_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces the output to its active state */ -#define HRTIM_OUTPUTSET_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces the output to its active state */ -#define HRTIM_OUTPUTSET_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces the output to its active state */ -#define HRTIM_OUTPUTSET_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces the output to its active state */ -#define HRTIM_OUTPUTSET_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces the output to its active state */ -#define HRTIM_OUTPUTSET_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces the output to its active state */ -#define HRTIM_OUTPUTSET_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces the output to its active state */ +#define HRTIM_OUTPUTSET_NONE 0x00000000U /*!< Reset the output set crossbar */ +#define HRTIM_OUTPUTSET_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its active state */ +#define HRTIM_OUTPUTSET_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces the output to its active state */ +#define HRTIM_OUTPUTSET_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces the output to its active state */ +#define HRTIM_OUTPUTSET_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces the output to its active state */ +#define HRTIM_OUTPUTSET_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces the output to its active state */ +#define HRTIM_OUTPUTSET_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces the output to its active state */ +#define HRTIM_OUTPUTSET_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces the output to its active state */ +#define HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its active state */ +#define HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its active state */ +#define HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its active state */ +#define HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its active state */ +#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */ +#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */ +#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */ +#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */ +#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */ +#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */ +#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */ +#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */ +#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */ +#define HRTIM_OUTPUTSET_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces the output to its active state */ +#define HRTIM_OUTPUTSET_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces the output to its active state */ +#define HRTIM_OUTPUTSET_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces the output to its active state */ +#define HRTIM_OUTPUTSET_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces the output to its active state */ +#define HRTIM_OUTPUTSET_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces the output to its active state */ +#define HRTIM_OUTPUTSET_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces the output to its active state */ +#define HRTIM_OUTPUTSET_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces the output to its active state */ +#define HRTIM_OUTPUTSET_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces the output to its active state */ +#define HRTIM_OUTPUTSET_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces the output to its active state */ +#define HRTIM_OUTPUTSET_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces the output to its active state */ +#define HRTIM_OUTPUTSET_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces the output to its active state */ /** * @} */ @@ -1054,90 +1002,38 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @brief Constants defining the events that can be selected to configure the * set crossbar of a timer output */ -#define HRTIM_OUTPUTRESET_NONE 0x00000000U /*!< Reset the output reset crossbar */ -#define HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMPER (HRTIM_RST1R_PER) /*!< Timer period event forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMCMP1 (HRTIM_RST1R_CMP1) /*!< Timer compare 1 event forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMCMP2 (HRTIM_RST1R_CMP2) /*!< Timer compare 2 event forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMCMP3 (HRTIM_RST1R_CMP3) /*!< Timer compare 3 event forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMCMP4 (HRTIM_RST1R_CMP4) /*!< Timer compare 4 event forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_MASTERPER (HRTIM_RST1R_MSTPER) /*!< The master timer period event forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its inactive state */ -/* Timer Events mapping for Timer A */ -#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */ -/* Timer Events mapping for Timer B */ -#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */ -/* Timer Events mapping for Timer C */ -#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */ -/* Timer Events mapping for Timer D */ -#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */ -/* Timer Events mapping for Timer E */ -#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */ -/* Timer Events mapping for Timer F */ -#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */ - -#define HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1) /*!< External event 1 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2) /*!< External event 2 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3) /*!< External event 3 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_EEV_4 (HRTIM_RST1R_EXTVNT4) /*!< External event 4 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_EEV_5 (HRTIM_RST1R_EXTVNT5) /*!< External event 5 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_EEV_6 (HRTIM_RST1R_EXTVNT6) /*!< External event 6 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_EEV_7 (HRTIM_RST1R_EXTVNT7) /*!< External event 7 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_EEV_8 (HRTIM_RST1R_EXTVNT8) /*!< External event 8 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_EEV_9 (HRTIM_RST1R_EXTVNT9) /*!< External event 9 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_EEV_10 (HRTIM_RST1R_EXTVNT10) /*!< External event 10 forces the output to its inactive state */ -#define HRTIM_OUTPUTRESET_UPDATE (HRTIM_RST1R_UPDATE) /*!< Timer register update event forces the output to its inactive state */ +#define HRTIM_OUTPUTRESET_NONE 0x00000000U /*!< Reset the output reset crossbar */ +#define HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */ +#define HRTIM_OUTPUTRESET_TIMPER (HRTIM_RST1R_PER) /*!< Timer period event forces the output to its inactive state */ +#define HRTIM_OUTPUTRESET_TIMCMP1 (HRTIM_RST1R_CMP1) /*!< Timer compare 1 event forces the output to its inactive state */ +#define HRTIM_OUTPUTRESET_TIMCMP2 (HRTIM_RST1R_CMP2) /*!< Timer compare 2 event forces the output to its inactive state */ +#define HRTIM_OUTPUTRESET_TIMCMP3 (HRTIM_RST1R_CMP3) /*!< Timer compare 3 event forces the output to its inactive state */ +#define HRTIM_OUTPUTRESET_TIMCMP4 (HRTIM_RST1R_CMP4) /*!< Timer compare 4 event forces the output to its inactive state */ +#define HRTIM_OUTPUTRESET_MASTERPER (HRTIM_RST1R_MSTPER) /*!< The master timer period event forces the output to its inactive state */ +#define HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its inactive state */ +#define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its inactive state */ +#define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its inactive state */ +#define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its inactive state */ +#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */ +#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */ +#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */ +#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */ +#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */ +#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */ +#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */ +#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */ +#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */ +#define HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1) /*!< External event 1 forces the output to its inactive state */ +#define HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2) /*!< External event 2 forces the output to its inactive state */ +#define HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3) /*!< External event 3 forces the output to its inactive state */ +#define HRTIM_OUTPUTRESET_EEV_4 (HRTIM_RST1R_EXTVNT4) /*!< External event 4 forces the output to its inactive state */ +#define HRTIM_OUTPUTRESET_EEV_5 (HRTIM_RST1R_EXTVNT5) /*!< External event 5 forces the output to its inactive state */ +#define HRTIM_OUTPUTRESET_EEV_6 (HRTIM_RST1R_EXTVNT6) /*!< External event 6 forces the output to its inactive state */ +#define HRTIM_OUTPUTRESET_EEV_7 (HRTIM_RST1R_EXTVNT7) /*!< External event 7 forces the output to its inactive state */ +#define HRTIM_OUTPUTRESET_EEV_8 (HRTIM_RST1R_EXTVNT8) /*!< External event 8 forces the output to its inactive state */ +#define HRTIM_OUTPUTRESET_EEV_9 (HRTIM_RST1R_EXTVNT9) /*!< External event 9 forces the output to its inactive state */ +#define HRTIM_OUTPUTRESET_EEV_10 (HRTIM_RST1R_EXTVNT10) /*!< External event 10 forces the output to its inactive state */ +#define HRTIM_OUTPUTRESET_UPDATE (HRTIM_RST1R_UPDATE) /*!< Timer register update event forces the output to its inactive state */ /** * @} */ @@ -2115,7 +2011,7 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< */ /* Private macros --------------------------------------------------------*/ -/** @addtogroup HRTIM_Private_Macros HRTIM Private Macros +/** @addtogroup HRTIM_Private_Macros * @{ */ #define IS_HRTIM_TIMERINDEX(TIMERINDEX)\ diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_hsem.c b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_hsem.c index 0f6add2aca5..bba63f6aea8 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_hsem.c +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_hsem.c @@ -233,7 +233,11 @@ void HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID) assert_param(IS_HSEM_PROCESSID(ProcessID)); /* Clear the semaphore by writing to the R register : the MasterID , the processID and take bit = 0 */ +#if USE_MULTI_CORE_SHARED_CODE != 0U + HSEM->R[SemID] = (ProcessID | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID)); +#else HSEM->R[SemID] = (ProcessID | HSEM_CR_COREID_CURRENT); +#endif } diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_irda.c b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_irda.c index e6aa697519f..eec986d4629 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_irda.c +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_irda.c @@ -206,7 +206,7 @@ #define IRDA_TEACK_REACK_TIMEOUT 1000U /*!< IRDA TX or RX enable acknowledge time-out value */ #define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE \ - | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */ + | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */ #define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */ @@ -225,7 +225,8 @@ * @param __PRESCALER__ IRDA clock prescaler value. * @retval Division result */ -#define IRDA_DIV_SAMPLING16(__PCLK__, __BAUD__, __PRESCALER__) ((((__PCLK__)/IRDAPrescTable[(__PRESCALER__)]) + ((__BAUD__)/2U)) / (__BAUD__)) +#define IRDA_DIV_SAMPLING16(__PCLK__, __BAUD__, __PRESCALER__) ((((__PCLK__)/IRDAPrescTable[(__PRESCALER__)])\ + + ((__BAUD__)/2U)) / (__BAUD__)) /** * @} */ @@ -240,7 +241,8 @@ void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda); #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda); static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda); -static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); +static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda); static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda); static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma); @@ -476,7 +478,8 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, + pIRDA_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -715,6 +718,7 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD While receiving data, transmission should be avoided as the data to be transmitted could be corrupted. + [..] (#) There are two modes of transfer: (++) Blocking mode: the communication is performed in polling mode. The HAL status of all data processing is returned by the same function @@ -752,28 +756,28 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD (++) HAL_IRDA_ErrorCallback() (#) Non-Blocking mode transfers could be aborted using Abort API's : - (+) HAL_IRDA_Abort() - (+) HAL_IRDA_AbortTransmit() - (+) HAL_IRDA_AbortReceive() - (+) HAL_IRDA_Abort_IT() - (+) HAL_IRDA_AbortTransmit_IT() - (+) HAL_IRDA_AbortReceive_IT() + (++) HAL_IRDA_Abort() + (++) HAL_IRDA_AbortTransmit() + (++) HAL_IRDA_AbortReceive() + (++) HAL_IRDA_Abort_IT() + (++) HAL_IRDA_AbortTransmit_IT() + (++) HAL_IRDA_AbortReceive_IT() (#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided: - (+) HAL_IRDA_AbortCpltCallback() - (+) HAL_IRDA_AbortTransmitCpltCallback() - (+) HAL_IRDA_AbortReceiveCpltCallback() + (++) HAL_IRDA_AbortCpltCallback() + (++) HAL_IRDA_AbortTransmitCpltCallback() + (++) HAL_IRDA_AbortReceiveCpltCallback() (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : - (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, - and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side. - If user wants to abort it, Abort services should be called by user. - (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. - This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed. + (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, + and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side. + If user wants to abort it, Abort services should be called by user. + (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed. @endverbatim * @{ @@ -781,10 +785,13 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD /** * @brief Send an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must reflect the number + * of u16 available through pData. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be sent. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. * @param Timeout Specify timeout value. * @retval HAL status */ @@ -867,10 +874,13 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u /** * @brief Receive an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must reflect the number + * of u16 available through pData. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be received. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. * @param Timeout Specify timeout value. * @retval HAL status */ @@ -955,10 +965,13 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui /** * @brief Send an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must reflect the number + * of u16 available through pData. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be sent. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) @@ -997,10 +1010,13 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData /** * @brief Receive an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must reflect the number + * of u16 available through pData. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be received. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) @@ -1046,10 +1062,13 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, /** * @brief Send an amount of data in DMA mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must reflect the number + * of u16 available through pData. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. - * @param pData pointer to data buffer. - * @param Size amount of data to be sent. + * @param pData pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) @@ -1121,12 +1140,15 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat /** * @brief Receive an amount of data in DMA mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must reflect the number + * of u16 available through pData. * @note When the IRDA parity is enabled (PCE = 1), the received data contains * the parity bit (MSB position). * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be received. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) @@ -1354,7 +1376,7 @@ HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda) * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda) { /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ @@ -1440,7 +1462,7 @@ HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda) * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda) { /* Disable TXEIE and TCIE interrupts */ @@ -1492,7 +1514,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda) * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ @@ -1550,7 +1572,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda) { uint32_t abortcplt = 1U; @@ -1682,7 +1704,7 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda) { /* Disable TXEIE and TCIE interrupts */ @@ -1760,7 +1782,7 @@ HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ @@ -2151,7 +2173,8 @@ __weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda) HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda) { /* Return IRDA handle state */ - uint32_t temp1, temp2; + uint32_t temp1; + uint32_t temp2; temp1 = (uint32_t)hirda->gState; temp2 = (uint32_t)hirda->RxState; @@ -2216,6 +2239,7 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) const uint16_t IRDAPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; PLL2_ClocksTypeDef pll2_clocks; PLL3_ClocksTypeDef pll3_clocks; + uint32_t pclk; /* Check the communication parameters */ assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate)); @@ -2244,7 +2268,7 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) MODIFY_REG(hirda->Instance->PRESC, USART_PRESC_PRESCALER, hirda->Init.ClockPrescaler); /*-------------------------- USART GTPR Configuration ----------------------*/ - MODIFY_REG(hirda->Instance->GTPR, (uint16_t)USART_GTPR_PSC, hirda->Init.Prescaler); + MODIFY_REG(hirda->Instance->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)hirda->Init.Prescaler); /*-------------------------- USART BRR Configuration -----------------------*/ IRDA_GETCLOCKSOURCE(hirda, clocksource); @@ -2252,10 +2276,12 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) switch (clocksource) { case IRDA_CLOCKSOURCE_D2PCLK1: - tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); + pclk = HAL_RCC_GetPCLK1Freq(); + tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); break; case IRDA_CLOCKSOURCE_D2PCLK2: - tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); + pclk = HAL_RCC_GetPCLK2Freq(); + tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); break; case IRDA_CLOCKSOURCE_PLL2Q: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); @@ -2349,7 +2375,8 @@ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda) * @param Timeout Timeout duration * @retval HAL status */ -static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) +static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) { /* Wait until flag is set */ while ((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status) diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_irda.h b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_irda.h index 996a8004d94..1a82ca01b42 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_irda.h +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_irda.h @@ -305,7 +305,7 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @} */ -/** @defgroup IRDA_ClockPrescaler Clock Prescaler +/** @defgroup IRDA_ClockPrescaler IRDA Clock Prescaler * @{ */ #define IRDA_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */ @@ -459,8 +459,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer */ /** - * @} - */ + * @} + */ /* Exported macros -----------------------------------------------------------*/ /** @defgroup IRDA_Exported_Macros IRDA Exported Macros @@ -490,10 +490,10 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @retval None */ #define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) \ - do{ \ - SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \ - SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \ - } while(0U) + do{ \ + SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \ + } while(0U) /** @brief Clear the specified IRDA pending flag. * @param __HANDLE__ specifies the IRDA Handle. @@ -608,7 +608,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @arg @ref IRDA_IT_PE Parity Error interrupt * @retval The new state of __IT__ (SET or RESET). */ -#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET) +#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ + & (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET) /** @brief Check whether the specified IRDA interrupt source is enabled or not. * @param __HANDLE__ specifies the IRDA Handle. @@ -623,8 +624,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @retval The new state of __IT__ (SET or RESET). */ #define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \ - (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET) + (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET) /** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the IRDA Handle. @@ -662,7 +663,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @param __HANDLE__ specifies the IRDA Handle. * @retval None */ -#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) +#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\ + &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) /** @brief Enable UART/USART associated to IRDA Handle. * @param __HANDLE__ specifies the IRDA Handle. @@ -709,7 +711,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @param __MODE__ IRDA communication mode. * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ -#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) +#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__)\ + & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) /** @brief Ensure that IRDA power mode is valid. * @param __MODE__ IRDA power mode. @@ -723,17 +726,17 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) */ #define IS_IRDA_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV1) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV2) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV4) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV6) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV8) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV10) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV12) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV16) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV32) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV64) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV128) || \ - ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV256)) + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV2) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV4) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV6) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV8) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV10) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV12) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV16) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV32) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV64) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV128) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV256)) /** @brief Ensure that IRDA state is valid. * @param __STATE__ IRDA state mode. @@ -778,8 +781,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \ ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST)) /** - * @} - */ + * @} + */ /* Include IRDA HAL Extended module */ #include "stm32h7xx_hal_irda_ex.h" @@ -801,7 +804,8 @@ void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda); #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) /* Callbacks Register/UnRegister functions ***********************************/ -HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, + pIRDA_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_irda_ex.h b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_irda_ex.h index 30e1e257597..c1a2f2072f1 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_irda_ex.h +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_irda_ex.h @@ -33,6 +33,7 @@ extern "C" { */ /** @defgroup IRDAEx IRDAEx + * @brief IRDA Extended HAL module driver * @{ */ @@ -69,12 +70,13 @@ extern "C" { * @param __CLOCKSOURCE__ output variable. * @retval IRDA clocking source, written in __CLOCKSOURCE__. */ +#if defined(UART9) && defined(USART10) #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ case RCC_USART1CLKSOURCE_D2PCLK2: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK2; \ break; \ @@ -96,12 +98,12 @@ extern "C" { default: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == USART2) \ { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ case RCC_USART2CLKSOURCE_D2PCLK1: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1; \ break; \ @@ -123,12 +125,12 @@ extern "C" { default: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == USART3) \ { \ - switch(__HAL_RCC_GET_USART3_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ case RCC_USART3CLKSOURCE_D2PCLK1: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1; \ break; \ @@ -150,12 +152,12 @@ extern "C" { default: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == UART4) \ { \ - switch(__HAL_RCC_GET_UART4_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_UART4_SOURCE()) \ + { \ case RCC_UART4CLKSOURCE_D2PCLK1: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1; \ break; \ @@ -177,12 +179,12 @@ extern "C" { default: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if ((__HANDLE__)->Instance == UART5) \ { \ - switch(__HAL_RCC_GET_UART5_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_UART5_SOURCE()) \ + { \ case RCC_UART5CLKSOURCE_D2PCLK1: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1; \ break; \ @@ -204,12 +206,12 @@ extern "C" { default: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == USART6) \ { \ - switch(__HAL_RCC_GET_USART6_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_USART6_SOURCE()) \ + { \ case RCC_USART6CLKSOURCE_D2PCLK2: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK2; \ break; \ @@ -231,12 +233,12 @@ extern "C" { default: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == UART7) \ { \ - switch(__HAL_RCC_GET_UART7_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_UART7_SOURCE()) \ + { \ case RCC_UART7CLKSOURCE_D2PCLK1: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1; \ break; \ @@ -258,12 +260,12 @@ extern "C" { default: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if((__HANDLE__)->Instance == UART8) \ { \ - switch(__HAL_RCC_GET_UART8_SOURCE()) \ - { \ + switch(__HAL_RCC_GET_UART8_SOURCE()) \ + { \ case RCC_UART8CLKSOURCE_D2PCLK1: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1; \ break; \ @@ -285,13 +287,292 @@ extern "C" { default: \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ + } \ + else if((__HANDLE__)->Instance == UART9) \ + { \ + switch(__HAL_RCC_GET_UART9_SOURCE()) \ + { \ + case RCC_UART9CLKSOURCE_D2PCLK2: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK2; \ + break; \ + case RCC_UART9CLKSOURCE_PLL2: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_UART9CLKSOURCE_PLL3: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \ + break; \ + case RCC_UART9CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_UART9CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \ + break; \ + case RCC_UART9CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART10) \ + { \ + switch(__HAL_RCC_GET_USART10_SOURCE()) \ + { \ + case RCC_USART10CLKSOURCE_D2PCLK2: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK2; \ + break; \ + case RCC_USART10CLKSOURCE_PLL2: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_USART10CLKSOURCE_PLL3: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \ + break; \ + case RCC_USART10CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART10CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART10CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#else +#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_D2PCLK2: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_PLL2: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_USART1CLKSOURCE_PLL3: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_D2PCLK1: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_PLL2: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_USART2CLKSOURCE_PLL3: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ + case RCC_USART3CLKSOURCE_D2PCLK1: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1; \ + break; \ + case RCC_USART3CLKSOURCE_PLL2: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_USART3CLKSOURCE_PLL3: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \ + break; \ + case RCC_USART3CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART3CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART3CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == UART4) \ + { \ + switch(__HAL_RCC_GET_UART4_SOURCE()) \ + { \ + case RCC_UART4CLKSOURCE_D2PCLK1: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1; \ + break; \ + case RCC_UART4CLKSOURCE_PLL2: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_UART4CLKSOURCE_PLL3: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \ + break; \ + case RCC_UART4CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_UART4CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \ + break; \ + case RCC_UART4CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if ((__HANDLE__)->Instance == UART5) \ + { \ + switch(__HAL_RCC_GET_UART5_SOURCE()) \ + { \ + case RCC_UART5CLKSOURCE_D2PCLK1: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1; \ + break; \ + case RCC_UART5CLKSOURCE_PLL2: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_UART5CLKSOURCE_PLL3: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \ + break; \ + case RCC_UART5CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_UART5CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \ + break; \ + case RCC_UART5CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART6) \ + { \ + switch(__HAL_RCC_GET_USART6_SOURCE()) \ + { \ + case RCC_USART6CLKSOURCE_D2PCLK2: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK2; \ + break; \ + case RCC_USART6CLKSOURCE_PLL2: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_USART6CLKSOURCE_PLL3: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \ + break; \ + case RCC_USART6CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART6CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART6CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == UART7) \ + { \ + switch(__HAL_RCC_GET_UART7_SOURCE()) \ + { \ + case RCC_UART7CLKSOURCE_D2PCLK1: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1; \ + break; \ + case RCC_UART7CLKSOURCE_PLL2: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_UART7CLKSOURCE_PLL3: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \ + break; \ + case RCC_UART7CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_UART7CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \ + break; \ + case RCC_UART7CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == UART8) \ + { \ + switch(__HAL_RCC_GET_UART8_SOURCE()) \ + { \ + case RCC_UART8CLKSOURCE_D2PCLK1: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1; \ + break; \ + case RCC_UART8CLKSOURCE_PLL2: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_UART8CLKSOURCE_PLL3: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \ + break; \ + case RCC_UART8CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_UART8CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \ + break; \ + case RCC_UART8CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ } \ else \ { \ (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ } \ } while(0U) +#endif /* UART9 && USART10 */ /** @brief Compute the mask to apply to retrieve the received data * according to the word length and to the parity bits activation. @@ -300,44 +581,44 @@ extern "C" { */ #define IRDA_MASK_COMPUTATION(__HANDLE__) \ do { \ - if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \ - { \ - if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ - { \ + if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ + { \ (__HANDLE__)->Mask = 0x01FFU ; \ - } \ - else \ - { \ + } \ + else \ + { \ (__HANDLE__)->Mask = 0x00FFU ; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \ - { \ - if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ - { \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ + { \ (__HANDLE__)->Mask = 0x00FFU ; \ - } \ - else \ - { \ + } \ + else \ + { \ (__HANDLE__)->Mask = 0x007FU ; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \ - { \ - if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ - { \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \ + { \ + if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ + { \ (__HANDLE__)->Mask = 0x007FU ; \ - } \ - else \ - { \ + } \ + else \ + { \ (__HANDLE__)->Mask = 0x003FU ; \ - } \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x0000U; \ - } \ -} while(0U) + } \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x0000U; \ + } \ + } while(0U) /** @brief Ensure that IRDA frame length is valid. * @param __LENGTH__ IRDA frame length. diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_iwdg.c b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_iwdg.c index 1ff788b0212..e630482d778 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_iwdg.c +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_iwdg.c @@ -36,7 +36,7 @@ (+) Debug mode : When the microcontroller enters debug mode (core halted), the IWDG counter either continues to work normally or stops, depending on DBG_IWDG_STOP configuration bit in DBG module, accessible through - __HAL_DBGMCU_FREEZE_IWDG1() or __HAL_DBGMCU_FREEZE2_IWDG2() and + __HAL_DBGMCU_FREEZE_IWDG1() or __HAL_DBGMCU_FREEZE2_IWDG2() and __HAL_DBGMCU_UnFreeze_IWDG1 or __HAL_DBGMCU_UnFreeze2_IWDG2() macros. [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s @@ -49,19 +49,19 @@ ============================================================================== [..] (#) Use IWDG using HAL_IWDG_Init() function to : - (+) Enable instance by writing Start keyword in IWDG_KEY register. LSI + (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI clock is forced ON and IWDG counter starts counting down. - (+) Enable write access to configuration registers: + (++) Enable write access to configuration registers: IWDG_PR, IWDG_RLR and IWDG_WINR. - (+) Configure the IWDG prescaler and counter reload value. This reload + (++) Configure the IWDG prescaler and counter reload value. This reload value will be loaded in the IWDG counter each time the watchdog is reloaded, then the IWDG will start counting down from this value. - (+) Wait for status flags to be reset. - (+) Depending on window parameter: - (++) If Window Init parameter is same as Window register value, + (++) Wait for status flags to be reset. + (++) Depending on window parameter: + (+++) If Window Init parameter is same as Window register value, nothing more is done but reload counter value in order to exit function with exact time base. - (++) Else modify Window register. This will automatically reload + (+++) Else modify Window register. This will automatically reload watchdog counter. (#) Then the application program must refresh the IWDG counter at regular @@ -125,8 +125,8 @@ */ /** @addtogroup IWDG_Exported_Functions_Group1 - * @brief Initialization and Start functions. - * + * @brief Initialization and Start functions. + * @verbatim =============================================================================== ##### Initialization and Start functions ##### @@ -214,8 +214,8 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) /** @addtogroup IWDG_Exported_Functions_Group2 - * @brief IO operation functions - * + * @brief IO operation functions + * @verbatim =============================================================================== ##### IO operation functions ##### diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_lptim.c b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_lptim.c index 0f17a9ea7e9..454b48469f6 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_lptim.c +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_lptim.c @@ -92,19 +92,19 @@ *** Callback registration *** ============================================= - + [..] The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - + [..] Use Function @ref HAL_LPTIM_RegisterCallback() to register a callback. @ref HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - + [..] Use function @ref HAL_LPTIM_UnRegisterCallback() to reset a callback to the default weak function. @ref HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. - + [..] These functions allow to register/unregister following callbacks: (+) MspInitCallback : LPTIM Base Msp Init Callback. @@ -117,15 +117,18 @@ (+) DirectionUpCallback : Up-counting direction change Callback. (+) DirectionDownCallback : Down-counting direction change Callback. + [..] By default, after the Init and when the state is HAL_LPTIM_STATE_RESET all interrupt callbacks are set to the corresponding weak functions: examples @ref HAL_LPTIM_TriggerCallback(), @ref HAL_LPTIM_CompareMatchCallback(). + [..] Exception done for MspInit and MspDeInit functions that are reset to the legacy weak functionalities in the Init/DeInit only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init/DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + [..] Callbacks can be registered/unregistered in HAL_LPTIM_STATE_READY state only. Exception done MspInit/MspDeInit that can be registered/unregistered in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state, @@ -133,6 +136,7 @@ In that case first register the MspInit/MspDeInit user callbacks using @ref HAL_LPTIM_RegisterCallback() before calling DeInit or Init function. + [..] When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks are set to the corresponding weak functions. @@ -148,7 +152,8 @@ * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause - * ****************************************************************************** + * + ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -176,6 +181,7 @@ #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim); #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ +static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag); /* Exported functions --------------------------------------------------------*/ @@ -350,6 +356,11 @@ HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim) /* Disable the LPTIM Peripheral Clock */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) if (hlptim->MspDeInitCallback == NULL) { @@ -458,12 +469,30 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Peri /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); + /* Load the pulse value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); + /* Wait for the completion of the write operation to the LPTIM_CMP register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); @@ -490,6 +519,11 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim) /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Change the TIM state*/ hlptim->State = HAL_LPTIM_STATE_READY; @@ -519,6 +553,41 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t P /* Reset WAVE bit to set PWM mode */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + + /* Load the period value in the autoreload register */ + __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); + + /* Load the pulse value in the compare register */ + __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); + + /* Wait for the completion of the write operation to the LPTIM_CMP register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Enable Autoreload write complete interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); @@ -541,12 +610,6 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t P /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - - /* Load the pulse value in the compare register */ - __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); - /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); @@ -573,6 +636,11 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Disable Autoreload write complete interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); @@ -624,12 +692,30 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); + /* Load the pulse value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); + /* Wait for the completion of the write operation to the LPTIM_CMP register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); @@ -656,6 +742,11 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim) /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Change the TIM state*/ hlptim->State = HAL_LPTIM_STATE_READY; @@ -685,6 +776,41 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint3 /* Reset WAVE bit to set one pulse mode */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + + /* Load the period value in the autoreload register */ + __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); + + /* Load the pulse value in the compare register */ + __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); + + /* Wait for the completion of the write operation to the LPTIM_CMP register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Enable Autoreload write complete interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); @@ -707,12 +833,6 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint3 /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - - /* Load the pulse value in the compare register */ - __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); - /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); @@ -739,6 +859,11 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Disable Autoreload write complete interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); @@ -790,12 +915,30 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); + /* Load the pulse value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); + /* Wait for the completion of the write operation to the LPTIM_CMP register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); @@ -822,6 +965,11 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim) /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Change the TIM state*/ hlptim->State = HAL_LPTIM_STATE_READY; @@ -851,6 +999,41 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Set WAVE bit to enable the set once mode */ hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE; + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + + /* Load the period value in the autoreload register */ + __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); + + /* Load the pulse value in the compare register */ + __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); + + /* Wait for the completion of the write operation to the LPTIM_CMP register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Enable Autoreload write complete interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); @@ -873,12 +1056,6 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - - /* Load the pulse value in the compare register */ - __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); - /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); @@ -905,6 +1082,11 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Disable Autoreload write complete interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); @@ -970,9 +1152,18 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); @@ -999,6 +1190,11 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim) /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Reset ENC bit to disable the encoder interface */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC; @@ -1046,6 +1242,29 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Set ENC bit to enable the encoder interface */ hlptim->Instance->CFGR |= LPTIM_CFGR_ENC; + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + + /* Load the period value in the autoreload register */ + __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Enable "switch to down direction" interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_DOWN); @@ -1055,9 +1274,6 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); @@ -1084,6 +1300,11 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Reset ENC bit to disable the encoder interface */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC; @@ -1127,12 +1348,30 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); + /* Load the Timeout value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Timeout); + /* Wait for the completion of the write operation to the LPTIM_CMP register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); @@ -1159,6 +1398,11 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim) /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Reset TIMOUT bit to enable the timeout function */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT; @@ -1193,18 +1437,47 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Set TIMOUT bit to enable the timeout function */ hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT; - /* Enable Compare match interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM); - /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); + /* Load the Timeout value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Timeout); + /* Wait for the completion of the write operation to the LPTIM_CMP register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Enable Compare match interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM); + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); @@ -1231,6 +1504,11 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Reset TIMOUT bit to enable the timeout function */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT; @@ -1272,9 +1550,18 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + /* Load the period value in the autoreload register */ __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); @@ -1301,6 +1588,11 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim) /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Change the TIM state*/ hlptim->State = HAL_LPTIM_STATE_READY; @@ -1333,6 +1625,29 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC; } + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + + /* Load the period value in the autoreload register */ + __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); + + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Enable Autoreload write complete interrupt */ __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); @@ -1342,9 +1657,6 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); @@ -1371,12 +1683,16 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); + if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) + { + return HAL_TIMEOUT; + } + /* Disable Autoreload write complete interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); /* Disable Autoreload match interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM); - /* Change the TIM state*/ hlptim->State = HAL_LPTIM_STATE_READY; @@ -1973,16 +2289,40 @@ static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim) } #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ +/** + * @brief LPTimer Wait for flag set + * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains + * the configuration information for LPTIM module. + * @param flag The lptim flag + * @retval HAL status + */ +static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag) +{ + HAL_StatusTypeDef result = HAL_OK; + uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL); + do + { + count--; + if (count == 0UL) + { + result = HAL_TIMEOUT; + } + } + while((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL)); + + return result; +} + /** * @brief Disable LPTIM HW instance. - * @param lptim pointer to a LPTIM_HandleTypeDef structure that contains + * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains * the configuration information for LPTIM module. * @note The following sequence is required to solve LPTIM disable HW limitation. * Please check Errata Sheet ES0335 for more details under "MCU may remain * stuck in LPTIM interrupt when entering Stop mode" section. * @retval None */ -void LPTIM_Disable(LPTIM_HandleTypeDef *lptim) +void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim) { uint32_t tmpclksource = 0; uint32_t tmpIER; @@ -1995,7 +2335,7 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *lptim) /*********** Save LPTIM Config ***********/ /* Save LPTIM source clock */ - switch ((uint32_t)lptim->Instance) + switch ((uint32_t)hlptim->Instance) { case LPTIM1_BASE: tmpclksource = __HAL_RCC_GET_LPTIM1_SOURCE(); @@ -2003,28 +2343,34 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *lptim) case LPTIM2_BASE: tmpclksource = __HAL_RCC_GET_LPTIM2_SOURCE(); break; +#if defined(LPTIM3) case LPTIM3_BASE: tmpclksource = __HAL_RCC_GET_LPTIM3_SOURCE(); break; +#endif /* LPTIM3 */ +#if defined(LPTIM4) case LPTIM4_BASE: tmpclksource = __HAL_RCC_GET_LPTIM4_SOURCE(); break; +#endif /* LPTIM4 */ +#if defined(LPTIM5) case LPTIM5_BASE: tmpclksource = __HAL_RCC_GET_LPTIM5_SOURCE(); break; +#endif /* LPTIM5 */ default: break; } /* Save LPTIM configuration registers */ - tmpIER = lptim->Instance->IER; - tmpCFGR = lptim->Instance->CFGR; - tmpCMP = lptim->Instance->CMP; - tmpARR = lptim->Instance->ARR; - tmpCFGR2 = lptim->Instance->CFGR2; + tmpIER = hlptim->Instance->IER; + tmpCFGR = hlptim->Instance->CFGR; + tmpCMP = hlptim->Instance->CMP; + tmpARR = hlptim->Instance->ARR; + tmpCFGR2 = hlptim->Instance->CFGR2; /*********** Reset LPTIM ***********/ - switch ((uint32_t)lptim->Instance) + switch ((uint32_t)hlptim->Instance) { case LPTIM1_BASE: __HAL_RCC_LPTIM1_FORCE_RESET(); @@ -2034,30 +2380,33 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *lptim) __HAL_RCC_LPTIM2_FORCE_RESET(); __HAL_RCC_LPTIM2_RELEASE_RESET(); break; +#if defined(LPTIM3) case LPTIM3_BASE: __HAL_RCC_LPTIM3_FORCE_RESET(); __HAL_RCC_LPTIM3_RELEASE_RESET(); break; +#endif /* LPTIM3 */ +#if defined(LPTIM4) case LPTIM4_BASE: __HAL_RCC_LPTIM4_FORCE_RESET(); __HAL_RCC_LPTIM4_RELEASE_RESET(); break; +#endif /* LPTIM4 */ +#if defined(LPTIM5) case LPTIM5_BASE: __HAL_RCC_LPTIM5_FORCE_RESET(); __HAL_RCC_LPTIM5_RELEASE_RESET(); break; +#endif /* LPTIM5 */ default: break; } /*********** Restore LPTIM Config ***********/ - uint32_t Ref_Time; - uint32_t Time_Elapsed; - if ((tmpCMP != 0UL) || (tmpARR != 0UL)) { /* Force LPTIM source kernel clock from APB */ - switch ((uint32_t)lptim->Instance) + switch ((uint32_t)hlptim->Instance) { case LPTIM1_BASE: __HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_D2PCLK1); @@ -2065,15 +2414,21 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *lptim) case LPTIM2_BASE: __HAL_RCC_LPTIM2_CONFIG(RCC_LPTIM2CLKSOURCE_D3PCLK1); break; +#if defined(LPTIM3) case LPTIM3_BASE: __HAL_RCC_LPTIM3_CONFIG(RCC_LPTIM3CLKSOURCE_D3PCLK1); break; +#endif /* LPTIM3 */ +#if defined(LPTIM4) case LPTIM4_BASE: __HAL_RCC_LPTIM4_CONFIG(RCC_LPTIM4CLKSOURCE_D3PCLK1); break; +#endif /* LPTIM4 */ +#if defined(LPTIM5) case LPTIM5_BASE: __HAL_RCC_LPTIM5_CONFIG(RCC_LPTIM5CLKSOURCE_D3PCLK1); break; +#endif /* LPTIM5 */ default: break; } @@ -2081,35 +2436,34 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *lptim) if (tmpCMP != 0UL) { /* Restore CMP register (LPTIM should be enabled first) */ - lptim->Instance->CR |= LPTIM_CR_ENABLE; - lptim->Instance->CMP = tmpCMP; - /* Polling on CMP write ok status after above restore operation */ - Ref_Time = HAL_GetTick(); - do - { - Time_Elapsed = HAL_GetTick() - Ref_Time; - } while ((!(__HAL_LPTIM_GET_FLAG(lptim, LPTIM_FLAG_CMPOK))) && (Time_Elapsed <= TIMEOUT)); + hlptim->Instance->CR |= LPTIM_CR_ENABLE; + hlptim->Instance->CMP = tmpCMP; - __HAL_LPTIM_CLEAR_FLAG(lptim, LPTIM_FLAG_CMPOK); + /* Wait for the completion of the write operation to the LPTIM_CMP register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) + { + hlptim->State = HAL_LPTIM_STATE_TIMEOUT; + } + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); } if (tmpARR != 0UL) { /* Restore ARR register (LPTIM should be enabled first) */ - lptim->Instance->CR |= LPTIM_CR_ENABLE; - lptim->Instance->ARR = tmpARR; - /* Polling on ARR write ok status after above restore operation */ - Ref_Time = HAL_GetTick(); - do + hlptim->Instance->CR |= LPTIM_CR_ENABLE; + hlptim->Instance->ARR = tmpARR; + + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) { - Time_Elapsed = HAL_GetTick() - Ref_Time; - } while ((!(__HAL_LPTIM_GET_FLAG(lptim, LPTIM_FLAG_ARROK))) && (Time_Elapsed <= TIMEOUT)); + hlptim->State = HAL_LPTIM_STATE_TIMEOUT; + } - __HAL_LPTIM_CLEAR_FLAG(lptim, LPTIM_FLAG_ARROK); + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); } /* Restore LPTIM source kernel clock */ - switch ((uint32_t)lptim->Instance) + switch ((uint32_t)hlptim->Instance) { case LPTIM1_BASE: __HAL_RCC_LPTIM1_CONFIG(tmpclksource); @@ -2117,25 +2471,31 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *lptim) case LPTIM2_BASE: __HAL_RCC_LPTIM2_CONFIG(tmpclksource); break; +#if defined(LPTIM3) case LPTIM3_BASE: __HAL_RCC_LPTIM3_CONFIG(tmpclksource); break; +#endif /* LPTIM3 */ +#if defined(LPTIM4) case LPTIM4_BASE: __HAL_RCC_LPTIM4_CONFIG(tmpclksource); break; +#endif /* LPTIM4 */ +#if defined(LPTIM5) case LPTIM5_BASE: __HAL_RCC_LPTIM5_CONFIG(tmpclksource); break; +#endif /* LPTIM5 */ default: break; } } /* Restore configuration registers (LPTIM should be disabled first) */ - lptim->Instance->CR &= ~(LPTIM_CR_ENABLE); - lptim->Instance->IER = tmpIER; - lptim->Instance->CFGR = tmpCFGR; - lptim->Instance->CFGR2 = tmpCFGR2; + hlptim->Instance->CR &= ~(LPTIM_CR_ENABLE); + hlptim->Instance->IER = tmpIER; + hlptim->Instance->CFGR = tmpCFGR; + hlptim->Instance->CFGR2 = tmpCFGR2; __enable_irq(); } diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_lptim.h b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_lptim.h index 5779e3d1829..40c33185326 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_lptim.h +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_lptim.h @@ -13,7 +13,8 @@ * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause - * ****************************************************************************** + * + ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -399,6 +400,8 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @note The following sequence is required to solve LPTIM disable HW limitation. * Please check Errata Sheet ES0335 for more details under "MCU may remain * stuck in LPTIM interrupt when entering Stop mode" section. + * @note Please call @ref HAL_LPTIM_GetState() after a call to __HAL_LPTIM_DISABLE to + * check for TIMEOUT. * @retval None */ #define __HAL_LPTIM_DISABLE(__HANDLE__) LPTIM_Disable(__HANDLE__) @@ -435,6 +438,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @param __HANDLE__ LPTIM handle * @param __VALUE__ Autoreload value * @retval None + * @note The ARR register can only be modified when the LPTIM instance is enabled. */ #define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__)) @@ -443,6 +447,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @param __HANDLE__ LPTIM handle * @param __VALUE__ Compare value * @retval None + * @note The CMP register can only be modified when the LPTIM instance is enabled. */ #define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__)) @@ -491,6 +496,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @arg LPTIM_IT_ARRM : Autoreload match Interrupt. * @arg LPTIM_IT_CMPM : Compare match Interrupt. * @retval None. + * @note The LPTIM interrupts can only be enabled when the LPTIM instance is disabled. */ #define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) @@ -507,6 +513,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @arg LPTIM_IT_ARRM : Autoreload match Interrupt. * @arg LPTIM_IT_CMPM : Compare match Interrupt. * @retval None. + * @note The LPTIM interrupts can only be disabled when the LPTIM instance is disabled. */ #define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) @@ -745,7 +752,7 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); /** @defgroup LPTIM_Private_Functions LPTIM Private Functions * @{ */ -void LPTIM_Disable(LPTIM_HandleTypeDef *lptim); +void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim); /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_mmc.c b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_mmc.c index 2fd56367689..36169e857f1 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_mmc.c +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_mmc.c @@ -33,8 +33,9 @@ (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE(); (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init() and according to your pin assignment; - (##) NVIC configuration if you need to use interrupt process when using DMA transfer. - (+++) Configure the SDMMC interrupt priorities using functions HAL_NVIC_SetPriority(); + (##) NVIC configuration if you need to use interrupt process (HAL_MMC_ReadBlocks_IT() + and HAL_MMC_WriteBlocks_IT() APIs). + (+++) Configure the SDMMC interrupt priorities using function HAL_NVIC_SetPriority(); (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ() (+++) SDMMC interrupts are managed using the macros __HAL_MMC_ENABLE_IT() and __HAL_MMC_DISABLE_IT() inside the communication process. @@ -98,6 +99,17 @@ chosen as 512 bytes). You can choose either one block read operation or multiple block read operation by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. + You could also check the DMA transfer process through the MMC Rx interrupt event. + + (+) You can read from MMC card in Interrupt mode by using function HAL_MMC_ReadBlocks_IT(). + This function allows the read of 512 bytes blocks. + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. + You could also check the IT transfer process through the MMC Rx interrupt event. *** MMC Card Write operation *** =============================== @@ -107,12 +119,38 @@ chosen as 512 bytes). You can choose either one block read operation or multiple block read operation by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. (+) You can write to MMC card in DMA mode by using function HAL_MMC_WriteBlocks_DMA(). This function support only 512-bytes block length (the block size should be chosen as 512 byte). You can choose either one block read operation or multiple block read operation by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. + You could also check the DMA transfer process through the MMC Tx interrupt event. + + (+) You can write to MMC card in Interrupt mode by using function HAL_MMC_WriteBlocks_IT(). + This function allows the read of 512 bytes blocks. + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. + You could also check the IT transfer process through the MMC Tx interrupt event. + + *** MMC card information *** + =========================== + [..] + (+) To get MMC card information, you can use the function HAL_MMC_GetCardInfo(). + It returns useful information about the MMC card such as block size, card type, + block number ... + + *** MMC card CSD register *** + ============================ + [..] + (+) The HAL_MMC_GetCardCSD() API allows to get the parameters of the CSD register. + Some of the CSD parameters are useful for card initialization and identification. *** MMC card CID register *** ============================ @@ -240,7 +278,9 @@ static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus); static void MMC_PowerOFF(MMC_HandleTypeDef *hmmc); static void MMC_Write_IT(MMC_HandleTypeDef *hmmc); static void MMC_Read_IT(MMC_HandleTypeDef *hmmc); -static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pBlockNbr, uint32_t Timeout); +static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state); +static uint32_t MMC_DDR_Mode(MMC_HandleTypeDef *hmmc, FunctionalState state); +HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex, uint32_t Timeout); /** @@ -498,7 +538,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui SDMMC_DataInitTypeDef config; uint32_t errorstate; uint32_t tickstart = HAL_GetTick(); - uint32_t count, data; + uint32_t count, data, dataremaining; uint32_t add = BlockAdd; uint8_t *tempbuff = pData; @@ -521,7 +561,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui hmmc->State = HAL_MMC_STATE_BUSY; /* Initialize data control register */ - hmmc->Instance->DCTRL = 0; + hmmc->Instance->DCTRL = 0U; if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) { @@ -574,9 +614,10 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui } /* Poll on SDMMC flags */ + dataremaining = config.DataLength; while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF)) + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U)) { /* Read data from SDMMC Rx FIFO */ for(count = 0U; count < 8U; count++) @@ -591,6 +632,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); tempbuff++; } + dataremaining -= 32U; } if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) @@ -611,7 +653,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); if(errorstate != HAL_MMC_ERROR_NONE) { - /* Clear all the static flags */ + /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); hmmc->ErrorCode |= errorstate; hmmc->State = HAL_MMC_STATE_READY; @@ -680,7 +722,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u SDMMC_DataInitTypeDef config; uint32_t errorstate; uint32_t tickstart = HAL_GetTick(); - uint32_t count, data; + uint32_t count, data, dataremaining; uint32_t add = BlockAdd; uint8_t *tempbuff = pData; @@ -703,7 +745,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u hmmc->State = HAL_MMC_STATE_BUSY; /* Initialize data control register */ - hmmc->Instance->DCTRL = 0; + hmmc->Instance->DCTRL = 0U; if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) { @@ -756,11 +798,12 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u } /* Write block(s) in polling mode */ + dataremaining = config.DataLength; while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE)) + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U)) { - /* Write data to SDMMC Tx FIFO */ + /* Write data to SDMMC Tx FIFO */ for(count = 0U; count < 8U; count++) { data = (uint32_t)(*tempbuff); @@ -773,6 +816,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u tempbuff++; (void)SDMMC_WriteFIFO(hmmc->Instance, &data); } + dataremaining -= 32U; } if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) @@ -789,7 +833,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u /* Send stop transmission command in case of multiblock write */ if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) { - /* Send stop transmission command */ + /* Send stop transmission command */ errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); if(errorstate != HAL_MMC_ERROR_NONE) { @@ -895,16 +939,16 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, add *= 512U; } - /* Set Block Size for Card */ + /* Set Block Size for Card */ errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE); if(errorstate != HAL_MMC_ERROR_NONE) { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= errorstate; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } /* Configure the MMC DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; @@ -1170,7 +1214,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData * @note You could also check the DMA transfer process through the MMC Tx * interrupt event. * @param hmmc: Pointer to MMC handle - * @param pData: pointer to the buffer that will contain the data to transmit + * @param pData: Pointer to the buffer that will contain the data to transmit * @param BlockAdd: Block Address where data will be written * @param NumberOfBlocks: Number of blocks to write * @retval HAL status @@ -1220,6 +1264,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pDat hmmc->State = HAL_MMC_STATE_READY; return HAL_ERROR; } + /* Configure the MMC DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks; @@ -1328,12 +1373,11 @@ HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, end_add *= 512U; } - /* Send CMD35 MMC_ERASE_GRP_START with argument as addr */ errorstate = SDMMC_CmdEraseStartAdd(hmmc->Instance, start_add); if(errorstate != HAL_MMC_ERROR_NONE) { - /* Clear all the static flags */ + /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); hmmc->ErrorCode |= errorstate; hmmc->State = HAL_MMC_STATE_READY; @@ -1344,7 +1388,7 @@ HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, errorstate = SDMMC_CmdEraseEndAdd(hmmc->Instance, end_add); if(errorstate != HAL_MMC_ERROR_NONE) { - /* Clear all the static flags */ + /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); hmmc->ErrorCode |= errorstate; hmmc->State = HAL_MMC_STATE_READY; @@ -1383,11 +1427,16 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) uint32_t context = hmmc->Context; /* Check for SDMMC interrupt flags */ - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DATAEND) != RESET) + if((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & MMC_CONTEXT_IT) != 0U)) + { + MMC_Read_IT(hmmc); + } + + else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) != RESET) { __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_DATAEND); - __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT |\ + __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT |\ SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE |\ SDMMC_IT_RXFIFOHF); @@ -1480,17 +1529,12 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) } } - else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_TXFIFOHE) != RESET) + else if((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & MMC_CONTEXT_IT) != 0U)) { MMC_Write_IT(hmmc); } - else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_RXFIFOHF) != RESET) - { - MMC_Read_IT(hmmc); - } - - else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DCRCFAIL| SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_TXUNDERR) != RESET) + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL| SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | SDMMC_FLAG_TXUNDERR) != RESET) { /* Set Error code */ if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DCRCFAIL) != RESET) @@ -1513,8 +1557,6 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) /* Clear All flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); - __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DCRCFAIL); - /* Disable all interrupts */ __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); @@ -1559,8 +1601,9 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) } } - else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_IDMABTC) != RESET) + else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_IDMABTC) != RESET) { + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_IT_IDMABTC); if(READ_BIT(hmmc->Instance->IDMACTRL, SDMMC_IDMA_IDMABACT) == 0U) { /* Current buffer is buffer0, Transfer complete for buffer1 */ @@ -1601,7 +1644,6 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) #endif } } - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_IT_IDMABTC); } else @@ -1622,7 +1664,7 @@ HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc) /** * @brief Return the MMC error code -* @param hmmc : pointer to a MMC_HandleTypeDef structure that contains +* @param hmmc : Pointer to a MMC_HandleTypeDef structure that contains * the configuration information. * @retval MMC Error Code */ @@ -1657,7 +1699,7 @@ __weak void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc) UNUSED(hmmc); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_MMC_ErrorCallback can be implemented in the user file + the HAL_MMC_RxCpltCallback can be implemented in the user file */ } @@ -1687,7 +1729,7 @@ __weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc) UNUSED(hmmc); /* NOTE : This function should not be modified, when the callback is needed, - the HAL_MMC_ErrorCallback can be implemented in the user file + the HAL_MMC_AbortCallback can be implemented in the user file */ } @@ -1953,7 +1995,7 @@ HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTyp * @brief Returns information the information of the card which are stored on * the CSD register. * @param hmmc: Pointer to MMC handle - * @param pCSD: Pointer to a HAL_MMC_CardInfoTypedef structure that + * @param pCSD: Pointer to a HAL_MMC_CardCSDTypeDef structure that * contains all CSD register parameters * @retval HAL status */ @@ -1987,7 +2029,7 @@ HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTyp pCSD->Reserved2 = 0U; /*!< Reserved */ - if(MMC_ReadExtCSD(hmmc, &block_nbr, 0x0FFFFFFFU) != HAL_OK) + if(MMC_ReadExtCSD(hmmc, &block_nbr, 212, 0x0FFFFFFFU) != HAL_OK) /* Field SEC_COUNT [215:212] */ { return HAL_ERROR; } @@ -2101,10 +2143,10 @@ HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoT */ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode) { - __IO uint32_t count = 0; + __IO uint32_t count = 0U; SDMMC_InitTypeDef Init; uint32_t errorstate; - uint32_t response = 0, busy = 0; + uint32_t response = 0U, busy = 0U; /* Check the parameters */ assert_param(IS_SDMMC_BUS_WIDE(WideMode)); @@ -2114,7 +2156,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32 if(WideMode == SDMMC_BUS_WIDE_8B) { - errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200); + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U); if(errorstate != HAL_MMC_ERROR_NONE) { hmmc->ErrorCode |= errorstate; @@ -2122,7 +2164,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32 } else if(WideMode == SDMMC_BUS_WIDE_4B) { - errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100); + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U); if(errorstate != HAL_MMC_ERROR_NONE) { hmmc->ErrorCode |= errorstate; @@ -2130,7 +2172,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32 } else if(WideMode == SDMMC_BUS_WIDE_1B) { - errorstate = SDMMC_CmdSwitch(hmmc->Instance, SDMMC_BUS_WIDE_1B /*0x03B70000*/); + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70000U); if(errorstate != HAL_MMC_ERROR_NONE) { hmmc->ErrorCode |= errorstate; @@ -2141,7 +2183,8 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32 /* WideMode is not a valid argument*/ hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; } -/* Check for switch error and violation of the trial number of sending CMD 13 */ + + /* Check for switch error and violation of the trial number of sending CMD 13 */ while(busy == 0U) { if(count == SDMMC_MAX_TRIAL) @@ -2153,7 +2196,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32 count++; /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ - errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16)); + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); if(errorstate != HAL_MMC_ERROR_NONE) { hmmc->ErrorCode |= errorstate; @@ -2179,7 +2222,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32 count--; /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ - errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16)); + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); if(errorstate != HAL_MMC_ERROR_NONE) { hmmc->ErrorCode |= errorstate; @@ -2213,6 +2256,162 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32 return HAL_OK; } +/** + * @brief Configure the speed bus mode + * @param hmmc: Pointer to the MMC handle + * @param SpeedMode: Specifies the MMC card speed bus mode + * This parameter can be one of the following values: + * @arg SDMMC_SPEED_MODE_AUTO: Max speed mode supported by the card + * @arg SDMMC_SPEED_MODE_DEFAULT: Default Speed (MMC @ 26MHz) + * @arg SDMMC_SPEED_MODE_HIGH: High Speed (MMC @ 52 MHz) + * @arg SDMMC_SPEED_MODE_DDR: High Speed DDR (MMC DDR @ 52 MHz) + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint32_t SpeedMode) +{ + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + uint32_t device_type; + uint32_t errorstate; + + /* Check the parameters */ + assert_param(IS_SDMMC_SPEED_MODE(SpeedMode)); + /* Change State */ + hmmc->State = HAL_MMC_STATE_BUSY; + + if(MMC_ReadExtCSD(hmmc, &device_type, 196, 0x0FFFFFFFU) != HAL_OK) /* Field DEVICE_TYPE [196] */ + { + return HAL_ERROR; + } + + switch (SpeedMode) + { + case SDMMC_SPEED_MODE_AUTO: + { + if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS) != 0U) && ((device_type & 0x04U) != 0U)) + { + /* High Speed DDR mode allowed */ + errorstate = MMC_HighSpeed(hmmc, ENABLE); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + else + { + errorstate = MMC_DDR_Mode(hmmc, ENABLE); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + } + } + else if ((device_type & 0x02U) != 0U) + { + /* High Speed mode allowed */ + errorstate = MMC_HighSpeed(hmmc, ENABLE); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + } + else + { + /* Nothing to do : keep current speed */ + } + break; + } + case SDMMC_SPEED_MODE_DDR: + { + if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS) != 0U) && ((device_type & 0x04U) != 0U)) + { + /* High Speed DDR mode allowed */ + errorstate = MMC_HighSpeed(hmmc, ENABLE); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + else + { + errorstate = MMC_DDR_Mode(hmmc, ENABLE); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + } + } + else + { + /* High Speed DDR mode not allowed */ + hmmc->ErrorCode |= HAL_MMC_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + break; + } + case SDMMC_SPEED_MODE_HIGH: + { + if ((device_type & 0x02U) != 0U) + { + /* High Speed mode allowed */ + errorstate = MMC_HighSpeed(hmmc, ENABLE); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + } + else + { + /* High Speed mode not allowed */ + hmmc->ErrorCode |= HAL_MMC_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + break; + } + case SDMMC_SPEED_MODE_DEFAULT: + { + if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) != 0U) + { + /* High Speed DDR mode activated */ + errorstate = MMC_DDR_Mode(hmmc, DISABLE); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + } + if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) != 0U) + { + /* High Speed mode activated */ + errorstate = MMC_HighSpeed(hmmc, DISABLE); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + } + break; + } + default: + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + status = HAL_ERROR; + break; + } + + /* Verify that MMC card is ready to use after Speed mode switch*/ + tickstart = HAL_GetTick(); + while ((HAL_MMC_GetCardState(hmmc) != HAL_MMC_CARD_TRANSFER)) + { + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + + /* Change State */ + hmmc->State = HAL_MMC_STATE_READY; + return status; +} + /** * @brief Gets the current mmc card data state. * @param hmmc: pointer to MMC handle @@ -2222,7 +2421,7 @@ HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc) { uint32_t cardstate; uint32_t errorstate; - uint32_t resp1 = 0; + uint32_t resp1 = 0U; errorstate = MMC_SendStatus(hmmc, &resp1); if(errorstate != HAL_MMC_ERROR_NONE) @@ -2250,7 +2449,7 @@ HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc) SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); /* Clear All flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); /* If IDMA Context, disable Internal DMA */ hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; @@ -2290,7 +2489,7 @@ HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc) hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; /* Clear All flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); CardState = HAL_MMC_GetCardState(hmmc); hmmc->State = HAL_MMC_STATE_READY; @@ -2338,8 +2537,8 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) { HAL_MMC_CardCSDTypeDef CSD; uint32_t errorstate; - uint16_t mmc_rca = 1; - MMC_InitTypeDef Init; + uint16_t mmc_rca = 1U; + MMC_InitTypeDef Init; /* Check the power State */ if(SDMMC_GetPowerState(hmmc->Instance) == 0U) @@ -2356,11 +2555,11 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) } else { - /* Get Card identification number data */ - hmmc->CID[0] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); - hmmc->CID[1] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2); - hmmc->CID[2] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP3); - hmmc->CID[3] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP4); + /* Get Card identification number data */ + hmmc->CID[0U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + hmmc->CID[1U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2); + hmmc->CID[2U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP3); + hmmc->CID[3U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP4); } /* Send CMD3 SET_REL_ADDR with argument 0 */ @@ -2378,22 +2577,22 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) errorstate = SDMMC_CmdSendCSD(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U)); if(errorstate != HAL_MMC_ERROR_NONE) { - return errorstate; + return errorstate; + } + else + { + /* Get Card Specific Data */ + hmmc->CSD[0U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + hmmc->CSD[1U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2); + hmmc->CSD[2U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP3); + hmmc->CSD[3U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP4); } - else - { - /* Get Card Specific Data */ - hmmc->CSD[0U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); - hmmc->CSD[1U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2); - hmmc->CSD[2U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP3); - hmmc->CSD[3U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP4); - } /* Get the Card Class */ - hmmc->MmcCard.Class = (SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2) >> 20); + hmmc->MmcCard.Class = (SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2) >> 20U); /* Select the Card */ - errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16)); + errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); if(errorstate != HAL_MMC_ERROR_NONE) { return errorstate; @@ -2406,7 +2605,7 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) } /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ - errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16)); + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); if(errorstate != HAL_MMC_ERROR_NONE) { hmmc->ErrorCode |= errorstate; @@ -2433,8 +2632,8 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) */ static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc) { - __IO uint32_t count = 0; - uint32_t response = 0, validvoltage = 0; + __IO uint32_t count = 0U; + uint32_t response = 0U, validvoltage = 0U; uint32_t errorstate; /* CMD0: GO_IDLE_STATE */ @@ -2489,10 +2688,9 @@ static void MMC_PowerOFF(MMC_HandleTypeDef *hmmc) (void)SDMMC_PowerState_OFF(hmmc->Instance); } - /** * @brief Returns the current card's status. - * @param hmmc: pointer to MMC handle + * @param hmmc: Pointer to MMC handle * @param pCardStatus: pointer to the buffer that will contain the MMC card * status (Card Status register) * @retval error state @@ -2507,7 +2705,7 @@ static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus) } /* Send Status command */ - errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16)); + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U)); if(errorstate != HAL_MMC_ERROR_NONE) { return errorstate; @@ -2522,11 +2720,12 @@ static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus) /** * @brief Reads extended CSD register to get the sectors number of the device * @param hmmc: Pointer to MMC handle - * @param pBlockNbr: Pointer to the read buffer + * @param pFieldData: Pointer to the read buffer + * @param pFieldIndex: Index of the field to be read * @param Timeout: Specify timeout value * @retval HAL status */ -HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pBlockNbr, uint32_t Timeout) +HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex, uint32_t Timeout) { SDMMC_DataInitTypeDef config; uint32_t errorstate; @@ -2535,7 +2734,7 @@ HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pBlockNbr, u uint32_t i = 0; uint32_t tmp_data; - hmmc->ErrorCode = HAL_DMA_ERROR_NONE; + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; /* Initialize data control register */ hmmc->Instance->DCTRL = 0; @@ -2589,9 +2788,11 @@ HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pBlockNbr, u for(count = 0U; count < 8U; count++) { tmp_data = SDMMC_ReadFIFO(hmmc->Instance); - if ((i == 48U) && (count == 5U)) + /* eg : SEC_COUNT : FieldIndex = 212 => i+count = 53 */ + /* DEVICE_TYPE : FieldIndex = 196 => i+count = 49 */ + if ((i + count) == ((uint32_t)FieldIndex/4U)) { - *pBlockNbr = tmp_data; + *pFieldData = tmp_data; } } i += 8U; @@ -2615,7 +2816,7 @@ HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pBlockNbr, u } /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); hmmc->State = HAL_MMC_STATE_READY; @@ -2635,21 +2836,25 @@ static void MMC_Read_IT(MMC_HandleTypeDef *hmmc) tmp = hmmc->pRxBuffPtr; - /* Read data from SDMMC Rx FIFO */ - for(count = 0U; count < 8U; count++) + if (hmmc->RxXferSize >= 32U) { - data = SDMMC_ReadFIFO(hmmc->Instance); - *tmp = (uint8_t)(data & 0xFFU); - tmp++; - *tmp = (uint8_t)((data >> 8U) & 0xFFU); - tmp++; - *tmp = (uint8_t)((data >> 16U) & 0xFFU); - tmp++; - *tmp = (uint8_t)((data >> 24U) & 0xFFU); - tmp++; - } + /* Read data from SDMMC Rx FIFO */ + for(count = 0U; count < 8U; count++) + { + data = SDMMC_ReadFIFO(hmmc->Instance); + *tmp = (uint8_t)(data & 0xFFU); + tmp++; + *tmp = (uint8_t)((data >> 8U) & 0xFFU); + tmp++; + *tmp = (uint8_t)((data >> 16U) & 0xFFU); + tmp++; + *tmp = (uint8_t)((data >> 24U) & 0xFFU); + tmp++; + } - hmmc->pRxBuffPtr = tmp; + hmmc->pRxBuffPtr = tmp; + hmmc->RxXferSize -= 32U; + } } /** @@ -2665,21 +2870,185 @@ static void MMC_Write_IT(MMC_HandleTypeDef *hmmc) tmp = hmmc->pTxBuffPtr; - /* Write data to SDMMC Tx FIFO */ - for(count = 0U; count < 8U; count++) + if (hmmc->TxXferSize >= 32U) { - data = (uint32_t)(*tmp); - tmp++; - data |= ((uint32_t)(*tmp) << 8U); - tmp++; - data |= ((uint32_t)(*tmp) << 16U); - tmp++; - data |= ((uint32_t)(*tmp) << 24U); - tmp++; - (void)SDMMC_WriteFIFO(hmmc->Instance, &data); + /* Write data to SDMMC Tx FIFO */ + for(count = 0U; count < 8U; count++) + { + data = (uint32_t)(*tmp); + tmp++; + data |= ((uint32_t)(*tmp) << 8U); + tmp++; + data |= ((uint32_t)(*tmp) << 16U); + tmp++; + data |= ((uint32_t)(*tmp) << 24U); + tmp++; + (void)SDMMC_WriteFIFO(hmmc->Instance, &data); + } + + hmmc->pTxBuffPtr = tmp; + hmmc->TxXferSize -= 32U; } +} - hmmc->pTxBuffPtr = tmp; +/** + * @brief Switches the MMC card to high speed mode. + * @param hmmc: MMC handle + * @param state: State of high speed mode + * @retval MMC Card error state + */ +static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state) +{ + uint32_t errorstate = HAL_MMC_ERROR_NONE; + uint32_t response, count; + + if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) != 0U) && (state == DISABLE)) + { + /* Index : 185 - Value : 0 */ + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B90000U); + } + + if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) == 0U) && (state != DISABLE)) + { + /* Index : 185 - Value : 1 */ + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B90100U); + } + + if(errorstate == HAL_MMC_ERROR_NONE) + { + /* Check for switch error */ + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if(errorstate == HAL_MMC_ERROR_NONE) + { + /* Get command response */ + response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + if ((response & 0x80U) != 0U) + { + errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE; + } + else + { + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + count = SDMMC_MAX_TRIAL; + while(((response & 0x100U) == 0U) && (count != 0U)) + { + count--; + + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + break; + } + + /* Get command response */ + response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + } + + /* Configure high speed */ + if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE)) + { + if (state == DISABLE) + { + CLEAR_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED); + } + else + { + SET_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED); + } + } + } + } + } + + return errorstate; +} + +/** + * @brief Switches the MMC card to Double Data Rate (DDR) mode. + * @param hmmc: MMC handle + * @param state: State of DDR mode + * @retval MMC Card error state + */ +static uint32_t MMC_DDR_Mode(MMC_HandleTypeDef *hmmc, FunctionalState state) +{ + uint32_t errorstate = HAL_MMC_ERROR_NONE; + uint32_t response, count; + + if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) != 0U) && (state == DISABLE)) + { + if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS_0) != 0U) + { + /* Index : 183 - Value : 5 */ + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70500U); + } + else + { + /* Index : 183 - Value : 6 */ + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70600U); + } + } + + if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U) && (state != DISABLE)) + { + if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS_0) != 0U) + { + /* Index : 183 - Value : 1 */ + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U); + } + else + { + /* Index : 183 - Value : 2 */ + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U); + } + } + + if(errorstate == HAL_MMC_ERROR_NONE) + { + /* Check for switch error */ + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if(errorstate == HAL_MMC_ERROR_NONE) + { + /* Get command response */ + response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + if ((response & 0x80U) != 0U) + { + errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE; + } + else + { + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + count = SDMMC_MAX_TRIAL; + while(((response & 0x100U) == 0U) && (count != 0U)) + { + count--; + + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + break; + } + + /* Get command response */ + response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + } + + /* Configure DDR mode */ + if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE)) + { + if (state == DISABLE) + { + CLEAR_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_DDR); + } + else + { + SET_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_DDR); + } + } + } + } + } + + return errorstate; } /** @@ -2742,7 +3111,6 @@ __weak void HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback(MMC_HandleTypeDef *hmmc */ } - /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_mmc.h b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_mmc.h index 4cb01ad1b99..e5c42303add 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_mmc.h +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_mmc.h @@ -92,7 +92,7 @@ typedef struct uint32_t Class; /*!< Specifies the class of the card class */ - uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */ + uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */ uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */ @@ -115,29 +115,29 @@ typedef struct { MMC_TypeDef *Instance; /*!< MMC registers base address */ - MMC_InitTypeDef Init; /*!< MMC required parameters */ + MMC_InitTypeDef Init; /*!< MMC required parameters */ - HAL_LockTypeDef Lock; /*!< MMC locking object */ + HAL_LockTypeDef Lock; /*!< MMC locking object */ - uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */ + uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */ - uint32_t TxXferSize; /*!< MMC Tx Transfer size */ + uint32_t TxXferSize; /*!< MMC Tx Transfer size */ - uint8_t *pRxBuffPtr; /*!< Pointer to MMC Rx transfer Buffer */ + uint8_t *pRxBuffPtr; /*!< Pointer to MMC Rx transfer Buffer */ - uint32_t RxXferSize; /*!< MMC Rx Transfer size */ + uint32_t RxXferSize; /*!< MMC Rx Transfer size */ - __IO uint32_t Context; /*!< MMC transfer context */ + __IO uint32_t Context; /*!< MMC transfer context */ - __IO HAL_MMC_StateTypeDef State; /*!< MMC card State */ + __IO HAL_MMC_StateTypeDef State; /*!< MMC card State */ - __IO uint32_t ErrorCode; /*!< MMC Card Error codes */ + __IO uint32_t ErrorCode; /*!< MMC Card Error codes */ - HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */ + HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */ - uint32_t CSD[4]; /*!< MMC card specific data table */ + uint32_t CSD[4U]; /*!< MMC card specific data table */ - uint32_t CID[4]; /*!< MMC card identification number table */ + uint32_t CID[4U]; /*!< MMC card identification number table */ uint32_t Ext_CSD[128]; @@ -283,12 +283,12 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); #define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ #define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */ #define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the - number of transferred bytes does not match the block length */ + number of transferred bytes does not match the block length */ #define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */ #define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */ #define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */ #define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock - command or if there was an attempt to access a locked card */ + command or if there was an attempt to access a locked card */ #define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */ #define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */ #define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */ @@ -300,7 +300,7 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); #define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */ #define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */ #define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out - of erase sequence command was received */ + of erase sequence command was received */ #define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */ #define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */ #define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */ @@ -352,7 +352,7 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); * @{ */ #define MMC_LOW_CAPACITY_CARD ((uint32_t)0x00000000U) /*!< MMC Card Capacity <=2Gbytes */ -#define MMC_HIGH_CAPACITY_CARD ((uint32_t)0x00000001U) /*!< MMC Card Capacity >2Gbytes and <2Tbytes */ +#define MMC_HIGH_CAPACITY_CARD ((uint32_t)0x00000001U) /*!< MMC Card Capacity >2Gbytes and <2Tbytes */ /** * @} @@ -462,8 +462,8 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); * @arg SDMMC_FLAG_DHOLD: Data transfer Hold * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 - * @arg SDMMC_FLAG_CPSMACT: Command path state machine active * @arg SDMMC_FLAG_DPSMACT: Data path state machine active + * @arg SDMMC_FLAG_CPSMACT: Command path state machine active * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full @@ -529,22 +529,16 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt - * @arg SDMMC_IT_DPSMACT: Data path state machine active interrupt - * @arg SDMMC_IT_CPSMACT: Command path state machine active interrupt * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDMMC_IT_BUSYD0: Inverted value of SDMMC_D0 line (Busy) * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt - * @arg SDMMC_IT_IDMATE: IDMA transfer error interrupt * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt * @retval The new state of MMC IT (SET or RESET). */ @@ -567,13 +561,16 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt + * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt - * @arg SDMMC_IT_IDMATE: IDMA transfer error interrupt * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt * @retval None */ @@ -639,6 +636,7 @@ HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Ca * @{ */ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode); +HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint32_t SpeedMode); /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_pcd.c b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_pcd.c index 0c20395af59..bc601e8f92d 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_pcd.c +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_pcd.c @@ -1039,7 +1039,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t i, ep_intr, epint, epnum = 0U; + uint32_t i, ep_intr, epint, epnum; uint32_t fifoemptymsk, temp; USB_OTG_EPTypeDef *ep; @@ -1360,6 +1360,10 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /* Handle Incomplete ISO IN Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) { + /* Keep application checking the corresponding Iso IN endpoint + causing the incomplete Interrupt */ + epnum = 0U; + #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum); #else @@ -1372,6 +1376,10 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /* Handle Incomplete ISO OUT Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) { + /* Keep application checking the corresponding Iso OUT endpoint + causing the incomplete Interrupt */ + epnum = 0U; + #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); #else diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_ramecc.c b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_ramecc.c index c06a8a90b17..029affafa1d 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_ramecc.c +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_ramecc.c @@ -134,7 +134,7 @@ HAL_StatusTypeDef HAL_RAMECC_Init(RAMECC_HandleTypeDef *hramecc) hramecc->Instance->CR &= ~RAMECC_CR_ECCELEN; /* Disable all global interrupts */ - ((RAMECC_TypeDef *)((uint32_t)&hramecc->Instance & 0xFFFFFF00U))->IER &= \ + ((RAMECC_TypeDef *)((uint32_t)hramecc->Instance & 0xFFFFFF00U))->IER &= \ ~(RAMECC_IER_GIE | RAMECC_IER_GECCSEIE | RAMECC_IER_GECCDEIE | RAMECC_IER_GECCDEBWIE); /* Disable all interrupts monitor */ @@ -175,7 +175,7 @@ HAL_StatusTypeDef HAL_RAMECC_DeInit(RAMECC_HandleTypeDef *hramecc) hramecc->Instance->CR &= ~RAMECC_CR_ECCELEN; /* Disable all global interrupts */ - ((RAMECC_TypeDef *)((uint32_t)&hramecc->Instance & 0xFFFFFF00U))->IER &= \ + ((RAMECC_TypeDef *)((uint32_t)hramecc->Instance & 0xFFFFFF00U))->IER &= \ ~(RAMECC_IER_GIE | RAMECC_IER_GECCSEIE | RAMECC_IER_GECCDEIE | RAMECC_IER_GECCDEBWIE); /* Disable all interrupts monitor */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_ramecc.h b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_ramecc.h index d9c90960aef..8bf1b3bb749 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_ramecc.h +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_ramecc.h @@ -136,7 +136,7 @@ typedef struct __RAMECC_HandleTypeDef -#define __HAL_RAMECC_DISABLE_GLOBAL_IT(__HANDLE__, __INTERRUPT__) ((((RAMECC_TypeDef *)((uint32_t)&(__HANDLE__)->Instance & 0xFFFFFF00U))->IER) &= ~((__INTERRUPT__) & ~RAMECC_IT_GLOBAL_ID)) +#define __HAL_RAMECC_DISABLE_GLOBAL_IT(__HANDLE__, __INTERRUPT__) ((((RAMECC_TypeDef *)((uint32_t)(__HANDLE__)->Instance & 0xFFFFFF00U))->IER) &= ~((__INTERRUPT__) & ~RAMECC_IT_GLOBAL_ID)) #define __HAL_RAMECC_DISABLE_MONITOR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~((__INTERRUPT__) & ~RAMECC_IT_MONITOR_ID)) /** diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_rcc.c b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_rcc.c index 436595d6e7c..f7e8f34e77e 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_rcc.c @@ -214,7 +214,7 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) SystemCoreClock = HSI_VALUE; /* Adapt Systick interrupt period */ - if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + if(HAL_InitTick(uwTickPrio) != HAL_OK) { return HAL_ERROR; } @@ -1048,7 +1048,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui SystemCoreClock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); /* Configure the source of time base considering new system clocks settings*/ - halstatus = HAL_InitTick (TICK_INT_PRIORITY); + halstatus = HAL_InitTick (uwTickPrio); return halstatus; } diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_rcc_ex.c b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_rcc_ex.c index aecc004ca9e..66525c83ab2 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_rcc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_rcc_ex.c @@ -1908,6 +1908,33 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) break; } + default : + { + frequency = 0; + break; + } + } + } + else if (PeriphClk == RCC_PERIPHCLK_SDMMC) + { + /* Get SDMMC clock source */ + srcclk= __HAL_RCC_GET_SDMMC_SOURCE(); + + switch (srcclk) + { + case RCC_SDMMCCLKSOURCE_PLL: /* PLL1 is the clock source for SDMMC */ + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + break; + } + case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is the clock source for SDMMC */ + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_R_Frequency; + break; + } + default : { frequency = 0; diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_sd.c b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_sd.c index 36daf5c4d95..0a4a7e738e6 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_sd.c +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_sd.c @@ -27,14 +27,15 @@ SDMMC driver functions to interface with SD and uSD cards devices. It is used as follows: - (#)Initialize the SDMMC low level resources by implement the HAL_SD_MspInit() API: + (#)Initialize the SDMMC low level resources by implementing the HAL_SD_MspInit() API: (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE(); (##) SDMMC pins configuration for SD card (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE(); (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init() and according to your pin assignment; - (##) NVIC configuration if you need to use interrupt process when using DMA transfer. - (+++) Configure the SDMMC interrupt priorities using functions HAL_NVIC_SetPriority(); + (##) NVIC configuration if you need to use interrupt process (HAL_SD_ReadBlocks_IT() + and HAL_SD_WriteBlocks_IT() APIs). + (+++) Configure the SDMMC interrupt priorities using function HAL_NVIC_SetPriority(); (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ() (+++) SDMMC interrupts are managed using the macros __HAL_SD_ENABLE_IT() and __HAL_SD_DISABLE_IT() inside the communication process. @@ -49,7 +50,7 @@ ================================================ [..] To initialize the SD Card, use the HAL_SD_Init() function. It Initializes - the SD Card and put it into StandBy State (Ready for data transfer). + SDMMC Peripheral(STM32 side) and the SD Card, and put it into StandBy State (Ready for data transfer). This function provide the following operations: (#) Apply the SD Card initialization process at 400KHz and check the SD Card @@ -62,11 +63,16 @@ In initialization mode and according to the SD Card standard, make sure that the SDMMC_CK frequency doesn't exceed 400KHz. - (#) Get the SD CID and CSD data. All these information are managed by the SDCardInfo - structure. This structure provide also ready computed SD Card capacity - and Block size. + This phase of initialization is done through SDMMC_Init() and + SDMMC_PowerState_ON() SDMMC low level APIs. - -@- These information are stored in SD handle structure in case of future use. + (#) Initialize the SD card. The API used is HAL_SD_InitCard(). + This phase allows the card initialization and identification + and check the SD Card type (Standard Capacity or High Capacity) + The initialization flow is compatible with SD standard. + + This API (HAL_SD_InitCard()) could be used also to reinitialize the card in case + of plug-off plug-in. (#) Configure the SD Card Data transfer frequency. You can change or adapt this frequency by adjusting the "ClockDiv" field. @@ -85,12 +91,26 @@ chosen as 512 bytes). You can choose either one block read operation or multiple block read operation by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_SD_GetCardState() function for SD card state. (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA(). This function support only 512-bytes block length (the block size should be chosen as 512 bytes). You can choose either one block read operation or multiple block read operation by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_SD_GetCardState() function for SD card state. + You could also check the DMA transfer process through the SD Rx interrupt event. + + (+) You can read from SD card in Interrupt mode by using function HAL_SD_ReadBlocks_IT(). + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_SD_GetCardState() function for SD card state. + You could also check the IT transfer process through the SD Rx interrupt event. *** SD Card Write operation *** =============================== @@ -100,19 +120,49 @@ chosen as 512 bytes). You can choose either one block read operation or multiple block read operation by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_SD_GetCardState() function for SD card state. (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA(). This function support only 512-bytes block length (the block size should be - chosen as 512 byte). + chosen as 512 bytes). You can choose either one block read operation or multiple block read operation by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_SD_GetCardState() function for SD card state. + You could also check the DMA transfer process through the SD Tx interrupt event. + + (+) You can write to SD card in Interrupt mode by using function HAL_SD_WriteBlocks_IT(). + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_SD_GetCardState() function for SD card state. + You could also check the IT transfer process through the SD Tx interrupt event. *** SD card status *** ====================== [..] - (+) At any time, you can check the SD Card status and get the SD card state - by using the HAL_SD_GetStatusInfo() function. This function checks first if the - SD card is still connected and then get the internal SD Card transfer state. + (+) The SD Status contains status bits that are related to the SD Memory + Card proprietary features. To get SD card status use the HAL_SD_GetCardStatus(). + + *** SD card information *** + =========================== + [..] + (+) To get SD card information, you can use the function HAL_SD_GetCardInfo(). + It returns useful information about the SD card such as block size, card type, + block number ... + + *** SD card CSD register *** + ============================ + (+) The HAL_SD_GetCardCSD() API allows to get the parameters of the CSD register. + Some of the CSD parameters are useful for card initialization and identification. + + *** SD card CID register *** + ============================ + (+) The HAL_SD_GetCardCID() API allows to get the parameters of the CID register. + Some of the CSD parameters are useful for card initialization and identification. *** SD HAL driver macros list *** ================================== @@ -236,20 +286,20 @@ /** @defgroup SD_Private_Functions SD Private Functions * @{ */ -static uint32_t SD_InitCard(SD_HandleTypeDef *hsd); -static uint32_t SD_PowerON(SD_HandleTypeDef *hsd); -static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus); -static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus); -static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd); +static uint32_t SD_InitCard (SD_HandleTypeDef *hsd); +static uint32_t SD_PowerON (SD_HandleTypeDef *hsd); +static uint32_t SD_SendSDStatus (SD_HandleTypeDef *hsd, uint32_t *pSDstatus); +static uint32_t SD_SendStatus (SD_HandleTypeDef *hsd, uint32_t *pCardStatus); +static uint32_t SD_WideBus_Enable (SD_HandleTypeDef *hsd); static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd); -static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR); -static void SD_PowerOFF(SD_HandleTypeDef *hsd); -static void SD_Write_IT(SD_HandleTypeDef *hsd); -static void SD_Read_IT(SD_HandleTypeDef *hsd); -static uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd); +static uint32_t SD_FindSCR (SD_HandleTypeDef *hsd, uint32_t *pSCR); +static void SD_PowerOFF (SD_HandleTypeDef *hsd); +static void SD_Write_IT (SD_HandleTypeDef *hsd); +static void SD_Read_IT (SD_HandleTypeDef *hsd); +static uint32_t SD_HighSpeed (SD_HandleTypeDef *hsd); #if (USE_SD_TRANSCEIVER != 0U) -static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd); -static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd); +static uint32_t SD_UltraHighSpeed (SD_HandleTypeDef *hsd); +static uint32_t SD_DDR_Mode (SD_HandleTypeDef *hsd); #endif /* USE_SD_TRANSCEIVER */ /** * @} @@ -283,7 +333,7 @@ static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd); */ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) { - HAL_SD_CardStatusTypedef CardStatus; + HAL_SD_CardStatusTypeDef CardStatus; uint32_t speedgrade, unitsize; uint32_t tickstart; @@ -305,6 +355,14 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) { /* Allocate lock resource and initialize it */ hsd->Lock = HAL_UNLOCKED; + +#if (USE_SD_TRANSCEIVER != 0U) + /* Force SDMMC_TRANSCEIVER_PRESENT for Legacy usage */ + if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_UNKNOWN) + { + hsd->Init.TranceiverPresent = SDMMC_TRANSCEIVER_PRESENT; + } +#endif #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) /* Reset Callback pointers in HAL_SD_STATE_RESET only */ hsd->TxCpltCallback = HAL_SD_TxCpltCallback; @@ -316,7 +374,10 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) hsd->Write_DMADblBuf0CpltCallback = HAL_SDEx_Write_DMADoubleBuffer0CpltCallback; hsd->Write_DMADblBuf1CpltCallback = HAL_SDEx_Write_DMADoubleBuffer1CpltCallback; #if (USE_SD_TRANSCEIVER != 0U) - hsd->DriveTransceiver_1_8V_Callback = HAL_SD_DriveTransceiver_1_8V_Callback; + if hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT) + { + hsd->DriveTransceiver_1_8V_Callback = HAL_SD_DriveTransceiver_1_8V_Callback; + } #endif /* USE_SD_TRANSCEIVER */ if(hsd->MspInitCallback == NULL) @@ -405,6 +466,7 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) uint32_t errorstate; HAL_StatusTypeDef status; SD_InitTypeDef Init; + uint32_t sdmmc_clk; /* Default SDMMC peripheral configuration for SD card initialization */ Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING; @@ -414,8 +476,11 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) Init.ClockDiv = SDMMC_INIT_CLK_DIV; #if (USE_SD_TRANSCEIVER != 0U) || defined (USE_SD_DIRPOL) + if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT) + { /* Set Transceiver polarity */ hsd->Instance->POWER |= SDMMC_POWER_DIRPOL; + } #endif /* USE_SD_TRANSCEIVER */ /* Initialize SDMMC peripheral interface with default configuration */ @@ -432,6 +497,19 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) return HAL_ERROR; } + /* wait 74 Cycles: required power up waiting time before starting + the SD initialization sequence */ + sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC)/(2U*SDMMC_INIT_CLK_DIV); + + if(sdmmc_clk != 0U) + { + HAL_Delay(1U+ (74U*1000U/(sdmmc_clk))); + } + else + { + HAL_Delay(2U); + } + /* Identify card operating voltage */ errorstate = SD_PowerON(hsd); if(errorstate != HAL_SD_ERROR_NONE) @@ -473,15 +551,18 @@ HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd) #if (USE_SD_TRANSCEIVER != 0U) /* Desactivate the 1.8V Mode */ -#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) - if(hsd->DriveTransceiver_1_8V_Callback == NULL) + if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT) { - hsd->DriveTransceiver_1_8V_Callback = HAL_SD_DriveTransceiver_1_8V_Callback; - } - hsd->DriveTransceiver_1_8V_Callback(RESET); +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + if(hsd->DriveTransceiver_1_8V_Callback == NULL) + { + hsd->DriveTransceiver_1_8V_Callback = HAL_SD_DriveTransceiver_1_8V_Callback; + } + hsd->DriveTransceiver_1_8V_Callback(RESET); #else - HAL_SD_DriveTransceiver_1_8V_Callback(RESET); + HAL_SD_DriveTransceiver_1_8V_Callback(RESET); #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + } #endif /* USE_SD_TRANSCEIVER */ /* Set SD power state to off */ @@ -573,7 +654,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 SDMMC_DataInitTypeDef config; uint32_t errorstate; uint32_t tickstart = HAL_GetTick(); - uint32_t count, data; + uint32_t count, data, dataremaining; uint32_t add = BlockAdd; uint8_t *tempbuff = pData; @@ -645,13 +726,15 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } /* Poll on SDMMC flags */ + dataremaining = config.DataLength; while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { - if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) + if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U)) { /* Read data from SDMMC Rx FIFO */ for(count = 0U; count < 8U; count++) @@ -666,6 +749,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); tempbuff++; } + dataremaining -= 32U; } if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) @@ -674,6 +758,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT; hsd->State= HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_TIMEOUT; } } @@ -692,6 +777,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } } @@ -704,6 +790,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) @@ -712,6 +799,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) @@ -720,6 +808,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } else @@ -758,7 +847,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint SDMMC_DataInitTypeDef config; uint32_t errorstate; uint32_t tickstart = HAL_GetTick(); - uint32_t count, data; + uint32_t count, data, dataremaining; uint32_t add = BlockAdd; uint8_t *tempbuff = pData; @@ -830,13 +919,15 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } /* Write block(s) in polling mode */ + dataremaining = config.DataLength; while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { - if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE)) + if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U)) { /* Write data to SDMMC Tx FIFO */ for(count = 0U; count < 8U; count++) @@ -851,6 +942,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint tempbuff++; (void)SDMMC_WriteFIFO(hsd->Instance, &data); } + dataremaining -= 32U; } if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) @@ -859,6 +951,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_TIMEOUT; } } @@ -877,6 +970,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } } @@ -889,6 +983,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) @@ -897,6 +992,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR)) @@ -905,6 +1001,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } else @@ -1018,6 +1115,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } @@ -1123,6 +1221,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } @@ -1231,6 +1330,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u __HAL_SD_DISABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } @@ -1339,6 +1439,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, __HAL_SD_DISABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND)); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } @@ -1467,11 +1568,16 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) uint32_t context = hsd->Context; /* Check for SDMMC interrupt flags */ - if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DATAEND) != RESET) + if((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & SD_CONTEXT_IT) != 0U)) + { + SD_Read_IT(hsd); + } + + else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) != RESET) { __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DATAEND); - __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT |\ + __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT |\ SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE |\ SDMMC_IT_RXFIFOHF); @@ -1498,6 +1604,7 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) { #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) @@ -1537,6 +1644,7 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) } hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; if(((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) { #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) @@ -1560,17 +1668,12 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) } } - else if((__HAL_SD_GET_FLAG(hsd, SDMMC_IT_TXFIFOHE) != RESET) && ((context & SD_CONTEXT_IT) != 0U)) + else if((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & SD_CONTEXT_IT) != 0U)) { SD_Write_IT(hsd); } - else if((__HAL_SD_GET_FLAG(hsd, SDMMC_IT_RXFIFOHF) != RESET) && ((context & SD_CONTEXT_IT) != 0U)) - { - SD_Read_IT(hsd); - } - - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_TXUNDERR) != RESET) + else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | SDMMC_FLAG_TXUNDERR) != RESET) { /* Set Error code */ if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL) != RESET) @@ -1608,6 +1711,7 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) { /* Set the SD state to ready to be able to start again the process */ hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) hsd->ErrorCallback(hsd); #else @@ -1637,12 +1741,13 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) } } - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_IDMABTC) != RESET) + else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_IDMABTC) != RESET) { + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_IDMABTC); if(READ_BIT(hsd->Instance->IDMACTRL, SDMMC_IDMA_IDMABACT) == 0U) { /* Current buffer is buffer0, Transfer complete for buffer1 */ - if((hsd->Context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) + if((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) { #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) hsd->Write_DMADblBuf1CpltCallback(hsd); @@ -1679,7 +1784,6 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ } } - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_IDMABTC); } else { @@ -2083,11 +2187,11 @@ HAL_StatusTypeDef HAL_SD_UnRegisterTransceiverCallback(SD_HandleTypeDef *hsd) * @brief Returns information the information of the card which are stored on * the CID register. * @param hsd: Pointer to SD handle - * @param pCID: Pointer to a HAL_SD_CIDTypedef structure that + * @param pCID: Pointer to a HAL_SD_CardCIDTypeDef structure that * contains all CID register parameters * @retval HAL status */ -HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypedef *pCID) +HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID) { pCID->ManufacturerID = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24U); @@ -2116,11 +2220,11 @@ HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypedef * @brief Returns information the information of the card which are stored on * the CSD register. * @param hsd: Pointer to SD handle - * @param pCSD: Pointer to a HAL_SD_CardInfoTypedef structure that + * @param pCSD: Pointer to a HAL_SD_CardCSDTypeDef structure that * contains all CSD register parameters * @retval HAL status */ -HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypedef *pCSD) +HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD) { pCSD->CSDStruct = (uint8_t)((hsd->CSD[0] & 0xC0000000U) >> 30U); @@ -2230,11 +2334,11 @@ HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypedef /** * @brief Gets the SD status info. * @param hsd: Pointer to SD handle - * @param pStatus: Pointer to the HAL_SD_CardStatusTypedef structure that + * @param pStatus: Pointer to the HAL_SD_CardStatusTypeDef structure that * will contain the SD card status information * @retval HAL status */ -HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pStatus) +HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus) { uint32_t sd_status[16]; uint32_t errorstate; @@ -2420,105 +2524,160 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t hsd->State = HAL_SD_STATE_BUSY; #if (USE_SD_TRANSCEIVER != 0U) - switch (SpeedMode) + if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT) { - case SDMMC_SPEED_MODE_AUTO: + switch (SpeedMode) { - if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || - (hsd->SdCard.CardType == CARD_SDHC_SDXC)) + case SDMMC_SPEED_MODE_AUTO: { - hsd->Instance->CLKCR |= 0x00100000U; - /* Enable Ultra High Speed */ - if (SD_UltraHighSpeed(hsd) != HAL_SD_ERROR_NONE) + if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || + (hsd->SdCard.CardType == CARD_SDHC_SDXC)) + { + hsd->Instance->CLKCR |= SDMMC_CLKCR_BUSSPEED; + /* Enable Ultra High Speed */ + if (SD_UltraHighSpeed(hsd) != HAL_SD_ERROR_NONE) + { + if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + } + } + else if (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) { + /* Enable High Speed */ if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; status = HAL_ERROR; } } - } - else if (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) - { - /* Enable High Speed */ - if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE) + else { - hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; - status = HAL_ERROR; + /*Nothing to do, Use defaultSpeed */ } + break; } - else - { - /*Nothing to do, Use defaultSpeed */ - } - break; - } case SDMMC_SPEED_MODE_ULTRA: - { - if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || - (hsd->SdCard.CardType == CARD_SDHC_SDXC)) { - hsd->Instance->CLKCR |= 0x00100000U; - /* Enable UltraHigh Speed */ - if (SD_UltraHighSpeed(hsd) != HAL_SD_ERROR_NONE) + if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || + (hsd->SdCard.CardType == CARD_SDHC_SDXC)) + { + /* Enable UltraHigh Speed */ + if (SD_UltraHighSpeed(hsd) != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + hsd->Instance->CLKCR |= SDMMC_CLKCR_BUSSPEED; + } + else { hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; status = HAL_ERROR; } + break; } - else - { - hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; - status = HAL_ERROR; - } - break; - } case SDMMC_SPEED_MODE_DDR: - { - if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || - (hsd->SdCard.CardType == CARD_SDHC_SDXC)) { - hsd->Instance->CLKCR |= 0x00100000U; - /* Enable DDR Mode*/ - if (SD_DDR_Mode(hsd) != HAL_SD_ERROR_NONE) + if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || + (hsd->SdCard.CardType == CARD_SDHC_SDXC)) + { + /* Enable DDR Mode*/ + if (SD_DDR_Mode(hsd) != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + hsd->Instance->CLKCR |= SDMMC_CLKCR_BUSSPEED | SDMMC_CLKCR_DDR; + } + else { hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; status = HAL_ERROR; } + break; } - else + case SDMMC_SPEED_MODE_HIGH: { - hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; - status = HAL_ERROR; + if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || + (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) || + (hsd->SdCard.CardType == CARD_SDHC_SDXC)) + { + /* Enable High Speed */ + if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + } + else + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + break; } + case SDMMC_SPEED_MODE_DEFAULT: + break; + default: + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + status = HAL_ERROR; break; } - case SDMMC_SPEED_MODE_HIGH: + } + else + { + switch (SpeedMode) { - if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || - (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) || - (hsd->SdCard.CardType == CARD_SDHC_SDXC)) + case SDMMC_SPEED_MODE_AUTO: { - /* Enable High Speed */ - if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE) + if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || + (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) || + (hsd->SdCard.CardType == CARD_SDHC_SDXC)) { - hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; - status = HAL_ERROR; + /* Enable High Speed */ + if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } } + else + { + /*Nothing to do, Use defaultSpeed */ + } + break; } - else + case SDMMC_SPEED_MODE_HIGH: { - hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; - status = HAL_ERROR; + if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || + (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) || + (hsd->SdCard.CardType == CARD_SDHC_SDXC)) + { + /* Enable High Speed */ + if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + } + else + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + status = HAL_ERROR; + } + break; } - break; - } case SDMMC_SPEED_MODE_DEFAULT: break; + case SDMMC_SPEED_MODE_ULTRA: /*not valid without transceiver*/ default: hsd->ErrorCode |= HAL_SD_ERROR_PARAM; status = HAL_ERROR; break; + } } #else switch (SpeedMode) @@ -2572,7 +2731,6 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t } #endif /* USE_SD_TRANSCEIVER */ - /* Verify that SD card is ready to use after Speed mode switch*/ tickstart = HAL_GetTick(); while ((HAL_SD_GetCardState(hsd) != HAL_SD_CARD_TRANSFER)) @@ -2595,7 +2753,7 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t * @param hsd: pointer to SD handle * @retval Card state */ -HAL_SD_CardStateTypedef HAL_SD_GetCardState(SD_HandleTypeDef *hsd) +HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd) { uint32_t cardstate; uint32_t errorstate; @@ -2609,7 +2767,7 @@ HAL_SD_CardStateTypedef HAL_SD_GetCardState(SD_HandleTypeDef *hsd) cardstate = ((resp1 >> 9U) & 0x0FU); - return (HAL_SD_CardStateTypedef)cardstate; + return (HAL_SD_CardStateTypeDef)cardstate; } /** @@ -2620,14 +2778,14 @@ HAL_SD_CardStateTypedef HAL_SD_GetCardState(SD_HandleTypeDef *hsd) */ HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) { - HAL_SD_CardStateTypedef CardState; + HAL_SD_CardStateTypeDef CardState; /* DIsable All interrupts */ __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); /* Clear All flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); /* If IDMA Context, disable Internal DMA */ hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; @@ -2657,7 +2815,7 @@ HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) */ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) { - HAL_SD_CardStateTypedef CardState; + HAL_SD_CardStateTypeDef CardState; /* Disable All interrupts */ __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ @@ -2714,9 +2872,9 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) */ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) { - HAL_SD_CardCSDTypedef CSD; + HAL_SD_CardCSDTypeDef CSD; uint32_t errorstate; - uint16_t sd_rca = 1; + uint16_t sd_rca = 1U; /* Check the power State */ if(SDMMC_GetPowerState(hsd->Instance) == 0U) @@ -2736,10 +2894,10 @@ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) else { /* Get Card identification number data */ - hsd->CID[0] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); - hsd->CID[1] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2); - hsd->CID[2] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3); - hsd->CID[3] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4); + hsd->CID[0U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); + hsd->CID[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2); + hsd->CID[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3); + hsd->CID[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4); } } @@ -2767,15 +2925,15 @@ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) else { /* Get Card Specific Data */ - hsd->CSD[0] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); - hsd->CSD[1] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2); - hsd->CSD[2] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3); - hsd->CSD[3] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4); + hsd->CSD[0U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); + hsd->CSD[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2); + hsd->CSD[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3); + hsd->CSD[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4); } } /* Get the Card Class */ - hsd->SdCard.Class = (SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2) >> 20); + hsd->SdCard.Class = (SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2) >> 20U); /* Get CSD parameters */ if (HAL_SD_GetCardCSD(hsd, &CSD) != HAL_OK) @@ -2784,7 +2942,7 @@ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) } /* Select the Card */ - errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16)); + errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16U)); if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; @@ -2803,8 +2961,8 @@ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) */ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) { - __IO uint32_t count = 0; - uint32_t response = 0, validvoltage = 0; + __IO uint32_t count = 0U; + uint32_t response = 0U, validvoltage = 0U; uint32_t errorstate; #if (USE_SD_TRANSCEIVER != 0U) uint32_t tickstart = HAL_GetTick(); @@ -2880,78 +3038,81 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) { hsd->SdCard.CardType = CARD_SDHC_SDXC; #if (USE_SD_TRANSCEIVER != 0U) - if((response & SD_SWITCH_1_8V_CAPACITY) == SD_SWITCH_1_8V_CAPACITY) + if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT) { - hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED; + if((response & SD_SWITCH_1_8V_CAPACITY) == SD_SWITCH_1_8V_CAPACITY) + { + hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED; - /* Start switching procedue */ - hsd->Instance->POWER |= SDMMC_POWER_VSWITCHEN; + /* Start switching procedue */ + hsd->Instance->POWER |= SDMMC_POWER_VSWITCHEN; - /* Send CMD11 to switch 1.8V mode */ - errorstate = SDMMC_CmdVoltageSwitch(hsd->Instance); - if(errorstate != HAL_SD_ERROR_NONE) - { - return errorstate; - } + /* Send CMD11 to switch 1.8V mode */ + errorstate = SDMMC_CmdVoltageSwitch(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } - /* Check to CKSTOP */ - while(( hsd->Instance->STA & SDMMC_FLAG_CKSTOP) != SDMMC_FLAG_CKSTOP) - { - if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + /* Check to CKSTOP */ + while(( hsd->Instance->STA & SDMMC_FLAG_CKSTOP) != SDMMC_FLAG_CKSTOP) { - return HAL_SD_ERROR_TIMEOUT; + if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + return HAL_SD_ERROR_TIMEOUT; + } } - } - /* Clear CKSTOP Flag */ - hsd->Instance->ICR = SDMMC_FLAG_CKSTOP; + /* Clear CKSTOP Flag */ + hsd->Instance->ICR = SDMMC_FLAG_CKSTOP; - /* Check to BusyD0 */ - if(( hsd->Instance->STA & SDMMC_FLAG_BUSYD0) != SDMMC_FLAG_BUSYD0) - { - /* Error when activate Voltage Switch in SDMMC Peripheral */ - return SDMMC_ERROR_UNSUPPORTED_FEATURE; - } - else - { - /* Enable Transceiver Switch PIN */ + /* Check to BusyD0 */ + if(( hsd->Instance->STA & SDMMC_FLAG_BUSYD0) != SDMMC_FLAG_BUSYD0) + { + /* Error when activate Voltage Switch in SDMMC Peripheral */ + return SDMMC_ERROR_UNSUPPORTED_FEATURE; + } + else + { + /* Enable Transceiver Switch PIN */ #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) - hsd->DriveTransceiver_1_8V_Callback(SET); + hsd->DriveTransceiver_1_8V_Callback(SET); #else - HAL_SD_DriveTransceiver_1_8V_Callback(SET); + HAL_SD_DriveTransceiver_1_8V_Callback(SET); #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ - /* Switch ready */ - hsd->Instance->POWER |= SDMMC_POWER_VSWITCH; + /* Switch ready */ + hsd->Instance->POWER |= SDMMC_POWER_VSWITCH; - /* Check VSWEND Flag */ - while(( hsd->Instance->STA & SDMMC_FLAG_VSWEND) != SDMMC_FLAG_VSWEND) - { - if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + /* Check VSWEND Flag */ + while(( hsd->Instance->STA & SDMMC_FLAG_VSWEND) != SDMMC_FLAG_VSWEND) { - return HAL_SD_ERROR_TIMEOUT; + if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + { + return HAL_SD_ERROR_TIMEOUT; + } } - } - /* Clear VSWEND Flag */ - hsd->Instance->ICR = SDMMC_FLAG_VSWEND; + /* Clear VSWEND Flag */ + hsd->Instance->ICR = SDMMC_FLAG_VSWEND; - /* Check BusyD0 status */ - if(( hsd->Instance->STA & SDMMC_FLAG_BUSYD0) == SDMMC_FLAG_BUSYD0) - { - /* Error when enabling 1.8V mode */ - return HAL_SD_ERROR_INVALID_VOLTRANGE; - } - /* Switch to 1.8V OK */ + /* Check BusyD0 status */ + if(( hsd->Instance->STA & SDMMC_FLAG_BUSYD0) == SDMMC_FLAG_BUSYD0) + { + /* Error when enabling 1.8V mode */ + return HAL_SD_ERROR_INVALID_VOLTRANGE; + } + /* Switch to 1.8V OK */ - /* Disable VSWITCH FLAG from SDMMC Peripheral */ - hsd->Instance->POWER = 0x13U; + /* Disable VSWITCH FLAG from SDMMC Peripheral */ + hsd->Instance->POWER = 0x13U; - /* Clean Status flags */ - hsd->Instance->ICR = 0xFFFFFFFFU; - } + /* Clean Status flags */ + hsd->Instance->ICR = 0xFFFFFFFFU; + } - hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED; + hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED; + } } #endif /* USE_SD_TRANSCEIVER */ } @@ -2992,7 +3153,7 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) } /* Set block size for card if it is not equal to current block size for card */ - errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64); + errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U); if(errorstate != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= HAL_SD_ERROR_NONE; @@ -3000,7 +3161,7 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) } /* Send CMD55 */ - errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16)); + errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); if(errorstate != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= HAL_SD_ERROR_NONE; @@ -3009,7 +3170,7 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) /* Configure the SD DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = 64; + config.DataLength = 64U; config.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B; config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; @@ -3093,7 +3254,7 @@ static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus) } /* Send Status command */ - errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16)); + errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; @@ -3112,7 +3273,7 @@ static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus) */ static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd) { - uint32_t scr[2] = {0, 0}; + uint32_t scr[2U] = {0UL, 0UL}; uint32_t errorstate; if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) @@ -3128,17 +3289,17 @@ static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd) } /* If requested card supports wide bus operation */ - if((scr[1] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO) + if((scr[1U] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO) { /* Send CMD55 APP_CMD with argument as card's RCA.*/ - errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16)); + errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; } /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */ - errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2); + errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2U); if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; @@ -3159,7 +3320,7 @@ static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd) */ static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd) { - uint32_t scr[2] = {0, 0}; + uint32_t scr[2U] = {0UL, 0UL}; uint32_t errorstate; if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) @@ -3175,17 +3336,17 @@ static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd) } /* If requested card supports 1 bit mode operation */ - if((scr[1] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO) + if((scr[1U] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO) { /* Send CMD55 APP_CMD with argument as card's RCA */ - errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16)); + errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; } /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */ - errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0); + errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0U); if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; @@ -3211,26 +3372,26 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) SDMMC_DataInitTypeDef config; uint32_t errorstate; uint32_t tickstart = HAL_GetTick(); - uint32_t index = 0; - uint32_t tempscr[2] = {0, 0}; + uint32_t index = 0U; + uint32_t tempscr[2U] = {0UL, 0UL}; uint32_t *scr = pSCR; /* Set Block Size To 8 Bytes */ - errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8); + errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8U); if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; } /* Send CMD55 APP_CMD with argument as card's RCA */ - errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16)); + errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16U)); if(errorstate != HAL_SD_ERROR_NONE) { return errorstate; } config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = 8; + config.DataLength = 8U; config.DataBlockSize = SDMMC_DATABLOCK_SIZE_8B; config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; @@ -3308,21 +3469,25 @@ static void SD_Read_IT(SD_HandleTypeDef *hsd) tmp = hsd->pRxBuffPtr; - /* Read data from SDMMC Rx FIFO */ - for(count = 0U; count < 8U; count++) + if (hsd->RxXferSize >= 32U) { - data = SDMMC_ReadFIFO(hsd->Instance); - *tmp = (uint8_t)(data & 0xFFU); - tmp++; - *tmp = (uint8_t)((data >> 8U) & 0xFFU); - tmp++; - *tmp = (uint8_t)((data >> 16U) & 0xFFU); - tmp++; - *tmp = (uint8_t)((data >> 24U) & 0xFFU); - tmp++; - } + /* Read data from SDMMC Rx FIFO */ + for(count = 0U; count < 8U; count++) + { + data = SDMMC_ReadFIFO(hsd->Instance); + *tmp = (uint8_t)(data & 0xFFU); + tmp++; + *tmp = (uint8_t)((data >> 8U) & 0xFFU); + tmp++; + *tmp = (uint8_t)((data >> 16U) & 0xFFU); + tmp++; + *tmp = (uint8_t)((data >> 24U) & 0xFFU); + tmp++; + } - hsd->pRxBuffPtr = tmp; + hsd->pRxBuffPtr = tmp; + hsd->RxXferSize -= 32U; + } } /** @@ -3338,21 +3503,25 @@ static void SD_Write_IT(SD_HandleTypeDef *hsd) tmp = hsd->pTxBuffPtr; - /* Write data to SDMMC Tx FIFO */ - for(count = 0U; count < 8U; count++) + if (hsd->TxXferSize >= 32U) { - data = (uint32_t)(*tmp); - tmp++; - data |= ((uint32_t)(*tmp) << 8U); - tmp++; - data |= ((uint32_t)(*tmp) << 16U); - tmp++; - data |= ((uint32_t)(*tmp) << 24U); - tmp++; - (void)SDMMC_WriteFIFO(hsd->Instance, &data); - } + /* Write data to SDMMC Tx FIFO */ + for(count = 0U; count < 8U; count++) + { + data = (uint32_t)(*tmp); + tmp++; + data |= ((uint32_t)(*tmp) << 8U); + tmp++; + data |= ((uint32_t)(*tmp) << 16U); + tmp++; + data |= ((uint32_t)(*tmp) << 24U); + tmp++; + (void)SDMMC_WriteFIFO(hsd->Instance, &data); + } - hsd->pTxBuffPtr = tmp; + hsd->pTxBuffPtr = tmp; + hsd->TxXferSize -= 32U; + } } /** @@ -3457,7 +3626,7 @@ uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd) } /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); /* Test if the switch mode HS is ok */ if ((((uint8_t*)SD_hs)[13] & 2U) != 2U) @@ -3718,8 +3887,8 @@ static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd) #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ #if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2) /* Enable DelayBlock Peripheral */ - /* SDMMC_FB_CLK tuned feedback clock selected as receive clock, for SDR104 */ - MODIFY_REG(hsd->Instance->CLKCR, SDMMC_CLKCR_SELCLKRX,SDMMC_CLKCR_SELCLKRX_1); + /* SDMMC_CKin feedback clock selected as receive clock, for DDR50 */ + MODIFY_REG(hsd->Instance->CLKCR, SDMMC_CLKCR_SELCLKRX,SDMMC_CLKCR_SELCLKRX_0); if (DelayBlock_Enable(SD_GET_DLYB_INSTANCE(hsd->Instance)) != HAL_OK) { return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR); diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_sd.h b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_sd.h index 824dc1cef0c..ce290db821f 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_sd.h +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_sd.h @@ -66,7 +66,7 @@ typedef enum /** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure * @{ */ -typedef uint32_t HAL_SD_CardStateTypedef; +typedef uint32_t HAL_SD_CardStateTypeDef; #define HAL_SD_CARD_READY 0x00000001U /*!< Card state is ready */ #define HAL_SD_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state */ @@ -98,7 +98,7 @@ typedef struct uint32_t Class; /*!< Specifies the class of the card class */ - uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */ + uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */ uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */ @@ -123,23 +123,23 @@ typedef struct { SD_TypeDef *Instance; /*!< SD registers base address */ - SD_InitTypeDef Init; /*!< SD required parameters */ + SD_InitTypeDef Init; /*!< SD required parameters */ - HAL_LockTypeDef Lock; /*!< SD locking object */ + HAL_LockTypeDef Lock; /*!< SD locking object */ - uint8_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */ + uint8_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */ - uint32_t TxXferSize; /*!< SD Tx Transfer size */ + uint32_t TxXferSize; /*!< SD Tx Transfer size */ - uint8_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */ + uint8_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */ - uint32_t RxXferSize; /*!< SD Rx Transfer size */ + uint32_t RxXferSize; /*!< SD Rx Transfer size */ - __IO uint32_t Context; /*!< SD transfer context */ + __IO uint32_t Context; /*!< SD transfer context */ - __IO HAL_SD_StateTypeDef State; /*!< SD card State */ + __IO HAL_SD_StateTypeDef State; /*!< SD card State */ - __IO uint32_t ErrorCode; /*!< SD Card Error codes */ + __IO uint32_t ErrorCode; /*!< SD Card Error codes */ HAL_SD_CardInfoTypeDef SdCard; /*!< SD Card information */ @@ -212,7 +212,7 @@ typedef struct __IO uint8_t ECC; /*!< ECC code */ __IO uint8_t CSD_CRC; /*!< CSD CRC */ __IO uint8_t Reserved4; /*!< Always 1 */ -}HAL_SD_CardCSDTypedef; +}HAL_SD_CardCSDTypeDef; /** * @} */ @@ -233,7 +233,7 @@ typedef struct __IO uint8_t CID_CRC; /*!< CID CRC */ __IO uint8_t Reserved2; /*!< Always 1 */ -}HAL_SD_CardCIDTypedef; +}HAL_SD_CardCIDTypeDef; /** * @} */ @@ -256,7 +256,7 @@ typedef struct __IO uint8_t UhsSpeedGrade; /*!< Carries information about the speed grade of UHS card */ __IO uint8_t UhsAllocationUnitSize; /*!< Carries information about the UHS card's allocation unit size */ __IO uint8_t VideoSpeedClass; /*!< Carries information about the Video Speed Class of UHS card */ -}HAL_SD_CardStatusTypedef; +}HAL_SD_CardStatusTypeDef; /** * @} */ @@ -373,7 +373,7 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status); #define CARD_NORMAL_SPEED ((uint32_t)0x00000000U) /*!< Normal Speed Card <12.5Mo/s , Spec Version 1.01 */ #define CARD_HIGH_SPEED ((uint32_t)0x00000100U) /*!< High Speed Card <25Mo/s , Spec version 2.00 */ #define CARD_ULTRA_HIGH_SPEED ((uint32_t)0x00000200U) /*!< UHS-I SD Card <50Mo/s for SDR50, DDR5 Cards - and <104Mo/s for SDR104, Spec version 3.01 */ + and <104Mo/s for SDR104, Spec version 3.01 */ #define CARD_SDSC ((uint32_t)0x00000000U) /*!< SD Standard Capacity <2Go */ #define CARD_SDHC_SDXC ((uint32_t)0x00000001U) /*!< SD High Capacity <32Go, SD Extended Capacity <2To */ @@ -496,8 +496,8 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status); * @arg SDMMC_FLAG_DHOLD: Data transfer Hold * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 - * @arg SDMMC_FLAG_CPSMACT: Command path state machine active * @arg SDMMC_FLAG_DPSMACT: Data path state machine active + * @arg SDMMC_FLAG_CPSMACT: Command path state machine active * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full @@ -563,22 +563,16 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status); * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt - * @arg SDMMC_IT_DPSMACT: Data path state machine active interrupt - * @arg SDMMC_IT_CPSMACT: Command path state machine active interrupt * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDMMC_IT_BUSYD0: Inverted value of SDMMC_D0 line (Busy) * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt - * @arg SDMMC_IT_IDMATE: IDMA transfer error interrupt * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt * @retval The new state of SD IT (SET or RESET). */ @@ -607,7 +601,6 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status); * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt - * @arg SDMMC_IT_IDMATE: IDMA transfer error interrupt * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt * @retval None */ @@ -628,11 +621,11 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status); /** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ -HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd); -HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd); -HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd); -void HAL_SD_MspInit(SD_HandleTypeDef *hsd); -void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd); +HAL_StatusTypeDef HAL_SD_Init (SD_HandleTypeDef *hsd); +HAL_StatusTypeDef HAL_SD_InitCard (SD_HandleTypeDef *hsd); +HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd); +void HAL_SD_MspInit (SD_HandleTypeDef *hsd); +void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd); /** * @} */ @@ -641,27 +634,27 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd); * @{ */ /* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); -HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); -HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd); +HAL_StatusTypeDef HAL_SD_ReadBlocks (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); +HAL_StatusTypeDef HAL_SD_WriteBlocks (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); +HAL_StatusTypeDef HAL_SD_Erase (SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd); /* Non-Blocking mode: IT */ -HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); -HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_SD_ReadBlocks_IT (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_SD_WriteBlocks_IT (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); -void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd); +void HAL_SD_IRQHandler (SD_HandleTypeDef *hsd); /* Callback in non blocking modes (DMA) */ -void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd); -void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd); -void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd); -void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd); +void HAL_SD_TxCpltCallback (SD_HandleTypeDef *hsd); +void HAL_SD_RxCpltCallback (SD_HandleTypeDef *hsd); +void HAL_SD_ErrorCallback (SD_HandleTypeDef *hsd); +void HAL_SD_AbortCallback (SD_HandleTypeDef *hsd); #if (USE_SD_TRANSCEIVER != 0U) /* Callback to switch in 1.8V mode */ -void HAL_SD_DriveTransceiver_1_8V_Callback(FlagStatus status); +void HAL_SD_DriveTransceiver_1_8V_Callback(FlagStatus status); #endif /* USE_SD_TRANSCEIVER */ #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) @@ -691,11 +684,11 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t /** @defgroup SD_Exported_Functions_Group4 SD card related functions * @{ */ -HAL_SD_CardStateTypedef HAL_SD_GetCardState(SD_HandleTypeDef *hsd); -HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypedef *pCID); -HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypedef *pCSD); -HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pStatus); -HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo); +HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd); +HAL_StatusTypeDef HAL_SD_GetCardCID (SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID); +HAL_StatusTypeDef HAL_SD_GetCardCSD (SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD); +HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus); +HAL_StatusTypeDef HAL_SD_GetCardInfo (SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo); /** * @} */ @@ -704,7 +697,7 @@ HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInf * @{ */ HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd); -uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd); +uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd); /** * @} */ @@ -712,7 +705,7 @@ uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd); /** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management * @{ */ -HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd); +HAL_StatusTypeDef HAL_SD_Abort (SD_HandleTypeDef *hsd); HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd); /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_sd_ex.c b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_sd_ex.c index 7401143b1e1..5598e64abfc 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_sd_ex.c +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_sd_ex.c @@ -14,7 +14,6 @@ [..] The SD Extension HAL driver can be used as follows: (+) Configure Buffer0 and Buffer1 start address and Buffer size using HAL_SDEx_ConfigDMAMultiBuffer() function. - (+) Start Read and Write for multibuffer mode using HAL_SDEx_ReadBlocksDMAMultiBuffer() and HAL_SDEx_WriteBlocksDMAMultiBuffer() functions. @endverbatim @@ -130,7 +129,7 @@ HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint3 /* Initialize data control register */ hsd->Instance->DCTRL = 0; /* Clear old Flags*/ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); hsd->ErrorCode = HAL_SD_ERROR_NONE; hsd->State = HAL_SD_STATE_BUSY; diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_sd_ex.h b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_sd_ex.h index 80f0ff97b85..acc0cedb87f 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_sd_ex.h +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_sd_ex.h @@ -18,8 +18,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32H7xx_HAL_SD_EX_H -#define STM32H7xx_HAL_SD_EX_H +#ifndef STM32H7xx_HAL_SDEX_H +#define STM32H7xx_HAL_SDEX_H #ifdef __cplusplus extern "C" { @@ -108,6 +108,6 @@ void HAL_SDEx_Write_DMADoubleBuffer1CpltCallback(SD_HandleTypeDef *hsd); #endif -#endif /* stm32h7xx_HAL_SDEx_H */ +#endif /* stm32h7xx_HAL_SDEX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_smartcard.c b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_smartcard.c index c180fc0365b..91b6bcb48c0 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_smartcard.c +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_smartcard.c @@ -196,8 +196,8 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants - * @{ - */ + * @{ + */ #define SMARTCARD_TEACK_REACK_TIMEOUT 1000U /*!< SMARTCARD TX or RX enable acknowledge time-out value */ #define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ @@ -231,7 +231,8 @@ void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard); static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard); static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard); static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard); -static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); +static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, + FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard); static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard); static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma); @@ -481,7 +482,8 @@ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, + HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -603,7 +605,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmart * @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID * @retval HAL status */ -HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID) +HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, + HAL_SMARTCARD_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; @@ -754,29 +757,30 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma (++) HAL_SMARTCARD_RxCpltCallback() (++) HAL_SMARTCARD_ErrorCallback() + [..] (#) Non-Blocking mode transfers could be aborted using Abort API's : - (+) HAL_SMARTCARD_Abort() - (+) HAL_SMARTCARD_AbortTransmit() - (+) HAL_SMARTCARD_AbortReceive() - (+) HAL_SMARTCARD_Abort_IT() - (+) HAL_SMARTCARD_AbortTransmit_IT() - (+) HAL_SMARTCARD_AbortReceive_IT() + (++) HAL_SMARTCARD_Abort() + (++) HAL_SMARTCARD_AbortTransmit() + (++) HAL_SMARTCARD_AbortReceive() + (++) HAL_SMARTCARD_Abort_IT() + (++) HAL_SMARTCARD_AbortTransmit_IT() + (++) HAL_SMARTCARD_AbortReceive_IT() (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided: - (+) HAL_SMARTCARD_AbortCpltCallback() - (+) HAL_SMARTCARD_AbortTransmitCpltCallback() - (+) HAL_SMARTCARD_AbortReceiveCpltCallback() + (++) HAL_SMARTCARD_AbortCpltCallback() + (++) HAL_SMARTCARD_AbortTransmitCpltCallback() + (++) HAL_SMARTCARD_AbortReceiveCpltCallback() (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : - (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, - and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side. - If user wants to abort it, Abort services should be called by user. - (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. - This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed. + (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, + and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side. + If user wants to abort it, Abort services should be called by user. + (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed. @endverbatim * @{ @@ -795,7 +799,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma * @param Timeout Timeout duration. * @retval HAL status */ -HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, + uint32_t Timeout) { uint32_t tickstart; uint8_t *ptmpdata = pData; @@ -841,7 +846,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui hsmartcard->Instance->TDR = (uint8_t)(*ptmpdata & 0xFFU); ptmpdata++; } - if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart, Timeout) != HAL_OK) + if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart, + Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -882,7 +888,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui * @param Timeout Timeout duration. * @retval HAL status */ -HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, + uint32_t Timeout) { uint32_t tickstart; uint8_t *ptmpdata = pData; @@ -1139,7 +1146,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard hsmartcard->hdmatx->XferAbortCallback = NULL; /* Enable the SMARTCARD transmit DMA channel */ - if (HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR, Size) == HAL_OK) + if (HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR, + Size) == HAL_OK) { /* Clear the TC flag in the ICR register */ CLEAR_BIT(hsmartcard->Instance->ICR, USART_ICR_TCCF); @@ -1215,7 +1223,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, hsmartcard->hdmarx->XferAbortCallback = NULL; /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr, Size) == HAL_OK) + if (HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr, + Size) == HAL_OK) { /* Process Unlocked */ __HAL_UNLOCK(hsmartcard); @@ -1268,7 +1277,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) { /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); + CLEAR_BIT(hsmartcard->Instance->CR1, + (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE | + USART_CR1_EOBIE)); CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); /* Disable the SMARTCARD DMA Tx request if enabled */ @@ -1326,7 +1337,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) hsmartcard->RxXferCount = 0U; /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | + SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -1456,7 +1469,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard hsmartcard->RxXferCount = 0U; /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | + SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; @@ -1484,7 +1499,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) uint32_t abortcplt = 1U; /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); + CLEAR_BIT(hsmartcard->Instance->CR1, + (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE | + USART_CR1_EOBIE)); CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised @@ -1581,7 +1598,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | + SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -1709,7 +1728,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmart * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard) { /* Disable RTOIE, EOBIE, RXNE, PE, RXFT and ERR (Frame error, noise error, overrun error) interrupts */ @@ -1751,7 +1770,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc hsmartcard->RxISR = NULL; /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | + SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; @@ -1775,7 +1796,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc hsmartcard->RxISR = NULL; /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | + SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; @@ -2044,7 +2067,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/ if (__HAL_SMARTCARD_GET_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET) { - if(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET) + if (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET) { SMARTCARD_EndTransmit_IT(hsmartcard); return; @@ -2206,7 +2229,8 @@ __weak void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsma HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard) { /* Return SMARTCARD handle state */ - uint32_t temp1, temp2; + uint32_t temp1; + uint32_t temp2; temp1 = (uint32_t)hsmartcard->gState; temp2 = (uint32_t)hsmartcard->RxState; @@ -2271,6 +2295,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard const uint16_t SMARTCARDPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; PLL2_ClocksTypeDef pll2_clocks; PLL3_ClocksTypeDef pll3_clocks; + uint32_t pclk; /* Check the parameters */ assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance)); @@ -2342,10 +2367,12 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard switch (clocksource) { case SMARTCARD_CLOCKSOURCE_D2PCLK1: - tmpreg = (uint16_t)(((HAL_RCC_GetPCLK1Freq() / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + pclk = HAL_RCC_GetPCLK1Freq(); + tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_D2PCLK2: - tmpreg = (uint16_t)(((HAL_RCC_GetPCLK2Freq() / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + pclk = HAL_RCC_GetPCLK2Freq(); + tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_PLL2Q: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); @@ -2480,7 +2507,8 @@ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmar if ((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) { /* Wait until TEACK flag is set */ - if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK) + if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart, + SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK) { /* Timeout occurred */ return HAL_TIMEOUT; @@ -2490,7 +2518,8 @@ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmar if ((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) { /* Wait until REACK flag is set */ - if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK) + if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, tickstart, + SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK) { /* Timeout occurred */ return HAL_TIMEOUT; @@ -2517,7 +2546,8 @@ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmar * @param Timeout Timeout duration. * @retval HAL status */ -static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) +static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, + FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { /* Wait until flag is set */ while ((__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) ? SET : RESET) == Status) @@ -2641,7 +2671,7 @@ static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma) /* Stop SMARTCARD DMA Tx request if ongoing */ if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) { - if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) { hsmartcard->TxXferCount = 0U; SMARTCARD_EndTxTransfer(hsmartcard); @@ -2720,7 +2750,9 @@ static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma) hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | + SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -2767,7 +2799,9 @@ static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma) hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | + SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -2827,7 +2861,9 @@ static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) hsmartcard->RxXferCount = 0U; /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | + SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_smartcard.h b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_smartcard.h index a3721634027..fae3bd4ae6d 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_smartcard.h +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_smartcard.h @@ -442,7 +442,7 @@ typedef enum * @} */ -/** @defgroup SMARTCARD_ClockPrescaler Clock Prescaler +/** @defgroup SMARTCARD_ClockPrescaler SMARTCARD Clock Prescaler * @{ */ #define SMARTCARD_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */ @@ -560,15 +560,15 @@ typedef enum */ #if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1 #define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \ - (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ + (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ } while(0U) #else #define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \ - (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \ + (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \ } while(0U) #endif /*USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ @@ -576,11 +576,11 @@ typedef enum * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ -#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) \ - do{ \ - SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \ - SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \ - } while(0U) +#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \ + } while(0U) /** @brief Clear the specified SMARTCARD pending flag. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -729,7 +729,8 @@ typedef enum * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET) +#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ + & ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET) /** @brief Check whether the specified SmartCard interrupt source is enabled or not. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -753,8 +754,8 @@ typedef enum * @retval The new state of __INTERRUPT__ (SET or RESET). */ #define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \ - (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK))) != 0U) ? SET : RESET) + (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK))) != 0U) ? SET : RESET) /** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -795,7 +796,8 @@ typedef enum * @param __HANDLE__ specifies the SMARTCARD Handle. * @retval None */ -#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) +#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\ + &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) /** @brief Enable the USART associated to the SMARTCARD Handle. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -823,12 +825,156 @@ typedef enum * @param __CLOCKSOURCE__ output variable. * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__. */ +#if defined(UART9) && defined(USART10) +#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if ((__HANDLE__)->Instance == USART1) \ + { \ + switch (__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_D2PCLK2: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_PLL2: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_USART1CLKSOURCE_PLL3: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if ((__HANDLE__)->Instance == USART2) \ + { \ + switch (__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_D2PCLK1: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_PLL2: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_USART2CLKSOURCE_PLL3: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if ((__HANDLE__)->Instance == USART3) \ + { \ + switch (__HAL_RCC_GET_USART3_SOURCE()) \ + { \ + case RCC_USART3CLKSOURCE_D2PCLK1: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK1; \ + break; \ + case RCC_USART3CLKSOURCE_PLL2: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_USART3CLKSOURCE_PLL3: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q; \ + break; \ + case RCC_USART3CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART3CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART3CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if ((__HANDLE__)->Instance == USART6) \ + { \ + switch (__HAL_RCC_GET_USART6_SOURCE()) \ + { \ + case RCC_USART6CLKSOURCE_D2PCLK2: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK2; \ + break; \ + case RCC_USART6CLKSOURCE_PLL2: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_USART6CLKSOURCE_PLL3: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q; \ + break; \ + case RCC_USART6CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART6CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART6CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if ((__HANDLE__)->Instance == USART10) \ + { \ + switch (__HAL_RCC_GET_USART10_SOURCE()) \ + { \ + case RCC_USART10CLKSOURCE_D2PCLK2: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK2; \ + break; \ + case RCC_USART10CLKSOURCE_PLL2: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q; \ + break; \ + case RCC_USART10CLKSOURCE_PLL3: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q; \ + break; \ + case RCC_USART10CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART10CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART10CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#else #define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if ((__HANDLE__)->Instance == USART1) \ { \ - switch (__HAL_RCC_GET_USART1_SOURCE()) \ - { \ + switch (__HAL_RCC_GET_USART1_SOURCE()) \ + { \ case RCC_USART1CLKSOURCE_D2PCLK2: \ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK2; \ break; \ @@ -850,17 +996,17 @@ typedef enum default: \ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if ((__HANDLE__)->Instance == USART2) \ { \ - switch (__HAL_RCC_GET_USART2_SOURCE()) \ - { \ + switch (__HAL_RCC_GET_USART2_SOURCE()) \ + { \ case RCC_USART2CLKSOURCE_D2PCLK1: \ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK1; \ break; \ case RCC_USART2CLKSOURCE_PLL2: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q; \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q; \ break; \ case RCC_USART2CLKSOURCE_PLL3: \ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q; \ @@ -877,12 +1023,12 @@ typedef enum default: \ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if ((__HANDLE__)->Instance == USART3) \ { \ - switch (__HAL_RCC_GET_USART3_SOURCE()) \ - { \ + switch (__HAL_RCC_GET_USART3_SOURCE()) \ + { \ case RCC_USART3CLKSOURCE_D2PCLK1: \ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK1; \ break; \ @@ -904,12 +1050,12 @@ typedef enum default: \ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else if ((__HANDLE__)->Instance == USART6) \ { \ - switch (__HAL_RCC_GET_USART6_SOURCE()) \ - { \ + switch (__HAL_RCC_GET_USART6_SOURCE()) \ + { \ case RCC_USART6CLKSOURCE_D2PCLK2: \ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK2; \ break; \ @@ -931,13 +1077,14 @@ typedef enum default: \ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ break; \ - } \ + } \ } \ else \ { \ (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ } \ } while(0U) +#endif /* UART9 && USART10 */ /** @brief Check the Baud rate range. * @note The maximum Baud Rate is derived from the maximum clock on H7 (100 MHz) @@ -998,7 +1145,8 @@ typedef enum * @param __CPOL__ SMARTCARD frame polarity. * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid) */ -#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH)) +#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW)\ + || ((__CPOL__) == SMARTCARD_POLARITY_HIGH)) /** @brief Ensure that SMARTCARD frame phase is valid. * @param __CPHA__ SMARTCARD frame phase. @@ -1038,18 +1186,18 @@ typedef enum * @param __CLOCKPRESCALER__ SMARTCARD clock Prescaler value. * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) */ -#define IS_SMARTCARD_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV1) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV2) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV4) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV6) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV8) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV10) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV12) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV16) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV32) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV64) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV128) || \ - ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV256)) +#define IS_SMARTCARD_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV1) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV2) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV4) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV6) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV8) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV10) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV12) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV16) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV32) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV64) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV128) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV256)) /** @brief Ensure that SMARTCARD advanced features initialization is valid. * @param __INIT__ SMARTCARD advanced features initialization. @@ -1144,8 +1292,10 @@ void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard); #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) /* Callbacks Register/UnRegister functions ***********************************/ -HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, + HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, + HAL_SMARTCARD_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ /** @@ -1157,8 +1307,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma * @{ */ -HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, + uint32_t Timeout); HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_smartcard_ex.c b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_smartcard_ex.c index 235f7cae731..ac0e473fc63 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_smartcard_ex.c +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_smartcard_ex.c @@ -55,11 +55,17 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ +/** @defgroup SMARTCARDEx_Private_Constants SMARTCARD Extended Private Constants + * @{ + */ /* UART RX FIFO depth */ #define RX_FIFO_DEPTH 8U /* UART TX FIFO depth */ #define TX_FIFO_DEPTH 8U +/** + * @} + */ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ @@ -188,8 +194,8 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef This subsection provides a set of FIFO mode related callback functions. (#) TX/RX Fifos Callbacks: - (+) HAL_SMARTCARDEx_RxFifoFullCallback() - (+) HAL_SMARTCARDEx_TxFifoEmptyCallback() + (++) HAL_SMARTCARDEx_RxFifoFullCallback() + (++) HAL_SMARTCARDEx_TxFifoEmptyCallback() @endverbatim * @{ @@ -231,15 +237,16 @@ __weak void HAL_SMARTCARDEx_TxFifoEmptyCallback(SMARTCARD_HandleTypeDef *hsmartc * @} */ -/** @defgroup SMARTCARD_Exported_Functions_Group3 Extended Peripheral Peripheral Control functions +/** @defgroup SMARTCARDEx_Exported_Functions_Group3 Extended Peripheral FIFO Control functions * @brief SMARTCARD control functions * @verbatim =============================================================================== - ##### Peripheral Control functions ##### + ##### Peripheral FIFO Control functions ##### =============================================================================== [..] - This subsection provides a set of functions allowing to control the SMARTCARD. + This subsection provides a set of functions allowing to control the SMARTCARD + FIFO feature. (+) HAL_SMARTCARDEx_EnableFifoMode() API enables the FIFO mode (+) HAL_SMARTCARDEx_DisableFifoMode() API disables the FIFO mode (+) HAL_SMARTCARDEx_SetTxFifoThreshold() API sets the TX FIFO threshold @@ -433,7 +440,7 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hs * @} */ -/** @defgroup SMARTCARDEx_Private_Functions SMARTCARD Extended private Functions +/** @defgroup SMARTCARDEx_Private_Functions SMARTCARD Extended Private Functions * @{ */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_smartcard_ex.h b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_smartcard_ex.h index e31982c7acc..d6650a15695 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_smartcard_ex.h +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_smartcard_ex.h @@ -68,7 +68,7 @@ extern "C" { * @} */ -/** @defgroup SMARTCARDEx_FIFO_mode SMARTCARDEx FIFO mode +/** @defgroup SMARTCARDEx_FIFO_mode SMARTCARD FIFO mode * @brief SMARTCARD FIFO mode * @{ */ @@ -78,7 +78,7 @@ extern "C" { * @} */ -/** @defgroup SMARTCARDEx_TXFIFO_threshold_level SMARTCARDEx TXFIFO threshold level +/** @defgroup SMARTCARDEx_TXFIFO_threshold_level SMARTCARD TXFIFO threshold level * @brief SMARTCARD TXFIFO level * @{ */ @@ -92,7 +92,7 @@ extern "C" { * @} */ -/** @defgroup SMARTCARDEx_RXFIFO_threshold_level SMARTCARDEx RXFIFO threshold level +/** @defgroup SMARTCARDEx_RXFIFO_threshold_level SMARTCARD RXFIFO threshold level * @brief SMARTCARD RXFIFO level * @{ */ @@ -207,7 +207,7 @@ extern "C" { do { \ if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION)) \ { \ - (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \ + (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \ } \ else \ { \ @@ -238,29 +238,29 @@ extern "C" { * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) */ #define IS_SMARTCARD_FIFOMODE_STATE(__STATE__) (((__STATE__) == SMARTCARD_FIFOMODE_DISABLE ) || \ - ((__STATE__) == SMARTCARD_FIFOMODE_ENABLE)) + ((__STATE__) == SMARTCARD_FIFOMODE_ENABLE)) /** @brief Ensure that SMARTCARD TXFIFO threshold level is valid. * @param __THRESHOLD__ SMARTCARD TXFIFO threshold level. * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) */ #define IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_8) || \ - ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_4) || \ - ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_2) || \ - ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3_4) || \ - ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7_8) || \ - ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_8_8)) + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_8_8)) /** @brief Ensure that SMARTCARD RXFIFO threshold level is valid. * @param __THRESHOLD__ SMARTCARD RXFIFO threshold level. * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) */ #define IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_8) || \ - ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_4) || \ - ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_2) || \ - ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3_4) || \ - ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7_8) || \ - ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_8_8)) + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_8_8)) /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_tim.c b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_tim.c index 59a09f84661..fee082ace58 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_tim.c +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_tim.c @@ -3747,6 +3747,10 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @note To output a waveform with a minimum delay user can enable the fast + * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx + * output is forced in response to the edge detection on TIx input, + * without taking in account the comparison. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_tim.h b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_tim.h index b4ce7ea7f53..d370d1613d6 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_tim.h +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_tim.h @@ -235,7 +235,12 @@ typedef struct uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ uint32_t MasterSlaveMode; /*!< Master/slave mode selection - This parameter can be a value of @ref TIM_Master_Slave_Mode */ + This parameter can be a value of @ref TIM_Master_Slave_Mode + @note When the Master/slave mode is enabled, the effect of + an event on the trigger input (TRGI) is delayed to allow a + perfect synchronization between the current timer and its + slaves (through TRGO). It is not mandatory in case of timer + synchronization mode. */ } TIM_MasterConfigTypeDef; /** @@ -1508,12 +1513,62 @@ mode. * @retval None */ #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\ - ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE)) + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE)) + +/** + * @brief Enable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @note When fast mode is enabled an active edge on the trigger input acts + * like a compare match on CCx output. Delay to sample the trigger + * input and to activate CCx output is reduced to 3 clock cycles. + * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\ + ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE)) + +/** + * @brief Disable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @note When fast mode is disabled CCx output behaves normally depending + * on counter and CCRx values even when the trigger is ON. The minimum + * delay to activate CCx output when an active edge occurs on the + * trigger input is 5 clock cycles. + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\ + ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE)) /** * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. @@ -1876,10 +1931,10 @@ mode. ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\ - ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC)) + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ @@ -1888,10 +1943,10 @@ mode. ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ - ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ + ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_tim_ex.c b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_tim_ex.c index d3e56980265..950a8da50c7 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_tim_ex.c +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_tim_ex.c @@ -1694,6 +1694,9 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, * @param htim TIM handle * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that * contains the BDTR Register configuration information for the TIM peripheral. + * @note Interrupts can be generated when an active level is detected on the + * break input, the break 2 input or the system break input. Break + * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, @@ -1767,10 +1770,10 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, { uint32_t tmporx; - uint32_t bkin_enable_mask = 0U; - uint32_t bkin_polarity_mask = 0U; - uint32_t bkin_enable_bitpos = 0U; - uint32_t bkin_polarity_bitpos = 0U; + uint32_t bkin_enable_mask; + uint32_t bkin_polarity_mask; + uint32_t bkin_enable_bitpos; + uint32_t bkin_polarity_bitpos; /* Check the parameters */ assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); @@ -1815,11 +1818,19 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, { bkin_enable_mask = TIM1_AF1_BKDF1BK0E; bkin_enable_bitpos = 8U; + bkin_polarity_mask = 0U; + bkin_polarity_bitpos = 0U; break; } default: + { + bkin_enable_mask = 0U; + bkin_polarity_mask = 0U; + bkin_enable_bitpos = 0U; + bkin_polarity_bitpos = 0U; break; + } } switch (BreakInput) @@ -1882,9 +1893,9 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, * @arg TIM_TIM1_ETR_GPIO: TIM1_ETR is connected to GPIO * @arg TIM_TIM1_ETR_COMP1: TIM1_ETR is connected to COMP1 output * @arg TIM_TIM1_ETR_COMP2: TIM1_ETR is connected to COMP2 output - * @arg TIM_TIM1_ETR_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1 - * @arg TIM_TIM1_ETR_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2 - * @arg TIM_TIM1_ETR_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3 + * @arg TIM_TIM1_ETR_ADC2_AWD1: TIM1_ETR is connected to ADC2 AWD1 + * @arg TIM_TIM1_ETR_ADC2_AWD2: TIM1_ETR is connected to ADC2 AWD2 + * @arg TIM_TIM1_ETR_ADC2_AWD3: TIM1_ETR is connected to ADC2 AWD3 * @arg TIM_TIM1_ETR_ADC3_AWD1: TIM1_ETR is connected to ADC3 AWD1 * @arg TIM_TIM1_ETR_ADC3_AWD2: TIM1_ETR is connected to ADC3 AWD2 * @arg TIM_TIM1_ETR_ADC3_AWD3: TIM1_ETR is connected to ADC3 AWD3 @@ -1969,6 +1980,10 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) * @arg TIM_TIM8_TI1_GPIO: TIM8 TI1 is connected to GPIO * @arg TIM_TIM8_TI1_COMP2: TIM8 TI1 is connected to COMP2 output * + * For TIM12, the parameter can have the following values: (*) + * @arg TIM_TIM12_TI1_GPIO: TIM12 TI1 is connected to GPIO + * @arg TIM_TIM12_TI1_SPDIF_FS: TIM12 TI1 is connected to SPDIF FS + * * For TIM15, the parameter is one of the following values: * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO * @arg TIM_TIM15_TI1_TIM2: TIM15 TI1 is connected to TIM2 CH1 @@ -1990,10 +2005,11 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) * * For TIM17, the parameter can have the following values: * @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO - * @arg TIM_TIM17_TI1_SPDIFFS: TIM17 TI1 is connected to SPDIF FS + * @arg TIM_TIM17_TI1_SPDIF_FS: TIM17 TI1 is connected to SPDIF FS (*) * @arg TIM_TIM17_TI1_HSE_1MHZ: TIM17 TI1 is connected to HSE 1MHz * @arg TIM_TIM17_TI1_MCO1: TIM17 TI1 is connected to MCO1 * + * (*) Value not defined in all devices. \n * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel) diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_tim_ex.h b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_tim_ex.h index 1c26695ea11..37697193c1d 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_tim_ex.h +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_tim_ex.h @@ -93,9 +93,9 @@ TIMEx_BreakInputConfigTypeDef; #define TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */ #define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 OUT */ #define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 OUT */ -#define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD1 */ -#define TIM_TIM1_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_2) /* !< TIM1_ETR is connected to ADC1 AWD2 */ -#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC1 AWD3 */ +#define TIM_TIM1_ETR_ADC2_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC2 AWD1 */ +#define TIM_TIM1_ETR_ADC2_AWD2 (TIM1_AF1_ETRSEL_2) /* !< TIM1_ETR is connected to ADC2 AWD2 */ +#define TIM_TIM1_ETR_ADC2_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC2 AWD3 */ #define TIM_TIM1_ETR_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< TIM1_ETR is connected to ADC3 AWD1 */ #define TIM_TIM1_ETR_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC3 AWD2 */ #define TIM_TIM1_ETR_ADC3_AWD3 TIM1_AF1_ETRSEL_3 /* !< TIM1_ETR is connected to ADC3 AWD3 */ @@ -103,9 +103,9 @@ TIMEx_BreakInputConfigTypeDef; #define TIM_TIM8_ETR_GPIO 0x00000000U /* !< TIM8_ETR is connected to GPIO */ #define TIM_TIM8_ETR_COMP1 TIM8_AF1_ETRSEL_0 /* !< TIM8_ETR is connected to COMP1 OUT */ #define TIM_TIM8_ETR_COMP2 TIM8_AF1_ETRSEL_1 /* !< TIM8_ETR is connected to COMP2 OUT */ -#define TIM_TIM8_ETR_ADC1_AWD1 (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC1 AWD1 */ -#define TIM_TIM8_ETR_ADC1_AWD2 (TIM8_AF1_ETRSEL_2) /* !< TIM8_ETR is connected to ADC1 AWD2 */ -#define TIM_TIM8_ETR_ADC1_AWD3 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC1 AWD3 */ +#define TIM_TIM8_ETR_ADC2_AWD1 (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC2 AWD1 */ +#define TIM_TIM8_ETR_ADC2_AWD2 (TIM8_AF1_ETRSEL_2) /* !< TIM8_ETR is connected to ADC2 AWD2 */ +#define TIM_TIM8_ETR_ADC2_AWD3 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC2 AWD3 */ #define TIM_TIM8_ETR_ADC3_AWD1 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1) /* !< TIM8_ETR is connected to ADC3 AWD1 */ #define TIM_TIM8_ETR_ADC3_AWD2 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC3 AWD2 */ #define TIM_TIM8_ETR_ADC3_AWD3 TIM8_AF1_ETRSEL_3 /* !< TIM8_ETR is connected to ADC3 AWD3 */ @@ -190,6 +190,13 @@ TIMEx_BreakInputConfigTypeDef; #define TIM_TIM5_TI1_CAN_TMP TIM_TISEL_TI1SEL_0 /* !< TIM5_TI1 is connected to CAN TMP */ #define TIM_TIM5_TI1_CAN_RTP TIM_TISEL_TI1SEL_1 /* !< TIM5_TI1 is connected to CAN RTP */ +#if defined(TIM12_TI1_GPIO_SUPPORT) +#define TIM_TIM12_TI1_GPIO 0x00000000U /* !< TIM12 TI1 is connected to GPIO */ +#endif /* TIM12_TI1_GPIO_SUPPORT */ +#if defined(TIM12_TI1_SPDIF_FS_SUPPORT) +#define TIM_TIM12_TI1_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM12 TI1 is connected to SPDIF FS */ +#endif /* TIM12_TI1_SPDIF_FS_SUPPORT */ + #define TIM_TIM15_TI1_GPIO 0x00000000U /* !< TIM15_TI1 is connected to GPIO */ #define TIM_TIM15_TI1_TIM2_CH1 TIM_TISEL_TI1SEL_0 /* !< TIM15_TI1 is connected to TIM2 CH1 */ #define TIM_TIM15_TI1_TIM3_CH1 TIM_TISEL_TI1SEL_1 /* !< TIM15_TI1 is connected to TIM3 CH1 */ @@ -209,8 +216,10 @@ TIMEx_BreakInputConfigTypeDef; #define TIM_TIM16_TI1_WKUP_IT (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM16 TI1 is connected to WKUP_IT */ #define TIM_TIM17_TI1_GPIO 0x00000000U /* !< TIM17 TI1 is connected to GPIO */ -#define TIM_TIM17_TI1_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM17 TI1 is connected to RCC LSI */ -#define TIM_TIM17_TI1_RCC_HSE1MHZ TIM_TISEL_TI1SEL_1 /* !< TIM17 TI1 is connected to RCC LSE */ +#if defined(TIM17_TI1_SPDIF_FS_SUPPORT) +#define TIM_TIM17_TI1_SPDIF_FS TIM_TISEL_TI1SEL_0 /* !< TIM17 TI1 is connected to SPDIF FS */ +#endif /* TIM17_TI1_SPDIF_FS_SUPPORT */ +#define TIM_TIM17_TI1_RCC_HSE1MHZ TIM_TISEL_TI1SEL_1 /* !< TIM17 TI1 is connected to RCC HSE 1Mhz */ #define TIM_TIM17_TI1_RCC_MCO1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM17 TI1 is connected to RCC MCO1 */ /** * @} @@ -285,18 +294,18 @@ TIMEx_BreakInputConfigTypeDef; ((__TISEL__) == TIM_TIM17_TI1_RCC_MCO1)) #define IS_TIM_REMAP(__RREMAP__) (((__RREMAP__) == TIM_TIM1_ETR_GPIO) ||\ - ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD1) ||\ - ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD2) ||\ - ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD3) ||\ + ((__RREMAP__) == TIM_TIM1_ETR_ADC2_AWD1) ||\ + ((__RREMAP__) == TIM_TIM1_ETR_ADC2_AWD2) ||\ + ((__RREMAP__) == TIM_TIM1_ETR_ADC2_AWD3) ||\ ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD1) ||\ ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD2) ||\ ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD3) ||\ ((__RREMAP__) == TIM_TIM1_ETR_COMP1) ||\ ((__RREMAP__) == TIM_TIM1_ETR_COMP2) ||\ ((__RREMAP__) == TIM_TIM8_ETR_GPIO) ||\ - ((__RREMAP__) == TIM_TIM8_ETR_ADC1_AWD1) ||\ - ((__RREMAP__) == TIM_TIM8_ETR_ADC1_AWD2) ||\ - ((__RREMAP__) == TIM_TIM8_ETR_ADC1_AWD3) ||\ + ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD1) ||\ + ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD2) ||\ + ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD3) ||\ ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD1) ||\ ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD2) ||\ ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD3) ||\ diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_uart.c b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_uart.c index a6710cba27b..2e0a4c66e7d 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_uart.c +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_uart.c @@ -334,7 +334,6 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; - /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); /* Set the UART Communication parameters */ @@ -354,7 +353,6 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ @@ -401,7 +399,6 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; - /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); /* Set the UART Communication parameters */ @@ -424,7 +421,6 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); - /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ @@ -489,7 +485,6 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe huart->gState = HAL_UART_STATE_BUSY; - /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); /* Set the UART Communication parameters */ @@ -515,7 +510,6 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe /* Set the USART LIN Break detection length. */ MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength); - /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ @@ -575,7 +569,6 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add huart->gState = HAL_UART_STATE_BUSY; - /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); /* Set the UART Communication parameters */ @@ -604,7 +597,6 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add /* Set the wake up method by setting the WAKE bit in the CR1 register */ MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod); - /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ @@ -630,7 +622,6 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; - /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); huart->Instance->CR1 = 0x0U; @@ -653,7 +644,6 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_RESET; huart->RxState = HAL_UART_STATE_RESET; - /* Process Unlock */ __HAL_UNLOCK(huart); return HAL_OK; @@ -712,18 +702,18 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; if (pCallback == NULL) { - /* Update the error code */ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; return HAL_ERROR; } - /* Process locked */ + __HAL_LOCK(huart); if (huart->gState == HAL_UART_STATE_READY) @@ -783,10 +773,8 @@ HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_ break; default : - /* Update the error code */ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - /* Return error status */ status = HAL_ERROR; break; } @@ -804,24 +792,19 @@ HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_ break; default : - /* Update the error code */ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - /* Return error status */ status = HAL_ERROR; break; } } else { - /* Update the error code */ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - /* Return error status */ status = HAL_ERROR; } - /* Release Lock */ __HAL_UNLOCK(huart); return status; @@ -852,7 +835,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ __HAL_LOCK(huart); if (HAL_UART_STATE_READY == huart->gState) @@ -912,10 +894,8 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR break; default : - /* Update the error code */ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - /* Return error status */ status = HAL_ERROR; break; } @@ -933,24 +913,19 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR break; default : - /* Update the error code */ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - /* Return error status */ status = HAL_ERROR; break; } } else { - /* Update the error code */ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - /* Return error status */ status = HAL_ERROR; } - /* Release Lock */ __HAL_UNLOCK(huart); return status; @@ -1040,13 +1015,16 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR /** * @brief Send an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. * @note When FIFO mode is enabled, writing a data in the TDR register adds one * data to the TXFIFO. Write operations to the TDR register are performed * when TXFNF flag is set. From hardware perspective, TXFNF flag and * TXE are mapped on the same bit-field. * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be sent. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. * @param Timeout Timeout duration. * @retval HAL status */ @@ -1064,7 +1042,6 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u return HAL_ERROR; } - /* Process Locked */ __HAL_LOCK(huart); huart->ErrorCode = HAL_UART_ERROR_NONE; @@ -1076,7 +1053,7 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u huart->TxXferSize = Size; huart->TxXferCount = Size; - /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ + /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { pdata8bits = NULL; @@ -1115,7 +1092,6 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; @@ -1128,13 +1104,16 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u /** * @brief Receive an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO * is not empty. Read operations from the RDR register are performed when * RXFNE flag is set. From hardware perspective, RXFNE flag and * RXNE are mapped on the same bit-field. * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be received. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. * @param Timeout Timeout duration. * @retval HAL status */ @@ -1153,7 +1132,6 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui return HAL_ERROR; } - /* Process Locked */ __HAL_LOCK(huart); huart->ErrorCode = HAL_UART_ERROR_NONE; @@ -1204,7 +1182,6 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; @@ -1217,9 +1194,12 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui /** * @brief Send an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be sent. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) @@ -1232,7 +1212,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData return HAL_ERROR; } - /* Process Locked */ __HAL_LOCK(huart); huart->pTxBuffPtr = pData; @@ -1256,7 +1235,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData huart->TxISR = UART_TxISR_8BIT_FIFOEN; } - /* Process Unlocked */ __HAL_UNLOCK(huart); /* Enable the TX FIFO threshold interrupt */ @@ -1274,7 +1252,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData huart->TxISR = UART_TxISR_8BIT; } - /* Process Unlocked */ __HAL_UNLOCK(huart); /* Enable the Transmit Data Register Empty interrupt */ @@ -1291,9 +1268,12 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData /** * @brief Receive an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be received. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) @@ -1306,7 +1286,6 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, return HAL_ERROR; } - /* Process Locked */ __HAL_LOCK(huart); huart->pRxBuffPtr = pData; @@ -1336,7 +1315,6 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, huart->RxISR = UART_RxISR_8BIT_FIFOEN; } - /* Process Unlocked */ __HAL_UNLOCK(huart); /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ @@ -1355,7 +1333,6 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, huart->RxISR = UART_RxISR_8BIT; } - /* Process Unlocked */ __HAL_UNLOCK(huart); /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ @@ -1372,9 +1349,12 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, /** * @brief Send an amount of data in DMA mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be sent. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) @@ -1387,7 +1367,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat return HAL_ERROR; } - /* Process Locked */ __HAL_LOCK(huart); huart->pTxBuffPtr = pData; @@ -1417,7 +1396,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; - /* Process Unlocked */ __HAL_UNLOCK(huart); /* Restore huart->gState to ready */ @@ -1429,7 +1407,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat /* Clear the TC flag in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); - /* Process Unlocked */ __HAL_UNLOCK(huart); /* Enable the DMA transfer for transmit request by setting the DMAT bit @@ -1448,9 +1425,12 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat * @brief Receive an amount of data in DMA mode. * @note When the UART parity is enabled (PCE = 1), the received data contain * the parity bit (MSB position). + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. * @param huart UART handle. - * @param pData Pointer to data buffer. - * @param Size Amount of data to be received. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) @@ -1463,7 +1443,6 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData return HAL_ERROR; } - /* Process Locked */ __HAL_LOCK(huart); huart->pRxBuffPtr = pData; @@ -1492,7 +1471,6 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; - /* Process Unlocked */ __HAL_UNLOCK(huart); /* Restore huart->gState to ready */ @@ -1501,7 +1479,6 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData return HAL_ERROR; } } - /* Process Unlocked */ __HAL_UNLOCK(huart); /* Enable the UART Parity Error Interrupt */ @@ -1532,7 +1509,6 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) const HAL_UART_StateTypeDef gstate = huart->gState; const HAL_UART_StateTypeDef rxstate = huart->RxState; - /* Process Locked */ __HAL_LOCK(huart); if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && @@ -1552,7 +1528,6 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); } - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; @@ -1565,7 +1540,6 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) { - /* Process Locked */ __HAL_LOCK(huart); if (huart->gState == HAL_UART_STATE_BUSY_TX) @@ -1586,7 +1560,6 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); } - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; @@ -1671,7 +1644,7 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) { /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ @@ -1748,7 +1721,6 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; - /* Reset Handle ErrorCode to No Error */ huart->ErrorCode = HAL_UART_ERROR_NONE; return HAL_OK; @@ -1765,7 +1737,7 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) { /* Disable TCIE, TXEIE and TXFTIE interrupts */ @@ -1823,7 +1795,7 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) { /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */ @@ -1883,7 +1855,7 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) { uint32_t abortcplt = 1U; @@ -2027,7 +1999,7 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) { /* Disable interrupts */ @@ -2117,7 +2089,7 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ @@ -2212,7 +2184,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) uint32_t errorcode; /* If no error occurs */ - errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); if (errorflags == 0U) { /* UART in mode Receiver ---------------------------------------------------*/ @@ -2231,7 +2203,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /* If some errors occur */ if ((errorflags != 0U) && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) - || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U)))) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))) { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) @@ -2267,10 +2239,18 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) huart->ErrorCode |= HAL_UART_ERROR_ORE; } - /* Call UART Error Call back function if need be --------------------------*/ + /* UART Receiver Timeout interrupt occurred ---------------------------------*/ + if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + + huart->ErrorCode |= HAL_UART_ERROR_RTO; + } + + /* Call UART Error Call back function if need be ----------------------------*/ if (huart->ErrorCode != HAL_UART_ERROR_NONE) { - /* UART in mode Receiver ---------------------------------------------------*/ + /* UART in mode Receiver --------------------------------------------------*/ if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || ((cr3its & USART_CR3_RXFTIE) != 0U))) @@ -2281,11 +2261,14 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) } } - /* If Overrun error occurs, or if any error occurs in DMA mode reception, - consider error as blocking */ + /* If Error is to be considered as blocking : + - Receiver Timeout error in Reception + - Overrun error in Reception + - any error occurs in DMA mode reception + */ errorcode = huart->ErrorCode; if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || - ((errorcode & HAL_UART_ERROR_ORE) != 0U)) + ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) { /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, @@ -2551,6 +2534,9 @@ __weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) =============================================================================== [..] This subsection provides a set of functions allowing to control the UART. + (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly + (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature + (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode @@ -2564,6 +2550,99 @@ __weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) * @{ */ +/** + * @brief Update on the fly the receiver timeout value in RTOR register. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param TimeoutValue receiver timeout value in number of baud blocks. The timeout + * value must be less or equal to 0x0FFFFFFFF. + * @retval None + */ +void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue) +{ + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue)); + MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue); + } +} + +/** + * @brief Enable the UART receiver timeout feature. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart) +{ + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + if (huart->gState == HAL_UART_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Set the USART RTOEN bit */ + SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Disable the UART receiver timeout feature. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart) +{ + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + if (huart->gState == HAL_UART_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear the USART RTOEN bit */ + CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } + } + else + { + return HAL_ERROR; + } +} + /** * @brief Enable UART in mute mode (does not mean UART enters mute mode; * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called). @@ -2572,7 +2651,6 @@ __weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) { - /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; @@ -2593,7 +2671,6 @@ HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) { - /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; @@ -2624,7 +2701,6 @@ void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) { - /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; @@ -2636,7 +2712,6 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_READY; - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; @@ -2649,7 +2724,6 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) { - /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; @@ -2661,7 +2735,6 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_READY; - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; @@ -2678,7 +2751,6 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) /* Check the parameters */ assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); - /* Process Locked */ __HAL_LOCK(huart); huart->gState = HAL_UART_STATE_BUSY; @@ -2688,7 +2760,6 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_READY; - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; @@ -2699,8 +2770,8 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) */ /** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions - * @brief UART Peripheral State functions - * + * @brief UART Peripheral State functions + * @verbatim ============================================================================== ##### Peripheral State and Error functions ##### @@ -2722,7 +2793,8 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) */ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) { - uint32_t temp1, temp2; + uint32_t temp1; + uint32_t temp2; temp1 = huart->gState; temp2 = huart->RxState; @@ -2734,7 +2806,7 @@ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART. * @retval UART Error Code -*/ + */ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) { return huart->ErrorCode; @@ -2790,6 +2862,7 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) uint32_t lpuart_ker_ck_pres = 0x00000000U; PLL2_ClocksTypeDef pll2_clocks; PLL3_ClocksTypeDef pll3_clocks; + uint32_t pclk; /* Check the parameters */ assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); @@ -2868,7 +2941,7 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) case UART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) { - lpuart_ker_ck_pres = ((uint32_t) (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)) / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler)); + lpuart_ker_ck_pres = ((uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)) / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler)); } else { @@ -2881,7 +2954,6 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) case UART_CLOCKSOURCE_LSE: lpuart_ker_ck_pres = ((uint32_t)LSE_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler)); break; - case UART_CLOCKSOURCE_UNDEFINED: default: ret = HAL_ERROR; break; @@ -2901,7 +2973,8 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) switch (clocksource) { case UART_CLOCKSOURCE_D3PCLK1: - usartdiv = (uint32_t)(UART_DIV_LPUART(HAL_RCCEx_GetD3PCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = HAL_RCCEx_GetD3PCLK1Freq(); + usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); @@ -2927,7 +3000,6 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) case UART_CLOCKSOURCE_LSE: usartdiv = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; - case UART_CLOCKSOURCE_UNDEFINED: default: ret = HAL_ERROR; break; @@ -2951,10 +3023,12 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) switch (clocksource) { case UART_CLOCKSOURCE_D2PCLK1: - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = HAL_RCC_GetPCLK1Freq(); + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_D2PCLK2: - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = HAL_RCC_GetPCLK2Freq(); + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); @@ -2980,7 +3054,6 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) case UART_CLOCKSOURCE_LSE: usartdiv = (uint16_t)(UART_DIV_SAMPLING8((uint32_t)LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; - case UART_CLOCKSOURCE_UNDEFINED: default: ret = HAL_ERROR; break; @@ -3003,10 +3076,12 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) switch (clocksource) { case UART_CLOCKSOURCE_D2PCLK1: - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = HAL_RCC_GetPCLK1Freq(); + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_D2PCLK2: - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate, huart->Init.ClockPrescaler)); + pclk = HAL_RCC_GetPCLK2Freq(); + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; case UART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); @@ -3032,7 +3107,6 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) case UART_CLOCKSOURCE_LSE: usartdiv = (uint16_t)(UART_DIV_SAMPLING16((uint32_t)LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler)); break; - case UART_CLOCKSOURCE_UNDEFINED: default: ret = HAL_ERROR; break; @@ -3175,7 +3249,6 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_OK; @@ -3190,7 +3263,8 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) { /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) @@ -3207,11 +3281,32 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; - /* Process Unlocked */ __HAL_UNLOCK(huart); return HAL_TIMEOUT; } + + if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) + { + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) + { + /* Clear Receiver Timeout flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ErrorCode = HAL_UART_ERROR_RTO; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_TIMEOUT; + } + } } } return HAL_OK; diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_uart.h b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_uart.h index 6f4aac783ab..d20657e125f 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_uart.h +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_uart.h @@ -133,8 +133,6 @@ typedef struct This parameter can be a value of @ref UART_MSB_First. */ } UART_AdvFeatureInitTypeDef; - - /** * @brief HAL UART State definition * @note HAL UART State value is a combination of 2 different substates: gState and RxState (see @ref UART_State_Definition). @@ -190,7 +188,6 @@ typedef enum UART_CLOCKSOURCE_CSI = 0x20U, /*!< CSI clock source */ UART_CLOCKSOURCE_LSE = 0x40U, /*!< LSE clock source */ UART_CLOCKSOURCE_UNDEFINED = 0x80U /*!< Undefined clock source */ - } UART_ClockSourceTypeDef; /** @@ -225,9 +222,9 @@ typedef struct __UART_HandleTypeDef uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ - void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ + void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ - void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ + void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ @@ -335,8 +332,10 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer #define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */ #define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ #define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ +#define HAL_UART_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver Timeout error */ + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid Callback error */ +#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ /** * @} @@ -441,11 +440,11 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @} */ -/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut +/** @defgroup UART_Receiver_Timeout UART Receiver Timeout * @{ */ -#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART receiver timeout disable */ -#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART receiver timeout enable */ +#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART Receiver Timeout disable */ +#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART Receiver Timeout enable */ /** * @} */ @@ -699,6 +698,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer #define UART_FLAG_BUSY USART_ISR_BUSY /*!< UART busy flag */ #define UART_FLAG_ABRF USART_ISR_ABRF /*!< UART auto Baud rate flag */ #define UART_FLAG_ABRE USART_ISR_ABRE /*!< UART auto Baud rate error */ +#define UART_FLAG_RTOF USART_ISR_RTOF /*!< UART receiver timeout flag */ #define UART_FLAG_CTS USART_ISR_CTS /*!< UART clear to send flag */ #define UART_FLAG_CTSIF USART_ISR_CTSIF /*!< UART clear to send interrupt flag */ #define UART_FLAG_LBDF USART_ISR_LBDF /*!< UART LIN break detection flag */ @@ -749,6 +749,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer #define UART_IT_TXFE 0x173EU /*!< UART TXFIFO empty interruption */ #define UART_IT_RXFT 0x1A7CU /*!< UART RXFIFO threshold reached interruption */ #define UART_IT_TXFT 0x1B77U /*!< UART TXFIFO threshold reached interruption */ +#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */ #define UART_IT_ERR 0x0060U /*!< UART error interruption */ @@ -773,6 +774,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer #define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ #define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */ #define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */ +#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< UART receiver timeout clear flag */ /** * @} */ @@ -811,9 +813,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer */ #define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \ do{ \ - SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \ - SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \ - } while(0U) + SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \ + } while(0U) /** @brief Clear the specified UART pending flag. * @param __HANDLE__ specifies the UART Handle. @@ -826,6 +828,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag * @arg @ref UART_CLEAR_TXFECF TXFIFO empty clear Flag * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref UART_CLEAR_RTOF Receiver Timeout clear flag * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag * @arg @ref UART_CLEAR_CMF Character Match Clear Flag @@ -894,6 +897,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_FLAG_TC Transmission Complete flag * @arg @ref UART_FLAG_RXNE Receive data register not empty flag * @arg @ref UART_FLAG_RXFNE UART RXFIFO not empty flag + * @arg @ref UART_FLAG_RTOF Receiver Timeout flag * @arg @ref UART_FLAG_IDLE Idle Line detection flag * @arg @ref UART_FLAG_ORE Overrun Error flag * @arg @ref UART_FLAG_NE Noise Error flag @@ -920,6 +924,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_IT_TC Transmission complete interrupt * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt * @arg @ref UART_IT_IDLE Idle line detection interrupt * @arg @ref UART_IT_PE Parity Error interrupt * @arg @ref UART_IT_ERR Error interrupt (frame error, noise error, overrun error) @@ -947,6 +952,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_IT_TC Transmission complete interrupt * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt * @arg @ref UART_IT_IDLE Idle line detection interrupt * @arg @ref UART_IT_PE Parity Error interrupt * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) @@ -973,12 +979,14 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_IT_TC Transmission complete interrupt * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt * @arg @ref UART_IT_IDLE Idle line detection interrupt * @arg @ref UART_IT_PE Parity Error interrupt * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET) +#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ + & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET) /** @brief Check whether the specified UART interrupt source is enabled or not. * @param __HANDLE__ specifies the UART Handle. @@ -997,14 +1005,15 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_IT_TC Transmission complete interrupt * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt * @arg @ref UART_IT_IDLE Idle line detection interrupt * @arg @ref UART_IT_PE Parity Error interrupt * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) * @retval The new state of __INTERRUPT__ (SET or RESET). */ #define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : \ - (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET) + (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET) /** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the UART Handle. @@ -1016,6 +1025,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref UART_CLEAR_RTOF Receiver timeout clear flag * @arg @ref UART_CLEAR_TXFECF TXFIFO empty Clear Flag * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag @@ -1166,7 +1176,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @param __CLOCKPRESCALER__ UART prescaler value. * @retval Division result */ -#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((uint32_t)(((((uint64_t)(__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*256U) + (uint32_t)((__BAUD__)/2U)) / (__BAUD__))) +#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((uint32_t)(((((uint64_t)(__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*256U)\ + + (uint32_t)((__BAUD__)/2U)) / (__BAUD__))) /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. * @param __PCLK__ UART clock. @@ -1174,7 +1185,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @param __CLOCKPRESCALER__ UART prescaler value. * @retval Division result */ -#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*2U) + ((__BAUD__)/2U)) / (__BAUD__)) +#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*2U)\ + + ((__BAUD__)/2U)) / (__BAUD__)) /** @brief BRR division operation to set BRR register in 16-bit oversampling mode. * @param __PCLK__ UART clock. @@ -1182,7 +1194,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @param __CLOCKPRESCALER__ UART prescaler value. * @retval Division result */ -#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__))) + ((__BAUD__)/2U)) / (__BAUD__)) +#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))\ + + ((__BAUD__)/2U)) / (__BAUD__)) /** @brief Check whether or not UART instance is Low Power UART. * @param __HANDLE__ specifies the UART Handle. @@ -1243,10 +1256,10 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid) */ #define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\ - (((__CONTROL__) == UART_HWCONTROL_NONE) || \ - ((__CONTROL__) == UART_HWCONTROL_RTS) || \ - ((__CONTROL__) == UART_HWCONTROL_CTS) || \ - ((__CONTROL__) == UART_HWCONTROL_RTS_CTS)) + (((__CONTROL__) == UART_HWCONTROL_NONE) || \ + ((__CONTROL__) == UART_HWCONTROL_RTS) || \ + ((__CONTROL__) == UART_HWCONTROL_CTS) || \ + ((__CONTROL__) == UART_HWCONTROL_RTS_CTS)) /** * @brief Ensure that UART communication mode is valid. @@ -1294,8 +1307,15 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @param __TIMEOUT__ UART receiver timeout setting. * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) */ -#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \ - ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE)) +#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \ + ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE)) + +/** @brief Check the receiver timeout value. + * @note The maximum UART receiver timeout value is 0xFFFFFF. + * @param __TIMEOUTVALUE__ receiver timeout value. + * @retval Test result (TRUE or FALSE) + */ +#define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU) /** * @brief Ensure that UART LIN state is valid. @@ -1514,7 +1534,8 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ @@ -1563,6 +1584,10 @@ void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart); */ /* Peripheral Control functions ************************************************/ +void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue); +HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart); + HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart); @@ -1599,7 +1624,8 @@ void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart); HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart); -HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); /** diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_uart_ex.c b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_uart_ex.c index f379759a1d5..d6673100a49 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_uart_ex.c +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_uart_ex.c @@ -163,7 +163,8 @@ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart); * oversampling rate). * @retval HAL status */ -HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime) +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, + uint32_t DeassertionTime) { uint32_t temp; @@ -314,7 +315,7 @@ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) /** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions * @brief Extended Peripheral Control functions - * + * @verbatim =============================================================================== ##### Peripheral Control functions ##### @@ -335,9 +336,6 @@ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) * @{ */ - - - /** * @brief By default in multiprocessor mode, when the wake up method is set * to address mark, the UART handles only 4-bit long addresses detection; diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_uart_ex.h b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_uart_ex.h index 106f37e831c..a875a0092f2 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_uart_ex.h +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_uart_ex.h @@ -69,9 +69,9 @@ typedef struct /** @defgroup UARTEx_Word_Length UARTEx Word Length * @{ */ -#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */ -#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */ -#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */ +#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */ +#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */ +#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */ /** * @} */ @@ -79,8 +79,8 @@ typedef struct /** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length * @{ */ -#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */ -#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */ +#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */ +#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */ /** * @} */ @@ -89,8 +89,8 @@ typedef struct * @brief UART FIFO mode * @{ */ -#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ -#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ +#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ +#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ /** * @} */ @@ -138,7 +138,8 @@ typedef struct */ /* Initialization and de-initialization functions ****************************/ -HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime); +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, + uint32_t DeassertionTime); /** * @} @@ -165,7 +166,9 @@ void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart); + HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); + HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); @@ -189,6 +192,7 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 * @param __CLOCKSOURCE__ output variable. * @retval UART clocking source, written in __CLOCKSOURCE__. */ +#if defined(UART9) && defined(USART10) #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ @@ -407,6 +411,60 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 break; \ } \ } \ + else if((__HANDLE__)->Instance == UART9) \ + { \ + switch(__HAL_RCC_GET_UART9_SOURCE()) \ + { \ + case RCC_UART9CLKSOURCE_D2PCLK2: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2; \ + break; \ + case RCC_UART9CLKSOURCE_PLL2: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \ + break; \ + case RCC_UART9CLKSOURCE_PLL3: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \ + break; \ + case RCC_UART9CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_UART9CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_UART9CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART10) \ + { \ + switch(__HAL_RCC_GET_USART10_SOURCE()) \ + { \ + case RCC_USART10CLKSOURCE_D2PCLK2: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2; \ + break; \ + case RCC_USART10CLKSOURCE_PLL2: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \ + break; \ + case RCC_USART10CLKSOURCE_PLL3: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \ + break; \ + case RCC_USART10CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART10CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART10CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ else if((__HANDLE__)->Instance == LPUART1) \ { \ switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ @@ -439,6 +497,258 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ } \ } while(0U) +#else +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_D2PCLK2: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_PLL2: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \ + break; \ + case RCC_USART1CLKSOURCE_PLL3: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_D2PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_PLL2: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \ + break; \ + case RCC_USART2CLKSOURCE_PLL3: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ + case RCC_USART3CLKSOURCE_D2PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \ + break; \ + case RCC_USART3CLKSOURCE_PLL2: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \ + break; \ + case RCC_USART3CLKSOURCE_PLL3: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \ + break; \ + case RCC_USART3CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART3CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART3CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == UART4) \ + { \ + switch(__HAL_RCC_GET_UART4_SOURCE()) \ + { \ + case RCC_UART4CLKSOURCE_D2PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \ + break; \ + case RCC_UART4CLKSOURCE_PLL2: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \ + break; \ + case RCC_UART4CLKSOURCE_PLL3: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \ + break; \ + case RCC_UART4CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_UART4CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_UART4CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if ((__HANDLE__)->Instance == UART5) \ + { \ + switch(__HAL_RCC_GET_UART5_SOURCE()) \ + { \ + case RCC_UART5CLKSOURCE_D2PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \ + break; \ + case RCC_UART5CLKSOURCE_PLL2: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \ + break; \ + case RCC_UART5CLKSOURCE_PLL3: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \ + break; \ + case RCC_UART5CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_UART5CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_UART5CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART6) \ + { \ + switch(__HAL_RCC_GET_USART6_SOURCE()) \ + { \ + case RCC_USART6CLKSOURCE_D2PCLK2: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2; \ + break; \ + case RCC_USART6CLKSOURCE_PLL2: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \ + break; \ + case RCC_USART6CLKSOURCE_PLL3: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \ + break; \ + case RCC_USART6CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART6CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART6CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == UART7) \ + { \ + switch(__HAL_RCC_GET_UART7_SOURCE()) \ + { \ + case RCC_UART7CLKSOURCE_D2PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \ + break; \ + case RCC_UART7CLKSOURCE_PLL2: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \ + break; \ + case RCC_UART7CLKSOURCE_PLL3: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \ + break; \ + case RCC_UART7CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_UART7CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_UART7CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == UART8) \ + { \ + switch(__HAL_RCC_GET_UART8_SOURCE()) \ + { \ + case RCC_UART8CLKSOURCE_D2PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \ + break; \ + case RCC_UART8CLKSOURCE_PLL2: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \ + break; \ + case RCC_UART8CLKSOURCE_PLL3: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \ + break; \ + case RCC_UART8CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_UART8CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_UART8CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == LPUART1) \ + { \ + switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ + { \ + case RCC_LPUART1CLKSOURCE_D3PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D3PCLK1; \ + break; \ + case RCC_LPUART1CLKSOURCE_PLL2: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \ + break; \ + case RCC_LPUART1CLKSOURCE_PLL3: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \ + break; \ + case RCC_LPUART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_LPUART1CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_LPUART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#endif /* UART9 && USART10 */ /** @brief Report the UART mask to apply to retrieve the received data * according to the word length and to the parity bits activation. @@ -451,44 +761,44 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 */ #define UART_MASK_COMPUTATION(__HANDLE__) \ do { \ - if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ - { \ - if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ - { \ + if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ (__HANDLE__)->Mask = 0x01FFU ; \ - } \ - else \ - { \ + } \ + else \ + { \ (__HANDLE__)->Mask = 0x00FFU ; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ - { \ - if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ - { \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ (__HANDLE__)->Mask = 0x00FFU ; \ - } \ - else \ - { \ + } \ + else \ + { \ (__HANDLE__)->Mask = 0x007FU ; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \ - { \ - if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ - { \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ (__HANDLE__)->Mask = 0x007FU ; \ - } \ - else \ - { \ + } \ + else \ + { \ (__HANDLE__)->Mask = 0x003FU ; \ - } \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x0000U; \ - } \ -} while(0U) + } \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x0000U; \ + } \ + } while(0U) /** * @brief Ensure that UART frame length is valid. diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_usart.c b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_usart.c index 2537aaa368b..0458da47f73 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_usart.c +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_usart.c @@ -190,7 +190,8 @@ static void USART_DMAError(DMA_HandleTypeDef *hdma); static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma); static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); +static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart); static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart); static void USART_TxISR_8BIT(USART_HandleTypeDef *husart); @@ -421,7 +422,8 @@ __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) * @param pCallback pointer to the Callback function * @retval HAL status + */ -HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, + pUSART_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -732,9 +734,12 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ /** * @brief Simplex send an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pTxData. * @param husart USART handle. - * @param pTxData Pointer to data buffer. - * @param Size Amount of data to be sent. + * @param pTxData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. * @param Timeout Timeout duration. * @retval HAL status */ @@ -825,10 +830,13 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa /** * @brief Receive an amount of data in blocking mode. - * @note To receive synchronous data, dummy data are simultaneously transmitted. + * @note To receive synchronous data, dummy data are simultaneously transmitted. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pRxData. * @param husart USART handle. - * @param pRxData Pointer to data buffer. - * @param Size Amount of data to be received. + * @param pRxData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. * @param Timeout Timeout duration. * @retval HAL status */ @@ -934,14 +942,18 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat /** * @brief Full-Duplex Send and Receive an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number + * of u16 available through pTxData and through pRxData. * @param husart USART handle. - * @param pTxData pointer to TX data buffer. - * @param pRxData pointer to RX data buffer. - * @param Size amount of data to be sent (same amount to be received). + * @param pTxData pointer to TX data buffer (u8 or u16 data elements). + * @param pRxData pointer to RX data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be sent (same amount to be received). * @param Timeout Timeout duration. * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout) { uint8_t *prxdata8bits; uint16_t *prxdata16bits; @@ -1079,9 +1091,12 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t /** * @brief Send an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pTxData. * @param husart USART handle. - * @param pTxData pointer to data buffer. - * @param Size amount of data to be sent. + * @param pTxData pointer to data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) @@ -1158,10 +1173,13 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT /** * @brief Receive an amount of data in interrupt mode. - * @note To receive synchronous data, dummy data are simultaneously transmitted. + * @note To receive synchronous data, dummy data are simultaneously transmitted. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pRxData. * @param husart USART handle. - * @param pRxData pointer to data buffer. - * @param Size amount of data to be received. + * @param pRxData pointer to data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) @@ -1259,13 +1277,17 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx /** * @brief Full-Duplex Send and Receive an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number + * of u16 available through pTxData and through pRxData. * @param husart USART handle. - * @param pTxData pointer to TX data buffer. - * @param pRxData pointer to RX data buffer. - * @param Size amount of data to be sent (same amount to be received). + * @param pTxData pointer to TX data buffer (u8 or u16 data elements). + * @param pRxData pointer to RX data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be sent (same amount to be received). * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) { if (husart->State == HAL_USART_STATE_READY) @@ -1354,9 +1376,12 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint /** * @brief Send an amount of data in DMA mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pTxData. * @param husart USART handle. - * @param pTxData pointer to data buffer. - * @param Size amount of data to be sent. + * @param pTxData pointer to data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) @@ -1435,10 +1460,13 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p * @brief Receive an amount of data in DMA mode. * @note When the USART parity is enabled (PCE = 1), the received data contain * the parity bit (MSB position). - * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave. + * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pRxData. * @param husart USART handle. - * @param pRxData pointer to data buffer. - * @param Size amount of data to be received. + * @param pRxData pointer to data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) @@ -1549,13 +1577,17 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR /** * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode. * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number + * of u16 available through pTxData and through pRxData. * @param husart USART handle. - * @param pTxData pointer to TX data buffer. - * @param pRxData pointer to RX data buffer. - * @param Size amount of data to be received/sent. + * @param pTxData pointer to TX data buffer (u8 or u16 data elements). + * @param pRxData pointer to RX data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be received/sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) { HAL_StatusTypeDef status; uint32_t *tmp; @@ -1821,11 +1853,12 @@ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) { /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | + USART_CR1_TCIE)); CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); /* Disable the USART DMA Tx request if enabled */ @@ -1916,13 +1949,14 @@ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) { uint32_t abortcplt = 1U; /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | + USART_CR1_TCIE)); CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); /* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised @@ -2382,8 +2416,8 @@ __weak void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart) */ /** @defgroup USART_Exported_Functions_Group4 Peripheral State and Error functions - * @brief USART Peripheral State and Error functions - * + * @brief USART Peripheral State and Error functions + * @verbatim ============================================================================== ##### Peripheral State and Error functions ##### @@ -2429,8 +2463,8 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart) */ /** @defgroup USART_Private_Functions USART Private Functions - * @{ - */ + * @{ + */ /** * @brief Initialize the callbacks to their default values. @@ -2461,7 +2495,8 @@ void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart) static void USART_EndTransfer(USART_HandleTypeDef *husart) { /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | + USART_CR1_TCIE)); CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); /* At end of process, restore husart->State to Ready */ @@ -2769,7 +2804,8 @@ static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) * @param Timeout timeout duration. * @retval HAL status */ -static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) +static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) { /* Wait until flag is set */ while ((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status) @@ -2805,6 +2841,7 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) uint32_t usartdiv = 0x00000000; PLL2_ClocksTypeDef pll2_clocks; PLL3_ClocksTypeDef pll3_clocks; + uint32_t pclk; /* Check the parameters */ assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity)); @@ -2851,10 +2888,12 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) switch (clocksource) { case USART_CLOCKSOURCE_D2PCLK1: - usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate, husart->Init.ClockPrescaler)); + pclk = HAL_RCC_GetPCLK1Freq(); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler)); break; case USART_CLOCKSOURCE_D2PCLK2: - usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate, husart->Init.ClockPrescaler)); + pclk = HAL_RCC_GetPCLK2Freq(); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler)); break; case USART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_usart.h b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_usart.h index f06d41a6336..c794031a637 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_usart.h +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_usart.h @@ -437,10 +437,10 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin */ #if (USE_HAL_USART_REGISTER_CALLBACKS == 1) #define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_USART_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0U) + (__HANDLE__)->State = HAL_USART_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) #else #define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET) #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ @@ -594,7 +594,8 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_IT_PE Parity Error interrupt * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>> USART_ISR_POS))) != 0U) ? SET : RESET) +#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ + & ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>> USART_ISR_POS))) != 0U) ? SET : RESET) /** @brief Check whether the specified USART interrupt source is enabled or not. * @param __HANDLE__ specifies the USART Handle. @@ -617,8 +618,8 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @retval The new state of __INTERRUPT__ (SET or RESET). */ #define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ? (__HANDLE__)->Instance->CR1 : \ - (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK))) != 0U) ? SET : RESET) + (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ? (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK))) != 0U) ? SET : RESET) /** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag. @@ -705,13 +706,15 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @param __CLOCKPRESCALER__ UART prescaler value. * @retval Division result */ -#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U) + ((__BAUD__)/2U)) / (__BAUD__)) +#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U)\ + + ((__BAUD__)/2U)) / (__BAUD__)) /** @brief Report the USART clock source. * @param __HANDLE__ specifies the USART Handle. * @param __CLOCKSOURCE__ output variable. * @retval the USART clocking source, written in __CLOCKSOURCE__. */ +#if defined(UART9) && defined(USART10) #define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ @@ -749,7 +752,150 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK1; \ break; \ case RCC_USART2CLKSOURCE_PLL2: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2; \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2; \ + break; \ + case RCC_USART2CLKSOURCE_PLL3: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ + case RCC_USART3CLKSOURCE_D2PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK1; \ + break; \ + case RCC_USART3CLKSOURCE_PLL2: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2; \ + break; \ + case RCC_USART3CLKSOURCE_PLL3: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3; \ + break; \ + case RCC_USART3CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART3CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART3CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART6) \ + { \ + switch(__HAL_RCC_GET_USART6_SOURCE()) \ + { \ + case RCC_USART6CLKSOURCE_D2PCLK2: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK2; \ + break; \ + case RCC_USART6CLKSOURCE_PLL2: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2; \ + break; \ + case RCC_USART6CLKSOURCE_PLL3: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3; \ + break; \ + case RCC_USART6CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART6CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART6CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART10) \ + { \ + switch(__HAL_RCC_GET_USART10_SOURCE()) \ + { \ + case RCC_USART10CLKSOURCE_D2PCLK2: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK2; \ + break; \ + case RCC_USART10CLKSOURCE_PLL2: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2; \ + break; \ + case RCC_USART10CLKSOURCE_PLL3: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3; \ + break; \ + case RCC_USART10CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART10CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART10CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#else +#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_D2PCLK2: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_PLL2: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2; \ + break; \ + case RCC_USART1CLKSOURCE_PLL3: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_CSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_D2PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_PLL2: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2; \ break; \ case RCC_USART2CLKSOURCE_PLL3: \ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3; \ @@ -827,6 +973,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ } \ } while(0U) +#endif /* UART9 && USART10 */ /** @brief Check USART Baud rate. * @param __BAUDRATE__ Baudrate specified by the user. @@ -949,7 +1096,8 @@ void HAL_USART_MspDeInit(USART_HandleTypeDef *husart); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_USART_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, + pUSART_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ @@ -964,13 +1112,16 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size); HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size); HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart); diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_usart_ex.c b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_usart_ex.c index 03c0068cd5f..5a2f54ef8f1 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_usart_ex.c +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_usart_ex.c @@ -54,11 +54,17 @@ #ifdef HAL_USART_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ +/** @defgroup USARTEx_Private_Constants USARTEx Private Constants + * @{ + */ /* UART RX FIFO depth */ #define RX_FIFO_DEPTH 8U /* UART TX FIFO depth */ #define TX_FIFO_DEPTH 8U +/** + * @} + */ /* Private define ------------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_usart_ex.h b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_usart_ex.h index 188e03ffe14..8b6fe98ef86 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_usart_ex.h +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_usart_ex.h @@ -130,44 +130,44 @@ extern "C" { */ #define USART_MASK_COMPUTATION(__HANDLE__) \ do { \ - if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \ - { \ - if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ - { \ + if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ + { \ (__HANDLE__)->Mask = 0x01FFU; \ - } \ - else \ - { \ + } \ + else \ + { \ (__HANDLE__)->Mask = 0x00FFU; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \ - { \ - if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ - { \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ + { \ (__HANDLE__)->Mask = 0x00FFU; \ - } \ - else \ - { \ + } \ + else \ + { \ (__HANDLE__)->Mask = 0x007FU; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \ - { \ - if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ - { \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \ + { \ + if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ + { \ (__HANDLE__)->Mask = 0x007FU; \ - } \ - else \ - { \ + } \ + else \ + { \ (__HANDLE__)->Mask = 0x003FU; \ - } \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x0000U; \ - } \ -} while(0U) + } \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x0000U; \ + } \ + } while(0U) /** diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_adc.c b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_adc.c index 9944b1ecd05..26c48d15be7 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_adc.c +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_adc.c @@ -23,9 +23,9 @@ #include "stm32h7xx_ll_bus.h" #ifdef USE_FULL_ASSERT - #include "stm32_assert.h" +#include "stm32_assert.h" #else - #define assert_param(expr) ((void)0U) +#define assert_param(expr) ((void)0U) #endif /** @addtogroup STM32H7xx_LL_Driver @@ -332,7 +332,7 @@ ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) { /* Check the parameters */ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); - + if(ADCxy_COMMON == ADC12_COMMON) { /* Force reset of ADC clock (core clock) */ @@ -349,7 +349,7 @@ ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) /* Release reset of ADC clock (core clock) */ LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_ADC3); } - + return SUCCESS; } @@ -371,13 +371,13 @@ ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) { ErrorStatus status = SUCCESS; - + /* Check the parameters */ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock)); - + assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode)); - if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) + if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) { assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer)); assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay)); @@ -388,7 +388,7 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni /* On this STM32 serie, setting of these features is conditioned to */ /* ADC state: */ /* All ADC instances of the ADC common group must be disabled. */ - if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL) + if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL) { /* Configuration of ADC hierarchical scope: */ /* - common to several ADC */ @@ -399,16 +399,16 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni /* - Set ADC multimode configuration */ /* - Set ADC multimode DMA transfer */ /* - Set ADC multimode: delay between 2 sampling phases */ - if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) + if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) { MODIFY_REG(ADCxy_COMMON->CCR, - ADC_CCR_CKMODE + ADC_CCR_CKMODE | ADC_CCR_PRESC | ADC_CCR_DUAL | ADC_CCR_DAMDF | ADC_CCR_DELAY - , - ADC_CommonInitStruct->CommonClock + , + ADC_CommonInitStruct->CommonClock | ADC_CommonInitStruct->Multimode | ADC_CommonInitStruct->MultiDMATransfer | ADC_CommonInitStruct->MultiTwoSamplingDelay @@ -417,13 +417,13 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni else { MODIFY_REG(ADCxy_COMMON->CCR, - ADC_CCR_CKMODE + ADC_CCR_CKMODE | ADC_CCR_PRESC | ADC_CCR_DUAL | ADC_CCR_DAMDF | ADC_CCR_DELAY - , - ADC_CommonInitStruct->CommonClock + , + ADC_CommonInitStruct->CommonClock | LL_ADC_MULTI_INDEPENDENT ); } @@ -434,7 +434,7 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni /* the same ADC common instance are not disabled. */ status = ERROR; } - + return status; } @@ -450,7 +450,7 @@ void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) /* Set fields of ADC common */ /* (all ADC instances belonging to the same ADC common instance) */ ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2; - + /* Set fields of ADC multimode */ ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT; ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC; @@ -478,71 +478,71 @@ void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) { ErrorStatus status = SUCCESS; - + __IO uint32_t timeout_cpu_cycles = 0UL; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(ADCx)); - + /* Disable ADC instance if not already disabled. */ - if(LL_ADC_IsEnabled(ADCx) == 1UL) + if (LL_ADC_IsEnabled(ADCx) == 1UL) { /* Set ADC group regular trigger source to SW start to ensure to not */ /* have an external trigger event occurring during the conversion stop */ /* ADC disable process. */ LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE); - + /* Stop potential ADC conversion on going on ADC group regular. */ - if(LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL) + if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL) { - if(LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL) + if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL) { LL_ADC_REG_StopConversion(ADCx); } } - + /* Set ADC group injected trigger source to SW start to ensure to not */ /* have an external trigger event occurring during the conversion stop */ /* ADC disable process. */ LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE); - + /* Stop potential ADC conversion on going on ADC group injected. */ - if(LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL) + if (LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL) { - if(LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0UL) + if (LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0UL) { LL_ADC_INJ_StopConversion(ADCx); } } - + /* Wait for ADC conversions are effectively stopped */ timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES; - while (( LL_ADC_REG_IsStopConversionOngoing(ADCx) + while ((LL_ADC_REG_IsStopConversionOngoing(ADCx) | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1UL) { timeout_cpu_cycles--; - if(timeout_cpu_cycles == 0UL) + if (timeout_cpu_cycles == 0UL) { /* Time-out error */ status = ERROR; break; } } - + /* Flush group injected contexts queue (register JSQR): */ /* Note: Bit JQM must be set to empty the contexts queue (otherwise */ /* contexts queue is maintained with the last active context). */ LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY); - + /* Disable the ADC instance */ LL_ADC_Disable(ADCx); - + /* Wait for ADC instance is effectively disabled */ timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES; while (LL_ADC_IsDisableOngoing(ADCx) == 1UL) { timeout_cpu_cycles--; - if(timeout_cpu_cycles == 0UL) + if (timeout_cpu_cycles == 0UL) { /* Time-out error */ status = ERROR; @@ -550,18 +550,18 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) } } } - + /* Check whether ADC state is compliant with expected state */ - if(READ_BIT(ADCx->CR, - ( ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART - | ADC_CR_ADDIS | ADC_CR_ADEN ) - ) - == 0UL) + if (READ_BIT(ADCx->CR, + (ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART + | ADC_CR_ADDIS | ADC_CR_ADEN) + ) + == 0UL) { /* ========== Reset ADC registers ========== */ /* Reset register IER */ CLEAR_BIT(ADCx->IER, - ( LL_ADC_IT_ADRDY + (LL_ADC_IT_ADRDY | LL_ADC_IT_EOC | LL_ADC_IT_EOS | LL_ADC_IT_OVR @@ -574,10 +574,10 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) | LL_ADC_IT_AWD3 ) ); - + /* Reset register ISR */ SET_BIT(ADCx->ISR, - ( LL_ADC_FLAG_ADRDY + (LL_ADC_FLAG_ADRDY | LL_ADC_FLAG_EOC | LL_ADC_FLAG_EOS | LL_ADC_FLAG_OVR @@ -590,7 +590,7 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) | LL_ADC_FLAG_AWD3 ) ); - + /* Reset register CR */ /* - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, */ /* ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in */ @@ -603,7 +603,7 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) /* already done above. */ CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF); SET_BIT(ADCx->CR, ADC_CR_DEEPPWD); - + /* Reset register CFGR */ CLEAR_BIT(ADCx->CFGR, ( ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN @@ -626,60 +626,60 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) /* Reset register SMPR1 */ CLEAR_BIT(ADCx->SMPR1, - ( ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 + (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1) ); - + /* Reset register SMPR2 */ CLEAR_BIT(ADCx->SMPR2, - ( ADC_SMPR2_SMP19 | ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 + (ADC_SMPR2_SMP19 | ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10) ); - + /* Reset register TR1 */ CLEAR_BIT(ADCx->LTR1, ADC_LTR_LT); SET_BIT(ADCx->HTR1, ADC_HTR_HT); - + CLEAR_BIT(ADCx->LTR2, ADC_LTR_LT); SET_BIT(ADCx->HTR2, ADC_HTR_HT); CLEAR_BIT(ADCx->LTR3, ADC_LTR_LT); SET_BIT(ADCx->HTR3, ADC_HTR_HT); - + /* Reset register SQR1 */ CLEAR_BIT(ADCx->SQR1, - ( ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 + (ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 | ADC_SQR1_SQ1 | ADC_SQR1_L) ); - + /* Reset register SQR2 */ CLEAR_BIT(ADCx->SQR2, - ( ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 + (ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 | ADC_SQR2_SQ6 | ADC_SQR2_SQ5) ); - + /* Reset register SQR3 */ CLEAR_BIT(ADCx->SQR3, - ( ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 + (ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 | ADC_SQR3_SQ11 | ADC_SQR3_SQ10) ); - + /* Reset register SQR4 */ CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15); - + /* Reset register JSQR */ CLEAR_BIT(ADCx->JSQR, - ( ADC_JSQR_JL + (ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 - | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 ) + | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1) ); - + /* Reset register DR */ /* Note: bits in access mode read only, no direct reset applicable */ - + /* Reset register OFR1 */ CLEAR_BIT(ADCx->OFR1, ADC_OFR1_OFFSET1 | ADC_OFR1_OFFSET1_CH | ADC_OFR1_SSATE); /* Reset register OFR2 */ @@ -688,19 +688,19 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET3 | ADC_OFR3_OFFSET3_CH | ADC_OFR3_SSATE); /* Reset register OFR4 */ CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET4 | ADC_OFR4_OFFSET4_CH | ADC_OFR4_SSATE); - + /* Reset registers JDR1, JDR2, JDR3, JDR4 */ /* Note: bits in access mode read only, no direct reset applicable */ - + /* Reset register AWD2CR */ CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH); - + /* Reset register AWD3CR */ CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH); - + /* Reset register DIFSEL */ CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL); - + /* Reset register CALFACT */ CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S); @@ -720,7 +720,7 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) /* all ADC instances belonging to the common ADC instance. */ status = ERROR; } - + return status; } @@ -760,17 +760,17 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) { ErrorStatus status = SUCCESS; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(ADCx)); - + assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution)); assert_param(IS_LL_ADC_LEFT_BIT_SHIFT(ADC_InitStruct->LeftBitShift)); assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode)); - + /* Note: Hardware constraint (refer to description of this function): */ /* ADC instance must be disabled. */ - if(LL_ADC_IsEnabled(ADCx) == 0UL) + if (LL_ADC_IsEnabled(ADCx) == 0UL) { /* Configuration of ADC hierarchical scope: */ /* - ADC instance */ @@ -778,13 +778,13 @@ ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) /* - Set ADC conversion data alignment */ /* - Set ADC low power mode */ MODIFY_REG(ADCx->CFGR, - ADC_CFGR_RES + ADC_CFGR_RES | ADC_CFGR_AUTDLY - , - ADC_InitStruct->Resolution + , + ADC_InitStruct->Resolution | ADC_InitStruct->LowPowerMode ); - + MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LSHIFT, ADC_InitStruct->LeftBitShift); } else @@ -808,7 +808,7 @@ void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_16B; ADC_InitStruct->LeftBitShift = LL_ADC_LEFT_BIT_SHIFT_NONE; ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE; - + } /** @@ -846,22 +846,22 @@ void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) { ErrorStatus status = SUCCESS; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(ADCx)); assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource)); assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength)); - if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); } assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); assert_param(IS_LL_ADC_REG_DATA_TRANSFER_MODE(ADC_REG_InitStruct->DataTransferMode)); assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun)); - + /* Note: Hardware constraint (refer to description of this function): */ /* ADC instance must be disabled. */ - if(LL_ADC_IsEnabled(ADCx) == 0UL) + if (LL_ADC_IsEnabled(ADCx) == 0UL) { /* Configuration of ADC hierarchical scope: */ /* - ADC group regular */ @@ -874,18 +874,18 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I /* - Set ADC group regular overrun behavior */ /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */ /* setting of trigger source to SW start. */ - if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { MODIFY_REG(ADCx->CFGR, - ADC_CFGR_EXTSEL + ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN | ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_CONT | ADC_CFGR_DMNGT | ADC_CFGR_OVRMOD - , - ADC_REG_InitStruct->TriggerSource + , + ADC_REG_InitStruct->TriggerSource | ADC_REG_InitStruct->SequencerDiscont | ADC_REG_InitStruct->ContinuousMode | ADC_REG_InitStruct->DataTransferMode @@ -895,22 +895,22 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I else { MODIFY_REG(ADCx->CFGR, - ADC_CFGR_EXTSEL + ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN | ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_CONT | ADC_CFGR_DMNGT | ADC_CFGR_OVRMOD - , - ADC_REG_InitStruct->TriggerSource + , + ADC_REG_InitStruct->TriggerSource | LL_ADC_REG_SEQ_DISCONT_DISABLE | ADC_REG_InitStruct->ContinuousMode | ADC_REG_InitStruct->DataTransferMode | ADC_REG_InitStruct->Overrun ); } - + /* Set ADC group regular sequencer length and scan direction */ LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength); } @@ -977,20 +977,20 @@ void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) { ErrorStatus status = SUCCESS; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(ADCx)); assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource)); assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength)); - if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) + if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) { assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont)); } assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto)); - + /* Note: Hardware constraint (refer to description of this function): */ /* ADC instance must be disabled. */ - if(LL_ADC_IsEnabled(ADCx) == 0UL) + if (LL_ADC_IsEnabled(ADCx) == 0UL) { /* Configuration of ADC hierarchical scope: */ /* - ADC group injected */ @@ -1001,33 +1001,33 @@ ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_I /* from ADC group regular */ /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */ /* setting of trigger source to SW start. */ - if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { MODIFY_REG(ADCx->CFGR, - ADC_CFGR_JDISCEN + ADC_CFGR_JDISCEN | ADC_CFGR_JAUTO - , - ADC_INJ_InitStruct->SequencerDiscont + , + ADC_INJ_InitStruct->SequencerDiscont | ADC_INJ_InitStruct->TrigAuto ); } else { MODIFY_REG(ADCx->CFGR, - ADC_CFGR_JDISCEN + ADC_CFGR_JDISCEN | ADC_CFGR_JAUTO - , - LL_ADC_REG_SEQ_DISCONT_DISABLE + , + LL_ADC_REG_SEQ_DISCONT_DISABLE | ADC_INJ_InitStruct->TrigAuto ); } - + MODIFY_REG(ADCx->JSQR, - ADC_JSQR_JEXTSEL + ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN | ADC_JSQR_JL - , - ADC_INJ_InitStruct->TriggerSource + , + ADC_INJ_InitStruct->TriggerSource | ADC_INJ_InitStruct->SequencerLength ); } diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_adc.h b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_adc.h index 4c9a1d82339..bdae7b0ae24 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_adc.h +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_adc.h @@ -160,10 +160,10 @@ extern "C" { /* Mask containing trigger source masks for each of possible */ /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ -#define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \ - ((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | \ - ((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \ - ((ADC_JSQR_JEXTSEL) << (4U * 3UL)) ) +#define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \ + ((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | \ + ((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \ + ((ADC_JSQR_JEXTSEL) << (4U * 3UL)) ) /* Mask containing trigger edge masks for each of possible */ /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ @@ -371,6 +371,14 @@ extern "C" { #define TEMPSENSOR_CAL_VREFANALOG (3300UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */ +/* Registers addresses with ADC linearity calibration content (programmed during device production, specific to each device) */ +#define ADC_LINEAR_CALIB_REG_1_ADDR ((uint32_t*) (0x1FF1EC00UL)) +#define ADC_LINEAR_CALIB_REG_2_ADDR ((uint32_t*) (0x1FF1EC04UL)) +#define ADC_LINEAR_CALIB_REG_3_ADDR ((uint32_t*) (0x1FF1EC08UL)) +#define ADC_LINEAR_CALIB_REG_4_ADDR ((uint32_t*) (0x1FF1EC0CUL)) +#define ADC_LINEAR_CALIB_REG_5_ADDR ((uint32_t*) (0x1FF1EC10UL)) +#define ADC_LINEAR_CALIB_REG_6_ADDR ((uint32_t*) (0x1FF1EC14UL)) +#define ADC_LINEAR_CALIB_REG_COUNT (6UL) /** * @} */ @@ -390,7 +398,7 @@ extern "C" { * @retval Pointer to register address */ #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ - ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL)))) + ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL)))) /** * @} @@ -846,7 +854,6 @@ typedef struct #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */ #define LL_ADC_CHANNEL_19 (ADC_CHANNEL_19_NUMBER | ADC_CHANNEL_19_SMP | ADC_CHANNEL_19_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN19 */ -/*!< ADC3 is defined only in the case of STM32H7XX */ #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_19 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32H7, ADC channel available only on ADC instance: ADC3. */ #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32H7, ADC channel available only on ADC instance: ADC3. */ #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda. On STM32H7, ADC channel available only on ADC instance: ADC3. */ @@ -896,8 +903,8 @@ typedef struct */ /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode -* @{ -*/ + * @{ + */ #define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions are performed in single mode: one conversion per trigger */ #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */ /** @@ -916,8 +923,8 @@ typedef struct */ /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data -* @{ -*/ + * @{ + */ #define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun: data preserved */ #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */ /** @@ -1026,8 +1033,8 @@ typedef struct */ /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode -* @{ -*/ + * @{ + */ #define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL) /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */ #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */ /** @@ -1442,7 +1449,7 @@ typedef struct * @arg @ref LL_ADC_CHANNEL_VBAT (1) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2) - * + * * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). @@ -1451,13 +1458,13 @@ typedef struct */ #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) \ - ? ( \ + ? ( \ ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \ - ) \ - : \ - ( \ + ) \ + : \ + ( \ (uint32_t)POSITION_VAL((__CHANNEL__)) \ - ) \ + ) \ ) /** @@ -1493,7 +1500,7 @@ typedef struct * @arg @ref LL_ADC_CHANNEL_VBAT (1) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2) - * + * * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). @@ -1504,17 +1511,17 @@ typedef struct */ #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ (((__DECIMAL_NB__) <= 9UL) \ - ? ( \ + ? ( \ ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \ (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ - ) \ - : \ - ( \ + ) \ + : \ + ( \ ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \ (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ - ) \ + ) \ ) /** @@ -1560,7 +1567,7 @@ typedef struct * @arg @ref LL_ADC_CHANNEL_VBAT (1) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2) - * + * * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). @@ -1610,7 +1617,7 @@ typedef struct * @arg @ref LL_ADC_CHANNEL_VBAT (1) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2) - * + * * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). @@ -1660,7 +1667,7 @@ typedef struct * @arg @ref LL_ADC_CHANNEL_VBAT (1) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2) - * + * * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n * (2) On STM32H7, parameter available only on ADC instance: ADC2. * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. @@ -1682,6 +1689,8 @@ typedef struct ) \ ) \ ) + + /** * @brief Helper macro to define ADC analog watchdog parameter: * define a single channel to monitor with analog watchdog @@ -1717,7 +1726,7 @@ typedef struct * @arg @ref LL_ADC_CHANNEL_VBAT (1) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2) - * + * * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). @@ -1809,19 +1818,19 @@ typedef struct * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG (0)(2) * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ (0)(2) * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ (2) - * + * * (0) On STM32H7, parameter available only on analog watchdog number: AWD1.\n * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n * (2) On STM32H7, parameter available only on ADC instance: ADC2. */ #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \ (((__GROUP__) == LL_ADC_GROUP_REGULAR) \ - ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \ - : \ - ((__GROUP__) == LL_ADC_GROUP_INJECTED) \ - ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) \ - : \ - (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \ + ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \ + : \ + ((__GROUP__) == LL_ADC_GROUP_INJECTED) \ + ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) \ + : \ + (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \ ) /** @@ -2075,10 +2084,9 @@ typedef struct #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ __ADC_RESOLUTION__) \ (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \ - / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \ - (__ADC_RESOLUTION__), \ - LL_ADC_RESOLUTION_16B) \ - ) + / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \ + (__ADC_RESOLUTION__), \ + LL_ADC_RESOLUTION_16B)) /** * @brief Helper macro to calculate the temperature (unit: degree Celsius) @@ -2258,12 +2266,12 @@ __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Regis if (Register == LL_ADC_DMA_REG_REGULAR_DATA) { /* Retrieve address of register DR */ - data_reg_addr = (uint32_t)&(ADCx->DR); + data_reg_addr = (uint32_t) &(ADCx->DR); } else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */ { /* Retrieve address of register CDR */ - data_reg_addr = (uint32_t)&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR); + data_reg_addr = (uint32_t) &((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR); } return data_reg_addr; @@ -2565,7 +2573,7 @@ __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution { MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution); } - else /* rev.V */ + else /* Rev.V */ { if(LL_ADC_RESOLUTION_8B == Resolution) { @@ -2597,7 +2605,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES)); } - else + else /* Rev.V */ { if ((uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES)) == 0x0000001CUL) { @@ -2776,7 +2784,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_CHANNEL_VBAT (1) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2) - * + * * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). @@ -2847,7 +2855,7 @@ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint3 * @arg @ref LL_ADC_CHANNEL_VBAT (1) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2) - * + * * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). @@ -3387,7 +3395,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_CHANNEL_VBAT (1) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2) - * + * * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). @@ -3487,7 +3495,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * @arg @ref LL_ADC_CHANNEL_VBAT (1) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2) - * + * * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). @@ -3500,10 +3508,10 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_ { register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS)); - return (uint32_t) ((READ_BIT(*preg, + return (uint32_t)((READ_BIT(*preg, ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS - ); + ); } /** @@ -3918,7 +3926,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_CHANNEL_VBAT (1) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2) - * + * * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). @@ -3988,7 +3996,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * @arg @ref LL_ADC_CHANNEL_VBAT (1) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2) - * + * * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). @@ -4000,8 +4008,8 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) { return (uint32_t)((READ_BIT(ADCx->JSQR, - (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) - >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS + (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) + >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ); } @@ -4211,7 +4219,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_CHANNEL_VBAT (1) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2) - * + * * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). @@ -4242,7 +4250,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_CHANNEL_VBAT (1) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2) - * + * * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). @@ -4273,7 +4281,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_CHANNEL_VBAT (1) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2) - * + * * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). @@ -4304,7 +4312,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_CHANNEL_VBAT (1) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2) - * + * * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). @@ -4327,15 +4335,15 @@ __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, /* If parameter "TriggerSource" is set to SW start, then parameter */ /* "ExternalTriggerEdge" is discarded. */ register uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL); - MODIFY_REG(ADCx->JSQR , + MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 | - ADC_JSQR_JL , - TriggerSource | + ADC_JSQR_JL, + (TriggerSource & ADC_JSQR_JEXTSEL) | (ExternalTriggerEdge * (is_trigger_not_sw)) | (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) | (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) | @@ -4425,7 +4433,7 @@ __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, * @arg @ref LL_ADC_CHANNEL_VBAT (1) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2) - * + * * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). @@ -4511,7 +4519,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C * @arg @ref LL_ADC_CHANNEL_VBAT (1) * @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2) * @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2) - * + * * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n * (2) On STM32H7, parameter available only on ADC instance: ADC2.\n * (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)). @@ -4778,7 +4786,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG (0)(2) * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ (0)(2) * @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ (2) - * + * * (0) On STM32H7, parameter available only on analog watchdog number: AWD1.\n * (1) On STM32H7, parameter available only on ADC instance: ADC3.\n * (2) On STM32H7, parameter available only on ADC instance: ADC2. @@ -4791,7 +4799,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */ /* containing other bits reserved for other purpose. */ register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) - + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); + + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); MODIFY_REG(*preg, (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK), @@ -4920,13 +4928,13 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (0) * @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (0) * @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ - * + * * (0) On STM32H7, parameter available only on analog watchdog number: AWD1. */ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy) { register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) - + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); + + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); register uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK); @@ -4934,14 +4942,14 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint /* (parameter value LL_ADC_AWD_DISABLE). */ /* Else, the selected AWD is enabled and is monitoring a group of channels */ /* or a single channel. */ - if(AnalogWDMonitChannels != 0UL) + if (AnalogWDMonitChannels != 0UL) { - if(AWDy == LL_ADC_AWD1) + if (AWDy == LL_ADC_AWD1) { - if((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0UL) + if ((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0UL) { /* AWD monitoring a group of channels */ - AnalogWDMonitChannels = (( AnalogWDMonitChannels + AnalogWDMonitChannels = ((AnalogWDMonitChannels | (ADC_AWD_CR23_CHANNEL_MASK) ) & (~(ADC_CFGR_AWD1CH)) @@ -4957,10 +4965,10 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint } else { - if((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK) + if ((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK) { /* AWD monitoring a group of channels */ - AnalogWDMonitChannels = ( ADC_AWD_CR23_CHANNEL_MASK + AnalogWDMonitChannels = (ADC_AWD_CR23_CHANNEL_MASK | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN)) ); } @@ -4968,7 +4976,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint { /* AWD monitoring a single channel */ /* AWD monitoring a group of channels */ - AnalogWDMonitChannels = ( AnalogWDMonitChannels + AnalogWDMonitChannels = (AnalogWDMonitChannels | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR_AWD1CH_Pos) ); @@ -5032,7 +5040,8 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None */ -__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue) +__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, + uint32_t AWDThresholdValue) { /* Set bits with content of parameter "AWDThresholdValue" with bits */ /* position in register and register position depending on parameters */ @@ -5068,7 +5077,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH * @arg @ref LL_ADC_AWD_THRESHOLD_LOW * @retval Value between Min_Data=0x000 and Max_Data=0x3FFFFFF -*/ + */ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow) { register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL) @@ -5227,7 +5236,7 @@ __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio * @param ADCx ADC instance * @retval Ratio This parameter can be in the from 1 to 1024. -*/ + */ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx) { return (((uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR))+(1UL << ADC_CFGR2_OVSR_Pos)) >> ADC_CFGR2_OVSR_Pos); @@ -5251,7 +5260,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_9 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_10 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_11 -*/ + */ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS)); @@ -6048,7 +6057,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx) } /** - * @brief Get ADC group regular conversion data, range fit for + * @brief Get ADC group injected conversion data, range fit for * all ADC configurations: all ADC resolutions and * all oversampling increased data width (for devices * with feature oversampling). diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_gpio.h b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_gpio.h index ea416fe01ac..4b67d6cd158 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_gpio.h +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_gpio.h @@ -713,6 +713,7 @@ __STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); WRITE_REG(GPIOx->LCKR, PinMask); WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + /* Read LCKK register. This read is mandatory to complete key lock sequence */ temp = READ_REG(GPIOx->LCKR); (void) temp; } diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_hrtim.c b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_hrtim.c index a2495d48bd4..47adce64495 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_hrtim.c +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_hrtim.c @@ -54,7 +54,7 @@ * - SUCCESS: HRTIMx registers are de-initialized * - ERROR: invalid HRTIMx instance */ -ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef* HRTIMx) +ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef *HRTIMx) { ErrorStatus result = SUCCESS; diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_hrtim.h b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_hrtim.h index 63ecbb7e66c..c24b53c5688 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_hrtim.h +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_hrtim.h @@ -220,18 +220,18 @@ static const uint8_t REG_SHIFT_TAB_FLTxE[] = HRTIM_CR1_TEUDIS)) #define HRTIM_CR2_SWUPD_MASK ((uint32_t)(HRTIM_CR2_MSWU |\ - HRTIM_CR2_TASWU |\ - HRTIM_CR2_TBSWU |\ - HRTIM_CR2_TCSWU |\ - HRTIM_CR2_TDSWU |\ - HRTIM_CR2_TESWU)) + HRTIM_CR2_TASWU |\ + HRTIM_CR2_TBSWU |\ + HRTIM_CR2_TCSWU |\ + HRTIM_CR2_TDSWU |\ + HRTIM_CR2_TESWU)) #define HRTIM_CR2_SWRST_MASK ((uint32_t)(HRTIM_CR2_MRST |\ - HRTIM_CR2_TARST |\ - HRTIM_CR2_TBRST |\ - HRTIM_CR2_TCRST |\ - HRTIM_CR2_TDRST |\ - HRTIM_CR2_TERST)) + HRTIM_CR2_TARST |\ + HRTIM_CR2_TBRST |\ + HRTIM_CR2_TCRST |\ + HRTIM_CR2_TDRST |\ + HRTIM_CR2_TERST)) #define HRTIM_OENR_OEN_MASK ((uint32_t)(HRTIM_OENR_TA1OEN |\ HRTIM_OENR_TA2OEN |\ @@ -281,16 +281,6 @@ static const uint8_t REG_SHIFT_TAB_FLTxE[] = /* Private macros ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup HRTIM_LL_ES_INIT HRTIM Exported Init structure - * @{ - */ -/* TO BE COMPLETED */ -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - /* Exported constants --------------------------------------------------------*/ /** @defgroup HRTIM_LL_Exported_Constants HRTIM Exported Constants * @{ @@ -964,8 +954,8 @@ static const uint8_t REG_SHIFT_TAB_FLTxE[] = #define LL_HRTIM_CHP_PRESCALER_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 240 */ #define LL_HRTIM_CHP_PRESCALER_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 256 */ /** - * @} - */ + * @} + */ /** @defgroup HRTIM_LL_EC_CHP_DUTYCYCLE CHOPPER MODE DUTY CYCLE * @{ @@ -1007,166 +997,42 @@ static const uint8_t REG_SHIFT_TAB_FLTxE[] = * @} */ -/** @defgroup HRTIM_LL_EC_OUTPUTSET_INPUT OUTPUTSET INPUT +/** @defgroup HRTIM_LL_EC_CROSSBAR_INPUT CROSSBAR INPUT * @{ * @brief Constants defining the events that can be selected to configure the set/reset crossbar of a timer output. */ -#define LL_HRTIM_OUTPUTSET_NONE 0x00000000U /*!< Reset the output set crossbar */ -#define LL_HRTIM_OUTPUTSET_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces an output level transision */ -#define LL_HRTIM_OUTPUTSET_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces an output level transision */ -#define LL_HRTIM_OUTPUTSET_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces an output level transision */ -#define LL_HRTIM_OUTPUTSET_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces an output level transision */ -#define LL_HRTIM_OUTPUTSET_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces an output level transision */ -#define LL_HRTIM_OUTPUTSET_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces an output level transision */ -#define LL_HRTIM_OUTPUTSET_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces an output level transision */ -#define LL_HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces an output level transision */ -#define LL_HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces an output level transision */ -#define LL_HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces an output level transision */ -#define LL_HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces an output level transision */ - -/* Timer Events mapping for Timer A */ -#define LL_HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its ictive state */ -#define LL_HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */ -#define LL_HRTIM_OUTPUTSET_TIMAEV3_TIMBCMP4 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */ -#define LL_HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP2 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */ -#define LL_HRTIM_OUTPUTSET_TIMAEV5_TIMCCMP3 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */ -#define LL_HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP1 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */ -#define LL_HRTIM_OUTPUTSET_TIMAEV7_TIMDCMP2 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */ -#define LL_HRTIM_OUTPUTSET_TIMAEV8_TIMECMP3 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */ -#define LL_HRTIM_OUTPUTSET_TIMAEV9_TIMECMP4 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */ -/* Timer Events mapping for Timer B */ -#define LL_HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */ -#define LL_HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */ -#define LL_HRTIM_OUTPUTSET_TIMBEV3_TIMACMP4 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */ -#define LL_HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP3 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */ -#define LL_HRTIM_OUTPUTSET_TIMBEV5_TIMCCMP4 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */ -#define LL_HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP3 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */ -#define LL_HRTIM_OUTPUTSET_TIMBEV7_TIMDCMP4 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */ -#define LL_HRTIM_OUTPUTSET_TIMBEV8_TIMECMP1 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */ -#define LL_HRTIM_OUTPUTSET_TIMBEV9_TIMECMP2 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */ -/* Timer Events mapping for Timer C */ -#define LL_HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */ -#define LL_HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */ -#define LL_HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */ -#define LL_HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */ -#define LL_HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */ -#define LL_HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */ -#define LL_HRTIM_OUTPUTSET_TIMCEV7_TIMECMP2 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */ -#define LL_HRTIM_OUTPUTSET_TIMCEV8_TIMECMP3 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */ -#define LL_HRTIM_OUTPUTSET_TIMCEV9_TIMECMP4 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */ -/* Timer Events mapping for Timer D */ -#define LL_HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */ -#define LL_HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */ -#define LL_HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */ -#define LL_HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */ -#define LL_HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP1 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */ -#define LL_HRTIM_OUTPUTSET_TIMDEV6_TIMCCMP3 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */ -#define LL_HRTIM_OUTPUTSET_TIMDEV7_TIMCCMP4 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */ -#define LL_HRTIM_OUTPUTSET_TIMDEV8_TIMECMP1 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */ -#define LL_HRTIM_OUTPUTSET_TIMDEV9_TIMECMP4 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */ -/* Timer Events mapping for Timer E */ -#define LL_HRTIM_OUTPUTSET_TIMEEV1_TIMACMP3 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */ -#define LL_HRTIM_OUTPUTSET_TIMEEV2_TIMACMP4 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */ -#define LL_HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */ -#define LL_HRTIM_OUTPUTSET_TIMEEV4_TIMBCMP4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */ -#define LL_HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP1 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */ -#define LL_HRTIM_OUTPUTSET_TIMEEV6_TIMCCMP2 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */ -#define LL_HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP1 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */ -#define LL_HRTIM_OUTPUTSET_TIMEEV8_TIMDCMP2 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */ -#define LL_HRTIM_OUTPUTSET_TIMEEV9_TIMDCMP4 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */ -#define LL_HRTIM_OUTPUTSET_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces an output level transision */ -#define LL_HRTIM_OUTPUTSET_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces an output level transision */ -#define LL_HRTIM_OUTPUTSET_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces an output level transision */ -#define LL_HRTIM_OUTPUTSET_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces an output level transision */ -#define LL_HRTIM_OUTPUTSET_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces an output level transision */ -#define LL_HRTIM_OUTPUTSET_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces an output level transision */ -#define LL_HRTIM_OUTPUTSET_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces an output level transision */ -#define LL_HRTIM_OUTPUTSET_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces an output level transision */ -#define LL_HRTIM_OUTPUTSET_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces an output level transision */ -#define LL_HRTIM_OUTPUTSET_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces an output level transision */ -#define LL_HRTIM_OUTPUTSET_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces an output level transision */ -/** - * @} - */ - -/** @defgroup HRTIM_Output_Reset_Source HRTIM Output Reset Source - * @{ - * @brief Constants defining the events that can be selected to configure the - * set crossbar of a timer output - */ -#define LL_HRTIM_OUTPUTRESET_NONE 0x00000000U /*!< Reset the output reset crossbar */ -#define LL_HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMPER (HRTIM_RST1R_PER) /*!< Timer period event forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMCMP1 (HRTIM_RST1R_CMP1) /*!< Timer compare 1 event forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMCMP2 (HRTIM_RST1R_CMP2) /*!< Timer compare 2 event forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMCMP3 (HRTIM_RST1R_CMP3) /*!< Timer compare 3 event forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMCMP4 (HRTIM_RST1R_CMP4) /*!< Timer compare 4 event forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_MASTERPER (HRTIM_RST1R_MSTPER) /*!< The master timer period event forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its inactive state */ -/* Timer Events mapping for Timer A */ -#define LL_HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMAEV3_TIMBCMP4 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP2 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMAEV5_TIMCCMP3 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP1 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMAEV7_TIMDCMP2 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP3 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMAEV9_TIMECMP4 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */ -/* Timer Events mapping for Timer B */ -#define LL_HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMBEV3_TIMACMP4 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP3 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMBEV5_TIMCCMP4 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP3 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMBEV7_TIMDCMP4 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP1 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMBEV9_TIMECMP2 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */ -/* Timer Events mapping for Timer C */ -#define LL_HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP2 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP3 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMCEV9_TIMECMP4 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */ -/* Timer Events mapping for Timer D */ -#define LL_HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP1 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMDEV6_TIMCCMP3 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMDEV7_TIMCCMP4 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMDEV8_TIMECMP1 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMDEV9_TIMECMP4 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */ -/* Timer Events mapping for Timer E */ -#define LL_HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP3 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMEEV2_TIMACMP4 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP3 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMEEV4_TIMBCMP4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP1 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMEEV6_TIMCCMP2 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP1 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMEEV8_TIMDCMP2 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_TIMEEV9_TIMDCMP4 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1) /*!< External event 1 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2) /*!< External event 2 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3) /*!< External event 3 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_EEV_4 (HRTIM_RST1R_EXTVNT4) /*!< External event 4 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_EEV_5 (HRTIM_RST1R_EXTVNT5) /*!< External event 5 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_EEV_6 (HRTIM_RST1R_EXTVNT6) /*!< External event 6 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_EEV_7 (HRTIM_RST1R_EXTVNT7) /*!< External event 7 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_EEV_8 (HRTIM_RST1R_EXTVNT8) /*!< External event 8 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_EEV_9 (HRTIM_RST1R_EXTVNT9) /*!< External event 9 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_EEV_10 (HRTIM_RST1R_EXTVNT10) /*!< External event 10 forces the output to its inactive state */ -#define LL_HRTIM_OUTPUTRESET_UPDATE (HRTIM_RST1R_UPDATE) /*!< Timer register update event forces the output to its inactive state */ +#define LL_HRTIM_CROSSBAR_NONE 0x00000000U /*!< Reset the output set crossbar */ +#define LL_HRTIM_CROSSBAR_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces an output level transision */ +#define LL_HRTIM_CROSSBAR_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces an output level transision */ +#define LL_HRTIM_CROSSBAR_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces an output level transision */ +#define LL_HRTIM_CROSSBAR_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces an output level transision */ +#define LL_HRTIM_CROSSBAR_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces an output level transision */ +#define LL_HRTIM_CROSSBAR_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces an output level transision */ +#define LL_HRTIM_CROSSBAR_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces an output level transision */ +#define LL_HRTIM_CROSSBAR_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces an output level transision */ +#define LL_HRTIM_CROSSBAR_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces an output level transision */ +#define LL_HRTIM_CROSSBAR_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces an output level transision */ +#define LL_HRTIM_CROSSBAR_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces an output level transision */ +#define LL_HRTIM_CROSSBAR_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces an output level transision */ +#define LL_HRTIM_CROSSBAR_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces an output level transision */ +#define LL_HRTIM_CROSSBAR_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces an output level transision */ +#define LL_HRTIM_CROSSBAR_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces an output level transision */ +#define LL_HRTIM_CROSSBAR_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces an output level transision */ +#define LL_HRTIM_CROSSBAR_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces an output level transision */ +#define LL_HRTIM_CROSSBAR_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces an output level transision */ +#define LL_HRTIM_CROSSBAR_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces an output level transision */ +#define LL_HRTIM_CROSSBAR_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces an output level transision */ +#define LL_HRTIM_CROSSBAR_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces an output level transision */ +#define LL_HRTIM_CROSSBAR_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces an output level transision */ +#define LL_HRTIM_CROSSBAR_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces an output level transision */ +#define LL_HRTIM_CROSSBAR_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces an output level transision */ +#define LL_HRTIM_CROSSBAR_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces an output level transision */ +#define LL_HRTIM_CROSSBAR_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces an output level transision */ +#define LL_HRTIM_CROSSBAR_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces an output level transision */ +#define LL_HRTIM_CROSSBAR_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces an output level transision */ +#define LL_HRTIM_CROSSBAR_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces an output level transision */ +#define LL_HRTIM_CROSSBAR_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces an output level transision */ +#define LL_HRTIM_CROSSBAR_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces an output level transision */ /** * @} */ @@ -1188,8 +1054,8 @@ static const uint8_t REG_SHIFT_TAB_FLTxE[] = #define LL_HRTIM_OUT_NO_IDLE 0x00000000U /*!< The output is not affected by the burst mode operation */ #define LL_HRTIM_OUT_IDLE_WHEN_BURST (HRTIM_OUTR_IDLM1) /*!< The output is in idle state when requested by the burst mode controller */ /** - * @} - */ + * @} + */ /** @defgroup HRTIM_LL_EC_HALF_MODE HALF MODE * @{ @@ -1212,9 +1078,9 @@ static const uint8_t REG_SHIFT_TAB_FLTxE[] = */ /** @defgroup HRTIM_LL_EC_OUT_FAULTSTATE OUTPUT FAULT STATE - * @{ - * @brief Constants defining the output level when output is in FAULT state. - */ + * @{ + * @brief Constants defining the output level when output is in FAULT state. + */ #define LL_HRTIM_OUT_FAULTSTATE_NO_ACTION 0x00000000U /*!< The output is not affected by the fault input */ #define LL_HRTIM_OUT_FAULTSTATE_ACTIVE (HRTIM_OUTR_FAULT1_0) /*!< Output at active level when in FAULT state */ #define LL_HRTIM_OUT_FAULTSTATE_INACTIVE (HRTIM_OUTR_FAULT1_1) /*!< Output at inactive level when in FAULT state */ @@ -1534,7 +1400,7 @@ during a programmable period before the output takes its idle state. * @arg @ref LL_HRTIM_OUTPUTSTATE_IDLE * @arg @ref LL_HRTIM_OUTPUTSTATE_RUN * @arg @ref LL_HRTIM_OUTPUTSTATE_FAULT -*/ + */ #define __LL_HRTIM_GET_OUTPUT_STATE(__OUTPUT_STATUS_EN__, __OUTPUT_STATUS_DIS__)\ (((__OUTPUT_STATUS_EN__) == 1) ? LL_HRTIM_OUTPUTSTATE_RUN :\ ((__OUTPUT_STATUS_DIS__) == 0) ? LL_HRTIM_OUTPUTSTATE_IDLE : LL_HRTIM_OUTPUTSTATE_FAULT) @@ -2110,9 +1976,9 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsDisabledOutput(HRTIM_TypeDef *HRTIMx, uint32 */ __STATIC_INLINE void LL_HRTIM_ConfigADCTrig(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update, uint32_t Src) { - register uint32_t shift = ((3U * ADCTrig)& 0x1FU); + register uint32_t shift = ((3U * ADCTrig) & 0x1FU); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + - REG_OFFSET_TAB_ADCxR[ADCTrig])); + REG_OFFSET_TAB_ADCxR[ADCTrig])); MODIFY_REG(HRTIMx->sCommonRegs.CR1, (HRTIM_CR1_ADC1USRC << shift), (Update << shift)); WRITE_REG(*pReg, Src); } @@ -2169,8 +2035,8 @@ __STATIC_INLINE void LL_HRTIM_SetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t A */ __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig) { - register uint32_t shift = ((3U * ADCTrig) & 0x1FU); - return (READ_BIT(HRTIMx->sCommonRegs.CR1, (uint32_t)(HRTIM_CR1_ADC1USRC) << shift ) >> shift); + register const uint32_t shift = ((3U * ADCTrig) & 0x1FU); + return (READ_BIT(HRTIMx->sCommonRegs.CR1, (uint32_t)(HRTIM_CR1_ADC1USRC) << shift) >> shift); } /** @@ -2382,12 +2248,12 @@ __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST * -* @retval None + * @retval None */ __STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Src) { register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + - REG_OFFSET_TAB_ADCxR[ADCTrig])); + REG_OFFSET_TAB_ADCxR[ADCTrig])); WRITE_REG(*pReg, Src); } @@ -2604,7 +2470,7 @@ __STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCT __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig) { register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + - REG_OFFSET_TAB_ADCxR[ADCTrig])); + REG_OFFSET_TAB_ADCxR[ADCTrig])); return (*pReg); } @@ -3164,7 +3030,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t * TIMxCR TDU LL_HRTIM_TIM_GetUpdateTrig\n * TIMxCR TEU LL_HRTIM_TIM_GetUpdateTrig\n * TIMxCR MSTU LL_HRTIM_TIM_GetUpdateTrig - * @param HRTIMx High Resolution Timer instance + * @param HRTIMx High Resolution Timer instance * @param Timer This parameter can be one of the following values: * @arg @ref LL_HRTIM_TIMER_MASTER * @arg @ref LL_HRTIM_TIMER_A @@ -3288,7 +3154,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnablePushPullMode(HRTIM_TypeDef *HRTIMx, uint { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMCR_PSHPLL); } @@ -3308,7 +3174,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisablePushPullMode(HRTIM_TypeDef *HRTIMx, uin { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_TIMCR_PSHPLL); } @@ -3328,7 +3194,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(HRTIM_TypeDef *HRTIM { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMCR_PSHPLL) == (HRTIM_TIMCR_PSHPLL)) ? 1UL : 0UL); } @@ -3359,7 +3225,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); register uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU); MODIFY_REG(* pReg, (HRTIM_TIMCR_DELCMP2 << shift), (Mode << shift)); } @@ -3388,7 +3254,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(HRTIM_TypeDef *HRTIMx, uint { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); register uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU); return (READ_BIT(*pReg, (HRTIM_TIMCR_DELCMP2 << shift)) >> shift); } @@ -3418,7 +3284,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Tim { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCNTR_MCNTR, Counter); } @@ -3440,7 +3306,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounter(HRTIM_TypeDef *HRTIMx, uint32_t { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCNTR_MCNTR)); } @@ -3463,7 +3329,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Time { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MPER_MPER, Period); } @@ -3485,7 +3351,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MPER_MPER)); } @@ -3508,7 +3374,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MREP_MREP, Repetition); } @@ -3530,7 +3396,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRepetition(HRTIM_TypeDef *HRTIMx, uint3 { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MREP_MREP)); } @@ -3555,7 +3421,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Ti { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP1R, CompareValue); } @@ -3579,7 +3445,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare1(HRTIM_TypeDef *HRTIMx, uint32_ { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP1R)); } @@ -3604,7 +3470,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Ti { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP2R, CompareValue); } @@ -3628,7 +3494,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare2(HRTIM_TypeDef *HRTIMx, uint32_ { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP2R)); } @@ -3653,7 +3519,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Ti { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP3R, CompareValue); } @@ -3677,7 +3543,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare3(HRTIM_TypeDef *HRTIMx, uint32_ { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP3R)); } @@ -3702,7 +3568,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Ti { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP4R, CompareValue); } @@ -3726,7 +3592,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare4(HRTIM_TypeDef *HRTIMx, uint32_ { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP4R)); } @@ -3813,7 +3679,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t T { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); WRITE_REG(*pReg, ResetTrig); } @@ -3893,7 +3759,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(HRTIM_TypeDef *HRTIMx, uint32 { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_REG(*pReg)); } @@ -3913,7 +3779,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(HRTIM_TypeDef *HRTIMx, uint32_ { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_REG(*pReg)); } @@ -3933,7 +3799,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2(HRTIM_TypeDef *HRTIMx, uint32_ { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_REG(*pReg)); } @@ -4021,7 +3887,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) + - REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U))); + REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U))); WRITE_REG(*pReg, CaptureTrig); } @@ -4107,7 +3973,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) + - REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U))); + REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U))); return (READ_REG(*pReg)); } @@ -4127,7 +3993,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_OUTR_DTEN); } @@ -4147,7 +4013,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_ { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_OUTR_DTEN); } @@ -4167,7 +4033,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDeadTime(HRTIM_TypeDef *HRTIMx, u { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_OUTR_DTEN) == (HRTIM_OUTR_DTEN)) ? 1UL : 0UL); } @@ -4212,7 +4078,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_OUTR_DLYPRT, DLYPRTMode); } @@ -4253,7 +4119,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint3 { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_OUTR_DLYPRT)); } @@ -4274,7 +4140,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t T { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_OUTR_DLYPRTEN); } @@ -4295,7 +4161,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, HRTIM_OUTR_DLYPRTEN); } @@ -4315,7 +4181,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDLYPRT(HRTIM_TypeDef *HRTIMx, uin { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_OUTR_DLYPRTEN) == (HRTIM_OUTR_DLYPRTEN)) ? 1UL : 0UL); } @@ -4345,7 +4211,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef *HRTIMx, uint32_t Ti { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, Faults); } @@ -4375,7 +4241,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef *HRTIMx, uint32_t T { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); CLEAR_BIT(*pReg, Faults); } @@ -4405,7 +4271,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(HRTIM_TypeDef *HRTIMx, uint { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, Fault) == (Fault)) ? 1UL : 0UL); } @@ -4427,7 +4293,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_LockFault(HRTIM_TypeDef *HRTIMx, uint32_t Time { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_FLTR_FLTLCK); } @@ -4592,7 +4458,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(HRTIM_TypeDef *HR { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMISR_CPPSTAT)); } @@ -4614,7 +4480,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetIdlePushPullStatus(HRTIM_TypeDef *HRTIM { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_TIMISR_IPPSTAT)); } @@ -4674,7 +4540,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + - REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1FLTR << REG_SHIFT_TAB_EExSRC[iEvent]), (Filter << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -4731,8 +4597,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventFilter(HRTIM_TypeDef *HRTIMx, uint register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + - REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); - return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1FLTR) << (REG_SHIFT_TAB_EExSRC[iEvent] )) >> (REG_SHIFT_TAB_EExSRC[iEvent] )); + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); + return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1FLTR) << (REG_SHIFT_TAB_EExSRC[iEvent])) >> (REG_SHIFT_TAB_EExSRC[iEvent])); } /** @@ -4777,7 +4643,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uin register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + - REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1LTCH << REG_SHIFT_TAB_EExSRC[iEvent]), (LatchStatus << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -4820,8 +4686,8 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(HRTIM_TypeDef *HRTIMx, register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + - REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); - return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1LTCH) << REG_SHIFT_TAB_EExSRC[iEvent]) >> (REG_SHIFT_TAB_EExSRC[iEvent] )); + REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); + return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1LTCH) << REG_SHIFT_TAB_EExSRC[iEvent]) >> (REG_SHIFT_TAB_EExSRC[iEvent])); } /** @@ -4854,7 +4720,7 @@ __STATIC_INLINE void LL_HRTIM_DT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, u { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_SDTF | HRTIM_DTR_DTPRSC | HRTIM_DTR_SDTR, Configuration); } @@ -4883,7 +4749,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Ti { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_DTPRSC, Prescaler); } @@ -4911,7 +4777,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_ { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_DTPRSC)); } @@ -4932,7 +4798,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_DTR, RisingValue); } @@ -4952,7 +4818,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingValue(HRTIM_TypeDef *HRTIMx, uint3 { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_DTR)); } @@ -4975,7 +4841,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t T { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_SDTR, RisingSign); } @@ -4997,7 +4863,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingSign(HRTIM_TypeDef *HRTIMx, uint32 { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_SDTR)); } @@ -5018,7 +4884,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_DTF, FallingValue << HRTIM_DTR_DTF_Pos); } @@ -5038,7 +4904,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingValue(HRTIM_TypeDef *HRTIMx, uint { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_DTR_DTF)) >> HRTIM_DTR_DTF_Pos); } @@ -5061,7 +4927,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_DTR_SDTF, FallingSign); } @@ -5083,7 +4949,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(HRTIM_TypeDef *HRTIMx, uint3 { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_DTR_SDTF)); } @@ -5103,7 +4969,7 @@ __STATIC_INLINE void LL_HRTIM_DT_LockRising(HRTIM_TypeDef *HRTIMx, uint32_t Time { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTRLK); } @@ -5123,7 +4989,7 @@ __STATIC_INLINE void LL_HRTIM_DT_LockRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTRSLK); } @@ -5143,7 +5009,7 @@ __STATIC_INLINE void LL_HRTIM_DT_LockFalling(HRTIM_TypeDef *HRTIMx, uint32_t Tim { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTFLK); } @@ -5163,7 +5029,7 @@ __STATIC_INLINE void LL_HRTIM_DT_LockFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_DTR_DTFSLK); } @@ -5199,7 +5065,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_STRPW | HRTIM_CHPR_CARDTY | HRTIM_CHPR_CARFRQ, Configuration); } @@ -5239,7 +5105,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t T { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_CARFRQ, Prescaler); } @@ -5275,7 +5141,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32 { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_CHPR_CARFRQ)); } @@ -5307,7 +5173,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t T { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_CARDTY, DutyCycle); } @@ -5335,7 +5201,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32 { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_CHPR_CARDTY)); } @@ -5374,7 +5240,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); MODIFY_REG(*pReg, HRTIM_CHPR_STRPW, PulseWidth); } @@ -5410,7 +5276,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(HRTIM_TypeDef *HRTIMx, uint3 { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return (READ_BIT(*pReg, HRTIM_CHPR_STRPW)); } @@ -5501,82 +5367,45 @@ __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(HRTIM_TypeDef *HRTIMx, uint3 * @arg @ref LL_HRTIM_OUTPUT_TE1 * @arg @ref LL_HRTIM_OUTPUT_TE2 * @param SetSrc This parameter can be a combination of the following values: - * @arg @ref LL_HRTIM_OUTPUTSET_NONE - * @arg @ref LL_HRTIM_OUTPUTSET_RESYNC - * @arg @ref LL_HRTIM_OUTPUTSET_TIMPER - * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP1 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP2 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_MASTERPER - * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP1 - * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP2 - * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV3_TIMBCMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP2 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV5_TIMCCMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP1 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV7_TIMDCMP2 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV8_TIMECMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV9_TIMECMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV3_TIMACMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV5_TIMCCMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV7_TIMDCMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV8_TIMECMP1 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV9_TIMECMP2 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV7_TIMECMP2 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV8_TIMECMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV9_TIMECMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP1 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV6_TIMCCMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV7_TIMCCMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV8_TIMECMP1 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV9_TIMECMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV1_TIMACMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV2_TIMACMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV4_TIMBCMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP1 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV6_TIMCCMP2 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP1 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV8_TIMDCMP2 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV9_TIMDCMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_EEV_1 - * @arg @ref LL_HRTIM_OUTPUTSET_EEV_2 - * @arg @ref LL_HRTIM_OUTPUTSET_EEV_3 - * @arg @ref LL_HRTIM_OUTPUTSET_EEV_4 - * @arg @ref LL_HRTIM_OUTPUTSET_EEV_5 - * @arg @ref LL_HRTIM_OUTPUTSET_EEV_6 - * @arg @ref LL_HRTIM_OUTPUTSET_EEV_7 - * @arg @ref LL_HRTIM_OUTPUTSET_EEV_8 - * @arg @ref LL_HRTIM_OUTPUTSET_EEV_9 - * @arg @ref LL_HRTIM_OUTPUTSET_EEV_10 - * @arg @ref LL_HRTIM_OUTPUTSET_UPDATE - * (source = TIMy and destination = TIMx, Compare Unit = CMPz). + * @arg @ref LL_HRTIM_CROSSBAR_NONE + * @arg @ref LL_HRTIM_CROSSBAR_RESYNC + * @arg @ref LL_HRTIM_CROSSBAR_TIMPER + * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1 + * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2 + * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3 + * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4 + * @arg @ref LL_HRTIM_CROSSBAR_MASTERPER + * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1 + * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2 + * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3 + * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4 + * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1 + * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2 + * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3 + * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4 + * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5 + * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6 + * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7 + * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8 + * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9 + * @arg @ref LL_HRTIM_CROSSBAR_EEV_1 + * @arg @ref LL_HRTIM_CROSSBAR_EEV_2 + * @arg @ref LL_HRTIM_CROSSBAR_EEV_3 + * @arg @ref LL_HRTIM_CROSSBAR_EEV_4 + * @arg @ref LL_HRTIM_CROSSBAR_EEV_5 + * @arg @ref LL_HRTIM_CROSSBAR_EEV_6 + * @arg @ref LL_HRTIM_CROSSBAR_EEV_7 + * @arg @ref LL_HRTIM_CROSSBAR_EEV_8 + * @arg @ref LL_HRTIM_CROSSBAR_EEV_9 + * @arg @ref LL_HRTIM_CROSSBAR_EEV_10 + * @arg @ref LL_HRTIM_CROSSBAR_UPDATE * @retval None */ __STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t SetSrc) { register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + - REG_OFFSET_TAB_SETxR[iOutput])); + REG_OFFSET_TAB_SETxR[iOutput])); WRITE_REG(*pReg, SetSrc); } @@ -5659,81 +5488,44 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_ * @arg @ref LL_HRTIM_OUTPUT_TE1 * @arg @ref LL_HRTIM_OUTPUT_TE2 * @retval SetSrc This parameter can be a combination of the following values: - * @arg @ref LL_HRTIM_OUTPUTSET_NONE - * @arg @ref LL_HRTIM_OUTPUTSET_RESYNC - * @arg @ref LL_HRTIM_OUTPUTSET_TIMPER - * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP1 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP2 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_MASTERPER - * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP1 - * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP2 - * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV3_TIMBCMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP2 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV5_TIMCCMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP1 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV7_TIMDCMP2 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV8_TIMECMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV9_TIMECMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV3_TIMACMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV5_TIMCCMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV7_TIMDCMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV8_TIMECMP1 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV9_TIMECMP2 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV7_TIMECMP2 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV8_TIMECMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV9_TIMECMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP1 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV6_TIMCCMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV7_TIMCCMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV8_TIMECMP1 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV9_TIMECMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV1_TIMACMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV2_TIMACMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP3 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV4_TIMBCMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP1 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV6_TIMCCMP2 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP1 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV8_TIMDCMP2 - * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV9_TIMDCMP4 - * @arg @ref LL_HRTIM_OUTPUTSET_EEV_1 - * @arg @ref LL_HRTIM_OUTPUTSET_EEV_2 - * @arg @ref LL_HRTIM_OUTPUTSET_EEV_3 - * @arg @ref LL_HRTIM_OUTPUTSET_EEV_4 - * @arg @ref LL_HRTIM_OUTPUTSET_EEV_5 - * @arg @ref LL_HRTIM_OUTPUTSET_EEV_6 - * @arg @ref LL_HRTIM_OUTPUTSET_EEV_7 - * @arg @ref LL_HRTIM_OUTPUTSET_EEV_8 - * @arg @ref LL_HRTIM_OUTPUTSET_EEV_9 - * @arg @ref LL_HRTIM_OUTPUTSET_EEV_10 - * @arg @ref LL_HRTIM_OUTPUTSET_UPDATE - * (source = TIMy and destination = TIMx, Compare Unit = CMPz). + * @arg @ref LL_HRTIM_CROSSBAR_NONE + * @arg @ref LL_HRTIM_CROSSBAR_RESYNC + * @arg @ref LL_HRTIM_CROSSBAR_TIMPER + * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1 + * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2 + * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3 + * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4 + * @arg @ref LL_HRTIM_CROSSBAR_MASTERPER + * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1 + * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2 + * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3 + * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4 + * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1 + * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2 + * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3 + * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4 + * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5 + * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6 + * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7 + * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8 + * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9 + * @arg @ref LL_HRTIM_CROSSBAR_EEV_1 + * @arg @ref LL_HRTIM_CROSSBAR_EEV_2 + * @arg @ref LL_HRTIM_CROSSBAR_EEV_3 + * @arg @ref LL_HRTIM_CROSSBAR_EEV_4 + * @arg @ref LL_HRTIM_CROSSBAR_EEV_5 + * @arg @ref LL_HRTIM_CROSSBAR_EEV_6 + * @arg @ref LL_HRTIM_CROSSBAR_EEV_7 + * @arg @ref LL_HRTIM_CROSSBAR_EEV_8 + * @arg @ref LL_HRTIM_CROSSBAR_EEV_9 + * @arg @ref LL_HRTIM_CROSSBAR_EEV_10 + * @arg @ref LL_HRTIM_CROSSBAR_UPDATE */ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output) { register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + - REG_OFFSET_TAB_SETxR[iOutput])); + REG_OFFSET_TAB_SETxR[iOutput])); return (uint32_t) READ_REG(*pReg); } @@ -5816,82 +5608,45 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uin * @arg @ref LL_HRTIM_OUTPUT_TE1 * @arg @ref LL_HRTIM_OUTPUT_TE2 * @param ResetSrc This parameter can be a combination of the following values: - * @arg @ref LL_HRTIM_OUTPUTRESET_NONE - * @arg @ref LL_HRTIM_OUTPUTRESET_RESYNC - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMPER - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP1 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP2 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERPER - * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP1 - * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP2 - * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV3_TIMBCMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP2 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV5_TIMCCMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP1 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV7_TIMDCMP2 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV9_TIMECMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV3_TIMACMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV5_TIMCCMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV7_TIMDCMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP1 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV9_TIMECMP2 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP2 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV9_TIMECMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP1 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV6_TIMCCMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV7_TIMCCMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV8_TIMECMP1 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV9_TIMECMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV2_TIMACMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV4_TIMBCMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP1 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV6_TIMCCMP2 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP1 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV8_TIMDCMP2 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV9_TIMDCMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_1 - * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_2 - * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_3 - * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_4 - * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_5 - * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_6 - * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_7 - * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_8 - * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_9 - * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_10 - * @arg @ref LL_HRTIM_OUTPUTRESET_UPDATE - * (source = TIMy and destination = TIMx, Compare Unit = CMPz). + * @arg @ref LL_HRTIM_CROSSBAR_NONE + * @arg @ref LL_HRTIM_CROSSBAR_RESYNC + * @arg @ref LL_HRTIM_CROSSBAR_TIMPER + * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1 + * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2 + * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3 + * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4 + * @arg @ref LL_HRTIM_CROSSBAR_MASTERPER + * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1 + * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2 + * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3 + * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4 + * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1 + * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2 + * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3 + * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4 + * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5 + * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6 + * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7 + * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8 + * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9 + * @arg @ref LL_HRTIM_CROSSBAR_EEV_1 + * @arg @ref LL_HRTIM_CROSSBAR_EEV_2 + * @arg @ref LL_HRTIM_CROSSBAR_EEV_3 + * @arg @ref LL_HRTIM_CROSSBAR_EEV_4 + * @arg @ref LL_HRTIM_CROSSBAR_EEV_5 + * @arg @ref LL_HRTIM_CROSSBAR_EEV_6 + * @arg @ref LL_HRTIM_CROSSBAR_EEV_7 + * @arg @ref LL_HRTIM_CROSSBAR_EEV_8 + * @arg @ref LL_HRTIM_CROSSBAR_EEV_9 + * @arg @ref LL_HRTIM_CROSSBAR_EEV_10 + * @arg @ref LL_HRTIM_CROSSBAR_UPDATE * @retval None */ __STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ResetSrc) { register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) + - REG_OFFSET_TAB_SETxR[iOutput])); + REG_OFFSET_TAB_SETxR[iOutput])); WRITE_REG(*pReg, ResetSrc); } @@ -5974,81 +5729,44 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint3 * @arg @ref LL_HRTIM_OUTPUT_TE1 * @arg @ref LL_HRTIM_OUTPUT_TE2 * @retval ResetSrc This parameter can be a combination of the following values: - * @arg @ref LL_HRTIM_OUTPUTRESET_NONE - * @arg @ref LL_HRTIM_OUTPUTRESET_RESYNC - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMPER - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP1 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP2 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERPER - * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP1 - * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP2 - * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV3_TIMBCMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP2 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV5_TIMCCMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP1 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV7_TIMDCMP2 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV9_TIMECMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV3_TIMACMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV5_TIMCCMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV7_TIMDCMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP1 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV9_TIMECMP2 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP2 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV9_TIMECMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP1 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV6_TIMCCMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV7_TIMCCMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV8_TIMECMP1 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV9_TIMECMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV2_TIMACMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP3 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV4_TIMBCMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP1 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV6_TIMCCMP2 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP1 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV8_TIMDCMP2 - * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV9_TIMDCMP4 - * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_1 - * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_2 - * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_3 - * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_4 - * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_5 - * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_6 - * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_7 - * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_8 - * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_9 - * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_10 - * @arg @ref LL_HRTIM_OUTPUTRESET_UPDATE - * (source = TIMy and destination = TIMx, Compare Unit = CMPz). + * @arg @ref LL_HRTIM_CROSSBAR_NONE + * @arg @ref LL_HRTIM_CROSSBAR_RESYNC + * @arg @ref LL_HRTIM_CROSSBAR_TIMPER + * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1 + * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2 + * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3 + * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4 + * @arg @ref LL_HRTIM_CROSSBAR_MASTERPER + * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1 + * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2 + * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3 + * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4 + * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1 + * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2 + * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3 + * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4 + * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5 + * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6 + * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7 + * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8 + * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9 + * @arg @ref LL_HRTIM_CROSSBAR_EEV_1 + * @arg @ref LL_HRTIM_CROSSBAR_EEV_2 + * @arg @ref LL_HRTIM_CROSSBAR_EEV_3 + * @arg @ref LL_HRTIM_CROSSBAR_EEV_4 + * @arg @ref LL_HRTIM_CROSSBAR_EEV_5 + * @arg @ref LL_HRTIM_CROSSBAR_EEV_6 + * @arg @ref LL_HRTIM_CROSSBAR_EEV_7 + * @arg @ref LL_HRTIM_CROSSBAR_EEV_8 + * @arg @ref LL_HRTIM_CROSSBAR_EEV_9 + * @arg @ref LL_HRTIM_CROSSBAR_EEV_10 + * @arg @ref LL_HRTIM_CROSSBAR_UPDATE */ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output) { register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) + - REG_OFFSET_TAB_SETxR[iOutput])); + REG_OFFSET_TAB_SETxR[iOutput])); return (uint32_t) READ_REG(*pReg); } @@ -6091,7 +5809,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Output, { register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUT_CONFIG_MASK << REG_SHIFT_TAB_OUTxR[iOutput]), (Configuration << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -6121,7 +5839,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Ou { register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_POL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (Polarity << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -6149,7 +5867,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_ { register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_POL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -6179,8 +5897,8 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Ou { register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); - MODIFY_REG(*pReg, (HRTIM_OUTR_IDLM1 << (REG_SHIFT_TAB_OUTxR[iOutput] )), (IdleMode << (REG_SHIFT_TAB_OUTxR[iOutput] ))); + REG_OFFSET_TAB_OUTxR[iOutput])); + MODIFY_REG(*pReg, (HRTIM_OUTR_IDLM1 << (REG_SHIFT_TAB_OUTxR[iOutput])), (IdleMode << (REG_SHIFT_TAB_OUTxR[iOutput]))); } /** @@ -6207,7 +5925,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_ { register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLM1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -6238,7 +5956,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t O { register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_IDLES1 << REG_SHIFT_TAB_OUTxR[iOutput]), (IdleLevel << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -6266,7 +5984,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32 { register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLES1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -6299,7 +6017,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t { register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_FAULT1 << REG_SHIFT_TAB_OUTxR[iOutput]), (FaultState << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -6329,7 +6047,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetFaultState(HRTIM_TypeDef *HRTIMx, uint3 { register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_FAULT1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -6359,7 +6077,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t { register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_CHP1 << REG_SHIFT_TAB_OUTxR[iOutput]), (ChopperMode << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -6387,7 +6105,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetChopperMode(HRTIM_TypeDef *HRTIMx, uint { register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_CHP1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -6417,7 +6135,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t { register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); MODIFY_REG(*pReg, (HRTIM_OUTR_DIDL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (BMEntryMode << REG_SHIFT_TAB_OUTxR[iOutput])); } @@ -6445,7 +6163,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint { register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_DIDL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); } @@ -6474,7 +6192,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetDLYPRTOutStatus(HRTIM_TypeDef *HRTIMx, { register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1STAT) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >> HRTIM_TIMISR_O1STAT_Pos); } @@ -6512,7 +6230,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef *HRTIMx, uint32_t Out register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + - REG_OFFSET_TAB_SETxR[iOutput] + REG_OFFSET_TAB_OUT_LEVEL[OutputLevel])); + REG_OFFSET_TAB_SETxR[iOutput] + REG_OFFSET_TAB_OUT_LEVEL[OutputLevel])); SET_BIT(*pReg, HRTIM_SET1R_SST); } @@ -6540,7 +6258,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(HRTIM_TypeDef *HRTIMx, uint32_t O { register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) + - REG_OFFSET_TAB_OUTxR[iOutput])); + REG_OFFSET_TAB_OUTxR[iOutput])); return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1CPY) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >> HRTIM_TIMISR_O1CPY_Pos); } @@ -6611,7 +6329,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(HRTIM_TypeDef *HRTIMx, uint32_t O * @arg @ref LL_HRTIM_EVENT_9 * @arg @ref LL_HRTIM_EVENT_10 * @param Configuration This parameter must be a combination of all the following values: - * @arg @ref LL_HRTIM_EE_SRC_1 or @ref LL_HRTIM_EE_SRC_2 or @ref LL_HRTIM_EE_SRC_3 or @ref LL_HRTIM_EE_SRC_4 + * @arg External event source 1 or External event source 2 or External event source 3 or External event source 4 * @arg @ref LL_HRTIM_EE_POLARITY_HIGH or @ref LL_HRTIM_EE_POLARITY_LOW * @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL or @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE or @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE or @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES * @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE or @ref LL_HRTIM_EE_FASTMODE_ENABLE @@ -6621,7 +6339,7 @@ __STATIC_INLINE void LL_HRTIM_EE_Config(HRTIM_TypeDef *HRTIMx, uint32_t Event, u { register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EE_CONFIG_MASK << REG_SHIFT_TAB_EExSRC[iEvent]), (Configuration << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6651,17 +6369,17 @@ __STATIC_INLINE void LL_HRTIM_EE_Config(HRTIM_TypeDef *HRTIMx, uint32_t Event, u * @arg @ref LL_HRTIM_EVENT_9 * @arg @ref LL_HRTIM_EVENT_10 * @param Src This parameter can be one of the following values: - * @arg @ref LL_HRTIM_EE_SRC_1 - * @arg @ref LL_HRTIM_EE_SRC_2 - * @arg @ref LL_HRTIM_EE_SRC_3 - * @arg @ref LL_HRTIM_EE_SRC_4 + * @arg External event source 1 + * @arg External event source 2 + * @arg External event source 3 + * @arg External event source 4 * @retval None */ __STATIC_INLINE void LL_HRTIM_EE_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Src) { register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SRC << REG_SHIFT_TAB_EExSRC[iEvent]), (Src << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6690,16 +6408,16 @@ __STATIC_INLINE void LL_HRTIM_EE_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event, u * @arg @ref LL_HRTIM_EVENT_9 * @arg @ref LL_HRTIM_EVENT_10 * @retval EventSrc This parameter can be one of the following values: - * @arg @ref LL_HRTIM_EE_SRC_1 - * @arg @ref LL_HRTIM_EE_SRC_2 - * @arg @ref LL_HRTIM_EE_SRC_3 - * @arg @ref LL_HRTIM_EE_SRC_4 + * @arg External event source 1 + * @arg External event source 2 + * @arg External event source 3 + * @arg External event source 4 */ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event) { register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SRC) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -6738,7 +6456,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Eve { register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EECR1_EE1POL << REG_SHIFT_TAB_EExSRC[iEvent]), (Polarity << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6774,7 +6492,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t { register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1POL) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -6814,7 +6532,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t { register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SNS << REG_SHIFT_TAB_EExSRC[iEvent]), (Sensitivity << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6852,7 +6570,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSensitivity(HRTIM_TypeDef *HRTIMx, uint3 { register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SNS) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -6885,7 +6603,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Eve { register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); MODIFY_REG(*pReg, (HRTIM_EECR1_EE1FAST << REG_SHIFT_TAB_EExSRC[iEvent]), (FastMode << REG_SHIFT_TAB_EExSRC[iEvent])); } @@ -6916,7 +6634,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_EE_GetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t { register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + - REG_OFFSET_TAB_EECR[iEvent])); + REG_OFFSET_TAB_EECR[iEvent])); return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1FAST) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); } @@ -7068,7 +6786,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Fault, { register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); MODIFY_REG(*pReg, (HRTIM_FLT_CONFIG_MASK << REG_SHIFT_TAB_FLTxE[iFault]), (Configuration << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -7097,7 +6815,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, { register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1SRC << REG_SHIFT_TAB_FLTxE[iFault]), (Src << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -7123,7 +6841,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fau { register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1SRC << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]); } @@ -7151,7 +6869,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fa { register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1P << REG_SHIFT_TAB_FLTxE[iFault]), (Polarity << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -7161,7 +6879,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fa * FLTINR1 FLT2P LL_HRTIM_FLT_GetPolarity\n * FLTINR1 FLT3P LL_HRTIM_FLT_GetPolarity\n * FLTINR1 FLT4P LL_HRTIM_FLT_GetPolarity\n - * FLTINR2 FLT5P LL_HRTIM_FLT_GetPolarity + * FLTINR2 FLT5P LL_HRTIM_FLT_GetPolarity * @param HRTIMx High Resolution Timer instance * @param Fault This parameter can be one of the following values: * @arg @ref LL_HRTIM_FAULT_1 @@ -7177,7 +6895,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_ { register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1P << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]); } @@ -7219,7 +6937,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Faul { register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1F << REG_SHIFT_TAB_FLTxE[iFault]), (Filter << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -7259,7 +6977,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetFilter(HRTIM_TypeDef *HRTIMx, uint32_t { register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1F << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]); } @@ -7315,7 +7033,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_Lock(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1LCK << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -7339,7 +7057,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_Enable(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -7363,7 +7081,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_Disable(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + REG_OFFSET_TAB_FLTINR[iFault])); CLEAR_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])); } @@ -7386,10 +7104,10 @@ __STATIC_INLINE void LL_HRTIM_FLT_Disable(HRTIM_TypeDef *HRTIMx, uint32_t Fault) __STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabled(HRTIM_TypeDef *HRTIMx, uint32_t Fault) { register uint32_t iFault = (uint8_t)POSITION_VAL(Fault); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + - REG_OFFSET_TAB_FLTINR[iFault])); + register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + + REG_OFFSET_TAB_FLTINR[iFault])); return (((READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]) == - (HRTIM_IER_FLT1)) ? 1UL : 0UL); + (HRTIM_IER_FLT1)) ? 1UL : 0UL); } /** @@ -8063,7 +7781,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t T { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MUPD); } @@ -8085,7 +7803,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uin { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MUPD) == (HRTIM_MISR_MUPD)) ? 1UL : 0UL); } @@ -8108,7 +7826,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Time { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MREP); } @@ -8131,7 +7849,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_REP(HRTIM_TypeDef *HRTIMx, uint32 { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MREP) == (HRTIM_MISR_MREP)) ? 1UL : 0UL); } @@ -8154,7 +7872,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP1); } @@ -8176,7 +7894,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint3 { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MCMP1) == (HRTIM_MISR_MCMP1)) ? 1UL : 0UL); } @@ -8199,7 +7917,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP2); } @@ -8221,7 +7939,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint3 { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MCMP2) == (HRTIM_MISR_MCMP2)) ? 1UL : 0UL); } @@ -8244,7 +7962,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Tim { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP3); } @@ -8266,7 +7984,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint3 { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MCMP3) == (HRTIM_MISR_MCMP3)) ? 1UL : 0UL); } @@ -8289,7 +8007,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Tim { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_MICR_MCMP4); } @@ -8311,7 +8029,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint3 { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_MISR_MCMP4) == (HRTIM_MISR_MCMP4)) ? 1UL : 0UL); } @@ -8332,7 +8050,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_CPT1C); } @@ -8352,7 +8070,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint3 { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT1) == (HRTIM_TIMISR_CPT1)) ? 1UL : 0UL); } @@ -8373,7 +8091,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_CPT2C); } @@ -8393,7 +8111,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint3 { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT2) == (HRTIM_TIMISR_CPT2)) ? 1UL : 0UL); } @@ -8414,7 +8132,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_SET1C); } @@ -8434,7 +8152,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET1(HRTIM_TypeDef *HRTIMx, uint3 { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_SET1) == (HRTIM_TIMISR_SET1)) ? 1UL : 0UL); } @@ -8455,7 +8173,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Tim { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_RST1C); } @@ -8475,7 +8193,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST1(HRTIM_TypeDef *HRTIMx, uint3 { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_RST1) == (HRTIM_TIMISR_RST1)) ? 1UL : 0UL); } @@ -8496,7 +8214,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_SET2C); } @@ -8516,7 +8234,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET2(HRTIM_TypeDef *HRTIMx, uint3 { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_SET2) == (HRTIM_TIMISR_SET2)) ? 1UL : 0UL); } @@ -8537,7 +8255,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Tim { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_RST2C); } @@ -8557,7 +8275,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST2(HRTIM_TypeDef *HRTIMx, uint3 { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_RST2) == (HRTIM_TIMISR_RST2)) ? 1UL : 0UL); } @@ -8578,7 +8296,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Time { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_RSTC); } @@ -8598,7 +8316,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST(HRTIM_TypeDef *HRTIMx, uint32 { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_RST) == (HRTIM_TIMISR_RST)) ? 1UL : 0UL); } @@ -8619,7 +8337,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t T { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); SET_BIT(*pReg, HRTIM_TIMICR_DLYPRTC); } @@ -8639,7 +8357,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uin { register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + - REG_OFFSET_TAB_TIMER[iTimer])); + REG_OFFSET_TAB_TIMER[iTimer])); return ((READ_BIT(*pReg, HRTIM_TIMISR_DLYPRT) == (HRTIM_TIMISR_DLYPRT)) ? 1UL : 0UL); } diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_hsem.h b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_hsem.h index 01cd10d658c..b1d87580c2a 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_hsem.h +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_hsem.h @@ -84,6 +84,9 @@ extern "C" { #define LL_HSEM_SEMAPHORE_13 HSEM_C1IER_ISE13 #define LL_HSEM_SEMAPHORE_14 HSEM_C1IER_ISE14 #define LL_HSEM_SEMAPHORE_15 HSEM_C1IER_ISE15 +#if (HSEM_SEMID_MAX == 15) +#define LL_HSEM_SEMAPHORE_ALL 0x0000FFFFU +#else /* HSEM_SEMID_MAX == 31 */ #define LL_HSEM_SEMAPHORE_16 HSEM_C1IER_ISE16 #define LL_HSEM_SEMAPHORE_17 HSEM_C1IER_ISE17 #define LL_HSEM_SEMAPHORE_18 HSEM_C1IER_ISE18 @@ -101,6 +104,7 @@ extern "C" { #define LL_HSEM_SEMAPHORE_30 HSEM_C1IER_ISE30 #define LL_HSEM_SEMAPHORE_31 HSEM_C1IER_ISE31 #define LL_HSEM_SEMAPHORE_ALL 0xFFFFFFFFU +#endif /* HSEM_SEMID_MAX == 15 */ /** * @} */ @@ -346,6 +350,8 @@ __STATIC_INLINE void LL_HSEM_ResetAllLock(HSEM_TypeDef *HSEMx, uint32_t key, uin * @arg @ref LL_HSEM_SEMAPHORE_30 * @arg @ref LL_HSEM_SEMAPHORE_31 * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 + * depends on devices. * @retval None */ __STATIC_INLINE void LL_HSEM_EnableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) @@ -391,6 +397,8 @@ __STATIC_INLINE void LL_HSEM_EnableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t Semaph * @arg @ref LL_HSEM_SEMAPHORE_30 * @arg @ref LL_HSEM_SEMAPHORE_31 * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 + * depends on devices. * @retval None */ __STATIC_INLINE void LL_HSEM_DisableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) @@ -436,6 +444,8 @@ __STATIC_INLINE void LL_HSEM_DisableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t Semap * @arg @ref LL_HSEM_SEMAPHORE_30 * @arg @ref LL_HSEM_SEMAPHORE_31 * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 + * depends on devices. * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) @@ -625,6 +635,8 @@ __STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t * @arg @ref LL_HSEM_SEMAPHORE_30 * @arg @ref LL_HSEM_SEMAPHORE_31 * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 + * depends on devices. * @retval None */ __STATIC_INLINE void LL_HSEM_ClearFlag_C1ICR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) @@ -670,6 +682,8 @@ __STATIC_INLINE void LL_HSEM_ClearFlag_C1ICR(HSEM_TypeDef *HSEMx, uint32_t Semap * @arg @ref LL_HSEM_SEMAPHORE_30 * @arg @ref LL_HSEM_SEMAPHORE_31 * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 + * depends on devices. * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) @@ -715,6 +729,8 @@ __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1ISR(HSEM_TypeDef *HSEMx, uint32_ * @arg @ref LL_HSEM_SEMAPHORE_30 * @arg @ref LL_HSEM_SEMAPHORE_31 * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @note Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31 + * depends on devices. * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_lptim.c b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_lptim.c index 902519abb64..872a61dc489 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_lptim.c +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_lptim.c @@ -13,7 +13,8 @@ * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause - * ****************************************************************************** + * + ****************************************************************************** */ #if defined(USE_FULL_LL_DRIVER) @@ -109,21 +110,27 @@ ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx) LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPTIM2); LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPTIM2); } +#if defined(LPTIM3) else if (LPTIMx == LPTIM3) { LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPTIM3); LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPTIM3); } +#endif /* LPTIM3 */ +#if defined(LPTIM4) else if (LPTIMx == LPTIM4) { LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPTIM4); LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPTIM4); } +#endif /* LPTIM4 */ +#if defined(LPTIM5) else if (LPTIMx == LPTIM5) { LL_APB4_GRP1_ForceReset(LL_APB4_GRP1_PERIPH_LPTIM5); LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_LPTIM5); } +#endif /* LPTIM5 */ else { result = ERROR; @@ -233,11 +240,17 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) case LPTIM2_BASE: tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE); break; +#if defined(LPTIM3)&&defined(LPTIM4)&&defined(LPTIM5) case LPTIM3_BASE: case LPTIM4_BASE: case LPTIM5_BASE: tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM345_CLKSOURCE); break; +#elif defined(LPTIM3) + case LPTIM3_BASE: + tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM3_CLKSOURCE); + break; +#endif /* LPTIM3 && LPTIM4 && LPTIM5 */ default: break; } @@ -266,11 +279,17 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) case LPTIM2_BASE: LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE_PCLK4); break; +#if defined(LPTIM3)&&defined(LPTIM4)&&defined(LPTIM5) case LPTIM3_BASE: case LPTIM4_BASE: case LPTIM5_BASE: LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM345_CLKSOURCE_PCLK4); break; +#elif defined(LPTIM3) + case LPTIM3_BASE: + LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM3_CLKSOURCE_PCLK4); + break; +#endif /* LPTIM3 && LPTIM4 && LPTIM5*/ default: break; } diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_lptim.h b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_lptim.h index 304cc060b2b..05b7960f2f2 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_lptim.h +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_lptim.h @@ -283,7 +283,6 @@ typedef struct * @} */ - /** * @} */ @@ -304,7 +303,7 @@ typedef struct * @param __VALUE__ Value to be written in the register * @retval None */ -#define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->(__REG__), (__VALUE__)) +#define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) /** * @brief Read a value in LPTIM register @@ -312,7 +311,7 @@ typedef struct * @param __REG__ Register to be read * @retval Register value */ -#define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->(__REG__)) +#define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_lpuart.c b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_lpuart.c index 7ad012d24fe..8267e412701 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_lpuart.c +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_lpuart.c @@ -22,11 +22,11 @@ #include "stm32h7xx_ll_lpuart.h" #include "stm32h7xx_ll_rcc.h" #include "stm32h7xx_ll_bus.h" -#ifdef USE_FULL_ASSERT +#ifdef USE_FULL_ASSERT #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32H7xx_LL_Driver * @{ @@ -58,17 +58,17 @@ /* Check of parameters for configuration of LPUART registers */ #define IS_LL_LPUART_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPUART_PRESCALER_DIV1) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV2) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV4) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV6) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV8) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV10) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV12) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV16) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV32) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV64) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV128) \ - || ((__VALUE__) == LL_LPUART_PRESCALER_DIV256)) + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV2) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV4) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV6) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV8) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV10) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV12) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV16) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV32) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV64) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV128) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV256)) /* __BAUDRATE__ Depending on constraints applicable for LPUART BRR register */ /* value : */ @@ -85,25 +85,25 @@ #define IS_LL_LPUART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x000FFFFFU) #define IS_LL_LPUART_DIRECTION(__VALUE__) (((__VALUE__) == LL_LPUART_DIRECTION_NONE) \ - || ((__VALUE__) == LL_LPUART_DIRECTION_RX) \ - || ((__VALUE__) == LL_LPUART_DIRECTION_TX) \ - || ((__VALUE__) == LL_LPUART_DIRECTION_TX_RX)) + || ((__VALUE__) == LL_LPUART_DIRECTION_RX) \ + || ((__VALUE__) == LL_LPUART_DIRECTION_TX) \ + || ((__VALUE__) == LL_LPUART_DIRECTION_TX_RX)) #define IS_LL_LPUART_PARITY(__VALUE__) (((__VALUE__) == LL_LPUART_PARITY_NONE) \ - || ((__VALUE__) == LL_LPUART_PARITY_EVEN) \ - || ((__VALUE__) == LL_LPUART_PARITY_ODD)) + || ((__VALUE__) == LL_LPUART_PARITY_EVEN) \ + || ((__VALUE__) == LL_LPUART_PARITY_ODD)) #define IS_LL_LPUART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_LPUART_DATAWIDTH_7B) \ - || ((__VALUE__) == LL_LPUART_DATAWIDTH_8B) \ - || ((__VALUE__) == LL_LPUART_DATAWIDTH_9B)) + || ((__VALUE__) == LL_LPUART_DATAWIDTH_8B) \ + || ((__VALUE__) == LL_LPUART_DATAWIDTH_9B)) #define IS_LL_LPUART_STOPBITS(__VALUE__) (((__VALUE__) == LL_LPUART_STOPBITS_1) \ - || ((__VALUE__) == LL_LPUART_STOPBITS_2)) + || ((__VALUE__) == LL_LPUART_STOPBITS_2)) #define IS_LL_LPUART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_LPUART_HWCONTROL_NONE) \ - || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS) \ - || ((__VALUE__) == LL_LPUART_HWCONTROL_CTS) \ - || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS_CTS)) + || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS) \ + || ((__VALUE__) == LL_LPUART_HWCONTROL_CTS) \ + || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS_CTS)) /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_lpuart.h b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_lpuart.h index adfeb8a5ec0..a7ce8bc2b7d 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_lpuart.h +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_lpuart.h @@ -442,7 +442,8 @@ typedef struct * @param __BAUDRATE__ Baud Rate value to achieve * @retval LPUARTDIV value to be used for BRR register filling */ -#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)])) * LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK) +#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)])) * LPUART_LPUARTDIV_FREQ_MUL)\ + + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK) /** * @} @@ -1341,7 +1342,8 @@ __STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(USART_TypeDef *LPUARTx) * @param BaudRate Baud Rate * @retval None */ -__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t BaudRate) +__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue, + uint32_t BaudRate) { LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate); } @@ -1380,6 +1382,10 @@ __STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t { brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv); } + else + { + brrresult = 0x0UL; + } return (brrresult); } @@ -2481,12 +2487,12 @@ __STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32 if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT) { /* return address of TDR register */ - data_reg_addr = (uint32_t) & (LPUARTx->TDR); + data_reg_addr = (uint32_t) &(LPUARTx->TDR); } else { /* return address of RDR register */ - data_reg_addr = (uint32_t) & (LPUARTx->RDR); + data_reg_addr = (uint32_t) &(LPUARTx->RDR); } return data_reg_addr; @@ -2508,7 +2514,7 @@ __STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32 */ __STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx) { - return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR)); + return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU); } /** diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_rcc.h b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_rcc.h index 97b9ab4338f..bd8185f4d87 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_rcc.h +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_rcc.h @@ -69,23 +69,23 @@ extern const uint8_t LL_RCC_PrescTable[16]; #define D2CCIP2 0x8UL #define D3CCIP 0xCUL -#define REG_SHIFT 0U -#define POS_SHIFT 8U -#define CONFIG_SHIFT 16U -#define MASK_SHIFT 24U +#define LL_RCC_REG_SHIFT 0U +#define LL_RCC_POS_SHIFT 8U +#define LL_RCC_CONFIG_SHIFT 16U +#define LL_RCC_MASK_SHIFT 24U -#define LL_CLKSOURCE_SHIFT(__CLKSOURCE__) (((__CLKSOURCE__) >> POS_SHIFT ) & 0x1FUL) +#define LL_CLKSOURCE_SHIFT(__CLKSOURCE__) (((__CLKSOURCE__) >> LL_RCC_POS_SHIFT ) & 0x1FUL) -#define LL_CLKSOURCE_MASK(__CLKSOURCE__) ((((__CLKSOURCE__) >> MASK_SHIFT ) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__)) +#define LL_CLKSOURCE_MASK(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_MASK_SHIFT ) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__)) -#define LL_CLKSOURCE_CONFIG(__CLKSOURCE__) ((((__CLKSOURCE__) >> CONFIG_SHIFT) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__)) +#define LL_CLKSOURCE_CONFIG(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_CONFIG_SHIFT) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__)) -#define LL_CLKSOURCE_REG(__CLKSOURCE__) (((__CLKSOURCE__) >> REG_SHIFT ) & 0xFFUL) +#define LL_CLKSOURCE_REG(__CLKSOURCE__) (((__CLKSOURCE__) >> LL_RCC_REG_SHIFT ) & 0xFFUL) -#define LL_CLKSOURCE(__REG__, __MSK__, __POS__, __CLK__) ((uint32_t)((((__MSK__) >> (__POS__)) << MASK_SHIFT) | \ - (( __POS__ ) << POS_SHIFT) | \ - (( __REG__ ) << REG_SHIFT) | \ - (((__CLK__) >> (__POS__)) << CONFIG_SHIFT))) +#define LL_CLKSOURCE(__REG__, __MSK__, __POS__, __CLK__) ((uint32_t)((((__MSK__) >> (__POS__)) << LL_RCC_MASK_SHIFT) | \ + (( __POS__ ) << LL_RCC_POS_SHIFT) | \ + (( __REG__ ) << LL_RCC_REG_SHIFT) | \ + (((__CLK__) >> (__POS__)) << LL_RCC_CONFIG_SHIFT))) #if defined(USE_FULL_LL_DRIVER) /** @defgroup RCC_LL_Private_Macros RCC Private Macros @@ -2642,7 +2642,7 @@ __STATIC_INLINE uint32_t LL_RCC_GetClockSource(uint32_t Periph) { register const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->D1CCIPR) + LL_CLKSOURCE_REG(Periph))); - return (uint32_t) (Periph | (((READ_BIT(*pReg, LL_CLKSOURCE_MASK(Periph))) >> LL_CLKSOURCE_SHIFT(Periph)) << CONFIG_SHIFT) ); + return (uint32_t) (Periph | (((READ_BIT(*pReg, LL_CLKSOURCE_MASK(Periph))) >> LL_CLKSOURCE_SHIFT(Periph)) << LL_RCC_CONFIG_SHIFT) ); } /** diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_sdmmc.c b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_sdmmc.c index ddbb5a3e01f..3a9c4117fec 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_sdmmc.c +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_sdmmc.c @@ -302,10 +302,6 @@ HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx) /* Set power state to ON */ SDMMCx->POWER |= SDMMC_POWER_PWRCTRL; - /* 1ms: required power up waiting time before starting the SD initialization - sequence */ - HAL_Delay(2); - return HAL_OK; } @@ -741,7 +737,7 @@ uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx) uint32_t errorstate; /* Set Block Size for Card */ - sdmmc_cmdinit.Argument = 0; + sdmmc_cmdinit.Argument = 0U; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; @@ -765,7 +761,7 @@ uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx) uint32_t errorstate; /* Send CMD12 STOP_TRANSMISSION */ - sdmmc_cmdinit.Argument = 0; + sdmmc_cmdinit.Argument = 0U; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_STOP_TRANSMISSION; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; @@ -819,7 +815,7 @@ uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx) SDMMC_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; - sdmmc_cmdinit.Argument = 0; + sdmmc_cmdinit.Argument = 0U; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_GO_IDLE_STATE; sdmmc_cmdinit.Response = SDMMC_RESPONSE_NO; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; @@ -949,7 +945,7 @@ uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx) uint32_t errorstate; /* Send CMD51 SD_APP_SEND_SCR */ - sdmmc_cmdinit.Argument = 0; + sdmmc_cmdinit.Argument = 0U; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_SEND_SCR; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; @@ -973,7 +969,7 @@ uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx) uint32_t errorstate; /* Send CMD2 ALL_SEND_CID */ - sdmmc_cmdinit.Argument = 0; + sdmmc_cmdinit.Argument = 0U; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ALL_SEND_CID; sdmmc_cmdinit.Response = SDMMC_RESPONSE_LONG; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; @@ -1023,7 +1019,7 @@ uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA) uint32_t errorstate; /* Send CMD3 SD_CMD_SET_REL_ADDR */ - sdmmc_cmdinit.Argument = 0; + sdmmc_cmdinit.Argument = 0U; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; @@ -1070,7 +1066,7 @@ uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx) SDMMC_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; - sdmmc_cmdinit.Argument = 0; + sdmmc_cmdinit.Argument = 0U; sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_STATUS; sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; @@ -1086,7 +1082,7 @@ uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx) /** * @brief Sends host capacity support information and activates the card's * initialization process. Send SDMMC_CMD_SEND_OP_COND command - * @param SDIOx: Pointer to SDIO register base + * @param SDMMCx: Pointer to SDMMC register base * @parame Argument: Argument used for the command * @retval HAL status */ @@ -1110,7 +1106,7 @@ uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument) /** * @brief Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH comand - * @param SDIOx: Pointer to SDIO register base + * @param SDMMCx: Pointer to SDMMC register base * @parame Argument: Argument used for the command * @retval HAL status */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_sdmmc.h b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_sdmmc.h index 09de0eadcfb..30fd71d27cc 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_sdmmc.h +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_sdmmc.h @@ -46,7 +46,7 @@ */ typedef struct { - uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. + uint32_t ClockEdge; /*!< Specifies the SDMMC_CCK clock transition on which Data and Command change. This parameter can be a value of @ref SDMMC_LL_Clock_Edge */ uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or @@ -62,6 +62,10 @@ typedef struct uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller. This parameter can be a value between Min_Data = 0 and Max_Data = 1023 */ +#if (USE_SD_TRANSCEIVER != 0U) + uint32_t TranceiverPresent; /*!< Specifies if there is a 1V8 Tranceiver/Switcher. + This parameter can be a value of @ref SDMMC_LL_TRANCEIVER_PRESENT */ +#endif /* USE_SD_TRANSCEIVER */ }SDMMC_InitTypeDef; @@ -123,31 +127,31 @@ typedef struct /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants * @{ */ -#define SDMMC_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define SDMMC_ERROR_CMD_CRC_FAIL ((uint32_t)0x00000001U) /*!< Command response received (but CRC check failed) */ -#define SDMMC_ERROR_DATA_CRC_FAIL ((uint32_t)0x00000002U) /*!< Data block sent/received (CRC check failed) */ -#define SDMMC_ERROR_CMD_RSP_TIMEOUT ((uint32_t)0x00000004U) /*!< Command response timeout */ -#define SDMMC_ERROR_DATA_TIMEOUT ((uint32_t)0x00000008U) /*!< Data timeout */ -#define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /*!< Transmit FIFO underrun */ -#define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /*!< Receive FIFO overrun */ -#define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /*!< Misaligned address */ -#define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the - number of transferred bytes does not match the block length */ +#define SDMMC_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define SDMMC_ERROR_CMD_CRC_FAIL ((uint32_t)0x00000001U) /*!< Command response received (but CRC check failed) */ +#define SDMMC_ERROR_DATA_CRC_FAIL ((uint32_t)0x00000002U) /*!< Data block sent/received (CRC check failed) */ +#define SDMMC_ERROR_CMD_RSP_TIMEOUT ((uint32_t)0x00000004U) /*!< Command response timeout */ +#define SDMMC_ERROR_DATA_TIMEOUT ((uint32_t)0x00000008U) /*!< Data timeout */ +#define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /*!< Transmit FIFO underrun */ +#define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /*!< Receive FIFO overrun */ +#define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /*!< Misaligned address */ +#define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the + number of transferred bytes does not match the block length */ #define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /*!< An error in the sequence of erase command occurs */ -#define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /*!< An invalid selection for erase groups */ -#define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /*!< Attempt to program a write protect block */ -#define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock - command or if there was an attempt to access a locked card */ -#define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /*!< CRC check of the previous command failed */ -#define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /*!< Command is not legal for the card state */ -#define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /*!< Card internal ECC was applied but failed to correct the data */ -#define SDMMC_ERROR_CC_ERR ((uint32_t)0x00008000U) /*!< Internal card controller error */ -#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR ((uint32_t)0x00010000U) /*!< General or unknown error */ +#define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /*!< An invalid selection for erase groups */ +#define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /*!< Attempt to program a write protect block */ +#define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock + command or if there was an attempt to access a locked card */ +#define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /*!< CRC check of the previous command failed */ +#define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /*!< Command is not legal for the card state */ +#define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /*!< Card internal ECC was applied but failed to correct the data */ +#define SDMMC_ERROR_CC_ERR ((uint32_t)0x00008000U) /*!< Internal card controller error */ +#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR ((uint32_t)0x00010000U) /*!< General or unknown error */ #define SDMMC_ERROR_STREAM_READ_UNDERRUN ((uint32_t)0x00020000U) /*!< The card could not sustain data reading in stream rmode */ -#define SDMMC_ERROR_STREAM_WRITE_OVERRUN ((uint32_t)0x00040000U) /*!< The card could not sustain data programming in stream mode */ -#define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /*!< CID/CSD overwrite error */ -#define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /*!< Only partial address space was erased */ -#define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /*!< Command has been executed without using internal ECC */ +#define SDMMC_ERROR_STREAM_WRITE_OVERRUN ((uint32_t)0x00040000U) /*!< The card could not sustain data programming in stream mode */ +#define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /*!< CID/CSD overwrite error */ +#define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /*!< Only partial address space was erased */ +#define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /*!< Command has been executed without using internal ECC */ #define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */ #define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /*!< Error in sequence of authentication */ @@ -158,7 +162,7 @@ typedef struct #define SDMMC_ERROR_UNSUPPORTED_FEATURE ((uint32_t)0x10000000U) /*!< Error when feature is not insupported */ #define SDMMC_ERROR_BUSY ((uint32_t)0x20000000U) /*!< Error when transfer process is busy */ #define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /*!< Error while DMA transfer */ -#define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /*!< Timeout error */ +#define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /*!< Timeout error */ /** * @brief SDMMC Commands Index @@ -169,11 +173,11 @@ typedef struct #define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */ #define SDMMC_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */ #define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its - operating condition register (OCR) content in the response on the CMD line. */ + operating condition register (OCR) content in the response on the CMD line. */ #define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ #define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */ #define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information - and asks the card whether card supports voltage. */ + and asks the card whether card supports voltage. */ #define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ #define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */ #define SDMMC_CMD_VOLTAGE_SWITCH ((uint8_t)11U) /*!< SD card Voltage switch to 1.8V mode. */ @@ -182,17 +186,17 @@ typedef struct #define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */ #define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */ #define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands - (read, write, lock). Default block length is fixed to 512 Bytes. Not effective - for SDHS and SDXC. */ + (read, write, lock). Default block length is fixed to 512 Bytes. Not effective + for SDHS and SDXC. */ #define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of - fixed 512 bytes in case of SDHC and SDXC. */ + fixed 512 bytes in case of SDHC and SDXC. */ #define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by - STOP_TRANSMISSION command. */ + STOP_TRANSMISSION command. */ #define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ #define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */ #define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */ #define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of - fixed 512 bytes in case of SDHC and SDXC. */ + fixed 512 bytes in case of SDHC and SDXC. */ #define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ #define SDMMC_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */ #define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */ @@ -202,18 +206,18 @@ typedef struct #define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */ #define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */ #define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command - system set by switch function command (CMD6). */ + system set by switch function command (CMD6). */ #define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased. - Reserved for each command system set by switch function command (CMD6). */ + Reserved for each command system set by switch function command (CMD6). */ #define SDMMC_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */ #define SDMMC_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */ #define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */ #define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by - the SET_BLOCK_LEN command. */ + the SET_BLOCK_LEN command. */ #define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather - than a standard command. */ + than a standard command. */ #define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card - for general purpose/application specific commands. */ + for general purpose/application specific commands. */ #define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */ /** @@ -221,16 +225,16 @@ typedef struct * SDMMC_APP_CMD should be sent before sending these commands. */ #define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus - widths are given in SCR register. */ -#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */ + widths are given in SCR register. */ +#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */ #define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with - 32bit+CRC data block. */ + 32bit+CRC data block. */ #define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to - send its operating condition register (OCR) content in the response on the CMD line. */ + send its operating condition register (OCR) content in the response on the CMD line. */ #define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ -#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */ -#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */ -#define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */ +#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */ +#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */ +#define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */ /** * @brief Following commands are SD Card Specific security commands. @@ -315,8 +319,8 @@ typedef struct */ #define SDMMC_CCCC_ERASE ((uint32_t)0x00000020U) -#define SDMMC_CMDTIMEOUT ((uint32_t)5000U) /* Command send and response timeout */ -#define SDMMC_MAXERASETIMEOUT ((uint32_t)63000U) /* Max erase Timeout 63 s */ +#define SDMMC_CMDTIMEOUT ((uint32_t)5000U) /* Command send and response timeout */ +#define SDMMC_MAXERASETIMEOUT ((uint32_t)63000U) /* Max erase Timeout 63 s */ #define SDMMC_STOPTRANSFERTIMEOUT ((uint32_t)100000000U) /* Timeout for STOP TRANSMISSION command */ /** @defgroup SDMMC_LL_Clock_Edge Clock Edge @@ -326,7 +330,7 @@ typedef struct #define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE #define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \ - ((EDGE) == SDMMC_CLOCK_EDGE_FALLING)) + ((EDGE) == SDMMC_CLOCK_EDGE_FALLING)) /** * @} */ @@ -338,7 +342,7 @@ typedef struct #define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV #define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \ - ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE)) + ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE)) /** * @} */ @@ -351,8 +355,8 @@ typedef struct #define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1 #define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \ - ((WIDE) == SDMMC_BUS_WIDE_4B) || \ - ((WIDE) == SDMMC_BUS_WIDE_8B)) + ((WIDE) == SDMMC_BUS_WIDE_4B) || \ + ((WIDE) == SDMMC_BUS_WIDE_8B)) /** * @} */ @@ -383,7 +387,7 @@ typedef struct #define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN #define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \ - ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE)) + ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE)) /** * @} */ @@ -397,6 +401,16 @@ typedef struct * @} */ +/** @defgroup SDMMC_LL_TRANSCEIVER_PRESENT Tranceiver Present + * @{ + */ +#define SDMMC_TRANSCEIVER_UNKNOWN ((uint32_t)0x00000000U) +#define SDMMC_TRANSCEIVER_NOT_PRESENT ((uint32_t)0x00000001U) +#define SDMMC_TRANSCEIVER_PRESENT ((uint32_t)0x00000002U) + +/** + * @} + */ /** @defgroup SDMMC_LL_Command_Index Command Index * @{ @@ -414,8 +428,8 @@ typedef struct #define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP #define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) || \ - ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \ - ((RESPONSE) == SDMMC_RESPONSE_LONG)) + ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \ + ((RESPONSE) == SDMMC_RESPONSE_LONG)) /** * @} */ @@ -428,8 +442,8 @@ typedef struct #define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND #define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \ - ((WAIT) == SDMMC_WAIT_IT) || \ - ((WAIT) == SDMMC_WAIT_PEND)) + ((WAIT) == SDMMC_WAIT_IT) || \ + ((WAIT) == SDMMC_WAIT_PEND)) /** * @} */ @@ -441,7 +455,7 @@ typedef struct #define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN #define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \ - ((CPSM) == SDMMC_CPSM_ENABLE)) + ((CPSM) == SDMMC_CPSM_ENABLE)) /** * @} */ @@ -455,9 +469,9 @@ typedef struct #define SDMMC_RESP4 ((uint32_t)0x0000000CU) #define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \ - ((RESP) == SDMMC_RESP2) || \ - ((RESP) == SDMMC_RESP3) || \ - ((RESP) == SDMMC_RESP4)) + ((RESP) == SDMMC_RESP2) || \ + ((RESP) == SDMMC_RESP3) || \ + ((RESP) == SDMMC_RESP4)) /** @defgroup SDMMC_Internal_DMA_Mode SDMMC Internal DMA Mode * @{ @@ -499,20 +513,20 @@ typedef struct #define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) #define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B)) + ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B)) /** * @} */ @@ -524,7 +538,7 @@ typedef struct #define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR #define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \ - ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC)) + ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC)) /** * @} */ @@ -536,7 +550,7 @@ typedef struct #define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE_1 #define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \ - ((MODE) == SDMMC_TRANSFER_MODE_STREAM)) + ((MODE) == SDMMC_TRANSFER_MODE_STREAM)) /** * @} */ @@ -548,7 +562,7 @@ typedef struct #define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN #define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\ - ((DPSM) == SDMMC_DPSM_ENABLE)) + ((DPSM) == SDMMC_DPSM_ENABLE)) /** * @} */ @@ -628,9 +642,9 @@ typedef struct #define SDMMC_FLAG_IDMATE SDMMC_STA_IDMATE #define SDMMC_FLAG_IDMABTC SDMMC_STA_IDMABTC -#define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\ - SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\ - SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\ +#define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\ + SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\ + SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\ SDMMC_FLAG_DHOLD | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT |\ SDMMC_FLAG_BUSYD0END | SDMMC_FLAG_SDIOIT | SDMMC_FLAG_ACKFAIL |\ SDMMC_FLAG_ACKTIMEOUT | SDMMC_FLAG_VSWEND | SDMMC_FLAG_CKSTOP |\ @@ -778,8 +792,8 @@ typedef struct * @arg SDMMC_FLAG_DHOLD: Data transfer Hold * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 - * @arg SDMMC_FLAG_CPSMACT: Command path state machine active * @arg SDMMC_FLAG_DPSMACT: Data path state machine active + * @arg SDMMC_FLAG_CPSMACT: Command path state machine active * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full @@ -846,26 +860,20 @@ typedef struct * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt - * @arg SDMMC_IT_DPSMACT: Data path state machine active interrupt - * @arg SDMMC_IT_CPSMACT: Command path state machine active interrupt * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDMMC_IT_BUSYD0: Inverted value of SDMMC_D0 line (Busy) * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt - * @arg SDMMC_IT_IDMATE: IDMA transfer error interrupt * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt * @retval The new state of SDMMC_IT (SET or RESET). */ -#define __SDMMC_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) +#define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) /** * @brief Clears the SDMMC's interrupt pending bits. @@ -890,7 +898,6 @@ typedef struct * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt - * @arg SDMMC_IT_IDMATE: IDMA transfer error interrupt * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_spi.c b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_spi.c index 7916ff7f091..88669736c95 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_spi.c +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_spi.c @@ -28,7 +28,7 @@ #ifdef USE_FULL_ASSERT #include "stm32_assert.h" #else -#define assert_param(expr) ((void)0) +#define assert_param(expr) ((void)0U) #endif /** @addtogroup STM32H7xx_LL_Driver diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_system.h b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_system.h index 306f43744e4..2476adf4315 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_system.h +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_system.h @@ -1975,6 +1975,69 @@ __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); } +/** + * @} + */ + +#if defined(DUAL_CORE) +/** @defgroup SYSTEM_LL_EF_ART ART + * @{ + */ + +/** + * @brief Enable the Cortex-M4 ART cache. + * @rmtoll ART_CTR EN LL_ART_Enable + * @retval None + */ +__STATIC_INLINE void LL_ART_Enable(void) +{ + SET_BIT(ART->CTR, ART_CTR_EN); +} + +/** + * @brief Disable the Cortex-M4 ART cache. + * @rmtoll ART_CTR EN LL_ART_Disable + * @retval None + */ +__STATIC_INLINE void LL_ART_Disable(void) +{ + CLEAR_BIT(ART->CTR, ART_CTR_EN); +} + +/** + * @brief Check if the Cortex-M4 ART cache is enabled + * @rmtoll ART_CTR EN LL_ART_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ART_IsEnabled(void) +{ + return ((READ_BIT(ART->CTR, ART_CTR_EN) == ART_CTR_EN) ? 1UL : 0UL); +} + +/** + * @brief Set the Cortex-M4 ART cache Base Address. + * @rmtoll ART_CTR PCACHEADDR LL_ART_SetBaseAddress + * @param BaseAddress Specifies the Base address of 1 Mbyte address page (cacheable page) + from which the ART accelerator loads code to the cache. + * @retval None + */ +__STATIC_INLINE void LL_ART_SetBaseAddress(uint32_t BaseAddress) +{ + MODIFY_REG(ART->CTR, ART_CTR_PCACHEADDR, (((BaseAddress) >> 12U) & 0x000FFF00UL)); +} + +/** + * @brief Get the Cortex-M4 ART cache Base Address. + * @rmtoll ART_CTR PCACHEADDR LL_ART_GetBaseAddress + * @retval the Base address of 1 Mbyte address page (cacheable page) + from which the ART accelerator loads code to the cache + */ +__STATIC_INLINE uint32_t LL_ART_GetBaseAddress(void) +{ + return (uint32_t)(READ_BIT(ART->CTR, ART_CTR_PCACHEADDR) << 12U); +} +#endif /* DUAL_CORE */ + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_tim.c b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_tim.c index 2fd1a54c277..30e3be71a7e 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_tim.c +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_tim.c @@ -730,9 +730,9 @@ void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) * and DTG[7:0] can be write-locked depending on the LOCK configuration, it * can be necessary to configure all of them during the first write access to * the TIMx_BDTR register. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. - * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a second break input. * @param TIMx Timer Instance * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure) diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_tim.h b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_tim.h index fa99a6fd241..362efd7b487 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_tim.h +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_tim.h @@ -1362,7 +1362,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx) /** * @brief Set the timer counter counting mode. - * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to + * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to * check whether or not the counter mode selection feature is supported * by a timer instance. * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) @@ -1386,7 +1386,7 @@ __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMo /** * @brief Get actual counter mode. - * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to + * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to * check whether or not the counter mode selection feature is supported * by a timer instance. * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n @@ -1439,7 +1439,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx) /** * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. - * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check * whether or not the clock division feature is supported by the timer * instance. * @rmtoll CR1 CKD LL_TIM_SetClockDivision @@ -1457,7 +1457,7 @@ __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDi /** * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. - * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check * whether or not the clock division feature is supported by the timer * instance. * @rmtoll CR1 CKD LL_TIM_GetClockDivision @@ -1474,7 +1474,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx) /** * @brief Set the counter value. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. * @rmtoll CNT CNT LL_TIM_SetCounter * @param TIMx Timer instance @@ -1488,7 +1488,7 @@ __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) /** * @brief Get the counter value. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. * @rmtoll CNT CNT LL_TIM_GetCounter * @param TIMx Timer instance @@ -1542,7 +1542,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx) /** * @brief Set the auto-reload value. * @note The counter is blocked while the auto-reload value is null. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter * @rmtoll ARR ARR LL_TIM_SetAutoReload @@ -1558,7 +1558,7 @@ __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload /** * @brief Get the auto-reload value. * @rmtoll ARR ARR LL_TIM_GetAutoReload - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. * @param TIMx Timer instance * @retval Auto-reload value @@ -1571,7 +1571,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx) /** * @brief Set the repetition counter value. * @note For advanced timer instances RepetitionCounter can be up to 65535. - * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a repetition counter. * @rmtoll RCR REP LL_TIM_SetRepetitionCounter * @param TIMx Timer instance @@ -1585,7 +1585,7 @@ __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t Rep /** * @brief Get the repetition counter value. - * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a repetition counter. * @rmtoll RCR REP LL_TIM_GetRepetitionCounter * @param TIMx Timer instance @@ -1631,7 +1631,7 @@ __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx) * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, * they are updated only when a commutation event (COM) occurs. * @note Only on channels that have a complementary output. - * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check * whether or not a timer instance is able to generate a commutation event. * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload * @param TIMx Timer instance @@ -1644,7 +1644,7 @@ __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) /** * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. - * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check * whether or not a timer instance is able to generate a commutation event. * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload * @param TIMx Timer instance @@ -1657,7 +1657,7 @@ __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) /** * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). - * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check * whether or not a timer instance is able to generate a commutation event. * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate * @param TIMx Timer instance @@ -1701,7 +1701,7 @@ __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx) /** * @brief Set the lock level to freeze the * configuration of several capture/compare parameters. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * the lock mechanism is supported by a timer instance. * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel * @param TIMx Timer instance @@ -2003,7 +2003,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Chann /** * @brief Set the IDLE state of an output channel * @note This function is significant only for the timer instances - * supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) + * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx) * can be used to check whether or not a timer instance provides * a break input. * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n @@ -2227,7 +2227,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t /** * @brief Enable clearing the output channel on an external event. * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. - * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether * or not a timer instance can clear the OCxREF signal on an external event. * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n * CCMR1 OC2CE LL_TIM_OC_EnableClear\n @@ -2254,7 +2254,7 @@ __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) /** * @brief Disable clearing the output channel on an external event. - * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether * or not a timer instance can clear the OCxREF signal on an external event. * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n * CCMR1 OC2CE LL_TIM_OC_DisableClear\n @@ -2283,7 +2283,7 @@ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) * @brief Indicates clearing the output channel on an external event is enabled for the output channel. * @note This function enables clearing the output channel on an external event. * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. - * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether * or not a timer instance can clear the OCxREF signal on an external event. * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n @@ -2311,7 +2311,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Ch /** * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals). - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * dead-time insertion feature is supported by a timer instance. * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime @@ -2327,9 +2327,9 @@ __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) /** * @brief Set compare value for output channel 1 (TIMx_CCR1). * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not * output channel 1 is supported by a timer instance. * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 * @param TIMx Timer instance @@ -2344,9 +2344,9 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t Compare /** * @brief Set compare value for output channel 2 (TIMx_CCR2). * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not * output channel 2 is supported by a timer instance. * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 * @param TIMx Timer instance @@ -2361,9 +2361,9 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t Compare /** * @brief Set compare value for output channel 3 (TIMx_CCR3). * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not * output channel is supported by a timer instance. * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 * @param TIMx Timer instance @@ -2378,9 +2378,9 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t Compare /** * @brief Set compare value for output channel 4 (TIMx_CCR4). * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not * output channel 4 is supported by a timer instance. * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 * @param TIMx Timer instance @@ -2394,7 +2394,7 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t Compare /** * @brief Set compare value for output channel 5 (TIMx_CCR5). - * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not * output channel 5 is supported by a timer instance. * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5 * @param TIMx Timer instance @@ -2408,7 +2408,7 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t Compare /** * @brief Set compare value for output channel 6 (TIMx_CCR6). - * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not * output channel 6 is supported by a timer instance. * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6 * @param TIMx Timer instance @@ -2423,9 +2423,9 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t Compare /** * @brief Get compare value (TIMx_CCR1) set for output channel 1. * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not * output channel 1 is supported by a timer instance. * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 * @param TIMx Timer instance @@ -2439,9 +2439,9 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx) /** * @brief Get compare value (TIMx_CCR2) set for output channel 2. * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not * output channel 2 is supported by a timer instance. * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 * @param TIMx Timer instance @@ -2455,9 +2455,9 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx) /** * @brief Get compare value (TIMx_CCR3) set for output channel 3. * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not * output channel 3 is supported by a timer instance. * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 * @param TIMx Timer instance @@ -2471,9 +2471,9 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx) /** * @brief Get compare value (TIMx_CCR4) set for output channel 4. * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not * output channel 4 is supported by a timer instance. * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 * @param TIMx Timer instance @@ -2486,7 +2486,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx) /** * @brief Get compare value (TIMx_CCR5) set for output channel 5. - * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not * output channel 5 is supported by a timer instance. * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5 * @param TIMx Timer instance @@ -2499,7 +2499,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx) /** * @brief Get compare value (TIMx_CCR6) set for output channel 6. - * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not * output channel 6 is supported by a timer instance. * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6 * @param TIMx Timer instance @@ -2512,7 +2512,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx) /** * @brief Select on which reference signal the OC5REF is combined to. - * @note Macro @ref IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports the combined 3-phase PWM mode. * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n @@ -2816,7 +2816,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Chann /** * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). - * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides an XOR input. * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination * @param TIMx Timer instance @@ -2829,7 +2829,7 @@ __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) /** * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. - * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides an XOR input. * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination * @param TIMx Timer instance @@ -2842,7 +2842,7 @@ __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) /** * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. - * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides an XOR input. * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination * @param TIMx Timer instance @@ -2856,9 +2856,9 @@ __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) /** * @brief Get captured value for input channel 1. * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not * input channel 1 is supported by a timer instance. * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 * @param TIMx Timer instance @@ -2872,9 +2872,9 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx) /** * @brief Get captured value for input channel 2. * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not * input channel 2 is supported by a timer instance. * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 * @param TIMx Timer instance @@ -2888,9 +2888,9 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx) /** * @brief Get captured value for input channel 3. * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not * input channel 3 is supported by a timer instance. * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 * @param TIMx Timer instance @@ -2904,9 +2904,9 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx) /** * @brief Get captured value for input channel 4. * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports a 32 bits counter. - * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not * input channel 4 is supported by a timer instance. * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 * @param TIMx Timer instance @@ -2927,7 +2927,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx) /** * @brief Enable external clock mode 2. * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal. - * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports external clock mode2. * @rmtoll SMCR ECE LL_TIM_EnableExternalClock * @param TIMx Timer instance @@ -2940,7 +2940,7 @@ __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) /** * @brief Disable external clock mode 2. - * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports external clock mode2. * @rmtoll SMCR ECE LL_TIM_DisableExternalClock * @param TIMx Timer instance @@ -2953,7 +2953,7 @@ __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) /** * @brief Indicate whether external clock mode 2 is enabled. - * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports external clock mode2. * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock * @param TIMx Timer instance @@ -2970,9 +2970,9 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx) * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() * function. This timer input must be configured by calling * the @ref LL_TIM_IC_Config() function. - * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports external clock mode1. - * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports external clock mode2. * @rmtoll SMCR SMS LL_TIM_SetClockSource\n * SMCR ECE LL_TIM_SetClockSource @@ -2990,7 +2990,7 @@ __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSour /** * @brief Set the encoder interface mode. - * @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check * whether or not a timer instance supports the encoder mode. * @rmtoll SMCR SMS LL_TIM_SetEncoderMode * @param TIMx Timer instance @@ -3014,7 +3014,7 @@ __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMo */ /** * @brief Set the trigger output (TRGO) used for timer synchronization . - * @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check * whether or not a timer instance can operate as a master timer. * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput * @param TIMx Timer instance @@ -3036,7 +3036,7 @@ __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSy /** * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization . - * @note Macro @ref IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check + * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check * whether or not a timer instance can be used for ADC synchronization. * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2 * @param TIMx Timer Instance @@ -3066,7 +3066,7 @@ __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSyn /** * @brief Set the synchronization mode of a slave timer. - * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not * a timer instance can operate as a slave timer. * @rmtoll SMCR SMS LL_TIM_SetSlaveMode * @param TIMx Timer instance @@ -3085,7 +3085,7 @@ __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) /** * @brief Set the selects the trigger input to be used to synchronize the counter. - * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not * a timer instance can operate as a slave timer. * @rmtoll SMCR TS LL_TIM_SetTriggerInput * @param TIMx Timer instance @@ -3112,7 +3112,7 @@ __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerI /** * @brief Enable the Master/Slave mode. - * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not * a timer instance can operate as a slave timer. * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode * @param TIMx Timer instance @@ -3125,7 +3125,7 @@ __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) /** * @brief Disable the Master/Slave mode. - * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not * a timer instance can operate as a slave timer. * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode * @param TIMx Timer instance @@ -3138,7 +3138,7 @@ __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) /** * @brief Indicates whether the Master/Slave mode is enabled. - * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not * a timer instance can operate as a slave timer. * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode * @param TIMx Timer instance @@ -3151,7 +3151,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx) /** * @brief Configure the external trigger (ETR) input. - * @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides an external trigger input. * @rmtoll SMCR ETP LL_TIM_ConfigETR\n * SMCR ETPS LL_TIM_ConfigETR\n @@ -3199,7 +3199,7 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u */ /** * @brief Enable the break function. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR BKE LL_TIM_EnableBRK * @param TIMx Timer instance @@ -3214,7 +3214,7 @@ __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) * @brief Disable the break function. * @rmtoll BDTR BKE LL_TIM_DisableBRK * @param TIMx Timer instance - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @retval None */ @@ -3225,7 +3225,7 @@ __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) /** * @brief Configure the break input. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n * BDTR BKF LL_TIM_ConfigBRK @@ -3260,7 +3260,7 @@ __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, /** * @brief Enable the break 2 function. - * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a second break input. * @rmtoll BDTR BK2E LL_TIM_EnableBRK2 * @param TIMx Timer instance @@ -3273,7 +3273,7 @@ __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx) /** * @brief Disable the break 2 function. - * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a second break input. * @rmtoll BDTR BK2E LL_TIM_DisableBRK2 * @param TIMx Timer instance @@ -3286,7 +3286,7 @@ __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx) /** * @brief Configure the break 2 input. - * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a second break input. * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n * BDTR BK2F LL_TIM_ConfigBRK2 @@ -3320,7 +3320,7 @@ __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarit /** * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n * BDTR OSSR LL_TIM_SetOffStates @@ -3340,7 +3340,7 @@ __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdl /** * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active). - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput * @param TIMx Timer instance @@ -3353,7 +3353,7 @@ __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) /** * @brief Disable automatic output (MOE can be set only by software). - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput * @param TIMx Timer instance @@ -3366,7 +3366,7 @@ __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) /** * @brief Indicate whether automatic output is enabled. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput * @param TIMx Timer instance @@ -3381,7 +3381,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx) * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by * software and is reset in case of break or break2 event - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs * @param TIMx Timer instance @@ -3396,7 +3396,7 @@ __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by * software and is reset in case of break or break2 event. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs * @param TIMx Timer instance @@ -3409,7 +3409,7 @@ __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) /** * @brief Indicates whether outputs are enabled. - * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs * @param TIMx Timer instance @@ -3423,7 +3423,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) #if defined(TIM_BREAK_INPUT_SUPPORT) /** * @brief Enable the signals connected to the designated timer break input. - * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether + * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether * or not a timer instance allows for break input selection. * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n * AF1 BKCMP1E LL_TIM_EnableBreakInputSource\n @@ -3452,7 +3452,7 @@ __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t B /** * @brief Disable the signals connected to the designated timer break input. - * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether + * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether * or not a timer instance allows for break input selection. * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n * AF1 BKCMP1E LL_TIM_DisableBreakInputSource\n @@ -3481,7 +3481,7 @@ __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t /** * @brief Set the polarity of the break signal for the timer break input. - * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether + * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether * or not a timer instance allows for break input selection. * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n * AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n @@ -3518,7 +3518,7 @@ __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint3 */ /** * @brief Configures the timer DMA burst feature. - * @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or + * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or * not a timer instance supports the DMA burst mode. * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n * DCR DBA LL_TIM_ConfigDMABurst @@ -3584,7 +3584,7 @@ __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstB */ /** * @brief Remap TIM inputs (input channel, internal/external triggers). - * @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not + * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not * a some timer inputs can be remapped. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_usart.c b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_usart.c index d1700993467..cd044ca5bde 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_usart.c +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_usart.c @@ -22,17 +22,17 @@ #include "stm32h7xx_ll_usart.h" #include "stm32h7xx_ll_rcc.h" #include "stm32h7xx_ll_bus.h" -#ifdef USE_FULL_ASSERT +#ifdef USE_FULL_ASSERT #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32H7xx_LL_Driver * @{ */ -#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8) +#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8) || defined (UART9) || defined (USART10) /** @addtogroup USART_LL * @{ @@ -41,31 +41,23 @@ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ -/** @addtogroup USART_LL_Private_Constants - * @{ - */ - -/** - * @} - */ - /* Private macros ------------------------------------------------------------*/ /** @addtogroup USART_LL_Private_Macros * @{ */ #define IS_LL_USART_PRESCALER(__VALUE__) (((__VALUE__) == LL_USART_PRESCALER_DIV1) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV2) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV4) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV6) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV8) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV10) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV12) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV16) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV32) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV64) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV128) \ - || ((__VALUE__) == LL_USART_PRESCALER_DIV256)) + || ((__VALUE__) == LL_USART_PRESCALER_DIV2) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV4) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV6) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV8) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV10) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV12) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV16) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV32) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV64) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV128) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV256)) /* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available * divided by the smallest oversampling used on the USART (i.e. 8) */ @@ -78,42 +70,42 @@ #define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \ - || ((__VALUE__) == LL_USART_DIRECTION_RX) \ - || ((__VALUE__) == LL_USART_DIRECTION_TX) \ - || ((__VALUE__) == LL_USART_DIRECTION_TX_RX)) + || ((__VALUE__) == LL_USART_DIRECTION_RX) \ + || ((__VALUE__) == LL_USART_DIRECTION_TX) \ + || ((__VALUE__) == LL_USART_DIRECTION_TX_RX)) #define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \ - || ((__VALUE__) == LL_USART_PARITY_EVEN) \ - || ((__VALUE__) == LL_USART_PARITY_ODD)) + || ((__VALUE__) == LL_USART_PARITY_EVEN) \ + || ((__VALUE__) == LL_USART_PARITY_ODD)) #define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \ - || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \ - || ((__VALUE__) == LL_USART_DATAWIDTH_9B)) + || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \ + || ((__VALUE__) == LL_USART_DATAWIDTH_9B)) #define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \ - || ((__VALUE__) == LL_USART_OVERSAMPLING_8)) + || ((__VALUE__) == LL_USART_OVERSAMPLING_8)) #define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \ - || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT)) + || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT)) #define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \ - || ((__VALUE__) == LL_USART_PHASE_2EDGE)) + || ((__VALUE__) == LL_USART_PHASE_2EDGE)) #define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \ - || ((__VALUE__) == LL_USART_POLARITY_HIGH)) + || ((__VALUE__) == LL_USART_POLARITY_HIGH)) #define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \ - || ((__VALUE__) == LL_USART_CLOCK_ENABLE)) + || ((__VALUE__) == LL_USART_CLOCK_ENABLE)) #define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \ - || ((__VALUE__) == LL_USART_STOPBITS_1) \ - || ((__VALUE__) == LL_USART_STOPBITS_1_5) \ - || ((__VALUE__) == LL_USART_STOPBITS_2)) + || ((__VALUE__) == LL_USART_STOPBITS_1) \ + || ((__VALUE__) == LL_USART_STOPBITS_1_5) \ + || ((__VALUE__) == LL_USART_STOPBITS_2)) #define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \ - || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \ - || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \ - || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS)) + || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \ + || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \ + || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS)) /** * @} @@ -208,6 +200,26 @@ ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx) /* Release reset of UART clock */ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART8); } +#if defined(UART9) + else if (USARTx == UART9) + { + /* Force reset of UART clock */ + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_UART9); + + /* Release reset of UART clock */ + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_UART9); + } +#endif /* UART9 */ +#if defined(USART10) + else if (USARTx == USART10) + { + /* Force reset of USART clock */ + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART10); + + /* Release reset of USART clock */ + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART10); + } +#endif /* USART10 */ else { status = ERROR; @@ -310,6 +322,18 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini { periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART234578_CLKSOURCE); } +#if defined(UART9) + else if (USARTx == UART9) + { + periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART16_CLKSOURCE); + } +#endif /* UART9 */ +#if defined(USART10) + else if (USARTx == USART10) + { + periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART16_CLKSOURCE); + } +#endif /* USART10 */ else { /* Nothing to do, as error code is already assigned to ERROR value */ @@ -460,7 +484,7 @@ void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct) * @} */ -#endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 */ +#endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 || UART9 || USART10 */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_usart.h b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_usart.h index 5d26c51745d..8e2e154cf58 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_usart.h +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_usart.h @@ -32,7 +32,7 @@ extern "C" { * @{ */ -#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8) +#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8) || defined (UART9) || defined (USART10) /** @defgroup USART_LL USART * @{ @@ -44,33 +44,26 @@ extern "C" { * @{ */ /* Array used to get the USART prescaler division decimal values versus @ref USART_LL_EC_PRESCALER values */ -static const uint16_t USART_PRESCALER_TAB[] = -{ - (uint16_t)1, - (uint16_t)2, - (uint16_t)4, - (uint16_t)6, - (uint16_t)8, - (uint16_t)10, - (uint16_t)12, - (uint16_t)16, - (uint16_t)32, - (uint16_t)64, - (uint16_t)128, - (uint16_t)256 +static const uint32_t USART_PRESCALER_TAB[] = +{ + 1UL, + 2UL, + 4UL, + 6UL, + 8UL, + 10UL, + 12UL, + 16UL, + 32UL, + 64UL, + 128UL, + 256UL }; /** * @} */ /* Private constants ---------------------------------------------------------*/ -/** @defgroup USART_LL_Private_Constants USART Private Constants - * @{ - */ -/** - * @} - */ - /* Private macros ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) /** @defgroup USART_LL_Private_Macros USART Private Macros @@ -570,7 +563,8 @@ typedef struct * @param __BAUDRATE__ Baud rate value to achieve * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case */ -#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (((((__PERIPHCLK__)/(uint32_t)(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U) + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) +#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\ + + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) /** * @brief Compute USARTDIV value according to Peripheral Clock and @@ -592,7 +586,8 @@ typedef struct * @param __BAUDRATE__ Baud rate value to achieve * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case */ -#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((__PERIPHCLK__)/(uint32_t)(USART_PRESCALER_TAB[(__PRESCALER__)])) + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) +#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\ + + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) /** * @} @@ -1864,22 +1859,27 @@ __STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx) * @param BaudRate Baud Rate * @retval None */ -__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling, +__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, + uint32_t OverSampling, uint32_t BaudRate) { - register uint32_t usartdiv; + uint32_t usartdiv; register uint32_t brrtemp; - if (OverSampling == LL_USART_OVERSAMPLING_8) + if (PrescalerValue > LL_USART_PRESCALER_DIV256) + { + /* Do not overstep the size of USART_PRESCALER_TAB */ + } + else if (OverSampling == LL_USART_OVERSAMPLING_8) { - usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint16_t)PrescalerValue, BaudRate)); + usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint8_t)PrescalerValue, BaudRate)); brrtemp = usartdiv & 0xFFF0U; brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); USARTx->BRR = brrtemp; } else { - USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint16_t)PrescalerValue, BaudRate)); + USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint8_t)PrescalerValue, BaudRate)); } } @@ -1909,11 +1909,12 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph * @arg @ref LL_USART_OVERSAMPLING_8 * @retval Baud Rate */ -__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t OverSampling) +__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, + uint32_t OverSampling) { register uint32_t usartdiv; register uint32_t brrresult = 0x0U; - register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (uint32_t)(USART_PRESCALER_TAB[(uint16_t)PrescalerValue])); + register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue])); usartdiv = USARTx->BRR; @@ -3264,7 +3265,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx) /** * @brief Clear Noise Error detected Flag - * @rmtoll ICR NECF LL_USART_ClearFlag_NE + * @rmtoll ICR NECF LL_USART_ClearFlag_NE * @param USARTx USART Instance * @retval None */ @@ -4200,12 +4201,12 @@ __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT) { /* return address of TDR register */ - data_reg_addr = (uint32_t) & (USARTx->TDR); + data_reg_addr = (uint32_t) &(USARTx->TDR); } else { /* return address of RDR register */ - data_reg_addr = (uint32_t) & (USARTx->RDR); + data_reg_addr = (uint32_t) &(USARTx->RDR); } return data_reg_addr; @@ -4227,7 +4228,7 @@ __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t */ __STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx) { - return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR)); + return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU); } /** @@ -4362,7 +4363,7 @@ void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitS * @} */ -#endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 */ +#endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 || UART9 || USART10 */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_usb.c b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_usb.c index aeae776bc71..2eabfcebc00 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_usb.c +++ b/targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_usb.c @@ -931,7 +931,7 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uin count32b = ((uint32_t)len + 3U) / 4U; for (i = 0U; i < count32b; i++) { - USBx_DFIFO((uint32_t)ch_ep_num) = *((__packed uint32_t *)pSrc); + USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc); pSrc++; } } @@ -940,15 +940,10 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uin } /** - * @brief USB_ReadPacket : read a packet from the Tx FIFO associated - * with the EP/channel + * @brief USB_ReadPacket : read a packet from the RX FIFO * @param USBx Selected device * @param dest source pointer * @param len Number of bytes to read - * @param dma USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used * @retval pointer to destination buffer */ void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) @@ -960,7 +955,7 @@ void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) for (i = 0U; i < count32b; i++) { - *(__packed uint32_t *)pDest = USBx_DFIFO(0U); + __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U)); pDest++; } @@ -1911,7 +1906,6 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) uint32_t value; uint32_t i; - (void)USB_DisableGlobalInt(USBx); /* Flush FIFO */ @@ -1950,6 +1944,7 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) /* Clear any pending Host interrupts */ USBx_HOST->HAINT = 0xFFFFFFFFU; USBx->GINTSTS = 0xFFFFFFFFU; + (void)USB_EnableGlobalInt(USBx); return HAL_OK; From 087699156140746bdc8963e202b3824835c28ed4 Mon Sep 17 00:00:00 2001 From: Marc Emmers Date: Fri, 22 Feb 2019 14:46:51 +0100 Subject: [PATCH 144/227] Fixed missing #if in port_api.c --- targets/TARGET_NORDIC/TARGET_NRF5x/port_api.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/port_api.c b/targets/TARGET_NORDIC/TARGET_NRF5x/port_api.c index e8c57184a5a..346c0bf45c8 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/port_api.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/port_api.c @@ -36,6 +36,8 @@ * */ +#if DEVICE_PORTIN || DEVICE_PORTOUT || DEVICE_PORTINOUT + #include "port_api.h" #include "pinmap.h" @@ -132,3 +134,5 @@ int port_read(port_t *obj) { return ((m_ports[obj->port]->IN) & obj->mask); } + +#endif // DEVICE_PORTIN || DEVICE_PORTOUT || DEVICE_PORTINOUT \ No newline at end of file From b82becb323fda9c8d2d22301dd72f929fd288803 Mon Sep 17 00:00:00 2001 From: Marc Emmers Date: Mon, 30 Sep 2019 11:20:56 +0200 Subject: [PATCH 145/227] Add newline at end of file --- targets/TARGET_NORDIC/TARGET_NRF5x/port_api.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/port_api.c b/targets/TARGET_NORDIC/TARGET_NRF5x/port_api.c index 346c0bf45c8..dca31dbe4d4 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/port_api.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/port_api.c @@ -135,4 +135,4 @@ int port_read(port_t *obj) return ((m_ports[obj->port]->IN) & obj->mask); } -#endif // DEVICE_PORTIN || DEVICE_PORTOUT || DEVICE_PORTINOUT \ No newline at end of file +#endif // DEVICE_PORTIN || DEVICE_PORTOUT || DEVICE_PORTINOUT From 3d4c21d45a9815c8e8019c8ca0d186dc77e71baa Mon Sep 17 00:00:00 2001 From: Dominika Maziec Date: Fri, 27 Sep 2019 16:02:24 +0200 Subject: [PATCH 146/227] ATCmdParser doxygen header's documentation scanf --- platform/ATCmdParser.h | 3 +++ platform/source/ATCmdParser.cpp | 1 - 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/platform/ATCmdParser.h b/platform/ATCmdParser.h index d9a6e985437..c48235f7155 100644 --- a/platform/ATCmdParser.h +++ b/platform/ATCmdParser.h @@ -271,6 +271,9 @@ class ATCmdParser : private NonCopyable { /** * Direct scanf on underlying stream + * This function does not itself match whitespace in its format string, so \n is not significant to it. + * It should be used only when certain string is needed or format ends with certain character, otherwise + * it will fill the output with one character. * @see scanf * * @param format Format string to pass to scanf diff --git a/platform/source/ATCmdParser.cpp b/platform/source/ATCmdParser.cpp index 6f01a3ea790..c37d525f184 100644 --- a/platform/source/ATCmdParser.cpp +++ b/platform/source/ATCmdParser.cpp @@ -309,7 +309,6 @@ bool ATCmdParser::vrecv(const char *response, std::va_list args) if (whole_line_wanted && c != '\n') { // Don't attempt scanning until we get delimiter if they included it in format // This allows recv("Foo: %s\n") to work, and not match with just the first character of a string - // (scanf does not itself match whitespace in its format string, so \n is not significant to it) } else if (response) { sscanf(_buffer + offset, _buffer, &count); } From a604eca79ea53e425968e24c7364183b8c656f8d Mon Sep 17 00:00:00 2001 From: Filip Jagodzinski Date: Mon, 30 Sep 2019 09:40:51 +0200 Subject: [PATCH 147/227] Bump the six (Python module) version to 1.12.0 This version provides a few handy functions: six.ensure_binary, six.ensure_text, and six.ensure_str. --- requirements.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/requirements.txt b/requirements.txt index bcfb24342a6..c58992419e0 100644 --- a/requirements.txt +++ b/requirements.txt @@ -5,7 +5,7 @@ junit-xml==1.8 pyyaml==4.2b1 jsonschema==2.6.0 future==0.16.0 -six==1.11.0 +six==1.12.0 mbed-cloud-sdk>=2.0.6,<2.1 requests>=2.20,<2.21 idna>=2,<2.8 From e6363486dd19220839fe07ea9f49d2f31cf96765 Mon Sep 17 00:00:00 2001 From: Filip Jagodzinski Date: Mon, 30 Sep 2019 10:21:16 +0200 Subject: [PATCH 148/227] Tests: USB: Fix Python 3 compatibility Use integer division explicitly in basic test. Convert bytes to str for Python 3 in serial test. --- TESTS/host_tests/pyusb_basic.py | 2 +- TESTS/host_tests/usb_device_serial.py | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/TESTS/host_tests/pyusb_basic.py b/TESTS/host_tests/pyusb_basic.py index 54ecc265e4a..dc724ffaed4 100644 --- a/TESTS/host_tests/pyusb_basic.py +++ b/TESTS/host_tests/pyusb_basic.py @@ -1376,7 +1376,7 @@ def ep_test_abort(dev, log, verbose=False): payload_size = (NUM_PACKETS_UNTIL_ABORT + NUM_PACKETS_AFTER_ABORT) * ep_out.wMaxPacketSize num_bytes_written = 0 while num_bytes_written < payload_size: - payload_out = array.array('B', (num_bytes_written/ep_out.wMaxPacketSize + payload_out = array.array('B', (num_bytes_written//ep_out.wMaxPacketSize for _ in range(ep_out.wMaxPacketSize))) try: num_bytes_written += ep_out.write(payload_out) diff --git a/TESTS/host_tests/usb_device_serial.py b/TESTS/host_tests/usb_device_serial.py index e7c049cb218..c271176aa06 100644 --- a/TESTS/host_tests/usb_device_serial.py +++ b/TESTS/host_tests/usb_device_serial.py @@ -24,6 +24,7 @@ import sys import serial import serial.tools.list_ports as stlp +import six import mbed_host_tests @@ -268,7 +269,7 @@ def change_line_coding(self): mbed_serial.reset_output_buffer() mbed_serial.dtr = True try: - payload = mbed_serial.read(LINE_CODING_STRLEN) + payload = six.ensure_str(mbed_serial.read(LINE_CODING_STRLEN)) while len(payload) == LINE_CODING_STRLEN: baud, bits, parity, stop = (int(i) for i in payload.split(',')) new_line_coding = { @@ -277,7 +278,7 @@ def change_line_coding(self): 'parity': self._PARITIES[parity], 'stopbits': self._STOPBITS[stop]} mbed_serial.apply_settings(new_line_coding) - payload = mbed_serial.read(LINE_CODING_STRLEN) + payload = six.ensure_str(mbed_serial.read(LINE_CODING_STRLEN)) except serial.SerialException as exc: self.log('TEST ERROR: {}'.format(exc)) self.notify_complete(False) From f6507b714053f1621e86687c4f409ad783ca64d7 Mon Sep 17 00:00:00 2001 From: Mukund Ghonasgi Date: Wed, 18 Sep 2019 11:11:37 -0700 Subject: [PATCH 149/227] Cypress Cordio Driver Update --- .../TARGET_CYW43XXX/CyH4TransportDriver.cpp | 37 ++++-- .../TARGET_CYW43XXX/CyH4TransportDriver.h | 7 ++ .../TARGET_CYW43XXX/HCIDriver.cpp | 107 ++++++++++++++++-- 3 files changed, 134 insertions(+), 17 deletions(-) diff --git a/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CYW43XXX/CyH4TransportDriver.cpp b/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CYW43XXX/CyH4TransportDriver.cpp index db9277ea76d..a5a177fcb0c 100644 --- a/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CYW43XXX/CyH4TransportDriver.cpp +++ b/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CYW43XXX/CyH4TransportDriver.cpp @@ -29,7 +29,7 @@ CyH4TransportDriver::CyH4TransportDriver(PinName tx, PinName rx, PinName cts, Pi bt_host_wake_name(bt_host_wake_name), bt_device_wake_name(bt_device_wake_name), bt_host_wake(bt_host_wake_name, PIN_INPUT, PullNone, 0), - bt_device_wake(bt_device_wake_name, PIN_OUTPUT, PullDefault, 1), + bt_device_wake(bt_device_wake_name, PIN_OUTPUT, PullNone, 1), host_wake_irq_event(host_wake_irq), dev_wake_irq_event(dev_wake_irq) { @@ -61,9 +61,10 @@ CyH4TransportDriver::~CyH4TransportDriver() void CyH4TransportDriver::bt_host_wake_irq_handler(void) { - sleep_manager_lock_deep_sleep(); - CyH4TransportDriver::on_controller_irq(); - sleep_manager_unlock_deep_sleep(); + uart.attach( + callback(this, &CyH4TransportDriver::on_controller_irq), + SerialBase::RxIrq + ); } void CyH4TransportDriver::initialize() @@ -72,6 +73,8 @@ void CyH4TransportDriver::initialize() InterruptIn *host_wake_pin; #endif + sleep_manager_lock_deep_sleep(); + uart.format( /* bits */ 8, /* parity */ SerialBase::None, @@ -106,6 +109,7 @@ void CyH4TransportDriver::initialize() if (bt_device_wake_name != NC) bt_device_wake = WAKE_EVENT_ACTIVE_HIGH; } + sleep_manager_unlock_deep_sleep(); rtos::ThisThread::sleep_for(500); } @@ -115,6 +119,7 @@ uint16_t CyH4TransportDriver::write(uint8_t type, uint16_t len, uint8_t *pData) { uint16_t i = 0; + sleep_manager_lock_deep_sleep(); assert_bt_dev_wake(); while (i < len + 1) { @@ -125,19 +130,29 @@ uint16_t CyH4TransportDriver::write(uint8_t type, uint16_t len, uint8_t *pData) } deassert_bt_dev_wake(); + sleep_manager_unlock_deep_sleep(); return len; } +#if (defined(MBED_TICKLESS) && DEVICE_SLEEP && DEVICE_LPTICKER) +void CyH4TransportDriver::on_host_stack_inactivity() +{ + uart.attach(NULL, SerialBase::RxIrq); +} +#endif + void CyH4TransportDriver::on_controller_irq() { - assert_bt_dev_wake(); + sleep_manager_lock_deep_sleep(); + assert_bt_dev_wake(); - while (uart.readable()) { + while (uart.readable()) { uint8_t char_received = uart.getc(); on_data_received(&char_received, 1); } - deassert_bt_dev_wake(); + deassert_bt_dev_wake(); + sleep_manager_unlock_deep_sleep(); } void CyH4TransportDriver::assert_bt_dev_wake() @@ -154,7 +169,8 @@ void CyH4TransportDriver::assert_bt_dev_wake() void CyH4TransportDriver::deassert_bt_dev_wake() { #if (defined(MBED_TICKLESS) && DEVICE_SLEEP && DEVICE_LPTICKER) - //De-assert bt_device_wake + wait_us(5000); /* remove and replace when uart tx transmit complete api is available */ + //De-assert bt_device_wake if (dev_wake_irq_event == WAKE_EVENT_ACTIVE_LOW) { bt_device_wake = WAKE_EVENT_ACTIVE_HIGH; } else { @@ -163,6 +179,11 @@ void CyH4TransportDriver::deassert_bt_dev_wake() #endif } +void CyH4TransportDriver::update_uart_baud_rate(int baud) +{ + uart.baud(baud); +} + bool CyH4TransportDriver::get_enabled_powersave() { return (enabled_powersave); diff --git a/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CYW43XXX/CyH4TransportDriver.h b/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CYW43XXX/CyH4TransportDriver.h index 46b71148cca..9f0a64092bb 100644 --- a/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CYW43XXX/CyH4TransportDriver.h +++ b/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CYW43XXX/CyH4TransportDriver.h @@ -66,6 +66,12 @@ class CyH4TransportDriver : public cordio::CordioHCITransportDriver { void bt_host_wake_irq_handler(); +#if (defined(MBED_TICKLESS) && DEVICE_SLEEP && DEVICE_LPTICKER) + void on_host_stack_inactivity(); +#endif + + void update_uart_baud_rate(int baud); + bool get_enabled_powersave(); uint8_t get_host_wake_irq_event(); uint8_t get_dev_wake_irq_event(); @@ -101,6 +107,7 @@ class CyH4TransportDriver : public cordio::CordioHCITransportDriver { } // namespace ble #define DEF_BT_BAUD_RATE (115200) +#define DEF_BT_3M_BAUD_RATE (3000000) /* Both Host and BT device have to be adapt to this */ #define WAKE_EVENT_ACTIVE_HIGH ( 1 ) /* Interrupt Rising Edge */ #define WAKE_EVENT_ACTIVE_LOW ( 0 ) /* Interrupt Falling Edge */ diff --git a/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CYW43XXX/HCIDriver.cpp b/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CYW43XXX/HCIDriver.cpp index 5f7d82d17f0..cafdadf1a43 100644 --- a/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CYW43XXX/HCIDriver.cpp +++ b/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CYW43XXX/HCIDriver.cpp @@ -30,19 +30,27 @@ extern const int brcm_patch_ram_length; extern const uint8_t brcm_patchram_buf[]; static const uint8_t pre_brcm_patchram_buf[] = { - // RESET followed by download mini driver cmd + // RESET followed by update uart baudrate 0x03, 0x0C, 0x00, + 0x18, 0xFC, 0x06, 0x00, 0x00, 0xC0, 0xC6, 0x2D, 0x00, //update uart baudrate 3 mbp +}; + +static const uint8_t pre_brcm_patchram_buf2[] = { + //download mini driver 0x2E, 0xFC, 0x00, }; + static const uint8_t post_brcm_patchram_buf[] = { // RESET cmd 0x03, 0x0C, 0x00, }; static const int pre_brcm_patch_ram_length = sizeof(pre_brcm_patchram_buf); +static const int pre_brcm_patch_ram_length2 = sizeof(pre_brcm_patchram_buf2); static const int post_brcm_patch_ram_length = sizeof(post_brcm_patchram_buf); #define HCI_RESET_RAND_CNT 4 +#define HCI_VS_CMD_UPDATE_UART_BAUD_RATE 0xFC18 #define HCI_VS_CMD_SET_SLEEP_MODE 0xFC27 @@ -55,7 +63,7 @@ namespace cypress { class HCIDriver : public cordio::CordioHCIDriver { public: HCIDriver( - cordio::CordioHCITransportDriver& transport_driver, + ble::vendor::cypress_ble::CyH4TransportDriver& transport_driver, PinName bt_power_name, bool ps_enabled, uint8_t host_wake_irq, @@ -70,7 +78,8 @@ class HCIDriver : public cordio::CordioHCIDriver { service_pack_ptr(0), service_pack_length(0), service_pack_next(), - service_pack_transfered(false) { + service_pack_transfered(false), + cy_transport_driver(transport_driver) { } virtual cordio::buf_pool_desc_t get_buffer_pool_description() @@ -81,6 +90,9 @@ class HCIDriver : public cordio::CordioHCIDriver { virtual void do_initialize() { + //Prevent PSoC6 to enter deep-sleep till BT initialization is complete + sleep_manager_lock_deep_sleep(); + rtos::ThisThread::sleep_for(500); bt_power = 1; rtos::ThisThread::sleep_for(500); } @@ -113,6 +125,40 @@ class HCIDriver : public cordio::CordioHCIDriver { /* decode opcode */ switch (opcode) { + case HCI_VS_CMD_UPDATE_UART_BAUD_RATE: + cy_transport_driver.update_uart_baud_rate(DEF_BT_3M_BAUD_RATE); +#ifdef CY_DEBUG + HciReadLocalVerInfoCmd(); +#else + set_sleep_mode(); +#endif + break; + +#ifdef CY_DEBUG + case HCI_OPCODE_READ_LOCAL_VER_INFO: + uint8_t hci_version; + uint8_t hci_revision; + uint8_t lmp_revision; + uint16_t manufacturer_name; + + BSTREAM_TO_UINT8(hci_version, pMsg); + BSTREAM_TO_UINT8(hci_revision, pMsg); + BSTREAM_TO_UINT8(lmp_revision, pMsg); + BSTREAM_TO_UINT16(manufacturer_name, pMsg); + + if(hci_revision == 0 || manufacturer_name == 0xF) + { + printf("bt firmware download failed, rom code is being used\n"); + } + else + { + printf("bt firmware download success\n"); + } + + set_sleep_mode(); + break; +#endif + // Note: Reset is handled by ack_service_pack. case HCI_VS_CMD_SET_SLEEP_MODE: HciWriteLeHostSupport(); @@ -263,20 +309,40 @@ class HCIDriver : public cordio::CordioHCIDriver { } } +#if (defined(MBED_TICKLESS) && DEVICE_SLEEP && DEVICE_LPTICKER) + virtual void on_host_stack_inactivity(void) + { + cy_transport_driver.on_host_stack_inactivity(); + } +#endif + private: - // send pre_brcm_patchram_buf + // send pre_brcm_patchram_buf issue hci reset and update baud rate on 43012 void prepare_service_pack_transfert(void) { service_pack_ptr = pre_brcm_patchram_buf; service_pack_length = pre_brcm_patch_ram_length; + service_pack_next = &HCIDriver::prepare_service_pack_transfert2; + service_pack_index = 0; + service_pack_transfered = false; + send_service_pack_command(); + } + + // Called one pre_brcm_patchram_buf has been transferred; send pre_brcm_patchram_buf2 update uart baudrate + // on PSoC6 to send hci download minidriver + void prepare_service_pack_transfert2(void) + { + cy_transport_driver.update_uart_baud_rate(DEF_BT_3M_BAUD_RATE); + service_pack_ptr = pre_brcm_patchram_buf2; + service_pack_length = pre_brcm_patch_ram_length2; service_pack_next = &HCIDriver::start_service_pack_transfert; service_pack_index = 0; service_pack_transfered = false; send_service_pack_command(); } - // Called once pre_brcm_patchram_buf has been transferred; send brcm_patchram_buf + // Called once pre_brcm_patchram_buf2 has been transferred; send brcm_patchram_buf void start_service_pack_transfert(void) { service_pack_ptr = brcm_patchram_buf; @@ -290,6 +356,7 @@ class HCIDriver : public cordio::CordioHCIDriver { // Called once brcm_patchram_buf has been transferred; send post_brcm_patchram_buf void post_service_pack_transfert(void) { + cy_transport_driver.update_uart_baud_rate(DEF_BT_BAUD_RATE); service_pack_ptr = post_brcm_patchram_buf; service_pack_length = post_brcm_patch_ram_length; service_pack_next = &HCIDriver::terminate_service_pack_transfert;; @@ -307,7 +374,8 @@ class HCIDriver : public cordio::CordioHCIDriver { service_pack_next = NULL; service_pack_index = 0; service_pack_transfered = true; - set_sleep_mode(); + HciUpdateUartBaudRate(); + sleep_manager_unlock_deep_sleep(); } void send_service_pack_command(void) @@ -354,7 +422,11 @@ class HCIDriver : public cordio::CordioHCIDriver { pBuf[HCI_CMD_HDR_LEN] = 0x00; // no sleep } pBuf[HCI_CMD_HDR_LEN + 1] = 0x00; // no idle threshold host (N/A) - pBuf[HCI_CMD_HDR_LEN + 2] = 0x00; // no idle threshold HC (N/A) + if (is_powersave_on()) { + pBuf[HCI_CMD_HDR_LEN + 2] = 0x05; // no idle threshold HC (N/A) + } else { + pBuf[HCI_CMD_HDR_LEN + 2] = 0x00; // no idle threshold HC (N/A) + } if (is_powersave_on()) { pBuf[HCI_CMD_HDR_LEN + 3] = dev_wake_irq; // BT WAKE } else { @@ -363,7 +435,7 @@ class HCIDriver : public cordio::CordioHCIDriver { if (is_powersave_on()) { pBuf[HCI_CMD_HDR_LEN + 4] = host_wake_irq; // HOST WAKE } else { - pBuf[HCI_CMD_HDR_LEN + 3] = 0x00; // BT WAKE + pBuf[HCI_CMD_HDR_LEN + 4] = 0x00; // HOST WAKE } pBuf[HCI_CMD_HDR_LEN + 5] = 0x00; // Sleep during SCO pBuf[HCI_CMD_HDR_LEN + 6] = 0x00; // Combining sleep mode and SCM @@ -371,7 +443,23 @@ class HCIDriver : public cordio::CordioHCIDriver { pBuf[HCI_CMD_HDR_LEN + 8] = 0x00; // Active connection handling on suspend pBuf[HCI_CMD_HDR_LEN + 9] = 0x00; // resume timeout pBuf[HCI_CMD_HDR_LEN + 10] = 0x00; // break to host - pBuf[HCI_CMD_HDR_LEN + 10] = 0x00; // Pulsed host wake + pBuf[HCI_CMD_HDR_LEN + 11] = 0x00; // Pulsed host wake + hciCmdSend(pBuf); + } + } + + // 0x18, 0xFC, 0x06, 0x00, 0x00, 0xC0, 0xC6, 0x2D, 0x00, //update uart baudrate 3 mbp + void HciUpdateUartBaudRate() + { + uint8_t *pBuf; + if ((pBuf = hciCmdAlloc(HCI_VS_CMD_UPDATE_UART_BAUD_RATE, 6)) != NULL) + { + pBuf[HCI_CMD_HDR_LEN] = 0x00; // encoded_baud_rate + pBuf[HCI_CMD_HDR_LEN + 1] = 0x00; // use_encoded_form + pBuf[HCI_CMD_HDR_LEN + 2] = 0xC0; // explicit baud rate bit 0-7 + pBuf[HCI_CMD_HDR_LEN + 3] = 0xC6; // explicit baud rate bit 8-15 + pBuf[HCI_CMD_HDR_LEN + 4] = 0x2D; // explicit baud rate bit 16-23 + pBuf[HCI_CMD_HDR_LEN + 5] = 0x00; // explicit baud rate bit 24-31 hciCmdSend(pBuf); } } @@ -440,6 +528,7 @@ class HCIDriver : public cordio::CordioHCIDriver { int service_pack_length; void (HCIDriver::*service_pack_next)(); bool service_pack_transfered; + ble::vendor::cypress_ble::CyH4TransportDriver& cy_transport_driver; }; From 8bd35cc039c5104aae27ddc4bdf9dafc67d7fa1a Mon Sep 17 00:00:00 2001 From: Mukund Ghonasgi Date: Mon, 23 Sep 2019 11:29:57 -0700 Subject: [PATCH 150/227] Update Cordio BT Driver to support without BT Device Wake and Host Wake pins defined. --- .../TARGET_CYW43XXX/CyH4TransportDriver.cpp | 43 +++++++++++-------- 1 file changed, 26 insertions(+), 17 deletions(-) diff --git a/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CYW43XXX/CyH4TransportDriver.cpp b/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CYW43XXX/CyH4TransportDriver.cpp index a5a177fcb0c..bbfe456b444 100644 --- a/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CYW43XXX/CyH4TransportDriver.cpp +++ b/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CYW43XXX/CyH4TransportDriver.cpp @@ -93,12 +93,14 @@ void CyH4TransportDriver::initialize() ); #if (defined(MBED_TICKLESS) && DEVICE_SLEEP && DEVICE_LPTICKER) - //Register IRQ for Host WAKE - host_wake_pin = new InterruptIn(bt_host_wake_name); - if (host_wake_irq_event == WAKE_EVENT_ACTIVE_LOW) { - host_wake_pin->fall(callback(this, &CyH4TransportDriver::bt_host_wake_irq_handler)); - } else { - host_wake_pin->rise(callback(this, &CyH4TransportDriver::bt_host_wake_irq_handler)); + if (bt_host_wake_name != NC) { + //Register IRQ for Host WAKE + host_wake_pin = new InterruptIn(bt_host_wake_name); + if (host_wake_irq_event == WAKE_EVENT_ACTIVE_LOW) { + host_wake_pin->fall(callback(this, &CyH4TransportDriver::bt_host_wake_irq_handler)); + } else { + host_wake_pin->rise(callback(this, &CyH4TransportDriver::bt_host_wake_irq_handler)); + } } #endif @@ -137,7 +139,9 @@ uint16_t CyH4TransportDriver::write(uint8_t type, uint16_t len, uint8_t *pData) #if (defined(MBED_TICKLESS) && DEVICE_SLEEP && DEVICE_LPTICKER) void CyH4TransportDriver::on_host_stack_inactivity() { - uart.attach(NULL, SerialBase::RxIrq); + if (enabled_powersave) { + uart.attach(NULL, SerialBase::RxIrq); + } } #endif @@ -158,10 +162,12 @@ void CyH4TransportDriver::on_controller_irq() void CyH4TransportDriver::assert_bt_dev_wake() { #if (defined(MBED_TICKLESS) && DEVICE_SLEEP && DEVICE_LPTICKER) - if (dev_wake_irq_event == WAKE_EVENT_ACTIVE_LOW) { - bt_device_wake = WAKE_EVENT_ACTIVE_LOW; - } else { - bt_device_wake = WAKE_EVENT_ACTIVE_HIGH; + if (enabled_powersave) { + if (dev_wake_irq_event == WAKE_EVENT_ACTIVE_LOW) { + bt_device_wake = WAKE_EVENT_ACTIVE_LOW; + } else { + bt_device_wake = WAKE_EVENT_ACTIVE_HIGH; + } } #endif } @@ -169,16 +175,19 @@ void CyH4TransportDriver::assert_bt_dev_wake() void CyH4TransportDriver::deassert_bt_dev_wake() { #if (defined(MBED_TICKLESS) && DEVICE_SLEEP && DEVICE_LPTICKER) - wait_us(5000); /* remove and replace when uart tx transmit complete api is available */ - //De-assert bt_device_wake - if (dev_wake_irq_event == WAKE_EVENT_ACTIVE_LOW) { - bt_device_wake = WAKE_EVENT_ACTIVE_HIGH; - } else { - bt_device_wake = WAKE_EVENT_ACTIVE_LOW; + if (enabled_powersave) { + wait_us(5000); /* remove and replace when uart tx transmit complete api is available */ + //De-assert bt_device_wake + if (dev_wake_irq_event == WAKE_EVENT_ACTIVE_LOW) { + bt_device_wake = WAKE_EVENT_ACTIVE_HIGH; + } else { + bt_device_wake = WAKE_EVENT_ACTIVE_LOW; + } } #endif } + void CyH4TransportDriver::update_uart_baud_rate(int baud) { uart.baud(baud); From 1eb85aefaba1e094fa6ea2d1ba22e453c0bb7d57 Mon Sep 17 00:00:00 2001 From: Mukund Ghonasgi Date: Tue, 24 Sep 2019 16:49:54 -0700 Subject: [PATCH 151/227] Adapt to Target that don't support 3M BT Uart Baud --- .../TARGET_CYW43XXX/CyH4TransportDriver.h | 4 ++++ .../TARGET_CYW43XXX/HCIDriver.cpp | 17 ++++++++++++++++- 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CYW43XXX/CyH4TransportDriver.h b/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CYW43XXX/CyH4TransportDriver.h index 9f0a64092bb..da94932481f 100644 --- a/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CYW43XXX/CyH4TransportDriver.h +++ b/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CYW43XXX/CyH4TransportDriver.h @@ -112,6 +112,10 @@ class CyH4TransportDriver : public cordio::CordioHCITransportDriver { #define WAKE_EVENT_ACTIVE_HIGH ( 1 ) /* Interrupt Rising Edge */ #define WAKE_EVENT_ACTIVE_LOW ( 0 ) /* Interrupt Falling Edge */ +#if (defined(TARGET_CY8CPROTO_062_4343W)) +#define BT_UART_NO_3M_SUPPORT ( 1 ) +#endif + ble::vendor::cypress_ble::CyH4TransportDriver& ble_cordio_get_default_h4_transport_driver(); ble::vendor::cypress_ble::CyH4TransportDriver& ble_cordio_get_h4_transport_driver(); #endif diff --git a/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CYW43XXX/HCIDriver.cpp b/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CYW43XXX/HCIDriver.cpp index cafdadf1a43..2c1d941f83c 100644 --- a/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CYW43XXX/HCIDriver.cpp +++ b/features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CYW43XXX/HCIDriver.cpp @@ -29,11 +29,18 @@ extern const int brcm_patch_ram_length; extern const uint8_t brcm_patchram_buf[]; +#ifndef BT_UART_NO_3M_SUPPORT static const uint8_t pre_brcm_patchram_buf[] = { // RESET followed by update uart baudrate 0x03, 0x0C, 0x00, 0x18, 0xFC, 0x06, 0x00, 0x00, 0xC0, 0xC6, 0x2D, 0x00, //update uart baudrate 3 mbp }; +#else /* BT_UART_NO_3M_SUPPORT */ +static const uint8_t pre_brcm_patchram_buf[] = { + // RESET cmd + 0x03, 0x0C, 0x00, +}; +#endif /* BT_UART_NO_3M_SUPPORT */ static const uint8_t pre_brcm_patchram_buf2[] = { //download mini driver @@ -126,7 +133,9 @@ class HCIDriver : public cordio::CordioHCIDriver { /* decode opcode */ switch (opcode) { case HCI_VS_CMD_UPDATE_UART_BAUD_RATE: +#ifndef BT_UART_NO_3M_SUPPORT cy_transport_driver.update_uart_baud_rate(DEF_BT_3M_BAUD_RATE); +#endif /* BT_UART_NO_3M_SUPPORT */ #ifdef CY_DEBUG HciReadLocalVerInfoCmd(); #else @@ -333,9 +342,11 @@ class HCIDriver : public cordio::CordioHCIDriver { // on PSoC6 to send hci download minidriver void prepare_service_pack_transfert2(void) { +#ifndef BT_UART_NO_3M_SUPPORT cy_transport_driver.update_uart_baud_rate(DEF_BT_3M_BAUD_RATE); +#endif /* BT_UART_NO_3M_SUPPORT */ service_pack_ptr = pre_brcm_patchram_buf2; - service_pack_length = pre_brcm_patch_ram_length2; + service_pack_length = pre_brcm_patch_ram_length2; service_pack_next = &HCIDriver::start_service_pack_transfert; service_pack_index = 0; service_pack_transfered = false; @@ -374,7 +385,11 @@ class HCIDriver : public cordio::CordioHCIDriver { service_pack_next = NULL; service_pack_index = 0; service_pack_transfered = true; +#ifndef BT_UART_NO_3M_SUPPORT HciUpdateUartBaudRate(); +#else /* BT_UART_NO_3M_SUPPORT */ + set_sleep_mode(); +#endif /* BT_UART_NO_3M_SUPPORT */ sleep_manager_unlock_deep_sleep(); } From c9c7dbbaf057a1e1709fada13625a26cebc0b28e Mon Sep 17 00:00:00 2001 From: Filip Jagodzinski Date: Mon, 16 Sep 2019 10:37:29 +0200 Subject: [PATCH 152/227] Tests: USB: Clean up test failure output Catch all pyusb errors and report failures to the device. Printing full tracebacks was more confusing than useful. --- TESTS/host_tests/pyusb_basic.py | 102 +++++++++++++++++++++++++++----- 1 file changed, 87 insertions(+), 15 deletions(-) diff --git a/TESTS/host_tests/pyusb_basic.py b/TESTS/host_tests/pyusb_basic.py index dc724ffaed4..2d221ead39b 100644 --- a/TESTS/host_tests/pyusb_basic.py +++ b/TESTS/host_tests/pyusb_basic.py @@ -1,6 +1,6 @@ """ mbed SDK -Copyright (c) 2018-2018 ARM Limited +Copyright (c) 2018-2019 ARM Limited SPDX-License-Identifier: Apache-2.0 Licensed under the Apache License, Version 2.0 (the "License"); @@ -26,6 +26,7 @@ import array import random import os +import traceback import usb.core from usb.util import build_request_type @@ -122,6 +123,35 @@ def get_interface(dev, interface, alternate=0): usb.ENDPOINT_TYPE_INTERRUPT: 'INTERRUPT', usb.ENDPOINT_TYPE_ISOCHRONOUS: 'ISOCHRONOUS'} +def format_local_error_msg(fmt): + """Return an error message formatted with the last traceback entry from this file. + + The message is formatted according to fmt with data from the last traceback + enrty internal to this file. There are 4 arguments supplied to the format + function: filename, line_number, exc_type and exc_value. + + Returns None if formatting fails. + """ + try: + exc_type, exc_value, exc_traceback = sys.exc_info() + # A list of 4-tuples (filename, line_number, function_name, text). + tb_entries = traceback.extract_tb(exc_traceback) + # Reuse the filename from the first tuple instead of relying on __file__: + # 1. No need for path handling. + # 2. No need for file extension handling (i.e. .py vs .pyc). + name_of_this_file = tb_entries[0][0] + last_internal_tb_entry = [tb for tb in tb_entries if tb[0] == name_of_this_file][-1] + msg = fmt.format( + filename=last_internal_tb_entry[0], + line_number=last_internal_tb_entry[1], + exc_type=str(exc_type).strip(), + exc_value=str(exc_value).strip(), + ) + except (IndexError, KeyError): + msg = None + return msg + + class PyusbBasicTest(BaseHostTest): def _callback_control_basic_test(self, key, value, timestamp): @@ -137,8 +167,11 @@ def _callback_control_basic_test(self, key, value, timestamp): try: control_basic_test(dev, int(vendor_id), int(product_id), log=print) self.report_success() - except (RuntimeError) as exc: + except RuntimeError as exc: self.report_error(exc) + except usb.core.USBError as exc: + error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') + self.report_error(error_msg if error_msg is not None else exc) def _callback_control_stall_test(self, key, value, timestamp): @@ -151,8 +184,11 @@ def _callback_control_stall_test(self, key, value, timestamp): try: control_stall_test(dev, log=print) self.report_success() - except (RuntimeError) as exc: + except RuntimeError as exc: self.report_error(exc) + except usb.core.USBError as exc: + error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') + self.report_error(error_msg if error_msg is not None else exc) def _callback_control_sizes_test(self, key, value, timestamp): @@ -165,8 +201,11 @@ def _callback_control_sizes_test(self, key, value, timestamp): try: control_sizes_test(dev, log=print) self.report_success() - except (RuntimeError) as exc: + except RuntimeError as exc: self.report_error(exc) + except usb.core.USBError as exc: + error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') + self.report_error(error_msg if error_msg is not None else exc) def _callback_control_stress_test(self, key, value, timestamp): @@ -179,8 +218,11 @@ def _callback_control_stress_test(self, key, value, timestamp): try: control_stress_test(dev, log=print) self.report_success() - except (RuntimeError) as exc: + except RuntimeError as exc: self.report_error(exc) + except usb.core.USBError as exc: + error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') + self.report_error(error_msg if error_msg is not None else exc) def _callback_device_reset_test(self, key, value, timestamp): self.log("Received serial %s" % (value)) @@ -192,8 +234,11 @@ def _callback_device_reset_test(self, key, value, timestamp): try: self.device_reset_test.send(dev) self.report_success() - except (RuntimeError) as exc: + except RuntimeError as exc: self.report_error(exc) + except usb.core.USBError as exc: + error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') + self.report_error(error_msg if error_msg is not None else exc) def _callback_device_soft_reconnection_test(self, key, value, timestamp): self.log("Received serial %s" % (value)) @@ -205,8 +250,11 @@ def _callback_device_soft_reconnection_test(self, key, value, timestamp): try: self.device_soft_reconnection_test.send(dev) self.report_success() - except (RuntimeError) as exc: + except RuntimeError as exc: self.report_error(exc) + except usb.core.USBError as exc: + error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') + self.report_error(error_msg if error_msg is not None else exc) def _callback_device_suspend_resume_test(self, key, value, timestamp): @@ -219,8 +267,11 @@ def _callback_device_suspend_resume_test(self, key, value, timestamp): try: self.device_suspend_resume_test.send(dev) self.report_success() - except (RuntimeError) as exc: + except RuntimeError as exc: self.report_error(exc) + except usb.core.USBError as exc: + error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') + self.report_error(error_msg if error_msg is not None else exc) def _callback_repeated_construction_destruction_test(self, key, value, timestamp): @@ -233,8 +284,11 @@ def _callback_repeated_construction_destruction_test(self, key, value, timestamp try: self.repeated_construction_destruction_test.send(dev) self.report_success() - except (RuntimeError) as exc: + except RuntimeError as exc: self.report_error(exc) + except usb.core.USBError as exc: + error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') + self.report_error(error_msg if error_msg is not None else exc) def _callback_ep_test_data_correctness(self, key, value, timestamp): self.log("Received serial %s" % (value)) @@ -246,8 +300,11 @@ def _callback_ep_test_data_correctness(self, key, value, timestamp): try: ep_test_data_correctness(dev, log=print) self.report_success() - except (RuntimeError) as exc: + except RuntimeError as exc: self.report_error(exc) + except usb.core.USBError as exc: + error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') + self.report_error(error_msg if error_msg is not None else exc) def _callback_ep_test_halt(self, key, value, timestamp): self.log("Received serial %s" % (value)) @@ -259,8 +316,11 @@ def _callback_ep_test_halt(self, key, value, timestamp): try: ep_test_halt(dev, log=print) self.report_success() - except (RuntimeError) as exc: + except RuntimeError as exc: self.report_error(exc) + except usb.core.USBError as exc: + error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') + self.report_error(error_msg if error_msg is not None else exc) def _callback_ep_test_parallel_transfers(self, key, value, timestamp): self.log("Received serial %s" % (value)) @@ -272,8 +332,11 @@ def _callback_ep_test_parallel_transfers(self, key, value, timestamp): try: ep_test_parallel_transfers(dev, log=print) self.report_success() - except (RuntimeError) as exc: + except RuntimeError as exc: self.report_error(exc) + except usb.core.USBError as exc: + error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') + self.report_error(error_msg if error_msg is not None else exc) def _callback_ep_test_parallel_transfers_ctrl(self, key, value, timestamp): self.log("Received serial %s" % (value)) @@ -285,8 +348,11 @@ def _callback_ep_test_parallel_transfers_ctrl(self, key, value, timestamp): try: ep_test_parallel_transfers_ctrl(dev, log=print) self.report_success() - except (RuntimeError) as exc: + except RuntimeError as exc: self.report_error(exc) + except usb.core.USBError as exc: + error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') + self.report_error(error_msg if error_msg is not None else exc) def _callback_ep_test_abort(self, key, value, timestamp): self.log("Received serial %s" % (value)) @@ -298,8 +364,11 @@ def _callback_ep_test_abort(self, key, value, timestamp): try: ep_test_abort(dev, log=print) self.report_success() - except (RuntimeError) as exc: + except RuntimeError as exc: self.report_error(exc) + except usb.core.USBError as exc: + error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') + self.report_error(error_msg if error_msg is not None else exc) def _callback_ep_test_data_toggle(self, key, value, timestamp): self.log("Received serial %s" % (value)) @@ -311,8 +380,11 @@ def _callback_ep_test_data_toggle(self, key, value, timestamp): try: ep_test_data_toggle(dev, log=print) self.report_success() - except (RuntimeError) as exc: + except RuntimeError as exc: self.report_error(exc) + except usb.core.USBError as exc: + error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') + self.report_error(error_msg if error_msg is not None else exc) def _callback_reset_support(self, key, value, timestamp): status = "false" if sys.platform == "darwin" else "true" From 11dc3d2f7821dfecf833e646425f135df5b2ddd4 Mon Sep 17 00:00:00 2001 From: Filip Jagodzinski Date: Mon, 16 Sep 2019 12:29:49 +0200 Subject: [PATCH 153/227] Tests: USB: Distinguish failure/error in basic test --- TESTS/host_tests/pyusb_basic.py | 155 +++++++++++++++++++------------- 1 file changed, 91 insertions(+), 64 deletions(-) diff --git a/TESTS/host_tests/pyusb_basic.py b/TESTS/host_tests/pyusb_basic.py index 2d221ead39b..3a42f5681ae 100644 --- a/TESTS/host_tests/pyusb_basic.py +++ b/TESTS/host_tests/pyusb_basic.py @@ -123,6 +123,12 @@ def get_interface(dev, interface, alternate=0): usb.ENDPOINT_TYPE_INTERRUPT: 'INTERRUPT', usb.ENDPOINT_TYPE_ISOCHRONOUS: 'ISOCHRONOUS'} +# Greentea message keys used to notify DUT of test status +MSG_KEY_TEST_CASE_FAILED = 'fail' +MSG_KEY_TEST_CASE_PASSED = 'pass' +MSG_VALUE_DUMMY = '0' + + def format_local_error_msg(fmt): """Return an error message formatted with the last traceback entry from this file. @@ -161,230 +167,244 @@ def _callback_control_basic_test(self, key, value, timestamp): self.log("Received product_id %s" % (product_id)) dev = self.find_device(serial_number) - if(dev == None): + if dev is None: + self.notify_error('USB device (SN={}) not found.'.format(serial_number)) return try: control_basic_test(dev, int(vendor_id), int(product_id), log=print) - self.report_success() + self.notify_success() except RuntimeError as exc: - self.report_error(exc) + self.notify_failure(exc) except usb.core.USBError as exc: error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') - self.report_error(error_msg if error_msg is not None else exc) + self.notify_failure(error_msg if error_msg is not None else exc) def _callback_control_stall_test(self, key, value, timestamp): self.log("Received serial %s" % (value)) dev = self.find_device(value) - if(dev == None): + if dev is None: + self.notify_error('USB device (SN={}) not found.'.format(value)) return try: control_stall_test(dev, log=print) - self.report_success() + self.notify_success() except RuntimeError as exc: - self.report_error(exc) + self.notify_failure(exc) except usb.core.USBError as exc: error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') - self.report_error(error_msg if error_msg is not None else exc) + self.notify_failure(error_msg if error_msg is not None else exc) def _callback_control_sizes_test(self, key, value, timestamp): self.log("Received serial %s" % (value)) dev = self.find_device(value) - if(dev == None): + if dev is None: + self.notify_error('USB device (SN={}) not found.'.format(value)) return try: control_sizes_test(dev, log=print) - self.report_success() + self.notify_success() except RuntimeError as exc: - self.report_error(exc) + self.notify_failure(exc) except usb.core.USBError as exc: error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') - self.report_error(error_msg if error_msg is not None else exc) + self.notify_failure(error_msg if error_msg is not None else exc) def _callback_control_stress_test(self, key, value, timestamp): self.log("Received serial %s" % (value)) dev = self.find_device(value) - if(dev == None): + if dev is None: + self.notify_error('USB device (SN={}) not found.'.format(value)) return try: control_stress_test(dev, log=print) - self.report_success() + self.notify_success() except RuntimeError as exc: - self.report_error(exc) + self.notify_failure(exc) except usb.core.USBError as exc: error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') - self.report_error(error_msg if error_msg is not None else exc) + self.notify_failure(error_msg if error_msg is not None else exc) def _callback_device_reset_test(self, key, value, timestamp): self.log("Received serial %s" % (value)) dev = self.find_device(value) - if(dev == None): + if dev is None: + self.notify_error('USB device (SN={}) not found.'.format(value)) return try: self.device_reset_test.send(dev) - self.report_success() + self.notify_success() except RuntimeError as exc: - self.report_error(exc) + self.notify_failure(exc) except usb.core.USBError as exc: error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') - self.report_error(error_msg if error_msg is not None else exc) + self.notify_failure(error_msg if error_msg is not None else exc) def _callback_device_soft_reconnection_test(self, key, value, timestamp): self.log("Received serial %s" % (value)) dev = self.find_device(value) - if(dev == None): + if dev is None: + self.notify_error('USB device (SN={}) not found.'.format(value)) return try: self.device_soft_reconnection_test.send(dev) - self.report_success() + self.notify_success() except RuntimeError as exc: - self.report_error(exc) + self.notify_failure(exc) except usb.core.USBError as exc: error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') - self.report_error(error_msg if error_msg is not None else exc) + self.notify_failure(error_msg if error_msg is not None else exc) def _callback_device_suspend_resume_test(self, key, value, timestamp): self.log("Received serial %s" % (value)) dev = self.find_device(value) - if(dev == None): + if dev is None: + self.notify_error('USB device (SN={}) not found.'.format(value)) return try: self.device_suspend_resume_test.send(dev) - self.report_success() + self.notify_success() except RuntimeError as exc: - self.report_error(exc) + self.notify_failure(exc) except usb.core.USBError as exc: error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') - self.report_error(error_msg if error_msg is not None else exc) + self.notify_failure(error_msg if error_msg is not None else exc) def _callback_repeated_construction_destruction_test(self, key, value, timestamp): self.log("Received serial %s" % (value)) dev = self.find_device(value) - if(dev == None): + if dev is None: + self.notify_error('USB device (SN={}) not found.'.format(value)) return try: self.repeated_construction_destruction_test.send(dev) - self.report_success() + self.notify_success() except RuntimeError as exc: - self.report_error(exc) + self.notify_failure(exc) except usb.core.USBError as exc: error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') - self.report_error(error_msg if error_msg is not None else exc) + self.notify_failure(error_msg if error_msg is not None else exc) def _callback_ep_test_data_correctness(self, key, value, timestamp): self.log("Received serial %s" % (value)) dev = self.find_device(value) - if(dev == None): + if dev is None: + self.notify_error('USB device (SN={}) not found.'.format(value)) return try: ep_test_data_correctness(dev, log=print) - self.report_success() + self.notify_success() except RuntimeError as exc: - self.report_error(exc) + self.notify_failure(exc) except usb.core.USBError as exc: error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') - self.report_error(error_msg if error_msg is not None else exc) + self.notify_failure(error_msg if error_msg is not None else exc) def _callback_ep_test_halt(self, key, value, timestamp): self.log("Received serial %s" % (value)) dev = self.find_device(value) - if(dev == None): + if dev is None: + self.notify_error('USB device (SN={}) not found.'.format(value)) return try: ep_test_halt(dev, log=print) - self.report_success() + self.notify_success() except RuntimeError as exc: - self.report_error(exc) + self.notify_failure(exc) except usb.core.USBError as exc: error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') - self.report_error(error_msg if error_msg is not None else exc) + self.notify_failure(error_msg if error_msg is not None else exc) def _callback_ep_test_parallel_transfers(self, key, value, timestamp): self.log("Received serial %s" % (value)) dev = self.find_device(value) - if(dev == None): + if dev is None: + self.notify_error('USB device (SN={}) not found.'.format(value)) return try: ep_test_parallel_transfers(dev, log=print) - self.report_success() + self.notify_success() except RuntimeError as exc: - self.report_error(exc) + self.notify_failure(exc) except usb.core.USBError as exc: error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') - self.report_error(error_msg if error_msg is not None else exc) + self.notify_failure(error_msg if error_msg is not None else exc) def _callback_ep_test_parallel_transfers_ctrl(self, key, value, timestamp): self.log("Received serial %s" % (value)) dev = self.find_device(value) - if(dev == None): + if dev is None: + self.notify_error('USB device (SN={}) not found.'.format(value)) return try: ep_test_parallel_transfers_ctrl(dev, log=print) - self.report_success() + self.notify_success() except RuntimeError as exc: - self.report_error(exc) + self.notify_failure(exc) except usb.core.USBError as exc: error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') - self.report_error(error_msg if error_msg is not None else exc) + self.notify_failure(error_msg if error_msg is not None else exc) def _callback_ep_test_abort(self, key, value, timestamp): self.log("Received serial %s" % (value)) dev = self.find_device(value) - if(dev == None): + if dev is None: + self.notify_error('USB device (SN={}) not found.'.format(value)) return try: ep_test_abort(dev, log=print) - self.report_success() + self.notify_success() except RuntimeError as exc: - self.report_error(exc) + self.notify_failure(exc) except usb.core.USBError as exc: error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') - self.report_error(error_msg if error_msg is not None else exc) + self.notify_failure(error_msg if error_msg is not None else exc) def _callback_ep_test_data_toggle(self, key, value, timestamp): self.log("Received serial %s" % (value)) dev = self.find_device(value) - if(dev == None): + if dev is None: + self.notify_error('USB device (SN={}) not found.'.format(value)) return try: ep_test_data_toggle(dev, log=print) - self.report_success() + self.notify_success() except RuntimeError as exc: - self.report_error(exc) + self.notify_failure(exc) except usb.core.USBError as exc: error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') - self.report_error(error_msg if error_msg is not None else exc) + self.notify_failure(error_msg if error_msg is not None else exc) def _callback_reset_support(self, key, value, timestamp): status = "false" if sys.platform == "darwin" else "true" @@ -398,18 +418,25 @@ def find_device(self, serial_number): if dev is not None: break time.sleep(0.1) - if dev is None: - self.log("Device not found") - self.send_kv("failed", "0") return dev + def notify_success(self, value=None, msg=''): + """Report a host side test success to the DUT.""" + if msg: + self.log('TEST PASSED: {}'.format(msg)) + if value is None: + value = MSG_VALUE_DUMMY + self.send_kv(MSG_KEY_TEST_CASE_PASSED, value) - def report_success(self): - self.send_kv("pass", "0") - - def report_error(self, msg): + def notify_failure(self, msg): + """Report a host side test failure to the DUT.""" self.log('TEST FAILED: {}'.format(msg)) - self.send_kv("failed", "0") + self.send_kv(MSG_KEY_TEST_CASE_FAILED, MSG_VALUE_DUMMY) + + def notify_error(self, msg): + """Terminate the test with an error msg.""" + self.log('TEST ERROR: {}'.format(msg)) + self.notify_complete(None) def setup(self): self.__result = False From 85c495f451e2e76360997311f4c6d2da52b2c502 Mon Sep 17 00:00:00 2001 From: Filip Jagodzinski Date: Mon, 16 Sep 2019 13:39:22 +0200 Subject: [PATCH 154/227] Tests: USB: Extract common code in basic test --- TESTS/host_tests/pyusb_basic.py | 301 ++++++++++---------------------- 1 file changed, 91 insertions(+), 210 deletions(-) diff --git a/TESTS/host_tests/pyusb_basic.py b/TESTS/host_tests/pyusb_basic.py index 3a42f5681ae..ffec33558aa 100644 --- a/TESTS/host_tests/pyusb_basic.py +++ b/TESTS/host_tests/pyusb_basic.py @@ -160,19 +160,21 @@ def format_local_error_msg(fmt): class PyusbBasicTest(BaseHostTest): - def _callback_control_basic_test(self, key, value, timestamp): - serial_number, vendor_id, product_id = value.split(' ') - self.log("Received serial %s" % (serial_number)) - self.log("Received vendor_id %s" % (vendor_id)) - self.log("Received product_id %s" % (product_id)) - - dev = self.find_device(serial_number) - if dev is None: - self.notify_error('USB device (SN={}) not found.'.format(serial_number)) + def test_usb_device(self, usb_dev_serial_number, test_fun, **test_fun_kwargs): + """Find a USB device and execute a testing function. + + Search is based on usb_dev_serial_number. If the device is found, the + test_fun is executed with its dev argument set to the device found and + all other kwargs set as specified by test_fun_kwargs. + + The DUT is notified with either success, failure or error status. + """ + usb_device = self.find_device(usb_dev_serial_number) + if usb_device is None: + self.notify_error('USB device (SN={}) not found.'.format(usb_dev_serial_number)) return - try: - control_basic_test(dev, int(vendor_id), int(product_id), log=print) + test_fun(usb_device, **test_fun_kwargs) self.notify_success() except RuntimeError as exc: self.notify_failure(exc) @@ -180,231 +182,110 @@ def _callback_control_basic_test(self, key, value, timestamp): error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') self.notify_failure(error_msg if error_msg is not None else exc) + def _callback_control_basic_test(self, key, value, timestamp): + serial_number, vendor_id, product_id = value.split(' ') + self.test_usb_device( + usb_dev_serial_number=serial_number, + test_fun=control_basic_test, + log=print, + vendor_id=int(vendor_id), + product_id=int(product_id) + ) def _callback_control_stall_test(self, key, value, timestamp): - self.log("Received serial %s" % (value)) - - dev = self.find_device(value) - if dev is None: - self.notify_error('USB device (SN={}) not found.'.format(value)) - return - - try: - control_stall_test(dev, log=print) - self.notify_success() - except RuntimeError as exc: - self.notify_failure(exc) - except usb.core.USBError as exc: - error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') - self.notify_failure(error_msg if error_msg is not None else exc) - + self.test_usb_device( + usb_dev_serial_number=value, + test_fun=control_stall_test, + log=print + ) def _callback_control_sizes_test(self, key, value, timestamp): - self.log("Received serial %s" % (value)) - - dev = self.find_device(value) - if dev is None: - self.notify_error('USB device (SN={}) not found.'.format(value)) - return - - try: - control_sizes_test(dev, log=print) - self.notify_success() - except RuntimeError as exc: - self.notify_failure(exc) - except usb.core.USBError as exc: - error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') - self.notify_failure(error_msg if error_msg is not None else exc) - + self.test_usb_device( + usb_dev_serial_number=value, + test_fun=control_sizes_test, + log=print + ) def _callback_control_stress_test(self, key, value, timestamp): - self.log("Received serial %s" % (value)) - - dev = self.find_device(value) - if dev is None: - self.notify_error('USB device (SN={}) not found.'.format(value)) - return - - try: - control_stress_test(dev, log=print) - self.notify_success() - except RuntimeError as exc: - self.notify_failure(exc) - except usb.core.USBError as exc: - error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') - self.notify_failure(error_msg if error_msg is not None else exc) + self.test_usb_device( + usb_dev_serial_number=value, + test_fun=control_stress_test, + log=print + ) def _callback_device_reset_test(self, key, value, timestamp): - self.log("Received serial %s" % (value)) - - dev = self.find_device(value) - if dev is None: - self.notify_error('USB device (SN={}) not found.'.format(value)) - return - - try: - self.device_reset_test.send(dev) - self.notify_success() - except RuntimeError as exc: - self.notify_failure(exc) - except usb.core.USBError as exc: - error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') - self.notify_failure(error_msg if error_msg is not None else exc) + self.test_usb_device( + usb_dev_serial_number=value, + # Advance the coroutine to the next yield statement + # and send the usb_device to use. + test_fun=self.device_reset_test.send + ) def _callback_device_soft_reconnection_test(self, key, value, timestamp): - self.log("Received serial %s" % (value)) - - dev = self.find_device(value) - if dev is None: - self.notify_error('USB device (SN={}) not found.'.format(value)) - return - - try: - self.device_soft_reconnection_test.send(dev) - self.notify_success() - except RuntimeError as exc: - self.notify_failure(exc) - except usb.core.USBError as exc: - error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') - self.notify_failure(error_msg if error_msg is not None else exc) - + self.test_usb_device( + usb_dev_serial_number=value, + # Advance the coroutine to the next yield statement + # and send the usb_device to use. + test_fun=self.device_soft_reconnection_test.send + ) def _callback_device_suspend_resume_test(self, key, value, timestamp): - self.log("Received serial %s" % (value)) - - dev = self.find_device(value) - if dev is None: - self.notify_error('USB device (SN={}) not found.'.format(value)) - return - - try: - self.device_suspend_resume_test.send(dev) - self.notify_success() - except RuntimeError as exc: - self.notify_failure(exc) - except usb.core.USBError as exc: - error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') - self.notify_failure(error_msg if error_msg is not None else exc) - + self.test_usb_device( + usb_dev_serial_number=value, + # Advance the coroutine to the next yield statement + # and send the usb_device to use. + test_fun=self.device_suspend_resume_test.send + ) def _callback_repeated_construction_destruction_test(self, key, value, timestamp): - self.log("Received serial %s" % (value)) - - dev = self.find_device(value) - if dev is None: - self.notify_error('USB device (SN={}) not found.'.format(value)) - return - - try: - self.repeated_construction_destruction_test.send(dev) - self.notify_success() - except RuntimeError as exc: - self.notify_failure(exc) - except usb.core.USBError as exc: - error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') - self.notify_failure(error_msg if error_msg is not None else exc) + self.test_usb_device( + usb_dev_serial_number=value, + # Advance the coroutine to the next yield statement + # and send the usb_device to use. + test_fun=self.repeated_construction_destruction_test.send + ) def _callback_ep_test_data_correctness(self, key, value, timestamp): - self.log("Received serial %s" % (value)) - - dev = self.find_device(value) - if dev is None: - self.notify_error('USB device (SN={}) not found.'.format(value)) - return - - try: - ep_test_data_correctness(dev, log=print) - self.notify_success() - except RuntimeError as exc: - self.notify_failure(exc) - except usb.core.USBError as exc: - error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') - self.notify_failure(error_msg if error_msg is not None else exc) + self.test_usb_device( + usb_dev_serial_number=value, + test_fun=ep_test_data_correctness, + log=print + ) def _callback_ep_test_halt(self, key, value, timestamp): - self.log("Received serial %s" % (value)) - - dev = self.find_device(value) - if dev is None: - self.notify_error('USB device (SN={}) not found.'.format(value)) - return - - try: - ep_test_halt(dev, log=print) - self.notify_success() - except RuntimeError as exc: - self.notify_failure(exc) - except usb.core.USBError as exc: - error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') - self.notify_failure(error_msg if error_msg is not None else exc) + self.test_usb_device( + usb_dev_serial_number=value, + test_fun=ep_test_halt, + log=print + ) def _callback_ep_test_parallel_transfers(self, key, value, timestamp): - self.log("Received serial %s" % (value)) - - dev = self.find_device(value) - if dev is None: - self.notify_error('USB device (SN={}) not found.'.format(value)) - return - - try: - ep_test_parallel_transfers(dev, log=print) - self.notify_success() - except RuntimeError as exc: - self.notify_failure(exc) - except usb.core.USBError as exc: - error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') - self.notify_failure(error_msg if error_msg is not None else exc) + self.test_usb_device( + usb_dev_serial_number=value, + test_fun=ep_test_parallel_transfers, + log=print + ) def _callback_ep_test_parallel_transfers_ctrl(self, key, value, timestamp): - self.log("Received serial %s" % (value)) - - dev = self.find_device(value) - if dev is None: - self.notify_error('USB device (SN={}) not found.'.format(value)) - return - - try: - ep_test_parallel_transfers_ctrl(dev, log=print) - self.notify_success() - except RuntimeError as exc: - self.notify_failure(exc) - except usb.core.USBError as exc: - error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') - self.notify_failure(error_msg if error_msg is not None else exc) + self.test_usb_device( + usb_dev_serial_number=value, + test_fun=ep_test_parallel_transfers_ctrl, + log=print + ) def _callback_ep_test_abort(self, key, value, timestamp): - self.log("Received serial %s" % (value)) - - dev = self.find_device(value) - if dev is None: - self.notify_error('USB device (SN={}) not found.'.format(value)) - return - - try: - ep_test_abort(dev, log=print) - self.notify_success() - except RuntimeError as exc: - self.notify_failure(exc) - except usb.core.USBError as exc: - error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') - self.notify_failure(error_msg if error_msg is not None else exc) + self.test_usb_device( + usb_dev_serial_number=value, + test_fun=ep_test_abort, + log=print + ) def _callback_ep_test_data_toggle(self, key, value, timestamp): - self.log("Received serial %s" % (value)) - - dev = self.find_device(value) - if dev is None: - self.notify_error('USB device (SN={}) not found.'.format(value)) - return - - try: - ep_test_data_toggle(dev, log=print) - self.notify_success() - except RuntimeError as exc: - self.notify_failure(exc) - except usb.core.USBError as exc: - error_msg = format_local_error_msg('[{filename}]:{line_number}, Dev-host transfer error ({exc_value}).') - self.notify_failure(error_msg if error_msg is not None else exc) + self.test_usb_device( + usb_dev_serial_number=value, + test_fun=ep_test_data_toggle, + log=print + ) def _callback_reset_support(self, key, value, timestamp): status = "false" if sys.platform == "darwin" else "true" From 0f896fa97ddb7ef651367b05cad6e2bc68b0d669 Mon Sep 17 00:00:00 2001 From: Filip Jagodzinski Date: Tue, 17 Sep 2019 16:37:15 +0200 Subject: [PATCH 155/227] Tests: USB: Update error formatting in basic test --- TESTS/host_tests/pyusb_basic.py | 75 +++++++++++++++------------------ 1 file changed, 33 insertions(+), 42 deletions(-) diff --git a/TESTS/host_tests/pyusb_basic.py b/TESTS/host_tests/pyusb_basic.py index ffec33558aa..e7e22ad521f 100644 --- a/TESTS/host_tests/pyusb_basic.py +++ b/TESTS/host_tests/pyusb_basic.py @@ -85,13 +85,9 @@ def get_interface(dev, interface, alternate=0): FEATURE_ENDPOINT_HALT = 0 FEATURE_DEVICE_REMOTE_WAKEUP = 1 - - DEVICE_QUALIFIER_DESC_SIZE = 10 - DESC_TYPE_DEVICE_QUALIFIER = 0x06 - DEVICE_DESC_SIZE = 18 device_descriptor_parser = struct.Struct('BBHBBBBHHHBBBB') device_descriptor_keys = ['bLength', 'bDescriptorType', 'bcdUSB', 'bDeviceClass', @@ -352,11 +348,9 @@ def setup(self): self.register_callback('reset_support', self._callback_reset_support) - def result(self): return self.__result - def teardown(self): pass @@ -415,10 +409,9 @@ def get_set_configuration_test(dev, log): # check if dafault(1) configuration set try: ret = usb.control.get_configuration(dev) - raise_if_different(1, ret, lineno(), "FAILED - expected first configuration set") + raise_if_different(1, ret, lineno(), 'Invalid configuration.') except usb.core.USBError as error: - print(error) - raise_unconditionally(lineno(), "FAILED - get_configuration !!!") + raise_unconditionally(lineno(), 'get_configuration request failed ({}).'.format(str(error).strip())) cfg = dev.get_active_configuration() for intf in cfg: @@ -428,17 +421,15 @@ def get_set_configuration_test(dev, log): try: ret = dev.set_configuration(0) except usb.core.USBError as error: - print(error) - raise_unconditionally(lineno(), "FAILED - set_configuration(0) !!!") + raise_unconditionally(lineno(), 'set_configuration request (deconfigure) failed ({}).'.format(str(error).strip())) # check if deconfigured try: ret = usb.control.get_configuration(dev) - raise_if_different(0, ret, lineno(), "FAILED - expected to be deconfigured") + raise_if_different(0, ret, lineno(), 'Invalid configuration.') print("device deconfigured - OK") except usb.core.USBError as error: - print(error) - raise_unconditionally(lineno(), "FAILED - get_active_configuration !!!") + raise_unconditionally(lineno(), 'get_configuration request failed ({}).'.format(str(error).strip())) # for every configuration for cfg in dev: @@ -446,17 +437,15 @@ def get_set_configuration_test(dev, log): # set configuration ret = cfg.set() except usb.core.USBError as error: - print(error) - raise_unconditionally(lineno(), "FAILED - set configuration") + raise_unconditionally(lineno(), 'set_configuration request failed ({}).'.format(str(error).strip())) # check if configured try: ret = usb.control.get_configuration(dev) - raise_if_different(cfg.bConfigurationValue, ret, lineno(), "FAILED - expected {} configuration set".format(cfg.bConfigurationValue)) + raise_if_different(cfg.bConfigurationValue, ret, lineno(), 'Invalid configuration.') print("configuration {} set - OK ".format(cfg.bConfigurationValue)) except usb.core.USBError as error: - print(error) - raise_unconditionally(lineno(), "FAILED - get_configuration !!!") + raise_unconditionally(lineno(), 'get_configuration request failed ({}).'.format(str(error).strip())) # test control data transfer after configuration set control_data_test(dev, [64, 256], log) print("") # new line @@ -477,7 +466,7 @@ def get_set_interface_test(dev, log): cfg.set() # for every interface for intf in cfg: - intf.set_altsetting(); + intf.set_altsetting() altsett = usb.control.get_interface(dev, intf.bInterfaceNumber) raise_if_different(intf.bAlternateSetting, altsett, lineno(), text='Wrong alternate setting for interface {}'.format(intf.bInterfaceNumber)) print("cfg({}) inteface {}.{} set - OK".format(cfg.bConfigurationValue, intf.bInterfaceNumber, intf.bAlternateSetting)) @@ -583,15 +572,13 @@ def set_clear_feature_test(dev, log): try: usb.control.set_feature(dev, FEATURE_ENDPOINT_HALT, ep) except usb.core.USBError as err: - print(err) - raise_unconditionally(lineno(), "endpoint {} halt failed".format(ep.bEndpointAddress)) + raise_unconditionally(lineno(), 'set_feature request (halt) failed for endpoint {} ({}).'.format(ep.bEndpointAddress, str(err).strip())) # check if endpoint was halted try: ret = usb.control.get_status(dev, ep) except usb.core.USBError as err: - print(err) - raise_unconditionally(lineno(), "endpoint status failed".format(ep.bEndpointAddress)) + raise_unconditionally(lineno(), 'get_status request failed for endpoint {} ({}).'.format(ep.bEndpointAddress, str(err).strip())) if(ret != 1): raise_unconditionally(lineno(), "endpoint {} was not halted".format(ep.bEndpointAddress)) print("cfg({}) intf({}.{}) ep {} halted - OK".format(cfg.bConfigurationValue, intf.bInterfaceNumber, intf.bAlternateSetting, ep.bEndpointAddress)) @@ -600,8 +587,7 @@ def set_clear_feature_test(dev, log): try: usb.control.clear_feature(dev, FEATURE_ENDPOINT_HALT, ep) except usb.core.USBError as err: - print(err) - raise_unconditionally(lineno(), "endpoint {} unhalt failed".format(ep.bEndpointAddress)) + raise_unconditionally(lineno(), "clear_feature request (unhalt) failed for endpoint {} ({})".format(ep.bEndpointAddress, str(err).strip())) # check if endpoint was unhalted ret = usb.control.get_status(dev, ep) @@ -635,9 +621,9 @@ def get_descriptor_test(dev, vendor_id, product_id, log): try: ret = get_descriptor(dev, (DESC_TYPE_DEVICE << 8) | (0 << 0), 0, DEVICE_DESC_SIZE) dev_desc = dict(zip(device_descriptor_keys, device_descriptor_parser.unpack(ret))) - raise_if_different(DEVICE_DESC_SIZE, dev_desc['bLength'], lineno(), text='Wrong device descriptor size !!!') - raise_if_different(vendor_id, dev_desc['idVendor'], lineno(), text='Wrong vendor id !!!') - raise_if_different(product_id, dev_desc['idProduct'], lineno(), text='Wrong product id !!!') + raise_if_different(DEVICE_DESC_SIZE, dev_desc['bLength'], lineno(), text='Wrong device descriptor size.') + raise_if_different(vendor_id, dev_desc['idVendor'], lineno(), text='Wrong vendor ID.') + raise_if_different(product_id, dev_desc['idProduct'], lineno(), text='Wrong product ID.') except usb.core.USBError: raise_unconditionally(lineno(), "Requesting device descriptor failed") @@ -645,21 +631,21 @@ def get_descriptor_test(dev, vendor_id, product_id, log): try: ret = get_descriptor(dev, (DESC_TYPE_CONFIG << 8) | (0 << 0), 0, CONFIGURATION_DESC_SIZE) conf_desc = dict(zip(configuration_descriptor_keys, configuration_descriptor_parser.unpack(ret))) - raise_if_different(CONFIGURATION_DESC_SIZE, conf_desc['bLength'], lineno(), text='Wrong configuration descriptor size !!!') + raise_if_different(CONFIGURATION_DESC_SIZE, conf_desc['bLength'], lineno(), text='Wrong configuration descriptor size.') except usb.core.USBError: raise_unconditionally(lineno(), "Requesting configuration descriptor failed") # interface descriptor try: ret = get_descriptor(dev, (DESC_TYPE_INTERFACE << 8) | (0 << 0), 0, INTERFACE_DESC_SIZE) - raise_unconditionally(lineno(), "Requesting interface descriptor should fail since it is not directly accessible") + raise_unconditionally(lineno(), "Requesting interface descriptor should fail since it is not directly accessible.") except usb.core.USBError: log("interface descriptor is not directly accessible - OK") # endpoint descriptor try: ret = get_descriptor(dev, (DESC_TYPE_ENDPOINT << 8) | (0 << 0), 0, ENDPOINT_DESC_SIZE) - raise_unconditionally(lineno(), "Requesting endpoint descriptor should fail since it is not directly accessible") + raise_unconditionally(lineno(), "Requesting endpoint descriptor should fail since it is not directly accessible.") except usb.core.USBError: log("endpoint descriptor is not directly accessible - OK") print("") # new line @@ -687,7 +673,7 @@ def set_descriptor_test(dev, log): data = bytearray(DEVICE_DESC_SIZE) # Descriptor data try: dev.ctrl_transfer(request_type, request, value, index, data) - raise_unconditionally(lineno(), "SET_DESCRIPTOR should fail since it is not implemented") + raise_unconditionally(lineno(), "set_descriptor request should fail since it is not implemented") except usb.core.USBError: log("SET_DESCRIPTOR is unsupported - OK") print("") # new line @@ -715,7 +701,7 @@ def synch_frame_test(dev, log): ret = ret[0] | (ret[1] << 8) log("synch frame ret: %d" % (ret)) except usb.core.USBError: - raise_unconditionally(lineno(), "SYNCH_FRAME failed") + raise_unconditionally(lineno(), "SYNCH_FRAME request failed") print("") # new line @@ -847,7 +833,7 @@ def control_data_test(dev, sizes_list, log): ret = dev.ctrl_transfer(request_type, request, value, index, length, 5000) raise_if_different(i, len(ret), lineno(), "send/receive data is the wrong size") for j in range(0, i): - raise_if_different(data[j], ret[j], lineno(), "send/receive data not match") + raise_if_different(data[j], ret[j], lineno(), "send/receive data mismatch") except usb.core.USBError: raise_unconditionally(lineno(), "VENDOR_TEST_CTRL_IN_SIZES failed") count += 1 @@ -1001,7 +987,7 @@ def timer_handler(): raise RuntimeError('Invalid endpoint status after halt operation') except Exception as err: ctrl_error.set() - log('Endpoint {:#04x} halt failed ({}).'.format(ep_to_halt.bEndpointAddress, err)) + log('Endpoint {:#04x} halt failed ({!r}).'.format(ep_to_halt.bEndpointAddress, err)) # Whether the halt operation was successful or not, # wait a bit so the main thread has a chance to run into a USBError # or report the failure of halt operation. @@ -1015,27 +1001,32 @@ def timer_handler(): try: while delayed_halt.is_alive(): if ctrl_error.is_set(): - raise_unconditionally(lineno(), 'Halting endpoint {0.bEndpointAddress:#04x} failed' - .format(ep_to_halt)) + break try: loopback_ep_test(ep_out, ep_in, ep_out.wMaxPacketSize) except usb.core.USBError as err: + if ctrl_error.is_set(): + break try: ep_status = usb.control.get_status(dev, ep_to_halt) except usb.core.USBError as err: + if ctrl_error.is_set(): + break raise_unconditionally(lineno(), 'Unable to get endpoint status ({!r}).'.format(err)) if ep_status == 1: # OK, got USBError because of endpoint halt return else: raise_unconditionally(lineno(), 'Unexpected error ({!r}).'.format(err)) - except: - raise + if ctrl_error.is_set(): + raise_unconditionally(lineno(), 'Halting endpoint {0.bEndpointAddress:#04x} failed' + .format(ep_to_halt)) finally: # Always wait for the Timer thread created above. delayed_halt.join() - ep_out.clear_halt() - ep_in.clear_halt() + if not ctrl_error.is_set(): + ep_out.clear_halt() + ep_in.clear_halt() raise_unconditionally(lineno(), 'Halting endpoint {0.bEndpointAddress:#04x}' ' during transmission did not raise USBError.' .format(ep_to_halt)) From 12e595577111186463c7ea8f0b7a5c4238f716a2 Mon Sep 17 00:00:00 2001 From: Filip Jagodzinski Date: Wed, 18 Sep 2019 11:16:01 +0200 Subject: [PATCH 156/227] Tests: USB: Remove outdated docs from basic test --- TESTS/host_tests/pyusb_basic.py | 151 -------------------------------- 1 file changed, 151 deletions(-) diff --git a/TESTS/host_tests/pyusb_basic.py b/TESTS/host_tests/pyusb_basic.py index e7e22ad521f..6ad2a255fd2 100644 --- a/TESTS/host_tests/pyusb_basic.py +++ b/TESTS/host_tests/pyusb_basic.py @@ -1639,154 +1639,3 @@ def get_descriptor(dev, type_index, lang_id, length): ret = dev.ctrl_transfer(request_type, request, value, index, length) return ret - - -""" -For documentation purpose until test writing finished -TODO: remove this if not needed anymore - - -def test_device(serial_number, log=print): - dev = usb.core.find(custom_match=TestMatch(serial_number)) - if dev is None: - log("Device not found") - return - - ## --Control Tests-- ## - #control_basic_test(dev, log) - # Test control IN/OUT/NODATA - control_stall_test(dev, log) - # Invalid control in/out/nodata requests are stalled - # Stall during different points in the control transfer - #control_sizes_test(dev, log) - # Test control requests of various data stage sizes (1,8,16,32,64,255,256,...) - control_stress_test(dev, log) - # normal and delay mode - - ## --Endpoint test-- ## - #for each endpoint - #-test all allowed wMaxPacketSize sizes and transfer types - #-stall tests - #-set/clear stall control request - #-stall at random points of sending/receiveing data - #-test aborting an in progress transfer - #test as many endpoints at once as possible - #test biggest configuration possible - - ## --physical test-- ## - #-reset notification/handling - #-connect/disconnect tests - have device disconnect and then reconnect - #-disconnect during various phases of control transfers and endpoint transfers - #-suspend/resume tests (may not be possible to test with current framework) - #-suspend/resume notifications - - ## -- Stress tests-- ## - #-concurrent tests (all endpoints at once including control) - #-concurrent tests + reset + delay - - ## -- other tests-- ## - #-report throughput for in/out of control, bulk, interrupt and iso transfers - #-verify that construction/destruction repeatedly works gracefully - - intf = get_interface(dev, 0, 0) - - # Find endpoints - bulk_in = None - bulk_out = None - int_in = None - int_out = None - - for endpoint in intf: - log("Processing endpoint %s" % endpoint) - ep_type = endpoint.bmAttributes & 0x3 - if ep_type == 2: - if endpoint.bEndpointAddress & 0x80: - assert bulk_in is None - bulk_in = endpoint - else: - assert bulk_out is None - bulk_out = endpoint - elif ep_type == 3: - if endpoint.bEndpointAddress & 0x80: - assert int_in is None - int_in = endpoint - else: - assert int_out is None - int_out = endpoint - assert bulk_in is not None - assert bulk_out is not None - assert int_in is not None - assert int_out is not None - bulk_out.write("hello" + "x" *256); - int_out.write("world" + "x" *256); - - dev.set_interface_altsetting(0, 1) - - intf = get_interface(dev, 0, 0) - - # Find endpoints - bulk_in = None - bulk_out = None - int_in = None - int_out = None - - for endpoint in intf: - log("Processing endpoint %s" % endpoint) - ep_type = endpoint.bmAttributes & 0x3 - if ep_type == 2: - if endpoint.bEndpointAddress & 0x80: - assert bulk_in is None - bulk_in = endpoint - else: - assert bulk_out is None - bulk_out = endpoint - elif ep_type == 3: - if endpoint.bEndpointAddress & 0x80: - assert int_in is None - int_in = endpoint - else: - assert int_out is None - int_out = endpoint - assert bulk_in is not None - assert bulk_out is not None - assert int_in is not None - assert int_out is not None - bulk_out.write("hello2" + "x" *256); - int_out.write("world2" + "x" *256); - - - t = Thread(target=write_data, args=(bulk_out,)) - t.start() - - for _ in range(10): - request_type = build_request_type(CTRL_OUT, CTRL_TYPE_VENDOR, - CTRL_RECIPIENT_DEVICE) - request = VENDOR_TEST_CTRL_NONE_DELAY - value = 0 # Always 0 for this request - index = 0 # Communication interface - length = 0 # No data - dev.ctrl_transfer(request_type, request, value, index, length, 5000) - - t.join() - - -def write_data(pipe): - print("Write data running") - count = 0 - for _ in range(40): - pipe.write("Value is %s" % count) - count += 1 - print("Count %s" % count) - time.sleep(0.5) - - -def main(): - parser = ArgumentParser(description="USB basic test") - parser.add_argument('serial', help='USB serial number of DUT') - args = parser.parse_args() - ret = test_device(args.serial) - print("Test %s" % "passed" if ret else "failed") - -if __name__ == "__main__": - main() -""" From f295272b3b7a3402e2c1355aeef825cef3dc77c7 Mon Sep 17 00:00:00 2001 From: Kimmo Vaisanen Date: Mon, 30 Sep 2019 12:36:55 +0300 Subject: [PATCH 157/227] LoRa: Fix build warning about _ongoing_tx_msg _ongoing_tx_msg was incorrectly initialized before _mlme_confirmation. Fixes following build warning: [Warning] LoRaMac.h@691,26: 'LoRaMac::_ongoing_tx_msg' will be initialized after [-Wreorder] [Warning] LoRaMac.h@689,28: 'loramac_mlme_confirm_t LoRaMac::_mlme_confirmation' [-Wreorder] [Warning] LoRaMac.cpp@68,1: when initialized here [-Wreorder] --- features/lorawan/lorastack/mac/LoRaMac.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/features/lorawan/lorastack/mac/LoRaMac.cpp b/features/lorawan/lorastack/mac/LoRaMac.cpp index 580ffacc29c..1484551e415 100644 --- a/features/lorawan/lorastack/mac/LoRaMac.cpp +++ b/features/lorawan/lorastack/mac/LoRaMac.cpp @@ -76,8 +76,8 @@ LoRaMac::LoRaMac() _mcps_indication(), _mcps_confirmation(), _mlme_indication(), - _ongoing_tx_msg(), _mlme_confirmation(), + _ongoing_tx_msg(), _is_nwk_joined(false), _can_cancel_tx(true), _continuous_rx2_window_open(false), From d48ea364ffaace3b1a3e2eb2071c57408fcb61c3 Mon Sep 17 00:00:00 2001 From: Mirela Chirica Date: Mon, 30 Sep 2019 14:01:05 +0300 Subject: [PATCH 158/227] Cellular: Include of errno.h needed for Mac OS X --- features/cellular/framework/AT/ATHandler.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/features/cellular/framework/AT/ATHandler.cpp b/features/cellular/framework/AT/ATHandler.cpp index 295967691be..540f12577c0 100644 --- a/features/cellular/framework/AT/ATHandler.cpp +++ b/features/cellular/framework/AT/ATHandler.cpp @@ -18,6 +18,7 @@ #include #include #include +#include #include "ATHandler.h" #include "mbed_poll.h" #include "FileHandle.h" From 9dab079d33e2c02acabbb18fd5a374f29cc8d597 Mon Sep 17 00:00:00 2001 From: Mirela Chirica Date: Mon, 30 Sep 2019 14:04:58 +0300 Subject: [PATCH 159/227] Cellular: Removed not used variable --- features/cellular/framework/AT/ATHandler.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/features/cellular/framework/AT/ATHandler.cpp b/features/cellular/framework/AT/ATHandler.cpp index 540f12577c0..9b35a37b8f2 100644 --- a/features/cellular/framework/AT/ATHandler.cpp +++ b/features/cellular/framework/AT/ATHandler.cpp @@ -749,8 +749,7 @@ int32_t ATHandler::read_int() } errno = 0; - char *endptr; - long result = std::strtol(buff, &endptr, 10); + long result = std::strtol(buff, NULL, 10); if ((result == LONG_MIN || result == LONG_MAX) && errno == ERANGE) { return -1; // overflow/underflow } From 89ce27b3fca448b702b3f129becbf724ef2bc4c4 Mon Sep 17 00:00:00 2001 From: Chris Trowbridge Date: Wed, 25 Sep 2019 11:57:12 -0400 Subject: [PATCH 160/227] EP_AGORA: Add config logic to enable BLE, cell, and LoRa by default --- .../TARGET_EP_AGORA/ONBOARD_TELIT_ME910.cpp | 140 ++++++++++++++++++ .../TARGET_EP_AGORA/ONBOARD_TELIT_ME910.h | 38 +++++ .../TARGET_EP_AGORA/mbed_lib.json | 15 ++ .../TARGET_EP_AGORA/onboard_modem_api.c | 73 +++++++++ targets/targets.json | 10 +- 5 files changed, 273 insertions(+), 3 deletions(-) create mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_EP_AGORA/ONBOARD_TELIT_ME910.cpp create mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_EP_AGORA/ONBOARD_TELIT_ME910.h create mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_EP_AGORA/mbed_lib.json create mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_EP_AGORA/onboard_modem_api.c diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_EP_AGORA/ONBOARD_TELIT_ME910.cpp b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_EP_AGORA/ONBOARD_TELIT_ME910.cpp new file mode 100644 index 00000000000..cf339323c81 --- /dev/null +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_EP_AGORA/ONBOARD_TELIT_ME910.cpp @@ -0,0 +1,140 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2019 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if MBED_CONF_NSAPI_PRESENT + +#if EP_AGORA_ENABLE_CELL + +#include "cellular/onboard_modem_api.h" +#include "UARTSerial.h" +#include "ONBOARD_TELIT_ME910.h" +#include "ThisThread.h" +#include "CellularLog.h" + +using namespace mbed; + +ONBOARD_TELIT_ME910::ONBOARD_TELIT_ME910(FileHandle *fh) : TELIT_ME910(fh, PIN_NAME_CELL_ON_OFF, true) +{ +} + +nsapi_error_t ONBOARD_TELIT_ME910::hard_power_on() +{ + ::onboard_modem_init(); + return NSAPI_ERROR_OK; +} + +nsapi_error_t ONBOARD_TELIT_ME910::hard_power_off() +{ + ::onboard_modem_deinit(); + return NSAPI_ERROR_OK; +} + +nsapi_error_t ONBOARD_TELIT_ME910::soft_power_on() +{ + ::onboard_modem_power_up(); + // From Telit_xE910 Global form factor App note: It is mandatory to avoid sending data to the serial ports during the first 200ms of the module start-up. + rtos::ThisThread::sleep_for(200); + return NSAPI_ERROR_OK; +} + +nsapi_error_t ONBOARD_TELIT_ME910::soft_power_off() +{ + ::onboard_modem_power_down(); + return NSAPI_ERROR_OK; +} + +nsapi_error_t ONBOARD_TELIT_ME910::init() +{ + nsapi_error_t err = AT_CellularDevice::init(); + if (err != NSAPI_ERROR_OK) { + return err; + } + _at->lock(); +#if DEVICE_SERIAL_FC + _at->at_cmd_discard("&K3;&C1;&D0", ""); +#else + _at->at_cmd_discard("&K0;&C1;&D0", ""); +#endif + + // AT#QSS=1 + // Enable the Query SIM Status unsolicited indication in the ME. The format of the + // unsolicited indication is the following: + // #QSS: + // The ME informs at + // every SIM status change through the basic unsolicited indication where range is 0...1 + // values: + // - 0: SIM not inserted + // - 1: SIM inserted + _at->at_cmd_discard("#QSS", "=1"); + + // AT#PSNT=1 + // Set command enables unsolicited result code for packet service network type (PSNT) + // having the following format: + // #PSNT: + // values: + // - 0: GPRS network + // - 4: LTE network + // - 5: unknown or not registered + _at->at_cmd_discard("#PSNT", "=1"); + + // AT+CMER=2 + // Set command enables sending of unsolicited result codes from TA to TE in the case of + // indicator state changes. + // Current setting: buffer +CIEV Unsolicited Result Codes in the TA when TA-TE link is + // reserved (e.g. on-line data mode) and flush them to the TE after + // reservation; otherwise forward them directly to the TE + _at->at_cmd_discard("+CMER", "=2"); + + // AT+CMEE=2 + // Set command disables the use of result code +CME ERROR: as an indication of an + // error relating to the +Cxxx command issued. When enabled, device related errors cause the +CME + // ERROR: final result code instead of the default ERROR final result code. ERROR is returned + // normally when the error message is related to syntax, invalid parameters or DTE functionality. + // Current setting: enable and use verbose values + _at->at_cmd_discard("+CMEE", "=2"); + + // AT#PORTCFG=0 + // Set command allows to connect Service Access Points to the external physical ports giving a great + // flexibility. Examples of Service Access Points: AT Parser Instance #1, #2, #3, etc.. + _at->at_cmd_discard("#PORTCFG", "=3"); + + // AT&W&P + // - AT&W: Execution command stores on profile the complete configuration of the device. If + // parameter is omitted, the command has the same behavior of AT&W0. + // - AT&P: Execution command defines which full profile will be loaded at startup. If parameter + // is omitted, the command has the same behavior as AT&P0 + _at->at_cmd_discard("&W&P", ""); + + return _at->unlock_return_error(); +} + +CellularDevice *CellularDevice::get_target_default_instance() +{ + static UARTSerial serial(MDMTXD, MDMRXD, 115200); +#if DEVICE_SERIAL_FC + if (MDMRTS != NC && MDMCTS != NC) { + tr_debug("Modem flow control: RTS %d CTS %d", MDMRTS, MDMCTS); + serial.set_flow_control(SerialBase::RTSCTS, MDMRTS, MDMCTS); + } +#endif + static ONBOARD_TELIT_ME910 device(&serial); + return &device; +} + +#endif // EP_AGORA_ENABLE_CELL + +#endif // MBED_CONF_NSAPI_PRESENT diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_EP_AGORA/ONBOARD_TELIT_ME910.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_EP_AGORA/ONBOARD_TELIT_ME910.h new file mode 100644 index 00000000000..137514207fc --- /dev/null +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_EP_AGORA/ONBOARD_TELIT_ME910.h @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2019 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ONBOARD_TELIT_ME910_ +#define ONBOARD_TELIT_ME910_ + +#include "TELIT_ME910.h" + +namespace mbed { + +class ONBOARD_TELIT_ME910 : public TELIT_ME910 { +public: + ONBOARD_TELIT_ME910(FileHandle *fh); + + virtual nsapi_error_t init(); + virtual nsapi_error_t hard_power_on(); + virtual nsapi_error_t hard_power_off(); + virtual nsapi_error_t soft_power_on(); + virtual nsapi_error_t soft_power_off(); +}; + +} // namespace mbed + +#endif // ONBOARD_TELIT_ME910_ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_EP_AGORA/mbed_lib.json b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_EP_AGORA/mbed_lib.json new file mode 100644 index 00000000000..0490d9aced9 --- /dev/null +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_EP_AGORA/mbed_lib.json @@ -0,0 +1,15 @@ +{ + "name": "ep-agora", + "config": { + "enable-cell" : { + "help" : "Enable the cell module on the EP_AGORA board", + "macro_name" : "EP_AGORA_ENABLE_CELL", + "value" : true + } + }, + "target_overrides": { + "EP_AGORA": { + "target.network-default-interface-type": "CELLULAR" + } + } +} \ No newline at end of file diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_EP_AGORA/onboard_modem_api.c b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_EP_AGORA/onboard_modem_api.c new file mode 100644 index 00000000000..979becbd183 --- /dev/null +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_EP_AGORA/onboard_modem_api.c @@ -0,0 +1,73 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2019 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if MBED_CONF_NSAPI_PRESENT + +#include "cellular/onboard_modem_api.h" +#include "gpio_api.h" +#include "platform/mbed_thread.h" +#include "PinNames.h" + +#if MODEM_ON_BOARD + +static void press_power_button(int time_ms) +{ + gpio_t gpio; + + gpio_init_out_ex(&gpio, PIN_NAME_CELL_ON_OFF, 1); + gpio_write(&gpio, 0); + thread_sleep_for(time_ms); + gpio_write(&gpio, 1); +} + +void onboard_modem_init() +{ + gpio_t gpio; + + gpio_init_out_ex(&gpio, PIN_NAME_CELL_POWER_ENABLE, 0); + gpio_write(&gpio, 1); +} + +void onboard_modem_deinit() +{ + gpio_t gpio; + + gpio_init_out_ex(&gpio, PIN_NAME_CELL_POWER_ENABLE, 1); + gpio_write(&gpio, 0); +} + +void onboard_modem_power_up() +{ + /* keep the power line low for 5 seconds */ + press_power_button(5000); + /* give modem a little time to respond */ + thread_sleep_for(20 * 1000); +} + +void onboard_modem_power_down() +{ + gpio_t gpio; + + gpio_init_out_ex(&gpio, PIN_NAME_CELL_ON_OFF, 0); + /* keep the power line low for more than 3 seconds. + * If 3G_ON_OFF pin is kept low for more than a second, a controlled disconnect and shutdown takes + * place, Due to the network disconnect, shut-off can take up to 30 seconds. However, we wait for 10 + * seconds only */ + thread_sleep_for(10 * 1000); +} +#endif //MODEM_ON_BOARD +#endif //MBED_CONF_NSAPI_PRESENT diff --git a/targets/targets.json b/targets/targets.json index d818a664c79..588474246c6 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -9326,18 +9326,22 @@ "config": { "modem_is_on_board": { "help": "Value: Tells the build system that the modem is on-board as oppose to a plug-in shield/module.", - "value": 0, + "value": 1, "macro_name": "MODEM_ON_BOARD" }, "modem_data_connection_type": { "help": "Value: Defines how an on-board modem is wired up to the MCU, e.g., data connection can be a UART or USB and so forth.", - "value": 0, + "value": 1, "macro_name": "MODEM_ON_BOARD_UART" } }, "components_add": ["SPIF"], "components_remove": ["QSPIF"], - "release_versions": ["5"] + "release_versions": ["5"], + "macros_add": [ + "CONFIG_GPIO_AS_PINRESET", + "NRF52_ERRATA_20" + ] }, "IM880B": { "inherits": ["FAMILY_STM32"], From 78f32920361fc53926d1c9ff639d42f19dc9186f Mon Sep 17 00:00:00 2001 From: Ari Parkkila Date: Fri, 27 Sep 2019 02:09:36 -0700 Subject: [PATCH 161/227] Cellular: Fix setting of PDP context ID (cid) --- UNITTESTS/stubs/AT_CellularContext_stub.cpp | 4 ++++ UNITTESTS/stubs/AT_CellularStack_stub.cpp | 3 +++ UNITTESTS/target_h/myCellularContext.h | 4 ++++ .../framework/AT/AT_CellularContext.cpp | 22 ++++++++++++++----- .../framework/AT/AT_CellularContext.h | 1 + .../framework/AT/AT_CellularStack.cpp | 5 +++++ .../cellular/framework/AT/AT_CellularStack.h | 8 +++++++ 7 files changed, 41 insertions(+), 6 deletions(-) diff --git a/UNITTESTS/stubs/AT_CellularContext_stub.cpp b/UNITTESTS/stubs/AT_CellularContext_stub.cpp index 4983d117afb..8ecf796b215 100644 --- a/UNITTESTS/stubs/AT_CellularContext_stub.cpp +++ b/UNITTESTS/stubs/AT_CellularContext_stub.cpp @@ -279,6 +279,10 @@ void AT_CellularContext::set_disconnect() { } +void AT_CellularContext::set_cid(int cid) +{ +} + void AT_CellularContext::do_connect_with_retry() { diff --git a/UNITTESTS/stubs/AT_CellularStack_stub.cpp b/UNITTESTS/stubs/AT_CellularStack_stub.cpp index 998cd20c938..054396a2a90 100644 --- a/UNITTESTS/stubs/AT_CellularStack_stub.cpp +++ b/UNITTESTS/stubs/AT_CellularStack_stub.cpp @@ -94,3 +94,6 @@ void AT_CellularStack::socket_attach(nsapi_socket_t handle, void (*callback)(voi { } +void AT_CellularStack::set_cid(int cid) +{ +} diff --git a/UNITTESTS/target_h/myCellularContext.h b/UNITTESTS/target_h/myCellularContext.h index 0da0096fd24..172e4e0ff27 100644 --- a/UNITTESTS/target_h/myCellularContext.h +++ b/UNITTESTS/target_h/myCellularContext.h @@ -216,6 +216,10 @@ class myCellularContext : public CellularContext { { }; + void set_cid(int cid) + { + }; + void do_connect_with_retry() { }; diff --git a/features/cellular/framework/AT/AT_CellularContext.cpp b/features/cellular/framework/AT/AT_CellularContext.cpp index 2d782a5c85a..e0e192e8fbe 100644 --- a/features/cellular/framework/AT/AT_CellularContext.cpp +++ b/features/cellular/framework/AT/AT_CellularContext.cpp @@ -299,7 +299,7 @@ void AT_CellularContext::delete_current_context() _at.at_cmd_discard("+CGDCONT", "=", "%d", _cid); if (_at.get_last_error() == NSAPI_ERROR_OK) { - _cid = -1; + set_cid(-1); _new_context_set = false; } @@ -347,7 +347,7 @@ bool AT_CellularContext::get_context() { _at.cmd_start_stop("+CGDCONT", "?"); _at.resp_start("+CGDCONT:"); - _cid = -1; + set_cid(-1); int cid_max = 0; // needed when creating new context char apn[MAX_ACCESSPOINT_NAME_LENGTH]; int apn_len = 0; @@ -373,7 +373,7 @@ bool AT_CellularContext::get_context() if (get_property(pdp_type_t_to_cellular_property(pdp_type)) || ((pdp_type == IPV4V6_PDP_TYPE && (get_property(PROPERTY_IPV4_PDP_TYPE) && get_property(PROPERTY_IPV6_PDP_TYPE))) && !_nonip_req)) { _pdp_type = pdp_type; - _cid = cid; + set_cid(cid); } } } @@ -423,7 +423,7 @@ bool AT_CellularContext::set_new_context(int cid) if (success) { _pdp_type = pdp_type; - _cid = cid; + set_cid(cid); _new_context_set = true; tr_info("New PDP context %d, type %d", _cid, pdp_type); } @@ -661,7 +661,7 @@ void AT_CellularContext::do_disconnect() if (_new_context_set) { delete_current_context(); } - _cid = -1; + set_cid(-1); _cb_data.error = NSAPI_ERROR_NO_CONNECTION; } @@ -697,7 +697,7 @@ void AT_CellularContext::do_disconnect() if (_new_context_set) { delete_current_context(); } - _cid = -1; + set_cid(-1); _cb_data.error = _at.unlock_return_error(); } @@ -994,6 +994,7 @@ void AT_CellularContext::cellular_callback(nsapi_event_t ev, intptr_t ptr) } else if (ev == NSAPI_EVENT_CONNECTION_STATUS_CHANGE && ptr == NSAPI_STATUS_DISCONNECTED) { tr_info("cellular_callback: PPP mode and NSAPI_STATUS_DISCONNECTED"); _cb_data.error = NSAPI_ERROR_NO_CONNECTION; + set_cid(-1); _is_connected = false; ppp_disconnected(); } @@ -1001,6 +1002,7 @@ void AT_CellularContext::cellular_callback(nsapi_event_t ev, intptr_t ptr) #else if (ev == NSAPI_EVENT_CONNECTION_STATUS_CHANGE && ptr == NSAPI_STATUS_DISCONNECTED) { tr_info("cb: CellularContext disconnected"); + set_cid(-1); _is_connected = false; } #endif // NSAPI_PPP_AVAILABLE @@ -1065,3 +1067,11 @@ void AT_CellularContext::set_disconnect() _is_connected = false; _device->cellular_callback(NSAPI_EVENT_CONNECTION_STATUS_CHANGE, NSAPI_STATUS_DISCONNECTED, this); } + +void AT_CellularContext::set_cid(int cid) +{ + _cid = cid; + if (_stack) { + static_cast(_stack)->set_cid(_cid); + } +} diff --git a/features/cellular/framework/AT/AT_CellularContext.h b/features/cellular/framework/AT/AT_CellularContext.h index 439127273ab..173a836a3c4 100644 --- a/features/cellular/framework/AT/AT_CellularContext.h +++ b/features/cellular/framework/AT/AT_CellularContext.h @@ -119,6 +119,7 @@ class AT_CellularContext : public CellularContext, public AT_CellularBase { void ciot_opt_cb(mbed::CellularNetwork::CIoT_Supported_Opt ciot_opt); virtual void do_connect_with_retry(); void do_disconnect(); + void set_cid(int cid); private: bool _is_connected; ContextOperation _current_op; diff --git a/features/cellular/framework/AT/AT_CellularStack.cpp b/features/cellular/framework/AT/AT_CellularStack.cpp index 621431eabe0..a1410fd0277 100644 --- a/features/cellular/framework/AT/AT_CellularStack.cpp +++ b/features/cellular/framework/AT/AT_CellularStack.cpp @@ -98,6 +98,11 @@ const char *AT_CellularStack::get_ip_address() return (ipv4 || ipv6) ? _ip : NULL; } +void AT_CellularStack::set_cid(int cid) +{ + _cid = cid; +} + nsapi_error_t AT_CellularStack::socket_stack_init() { return NSAPI_ERROR_OK; diff --git a/features/cellular/framework/AT/AT_CellularStack.h b/features/cellular/framework/AT/AT_CellularStack.h index 5015aeee48b..2402289bf2c 100644 --- a/features/cellular/framework/AT/AT_CellularStack.h +++ b/features/cellular/framework/AT/AT_CellularStack.h @@ -44,6 +44,14 @@ class AT_CellularStack : public NetworkStack, public AT_CellularBase { public: // NetworkStack virtual const char *get_ip_address(); + + /** + * Set PDP context ID for this stack + * + * @param cid value from AT+CGDCONT, where -1 is undefined + */ + void set_cid(int cid); + protected: // NetworkStack /** From a7038fb818e482746f1347a729f7079354901c0f Mon Sep 17 00:00:00 2001 From: Qinghao Shi Date: Fri, 27 Sep 2019 00:28:28 +0100 Subject: [PATCH 162/227] TEST: change intefration fs test format and mount order --- TESTS/integration/fs-single/main.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/TESTS/integration/fs-single/main.cpp b/TESTS/integration/fs-single/main.cpp index 9129c96d1db..7a423b685ee 100644 --- a/TESTS/integration/fs-single/main.cpp +++ b/TESTS/integration/fs-single/main.cpp @@ -66,12 +66,12 @@ LittleFileSystem fs("sd"); static control_t test_format(const size_t call_count) { + int format_err = fs.format(&sd); + TEST_ASSERT_EQUAL_INT_MESSAGE(0, format_err, "could not format block device"); + int mount_err = fs.mount(&sd); TEST_ASSERT_EQUAL_INT_MESSAGE(0, mount_err, "could not mount block device"); - int format_err = fs.reformat(&sd); - TEST_ASSERT_EQUAL_INT_MESSAGE(0, format_err, "could not format block device"); - return CaseNext; } From 04767f30223e86039b2a4e0886e25214e772382a Mon Sep 17 00:00:00 2001 From: Janne Kiiskila Date: Mon, 30 Sep 2019 14:43:34 +0300 Subject: [PATCH 163/227] AT_CellularDevice.cpp - unused variable err warning MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We get this compiler warning; Compile [ 7.9%]: AT_CellularDevice.cpp [Warning] AT_CellularDevice.cpp@206,18: variable 'err' set but not used [-Wunused-but-set-variable] Due to the fact, that the code that would actually use this variable is behind trace flags. Based on review feedback from Antti Kauppila and Kimmo Väisänen, adding same flagging also for that. - Reason being - the operation needs to be within the locks. --- features/cellular/framework/AT/AT_CellularDevice.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/features/cellular/framework/AT/AT_CellularDevice.cpp b/features/cellular/framework/AT/AT_CellularDevice.cpp index 8835d76a1ea..65d9b6d0bd7 100644 --- a/features/cellular/framework/AT/AT_CellularDevice.cpp +++ b/features/cellular/framework/AT/AT_CellularDevice.cpp @@ -203,7 +203,9 @@ nsapi_error_t AT_CellularDevice::get_sim_state(SimState &state) _at->flush(); nsapi_error_t error = _at->at_cmd_str("+CPIN", "?", simstr, sizeof(simstr)); ssize_t len = strlen(simstr); +#if MBED_CONF_MBED_TRACE_ENABLE device_err_t err = _at->get_last_device_error(); +#endif _at->unlock(); if (len != -1) { From b152f4e5f11777eadd807dec93521645113a0d63 Mon Sep 17 00:00:00 2001 From: Ladislas de Toldi Date: Fri, 13 Sep 2019 17:55:15 +0200 Subject: [PATCH 164/227] update googletest to v1.8.1 --- UNITTESTS/CMakeLists.txt | 4 ++-- UNITTESTS/googletest-CMakeLists.txt.in | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/UNITTESTS/CMakeLists.txt b/UNITTESTS/CMakeLists.txt index 926d13b8a41..9b395daacaa 100644 --- a/UNITTESTS/CMakeLists.txt +++ b/UNITTESTS/CMakeLists.txt @@ -52,8 +52,8 @@ add_subdirectory(${CMAKE_BINARY_DIR}/googletest-src # dependencies automatically when using CMake 2.8.11 or # later. target_include_directories(gmock_main SYSTEM BEFORE INTERFACE - "${gtest_SOURCE_DIR}/include" - "${gmock_SOURCE_DIR}/include") + "$" + "$") #################### # TESTING diff --git a/UNITTESTS/googletest-CMakeLists.txt.in b/UNITTESTS/googletest-CMakeLists.txt.in index 9041496e1b8..f4b4894a517 100644 --- a/UNITTESTS/googletest-CMakeLists.txt.in +++ b/UNITTESTS/googletest-CMakeLists.txt.in @@ -5,7 +5,7 @@ project(googletest-download NONE) include(ExternalProject) ExternalProject_Add(googletest GIT_REPOSITORY https://github.com/google/googletest.git - GIT_TAG 8bc11c040a1dcbe50c340b21d78175d152dd3837 + GIT_TAG release-1.8.1 SOURCE_DIR "${CMAKE_BINARY_DIR}/googletest-src" BINARY_DIR "${CMAKE_BINARY_DIR}/googletest-build" CONFIGURE_COMMAND "" From 74715c71f7d552c5732dacebbdb435693f94bfe1 Mon Sep 17 00:00:00 2001 From: Ladislas de Toldi Date: Mon, 30 Sep 2019 09:47:44 +0200 Subject: [PATCH 165/227] Update README with Google Test version 1.8.1 --- UNITTESTS/README.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/UNITTESTS/README.md b/UNITTESTS/README.md index 1351c0250e3..d45b3b10762 100644 --- a/UNITTESTS/README.md +++ b/UNITTESTS/README.md @@ -85,6 +85,8 @@ Mbed CLI supports unit tests through the `mbed test --unittests` command. For in A unit tests suite consists of one or more test cases. The test cases should cover all the functions in a class under test. All the external dependencies are stubbed including the other classes in the same module. Avoid stubbing header files. Finally, analyze code coverage to ensure all code is tested, and no dead code is found. +Unit tests are written using [Google Test v1.8.1](https://github.com/google/googletest/releases/tag/release-1.8.1). + Please see the [documentation for Google Test](https://github.com/google/googletest/blob/master/googletest/docs/primer.md) to learn how to write unit tests using its framework. See the [documentation for Google Mock](https://github.com/google/googletest/blob/master/googlemock/docs/Documentation.md) if you want to write and use C++ mock classes instead of stubs. #### Test suite configuration From 0a58c80b56c8f9e806bb5b59cfe0c5d209e1d41f Mon Sep 17 00:00:00 2001 From: Kevin Bracey Date: Thu, 26 Sep 2019 16:07:48 +0300 Subject: [PATCH 166/227] Tighten GCC 2-region _sbrk When moving to the second heap region due to overflowing the first region, the `_sbrk` implementation assumed the allocation would fit in the second region, and didn't check for that overflowing too. Problem revealed in `stats_heap` test with GCC 8 on K64F - the allocation attempt for 1GiB crashed, as `_sbrk` indicated 1GiB was available at the start of the second region. second region. Presumably older versions of newlib fault that allocation attempt before passing to `_sbrk`. While there, adjust the code to not use a separate static `bool`, saving RAM. We can track with just one pointer, as order of the two regions is fixed, and already relied on by newlib. --- platform/source/mbed_retarget.cpp | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/platform/source/mbed_retarget.cpp b/platform/source/mbed_retarget.cpp index c4428544d95..2038c1adad6 100644 --- a/platform/source/mbed_retarget.cpp +++ b/platform/source/mbed_retarget.cpp @@ -1268,7 +1268,7 @@ extern "C" WEAK void __cxa_pure_virtual(void) extern uint32_t __mbed_sbrk_start; extern uint32_t __mbed_krbs_start; /* Additional RAM memory used for heap - please note this - * address should be lower address then the previous default address + * address must be lower address then the previous default address */ extern uint32_t __mbed_sbrk_start_0; extern uint32_t __mbed_krbs_start_0; @@ -1276,19 +1276,18 @@ extern uint32_t __mbed_krbs_start_0; extern "C" WEAK caddr_t _sbrk(int incr) { static uint32_t heap = (uint32_t) &__mbed_sbrk_start_0; - static bool once = true; uint32_t prev_heap = heap; uint32_t new_heap = heap + incr; /** - * If the new address is outside the first region, start allocating from the second region. - * Jump to second region is done just once, and `static bool once` is used to keep track of that. + * If we exceed the first region, start allocating from the second region. */ - if (once && (new_heap > (uint32_t) &__mbed_krbs_start_0)) { - once = false; + if (prev_heap <= (uint32_t) &__mbed_krbs_start_0 && new_heap > (uint32_t) &__mbed_krbs_start_0) { prev_heap = (uint32_t) &__mbed_sbrk_start; new_heap = prev_heap + incr; - } else if (new_heap > (uint32_t) &__mbed_krbs_start) { + } + + if (new_heap > (uint32_t) &__mbed_krbs_start) { /** * If the new address is outside the second region, return out-of-memory. */ From c81995cf561e0cb66e4ec492c97b0beabb59bd29 Mon Sep 17 00:00:00 2001 From: Qinghao Shi Date: Fri, 27 Sep 2019 15:58:28 +0100 Subject: [PATCH 167/227] FASTMODEL: add simulated TRNG implementation to fastmodel --- .../TARGET_ARM_FM/TARGET_FVP_MPS2/objects.h | 4 ++ .../TARGET_ARM_FM/TARGET_FVP_MPS2/trng_api.c | 56 +++++++++++++++++++ 2 files changed, 60 insertions(+) create mode 100644 targets/TARGET_ARM_FM/TARGET_FVP_MPS2/trng_api.c diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/objects.h b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/objects.h index c85d29317bb..ef09fd7f0bf 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/objects.h +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/objects.h @@ -78,6 +78,10 @@ struct flash_s { uint8_t not_used; }; +struct trng_s { + uint8_t not_used; +}; + #include "gpio_object.h" #ifdef __cplusplus diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/trng_api.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/trng_api.c new file mode 100644 index 00000000000..b31a26d2423 --- /dev/null +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/trng_api.c @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2017-2019 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "trng_api.h" +#include "device.h" +#include + + + +void trng_init(trng_t *obj) +{ + srand(0); + (void)obj; +} + + +void trng_free(trng_t *obj) +{ + (void)obj; +} + +/** Get random data from TRNG peripheral + * + * @param obj The TRNG object + * @param output The pointer to an output array + * @param length The size of output data, to avoid buffer overwrite + * @param output_length The length of generated data + * @return 0 success, -1 fail + */ +int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length) +{ + (void)obj; + (void)output; + + for (int i = 0; i < length; ++i) { + output[i] = rand() % 256; + } + *output_length = length; + + return 0; + +} From 828b2f132e0f3c903020aff9d87a82fab23df6a0 Mon Sep 17 00:00:00 2001 From: Qinghao Shi Date: Fri, 27 Sep 2019 15:59:42 +0100 Subject: [PATCH 168/227] FASTMODEL: enable PSA tests for fastmodel --- targets/targets.json | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/targets/targets.json b/targets/targets.json index 588474246c6..928101029ff 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -8597,7 +8597,7 @@ "ARM_FM": { "inherits": ["Target"], "public": false, - "extra_labels": ["ARM_FM"] + "extra_labels": ["ARM_FM","PSA"] }, "FVP_MPS2": { "inherits": ["ARM_FM"], @@ -8621,6 +8621,7 @@ "SPI", "SPISLAVE", "TSC", + "TRNG", "USTICKER" ], "release_versions": ["5"], From 4e3d31540a46ab64a0f975ae25a609f8808105d5 Mon Sep 17 00:00:00 2001 From: Qinghao Shi Date: Mon, 30 Sep 2019 16:30:51 +0100 Subject: [PATCH 169/227] FASTMODEL: update trng based on comments --- targets/TARGET_ARM_FM/TARGET_FVP_MPS2/trng_api.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/trng_api.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/trng_api.c index b31a26d2423..51ae4c3d256 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/trng_api.c +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/trng_api.c @@ -44,7 +44,6 @@ void trng_free(trng_t *obj) int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length) { (void)obj; - (void)output; for (int i = 0; i < length; ++i) { output[i] = rand() % 256; @@ -52,5 +51,4 @@ int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_l *output_length = length; return 0; - } From ce73f8ecdd0e231fbd5effaae8f269b203b1a068 Mon Sep 17 00:00:00 2001 From: Qinghao Shi Date: Mon, 30 Sep 2019 16:43:44 +0100 Subject: [PATCH 170/227] FASTMODEL: add a comment for TRNG simulation --- targets/TARGET_ARM_FM/TARGET_FVP_MPS2/trng_api.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/trng_api.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/trng_api.c index 51ae4c3d256..ef2e278cbe6 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/trng_api.c +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/trng_api.c @@ -19,7 +19,9 @@ #include "device.h" #include - +/** NOTE: FastModel are software models not contain any TRNG peripheral + * So C library srand() and rand() are used to simulate TRNG device + */ void trng_init(trng_t *obj) { From 2d2fdf7cf9bf4f07332dfbd59f7aca08b1a929e7 Mon Sep 17 00:00:00 2001 From: int_szyk Date: Tue, 24 Sep 2019 10:44:38 +0200 Subject: [PATCH 171/227] CellularUtil prefer_ipv6: check length. Fixes Coverity issue about not checking the length of string before copying it. --- features/cellular/framework/common/CellularUtil.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/features/cellular/framework/common/CellularUtil.cpp b/features/cellular/framework/common/CellularUtil.cpp index 0ad61544ee3..1128955e0e6 100644 --- a/features/cellular/framework/common/CellularUtil.cpp +++ b/features/cellular/framework/common/CellularUtil.cpp @@ -236,7 +236,7 @@ void prefer_ipv6(char *ip, size_t ip_size, char *ip2, size_t ip2_size) if (temp) { // ipv6 was found in ip2 but not in ip ---> we must swap them. Sadly ip and ip2 might not be pointers // so we can't just swap them, must use copy. - if (strlen(ip) < ip2_size && strlen(ip2) < ip_size && strlen(ip) < 64) { + if (strlen(ip) < ip2_size && strlen(ip2) < ip_size && strlen(ip) < 64 && strlen(ip2) < 64) { char tmp[64]; strncpy(tmp, ip, strlen(ip)); tmp[strlen(ip)] = '\0'; From 85f104755fee8aa69c85b6da125eaeb2771c0cd6 Mon Sep 17 00:00:00 2001 From: int_szyk Date: Tue, 24 Sep 2019 11:01:00 +0200 Subject: [PATCH 172/227] CellularStack: remove unnecessary assignment. Fixes Coverity issue about unused variable. --- .../targets/RiotMicro/AT/RM1000_AT_CellularStack.cpp | 3 +-- .../framework/targets/UBLOX/AT/UBLOX_AT_CellularStack.cpp | 6 ++---- 2 files changed, 3 insertions(+), 6 deletions(-) diff --git a/features/cellular/framework/targets/RiotMicro/AT/RM1000_AT_CellularStack.cpp b/features/cellular/framework/targets/RiotMicro/AT/RM1000_AT_CellularStack.cpp index dc202aa8bed..0b73dfb3f50 100644 --- a/features/cellular/framework/targets/RiotMicro/AT/RM1000_AT_CellularStack.cpp +++ b/features/cellular/framework/targets/RiotMicro/AT/RM1000_AT_CellularStack.cpp @@ -281,10 +281,9 @@ nsapi_size_or_error_t RM1000_AT_CellularStack::socket_recvfrom_impl(CellularSock } else { if (count == 0) { // Timeout with nothing received - nsapi_error_size = NSAPI_ERROR_WOULD_BLOCK; success = false; } - size = 0; // This simply to cause an exit + break; } } timer.stop(); diff --git a/features/cellular/framework/targets/UBLOX/AT/UBLOX_AT_CellularStack.cpp b/features/cellular/framework/targets/UBLOX/AT/UBLOX_AT_CellularStack.cpp index 848fbb5b1da..819eef3df86 100644 --- a/features/cellular/framework/targets/UBLOX/AT/UBLOX_AT_CellularStack.cpp +++ b/features/cellular/framework/targets/UBLOX/AT/UBLOX_AT_CellularStack.cpp @@ -302,10 +302,9 @@ nsapi_size_or_error_t UBLOX_AT_CellularStack::socket_recvfrom_impl(CellularSocke } else { if (count == 0) { // Timeout with nothing received - nsapi_error_size = NSAPI_ERROR_WOULD_BLOCK; success = false; } - size = 0; // This simply to cause an exit + break; } } } else if (socket->proto == NSAPI_TCP) { @@ -346,10 +345,9 @@ nsapi_size_or_error_t UBLOX_AT_CellularStack::socket_recvfrom_impl(CellularSocke } else { if (count == 0) { // Timeout with nothing received - nsapi_error_size = NSAPI_ERROR_WOULD_BLOCK; success = false; } - size = 0; // This simply to cause an exit + break; } } } From e7b5a4f32b367abdf26c712f74cf0bf6dbed2c99 Mon Sep 17 00:00:00 2001 From: int_szyk Date: Tue, 24 Sep 2019 11:35:52 +0200 Subject: [PATCH 173/227] sn_coap_builder: remove unnecessary code. Fixes Coverity issue about unused variable. --- features/frameworks/mbed-coap/source/sn_coap_builder.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/features/frameworks/mbed-coap/source/sn_coap_builder.c b/features/frameworks/mbed-coap/source/sn_coap_builder.c index d34edb04788..bd560511576 100644 --- a/features/frameworks/mbed-coap/source/sn_coap_builder.c +++ b/features/frameworks/mbed-coap/source/sn_coap_builder.c @@ -484,15 +484,6 @@ static uint8_t sn_coap_builder_options_calculate_jump_need(const sn_coap_hdr_s * } } - else { - if (src_coap_msg_ptr->uri_path_ptr != 0) { - previous_option_number = (COAP_OPTION_URI_PATH); - } - - if (src_coap_msg_ptr->content_format != COAP_CT_NONE) { - previous_option_number = (COAP_OPTION_CONTENT_FORMAT); - } - } return needed_space; } From 95766d71ac5474005b41be47360d7b7b9547f079 Mon Sep 17 00:00:00 2001 From: int_szyk Date: Tue, 24 Sep 2019 12:53:53 +0200 Subject: [PATCH 174/227] thread_mle_message_handler: fix null comparison. Fixes Coverity issue about comparing nullptr. --- .../source/6LoWPAN/Thread/thread_mle_message_handler.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_mle_message_handler.c b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_mle_message_handler.c index 68df5ed7190..a8253c5f8eb 100644 --- a/features/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_mle_message_handler.c +++ b/features/nanostack/sal-stack-nanostack/source/6LoWPAN/Thread/thread_mle_message_handler.c @@ -514,7 +514,7 @@ static void thread_parse_annoucement(protocol_interface_info_entry_t *cur, mle_m channel_page = ptr[0]; channel = common_read_16_bit(&ptr[1]); - if (linkConfiguration->timestamp == timestamp) { + if (linkConfiguration && linkConfiguration->timestamp == timestamp) { // We received same timestamp tr_debug("Same timestamp"); return; @@ -527,7 +527,7 @@ static void thread_parse_annoucement(protocol_interface_info_entry_t *cur, mle_m } - if (linkConfiguration->timestamp > timestamp) { + if (linkConfiguration && linkConfiguration->timestamp > timestamp) { // We received older time stamp we just announce back to originator channel thread_bootstrap_announce_send(cur, linkConfiguration->channel_page, linkConfiguration->rfChannel, linkConfiguration->panId, linkConfiguration->timestamp, channel); return; From 8e6c6d1d8e7915e23f881c104b1fdfefb9515eb3 Mon Sep 17 00:00:00 2001 From: Kyle Kearney Date: Thu, 19 Sep 2019 11:05:05 -0700 Subject: [PATCH 175/227] Avoid doubly allocating whd thread stack Don't malloc during wifi initialization, as that could cause double allocation in some cases. The thread stack will be allocated by cy_rtos_thread_start if necessary. --- targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_wifi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_wifi.c b/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_wifi.c index 8f8694c22e6..88534398025 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_wifi.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_wifi.c @@ -186,7 +186,7 @@ cy_rslt_t cybsp_wifi_init_primary(whd_interface_t* interface) { whd_init_config_t whd_init_config; whd_init_config.thread_stack_size = (uint32_t)THREAD_STACK_SIZE; - whd_init_config.thread_stack_start = (uint8_t *)malloc(THREAD_STACK_SIZE); + whd_init_config.thread_stack_start = NULL; whd_init_config.thread_priority = (uint32_t)THREAD_PRIORITY; whd_init_config.country = COUNTRY; From 91131a03f78f273b1056176fc2d04427239b7c39 Mon Sep 17 00:00:00 2001 From: Kyle Kearney Date: Thu, 19 Sep 2019 11:47:28 -0700 Subject: [PATCH 176/227] Consolidate/clean up wifi initialization --- .../TARGET_CY8CKIT_062S2_43012/cybsp.c | 37 +++++--- .../TARGET_CY8CKIT_062S2_43012/cybsp.h | 30 ++++++- .../TARGET_CY8CKIT_062_BLE/cybsp.c | 37 ++++++-- .../TARGET_CY8CKIT_062_BLE/cybsp.h | 19 ++++- .../TARGET_CY8CKIT_062_WIFI_BT/cybsp.c | 37 +++++--- .../TARGET_CY8CKIT_062_WIFI_BT/cybsp.h | 17 +++- .../TARGET_CY8CPROTO_062_4343W/cybsp.c | 37 ++++++-- .../TARGET_CY8CPROTO_062_4343W/cybsp.h | 22 ++++- .../TARGET_CY8CPROTO_064_SB/cybsp.c | 44 +++++++++- .../TARGET_CY8CPROTO_064_SB/cybsp.h | 24 +++++- .../TARGET_CYW943012P6EVB_01/cybsp.c | 38 ++++++--- .../TARGET_CYW943012P6EVB_01/cybsp.h | 22 ++++- .../TARGET_PSOC6/common/cy_network_buffer.c | 4 +- .../TARGET_PSOC6/common/cy_network_buffer.h | 4 +- .../TARGET_PSOC6/common/cybsp_wifi.c | 80 +++++++++++------ .../TARGET_PSOC6/common/cybsp_wifi.h | 28 ++++-- .../TARGET_PSOC6/common/cybsp_wifi_sdio.c | 73 ---------------- .../TARGET_PSOC6/common/cybsp_wifi_sdio.h | 85 ------------------- 18 files changed, 382 insertions(+), 256 deletions(-) delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_wifi_sdio.c delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_wifi_sdio.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp.c index 06036122a72..41a3d81d2fa 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp.c @@ -32,11 +32,19 @@ extern "C" { #endif -cy_rslt_t cybsp_init(void) +#if defined(CYBSP_WIFI_CAPABLE) +static cyhal_sdio_t sdio_obj; + +cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void) { - cy_rslt_t result; + return &sdio_obj; +} +#endif - result = cyhal_hwmgr_init(); +cy_rslt_t cybsp_init(void) +{ + /* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */ + cy_rslt_t result = cyhal_hwmgr_init(); init_cycfg_system(); if (CY_RSLT_SUCCESS == result) @@ -77,14 +85,24 @@ cy_rslt_t cybsp_init(void) #endif /* __MBED__ */ #if defined(CYBSP_WIFI_CAPABLE) - /* Initialize SDIO interface. - NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically done - when starting up WiFi. */ + /* Initialize SDIO interface. This must be done before other HAL API calls as some SDIO implementations require + * specific peripheral instances. + * NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically + * done when starting up WiFi. + */ if (CY_RSLT_SUCCESS == result) { - /* Reserves: CYBSP_WIFI_SDIO, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3 - * CYBSP_WIFI_SDIO_CMD, CYBSP_WIFI_SDIO_CLK and CYBSP_WIFI_WL_REG_ON */ - result = cybsp_wifi_sdio_init(); + /* Reserves: CYBSP_WIFI_SDIO, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3 + * CYBSP_WIFI_SDIO_CMD and CYBSP_WIFI_SDIO_CLK. + */ + result = cyhal_sdio_init( + &sdio_obj, + CYBSP_WIFI_SDIO_CMD, + CYBSP_WIFI_SDIO_CLK, + CYBSP_WIFI_SDIO_D0, + CYBSP_WIFI_SDIO_D1, + CYBSP_WIFI_SDIO_D2, + CYBSP_WIFI_SDIO_D3); } #endif /* defined(CYBSP_WIFI_CAPABLE) */ @@ -94,7 +112,6 @@ cy_rslt_t cybsp_init(void) return result; } - #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp.h index 776bfe39bc6..ca34190f912 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp.h @@ -28,7 +28,7 @@ #include "cybsp_types.h" #include "cybsp_core.h" #if defined(CYBSP_WIFI_CAPABLE) -#include "cybsp_wifi_sdio.h" +#include "cyhal_sdio.h" #endif #ifndef __MBED__ #include "cybsp_retarget.h" @@ -41,6 +41,30 @@ extern "C" { #endif -#if defined(__cplusplus) +/** +* \addtogroup group_bsp_functions Functions +* \{ +*/ + +/** + * \brief Initialize all hardware on the board + * \returns CY_RSLT_SUCCESS if the board is sucessfully initialized, if there is + * a problem initializing any hardware it returns an error code specific + * to the hardware module that had a problem. + */ +cy_rslt_t cybsp_init(void); + +#if defined(CYBSP_WIFI_CAPABLE) +/** + * \brief Get the initialized sdio object used for communicating with the WiFi Chip. + * \note This function should only be called after cybsp_init(); + * \returns The initialized sdio object. + */ +cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void); +#endif /* defined(CYBSP_WIFI_CAPABLE) */ + +/** \} group_bsp_functions */ + +#ifdef __cplusplus } -#endif +#endif /* __cplusplus */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp.c index f88ca772de0..e8d1a7d4bc4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp.c @@ -24,17 +24,26 @@ #include #include "cybsp.h" -#include "cycfg_system.h" +#include "cyhal_utils.h" +#include "cycfg.h" #if defined(__cplusplus) extern "C" { #endif -cy_rslt_t cybsp_init(void) +#if defined(CYBSP_WIFI_CAPABLE) +static cyhal_sdio_t sdio_obj; + +cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void) { - cy_rslt_t result; + return &sdio_obj; +} +#endif - result = cyhal_hwmgr_init(); +cy_rslt_t cybsp_init(void) +{ + /* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */ + cy_rslt_t result = cyhal_hwmgr_init(); init_cycfg_system(); if (CY_RSLT_SUCCESS == result) @@ -42,7 +51,12 @@ cy_rslt_t cybsp_init(void) result = cybsp_register_sysclk_pm_callback(); } -#ifndef __MBED__ +#if defined(CYBSP_WIFI_CAPABLE) + /* Initialize SDIO interface. This must be done before other HAL API calls as some SDIO implementations require + * specific peripheral instances. + * NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically + * done when starting up WiFi. + */ if (CY_RSLT_SUCCESS == result) { /* Initialize User LEDs */ @@ -68,8 +82,19 @@ cy_rslt_t cybsp_init(void) * clock dividers */ result = cybsp_retarget_init(); } + /* Reserves: CYBSP_WIFI_SDIO, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3 + * CYBSP_WIFI_SDIO_CMD and CYBSP_WIFI_SDIO_CLK. + */ + result = cyhal_sdio_init( + &sdio_obj, + CYBSP_WIFI_SDIO_CMD, + CYBSP_WIFI_SDIO_CLK, + CYBSP_WIFI_SDIO_D0, + CYBSP_WIFI_SDIO_D1, + CYBSP_WIFI_SDIO_D2, + CYBSP_WIFI_SDIO_D3); } -#endif /* __MBED__ */ +#endif /* defined(CYBSP_WIFI_CAPABLE) */ /* CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was reserved by * user previously. Please review the Device Configurator (design.modus) and the BSP reservation list diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp.h index 33d9e0352e0..e7529ed433a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp.h @@ -37,6 +37,21 @@ extern "C" { #endif -#if defined(__cplusplus) +/** +* \addtogroup group_bsp_functions Functions +* \{ +*/ +#if defined(CYBSP_WIFI_CAPABLE) +/** + * \brief Get the initialized sdio object used for communicating with the WiFi Chip. + * \note This function should only be called after cybsp_init(); + * \returns The initialized sdio object. + */ +cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void); +#endif /* defined(CYBSP_WIFI_CAPABLE) */ + +/** \} group_bsp_functions */ + +#ifdef __cplusplus } -#endif +#endif /* __cplusplus */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp.c index fdda76e36f4..880d747c2d4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp.c @@ -32,11 +32,19 @@ extern "C" { #endif -cy_rslt_t cybsp_init(void) +#if defined(CYBSP_WIFI_CAPABLE) +static cyhal_sdio_t sdio_obj; + +cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void) { - cy_rslt_t result; + return &sdio_obj; +} +#endif - result = cyhal_hwmgr_init(); +cy_rslt_t cybsp_init(void) +{ + /* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */ + cy_rslt_t result = cyhal_hwmgr_init(); init_cycfg_system(); if (CY_RSLT_SUCCESS == result) @@ -74,15 +82,24 @@ cy_rslt_t cybsp_init(void) #endif /* __MBED__ */ #if defined(CYBSP_WIFI_CAPABLE) - /* Initialize UDB SDIO interface. This must be done before any other HAL API attempts to allocate clocks or DMA - instances. The UDB SDIO interface uses specific instances which are reserved as part of this call. - NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically done - when starting up WiFi. */ + /* Initialize SDIO interface. This must be done before other HAL API calls as some SDIO implementations require + * specific peripheral instances. + * NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically + * done when starting up WiFi. + */ if (CY_RSLT_SUCCESS == result) { - /* Reserves: CYBSP_WIFI_SDIO, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3 - * CYBSP_WIFI_SDIO_CMD, CYBSP_WIFI_SDIO_CLK and CYBSP_WIFI_WL_REG_ON */ - result = cybsp_wifi_sdio_init(); + /* Reserves: CYBSP_WIFI_SDIO, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3 + * CYBSP_WIFI_SDIO_CMD and CYBSP_WIFI_SDIO_CLK. + */ + result = cyhal_sdio_init( + &sdio_obj, + CYBSP_WIFI_SDIO_CMD, + CYBSP_WIFI_SDIO_CLK, + CYBSP_WIFI_SDIO_D0, + CYBSP_WIFI_SDIO_D1, + CYBSP_WIFI_SDIO_D2, + CYBSP_WIFI_SDIO_D3); } #endif /* defined(CYBSP_WIFI_CAPABLE) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp.h index 1d404085a17..ff576cae162 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp.h @@ -28,7 +28,7 @@ #include "cybsp_types.h" #include "cybsp_core.h" #if defined(CYBSP_WIFI_CAPABLE) -#include "cybsp_wifi_sdio.h" +#include "cyhal_sdio.h" #endif #ifndef __MBED__ #include "cybsp_retarget.h" @@ -47,6 +47,17 @@ extern cyhal_uart_t cybsp_debug_uart; extern cyhal_i2c_t cybsp_i2c; extern cyhal_rtc_t cybsp_rtc; -#if defined(__cplusplus) +#if defined(CYBSP_WIFI_CAPABLE) +/** + * \brief Get the initialized sdio object used for communicating with the WiFi Chip. + * \note This function should only be called after cybsp_init(); + * \returns The initialized sdio object. + */ +cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void); +#endif /* defined(CYBSP_WIFI_CAPABLE) */ + +/** \} group_bsp_functions */ + +#ifdef __cplusplus } -#endif +#endif /* __cplusplus */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp.c index f0a2a096268..3ea4df46701 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp.c @@ -25,17 +25,26 @@ #include #include "cybsp.h" +#include "cyhal_utils.h" #include "cycfg.h" #if defined(__cplusplus) extern "C" { #endif -cy_rslt_t cybsp_init(void) +#if defined(CYBSP_WIFI_CAPABLE) +static cyhal_sdio_t sdio_obj; + +cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void) { - cy_rslt_t result; + return &sdio_obj; +} +#endif - result = cyhal_hwmgr_init(); +cy_rslt_t cybsp_init(void) +{ + /* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */ + cy_rslt_t result = cyhal_hwmgr_init(); init_cycfg_system(); if (CY_RSLT_SUCCESS == result) @@ -65,14 +74,24 @@ cy_rslt_t cybsp_init(void) #endif /* __MBED__ */ #if defined(CYBSP_WIFI_CAPABLE) - /* Initialize SDIO interface. - NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically done - when starting up WiFi. */ + /* Initialize SDIO interface. This must be done before other HAL API calls as some SDIO implementations require + * specific peripheral instances. + * NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically + * done when starting up WiFi. + */ if (CY_RSLT_SUCCESS == result) { - /* Reserves: CYBSP_WIFI_SDIO, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3 - * CYBSP_WIFI_SDIO_CMD, CYBSP_WIFI_SDIO_CLK and CYBSP_WIFI_WL_REG_ON */ - result = cybsp_wifi_sdio_init(); + /* Reserves: CYBSP_WIFI_SDIO, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3 + * CYBSP_WIFI_SDIO_CMD and CYBSP_WIFI_SDIO_CLK. + */ + result = cyhal_sdio_init( + &sdio_obj, + CYBSP_WIFI_SDIO_CMD, + CYBSP_WIFI_SDIO_CLK, + CYBSP_WIFI_SDIO_D0, + CYBSP_WIFI_SDIO_D1, + CYBSP_WIFI_SDIO_D2, + CYBSP_WIFI_SDIO_D3); } #endif /* defined(CYBSP_WIFI_CAPABLE) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp.h index 2cb1397f9a3..356cf3f12c3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp.h @@ -28,7 +28,7 @@ #include "cybsp_types.h" #include "cybsp_core.h" #if defined(CYBSP_WIFI_CAPABLE) -#include "cybsp_wifi_sdio.h" +#include "cyhal_sdio.h" #endif #ifndef __MBED__ #include "cybsp_retarget.h" @@ -39,6 +39,22 @@ extern "C" { #endif -#if defined(__cplusplus) +/** +* \addtogroup group_bsp_functions Functions +* \{ +*/ + +#if defined(CYBSP_WIFI_CAPABLE) +/** + * \brief Get the initialized sdio object used for communicating with the WiFi Chip. + * \note This function should only be called after cybsp_init(); + * \returns The initialized sdio object. + */ +cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void); +#endif /* defined(CYBSP_WIFI_CAPABLE) */ + +/** \} group_bsp_functions */ + +#ifdef __cplusplus } -#endif +#endif /* __cplusplus */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.c index ea7e81e5927..e98ad6a1a1d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.c @@ -23,17 +23,28 @@ * limitations under the License. *******************************************************************************/ +#include #include "cybsp.h" +#include "cyhal_utils.h" #include "cycfg.h" #if defined(__cplusplus) extern "C" { #endif -cy_rslt_t cybsp_init(void) +#if defined(CYBSP_WIFI_CAPABLE) +static cyhal_sdio_t sdio_obj; + +cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void) { - cy_rslt_t result = CY_RSLT_SUCCESS; + return &sdio_obj; +} +#endif +cy_rslt_t cybsp_init(void) +{ + /* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */ + cy_rslt_t result = cyhal_hwmgr_init(); init_cycfg_system(); result = cybsp_register_sysclk_pm_callback(); @@ -52,8 +63,33 @@ cy_rslt_t cybsp_init(void) result = cybsp_retarget_init(); } } -#endif - + +#if defined(CYBSP_WIFI_CAPABLE) + /* Initialize SDIO interface. This must be done before other HAL API calls as some SDIO implementations require + * specific peripheral instances. + * NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically + * done when starting up WiFi. + */ + if (CY_RSLT_SUCCESS == result) + { + /* Reserves: CYBSP_WIFI_SDIO, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3 + * CYBSP_WIFI_SDIO_CMD and CYBSP_WIFI_SDIO_CLK. + */ + result = cyhal_sdio_init( + &sdio_obj, + CYBSP_WIFI_SDIO_CMD, + CYBSP_WIFI_SDIO_CLK, + CYBSP_WIFI_SDIO_D0, + CYBSP_WIFI_SDIO_D1, + CYBSP_WIFI_SDIO_D2, + CYBSP_WIFI_SDIO_D3); + } +#endif /* defined(CYBSP_WIFI_CAPABLE) */ + + /* CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was reserved by + * user previously. Please review the Device Configurator (design.modus) and the BSP reservation list + * (cyreservedresources.list) to make sure no resources are reserved by both. + */ return result; } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.h index afd1a4dd006..1aa9e3d7eb3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.h @@ -30,7 +30,29 @@ #ifndef __MBED__ #include "cybsp_retarget.h" #endif /* __MBED__ */ +#if defined(CYBSP_WIFI_CAPABLE) +#include "cyhal_sdio.h" +#endif #if defined(__cplusplus) -} +extern "C" { #endif +/** +* \addtogroup group_bsp_functions Functions +* \{ +*/ + +#if defined(CYBSP_WIFI_CAPABLE) +/** + * \brief Get the initialized sdio object used for communicating with the WiFi Chip. + * \note This function should only be called after cybsp_init(); + * \returns The initialized sdio object. + */ +cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void); +#endif /* defined(CYBSP_WIFI_CAPABLE) */ + +/** \} group_bsp_functions */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/cybsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/cybsp.c index 7f6f29ad83a..ef48c9e578a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/cybsp.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/cybsp.c @@ -25,17 +25,26 @@ #include #include "cybsp.h" +#include "cyhal_utils.h" #include "cycfg.h" #if defined(__cplusplus) extern "C" { #endif -cy_rslt_t cybsp_init(void) +#if defined(CYBSP_WIFI_CAPABLE) +static cyhal_sdio_t sdio_obj; + +cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void) { - cy_rslt_t result; + return &sdio_obj; +} +#endif - result = cyhal_hwmgr_init(); +cy_rslt_t cybsp_init(void) +{ + /* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */ + cy_rslt_t result = cyhal_hwmgr_init(); init_cycfg_system(); if (CY_RSLT_SUCCESS == result) @@ -70,15 +79,24 @@ cy_rslt_t cybsp_init(void) #endif /* __MBED__ */ #if defined(CYBSP_WIFI_CAPABLE) - /* Initialize UDB SDIO interface. This must be done before any other HAL API attempts to allocate clocks or DMA - instances. The UDB SDIO interface uses specific instances which are reserved as part of this call. - NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically done - when starting up WiFi. */ + /* Initialize SDIO interface. This must be done before other HAL API calls as some SDIO implementations require + * specific peripheral instances. + * NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically + * done when starting up WiFi. + */ if (CY_RSLT_SUCCESS == result) { - /* Reserves: CYBSP_WIFI_SDIO, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3 - * CYBSP_WIFI_SDIO_CMD, CYBSP_WIFI_SDIO_CLK and CYBSP_WIFI_WL_REG_ON */ - result = cybsp_wifi_sdio_init(); + /* Reserves: CYBSP_WIFI_SDIO, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3 + * CYBSP_WIFI_SDIO_CMD and CYBSP_WIFI_SDIO_CLK. + */ + result = cyhal_sdio_init( + &sdio_obj, + CYBSP_WIFI_SDIO_CMD, + CYBSP_WIFI_SDIO_CLK, + CYBSP_WIFI_SDIO_D0, + CYBSP_WIFI_SDIO_D1, + CYBSP_WIFI_SDIO_D2, + CYBSP_WIFI_SDIO_D3); } #endif /* defined(CYBSP_WIFI_CAPABLE) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/cybsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/cybsp.h index 7f1228bd8f7..47e6d96fa28 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/cybsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/cybsp.h @@ -28,7 +28,7 @@ #include "cybsp_types.h" #include "cybsp_core.h" #if defined(CYBSP_WIFI_CAPABLE) -#include "cybsp_wifi_sdio.h" +#include "cyhal_sdio.h" #endif #ifndef __MBED__ #include "cybsp_retarget.h" @@ -39,6 +39,22 @@ extern "C" { #endif -#if defined(__cplusplus) +/** +* \addtogroup group_bsp_functions Functions +* \{ +*/ + +#if defined(CYBSP_WIFI_CAPABLE) +/** + * \brief Get the initialized sdio object used for communicating with the WiFi Chip. + * \note This function should only be called after cybsp_init(); + * \returns The initialized sdio object. + */ +cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void); +#endif /* defined(CYBSP_WIFI_CAPABLE) */ + +/** \} group_bsp_functions */ + +#ifdef __cplusplus } -#endif +#endif /* __cplusplus */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/common/cy_network_buffer.c b/targets/TARGET_Cypress/TARGET_PSOC6/common/cy_network_buffer.c index 01d2cb06dad..36f8e95c5fd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/common/cy_network_buffer.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/common/cy_network_buffer.c @@ -23,7 +23,7 @@ * limitations under the License. *******************************************************************************/ -#if defined(TARGET_WHD) +#if defined(CYBSP_WIFI_CAPABLE) #include #include "cy_network_buffer.h" @@ -108,4 +108,4 @@ whd_result_t cy_buffer_add_remove_at_front(whd_buffer_t *buffer, int32_t add_rem return WHD_SUCCESS; } -#endif /* defined(TARGET_WHD) */ +#endif /* defined(CYBSP_WIFI_CAPABLE) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/common/cy_network_buffer.h b/targets/TARGET_Cypress/TARGET_PSOC6/common/cy_network_buffer.h index 17dc536de25..a8e2aad2c35 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/common/cy_network_buffer.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/common/cy_network_buffer.h @@ -32,7 +32,7 @@ */ #pragma once -#if defined(TARGET_WHD) +#if defined(CYBSP_WIFI_CAPABLE) #include #include @@ -176,6 +176,6 @@ void cy_network_process_ethernet_data(whd_interface_t interface, whd_buffer_t bu } #endif /* __cplusplus */ -#endif /* defined(TARGET_WHD) */ +#endif /* defined(CYBSP_WIFI_CAPABLE) */ /** \} group_bsp_network_buffer */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_wifi.c b/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_wifi.c index 88534398025..a80bdc6e301 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_wifi.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_wifi.c @@ -23,13 +23,12 @@ *******************************************************************************/ #if defined(CYBSP_WIFI_CAPABLE) -#include "cybsp_types.h" +#include "cybsp.h" #include "cybsp_wifi.h" #include "cy_network_buffer.h" #include "cyabs_rtos.h" #include "whd_types.h" #include "cyhal.h" -#include "cybsp_wifi_sdio.h" #include "cycfg.h" #if defined(__cplusplus) @@ -40,6 +39,7 @@ extern "C" { #define THREAD_PRIORITY CY_RTOS_PRIORITY_HIGH #define COUNTRY WHD_COUNTRY_AUSTRALIA #define DEFAULT_OOB_PIN 0 +#define WLAN_POWER_UP_DELAY_MS 250 #define SDIO_ENUMERATION_TRIES 500 #define SDIO_RETRY_DELAY_MS 1 @@ -83,6 +83,7 @@ extern "C" { #endif /* (CY_SDIO_BUS_USE_OOB_INTR != 0) */ static whd_driver_t whd_drv; + static whd_buffer_funcs_t buffer_ops = { .whd_host_buffer_get = cy_host_buffer_get, @@ -152,32 +153,49 @@ static cy_rslt_t cybsp_sdio_enumerate(const cyhal_sdio_t *sdio_object) return result; } +static cy_rslt_t reset_wifi_chip(void) +{ + /* WiFi into reset */ + cy_rslt_t result = cyhal_gpio_init(CYBSP_WIFI_WL_REG_ON, CYHAL_GPIO_DIR_OUTPUT, CYHAL_GPIO_DRIVE_PULLUP, 0); + if(result == CY_RSLT_SUCCESS) + { + /* WiFi out of reset */ + cyhal_gpio_write(CYBSP_WIFI_WL_REG_ON, true); + Cy_SysLib_Delay(WLAN_POWER_UP_DELAY_MS); + } + return result; +} + static cy_rslt_t init_sdio_bus(void) { - cyhal_sdio_t* sdio_p = cybsp_get_wifi_sdio_obj(); - cy_rslt_t result = cybsp_sdio_enumerate(sdio_p); + cy_rslt_t result = reset_wifi_chip(); if(result == CY_RSLT_SUCCESS) { - whd_sdio_config_t whd_sdio_config; - whd_oob_config_t oob_config; - cyhal_sdio_cfg_t config; - - oob_config.host_oob_pin = CY_WIFI_HOST_WAKE_GPIO; - oob_config.dev_gpio_sel = DEFAULT_OOB_PIN; - oob_config.is_falling_edge = (CY_WIFI_HOST_WAKE_IRQ_EVENT == CYHAL_GPIO_IRQ_FALL) - ? WHD_TRUE - : WHD_FALSE; - oob_config.intr_priority = CY_WIFI_OOB_INTR_PRIORITY; - - whd_sdio_config.sdio_1bit_mode = WHD_FALSE; - whd_sdio_config.high_speed_sdio_clock = WHD_FALSE; - whd_sdio_config.oob_config = oob_config; - whd_bus_sdio_attach(whd_drv, &whd_sdio_config, sdio_p); - - /* Increase frequency to 25 MHz for better performance */ - config.frequencyhal_hz = 25000000; - config.block_size = 0; - cyhal_sdio_configure(sdio_p, &config); + cyhal_sdio_t* sdio_p = cybsp_get_wifi_sdio_obj(); + cy_rslt_t result = cybsp_sdio_enumerate(sdio_p); + if(result == CY_RSLT_SUCCESS) + { + whd_sdio_config_t whd_sdio_config; + whd_oob_config_t oob_config; + cyhal_sdio_cfg_t config; + + oob_config.host_oob_pin = CY_WIFI_HOST_WAKE_GPIO; + oob_config.dev_gpio_sel = DEFAULT_OOB_PIN; + oob_config.is_falling_edge = (CY_WIFI_HOST_WAKE_IRQ_EVENT == CYHAL_GPIO_IRQ_FALL) + ? WHD_TRUE + : WHD_FALSE; + oob_config.intr_priority = CY_WIFI_OOB_INTR_PRIORITY; + + whd_sdio_config.sdio_1bit_mode = WHD_FALSE; + whd_sdio_config.high_speed_sdio_clock = WHD_FALSE; + whd_sdio_config.oob_config = oob_config; + whd_bus_sdio_attach(whd_drv, &whd_sdio_config, sdio_p); + + /* Increase frequency to 25 MHz for better performance */ + config.frequencyhal_hz = 25000000; + config.block_size = 0; + cyhal_sdio_configure(sdio_p, &config); + } } return result; } @@ -207,6 +225,20 @@ cy_rslt_t cybsp_wifi_init_secondary(whd_interface_t* interface, whd_mac_t* mac_a return whd_add_secondary_interface(whd_drv, mac_address, interface); } +cy_rslt_t cybsp_wifi_deinit(whd_interface_t interface) +{ + cy_rslt_t result = whd_wifi_off(interface); + if(result == CY_RSLT_SUCCESS) + { + result = whd_deinit(interface); + if(result == CY_RSLT_SUCCESS) + { + cyhal_gpio_free(CYBSP_WIFI_WL_REG_ON); + } + } + return result; +} + whd_driver_t cybsp_get_wifi_driver(void) { return whd_drv; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_wifi.h b/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_wifi.h index b5de32ef665..31bfc82566e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_wifi.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_wifi.h @@ -48,9 +48,12 @@ extern "C" { * \{ */ -/** Initialization of the wifi driver failed. */ +/** Initialization of the WiFi driver failed. */ #define CYBSP_RSLT_WIFI_INIT_FAILED (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 4)) +/** SDIO enumeration failed. */ +#define CYBSP_RSLT_WIFI_SDIO_ENUM_TIMEOUT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 5)) + /** \} group_bsp_board_macros */ /** @@ -58,17 +61,21 @@ extern "C" { * \{ */ -/** Initializes the primary interface for the wifi driver on the board. This function does the following - * 1) Initializes the wifi driver. - * 2) Turns on the WIFI chip. +/** Initializes the primary interface for the WiFi driver on the board. This function + * does the following + * 1) Initializes the WiFi driver. + * 2) Turns on the WiFi chip. + * + * @note This function cannot be called multiple times. The user needs to first de-initialize + * before calling this function again. * * @param[out] interface Interface to be initialized * @return CY_RSLT_SUCCESS for successful initialization or error if initialization failed. */ cy_rslt_t cybsp_wifi_init_primary(whd_interface_t* interface); -/** This function initializes and adds a secondary interface to the wifi driver. - * @note This function does not initialize the wifi driver or turn on the wifi chip. +/** This function initializes and adds a secondary interface to the WiFi driver. + * @note This function does not initialize the WiFi driver or turn on the WiFi chip. * That is required to be done by the primary interface * * @param[out] interface Interface to be initialized @@ -77,6 +84,15 @@ cy_rslt_t cybsp_wifi_init_primary(whd_interface_t* interface); */ cy_rslt_t cybsp_wifi_init_secondary(whd_interface_t* interface, whd_mac_t* mac_address); +/** De-initializes all WiFi interfaces and the WiFi driver. This function does the following + * 1) Deinitializes all WiFi interfaces and WiFi driver. + * 2) Turns off the WiFi chip. + * + * @param[in] interface Interface to be de-initialized. + * @return CY_RSLT_SUCCESS for successful de-initialization or error if de-initialization failed. + */ +cy_rslt_t cybsp_wifi_deinit(whd_interface_t interface); + /** Gets the wifi driver instance initialized by the driver. This should only be called * after the interface is initialized by cybsp_wifi_init_primary(). * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_wifi_sdio.c b/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_wifi_sdio.c deleted file mode 100644 index 1780057e370..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_wifi_sdio.c +++ /dev/null @@ -1,73 +0,0 @@ -/***************************************************************************//** -* \file cybsp_wifi_sdio.c -* -* \brief -* Utility functions to intialize the SDIO communication bus used to -* communicate with the WiFi radio. -* -******************************************************************************** -* \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ -#include "cybsp_wifi_sdio.h" -#include "cyhal_gpio_impl.h" -#include "cybsp_types.h" - -#if defined(CYBSP_WIFI_CAPABLE) - -#define WLAN_POWER_UP_DELAY_MS 250 - -static cyhal_sdio_t sdio_obj; - -static cy_rslt_t reset_wifi_chip(void) -{ - /* WiFi into reset */ - cy_rslt_t result = cyhal_gpio_init(CYBSP_WIFI_WL_REG_ON, CYHAL_GPIO_DIR_OUTPUT, CYHAL_GPIO_DRIVE_PULLUP, 0); - if(result == CY_RSLT_SUCCESS) - { - /* WiFi out of reset */ - cyhal_gpio_write(CYBSP_WIFI_WL_REG_ON, true); - Cy_SysLib_Delay(WLAN_POWER_UP_DELAY_MS); - } - return result; -} - -void cybsp_wifi_sdio_deinit(void) -{ - cyhal_sdio_free(&sdio_obj); - cyhal_gpio_free(CYBSP_WIFI_WL_REG_ON); -} - -cy_rslt_t cybsp_wifi_sdio_init(void) -{ - cy_rslt_t result = cyhal_sdio_init(&sdio_obj, CYBSP_WIFI_SDIO_CMD, CYBSP_WIFI_SDIO_CLK, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3); - if(result == CY_RSLT_SUCCESS) - { - cy_rslt_t result = reset_wifi_chip(); - if (result != CY_RSLT_SUCCESS) - { - cybsp_wifi_sdio_deinit(); - } - } - return result; -} - -cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void) -{ - return &sdio_obj; -} - -#endif /* defined(CYBSP_WIFI_CAPABLE) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_wifi_sdio.h b/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_wifi_sdio.h deleted file mode 100644 index f8152cbaf05..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_wifi_sdio.h +++ /dev/null @@ -1,85 +0,0 @@ -/***************************************************************************//** -* \file cybsp_wifi_sdio.h -* -* \brief -* Utility functions to intialize the SDIO communication bus used to -* communicate with the WiFi radio. -* -******************************************************************************** -* \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -/** -* \addtogroup group_bsp_board_wifi WiFi -* \ingroup group_bsp_abstraction -* \{ -* Basic abstraction layer for dealing with boards containing a Cypress MCU. This -* API provides convenience methods for initializing and manipulating different -* hardware found on the board. -* -* \defgroup group_bsp_board_wifi_macros Macros -* \defgroup group_bsp_board_wifi_functions Functions -*/ -#pragma once - -#include "cy_result.h" -#include "cyhal.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/** -* \addtogroup group_bsp_board_wifi_macros -* \{ -*/ - -/** SDIO enumeration failed. */ -#define CYBSP_RSLT_WIFI_SDIO_ENUM_TIMEOUT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 5)) - -/** \} group_bsp_board_wifi_macros */ - -/** -* \addtogroup group_bsp_board_wifi_functions -* \{ -*/ - -/** Initializes and enumerates the SDIO object connected to the wifi chip. - * The following operations are performed, - * -# Initializes the SDIO interface on the board connect to the wifi chip. - * -# Resets the wifi chip. - * - * @return CY_RSLT_SUCCESS for successful initialization or error if initialization failed. - */ -cy_rslt_t cybsp_wifi_sdio_init(void); - -/** Frees up any resources allocated by the cybsp_wifi_sdio_init() */ -void cybsp_wifi_sdio_deinit(void); - -/** Get the initialized sdio object. This should only be called after cybsp_wifi_sdio_init(); - * - * @return The initialized and enumerated sdio object. - */ -cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void); - -/** \} group_bsp_board_wifi_functions */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -/** \} group_bsp_board_wifi */ \ No newline at end of file From 85ba6ea4f36c06ebdd87e5aa8e8fd2464bbe570d Mon Sep 17 00:00:00 2001 From: Kyle Kearney Date: Thu, 19 Sep 2019 11:53:07 -0700 Subject: [PATCH 177/227] Simplify BSP contents Remove some (Cypress-proprietary) BSP interfaces and hardware initialization from the BSPs which is better implemented by a library or application firmware. Move some remaining functionality from common to the individual targets. --- .../TARGET_CY8CKIT_062S2_43012/cybsp.c | 75 ++-- .../TARGET_CY8CKIT_062S2_43012/cybsp.h | 23 +- .../TARGET_CY8CKIT_062S2_43012/cybsp_types.h | 349 +++++++-------- .../TARGET_CY8CKIT_062_BLE/cybsp.c | 65 +-- .../TARGET_CY8CKIT_062_BLE/cybsp.h | 36 +- .../TARGET_CY8CKIT_062_BLE/cybsp_types.h | 268 ++++++------ .../TARGET_CY8CKIT_062_WIFI_BT/cybsp.c | 72 ++-- .../TARGET_CY8CKIT_062_WIFI_BT/cybsp.h | 42 +- .../TARGET_CY8CKIT_062_WIFI_BT/cybsp_types.h | 314 +++++++------- .../TARGET_CY8CPROTO_062_4343W/cybsp.c | 64 +-- .../TARGET_CY8CPROTO_062_4343W/cybsp.h | 31 +- .../TARGET_CY8CPROTO_062_4343W/cybsp_types.h | 172 ++++---- .../TARGET_CY8CPROTO_064_SB/cybsp.c | 52 ++- .../TARGET_CY8CPROTO_064_SB/cybsp.h | 31 +- .../TARGET_CY8CPROTO_064_SB/cybsp_types.h | 157 ++++--- .../TARGET_CYW943012P6EVB_01/cybsp.c | 69 +-- .../TARGET_CYW943012P6EVB_01/cybsp.h | 31 +- .../TARGET_CYW943012P6EVB_01/cybsp_types.h | 408 +++++++----------- .../TARGET_PSOC6/common/cybsp_core.c | 92 ---- .../TARGET_PSOC6/common/cybsp_core.h | 150 ------- 20 files changed, 1133 insertions(+), 1368 deletions(-) delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_core.c delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_core.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp.c index 41a3d81d2fa..f460f83ac42 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp.c @@ -1,9 +1,9 @@ /***************************************************************************//** -* \file CY8CKIT-062S2-43012/cybsp.c +* \file cybsp.c * * Description: -* Provides APIs for interacting with the hardware contained on the Cypress -* CY8CKIT-062S2-43012 pioneer kit. +* Provides initialization code for starting up the hardware contained on the +* Cypress board. * ******************************************************************************** * \copyright @@ -32,6 +32,15 @@ extern "C" { #endif +/* The sysclk deep sleep callback is recommended to be the last callback that +* is executed before entry into deep sleep mode and the first one upon +* exit the deep sleep mode. +* Doing so minimizes the time spent on low power mode entry and exit. +*/ +#ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER + #define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u) +#endif + #if defined(CYBSP_WIFI_CAPABLE) static cyhal_sdio_t sdio_obj; @@ -41,6 +50,29 @@ cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void) } #endif +/** + * Registers a power management callback that prepares the clock system + * for entering deep sleep mode and restore the clocks upon wakeup from deep sleep. + * NOTE: This is called automatically as part of \ref cybsp_init + */ +static cy_rslt_t cybsp_register_sysclk_pm_callback(void) +{ + cy_rslt_t result = CY_RSLT_SUCCESS; + static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = {NULL, NULL}; + static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback = { + .callback = &Cy_SysClk_DeepSleepCallback, + .type = CY_SYSPM_DEEPSLEEP, + .callbackParams = &cybsp_sysclk_pm_callback_param, + .order = CYBSP_SYSCLK_PM_CALLBACK_ORDER + }; + + if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback)) + { + result = CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK; + } + return result; +} + cy_rslt_t cybsp_init(void) { /* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */ @@ -52,38 +84,6 @@ cy_rslt_t cybsp_init(void) result = cybsp_register_sysclk_pm_callback(); } -#ifndef __MBED__ - if (CY_RSLT_SUCCESS == result) - { - /* Initialize User LEDs */ - /* Reserves: CYBSP_USER_LED1 */ - result |= cybsp_led_init(CYBSP_USER_LED1); - /* Reserves: CYBSP_USER_LED2 */ - result |= cybsp_led_init(CYBSP_USER_LED2); - /* Reserves: CYBSP_USER_LED3 */ - result |= cybsp_led_init(CYBSP_USER_LED3); - /* Reserves: CYBSP_USER_LED4 */ - result |= cybsp_led_init(CYBSP_USER_LED4); - /* Reserves: CYBSP_USER_LED5 */ - result |= cybsp_led_init(CYBSP_USER_LED5); - /* Initialize User Buttons */ - /* Reserves: CYBSP_USER_BTN1 */ - result |= cybsp_btn_init(CYBSP_USER_BTN1); - /* Reserves: CYBSP_USER_BTN2 */ - result |= cybsp_btn_init(CYBSP_USER_BTN2); - - CY_ASSERT(CY_RSLT_SUCCESS == result); - - /* Initialize retargetting stdio to 'DEBUG_UART' peripheral */ - if (CY_RSLT_SUCCESS == result) - { - /* Reserves: CYBSP_DEBUG_UART_RX, CYBSP_DEBUG_UART_TX, CYBSP_DEBUG_UART_RTS, CYBSP_DEBUG_UART_CTS - * corresponding SCB instance and one of available clock dividers */ - result = cybsp_retarget_init(); - } - } -#endif /* __MBED__ */ - #if defined(CYBSP_WIFI_CAPABLE) /* Initialize SDIO interface. This must be done before other HAL API calls as some SDIO implementations require * specific peripheral instances. @@ -107,8 +107,9 @@ cy_rslt_t cybsp_init(void) #endif /* defined(CYBSP_WIFI_CAPABLE) */ /* CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was reserved by - * user previously. Please review the Device Configurator (design.modus) and the BSP reservation list - * (cyreservedresources.list) to make sure no resources are reserved by both. */ + * user previously. Please review the Device Configurator (design.modus) and the BSP reservation list + * (cyreservedresources.list) to make sure no resources are reserved by both. + */ return result; } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp.h index ca34190f912..bd930510eda 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp.h @@ -1,9 +1,8 @@ /***************************************************************************//** -* \file CY8CKIT-062S2-43012/cybsp.h +* \file cybsp.h * -* Description: -* Provides APIs for interacting with the hardware contained on the Cypress -* CY8CKIT-062S2-43012 pioneer kit. +* \brief +* Basic API for setting up boards containing a Cypress MCU. * ******************************************************************************** * \copyright @@ -25,21 +24,25 @@ #pragma once +#include "cy_result.h" #include "cybsp_types.h" -#include "cybsp_core.h" #if defined(CYBSP_WIFI_CAPABLE) #include "cyhal_sdio.h" #endif -#ifndef __MBED__ -#include "cybsp_retarget.h" -#include "cybsp_serial_flash.h" -#include "cybsp_rgb_led.h" -#endif /* __MBED__ */ #if defined(__cplusplus) extern "C" { #endif +/** +* \addtogroup group_bsp_macros Macros +* \{ +*/ + +/** Failed to configure sysclk power management callback */ +#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0)) + +/** \} group_bsp_macros */ /** * \addtogroup group_bsp_functions Functions diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp_types.h index cfec04a1e25..417505e83c2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp_types.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp_types.h @@ -25,256 +25,221 @@ #pragma once -#include "cyhal.h" +#include "cyhal_pin_package.h" #if defined(__cplusplus) extern "C" { #endif + +/** +* \addtogroup group_bsp_pin_state Pin States +* \{ +*/ + +/** Pin state for the LED on. */ +#define CYBSP_LED_STATE_ON (0U) +/** Pin state for the LED off. */ +#define CYBSP_LED_STATE_OFF (1U) + +/** Pin state for when a button is pressed. */ +#define CYBSP_BTN_PRESSED (0U) +/** Pin state for when a button is released. */ +#define CYBSP_BTN_OFF (1U) + +/** \} group_bsp_pin_state */ + + /** * \addtogroup group_bsp_pins Pin Mappings * \{ */ -// Arduino connector namings -/** Arduino A0 */ -#define CYBSP_A0 P10_0 -/** Arduino A1 */ -#define CYBSP_A1 P10_1 -/** Arduino A2 */ -#define CYBSP_A2 P10_2 -/** Arduino A3 */ -#define CYBSP_A3 P10_3 -/** Arduino A4 */ -#define CYBSP_A4 P10_4 -/** Arduino A5 */ -#define CYBSP_A5 P10_5 -/** Arduino D0 */ -#define CYBSP_D0 P5_0 -/** Arduino D1 */ -#define CYBSP_D1 P5_1 -/** Arduino D2 */ -#define CYBSP_D2 P5_2 -/** Arduino D3 */ -#define CYBSP_D3 P5_3 -/** Arduino D4 */ -#define CYBSP_D4 P5_4 -/** Arduino D5 */ -#define CYBSP_D5 P5_5 -/** Arduino D6 */ -#define CYBSP_D6 P5_6 -/** Arduino D7 */ -#define CYBSP_D7 P0_2 -/** Arduino D8 */ -#define CYBSP_D8 P13_0 -/** Arduino D9 */ -#define CYBSP_D9 P13_1 -/** Arduino D10 */ -#define CYBSP_D10 P12_3 -/** Arduino D11 */ -#define CYBSP_D11 P12_0 -/** Arduino D12 */ -#define CYBSP_D12 P12_1 -/** Arduino D13 */ -#define CYBSP_D13 P12_2 -/** Arduino D14 */ -#define CYBSP_D14 P6_1 -/** Arduino D15 */ -#define CYBSP_D15 P6_0 +/** +* \addtogroup group_bsp_pins_led LED Pins +* \{ +*/ +/** LED 8; User LED1 (orange) */ +#define CYBSP_LED8 (P1_5) +/** LED 9; User LED2 (red) */ +#define CYBSP_LED9 (P11_1) +/** LED 5: RGB LED - Red; User LED3 */ +#define CYBSP_LED_RGB_RED (P1_1) +/** LED 5: RGB LED - Green; User LED4 */ +#define CYBSP_LED_RGB_GREEN (P0_5) +/** LED 5: RGB LED - Blue; User LED5 */ +#define CYBSP_LED_RGB_BLUE (P7_3) + +/** LED 8; User LED1 (orange) */ +#define CYBSP_USER_LED1 (CYBSP_LED8) +/** LED 9; User LED2 (red) */ +#define CYBSP_USER_LED2 (CYBSP_LED9) +/** LED 5: RGB LED - Red; User LED3 */ +#define CYBSP_USER_LED3 (CYBSP_LED_RGB_RED) +/** LED 5: RGB LED - Green; User LED4 */ +#define CYBSP_USER_LED4 (CYBSP_LED_RGB_GREEN) +/** LED 5: RGB LED - Blue; User LED5 */ +#define CYBSP_USER_LED5 (CYBSP_LED_RGB_BLUE) +/** LED 8; User LED1 (orange) */ +#define CYBSP_USER_LED (CYBSP_USER_LED1) + +/** \} group_bsp_pins_led */ -/** Pin: WCO input */ -#define CYBSP_WCO_IN P0_0 -/** Pin: WCO output */ -#define CYBSP_WCO_OUT P0_1 + +/** +* \addtogroup group_bsp_pins_btn Button Pins +* \{ +*/ + +/** Switch 2; User Button 1 */ +#define CYBSP_SW2 (P0_4) +/** Switch 4; User Button 2 */ +#define CYBSP_SW4 (P1_4) + +/** Switch 2; User Button 1 */ +#define CYBSP_USER_BTN1 (CYBSP_SW2) +/** Switch 4; User Button 2 */ +#define CYBSP_USER_BTN2 (CYBSP_SW4) +/** Switch 2; User Button 1 */ +#define CYBSP_USER_BTN (CYBSP_USER_BTN1) + +/** \} group_bsp_pins_btn */ + + +/** +* \addtogroup group_bsp_pins_comm Communication Pins +* \{ +*/ /** Pin: WIFI SDIO D0 */ -/* Corresponds to: ioss[0].port[2].pin[0], sdhc[0] */ -#define CYBSP_WIFI_SDIO_D0 P2_0 +#define CYBSP_WIFI_SDIO_D0 (P2_0) /** Pin: WIFI SDIO D1 */ -/* Corresponds to: ioss[0].port[2].pin[1], sdhc[0] */ -#define CYBSP_WIFI_SDIO_D1 P2_1 +#define CYBSP_WIFI_SDIO_D1 (P2_1) /** Pin: WIFI SDIO D2 */ -/* Corresponds to: ioss[0].port[2].pin[2], sdhc[0] */ -#define CYBSP_WIFI_SDIO_D2 P2_2 +#define CYBSP_WIFI_SDIO_D2 (P2_2) /** Pin: WIFI SDIO D3 */ -/* Corresponds to: ioss[0].port[2].pin[3], sdhc[0] */ -#define CYBSP_WIFI_SDIO_D3 P2_3 +#define CYBSP_WIFI_SDIO_D3 (P2_3) /** Pin: WIFI SDIO CMD */ -/* Corresponds to: ioss[0].port[2].pin[4], sdhc[0] */ -#define CYBSP_WIFI_SDIO_CMD P2_4 +#define CYBSP_WIFI_SDIO_CMD (P2_4) /** Pin: WIFI SDIO CLK */ -/* Corresponds to: ioss[0].port[2].pin[5], sdhc[0] */ -#define CYBSP_WIFI_SDIO_CLK P2_5 +#define CYBSP_WIFI_SDIO_CLK (P2_5) /** Pin: WIFI ON */ -/* Corresponds to: ioss[0].port[2].pin[6], sdhc[0] */ -#define CYBSP_WIFI_WL_REG_ON P2_6 +#define CYBSP_WIFI_WL_REG_ON (P2_6) /** Pin: WIFI Host Wakeup */ -#define CYBSP_WIFI_HOST_WAKE P4_1 +#define CYBSP_WIFI_HOST_WAKE (P4_1) /** Pin: BT UART RX */ -#define CYBSP_BT_UART_RX P3_0 +#define CYBSP_BT_UART_RX (P3_0) /** Pin: BT UART TX */ -#define CYBSP_BT_UART_TX P3_1 +#define CYBSP_BT_UART_TX (P3_1) /** Pin: BT UART RTS */ -#define CYBSP_BT_UART_RTS P3_2 +#define CYBSP_BT_UART_RTS (P3_2) /** Pin: BT UART CTS */ -#define CYBSP_BT_UART_CTS P3_3 +#define CYBSP_BT_UART_CTS (P3_3) + /** Pin: BT Power */ -#define CYBSP_BT_POWER P3_4 +#define CYBSP_BT_POWER (P3_4) /** Pin: BT Host Wakeup */ -#define CYBSP_BT_HOST_WAKE P4_0 +#define CYBSP_BT_HOST_WAKE (P4_0) /** Pin: BT Device Wakeup */ -#define CYBSP_BT_DEVICE_WAKE P3_5 +#define CYBSP_BT_DEVICE_WAKE (P3_5) /** Pin: UART RX */ -/* Corresponds to: ioss[0].port[5].pin[0], scb[5] */ -#define CYBSP_DEBUG_UART_RX P5_0 +#define CYBSP_DEBUG_UART_RX (P5_0) /** Pin: UART TX */ -/* Corresponds to: ioss[0].port[5].pin[1], scb[5] */ -#define CYBSP_DEBUG_UART_TX P5_1 +#define CYBSP_DEBUG_UART_TX (P5_1) /** Pin: UART RX */ -/* Corresponds to: ioss[0].port[5].pin[2], scb[5] */ -#define CYBSP_DEBUG_UART_RTS P5_2 +#define CYBSP_DEBUG_UART_RTS (P5_2) /** Pin: UART TX */ -/* Corresponds to: ioss[0].port[5].pin[3], scb[5] */ -#define CYBSP_DEBUG_UART_CTS P5_3 +#define CYBSP_DEBUG_UART_CTS (P5_3) /** Pin: I2C SCL */ -#define CYBSP_I2C_SCL P6_0 +#define CYBSP_I2C_SCL (P6_0) /** Pin: I2C SDA */ -#define CYBSP_I2C_SDA P6_1 +#define CYBSP_I2C_SDA (P6_1) /** Pin: SWO */ -#define CYBSP_SWO P6_4 +#define CYBSP_SWO (P6_4) /** Pin: SWDIO */ -#define CYBSP_SWDIO P6_6 +#define CYBSP_SWDIO (P6_6) /** Pin: SWDCK */ -#define CYBSP_SWDCK P6_7 - -/** Pin: CapSesnse RX */ -#define CYBSP_CSD_RX P1_0 -/** Pin: CapSesnse CINA */ -#define CYBSP_CINA P7_1 -/** Pin: CapSesnse CINB */ -#define CYBSP_CINB P7_2 -/** Pin: CapSesnse CMOD */ -#define CYBSP_CMOD P7_7 -/** Pin: CapSesnse Button 0 */ -#define CYBSP_CSD_BTN0 P8_1 -/** Pin: CapSesnse Button 1 */ -#define CYBSP_CSD_BTN1 P8_2 -/** Pin: CapSesnse Slider 0 */ -#define CYBSP_CSD_SLD0 P8_3 -/** Pin: CapSesnse Slider 1 */ -#define CYBSP_CSD_SLD1 P8_4 -/** Pin: CapSesnse Slider 2 */ -#define CYBSP_CSD_SLD2 P8_5 -/** Pin: CapSesnse Slider 3 */ -#define CYBSP_CSD_SLD3 P8_6 -/** Pin: CapSesnse Slider 4 */ -#define CYBSP_CSD_SLD4 P8_7 +#define CYBSP_SWDCK (P6_7) /** Pin: QUAD SPI SS */ -#define CYBSP_QSPI_SS P11_2 +#define CYBSP_QSPI_SS (P11_2) /** Pin: QUAD SPI D3 */ -#define CYBSP_QSPI_D3 P11_3 +#define CYBSP_QSPI_D3 (P11_3) /** Pin: QUAD SPI D2 */ -#define CYBSP_QSPI_D2 P11_4 +#define CYBSP_QSPI_D2 (P11_4) /** Pin: QUAD SPI D1 */ -#define CYBSP_QSPI_D1 P11_5 +#define CYBSP_QSPI_D1 (P11_5) /** Pin: QUAD SPI D0 */ -#define CYBSP_QSPI_D0 P11_6 +#define CYBSP_QSPI_D0 (P11_6) /** Pin: QUAD SPI SCK */ -#define CYBSP_QSPI_SCK P11_7 +#define CYBSP_QSPI_SCK (P11_7) /** Host-wake GPIO drive mode */ -#define CYBSP_WIFI_HOST_WAKE_GPIO_DM CYHAL_GPIO_DRIVE_ANALOG +#define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG) /** Host-wake IRQ event */ -#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT CYHAL_GPIO_IRQ_RISE - -/** BSP user LED reference designator to pin mapping */ -#define LED9_R P11_1 -/** BSP user LED reference designator to pin mapping */ -#define LED8_O P1_5 -/** BSP user LED reference designator to pin mapping */ -#define LED5_RGB_R P1_1 -/** BSP user LED reference designator to pin mapping */ -#define LED5_RGB_G P0_5 -/** BSP user LED reference designator to pin mapping */ -#define LED5_RGB_B P7_3 +#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_RISE) -/** BSP LED defines by LED color */ -#define CYBSP_LED_RED LED5_RGB_R -/** BSP LED defines by LED color */ -#define CYBSP_LED_GREEN LED5_RGB_G -/** BSP LED defines by LED color */ -#define CYBSP_LED_BLUE LED5_RGB_B -/** BSP LED defines by LED color */ -#define CYBSP_LED_ORANGE LED8 +/** \} group_bsp_pins_comm */ -/** BSP user button reference designator to pin mapping */ -#define SW2 P0_4 -/** BSP user button reference designator to pin mapping */ -#define SW4 P1_4 - - -/** \} group_bsp_cy8ckit_pins */ - /** -* \addtogroup group_bsp_enums Enumerated Types +* \addtogroup group_bsp_pins_arduino Arduino Header Pins * \{ */ -/** Enum defining the different states for the LED. */ -typedef enum -{ - CYBSP_LED_STATE_ON = 0, - CYBSP_LED_STATE_OFF = 1, -} cybsp_led_state_t; - -/** Enum defining the different states for a button. */ -typedef enum -{ - CYBSP_BTN_PRESSED = 0, - CYBSP_BTN_OFF = 1, -} cybsp_btn_state_t; - - -/** Enum defining the different user LEDs available on the board. */ -typedef enum -{ - CYBSP_LED_RGB_RED = LED5_RGB_R, - CYBSP_LED_RGB_GREEN = LED5_RGB_G, - CYBSP_LED_RGB_BLUE = LED5_RGB_B, - - /* Corresponds to: ioss[0].port[11].pin[1] */ - CYBSP_USER_LED1 = LED9_R, - /* Corresponds to: ioss[0].port[1].pin[5] */ - CYBSP_USER_LED2 = LED8_O, - /* Corresponds to: ioss[0].port[1].pin[1] */ - CYBSP_USER_LED3 = CYBSP_LED_RGB_RED, - /* Corresponds to: ioss[0].port[0].pin[5] */ - CYBSP_USER_LED4 = CYBSP_LED_RGB_GREEN, - /* Corresponds to: ioss[0].port[7].pin[3] */ - CYBSP_USER_LED5 = CYBSP_LED_RGB_BLUE, - CYBSP_USER_LED = CYBSP_USER_LED1, -} cybsp_led_t; - - -/** Enum defining the different user buttons available on the board. */ -typedef enum -{ - /* Corresponds to: ioss[0].port[0].pin[4] */ - CYBSP_USER_BTN1 = SW2, - /* Corresponds to: ioss[0].port[1].pin[4] */ - CYBSP_USER_BTN2 = SW4, - CYBSP_USER_BTN = CYBSP_USER_BTN1, -} cybsp_btn_t; - - -/** \} group_bsp_enums */ +/** Arduino A0 */ +#define CYBSP_A0 P10_0 +/** Arduino A1 */ +#define CYBSP_A1 P10_1 +/** Arduino A2 */ +#define CYBSP_A2 P10_2 +/** Arduino A3 */ +#define CYBSP_A3 P10_3 +/** Arduino A4 */ +#define CYBSP_A4 P10_4 +/** Arduino A5 */ +#define CYBSP_A5 P10_5 +/** Arduino D0 */ +#define CYBSP_D0 (P5_0) +/** Arduino D1 */ +#define CYBSP_D1 (P5_1) +/** Arduino D2 */ +#define CYBSP_D2 (P5_2) +/** Arduino D3 */ +#define CYBSP_D3 (P5_3) +/** Arduino D4 */ +#define CYBSP_D4 (P5_4) +/** Arduino D5 */ +#define CYBSP_D5 (P5_5) +/** Arduino D6 */ +#define CYBSP_D6 (P5_6) +/** Arduino D7 */ +#define CYBSP_D7 (P0_2) +/** Arduino D8 */ +#define CYBSP_D8 (P13_0) +/** Arduino D9 */ +#define CYBSP_D9 (P13_1) +/** Arduino D10 */ +#define CYBSP_D10 (P12_3) +/** Arduino D11 */ +#define CYBSP_D11 (P12_0) +/** Arduino D12 */ +#define CYBSP_D12 (P12_1) +/** Arduino D13 */ +#define CYBSP_D13 (P12_2) +/** Arduino D14 */ +#define CYBSP_D14 (P6_1) +/** Arduino D15 */ +#define CYBSP_D15 (P6_0) + +/** \} group_bsp_pins_arduino */ + +/** \} group_bsp_pins */ #if defined(__cplusplus) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp.c index e8d1a7d4bc4..f460f83ac42 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp.c @@ -1,8 +1,9 @@ /***************************************************************************//** -* \file CY8CKIT-062-BLE/cybsp.c +* \file cybsp.c * * Description: -* Provides basic hardware initialization for the CY8CKIT-062-BLE pioneer kit. +* Provides initialization code for starting up the hardware contained on the +* Cypress board. * ******************************************************************************** * \copyright @@ -31,6 +32,15 @@ extern "C" { #endif +/* The sysclk deep sleep callback is recommended to be the last callback that +* is executed before entry into deep sleep mode and the first one upon +* exit the deep sleep mode. +* Doing so minimizes the time spent on low power mode entry and exit. +*/ +#ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER + #define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u) +#endif + #if defined(CYBSP_WIFI_CAPABLE) static cyhal_sdio_t sdio_obj; @@ -40,6 +50,29 @@ cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void) } #endif +/** + * Registers a power management callback that prepares the clock system + * for entering deep sleep mode and restore the clocks upon wakeup from deep sleep. + * NOTE: This is called automatically as part of \ref cybsp_init + */ +static cy_rslt_t cybsp_register_sysclk_pm_callback(void) +{ + cy_rslt_t result = CY_RSLT_SUCCESS; + static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = {NULL, NULL}; + static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback = { + .callback = &Cy_SysClk_DeepSleepCallback, + .type = CY_SYSPM_DEEPSLEEP, + .callbackParams = &cybsp_sysclk_pm_callback_param, + .order = CYBSP_SYSCLK_PM_CALLBACK_ORDER + }; + + if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback)) + { + result = CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK; + } + return result; +} + cy_rslt_t cybsp_init(void) { /* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */ @@ -59,29 +92,6 @@ cy_rslt_t cybsp_init(void) */ if (CY_RSLT_SUCCESS == result) { - /* Initialize User LEDs */ - /* Reserves: CYBSP_USER_LED1 */ - result |= cybsp_led_init(CYBSP_USER_LED1); - /* Reserves: CYBSP_USER_LED2 */ - result |= cybsp_led_init(CYBSP_USER_LED2); - /* Reserves: CYBSP_USER_LED3 */ - result |= cybsp_led_init(CYBSP_USER_LED3); - /* Reserves: CYBSP_USER_LED4 */ - result |= cybsp_led_init(CYBSP_USER_LED4); - /* Reserves: CYBSP_USER_LED5 */ - result |= cybsp_led_init(CYBSP_USER_LED5); - /* Initialize User Buttons */ - /* Reserves: CYBSP_USER_BTN1 */ - result |= cybsp_btn_init(CYBSP_USER_BTN1); - CY_ASSERT(CY_RSLT_SUCCESS == result); - - /* Initialize retargetting stdio to 'DEBUG_UART' peripheral */ - if (CY_RSLT_SUCCESS == result) - { - /* Reserves: CYBSP_DEBUG_UART_RX, CYBSP_DEBUG_UART_TX, corresponding SCB instance and one of available - * clock dividers */ - result = cybsp_retarget_init(); - } /* Reserves: CYBSP_WIFI_SDIO, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3 * CYBSP_WIFI_SDIO_CMD and CYBSP_WIFI_SDIO_CLK. */ @@ -97,8 +107,9 @@ cy_rslt_t cybsp_init(void) #endif /* defined(CYBSP_WIFI_CAPABLE) */ /* CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was reserved by - * user previously. Please review the Device Configurator (design.modus) and the BSP reservation list - * (cyreservedresources.list) to make sure no resources are reserved by both. */ + * user previously. Please review the Device Configurator (design.modus) and the BSP reservation list + * (cyreservedresources.list) to make sure no resources are reserved by both. + */ return result; } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp.h index e7529ed433a..bd930510eda 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp.h @@ -1,9 +1,8 @@ /***************************************************************************//** -* \file CY8CKIT-062-BLE/cybsp.h +* \file cybsp.h * -* Description: -* Provides APIs for interacting with the hardware contained on the Cypress -* CY8CKIT-062-BLE pioneer kit. +* \brief +* Basic API for setting up boards containing a Cypress MCU. * ******************************************************************************** * \copyright @@ -25,22 +24,39 @@ #pragma once +#include "cy_result.h" #include "cybsp_types.h" -#include "cybsp_core.h" -#ifndef __MBED__ -#include "cybsp_retarget.h" -#include "cybsp_serial_flash.h" -#include "cybsp_rgb_led.h" -#endif /* __MBED__ */ +#if defined(CYBSP_WIFI_CAPABLE) +#include "cyhal_sdio.h" +#endif #if defined(__cplusplus) extern "C" { #endif +/** +* \addtogroup group_bsp_macros Macros +* \{ +*/ + +/** Failed to configure sysclk power management callback */ +#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0)) + +/** \} group_bsp_macros */ + /** * \addtogroup group_bsp_functions Functions * \{ */ + +/** + * \brief Initialize all hardware on the board + * \returns CY_RSLT_SUCCESS if the board is sucessfully initialized, if there is + * a problem initializing any hardware it returns an error code specific + * to the hardware module that had a problem. + */ +cy_rslt_t cybsp_init(void); + #if defined(CYBSP_WIFI_CAPABLE) /** * \brief Get the initialized sdio object used for communicating with the WiFi Chip. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp_types.h index bbf71f770f9..cc98e1bd59b 100755 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp_types.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp_types.h @@ -31,173 +31,169 @@ extern "C" { #endif + +/** +* \addtogroup group_bsp_pin_state Pin States +* \{ +*/ + +/** Pin state for the LED on. */ +#define CYBSP_LED_STATE_ON (0U) +/** Pin state for the LED off. */ +#define CYBSP_LED_STATE_OFF (1U) + +/** Pin state for when a button is pressed. */ +#define CYBSP_BTN_PRESSED (0U) +/** Pin state for when a button is released. */ +#define CYBSP_BTN_OFF (1U) + +/** \} group_bsp_pin_state */ + + /** * \addtogroup group_bsp_pins Pin Mappings * \{ */ -// Arduino connector namings +/** +* \addtogroup group_bsp_pins_led LED Pins +* \{ +*/ + +/** LED 8; User LED1 */ +#define CYBSP_LED8 (P1_5) +/** LED 9; User LED2 */ +#define CYBSP_LED9 (P13_7) +/** LED 5: RGB LED - Red; User LED3 */ +#define CYBSP_LED_RGB_RED (P0_3) +/** LED 5: RGB LED - Green; User LED4 */ +#define CYBSP_LED_RGB_GREEN (P1_1) +/** LED 5: RGB LED - Blue; User LED5 */ +#define CYBSP_LED_RGB_BLUE (P11_1) + +/** LED 8; User LED1 */ +#define CYBSP_USER_LED1 (CYBSP_LED8) +/** LED 9; User LED2 */ +#define CYBSP_USER_LED2 (CYBSP_LED9) +/** LED 5: RGB LED - Red; User LED3 */ +#define CYBSP_USER_LED3 (CYBSP_LED_RGB_RED) +/** LED 5: RGB LED - Green; User LED4 */ +#define CYBSP_USER_LED4 (CYBSP_LED_RGB_GREEN) +/** LED 5: RGB LED - Blue; User LED5 */ +#define CYBSP_USER_LED5 (CYBSP_LED_RGB_BLUE) +/** LED 8; User LED1 */ +#define CYBSP_USER_LED (CYBSP_USER_LED1) + +/** \} group_bsp_pins_led */ + +/** +* \addtogroup group_bsp_pins_btn Button Pins +* \{ +*/ + +/** Switch 2; User Button 1 */ +#define CYBSP_SW2 (P0_4) + +/** Switch 2; User Button 1 */ +#define CYBSP_USER_BTN1 (CYBSP_SW2) +/** Switch 2; User Button 1 */ +#define CYBSP_USER_BTN (CYBSP_USER_BTN1) + +/** \} group_bsp_pins_btn */ + + +/** +* \addtogroup group_bsp_pins_comm Communication Pins +* \{ +*/ + +/** Pin: UART RX */ +#define CYBSP_DEBUG_UART_RX (P5_0) +/** Pin: UART TX */ +#define CYBSP_DEBUG_UART_TX (P5_1) + +/** Pin: I2C SCL */ +#define CYBSP_I2C_SCL (P6_0) +/** Pin: I2C SDA */ +#define CYBSP_I2C_SDA (P6_1) + +/** Pin: SWO */ +#define CYBSP_SWO (P6_4) +/** Pin: SWDIO */ +#define CYBSP_SWDIO (P6_6) +/** Pin: SWDCK */ +#define CYBSP_SWDCK (P6_7) + +/** Pin: QUAD SPI SS */ +#define CYBSP_QSPI_SS (P11_2) +/** Pin: QUAD SPI D3 */ +#define CYBSP_QSPI_D3 (P11_3) +/** Pin: QUAD SPI D2 */ +#define CYBSP_QSPI_D2 (P11_4) +/** Pin: QUAD SPI D1 */ +#define CYBSP_QSPI_D1 (P11_5) +/** Pin: QUAD SPI D0 */ +#define CYBSP_QSPI_D0 (P11_6) +/** Pin: QUAD SPI SCK */ +#define CYBSP_QSPI_SCK (P11_7) + +/** \} group_bsp_pins_comm */ + + +/** +* \addtogroup group_bsp_pins_arduino Arduino Header Pins +* \{ +*/ + /** Arduino A0 */ -#define CYBSP_A0 P10_0 +#define CYBSP_A0 P10_0 /** Arduino A1 */ -#define CYBSP_A1 P10_1 +#define CYBSP_A1 P10_1 /** Arduino A2 */ -#define CYBSP_A2 P10_2 +#define CYBSP_A2 P10_2 /** Arduino A3 */ -#define CYBSP_A3 P10_3 +#define CYBSP_A3 P10_3 /** Arduino A4 */ -#define CYBSP_A4 P10_4 +#define CYBSP_A4 P10_4 /** Arduino A5 */ -#define CYBSP_A5 P10_5 +#define CYBSP_A5 P10_5 /** Arduino D0 */ -#define CYBSP_D0 P5_0 +#define CYBSP_D0 (P5_0) /** Arduino D1 */ -#define CYBSP_D1 P5_1 +#define CYBSP_D1 (P5_1) /** Arduino D2 */ -#define CYBSP_D2 P5_2 +#define CYBSP_D2 (P5_2) /** Arduino D3 */ -#define CYBSP_D3 P5_3 +#define CYBSP_D3 (P5_3) /** Arduino D4 */ -#define CYBSP_D4 P5_4 +#define CYBSP_D4 (P5_4) /** Arduino D5 */ -#define CYBSP_D5 P5_5 +#define CYBSP_D5 (P5_5) /** Arduino D6 */ -#define CYBSP_D6 P5_6 +#define CYBSP_D6 (P5_6) /** Arduino D7 */ -#define CYBSP_D7 P0_2 +#define CYBSP_D7 (P0_2) /** Arduino D8 */ -#define CYBSP_D8 P13_0 +#define CYBSP_D8 (P13_0) /** Arduino D9 */ -#define CYBSP_D9 P13_1 +#define CYBSP_D9 (P13_1) /** Arduino D10 */ -#define CYBSP_D10 P12_3 +#define CYBSP_D10 (P12_3) /** Arduino D11 */ -#define CYBSP_D11 P12_0 +#define CYBSP_D11 (P12_0) /** Arduino D12 */ -#define CYBSP_D12 P12_1 +#define CYBSP_D12 (P12_1) /** Arduino D13 */ -#define CYBSP_D13 P12_2 +#define CYBSP_D13 (P12_2) /** Arduino D14 */ -#define CYBSP_D14 P6_1 +#define CYBSP_D14 (P6_1) /** Arduino D15 */ -#define CYBSP_D15 P6_0 +#define CYBSP_D15 (P6_0) -// Generic signal names -/** Pin: WCO input */ -#define CYBSP_WCO_IN P0_0 -/** Pin: WCO output */ -#define CYBSP_WCO_OUT P0_1 - -/** Pin: UART RX */ -/* Corresponds to: ioss[0].port[5].pin[0], scb[5] */ -#define CYBSP_DEBUG_UART_RX P5_0 -/** Pin: UART TX */ -/* Corresponds to: ioss[0].port[5].pin[1], scb[5] */ -#define CYBSP_DEBUG_UART_TX P5_1 - -/** Pin: I2C SCL */ -#define CYBSP_I2C_SCL P6_0 -/** Pin: I2C SDA */ -#define CYBSP_I2C_SDA P6_1 - -/** Pin: SWO */ -#define CYBSP_SWO P6_4 -/** Pin: SWDIO */ -#define CYBSP_SWDIO P6_6 -/** Pin: SWDCK */ -#define CYBSP_SWDCK P6_7 - -/** Pin: CapSesnse TX */ -#define CYBSP_CSD_TX P1_0 -/** Pin: CapSesnse CINA */ -#define CYBSP_CINA P7_1 -/** Pin: CapSesnse CINB */ -#define CYBSP_CINB P7_2 -/** Pin: CapSesnse CMOD */ -#define CYBSP_CMOD P7_7 -/** Pin: CapSesnse Button 0 */ -#define CYBSP_CSD_BTN0 P8_1 -/** Pin: CapSesnse Button 1 */ -#define CYBSP_CSD_BTN1 P8_2 -/** Pin: CapSesnse Slider 0 */ -#define CYBSP_CSD_SLD0 P8_3 -/** Pin: CapSesnse Slider 1 */ -#define CYBSP_CSD_SLD1 P8_4 -/** Pin: CapSesnse Slider 2 */ -#define CYBSP_CSD_SLD2 P8_5 -/** Pin: CapSesnse Slider 3 */ -#define CYBSP_CSD_SLD3 P8_6 -/** Pin: CapSesnse Slider 4 */ -#define CYBSP_CSD_SLD4 P8_7 - -/** Pin: QUAD SPI SS */ -#define CYBSP_QSPI_SS P11_2 -/** Pin: QUAD SPI D3 */ -#define CYBSP_QSPI_D3 P11_3 -/** Pin: QUAD SPI D2 */ -#define CYBSP_QSPI_D2 P11_4 -/** Pin: QUAD SPI D1 */ -#define CYBSP_QSPI_D1 P11_5 -/** Pin: QUAD SPI D0 */ -#define CYBSP_QSPI_D0 P11_6 -/** Pin: QUAD SPI SCK */ -#define CYBSP_QSPI_SCK P11_7 +/** \} group_bsp_pins_arduino */ /** \} group_bsp_pins */ -/** -* \addtogroup group_bsp_enums Enumerated Types -* \{ -*/ - -/** Enum defining the different states for the LED. */ -typedef enum -{ - CYBSP_LED_STATE_ON = 0, - CYBSP_LED_STATE_OFF = 1, -} cybsp_led_state_t; - -/** Enum defining the different states for a button. */ -typedef enum -{ - CYBSP_BTN_PRESSED = 0, - CYBSP_BTN_OFF = 1, -} cybsp_btn_state_t; - -/** Enum defining the different LED pins on the board. */ -typedef enum -{ - CYBSP_LED9 = P13_7, - CYBSP_LED8 = P1_5, - CYBSP_LED_RGB_RED = P0_3, - CYBSP_LED_RGB_GREEN = P1_1, - CYBSP_LED_RGB_BLUE = P11_1, - - /* Corresponds to: ioss[0].port[1].pin[5] */ - CYBSP_USER_LED1 = CYBSP_LED8, - /* Corresponds to: ioss[0].port[13].pin[7] */ - CYBSP_USER_LED2 = CYBSP_LED9, - /* Corresponds to: ioss[0].port[0].pin[3] */ - CYBSP_USER_LED3 = CYBSP_LED_RGB_RED, - /* Corresponds to: ioss[0].port[1].pin[1] */ - CYBSP_USER_LED4 = CYBSP_LED_RGB_GREEN, - /* Corresponds to: ioss[0].port[11].pin[1] */ - CYBSP_USER_LED5 = CYBSP_LED_RGB_BLUE, - CYBSP_USER_LED = CYBSP_USER_LED1, -} cybsp_led_t; - -/** Enum defining the different button pins on the board. */ -typedef enum -{ - CYBSP_SW2 = P0_4, - - /* Corresponds to: ioss[0].port[0].pin[4] */ - CYBSP_USER_BTN1 = CYBSP_SW2, - CYBSP_USER_BTN = CYBSP_USER_BTN1, -} cybsp_btn_t; - -/** \} group_bsp_enums */ - #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp.c index 880d747c2d4..f460f83ac42 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp.c @@ -1,9 +1,9 @@ /***************************************************************************//** -* \file CY8CKIT-062-WIFI-BT/cybsp.c +* \file cybsp.c * * Description: -* Provides APIs for interacting with the hardware contained on the Cypress -* CY8CKIT-062-WIFI-BT pioneer kit. +* Provides initialization code for starting up the hardware contained on the +* Cypress board. * ******************************************************************************** * \copyright @@ -32,6 +32,15 @@ extern "C" { #endif +/* The sysclk deep sleep callback is recommended to be the last callback that +* is executed before entry into deep sleep mode and the first one upon +* exit the deep sleep mode. +* Doing so minimizes the time spent on low power mode entry and exit. +*/ +#ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER + #define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u) +#endif + #if defined(CYBSP_WIFI_CAPABLE) static cyhal_sdio_t sdio_obj; @@ -41,6 +50,29 @@ cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void) } #endif +/** + * Registers a power management callback that prepares the clock system + * for entering deep sleep mode and restore the clocks upon wakeup from deep sleep. + * NOTE: This is called automatically as part of \ref cybsp_init + */ +static cy_rslt_t cybsp_register_sysclk_pm_callback(void) +{ + cy_rslt_t result = CY_RSLT_SUCCESS; + static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = {NULL, NULL}; + static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback = { + .callback = &Cy_SysClk_DeepSleepCallback, + .type = CY_SYSPM_DEEPSLEEP, + .callbackParams = &cybsp_sysclk_pm_callback_param, + .order = CYBSP_SYSCLK_PM_CALLBACK_ORDER + }; + + if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback)) + { + result = CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK; + } + return result; +} + cy_rslt_t cybsp_init(void) { /* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */ @@ -52,35 +84,6 @@ cy_rslt_t cybsp_init(void) result = cybsp_register_sysclk_pm_callback(); } -#ifndef __MBED__ - if (CY_RSLT_SUCCESS == result) - { - /* Initialize User LEDs */ - /* Reserves: CYBSP_USER_LED1 */ - result |= cybsp_led_init(CYBSP_USER_LED1); - /* Reserves: CYBSP_USER_LED2 */ - result |= cybsp_led_init(CYBSP_USER_LED2); - /* Reserves: CYBSP_USER_LED3 */ - result |= cybsp_led_init(CYBSP_USER_LED3); - /* Reserves: CYBSP_USER_LED4 */ - result |= cybsp_led_init(CYBSP_USER_LED4); - /* Reserves: CYBSP_USER_LED5 */ - result |= cybsp_led_init(CYBSP_USER_LED5); - /* Initialize User Buttons */ - /* Reserves: CYBSP_USER_BTN1 */ - result |= cybsp_btn_init(CYBSP_USER_BTN1); - CY_ASSERT(CY_RSLT_SUCCESS == result); - - /* Initialize retargetting stdio to 'DEBUG_UART' peripheral */ - if (CY_RSLT_SUCCESS == result) - { - /* Reserves: CYBSP_DEBUG_UART_RX, CYBSP_DEBUG_UART_TX, corresponding SCB instance - * and one of available clock dividers */ - result = cybsp_retarget_init(); - } - } -#endif /* __MBED__ */ - #if defined(CYBSP_WIFI_CAPABLE) /* Initialize SDIO interface. This must be done before other HAL API calls as some SDIO implementations require * specific peripheral instances. @@ -104,8 +107,9 @@ cy_rslt_t cybsp_init(void) #endif /* defined(CYBSP_WIFI_CAPABLE) */ /* CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was reserved by - * user previously. Please review the Device Configurator (design.modus) and the BSP reservation list - * (cyreservedresources.list) to make sure no resources are reserved by both. */ + * user previously. Please review the Device Configurator (design.modus) and the BSP reservation list + * (cyreservedresources.list) to make sure no resources are reserved by both. + */ return result; } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp.h index ff576cae162..bd930510eda 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp.h @@ -1,9 +1,8 @@ /***************************************************************************//** -* \file CY8CKIT-062-WIFI-BT/cybsp.h +* \file cybsp.h * -* Description: -* Provides APIs for interacting with the hardware contained on the Cypress -* CY8CKIT-062-WIFI-BT pioneer kit. +* \brief +* Basic API for setting up boards containing a Cypress MCU. * ******************************************************************************** * \copyright @@ -25,27 +24,38 @@ #pragma once +#include "cy_result.h" #include "cybsp_types.h" -#include "cybsp_core.h" #if defined(CYBSP_WIFI_CAPABLE) #include "cyhal_sdio.h" #endif -#ifndef __MBED__ -#include "cybsp_retarget.h" -#include "cybsp_serial_flash.h" -#include "cybsp_rgb_led.h" -#endif /* __MBED__ */ #if defined(__cplusplus) extern "C" { #endif -// HAL HW configuration data -extern cyhal_qspi_t cybsp_qspi; -extern cyhal_uart_t cybsp_bt_uart; -extern cyhal_uart_t cybsp_debug_uart; -extern cyhal_i2c_t cybsp_i2c; -extern cyhal_rtc_t cybsp_rtc; +/** +* \addtogroup group_bsp_macros Macros +* \{ +*/ + +/** Failed to configure sysclk power management callback */ +#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0)) + +/** \} group_bsp_macros */ + +/** +* \addtogroup group_bsp_functions Functions +* \{ +*/ + +/** + * \brief Initialize all hardware on the board + * \returns CY_RSLT_SUCCESS if the board is sucessfully initialized, if there is + * a problem initializing any hardware it returns an error code specific + * to the hardware module that had a problem. + */ +cy_rslt_t cybsp_init(void); #if defined(CYBSP_WIFI_CAPABLE) /** diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp_types.h index 38114272872..1f05075b6e4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp_types.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp_types.h @@ -25,223 +25,213 @@ #pragma once -#include "cyhal.h" +#include "cyhal_pin_package.h" #if defined(__cplusplus) extern "C" { #endif + +/** +* \addtogroup group_bsp_pin_state Pin States +* \{ +*/ + +/** Pin state for the LED on. */ +#define CYBSP_LED_STATE_ON (0U) +/** Pin state for the LED off. */ +#define CYBSP_LED_STATE_OFF (1U) + +/** Pin state for when a button is pressed. */ +#define CYBSP_BTN_PRESSED (0U) +/** Pin state for when a button is released. */ +#define CYBSP_BTN_OFF (1U) + +/** \} group_bsp_pin_state */ + + /** * \addtogroup group_bsp_pins Pin Mappings * \{ */ -// Arduino connector namings -/** Arduino A0 */ -#define CYBSP_A0 P10_0 -/** Arduino A1 */ -#define CYBSP_A1 P10_1 -/** Arduino A2 */ -#define CYBSP_A2 P10_2 -/** Arduino A3 */ -#define CYBSP_A3 P10_3 -/** Arduino A4 */ -#define CYBSP_A4 P10_4 -/** Arduino A5 */ -#define CYBSP_A5 P10_5 -/** Arduino D0 */ -#define CYBSP_D0 P5_0 -/** Arduino D1 */ -#define CYBSP_D1 P5_1 -/** Arduino D2 */ -#define CYBSP_D2 P5_2 -/** Arduino D3 */ -#define CYBSP_D3 P5_3 -/** Arduino D4 */ -#define CYBSP_D4 P5_4 -/** Arduino D5 */ -#define CYBSP_D5 P5_5 -/** Arduino D6 */ -#define CYBSP_D6 P5_6 -/** Arduino D7 */ -#define CYBSP_D7 P0_2 -/** Arduino D8 */ -#define CYBSP_D8 P13_0 -/** Arduino D9 */ -#define CYBSP_D9 P13_1 -/** Arduino D10 */ -#define CYBSP_D10 P12_3 -/** Arduino D11 */ -#define CYBSP_D11 P12_0 -/** Arduino D12 */ -#define CYBSP_D12 P12_1 -/** Arduino D13 */ -#define CYBSP_D13 P12_2 -/** Arduino D14 */ -#define CYBSP_D14 P6_1 -/** Arduino D15 */ -#define CYBSP_D15 P6_0 +/** +* \addtogroup group_bsp_pins_led LED Pins +* \{ +*/ + +/** LED 8; User LED1 */ +#define CYBSP_LED8 (P1_5) +/** LED 9; User LED2 */ +#define CYBSP_LED9 (P13_7) +/** LED 5: RGB LED - Red; User LED3 */ +#define CYBSP_LED_RGB_RED (P0_3) +/** LED 5: RGB LED - Green; User LED4 */ +#define CYBSP_LED_RGB_GREEN (P1_1) +/** LED 5: RGB LED - Blue; User LED5 */ +#define CYBSP_LED_RGB_BLUE (P11_1) + +/** LED 8; User LED1 */ +#define CYBSP_USER_LED1 (CYBSP_LED8) +/** LED 9; User LED2 */ +#define CYBSP_USER_LED2 (CYBSP_LED9) +/** LED 5: RGB LED - Red; User LED3 */ +#define CYBSP_USER_LED3 (CYBSP_LED_RGB_RED) +/** LED 5: RGB LED - Green; User LED4 */ +#define CYBSP_USER_LED4 (CYBSP_LED_RGB_GREEN) +/** LED 5: RGB LED - Blue; User LED5 */ +#define CYBSP_USER_LED5 (CYBSP_LED_RGB_BLUE) +/** LED 8; User LED1 */ +#define CYBSP_USER_LED (CYBSP_USER_LED1) + +/** \} group_bsp_pins_led */ + + +/** +* \addtogroup group_bsp_pins_btn Button Pins +* \{ +*/ + +/** Switch 2; User Button 1 */ +#define CYBSP_SW2 (P0_4) + +/** Switch 2; User Button 1 */ +#define CYBSP_USER_BTN1 (CYBSP_SW2) +/** Switch 2; User Button 1 */ +#define CYBSP_USER_BTN (CYBSP_USER_BTN1) -// Generic signal names -/** Pin: WCO input */ -#define CYBSP_WCO_IN P0_0 -/** Pin: WCO output */ -#define CYBSP_WCO_OUT P0_1 +/** \} group_bsp_pins_btn */ + + +/** +* \addtogroup group_bsp_pins_comm Communication Pins +* \{ +*/ /** Pin: WIFI SDIO D0 */ -/* Corresponds to: ioss[0].port[2].pin[0], udb[0] */ -#define CYBSP_WIFI_SDIO_D0 P2_0 +#define CYBSP_WIFI_SDIO_D0 (P2_0) /** Pin: WIFI SDIO D1 */ -/* Corresponds to: ioss[0].port[2].pin[1], udb[0] */ -#define CYBSP_WIFI_SDIO_D1 P2_1 +#define CYBSP_WIFI_SDIO_D1 (P2_1) /** Pin: WIFI SDIO D2 */ -/* Corresponds to: ioss[0].port[2].pin[2], udb[0] */ -#define CYBSP_WIFI_SDIO_D2 P2_2 +#define CYBSP_WIFI_SDIO_D2 (P2_2) /** Pin: WIFI SDIO D3 */ -/* Corresponds to: ioss[0].port[2].pin[3], udb[0] */ -#define CYBSP_WIFI_SDIO_D3 P2_3 +#define CYBSP_WIFI_SDIO_D3 (P2_3) /** Pin: WIFI SDIO CMD */ -/* Corresponds to: ioss[0].port[2].pin[4], udb[0] */ -#define CYBSP_WIFI_SDIO_CMD P2_4 +#define CYBSP_WIFI_SDIO_CMD (P2_4) /** Pin: WIFI SDIO CLK */ -/* Corresponds to: ioss[0].port[2].pin[5], udb[0] */ -#define CYBSP_WIFI_SDIO_CLK P2_5 +#define CYBSP_WIFI_SDIO_CLK (P2_5) /** Pin: WIFI ON */ -/* Corresponds to: ioss[0].port[2].pin[6], udb[0] */ -#define CYBSP_WIFI_WL_REG_ON P2_6 +#define CYBSP_WIFI_WL_REG_ON (P2_6) /** Pin: WIFI Host Wakeup */ -#define CYBSP_WIFI_HOST_WAKE P2_7 +#define CYBSP_WIFI_HOST_WAKE (P2_7) /** Pin: BT UART RX */ -#define CYBSP_BT_UART_RX P3_0 +#define CYBSP_BT_UART_RX (P3_0) /** Pin: BT UART TX */ -#define CYBSP_BT_UART_TX P3_1 +#define CYBSP_BT_UART_TX (P3_1) /** Pin: BT UART RTS */ -#define CYBSP_BT_UART_RTS P3_2 +#define CYBSP_BT_UART_RTS (P3_2) /** Pin: BT UART CTS */ -#define CYBSP_BT_UART_CTS P3_3 +#define CYBSP_BT_UART_CTS (P3_3) /** Pin: BT Power */ -#define CYBSP_BT_POWER P3_4 +#define CYBSP_BT_POWER (P3_4) /** Pin: BT Host Wakeup */ -#define CYBSP_BT_HOST_WAKE P3_5 +#define CYBSP_BT_HOST_WAKE (P3_5) /** Pin: BT Device Wakeup */ -#define CYBSP_BT_DEVICE_WAKE P4_0 +#define CYBSP_BT_DEVICE_WAKE (P4_0) /** Pin: UART RX */ -/* Corresponds to: ioss[0].port[5].pin[0], scb[5] */ -#define CYBSP_DEBUG_UART_RX P5_0 +#define CYBSP_DEBUG_UART_RX (P5_0) /** Pin: UART TX */ -/* Corresponds to: ioss[0].port[5].pin[1], scb[5] */ -#define CYBSP_DEBUG_UART_TX P5_1 +#define CYBSP_DEBUG_UART_TX (P5_1) /** Pin: I2C SCL */ -#define CYBSP_I2C_SCL P6_0 +#define CYBSP_I2C_SCL (P6_0) /** Pin: I2C SDA */ -#define CYBSP_I2C_SDA P6_1 +#define CYBSP_I2C_SDA (P6_1) /** Pin: SWO */ -#define CYBSP_SWO P6_4 +#define CYBSP_SWO (P6_4) /** Pin: SWDIO */ -#define CYBSP_SWDIO P6_6 +#define CYBSP_SWDIO (P6_6) /** Pin: SWDCK */ -#define CYBSP_SWDCK P6_7 - -/** Pin: CapSesnse TX */ -#define CYBSP_CSD_TX P1_0 -/** Pin: CapSesnse CINA */ -#define CYBSP_CINA P7_1 -/** Pin: CapSesnse CINB */ -#define CYBSP_CINB P7_2 -/** Pin: CapSesnse CMOD */ -#define CYBSP_CMOD P7_7 -/** Pin: CapSesnse Button 0 */ -#define CYBSP_CSD_BTN0 P8_1 -/** Pin: CapSesnse Button 1 */ -#define CYBSP_CSD_BTN1 P8_2 -/** Pin: CapSesnse Slider 0 */ -#define CYBSP_CSD_SLD0 P8_3 -/** Pin: CapSesnse Slider 1 */ -#define CYBSP_CSD_SLD1 P8_4 -/** Pin: CapSesnse Slider 2 */ -#define CYBSP_CSD_SLD2 P8_5 -/** Pin: CapSesnse Slider 3 */ -#define CYBSP_CSD_SLD3 P8_6 -/** Pin: CapSesnse Slider 4 */ -#define CYBSP_CSD_SLD4 P8_7 +#define CYBSP_SWDCK (P6_7) /** Pin: QUAD SPI SS */ -#define CYBSP_QSPI_SS P11_2 +#define CYBSP_QSPI_SS (P11_2) /** Pin: QUAD SPI D3 */ -#define CYBSP_QSPI_D3 P11_3 +#define CYBSP_QSPI_D3 (P11_3) /** Pin: QUAD SPI D2 */ -#define CYBSP_QSPI_D2 P11_4 +#define CYBSP_QSPI_D2 (P11_4) /** Pin: QUAD SPI D1 */ -#define CYBSP_QSPI_D1 P11_5 +#define CYBSP_QSPI_D1 (P11_5) /** Pin: QUAD SPI D0 */ -#define CYBSP_QSPI_D0 P11_6 +#define CYBSP_QSPI_D0 (P11_6) /** Pin: QUAD SPI SCK */ -#define CYBSP_QSPI_SCK P11_7 +#define CYBSP_QSPI_SCK (P11_7) /** Host-wake GPIO drive mode */ -#define CYBSP_WIFI_HOST_WAKE_GPIO_DM CYHAL_GPIO_DRIVE_ANALOG +#define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG) /** Host-wake IRQ event */ -#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT CYHAL_GPIO_IRQ_RISE +#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_RISE) + +/** \} group_bsp_pins_comm */ -/** \} group_bsp_pins */ /** -* \addtogroup group_bsp_enums Enumerated Types +* \addtogroup group_bsp_pins_arduino Arduino Header Pins * \{ */ -/** Enum defining the different states for the LED. */ -typedef enum -{ - CYBSP_LED_STATE_ON = 0, - CYBSP_LED_STATE_OFF = 1, -} cybsp_led_state_t; - -/** Enum defining the different states for a button. */ -typedef enum -{ - CYBSP_BTN_PRESSED = 0, - CYBSP_BTN_OFF = 1, -} cybsp_btn_state_t; - -/** Enum defining the different LED pins on the board. */ -typedef enum -{ - CYBSP_LED9 = P13_7, - CYBSP_LED8 = P1_5, - CYBSP_LED_RGB_RED = P0_3, - CYBSP_LED_RGB_GREEN = P1_1, - CYBSP_LED_RGB_BLUE = P11_1, - - /* Corresponds to: ioss[0].port[1].pin[5] */ - CYBSP_USER_LED1 = CYBSP_LED8, - /* Corresponds to: ioss[0].port[13].pin[7] */ - CYBSP_USER_LED2 = CYBSP_LED9, - /* Corresponds to: ioss[0].port[0].pin[3] */ - CYBSP_USER_LED3 = CYBSP_LED_RGB_RED, - /* Corresponds to: ioss[0].port[1].pin[1] */ - CYBSP_USER_LED4 = CYBSP_LED_RGB_GREEN, - /* Corresponds to: ioss[0].port[11].pin[1] */ - CYBSP_USER_LED5 = CYBSP_LED_RGB_BLUE, - CYBSP_USER_LED = CYBSP_USER_LED1, -} cybsp_led_t; - -/** Enum defining the different button pins on the board. */ -typedef enum -{ - CYBSP_SW2 = P0_4, - - /* Corresponds to: ioss[0].port[0].pin[4] */ - CYBSP_USER_BTN1 = CYBSP_SW2, - CYBSP_USER_BTN = CYBSP_USER_BTN1, -} cybsp_btn_t; - -/** \} group_bsp_enums */ +/** Arduino A0 */ +#define CYBSP_A0 P10_0 +/** Arduino A1 */ +#define CYBSP_A1 P10_1 +/** Arduino A2 */ +#define CYBSP_A2 P10_2 +/** Arduino A3 */ +#define CYBSP_A3 P10_3 +/** Arduino A4 */ +#define CYBSP_A4 P10_4 +/** Arduino A5 */ +#define CYBSP_A5 P10_5 +/** Arduino D0 */ +#define CYBSP_D0 (P5_0) +/** Arduino D1 */ +#define CYBSP_D1 (P5_1) +/** Arduino D2 */ +#define CYBSP_D2 (P5_2) +/** Arduino D3 */ +#define CYBSP_D3 (P5_3) +/** Arduino D4 */ +#define CYBSP_D4 (P5_4) +/** Arduino D5 */ +#define CYBSP_D5 (P5_5) +/** Arduino D6 */ +#define CYBSP_D6 (P5_6) +/** Arduino D7 */ +#define CYBSP_D7 (P0_2) +/** Arduino D8 */ +#define CYBSP_D8 (P13_0) +/** Arduino D9 */ +#define CYBSP_D9 (P13_1) +/** Arduino D10 */ +#define CYBSP_D10 (P12_3) +/** Arduino D11 */ +#define CYBSP_D11 (P12_0) +/** Arduino D12 */ +#define CYBSP_D12 (P12_1) +/** Arduino D13 */ +#define CYBSP_D13 (P12_2) +/** Arduino D14 */ +#define CYBSP_D14 (P6_1) +/** Arduino D15 */ +#define CYBSP_D15 (P6_0) + +/** \} group_bsp_pins_arduino */ + +/** \} group_bsp_pins */ #if defined(__cplusplus) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp.c index 3ea4df46701..f460f83ac42 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp.c @@ -1,9 +1,9 @@ /***************************************************************************//** -* \file TARGET_CY8CPROTO_062_4343W/cybsp.c +* \file cybsp.c * * Description: -* Provides APIs for interacting with the hardware contained on the Cypress -* CY8CPROTO-062-4343W prototyping kit. +* Provides initialization code for starting up the hardware contained on the +* Cypress board. * ******************************************************************************** * \copyright @@ -32,6 +32,15 @@ extern "C" { #endif +/* The sysclk deep sleep callback is recommended to be the last callback that +* is executed before entry into deep sleep mode and the first one upon +* exit the deep sleep mode. +* Doing so minimizes the time spent on low power mode entry and exit. +*/ +#ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER + #define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u) +#endif + #if defined(CYBSP_WIFI_CAPABLE) static cyhal_sdio_t sdio_obj; @@ -41,6 +50,29 @@ cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void) } #endif +/** + * Registers a power management callback that prepares the clock system + * for entering deep sleep mode and restore the clocks upon wakeup from deep sleep. + * NOTE: This is called automatically as part of \ref cybsp_init + */ +static cy_rslt_t cybsp_register_sysclk_pm_callback(void) +{ + cy_rslt_t result = CY_RSLT_SUCCESS; + static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = {NULL, NULL}; + static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback = { + .callback = &Cy_SysClk_DeepSleepCallback, + .type = CY_SYSPM_DEEPSLEEP, + .callbackParams = &cybsp_sysclk_pm_callback_param, + .order = CYBSP_SYSCLK_PM_CALLBACK_ORDER + }; + + if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback)) + { + result = CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK; + } + return result; +} + cy_rslt_t cybsp_init(void) { /* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */ @@ -52,27 +84,6 @@ cy_rslt_t cybsp_init(void) result = cybsp_register_sysclk_pm_callback(); } -#ifndef __MBED__ - if (CY_RSLT_SUCCESS == result) - { - /* Initialize User LEDs */ - /* Reserves: CYBSP_USER_LED1 */ - result |= cybsp_led_init(CYBSP_USER_LED1); - /* Initialize User Buttons */ - /* Reserves: CYBSP_USER_BTN1 */ - result |= cybsp_btn_init(CYBSP_USER_BTN1); - CY_ASSERT(CY_RSLT_SUCCESS == result); - - /* Initialize retargetting stdio to 'DEBUG_UART' peripheral */ - if (CY_RSLT_SUCCESS == result) - { - /* Reserves: CYBSP_DEBUG_UART_RX, CYBSP_DEBUG_UART_TX, corresponding SCB instance - * and one of available clock dividers */ - result = cybsp_retarget_init(); - } - } -#endif /* __MBED__ */ - #if defined(CYBSP_WIFI_CAPABLE) /* Initialize SDIO interface. This must be done before other HAL API calls as some SDIO implementations require * specific peripheral instances. @@ -96,8 +107,9 @@ cy_rslt_t cybsp_init(void) #endif /* defined(CYBSP_WIFI_CAPABLE) */ /* CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was reserved by - * user previously. Please review the Device Configurator (design.modus) and the BSP reservation list - * (cyreservedresources.list) to make sure no resources are reserved by both. */ + * user previously. Please review the Device Configurator (design.modus) and the BSP reservation list + * (cyreservedresources.list) to make sure no resources are reserved by both. + */ return result; } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp.h index 356cf3f12c3..bd930510eda 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp.h @@ -1,9 +1,8 @@ /***************************************************************************//** -* \file CY8CPROTO-062-4343W/cybsp.h +* \file cybsp.h * -* Description: -* Provides APIs for interacting with the hardware contained on the Cypress -* CY8CPROTO-062-4343W prototyping kit. +* \brief +* Basic API for setting up boards containing a Cypress MCU. * ******************************************************************************** * \copyright @@ -25,25 +24,39 @@ #pragma once +#include "cy_result.h" #include "cybsp_types.h" -#include "cybsp_core.h" #if defined(CYBSP_WIFI_CAPABLE) #include "cyhal_sdio.h" #endif -#ifndef __MBED__ -#include "cybsp_retarget.h" -#include "cybsp_serial_flash.h" -#endif /* __MBED__ */ #if defined(__cplusplus) extern "C" { #endif +/** +* \addtogroup group_bsp_macros Macros +* \{ +*/ + +/** Failed to configure sysclk power management callback */ +#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0)) + +/** \} group_bsp_macros */ + /** * \addtogroup group_bsp_functions Functions * \{ */ +/** + * \brief Initialize all hardware on the board + * \returns CY_RSLT_SUCCESS if the board is sucessfully initialized, if there is + * a problem initializing any hardware it returns an error code specific + * to the hardware module that had a problem. + */ +cy_rslt_t cybsp_init(void); + #if defined(CYBSP_WIFI_CAPABLE) /** * \brief Get the initialized sdio object used for communicating with the WiFi Chip. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp_types.h index dbe43d4c36e..7012ebd7f83 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp_types.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp_types.h @@ -25,124 +25,144 @@ #pragma once -#include "cyhal.h" +#include "cyhal_pin_package.h" #if defined(__cplusplus) extern "C" { #endif + +/** +* \addtogroup group_bsp_pin_state Pin States +* \{ +*/ + +/** Pin state for the LED on. */ +#define CYBSP_LED_STATE_ON (0U) +/** Pin state for the LED off. */ +#define CYBSP_LED_STATE_OFF (1U) + +/** Pin state for when a button is pressed. */ +#define CYBSP_BTN_PRESSED (0U) +/** Pin state for when a button is released. */ +#define CYBSP_BTN_OFF (1U) + +/** \} group_bsp_pin_state */ + + /** * \addtogroup group_bsp_pins Pin Mappings * \{ */ +/** +* \addtogroup group_bsp_pins_led LED Pins +* \{ +*/ + +/** LED 4; User LED1 (red) */ +#define CYBSP_LED4 (P13_7) + +/** LED 4; User LED1 (red) */ +#define CYBSP_USER_LED1 (CYBSP_LED4) +/** LED 4; User LED1 (red) */ +#define CYBSP_USER_LED (CYBSP_USER_LED1) + +/** \} group_bsp_pins_led */ + + +/** +* \addtogroup group_bsp_pins_btn Button Pins +* \{ +*/ + +/** Switch 2; User Button 1 */ +#define CYBSP_SW2 (P0_4) + +/** Switch 2; User Button 1 */ +#define CYBSP_USER_BTN1 (CYBSP_SW2) +/** Switch 2; User Button 1 */ +#define CYBSP_USER_BTN (CYBSP_USER_BTN1) + +/** \} group_bsp_pins_btn */ + + +/** +* \addtogroup group_bsp_pins_comm Communication Pins +* \{ +*/ + /** Pin: WIFI SDIO D0 */ -/* Corresponds to: ioss[0].port[2].pin[0], sdhc[0] */ -#define CYBSP_WIFI_SDIO_D0 P2_0 +#define CYBSP_WIFI_SDIO_D0 (P2_0) /** Pin: WIFI SDIO D1 */ -/* Corresponds to: ioss[0].port[2].pin[1], sdhc[0] */ -#define CYBSP_WIFI_SDIO_D1 P2_1 +#define CYBSP_WIFI_SDIO_D1 (P2_1) /** Pin: WIFI SDIO D2 */ -/* Corresponds to: ioss[0].port[2].pin[2], sdhc[0] */ -#define CYBSP_WIFI_SDIO_D2 P2_2 +#define CYBSP_WIFI_SDIO_D2 (P2_2) /** Pin: WIFI SDIO D3 */ -/* Corresponds to: ioss[0].port[2].pin[3], sdhc[0] */ -#define CYBSP_WIFI_SDIO_D3 P2_3 +#define CYBSP_WIFI_SDIO_D3 (P2_3) /** Pin: WIFI SDIO CMD */ -/* Corresponds to: ioss[0].port[2].pin[4], sdhc[0] */ -#define CYBSP_WIFI_SDIO_CMD P2_4 +#define CYBSP_WIFI_SDIO_CMD (P2_4) /** Pin: WIFI SDIO CLK */ -/* Corresponds to: ioss[0].port[2].pin[5], sdhc[0] */ -#define CYBSP_WIFI_SDIO_CLK P2_5 +#define CYBSP_WIFI_SDIO_CLK (P2_5) /** Pin: WIFI ON */ -/* Corresponds to: ioss[0].port[2].pin[6], sdhc[0] */ -#define CYBSP_WIFI_WL_REG_ON P2_6 +#define CYBSP_WIFI_WL_REG_ON (P2_6) /** Pin: WIFI Host Wakeup */ -#define CYBSP_WIFI_HOST_WAKE P0_4 +#define CYBSP_WIFI_HOST_WAKE (P0_4) /** Pin: BT UART RX */ -#define CYBSP_BT_UART_RX P3_0 +#define CYBSP_BT_UART_RX (P3_0) /** Pin: BT UART TX */ -#define CYBSP_BT_UART_TX P3_1 +#define CYBSP_BT_UART_TX (P3_1) /** Pin: BT UART RTS */ -#define CYBSP_BT_UART_RTS P3_2 +#define CYBSP_BT_UART_RTS (P3_2) /** Pin: BT UART CTS */ -#define CYBSP_BT_UART_CTS P3_3 +#define CYBSP_BT_UART_CTS (P3_3) /** Pin: BT Power */ -#define CYBSP_BT_POWER P3_4 +#define CYBSP_BT_POWER (P3_4) /** Pin: BT Host Wakeup */ -#define CYBSP_BT_HOST_WAKE P4_0 +#define CYBSP_BT_HOST_WAKE (P4_0) /** Pin: BT Device Wakeup */ -#define CYBSP_BT_DEVICE_WAKE P3_5 +#define CYBSP_BT_DEVICE_WAKE (P3_5) /** Pin: UART RX */ -/* Corresponds to: ioss[0].port[5].pin[0], scb[5] */ -#define CYBSP_DEBUG_UART_RX P5_0 +#define CYBSP_DEBUG_UART_RX (P5_0) /** Pin: UART TX */ -/* Corresponds to: ioss[0].port[5].pin[1], scb[5] */ -#define CYBSP_DEBUG_UART_TX P5_1 +#define CYBSP_DEBUG_UART_TX (P5_1) + +/** Pin: I2C SCL */ +#define CYBSP_I2C_SCL (P6_0) +/** Pin: I2C SDA */ +#define CYBSP_I2C_SDA (P6_1) + +/** Pin: SWO */ +#define CYBSP_SWO (P6_4) +/** Pin: SWDIO */ +#define CYBSP_SWDIO (P6_6) +/** Pin: SWDCK */ +#define CYBSP_SWDCK (P6_7) /** Pin: QUAD SPI SS */ -#define CYBSP_QSPI_SS P11_2 +#define CYBSP_QSPI_SS (P11_2) /** Pin: QUAD SPI D3 */ -#define CYBSP_QSPI_D3 P11_3 +#define CYBSP_QSPI_D3 (P11_3) /** Pin: QUAD SPI D2 */ -#define CYBSP_QSPI_D2 P11_4 +#define CYBSP_QSPI_D2 (P11_4) /** Pin: QUAD SPI D1 */ -#define CYBSP_QSPI_D1 P11_5 +#define CYBSP_QSPI_D1 (P11_5) /** Pin: QUAD SPI D0 */ -#define CYBSP_QSPI_D0 P11_6 +#define CYBSP_QSPI_D0 (P11_6) /** Pin: QUAD SPI SCK */ -#define CYBSP_QSPI_SCK P11_7 +#define CYBSP_QSPI_SCK (P11_7) /** Host-wake GPIO drive mode */ -#define CYBSP_WIFI_HOST_WAKE_GPIO_DM CYHAL_GPIO_DRIVE_ANALOG +#define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG) /** Host-wake IRQ event */ -#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT CYHAL_GPIO_IRQ_RISE +#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_RISE) -/** \} group_bsp_pins */ +/** \} group_bsp_pins_comm */ -/** -* \addtogroup group_bsp_enums Enumerated Types -* \{ -*/ - -/** Enum defining the different states for the LED. */ -typedef enum -{ - CYBSP_LED_STATE_ON = 0, - CYBSP_LED_STATE_OFF = 1, -} cybsp_led_state_t; - -/** Enum defining the different states for a button. */ -typedef enum -{ - CYBSP_BTN_PRESSED = 0, - CYBSP_BTN_OFF = 1, -} cybsp_btn_state_t; - -/** Enum defining the different LED pins on the board. */ -typedef enum -{ - CYBSP_LED_RED = P13_7, - - /* Corresponds to: ioss[0].port[13].pin[7] */ - CYBSP_USER_LED1 = CYBSP_LED_RED, - CYBSP_USER_LED = CYBSP_USER_LED1, -} cybsp_led_t; - -/** Enum defining the different button pins on the board. */ -typedef enum -{ - CYBSP_SW2 = P0_4, - - /* Corresponds to: ioss[0].port[0].pin[4] */ - CYBSP_USER_BTN1 = CYBSP_SW2, - CYBSP_USER_BTN = CYBSP_USER_BTN1, -} cybsp_btn_t; - -/** \} group_bsp_enums */ +/** \} group_bsp_pins */ #if defined(__cplusplus) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.c index e98ad6a1a1d..f460f83ac42 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.c @@ -1,9 +1,9 @@ /***************************************************************************//** -* \file CY8CPROTO-064-SB/cybsp.c +* \file cybsp.c * * Description: -* Provides APIs for interacting with the hardware contained on the Cypress -* CY8CPROTO-064-SB prototyping kit. +* Provides initialization code for starting up the hardware contained on the +* Cypress board. * ******************************************************************************** * \copyright @@ -32,6 +32,15 @@ extern "C" { #endif +/* The sysclk deep sleep callback is recommended to be the last callback that +* is executed before entry into deep sleep mode and the first one upon +* exit the deep sleep mode. +* Doing so minimizes the time spent on low power mode entry and exit. +*/ +#ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER + #define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u) +#endif + #if defined(CYBSP_WIFI_CAPABLE) static cyhal_sdio_t sdio_obj; @@ -41,27 +50,38 @@ cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void) } #endif +/** + * Registers a power management callback that prepares the clock system + * for entering deep sleep mode and restore the clocks upon wakeup from deep sleep. + * NOTE: This is called automatically as part of \ref cybsp_init + */ +static cy_rslt_t cybsp_register_sysclk_pm_callback(void) +{ + cy_rslt_t result = CY_RSLT_SUCCESS; + static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = {NULL, NULL}; + static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback = { + .callback = &Cy_SysClk_DeepSleepCallback, + .type = CY_SYSPM_DEEPSLEEP, + .callbackParams = &cybsp_sysclk_pm_callback_param, + .order = CYBSP_SYSCLK_PM_CALLBACK_ORDER + }; + + if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback)) + { + result = CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK; + } + return result; +} + cy_rslt_t cybsp_init(void) { /* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */ cy_rslt_t result = cyhal_hwmgr_init(); init_cycfg_system(); - result = cybsp_register_sysclk_pm_callback(); -#ifndef __MBED__ if (CY_RSLT_SUCCESS == result) { - /* Initialize User LEDs */ - result |= cybsp_led_init(CYBSP_USER_LED1); - result |= cybsp_led_init(CYBSP_USER_LED2); - /* Initialize User Buttons */ - result |= cybsp_btn_init(CYBSP_USER_BTN1); - - /* Initialize retargetting stdio to 'DEBUG_UART' peripheral */ - if (CY_RSLT_SUCCESS == result) - { - result = cybsp_retarget_init(); - } + result = cybsp_register_sysclk_pm_callback(); } #if defined(CYBSP_WIFI_CAPABLE) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.h index 1aa9e3d7eb3..bd930510eda 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.h @@ -1,9 +1,8 @@ /***************************************************************************//** -* \file CY8CPROTO-064-SB/cybsp.h +* \file cybsp.h * -* Description: -* Provides APIs for interacting with the hardware contained on the Cypress -* CY8CPROTO-064-SB prototyping kit. +* \brief +* Basic API for setting up boards containing a Cypress MCU. * ******************************************************************************** * \copyright @@ -25,11 +24,8 @@ #pragma once +#include "cy_result.h" #include "cybsp_types.h" -#include "cybsp_core.h" -#ifndef __MBED__ -#include "cybsp_retarget.h" -#endif /* __MBED__ */ #if defined(CYBSP_WIFI_CAPABLE) #include "cyhal_sdio.h" #endif @@ -37,11 +33,30 @@ #if defined(__cplusplus) extern "C" { #endif + +/** +* \addtogroup group_bsp_macros Macros +* \{ +*/ + +/** Failed to configure sysclk power management callback */ +#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0)) + +/** \} group_bsp_macros */ + /** * \addtogroup group_bsp_functions Functions * \{ */ +/** + * \brief Initialize all hardware on the board + * \returns CY_RSLT_SUCCESS if the board is sucessfully initialized, if there is + * a problem initializing any hardware it returns an error code specific + * to the hardware module that had a problem. + */ +cy_rslt_t cybsp_init(void); + #if defined(CYBSP_WIFI_CAPABLE) /** * \brief Get the initialized sdio object used for communicating with the WiFi Chip. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp_types.h index 7247a347f35..80d56e4a650 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp_types.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp_types.h @@ -25,122 +25,115 @@ #pragma once -#include "cyhal.h" +#include "cyhal_pin_package.h" #if defined(__cplusplus) extern "C" { #endif + +/** +* \addtogroup group_bsp_pin_state Pin States +* \{ +*/ + +/** Pin state for the LED on. */ +#define CYBSP_LED_STATE_ON (0U) +/** Pin state for the LED off. */ +#define CYBSP_LED_STATE_OFF (1U) + +/** Pin state for when a button is pressed. */ +#define CYBSP_BTN_PRESSED (0U) +/** Pin state for when a button is released. */ +#define CYBSP_BTN_OFF (1U) + +/** \} group_bsp_pin_state */ + + /** * \addtogroup group_bsp_pins Pin Mappings * \{ */ -/* Board components mapping */ -/** Pin: LED3 in the CY8CPROTO-064-SB board */ -#define CYBSP_LED3 P13_7 -/** Pin: LED4 in the CY8CPROTO-064-SB board */ -#define CYBSP_LED4 P1_5 -/** Pin: SW2 in the CY8CPROTO-064-SB board */ -#define CYBSP_SW2 P0_4 - -/* Board peripheral count */ -/** Macro: Number of LEDs on CY8CPROTO-064-SB board */ -#define CYBSP_LED_COUNT 2 -/** Macro: Number of buttons on CY8CPROTO-064-SB board */ -#define CYBSP_BTN_COUNT 1 - -/* Generic signal names */ -/** Pin: WCO input */ -#define CYBSP_WCO_IN P0_0 -/** Pin: WCO output */ -#define CYBSP_WCO_OUT P0_1 - -/** Pin: ECO input */ -#define CYBSP_ECO_IN P12_6 -/** Pin: ECO output */ -#define CYBSP_ECO_OUT P12_7 +/** +* \addtogroup group_bsp_pins_led LED Pins +* \{ +*/ + +/** LED 3; User LED1 */ +#define CYBSP_LED3 (P13_7) +/** LED 4; User LED2 */ +#define CYBSP_LED4 (P1_5) + +/** LED 3; User LED1 */ +#define CYBSP_USER_LED1 (CYBSP_LED3) +/** LED 4; User LED2 */ +#define CYBSP_USER_LED2 (CYBSP_LED4) +/** LED 3; User LED1 */ +#define CYBSP_USER_LED (CYBSP_USER_LED1) + +/** \} group_bsp_pins_led */ + +/** +* \addtogroup group_bsp_pins_btn Button Pins +* \{ +*/ + +/** Switch 2; User Button 1 */ +#define CYBSP_SW2 (P0_4) + +/** Switch 2; User Button 1 */ +#define CYBSP_USER_BTN1 (CYBSP_SW2) +/** Switch 2; User Button 1 */ +#define CYBSP_USER_BTN (CYBSP_USER_BTN1) + +/** \} group_bsp_pins_btn */ + + +/** +* \addtogroup group_bsp_pins_comm Communication Pins +* \{ +*/ /** Pin: UART RX */ -#define CYBSP_UART_RX P5_0 +#define CYBSP_UART_RX (P5_0) /** Pin: UART TX */ -#define CYBSP_UART_TX P5_1 +#define CYBSP_UART_TX (P5_1) /** Pin: UART RX */ -#define CYBSP_DEBUG_UART_RX P5_0 +#define CYBSP_DEBUG_UART_RX (P5_0) /** Pin: UART TX */ -#define CYBSP_DEBUG_UART_TX P5_1 +#define CYBSP_DEBUG_UART_TX (P5_1) /** Pin: I2C SCL */ -#define CYBSP_I2C_SCL P6_0 +#define CYBSP_I2C_SCL (P6_0) /** Pin: I2C SDA */ -#define CYBSP_I2C_SDA P6_1 +#define CYBSP_I2C_SDA (P6_1) /** Pin: SWDIO */ -#define CYBSP_SWDIO P6_6 +#define CYBSP_SWDIO (P6_6) /** Pin: SWDCK */ -#define CYBSP_SWDCK P6_7 +#define CYBSP_SWDCK (P6_7) /** Pin: SWO */ -#define CYBSP_SWO P6_4 +#define CYBSP_SWO (P6_4) /** Pin: QUAD SPI SS */ -#define CYBSP_QSPI_SS P11_2 +#define CYBSP_QSPI_SS (P11_2) /** Pin: QUAD SPI D3 */ -#define CYBSP_QSPI_D3 P11_3 +#define CYBSP_QSPI_D3 (P11_3) /** Pin: QUAD SPI D2 */ -#define CYBSP_QSPI_D2 P11_4 +#define CYBSP_QSPI_D2 (P11_4) /** Pin: QUAD SPI D1 */ -#define CYBSP_QSPI_D1 P11_5 +#define CYBSP_QSPI_D1 (P11_5) /** Pin: QUAD SPI D0 */ -#define CYBSP_QSPI_D0 P11_6 +#define CYBSP_QSPI_D0 (P11_6) /** Pin: QUAD SPI SCK */ -#define CYBSP_QSPI_SCK P11_7 +#define CYBSP_QSPI_SCK (P11_7) -/** Pin: USB Device D+ */ -#define CYBSP_USB_DP P14_0 -/** Pin: USB Device D- */ -#define CYBSP_USB_DM P14_1 +/** \} group_bsp_pins_comm */ /** \} group_bsp_pins */ -/** -* \addtogroup group_bsp_enums Enumerated Types -* \{ -*/ - -/** Enum defining the different states for the LED. */ -typedef enum -{ - CYBSP_LED_STATE_ON = 0, - CYBSP_LED_STATE_OFF = 1, -} cybsp_led_state_t; - -/** Enum defining the different states for a button. */ -typedef enum -{ - CYBSP_BTN_PRESSED = 0, - CYBSP_BTN_OFF = 1, -} cybsp_btn_state_t; - -/** Enum defining the different LED pins on the board. */ -typedef enum -{ - CYBSP_LED_RED = CYBSP_LED3, - CYBSP_LED_GREEN = CYBSP_LED4, - - CYBSP_USER_LED = CYBSP_LED_RED, - CYBSP_USER_LED1 = CYBSP_LED_RED, - CYBSP_USER_LED2 = CYBSP_LED_GREEN, -} cybsp_led_t; - -/** Enum defining the different button pins on the board. */ -typedef enum -{ - CYBSP_USER_BTN = CYBSP_SW2, - CYBSP_USER_BTN1 = CYBSP_SW2, -} cybsp_btn_t; - -/** \} group_bsp_enums */ #if defined(__cplusplus) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/cybsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/cybsp.c index ef48c9e578a..f460f83ac42 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/cybsp.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/cybsp.c @@ -1,9 +1,9 @@ /***************************************************************************//** -* \file CYW943012P6EVB-01/cybsp.c +* \file cybsp.c * * Description: -* Provides APIs for interacting with the hardware contained on the Cypress -* CYW943012P6EVB-01 kit. +* Provides initialization code for starting up the hardware contained on the +* Cypress board. * ******************************************************************************** * \copyright @@ -32,6 +32,15 @@ extern "C" { #endif +/* The sysclk deep sleep callback is recommended to be the last callback that +* is executed before entry into deep sleep mode and the first one upon +* exit the deep sleep mode. +* Doing so minimizes the time spent on low power mode entry and exit. +*/ +#ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER + #define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u) +#endif + #if defined(CYBSP_WIFI_CAPABLE) static cyhal_sdio_t sdio_obj; @@ -41,6 +50,29 @@ cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void) } #endif +/** + * Registers a power management callback that prepares the clock system + * for entering deep sleep mode and restore the clocks upon wakeup from deep sleep. + * NOTE: This is called automatically as part of \ref cybsp_init + */ +static cy_rslt_t cybsp_register_sysclk_pm_callback(void) +{ + cy_rslt_t result = CY_RSLT_SUCCESS; + static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = {NULL, NULL}; + static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback = { + .callback = &Cy_SysClk_DeepSleepCallback, + .type = CY_SYSPM_DEEPSLEEP, + .callbackParams = &cybsp_sysclk_pm_callback_param, + .order = CYBSP_SYSCLK_PM_CALLBACK_ORDER + }; + + if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback)) + { + result = CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK; + } + return result; +} + cy_rslt_t cybsp_init(void) { /* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */ @@ -52,32 +84,6 @@ cy_rslt_t cybsp_init(void) result = cybsp_register_sysclk_pm_callback(); } -#ifndef __MBED__ - if (CY_RSLT_SUCCESS == result) - { - /* Initialize User LEDs */ - /* Reserves: CYBSP_USER_LED1 */ - result |= cybsp_led_init(CYBSP_USER_LED1); - /* Reserves: CYBSP_USER_LED2 */ - result |= cybsp_led_init(CYBSP_USER_LED2); - /* Reserves: CYBSP_USER_LED3 */ - result |= cybsp_led_init(CYBSP_USER_LED3); - /* Initialize User Buttons */ - /* Reserves: CYBSP_USER_BTN1 */ - result |= cybsp_btn_init(CYBSP_USER_BTN1); - - CY_ASSERT(CY_RSLT_SUCCESS == result); - - /* Initialize retargetting stdio to 'DEBUG_UART' peripheral */ - if (CY_RSLT_SUCCESS == result) - { - /* Reserves: CYBSP_DEBUG_UART_RX, CYBSP_DEBUG_UART_TX, corresponding SCB instance - * and one of available clock dividers */ - result = cybsp_retarget_init(); - } - } -#endif /* __MBED__ */ - #if defined(CYBSP_WIFI_CAPABLE) /* Initialize SDIO interface. This must be done before other HAL API calls as some SDIO implementations require * specific peripheral instances. @@ -101,8 +107,9 @@ cy_rslt_t cybsp_init(void) #endif /* defined(CYBSP_WIFI_CAPABLE) */ /* CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was reserved by - * user previously. Please review the Device Configurator (design.modus) and the BSP reservation list - * (cyreservedresources.list) to make sure no resources are reserved by both. */ + * user previously. Please review the Device Configurator (design.modus) and the BSP reservation list + * (cyreservedresources.list) to make sure no resources are reserved by both. + */ return result; } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/cybsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/cybsp.h index 47e6d96fa28..bd930510eda 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/cybsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/cybsp.h @@ -1,9 +1,8 @@ /***************************************************************************//** -* \file CYW943012P6EVB-01/cybsp.h +* \file cybsp.h * -* Description: -* Provides APIs for interacting with the hardware contained on the Cypress -* CYW943012P6EVB-01 kit. +* \brief +* Basic API for setting up boards containing a Cypress MCU. * ******************************************************************************** * \copyright @@ -25,25 +24,39 @@ #pragma once +#include "cy_result.h" #include "cybsp_types.h" -#include "cybsp_core.h" #if defined(CYBSP_WIFI_CAPABLE) #include "cyhal_sdio.h" #endif -#ifndef __MBED__ -#include "cybsp_retarget.h" -#include "cybsp_rgb_led.h" -#endif /* __MBED__ */ #if defined(__cplusplus) extern "C" { #endif +/** +* \addtogroup group_bsp_macros Macros +* \{ +*/ + +/** Failed to configure sysclk power management callback */ +#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0)) + +/** \} group_bsp_macros */ + /** * \addtogroup group_bsp_functions Functions * \{ */ +/** + * \brief Initialize all hardware on the board + * \returns CY_RSLT_SUCCESS if the board is sucessfully initialized, if there is + * a problem initializing any hardware it returns an error code specific + * to the hardware module that had a problem. + */ +cy_rslt_t cybsp_init(void); + #if defined(CYBSP_WIFI_CAPABLE) /** * \brief Get the initialized sdio object used for communicating with the WiFi Chip. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/cybsp_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/cybsp_types.h index 24c034007aa..b390ebf6e1b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/cybsp_types.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/cybsp_types.h @@ -25,287 +25,205 @@ #pragma once -#include "cyhal.h" +#include "cyhal_pin_package.h" #if defined(__cplusplus) extern "C" { #endif + +/** +* \addtogroup group_bsp_pin_state Pin States +* \{ +*/ + +/** Pin state for the LED on. */ +#define CYBSP_LED_STATE_ON (0U) +/** Pin state for the LED off. */ +#define CYBSP_LED_STATE_OFF (1U) + +/** Pin state for when a button is pressed. */ +#define CYBSP_BTN_PRESSED (0U) +/** Pin state for when a button is released. */ +#define CYBSP_BTN_OFF (1U) + +/** \} group_bsp_pin_state */ + + /** * \addtogroup group_bsp_pins Pin Mappings * \{ */ -// Arduino connector namings +/** +* \addtogroup group_bsp_pins_led LED Pins +* \{ +*/ + +/** LED 5: RGB LED - Red; User LED1 */ +#define CYBSP_LED_RGB_RED (P0_3) +/** LED 5: RGB LED - Green; User LED2 */ +#define CYBSP_LED_RGB_GREEN (P1_1) +/** LED 5: RGB LED - Blue; User LED3 */ +#define CYBSP_LED_RGB_BLUE (P10_6) + +/** LED 5: RGB LED - Red; User LED1 */ +#define CYBSP_USER_LED1 (CYBSP_LED_RGB_RED) +/** LED 5: RGB LED - Green; User LED2 */ +#define CYBSP_USER_LED2 (CYBSP_LED_RGB_GREEN) +/** LED 5: RGB LED - Blue; User LED3 */ +#define CYBSP_USER_LED3 (CYBSP_LED_RGB_BLUE) +/** LED 8; User LED1 */ +#define CYBSP_USER_LED (CYBSP_USER_LED1) + +/** \} group_bsp_pins_led */ + +/** +* \addtogroup group_bsp_pins_btn Button Pins +* \{ +*/ + +/** Switch 6; User Button 1 */ +#define CYBSP_SW6 (P0_4) + +/** Switch 6; User Button 1 */ +#define CYBSP_USER_BTN1 (CYBSP_SW6) +/** Switch 6; User Button 1 */ +#define CYBSP_USER_BTN (CYBSP_USER_BTN1) + +/** \} group_bsp_pins_btn */ + + +/** +* \addtogroup group_bsp_pins_comm Communication Pins +* \{ +*/ + +/** Pin: WIFI SDIO D0 */ +#define CYBSP_WIFI_SDIO_D0 (P2_0) +/** Pin: WIFI SDIO D1 */ +#define CYBSP_WIFI_SDIO_D1 (P2_1) +/** Pin: WIFI SDIO D2 */ +#define CYBSP_WIFI_SDIO_D2 (P2_2) +/** Pin: WIFI SDIO D3 */ +#define CYBSP_WIFI_SDIO_D3 (P2_3) +/** Pin: WIFI SDIO CMD */ +#define CYBSP_WIFI_SDIO_CMD (P2_4) +/** Pin: WIFI SDIO CLK */ +#define CYBSP_WIFI_SDIO_CLK (P2_5) +/** Pin: WIFI ON */ +#define CYBSP_WIFI_WL_REG_ON (P2_6) +/** Pin: WIFI Host Wakeup */ +#define CYBSP_WIFI_HOST_WAKE (P2_7) + +/** Pin: BT UART RX */ +#define CYBSP_BT_UART_RX (P3_0) +/** Pin: BT UART TX */ +#define CYBSP_BT_UART_TX (P3_1) +/** Pin: BT UART RTS */ +#define CYBSP_BT_UART_RTS (P3_2) +/** Pin: BT UART CTS */ +#define CYBSP_BT_UART_CTS (P3_3) + +/** Pin: BT Power */ +#define CYBSP_BT_POWER (P3_4) +/** Pin: BT Host Wakeup */ +#define CYBSP_BT_HOST_WAKE (P3_5) +/** Pin: BT Device Wakeup */ +#define CYBSP_BT_DEVICE_WAKE (P4_0) + +/** Pin: UART RX */ +#define CYBSP_DEBUG_UART_RX (P13_0) +/** Pin: UART TX */ +#define CYBSP_DEBUG_UART_TX (P13_1) + +/** Pin: I2C SCL */ +#define CYBSP_I2C_SCL (P6_0) +/** Pin: I2C SDA */ +#define CYBSP_I2C_SDA (P6_1) + +/** Pin: SWO */ +#define CYBSP_SWO (P6_4) +/** Pin: SWDIO */ +#define CYBSP_SWDIO (P6_6) +/** Pin: SWDCK */ +#define CYBSP_SWDCK (P6_7) + +/** Pin: QUAD SPI SS */ +#define CYBSP_QSPI_SS (P11_2) +/** Pin: QUAD SPI D3 */ +#define CYBSP_QSPI_D3 (P11_3) +/** Pin: QUAD SPI D2 */ +#define CYBSP_QSPI_D2 (P11_4) +/** Pin: QUAD SPI D1 */ +#define CYBSP_QSPI_D1 (P11_5) +/** Pin: QUAD SPI D0 */ +#define CYBSP_QSPI_D0 (P11_6) +/** Pin: QUAD SPI SCK */ +#define CYBSP_QSPI_SCK (P11_7) + +/** Host-wake GPIO drive mode */ +#define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG) +/** Host-wake IRQ event */ +#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_RISE) + +/** \} group_bsp_pins_comm */ + + +/** +* \addtogroup group_bsp_pins_arduino Arduino Header Pins +* \{ +*/ + /** Arduino A0 */ -#define CYBSP_A0 P10_0 +#define CYBSP_A0 P10_0 /** Arduino A1 */ -#define CYBSP_A1 P10_1 +#define CYBSP_A1 P10_1 /** Arduino A2 */ -#define CYBSP_A2 P6_4 +#define CYBSP_A2 P6_4 /** Arduino A3 */ -#define CYBSP_A3 P6_5 +#define CYBSP_A3 P6_5 /** Arduino A4 */ -#define CYBSP_A4 P10_4 +#define CYBSP_A4 P10_4 /** Arduino A5 */ -#define CYBSP_A5 P10_5 +#define CYBSP_A5 P10_5 /** Arduino D0 */ -#define CYBSP_D0 P5_0 +#define CYBSP_D0 (P5_0) /** Arduino D1 */ -#define CYBSP_D1 P5_1 +#define CYBSP_D1 (P5_1) /** Arduino D2 */ -#define CYBSP_D2 P5_2 +#define CYBSP_D2 (P5_2) /** Arduino D3 */ -#define CYBSP_D3 P5_3 +#define CYBSP_D3 (P5_3) /** Arduino D4 */ -#define CYBSP_D4 P5_4 +#define CYBSP_D4 (P5_4) /** Arduino D5 */ -#define CYBSP_D5 P5_5 +#define CYBSP_D5 (P5_5) /** Arduino D6 */ -#define CYBSP_D6 P5_6 +#define CYBSP_D6 (P5_6) /** Arduino D7 */ -#define CYBSP_D7 P5_7 +#define CYBSP_D7 (P5_7) /** Arduino D8 */ -#define CYBSP_D8 NC +#define CYBSP_D8 (NC) /** Arduino D9 */ -#define CYBSP_D9 NC +#define CYBSP_D9 (NC) /** Arduino D10 */ -#define CYBSP_D10 P0_5 +#define CYBSP_D10 (P0_5) /** Arduino D11 */ -#define CYBSP_D11 P0_2 +#define CYBSP_D11 (P0_2) /** Arduino D12 */ -#define CYBSP_D12 P0_3 +#define CYBSP_D12 (P0_3) /** Arduino D13 */ -#define CYBSP_D13 P0_4 +#define CYBSP_D13 (P0_4) /** Arduino D14 */ -#define CYBSP_D14 P1_0 +#define CYBSP_D14 (P1_0) /** Arduino D15 */ -#define CYBSP_D15 P1_1 - -// Generic signal names -/** Pin: CYBSP_WCO_IN */ -#define CYBSP_WCO_IN P0_0 -/** Pin: CYBSP_WCO_OUT */ -#define CYBSP_WCO_OUT P0_1 - -/** Pin: CYBSP_CSD_TX */ -#define CYBSP_CSD_TX P1_0 -/** Pin: CYBSP_WL_SECI_IN */ -#define CYBSP_WL_SECI_IN P1_2 -/** Pin: CYBSP_WL_FRAM_SYNC */ -#define CYBSP_WL_FRAM_SYNC P1_3 -/** Pin: CYBSP_WL_PRIORITY */ -#define CYBSP_WL_PRIORITY P1_4 -/** Pin: CYBSP_WL_SECI_OUT */ -#define CYBSP_WL_SECI_OUT P1_5 - -/** Pin: CYBSP_WIFI_SDIO_D0 */ -/* Corresponds to: ioss[0].port[2].pin[0], udb[0] */ -#define CYBSP_WIFI_SDIO_D0 P2_0 -/** Pin: CYBSP_WIFI_SDIO_D1 */ -/* Corresponds to: ioss[0].port[2].pin[1], udb[0] */ -#define CYBSP_WIFI_SDIO_D1 P2_1 -/** Pin: CYBSP_WIFI_SDIO_D2 */ -/* Corresponds to: ioss[0].port[2].pin[2], udb[0] */ -#define CYBSP_WIFI_SDIO_D2 P2_2 -/** Pin: CYBSP_WIFI_SDIO_D3 */ -/* Corresponds to: ioss[0].port[2].pin[3], udb[0] */ -#define CYBSP_WIFI_SDIO_D3 P2_3 -/** Pin: CYBSP_WIFI_SDIO_CMD */ -/* Corresponds to: ioss[0].port[2].pin[4], udb[0] */ -#define CYBSP_WIFI_SDIO_CMD P2_4 -/** Pin: CYBSP_WIFI_SDIO_CLK */ -/* Corresponds to: ioss[0].port[2].pin[5], udb[0] */ -#define CYBSP_WIFI_SDIO_CLK P2_5 -/** Pin: CYBSP_WIFI_WL_REG_ON */ -/* Corresponds to: ioss[0].port[2].pin[6], udb[0] */ -#define CYBSP_WIFI_WL_REG_ON P2_6 -/** Pin: CYBSP_WIFI_HOST_WAKE */ -#define CYBSP_WIFI_HOST_WAKE P2_7 -/** Host-wake GPIO drive mode */ -#define CYBSP_WIFI_HOST_WAKE_GPIO_DM CYHAL_GPIO_DRIVE_ANALOG -/** Host-wake IRQ event */ -#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT CYHAL_GPIO_IRQ_RISE +#define CYBSP_D15 (P1_1) -/** Pin: CYBSP_BT_UART_RX */ -#define CYBSP_BT_UART_RX P3_0 -/** Pin: CYBSP_BT_UART_TX */ -#define CYBSP_BT_UART_TX P3_1 -/** Pin: CYBSP_BT_UART_RTS */ -#define CYBSP_BT_UART_RTS P3_2 -/** Pin: CYBSP_BT_UART_CTS */ -#define CYBSP_BT_UART_CTS P3_3 - -/** Pin: BT Power */ -#define CYBSP_BT_POWER P3_4 -/** Pin: CYBSP_BT_HOST_WAKE */ -#define CYBSP_BT_HOST_WAKE P3_5 -/** Pin: CYBSP_BT_DEVICE_WAKE */ -#define CYBSP_BT_DEVICE_WAKE P4_0 -/** Pin: CYBSP_BT_RST */ -#define CYBSP_BT_RST P4_1 - -/** Pin: UART RX */ -/* Corresponds to: ioss[0].port[13].pin[0], scb[6] */ -#define CYBSP_DEBUG_UART_RX P13_0 -/** Pin: UART TX */ -/* Corresponds to: ioss[0].port[13].pin[1], scb[6] */ -#define CYBSP_DEBUG_UART_TX P13_1 - -/** Pin: CYBSP_I2C_SCL */ -#define CYBSP_I2C_SCL P6_0 -/** Pin: CYBSP_I2C_SDA */ -#define CYBSP_I2C_SDA P6_1 -/** Pin: CYBSP_TDO_SWO */ -#define CYBSP_TDO_SWO P6_4 -/** Pin: CYBSP_TMS_SWDIO */ -#define CYBSP_TMS_SWDIO P6_6 -/** Pin: CYBSP_SWCLK */ -#define CYBSP_SWCLK P6_7 - -/** Pin: CYBSP_TRACECLK */ -#define CYBSP_TRACECLK P7_0 -/** Pin: CYBSP_CINTA */ -#define CYBSP_CINTA P7_1 -/** Pin: CYBSP_CINTB */ -#define CYBSP_CINTB P7_2 -/** Pin: CYBSP_CMOD */ -#define CYBSP_CMOD P7_7 - -/** Pin: CYBSP_CSD_BTN0 */ -#define CYBSP_CSD_BTN0 P8_1 -/** Pin: CYBSP_CSD_BTN1 */ -#define CYBSP_CSD_BTN1 P8_2 -/** Pin: CYBSP_CSD_SLD0 */ -#define CYBSP_CSD_SLD0 P8_3 -/** Pin: CYBSP_CSD_SLD1 */ -#define CYBSP_CSD_SLD1 P8_4 -/** Pin: CYBSP_CSD_SLD2 */ -#define CYBSP_CSD_SLD2 P8_5 -/** Pin: CYBSP_CSD_SLD3 */ -#define CYBSP_CSD_SLD3 P8_6 -/** Pin: CYBSP_CSD_SLD4 */ -#define CYBSP_CSD_SLD4 P8_7 - -/** Pin: CYBSP_TRACEDATA3 */ -#define CYBSP_TRACEDATA3 P9_0 -/** Pin: CYBSP_TRACEDATA2 */ -#define CYBSP_TRACEDATA2 P9_1 -/** Pin: CYBSP_TRACEDATA1 */ -#define CYBSP_TRACEDATA1 P9_2 -/** Pin: CYBSP_TRACEDATA0 */ -#define CYBSP_TRACEDATA0 P9_3 - -/** Pin: CYBSP_ROW6_SPI_MOSI */ -#define CYBSP_ROW6_SPI_MOSI P10_0 -/** Pin: CYBSP_COL8_SPI_MISO */ -#define CYBSP_COL8_SPI_MISO P10_1 -/** Pin: CYBSP_ROW7_SPI_CLK */ -#define CYBSP_ROW7_SPI_CLK P10_2 -/** Pin: CYBSP_COL7_SPI_CS */ -#define CYBSP_COL7_SPI_CS P10_3 -/** Pin: CYBSP_BAT_MON */ -#define CYBSP_BAT_MON P10_4 -/** Pin: CYBSP_WL_WAKE */ -#define CYBSP_WL_WAKE P10_7 - -/** Pin: CYBSP_UART_RX */ -#define CYBSP_UART_RX P11_0 -/** Pin: CYBSP_UART_TX */ -#define CYBSP_UART_TX P11_1 -/** Pin: CYBSP_QSPI_SS */ -#define CYBSP_QSPI_SS P11_2 -/** Pin: CYBSP_QSPI_D3 */ -#define CYBSP_QSPI_D3 P11_3 -/** Pin: CYBSP_QSPI_D2 */ -#define CYBSP_QSPI_D2 P11_4 -/** Pin: CYBSP_QSPI_D1 */ -#define CYBSP_QSPI_D1 P11_5 -/** Pin: CYBSP_QSPI_D0 */ -#define CYBSP_QSPI_D0 P11_6 -/** Pin: CYBSP_QSPI_SCK */ -#define CYBSP_QSPI_SCK P11_7 - -/** Pin: CYBSP_BT_GPIO4 */ -#define CYBSP_BT_GPIO4 P12_0 -/** Pin: CYBSP_BT_GPIO5 */ -#define CYBSP_BT_GPIO5 P12_1 -/** Pin: CYBSP_BT_GPIO2 */ -#define CYBSP_BT_GPIO2 P12_2 -/** Pin: CYBSP_BT_GPIO3 */ -#define CYBSP_BT_GPIO3 P12_3 -/** Pin: CYBSP_ECO_IN */ -#define CYBSP_ECO_IN P12_6 -/** Pin: CYBSP_ECO_OUT */ -#define CYBSP_ECO_OUT P12_7 - -/** Pin: CYBSP_P6_UART_RX */ -/* Corresponds to: ioss[0].port[13].pin[0], scb[6] */ -#define CYBSP_P6_UART_RX P13_0 -/** Pin: CYBSP_P6_UART_TX */ -/* Corresponds to: ioss[0].port[13].pin[1], scb[6] */ -#define CYBSP_P6_UART_TX P13_1 -/** Pin: CYBSP_USB_DEV_VBUS_DET */ -#define CYBSP_USB_DEV_VBUS_DET P13_4 -/** Pin: CYBSP_USB_HOST_EN */ -#define CYBSP_USB_HOST_EN P13_5 -/** Pin: CYBSP_USB_INT_L */ -#define CYBSP_USB_INT_L P13_7 - -/** Pin: CYBSP_USB_DP */ -#define CYBSP_USB_DP P14_0 -/** Pin: CYBSP_USB_DM */ -#define CYBSP_USB_DM P14_1 +/** \} group_bsp_pins_arduino */ /** \} group_bsp_pins */ -/** -* \addtogroup group_bsp_enums Enumerated Types -* \{ -*/ - -/** Enum defining the different states for the LED. */ -typedef enum -{ - CYBSP_LED_STATE_ON = 0, - CYBSP_LED_STATE_OFF = 1, -} cybsp_led_state_t; - -/** Enum defining the different states for a button. */ -typedef enum -{ - CYBSP_BTN_PRESSED = 0, - CYBSP_BTN_OFF = 1, -} cybsp_btn_state_t; - -/** Enum defining the different LED pins on the board. */ -typedef enum -{ - CYBSP_LED_RGB_RED = P0_3, - CYBSP_LED_RGB_GREEN = P1_1, - CYBSP_LED_RGB_BLUE = P10_6, - - /* Corresponds to: ioss[0].port[0].pin[3] */ - CYBSP_USER_LED1 = CYBSP_LED_RGB_RED, - /* Corresponds to: ioss[0].port[1].pin[1] */ - CYBSP_USER_LED2 = CYBSP_LED_RGB_GREEN, - /* Corresponds to: ioss[0].port[10].pin[6] */ - CYBSP_USER_LED3 = CYBSP_LED_RGB_BLUE, - CYBSP_USER_LED = CYBSP_USER_LED1, -} cybsp_led_t; - -/** Enum defining the different button pins on the board. */ -typedef enum -{ - CYBSP_SW6 = P0_4, - - /* Corresponds to: ioss[0].port[0].pin[4] */ - CYBSP_USER_BTN1 = CYBSP_SW6, - CYBSP_USER_BTN = CYBSP_USER_BTN1, -} cybsp_btn_t; - -/** \} group_bsp_enums */ - #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_core.c b/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_core.c deleted file mode 100644 index ce86500533f..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_core.c +++ /dev/null @@ -1,92 +0,0 @@ -/***************************************************************************//** -* \file cybsp_core.c -* -* \brief -* Provides utility functions that are used by board support packages. -* -******************************************************************************** -* \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include "cybsp_core.h" -#include "cyhal.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -cy_rslt_t cybsp_led_init(cybsp_led_t which) -{ - return cyhal_gpio_init((cyhal_gpio_t)which, CYHAL_GPIO_DIR_OUTPUT, CYHAL_GPIO_DRIVE_STRONG, CYBSP_LED_STATE_OFF); -} - -void cybsp_led_set_state(cybsp_led_t which, bool on) -{ - cyhal_gpio_write((cyhal_gpio_t)which, on); -} - -void cybsp_led_toggle(cybsp_led_t which) -{ - cyhal_gpio_toggle((cyhal_gpio_t)which); -} - -cy_rslt_t cybsp_btn_init(cybsp_btn_t which) -{ - return cyhal_gpio_init((cyhal_gpio_t)which, CYHAL_GPIO_DIR_INPUT, CYHAL_GPIO_DRIVE_PULLUP, CYBSP_BTN_OFF); -} - -bool cybsp_btn_get_state(cybsp_btn_t which) -{ - return cyhal_gpio_read((cyhal_gpio_t)which); -} - -void cybsp_btn_set_interrupt(cybsp_btn_t which, cyhal_gpio_event_t type, cyhal_gpio_event_callback_t callback, void *callback_arg) -{ - cyhal_gpio_register_callback((cyhal_gpio_t)which, callback, callback_arg); - cyhal_gpio_enable_event((cyhal_gpio_t)which, type, 7, 1); -} - -/* The sysclk deep sleep callback is recommended to be the last callback that -* is executed before entry into deep sleep mode and the first one upon -* exit the deep sleep mode. -* Doing so minimizes the time spent on low power mode entry and exit. -*/ -#ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER - #define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u) -#endif - -cy_rslt_t cybsp_register_sysclk_pm_callback(void) -{ - cy_rslt_t result = CY_RSLT_SUCCESS; - static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = {NULL, NULL}; - static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback = { - .callback = &Cy_SysClk_DeepSleepCallback, - .type = CY_SYSPM_DEEPSLEEP, - .callbackParams = &cybsp_sysclk_pm_callback_param, - .order = CYBSP_SYSCLK_PM_CALLBACK_ORDER - }; - - if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback)) - { - result = CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK; - } - return result; -} - -#if defined(__cplusplus) -} -#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_core.h b/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_core.h deleted file mode 100644 index 0f876e76602..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_core.h +++ /dev/null @@ -1,150 +0,0 @@ -/***************************************************************************//** -* \file cybsp_core.h -* -* \brief -* Basic abstraction layer for dealing with boards containing a Cypress MCU. This -* API provides convenience methods for initializing and manipulating different -* hardware found on the board. -* -******************************************************************************** -* \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -/** -* \addtogroup group_bsp_core Core -* \{ -* Basic abstraction layer for dealing with boards containing a Cypress MCU. This -* API provides convenience methods for initializing and manipulating different -* hardware found on the board. -* -* \defgroup group_bsp_core_macros Macros -* \defgroup group_bsp_core_functions Functions -*/ - -#pragma once - -#include -#include "cy_result.h" -#include "cyhal_gpio.h" -#include "cybsp_types.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/** -* \addtogroup group_bsp_core_macros -* \{ -*/ - -/** Failed to configure sysclk power management callback */ -#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0)) - -/** \} group_bsp_core_macros */ - -/** -* \addtogroup group_bsp_core_functions -* \{ -*/ - -/** - * \brief Initialize all hardware on the board - * \returns CY_RSLT_SUCCESS if the board is sucessfully initialized, if there is - * a problem initializing any hardware it returns an error code specific - * to the hardware module that had a problem. - */ -cy_rslt_t cybsp_init(void); - -/** - * \brief Init and allocate the specified LED, setting the GPIO drive mode as necessary - * \param which The specific LED number to enable, see BSP header file for available LEDs - * \returns CY_RSLT_SUCCESS if the LED was enabled successfully - */ -cy_rslt_t cybsp_led_init(cybsp_led_t which); - -/** - * \brief Toggle the specified LED - * \param which The specific LED number to enable, see BSP header file for available LEDs - */ -void cybsp_led_toggle(cybsp_led_t which); - -/** - * \brief Sets the state of the LED. - * \param which The specific LED number to set state, see BSP header file for available LEDs - * \param on Whether the LED should be turned on (true) or off (false) - */ -void cybsp_led_set_state(cybsp_led_t which, bool on); - -/** - * \brief Turns the LED on. - * \param which The specific LED number to set state, see BSP header file for available LEDs - * \returns CY_RSLT_SUCCESS if the LED was turned on - */ -static inline void cybsp_led_on(cybsp_led_t which) -{ - cybsp_led_set_state(which, CYBSP_LED_STATE_ON); -} - -/** - * \brief Turns the LED off. - * \param which The specific LED number to set state, see BSP header file for available LEDs - * \returns CY_RSLT_SUCCESS if the LED was turned off - */ -static inline void cybsp_led_off(cybsp_led_t which) -{ - cybsp_led_set_state(which, CYBSP_LED_STATE_OFF); -} - -/** - * \brief Init and allocate the specified button, setting the GPIO drive mode as necessary - * \param which The specific button number to enable, see BSP header file for available buttones - * \returns CY_RSLT_SUCCESS if the button was enabled successfully - */ -cy_rslt_t cybsp_btn_init(cybsp_btn_t which); - -/** - * \brief Sets the state of the button. - * \param which The specific button number to get state from, see BSP header file for available buttones - * \returns State of the button - */ -bool cybsp_btn_get_state(cybsp_btn_t which); - -/** - * \brief Sets the interrupt to trigger when the button state is changed. - * \param which The specific button number to get state from, see BSP header file for available buttones - * \param type The type sets level vs edge and active high vs active low - * \param callback The function pointer to call when the button state changes. NULL to unregister. - * \param callback_arg The optional argument to provide when the callback is executed. This can be NULL. - */ -void cybsp_btn_set_interrupt(cybsp_btn_t which, cyhal_gpio_event_t type, cyhal_gpio_event_callback_t callback, void *callback_arg); - -/** - * \brief Registers a power management callback that prepares the clock system - * for entering deep sleep mode and restore the clocks upon wakeup from deep sleep. - * NOTE: This is called automatically as part of \ref cybsp_init - * \returns CY_RSLT_SUCCESS if the callback is sucessfully registered, if there is - * a problem registering the callback it returns CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK. - */ -cy_rslt_t cybsp_register_sysclk_pm_callback(void); - -/** \} group_bsp_core_functions */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -/** \} group_bsp_core */ From 222443ea632fc8e887eea4f78731921a90077a22 Mon Sep 17 00:00:00 2001 From: Kyle Kearney Date: Thu, 19 Sep 2019 12:01:29 -0700 Subject: [PATCH 178/227] Refactor serial flash support --- ...al_flash_prog.c => cy_serial_flash_prog.c} | 32 ++- .../common/cy_serial_flash_qspi.c | 218 ++++++++++++++++++ ..._serial_flash.h => cy_serial_flash_qspi.h} | 92 +++++--- .../TARGET_PSOC6/common/cybsp_serial_flash.c | 180 --------------- .../TARGET_PSOC6/mbed_overrides.c | 14 +- 5 files changed, 306 insertions(+), 230 deletions(-) rename targets/TARGET_Cypress/TARGET_PSOC6/common/{cybsp_serial_flash_prog.c => cy_serial_flash_prog.c} (74%) create mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/common/cy_serial_flash_qspi.c rename targets/TARGET_Cypress/TARGET_PSOC6/common/{cybsp_serial_flash.h => cy_serial_flash_qspi.h} (53%) delete mode 100644 targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_serial_flash.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_serial_flash_prog.c b/targets/TARGET_Cypress/TARGET_PSOC6/common/cy_serial_flash_prog.c similarity index 74% rename from targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_serial_flash_prog.c rename to targets/TARGET_Cypress/TARGET_PSOC6/common/cy_serial_flash_prog.c index c0306dc6fbd..69f416349e0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_serial_flash_prog.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/common/cy_serial_flash_prog.c @@ -1,11 +1,12 @@ /***************************************************************************//** -* \file cybsp_serial_flash_prog.c +* \file cy_serial_flash_prog.c * * \brief * Provides variables necessary to inform programming tools how to program the * attached serial flash memory. The variables used here must be placed at * specific locations in order to be detected and used by programming tools -* to know that there is an attached memory and its characteristics. +* to know that there is an attached memory and its characteristics. Uses the +* configuration provided as part of BSP. * ******************************************************************************** * \copyright @@ -26,22 +27,22 @@ *******************************************************************************/ /** -* \addtogroup group_bsp_serial_flash Serial Flash +* \addtogroup group_serial_flash Serial Flash * \{ * Variables for informing programming tools that there is an attached memory device and what * its characteristics are so it can be programmed just like the on-chip memory. * -* \defgroup group_bsp_serial_flash_variables Variables +* \defgroup group_serial_flash_variables Variables */ #include -#include "cybsp_types.h" #if defined(__cplusplus) extern "C" { #endif -#if defined(CYBSP_QSPI_SCK) && (DEVICE_QSPI) +#if defined(CY_ENABLE_XIP_PROGRAM) + #include "cycfg_qspi_memslot.h" typedef struct @@ -51,7 +52,7 @@ typedef struct } stc_smif_ipblocks_arr_t; /** -* \addtogroup group_bsp_serial_flash_variables +* \addtogroup group_serial_flash_variables * \{ */ @@ -61,7 +62,7 @@ typedef struct * are multiple ways this can be accomplished including: * 1) Placing it in a dedicated memory block with a known address. (as done here) * 2) Placing it at an absolute location via a the linker script - * 3) Using cymcuelftool to recompute the checksum and patch the elf file after linking + * 3) Using 'cymcuelftool -S' to recompute the checksum and patch the elf file after linking */ CY_SECTION(".cy_sflash_user_data") __attribute__( (used) ) const stc_smif_ipblocks_arr_t smifIpBlocksArr = {&smifBlockConfig, 0x00000000}; @@ -81,14 +82,21 @@ const uint32_t cyToc[128] = 0, /* Offset=0x0008: Key Storage Address */ (int)&smifIpBlocksArr, /* Offset=0x000C: This points to a null terminated array of SMIF structures. */ 0x10000000u, /* Offset=0x0010: App image start address */ - [127] = 0x0B1F0000 /* Offset=0x01FC: CRC16-CCITT (the upper 2 bytes contain the CRC and the lower 2 bytes are 0) */ + /* Offset=0x0014-0x01F7: Reserved */ + [126] = 0x000002C2, /* Offset=0x01F8: Bits[ 1: 0] CLOCK_CONFIG (0=8MHz, 1=25MHz, 2=50MHz, 3=100MHz) + Bits[ 4: 2] LISTEN_WINDOW (0=20ms, 1=10ms, 2=1ms, 3=0ms, 4=100ms) + Bits[ 6: 5] SWJ_PINS_CTL (0/1/3=Disable SWJ, 2=Enable SWJ) + Bits[ 8: 7] APP_AUTHENTICATION (0/2/3=Enable, 1=Disable) + Bits[10: 9] FB_BOOTLOADER_CTL: UNUSED */ + [127] = 0x3BB30000 /* Offset=0x01FC: CRC16-CCITT (the upper 2 bytes contain the CRC and the lower 2 bytes are 0) */ }; -/** \} group_bsp_serial_flash_variables */ -#endif /* defined(CYBSP_QSPI_SCK) && (DEVICE_QSPI) */ +/** \} group_serial_flash_variables */ + +#endif /* defined(CY_ENABLE_XIP_PROGRAM) */ #if defined(__cplusplus) } #endif -/** \} group_bsp_serial_flash */ +/** \} group_serial_flash */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/common/cy_serial_flash_qspi.c b/targets/TARGET_Cypress/TARGET_PSOC6/common/cy_serial_flash_qspi.c new file mode 100644 index 00000000000..963982b6aa0 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/common/cy_serial_flash_qspi.c @@ -0,0 +1,218 @@ +/***************************************************************************//** +* \file cy_serial_flash_qspi.c +* +* \brief +* Provides APIs for interacting with an external flash connected to the SPI or +* QSPI interface, uses SFDP to auto-discover memory properties if SFDP is +* enabled in the configuration. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include +#include "cy_serial_flash_qspi.h" +#include "cyhal_qspi.h" +#include "cy_utils.h" + +#ifdef CY_IP_MXSMIF + +#if defined(__cplusplus) +extern "C" { +#endif + + +/** \cond internal */ + +/** Timeout to apply while polling the memory for its ready status after quad + * enable command has been sent out. Quad enable is a non-volatile write. +*/ +#define CY_SERIAL_FLASH_QUAD_ENABLE_TIMEOUT_US (5000lu) /* in microseconds */ + +/* Number of memories supported by the driver */ +#define SMIF_MEM_DEVICES (1u) + +/* SMIF slot from which the memory configuration is picked up - fixed to 0 as the driver + * supports only one device */ +#define MEM_SLOT (0u) + +/** \endcond */ + +static cyhal_qspi_t qspi_obj; + +static cy_stc_smif_mem_config_t * qspi_mem_config[SMIF_MEM_DEVICES]; + +static cy_stc_smif_block_config_t qspi_block_config = +{ + /* The number of SMIF memories defined. */ + .memCount = SMIF_MEM_DEVICES, + /* The pointer to the array of memory config structures of size memCount. */ + .memConfig = (cy_stc_smif_mem_config_t**)qspi_mem_config, + /* The version of the SMIF driver. */ + .majorVersion = CY_SMIF_DRV_VERSION_MAJOR, + /* The version of the SMIF driver. */ + .minorVersion = CY_SMIF_DRV_VERSION_MINOR +}; + +/* The driver supports only one memory. When multiple memory configurations + * are generated by the SMIF configurator tool, provide only the + * configuration for memory that need to be supported by the driver. + * Memory configuration can be changed by deinit followed by init with new + * configuration */ +cy_rslt_t cy_serial_flash_qspi_init( + const cy_stc_smif_mem_config_t* mem_config, + cyhal_gpio_t io0, + cyhal_gpio_t io1, + cyhal_gpio_t io2, + cyhal_gpio_t io3, + cyhal_gpio_t io4, + cyhal_gpio_t io5, + cyhal_gpio_t io6, + cyhal_gpio_t io7, + cyhal_gpio_t sclk, + cyhal_gpio_t ssel, + uint32_t hz) +{ + cy_en_smif_status_t smifStatus = CY_SMIF_SUCCESS; + + + cy_rslt_t result = cyhal_qspi_init(&qspi_obj, io0, io1, io2, io3, io4, io5, io6, io7, + sclk, ssel, hz, 0); + + qspi_mem_config[MEM_SLOT] = (cy_stc_smif_mem_config_t*) mem_config; + + if(CY_RSLT_SUCCESS == result) + { + /* Perform SFDP detection and XIP register configuration depending on the + * memory configuration. + */ + smifStatus = Cy_SMIF_MemInit(qspi_obj.base, &qspi_block_config, &qspi_obj.context); + if(CY_SMIF_SUCCESS == smifStatus) + { + /* Enable Quad mode (1-1-4 or 1-4-4 modes) to use all the four I/Os during + * communication. + */ + + if(qspi_block_config.memConfig[MEM_SLOT]->deviceCfg->readCmd->dataWidth == CY_SMIF_WIDTH_QUAD + || qspi_block_config.memConfig[MEM_SLOT]->deviceCfg->programCmd->dataWidth == CY_SMIF_WIDTH_QUAD) + { + bool isQuadEnabled = false; + smifStatus = Cy_SMIF_MemIsQuadEnabled(qspi_obj.base, qspi_block_config.memConfig[MEM_SLOT], &isQuadEnabled, &qspi_obj.context); + if(CY_SMIF_SUCCESS == smifStatus) + { + if(!isQuadEnabled) + { + smifStatus = Cy_SMIF_MemEnableQuadMode(qspi_obj.base, qspi_block_config.memConfig[MEM_SLOT], CY_SERIAL_FLASH_QUAD_ENABLE_TIMEOUT_US, &qspi_obj.context); + } + } + } + } + } + + if((CY_RSLT_SUCCESS == result) && (CY_SMIF_SUCCESS == smifStatus)) + { + return CY_RSLT_SUCCESS; + } + else + { + Cy_SMIF_MemDeInit(qspi_obj.base); + cy_serial_flash_qspi_deinit(); + return (cy_rslt_t)smifStatus; + } +} + +void cy_serial_flash_qspi_deinit(void) +{ + Cy_SMIF_MemDeInit(qspi_obj.base); + cyhal_qspi_free(&qspi_obj); +} + +size_t cy_serial_flash_qspi_get_size(void) +{ + return (size_t)qspi_block_config.memConfig[MEM_SLOT]->deviceCfg->memSize; +} + +/* address is ignored for the memory with uniform sector size. Currently, + * QSPI Configurator does not support memories with hybrid sectors. + */ +size_t cy_serial_flash_qspi_get_erase_size(uint32_t addr) +{ + CY_UNUSED_PARAMETER(addr); + return (size_t)qspi_block_config.memConfig[MEM_SLOT]->deviceCfg->eraseSize; +} + +cy_rslt_t cy_serial_flash_qspi_read(uint32_t addr, size_t length, uint8_t *buf) +{ + /* Cy_SMIF_MemRead() returns error if (addr + length) > total flash size. */ + return (cy_rslt_t)Cy_SMIF_MemRead(qspi_obj.base, qspi_block_config.memConfig[MEM_SLOT], addr, buf, length, &qspi_obj.context); +} + +cy_rslt_t cy_serial_flash_qspi_write(uint32_t addr, size_t length, const uint8_t *buf) +{ + /* Cy_SMIF_MemWrite() returns error if (addr + length) > total flash size. */ + return (cy_rslt_t)Cy_SMIF_MemWrite(qspi_obj.base, qspi_block_config.memConfig[MEM_SLOT], addr, (uint8_t *)buf, length, &qspi_obj.context); +} + +/* Does not support hybrid sectors, sector size must be uniform on the entire + * chip. Use cy_serial_flash_qspi_get_erase_size(addr) to implement hybrid sector + * support when QSPI Configurator and PDL supports memories with hybrid sectors. + */ +cy_rslt_t cy_serial_flash_qspi_erase(uint32_t addr, size_t length) +{ + cy_en_smif_status_t smifStatus; + + /* If the erase is for the entire chip, use chip erase command */ + if((addr == 0u) && (length == cy_serial_flash_qspi_get_size())) + { + smifStatus = Cy_SMIF_MemEraseChip(qspi_obj.base, qspi_block_config.memConfig[MEM_SLOT], &qspi_obj.context); + } + else + { + /* Cy_SMIF_MemEraseSector() returns error if (addr + length) > total flash size + * or if addr is not aligned to erase sector size or if (addr + length) + * is not aligned to erase sector size. + */ + smifStatus = Cy_SMIF_MemEraseSector(qspi_obj.base, qspi_block_config.memConfig[MEM_SLOT], addr, length, &qspi_obj.context); + } + + return (cy_rslt_t)smifStatus; +} + +// This function enables or disables XIP on the MCU, does not send any command +// to the serial flash. XIP register configuration is already done as part of +// cy_serial_flash_qspi_init() if MMIO mode is enabled in the QSPI +// Configurator. +cy_rslt_t cy_serial_flash_qspi_enable_xip(bool enable) +{ + if(enable) + { + Cy_SMIF_SetMode(qspi_obj.base, CY_SMIF_MEMORY); + } + else + { + Cy_SMIF_SetMode(qspi_obj.base, CY_SMIF_NORMAL); + } + + return CY_RSLT_SUCCESS; +} + +#if defined(__cplusplus) +} +#endif + +#endif /* CY_IP_MXSMIF */ + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_serial_flash.h b/targets/TARGET_Cypress/TARGET_PSOC6/common/cy_serial_flash_qspi.h similarity index 53% rename from targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_serial_flash.h rename to targets/TARGET_Cypress/TARGET_PSOC6/common/cy_serial_flash_qspi.h index cf550112748..d4c85ac28e9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_serial_flash.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/common/cy_serial_flash_qspi.h @@ -1,5 +1,5 @@ /***************************************************************************//** -* \file cybsp_serial_flash.h +* \file cy_serial_flash_qspi.h * * \brief * Provides APIs for interacting with an external flash connected to the SPI or @@ -25,55 +25,83 @@ *******************************************************************************/ /** -* \addtogroup group_bsp_serial_flash Serial Flash +* \addtogroup group_serial_flash Serial Flash * \{ -* Driver for interfacing with the serial flash (QSPI NOR flash) on Cypress boards. +* Driver for interfacing with the serial flash (QSPI NOR flash). * -* \defgroup group_bsp_serial_flash_macros Macros -* \defgroup group_bsp_serial_flash_functions Functions +* \defgroup group_serial_flash_macros Macros +* \defgroup group_serial_flash_functions Functions */ #pragma once #include #include "cy_result.h" +#include "cy_pdl.h" +#include "cyhal.h" + +#ifdef CY_IP_MXSMIF #if defined(__cplusplus) extern "C" { #endif /** -* \addtogroup group_bsp_serial_flash_macros +* \addtogroup group_serial_flash_macros * \{ */ /** The function or operation is not supported on the target or the memory */ -#define CYBSP_RSLT_SERIAL_FLASH_ERR_UNSUPPORTED (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 6)) +#define CY_RSLT_SERIAL_FLASH_ERR_UNSUPPORTED (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_BOARD_LIB_SERIAL_FLASH, 1)) -/** \} group_bsp_serial_flash_macros */ +/** \} group_serial_flash_macros */ /** -* \addtogroup group_bsp_serial_flash_functions +* \addtogroup group_serial_flash_functions * \{ */ /** - * \brief Initializes the serial flash on the board. + * \brief Initializes the serial flash memory. + * \param mem_config Memory configuration to be used for initializing + * \param io0 Data/IO pin 0 connected to the memory + * \param io1 Data/IO pin 1 connected to the memory + * \param io2 Data/IO pin 2 connected to the memory + * \param io3 Data/IO pin 3 connected to the memory + * \param io4 Data/IO pin 4 connected to the memory + * \param io5 Data/IO pin 5 connected to the memory + * \param io6 Data/IO pin 6 connected to the memory + * \param io7 Data/IO pin 7 connected to the memory + * \param sclk Clock pin connected to the memory + * \param ssel Slave select pin connected to the memory + * \param hz Clock frequency to be used with the memory * \returns CY_RSLT_SUCCESS if the initialization was successful, an error code * otherwise. */ -cy_rslt_t cybsp_serial_flash_init(void); +cy_rslt_t cy_serial_flash_qspi_init( + const cy_stc_smif_mem_config_t* mem_config, + cyhal_gpio_t io0, + cyhal_gpio_t io1, + cyhal_gpio_t io2, + cyhal_gpio_t io3, + cyhal_gpio_t io4, + cyhal_gpio_t io5, + cyhal_gpio_t io6, + cyhal_gpio_t io7, + cyhal_gpio_t sclk, + cyhal_gpio_t ssel, + uint32_t hz); /** - * \brief De-initializes the serial flash on the board. + * \brief De-initializes the serial flash memory. */ -void cybsp_serial_flash_deinit(void); +void cy_serial_flash_qspi_deinit(void); /** - * \brief Returns the size of the serial flash on the board in bytes. + * \brief Returns the size of the serial flash memory in bytes. * \returns Memory size in bytes. */ -size_t cybsp_serial_flash_get_size(void); +size_t cy_serial_flash_qspi_get_size(void); /** * \brief Returns the size of the erase sector to which the given address @@ -81,38 +109,38 @@ size_t cybsp_serial_flash_get_size(void); * \param addr Address that belongs to the sector for which size is returned. * \returns Erase sector size in bytes. */ -size_t cybsp_serial_flash_get_erase_size(uint32_t addr); +size_t cy_serial_flash_qspi_get_erase_size(uint32_t addr); /** - * \brief Reads data from the serial flash on the board. This is a blocking + * \brief Reads data from the serial flash memory. This is a blocking * function. Returns error if (addr + length) exceeds the flash size. * \param addr Starting address to read from * \param length Number of data bytes to read * \param buf Pointer to the buffer to store the data read from the memory * \returns CY_RSLT_SUCCESS if the read was successful, an error code otherwise. */ -cy_rslt_t cybsp_serial_flash_read(uint32_t addr, size_t length, uint8_t *buf); +cy_rslt_t cy_serial_flash_qspi_read(uint32_t addr, size_t length, uint8_t *buf); /** - * \brief Writes the data to the serial flash on the board. The program area + * \brief Writes the data to the serial flash memory. The program area * must have been erased prior to calling this API using - * \ref cybsp_serial_flash_erase() This is a blocking function. Returns error if + * \ref cy_serial_flash_qspi_erase() This is a blocking function. Returns error if * (addr + length) exceeds the flash size. * \param addr Starting address to write to * \param length Number of bytes to write * \param buf Pointer to the buffer storing the data to be written * \returns CY_RSLT_SUCCESS if the write was successful, an error code - * otherwise. + * otherwise. */ -cy_rslt_t cybsp_serial_flash_write(uint32_t addr, size_t length, const uint8_t *buf); +cy_rslt_t cy_serial_flash_qspi_write(uint32_t addr, size_t length, const uint8_t *buf); /** - * \brief Erases the serial flash on the board, uses chip erase command when + * \brief Erases the serial flash memory, uses chip erase command when * addr = 0 and length = flash_size otherwise uses sector erase command. This is * a blocking function. Returns error if addr or (addr + length) is not aligned * to the sector size or if (addr + length) exceeds the flash size. - * Call \ref cybsp_serial_flash_get_size() to get the flash size and - * call \ref cybsp_serial_flash_get_erase_size() to get the size of an erase + * Call \ref cy_serial_flash_qspi_get_size() to get the flash size and + * call \ref cy_serial_flash_qspi_get_erase_size() to get the size of an erase * sector. * * \param addr Starting address to begin erasing @@ -120,24 +148,26 @@ cy_rslt_t cybsp_serial_flash_write(uint32_t addr, size_t length, const uint8_t * * \returns CY_RSLT_SUCCESS if the erase was successful, an error code * otherwise. */ -cy_rslt_t cybsp_serial_flash_erase(uint32_t addr, size_t length); +cy_rslt_t cy_serial_flash_qspi_erase(uint32_t addr, size_t length); /** * \brief Enables Execute-in-Place (memory mapped) mode on the MCU. This * function does not send any command to the serial flash. This may not be * supported on all the targets in which case - * CYBSP_RSLT_SERIAL_FLASH_ERR_UNSUPPORTED is returned. + * CY_RSLT_SERIAL_FLASH_ERR_UNSUPPORTED is returned. * \param enable true: XIP mode is set, false: normal mode is set * \returns CY_RSLT_SUCCESS if the operation was successful. - * CYBSP_RSLT_SERIAL_FLASH_ERR_UNSUPPORTED if the target does not + * CY_RSLT_SERIAL_FLASH_ERR_UNSUPPORTED if the target does not * support XIP. */ -cy_rslt_t cybsp_serial_flash_enable_xip(bool enable); +cy_rslt_t cy_serial_flash_qspi_enable_xip(bool enable); -/** \} group_bsp_serial_flash_functions */ +/** \} group_serial_flash_functions */ #if defined(__cplusplus) } #endif -/** \} group_bsp_serial_flash */ +#endif /* CY_IP_MXSMIF */ + +/** \} group_serial_flash */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_serial_flash.c b/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_serial_flash.c deleted file mode 100644 index f8b5dac666e..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_serial_flash.c +++ /dev/null @@ -1,180 +0,0 @@ -/***************************************************************************//** -* \file cybsp_serial_flash.c -* -* \brief -* Provides APIs for interacting with an external flash connected to the SPI or -* QSPI interface, uses the configuration generated by the QSPI configurator, -* uses SFDP to auto-discover memory properties if SFDP is enabled in the -* configuration. -* -******************************************************************************** -* \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include -#include "cybsp_serial_flash.h" -#include "cy_pdl.h" -#include "cyhal_qspi.h" -#include "cy_utils.h" -#include "cybsp.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -#if defined(CYBSP_QSPI_SCK) -#include "cycfg_qspi_memslot.h" - -/** \cond internal */ - -#define QSPI_BUS_FREQUENCY_HZ (50000000lu) - -/** Timeout to apply while polling the memory for its ready status after quad - * enable command has been sent out. Quad enable is a non-volatile write. -*/ -#define CYBSP_SERIAL_FLASH_QUAD_ENABLE_TIMEOUT_US (5000lu) /* in microseconds */ - -/* SMIF slot number to which the memory is connected */ -#define MEM_SLOT (0u) - -/** \endcond */ - -static cyhal_qspi_t qspi_obj; - -cy_rslt_t cybsp_serial_flash_init(void) -{ - cy_en_smif_status_t smifStatus = CY_SMIF_SUCCESS; - - cy_rslt_t result = cyhal_qspi_init(&qspi_obj, CYBSP_QSPI_D0, CYBSP_QSPI_D1, CYBSP_QSPI_D2, CYBSP_QSPI_D3, NC, NC, NC, NC, - CYBSP_QSPI_SCK, CYBSP_QSPI_SS, QSPI_BUS_FREQUENCY_HZ, 0); - if(CY_RSLT_SUCCESS == result) - { - /* Perform SFDP detection and XIP register configuration depending on the - * memory configuration. - */ - smifStatus = Cy_SMIF_Memslot_Init(qspi_obj.base, (cy_stc_smif_block_config_t *) &smifBlockConfig, &qspi_obj.context); - if(CY_SMIF_SUCCESS == smifStatus) - { - /* Enable Quad mode (1-1-4 or 1-4-4 modes) to use all the four I/Os during - * communication. - */ - if(smifMemConfigs[MEM_SLOT]->deviceCfg->readCmd->dataWidth == CY_SMIF_WIDTH_QUAD - || smifMemConfigs[MEM_SLOT]->deviceCfg->programCmd->dataWidth == CY_SMIF_WIDTH_QUAD) - { - bool isQuadEnabled = false; - smifStatus = Cy_SMIF_MemIsQuadEnabled(qspi_obj.base, smifMemConfigs[MEM_SLOT], &isQuadEnabled, &qspi_obj.context); - if(CY_SMIF_SUCCESS == smifStatus) - { - if(!isQuadEnabled) - { - smifStatus = Cy_SMIF_MemEnableQuadMode(qspi_obj.base, smifMemConfigs[MEM_SLOT], CYBSP_SERIAL_FLASH_QUAD_ENABLE_TIMEOUT_US, &qspi_obj.context); - } - } - } - } - } - - if((CY_RSLT_SUCCESS == result) && (CY_SMIF_SUCCESS == smifStatus)) - { - return CY_RSLT_SUCCESS; - } - else - { - cybsp_serial_flash_deinit(); - return (cy_rslt_t)smifStatus; - } -} - -void cybsp_serial_flash_deinit(void) -{ - cyhal_qspi_free(&qspi_obj); -} - -size_t cybsp_serial_flash_get_size(void) -{ - return (size_t)smifMemConfigs[MEM_SLOT]->deviceCfg->memSize; -} - -/* address is ignored for the memory with uniform sector size. Currently, - * QSPI Configurator does not support memories with hybrid sectors. - */ -size_t cybsp_serial_flash_get_erase_size(uint32_t addr) -{ - CY_UNUSED_PARAMETER(addr); - return (size_t)smifMemConfigs[MEM_SLOT]->deviceCfg->eraseSize; -} - -cy_rslt_t cybsp_serial_flash_read(uint32_t addr, size_t length, uint8_t *buf) -{ - /* Cy_SMIF_MemRead() returns error if (addr + length) > total flash size. */ - return (cy_rslt_t)Cy_SMIF_MemRead(qspi_obj.base, smifMemConfigs[MEM_SLOT], addr, buf, length, &qspi_obj.context); -} - -cy_rslt_t cybsp_serial_flash_write(uint32_t addr, size_t length, const uint8_t *buf) -{ - /* Cy_SMIF_MemWrite() returns error if (addr + length) > total flash size. */ - return (cy_rslt_t)Cy_SMIF_MemWrite(qspi_obj.base, smifMemConfigs[MEM_SLOT], addr, (uint8_t *)buf, length, &qspi_obj.context); -} - -/* Does not support hybrid sectors, sector size must be uniform on the entire - * chip. Use cybsp_serial_flash_get_erase_size(addr) to implement hybrid sector - * support when QSPI Configurator and PDL supports memories with hybrid sectors. - */ -cy_rslt_t cybsp_serial_flash_erase(uint32_t addr, size_t length) -{ - cy_en_smif_status_t smifStatus; - - /* If the erase is for the entire chip, use chip erase command */ - if((addr == 0u) && (length == cybsp_serial_flash_get_size())) - { - smifStatus = Cy_SMIF_MemEraseChip(qspi_obj.base, smifMemConfigs[MEM_SLOT], &qspi_obj.context); - } - else - { - /* Cy_SMIF_MemEraseSector() returns error if (addr + length) > total flash size - * or if addr is not aligned to erase sector size or if (addr + length) - * is not aligned to erase sector size. - */ - smifStatus = Cy_SMIF_MemEraseSector(qspi_obj.base, smifMemConfigs[MEM_SLOT], addr, length, &qspi_obj.context); - } - - return (cy_rslt_t)smifStatus; -} - -// This function enables or disables XIP on the MCU, does not send any command -// to the serial flash. XIP register configuration is already done as part of -// cybsp_serial_flash_init() if MMIO mode is enabled in the QSPI -// Configurator. -cy_rslt_t cybsp_serial_flash_enable_xip(bool enable) -{ - if(enable) - { - Cy_SMIF_SetMode(qspi_obj.base, CY_SMIF_MEMORY); - } - else - { - Cy_SMIF_SetMode(qspi_obj.base, CY_SMIF_NORMAL); - } - - return CY_RSLT_SUCCESS; -} - -#endif /* defined(CYBSP_QSPI_SCK) */ - -#if defined(__cplusplus) -} -#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/mbed_overrides.c b/targets/TARGET_Cypress/TARGET_PSOC6/mbed_overrides.c index 26b366c32a9..3fc9263ff81 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/mbed_overrides.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/mbed_overrides.c @@ -19,13 +19,13 @@ #include "device.h" #include "cycfg.h" #include "cyhal_hwmgr.h" -#include "cybsp_core.h" +#include "cybsp.h" #include "mbed_power_mgmt.h" #include "rtos_idle.h" #include "us_ticker_api.h" -#if defined(CYBSP_ENABLE_FLASH_STORAGE) -#include "cybsp_serial_flash.h" -#endif /* defined(CYBSP_ENABLE_FLASH_STORAGE) */ +#if defined(MBED_CONF_TARGET_XIP_ENABLE) +#include "cy_serial_flash_qspi.h" +#endif /* defined(MBED_CONF_TARGET_XIP_ENABLE) */ #if defined(COMPONENT_SPM_MAILBOX) void mailbox_init(void); @@ -93,9 +93,9 @@ void mbed_sdk_init(void) #if defined(CYBSP_ENABLE_FLASH_STORAGE) /* The linker script allows storing data in external memory, if needed, enable access to that memory. */ - cybsp_serial_flash_init(); - cybsp_serial_flash_enable_xip(true); -#endif /* defined(CYBSP_ENABLE_FLASH_STORAGE) */ + cy_serial_flash_init(); + cy_serial_flash_enable_xip(true); +#endif /* Enable global interrupts (disabled in CM4 startup assembly) */ __enable_irq(); From 45b674623fdeb44afc9ffa7453616c70ebc789f4 Mon Sep 17 00:00:00 2001 From: Kyle Kearney Date: Thu, 19 Sep 2019 12:03:32 -0700 Subject: [PATCH 179/227] Update CY8CPROTO-064-SB linker scripts Update linker scripts for the latest PDL to be consistent with other Cypress targets --- .../device/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct | 14 ++++++-------- .../TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld | 18 +++++++----------- .../device/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf | 12 +++++++----- .../TOOLCHAIN_IAR/startup_psoc6_01_cm4.S | 4 ---- .../device/system_psoc6.h | 7 ++++++- .../device/system_psoc6_cm4.c | 2 +- 6 files changed, 27 insertions(+), 30 deletions(-) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct index 542ebce868f..b2d1ee2e364 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct @@ -4,7 +4,7 @@ ;******************************************************************************* ;* \file cyb06xx7_cm4_dual.sct -;* \version 2.50 +;* \version 2.60 ;* ;* Linker file for the ARMCC. ;* @@ -78,6 +78,7 @@ #define MBED_BOOT_STACK_SIZE 0x400 #endif +; Size of the stack section at the end of CM4 SRAM #define STACK_SIZE MBED_BOOT_STACK_SIZE ; The defines below describe the location and size of blocks of memory in the target. @@ -133,12 +134,9 @@ #define EFUSE_START 0x90700000 #define EFUSE_SIZE 0x100000 -; Size and start address of the Cortex-M4 application image -#define FLASH_CM4_SIZE FLASH_SIZE -#define FLASH_CM4_START FLASH_START -; Cortex-M4 application image -LR_IROM1 FLASH_CM4_START FLASH_CM4_SIZE +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE { ER_FLASH_VECTORS +0 { @@ -159,7 +157,7 @@ LR_IROM1 FLASH_CM4_START FLASH_CM4_SIZE RW_RAM_DATA +0 { * (.cy_ramfunc) - .ANY (+RW, +ZI) + * (+RW, +ZI) } ; Place variables in the section that should not be initialized during the @@ -275,7 +273,7 @@ CYMETA 0x90500000 /* The following symbols used by the cymcuelftool. */ /* Flash */ #define __cy_memory_0_start 0x10000000 -#define __cy_memory_0_length 0x00100000 +#define __cy_memory_0_length 0x000D0000 #define __cy_memory_0_row_size 0x200 /* Emulated EEPROM Flash area */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld index ebb6f76525c..0a81d0b541d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyb06xx7_cm4_dual.ld -* \version 2.50 +* \version 2.60 * * Linker file for the GNU C compiler. * @@ -76,6 +76,7 @@ ENTRY(Reset_Handler) #define MBED_BOOT_STACK_SIZE 0x400 #endif +/* Size of the stack section at the end of CM4 SRAM */ STACK_SIZE = MBED_BOOT_STACK_SIZE; /* Force symbol to be entered in the output file as an undefined symbol. Doing @@ -118,10 +119,6 @@ MEMORY efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ } -/* Size and start address of the Cortex-M4 application image */ -FLASH_CM4_SIZE = LENGTH(flash); -FLASH_CM4_START = ORIGIN(flash); - /* Library configurations */ GROUP(libgcc.a libc.a libm.a libnosys.a) @@ -161,8 +158,8 @@ GROUP(libgcc.a libc.a libm.a libnosys.a) SECTIONS { - /* Cortex-M4 application image */ - .text FLASH_CM4_START : + /* Cortex-M4 application flash area */ + .text ORIGIN(flash) : { . = ALIGN(4); __Vectors = . ; @@ -278,7 +275,6 @@ SECTIONS KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); - . = ALIGN(4); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); @@ -339,7 +335,7 @@ SECTIONS __HeapLimit = .; } > ram - + /* Set stack top to end of RAM, and stack limit move down by * size of stack_dummy section */ __StackTop = ORIGIN(ram) + LENGTH(ram); @@ -392,7 +388,7 @@ SECTIONS KEEP(*(.cy_toc_part2)) } > sflash_toc_2 - + /* Supervisory Flash: Table of Content # 2 Copy */ .cy_rtoc_part2 : { @@ -426,7 +422,7 @@ SECTIONS /* The following symbols used by the cymcuelftool. */ /* Flash */ __cy_memory_0_start = 0x10000000; -__cy_memory_0_length = 0x00100000; +__cy_memory_0_length = 0x000D0000; __cy_memory_0_row_size = 0x200; /* Emulated EEPROM Flash area */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf index 67556454eb5..f6322dc7bcb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cyb06xx7_cm4_dual.icf -* \version 2.50 +* \version 2.60 * * Linker file for the IAR compiler. * @@ -156,7 +156,7 @@ if (!isdefinedsymbol(__STACK_SIZE)) { /* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ if (!isdefinedsymbol(__HEAP_SIZE)) { - define symbol __ICFEDIT_size_heap__ = 0x400; + define symbol __ICFEDIT_size_heap__ = 0x0400; } else { define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; } @@ -191,8 +191,10 @@ do not initialize { section .noinit, section .intvec_ram }; /*-Placement-*/ -/* Flash - Cortex-M4 application image */ -place in IROM1_region { block RO }; +/* Flash - Cortex-M4 application */ +place at start of IROM1_region { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ ".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; /* Emulated EEPROM Flash area */ @@ -245,7 +247,7 @@ keep { section .cy_app_signature, /* The following symbols used by the cymcuelftool. */ /* Flash */ define exported symbol __cy_memory_0_start = 0x10000000; -define exported symbol __cy_memory_0_length = 0x00100000; +define exported symbol __cy_memory_0_length = 0x000D0000; define exported symbol __cy_memory_0_row_size = 0x200; /* Emulated EEPROM Flash area */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S index 75747c4face..f4ca47b4579 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S @@ -310,10 +310,6 @@ intvec_copy STR r0, [r1] dsb - ; Enable the FPU if used - LDR R0, =Cy_SystemInitFpuEnable - BLX R0 - ; Initialize data sections LDR R0, =__iar_data_init3 BLX R0 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/system_psoc6.h index 53bc71262c6..423361f58ab 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/system_psoc6.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/system_psoc6.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file system_psoc6.h -* \version 2.50 +* \version 2.60 * * \brief Device system header file. * @@ -320,6 +320,11 @@ *
Reason for Change
2.60Updated linker scripts.Provided support for new devices, updated usage of CM0p prebuilt image.
2.50Updated assembler files, C files, linker scripts.Dynamic allocated HEAP size for Arm Compiler 6, IAR 8.
+* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
2.3RThe character sequence // shall not be used within a comment.The comments provide a useful WEB link to the documentation.
+* +* \section group_system_config_changelog Changelog +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
VersionChangesReason for Change
2.60Updated linker scripts.Provided support for new devices, updated usage of CM0p prebuilt image.
2.50Updated assembler files, C files, linker scripts.Dynamic allocated HEAP size for Arm Compiler 6, IAR 8.
2.40Updated assembler files, C files, linker scripts.Added Arm Compiler 6 support.
2.30Added assembler files, linker scripts for Mbed OS.Added Arm Mbed OS embedded operating system support.
Updated linker scripts to extend the Flash and Ram memories size available for the CM4 core.Enhanced PDL usability.
2.20Moved the Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit() functions implementation from IPC to Startup.Changed the IPC driver configuration method from compile time to run time.
2.10Added constructor attribute to SystemInit() function declaration for ARM MDK compiler. \n +* Removed $Sub$$main symbol for ARM MDK compiler. +* uVision Debugger support.
Updated description of the Startup behavior for Single-Core Devices. \n +* Added note about WDT disabling by SystemInit() function. +* Documentation improvement.
2.0Added restoring of FLL registers to the default state in SystemInit() API for single core devices. +* Single core device support. +*
Added Normal Access Restrictions, Public Key, TOC part2 and TOC part2 copy to Supervisory flash linker memory regions. \n +* Renamed 'wflash' memory region to 'em_eeprom'. +* Linker scripts usability improvement.
Added Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit(), Cy_Flash_Init() functions call to SystemInit() API.Reserved system resources for internal operations.
Added clearing and releasing of IPC structure #7 (reserved for the Deep-Sleep operations) to SystemInit() API.To avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering.
1.0Initial version
+* +* +* \defgroup group_system_config_macro Macro +* \{ +* \defgroup group_system_config_system_macro System +* \defgroup group_system_config_cm4_status_macro Cortex-M4 Status +* \defgroup group_system_config_user_settings_macro User Settings +* \} +* \defgroup group_system_config_functions Functions +* \{ +* \defgroup group_system_config_system_functions System +* \defgroup group_system_config_cm4_functions Cortex-M4 Control +* \} +* \defgroup group_system_config_globals Global Variables +* +* \} +*/ + +/** +* \addtogroup group_system_config_system_functions +* \{ +* \details +* The following system functions implement CMSIS Core functions. +* Refer to the [CMSIS documentation] +* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") +* for more details. +* \} +*/ + +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************************* +* Include files +*******************************************************************************/ +#include + + +/******************************************************************************* +* Global preprocessor symbols/macros ('define') +*******************************************************************************/ +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined (__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3))) + #define CY_SYSTEM_CPU_CM0P 1UL +#else + #define CY_SYSTEM_CPU_CM0P 0UL +#endif + +#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) + #include "cyfitter.h" +#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */ + + + + +/******************************************************************************* +* +* START OF USER SETTINGS HERE +* =========================== +* +* All lines with '<<<' can be set by user. +* +*******************************************************************************/ + +/** +* \addtogroup group_system_config_user_settings_macro +* \{ +*/ + +#if defined (CYDEV_CLK_EXTCLK__HZ) + #define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ) +#else + /***************************************************************************//** + * External Clock Frequency (in Hz, [value]UL). If compiled within + * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. + * Otherwise, edit the value below. + * (USER SETTING) + *******************************************************************************/ + #define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */ +#endif /* (CYDEV_CLK_EXTCLK__HZ) */ + + +#if defined (CYDEV_CLK_ECO__HZ) + #define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ) +#else + /***************************************************************************//** + * \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled + * within PSoC Creator and the clock is enabled in the DWR, the value from DWR + * used. + * (USER SETTING) + *******************************************************************************/ + #define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */ +#endif /* (CYDEV_CLK_ECO__HZ) */ + + +#if defined (CYDEV_CLK_ALTHF__HZ) + #define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ) +#else + /***************************************************************************//** + * \brief Alternate high frequency (in Hz, [value]UL). If compiled within + * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. + * Otherwise, edit the value below. + * (USER SETTING) + *******************************************************************************/ + #define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */ +#endif /* (CYDEV_CLK_ALTHF__HZ) */ + + +/***************************************************************************//** +* \brief Start address of the Cortex-M4 application ([address]UL) +* (USER SETTING) +*******************************************************************************/ +#if !defined (CY_CORTEX_M4_APPL_ADDR) + #define CY_CORTEX_M4_APPL_ADDR (CY_FLASH_BASE + 0x2000U) /* <<< 8 kB of flash is reserved for the Cortex-M0+ application */ +#endif /* (CY_CORTEX_M4_APPL_ADDR) */ + + +/***************************************************************************//** +* \brief IPC Semaphores allocation ([value]UL). +* (USER SETTING) +*******************************************************************************/ +#define CY_IPC_SEMA_COUNT (128UL) /* <<< This will allow 128 (4*32) semaphores */ + + +/***************************************************************************//** +* \brief IPC Pipe definitions ([value]UL). +* (USER SETTING) +*******************************************************************************/ +#define CY_IPC_MAX_ENDPOINTS (8UL) /* <<< 8 endpoints */ + + +/******************************************************************************* +* +* END OF USER SETTINGS HERE +* ========================= +* +*******************************************************************************/ + +/** \} group_system_config_user_settings_macro */ + + +/** +* \addtogroup group_system_config_system_macro +* \{ +*/ + +#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) + /** The Cortex-M0+ startup driver identifier */ + #define CY_STARTUP_M0P_ID ((uint32_t)((uint32_t)((0x0EU) & 0x3FFFU) << 18U)) +#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */ + +#if (CY_SYSTEM_CPU_CM0P != 1UL) || defined(CY_DOXYGEN) + /** The Cortex-M4 startup driver identifier */ + #define CY_STARTUP_M4_ID ((uint32_t)((uint32_t)((0x0FU) & 0x3FFFU) << 18U)) +#endif /* (CY_SYSTEM_CPU_CM0P != 1UL) */ + +/** \} group_system_config_system_macro */ + + +/** +* \addtogroup group_system_config_system_functions +* \{ +*/ +extern void SystemInit(void); + +extern void SystemCoreClockUpdate(void); +/** \} group_system_config_system_functions */ + + +/** +* \addtogroup group_system_config_cm4_functions +* \{ +*/ +extern uint32_t Cy_SysGetCM4Status(void); +extern void Cy_SysEnableCM4(uint32_t vectorTableOffset); +extern void Cy_SysDisableCM4(void); +extern void Cy_SysRetainCM4(void); +extern void Cy_SysResetCM4(void); +/** \} group_system_config_cm4_functions */ + + +/** \cond */ +extern void Default_Handler (void); + +void Cy_SysIpcPipeIsrCm0(void); +void Cy_SysIpcPipeIsrCm4(void); + +extern void Cy_SystemInit(void); +extern void Cy_SystemInitFpuEnable(void); + +extern uint32_t cy_delayFreqHz; +extern uint32_t cy_delayFreqKhz; +extern uint8_t cy_delayFreqMhz; +extern uint32_t cy_delay32kMs; +/** \endcond */ + + +#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) +/** +* \addtogroup group_system_config_cm4_status_macro +* \{ +*/ +#define CY_SYS_CM4_STATUS_ENABLED (3U) /**< The Cortex-M4 core is enabled: power on, clock on, no isolate, no reset and no retain. */ +#define CY_SYS_CM4_STATUS_DISABLED (0U) /**< The Cortex-M4 core is disabled: power off, clock off, isolate, reset and no retain. */ +#define CY_SYS_CM4_STATUS_RETAINED (2U) /**< The Cortex-M4 core is retained. power off, clock off, isolate, no reset and retain. */ +#define CY_SYS_CM4_STATUS_RESET (1U) /**< The Cortex-M4 core is in the Reset mode: clock off, no isolated, no retain and reset. */ +/** \} group_system_config_cm4_status_macro */ + +#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */ + + +/******************************************************************************* +* IPC Configuration +* ========================= +*******************************************************************************/ +/* IPC CY_PIPE default configuration */ +#define CY_SYS_CYPIPE_CLIENT_CNT (8UL) + +#define CY_SYS_INTR_CYPIPE_MUX_EP0 (1UL) /* IPC CYPRESS PIPE */ +#define CY_SYS_INTR_CYPIPE_PRIOR_EP0 (1UL) /* Notifier Priority */ +#define CY_SYS_INTR_CYPIPE_PRIOR_EP1 (1UL) /* Notifier Priority */ + +#define CY_SYS_CYPIPE_CHAN_MASK_EP0 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP0) +#define CY_SYS_CYPIPE_CHAN_MASK_EP1 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP1) + + +/******************************************************************************/ +/* + * The System pipe configuration defines the IPC channel number, interrupt + * number, and the pipe interrupt mask for the endpoint. + * + * The format of the endPoint configuration + * Bits[31:16] Interrupt Mask + * Bits[15:8 ] IPC interrupt + * Bits[ 7:0 ] IPC channel + */ + +/* System Pipe addresses */ +/* CyPipe defines */ + +#define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 ) + +#define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ + | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP0) +#define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ + | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP1) + +/******************************************************************************/ + + +/** \addtogroup group_system_config_globals +* \{ +*/ + +extern uint32_t SystemCoreClock; +extern uint32_t cy_BleEcoClockFreqHz; +extern uint32_t cy_Hfclk0FreqHz; +extern uint32_t cy_PeriClkFreqHz; + +/** \} group_system_config_globals */ + + + +/** \cond INTERNAL */ +/******************************************************************************* +* Backward compatibility macro. The following code is DEPRECATED and must +* not be used in new projects +*******************************************************************************/ + +/* BWC defines for functions related to enter/exit critical section */ +#define Cy_SaveIRQ Cy_SysLib_EnterCriticalSection +#define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection +#define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0) +#define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1) + +/** \endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_PSOC6_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/system_psoc6_cm4.c new file mode 100644 index 00000000000..0a18f50a4d4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/device/system_psoc6_cm4.c @@ -0,0 +1,552 @@ +/***************************************************************************//** +* \file system_psoc6_cm4.c +* \version 2.60 +* +* The device system-source file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include +#include "system_psoc6.h" +#include "cy_device.h" +#include "cy_device_headers.h" +#include "cy_syslib.h" +#include "cy_wdt.h" + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + #include "cy_ipc_sema.h" + #include "cy_ipc_pipe.h" + #include "cy_ipc_drv.h" + + #if defined(CY_DEVICE_PSOC6ABLE2) + #include "cy_flash.h" + #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ +#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ + + +/******************************************************************************* +* SystemCoreClockUpdate() +*******************************************************************************/ + +/** Default HFClk frequency in Hz */ +#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL) + +/** Default PeriClk frequency in Hz */ +#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL) + +/** Default SlowClk system core frequency in Hz */ +#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL) + +/** IMO frequency in Hz */ +#define CY_CLK_IMO_FREQ_HZ (8000000UL) + +/** HVILO frequency in Hz */ +#define CY_CLK_HVILO_FREQ_HZ (32000UL) + +/** PILO frequency in Hz */ +#define CY_CLK_PILO_FREQ_HZ (32768UL) + +/** WCO frequency in Hz */ +#define CY_CLK_WCO_FREQ_HZ (32768UL) + +/** ALTLF frequency in Hz */ +#define CY_CLK_ALTLF_FREQ_HZ (32768UL) + + +/** +* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, +* which is the system clock frequency supplied to the SysTick timer and the +* processor core clock. +* This variable implements CMSIS Core global variable. +* Refer to the [CMSIS documentation] +* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") +* for more details. +* This variable can be used by debuggers to query the frequency +* of the debug timer or to configure the trace clock speed. +* +* \attention Compilers must be configured to avoid removing this variable in case +* the application program is not using it. Debugging systems require the variable +* to be physically present in memory so that it can be examined to configure the debugger. */ +uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; + +/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; + +/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */ +#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) + uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; +#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ + +/* SCB->CPACR */ +#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u) + + +/******************************************************************************* +* SystemInit() +*******************************************************************************/ + +/* CLK_FLL_CONFIG default values */ +#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u) +#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u) +#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) +#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) + + +/******************************************************************************* +* SystemCoreClockUpdate (void) +*******************************************************************************/ + +/* Do not use these definitions directly in your application */ +#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) +#define CY_DELAY_1K_THRESHOLD (1000u) +#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) +#define CY_DELAY_1M_THRESHOLD (1000000u) +#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) +uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / + CY_DELAY_1K_THRESHOLD; + +uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) / + CY_DELAY_1M_THRESHOLD); + +uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * + ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD); + +#define CY_ROOT_PATH_SRC_IMO (0UL) +#define CY_ROOT_PATH_SRC_EXT (1UL) +#if (SRSS_ECO_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_ECO (2UL) +#endif /* (SRSS_ECO_PRESENT == 1U) */ +#if (SRSS_ALTHF_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_ALTHF (3UL) +#endif /* (SRSS_ALTHF_PRESENT == 1U) */ +#define CY_ROOT_PATH_SRC_DSI_MUX (4UL) +#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL) +#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL) +#if (SRSS_ALTLF_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL) +#endif /* (SRSS_ALTLF_PRESENT == 1U) */ +#if (SRSS_PILO_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL) +#endif /* (SRSS_PILO_PRESENT == 1U) */ + + +/******************************************************************************* +* Function Name: SystemInit +****************************************************************************//** +* \cond +* Initializes the system: +* - Restores FLL registers to the default state for single core devices. +* - Unlocks and disables WDT. +* - Calls Cy_PDL_Init() function to define the driver library. +* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator. +* - Calls \ref SystemCoreClockUpdate(). +* \endcond +*******************************************************************************/ +void SystemInit(void) +{ + Cy_PDL_Init(CY_DEVICE_CFG); + +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Restore FLL registers to the default state as they are not restored by the ROM code */ + uint32_t copy = SRSS->CLK_FLL_CONFIG; + copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk; + SRSS->CLK_FLL_CONFIG = copy; + + copy = SRSS->CLK_ROOT_SELECT[0u]; + copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/ + SRSS->CLK_ROOT_SELECT[0u] = copy; + + SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE; + SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE; + SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE; + SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE; + + /* Unlock and disable WDT */ + Cy_WDT_Unlock(); + Cy_WDT_Disable(); + #endif /* (__CM0P_PRESENT == 0) */ +#endif /* __CM0P_PRESENT */ + + Cy_SystemInit(); + SystemCoreClockUpdate(); + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Allocate and initialize semaphores for the system operations. */ + static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD]; + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray); + #else + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL); + #endif /* (__CM0P_PRESENT) */ +#else + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL); +#endif /* __CM0P_PRESENT */ + + + /******************************************************************************** + * + * Initializes the system pipes. The system pipes are used by BLE and Flash. + * + * If the default startup file is not used, or SystemInit() is not called in your + * project, call the following three functions prior to executing any flash or + * EmEEPROM write or erase operation: + * -# Cy_IPC_Sema_Init() + * -# Cy_IPC_Pipe_Config() + * -# Cy_IPC_Pipe_Init() + * -# Cy_Flash_Init() + * + *******************************************************************************/ + /* Create an array of endpoint structures */ + static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS]; + + Cy_IPC_Pipe_Config(systemIpcPipeEpArray); + + static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT]; + + static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm4 = + { + /* .ep0ConfigData */ + { + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0, + /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0, + /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0, + /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR, + /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0 + }, + /* .ep1ConfigData */ + { + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1, + /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1, + /* .ipcNotifierMuxNumber */ 0u, + /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR, + /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1 + }, + /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT, + /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray, + /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4 + }; + + if (cy_device->flashPipeRequired != 0u) + { + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); + } + +#if defined(CY_DEVICE_PSOC6ABLE2) + Cy_Flash_Init(); +#endif /* defined(CY_DEVICE_PSOC6ABLE2) */ + +#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ +} + + +/******************************************************************************* +* Function Name: Cy_SystemInit +****************************************************************************//** +* +* The function is called during device startup. Once project compiled as part of +* the PSoC Creator project, the Cy_SystemInit() function is generated by the +* PSoC Creator. +* +* The function generated by PSoC Creator performs all of the necessary device +* configuration based on the design settings. This includes settings from the +* Design Wide Resources (DWR) such as Clocks and Pins as well as any component +* configuration that is necessary. +* +*******************************************************************************/ +__WEAK void Cy_SystemInit(void) +{ + /* Empty weak function. The actual implementation to be in the PSoC Creator + * generated strong function. + */ +} + + +/******************************************************************************* +* Function Name: SystemCoreClockUpdate +****************************************************************************//** +* +* Gets core clock frequency and updates \ref SystemCoreClock, \ref +* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz. +* +* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref +* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles(). +* +*******************************************************************************/ +void SystemCoreClockUpdate (void) +{ + uint32_t srcFreqHz; + uint32_t pathFreqHz; + uint32_t fastClkDiv; + uint32_t periClkDiv; + uint32_t rootPath; + uint32_t srcClk; + + /* Get root path clock for the high-frequency clock # 0 */ + rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]); + + /* Get source of the root path clock */ + srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]); + + /* Get frequency of the source */ + switch (srcClk) + { + case CY_ROOT_PATH_SRC_IMO: + srcFreqHz = CY_CLK_IMO_FREQ_HZ; + break; + + case CY_ROOT_PATH_SRC_EXT: + srcFreqHz = CY_CLK_EXT_FREQ_HZ; + break; + + #if (SRSS_ECO_PRESENT == 1U) + case CY_ROOT_PATH_SRC_ECO: + srcFreqHz = CY_CLK_ECO_FREQ_HZ; + break; + #endif /* (SRSS_ECO_PRESENT == 1U) */ + +#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) + case CY_ROOT_PATH_SRC_ALTHF: + srcFreqHz = cy_BleEcoClockFreqHz; + break; +#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */ + + case CY_ROOT_PATH_SRC_DSI_MUX: + { + uint32_t dsi_src; + dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]); + switch (dsi_src) + { + case CY_ROOT_PATH_SRC_DSI_MUX_HVILO: + srcFreqHz = CY_CLK_HVILO_FREQ_HZ; + break; + + case CY_ROOT_PATH_SRC_DSI_MUX_WCO: + srcFreqHz = CY_CLK_WCO_FREQ_HZ; + break; + + #if (SRSS_ALTLF_PRESENT == 1U) + case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF: + srcFreqHz = CY_CLK_ALTLF_FREQ_HZ; + break; + #endif /* (SRSS_ALTLF_PRESENT == 1U) */ + + #if (SRSS_PILO_PRESENT == 1U) + case CY_ROOT_PATH_SRC_DSI_MUX_PILO: + srcFreqHz = CY_CLK_PILO_FREQ_HZ; + break; + #endif /* (SRSS_PILO_PRESENT == 1U) */ + + default: + srcFreqHz = CY_CLK_HVILO_FREQ_HZ; + break; + } + } + break; + + default: + srcFreqHz = CY_CLK_EXT_FREQ_HZ; + break; + } + + if (rootPath == 0UL) + { + /* FLL */ + bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS)); + bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)); + bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) || + (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3))); + if ((fllOutputAuto && fllLocked) || fllOutputOutput) + { + uint32_t fllMult; + uint32_t refDiv; + uint32_t outputDiv; + + fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG); + refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2); + outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL; + + pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv; + } + else + { + pathFreqHz = srcFreqHz; + } + } + else if ((rootPath == 1UL) || (rootPath == 2UL)) + { + /* PLL */ + bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL])); + bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])); + bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) || + (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]))); + if ((pllOutputAuto && pllLocked) || pllOutputOutput) + { + uint32_t feedbackDiv; + uint32_t referenceDiv; + uint32_t outputDiv; + + feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); + referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); + outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); + + pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv; + + } + else + { + pathFreqHz = srcFreqHz; + } + } + else + { + /* Direct */ + pathFreqHz = srcFreqHz; + } + + /* Get frequency after hf_clk pre-divider */ + pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]); + cy_Hfclk0FreqHz = pathFreqHz; + + /* Fast Clock Divider */ + fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL); + + /* Peripheral Clock Divider */ + periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL); + cy_PeriClkFreqHz = pathFreqHz / periClkDiv; + + pathFreqHz = pathFreqHz / fastClkDiv; + SystemCoreClock = pathFreqHz; + + /* Sets clock frequency for Delay API */ + cy_delayFreqHz = SystemCoreClock; + cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; + cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; +} + + +/******************************************************************************* +* Function Name: Cy_SystemInitFpuEnable +****************************************************************************//** +* +* Enables the FPU if it is used. The function is called from the startup file. +* +*******************************************************************************/ +void Cy_SystemInitFpuEnable(void) +{ + #if defined (__FPU_USED) && (__FPU_USED == 1U) + uint32_t interruptState; + interruptState = Cy_SysLib_EnterCriticalSection(); + SCB->CPACR |= SCB_CPACR_CP10_CP11_ENABLE; + __DSB(); + __ISB(); + Cy_SysLib_ExitCriticalSection(interruptState); + #endif /* (__FPU_USED) && (__FPU_USED == 1U) */ +} + + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) +/******************************************************************************* +* Function Name: Cy_SysIpcPipeIsrCm4 +****************************************************************************//** +* +* This is the interrupt service routine for the system pipe. +* +*******************************************************************************/ +void Cy_SysIpcPipeIsrCm4(void) +{ + Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM4_ADDR); +} +#endif + + +/******************************************************************************* +* Function Name: Cy_MemorySymbols +****************************************************************************//** +* +* The intention of the function is to declare boundaries of the memories for the +* MDK compilers. For the rest of the supported compilers, this is done using +* linker configuration files. The following symbols used by the cymcuelftool. +* +*******************************************************************************/ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) +__asm void Cy_MemorySymbols(void) +{ + /* Flash */ + EXPORT __cy_memory_0_start + EXPORT __cy_memory_0_length + EXPORT __cy_memory_0_row_size + + /* Working Flash */ + EXPORT __cy_memory_1_start + EXPORT __cy_memory_1_length + EXPORT __cy_memory_1_row_size + + /* Supervisory Flash */ + EXPORT __cy_memory_2_start + EXPORT __cy_memory_2_length + EXPORT __cy_memory_2_row_size + + /* XIP */ + EXPORT __cy_memory_3_start + EXPORT __cy_memory_3_length + EXPORT __cy_memory_3_row_size + + /* eFuse */ + EXPORT __cy_memory_4_start + EXPORT __cy_memory_4_length + EXPORT __cy_memory_4_row_size + + /* Flash */ +__cy_memory_0_start EQU __cpp(CY_FLASH_BASE) +__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE) +__cy_memory_0_row_size EQU 0x200 + + /* Flash region for EEPROM emulation */ +__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE) +__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE) +__cy_memory_1_row_size EQU 0x200 + + /* Supervisory Flash */ +__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE) +__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE) +__cy_memory_2_row_size EQU 0x200 + + /* XIP */ +__cy_memory_3_start EQU __cpp(CY_XIP_BASE) +__cy_memory_3_length EQU __cpp(CY_XIP_SIZE) +__cy_memory_3_row_size EQU 0x200 + + /* eFuse */ +__cy_memory_4_start EQU __cpp(0x90700000) +__cy_memory_4_length EQU __cpp(0x100000) +__cy_memory_4_row_size EQU __cpp(1) +} +#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */ + + +/* [] END OF FILE */ diff --git a/targets/targets.json b/targets/targets.json index b8d58117454..3bf1370fdd2 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -9123,6 +9123,23 @@ "sectors": [[268443648, 512]], "bootloader_supported": true }, + "CY8CPROTO_063_BLE": { + "inherits": ["MCU_PSOC6_M4"], + "components_remove": ["QSPIF"], + "device_has_remove": ["USBDEVICE", "QSPI"], + "extra_labels_add": [ + "PSOC6_01", + "MXCRYPTO_01", + "CM0P_SLEEP" + ], + "macros_add": ["CYBLE_416045_02"], + "detect_code": ["1904"], + "post_binary_hook": { + "function": "PSOC6Code.complete" + }, + "sectors": [[268443648, 512]], + "bootloader_supported": true + }, "CY8CPROTO_064_SB": { "inherits": ["MCU_PSOC6_M4"], "components_remove": ["QSPIF"], From 82f2b72777dfe81e6e94935088a4cab834ba034c Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Thu, 3 Oct 2019 17:42:17 +0200 Subject: [PATCH 210/227] DISCO_L4R9I: update default STMOD+ pin --- .../TARGET_STM32L4R9xI/TARGET_DISCO_L4R9I/PinNames.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/TARGET_DISCO_L4R9I/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/TARGET_DISCO_L4R9I/PinNames.h index f8c96d01f2c..98dd8da49d6 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/TARGET_DISCO_L4R9I/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/TARGET_DISCO_L4R9I/PinNames.h @@ -362,8 +362,8 @@ typedef enum { /**** STMOD+ pins ****/ STMOD_1 = PA_6, - STMOD_2 = PB_15, - STMOD_3 = PB_14, + STMOD_2 = PB_10, + STMOD_3 = PB_11, STMOD_4 = PB_13, // STMOD_5 is connected to GND // STMOD_6 is connected to +5V From 19b641bb6631d83c919f229073fd22233a212567 Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Thu, 3 Oct 2019 14:17:04 +0200 Subject: [PATCH 211/227] STM32L151: update calibration memory address --- .../TARGET_STM32L1/device/stm32l1xx_ll_adc.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_adc.h b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_adc.h index d83377cae1a..03dc3167d02 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_adc.h +++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_adc.h @@ -340,11 +340,21 @@ extern "C" { /* ADC internal channels related definitions */ /* Internal voltage reference VrefInt */ +#if defined(STM32L151xBA) +#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FF80079U)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#else #define VREFINT_CAL_ADDR ((uint16_t*) (0x1FF800F8U)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#endif + #define VREFINT_CAL_VREF ( 3000U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ /* Temperature sensor */ +#if defined(STM32L151xBA) +#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FF8007AU)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FF8007EU)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#else #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FF800FAU)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FF800FEU)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#endif #define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ #define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ #define TEMPSENSOR_CAL_VREFANALOG ( 3000U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */ From cece48292aaadc876a2499d6cadea0793276532e Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Thu, 3 Oct 2019 17:40:22 +0200 Subject: [PATCH 212/227] pinmap_peripheral: update error code --- hal/mbed_pinmap_common.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hal/mbed_pinmap_common.c b/hal/mbed_pinmap_common.c index 6903dca791d..f47cb1a34c2 100644 --- a/hal/mbed_pinmap_common.c +++ b/hal/mbed_pinmap_common.c @@ -74,7 +74,7 @@ uint32_t pinmap_peripheral(PinName pin, const PinMap *map) } peripheral = pinmap_find_peripheral(pin, map); if ((uint32_t)NC == peripheral) { // no mapping available - MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_PINMAP_INVALID), "pinmap not found for peripheral", peripheral); + MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_PINMAP_INVALID), "pinmap not found for peripheral", pin); } return peripheral; } @@ -99,7 +99,7 @@ uint32_t pinmap_function(PinName pin, const PinMap *map) } function = pinmap_find_function(pin, map); if ((uint32_t)NC == function) { // no mapping available - MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_PINMAP_INVALID), "pinmap not found for function", function); + MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_PINMAP_INVALID), "pinmap not found for function", pin); } return function; } From a0b33ee1a4fb3280f78232769a7bb5c200262fc8 Mon Sep 17 00:00:00 2001 From: Kimmo Vaisanen Date: Thu, 3 Oct 2019 09:27:12 +0300 Subject: [PATCH 213/227] Cellular: Remove old deprecated tests Cellular tests have been replaced with generic mbed-os netsocket and network interface tests. --- TESTS/netsocket/README.md | 61 +++- features/cellular/README.md | 17 +- .../TESTS/api/cellular_device/main.cpp | 221 --------------- .../TESTS/api/cellular_information/main.cpp | 117 -------- .../TESTS/api/cellular_network/main.cpp | 251 ----------------- .../cellular/TESTS/api/cellular_sms/main.cpp | 261 ------------------ .../cellular/TESTS/cellular_tests_common.h | 66 ----- features/cellular/TESTS/socket/udp/main.cpp | 217 --------------- .../socket/udp/template_mbed_app.json.txt | 47 ---- features/cellular/junit_xsl.xslt | 101 ------- features/cellular/xsl_script.sh | 35 --- 11 files changed, 61 insertions(+), 1333 deletions(-) delete mode 100644 features/cellular/TESTS/api/cellular_device/main.cpp delete mode 100644 features/cellular/TESTS/api/cellular_information/main.cpp delete mode 100644 features/cellular/TESTS/api/cellular_network/main.cpp delete mode 100644 features/cellular/TESTS/api/cellular_sms/main.cpp delete mode 100644 features/cellular/TESTS/cellular_tests_common.h delete mode 100644 features/cellular/TESTS/socket/udp/main.cpp delete mode 100644 features/cellular/TESTS/socket/udp/template_mbed_app.json.txt delete mode 100644 features/cellular/junit_xsl.xslt delete mode 100755 features/cellular/xsl_script.sh diff --git a/TESTS/netsocket/README.md b/TESTS/netsocket/README.md index 8cab4dd5134..350ecbfcf7b 100644 --- a/TESTS/netsocket/README.md +++ b/TESTS/netsocket/README.md @@ -386,10 +386,18 @@ Wi-Fi tests require some more configuration, so for Wi-Fi purposes, the `mbed_ap "echo-server-port" : { "help" : "Port of echo server", "value" : "7" - } + }, + "echo-server-discard-port" : { + "help" : "Discard port of echo server", + "value" : "9" + }, "echo-server-port-tls" : { - "help" : "Port of echo server TLS", + "help" : "Port of echo server for TLS", "value" : "2007" + }, + "echo-server-discard-port-tls" : { + "help" : "Discard port of echo server for TLS", + "value" : "2009" } }, "target_overrides": { @@ -403,7 +411,54 @@ Wi-Fi tests require some more configuration, so for Wi-Fi purposes, the `mbed_ap } ``` -Please, see `mbed-os/tools/test_configs` folder for examples. +Cellular tests require some more configuration, so for cellular purposes, the `mbed_app.json` might look like this: +NOTE! These are just typical settings needed for cellular. Actual configuration values depend on used target HW, SIM, modem and network capabilities. + +``` +{ + "config": { + "echo-server-addr" : { + "help" : "IP address of echo server", + "value" : "\"echo.mbedcloudtesting.com\"" + }, + "echo-server-port" : { + "help" : "Port of echo server", + "value" : "7" + }, + "echo-server-discard-port" : { + "help" : "Discard port of echo server", + "value" : "9" + }, + "echo-server-port-tls" : { + "help" : "Port of echo server for TLS", + "value" : "2007" + }, + "echo-server-discard-port-tls" : { + "help" : "Discard port of echo server for TLS", + "value" : "2009" + } + }, + "target_overrides": { + "*": { + "target.network-default-interface-type": "CELLULAR", + "nsapi.default-cellular-sim-pin": "\"SIM PIN if needed\"", + "nsapi.default-cellular-plmn": "\"PLMN if needed\"", + "nsapi.default-cellular-apn": "\"APN if needed\"", + "nsapi.default-cellular-username": "\"SIM USERNAME if needed\"", + "nsapi.default-cellular-password": "\"SIM PASSWORD if needed\"", + "lwip.ipv4-enabled": true, + "lwip.ipv6-enabled": true, + "lwip.tcp-enabled": true, + "lwip.ppp-enabled": true, + "lwip.ethernet-enabled": false, + ".provide-default": true, + "cellular.radio-access-technology": + } + } +} +``` + +Please, see `mbed-os/tools/test_configs` folder for examples for different technologies. Now build the test binaries: diff --git a/features/cellular/README.md b/features/cellular/README.md index 97f1ba0b140..f8bd927eb56 100644 --- a/features/cellular/README.md +++ b/features/cellular/README.md @@ -9,8 +9,6 @@ This is the Github repo for Mbed cellular connectivity: device Implementation of cellular device and state machine targets Vendor specific cellular module adaptations - TESTS Cellular Greentea test - **Note:** Application developers should use only the `API` folder. ## Known limitations @@ -28,6 +26,7 @@ You can change cellular defaults in the `mbed_lib.json` configuration file. ## Debug traces You can define the debug tracing level in the `mbed_app.json` configuration file: + ``` "target_overrides": { "*": { @@ -48,18 +47,8 @@ You can define the debug tracing level in the `mbed_app.json` configuration file ## Greentea tests -The `TESTS` folder contains Greentea tests for cellular specific classes. You need to give relevant configuration file with `--app-config` parameter, such as: - -``` -mbed test -n features-cellular-tests-* --app-config features\cellular\TESTS\socket\udp\template_mbed_app.json.txt -v -``` - -**Note:** Greentea tests use SIM PIN, so you need to change that or your SIM card may get locked. +Cellular connectivity can be tested with generic Mbed OS netsocket and network interface tests found in Mbed OS root `TESTS` directory. For more information, see `TESTS/netsocket/README.md` and `TESTS/network/interface/README.md`. ## Unit tests -Cellular unit tests are in Mbed OS root `UNITTESTS`. Unit tests are based on the stubbing method. - -You need the following applications: `cpputest`, `gcov` and `lcov` (genhtml) for running the tests. - -After you run the `run_tests` script, you can find test results in `UNITTESTS/results`, and line and function coverages in `UNITTESTS/coverages`. +Cellular unit tests are in Mbed OS root `UNITTESTS/features/cellular`. diff --git a/features/cellular/TESTS/api/cellular_device/main.cpp b/features/cellular/TESTS/api/cellular_device/main.cpp deleted file mode 100644 index d471f176136..00000000000 --- a/features/cellular/TESTS/api/cellular_device/main.cpp +++ /dev/null @@ -1,221 +0,0 @@ -/* - * Copyright (c) 2018, Arm Limited and affiliates. - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if !defined(MBED_CONF_NSAPI_PRESENT) || !defined(MBED_CONF_APP_CELLULAR_SIM_PIN) -#error [NOT_SUPPORTED] A json configuration file is needed & SIM pin code is needed. Skipping this build. -#else - - -#include "greentea-client/test_env.h" -#include "unity.h" -#include "utest.h" - -#include "mbed.h" - -#include "CellularLog.h" -#include "CellularDevice.h" -#include "Semaphore.h" -#include "../../cellular_tests_common.h" - -static CellularDevice *device; -static rtos::Semaphore semaphore; - - -const int TIME_OUT_DEVICE_READY = 5 * 60 * 1000; // 5 minutes -const int TIME_OUT_REGISTER = 10 * 60 * 1000; // 10 minutes - -enum CurrentOp { - OP_DEVICE_READY, - OP_SIM_READY, - OP_REGISTER, - OP_ATTACH -}; -static CurrentOp op; - -static void create_device() -{ - device = CellularDevice::get_default_instance(); - TEST_ASSERT(device != NULL); -} - -static void open_close_interfaces() -{ - CellularNetwork *nw = device->open_network(); - TEST_ASSERT(nw != NULL); - device->close_network(); - - CellularInformation *info = device->open_information(); - TEST_ASSERT(info != NULL); - device->close_information(); - - CellularSMS *sms = device->open_sms(); - TEST_ASSERT(sms != NULL); - device->close_sms(); - - CellularContext *ctx = device->create_context(); - TEST_ASSERT(ctx != NULL); - TEST_ASSERT(device->get_context_list() == ctx); - device->delete_context(ctx); -} - -static void other_methods() -{ - // test first without any open interfaces - device->set_timeout(5000); - device->modem_debug_on(true); - device->modem_debug_on(false); - - CellularNetwork *nw = device->open_network(); - TEST_ASSERT(nw != NULL); - - // then test with open interface which is called - device->set_timeout(5000); - device->modem_debug_on(true); - device->modem_debug_on(false); - - TEST_ASSERT(device->get_queue() != NULL); - TEST_ASSERT(device->hard_power_on() == NSAPI_ERROR_OK); - TEST_ASSERT(device->soft_power_on() == NSAPI_ERROR_OK); - wait(10); - TEST_ASSERT_EQUAL_INT(device->init(), NSAPI_ERROR_OK); -} - -static void shutdown() -{ - TEST_ASSERT(device->shutdown() == NSAPI_ERROR_OK); - TEST_ASSERT(device->soft_power_off() == NSAPI_ERROR_OK); - TEST_ASSERT(device->hard_power_off() == NSAPI_ERROR_OK); -} - -static void callback_func(nsapi_event_t ev, intptr_t ptr) -{ - if (ev >= NSAPI_EVENT_CELLULAR_STATUS_BASE && ev <= NSAPI_EVENT_CELLULAR_STATUS_END) { - cell_callback_data_t *ptr_data = (cell_callback_data_t *)ptr; - cellular_connection_status_t cell_ev = (cellular_connection_status_t)ev; - if (cell_ev == CellularDeviceReady && ptr_data->error == NSAPI_ERROR_OK && op == OP_DEVICE_READY) { - TEST_ASSERT_EQUAL_INT(semaphore.release(), osOK); - } else if (cell_ev == CellularSIMStatusChanged && ptr_data->error == NSAPI_ERROR_OK && - ptr_data->status_data == CellularDevice::SimStateReady && op == OP_SIM_READY) { - TEST_ASSERT_EQUAL_INT(semaphore.release(), osOK); - } else if (cell_ev == CellularRegistrationStatusChanged && - (ptr_data->status_data == CellularNetwork::RegisteredHomeNetwork || - ptr_data->status_data == CellularNetwork::RegisteredRoaming || - ptr_data->status_data == CellularNetwork::AlreadyRegistered) && - ptr_data->error == NSAPI_ERROR_OK && - op == OP_REGISTER) { - TEST_ASSERT_EQUAL_INT(semaphore.release(), osOK); - } else if (cell_ev == CellularAttachNetwork && ptr_data->status_data == CellularNetwork::Attached && - ptr_data->error == NSAPI_ERROR_OK && op == OP_ATTACH) { - TEST_ASSERT_EQUAL_INT(semaphore.release(), osOK); - } - } -} - -static void init_to_device_ready_state() -{ - device = CellularDevice::get_default_instance(); - TEST_ASSERT(device != NULL); - -#ifdef MBED_CONF_APP_CELLULAR_SIM_PIN - device->set_sim_pin(MBED_CONF_APP_CELLULAR_SIM_PIN); -#endif -#ifdef MBED_CONF_APP_CELLULAR_PLMN - device->set_plmn(MBED_CONF_APP_CELLULAR_PLMN); -#endif - device->attach(&callback_func); - - op = OP_DEVICE_READY; - TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_OK, device->hard_power_on()); - TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_OK, device->soft_power_on()); - TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_OK, device->init()); - TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_OK, device->set_device_ready()); - - int sema_err = semaphore.wait(TIME_OUT_DEVICE_READY); - TEST_ASSERT_EQUAL_INT(1, sema_err); -} - -static void continue_to_sim_ready_state() -{ - op = OP_SIM_READY; - TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_OK, device->set_sim_ready()); - - int sema_err = semaphore.wait(TIME_OUT_DEVICE_READY); - TEST_ASSERT_EQUAL_INT(1, sema_err); -} - -static void continue_to_register_state() -{ - op = OP_REGISTER; - TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_OK, device->register_to_network()); - - int sema_err = semaphore.wait(TIME_OUT_REGISTER); // cellular network searching may take several minutes - TEST_ASSERT_EQUAL_INT(1, sema_err); -} - -static void continue_to_attach_state() -{ - op = OP_ATTACH; - TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_OK, device->attach_to_network()); - - int sema_err = semaphore.wait(TIME_OUT_REGISTER); // cellular network attach may take several minutes - TEST_ASSERT_EQUAL_INT(1, sema_err); -} - -using namespace utest::v1; - -static utest::v1::status_t greentea_failure_handler(const Case *const source, const failure_t reason) -{ -#if MBED_CONF_MBED_TRACE_ENABLE - trace_close(); -#endif - greentea_case_failure_abort_handler(source, reason); - return STATUS_ABORT; -} - -static Case cases[] = { - Case("CellularDevice create device", create_device, greentea_failure_handler), - Case("CellularDevice Open and close interfaces", open_close_interfaces, greentea_failure_handler), - Case("CellularDevice other methods", other_methods, greentea_failure_handler), - Case("CellularDevice init to device ready", init_to_device_ready_state, greentea_failure_handler), - Case("CellularDevice sim ready", continue_to_sim_ready_state, greentea_failure_handler), - Case("CellularDevice register", continue_to_register_state, greentea_failure_handler), - Case("CellularDevice attach", continue_to_attach_state, greentea_failure_handler), - Case("CellularDevice shutdown", shutdown, greentea_failure_handler), -}; - -static utest::v1::status_t test_setup(const size_t number_of_cases) -{ - GREENTEA_SETUP(10 * 60, "default_auto"); - return verbose_test_setup_handler(number_of_cases); -} - -static Specification specification(test_setup, cases); - -int main() -{ -#if MBED_CONF_MBED_TRACE_ENABLE - trace_open(); -#endif - - int ret = Harness::run(specification); -#if MBED_CONF_MBED_TRACE_ENABLE - trace_close(); -#endif - return ret; -} - -#endif !defined(MBED_CONF_NSAPI_PRESENT) || !defined(MBED_CONF_APP_CELLULAR_SIM_PIN) diff --git a/features/cellular/TESTS/api/cellular_information/main.cpp b/features/cellular/TESTS/api/cellular_information/main.cpp deleted file mode 100644 index 29897823291..00000000000 --- a/features/cellular/TESTS/api/cellular_information/main.cpp +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright (c) 2018, Arm Limited and affiliates. - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - -#if !defined(MBED_CONF_NSAPI_PRESENT) || !defined(MBED_CONF_APP_CELLULAR_SIM_PIN) -#error [NOT_SUPPORTED] A json configuration file is needed & SIM pin code is needed. Skipping this build. -#else - -#include "CellularUtil.h" // for CELLULAR_ helper macros - -#include "greentea-client/test_env.h" -#include "unity.h" -#include "utest.h" - -#include "mbed.h" - - -#include "AT_CellularInformation.h" -#include "CellularContext.h" -#include "CellularDevice.h" -#include "../../cellular_tests_common.h" - -static CellularContext *ctx; - -static void init_to_sim_state() -{ - ctx = CellularContext::get_default_instance(); - TEST_ASSERT(ctx != NULL); - ctx->set_sim_pin(MBED_CONF_APP_CELLULAR_SIM_PIN); -#ifdef MBED_CONF_APP_APN - ctx->set_credentials(MBED_CONF_APP_APN); -#endif - TEST_ASSERT(ctx->set_sim_ready() == NSAPI_ERROR_OK); -} - -static void test_information_interface() -{ - CellularDevice *dev = CellularDevice::get_default_instance(); - - CellularInformation *info = dev->open_information(); - const int kbuf_size = 100; - char *buf = new char[kbuf_size]; - - TEST_ASSERT(info->get_manufacturer(buf, kbuf_size) == NSAPI_ERROR_OK); - TEST_ASSERT(info->get_model(buf, kbuf_size) == NSAPI_ERROR_OK); - TEST_ASSERT(info->get_revision(buf, kbuf_size) == NSAPI_ERROR_OK); - TEST_ASSERT((info->get_serial_number(buf, kbuf_size, CellularInformation::SN) == NSAPI_ERROR_OK) || - ((((AT_CellularInformation *)info)->get_device_error().errType == 3) && // 3 == CME error from the modem - (((AT_CellularInformation *)info)->get_device_error().errCode == 4))); // 4 == "operation not supported" - - nsapi_error_t err = info->get_serial_number(buf, kbuf_size, CellularInformation::IMEI); - TEST_ASSERT(err == NSAPI_ERROR_UNSUPPORTED || err == NSAPI_ERROR_OK); - - err = info->get_serial_number(buf, kbuf_size, CellularInformation::IMEISV); - TEST_ASSERT(err == NSAPI_ERROR_UNSUPPORTED || err == NSAPI_ERROR_OK); - - err = info->get_serial_number(buf, kbuf_size, CellularInformation::SVN); - TEST_ASSERT(err == NSAPI_ERROR_UNSUPPORTED || err == NSAPI_ERROR_OK); - - err = info->get_imsi(buf, kbuf_size); - TEST_ASSERT(err == NSAPI_ERROR_UNSUPPORTED || err == NSAPI_ERROR_OK); - - err = info->get_iccid(buf, kbuf_size); - TEST_ASSERT(err == NSAPI_ERROR_UNSUPPORTED || err == NSAPI_ERROR_OK); - - dev->close_information(); - - delete [] buf; -} - -using namespace utest::v1; - -static utest::v1::status_t greentea_failure_handler(const Case *const source, const failure_t reason) -{ - greentea_case_failure_abort_handler(source, reason); - return STATUS_ABORT; -} - -static Case cases[] = { - Case("CellularInformation init", init_to_sim_state, greentea_failure_handler), - Case("CellularInformation test interface", test_information_interface, greentea_failure_handler) -}; - -static utest::v1::status_t test_setup(const size_t number_of_cases) -{ - GREENTEA_SETUP(10 * 60, "default_auto"); - return verbose_test_setup_handler(number_of_cases); -} - -static Specification specification(test_setup, cases); - -int main() -{ -#if MBED_CONF_MBED_TRACE_ENABLE - trace_open(); -#endif - int ret = Harness::run(specification); -#if MBED_CONF_MBED_TRACE_ENABLE - trace_close(); -#endif - return ret; -} -#endif // !defined(MBED_CONF_NSAPI_PRESENT) || !defined(MBED_CONF_APP_CELLULAR_SIM_PIN) diff --git a/features/cellular/TESTS/api/cellular_network/main.cpp b/features/cellular/TESTS/api/cellular_network/main.cpp deleted file mode 100644 index b21c44c9261..00000000000 --- a/features/cellular/TESTS/api/cellular_network/main.cpp +++ /dev/null @@ -1,251 +0,0 @@ -/* - * Copyright (c) 2018, Arm Limited and affiliates. - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - -#if !defined(MBED_CONF_NSAPI_PRESENT) || !defined(MBED_CONF_APP_CELLULAR_SIM_PIN) -#error [NOT_SUPPORTED] A json configuration file is needed & SIM pin code is needed. Skipping this build. -#else - -#include "greentea-client/test_env.h" -#include "unity.h" -#include "utest.h" - -#include "mbed.h" - -#include "AT_CellularNetwork.h" -#include "CellularContext.h" -#include "CellularDevice.h" -#include "../../cellular_tests_common.h" - -#define NETWORK_TIMEOUT (180*1000) - -static CellularContext *ctx; -static CellularDevice *device; -static CellularNetwork *nw; - -static void init_network_interface() -{ - ctx = CellularContext::get_default_instance(); - TEST_ASSERT(ctx != NULL); - ctx->set_sim_pin(MBED_CONF_APP_CELLULAR_SIM_PIN); -#ifdef MBED_CONF_APP_APN - ctx->set_credentials(MBED_CONF_APP_APN); -#endif - TEST_ASSERT(ctx->register_to_network() == NSAPI_ERROR_OK); - - device = CellularDevice::get_default_instance(); - TEST_ASSERT(device != NULL); -} - -static bool get_network_registration(CellularNetwork::RegistrationType type, - CellularNetwork::RegistrationStatus &status, bool &is_registered) -{ - is_registered = false; - CellularNetwork::registration_params_t reg_params; - nsapi_error_t err = nw->get_registration_params(type, reg_params); - TEST_ASSERT(err == NSAPI_ERROR_OK || err == NSAPI_ERROR_UNSUPPORTED); - - status = reg_params._status; - switch (status) { - case CellularNetwork::RegisteredRoaming: - case CellularNetwork::RegisteredHomeNetwork: - is_registered = true; - break; - case CellularNetwork::RegisteredSMSOnlyRoaming: - case CellularNetwork::RegisteredSMSOnlyHome: - case CellularNetwork::RegisteredCSFBNotPreferredRoaming: - case CellularNetwork::RegisteredCSFBNotPreferredHome: - case CellularNetwork::AttachedEmergencyOnly: - case CellularNetwork::RegistrationDenied: - case CellularNetwork::NotRegistered: - case CellularNetwork::Unknown: - case CellularNetwork::SearchingNetwork: - default: - break; - } - return true; -} - -static bool is_registered() -{ - CellularNetwork::RegistrationStatus status; - bool is_registered = false; - - for (int type = 0; type < CellularNetwork::C_MAX; type++) { - if (get_network_registration((CellularNetwork::RegistrationType) type, status, is_registered)) { - if (is_registered) { - break; - } - } - } - - return is_registered; -} - -static void nw_callback(nsapi_event_t ev, intptr_t intptr) -{ -} - -static void test_network_registration() -{ - device->set_timeout(10 * 1000); - nw = device->open_network(); - TEST_ASSERT(nw != NULL); - - nw->attach(&nw_callback); - - bool success = false; - for (int type = 0; type < CellularNetwork::C_MAX; type++) { - if (!nw->set_registration_urc((CellularNetwork::RegistrationType)type, true)) { - success = true; - } - } - // each modem should support at least one registration type - TEST_ASSERT(success); - - int sanity_count = 0; - while (is_registered() == false) { - if (sanity_count == 0) { - TEST_ASSERT(nw->set_registration() == NSAPI_ERROR_OK); - } - sanity_count++; - wait(2); - TEST_ASSERT(sanity_count < 60); - } - - // device was registered right away, test set_registration call - if (sanity_count == 0) { - TEST_ASSERT(nw->set_registration() == NSAPI_ERROR_OK); - } - - CellularNetwork::NWRegisteringMode reg_mode = CellularNetwork::NWModeDeRegister; - TEST_ASSERT(nw->get_network_registering_mode(reg_mode) == NSAPI_ERROR_OK); - TEST_ASSERT(reg_mode == CellularNetwork::NWModeAutomatic); -} - -static void test_attach() -{ - wait(10); - TEST_ASSERT(nw->set_attach() == NSAPI_ERROR_OK); - - CellularNetwork::AttachStatus status; - TEST_ASSERT(nw->get_attach(status) == NSAPI_ERROR_OK); - TEST_ASSERT(status == CellularNetwork::Attached); -} - -static void test_other() -{ - TEST_ASSERT(nw->get_3gpp_error() == 0); - - nsapi_error_t err = nw->set_access_technology(CellularNetwork::RAT_GSM); - TEST_ASSERT(err == NSAPI_ERROR_OK || err == NSAPI_ERROR_UNSUPPORTED); - - // scanning of operators requires some delay before operation is allowed(seen with WISE_1570) - wait(5); - // scanning of operators might take a long time - device->set_timeout(240 * 1000); - CellularNetwork::operList_t operators; - int uplinkRate = -1; - TEST_ASSERT(nw->scan_plmn(operators, uplinkRate) == NSAPI_ERROR_OK); - device->set_timeout(10 * 1000); - - int rssi = -1; - int ber = -1; - err = nw->get_signal_quality(rssi, &ber); - TEST_ASSERT(err == NSAPI_ERROR_OK || err == NSAPI_ERROR_DEVICE_ERROR); - if (err == NSAPI_ERROR_DEVICE_ERROR) { - TEST_ASSERT((((AT_CellularNetwork *)nw)->get_device_error().errType == 3) && // 3 == CME error from the modem - ((((AT_CellularNetwork *)nw)->get_device_error().errCode == 100) || // 100 == unknown command for modem - (((AT_CellularNetwork *)nw)->get_device_error().errCode == 50))); // 50 == incorrect parameters // seen in wise_1570 for not supported commands - } - - CellularNetwork::registration_params_t reg_params; - reg_params._cell_id = -5; - TEST_ASSERT(nw->get_registration_params(reg_params) == NSAPI_ERROR_OK); - TEST_ASSERT(reg_params._cell_id != -5); - - int format = -1; - CellularNetwork::operator_t operator_params; - // all params are optional so can't test operator_params - err = nw->get_operator_params(format, operator_params); - TEST_ASSERT(err == NSAPI_ERROR_OK); - - nsapi_connection_status_t st = ctx->get_connection_status(); - TEST_ASSERT(st == NSAPI_STATUS_DISCONNECTED); - - // TELIT_HE910 and QUECTEL_BG96 just gives an error and no specific error number so we can't know is this real error or that modem/network does not support the command - CellularNetwork::CIoT_Supported_Opt supported_opt = CellularNetwork::CIOT_OPT_MAX; - CellularNetwork::CIoT_Preferred_UE_Opt preferred_opt = CellularNetwork::PREFERRED_UE_OPT_MAX; - err = nw->get_ciot_ue_optimization_config(supported_opt, preferred_opt); - TEST_ASSERT(err == NSAPI_ERROR_OK || err == NSAPI_ERROR_DEVICE_ERROR); - - err = nw->set_ciot_optimization_config(supported_opt, preferred_opt, NULL); - TEST_ASSERT(err == NSAPI_ERROR_OK || err == NSAPI_ERROR_DEVICE_ERROR); -} - -static void test_detach() -{ - // in PPP mode there is NO CARRIER waiting so flush it out - rtos::ThisThread::sleep_for(6 * 1000); - ((AT_CellularNetwork *)nw)->get_at_handler().flush(); - - nsapi_connection_status_t st = ctx->get_connection_status(); - TEST_ASSERT(st == NSAPI_STATUS_DISCONNECTED); - - TEST_ASSERT(nw->detach() == NSAPI_ERROR_OK); - // wait to process URC's, received after detach - rtos::ThisThread::sleep_for(500); - st = ctx->get_connection_status(); - TEST_ASSERT(st == NSAPI_STATUS_DISCONNECTED); -} - -using namespace utest::v1; - -static utest::v1::status_t greentea_failure_handler(const Case *const source, const failure_t reason) -{ - greentea_case_failure_abort_handler(source, reason); - return STATUS_ABORT; -} - -static Case cases[] = { - Case("CellularNetwork init", init_network_interface, greentea_failure_handler), - Case("CellularNetwork test registering", test_network_registration, greentea_failure_handler), - Case("CellularNetwork test attach", test_attach, greentea_failure_handler), - Case("CellularNetwork test other functions", test_other, greentea_failure_handler), - Case("CellularNetwork test detach", test_detach, greentea_failure_handler) -}; - -static utest::v1::status_t test_setup(const size_t number_of_cases) -{ - GREENTEA_SETUP(10 * 60, "default_auto"); - return verbose_test_setup_handler(number_of_cases); -} - -static Specification specification(test_setup, cases); - -int main() -{ -#if MBED_CONF_MBED_TRACE_ENABLE - trace_open(); -#endif - int ret = Harness::run(specification); -#if MBED_CONF_MBED_TRACE_ENABLE - trace_close(); -#endif - return ret; -} -#endif // !defined(MBED_CONF_NSAPI_PRESENT) || !defined(MBED_CONF_APP_CELLULAR_SIM_PIN) diff --git a/features/cellular/TESTS/api/cellular_sms/main.cpp b/features/cellular/TESTS/api/cellular_sms/main.cpp deleted file mode 100644 index c1e7656c7a5..00000000000 --- a/features/cellular/TESTS/api/cellular_sms/main.cpp +++ /dev/null @@ -1,261 +0,0 @@ -/* - * Copyright (c) 2018, Arm Limited and affiliates. - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - - -#if !defined(MBED_CONF_NSAPI_PRESENT) || !defined(MBED_CONF_APP_CELLULAR_SIM_PIN) -#error [NOT_SUPPORTED] A json configuration file is needed & SIM pin code is needed. Skipping this build. -#else - -#if defined(TARGET_ADV_WISE_1570) || defined(TARGET_MTB_ADV_WISE_1570) -#error [NOT_SUPPORTED] target MTB_ADV_WISE_1570 does not have SMS functionality -#else - -#include "greentea-client/test_env.h" -#include "unity.h" -#include "utest.h" - -#include "mbed.h" - -#include "AT_CellularSMS.h" -#include "CellularContext.h" -#include "CellularDevice.h" -#include "../../cellular_tests_common.h" - -#define NETWORK_TIMEOUT (600*1000) -#define SIM_BUSY 314 - -static CellularContext *ctx; -static CellularDevice *device; -static CellularSMS *sms; -static char service_center_address[SMS_MAX_PHONE_NUMBER_SIZE]; -static int service_address_type; - -static void create_context() -{ - device = CellularDevice::get_default_instance(); - TEST_ASSERT(device != NULL); - device->set_timeout(9000); - ctx = CellularContext::get_default_instance(); - TEST_ASSERT(ctx != NULL); - ctx->set_sim_pin(MBED_CONF_APP_CELLULAR_SIM_PIN); -#ifdef MBED_CONF_APP_APN - ctx->set_credentials(MBED_CONF_APP_APN); -#endif -} - -static void store_service_center_address() -{ - // First we need to go SIM_PIN state to make sure that we can get service address and device ready to accept AT commands - create_context(); - TEST_ASSERT(ctx->set_sim_ready() == NSAPI_ERROR_OK); - - wait(5); // some modems needs more time access sim - - ATHandler *at_init = device->get_at_handler(); - at_init->lock(); - at_init->set_at_timeout(30 * 1000); - at_init->cmd_start("AT+CSCA?"); - at_init->cmd_stop(); - - TEST_ASSERT(at_init->get_last_error() == NSAPI_ERROR_OK); - - at_init->resp_start("+CSCA:"); - at_init->read_string(service_center_address, sizeof(service_center_address)); - service_address_type = at_init->read_int(); - at_init->resp_stop(); - TEST_ASSERT(at_init->get_last_error() == NSAPI_ERROR_OK); - - at_init->unlock(); - device->release_at_handler(at_init); -} - -static void init() -{ - // First store current service address - store_service_center_address(); - create_context(); - - TEST_ASSERT(ctx->register_to_network() == NSAPI_ERROR_OK); - sms = device->open_sms(); - TEST_ASSERT(sms != NULL); - wait(3); // some modems needs more time access sim -} - -static void test_sms_initialize_text_mode() -{ - nsapi_error_t err = sms->initialize(CellularSMS::CellularSMSMmodeText); - TEST_ASSERT(err == NSAPI_ERROR_OK || (err == NSAPI_ERROR_DEVICE_ERROR && - ((AT_CellularSMS *)sms)->get_device_error().errCode == SIM_BUSY)); - -} - -static void test_sms_initialize_pdu_mode() -{ - nsapi_error_t err = sms->initialize(CellularSMS::CellularSMSMmodePDU); - TEST_ASSERT(err == NSAPI_ERROR_OK || err == NSAPI_ERROR_UNSUPPORTED || (err == NSAPI_ERROR_DEVICE_ERROR && - ((AT_CellularSMS *)sms)->get_device_error().errCode == SIM_BUSY)); -} - -static void test_set_cscs() -{ - nsapi_error_t err = sms->set_cscs("IRA"); - TEST_ASSERT(err == NSAPI_ERROR_OK || err == NSAPI_ERROR_UNSUPPORTED || (err == NSAPI_ERROR_DEVICE_ERROR && - ((AT_CellularSMS *)sms)->get_device_error().errCode == SIM_BUSY)); - err = sms->set_cscs("UCS2"); - TEST_ASSERT(err == NSAPI_ERROR_OK || err == NSAPI_ERROR_UNSUPPORTED || (err == NSAPI_ERROR_DEVICE_ERROR && - ((AT_CellularSMS *)sms)->get_device_error().errCode == SIM_BUSY)); - err = sms->set_cscs("GSM"); - TEST_ASSERT(err == NSAPI_ERROR_OK || err == NSAPI_ERROR_UNSUPPORTED || (err == NSAPI_ERROR_DEVICE_ERROR && - ((AT_CellularSMS *)sms)->get_device_error().errCode == SIM_BUSY)); -} - -static void test_set_csca() -{ - nsapi_error_t err = sms->set_csca("55555", 129); - TEST_ASSERT(err == NSAPI_ERROR_OK || (err == NSAPI_ERROR_DEVICE_ERROR && - ((AT_CellularSMS *)sms)->get_device_error().errCode == SIM_BUSY)); - err = sms->set_csca("+35855555", 145); - TEST_ASSERT(err == NSAPI_ERROR_OK || (err == NSAPI_ERROR_DEVICE_ERROR && - ((AT_CellularSMS *)sms)->get_device_error().errCode == SIM_BUSY)); - err = sms->set_csca(service_center_address, service_address_type); - TEST_ASSERT(err == NSAPI_ERROR_OK || (err == NSAPI_ERROR_DEVICE_ERROR && - ((AT_CellularSMS *)sms)->get_device_error().errCode == SIM_BUSY)); -} - -static void test_set_cpms_me() -{ - nsapi_error_t err = sms->set_cpms("ME", "ME", "ME"); - TEST_ASSERT(err == NSAPI_ERROR_OK || err == NSAPI_ERROR_UNSUPPORTED || (err == NSAPI_ERROR_DEVICE_ERROR && - ((AT_CellularSMS *)sms)->get_device_error().errCode == SIM_BUSY)); -} - -#ifdef MBED_CONF_APP_CELLULAR_PHONE_NUMBER -static const char TEST_MESSAGE[] = "abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ"; -static int callbacks_received = 0; - -static void sms_callback() -{ - callbacks_received++; -} - -static void test_set_sms_callback() -{ - sms->set_sms_callback(sms_callback); -} - - -static void test_set_cpms_sm() -{ - TEST_ASSERT(sms->set_cpms("SM", "SM", "SM") == NSAPI_ERROR_OK); -} - -static void test_sms_send() -{ - const int msg_len = strlen(TEST_MESSAGE); - TEST_ASSERT(sms->send_sms(MBED_CONF_APP_CELLULAR_PHONE_NUMBER, TEST_MESSAGE, msg_len) == msg_len); -} - -static void test_get_sms() -{ - uint16_t buf_len = sizeof(TEST_MESSAGE); - char buf[buf_len]; - - char phone_num[SMS_MAX_PHONE_NUMBER_SIZE]; - - char time_stamp[SMS_MAX_TIME_STAMP_SIZE]; - - int buf_size = 0; - - wait(7); - - TEST_ASSERT(sms->get_sms(buf, buf_len, phone_num, SMS_MAX_PHONE_NUMBER_SIZE, time_stamp, SMS_MAX_TIME_STAMP_SIZE, &buf_size) == buf_len - 1); - TEST_ASSERT(strcmp(phone_num, MBED_CONF_APP_CELLULAR_PHONE_NUMBER) == 0); - TEST_ASSERT(strcmp(buf, TEST_MESSAGE) == 0); - TEST_ASSERT(buf_size == 0); - TEST_ASSERT(callbacks_received > 0); - callbacks_received = 0; - -} - -static void test_delete_all_messages() -{ - //send a message so that there is something to delete - test_sms_send(); - wait(7); - TEST_ASSERT(sms->delete_all_messages() == NSAPI_ERROR_OK); - callbacks_received = 0; -} - -static void test_set_extra_sim_wait_time_1000() -{ - sms->set_extra_sim_wait_time(1000); -} - -#endif - -using namespace utest::v1; - -static utest::v1::status_t greentea_failure_handler(const Case *const source, const failure_t reason) -{ - greentea_case_failure_abort_handler(source, reason); - return STATUS_ABORT; -} - -static Case cases[] = { - Case("CellularSMS init", init, greentea_failure_handler), - Case("CellularSMS test ME for storage", test_set_cpms_me, greentea_failure_handler), - Case("CellularSMS test initialize to PDU mode", test_sms_initialize_pdu_mode, greentea_failure_handler), - Case("CellularSMS test character sets", test_set_cscs, greentea_failure_handler), - Case("CellularSMS test service center address", test_set_csca, greentea_failure_handler) -#ifdef MBED_CONF_APP_CELLULAR_PHONE_NUMBER - , - Case("CellularSMS test delete all messages", test_delete_all_messages, greentea_failure_handler), - Case("CellularSMS test sms callback", test_set_sms_callback, greentea_failure_handler), - Case("CellularSMS test sms send", test_sms_send, greentea_failure_handler), - Case("CellularSMS test get sms", test_get_sms, greentea_failure_handler), - Case("CellularSMS test set sim wait time 1s", test_set_extra_sim_wait_time_1000, greentea_failure_handler), - Case("CellularSMS test SM for storage", test_set_cpms_sm, greentea_failure_handler), - Case("CellularSMS test initialize to text mode", test_sms_initialize_text_mode, greentea_failure_handler), - Case("CellularSMS test delete all messages", test_delete_all_messages, greentea_failure_handler), - Case("CellularSMS test sms send", test_sms_send, greentea_failure_handler), - Case("CellularSMS test get sms", test_get_sms, greentea_failure_handler), - Case("CellularSMS test delete all messages", test_delete_all_messages, greentea_failure_handler) -#endif -}; - -static utest::v1::status_t test_setup(const size_t number_of_cases) -{ - GREENTEA_SETUP(600, "default_auto"); - return verbose_test_setup_handler(number_of_cases); -} - -static Specification specification(test_setup, cases); - -int main() -{ -#if MBED_CONF_MBED_TRACE_ENABLE - trace_open(); -#endif - int ret = Harness::run(specification); -#if MBED_CONF_MBED_TRACE_ENABLE - trace_close(); -#endif - return ret; -} - -#endif //defined(TARGET_ADV_WISE_1570) || defined(TARGET_MTB_ADV_WISE_1570) -#endif // !defined(MBED_CONF_NSAPI_PRESENT) || !defined(MBED_CONF_APP_CELLULAR_SIM_PIN) diff --git a/features/cellular/TESTS/cellular_tests_common.h b/features/cellular/TESTS/cellular_tests_common.h deleted file mode 100644 index 0303552412f..00000000000 --- a/features/cellular/TESTS/cellular_tests_common.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) 2018, Arm Limited and affiliates. - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef CELLULAR_TESTS_COMMON_H_ -#define CELLULAR_TESTS_COMMON_H_ - -#include "CellularLog.h" - -#if MBED_CONF_MBED_TRACE_ENABLE - -static rtos::Mutex trace_mutex; - -void trace_wait() -{ - trace_mutex.lock(); -} - -void trace_release() -{ - trace_mutex.unlock(); -} - -static char time_st[sizeof("[12345678]") + 1]; - -static char *trace_time(size_t ss) -{ - snprintf(time_st, sizeof("[12345678]"), "[%08llu]", rtos::Kernel::get_ms_count()); - return time_st; -} - -static void trace_open() -{ - mbed_trace_init(); - mbed_trace_prefix_function_set(&trace_time); - mbed_trace_mutex_wait_function_set(trace_wait); - mbed_trace_mutex_release_function_set(trace_release); - - mbed_cellular_trace::mutex_wait_function_set(trace_wait); - mbed_cellular_trace::mutex_release_function_set(trace_release); -} - -static void trace_close() -{ - mbed_cellular_trace::mutex_wait_function_set(NULL); - mbed_cellular_trace::mutex_release_function_set(NULL); - - mbed_trace_free(); -} - -#endif // MBED_CONF_MBED_TRACE_ENABLE - - -#endif /* CELLULAR_TESTS_COMMON_H_ */ diff --git a/features/cellular/TESTS/socket/udp/main.cpp b/features/cellular/TESTS/socket/udp/main.cpp deleted file mode 100644 index 3efd3814cd8..00000000000 --- a/features/cellular/TESTS/socket/udp/main.cpp +++ /dev/null @@ -1,217 +0,0 @@ -/* - * Copyright (c) 2018, Arm Limited and affiliates. - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if !defined(MBED_CONF_NSAPI_PRESENT) || !defined(MBED_CONF_APP_CELLULAR_SIM_PIN) -#error [NOT_SUPPORTED] A json configuration file is needed & SIM pin code is needed. Skipping this build. -#else - -#include "CellularUtil.h" // for CELLULAR_ helper macros - -#include "greentea-client/test_env.h" -#include "unity.h" -#include "utest.h" - -#include "mbed.h" - -#include "CellularContext.h" - -#if MBED_CONF_CELLULAR_USE_APN_LOOKUP || MBED_CONF_PPP_CELL_IFACE_APN_LOOKUP -#include "APN_db.h" -#endif //MBED_CONF_CELLULAR_USE_APN_LOOKUP || MBED_CONF_PPP_CELL_IFACE_APN_LOOKUP - -#include "../../cellular_tests_common.h" - -#define NETWORK_TIMEOUT (180*1000) -#define SOCKET_TIMEOUT (30*1000) - -#define ECHO_SERVER_NAME "echo.mbedcloudtesting.com" -#define ECHO_SERVER_UDP_PORT 8877 - -static CellularContext *ctx; -static SocketAddress echo_server_addr; -static rtos::EventFlags eventFlags; - -class EchoSocket : public UDPSocket { -public: - EchoSocket(int size) : UDPSocket(), _data(0), _size(size), _async_flag(0), _tx_pending(false), _rx_pending(false) - { - } - virtual ~EchoSocket() - { - delete _data; - } - void set_async(int async) - { - _async_flag = async; - if (_async_flag) { - set_blocking(false); - sigio(callback(this, &EchoSocket::async_callback)); - } - } - - void test_sendto(const char *const hostname = NULL) - { - if (!_data) { - _data = new uint8_t[_size]; - for (int i = 0; i < _size; i++) { - _data[i] = (uint8_t)rand(); - } - } - nsapi_size_or_error_t ret; - if (hostname) { - ret = sendto(hostname, ECHO_SERVER_UDP_PORT, _data, _size); - } else { - ret = sendto(echo_server_addr, _data, _size); - } - if (ret == _size) { // send successful - _tx_pending = false; - } else { - TEST_ASSERT(_async_flag && ret == NSAPI_ERROR_WOULD_BLOCK); - _tx_pending = true; - } - } - - void test_recvfrom() - { - uint8_t *buf = new uint8_t[_size]; - memset(buf, 0, _size); - SocketAddress recv_address; - nsapi_size_or_error_t ret = recvfrom(&recv_address, buf, _size); - if (ret == _size) { // recv successful - _rx_pending = false; - TEST_ASSERT(recv_address == echo_server_addr); - TEST_ASSERT(memcmp(_data, buf, _size) == 0); - delete _data; - _data = NULL; - _rx_pending = false; - } else { - TEST_ASSERT(_async_flag && ret == NSAPI_ERROR_WOULD_BLOCK); - _rx_pending = true; - } - delete buf; - } - - bool async_process() - { - if (_tx_pending) { - test_sendto(); - } - if (_rx_pending) { - test_recvfrom(); - } - return _tx_pending | _rx_pending; - } - -private: - void async_callback() - { - eventFlags.set(_async_flag); - } - uint8_t *_data; - int _size; - uint32_t _async_flag; // 0 for blocking socket, signal bit for async - bool _tx_pending; - bool _rx_pending; -}; - -static void udp_network_stack() -{ - ctx = CellularContext::get_default_instance(); - TEST_ASSERT(ctx != NULL); - ctx->set_sim_pin(MBED_CONF_APP_CELLULAR_SIM_PIN); -#ifdef MBED_CONF_APP_APN - ctx->set_credentials(MBED_CONF_APP_APN, MBED_CONF_APP_USERNAME, MBED_CONF_APP_PASSWORD); -#endif - TEST_ASSERT(ctx->connect() == NSAPI_ERROR_OK); -} - -static void udp_gethostbyname() -{ - TEST_ASSERT(ctx->gethostbyname(ECHO_SERVER_NAME, &echo_server_addr) == 0); - tr_info("Echo server IP: %s", echo_server_addr.get_ip_address()); - echo_server_addr.set_port(7); -} - -static void udp_socket_send_receive() -{ - EchoSocket echo_socket(4); - TEST_ASSERT(echo_socket.open(ctx) == NSAPI_ERROR_OK); - echo_socket.set_blocking(true); - echo_socket.set_timeout(SOCKET_TIMEOUT); - echo_socket.test_sendto(); - echo_socket.test_recvfrom(); - TEST_ASSERT(echo_socket.close() == NSAPI_ERROR_OK); -} - -static void udp_socket_send_receive_async() -{ - int async_flag = 1; - TEST_ASSERT(!(eventFlags.clear(async_flag) & osFlagsError)); - - EchoSocket echo_socket(4); - TEST_ASSERT(echo_socket.open(ctx) == NSAPI_ERROR_OK); - echo_socket.set_async(async_flag); - echo_socket.test_sendto(); - echo_socket.test_recvfrom(); - - while (true) { - TEST_ASSERT((eventFlags.wait_any(async_flag, SOCKET_TIMEOUT) & (osFlagsError)) != osFlagsError); - if (!echo_socket.async_process()) { - break; - } - } - TEST_ASSERT(echo_socket.close() == NSAPI_ERROR_OK); -} - -using namespace utest::v1; - -static utest::v1::status_t greentea_failure_handler(const Case *const source, const failure_t reason) -{ -#if MBED_CONF_MBED_TRACE_ENABLE - trace_close(); -#endif - greentea_case_failure_abort_handler(source, reason); - return STATUS_ABORT; -} - -static Case cases[] = { - Case("UDP network stack", udp_network_stack, greentea_failure_handler), - Case("UDP gethostbyname", udp_gethostbyname, greentea_failure_handler), - Case("UDP socket send/receive", udp_socket_send_receive, greentea_failure_handler), - Case("UDP socket send/receive async", udp_socket_send_receive_async, greentea_failure_handler), -}; - -static utest::v1::status_t test_setup(const size_t number_of_cases) -{ - GREENTEA_SETUP(10 * 60, "default_auto"); // network registration may take up to 180 seconds, DNS query a couple of minutes, etc. - return verbose_test_setup_handler(number_of_cases); -} - -static Specification specification(test_setup, cases); - -int main() -{ -#if MBED_CONF_MBED_TRACE_ENABLE - trace_open(); -#endif - int ret = Harness::run(specification); -#if MBED_CONF_MBED_TRACE_ENABLE - trace_close(); -#endif - return ret; -} -#endif // !defined(MBED_CONF_NSAPI_PRESENT) || !defined(MBED_CONF_APP_CELLULAR_SIM_PIN) diff --git a/features/cellular/TESTS/socket/udp/template_mbed_app.json.txt b/features/cellular/TESTS/socket/udp/template_mbed_app.json.txt deleted file mode 100644 index 983fd68dd97..00000000000 --- a/features/cellular/TESTS/socket/udp/template_mbed_app.json.txt +++ /dev/null @@ -1,47 +0,0 @@ -{ - "config": { - "cellular_sim_pin": { - "help": "PIN code", - "value": "\"1234\"" - }, - "cellular_plmn": { - "help": "plmn to select manual registration", - "value": 0 - }, - "apn": { - "help": "The APN string to use for this SIM/network, set to 0 if none", - "value": 0 - }, - "username": { - "help": "The user name string to use for this APN, set to zero if none", - "value": 0 - }, - "password": { - "help": "The password string to use for this APN, set to 0 if none", - "value": 0 - }, - "trace-level": { - "help": "Note that excessive trace prints may mess up with Greentea parsing", - "macro_name": "MBED_TRACE_MAX_LEVEL", - "value": "TRACE_LEVEL_ERROR" - } - }, - "target_overrides": { - "*": { - "nsapi.dns-response-wait-time": 30000, - "ppp-cell-iface.apn-lookup": false, - "cellular.use-apn-lookup": false, - "mbed-trace.enable": false, - "lwip.ipv4-enabled": true, - "lwip.ipv6-enabled": true, - "lwip.tcp-enabled": false, - "lwip.ppp-enabled": true, - "lwip.ethernet-enabled": false, - "platform.stdio-convert-newlines": true, - "platform.default-serial-baud-rate": 115200, - "drivers.uart-serial-txbuf-size": 512, - "drivers.uart-serial-rxbuf-size": 1024, - "cellular.debug-at": false - } - } -} diff --git a/features/cellular/junit_xsl.xslt b/features/cellular/junit_xsl.xslt deleted file mode 100644 index 7376b27f268..00000000000 --- a/features/cellular/junit_xsl.xslt +++ /dev/null @@ -1,101 +0,0 @@ - - - - - - - - - -

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