isa: add ALU64 and GF instructions

src/isa/alu64/bytecode.rs

@@ -24,7 +24,7 @@
 
 use core::ops::RangeInclusive;
 
-use super::{ArithmInstr, CtrlInstr, RegInstr};
+use super::{CtrlInstr, FieldInstr, RegInstr};
 use crate::isa::bytecode::CodeEofError;
 use crate::isa::{Bytecode, BytecodeRead, BytecodeWrite, Instr, InstructionSet, ReservedInstr};
 
@@ -104,7 +104,7 @@ impl<Id> Bytecode<Id> for RegInstr {
     }
 }
 
-impl<Id> Bytecode<Id> for ArithmInstr {
+impl<Id> Bytecode<Id> for FieldInstr {
     fn op_range() -> RangeInclusive<u8> { todo!() }
 
     fn opcode_byte(&self) -> u8 { todo!() }

src/isa/alu64/exec.rs

@@ -24,7 +24,7 @@
 
 use std::collections::BTreeSet;
 
-use super::{ArithmInstr, CtrlInstr, RegInstr};
+use super::{CtrlInstr, FieldInstr, RegInstr};
 use crate::core::{AluCore, Reg, Site};
 use crate::isa::{ExecStep, Instr, Instruction, InstructionSet, ReservedInstr};
 
@@ -92,7 +92,7 @@ impl Instruction for RegInstr {
     }
 }
 
-impl Instruction for ArithmInstr {
+impl Instruction for FieldInstr {
     type Context<'ctx> = ();
 
     fn src_regs(&self) -> BTreeSet<Reg> { todo!() }

src/isa/alu64/instr.rs

@@ -22,23 +22,152 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
+use amplify::num::u2;
+
+use crate::core::IdxA;
+use crate::regs::{RegA, A};
+
 /// Control flow instructions.
 #[derive(Clone, PartialEq, Eq, Hash, Debug, Display)]
 #[display(inner)]
 pub enum CtrlInstr {
-    Placeholder,
+    /// Not an operation.
+    Nop,
+
+    /// Test ck value, terminates if in failed state.
+    Chk,
+
+    /// Invert `ct` register.
+    NotCk,
+
+    /// Set `ck` register to a failed state.
+    Fail,
+
+    /// Reset `ck` register.
+    Rset,
+
+    /// Jump to location (unconditionally).
+    Jmp,
+
+    /// Jump to location if `ct` is true.
+    Jif,
+
+    /// Jump to location if `ck` is in a failed state.
+    JiFail,
+
+    /// Relative jump.
+    Sh,
+
+    /// Relative jump if `ct` is true.
+    ShIf,
+
+    /// Relative jump if `ck` is in a failed state.
+    ShIfail,
+
+    /// External jump.
+    Exec,
+
+    /// Subroutine call.
+    Fn,
+
+    /// External subroutine call.
+    Call,
+
+    /// Return from a subroutine or finish program.
+    Ret,
+
+    /// Stop the program.
+    Stop,
 }
 
 /// Register manipulation instructions.
 #[derive(Clone, PartialEq, Eq, Hash, Debug, Display)]
 #[display(inner)]
 pub enum RegInstr {
-    Placeholder,
+    /// Clear register (sets to an undefined state).
+    Clr { dst: A },
+
+    /// Put a constant value to a register,
+    Put { dst: A, val: u64 },
+
+    /// Put a constant value to a register if it doesn't contain data,
+    Pif { dst: A, val: u64 },
+
+    /// Test whether a register is set.
+    Test { src: A },
+
+    /// Copy source to destination.
+    ///
+    /// If `src` and `dst` have a different bit dimension, the value is extended with zeros (as
+    /// unsigned little-endian integer).
+    Cpy { dst: A, src: A },
+
+    /// Swap values of two registers.
+    ///
+    /// If the registers have a different bit dimension, the value of the smaller-sized register is
+    /// extended with zeros (as unsigned little-endian integer) and the value of larger-sized
+    /// register is divided by the modulo (the most significant bits get dropped).
+    Swp { src_dst1: A, src_dst2: A },
+
+    /// Check whether value of two registers is equal.
+    ///
+    /// If the registers have a different bit dimension, performs unsigned integer comparison using
+    /// little-endian encoding.
+    Eq { src1: A, src2: A },
 }
 
-/// Arithmetic instructions for natural numbers.
+/// Arithmetic instructions for finite fields.
 #[derive(Clone, PartialEq, Eq, Hash, Debug, Display)]
 #[display(inner)]
-pub enum ArithmInstr {
-    Placeholder,
+#[non_exhaustive]
+pub enum FieldInstr {
+    /// Increment register value using finite-field (modulo) arithmetics of the `order`.
+    IncMod {
+        /// Destination register.
+        dst: RegA,
+        /// Value to add.
+        val: u2,
+        /// Order of the finite field.
+        // 2-bit smaller than complete no of bytes.
+        order: u64,
+    },
+
+    /// Decrement register value using finite-field (modulo) arithmetics of the `order`.
+    DecMod {
+        /// Destination register.
+        dst: RegA,
+        /// Value to add.
+        val: u2,
+        /// Order of the finite field.
+        // 2-bit smaller than complete no of bytes.
+        order: u64,
+    },
+
+    /// Add `src` value to `src_dst` value using finite-field (modulo) arithmetics of the `order`.
+    AddMod {
+        src_dst: RegA,
+        src: IdxA,
+        /// Order of the finite field.
+        // 2-bit smaller than complete no of bytes.
+        order: u64,
+    },
+
+    /// Negate value using finite-field arithmetics.
+    NegMod {
+        dst: RegA,
+        src: IdxA,
+        /// Order of the finite field.
+        // 2-bit smaller than complete no of bytes.
+        order: u64,
+    },
+
+    /// Multiply `src` value to `src_dst` value using finite-field (modulo) arithmetics of the
+    /// `order`.
+    MulMod {
+        src_dst: RegA,
+        src: IdxA,
+        /// Order of the finite field.
+        // 2-bit smaller than complete no of bytes.
+        order: u64,
+    },
 }

src/isa/alu64/mod.rs

@@ -28,4 +28,4 @@ mod bytecode;
 mod instr;
 mod exec;
 
-pub use instr::{ArithmInstr, CtrlInstr, RegInstr};
+pub use instr::{CtrlInstr, FieldInstr, RegInstr};

src/isa/arch.rs

@@ -28,7 +28,7 @@ use amplify::confinement::TinyOrdSet;
 use strict_encoding::stl::AlphaCapsNum;
 use strict_encoding::RString;
 
-use super::{ArithmInstr, CtrlInstr, Instruction, RegInstr};
+use super::{CtrlInstr, FieldInstr, Instruction, RegInstr};
 use crate::stl::LIB_NAME_ALUVM;
 
 pub const ISA_ID_MAX_LEN: usize = 16;
@@ -95,7 +95,7 @@ pub enum Instr<Ext: InstructionSet = ReservedInstr> {
     Reg(RegInstr),
 
     /// Arithmetic instructions for natural numbers.
-    An(ArithmInstr),
+    An(FieldInstr),
 
     // #[cfg(feature = "str")]
     // Str(array::instr::StrInstr),

src/isa/mod.rs

@@ -29,7 +29,7 @@ mod alu64;
 mod bytecode;
 mod arch;
 
-pub use alu64::{ArithmInstr, CtrlInstr, RegInstr};
+pub use alu64::{CtrlInstr, FieldInstr, RegInstr};
 pub use arch::{Instr, InstructionSet, IsaId, ReservedInstr, ISA_ALU64, ISA_AN, ISA_ID_MAX_LEN};
 pub use bytecode::{Bytecode, BytecodeRead, BytecodeWrite, CodeEofError};
 pub use instr::{ExecStep, Instruction};