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Hello! Nice work on your project and i'm interested in recreating your work for a student club! I'm new to FPGA and currently using a Xilinx Artix-7 FPGA (Nexys 4 ddr) with Vivado. May I know if i should include all the verilog files from your src1 and src2 folders into VIvado? Could you provide a step-by-step guide on how you implemented this on your fpga? And how did you connect your camera module? Thanks so much!
The text was updated successfully, but these errors were encountered:
Hello! Nice work on your project and i'm interested in recreating your work for a student club! I'm new to FPGA and currently using a Xilinx Artix-7 FPGA (Nexys 4 ddr) with Vivado. May I know if i should include all the verilog files from your src1 and src2 folders into VIvado? Could you provide a step-by-step guide on how you implemented this on your fpga? And how did you connect your camera module? Thanks so much!
The text was updated successfully, but these errors were encountered: