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CMakeLists.txt
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CMakeLists.txt
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cmake_minimum_required(VERSION 3.4.3 FATAL_ERROR)
project(STINCILLA CXX)
enable_testing()
find_package(AnyDSL_runtime REQUIRED)
include_directories(${AnyDSL_runtime_INCLUDE_DIRS})
set(BACKEND ${BACKEND} CACHE STRING "select the backend from the following: CPU, AVX, NVVM, CUDA, OPENCL, AMDGPU, HLS")
if(NOT BACKEND)
set(BACKEND opencl CACHE STRING "select the backend from the following: CPU, AVX, NVVM, CUDA, OPENCL, AMDGPU, HLS" FORCE)
endif()
string(TOLOWER "${BACKEND}" BACKEND)
message(STATUS "Selected backend: ${BACKEND}")
if (BACKEND STREQUAL "opencl")
if(NOT PARALLEL)
set(PARALLEL "task" CACHE STRING "Parallelisation on, data , task" FORCE)
endif()
message(STATUS "Parallelism method: ${PARALLEL}")
else()
unset(PARALLEL CACHE)
endif()
set(PIXEL_TYPE ${PIXEL_TYPE} CACHE STRING "select the pixel type from the following: f32, i32, u8")
if(NOT PIXEL_TYPE)
set(PIXEL_TYPE i32 CACHE STRING "select the pixel type from the following: f32, i32, u8" FORCE)
endif()
string(TOLOWER "${PIXEL_TYPE}" PIXEL_TYPE)
message(STATUS "Selected pixel type: ${PIXEL_TYPE}")
if(PIXEL_TYPE STREQUAL "i32")
set(STINCILLA_DATA_TYPE int)
elseif(PIXEL_TYPE STREQUAL "u8")
set(STINCILLA_DATA_TYPE uchar)
else()
set(STINCILLA_DATA_TYPE float)
endif()
if(BACKEND STREQUAL "hls")
set(SYNTHESIS ON CACHE BOOL "ON: Synthesis and HDL generation (also required for HW emulation), OFF: C simulation")
string(TOLOWER "${SYNTHESIS}" SYNTHESIS)
message(STATUS "HW Synthesis: ${SYNTHESIS}")
set(FPGA_PART xc7z020clg484-1 CACHE STRING "Specify FPGA part or Board model: U50, U200, U250, U280")
string(TOLOWER "${FPGA_PART}" FPGA_PART)
message(STATUS "Selected FPGA: ${FPGA_PART}")
set(GMEM_BANKS_OPT OFF CACHE BOOL "FPGA memory bank optimization")
message(STATUS "FPGA memory bank optimization: ${GMEM_BANKS_OPT}")
set(ANYDSL_FPGA "HPC" CACHE STRING "None, HPC, SOC, HPC_STREAM,BENCHMAR, GMEM_OPT")
message(STATUS "Application configurations: ${ANYDSL_FPGA}")
set(SOC OFF CACHE BOOL "ON: SoC IP generation, OFF: IP generation / HPC accelerator integration")
string(TOLOWER "${SOC}" SOC)
message(STATUS "SoC integration: ${SOC}")
if(NOT SOC AND SYNTHESIS)
set(HW_EMULATION OFF CACHE BOOL "ON: Hardware emulation, OFF: Hardware generation")
set(PROFILER OFF CACHE BOOL " Runtime profiling and generating waveforms for hardware signals")
if(HW_EMULATION)
set(ENV{XCL_EMULATION_MODE} "hw_emu")
message(STATUS "Hardware will be generated for emulation")
else()
set(ENV{XCL_EMULATION_MODE} "hw")
message(STATUS "FPGA bitstream will be generated")
endif()
if (PROFILER)
message(STATUS "Profiler is enabled, performance might be affected.")
endif()
else()
set(HW_EMULATION OFF INTERNAL)
endif()
else()
unset(SYNTHESIS CACHE)
unset(FPGA_PART CACHE)
unset(SOC CACHE)
unset(ANYDSL_FPGA CACHE)
unset(PROFILER CACHE)
unset(HW_EMULATION CACHE)
unset(GMEM_BANKS_OPT CACHE)
endif()
set(BACKEND_FILE ${CMAKE_CURRENT_SOURCE_DIR}/src/backend_${BACKEND}.impala)
set(PIXEL_TYPE_FILE ${CMAKE_CURRENT_SOURCE_DIR}/src/pixel_${PIXEL_TYPE}.impala)
set(PIXEL_U8_FILE ${CMAKE_CURRENT_SOURCE_DIR}/src/pixel_u8.impala)
set(PIXEL_I32_FILE ${CMAKE_CURRENT_SOURCE_DIR}/src/pixel_i32.impala)
set(PIXEL_F32_FILE ${CMAKE_CURRENT_SOURCE_DIR}/src/pixel_f32.impala)
set(CONFIG_FILES ${BACKEND_FILE} ${PIXEL_TYPE_FILE})
set(CLANG_FLAGS -march=native)
set(IMPALA_FLAGS --log-level info)
set(ANYDSL_RUNTIME_LIBRARIES ${AnyDSL_runtime_LIBRARIES})
set(HLS_FLAGS ${SOC} ${SYNTHESIS} ${FPGA_PART} ${PROFILER} ${HW_EMULATION} ${GMEM_BANKS_OPT})
if(BACKEND STREQUAL "cpu" OR BACKEND STREQUAL "avx")
set(DEVICE "cpu")
set(MAPPING_FILES ${CMAKE_CURRENT_SOURCE_DIR}/src/mapping_${DEVICE}.impala)
elseif(BACKEND STREQUAL "opencl" AND PARALLEL STREQUAL "task" OR BACKEND STREQUAL "hls")
set(DEVICE "fpga")
if(NOT ANYDSL_FPGA)
set(ANYDSL_FPGA "HPC" CACHE STRING "")
endif()
set(IMPALA_FLAGS --log-level info --hls-flags ${ANYDSL_FPGA})
if(BACKEND STREQUAL "hls")
set(MAPPING_FILES ${CMAKE_CURRENT_SOURCE_DIR}/src/mapping_${DEVICE}.impala ${CMAKE_CURRENT_SOURCE_DIR}/src/mapping_fpga_img_hls.impala)
else()
# Task-based (single-workitem) OpenCL for FPGA
set(MAPPING_FILES ${CMAKE_CURRENT_SOURCE_DIR}/src/mapping_${DEVICE}.impala ${CMAKE_CURRENT_SOURCE_DIR}/src/mapping_fpga_img_opencl.impala)
endif()
else()
# data-parallel OpenCL(CPU, GPU, FPGA) and cuda
set(DEVICE "acc")
set(MAPPING_FILES ${CMAKE_CURRENT_SOURCE_DIR}/src/mapping_${DEVICE}.impala)
endif()
set(STINCILLA_COMMON_INCLUDE_DIRS ${CMAKE_CURRENT_SOURCE_DIR}/src/common/pnm_image)
include_directories(${STINCILLA_COMMON_INCLUDE_DIRS})
add_subdirectory(test)
add_subdirectory(apps)
set(DSL_TYPE_FILES utils.impala stencil_lib.impala stencil_lib_img_proc.impala)