-
Notifications
You must be signed in to change notification settings - Fork 5
/
APT-KRIA-FMC.pro
319 lines (319 loc) · 4.96 KB
/
APT-KRIA-FMC.pro
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
update=12/26/2022 1:31:56 PM
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=16
BoardThickness=1.6
AllowMicroVias=1
AllowBlindVias=1
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.08127999999999999
MinViaDiameter=0.25
MinViaDrill=0.127
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.25
TrackWidth2=0.09398
TrackWidth3=0.1016
TrackWidth4=0.10795
TrackWidth5=0.127
TrackWidth6=0.13208
TrackWidth7=0.1397
TrackWidth8=0.1524
TrackWidth9=0.2032
TrackWidth10=0.254
TrackWidth11=0.3048
TrackWidth12=0.3175
TrackWidth13=0.4064
TrackWidth14=0.5
TrackWidth15=0.508
TrackWidth16=0.5588
TrackWidth17=0.635
TrackWidth18=1.016
ViaDiameter1=0.8
ViaDrill1=0.4
ViaDiameter2=0.4
ViaDrill2=0.2
ViaDiameter3=0.5
ViaDrill3=0.25
ViaDiameter4=0.55
ViaDrill4=0.3
ViaDiameter5=0.6096
ViaDrill5=0.3048
ViaDiameter6=0.65
ViaDrill6=0.25
ViaDiameter7=0.8
ViaDrill7=0.4
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
dPairWidth2=0.08128
dPairGap2=0.1143
dPairViaGap2=0
dPairWidth3=0.09906
dPairGap3=0.1016
dPairViaGap3=0
dPairWidth4=0.1016
dPairGap4=0.17
dPairViaGap4=0
SilkLineWidth=0.12
SilkTextSizeV=0.5
SilkTextSizeH=0.5
SilkTextSizeThickness=0.09999999999999999
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.05
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0
SolderMaskMinWidth=0
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=TOP_01.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=GND_02.Cu
Type=1
Enabled=1
[pcbnew/Layer.In2.Cu]
Name=SIG_03.Cu
Type=0
Enabled=1
[pcbnew/Layer.In3.Cu]
Name=GND_04.Cu
Type=1
Enabled=1
[pcbnew/Layer.In4.Cu]
Name=SIG_05.Cu
Type=0
Enabled=1
[pcbnew/Layer.In5.Cu]
Name=GND_06.Cu
Type=1
Enabled=1
[pcbnew/Layer.In6.Cu]
Name=PWR_07.Cu
Type=1
Enabled=1
[pcbnew/Layer.In7.Cu]
Name=PWR_08.Cu
Type=1
Enabled=1
[pcbnew/Layer.In8.Cu]
Name=PWR_09.Cu
Type=1
Enabled=1
[pcbnew/Layer.In9.Cu]
Name=PWR_10.Cu
Type=1
Enabled=1
[pcbnew/Layer.In10.Cu]
Name=GND_11.Cu
Type=1
Enabled=1
[pcbnew/Layer.In11.Cu]
Name=SIG_12.Cu
Type=0
Enabled=1
[pcbnew/Layer.In12.Cu]
Name=GND_13.Cu
Type=1
Enabled=1
[pcbnew/Layer.In13.Cu]
Name=SIG_14.Cu
Type=0
Enabled=1
[pcbnew/Layer.In14.Cu]
Name=GND_15.Cu
Type=1
Enabled=1
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=BOT_16.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.1
TrackWidth=0.25
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.25
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/1]
Name=ZDIFF=100
Clearance=0.1
TrackWidth=0.10668
ViaDiameter=0.4
ViaDrill=0.2
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.10668
dPairGap=0.254
dPairViaGap=0.25
[pcbnew/Netclasses/2]
Name=ZDIFF=90
Clearance=0.1
TrackWidth=0.127
ViaDiameter=0.4
ViaDrill=0.2
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.127
dPairGap=0.1778
dPairViaGap=0.25
[pcbnew/Netclasses/3]
Name=ZSINGLE=50
Clearance=0.1
TrackWidth=0.13208
ViaDiameter=0.4
ViaDrill=0.2
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.13208
dPairGap=0.18
dPairViaGap=0.25
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=PDFS/
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1