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    (title "Top Sheet")
    (date "2023-12-21")
    (rev "1.00")
    (company "ApotheoTech LLC")
    (comment 1 "SCH: APT-KRIA-FMC")
    (comment 2 "Author: Chance Reimer")
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  (text "PS_POR is pulled up 4.7K to 1.8V on SOM" (at 266.827 234.569 0)
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  (text "Refer to page 11/842 of PIC datasheet\nfor SCL2 (pins 9, 10 for 40 pin UQFN)"
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  (text "* SD reset is 3.3V nominal, no change\n* Raspberry Pi Resets are 3.3V nominal, no change\n* USB reset is 1.8V nominal, "
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  (text "Voltage Level Conversion" (at 170.815 134.366 0)
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  (text "Pull up, DIR high is translation from A to B\nWant POR_B to be controlled by carrier card,\nit is held in reset until PS side is good\nRefer to p age 24 of UG1089\nOnce CC_PS is good, check the PS_POR_B\nto reset all PS reliant domains"
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  (text "Reasoning: Want PS_POR_B to be pulled \nlow here during startup (Q21 Gate High)\nSo PS_POR_B is low. On Powerup, PIC \npulls PS_POR_B_3V3_L low to deassert PS_POR_B"
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  (text "PIC18LF47K42-I/MV Reset Pinout" (at 15.494 32.131 0)
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  (text "Place all *_N pins as high (1) when not in reset" (at 136.144 66.802 0)
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  (text "DIR is high, goes from A to B\nReferenced from VCCA"
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  (text "Does PGC mean ICSPCLK?\nDoes PGD mean ICSPDAT?\n\nRefering to sheet 8/9 for Curiosity HPC for a reference pinout (RB7 for data, RB6 for clock)"
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  (text "Kria MIO Banks are fixed at 1.8V\nUse 1.8V from PS voltage supply for reference voltage conversion"
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  (text "Refer to ICD4/PICkit 4 Target Adapter Board\nCortex JTAG/SWD (10 pin mini) which this is based off of\n"
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