Clock domain crossing

[mounakrishna99]

Hi,
I have a large design in which I am actually trying to pinmux the JTAG IO pins with GPIOs. During that process, since the JTAG is in different clock domain I am facing issues with connection. As per the design specs, I don't need to take care of the domain crossing. To achieve that, I found that I need to use mkNullCrossingWire. But I am facing issues if I use that. Can anyone help me to fix this?
I checked #33 and #637. I see that the solution is to pass the values as module paramters. But in my case, I am not sure how to do that.

I have attached a simpler version of the code where the same problem is replicated. This simpler design resembles the Testbench as the top module (SoC), mod1 as the pinmuxing module and mod2 to be the JTAG module.

Changing the Wires() in mod1.bsv to registers works. But I don't want registers there. I want them to act as just a simple connection from the Testbench to mod2.

package Testbench;
  import Clocks :: *;
  import BUtils :: *;
  import mod1 :: *;
  import mod2 :: *;
  interface Ifc_Testbench;
    method Bit#(1) out;
    method Action ma_in (Bit#(1) in);
  endinterface
  (*synthesize*)
  module mkTestbench(Clock tck_clk, Reset trst, Ifc_Testbench ifc);
    let curr_clk <- exposeCurrentClock;
    let curr_rst <- exposeCurrentReset;
    Ifc_mod1 mod1 <- mkmod1;
    Ifc_mod2 mod2 <- mkmod2(clocked_by tck_clk, reset_by trst);
    ReadOnly#(Bit#(1)) cr_val_in <- mkNullCrossingWire(clocked_by tck_clk, reset_by trst, curr_clk, mod2.out);
    ReadOnly#(Bit#(1)) cr_val_out <- mkNullCrossingWire(tck_clk, mod1.val_out);
    rule connect_mods_out;
      mod1.val_in(cr_val_in);
    endrule                                                                                                                                                                                                          
    rule connect_mods_in;                                                                                                                                                                                            
      mod2.ma_in(cr_val_out);                                                                                                                                                                                        
    endrule                                                                                                                                                                                                          
                                                                                                                                                                                                                     
    method out = mod1.pad_out;                                                                                                                                                                                       
    method Action ma_in (Bit#(1) in);                                                                                                                                                                                
      mod1.pad_in(in);                                                                                                                                                                                               
    endmethod                                                                                                                                                                                                        
  endmodule                                                                                                                                                                                                          
endpackage 

package mod1;
  interface Ifc_mod1;
    method Bit#(1) val_out;
    method Action val_in (Bit#(1) in);
    method Bit#(1) pad_out;
    method Action pad_in (Bit#(1) in);
  endinterface
  module mkmod1(Ifc_mod1);
    Wire#(Bit#(1)) wr_val_in  <- mkDWire(0);
    Wire#(Bit#(1)) wr_val_out <- mkDWire(0);
    Wire#(Bit#(1)) wr_pad_in  <- mkDWire(0);
    Wire#(Bit#(1)) wr_pad_out <- mkDWire(0);
    rule rl_connect_in;
      wr_val_out <= wr_pad_in;
    endrule
    rule rl_connect_out;
      wr_pad_out <= wr_val_in;
    endrule
    method pad_out = wr_pad_out;
    method Action pad_in (Bit#(1) in );
      wr_pad_in <= in;                                                                                                                                                                                               
    endmethod                                                                                                                                                                                                        
    method val_out = wr_val_out;                                                                                                                                                                                     
    method Action val_in (Bit#(1) in );                                                                                                                                                                              
      wr_val_in <= in;                                                                                                                                                                                               
    endmethod                                                                                                                                                                                                        
  endmodule                                                                                                                                                                                                          
                                                                                                                                                                                                                     
endpackage

package mod2;
  interface Ifc_mod2;
    method Bit#(1) out;
    method Action ma_in (Bit#(1) in);
  endinterface
  module mkmod2(Ifc_mod2);
    Reg#(Bit#(1)) rg_in <- mkReg(0);
    Reg#(Bit#(1)) rg_out <- mkReg(0);
    rule rl_connect;
      rg_out <= rg_in;
    endrule
    method out = rg_out;
    method Action ma_in (Bit#(1) in );
      rg_in <= in;
    endmethod
  endmodule
endpackage

The error I get is attached below:

compiling /home/mounakrishna/WORK/Bluespec_BSV_Tutorial/Example_Programs/test/src_BSV/Testbench.bsv
code generation for mkTestbench starts
Error: "Clocks.bsv", line 1753, column 9: (G0005)
  The assertion `can_schedule_first' failed for rule
  `RL_cr_val_out_clock_domain_crossing'
  because before it can be executed:
    RL_mod1_rl_connect_in must be executed
Elaborated error module file created: build_v/mkTestbench.ba
make: *** [Makefile:122: verilog] Error 1