hold off on SYNC reset of core for error reporting via SYNC interface

[caryan]

I've observed single JESD core clock drops in sync. Since this is after a synchronizer this probably error reporting via the SYNC interface for 1 or 2 frames --- c.f. section 7.6.4 of the JESD spec.. This causes the core to reset and starts to send CGS. Since SYNC has returned to deasserted it continues to the ILA sequence. The receiver gets completely thrown and and then asserts SYNC for long enough to reinitialize the link properly.