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jakubcabaljakubcabal
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Merge branch 'benesd_feat_thunderfjord_boot_3dparty' into 'devel'
Add boot support for fb2cdg1 See merge request ndk/ndk-fpga!296
2 parents 7cde553 + 7d7a751 commit ca04cca

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-86
lines changed

5 files changed

+97
-86
lines changed

‎cards/silicom/fb2cdg1/config/card_const.tcl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ set NET_MOD_ARCH "F_TILE"
1818
# Achitecture of SDM/SYSMON module
1919
set SDM_SYSMON_ARCH "INTEL_SDM"
2020
# Boot controller type (5=OFS_PMCI)
21-
set BOOT_TYPE 0
21+
set BOOT_TYPE 5
2222

2323
# Total number of QSFP cages
2424
set QSFP_CAGES 2

‎cards/silicom/fb2cdg1/readme.rst‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,7 @@ NDK firmware support
2525
- Makefile targets for building the NDK firmware (valid for Minimal app, may vary for other apps):
2626
- Use ``make 400g2`` command for firmware with 2x400GE (default).
2727
- Support for booting the NDK firmware using the nfb-boot tool:
28-
- NO
28+
- YES, starting with the nfb-framework version 6.28.5
2929

3030
.. note::
3131

‎cards/silicom/fb2cdg1/src/Modules.tcl‎

Lines changed: 13 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,12 +8,23 @@
88
array set ARCHGRP_ARR $ARCHGRP
99

1010
# Paths
11-
# set PMCI_FB2CDG1_BASE "$ENTITY_BASE/comp/pmci"
11+
set PMCI_FB2CDG1_BASE "$OFM_PATH/extra/ip-3rdparty/silicom/fb2cdg1"
1212
set FPGA_COMMON_BASE "$ARCHGRP_ARR(CORE_BASE)/top"
1313

1414
# Components
1515
lappend COMPONENTS [list "FPGA_COMMON" $FPGA_COMMON_BASE $ARCHGRP]
16-
# lappend COMPONENTS [list "PMCI_FB2CDG1" $PMCI_FB2CDG1_BASE "FULL" ]
16+
# Check whether the 3rd-party repository exists
17+
if ![file exists $PMCI_FB2CDG1_BASE/Modules.tcl] {
18+
puts "\n"
19+
puts "ERROR: PMCI IP is not present. PMCI requires an additional license."
20+
puts "------------------------------------------------------------------------------------------------"
21+
puts "Please contact Support for more information (see the Partners section of the NDK documentation)."
22+
puts "------------------------------------------------------------------------------------------------"
23+
puts "\n"
24+
exit 1
25+
} else {
26+
lappend COMPONENTS [list "PMCI_FB2CDG1" $PMCI_FB2CDG1_BASE "FULL" ]
27+
}
1728

1829
# IP components
1930
set IP_COMMON_TCL $ARCHGRP_ARR(IP_TEMPLATE_ROOT)/common.tcl

‎cards/silicom/fb2cdg1/src/Quartus.inc.tcl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,7 @@ lappend HIERARCHY(COMPONENTS) \
4242
set SYNTH_FLAGS(MODULE) "FPGA"
4343
set SYNTH_FLAGS(FPGA) $CARD_FPGA
4444
set SYNTH_FLAGS(BITSTREAM) "OFS_PMCI"
45-
set SYNTH_FLAGS(OFS_PMCI_SCRIPT_DIR) $CARD_BASE/scripts/
45+
set SYNTH_FLAGS(OFS_PMCI_SCRIPT_DIR) $OFM_PATH/extra/ip-3rdparty/silicom/fb2cdg1/scripts
4646

4747
# Enable Quartus Support-Logic Generation stage
4848
set SYNTH_FLAGS(QUARTUS_TLG) 1

‎cards/silicom/fb2cdg1/src/fpga.vhd‎

Lines changed: 81 additions & 81 deletions
Original file line numberDiff line numberDiff line change
@@ -77,40 +77,40 @@ port (
7777

7878
QSFP1_LED_R : out std_logic;
7979
QSFP1_LED_G : out std_logic;
80-
QSFP1_LED_B : out std_logic
81-
82-
-- -- =========================================================================
83-
-- -- BMC INTERFACE
84-
-- -- =========================================================================
85-
-- -- QSPI interface from FPGA to Max10:
86-
-- QSPI_CSN_1V2 : out std_logic;
87-
-- QSPI_D0 : inout std_logic;
88-
-- QSPI_D1 : inout std_logic;
89-
-- QSPI_D2 : inout std_logic;
90-
-- QSPI_D3 : inout std_logic;
91-
-- QSPI_CLK : out std_logic;
92-
93-
-- -- SPI Ingress (Seen from BMC) FPGA > MAX
94-
-- SPI_INGRESS_SCLK : out std_logic;
95-
-- SPI_INGRESS_CSN : out std_logic;
96-
-- SPI_INGRESS_MISO : in std_logic;
97-
-- SPI_INGRESS_MOSI : out std_logic;
98-
99-
-- -- SPI Egress (Seen from BMC) MAX > FPGA
100-
-- SPI_EGRESS_MOSI : in std_logic;
101-
-- SPI_EGRESS_CSN : in std_logic;
102-
-- SPI_EGRESS_SCLK : in std_logic;
103-
-- SPI_EGRESS_MISO : out std_logic;
104-
105-
-- -- Misc signals between FPGA and BMC:
106-
-- -- Heart beat from BMC NIOS in the BMC
107-
-- MAX_FPGA_HB_1V2 : in std_logic;
108-
-- -- Heart beat from PMCI NIOS in this FPGA
109-
-- FPGA_MAX_HB : out std_logic;
110-
-- -- Single Event Upset. Active high.
111-
-- FPGA_MAX_FPGA_SEU_1V2 : out std_logic;
112-
-- -- Thermal shutdown. Active Low
113-
-- FPGA_MAX_THRM_SHTD_N_1V2 : out std_logic
80+
QSFP1_LED_B : out std_logic;
81+
82+
-- =========================================================================
83+
-- BMC INTERFACE
84+
-- =========================================================================
85+
-- QSPI interface from FPGA to Max10:
86+
QSPI_CSN_1V2 : out std_logic;
87+
QSPI_D0 : inout std_logic;
88+
QSPI_D1 : inout std_logic;
89+
QSPI_D2 : inout std_logic;
90+
QSPI_D3 : inout std_logic;
91+
QSPI_CLK : out std_logic;
92+
93+
-- SPI Ingress (Seen from BMC) FPGA > MAX
94+
SPI_INGRESS_SCLK : out std_logic;
95+
SPI_INGRESS_CSN : out std_logic;
96+
SPI_INGRESS_MISO : in std_logic;
97+
SPI_INGRESS_MOSI : out std_logic;
98+
99+
-- SPI Egress (Seen from BMC) MAX > FPGA
100+
SPI_EGRESS_MOSI : in std_logic;
101+
SPI_EGRESS_CSN : in std_logic;
102+
SPI_EGRESS_SCLK : in std_logic;
103+
SPI_EGRESS_MISO : out std_logic;
104+
105+
-- Misc signals between FPGA and BMC:
106+
-- Heart beat from BMC NIOS in the BMC
107+
MAX_FPGA_HB_1V2 : in std_logic;
108+
-- Heart beat from PMCI NIOS in this FPGA
109+
FPGA_MAX_HB : out std_logic;
110+
-- Single Event Upset. Active high.
111+
FPGA_MAX_FPGA_SEU_1V2 : out std_logic;
112+
-- Thermal shutdown. Active Low
113+
FPGA_MAX_THRM_SHTD_N_1V2 : out std_logic
114114
);
115115
end entity;
116116

@@ -301,52 +301,52 @@ begin
301301
MISC_OUT => open
302302
);
303303

304-
-- -- BMC controller
305-
-- QSPI_D0 <= qspi_data_out(0) when qspi_data_oe(0) = '1' else 'Z';
306-
-- QSPI_D1 <= qspi_data_out(1) when qspi_data_oe(1) = '1' else 'Z';
307-
-- QSPI_D2 <= qspi_data_out(2) when qspi_data_oe(2) = '1' else 'Z';
308-
-- QSPI_D3 <= qspi_data_out(3) when qspi_data_oe(3) = '1' else 'Z';
309-
310-
-- pmci_i : entity work.PMCI_FB2CDG1
311-
-- generic map(
312-
-- DEVICE => "AGILEX",
313-
-- G_SWB_RD_TYPE => 1 -- Thunderfjord
314-
-- ) port map(
315-
-- CLK => boot_mi_clk,
316-
-- RESET => boot_mi_reset,
317-
318-
-- MI_DWR => boot_mi_dwr,
319-
-- MI_ADDR => boot_mi_addr,
320-
-- MI_RD => boot_mi_rd,
321-
-- MI_WR => boot_mi_wr,
322-
-- MI_BE => boot_mi_be,
323-
-- MI_DRD => boot_mi_drd,
324-
-- MI_ARDY => boot_mi_ardy,
325-
-- MI_DRDY => boot_mi_drdy,
326-
327-
-- FLASH_CTRLR_ATOM_PORTS_DCLK => QSPI_CLK,
328-
-- FLASH_CTRLR_ATOM_PORTS_NCS => QSPI_CSN_1V2,
329-
-- FLASH_CTRLR_ATOM_PORTS_OE => open,
330-
-- FLASH_CTRLR_ATOM_PORTS_DATAOUT => qspi_data_out,
331-
-- FLASH_CTRLR_ATOM_PORTS_DATAOE => qspi_data_oe,
332-
-- FLASH_CTRLR_ATOM_PORTS_DATAIN => QSPI_D3 & QSPI_D2 & QSPI_D1 & QSPI_D0,
333-
334-
-- M10_GPIO_FPGA_USR_100M => '0',
335-
-- M10_GPIO_FPGA_M10_HB => MAX_FPGA_HB_1V2,
336-
-- M10_GPIO_PMCI_NIOS_HB => FPGA_MAX_HB,
337-
-- M10_GPIO_M10_SEU_ERROR => '0',
338-
-- M10_GPIO_FPGA_THERM_SHDN => FPGA_MAX_THRM_SHTD_N_1V2,
339-
-- M10_GPIO_FPGA_SEU_ERROR => FPGA_MAX_FPGA_SEU_1V2,
340-
341-
-- SPI_INGRESS_SCLK => SPI_INGRESS_SCLK,
342-
-- SPI_INGRESS_CSN => SPI_INGRESS_CSN,
343-
-- SPI_INGRESS_MISO => SPI_INGRESS_MISO,
344-
-- SPI_INGRESS_MOSI => SPI_INGRESS_MOSI,
345-
346-
-- SPI_EGRESS_MOSI => SPI_EGRESS_MOSI,
347-
-- SPI_EGRESS_CSN => SPI_EGRESS_CSN,
348-
-- SPI_EGRESS_SCLK => SPI_EGRESS_SCLK,
349-
-- SPI_EGRESS_MISO => SPI_EGRESS_MISO
350-
-- );
304+
-- BMC controller
305+
QSPI_D0 <= qspi_data_out(0) when qspi_data_oe(0) = '1' else 'Z';
306+
QSPI_D1 <= qspi_data_out(1) when qspi_data_oe(1) = '1' else 'Z';
307+
QSPI_D2 <= qspi_data_out(2) when qspi_data_oe(2) = '1' else 'Z';
308+
QSPI_D3 <= qspi_data_out(3) when qspi_data_oe(3) = '1' else 'Z';
309+
310+
pmci_i : entity work.PMCI_FB2CDG1
311+
generic map(
312+
DEVICE => "AGILEX",
313+
G_SWB_RD_TYPE => 1 -- Thunderfjord
314+
) port map(
315+
CLK => boot_mi_clk,
316+
RESET => boot_mi_reset,
317+
318+
MI_DWR => boot_mi_dwr,
319+
MI_ADDR => boot_mi_addr,
320+
MI_RD => boot_mi_rd,
321+
MI_WR => boot_mi_wr,
322+
MI_BE => boot_mi_be,
323+
MI_DRD => boot_mi_drd,
324+
MI_ARDY => boot_mi_ardy,
325+
MI_DRDY => boot_mi_drdy,
326+
327+
FLASH_CTRLR_ATOM_PORTS_DCLK => QSPI_CLK,
328+
FLASH_CTRLR_ATOM_PORTS_NCS => QSPI_CSN_1V2,
329+
FLASH_CTRLR_ATOM_PORTS_OE => open,
330+
FLASH_CTRLR_ATOM_PORTS_DATAOUT => qspi_data_out,
331+
FLASH_CTRLR_ATOM_PORTS_DATAOE => qspi_data_oe,
332+
FLASH_CTRLR_ATOM_PORTS_DATAIN => QSPI_D3 & QSPI_D2 & QSPI_D1 & QSPI_D0,
333+
334+
M10_GPIO_FPGA_USR_100M => '0',
335+
M10_GPIO_FPGA_M10_HB => MAX_FPGA_HB_1V2,
336+
M10_GPIO_PMCI_NIOS_HB => FPGA_MAX_HB,
337+
M10_GPIO_M10_SEU_ERROR => '0',
338+
M10_GPIO_FPGA_THERM_SHDN => FPGA_MAX_THRM_SHTD_N_1V2,
339+
M10_GPIO_FPGA_SEU_ERROR => FPGA_MAX_FPGA_SEU_1V2,
340+
341+
SPI_INGRESS_SCLK => SPI_INGRESS_SCLK,
342+
SPI_INGRESS_CSN => SPI_INGRESS_CSN,
343+
SPI_INGRESS_MISO => SPI_INGRESS_MISO,
344+
SPI_INGRESS_MOSI => SPI_INGRESS_MOSI,
345+
346+
SPI_EGRESS_MOSI => SPI_EGRESS_MOSI,
347+
SPI_EGRESS_CSN => SPI_EGRESS_CSN,
348+
SPI_EGRESS_SCLK => SPI_EGRESS_SCLK,
349+
SPI_EGRESS_MISO => SPI_EGRESS_MISO
350+
);
351351

352352
end architecture;

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