fix(cocotbext - ndk_core): set 400MHz as default value for P_TILE PCIe CLK

Author: martinspinler

python/cocotbext/cocotbext/ndk_core/nfbdevice.py

@@ -128,7 +128,13 @@ async def _init_clks(self):
             await cocotb.start(Clock(self._core.clk_gen_i.OUTCLK_3, 10, 'ns').start())
 
         for pcie_clk in self._core.pcie_i.pcie_core_i.pcie_hip_clk:
-            await cocotb.start(Clock(pcie_clk, 4, 'ns').start())
+            if self._core.pcie_i.pcie_core_i.ENDPOINT_TYPE.value.decode() == "P_TILE":
+                # This is default value in IP core for g4_pld_clkfreq_user_hwctl
+                period = 2.5
+            else:
+                period = 4
+
+            await cocotb.start(Clock(pcie_clk, period, 'ns').start())
 
         for eth_core in self._core.network_mod_i.eth_core_g if hasattr(self._core.network_mod_i, 'eth_core_g') else []:
             if hasattr(eth_core.network_mod_core_i, 'cmac_clk_322m'):