Investigate jump table compression for code size

[resistor]

The AArch64 backend uses compressed jump tables to reduce code size. By default, jump table entries are stored as 32-bit PC-relative offsets, but can be optimized to 16 or even 8-bit relative offsets as appropriate.

We should evaluate whether this optimization is worth porting to RISCV and then enabling for CHERIoT. I know that we do see jump tables occurring in the CheriotRTOS test suite binaries, but don't have a sense of what scale of savings we could achieve here.

Relevant source file is: https://github.com/llvm/llvm-project/blob/590f451b60d434b26c634a07125fb05baf461fa0/llvm/lib/Target/AArch64/AArch64CompressJumpTables.cpp#L1

[davidchisnall]

I’m not sure what the total saving would be, but a 16-bit offset has a range of 128 KiB (low bit must be zero because instructions must be 2-byte aligned). That’s approximately 100% of compartments and so simply always using 16-bit displacements would make sense in CHERIoT. This might be a use for the ‘tiny’ code model.

I think this is made a bit harder in RISC-V by the prevalence of relaxations, but that should just miss some optimisation opportunities if they are ignored (relaxations never make two labels further apart).

[resistor]

I think the first step here would be to introduce a PseudoBR_JT that defers jump table branch expansion until after code size can be computed.