Issues Encountered with Mithril Plugin for Row Hammer Simulation

[jtueszero]

I attempted to use the provided Mithril plugin for row hammer simulation but encountered two issues:

1. Issue: std::bad_array_new_length or std::bad_alloc Errors
   Errors occur with specific multicore workloads such as mix 12, 13, 14, ... 20 and mix 32, 34 .... etc.

I found solution for this issue : Modify line 127 of mithril.cpp as follows:
m_ctrl(ctrl), m_src_ref_ctrs(src_ref_ctrs), m_src_all_bank_ctr(m_src_all_bank_ctr),
should be updated to:
m_ctrl(ctrl), m_src_ref_ctrs(src_ref_ctrs), m_src_all_bank_ctr(src_all_bank_ctr),

2. Issue: External rfm Command Handling and Segmentation Fault Errors
   mithril.cpp processes external rfm commands and performs refresh operations based on the max index in the rfm command. An external mechanism to issue rfm is required. However, upon implementing this using rfm_manager, a Segmentation Fault (core dumped) error occurs.

Error Analysis (via gdb):
Program received signal SIGFPE, Arithmetic exception.
std::_Hashtable<int, std::pair<int const, Ramulator::Mithril::MithrilBank::CommandHandler>, std::allocator<std::pair<int const, Ramulator::Mithril::MithrilBank::CommandHandler> >, std::__detail::_Select1st, std::equal_to, std::hash, std::__detail::_Mod_range_hashing, std::__detail::_Default_ranged_hash, std::__detail::_Prime_rehash_policy, std::__detail::_Hashtable_traits<false, false, true> >::find (__k=@0x59451c: 3, this=0x6846c0) at /usr/include/c++/11/bits/hashtable.h:1594
1594 std::size_t __bkt = _M_bucket_index(__code);
(gdb) bt
#0 std::_Hashtable<int, std::pair<int const, Ramulator::Mithril::MithrilBank::CommandHandler>, std::allocator<std::pair<int const, Ramulator::Mithril::MithrilBank::CommandHandler> >, std::__detail::_Select1st, std::equal_to, std::hash, std::__detail::_Mod_range_hashing, std::__detail::_Default_ranged_hash, std::__detail::_Prime_rehash_policy, std::__detail::_Hashtable_traits<false, false, true> >::find (__k=@0x59451c: 3, this=0x6846c0) at /usr/include/c++/11/bits/hashtable.h:1594
#1 std::unordered_map<int, Ramulator::Mithril::MithrilBank::CommandHandler, std::hash, std::equal_to, std::allocator<std::pair<int const, Ramulator::Mithril::MithrilBank::CommandHandler> > >::find (__x=@0x59451c: 3, this=0x6846c0)
at /usr/include/c++/11/bits/unordered_map.h:869
#2 Ramulator::Mithril::MithrilBank::on_request (req=..., this=0x684640) at /home/HY/BreakHammer/src/dram_controller/impl/plugin/mithril.cpp:138
#3 Ramulator::Mithril::update (this=0x67ef60, request_found=, req_it=...) at /home/HY/BreakHammer/src/dram_controller/impl/plugin/mithril.cpp:115
#4 0x00007ffff7d34853 in Ramulator::BHDRAMController::tick (this=0x67cdd0) at /home/HY/BreakHammer/src/dram_controller/impl/bh_dram_controller.cpp:165
#5 0x00007ffff7bde7fc in Ramulator::BHDRAMSystem::tick (this=) at /home/HY/BreakHammer/src/memory_system/impl/bh_DRAM_system.cpp:78
#6 0x000000000042bd4a in main (argc=, argv=) at /home/HY/BreakHammer/src/main.cpp:113
(gdb) exit

Below is the YAML file used during the tests:

Frontend:
Translation:
impl: RandomTranslation
max_addr: 17179869184
clock_ratio: 8
impl: BHO3
inst_window_depth: 128
lat_dump_path: /home/HY/BreakHammer/Debug/Mithril/example.memlat.dump
llc_capacity_per_core: 2MB
llc_num_mshr_per_core: 16
no_wait_trace_cache_only: false
num_expected_insts: 10000000
num_max_cycles: 300000000
trace_cache_only: false
traces:

• /home/HY/BreakHammer/cputraces/tpch17
• /home/HY/BreakHammer/cputraces/jp2_decode
• /home/HY/BreakHammer/cputraces/526.blender
• /home/HY/BreakHammer/cputraces/557.xz
  MemorySystem:
  AddrMapper:
  impl: RoBaRaCoCh_with_rit
  BHDRAMController:
  BHScheduler:
  impl: BHScheduler
  RefreshManager:
  impl: AllBank
  RowPolicy:
  cap: 4
  impl: CloseRowPolicy
  impl: BHDRAMController
  plugins:
  • ControllerPlugin:
    commands_to_count:
    • ACT
    • PRE
      impl: CommandCounter
      path: /home/HY/BreakHammer/Debug/Mithril/example.cmd.count
  • ControllerPlugin:
    impl: Mithril
    ad_th: 1
    num_ctrs: 24711
    DRAM:
    RFM:
    BRC: 2
    current:
    preset: Default
    drampower_enable: true
    impl: DDR5-VRR
    org:
    channel: 1
    preset: DDR5_16Gb_x8
    rank: 2
    timing:
    preset: DDR5_3200AN
    voltage:
    preset: Default
    clock_ratio: 3
    impl: BHDRAMSystem

I would greatly appreciate any insights or recommendations for resolving these issues.