From 79a65488850082d674996a8f38a58379b3dab1f8 Mon Sep 17 00:00:00 2001
From: Alec Edgington <alec.edgington@quantinuum.com>
Date: Fri, 24 Jan 2025 13:38:05 +0000
Subject: [PATCH 1/3] Fix conversion of BitEq and BitNeq to QASM.

---
 pytket/binders/circuit/clexpr.cpp | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/pytket/binders/circuit/clexpr.cpp b/pytket/binders/circuit/clexpr.cpp
index 94ddefdcc4..41173861e0 100644
--- a/pytket/binders/circuit/clexpr.cpp
+++ b/pytket/binders/circuit/clexpr.cpp
@@ -149,9 +149,11 @@ static std::string qasm_expr_repr(
       if (n_args != 2) {
         throw std::logic_error("BitEq with != 2 arguments");
       }
+      ss << "~(";
       ss << qasm_arg_repr(args[0], input_bits, input_regs, ArgValueType::Bit);
-      ss << " == ";
+      ss << " ^ ";
       ss << qasm_arg_repr(args[1], input_bits, input_regs, ArgValueType::Bit);
+      ss << ")";
       break;
 
     case ClOp::BitNeq:
@@ -159,7 +161,7 @@ static std::string qasm_expr_repr(
         throw std::logic_error("BitNeq with != 2 arguments");
       }
       ss << qasm_arg_repr(args[0], input_bits, input_regs, ArgValueType::Bit)
-         << " != "
+         << " ^ "
          << qasm_arg_repr(args[1], input_bits, input_regs, ArgValueType::Bit);
       break;
 

From 0d139e755fac5a6b688512871debd6f25ea05234 Mon Sep 17 00:00:00 2001
From: Alec Edgington <alec.edgington@quantinuum.com>
Date: Fri, 24 Jan 2025 13:49:09 +0000
Subject: [PATCH 2/3] Add test.

---
 pytket/tests/clexpr_test.py | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/pytket/tests/clexpr_test.py b/pytket/tests/clexpr_test.py
index 22be69f35f..463c084b18 100644
--- a/pytket/tests/clexpr_test.py
+++ b/pytket/tests/clexpr_test.py
@@ -255,3 +255,32 @@ def test_add_logicexp_as_clexpr() -> None:
 c = (a | b);
 """
     )
+
+
+def test_biteq_bitneq_to_qasm() -> None:
+    # https://github.com/CQCL/tket/issues/1753
+    c = Circuit(0, 3)
+    c.add_clexpr(
+        WiredClExpr(
+            expr=ClExpr(
+                op=ClOp.BitAnd,
+                args=[
+                    ClExpr(op=ClOp.BitEq, args=[ClBitVar(0), 0]),
+                    ClExpr(op=ClOp.BitNeq, args=[ClBitVar(1), 1]),
+                ],
+            ),
+            bit_posn={0: 0, 1: 1},
+            output_posn=[2],
+        ),
+        c.bits,
+    )
+    qasm = circuit_to_qasm_str(c, header="hqslib1")
+    assert (
+        qasm
+        == """OPENQASM 2.0;
+include "hqslib1.inc";
+
+creg c[3];
+c[2] = ((~(c[0] ^ 0)) & (c[1] ^ 1));
+"""
+    )

From 54ffdf484014d2645b66656cbe74a44cd29d44ec Mon Sep 17 00:00:00 2001
From: Alec Edgington <alec.edgington@quantinuum.com>
Date: Fri, 24 Jan 2025 13:50:44 +0000
Subject: [PATCH 3/3] Update changelog.

---
 pytket/docs/changelog.rst | 1 +
 1 file changed, 1 insertion(+)

diff --git a/pytket/docs/changelog.rst b/pytket/docs/changelog.rst
index 2ddd62469e..132612ed68 100644
--- a/pytket/docs/changelog.rst
+++ b/pytket/docs/changelog.rst
@@ -12,6 +12,7 @@ Fixes:
 
 * Make `CliffordCircuitPredicate` accept circuits containing measurements.
 * Make `DecomposeBoxes` pass recurse into conditional boxes.
+* Fix conversion of `ClOp.BitEq` and `ClOp.BitNeq` to QASM.
 
 1.39.0 (January 2025)
 ---------------------