table-of-contents.adoc

List of Figures

• Loongson 3 System architecture

• Loongson 3 node structure

• Loongson 3A5000 chip structure

• Stable reset control for multi-chip interconnection

• GS464V structure

• Interrupt routing of Loongson 3A5000 processor

• General mode timing

• Reverse mode timing

• Access to the HT protocol configuration in the Loongson 3A5000

• Structure of four Loongson 3 chips interconnected

• Structure of sixteen Loongson 3 chips interconnected

• Structure of two Loongson 3 chips with 8-bit interconnection

• Structure of two Loongson 3 chips with 16-bit interconnection

List of Tables

• Descriptions of control pins

• System global address layout at the node level

• Address layout within nodes

• SCID_SEL Address bit configuration

• 44-bit physical address layout within nodes

• Space access attributes corresponding to MMAP

• Table of address window registers

• Description of MMAP register bit field

• Correspondence from the device number to the module it belongs to

• Space access attributes corresponding to MMAP

• Version register

• Chip characteristics register

• Manufacturer name register

• Chip name register

• Function configuration register

• Pin controller driver configuration register

• Function collection register

• Temperature collection register

• Node clock software multiplier configuration register

• Memory clock software multiplier configuration register

• Processor core software frequency division configuration

• Processor core software reset control register

• Chip routing configuration register

• Other function configuration register

• Temperature observation register

• Processor core SRAM adjustment register

• FUSE0 observation register

• FUSE1 observation register

• Processor internal clock description

• Processor core software frequency division configuration

• Other function configuration register

• Other function configuration register

• Processor core private frequency division register

• Function configuration register

• Other function configuration register

• Function configuration register

• Other function configuration register

• Other function configuration register

• GPIO output enable register

• Address access method

• Configuration register instruction access method

• Register description

• Other function configuration register

• Node counter register

• Output enable register

• Input/Output Register

• Interrupt control register

• Table of GPIO multiplexing function

• Interrupt control register

• List of configuration information for the instruction set functions implemented in the 3A5000

• Shared Cache lock window register configuration

• Shared Cache configuration register (SC_CONFIG)

• Registers related to inter-processor interrupt and their functional descriptions

• List of inter-processor interrupt and communication registers for processor core 0

• List of inter-processor interrupt and communication registers for processor core 1

• List of inter-processor interrupt and communication registers for processor core 2

• List of inter-processor interrupt and communication registers for processor core 3

• List of inter-processor interrupt and communication registers for the current processor core

• Processor core inter-processor communication registers

• Processor core inter-processor communication registers

• Interrupt control register

• I/O control register address

• Description of the interrupt routing register

• Interrupt routing register address

• Processor core private interrupt status register

• Other function configuration register

• Extended I/O interrupt enable register

• Extended I/O interrupt auto-rotation enable register

• Extended I/O interrupt interrupt status register

• Extended I/O interrupt status register for each processor core

• Description of the interrupt pin routing register

• Interrupt routing register address

• Description of the interrupt destination processor core routing register

• Interrupt destination processor core routing register address

• Interrupt destination node mapping method configuration

• Extended I/O interrupt status register for the current processor core

• Extended I/O interrupt trigger register

• Description of temperature collection register

• Extended I/O interrupt trigger register

• Description of high/low temperature interrupt register

• Description of high-temperature underclock control register

• Description of temperature status detection and control register

• Description of temperature sensor configuration register

• Description of temperature sensor data register

• Software-visible parameter list of the memory controller

• Memory controller 0 error status observation register

• Memory controller 1 error status observation register

• Pin signals related to HyperTransport bus

• Commands that can be received by the HyperTransport receiver

• Commands that will be transported in both modes

• Default address window layout of the 4 HyperTransport interfaces

• Address window distribution inside the HyperTransport interface of the Loongson 3 processor

• Address window provided in the HyperTransport interface of the Loongson 3A5000 processor

• Software visible registers in the HT controller

• Bridge control register

• Definition of command, capabilities pointer, capability ID registers

• Definition of link config, link control registers

• Definition of revision id, link freq, link error, link freq capregisters

• Definition of feature registers

• Error Retry Control Register

• Retry Count Register

• Revision ID Register

• Interrupt capability register

• Interrupt dataport register

• Interrupt intrlnfo register 1

• Interrupt intrlnfo register 2

• Interrupt vectors mapping

• HT bus interrupt vector register definition 1

• HT bus interrupt vector register definition 2

• HT bus interrupt vector register definition 3

• HT bus interrupt vector register definition 4

• HT bus interrupt vector register definition 5

• HT bus interrupt vector register definition 6

• HT bus interrupt vector register definition 7

• HT bus interrupt vector register definition 8

• HT bus interrupt enable register definition 1

• HT bus interrupt enable register definition 2

• HT bus interrupt enable register definition 3

• HT bus interrupt enable register definition 4

• HT bus interrupt enable register definition 5

• HT bus interrupt enable register definition 6

• HT bus interrupt enable register definition 7

• HT bus interrupt enable register definition 8

• Link Train Register

• Definition of busreceive address window 0 enable (external access) register

• Definition of HT bus receive address window 0 base address (external access) register

• Definition of HT bus receive address window 1 enable (external access) register

• Definition of bus receive address window 1 base address (external access) register

• Definition of bus receive address window 2 enable (external access) register

• Definition of HT bus receive address window 2 base address (external Access) register

• Definition of HT bus receive address window 3 enable (external access) register

• Definition of HT bus receive address window 3 base address (external access) register

• Definition of HT bus receive address window 4 enable (external access) register

• Definition of HT bus receive address window 4 base address (external access) register

• Definition of configuration space extended address translation register

• Definition of extended address translation register

• HT bus POST address window 0 enable (internal access)

• HT bus POST address window 0 base address (internal access)

• HT bus POST address window 1 enable (internal access)

• HT bus POST address window 1 base address (internal access)

• HT bus prefetchable address window 0 enable (internal access)

• HT bus prefetchable address window 0 base address (internal access)

• HT bus prefetchable address window 1 enable (internal access)

• HT bus prefetchable address window 1 base address (internal access)

• HT bus uncache address window 0 enable (internal access)

• HT bus uncache address window 0 base address (internal access)

• HT bus uncache address window 1 enable (internal access)

• HT bus uncache address window 1 base address (internal access)

• HT bus uncache address window 2 enable (internal access)

• HT Bus uncache Address Window 2 Base Address (Internal Access)

• HT bus uncache address window 3 enable (internal access)

• HT Bus uncache address window 3 base address (internal access)

• Definition of HT bus P2P address window 0 enable (external access) register

• Definition of HT bus P2P address window 0 base address (external access) register

• Definition of HT bus P2P address window 1 enable (external access) register

• Definition of HT bus P2P address window 1 base address (external access) register

• Definition of controller parameter configuration register 0

• Definition of controller parameter configuration register 1

• Receive diagnostic register

• PHY status register

• Transport command Cache size register

• Transport data Cache size register

• Transport Cache debug register

• Receive buffer initialization configuration register

• Training 0 timeout short counter register

• Training 0 timeout long counter register

• Training 1 counter register

• Training 2 counter register

• Training 3 counter register

• Software frequency configuration register

• PHY impedance matching control register

• PHY configuration register

• Link initialization debug register

• LDT debug register 1

• LDT debug register 2

• LDT debug register 3

• LDT debug register 4

• LDT debug register 5

• LDT debug register 6

• HT TX POST ID WIN0

• HT TX POST ID WIN1

• HT TX POST ID WIN2

• HT TX POST ID WIN3

• HT RX INT TRANS Lo

• HT RX INT TRANS Hi

• Data transport register

• Interrupt enable register

• Interrupt identity register

• Table of interrupt control function

• FIFO control register

• Line control register

• MODEM Control Register

• MODEM state register

• Receive FIFO counter

• Transport FIFO counter

• Frequency division latchs 1

• Frequency division latchs 2

• Frequency division latchs 3

• Control register

• State register

• Transport data register

• External register

• Frequency division factor

• Parameter control register

• Chip select control register

• Timing control register

• Custom controller register

• Custom command register

• Custom data register 0

• Custom data register 1

• Custom timing register 0

• Custom timing register 1

• Custom timing register 2

• Frequency division latch low-order byte register

• Frequency division latch high-order byte register

• Control register

• Transport data register

• Receive data register

• Command control register

• State register

• Slave device controller register

• HT RX INT TRANS Lo

• HT RX INT TRANS Hi

• Other function configuration register

• Processor core inter-processor communication registers