From 2e613d006d0f261e2e18bd8c26161d8e3411a17e Mon Sep 17 00:00:00 2001 From: HorrorTroll Date: Thu, 29 Feb 2024 15:24:16 +0700 Subject: [PATCH 01/19] Update OTG LLD close to AT32 instead STM32 and patch some issues --- .../ext/CMSIS/ArteryTek/AT32F415/at32f415.h | 2 +- .../ext/CMSIS/ArteryTek/AT32F415/at32f415cx.h | 11 +- .../ext/CMSIS/ArteryTek/AT32F415/at32f415kx.h | 11 +- .../ext/CMSIS/ArteryTek/AT32F415/at32f415rx.h | 11 +- .../ArteryTek/AT32F415/system_at32f415.h | 2 +- os/hal/ports/AT32/LLD/EXINTv1/at32_exint1.inc | 2 +- os/hal/ports/AT32/LLD/OTGv1/at32_otg.h | 624 +++++++++--------- os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.c | 229 +++---- os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.h | 14 +- 9 files changed, 428 insertions(+), 478 deletions(-) diff --git a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415.h b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415.h index 61a3258568..07550788dd 100644 --- a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415.h +++ b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415.h @@ -204,4 +204,4 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} error_status; * @} */ -/*********************** (C) COPYRIGHT Artery Technologies *****END OF FILE****/ +/*********************** (C) COPYRIGHT Artery Technology *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415cx.h b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415cx.h index a1609cf0dd..5812f76baa 100644 --- a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415cx.h +++ b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415cx.h @@ -470,10 +470,7 @@ typedef struct { __IO uint32_t EVTOUT; /*!< IOMUX Event output control register, Address offset: 0x00 */ __IO uint32_t REMAP; /*!< IOMUX remap register 1, Address offset: 0x04 */ - __IO uint32_t EXINTC1; /*!< IOMUX external interrupt config register 1, Address offset: 0x08 */ - __IO uint32_t EXINTC2; /*!< IOMUX external interrupt config register 2, Address offset: 0x0C */ - __IO uint32_t EXINTC3; /*!< IOMUX external interrupt config register 3, Address offset: 0x10 */ - __IO uint32_t EXINTC4; /*!< IOMUX external interrupt config register 4, Address offset: 0x14 */ + __IO uint32_t EXINTC[4]; /*!< IOMUX external interrupt config register, Address offset: 0x08 ~ 0x14 */ uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */ __IO uint32_t REMAP2; /*!< IOMUX remap register 2, Address offset: 0x1C */ __IO uint32_t REMAP3; /*!< IOMUX remap register 3, Address offset: 0x20 */ @@ -696,9 +693,7 @@ typedef struct #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< FLASH registers base address */ #define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */ -#define UID1_BASE 0x1FFFF7E8U /*!< Unique device ID register 1 base address */ -#define UID2_BASE 0x1FFFF7ECU /*!< Unique device ID register 2 base address */ -#define UID3_BASE 0x1FFFF7F0U /*!< Unique device ID register 3 base address */ +#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */ #define USD_BASE 0x1FFFF800U /*!< FLASH User System Data base address */ #define DEBUG_BASE 0xE0042000U /*!< Debug MCU registers base address */ @@ -10494,4 +10489,4 @@ typedef struct #endif /* __AT32F415Cx_H */ -/*********************** (C) COPYRIGHT Artery Technologies *****END OF FILE****/ +/*********************** (C) COPYRIGHT Artery Technology *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415kx.h b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415kx.h index cbf383d983..77ea395899 100644 --- a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415kx.h +++ b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415kx.h @@ -469,10 +469,7 @@ typedef struct { __IO uint32_t EVTOUT; /*!< IOMUX Event output control register, Address offset: 0x00 */ __IO uint32_t REMAP; /*!< IOMUX remap register 1, Address offset: 0x04 */ - __IO uint32_t EXINTC1; /*!< IOMUX external interrupt config register 1, Address offset: 0x08 */ - __IO uint32_t EXINTC2; /*!< IOMUX external interrupt config register 2, Address offset: 0x0C */ - __IO uint32_t EXINTC3; /*!< IOMUX external interrupt config register 3, Address offset: 0x10 */ - __IO uint32_t EXINTC4; /*!< IOMUX external interrupt config register 4, Address offset: 0x14 */ + __IO uint32_t EXINTC[4]; /*!< IOMUX external interrupt config register, Address offset: 0x08 ~ 0x14 */ uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */ __IO uint32_t REMAP2; /*!< IOMUX remap register 2, Address offset: 0x1C */ __IO uint32_t REMAP3; /*!< IOMUX remap register 3, Address offset: 0x20 */ @@ -694,9 +691,7 @@ typedef struct #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< FLASH registers base address */ #define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */ -#define UID1_BASE 0x1FFFF7E8U /*!< Unique device ID register 1 base address */ -#define UID2_BASE 0x1FFFF7ECU /*!< Unique device ID register 2 base address */ -#define UID3_BASE 0x1FFFF7F0U /*!< Unique device ID register 3 base address */ +#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */ #define USD_BASE 0x1FFFF800U /*!< FLASH User System Data base address */ #define DEBUG_BASE 0xE0042000U /*!< Debug MCU registers base address */ @@ -10444,4 +10439,4 @@ typedef struct #endif /* __AT32F415Kx_H */ -/*********************** (C) COPYRIGHT Artery Technologies *****END OF FILE****/ +/*********************** (C) COPYRIGHT Artery Technology *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415rx.h b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415rx.h index 7339296261..708df9bc40 100644 --- a/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415rx.h +++ b/os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415rx.h @@ -472,10 +472,7 @@ typedef struct { __IO uint32_t EVTOUT; /*!< IOMUX Event output control register, Address offset: 0x00 */ __IO uint32_t REMAP; /*!< IOMUX remap register 1, Address offset: 0x04 */ - __IO uint32_t EXINTC1; /*!< IOMUX external interrupt config register 1, Address offset: 0x08 */ - __IO uint32_t EXINTC2; /*!< IOMUX external interrupt config register 2, Address offset: 0x0C */ - __IO uint32_t EXINTC3; /*!< IOMUX external interrupt config register 3, Address offset: 0x10 */ - __IO uint32_t EXINTC4; /*!< IOMUX external interrupt config register 4, Address offset: 0x14 */ + __IO uint32_t EXINTC[4]; /*!< IOMUX external interrupt config register, Address offset: 0x08 ~ 0x14 */ uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */ __IO uint32_t REMAP2; /*!< IOMUX remap register 2, Address offset: 0x1C */ __IO uint32_t REMAP3; /*!< IOMUX remap register 3, Address offset: 0x20 */ @@ -700,9 +697,7 @@ typedef struct #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< FLASH registers base address */ #define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */ -#define UID1_BASE 0x1FFFF7E8U /*!< Unique device ID register 1 base address */ -#define UID2_BASE 0x1FFFF7ECU /*!< Unique device ID register 2 base address */ -#define UID3_BASE 0x1FFFF7F0U /*!< Unique device ID register 3 base address */ +#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */ #define USD_BASE 0x1FFFF800U /*!< FLASH User System Data base address */ #define DEBUG_BASE 0xE0042000U /*!< Debug MCU registers base address */ @@ -10537,4 +10532,4 @@ typedef struct #endif /* __AT32F415Rx_H */ -/*********************** (C) COPYRIGHT Artery Technologies *****END OF FILE****/ +/*********************** (C) COPYRIGHT Artery Technology *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ArteryTek/AT32F415/system_at32f415.h b/os/common/ext/CMSIS/ArteryTek/AT32F415/system_at32f415.h index e6a798bae5..9be1d33002 100644 --- a/os/common/ext/CMSIS/ArteryTek/AT32F415/system_at32f415.h +++ b/os/common/ext/CMSIS/ArteryTek/AT32F415/system_at32f415.h @@ -109,4 +109,4 @@ extern void SystemCoreClockUpdate(void); * @} */ -/*********************** (C) COPYRIGHT Artery Technologies *****END OF FILE****/ +/*********************** (C) COPYRIGHT Artery Technology *****END OF FILE****/ diff --git a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint1.inc b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint1.inc index e33a9e57b8..cad5ad33b9 100644 --- a/os/hal/ports/AT32/LLD/EXINTv1/at32_exint1.inc +++ b/os/hal/ports/AT32/LLD/EXINTv1/at32_exint1.inc @@ -82,7 +82,7 @@ OSAL_IRQ_HANDLER(AT32_EXINT1_HANDLER) { OSAL_IRQ_PROLOGUE(); - extiGetAndClearGroup1(1U << 1, intsts); + exintGetAndClearGroup1(1U << 1, intsts); exint_serve_irq(intsts, 1); diff --git a/os/hal/ports/AT32/LLD/OTGv1/at32_otg.h b/os/hal/ports/AT32/LLD/OTGv1/at32_otg.h index 5f670e430d..ba9c2fd97d 100644 --- a/os/hal/ports/AT32/LLD/OTGv1/at32_otg.h +++ b/os/hal/ports/AT32/LLD/OTGv1/at32_otg.h @@ -43,13 +43,14 @@ typedef struct { volatile uint32_t HCCHAR; /**< @brief Host channel characteristics register. */ - volatile uint32_t resvd8; + volatile uint32_t HCSPLT; /**< @brief Host channel split register. */ volatile uint32_t HCINT; /**< @brief Host channel interrupt register.*/ volatile uint32_t HCINTMSK; /**< @brief Host channel interrupt mask register. */ volatile uint32_t HCTSIZ; /**< @brief Host channel transfer size register. */ - volatile uint32_t resvd14; + volatile uint32_t HCDMA; /**< @brief Host channel DMA address + register. */ volatile uint32_t resvd18; volatile uint32_t resvd1c; } at32_otg_host_chn_t; @@ -66,7 +67,8 @@ typedef struct { volatile uint32_t resvdC; volatile uint32_t DIEPTSIZ; /**< @brief Device IN endpoint transfer size register. */ - volatile uint32_t resvd14; + volatile uint32_t DIEPDMA; /**< @brief Device IN endpoint DMA address + register. */ volatile uint32_t DTXFSTS; /**< @brief Device IN endpoint transmit FIFO status register. */ volatile uint32_t resvd1C; @@ -84,7 +86,8 @@ typedef struct { volatile uint32_t resvdC; volatile uint32_t DOEPTSIZ; /**< @brief Device OUT endpoint transfer size register. */ - volatile uint32_t resvd14; + volatile uint32_t DOEPDMA; /**< @brief Device OUT endpoint DMA address + register. */ volatile uint32_t resvd18; volatile uint32_t resvd1C; } at32_otg_out_ep_t; @@ -107,12 +110,12 @@ typedef struct { volatile uint32_t GRXFSIZ; /**< @brief Receive FIFO size register. */ volatile uint32_t DIEPTXF0; /**< @brief Endpoint 0 transmit FIFO size register. */ - volatile uint32_t HNPTXSTS; /**< @brief Non-periodic transmit FIFO/queue - status register. */ + volatile uint32_t GNPTXSTS; /**< @brief Non-periodic TxFIFO size/request + queue status register. */ volatile uint32_t resvd30; volatile uint32_t resvd34; - volatile uint32_t GCCFG; /**< @brief General core configuration. */ - volatile uint32_t CID; /**< @brief Core ID register. */ + volatile uint32_t GCCFG; /**< @brief General controller config. */ + volatile uint32_t GUID; /**< @brief Controller ID register. */ volatile uint32_t resvd58[48]; volatile uint32_t HPTXFSIZ; /**< @brief Host periodic transmit FIFO size register. */ @@ -150,17 +153,23 @@ typedef struct { mask register. */ volatile uint32_t resvd820; volatile uint32_t resvd824; - volatile uint32_t DVBUSDIS; /**< @brief Device VBUS discharge time - register. */ - volatile uint32_t DVBUSPULSE; /**< @brief Device VBUS pulsing time - register. */ + volatile uint32_t resvd828; + volatile uint32_t resvd82C; volatile uint32_t resvd830; volatile uint32_t DIEPEMPMSK; /**< @brief Device IN endpoint FIFO empty interrupt mask register. */ - volatile uint32_t resvd838; - volatile uint32_t resvd83C; - volatile uint32_t resvd840[16]; - volatile uint32_t resvd880[16]; + volatile uint32_t DEACHINT; /**< @brief Device all endpoints interrupt + register. */ + volatile uint32_t DEACHINTMSK; /**< @brief Device all endpoints interrupt + mask register. */ + volatile uint32_t resvd840; + volatile uint32_t DIEPEACHMSK1; /**< @brief Device IN endpoint 1 + interrupt mask register. */ + volatile uint32_t resvd848[14]; + volatile uint32_t resvd880; + volatile uint32_t DOEPEACHMSK1; /**< @brief Device OUT endpoint 1 + interrupt mask register. */ + volatile uint32_t resvd888[14]; volatile uint32_t resvd8C0[16]; at32_otg_in_ep_t ie[16]; /**< @brief Input endpoints. */ at32_otg_out_ep_t oe[16]; /**< @brief Output endpoints. */ @@ -175,74 +184,50 @@ typedef struct { * @name GOTGCTL register bit definitions * @{ */ -#define GOTGCTL_BSVLD (1U << 19) /**< B-Session Valid. */ -#define GOTGCTL_ASVLD (1U << 18) /**< A-Session Valid. */ -#define GOTGCTL_DBCT (1U << 17) /**< Long/Short debounce time. */ -#define GOTGCTL_CIDSTS (1U << 16) /**< Connector ID status. */ -#define GOTGCTL_EHEN (1U << 12) -#define GOTGCTL_DHNPEN (1U << 11) /**< Device HNP enabled. */ -#define GOTGCTL_HSHNPEN (1U << 10) /**< Host Set HNP enable. */ -#define GOTGCTL_HNPRQ (1U << 9) /**< HNP request. */ -#define GOTGCTL_HNGSCS (1U << 8) /**< Host negotiation success. */ -#define GOTGCTL_BVALOVAL (1U << 7) -#define GOTGCTL_BVALOEN (1U << 6) -#define GOTGCTL_AVALOVAL (1U << 5) -#define GOTGCTL_AVALOEN (1U << 4) -#define GOTGCTL_VBVALOVAL (1U << 3) -#define GOTGCTL_VBVALOEN (1U << 2) -#define GOTGCTL_SRQ (1U << 1) /**< Session request. */ -#define GOTGCTL_SRQSCS (1U << 0) /**< Session request success. */ +#define GOTGCTL_CURMOD (1U << 21) /**< Current mode of operation. */ +#define GOTGCTL_CONIDSTS (1U << 16) /**< Connector ID status. */ /** @} */ /** * @name GOTGINT register bit definitions * @{ */ -#define GOTGINT_DBCDNE (1U << 19) /**< Debounce done. */ -#define GOTGINT_ADTOCHG (1U << 18) /**< A-Device timeout change. */ -#define GOTGINT_HNGDET (1U << 17) /**< Host negotiation detected. */ -#define GOTGINT_HNSSCHG (1U << 9) /**< Host negotiation success - status change. */ -#define GOTGINT_SRSSCHG (1U << 8) /**< Session request success - status change. */ -#define GOTGINT_SEDET (1U << 2) /**< Session end detected. */ +#define GOTGINT_SESENDDET (1U << 2) /**< Session end detected. */ /** @} */ /** * @name GAHBCFG register bit definitions * @{ */ -#define GAHBCFG_PTXFELVL (1U << 8) /**< Periodic TxFIFO empty +#define GAHBCFG_PTXFEMPLVL (1U << 8) /**< Periodic TxFIFO empty level. */ -#define GAHBCFG_TXFELVL (1U << 7) /**< Non-periodic TxFIFO empty +#define GAHBCFG_NPTXFEMPLVL (1U << 7) /**< Non-periodic TxFIFO empty level. */ #define GAHBCFG_DMAEN (1U << 5) /**< DMA enable (HS only). */ #define GAHBCFG_HBSTLEN_MASK (15U << 1) /**< Burst length/type mask (HS only). */ #define GAHBCFG_HBSTLEN(n) ((n) << 1) /**< Burst length/type (HS only). */ -#define GAHBCFG_GINTMSK (1U << 0) /**< Global interrupt mask. */ +#define GAHBCFG_GLBINTMSK (1U << 0) /**< Global interrupt mask. */ /** @} */ /** * @name GUSBCFG register bit definitions * @{ */ -#define GUSBCFG_CTXPKT (1U << 31) /**< Corrupt Tx packet. */ -#define GUSBCFG_FDMOD (1U << 30) /**< Force Device Mode. */ -#define GUSBCFG_FHMOD (1U << 29) /**< Force Host Mode. */ -#define GUSBCFG_TRDT_MASK (15U << 10) /**< USB Turnaround time field +#define GUSBCFG_COTXPKT (1U << 31) /**< Corrupt Tx packet. */ +#define GUSBCFG_FDEVMODE (1U << 30) /**< Force Device Mode. */ +#define GUSBCFG_FHSTMODE (1U << 29) /**< Force Host Mode. */ +#define GUSBCFG_USBTRDTIM_MASK (15U << 10) /**< USB Turnaround time field mask. */ -#define GUSBCFG_TRDT(n) ((n) << 10) /**< USB Turnaround time field +#define GUSBCFG_USBTRDTIM(n) ((n) << 10) /**< USB Turnaround time field value. */ -#define GUSBCFG_HNPCAP (1U << 9) /**< HNP-Capable. */ -#define GUSBCFG_SRPCAP (1U << 8) /**< SRP-Capable. */ #define GUSBCFG_PHYSEL (1U << 6) /**< USB 2.0 High-Speed PHY or USB 1.1 Full-Speed serial transceiver Select. */ -#define GUSBCFG_TOCAL_MASK (7U << 0) /**< HS/FS timeout calibration +#define GUSBCFG_TOUTCAL_MASK (7U << 0) /**< HS/FS timeout calibration field mask. */ -#define GUSBCFG_TOCAL(n) ((n) << 0) /**< HS/FS timeout calibration +#define GUSBCFG_TOUTCAL(n) ((n) << 0) /**< HS/FS timeout calibration field value. */ /** @} */ @@ -250,14 +235,15 @@ typedef struct { * @name GRSTCTL register bit definitions * @{ */ -#define GRSTCTL_AHBIDL (1U << 31) /**< AHB Master Idle. */ +#define GRSTCTL_AHBIDLE (1U << 31) /**< AHB master Idle. */ #define GRSTCTL_TXFNUM_MASK (31U << 6) /**< TxFIFO number field mask. */ #define GRSTCTL_TXFNUM(n) ((n) << 6) /**< TxFIFO number field value. */ #define GRSTCTL_TXFFLSH (1U << 5) /**< TxFIFO flush. */ #define GRSTCTL_RXFFLSH (1U << 4) /**< RxFIFO flush. */ -#define GRSTCTL_FCRST (1U << 2) /**< Host frame counter reset. */ -#define GRSTCTL_HSRST (1U << 1) /**< HClk soft reset. */ -#define GRSTCTL_CSRST (1U << 0) /**< Core soft reset. */ +#define GRSTCTL_FRMCNTRST (1U << 2) /**< Host frame counter reset. */ +#define GRSTCTL_PIUSFTRST (1U << 1) /**< PIU FS dedicated control + soft reset. */ +#define GRSTCTL_CSFTRST (1U << 0) /**< Controller soft reset. */ /** @} */ /** @@ -266,86 +252,84 @@ typedef struct { */ #define GINTSTS_WKUPINT (1U << 31) /**< Resume/Remote wakeup detected interrupt. */ -#define GINTSTS_SRQINT (1U << 30) /**< Session request/New session - detected interrupt. */ -#define GINTSTS_DISCINT (1U << 29) /**< Disconnect detected +#define GINTSTS_DISCONINT (1U << 29) /**< Disconnect detected interrupt. */ -#define GINTSTS_CIDSCHG (1U << 28) /**< Connector ID status change.*/ -#define GINTSTS_PTXFE (1U << 26) /**< Periodic TxFIFO empty. */ -#define GINTSTS_HCINT (1U << 25) /**< Host channels interrupt. */ -#define GINTSTS_HPRTINT (1U << 24) /**< Host port interrupt. */ -#define GINTSTS_IPXFR (1U << 21) /**< Incomplete periodic +#define GINTSTS_CONIDSCHG (1U << 28) /**< Connector ID status change.*/ +#define GINTSTS_PTXFEMP (1U << 26) /**< Periodic TxFIFO empty. */ +#define GINTSTS_HCHINT (1U << 25) /**< Host channels interrupt. */ +#define GINTSTS_PRTINT (1U << 24) /**< Host port interrupt. */ +#define GINTSTS_INCOMPIP (1U << 21) /**< Incomplete periodic transfer. */ -#define GINTSTS_IISOOXFR (1U << 21) /**< Incomplete isochronous OUT +#define GINTSTS_INCOMPISOOUT (1U << 21) /**< Incomplete isochronous OUT transfer. */ -#define GINTSTS_IISOIXFR (1U << 20) /**< Incomplete isochronous IN +#define GINTSTS_INCOMPISOIN (1U << 20) /**< Incomplete isochronous IN transfer. */ -#define GINTSTS_OEPINT (1U << 19) /**< OUT endpoints interrupt. */ -#define GINTSTS_IEPINT (1U << 18) /**< IN endpoints interrupt. */ +#define GINTSTS_OEPTINT (1U << 19) /**< OUT endpoints interrupt. */ +#define GINTSTS_IEPTINT (1U << 18) /**< IN endpoints interrupt. */ #define GINTSTS_EOPF (1U << 15) /**< End of periodic frame interrupt. */ -#define GINTSTS_ISOODRP (1U << 14) /**< Isochronous OUT packet +#define GINTSTS_ISOOUTDROP (1U << 14) /**< Isochronous OUT packet dropped interrupt. */ -#define GINTSTS_ENUMDNE (1U << 13) /**< Enumeration done. */ +#define GINTSTS_ENUMDONE (1U << 13) /**< Enumeration done. */ #define GINTSTS_USBRST (1U << 12) /**< USB reset. */ #define GINTSTS_USBSUSP (1U << 11) /**< USB suspend. */ -#define GINTSTS_ESUSP (1U << 10) /**< Early suspend. */ -#define GINTSTS_GONAKEFF (1U << 7) /**< Global OUT NAK effective. */ -#define GINTSTS_GINAKEFF (1U << 6) /**< Global IN non-periodic NAK +#define GINTSTS_ERLYSUSP (1U << 10) /**< Early suspend. */ +#define GINTSTS_GOUTNAKEFF (1U << 7) /**< Global OUT NAK effective. */ +#define GINTSTS_GINNAKEFF (1U << 6) /**< Global IN non-periodic NAK effective. */ -#define GINTSTS_NPTXFE (1U << 5) /**< Non-periodic TxFIFO empty. */ +#define GINTSTS_NPTXFEMP (1U << 5) /**< Non-periodic TxFIFO empty. */ #define GINTSTS_RXFLVL (1U << 4) /**< RxFIFO non-empty. */ #define GINTSTS_SOF (1U << 3) /**< Start of frame. */ #define GINTSTS_OTGINT (1U << 2) /**< OTG interrupt. */ -#define GINTSTS_MMIS (1U << 1) /**< Mode Mismatch interrupt. */ -#define GINTSTS_CMOD (1U << 0) /**< Current mode of operation. */ +#define GINTSTS_MODEMIS (1U << 1) /**< Mode mismatch interrupt. */ +#define GINTSTS_CURMOD (1U << 0) /**< Current mode of operation. */ /** @} */ /** * @name GINTMSK register bit definitions * @{ */ -#define GINTMSK_WKUM (1U << 31) /**< Resume/remote wakeup +#define GINTMSK_WKUPINTMSK (1U << 31) /**< Resume/remote wakeup detected interrupt mask. */ -#define GINTMSK_SRQM (1U << 30) /**< Session request/New session - detected interrupt mask. */ -#define GINTMSK_DISCM (1U << 29) /**< Disconnect detected +#define GINTMSK_DISCONINTMSK (1U << 29) /**< Disconnect detected interrupt mask. */ -#define GINTMSK_CIDSCHGM (1U << 28) /**< Connector ID status change +#define GINTMSK_CONIDSCHGMSK (1U << 28) /**< Connector ID status change mask. */ -#define GINTMSK_PTXFEM (1U << 26) /**< Periodic TxFIFO empty mask.*/ -#define GINTMSK_HCM (1U << 25) /**< Host channels interrupt +#define GINTMSK_PTXFEMPMSK (1U << 26) /**< Periodic TxFIFO empty mask.*/ +#define GINTMSK_HCHINTMSK (1U << 25) /**< Host channels interrupt mask. */ -#define GINTMSK_HPRTM (1U << 24) /**< Host port interrupt mask. */ -#define GINTMSK_IPXFRM (1U << 21) /**< Incomplete periodic +#define GINTMSK_PRTINTMSK (1U << 24) /**< Host port interrupt mask. */ +#define GINTMSK_INCOMPIPMSK (1U << 21) /**< Incomplete periodic transfer mask. */ -#define GINTMSK_IISOOXFRM (1U << 21) /**< Incomplete isochronous OUT +#define GINTMSK_INCOMPISOOUTMSK (1U << 21) /**< Incomplete isochronous OUT transfer mask. */ -#define GINTMSK_IISOIXFRM (1U << 20) /**< Incomplete isochronous IN +#define GINTMSK_INCOMISOINMSK (1U << 20) /**< Incomplete isochronous IN transfer mask. */ -#define GINTMSK_OEPM (1U << 19) /**< OUT endpoints interrupt +#define GINTMSK_OEPTINTMSK (1U << 19) /**< OUT endpoints interrupt mask. */ -#define GINTMSK_IEPM (1U << 18) /**< IN endpoints interrupt +#define GINTMSK_IEPTINTMSK (1U << 18) /**< IN endpoints interrupt mask. */ -#define GINTMSK_EOPFM (1U << 15) /**< End of periodic frame +#define GINTMSK_EOPFMSK (1U << 15) /**< End of periodic frame interrupt mask. */ -#define GINTMSK_ISOODRPM (1U << 14) /**< Isochronous OUT packet +#define GINTMSK_ISOOUTDROPMSK (1U << 14) /**< Isochronous OUT packet dropped interrupt mask. */ -#define GINTMSK_ENUMDNEM (1U << 13) /**< Enumeration done mask. */ -#define GINTMSK_USBRSTM (1U << 12) /**< USB reset mask. */ -#define GINTMSK_USBSUSPM (1U << 11) /**< USB suspend mask. */ -#define GINTMSK_ESUSPM (1U << 10) /**< Early suspend mask. */ -#define GINTMSK_GONAKEFFM (1U << 7) /**< Global OUT NAK effective +#define GINTMSK_ENUMDONEMSK (1U << 13) /**< Enumeration done mask. */ +#define GINTMSK_USBRSTMSK (1U << 12) /**< USB reset mask. */ +#define GINTMSK_USBSUSPMSK (1U << 11) /**< USB suspend interrupt + mask. */ +#define GINTMSK_ERLYSUSPMSK (1U << 10) /**< Early suspend interrupt mask. */ -#define GINTMSK_GINAKEFFM (1U << 6) /**< Global non-periodic IN NAK +#define GINTMSK_GOUTNAKEFFMSK (1U << 7) /**< Global OUT NAK effective + mask. */ +#define GINTMSK_GINNAKEFFMSK (1U << 6) /**< Global non-periodic IN NAK effective mask. */ -#define GINTMSK_NPTXFEM (1U << 5) /**< Non-periodic TxFIFO empty +#define GINTMSK_NPTXFEMPMSK (1U << 5) /**< Non-periodic TxFIFO empty mask. */ -#define GINTMSK_RXFLVLM (1U << 4) /**< Receive FIFO non-empty +#define GINTMSK_RXFLVLMSK (1U << 4) /**< Receive FIFO non-empty mask. */ -#define GINTMSK_SOFM (1U << 3) /**< Start of (micro)frame mask.*/ -#define GINTMSK_OTGM (1U << 2) /**< OTG interrupt mask. */ -#define GINTMSK_MMISM (1U << 1) /**< Mode Mismatch interrupt +#define GINTMSK_SOFMSK (1U << 3) /**< Start of Frame mask. */ +#define GINTMSK_OTGINTMSK (1U << 2) /**< OTG interrupt mask. */ +#define GINTMSK_MODEMISMSK (1U << 1) /**< Mode mismatch interrupt mask. */ /** @} */ @@ -366,8 +350,8 @@ typedef struct { #define GRXSTSR_BCNT(n) ((n) << 4) /**< Byte count value. */ #define GRXSTSR_CHNUM_MASK (15U << 0) /**< Channel number mask. */ #define GRXSTSR_CHNUM(n) ((n) << 0) /**< Channel number value. */ -#define GRXSTSR_EPNUM_MASK (15U << 0) /**< Endpoint number mask. */ -#define GRXSTSR_EPNUM(n) ((n) << 0) /**< Endpoint number value. */ +#define GRXSTSR_EPTNUM_MASK (15U << 0) /**< Endpoint number mask. */ +#define GRXSTSR_EPTNUM(n) ((n) << 0) /**< Endpoint number value. */ /** @} */ /** @@ -388,61 +372,60 @@ typedef struct { #define GRXSTSP_BCNT(n) ((n) << 4) /**< Byte count value. */ #define GRXSTSP_CHNUM_MASK (15U << 0) /**< Channel number mask. */ #define GRXSTSP_CHNUM(n) ((n) << 0) /**< Channel number value. */ -#define GRXSTSP_EPNUM_MASK (15U << 0) /**< Endpoint number mask. */ -#define GRXSTSP_EPNUM_OFF 0 /**< Endpoint number offset. */ -#define GRXSTSP_EPNUM(n) ((n) << 0) /**< Endpoint number value. */ +#define GRXSTSP_EPTNUM_MASK (15U << 0) /**< Endpoint number mask. */ +#define GRXSTSP_EPTNUM_OFF 0 /**< Endpoint number offset. */ +#define GRXSTSP_EPTNUM(n) ((n) << 0) /**< Endpoint number value. */ /** @} */ /** * @name GRXFSIZ register bit definitions * @{ */ -#define GRXFSIZ_RXFD_MASK (0xFFFFU << 0) /**< RxFIFO depth mask. */ -#define GRXFSIZ_RXFD(n) ((n) << 0) /**< RxFIFO depth value. */ +#define GRXFSIZ_RXFDEP_MASK (0xFFFFU << 0) /**< RxFIFO depth mask. */ +#define GRXFSIZ_RXFDEP(n) ((n) << 0) /**< RxFIFO depth value. */ /** @} */ /** * @name DIEPTXFx register bit definitions * @{ */ -#define DIEPTXF_INEPTXFD_MASK (0xFFFFU << 16) /**< IN endpoint TxFIFO depth - mask. */ -#define DIEPTXF_INEPTXFD(n) ((n) << 16) /**< IN endpoint TxFIFO depth - value. */ -#define DIEPTXF_INEPTXSA_MASK (0xFFFFU << 0) /**< IN endpoint FIFOx transmit - RAM start address mask.*/ -#define DIEPTXF_INEPTXSA(n) ((n) << 0) /**< IN endpoint FIFOx transmit - RAM start address value.*/ +#define DIEPTXF_INEPTXFDEP_MASK (0xFFFFU << 16) /**< IN endpoint TxFIFO + depth mask. */ +#define DIEPTXF_INEPTXFDEP(n) ((n) << 16) /**< IN endpoint TxFIFO depth + depth value. */ +#define DIEPTXF_INEPTXFSTADDR_MASK (0xFFFFU << 0) /**< IN endpoint FIFOx + transmit SRAM start + address mask. */ +#define DIEPTXF_INEPTXFSTADDR(n) ((n) << 0) /**< IN endpoint FIFOx + transmit SRAM start + address mask. */ /** @} */ /** * @name GCCFG register bit definitions * @{ */ -/* Definitions for stepping 1.*/ -#define GCCFG_NOVBUSSENS (1U << 21) /**< VBUS sensing disable. */ +#define GCCFG_WAIT_CLK_RCV (1U << 22) /**< Wait clksoure recover (HS + only). */ +#define GCCFG_VBUSIG (1U << 21) /**< VBUS ignored. */ #define GCCFG_SOFOUTEN (1U << 20) /**< SOF output enable. */ -#define GCCFG_VBUSBSEN (1U << 19) /**< Enable the VBUS sensing "B" - device. */ -#define GCCFG_VBUSASEN (1U << 18) /**< Enable the VBUS sensing "A" - device. */ - -/* Definitions for stepping 2.*/ -#define GCCFG_VBDEN (1U << 21) /**< VBUS sensing enable. */ -#define GCCFG_PWRDWN (1U << 16) /**< Power down. */ +#define GCCFG_BVALIDSESEN (1U << 19) /**< B valid sensing enable. */ +#define GCCFG_AVALIDSESEN (1U << 18) /**< A valid sensing enable. */ +#define GCCFG_LP_MODE (1U << 17) /**< Low-power mode. */ +#define GCCFG_PWRDOWN (1U << 16) /**< Power down. */ /** @} */ /** * @name HPTXFSIZ register bit definitions * @{ */ -#define HPTXFSIZ_PTXFD_MASK (0xFFFFU << 16) /**< Host periodic TxFIFO +#define HPTXFSIZ_PTXFSIZE_MASK (0xFFFFU << 16) /**< Host periodic TxFIFO depth mask. */ -#define HPTXFSIZ_PTXFD(n) ((n) << 16) /**< Host periodic TxFIFO +#define HPTXFSIZ_PTXFSIZE(n) ((n) << 16) /**< Host periodic TxFIFO depth value. */ -#define HPTXFSIZ_PTXSA_MASK (0xFFFFU << 0) /**< Host periodic TxFIFO - Start address mask. */ -#define HPTXFSIZ_PTXSA(n) ((n) << 0) /**< Host periodic TxFIFO +#define HPTXFSIZ_PTXFSTADDR_MASK (0xFFFFU << 0) /**< Host periodic TxFIFO + start address mask. */ +#define HPTXFSIZ_PTXFSTADDR(n) ((n) << 0) /**< Host periodic TxFIFO start address value. */ /** @} */ @@ -450,12 +433,12 @@ typedef struct { * @name HCFG register bit definitions * @{ */ -#define HCFG_FSLSS (1U << 2) /**< FS- and LS-only support. */ -#define HCFG_FSLSPCS_MASK (3U << 0) /**< FS/LS PHY clock select +#define HCFG_FSLSSUPP (1U << 2) /**< FS- and LS-only support. */ +#define HCFG_FSLSPCLKSEL_MASK (3U << 0) /**< FS/LS PHY clock select mask. */ -#define HCFG_FSLSPCS_48 (1U << 0) /**< PHY clock is running at +#define HCFG_FSLSPCLKSEL_48 (1U << 0) /**< PHY clock is running at 48 MHz. */ -#define HCFG_FSLSPCS_6 (2U << 0) /**< PHY clock is running at +#define HCFG_FSLSPCLKSEL_6 (2U << 0) /**< PHY clock is running at 6 MHz. */ /** @} */ @@ -463,17 +446,17 @@ typedef struct { * @name HFIR register bit definitions * @{ */ -#define HFIR_FRIVL_MASK (0xFFFFU << 0) /**< Frame interval mask. */ -#define HFIR_FRIVL(n) ((n) << 0) /**< Frame interval value. */ +#define HFIR_FRINT_MASK (0xFFFFU << 0) /**< Frame interval mask. */ +#define HFIR_FRINT(n) ((n) << 0) /**< Frame interval value. */ /** @} */ /** * @name HFNUM register bit definitions * @{ */ -#define HFNUM_FTREM_MASK (0xFFFFU << 16) /**< Frame time Remaining +#define HFNUM_FTREM_MASK (0xFFFFU << 16) /**< Frame time remaining mask. */ -#define HFNUM_FTREM(n) ((n) << 16) /**< Frame time Remaining +#define HFNUM_FTREM(n) ((n) << 16) /**< Frame time remaining value. */ #define HFNUM_FRNUM_MASK (0xFFFFU << 0) /**< Frame number mask. */ #define HFNUM_FRNUM(n) ((n) << 0) /**< Frame number value. */ @@ -489,17 +472,17 @@ typedef struct { #define HPTXSTS_PTXQTOP(n) ((n) << 24) /**< Top of the periodic transmit request queue value. */ -#define HPTXSTS_PTXQSAV_MASK (0xFF<< 16) /**< Periodic transmit request - queue Space Available +#define HPTXSTS_PTXQSPCAVAIL_MASK (0xFF<< 16) /**< Periodic transmit request + queue space available mask. */ -#define HPTXSTS_PTXQSAV(n) ((n) << 16) /**< Periodic transmit request - queue Space Available +#define HPTXSTS_PTXQSPCAVAIL(n) ((n) << 16) /**< Periodic transmit request + queue space available value. */ -#define HPTXSTS_PTXFSAVL_MASK (0xFFFF<< 0) /**< Periodic transmit Data - FIFO Space Available +#define HPTXSTS_PTXFSPCAVAIL_MASK (0xFFFF<< 0) /**< Periodic transmit data + FIFO space available mask. */ -#define HPTXSTS_PTXFSAVL(n) ((n) << 0) /**< Periodic transmit Data - FIFO Space Available +#define HPTXSTS_PTXFSPCAVAIL(n) ((n) << 0) /**< Periodic transmit data + FIFO space available value. */ /** @} */ @@ -517,9 +500,9 @@ typedef struct { * @name HAINTMSK register bit definitions * @{ */ -#define HAINTMSK_HAINTM_MASK (0xFFFFU << 0) /**< Channel interrupt mask +#define HAINTMSK_HAINTMSK_MASK (0xFFFFU << 0) /**< Channel interrupt mask mask. */ -#define HAINTMSK_HAINTM(n) ((n) << 0) /**< Channel interrupt mask +#define HAINTMSK_HAINTMSK(n) ((n) << 0) /**< Channel interrupt mask value. */ /** @} */ @@ -527,24 +510,24 @@ typedef struct { * @name HPRT register bit definitions * @{ */ -#define HPRT_PSPD_MASK (3U << 17) /**< Port speed mask. */ -#define HPRT_PSPD_FS (1U << 17) /**< Full speed value. */ -#define HPRT_PSPD_LS (2U << 17) /**< Low speed value. */ -#define HPRT_PTCTL_MASK (15U << 13) /**< Port Test control mask. */ -#define HPRT_PTCTL(n) ((n) << 13) /**< Port Test control value. */ -#define HPRT_PPWR (1U << 12) /**< Port power. */ -#define HPRT_PLSTS_MASK (3U << 11) /**< Port Line status mask. */ -#define HPRT_PLSTS_DM (1U << 11) /**< Logic level of D-. */ -#define HPRT_PLSTS_DP (1U << 10) /**< Logic level of D+. */ -#define HPRT_PRST (1U << 8) /**< Port reset. */ -#define HPRT_PSUSP (1U << 7) /**< Port suspend. */ -#define HPRT_PRES (1U << 6) /**< Port Resume. */ -#define HPRT_POCCHNG (1U << 5) /**< Port overcurrent change. */ -#define HPRT_POCA (1U << 4) /**< Port overcurrent active. */ -#define HPRT_PENCHNG (1U << 3) /**< Port enable/disable change.*/ -#define HPRT_PENA (1U << 2) /**< Port enable. */ -#define HPRT_PCDET (1U << 1) /**< Port Connect detected. */ -#define HPRT_PCSTS (1U << 0) /**< Port connect status. */ +#define HPRT_PRTSPD_MASK (3U << 17) /**< Port speed mask. */ +#define HPRT_PRTSPD_FS (1U << 17) /**< Full speed value. */ +#define HPRT_PRTSPD_LS (2U << 17) /**< Low speed value. */ +#define HPRT_PRTTSTCTL_MASK (15U << 13) /**< Port test control mask. */ +#define HPRT_PRTTSTCTL(n) ((n) << 13) /**< Port test control value. */ +#define HPRT_PRTPWR (1U << 12) /**< Port power. */ +#define HPRT_PRTLNSTS_MASK (3U << 11) /**< Port line status mask. */ +#define HPRT_PRTLNSTS_DM (1U << 11) /**< Logic level of D-. */ +#define HPRT_PRTLNSTS_DP (1U << 10) /**< Logic level of D+. */ +#define HPRT_PRTRST (1U << 8) /**< Port reset. */ +#define HPRT_PRTSUSP (1U << 7) /**< Port suspend. */ +#define HPRT_PRTRES (1U << 6) /**< Port resume. */ +#define HPRT_PRTOVRCCHNG (1U << 5) /**< Port overcurrent change. */ +#define HPRT_PRTOVRCACT (1U << 4) /**< Port overcurrent active. */ +#define HPRT_PRTENCHNG (1U << 3) /**< Port enable/disable change.*/ +#define HPRT_PRTENA (1U << 2) /**< Port enable. */ +#define HPRT_PRTCONDET (1U << 1) /**< Port connect detected. */ +#define HPRT_PRTCONSTS (1U << 0) /**< Port connect status. */ /** @} */ /** @@ -552,22 +535,22 @@ typedef struct { * @{ */ #define HCCHAR_CHENA (1U << 31) /**< Channel enable. */ -#define HCCHAR_CHDIS (1U << 30) /**< Channel Disable. */ +#define HCCHAR_CHDIS (1U << 30) /**< Channel disable. */ #define HCCHAR_ODDFRM (1U << 29) /**< Odd frame. */ -#define HCCHAR_DAD_MASK (0x7FU << 22) /**< Device Address mask. */ -#define HCCHAR_DAD(n) ((n) << 22) /**< Device Address value. */ -#define HCCHAR_MCNT_MASK (3U << 20) /**< Multicount mask. */ -#define HCCHAR_MCNT(n) ((n) << 20) /**< Multicount value. */ -#define HCCHAR_EPTYP_MASK (3U << 18) /**< Endpoint type mask. */ -#define HCCHAR_EPTYP(n) ((n) << 18) /**< Endpoint type value. */ -#define HCCHAR_EPTYP_CTL (0U << 18) /**< Control endpoint value. */ -#define HCCHAR_EPTYP_ISO (1U << 18) /**< Isochronous endpoint value.*/ -#define HCCHAR_EPTYP_BULK (2U << 18) /**< Bulk endpoint value. */ -#define HCCHAR_EPTYP_INTR (3U << 18) /**< Interrupt endpoint value. */ -#define HCCHAR_LSDEV (1U << 17) /**< Low-Speed device. */ -#define HCCHAR_EPDIR (1U << 15) /**< Endpoint direction. */ -#define HCCHAR_EPNUM_MASK (15U << 11) /**< Endpoint number mask. */ -#define HCCHAR_EPNUM(n) ((n) << 11) /**< Endpoint number value. */ +#define HCCHAR_DEVADDR_MASK (0x7FU << 22) /**< Device address mask. */ +#define HCCHAR_DEVADDR(n) ((n) << 22) /**< Device address value. */ +#define HCCHAR_MC_MASK (3U << 20) /**< Multi count mask. */ +#define HCCHAR_MC(n) ((n) << 20) /**< Multi count value. */ +#define HCCHAR_EPTYPE_MASK (3U << 18) /**< Endpoint type mask. */ +#define HCCHAR_EPTYPE(n) ((n) << 18) /**< Endpoint type value. */ +#define HCCHAR_EPTYPE_CTL (0U << 18) /**< Control transfer value. */ +#define HCCHAR_EPTYPE_ISO (1U << 18) /**< Isochronous transfer value.*/ +#define HCCHAR_EPTYPE_BULK (2U << 18) /**< Bulk transfer value. */ +#define HCCHAR_EPTYPE_INTR (3U << 18) /**< Interrupt transfer value. */ +#define HCCHAR_LSPDDEV (1U << 17) /**< Low-speed device. */ +#define HCCHAR_EPTDIR (1U << 15) /**< Endpoint direction. */ +#define HCCHAR_EPTNUM_MASK (15U << 11) /**< Endpoint number mask. */ +#define HCCHAR_EPTNUM(n) ((n) << 11) /**< Endpoint number value. */ #define HCCHAR_MPS_MASK (0x7FFU << 0) /**< Maximum packet size mask.*/ #define HCCHAR_MPS(n) ((n) << 0) /**< Maximum packet size value. */ /** @} */ @@ -576,10 +559,10 @@ typedef struct { * @name HCINT register bit definitions * @{ */ -#define HCINT_DTERR (1U << 10) /**< Data toggle error. */ -#define HCINT_FRMOR (1U << 9) /**< Frame overrun. */ -#define HCINT_BBERR (1U << 8) /**< Babble error. */ -#define HCINT_TRERR (1U << 7) /**< Transaction Error. */ +#define HCINT_DTGLERR (1U << 10) /**< Data toggle error. */ +#define HCINT_FRMOVRUN (1U << 9) /**< Frame overrun. */ +#define HCINT_BBLERR (1U << 8) /**< Babble error. */ +#define HCINT_XACTERR (1U << 7) /**< Transaction error. */ #define HCINT_ACK (1U << 5) /**< ACK response received/transmitted interrupt. */ @@ -587,66 +570,67 @@ typedef struct { interrupt. */ #define HCINT_STALL (1U << 3) /**< STALL response received interrupt. */ -#define HCINT_AHBERR (1U << 2) /**< AHB error interrupt. */ -#define HCINT_CHH (1U << 1) /**< Channel halted. */ -#define HCINT_XFRC (1U << 0) /**< Transfer completed. */ +#define HCINT_AHBERR (1U << 2) /**< AHB error interrupt + (HS only). */ +#define HCINT_CHHLTD (1U << 1) /**< Channel halted. */ +#define HCINT_XFERC (1U << 0) /**< Transfer completed. */ /** @} */ /** * @name HCINTMSK register bit definitions * @{ */ -#define HCINTMSK_DTERRM (1U << 10) /**< Data toggle error mask. */ -#define HCINTMSK_FRMORM (1U << 9) /**< Frame overrun mask. */ -#define HCINTMSK_BBERRM (1U << 8) /**< Babble error mask. */ -#define HCINTMSK_TRERRM (1U << 7) /**< Transaction error mask. */ -#define HCINTMSK_NYET (1U << 6) /**< NYET response received +#define HCINTMSK_DTGLERRMSK (1U << 10) /**< Data toggle error mask. */ +#define HCINTMSK_FRMOVRUNMSK (1U << 9) /**< Frame overrun mask. */ +#define HCINTMSK_BBLERRMSK (1U << 8) /**< Babble error mask. */ +#define HCINTMSK_XACTERRMSK (1U << 7) /**< Transaction error mask. */ +#define HCINTMSK_NYETMSK (1U << 6) /**< NYET response received interrupt mask. */ -#define HCINTMSK_ACKM (1U << 5) /**< ACK Response +#define HCINTMSK_ACKMSK (1U << 5) /**< ACK response received/transmitted interrupt mask. */ -#define HCINTMSK_NAKM (1U << 4) /**< NAK response received +#define HCINTMSK_NAKMSK (1U << 4) /**< NAK response received interrupt mask. */ -#define HCINTMSK_STALLM (1U << 3) /**< STALL response received +#define HCINTMSK_STALLMSK (1U << 3) /**< STALL response received interrupt mask. */ -#define HCINTMSK_AHBERRM (1U << 2) /**< AHB error interrupt mask. */ -#define HCINTMSK_CHHM (1U << 1) /**< Channel halted mask. */ -#define HCINTMSK_XFRCM (1U << 0) /**< Transfer completed mask. */ +#define HCINTMSK_AHBERRMSK (1U << 2) /**< AHB error mask (HS only). */ +#define HCINTMSK_CHHLTDMSK (1U << 1) /**< Channel halted mask. */ +#define HCINTMSK_XFERCMSK (1U << 0) /**< Transfer completed mask. */ /** @} */ /** * @name HCTSIZ register bit definitions * @{ */ -#define HCTSIZ_DPID_MASK (3U << 29) /**< PID mask. */ -#define HCTSIZ_DPID_DATA0 (0U << 29) /**< DATA0. */ -#define HCTSIZ_DPID_DATA2 (1U << 29) /**< DATA2. */ -#define HCTSIZ_DPID_DATA1 (2U << 29) /**< DATA1. */ -#define HCTSIZ_DPID_MDATA (3U << 29) /**< MDATA. */ -#define HCTSIZ_DPID_SETUP (3U << 29) /**< SETUP. */ +#define HCTSIZ_PID_MASK (3U << 29) /**< PID mask. */ +#define HCTSIZ_PID_DATA0 (0U << 29) /**< DATA0. */ +#define HCTSIZ_PID_DATA2 (1U << 29) /**< DATA2. */ +#define HCTSIZ_PID_DATA1 (2U << 29) /**< DATA1. */ +#define HCTSIZ_PID_MDATA (3U << 29) /**< MDATA. */ +#define HCTSIZ_PID_SETUP (3U << 29) /**< SETUP. */ #define HCTSIZ_PKTCNT_MASK (0x3FFU << 19) /**< Packet count mask. */ #define HCTSIZ_PKTCNT(n) ((n) << 19) /**< Packet count value. */ -#define HCTSIZ_XFRSIZ_MASK (0x7FFFFU << 0) /**< Transfer size mask. */ -#define HCTSIZ_XFRSIZ(n) ((n) << 0) /**< Transfer size value. */ +#define HCTSIZ_XFERSIZE_MASK (0x7FFFFU << 0) /**< Transfer size mask. */ +#define HCTSIZ_XFERSIZE(n) ((n) << 0) /**< Transfer size value. */ /** @} */ /** * @name DCFG register bit definitions * @{ */ -#define DCFG_PFIVL_MASK (3U << 11) /**< Periodic frame interval +#define DCFG_PERFRINT_MASK (3U << 11) /**< Periodic frame interval mask. */ -#define DCFG_PFIVL(n) ((n) << 11) /**< Periodic frame interval +#define DCFG_PERFRINT(n) ((n) << 11) /**< Periodic frame interval value. */ -#define DCFG_DAD_MASK (0x7FU << 4)/**< Device address mask. */ -#define DCFG_DAD(n) ((n) << 4) /**< Device address value. */ -#define DCFG_NZLSOHSK (1U << 2) /**< Non-Zero-Length status +#define DCFG_DEVADDR_MASK (0x7FU << 4)/**< Device address mask. */ +#define DCFG_DEVADDR(n) ((n) << 4) /**< Device address value. */ +#define DCFG_NZSTSOUTHSHK (1U << 2) /**< Non-zero-length status OUT handshake. */ -#define DCFG_DSPD_MASK (3U << 0) /**< Device speed mask. */ -#define DCFG_DSPD_HS (0U << 0) /**< High speed (USB 2.0). */ -#define DCFG_DSPD_HS_FS (1U << 0) /**< High speed (USB 2.0) in FS +#define DCFG_DEVSPD_MASK (3U << 0) /**< Device speed mask. */ +#define DCFG_DEVSPD_HS (0U << 0) /**< High speed (USB 2.0). */ +#define DCFG_DEVSPD_HS_FS (1U << 0) /**< High speed (USB 2.0) in FS mode. */ -#define DCFG_DSPD_FS11 (3U << 0) /**< Full speed (USB 1.1 +#define DCFG_DEVSPD_FS11 (3U << 0) /**< Full speed (USB 1.1 transceiver clock is 48 MHz). */ /** @} */ @@ -655,36 +639,38 @@ typedef struct { * @name DCTL register bit definitions * @{ */ -#define DCTL_POPRGDNE (1U << 11) /**< Power-on programming done. */ -#define DCTL_CGONAK (1U << 10) /**< Clear global OUT NAK. */ -#define DCTL_SGONAK (1U << 9) /**< Set global OUT NAK. */ -#define DCTL_CGINAK (1U << 8) /**< Clear global non-periodic +#define DCTL_PWROPRGDNE (1U << 11) /**< Power-on programming done. */ +#define DCTL_CGOUTNAK (1U << 10) /**< Clear global OUT NAK. */ +#define DCTL_SGOUTNAK (1U << 9) /**< Set global OUT NAK. */ +#define DCTL_CGNPINNAK (1U << 8) /**< Clear global non-periodic IN NAK. */ -#define DCTL_SGINAK (1U << 7) /**< Set global non-periodic +#define DCTL_SGNPINNAK (1U << 7) /**< Set global non-periodic IN NAK. */ -#define DCTL_TCTL_MASK (7U << 4) /**< Test control mask. */ -#define DCTL_TCTL(n) ((n) << 4 /**< Test control value. */ -#define DCTL_GONSTS (1U << 3) /**< Global OUT NAK status. */ -#define DCTL_GINSTS (1U << 2) /**< Global non-periodic IN +#define DCTL_TSTCTL_MASK (7U << 4) /**< Test control mask. */ +#define DCTL_TSTCTL(n) ((n) << 4) /**< Test control value. */ +#define DCTL_GOUTNAKSTS (1U << 3) /**< Global OUT NAK status. */ +#define DCTL_GNPINNAKSTS (1U << 2) /**< Global non-periodic IN NAK status. */ -#define DCTL_SDIS (1U << 1) /**< Soft disconnect. */ -#define DCTL_RWUSIG (1U << 0) /**< Remote wakeup signaling. */ +#define DCTL_SFTDISCON (1U << 1) /**< Software disconnect. */ +#define DCTL_RWKUPSIG (1U << 0) /**< Remote wakeup signaling. */ /** @} */ /** * @name DSTS register bit definitions * @{ */ -#define DSTS_FNSOF_MASK (0x3FFU << 8) /**< Frame number of the +#define DSTS_SOFFN_MASK (0x3FFFU << 8) /**< Frame number of the received SOF mask. */ -#define DSTS_FNSOF(n) ((n) << 8) /**< Frame number of the +#define DSTS_SOFFN(n) ((n) << 8) /**< Frame number of the received SOF value. */ -#define DSTS_FNSOF_ODD (1U << 8) /**< Frame parity of the +#define DSTS_SOFFN_ODD (1U << 8) /**< Frame parity of the received SOF value. */ -#define DSTS_EERR (1U << 3) /**< Erratic error. */ +#define DSTS_ETICERR (1U << 3) /**< Erratic error. */ #define DSTS_ENUMSPD_MASK (3U << 1) /**< Enumerated speed mask. */ #define DSTS_ENUMSPD_FS_48 (3U << 1) /**< Full speed (PHY clock is running at 48 MHz). */ +#define DSTS_ENUMSPD_FS_30_60 (1U << 1) /**< Full speed (PHY clock is + running at 30/60 MHz). */ #define DSTS_ENUMSPD_HS_480 (0U << 1) /**< High speed. */ #define DSTS_SUSPSTS (1U << 0) /**< Suspend status. */ /** @} */ @@ -693,15 +679,15 @@ typedef struct { * @name DIEPMSK register bit definitions * @{ */ -#define DIEPMSK_TXFEM (1U << 6) /**< Transmit FIFO empty mask. */ -#define DIEPMSK_INEPNEM (1U << 6) /**< IN endpoint NAK effective +#define DIEPMSK_TXFIFOUDRMSK (1U << 8) /**< FIFO underrun mask. */ +#define DIEPMSK_INEPTNAKMSK (1U << 6) /**< IN endpoint NAK effective mask. */ -#define DIEPMSK_ITTXFEMSK (1U << 4) /**< IN token received when +#define DIEPMSK_INTKNTXFEMPMSK (1U << 4) /**< IN token received when TxFIFO empty mask. */ -#define DIEPMSK_TOCM (1U << 3) /**< Timeout condition mask. */ -#define DIEPMSK_EPDM (1U << 1) /**< Endpoint disabled +#define DIEPMSK_TIMEOUTMSK (1U << 3) /**< Timeout condition mask. */ +#define DIEPMSK_EPTDISMSK (1U << 1) /**< Endpoint disabled interrupt mask. */ -#define DIEPMSK_XFRCM (1U << 0) /**< Transfer completed +#define DIEPMSK_XFERCMSK (1U << 0) /**< Transfer completed interrupt mask. */ /** @} */ @@ -709,12 +695,12 @@ typedef struct { * @name DOEPMSK register bit definitions * @{ */ -#define DOEPMSK_OTEPDM (1U << 4) /**< OUT token received when +#define DOEPMSK_OUTTEPDMSK (1U << 4) /**< OUT token received when endpoint disabled mask. */ -#define DOEPMSK_STUPM (1U << 3) /**< SETUP phase done mask. */ -#define DOEPMSK_EPDM (1U << 1) /**< Endpoint disabled +#define DOEPMSK_SETUPMSK (1U << 3) /**< SETUP phase done mask. */ +#define DOEPMSK_EPTDISMSK (1U << 1) /**< Endpoint disabled interrupt mask. */ -#define DOEPMSK_XFRCM (1U << 0) /**< Transfer completed +#define DOEPMSK_XFERCMSK (1U << 0) /**< Transfer completed interrupt mask. */ /** @} */ @@ -722,13 +708,13 @@ typedef struct { * @name DAINT register bit definitions * @{ */ -#define DAINT_OEPINT_MASK (0xFFFFU << 16) /**< OUT endpoint interrupt +#define DAINT_OUTEPTINT_MASK (0xFFFFU << 16) /**< OUT endpoint interrupt bits mask. */ -#define DAINT_OEPINT(n) ((n) << 16) /**< OUT endpoint interrupt +#define DAINT_OUTEPTINT(n) ((n) << 16) /**< OUT endpoint interrupt bits value. */ -#define DAINT_IEPINT_MASK (0xFFFFU << 0) /**< IN endpoint interrupt +#define DAINT_INEPTINT_MASK (0xFFFFU << 0) /**< IN endpoint interrupt bits mask. */ -#define DAINT_IEPINT(n) ((n) << 0) /**< IN endpoint interrupt +#define DAINT_INEPTINT(n) ((n) << 0) /**< IN endpoint interrupt bits value. */ /** @} */ @@ -736,147 +722,126 @@ typedef struct { * @name DAINTMSK register bit definitions * @{ */ -#define DAINTMSK_OEPM_MASK (0xFFFFU << 16) /**< OUT EP interrupt mask +#define DAINTMSK_OUTEPTMSK_MASK (0xFFFFU << 16) /**< OUT EP interrupt mask bits mask. */ -#define DAINTMSK_OEPM(n) (1U <<(16+(n))) /**< OUT EP interrupt mask +#define DAINTMSK_OUTEPTMSK(n) (1U <<(16+(n))) /**< OUT EP interrupt mask bits value. */ -#define DAINTMSK_IEPM_MASK (0xFFFFU << 0) /**< IN EP interrupt mask +#define DAINTMSK_INEPTMSK_MASK (0xFFFFU << 0) /**< IN EP interrupt mask bits mask. */ -#define DAINTMSK_IEPM(n) (1U <<(n)) /**< IN EP interrupt mask +#define DAINTMSK_INEPTMSK(n) (1U <<(n)) /**< IN EP interrupt mask bits value. */ /** @} */ -/** - * @name DVBUSDIS register bit definitions - * @{ - */ -#define DVBUSDIS_VBUSDT_MASK (0xFFFFU << 0) /**< Device VBUS discharge - time mask. */ -#define DVBUSDIS_VBUSDT(n) ((n) << 0) /**< Device VBUS discharge - time value. */ -/** @} */ - -/** - * @name DVBUSPULSE register bit definitions - * @{ - */ -#define DVBUSPULSE_DVBUSP_MASK (0xFFFU << 0) /**< Device VBUSpulsing time - mask. */ -#define DVBUSPULSE_DVBUSP(n) ((n) << 0) /**< Device VBUS pulsing time - value. */ -/** @} */ - /** * @name DIEPEMPMSK register bit definitions * @{ */ -#define DIEPEMPMSK_INEPTXFEM(n) (1U << (n)) /**< IN EP Tx FIFO empty - interrupt mask bit. */ +#define DIEPEMPMSK_INEPTXFEMSK(n) (1U << (n)) /**< IN EP Tx FIFO empty + interrupt mask bit. */ /** @} */ /** * @name DIEPCTL register bit definitions * @{ */ -#define DIEPCTL_EPENA (1U << 31) /**< Endpoint enable. */ -#define DIEPCTL_EPDIS (1U << 30) /**< Endpoint disable. */ -#define DIEPCTL_SD1PID (1U << 29) /**< Set DATA1 PID. */ -#define DIEPCTL_SODDFRM (1U << 29) /**< Set odd frame. */ -#define DIEPCTL_SD0PID (1U << 28) /**< Set DATA0 PID. */ -#define DIEPCTL_SEVNFRM (1U << 28) /**< Set even frame. */ +#define DIEPCTL_EPTENA (1U << 31) /**< Endpoint enable. */ +#define DIEPCTL_EPTDIS (1U << 30) /**< Endpoint disable. */ +#define DIEPCTL_SETD1PID (1U << 29) /**< Set DATA1 PID. */ +#define DIEPCTL_SETODDFR (1U << 29) /**< Set odd frame. */ +#define DIEPCTL_SETD0PID (1U << 28) /**< Set DATA0 PID. */ +#define DIEPCTL_SETEVENFR (1U << 28) /**< Set even frame. */ #define DIEPCTL_SNAK (1U << 27) /**< Set NAK. */ #define DIEPCTL_CNAK (1U << 26) /**< Clear NAK. */ #define DIEPCTL_TXFNUM_MASK (15U << 22) /**< TxFIFO number mask. */ #define DIEPCTL_TXFNUM(n) ((n) << 22) /**< TxFIFO number value. */ #define DIEPCTL_STALL (1U << 21) /**< STALL handshake. */ -#define DIEPCTL_SNPM (1U << 20) /**< Snoop mode. */ -#define DIEPCTL_EPTYP_MASK (3U << 18) /**< Endpoint type mask. */ -#define DIEPCTL_EPTYP_CTRL (0U << 18) /**< Control. */ -#define DIEPCTL_EPTYP_ISO (1U << 18) /**< Isochronous. */ -#define DIEPCTL_EPTYP_BULK (2U << 18) /**< Bulk. */ -#define DIEPCTL_EPTYP_INTR (3U << 18) /**< Interrupt. */ +#define DIEPCTL_EPTYPE_MASK (3U << 18) /**< Endpoint type mask. */ +#define DIEPCTL_EPTYPE_CTRL (0U << 18) /**< Control. */ +#define DIEPCTL_EPTYPE_ISO (1U << 18) /**< Isochronous. */ +#define DIEPCTL_EPTYPE_BULK (2U << 18) /**< Bulk. */ +#define DIEPCTL_EPTYPE_INTR (3U << 18) /**< Interrupt. */ #define DIEPCTL_NAKSTS (1U << 17) /**< NAK status. */ -#define DIEPCTL_EONUM (1U << 16) /**< Even/odd frame. */ +#define DIEPCTL_EOFRNUM (1U << 16) /**< Even/odd frame. */ #define DIEPCTL_DPID (1U << 16) /**< Endpoint data PID. */ -#define DIEPCTL_USBAEP (1U << 15) /**< USB active endpoint. */ -#define DIEPCTL_MPSIZ_MASK (0x3FFU << 0) /**< Maximum Packet size mask.*/ -#define DIEPCTL_MPSIZ(n) ((n) << 0) /**< Maximum Packet size value. */ +#define DIEPCTL_USBACEPT (1U << 15) /**< USB active endpoint. */ +#define DIEPCTL_MPS_MASK (0x7FFU << 0) /**< Maximum packet size mask.*/ +#define DIEPCTL_MPS(n) ((n) << 0) /**< Maximum packet size value. */ /** @} */ /** * @name DIEPINT register bit definitions * @{ */ -#define DIEPINT_TXFE (1U << 7) /**< Transmit FIFO empty. */ -#define DIEPINT_INEPNE (1U << 6) /**< IN endpoint NAK effective. */ -#define DIEPINT_ITTXFE (1U << 4) /**< IN Token received when +#define DIEPINT_TXFEMP (1U << 7) /**< Transmit FIFO empty. */ +#define DIEPINT_INEPTNAK (1U << 6) /**< IN endpoint NAK effective. */ +#define DIEPINT_INTKNTXFEMP (1U << 4) /**< IN Token received when TxFIFO is empty. */ -#define DIEPINT_TOC (1U << 3) /**< Timeout condition. */ -#define DIEPINT_EPDISD (1U << 1) /**< Endpoint disabled +#define DIEPINT_TIMEOUT (1U << 3) /**< Timeout condition. */ +#define DIEPINT_EPTDISD (1U << 1) /**< Endpoint disabled + interrupt. */ +#define DIEPINT_XFERC (1U << 0) /**< Transfer completed interrupt. */ -#define DIEPINT_XFRC (1U << 0) /**< Transfer completed. */ /** @} */ /** * @name DIEPTSIZ register bit definitions * @{ */ -#define DIEPTSIZ_MCNT_MASK (3U << 29) /**< Multi count mask. */ -#define DIEPTSIZ_MCNT(n) ((n) << 29) /**< Multi count value. */ +#define DIEPTSIZ_MC_MASK (3U << 29) /**< Multi count mask. */ +#define DIEPTSIZ_MC(n) ((n) << 29) /**< Multi count value. */ #define DIEPTSIZ_PKTCNT_MASK (0x3FF<< 19) /**< Packet count mask. */ #define DIEPTSIZ_PKTCNT(n) ((n) << 19) /**< Packet count value. */ -#define DIEPTSIZ_XFRSIZ_MASK (0x7FFFFU << 0) /**< Transfer size mask. */ -#define DIEPTSIZ_XFRSIZ(n) ((n) << 0) /**< Transfer size value. */ +#define DIEPTSIZ_XFERSIZE_MASK (0x7FFFFU << 0) /**< Transfer size mask. */ +#define DIEPTSIZ_XFERSIZE(n) ((n) << 0) /**< Transfer size value. */ /** @} */ /** * @name DTXFSTS register bit definitions. * @{ */ -#define DTXFSTS_INEPTFSAV_MASK (0xFFFFU << 0) /**< IN endpoint TxFIFO space - available. */ +#define DTXFSTS_INEPTXFSAV_MASK (0xFFFFU << 0) /**< IN endpoint TxFIFO + space available. */ /** @} */ /** * @name DOEPCTL register bit definitions. * @{ */ -#define DOEPCTL_EPENA (1U << 31) /**< Endpoint enable. */ -#define DOEPCTL_EPDIS (1U << 30) /**< Endpoint disable. */ -#define DOEPCTL_SD1PID (1U << 29) /**< Set DATA1 PID. */ -#define DOEPCTL_SODDFRM (1U << 29) /**< Set odd frame. */ -#define DOEPCTL_SD0PID (1U << 28) /**< Set DATA0 PID. */ -#define DOEPCTL_SEVNFRM (1U << 28) /**< Set even frame. */ +#define DOEPCTL_EPTENA (1U << 31) /**< Endpoint enable. */ +#define DOEPCTL_EPTDIS (1U << 30) /**< Endpoint disable. */ +#define DOEPCTL_SETD1PID (1U << 29) /**< Set DATA1 PID. */ +#define DOEPCTL_SETODDFR (1U << 29) /**< Set odd frame. */ +#define DOEPCTL_SETD0PID (1U << 28) /**< Set DATA0 PID. */ +#define DOEPCTL_SETEVENFR (1U << 28) /**< Set even frame. */ #define DOEPCTL_SNAK (1U << 27) /**< Set NAK. */ #define DOEPCTL_CNAK (1U << 26) /**< Clear NAK. */ #define DOEPCTL_STALL (1U << 21) /**< STALL handshake. */ -#define DOEPCTL_SNPM (1U << 20) /**< Snoop mode. */ -#define DOEPCTL_EPTYP_MASK (3U << 18) /**< Endpoint type mask. */ -#define DOEPCTL_EPTYP_CTRL (0U << 18) /**< Control. */ -#define DOEPCTL_EPTYP_ISO (1U << 18) /**< Isochronous. */ -#define DOEPCTL_EPTYP_BULK (2U << 18) /**< Bulk. */ -#define DOEPCTL_EPTYP_INTR (3U << 18) /**< Interrupt. */ +#define DOEPCTL_SNP (1U << 20) /**< Snoop mode. */ +#define DOEPCTL_EPTYPE_MASK (3U << 18) /**< Endpoint type mask. */ +#define DOEPCTL_EPTYPE_CTRL (0U << 18) /**< Control. */ +#define DOEPCTL_EPTYPE_ISO (1U << 18) /**< Isochronous. */ +#define DOEPCTL_EPTYPE_BULK (2U << 18) /**< Bulk. */ +#define DOEPCTL_EPTYPE_INTR (3U << 18) /**< Interrupt. */ #define DOEPCTL_NAKSTS (1U << 17) /**< NAK status. */ -#define DOEPCTL_EONUM (1U << 16) /**< Even/odd frame. */ +#define DOEPCTL_EOFRNUM (1U << 16) /**< Even/odd frame. */ #define DOEPCTL_DPID (1U << 16) /**< Endpoint data PID. */ -#define DOEPCTL_USBAEP (1U << 15) /**< USB active endpoint. */ -#define DOEPCTL_MPSIZ_MASK (0x3FFU << 0)/**< Maximum Packet size mask. */ -#define DOEPCTL_MPSIZ(n) ((n) << 0) /**< Maximum Packet size value. */ +#define DOEPCTL_USBACEPT (1U << 15) /**< USB active endpoint. */ +#define DOEPCTL_MPS_MASK (0x7FFU << 0)/**< Maximum packet size mask. */ +#define DOEPCTL_MPS(n) ((n) << 0) /**< Maximum packet size value. */ /** @} */ /** * @name DOEPINT register bit definitions * @{ */ -#define DOEPINT_SETUP_RCVD (1U << 15) /**< SETUP packet received. */ #define DOEPINT_B2BSTUP (1U << 6) /**< Back-to-back SETUP packets received. */ -#define DOEPINT_OTEPDIS (1U << 4) /**< OUT token received when +#define DOEPINT_OUTTEPD (1U << 4) /**< OUT token received when endpoint disabled. */ -#define DOEPINT_STUP (1U << 3) /**< SETUP phase done. */ -#define DOEPINT_EPDISD (1U << 1) /**< Endpoint disabled +#define DOEPINT_SETUP (1U << 3) /**< SETUP phase done. */ +#define DOEPINT_EPTDISD (1U << 1) /**< Endpoint disabled interrupt. */ -#define DOEPINT_XFRC (1U << 0) /**< Transfer completed +#define DOEPINT_XFERC (1U << 0) /**< Transfer completed interrupt. */ /** @} */ @@ -886,21 +851,20 @@ typedef struct { */ #define DOEPTSIZ_RXDPID_MASK (3U << 29) /**< Received data PID mask. */ #define DOEPTSIZ_RXDPID(n) ((n) << 29) /**< Received data PID value. */ -#define DOEPTSIZ_STUPCNT_MASK (3U << 29) /**< SETUP packet count mask. */ -#define DOEPTSIZ_STUPCNT(n) ((n) << 29) /**< SETUP packet count value. */ +#define DOEPTSIZ_SETUPCNT_MASK (3U << 29) /**< SETUP packet count mask. */ +#define DOEPTSIZ_SETUPCNT(n) ((n) << 29) /**< SETUP packet count value. */ #define DOEPTSIZ_PKTCNT_MASK (0x3FFU << 19) /**< Packet count mask. */ #define DOEPTSIZ_PKTCNT(n) ((n) << 19) /**< Packet count value. */ -#define DOEPTSIZ_XFRSIZ_MASK (0x7FFFFU << 0) /**< Transfer size mask. */ -#define DOEPTSIZ_XFRSIZ(n) ((n) << 0) /**< Transfer size value. */ +#define DOEPTSIZ_XFERSIZE_MASK (0x7FFFFU << 0) /**< Transfer size mask. */ +#define DOEPTSIZ_XFERSIZE(n) ((n) << 0) /**< Transfer size value. */ /** @} */ /** * @name PCGCCTL register bit definitions * @{ */ -#define PCGCCTL_PHYSUSP (1U << 4) /**< PHY Suspended. */ -#define PCGCCTL_GATEHCLK (1U << 1) /**< Gate HCLK. */ -#define PCGCCTL_STPPCLK (1U << 0) /**< Stop PCLK. */ +#define PCGCCTL_SUSPENDM (1U << 4) /**< PHY Suspended. */ +#define PCGCCTL_STOPPCLK (1U << 0) /**< Stop PCLK. */ /** @} */ #define OTG_FS_ADDR 0x50000000 diff --git a/os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.c b/os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.c index 1801e04f4e..fc114fb9a6 100644 --- a/os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.c +++ b/os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.c @@ -34,25 +34,30 @@ /* Driver local definitions. */ /*===========================================================================*/ -#define TRDT_VALUE_FS 5 -#define TRDT_VALUE_HS 9 +#define USBTRDTIM_VALUE_FS 5 +#define USBTRDTIM_VALUE_HS 9 #define EP0_MAX_INSIZE 64 #define EP0_MAX_OUTSIZE 64 #if AT32_OTG_STEPPING == 1 -#if defined(BOARD_OTG_NOVBUSSENS) -#define GCCFG_INIT_VALUE (GCCFG_NOVBUSSENS | GCCFG_PWRDWN) +#if defined(BOARD_OTG_VBUSIG) +#define GCCFG_INIT_VALUE (GCCFG_VBUSIG | GCCFG_PWRDOWN) #else -#define GCCFG_INIT_VALUE (GCCFG_VBUSASEN | GCCFG_VBUSBSEN | \ - GCCFG_PWRDWN) +#define GCCFG_INIT_VALUE (GCCFG_AVALIDSESEN | GCCFG_BVALIDSESEN | \ + GCCFG_PWRDOWN) #endif #elif AT32_OTG_STEPPING == 2 -#if defined(BOARD_OTG_NOVBUSSENS) -#define GCCFG_INIT_VALUE GCCFG_PWRDWN +#if defined(BOARD_OTG_VBUSIG_LPM) +#define GCCFG_INIT_VALUE (GCCFG_VBUSIG | GCCFG_LP_MODE | \ + GCCFG_PWRDOWN) +#elif defined(BOARD_OTG_VBUSIG) +#define GCCFG_INIT_VALUE (GCCFG_VBUSIG | GCCFG_PWRDOWN) +#elif defined(BOARD_OTG_LPM) +#define GCCFG_INIT_VALUE (GCCFG_LP_MODE | GCCFG_PWRDOWN) #else -#define GCCFG_INIT_VALUE (GCCFG_VBDEN | GCCFG_PWRDWN) +#define GCCFG_INIT_VALUE GCCFG_PWRDOWN #endif #endif @@ -136,19 +141,19 @@ static void otg_core_reset(USBDriver *usbp) { at32_otg_t *otgp = usbp->otg; /* Wait AHB idle condition.*/ - while ((otgp->GRSTCTL & GRSTCTL_AHBIDL) == 0) + while ((otgp->GRSTCTL & GRSTCTL_AHBIDLE) == 0) ; /* Core reset and delay of at least 3 PHY cycles.*/ - otgp->GRSTCTL = GRSTCTL_CSRST; + otgp->GRSTCTL = GRSTCTL_CSFTRST; osalSysPolledDelayX(12); - while ((otgp->GRSTCTL & GRSTCTL_CSRST) != 0) + while ((otgp->GRSTCTL & GRSTCTL_CSFTRST) != 0) ; osalSysPolledDelayX(18); /* Wait AHB idle condition again.*/ - while ((otgp->GRSTCTL & GRSTCTL_AHBIDL) == 0) + while ((otgp->GRSTCTL & GRSTCTL_AHBIDLE) == 0) ; } @@ -158,18 +163,18 @@ static void otg_disable_ep(USBDriver *usbp) { for (i = 0; i <= usbp->otgparams->num_endpoints; i++) { - if ((otgp->ie[i].DIEPCTL & DIEPCTL_EPENA) != 0U) { - otgp->ie[i].DIEPCTL |= DIEPCTL_EPDIS; + if ((otgp->ie[i].DIEPCTL & DIEPCTL_EPTENA) != 0U) { + otgp->ie[i].DIEPCTL |= DIEPCTL_EPTDIS; } - if ((otgp->oe[i].DOEPCTL & DIEPCTL_EPENA) != 0U) { - otgp->oe[i].DOEPCTL |= DIEPCTL_EPDIS; + if ((otgp->oe[i].DOEPCTL & DIEPCTL_EPTENA) != 0U) { + otgp->oe[i].DOEPCTL |= DIEPCTL_EPTDIS; } otgp->ie[i].DIEPINT = 0xFFFFFFFF; otgp->oe[i].DOEPINT = 0xFFFFFFFF; } - otgp->DAINTMSK = DAINTMSK_OEPM(0) | DAINTMSK_IEPM(0); + otgp->DAINTMSK = DAINTMSK_OUTEPTMSK(0) | DAINTMSK_INEPTMSK(0); } static void otg_rxfifo_flush(USBDriver *usbp) { @@ -291,7 +296,7 @@ static void otg_rxfifo_handler(USBDriver *usbp) { /* Event details.*/ cnt = (sts & GRXSTSP_BCNT_MASK) >> GRXSTSP_BCNT_OFF; - ep = (sts & GRXSTSP_EPNUM_MASK) >> GRXSTSP_EPNUM_OFF; + ep = (sts & GRXSTSP_EPTNUM_MASK) >> GRXSTSP_EPTNUM_OFF; switch (sts & GRXSTSP_PKTSTS_MASK) { case GRXSTSP_SETUP_DATA: @@ -335,7 +340,7 @@ static bool otg_txfifo_handler(USBDriver *usbp, usbep_t ep) { /* Transaction end condition.*/ if (usbp->epc[ep]->in_state->txcnt >= usbp->epc[ep]->in_state->txsize) { #if 1 - usbp->otg->DIEPEMPMSK &= ~DIEPEMPMSK_INEPTXFEM(ep); + usbp->otg->DIEPEMPMSK &= ~DIEPEMPMSK_INEPTXFEMSK(ep); #endif return true; } @@ -347,7 +352,7 @@ static bool otg_txfifo_handler(USBDriver *usbp, usbep_t ep) { /* Checks if in the TXFIFO there is enough space to accommodate the next packet.*/ - if (((usbp->otg->ie[ep].DTXFSTS & DTXFSTS_INEPTFSAV_MASK) * 4) < n) + if (((usbp->otg->ie[ep].DTXFSTS & DTXFSTS_INEPTXFSAV_MASK) * 4) < n) return false; #if AT32_USB_OTGFIFO_FILL_BASEPRI @@ -378,10 +383,10 @@ static void otg_epin_handler(USBDriver *usbp, usbep_t ep) { otgp->ie[ep].DIEPINT = epint; - if (epint & DIEPINT_TOC) { + if (epint & DIEPINT_TIMEOUT) { /* Timeouts not handled yet, not sure how to handle.*/ } - if ((epint & DIEPINT_XFRC) && (otgp->DIEPMSK & DIEPMSK_XFRCM)) { + if ((epint & DIEPINT_XFERC) && (otgp->DIEPMSK & DIEPMSK_XFERCMSK)) { /* Transmit transfer complete.*/ USBInEndpointState *isp = usbp->epc[ep]->in_state; @@ -400,8 +405,8 @@ static void otg_epin_handler(USBDriver *usbp, usbep_t ep) { _usb_isr_invoke_in_cb(usbp, ep); } } - if ((epint & DIEPINT_TXFE) && - (otgp->DIEPEMPMSK & DIEPEMPMSK_INEPTXFEM(ep))) { + if ((epint & DIEPINT_TXFEMP) && + (otgp->DIEPEMPMSK & DIEPEMPMSK_INEPTXFEMSK(ep))) { /* TX FIFO empty or emptying.*/ otg_txfifo_handler(usbp, ep); } @@ -422,13 +427,13 @@ static void otg_epout_handler(USBDriver *usbp, usbep_t ep) { /* Resets all EP IRQ sources.*/ otgp->oe[ep].DOEPINT = epint; - if ((epint & DOEPINT_STUP) && (otgp->DOEPMSK & DOEPMSK_STUPM)) { + if ((epint & DOEPINT_SETUP) && (otgp->DOEPMSK & DOEPMSK_SETUPMSK)) { /* Setup packets handling, setup packets are handled using a specific callback.*/ _usb_isr_invoke_setup_cb(usbp, ep); } - if ((epint & DOEPINT_XFRC) && (otgp->DOEPMSK & DOEPMSK_XFRCM)) { + if ((epint & DOEPINT_XFERC) && (otgp->DOEPMSK & DOEPMSK_XFERCMSK)) { USBOutEndpointState *osp; /* OUT state structure pointer for this endpoint.*/ @@ -477,12 +482,12 @@ static void otg_isoc_in_failed_handler(USBDriver *usbp) { at32_otg_t *otgp = usbp->otg; for (ep = 0; ep <= usbp->otgparams->num_endpoints; ep++) { - if (((otgp->ie[ep].DIEPCTL & DIEPCTL_EPTYP_MASK) == DIEPCTL_EPTYP_ISO) && - ((otgp->ie[ep].DIEPCTL & DIEPCTL_EPENA) != 0)) { + if (((otgp->ie[ep].DIEPCTL & DIEPCTL_EPTYPE_MASK) == DIEPCTL_EPTYPE_ISO) && + ((otgp->ie[ep].DIEPCTL & DIEPCTL_EPTENA) != 0)) { /* Endpoint enabled -> ISOC IN transfer failed.*/ /* Disable endpoint.*/ - otgp->ie[ep].DIEPCTL |= (DIEPCTL_EPDIS | DIEPCTL_SNAK); - while (otgp->ie[ep].DIEPCTL & DIEPCTL_EPENA) + otgp->ie[ep].DIEPCTL |= (DIEPCTL_EPTDIS | DIEPCTL_SNAK); + while (otgp->ie[ep].DIEPCTL & DIEPCTL_EPTENA) ; /* Flush FIFO.*/ @@ -506,14 +511,14 @@ static void otg_isoc_out_failed_handler(USBDriver *usbp) { at32_otg_t *otgp = usbp->otg; for (ep = 0; ep <= usbp->otgparams->num_endpoints; ep++) { - if (((otgp->oe[ep].DOEPCTL & DOEPCTL_EPTYP_MASK) == DOEPCTL_EPTYP_ISO) && - ((otgp->oe[ep].DOEPCTL & DOEPCTL_EPENA) != 0)) { + if (((otgp->oe[ep].DOEPCTL & DOEPCTL_EPTYPE_MASK) == DOEPCTL_EPTYPE_ISO) && + ((otgp->oe[ep].DOEPCTL & DOEPCTL_EPTENA) != 0)) { #if 0 /* Endpoint enabled -> ISOC OUT transfer failed.*/ /* Disable endpoint.*/ /* CHTODO:: Core stucks here */ - otgp->oe[ep].DOEPCTL |= (DOEPCTL_EPDIS | DOEPCTL_SNAK); - while (otgp->oe[ep].DOEPCTL & DOEPCTL_EPENA) + otgp->oe[ep].DOEPCTL |= (DOEPCTL_EPTDIS | DOEPCTL_SNAK); + while (otgp->oe[ep].DOEPCTL & DOEPCTL_EPTENA) ; #endif /* Prepare transfer for next frame.*/ @@ -550,13 +555,13 @@ static void usb_lld_serve_interrupt(USBDriver *usbp) { if (sts & GINTSTS_WKUPINT) { /* If clocks are gated off, turn them back on (may be the case if coming out of suspend mode).*/ - if (otgp->PCGCCTL & (PCGCCTL_STPPCLK | PCGCCTL_GATEHCLK)) { + if (otgp->PCGCCTL & PCGCCTL_STOPPCLK) { /* Set to zero to un-gate the USB core clocks.*/ - otgp->PCGCCTL &= ~(PCGCCTL_STPPCLK | PCGCCTL_GATEHCLK); + otgp->PCGCCTL &= ~PCGCCTL_STOPPCLK; } /* Clear the Remote Wake-up Signaling.*/ - otgp->DCTL &= ~DCTL_RWUSIG; + otgp->DCTL &= ~DCTL_RWKUPSIG; _usb_wakeup(usbp); } @@ -571,15 +576,15 @@ static void usb_lld_serve_interrupt(USBDriver *usbp) { } /* Enumeration done.*/ - if (sts & GINTSTS_ENUMDNE) { + if (sts & GINTSTS_ENUMDONE) { /* Full or High speed timing selection.*/ if ((otgp->DSTS & DSTS_ENUMSPD_MASK) == DSTS_ENUMSPD_HS_480) { - otgp->GUSBCFG = (otgp->GUSBCFG & ~(GUSBCFG_TRDT_MASK)) | - GUSBCFG_TRDT(TRDT_VALUE_HS); + otgp->GUSBCFG = (otgp->GUSBCFG & ~(GUSBCFG_USBTRDTIM_MASK)) | + GUSBCFG_USBTRDTIM(USBTRDTIM_VALUE_HS); } else { - otgp->GUSBCFG = (otgp->GUSBCFG & ~(GUSBCFG_TRDT_MASK)) | - GUSBCFG_TRDT(TRDT_VALUE_FS); + otgp->GUSBCFG = (otgp->GUSBCFG & ~(GUSBCFG_USBTRDTIM_MASK)) | + GUSBCFG_USBTRDTIM(USBTRDTIM_VALUE_FS); } } @@ -588,14 +593,14 @@ static void usb_lld_serve_interrupt(USBDriver *usbp) { /* SOF interrupt was used to detect resume of the USB bus after issuing a remote wake up of the host, therefore we disable it again.*/ if (usbp->config->sof_cb == NULL) { - otgp->GINTMSK &= ~GINTMSK_SOFM; + otgp->GINTMSK &= ~GINTMSK_SOFMSK; } if (usbp->state == USB_SUSPENDED) { /* If clocks are gated off, turn them back on (may be the case if coming out of suspend mode).*/ - if (otgp->PCGCCTL & (PCGCCTL_STPPCLK | PCGCCTL_GATEHCLK)) { + if (otgp->PCGCCTL & PCGCCTL_STOPPCLK) { /* Set to zero to un-gate the USB core clocks.*/ - otgp->PCGCCTL &= ~(PCGCCTL_STPPCLK | PCGCCTL_GATEHCLK); + otgp->PCGCCTL &= ~PCGCCTL_STOPPCLK; } _usb_wakeup(usbp); } @@ -604,12 +609,12 @@ static void usb_lld_serve_interrupt(USBDriver *usbp) { } /* Isochronous IN failed handling */ - if (sts & GINTSTS_IISOIXFR) { + if (sts & GINTSTS_INCOMPISOIN) { otg_isoc_in_failed_handler(usbp); } /* Isochronous OUT failed handling */ - if (sts & GINTSTS_IISOOXFR) { + if (sts & GINTSTS_INCOMPISOOUT) { otg_isoc_out_failed_handler(usbp); } @@ -621,7 +626,7 @@ static void usb_lld_serve_interrupt(USBDriver *usbp) { /* IN/OUT endpoints event handling.*/ src = otgp->DAINT; - if (sts & GINTSTS_OEPINT) { + if (sts & GINTSTS_OEPTINT) { if (src & (1 << 16)) otg_epout_handler(usbp, 0); if (src & (1 << 17)) @@ -651,7 +656,7 @@ static void usb_lld_serve_interrupt(USBDriver *usbp) { otg_epout_handler(usbp, 8); #endif } - if (sts & GINTSTS_IEPINT) { + if (sts & GINTSTS_IEPTINT) { if (src & (1 << 0)) otg_epin_handler(usbp, 0); if (src & (1 << 1)) @@ -771,13 +776,13 @@ void usb_lld_start(USBDriver *usbp) { nvicEnableVector(AT32_OTG1_NUMBER, AT32_USB_OTG1_IRQ_PRIORITY); /* - Forced device mode. - - USB turn-around time = TRDT_VALUE_FS. + - USB turn-around time = USBTRDTIM_VALUE_FS. - Full Speed 1.1 PHY.*/ - otgp->GUSBCFG = GUSBCFG_FDMOD | GUSBCFG_TRDT(TRDT_VALUE_FS) | + otgp->GUSBCFG = GUSBCFG_FDEVMODE | GUSBCFG_USBTRDTIM(USBTRDTIM_VALUE_FS) | GUSBCFG_PHYSEL; /* 48MHz 1.1 PHY.*/ - otgp->DCFG = 0x02200000 | DCFG_DSPD_FS11; + otgp->DCFG = 0x02200000 | DCFG_DEVSPD_FS11; } #endif @@ -801,27 +806,26 @@ void usb_lld_start(USBDriver *usbp) { nvicEnableVector(AT32_OTG2_NUMBER, AT32_USB_OTG2_IRQ_PRIORITY); /* - Forced device mode. - - USB turn-around time = TRDT_VALUE_HS or TRDT_VALUE_FS.*/ + - USB turn-around time = USBTRDTIM_VALUE_HS or USBTRDTIM_VALUE_FS.*/ #if defined(BOARD_OTG2_USES_ULPI) /* High speed ULPI PHY.*/ - otgp->GUSBCFG = GUSBCFG_FDMOD | GUSBCFG_TRDT(TRDT_VALUE_HS) | - GUSBCFG_SRPCAP | GUSBCFG_HNPCAP; + otgp->GUSBCFG = GUSBCFG_FDEVMODE | GUSBCFG_USBTRDTIM(USBTRDTIM_VALUE_HS); #else - otgp->GUSBCFG = GUSBCFG_FDMOD | GUSBCFG_TRDT(TRDT_VALUE_FS) | + otgp->GUSBCFG = GUSBCFG_FDEVMODE | GUSBCFG_USBTRDTIM(USBTRDTIM_VALUE_FS) | GUSBCFG_PHYSEL; #endif #if defined(BOARD_OTG2_USES_ULPI) #if AT32_USE_USB_OTG2_HS /* USB 2.0 High Speed PHY in HS mode.*/ - otgp->DCFG = 0x02200000 | DCFG_DSPD_HS; + otgp->DCFG = 0x02200000 | DCFG_DEVSPD_HS; #else /* USB 2.0 High Speed PHY in FS mode.*/ - otgp->DCFG = 0x02200000 | DCFG_DSPD_HS_FS; + otgp->DCFG = 0x02200000 | DCFG_DEVSPD_HS_FS; #endif #else /* 48MHz 1.1 PHY.*/ - otgp->DCFG = 0x02200000 | DCFG_DSPD_FS11; + otgp->DCFG = 0x02200000 | DCFG_DEVSPD_FS11; #endif } #endif @@ -829,9 +833,6 @@ void usb_lld_start(USBDriver *usbp) { /* PHY enabled.*/ otgp->PCGCCTL = 0; - /* VBUS sensing and transceiver enabled.*/ - otgp->GOTGCTL = GOTGCTL_BVALOEN | GOTGCTL_BVALOVAL; - #if defined(BOARD_OTG2_USES_ULPI) #if AT32_USB_USE_OTG1 if (&USBD1 == usbp) { @@ -863,20 +864,20 @@ void usb_lld_start(USBDriver *usbp) { otgp->DOEPMSK = 0; otgp->DAINTMSK = 0; if (usbp->config->sof_cb == NULL) - otgp->GINTMSK = GINTMSK_ENUMDNEM | GINTMSK_USBRSTM | GINTMSK_USBSUSPM | - GINTMSK_ESUSPM | GINTMSK_SRQM | GINTMSK_WKUM | - GINTMSK_IISOIXFRM | GINTMSK_IISOOXFRM; + otgp->GINTMSK = GINTMSK_ENUMDONEMSK | GINTMSK_USBRSTMSK | GINTMSK_USBSUSPMSK | + GINTMSK_ERLYSUSPMSK | GINTMSK_WKUPINTMSK | + GINTMSK_INCOMISOINMSK | GINTMSK_INCOMPISOOUTMSK; else - otgp->GINTMSK = GINTMSK_ENUMDNEM | GINTMSK_USBRSTM | GINTMSK_USBSUSPM | - GINTMSK_ESUSPM | GINTMSK_SRQM | GINTMSK_WKUM | - GINTMSK_IISOIXFRM | GINTMSK_IISOOXFRM | - GINTMSK_SOFM; + otgp->GINTMSK = GINTMSK_ENUMDONEMSK | GINTMSK_USBRSTMSK | GINTMSK_USBSUSPMSK | + GINTMSK_ERLYSUSPMSK | GINTMSK_WKUPINTMSK | + GINTMSK_INCOMISOINMSK | GINTMSK_INCOMPISOOUTMSK | + GINTMSK_SOFMSK; /* Clears all pending IRQs, if any. */ otgp->GINTSTS = 0xFFFFFFFF; /* Global interrupts enable.*/ - otgp->GAHBCFG |= GAHBCFG_GINTMSK; + otgp->GAHBCFG |= GAHBCFG_GLBINTMSK; } } @@ -936,7 +937,7 @@ void usb_lld_reset(USBDriver *usbp) { /* Endpoint interrupts all disabled and cleared.*/ otgp->DIEPEMPMSK = 0; - otgp->DAINTMSK = DAINTMSK_OEPM(0) | DAINTMSK_IEPM(0); + otgp->DAINTMSK = DAINTMSK_OUTEPTMSK(0) | DAINTMSK_INEPTMSK(0); /* All endpoints in NAK mode, interrupts cleared.*/ for (i = 0; i <= usbp->otgparams->num_endpoints; i++) { @@ -954,23 +955,23 @@ void usb_lld_reset(USBDriver *usbp) { otg_rxfifo_flush(usbp); /* Resets the device address to zero.*/ - otgp->DCFG = (otgp->DCFG & ~DCFG_DAD_MASK) | DCFG_DAD(0); + otgp->DCFG = (otgp->DCFG & ~DCFG_DEVADDR_MASK) | DCFG_DEVADDR(0); /* Enables also EP-related interrupt sources.*/ - otgp->GINTMSK |= GINTMSK_RXFLVLM | GINTMSK_OEPM | GINTMSK_IEPM; - otgp->DIEPMSK = DIEPMSK_TOCM | DIEPMSK_XFRCM; - otgp->DOEPMSK = DOEPMSK_STUPM | DOEPMSK_XFRCM; + otgp->GINTMSK |= GINTMSK_RXFLVLMSK | GINTMSK_OEPTINTMSK | GINTMSK_IEPTINTMSK; + otgp->DIEPMSK = DIEPMSK_TIMEOUTMSK | DIEPMSK_XFERCMSK; + otgp->DOEPMSK = DOEPMSK_SETUPMSK | DOEPMSK_XFERCMSK; /* EP0 initialization, it is a special case.*/ usbp->epc[0] = &ep0config; - otgp->oe[0].DOEPTSIZ = DOEPTSIZ_STUPCNT(3); - otgp->oe[0].DOEPCTL = DOEPCTL_SD0PID | DOEPCTL_USBAEP | DOEPCTL_EPTYP_CTRL | - DOEPCTL_MPSIZ(ep0config.out_maxsize); + otgp->oe[0].DOEPTSIZ = DOEPTSIZ_SETUPCNT(3); + otgp->oe[0].DOEPCTL = DOEPCTL_SETD0PID | DOEPCTL_USBACEPT | DOEPCTL_EPTYPE_CTRL | + DOEPCTL_MPS(ep0config.out_maxsize); otgp->ie[0].DIEPTSIZ = 0; - otgp->ie[0].DIEPCTL = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_CTRL | - DIEPCTL_TXFNUM(0) | DIEPCTL_MPSIZ(ep0config.in_maxsize); - otgp->DIEPTXF0 = DIEPTXF_INEPTXFD(ep0config.in_maxsize / 4) | - DIEPTXF_INEPTXSA(otg_ram_alloc(usbp, + otgp->ie[0].DIEPCTL = DIEPCTL_SETD0PID | DIEPCTL_USBACEPT | DIEPCTL_EPTYPE_CTRL | + DIEPCTL_TXFNUM(0) | DIEPCTL_MPS(ep0config.in_maxsize); + otgp->DIEPTXF0 = DIEPTXF_INEPTXFDEP(ep0config.in_maxsize / 4) | + DIEPTXF_INEPTXFSTADDR(otg_ram_alloc(usbp, ep0config.in_maxsize / 4)); } @@ -984,7 +985,7 @@ void usb_lld_reset(USBDriver *usbp) { void usb_lld_set_address(USBDriver *usbp) { at32_otg_t *otgp = usbp->otg; - otgp->DCFG = (otgp->DCFG & ~DCFG_DAD_MASK) | DCFG_DAD(usbp->address); + otgp->DCFG = (otgp->DCFG & ~DCFG_DEVADDR_MASK) | DCFG_DEVADDR(usbp->address); } /** @@ -1002,16 +1003,16 @@ void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) { /* IN and OUT common parameters.*/ switch (usbp->epc[ep]->ep_mode & USB_EP_MODE_TYPE) { case USB_EP_MODE_TYPE_CTRL: - ctl = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_CTRL; + ctl = DIEPCTL_SETD0PID | DIEPCTL_USBACEPT | DIEPCTL_EPTYPE_CTRL; break; case USB_EP_MODE_TYPE_ISOC: - ctl = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_ISO; + ctl = DIEPCTL_SETD0PID | DIEPCTL_USBACEPT | DIEPCTL_EPTYPE_ISO; break; case USB_EP_MODE_TYPE_BULK: - ctl = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_BULK; + ctl = DIEPCTL_SETD0PID | DIEPCTL_USBACEPT | DIEPCTL_EPTYPE_BULK; break; case USB_EP_MODE_TYPE_INTR: - ctl = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_INTR; + ctl = DIEPCTL_SETD0PID | DIEPCTL_USBACEPT | DIEPCTL_EPTYPE_INTR; break; default: return; @@ -1020,12 +1021,12 @@ void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) { /* OUT endpoint activation or deactivation.*/ otgp->oe[ep].DOEPTSIZ = 0; if (usbp->epc[ep]->out_state != NULL) { - otgp->oe[ep].DOEPCTL = ctl | DOEPCTL_MPSIZ(usbp->epc[ep]->out_maxsize); - otgp->DAINTMSK |= DAINTMSK_OEPM(ep); + otgp->oe[ep].DOEPCTL = ctl | DOEPCTL_MPS(usbp->epc[ep]->out_maxsize); + otgp->DAINTMSK |= DAINTMSK_OUTEPTMSK(ep); } else { - otgp->oe[ep].DOEPCTL &= ~DOEPCTL_USBAEP; - otgp->DAINTMSK &= ~DAINTMSK_OEPM(ep); + otgp->oe[ep].DOEPCTL &= ~DOEPCTL_USBACEPT; + otgp->DAINTMSK &= ~DAINTMSK_OUTEPTMSK(ep); } /* IN endpoint activation or deactivation.*/ @@ -1035,20 +1036,20 @@ void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) { fsize = usbp->epc[ep]->in_maxsize / 4; if (usbp->epc[ep]->in_multiplier > 1) fsize *= usbp->epc[ep]->in_multiplier; - otgp->DIEPTXF[ep - 1] = DIEPTXF_INEPTXFD(fsize) | - DIEPTXF_INEPTXSA(otg_ram_alloc(usbp, fsize)); + otgp->DIEPTXF[ep - 1] = DIEPTXF_INEPTXFDEP(fsize) | + DIEPTXF_INEPTXFSTADDR(otg_ram_alloc(usbp, fsize)); otg_txfifo_flush(usbp, ep); otgp->ie[ep].DIEPCTL = ctl | DIEPCTL_TXFNUM(ep) | - DIEPCTL_MPSIZ(usbp->epc[ep]->in_maxsize); - otgp->DAINTMSK |= DAINTMSK_IEPM(ep); + DIEPCTL_MPS(usbp->epc[ep]->in_maxsize); + otgp->DAINTMSK |= DAINTMSK_INEPTMSK(ep); } else { otgp->DIEPTXF[ep - 1] = 0x02000400; /* Reset value.*/ otg_txfifo_flush(usbp, ep); - otgp->ie[ep].DIEPCTL &= ~DIEPCTL_USBAEP; - otgp->DAINTMSK &= ~DAINTMSK_IEPM(ep); + otgp->ie[ep].DIEPCTL &= ~DIEPCTL_USBACEPT; + otgp->DAINTMSK &= ~DAINTMSK_INEPTMSK(ep); } } @@ -1086,7 +1087,7 @@ usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep) { (void)usbp; ctl = usbp->otg->oe[ep].DOEPCTL; - if (!(ctl & DOEPCTL_USBAEP)) + if (!(ctl & DOEPCTL_USBACEPT)) return EP_STATUS_DISABLED; if (ctl & DOEPCTL_STALL) return EP_STATUS_STALLED; @@ -1111,7 +1112,7 @@ usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep) { (void)usbp; ctl = usbp->otg->ie[ep].DIEPCTL; - if (!(ctl & DIEPCTL_USBAEP)) + if (!(ctl & DIEPCTL_USBACEPT)) return EP_STATUS_DISABLED; if (ctl & DIEPCTL_STALL) return EP_STATUS_STALLED; @@ -1164,20 +1165,20 @@ void usb_lld_start_out(USBDriver *usbp, usbep_t ep) { rxsize = (pcnt * usbp->epc[ep]->out_maxsize + 3U) & 0xFFFFFFFCU; /* Setting up transaction parameters in DOEPTSIZ.*/ - usbp->otg->oe[ep].DOEPTSIZ = DOEPTSIZ_STUPCNT(3) | DOEPTSIZ_PKTCNT(pcnt) | - DOEPTSIZ_XFRSIZ(rxsize); + usbp->otg->oe[ep].DOEPTSIZ = DOEPTSIZ_SETUPCNT(3) | DOEPTSIZ_PKTCNT(pcnt) | + DOEPTSIZ_XFERSIZE(rxsize); /* Special case of isochronous endpoint.*/ if ((usbp->epc[ep]->ep_mode & USB_EP_MODE_TYPE) == USB_EP_MODE_TYPE_ISOC) { /* Odd/even bit toggling for isochronous endpoint.*/ - if (usbp->otg->DSTS & DSTS_FNSOF_ODD) - usbp->otg->oe[ep].DOEPCTL |= DOEPCTL_SEVNFRM; + if (usbp->otg->DSTS & DSTS_SOFFN_ODD) + usbp->otg->oe[ep].DOEPCTL |= DOEPCTL_SETEVENFR; else - usbp->otg->oe[ep].DOEPCTL |= DOEPCTL_SODDFRM; + usbp->otg->oe[ep].DOEPCTL |= DOEPCTL_SETODDFR; } /* Starting operation.*/ - usbp->otg->oe[ep].DOEPCTL |= DOEPCTL_EPENA | DOEPCTL_CNAK; + usbp->otg->oe[ep].DOEPCTL |= DOEPCTL_EPTENA | DOEPCTL_CNAK; } /** @@ -1195,7 +1196,7 @@ void usb_lld_start_in(USBDriver *usbp, usbep_t ep) { isp->totsize = isp->txsize; if (isp->txsize == 0) { /* Special case, sending zero size packet.*/ - usbp->otg->ie[ep].DIEPTSIZ = DIEPTSIZ_PKTCNT(1) | DIEPTSIZ_XFRSIZ(0); + usbp->otg->ie[ep].DIEPTSIZ = DIEPTSIZ_PKTCNT(1) | DIEPTSIZ_XFERSIZE(0); } else { if ((ep == 0) && (isp->txsize > EP0_MAX_INSIZE)) @@ -1205,22 +1206,22 @@ void usb_lld_start_in(USBDriver *usbp, usbep_t ep) { uint32_t pcnt = (isp->txsize + usbp->epc[ep]->in_maxsize - 1) / usbp->epc[ep]->in_maxsize; /* CHTODO: Support more than one packet per frame for isochronous transfers.*/ - usbp->otg->ie[ep].DIEPTSIZ = DIEPTSIZ_MCNT(1) | DIEPTSIZ_PKTCNT(pcnt) | - DIEPTSIZ_XFRSIZ(isp->txsize); + usbp->otg->ie[ep].DIEPTSIZ = DIEPTSIZ_MC(1) | DIEPTSIZ_PKTCNT(pcnt) | + DIEPTSIZ_XFERSIZE(isp->txsize); } /* Special case of isochronous endpoint.*/ if ((usbp->epc[ep]->ep_mode & USB_EP_MODE_TYPE) == USB_EP_MODE_TYPE_ISOC) { /* Odd/even bit toggling.*/ - if (usbp->otg->DSTS & DSTS_FNSOF_ODD) - usbp->otg->ie[ep].DIEPCTL |= DIEPCTL_SEVNFRM; + if (usbp->otg->DSTS & DSTS_SOFFN_ODD) + usbp->otg->ie[ep].DIEPCTL |= DIEPCTL_SETEVENFR; else - usbp->otg->ie[ep].DIEPCTL |= DIEPCTL_SODDFRM; + usbp->otg->ie[ep].DIEPCTL |= DIEPCTL_SETODDFR; } /* Starting operation.*/ - usbp->otg->ie[ep].DIEPCTL |= DIEPCTL_EPENA | DIEPCTL_CNAK; - usbp->otg->DIEPEMPMSK |= DIEPEMPMSK_INEPTXFEM(ep); + usbp->otg->ie[ep].DIEPCTL |= DIEPCTL_EPTENA | DIEPCTL_CNAK; + usbp->otg->DIEPEMPMSK |= DIEPEMPMSK_INEPTXFEMSK(ep); } /** diff --git a/os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.h b/os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.h index d205b2be5a..56cfc90b9d 100644 --- a/os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.h +++ b/os/hal/ports/AT32/LLD/OTGv1/hal_usb_lld.h @@ -518,9 +518,9 @@ struct USBDriver { * @notapi */ #if (AT32_OTG_STEPPING == 1) || defined(__DOXYGEN__) -#define usb_lld_connect_bus(usbp) ((usbp)->otg->GCCFG |= GCCFG_VBUSBSEN) +#define usb_lld_connect_bus(usbp) ((usbp)->otg->GCCFG |= GCCFG_BVALIDSESEN) #else -#define usb_lld_connect_bus(usbp) ((usbp)->otg->DCTL &= ~DCTL_SDIS) +#define usb_lld_connect_bus(usbp) ((usbp)->otg->DCTL &= ~DCTL_SFTDISCON) #endif /** @@ -529,9 +529,9 @@ struct USBDriver { * @notapi */ #if (AT32_OTG_STEPPING == 1) || defined(__DOXYGEN__) -#define usb_lld_disconnect_bus(usbp) ((usbp)->otg->GCCFG &= ~GCCFG_VBUSBSEN) +#define usb_lld_disconnect_bus(usbp) ((usbp)->otg->GCCFG &= ~GCCFG_BVALIDSESEN) #else -#define usb_lld_disconnect_bus(usbp) ((usbp)->otg->DCTL |= DCTL_SDIS) +#define usb_lld_disconnect_bus(usbp) ((usbp)->otg->DCTL |= DCTL_SFTDISCON) #endif /** @@ -541,13 +541,13 @@ struct USBDriver { */ #define usb_lld_wakeup_host(usbp) \ do { \ - (usbp)->otg->DCTL |= DCTL_RWUSIG; \ + (usbp)->otg->DCTL |= DCTL_RWKUPSIG; \ /* remote wakeup doesn't trigger the wakeup interrupt, therefore we use the SOF interrupt to detect resume of the bus.*/ \ (usbp)->otg->GINTSTS |= GINTSTS_SOF; \ - (usbp)->otg->GINTMSK |= GINTMSK_SOFM; \ + (usbp)->otg->GINTMSK |= GINTMSK_SOFMSK; \ osalThreadSleepMilliseconds(AT32_USB_HOST_WAKEUP_DURATION); \ - (usbp)->otg->DCTL &= ~DCTL_RWUSIG; \ + (usbp)->otg->DCTL &= ~DCTL_RWKUPSIG; \ } while (false) /*===========================================================================*/ From 91f62836dd71a7c9436d282fec87cb20f1fa296d Mon Sep 17 00:00:00 2001 From: HorrorTroll Date: Sat, 2 Mar 2024 13:13:56 +0700 Subject: [PATCH 02/19] Update registry for DMAMUX channel --- os/hal/ports/AT32/AT32F415/at32_registry.h | 480 ++++++++++----------- 1 file changed, 240 insertions(+), 240 deletions(-) diff --git a/os/hal/ports/AT32/AT32F415/at32_registry.h b/os/hal/ports/AT32/AT32F415/at32_registry.h index 859e24d829..93463f5fc4 100644 --- a/os/hal/ports/AT32/AT32F415/at32_registry.h +++ b/os/hal/ports/AT32/AT32F415/at32_registry.h @@ -62,8 +62,8 @@ #define AT32_HAS_ADC1 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID(1, 1) -#define AT32_ADC_ADC1_DMAMUX_CHANNEL 1 +#define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) +#define AT32_ADC_ADC1_DMAMUX_CHANNEL 2 #else #define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID(1, 1) #endif @@ -105,10 +105,10 @@ #define AT32_HAS_I2C1 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_I2C_I2C1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) -#define AT32_I2C_I2C1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) -#define AT32_I2C_I2C1_RX_DMAMUX_CHANNEL 2 -#define AT32_I2C_I2C1_TX_DMAMUX_CHANNEL 3 +#define AT32_I2C_I2C1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) +#define AT32_I2C_I2C1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) +#define AT32_I2C_I2C1_RX_DMAMUX_CHANNEL 3 +#define AT32_I2C_I2C1_TX_DMAMUX_CHANNEL 4 #else #define AT32_I2C_I2C1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) #define AT32_I2C_I2C1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) @@ -117,10 +117,10 @@ #define AT32_HAS_I2C2 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_I2C_I2C2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) -#define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) -#define AT32_I2C_I2C2_RX_DMAMUX_CHANNEL 2 -#define AT32_I2C_I2C2_TX_DMAMUX_CHANNEL 3 +#define AT32_I2C_I2C2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) +#define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) +#define AT32_I2C_I2C2_RX_DMAMUX_CHANNEL 3 +#define AT32_I2C_I2C2_TX_DMAMUX_CHANNEL 4 #else #define AT32_I2C_I2C2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) #define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) @@ -137,8 +137,8 @@ #define AT32_HAS_SDIO1 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) -#define AT32_SDC_SDIO1_DMAMUX_CHANNEL 4 +#define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#define AT32_SDC_SDIO1_DMAMUX_CHANNEL 5 #else #define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(2, 4) #endif @@ -149,10 +149,10 @@ #define AT32_SPI1_I2S_FULLDUPLEX FALSE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_SPI_SPI1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) -#define AT32_SPI_SPI1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) -#define AT32_SPI_SPI1_RX_DMAMUX_CHANNEL 5 -#define AT32_SPI_SPI1_TX_DMAMUX_CHANNEL 6 +#define AT32_SPI_SPI1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) +#define AT32_SPI_SPI1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_SPI_SPI1_RX_DMAMUX_CHANNEL 6 +#define AT32_SPI_SPI1_TX_DMAMUX_CHANNEL 7 #else #define AT32_SPI_SPI1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) #define AT32_SPI_SPI1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) @@ -163,10 +163,10 @@ #define AT32_SPI2_I2S_FULLDUPLEX FALSE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_SPI_SPI2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) -#define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) -#define AT32_SPI_SPI2_RX_DMAMUX_CHANNEL 5 -#define AT32_SPI_SPI2_TX_DMAMUX_CHANNEL 6 +#define AT32_SPI_SPI2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) +#define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_SPI_SPI2_RX_DMAMUX_CHANNEL 6 +#define AT32_SPI_SPI2_TX_DMAMUX_CHANNEL 7 #else #define AT32_SPI_SPI2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) #define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) @@ -211,10 +211,10 @@ #define AT32_HAS_USART1 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_USART1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#define AT32_UART_USART1_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_USART1_RX_DMAMUX_CHANNEL 7 -#define AT32_UART_USART1_TX_DMAMUX_CHANNEL 1 +#define AT32_UART_USART1_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_USART1_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) +#define AT32_UART_USART1_RX_DMAMUX_CHANNEL 1 +#define AT32_UART_USART1_TX_DMAMUX_CHANNEL 2 #else #define AT32_UART_USART1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) #define AT32_UART_USART1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) @@ -223,10 +223,10 @@ #define AT32_HAS_USART2 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_USART2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#define AT32_UART_USART2_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_USART2_RX_DMAMUX_CHANNEL 7 -#define AT32_UART_USART2_TX_DMAMUX_CHANNEL 1 +#define AT32_UART_USART2_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_USART2_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) +#define AT32_UART_USART2_RX_DMAMUX_CHANNEL 1 +#define AT32_UART_USART2_TX_DMAMUX_CHANNEL 2 #else #define AT32_UART_USART2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) #define AT32_UART_USART2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) @@ -235,10 +235,10 @@ #define AT32_HAS_USART3 FALSE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_USART3_RX_DMAMUX_CHANNEL 7 -#define AT32_UART_USART3_TX_DMAMUX_CHANNEL 1 +#define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) +#define AT32_UART_USART3_RX_DMAMUX_CHANNEL 1 +#define AT32_UART_USART3_TX_DMAMUX_CHANNEL 2 #else #define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) #define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) @@ -247,10 +247,10 @@ #define AT32_HAS_UART4 FALSE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_UART4_RX_DMAMUX_CHANNEL 7 -#define AT32_UART_UART4_TX_DMAMUX_CHANNEL 1 +#define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) +#define AT32_UART_UART4_RX_DMAMUX_CHANNEL 1 +#define AT32_UART_UART4_TX_DMAMUX_CHANNEL 2 #else #define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 3) #define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 5) @@ -259,10 +259,10 @@ #define AT32_HAS_UART5 FALSE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_UART5_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#define AT32_UART_UART5_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_UART5_RX_DMAMUX_CHANNEL 7 -#define AT32_UART_UART5_TX_DMAMUX_CHANNEL 1 +#define AT32_UART_UART5_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_UART5_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) +#define AT32_UART_UART5_RX_DMAMUX_CHANNEL 1 +#define AT32_UART_UART5_TX_DMAMUX_CHANNEL 2 #endif /* USB attributes.*/ @@ -287,8 +287,8 @@ #define AT32_HAS_ADC1 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID(1, 1) -#define AT32_ADC_ADC1_DMAMUX_CHANNEL 1 +#define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) +#define AT32_ADC_ADC1_DMAMUX_CHANNEL 2 #else #define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID(1, 1) #endif @@ -330,10 +330,10 @@ #define AT32_HAS_I2C1 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_I2C_I2C1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) -#define AT32_I2C_I2C1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) -#define AT32_I2C_I2C1_RX_DMAMUX_CHANNEL 2 -#define AT32_I2C_I2C1_TX_DMAMUX_CHANNEL 3 +#define AT32_I2C_I2C1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) +#define AT32_I2C_I2C1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) +#define AT32_I2C_I2C1_RX_DMAMUX_CHANNEL 3 +#define AT32_I2C_I2C1_TX_DMAMUX_CHANNEL 4 #else #define AT32_I2C_I2C1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) #define AT32_I2C_I2C1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) @@ -342,10 +342,10 @@ #define AT32_HAS_I2C2 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_I2C_I2C2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) -#define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) -#define AT32_I2C_I2C2_RX_DMAMUX_CHANNEL 2 -#define AT32_I2C_I2C2_TX_DMAMUX_CHANNEL 3 +#define AT32_I2C_I2C2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) +#define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) +#define AT32_I2C_I2C2_RX_DMAMUX_CHANNEL 3 +#define AT32_I2C_I2C2_TX_DMAMUX_CHANNEL 4 #else #define AT32_I2C_I2C2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) #define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) @@ -362,8 +362,8 @@ #define AT32_HAS_SDIO1 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) -#define AT32_SDC_SDIO1_DMAMUX_CHANNEL 4 +#define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#define AT32_SDC_SDIO1_DMAMUX_CHANNEL 5 #else #define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(2, 4) #endif @@ -374,10 +374,10 @@ #define AT32_SPI1_I2S_FULLDUPLEX FALSE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_SPI_SPI1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) -#define AT32_SPI_SPI1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) -#define AT32_SPI_SPI1_RX_DMAMUX_CHANNEL 5 -#define AT32_SPI_SPI1_TX_DMAMUX_CHANNEL 6 +#define AT32_SPI_SPI1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) +#define AT32_SPI_SPI1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_SPI_SPI1_RX_DMAMUX_CHANNEL 6 +#define AT32_SPI_SPI1_TX_DMAMUX_CHANNEL 7 #else #define AT32_SPI_SPI1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) #define AT32_SPI_SPI1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) @@ -388,10 +388,10 @@ #define AT32_SPI2_I2S_FULLDUPLEX FALSE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_SPI_SPI2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) -#define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) -#define AT32_SPI_SPI2_RX_DMAMUX_CHANNEL 5 -#define AT32_SPI_SPI2_TX_DMAMUX_CHANNEL 6 +#define AT32_SPI_SPI2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) +#define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_SPI_SPI2_RX_DMAMUX_CHANNEL 6 +#define AT32_SPI_SPI2_TX_DMAMUX_CHANNEL 7 #else #define AT32_SPI_SPI2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) #define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) @@ -436,10 +436,10 @@ #define AT32_HAS_USART1 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_USART1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#define AT32_UART_USART1_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_USART1_RX_DMAMUX_CHANNEL 7 -#define AT32_UART_USART1_TX_DMAMUX_CHANNEL 1 +#define AT32_UART_USART1_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_USART1_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) +#define AT32_UART_USART1_RX_DMAMUX_CHANNEL 1 +#define AT32_UART_USART1_TX_DMAMUX_CHANNEL 2 #else #define AT32_UART_USART1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) #define AT32_UART_USART1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) @@ -448,10 +448,10 @@ #define AT32_HAS_USART2 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_USART2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#define AT32_UART_USART2_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_USART2_RX_DMAMUX_CHANNEL 7 -#define AT32_UART_USART2_TX_DMAMUX_CHANNEL 1 +#define AT32_UART_USART2_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_USART2_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) +#define AT32_UART_USART2_RX_DMAMUX_CHANNEL 1 +#define AT32_UART_USART2_TX_DMAMUX_CHANNEL 2 #else #define AT32_UART_USART2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) #define AT32_UART_USART2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) @@ -460,10 +460,10 @@ #define AT32_HAS_USART3 FALSE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_USART3_RX_DMAMUX_CHANNEL 7 -#define AT32_UART_USART3_TX_DMAMUX_CHANNEL 1 +#define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) +#define AT32_UART_USART3_RX_DMAMUX_CHANNEL 1 +#define AT32_UART_USART3_TX_DMAMUX_CHANNEL 2 #else #define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) #define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) @@ -472,10 +472,10 @@ #define AT32_HAS_UART4 FALSE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_UART4_RX_DMAMUX_CHANNEL 7 -#define AT32_UART_UART4_TX_DMAMUX_CHANNEL 1 +#define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) +#define AT32_UART_UART4_RX_DMAMUX_CHANNEL 1 +#define AT32_UART_UART4_TX_DMAMUX_CHANNEL 2 #else #define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 3) #define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 5) @@ -484,10 +484,10 @@ #define AT32_HAS_UART5 FALSE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_UART5_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#define AT32_UART_UART5_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_UART5_RX_DMAMUX_CHANNEL 7 -#define AT32_UART_UART5_TX_DMAMUX_CHANNEL 1 +#define AT32_UART_UART5_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_UART5_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) +#define AT32_UART_UART5_RX_DMAMUX_CHANNEL 1 +#define AT32_UART_UART5_TX_DMAMUX_CHANNEL 2 #endif /* USB attributes.*/ @@ -512,8 +512,8 @@ #define AT32_HAS_ADC1 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID(1, 1) -#define AT32_ADC_ADC1_DMAMUX_CHANNEL 1 +#define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) +#define AT32_ADC_ADC1_DMAMUX_CHANNEL 2 #else #define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID(1, 1) #endif @@ -555,10 +555,10 @@ #define AT32_HAS_I2C1 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_I2C_I2C1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) -#define AT32_I2C_I2C1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) -#define AT32_I2C_I2C1_RX_DMAMUX_CHANNEL 2 -#define AT32_I2C_I2C1_TX_DMAMUX_CHANNEL 3 +#define AT32_I2C_I2C1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) +#define AT32_I2C_I2C1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) +#define AT32_I2C_I2C1_RX_DMAMUX_CHANNEL 3 +#define AT32_I2C_I2C1_TX_DMAMUX_CHANNEL 4 #else #define AT32_I2C_I2C1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) #define AT32_I2C_I2C1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) @@ -567,10 +567,10 @@ #define AT32_HAS_I2C2 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_I2C_I2C2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) -#define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) -#define AT32_I2C_I2C2_RX_DMAMUX_CHANNEL 2 -#define AT32_I2C_I2C2_TX_DMAMUX_CHANNEL 3 +#define AT32_I2C_I2C2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) +#define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) +#define AT32_I2C_I2C2_RX_DMAMUX_CHANNEL 3 +#define AT32_I2C_I2C2_TX_DMAMUX_CHANNEL 4 #else #define AT32_I2C_I2C2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) #define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) @@ -587,8 +587,8 @@ #define AT32_HAS_SDIO1 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) -#define AT32_SDC_SDIO1_DMAMUX_CHANNEL 4 +#define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#define AT32_SDC_SDIO1_DMAMUX_CHANNEL 5 #else #define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(2, 4) #endif @@ -599,10 +599,10 @@ #define AT32_SPI1_I2S_FULLDUPLEX FALSE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_SPI_SPI1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) -#define AT32_SPI_SPI1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) -#define AT32_SPI_SPI1_RX_DMAMUX_CHANNEL 5 -#define AT32_SPI_SPI1_TX_DMAMUX_CHANNEL 6 +#define AT32_SPI_SPI1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) +#define AT32_SPI_SPI1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_SPI_SPI1_RX_DMAMUX_CHANNEL 6 +#define AT32_SPI_SPI1_TX_DMAMUX_CHANNEL 7 #else #define AT32_SPI_SPI1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) #define AT32_SPI_SPI1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) @@ -613,10 +613,10 @@ #define AT32_SPI2_I2S_FULLDUPLEX FALSE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_SPI_SPI2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) -#define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) -#define AT32_SPI_SPI2_RX_DMAMUX_CHANNEL 5 -#define AT32_SPI_SPI2_TX_DMAMUX_CHANNEL 6 +#define AT32_SPI_SPI2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) +#define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_SPI_SPI2_RX_DMAMUX_CHANNEL 6 +#define AT32_SPI_SPI2_TX_DMAMUX_CHANNEL 7 #else #define AT32_SPI_SPI2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) #define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) @@ -661,10 +661,10 @@ #define AT32_HAS_USART1 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_USART1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#define AT32_UART_USART1_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_USART1_RX_DMAMUX_CHANNEL 7 -#define AT32_UART_USART1_TX_DMAMUX_CHANNEL 1 +#define AT32_UART_USART1_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_USART1_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) +#define AT32_UART_USART1_RX_DMAMUX_CHANNEL 1 +#define AT32_UART_USART1_TX_DMAMUX_CHANNEL 2 #else #define AT32_UART_USART1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) #define AT32_UART_USART1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) @@ -673,10 +673,10 @@ #define AT32_HAS_USART2 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_USART2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#define AT32_UART_USART2_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_USART2_RX_DMAMUX_CHANNEL 7 -#define AT32_UART_USART2_TX_DMAMUX_CHANNEL 1 +#define AT32_UART_USART2_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_USART2_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) +#define AT32_UART_USART2_RX_DMAMUX_CHANNEL 1 +#define AT32_UART_USART2_TX_DMAMUX_CHANNEL 2 #else #define AT32_UART_USART2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) #define AT32_UART_USART2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) @@ -685,10 +685,10 @@ #define AT32_HAS_USART3 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_USART3_RX_DMAMUX_CHANNEL 7 -#define AT32_UART_USART3_TX_DMAMUX_CHANNEL 1 +#define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) +#define AT32_UART_USART3_RX_DMAMUX_CHANNEL 1 +#define AT32_UART_USART3_TX_DMAMUX_CHANNEL 2 #else #define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) #define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) @@ -697,10 +697,10 @@ #define AT32_HAS_UART4 FALSE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_UART4_RX_DMAMUX_CHANNEL 7 -#define AT32_UART_UART4_TX_DMAMUX_CHANNEL 1 +#define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) +#define AT32_UART_UART4_RX_DMAMUX_CHANNEL 1 +#define AT32_UART_UART4_TX_DMAMUX_CHANNEL 2 #else #define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 3) #define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 5) @@ -709,10 +709,10 @@ #define AT32_HAS_UART5 FALSE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_UART5_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#define AT32_UART_UART5_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_UART5_RX_DMAMUX_CHANNEL 7 -#define AT32_UART_UART5_TX_DMAMUX_CHANNEL 1 +#define AT32_UART_UART5_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_UART5_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) +#define AT32_UART_UART5_RX_DMAMUX_CHANNEL 1 +#define AT32_UART_UART5_TX_DMAMUX_CHANNEL 2 #endif /* USB attributes.*/ @@ -737,8 +737,8 @@ #define AT32_HAS_ADC1 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID(1, 1) -#define AT32_ADC_ADC1_DMAMUX_CHANNEL 1 +#define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) +#define AT32_ADC_ADC1_DMAMUX_CHANNEL 2 #else #define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID(1, 1) #endif @@ -780,10 +780,10 @@ #define AT32_HAS_I2C1 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_I2C_I2C1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) -#define AT32_I2C_I2C1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) -#define AT32_I2C_I2C1_RX_DMAMUX_CHANNEL 2 -#define AT32_I2C_I2C1_TX_DMAMUX_CHANNEL 3 +#define AT32_I2C_I2C1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) +#define AT32_I2C_I2C1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) +#define AT32_I2C_I2C1_RX_DMAMUX_CHANNEL 3 +#define AT32_I2C_I2C1_TX_DMAMUX_CHANNEL 4 #else #define AT32_I2C_I2C1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) #define AT32_I2C_I2C1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) @@ -792,10 +792,10 @@ #define AT32_HAS_I2C2 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_I2C_I2C2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) -#define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) -#define AT32_I2C_I2C2_RX_DMAMUX_CHANNEL 2 -#define AT32_I2C_I2C2_TX_DMAMUX_CHANNEL 3 +#define AT32_I2C_I2C2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) +#define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) +#define AT32_I2C_I2C2_RX_DMAMUX_CHANNEL 3 +#define AT32_I2C_I2C2_TX_DMAMUX_CHANNEL 4 #else #define AT32_I2C_I2C2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) #define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) @@ -812,8 +812,8 @@ #define AT32_HAS_SDIO1 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) -#define AT32_SDC_SDIO1_DMAMUX_CHANNEL 4 +#define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#define AT32_SDC_SDIO1_DMAMUX_CHANNEL 5 #else #define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(2, 4) #endif @@ -824,10 +824,10 @@ #define AT32_SPI1_I2S_FULLDUPLEX FALSE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_SPI_SPI1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) -#define AT32_SPI_SPI1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) -#define AT32_SPI_SPI1_RX_DMAMUX_CHANNEL 5 -#define AT32_SPI_SPI1_TX_DMAMUX_CHANNEL 6 +#define AT32_SPI_SPI1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) +#define AT32_SPI_SPI1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_SPI_SPI1_RX_DMAMUX_CHANNEL 6 +#define AT32_SPI_SPI1_TX_DMAMUX_CHANNEL 7 #else #define AT32_SPI_SPI1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) #define AT32_SPI_SPI1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) @@ -838,10 +838,10 @@ #define AT32_SPI2_I2S_FULLDUPLEX FALSE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_SPI_SPI2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) -#define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) -#define AT32_SPI_SPI2_RX_DMAMUX_CHANNEL 5 -#define AT32_SPI_SPI2_TX_DMAMUX_CHANNEL 6 +#define AT32_SPI_SPI2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) +#define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_SPI_SPI2_RX_DMAMUX_CHANNEL 6 +#define AT32_SPI_SPI2_TX_DMAMUX_CHANNEL 7 #else #define AT32_SPI_SPI2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) #define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) @@ -886,10 +886,10 @@ #define AT32_HAS_USART1 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_USART1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#define AT32_UART_USART1_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_USART1_RX_DMAMUX_CHANNEL 7 -#define AT32_UART_USART1_TX_DMAMUX_CHANNEL 1 +#define AT32_UART_USART1_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_USART1_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) +#define AT32_UART_USART1_RX_DMAMUX_CHANNEL 1 +#define AT32_UART_USART1_TX_DMAMUX_CHANNEL 2 #else #define AT32_UART_USART1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) #define AT32_UART_USART1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) @@ -898,10 +898,10 @@ #define AT32_HAS_USART2 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_USART2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#define AT32_UART_USART2_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_USART2_RX_DMAMUX_CHANNEL 7 -#define AT32_UART_USART2_TX_DMAMUX_CHANNEL 1 +#define AT32_UART_USART2_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_USART2_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) +#define AT32_UART_USART2_RX_DMAMUX_CHANNEL 1 +#define AT32_UART_USART2_TX_DMAMUX_CHANNEL 2 #else #define AT32_UART_USART2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) #define AT32_UART_USART2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) @@ -910,10 +910,10 @@ #define AT32_HAS_USART3 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_USART3_RX_DMAMUX_CHANNEL 7 -#define AT32_UART_USART3_TX_DMAMUX_CHANNEL 1 +#define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) +#define AT32_UART_USART3_RX_DMAMUX_CHANNEL 1 +#define AT32_UART_USART3_TX_DMAMUX_CHANNEL 2 #else #define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) #define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) @@ -922,10 +922,10 @@ #define AT32_HAS_UART4 FALSE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_UART4_RX_DMAMUX_CHANNEL 7 -#define AT32_UART_UART4_TX_DMAMUX_CHANNEL 1 +#define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) +#define AT32_UART_UART4_RX_DMAMUX_CHANNEL 1 +#define AT32_UART_UART4_TX_DMAMUX_CHANNEL 2 #else #define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 3) #define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 5) @@ -934,10 +934,10 @@ #define AT32_HAS_UART5 FALSE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_UART5_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#define AT32_UART_UART5_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_UART5_RX_DMAMUX_CHANNEL 7 -#define AT32_UART_UART5_TX_DMAMUX_CHANNEL 1 +#define AT32_UART_UART5_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_UART5_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) +#define AT32_UART_UART5_RX_DMAMUX_CHANNEL 1 +#define AT32_UART_UART5_TX_DMAMUX_CHANNEL 2 #endif /* USB attributes.*/ @@ -962,8 +962,8 @@ #define AT32_HAS_ADC1 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID(1, 1) -#define AT32_ADC_ADC1_DMAMUX_CHANNEL 1 +#define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) +#define AT32_ADC_ADC1_DMAMUX_CHANNEL 2 #else #define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID(1, 1) #endif @@ -1005,10 +1005,10 @@ #define AT32_HAS_I2C1 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_I2C_I2C1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) -#define AT32_I2C_I2C1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) -#define AT32_I2C_I2C1_RX_DMAMUX_CHANNEL 2 -#define AT32_I2C_I2C1_TX_DMAMUX_CHANNEL 3 +#define AT32_I2C_I2C1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) +#define AT32_I2C_I2C1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) +#define AT32_I2C_I2C1_RX_DMAMUX_CHANNEL 3 +#define AT32_I2C_I2C1_TX_DMAMUX_CHANNEL 4 #else #define AT32_I2C_I2C1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) #define AT32_I2C_I2C1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) @@ -1017,10 +1017,10 @@ #define AT32_HAS_I2C2 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_I2C_I2C2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) -#define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) -#define AT32_I2C_I2C2_RX_DMAMUX_CHANNEL 2 -#define AT32_I2C_I2C2_TX_DMAMUX_CHANNEL 3 +#define AT32_I2C_I2C2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) +#define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) +#define AT32_I2C_I2C2_RX_DMAMUX_CHANNEL 3 +#define AT32_I2C_I2C2_TX_DMAMUX_CHANNEL 4 #else #define AT32_I2C_I2C2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) #define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) @@ -1037,8 +1037,8 @@ #define AT32_HAS_SDIO1 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) -#define AT32_SDC_SDIO1_DMAMUX_CHANNEL 4 +#define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#define AT32_SDC_SDIO1_DMAMUX_CHANNEL 5 #else #define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(2, 4) #endif @@ -1049,10 +1049,10 @@ #define AT32_SPI1_I2S_FULLDUPLEX FALSE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_SPI_SPI1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) -#define AT32_SPI_SPI1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) -#define AT32_SPI_SPI1_RX_DMAMUX_CHANNEL 5 -#define AT32_SPI_SPI1_TX_DMAMUX_CHANNEL 6 +#define AT32_SPI_SPI1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) +#define AT32_SPI_SPI1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_SPI_SPI1_RX_DMAMUX_CHANNEL 6 +#define AT32_SPI_SPI1_TX_DMAMUX_CHANNEL 7 #else #define AT32_SPI_SPI1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) #define AT32_SPI_SPI1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) @@ -1063,10 +1063,10 @@ #define AT32_SPI2_I2S_FULLDUPLEX FALSE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_SPI_SPI2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) -#define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) -#define AT32_SPI_SPI2_RX_DMAMUX_CHANNEL 5 -#define AT32_SPI_SPI2_TX_DMAMUX_CHANNEL 6 +#define AT32_SPI_SPI2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) +#define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_SPI_SPI2_RX_DMAMUX_CHANNEL 6 +#define AT32_SPI_SPI2_TX_DMAMUX_CHANNEL 7 #else #define AT32_SPI_SPI2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) #define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) @@ -1111,10 +1111,10 @@ #define AT32_HAS_USART1 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_USART1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#define AT32_UART_USART1_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_USART1_RX_DMAMUX_CHANNEL 7 -#define AT32_UART_USART1_TX_DMAMUX_CHANNEL 1 +#define AT32_UART_USART1_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_USART1_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) +#define AT32_UART_USART1_RX_DMAMUX_CHANNEL 1 +#define AT32_UART_USART1_TX_DMAMUX_CHANNEL 2 #else #define AT32_UART_USART1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) #define AT32_UART_USART1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) @@ -1123,10 +1123,10 @@ #define AT32_HAS_USART2 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_USART2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#define AT32_UART_USART2_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_USART2_RX_DMAMUX_CHANNEL 7 -#define AT32_UART_USART2_TX_DMAMUX_CHANNEL 1 +#define AT32_UART_USART2_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_USART2_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) +#define AT32_UART_USART2_RX_DMAMUX_CHANNEL 1 +#define AT32_UART_USART2_TX_DMAMUX_CHANNEL 2 #else #define AT32_UART_USART2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) #define AT32_UART_USART2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) @@ -1135,10 +1135,10 @@ #define AT32_HAS_USART3 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_USART3_RX_DMAMUX_CHANNEL 7 -#define AT32_UART_USART3_TX_DMAMUX_CHANNEL 1 +#define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) +#define AT32_UART_USART3_RX_DMAMUX_CHANNEL 1 +#define AT32_UART_USART3_TX_DMAMUX_CHANNEL 2 #else #define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) #define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) @@ -1147,10 +1147,10 @@ #define AT32_HAS_UART4 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_UART4_RX_DMAMUX_CHANNEL 7 -#define AT32_UART_UART4_TX_DMAMUX_CHANNEL 1 +#define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) +#define AT32_UART_UART4_RX_DMAMUX_CHANNEL 1 +#define AT32_UART_UART4_TX_DMAMUX_CHANNEL 2 #else #define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 3) #define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 5) @@ -1159,10 +1159,10 @@ #define AT32_HAS_UART5 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_UART5_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#define AT32_UART_UART5_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_UART5_RX_DMAMUX_CHANNEL 7 -#define AT32_UART_UART5_TX_DMAMUX_CHANNEL 1 +#define AT32_UART_UART5_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_UART5_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) +#define AT32_UART_UART5_RX_DMAMUX_CHANNEL 1 +#define AT32_UART_UART5_TX_DMAMUX_CHANNEL 2 #endif /* USB attributes.*/ @@ -1187,8 +1187,8 @@ #define AT32_HAS_ADC1 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID(1, 1) -#define AT32_ADC_ADC1_DMAMUX_CHANNEL 1 +#define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) +#define AT32_ADC_ADC1_DMAMUX_CHANNEL 2 #else #define AT32_ADC_ADC1_DMA_STREAM AT32_DMA_STREAM_ID(1, 1) #endif @@ -1230,10 +1230,10 @@ #define AT32_HAS_I2C1 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_I2C_I2C1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) -#define AT32_I2C_I2C1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) -#define AT32_I2C_I2C1_RX_DMAMUX_CHANNEL 2 -#define AT32_I2C_I2C1_TX_DMAMUX_CHANNEL 3 +#define AT32_I2C_I2C1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) +#define AT32_I2C_I2C1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) +#define AT32_I2C_I2C1_RX_DMAMUX_CHANNEL 3 +#define AT32_I2C_I2C1_TX_DMAMUX_CHANNEL 4 #else #define AT32_I2C_I2C1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) #define AT32_I2C_I2C1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) @@ -1242,10 +1242,10 @@ #define AT32_HAS_I2C2 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_I2C_I2C2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) -#define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) -#define AT32_I2C_I2C2_RX_DMAMUX_CHANNEL 2 -#define AT32_I2C_I2C2_TX_DMAMUX_CHANNEL 3 +#define AT32_I2C_I2C2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) +#define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) +#define AT32_I2C_I2C2_RX_DMAMUX_CHANNEL 3 +#define AT32_I2C_I2C2_TX_DMAMUX_CHANNEL 4 #else #define AT32_I2C_I2C2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) #define AT32_I2C_I2C2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) @@ -1262,8 +1262,8 @@ #define AT32_HAS_SDIO1 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) -#define AT32_SDC_SDIO1_DMAMUX_CHANNEL 4 +#define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) +#define AT32_SDC_SDIO1_DMAMUX_CHANNEL 5 #else #define AT32_SDC_SDIO1_DMA_STREAM AT32_DMA_STREAM_ID(2, 4) #endif @@ -1274,10 +1274,10 @@ #define AT32_SPI1_I2S_FULLDUPLEX FALSE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_SPI_SPI1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) -#define AT32_SPI_SPI1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) -#define AT32_SPI_SPI1_RX_DMAMUX_CHANNEL 5 -#define AT32_SPI_SPI1_TX_DMAMUX_CHANNEL 6 +#define AT32_SPI_SPI1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) +#define AT32_SPI_SPI1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_SPI_SPI1_RX_DMAMUX_CHANNEL 6 +#define AT32_SPI_SPI1_TX_DMAMUX_CHANNEL 7 #else #define AT32_SPI_SPI1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) #define AT32_SPI_SPI1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) @@ -1288,10 +1288,10 @@ #define AT32_SPI2_I2S_FULLDUPLEX FALSE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_SPI_SPI2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) -#define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) -#define AT32_SPI_SPI2_RX_DMAMUX_CHANNEL 5 -#define AT32_SPI_SPI2_TX_DMAMUX_CHANNEL 6 +#define AT32_SPI_SPI2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) +#define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) +#define AT32_SPI_SPI2_RX_DMAMUX_CHANNEL 6 +#define AT32_SPI_SPI2_TX_DMAMUX_CHANNEL 7 #else #define AT32_SPI_SPI2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) #define AT32_SPI_SPI2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) @@ -1336,10 +1336,10 @@ #define AT32_HAS_USART1 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_USART1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#define AT32_UART_USART1_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_USART1_RX_DMAMUX_CHANNEL 7 -#define AT32_UART_USART1_TX_DMAMUX_CHANNEL 1 +#define AT32_UART_USART1_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_USART1_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) +#define AT32_UART_USART1_RX_DMAMUX_CHANNEL 1 +#define AT32_UART_USART1_TX_DMAMUX_CHANNEL 2 #else #define AT32_UART_USART1_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 5) #define AT32_UART_USART1_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 4) @@ -1348,10 +1348,10 @@ #define AT32_HAS_USART2 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_USART2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#define AT32_UART_USART2_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_USART2_RX_DMAMUX_CHANNEL 7 -#define AT32_UART_USART2_TX_DMAMUX_CHANNEL 1 +#define AT32_UART_USART2_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_USART2_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) +#define AT32_UART_USART2_RX_DMAMUX_CHANNEL 1 +#define AT32_UART_USART2_TX_DMAMUX_CHANNEL 2 #else #define AT32_UART_USART2_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 6) #define AT32_UART_USART2_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) @@ -1360,10 +1360,10 @@ #define AT32_HAS_USART3 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_USART3_RX_DMAMUX_CHANNEL 7 -#define AT32_UART_USART3_TX_DMAMUX_CHANNEL 1 +#define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) +#define AT32_UART_USART3_RX_DMAMUX_CHANNEL 1 +#define AT32_UART_USART3_TX_DMAMUX_CHANNEL 2 #else #define AT32_UART_USART3_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 3) #define AT32_UART_USART3_TX_DMA_STREAM AT32_DMA_STREAM_ID(1, 2) @@ -1372,10 +1372,10 @@ #define AT32_HAS_UART4 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_UART4_RX_DMAMUX_CHANNEL 7 -#define AT32_UART_UART4_TX_DMAMUX_CHANNEL 1 +#define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) +#define AT32_UART_UART4_RX_DMAMUX_CHANNEL 1 +#define AT32_UART_UART4_TX_DMAMUX_CHANNEL 2 #else #define AT32_UART_UART4_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 3) #define AT32_UART_UART4_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 5) @@ -1384,10 +1384,10 @@ #define AT32_HAS_UART5 TRUE #if (AT32_DMA_USE_DMAMUX == TRUE) || defined(__DOXYGEN__) -#define AT32_UART_UART5_RX_DMA_STREAM AT32_DMA_STREAM_ID(1, 7) -#define AT32_UART_UART5_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) -#define AT32_UART_UART5_RX_DMAMUX_CHANNEL 7 -#define AT32_UART_UART5_TX_DMAMUX_CHANNEL 1 +#define AT32_UART_UART5_RX_DMA_STREAM AT32_DMA_STREAM_ID(2, 1) +#define AT32_UART_UART5_TX_DMA_STREAM AT32_DMA_STREAM_ID(2, 2) +#define AT32_UART_UART5_RX_DMAMUX_CHANNEL 1 +#define AT32_UART_UART5_TX_DMAMUX_CHANNEL 2 #endif /* USB attributes.*/ From b8b233ae24655c11f3fb9236c5f748d6df11d114 Mon Sep 17 00:00:00 2001 From: HorrorTroll Date: Sat, 30 Mar 2024 15:59:36 +0700 Subject: [PATCH 03/19] Small changes --- os/hal/boards/AT_START_F415/board.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/os/hal/boards/AT_START_F415/board.h b/os/hal/boards/AT_START_F415/board.h index ae3de31e48..23f945bb5e 100644 --- a/os/hal/boards/AT_START_F415/board.h +++ b/os/hal/boards/AT_START_F415/board.h @@ -173,7 +173,6 @@ * PA0 - Normal input (GPIOA_BUTTON) * PA2 - Alternate output (GPIOA_ARD_D1, GPIOA_USART2_TX) * PA3 - Normal input (GPIOA_ARD_D0, GPIOA_USART2_RX) - * PA13 - Pull-up input (GPIOA_SWDIO) * PA14 - Pull-down input (GPIOA_SWCLK) */ #define VAL_GPIOACFGLR 0x88884B84 /* PA7...PA0 */ @@ -182,8 +181,6 @@ /* * Port B setup. - * Everything input with pull-up except: - * PB3 - Pull-up input (GPIOB_SWO) */ #define VAL_GPIOBCFGLR 0x88888888 /* PB7...PB0 */ #define VAL_GPIOBCFGHR 0x88888888 /* PB15...PB8 */ @@ -203,6 +200,7 @@ /* * Port D setup. + * Everything input with pull-up except: * PD0 - Normal input (GPIOD_OSC_IN). * PD1 - Normal input (GPIOD_OSC_OUT). */ From 77cb0a4f7589f89e724f5e6ecb1d76d514dd1212 Mon Sep 17 00:00:00 2001 From: Joy Lee Date: Wed, 3 Apr 2024 20:39:24 +0800 Subject: [PATCH 04/19] [WB32 MCU] Added RTC hal. (#399) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * Fixed usb remote wakeup, i2c Added more rate configurations * Added RTC configuration in hal_lld.h * åˆæ­¥æµ‹è¯•é€šè¿‡ 实现RTC功能 * update * update rtc_lld * UPDATE * update * update æ­£å¼ç‰ˆæœ¬2 * update æ­£å¼ç‰ˆ * update æ­£å¼å‘布 * update æ­£å¼å‘布 * update 3G71 * update * update * update * update * update * update * update * update * update * Revert "Update keil project" This reverts commit 212316772920ef63174a3d4c0253c79b79b511a4. # Conflicts: # demos/WB32/RT-WB32FQ95-GENERIC/keil/ch.uvprojx * update ä¿®æ”¹æ ¼å¼ * Update demos/WB32/RT-WB32F3G71-RTC/debug.h Co-authored-by: Joy Lee * Update demos/WB32/RT-WB32F3G71-RTC/main.c Co-authored-by: Joy Lee * Update demos/WB32/RT-WB32F3G71-RTC/main.c Co-authored-by: Joy Lee * Update demos/WB32/RT-WB32F3G71-RTC/main.c Co-authored-by: Joy Lee * Revert "Update keil project" This reverts commit 212316772920ef63174a3d4c0253c79b79b511a4. # Conflicts: # demos/WB32/RT-WB32FQ95-GENERIC/keil/ch.uvprojx * update * update * update * update * Update os/hal/ports/WB32/LLD/RTCv1/hal_rtc_lld.c Co-authored-by: Joy Lee * Update os/hal/ports/WB32/LLD/RTCv1/hal_rtc_lld.c Co-authored-by: Joy Lee * Update os/hal/ports/WB32/LLD/RTCv1/hal_rtc_lld.c Co-authored-by: Joy Lee * Update os/hal/ports/WB32/LLD/RTCv1/hal_rtc_lld.c Co-authored-by: Joy Lee * Update os/hal/ports/WB32/LLD/RTCv1/hal_rtc_lld.c Co-authored-by: Joy Lee * UPDATE * update * update * update * update * update * Update hal_usb_lld.c * Update --------- Co-authored-by: bingkun.li Co-authored-by: wind <108604699+yelishang@users.noreply.github.com> Co-authored-by: wb --- demos/WB32/RT-WB32F3G71-RTC/Makefile | 204 ++ demos/WB32/RT-WB32F3G71-RTC/board/board.c | 82 + demos/WB32/RT-WB32F3G71-RTC/board/board.h | 56 + demos/WB32/RT-WB32F3G71-RTC/board/board.mk | 9 + demos/WB32/RT-WB32F3G71-RTC/cfg/chconf.h | 834 ++++++ demos/WB32/RT-WB32F3G71-RTC/cfg/halconf.h | 531 ++++ demos/WB32/RT-WB32F3G71-RTC/cfg/mcuconf.h | 182 ++ demos/WB32/RT-WB32F3G71-RTC/debug.c | 36 + demos/WB32/RT-WB32F3G71-RTC/debug.h | 25 + demos/WB32/RT-WB32F3G71-RTC/keil/ch.uvoptx | 2478 +++++++++++++++++ demos/WB32/RT-WB32F3G71-RTC/keil/ch.uvprojx | 1364 +++++++++ demos/WB32/RT-WB32F3G71-RTC/main.c | 236 ++ demos/WB32/RT-WB32F3G71-RTC/readme.md | 4 + demos/WB32/RT-WB32FQ95-GENERIC/cfg/mcuconf.h | 12 +- demos/WB32/RT-WB32FQ95-GENERIC/keil/ch.uvoptx | 224 +- .../WB32/RT-WB32FQ95-GENERIC/keil/ch.uvprojx | 11 +- os/hal/ports/WB32/LLD/EXTIv1/driver.mk | 2 + os/hal/ports/WB32/LLD/EXTIv1/wb32_exti.c | 145 + os/hal/ports/WB32/LLD/EXTIv1/wb32_exti.h | 117 + os/hal/ports/WB32/LLD/I2Cv1/hal_i2c_lld.c | 8 +- os/hal/ports/WB32/LLD/RTCv1/driver.mk | 8 + os/hal/ports/WB32/LLD/RTCv1/hal_rtc_lld.c | 617 ++++ os/hal/ports/WB32/LLD/RTCv1/hal_rtc_lld.h | 164 ++ os/hal/ports/WB32/LLD/USBv1/hal_usb_lld.c | 42 +- os/hal/ports/WB32/LLD/USBv1/hal_usb_lld.h | 2 +- os/hal/ports/WB32/WB32F3G71xx/hal_lld.c | 36 + os/hal/ports/WB32/WB32F3G71xx/hal_lld.h | 86 + os/hal/ports/WB32/WB32F3G71xx/platform.mk | 2 + os/hal/ports/WB32/WB32F3G71xx/wb32_rcc.h | 87 +- os/hal/ports/WB32/WB32F3G71xx/wb32_registry.h | 2 + os/hal/ports/WB32/WB32FQ95xx/hal_lld.c | 36 + os/hal/ports/WB32/WB32FQ95xx/hal_lld.h | 86 + os/hal/ports/WB32/WB32FQ95xx/platform.mk | 2 + os/hal/ports/WB32/WB32FQ95xx/wb32_rcc.h | 87 +- os/hal/ports/WB32/WB32FQ95xx/wb32_registry.h | 2 + 35 files changed, 7664 insertions(+), 155 deletions(-) create mode 100644 demos/WB32/RT-WB32F3G71-RTC/Makefile create mode 100644 demos/WB32/RT-WB32F3G71-RTC/board/board.c create mode 100644 demos/WB32/RT-WB32F3G71-RTC/board/board.h create mode 100644 demos/WB32/RT-WB32F3G71-RTC/board/board.mk create mode 100644 demos/WB32/RT-WB32F3G71-RTC/cfg/chconf.h create mode 100644 demos/WB32/RT-WB32F3G71-RTC/cfg/halconf.h create mode 100644 demos/WB32/RT-WB32F3G71-RTC/cfg/mcuconf.h create mode 100644 demos/WB32/RT-WB32F3G71-RTC/debug.c create mode 100644 demos/WB32/RT-WB32F3G71-RTC/debug.h create mode 100644 demos/WB32/RT-WB32F3G71-RTC/keil/ch.uvoptx create mode 100644 demos/WB32/RT-WB32F3G71-RTC/keil/ch.uvprojx create mode 100644 demos/WB32/RT-WB32F3G71-RTC/main.c create mode 100644 demos/WB32/RT-WB32F3G71-RTC/readme.md create mode 100644 os/hal/ports/WB32/LLD/EXTIv1/driver.mk create mode 100644 os/hal/ports/WB32/LLD/EXTIv1/wb32_exti.c create mode 100644 os/hal/ports/WB32/LLD/EXTIv1/wb32_exti.h create mode 100644 os/hal/ports/WB32/LLD/RTCv1/driver.mk create mode 100644 os/hal/ports/WB32/LLD/RTCv1/hal_rtc_lld.c create mode 100644 os/hal/ports/WB32/LLD/RTCv1/hal_rtc_lld.h diff --git a/demos/WB32/RT-WB32F3G71-RTC/Makefile b/demos/WB32/RT-WB32F3G71-RTC/Makefile new file mode 100644 index 0000000000..92711c3f92 --- /dev/null +++ b/demos/WB32/RT-WB32F3G71-RTC/Makefile @@ -0,0 +1,204 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = yes +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m3 + +# Imported source files and paths. +CHIBIOS := ../../../../ChibiOS +CHIBIOS_CONTRIB = $(CHIBIOS)/../ChibiOS-Contrib +CONFDIR := ./cfg +BUILDDIR := ./build +DEPDIR := ./.dep +BOARDDIR := ./board + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_wb32f3g71xx.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/WB32F3G71xx/platform.mk +include $(BOARDDIR)/board.mk +include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMv7-M/compilers/GCC/mk/port.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +# include $(CHIBIOS)/test/lib/test.mk +# include $(CHIBIOS)/test/rt/rt_test.mk +# include $(CHIBIOS)/test/oslib/oslib_test.mk +# include $(CHIBIOS)/os/hal/lib/streams/streams.mk +# include $(CHIBIOS)/os/various/shell/shell.mk + +# Define linker script file here +LDSCRIPT= $(STARTUPLD_CONTRIB)/WB32F3G71xC.ld + + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + $(CHIBIOS)/os/various/syscalls.c \ + $(CHIBIOS)/os/hal/lib/streams/chprintf.c \ + debug.c \ + main.c + +ALLINC += ./ \ + $(CHIBIOS)/os/common/lib/include \ + $(CHIBIOS)/os/common/oop/include \ + $(CHIBIOS)/os/hal/lib/streams + + + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## diff --git a/demos/WB32/RT-WB32F3G71-RTC/board/board.c b/demos/WB32/RT-WB32F3G71-RTC/board/board.c new file mode 100644 index 0000000000..d76353f822 --- /dev/null +++ b/demos/WB32/RT-WB32F3G71-RTC/board/board.c @@ -0,0 +1,82 @@ +/* + Copyright (C) 2023 Westberry Technology Corp., Ltd + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#include "hal.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void wb32_gpio_init(void) { + +#if WB32_HAS_GPIOA + rccEnableAPB1(RCC_APB1ENR_GPIOAEN); +#endif + +#if WB32_HAS_GPIOB + rccEnableAPB1(RCC_APB1ENR_GPIOBEN); +#endif + +#if WB32_HAS_GPIOC + rccEnableAPB1(RCC_APB1ENR_GPIOCEN); +#endif + +#if WB32_HAS_GPIOD + rccEnableAPB1(RCC_APB1ENR_GPIODEN); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + + wb32_clock_init(); + wb32_gpio_init(); +} +/** + * @brief Board-specific initialization code. + * @note You can add your board-specific code here. + */ +void boardInit(void) { + +} diff --git a/demos/WB32/RT-WB32F3G71-RTC/board/board.h b/demos/WB32/RT-WB32F3G71-RTC/board/board.h new file mode 100644 index 0000000000..64439c3791 --- /dev/null +++ b/demos/WB32/RT-WB32F3G71-RTC/board/board.h @@ -0,0 +1,56 @@ +#pragma once +/* + Copyright (C) 2023 Westberry Technology Corp., Ltd + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#ifndef BOARD_H +#define BOARD_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/* + * Setup board. + */ + +/* + * Board identifier. + */ +#define WB32FQ95xC +#if !defined(WB32F3G71xx) + #define WB32F3G71xx +#endif + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* BOARD_H */ diff --git a/demos/WB32/RT-WB32F3G71-RTC/board/board.mk b/demos/WB32/RT-WB32F3G71-RTC/board/board.mk new file mode 100644 index 0000000000..60673b374e --- /dev/null +++ b/demos/WB32/RT-WB32F3G71-RTC/board/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files. +BOARDSRC = $(BOARDDIR)/board.c + +# Required include directories +BOARDINC = $(BOARDDIR) + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC) diff --git a/demos/WB32/RT-WB32F3G71-RTC/cfg/chconf.h b/demos/WB32/RT-WB32F3G71-RTC/cfg/chconf.h new file mode 100644 index 0000000000..3fd3c65f9e --- /dev/null +++ b/demos/WB32/RT-WB32F3G71-RTC/cfg/chconf.h @@ -0,0 +1,834 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_7_0_ + +/*===========================================================================*/ +/** + * @name System settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Handling of instances. + * @note If enabled then threads assigned to various instances can + * interact each other using the same synchronization objects. + * If disabled then each OS instance is a separate world, no + * direct interactions are handled by the OS. + */ +#if !defined(CH_CFG_SMP_MODE) +#define CH_CFG_SMP_MODE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** + * @brief Kernel hardening level. + * @details This option is the level of functional-safety checks enabled + * in the kerkel. The meaning is: + * - 0: No checks, maximum performance. + * - 1: Reasonable checks. + * - 2: All checks. + * . + */ +#if !defined(CH_CFG_HARDENING_LEVEL) +#define CH_CFG_HARDENING_LEVEL 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Time Stamps APIs. + * @details If enabled then the time time stamps APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TIMESTAMP) +#define CH_CFG_USE_TIMESTAMP TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name OSLIB options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Memory checks APIs. + * @details If enabled then the memory checks APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCHECKS) +#define CH_CFG_USE_MEMCHECKS TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Objects Caches APIs. + * @details If enabled then the objects caches APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_CACHES) +#define CH_CFG_USE_OBJ_CACHES TRUE +#endif + +/** + * @brief Delegate threads APIs. + * @details If enabled then the delegate threads APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_DELEGATES) +#define CH_CFG_USE_DELEGATES TRUE +#endif + +/** + * @brief Jobs Queues APIs. + * @details If enabled then the jobs queues APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_JOBS) +#define CH_CFG_USE_JOBS TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_ALL +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add system custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add system initialization code here.*/ \ +} + +/** + * @brief OS instance structure extension. + * @details User fields added to the end of the @p os_instance_t structure. + */ +#define CH_CFG_OS_INSTANCE_EXTRA_FIELDS \ + /* Add OS instance custom fields here.*/ + +/** + * @brief OS instance initialization hook. + * + * @param[in] oip pointer to the @p os_instance_t structure + */ +#define CH_CFG_OS_INSTANCE_INIT_HOOK(oip) { \ + /* Add OS instance initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** + * @brief Runtime Faults Collection Unit hook. + * @details This hook is invoked each time new faults are collected and stored. + */ +#define CH_CFG_RUNTIME_FAULTS_HOOK(mask) { \ + /* Faults handling code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/demos/WB32/RT-WB32F3G71-RTC/cfg/halconf.h b/demos/WB32/RT-WB32F3G71-RTC/cfg/halconf.h new file mode 100644 index 0000000000..05807866c2 --- /dev/null +++ b/demos/WB32/RT-WB32F3G71-RTC/cfg/halconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS - Copyright (C) 2006..2023 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_8_4_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EFlash subsystem. + */ +#if !defined(HAL_USE_EFL) || defined(__DOXYGEN__) +#define HAL_USE_EFL FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC TRUE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS TRUE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT TRUE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables circular transfers APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) +#define SPI_USE_CIRCULAR FALSE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/demos/WB32/RT-WB32F3G71-RTC/cfg/mcuconf.h b/demos/WB32/RT-WB32F3G71-RTC/cfg/mcuconf.h new file mode 100644 index 0000000000..77cef7df98 --- /dev/null +++ b/demos/WB32/RT-WB32F3G71-RTC/cfg/mcuconf.h @@ -0,0 +1,182 @@ +/* + Copyright (C) 2023 Westberry Technology Corp., Ltd + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +#define WB32F3G71xx_MCUCONF TRUE + +/* + * WB32FQ95 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + */ + +/** + * @name Internal clock sources + * @{ + */ +#define WB32_HSECLK 12000000 +#define WB32_LSECLK 32768 + +/* + * HAL driver system settings. + */ +#define WB32_NO_INIT FALSE +#define WB32_MHSI_ENABLED TRUE +#define WB32_FHSI_ENABLED FALSE +#define WB32_LSI_ENABLED TRUE +#define WB32_HSE_ENABLED TRUE +#define WB32_LSE_ENABLED TRUE +#define WB32_PLL_ENABLED TRUE +#define WB32_MAINCLKSRC WB32_MAINCLKSRC_PLL +#define WB32_HSE_STATE ANCTL_HSECR0_HSEON +#define WB32_PLLSRC WB32_PLLSRC_HSE +#define WB32_PLLDIV_VALUE 2 +#define WB32_PLLMUL_VALUE 12 // The allowed range is 12,16,20,24. +#define WB32_HPRE 1 +#define WB32_PPRE1 1 +#define WB32_PPRE2 1 +#define WB32_USBPRE WB32_USBPRE_DIV1P5 +#define WB32_RTCSEL WB32_RTCSEL_HSEDIV +#define WB32_RTCLP_SEL WB32_RTCSEL_LSI +/* + * EXTI driver system settings. + */ +#define WB32_EXTI_REQUIRED +#define WB32_IRQ_EXTI0_PRIORITY 6 +#define WB32_IRQ_EXTI1_PRIORITY 6 +#define WB32_IRQ_EXTI2_PRIORITY 6 +#define WB32_IRQ_EXTI3_PRIORITY 6 +#define WB32_IRQ_EXTI4_PRIORITY 6 +#define WB32_IRQ_EXTI5_9_PRIORITY 6 +#define WB32_IRQ_EXTI10_15_PRIORITY 6 +#define WB32_IRQ_EXTI16_PRIORITY 6 +#define WB32_IRQ_EXTI17_PRIORITY 6 +#define WB32_IRQ_EXTI18_PRIORITY 6 +#define WB32_IRQ_EXTI19_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define WB32_TIM_MAX_CHANNELS 4 +#define WB32_GPT_USE_TIM1 FALSE +#define WB32_GPT_USE_TIM2 FALSE +#define WB32_GPT_USE_TIM3 FALSE +#define WB32_GPT_USE_TIM4 FALSE +#define WB32_GPT_TIM1_IRQ_PRIORITY 7 +#define WB32_GPT_TIM2_IRQ_PRIORITY 7 +#define WB32_GPT_TIM3_IRQ_PRIORITY 7 +#define WB32_GPT_TIM4_IRQ_PRIORITY 7 +/* + * RTC driver system settings. + */ +#define WB32_RTCAlarm_IRQ_PRIORITY 14 +#define WB32_RTC_IRQ_PRIORITY 15 + +/* + * ICU driver system settings. + */ +#define WB32_ICU_USE_TIM1 FALSE +#define WB32_ICU_USE_TIM2 FALSE +#define WB32_ICU_USE_TIM3 FALSE +#define WB32_ICU_USE_TIM4 FALSE +#define WB32_ICU_TIM1_IRQ_PRIORITY 7 +#define WB32_ICU_TIM2_IRQ_PRIORITY 7 +#define WB32_ICU_TIM3_IRQ_PRIORITY 7 +#define WB32_ICU_TIM4_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define WB32_PWM_USE_ADVANCED FALSE +#define WB32_PWM_USE_TIM1 FALSE +#define WB32_PWM_USE_TIM2 FALSE +#define WB32_PWM_USE_TIM3 FALSE +#define WB32_PWM_USE_TIM4 FALSE +#define WB32_PWM_TIM1_IRQ_PRIORITY 7 +#define WB32_PWM_TIM2_IRQ_PRIORITY 7 +#define WB32_PWM_TIM3_IRQ_PRIORITY 7 +#define WB32_PWM_TIM4_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define WB32_I2C_USE_I2C1 FALSE +#define WB32_I2C_USE_I2C2 FALSE +#define WB32_I2C_BUSY_TIMEOUT 50 +#define WB32_I2C_I2C1_IRQ_PRIORITY 5 +#define WB32_I2C_I2C2_IRQ_PRIORITY 5 + +/* + * SERIAL driver system settings. + */ +#define WB32_SERIAL_USE_UART1 TRUE +#define WB32_SERIAL_USE_UART2 FALSE +#define WB32_SERIAL_USE_UART3 FALSE +#define WB32_SERIAL_UART1_PRIORITY 12 +#define WB32_SERIAL_UART2_PRIORITY 12 +#define WB32_SERIAL_UART3_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define WB32_SPI_USE_QSPI FALSE +#define WB32_SPI_USE_SPIM2 FALSE +#define WB32_SPI_USE_SPIS1 FALSE +#define WB32_SPI_USE_SPIS2 FALSE +#define WB32_SPI_QSPI_IRQ_PRIORITY 10 +#define WB32_SPI_SPIM2_IRQ_PRIORITY 10 +#define WB32_SPI_SPIS1_IRQ_PRIORITY 10 +#define WB32_SPI_SPIS2_IRQ_PRIORITY 10 + +/* + * ST driver system settings. + */ +#define WB32_ST_IRQ_PRIORITY 8 +#define WB32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define WB32_UART_USE_UART1 FALSE +#define WB32_UART_USE_UART2 FALSE +#define WB32_UART_USE_UART3 FALSE +#define WB32_UART_UART1_IRQ_PRIORITY 12 +#define WB32_UART_UART2_IRQ_PRIORITY 12 +#define WB32_UART_UART3_IRQ_PRIORITY 12 + +/* + * USB driver system settings. + */ +#define WB32_USB_USE_USB1 TRUE +#define WB32_USB_USB1_IRQ_PRIORITY 13 +#define WB32_USB_HOST_WAKEUP_DURATION 10 + +/* + * ADC driver system settings. + */ +#define WB32_ADC_USE_ADC1 FALSE +#define WB32_ADC_ADC1_DMA_PRIORITY 2 +#define WB32_ADC_ADC1_IRQ_PRIORITY 6 + +#endif /* MCUCONF_H */ diff --git a/demos/WB32/RT-WB32F3G71-RTC/debug.c b/demos/WB32/RT-WB32F3G71-RTC/debug.c new file mode 100644 index 0000000000..bb2933b16c --- /dev/null +++ b/demos/WB32/RT-WB32F3G71-RTC/debug.c @@ -0,0 +1,36 @@ +/* + Copyright (C) 2023 Westberry Technology Corp., Ltd + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "debug.h" + +#define SERIAL_DEBUG_DRIVER SD1 +#define SERIAL_DEBUG_BAUND 115200 +#define SERIAL_DEBUG_TX_PIN PAL_LINE(GPIOA, 9U) +#define SERIAL_DEBUG_RX_PIN PAL_LINE(GPIOA, 10U) +#define SERIAL_DEBUG_TX_PAL_MODE 7 +#define SERIAL_DEBUG_RX_PAL_MODE 7 + +static SerialConfig serialConfig = {SERIAL_DEBUG_BAUND, 3, 0, 0, 0}; + +void serial_debug_init(void) { + + serialConfig.speed = SERIAL_DEBUG_BAUND; + palSetPadMode(PAL_PORT(SERIAL_DEBUG_TX_PIN), PAL_PAD(SERIAL_DEBUG_TX_PIN),PAL_MODE_ALTERNATE(SERIAL_DEBUG_TX_PAL_MODE) | PAL_WB32_PUPDR_PULLUP | PAL_WB32_OSPEED_HIGH); + palSetPadMode(PAL_PORT(SERIAL_DEBUG_RX_PIN), PAL_PAD(SERIAL_DEBUG_RX_PIN),PAL_MODE_ALTERNATE(SERIAL_DEBUG_RX_PAL_MODE) | PAL_WB32_PUPDR_PULLUP | PAL_WB32_OSPEED_HIGH); + + sdStart(&SERIAL_DEBUG_DRIVER, &serialConfig); +} + diff --git a/demos/WB32/RT-WB32F3G71-RTC/debug.h b/demos/WB32/RT-WB32F3G71-RTC/debug.h new file mode 100644 index 0000000000..12e35b6127 --- /dev/null +++ b/demos/WB32/RT-WB32F3G71-RTC/debug.h @@ -0,0 +1,25 @@ +/* + Copyright (C) 2023 Westberry Technology Corp., Ltd + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#pragma once + +#include +#include + +#define SERIAL_DEBUG_DRIVER SD1 + +void serial_debug_init(void); + diff --git a/demos/WB32/RT-WB32F3G71-RTC/keil/ch.uvoptx b/demos/WB32/RT-WB32F3G71-RTC/keil/ch.uvoptx new file mode 100644 index 0000000000..72563be4aa --- /dev/null +++ b/demos/WB32/RT-WB32F3G71-RTC/keil/ch.uvoptx @@ -0,0 +1,2478 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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100644 index 0000000000..877959e59e --- /dev/null +++ b/demos/WB32/RT-WB32F3G71-RTC/keil/ch.uvprojx @@ -0,0 +1,1364 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
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..\;..\cfg;..\..\..\..\..\ChibiOS\os\license;..\..\..\..\..\ChibiOS-Contrib\os\common\startup\ARMCMx\devices\WB32F3G71xx;..\..\..\..\..\ChibiOS\os\common\ext\ARM\CMSIS\Core\Include;..\..\..\..\..\ChibiOS-Contrib\os\common\ext\CMSIS\WB32\WB32F3G71xx;..\..\..\..\..\ChibiOS\os\common\portability\Keil;..\..\..\..\..\ChibiOS\os\common\ports\ARM-common;..\..\..\..\..\ChibiOS\os\common\ports\ARMv7-M;..\..\..\..\..\ChibiOS\os\rt\include;..\..\..\..\..\ChibiOS\os\oslib\include;..\..\..\..\..\ChibiOS\os\hal\osal\rt-nil;..\..\..\..\..\ChibiOS\os\hal\include;..\board;..\..\..\..\..\ChibiOS\os\hal\ports\common\ARMCMx;..\..\..\..\..\ChibiOS-Contrib\os\hal\ports\WB32\WB32F3G71xx;..\..\..\..\..\ChibiOS-Contrib\os\hal\ports\WB32\LLD\GPIOv1;..\..\..\..\os\hal\ports\WB32\LLD\DMAv1;..\..\..\..\os\hal\ports\WB32\LLD\TIMv1;..\..\..\..\..\ChibiOS\os\test\include;..\..\..\..\..\ChibiOS\test\rt\source\test;..\..\..\..\..\ChibiOS\test\oslib\source\test;..\..\..\..\os\hal\ports\WB32\LLD\RTCv1;..\..\..\..\os\hal\ports\WB32\LLD\UARTv1;..\..\..\..\..\ChibiOS\os\hal\templates;..\..\..\..\os\hal\include;..\..\..\..\os\hal\ports\WB32\LLD\EXTIv1;..\..\..\..\..\ChibiOS\os\common\lib\include;..\..\..\..\..\ChibiOS\os\common\oop\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpreproc --cpreproc_opts=-DCORTEX_USE_FPU=0 + + + ..\;..\cfg;..\..\..\..\..\ChibiOS\os\license;..\..\..\..\..\ChibiOS-Contrib\os\common\startup\ARMCMx\devices\WB32F3G71xx;..\..\..\..\..\ChibiOS\os\common\ports\ARMv7-M;..\board + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + license + + + chcustomer.h + 5 + ..\..\..\..\..\ChibiOS\os\license\chcustomer.h + + + chlicense.h + 5 + ..\..\..\..\..\ChibiOS\os\license\chlicense.h + + + chversion.h + 5 + ..\..\..\..\..\ChibiOS\os\license\chversion.h + + + + + startup + + + cstartup.s + 2 + ..\..\..\..\..\ChibiOS\os\common\startup\ARMCMx\compilers\RVCT\cstartup.s + + + vectors.s + 2 + ..\..\..\..\..\ChibiOS\os\common\startup\ARMCMx\compilers\RVCT\vectors.s + + + cmparams.h + 5 + ..\..\..\..\..\ChibiOS-Contrib\os\common\startup\ARMCMx\devices\WB32F3G71xx\cmparams.h + + + + + cmsis + + + core_cm3.h + 5 + ..\..\..\..\..\ChibiOS\os\common\ext\ARM\CMSIS\Core\Include\core_cm3.h + + + wb32f3g71xx.h + 5 + ..\..\..\..\..\ChibiOS-Contrib\os\common\ext\CMSIS\WB32\WB32F3G71xx\wb32f3g71xx.h + + + + + kernel port + + + chcore.c + 1 + ..\..\..\..\..\ChibiOS\os\common\ports\ARMv7-M\chcore.c + + + chcore.h + 5 + ..\..\..\..\..\ChibiOS\os\common\ports\ARMv7-M\chcore.h + + + mpu.h + 5 + ..\..\..\..\..\ChibiOS\os\common\ports\ARMv7-M\mpu.h + + + chcoreasm.s + 2 + ..\..\..\..\..\ChibiOS\os\common\ports\ARMv7-M\compilers\RVCT\chcoreasm.s + + + + + kernel + + + chalign.h + 5 + ..\..\..\..\..\ChibiOS\os\rt\include\chalign.h + + + ch.h + 5 + ..\..\..\..\..\ChibiOS\os\rt\include\ch.h + + + chcond.h + 5 + ..\..\..\..\..\ChibiOS\os\rt\include\chcond.h + + + chdebug.h + 5 + ..\..\..\..\..\ChibiOS\os\rt\include\chdebug.h + + + chdynamic.h + 5 + ..\..\..\..\..\ChibiOS\os\rt\include\chdynamic.h + + + chevents.h + 5 + ..\..\..\..\..\ChibiOS\os\rt\include\chevents.h + + + chmsg.h + 5 + ..\..\..\..\..\ChibiOS\os\rt\include\chmsg.h + + + chmtx.h + 5 + ..\..\..\..\..\ChibiOS\os\rt\include\chmtx.h + + + chregistry.h + 5 + ..\..\..\..\..\ChibiOS\os\rt\include\chregistry.h + + + chschd.h + 5 + ..\..\..\..\..\ChibiOS\os\rt\include\chschd.h + + + chsem.h + 5 + ..\..\..\..\..\ChibiOS\os\rt\include\chsem.h + + + chstats.h + 5 + ..\..\..\..\..\ChibiOS\os\rt\include\chstats.h + + + chsys.h + 5 + ..\..\..\..\..\ChibiOS\os\rt\include\chsys.h + + + chthreads.h + 5 + ..\..\..\..\..\ChibiOS\os\rt\include\chthreads.h + + + chtm.h + 5 + ..\..\..\..\..\ChibiOS\os\rt\include\chtm.h + + + chvt.h + 5 + ..\..\..\..\..\ChibiOS\os\rt\include\chvt.h + + + chcond.c + 1 + ..\..\..\..\..\ChibiOS\os\rt\src\chcond.c + + + chdebug.c + 1 + ..\..\..\..\..\ChibiOS\os\rt\src\chdebug.c + + + chdynamic.c + 1 + ..\..\..\..\..\ChibiOS\os\rt\src\chdynamic.c + + + chevents.c + 1 + ..\..\..\..\..\ChibiOS\os\rt\src\chevents.c + + + chmsg.c + 1 + ..\..\..\..\..\ChibiOS\os\rt\src\chmsg.c + + + chmtx.c + 1 + ..\..\..\..\..\ChibiOS\os\rt\src\chmtx.c + + + chregistry.c + 1 + ..\..\..\..\..\ChibiOS\os\rt\src\chregistry.c + + + chschd.c + 1 + ..\..\..\..\..\ChibiOS\os\rt\src\chschd.c + + + chsem.c + 1 + ..\..\..\..\..\ChibiOS\os\rt\src\chsem.c + + + chstats.c + 1 + ..\..\..\..\..\ChibiOS\os\rt\src\chstats.c + + + chsys.c + 1 + ..\..\..\..\..\ChibiOS\os\rt\src\chsys.c + + + chthreads.c + 1 + ..\..\..\..\..\ChibiOS\os\rt\src\chthreads.c + + + chtm.c + 1 + ..\..\..\..\..\ChibiOS\os\rt\src\chtm.c + + + chvt.c + 1 + ..\..\..\..\..\ChibiOS\os\rt\src\chvt.c + + + chrfcu.c + 1 + ..\..\..\..\..\ChibiOS\os\rt\src\chrfcu.c + + + chinstances.c + 1 + ..\..\..\..\..\ChibiOS\os\rt\src\chinstances.c + + + chchecks.h + 5 + ..\..\..\..\..\ChibiOS\os\rt\include\chchecks.h + + + chtrace.h + 5 + ..\..\..\..\..\ChibiOS\os\rt\include\chtrace.h + + + chtrace.c + 1 + ..\..\..\..\..\ChibiOS\os\rt\src\chtrace.c + + + chrestrictions.h + 5 + ..\..\..\..\..\ChibiOS\os\rt\include\chrestrictions.h + + + chtime.h + 5 + ..\..\..\..\..\ChibiOS\os\rt\include\chtime.h + + + + + oslib + + + chbsem.h + 5 + ..\..\..\..\..\ChibiOS\os\oslib\include\chbsem.h + + + chdelegates.h + 5 + ..\..\..\..\..\ChibiOS\os\oslib\include\chdelegates.h + + + chfactory.h + 5 + ..\..\..\..\..\ChibiOS\os\oslib\include\chfactory.h + + + chjobs.h + 5 + ..\..\..\..\..\ChibiOS\os\oslib\include\chjobs.h + + + chlib.h + 5 + ..\..\..\..\..\ChibiOS\os\oslib\include\chlib.h + + + chmboxes.h + 5 + ..\..\..\..\..\ChibiOS\os\oslib\include\chmboxes.h + + + chmemcore.h + 5 + ..\..\..\..\..\ChibiOS\os\oslib\include\chmemcore.h + + + chmemheaps.h + 5 + ..\..\..\..\..\ChibiOS\os\oslib\include\chmemheaps.h + + + chmempools.h + 5 + ..\..\..\..\..\ChibiOS\os\oslib\include\chmempools.h + + + chobjcaches.h + 5 + ..\..\..\..\..\ChibiOS\os\oslib\include\chobjcaches.h + + + chobjfifos.h + 5 + ..\..\..\..\..\ChibiOS\os\oslib\include\chobjfifos.h + + + chpipes.h + 5 + ..\..\..\..\..\ChibiOS\os\oslib\include\chpipes.h + + + chdelegates.c + 1 + ..\..\..\..\..\ChibiOS\os\oslib\src\chdelegates.c + + + chfactory.c + 1 + ..\..\..\..\..\ChibiOS\os\oslib\src\chfactory.c + + + chmboxes.c + 1 + ..\..\..\..\..\ChibiOS\os\oslib\src\chmboxes.c + + + chmemcore.c + 1 + ..\..\..\..\..\ChibiOS\os\oslib\src\chmemcore.c + + + chmemheaps.c + 1 + ..\..\..\..\..\ChibiOS\os\oslib\src\chmemheaps.c + + + chmempools.c + 1 + ..\..\..\..\..\ChibiOS\os\oslib\src\chmempools.c + + + chobjcaches.c + 1 + ..\..\..\..\..\ChibiOS\os\oslib\src\chobjcaches.c + + + chpipes.c + 1 + ..\..\..\..\..\ChibiOS\os\oslib\src\chpipes.c + + + chmemchecks.c + 1 + ..\..\..\..\..\ChibiOS\os\oslib\src\chmemchecks.c + + + + + osal + + + osal.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\osal\rt-nil\osal.c + + + osal.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\osal\rt-nil\osal.h + + + + + hal + + + hal.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal.h + + + hal_adc.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_adc.h + + + hal_buffers.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_buffers.h + + + hal_can.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_can.h + + + hal_channels.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_channels.h + + + hal_dac.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_dac.h + + + hal_files.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_files.h + + + hal_gpt.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_gpt.h + + + hal_i2c.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_i2c.h + + + hal_i2s.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_i2s.h + + + hal_icu.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_icu.h + + + hal_ioblock.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_ioblock.h + + + hal_mac.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_mac.h + + + hal_mii.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_mii.h + + + hal_mmc_spi.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_mmc_spi.h + + + hal_mmcsd.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_mmcsd.h + + + hal_pal.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_pal.h + + + hal_pwm.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_pwm.h + + + hal_queues.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_queues.h + + + hal_rtc.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_rtc.h + + + hal_sdc.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_sdc.h + + + hal_serial.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_serial.h + + + hal_serial_usb.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_serial_usb.h + + + hal_spi.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_spi.h + + + hal_st.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_st.h + + + hal_streams.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_streams.h + + + hal_uart.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_uart.h + + + hal_usb.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_usb.h + + + hal_usb_cdc.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_usb_cdc.h + + + hal_wdg.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_wdg.h + + + hal.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal.c + + + hal_adc.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_adc.c + + + hal_buffers.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_buffers.c + + + hal_can.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_can.c + + + hal_dac.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_dac.c + + + hal_gpt.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_gpt.c + + + hal_i2c.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_i2c.c + + + hal_i2s.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_i2s.c + + + hal_icu.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_icu.c + + + hal_mac.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_mac.c + + + hal_mmc_spi.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_mmc_spi.c + + + hal_mmcsd.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_mmcsd.c + + + hal_pal.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_pal.c + + + hal_pwm.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_pwm.c + + + hal_queues.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_queues.c + + + hal_rtc.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_rtc.c + + + hal_sdc.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_sdc.c + + + hal_serial.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_serial.c + + + hal_serial_usb.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_serial_usb.c + + + hal_spi.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_spi.c + + + hal_st.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_st.c + + + hal_uart.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_uart.c + + + hal_usb.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_usb.c + + + hal_wdg.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_wdg.c + + + hal_crypto.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_crypto.h + + + hal_efl.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_efl.h + + + hal_flash.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_flash.h + + + hal_objects.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_objects.h + + + hal_persistent.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_persistent.h + + + hal_sio.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_sio.h + + + hal_trng.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_trng.h + + + hal_wspi.h + 5 + ..\..\..\..\..\ChibiOS\os\hal\include\hal_wspi.h + + + hal_crypto.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_crypto.c + + + hal_efl.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_efl.c + + + hal_flash.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_flash.c + + + hal_sio.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_sio.c + + + hal_trng.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_trng.c + + + hal_wspi.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\src\hal_wspi.c + + + + + hal_port + + + hal_pal_lld.c + 1 + ..\..\..\..\..\ChibiOS-Contrib\os\hal\ports\WB32\LLD\GPIOv1\hal_pal_lld.c + + + hal_lld.c + 1 + ..\..\..\..\..\ChibiOS-Contrib\os\hal\ports\WB32\WB32F3G71xx\hal_lld.c + + + wb32_isr.c + 1 + ..\..\..\..\..\ChibiOS-Contrib\os\hal\ports\WB32\WB32F3G71xx\wb32_isr.c + + + nvic.c + 1 + ..\..\..\..\..\ChibiOS\os\hal\ports\common\ARMCMx\nvic.c + + + hal_st_lld.c + 1 + ..\..\..\..\os\hal\ports\WB32\LLD\TIMv1\hal_st_lld.c + + + hal_rtc_lld.c + 1 + ..\..\..\..\os\hal\ports\WB32\LLD\RTCv1\hal_rtc_lld.c + + + hal_serial_lld.c + 1 + ..\..\..\..\os\hal\ports\WB32\LLD\UARTv1\hal_serial_lld.c + + + wb32_exti.c + 1 + ..\..\..\..\os\hal\ports\WB32\LLD\EXTIv1\wb32_exti.c + + + + + board + + + board.c + 1 + ..\board\board.c + + + board.h + 5 + ..\board\board.h + + + + + test + + + rt_test_root.c + 1 + ..\..\..\..\..\ChibiOS\test\rt\source\test\rt_test_root.c + + + rt_test_sequence_001.c + 1 + ..\..\..\..\..\ChibiOS\test\rt\source\test\rt_test_sequence_001.c + + + rt_test_sequence_002.c + 1 + ..\..\..\..\..\ChibiOS\test\rt\source\test\rt_test_sequence_002.c + + + rt_test_sequence_003.c + 1 + ..\..\..\..\..\ChibiOS\test\rt\source\test\rt_test_sequence_003.c + + + rt_test_sequence_004.c + 1 + ..\..\..\..\..\ChibiOS\test\rt\source\test\rt_test_sequence_004.c + + + rt_test_sequence_005.c + 1 + ..\..\..\..\..\ChibiOS\test\rt\source\test\rt_test_sequence_005.c + + + rt_test_sequence_006.c + 1 + ..\..\..\..\..\ChibiOS\test\rt\source\test\rt_test_sequence_006.c + + + rt_test_sequence_007.c + 1 + ..\..\..\..\..\ChibiOS\test\rt\source\test\rt_test_sequence_007.c + + + rt_test_sequence_008.c + 1 + ..\..\..\..\..\ChibiOS\test\rt\source\test\rt_test_sequence_008.c + + + rt_test_sequence_009.c + 1 + ..\..\..\..\..\ChibiOS\test\rt\source\test\rt_test_sequence_009.c + + + rt_test_sequence_010.c + 1 + ..\..\..\..\..\ChibiOS\test\rt\source\test\rt_test_sequence_010.c + + + rt_test_sequence_011.c + 1 + ..\..\..\..\..\ChibiOS\test\rt\source\test\rt_test_sequence_011.c + + + rt_test_sequence_012.c + 1 + ..\..\..\..\..\ChibiOS\test\rt\source\test\rt_test_sequence_012.c + + + oslib_test_root.c + 1 + ..\..\..\..\..\ChibiOS\test\oslib\source\test\oslib_test_root.c + + + oslib_test_sequence_001.c + 1 + ..\..\..\..\..\ChibiOS\test\oslib\source\test\oslib_test_sequence_001.c + + + oslib_test_sequence_002.c + 1 + ..\..\..\..\..\ChibiOS\test\oslib\source\test\oslib_test_sequence_002.c + + + oslib_test_sequence_003.c + 1 + ..\..\..\..\..\ChibiOS\test\oslib\source\test\oslib_test_sequence_003.c + + + oslib_test_sequence_004.c + 1 + ..\..\..\..\..\ChibiOS\test\oslib\source\test\oslib_test_sequence_004.c + + + oslib_test_sequence_005.c + 1 + ..\..\..\..\..\ChibiOS\test\oslib\source\test\oslib_test_sequence_005.c + + + oslib_test_sequence_006.c + 1 + ..\..\..\..\..\ChibiOS\test\oslib\source\test\oslib_test_sequence_006.c + + + oslib_test_sequence_007.c + 1 + ..\..\..\..\..\ChibiOS\test\oslib\source\test\oslib_test_sequence_007.c + + + oslib_test_sequence_008.c + 1 + ..\..\..\..\..\ChibiOS\test\oslib\source\test\oslib_test_sequence_008.c + + + oslib_test_sequence_009.c + 1 + ..\..\..\..\..\ChibiOS\test\oslib\source\test\oslib_test_sequence_009.c + + + ch_test.c + 1 + ..\..\..\..\..\ChibiOS\os\test\src\ch_test.c + + + ch_test_printf.c + 1 + ..\..\..\..\..\ChibiOS\os\test\src\ch_test_printf.c + + + + + demo + + + main.c + 1 + ..\main.c + + + chconf.h + 5 + ..\cfg\chconf.h + + + halconf.h + 5 + ..\cfg\halconf.h + + + mcuconf.h + 5 + ..\cfg\mcuconf.h + + + debug.c + 1 + ..\debug.c + + + chprintf.c + 1 + ..\..\..\..\..\ChibiOS\os\common\lib\src\chprintf.c + + + memstreams.c + 1 + ..\..\..\..\..\ChibiOS\os\common\lib\src\memstreams.c + + + oop_base_object.c + 1 + ..\..\..\..\..\ChibiOS\os\common\oop\src\oop_base_object.c + + + + + + + + + + + + + + diff --git a/demos/WB32/RT-WB32F3G71-RTC/main.c b/demos/WB32/RT-WB32F3G71-RTC/main.c new file mode 100644 index 0000000000..534b0f94c2 --- /dev/null +++ b/demos/WB32/RT-WB32F3G71-RTC/main.c @@ -0,0 +1,236 @@ +/* + Copyright (C) 2023 Westberry Technology Corp., Ltd + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "debug.h" +#include "chprintf.h" + +#define PORTAB_LINE_LED1 PAL_LINE(GPIOB, 14U) +#define PORTAB_LINE_LED2 PAL_LINE(GPIOB, 13U) +#define PORTAB_LED_OFF PAL_HIGH +#define PORTAB_LED_ON AL_LOW +#define RTC_ALARMPERIOD 10 +#define TEST_ALARM_WAKEUP TRUE + +RTCDateTime timespec; +RTCAlarm alarmspec; + +extern void __early_init(void); + +#if TEST_ALARM_WAKEUP + +static const uint32_t pre_lp_code[] = {553863175u,554459777u,1208378049u,4026624001u,688390415u,554227969u,3204472833u,1198571264u,1073807360u,1073808388u}; +#define PRE_LP() ((void(*)(void))((unsigned int)(pre_lp_code) | 0x01))() + +static const uint32_t post_lp_code[] = {553863177u,554459777u,1208509121u,51443856u,4026550535u,1745485839u,3489677954u,536895496u,673389632u,1198578684u,1073807360u,536866816u,1073808388u}; +#define POST_LP() ((void(*)(void))((unsigned int)(post_lp_code) | 0x01))() + +static void stop_mode_entry(void) { + + EXTI->PR = 0x7FFFF; + for (uint8_t i = 0; i < 8; i++) { + for (uint8_t j = 0; j < 32; j++) { + if (NVIC->ISPR[i] & (0x01UL < j)) { + NVIC->ICPR[i] = (0x01UL < j); + } + } + } + SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk; // Clear Systick IRQ Pending + + /* Clear all bits except DBP and FCLKSD bit */ + PWR->CR0 &= 0x09U; + + /* STOP LP4 MODE S32KON */ + PWR->CR0 |= 0x3B004U; + PWR->CFGR = 0x3B3; + + PRE_LP(); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Request Wait For Interrupt */ + __WFI(); + + POST_LP(); + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (~SCB_SCR_SLEEPDEEP_Msk); +} + +/* + * Running indicator thread. + */ +static THD_WORKING_AREA(blinkWA, 128); +static THD_FUNCTION(blink_thd, arg) { + (void)arg; + while (true) { + chThdSleepMilliseconds(100); + palToggleLine(PORTAB_LINE_LED2); + } +} + +static void my_cb(RTCDriver *rtcp, rtcevent_t event) { + + (void)rtcp; + + switch (event) { + case RTC_EVENT_OVERFLOW: break; + case RTC_EVENT_SECOND: { + palToggleLine(PORTAB_LINE_LED1); + } break; + case RTC_EVENT_ALARM: { + osalSysLockFromISR(); + NVIC_DisableIRQ(RTCAlarm_IRQn); + osalSysUnlockFromISR(); + } break; + } +} + +int main(void) { + + uint32_t tv_sec; + + halInit(); + chSysInit(); + + serial_debug_init(); + + /* + * Init LED port and pad. + */ + palSetPadMode(PAL_PORT(PORTAB_LINE_LED1), PAL_PAD(PORTAB_LINE_LED1), PAL_WB32_MODE_OUTPUT | PAL_WB32_OTYPE_PUSHPULL); + palSetPadMode(PAL_PORT(PORTAB_LINE_LED2), PAL_PAD(PORTAB_LINE_LED2), PAL_WB32_MODE_OUTPUT | PAL_WB32_OTYPE_PUSHPULL); + + chThdCreateStatic(blinkWA, sizeof(blinkWA), NORMALPRIO, blink_thd, NULL); + + while (true){ + chThdSleepSeconds(2); + rtcGetTime(&RTCD1, ×pec); + chprintf((BaseSequentialStream *)&SERIAL_DEBUG_DRIVER, + "lsi sleep %ds year = %d month = %d dstflag=%d dayofweek = %d day = %d millisecond = %d\r\n", + RTC_ALARMPERIOD, timespec.year, timespec.month, timespec.dstflag, timespec.dayofweek, timespec.day, timespec.millisecond); + chThdSleepSeconds(3); + + chSysDisable(); + wb32_set_main_clock_to_mhsi(); + + rtclp_lld_init(); + rtcSetCallback(&RTCD1, my_cb); + rtcWB32GetSecMsec(&RTCD1, &tv_sec, NULL); + alarmspec.tv_sec = tv_sec + RTC_ALARMPERIOD; + rtcSetAlarm(&RTCD1, 0, &alarmspec); + NVIC_EnableIRQ(RTCAlarm_IRQn); + + stop_mode_entry(); + + /* Recovery clock */ + __early_init(); + rtc_lld_init(); + rccEnableEXTI(); + rccEnableUART1(); + rtcSetCallback(&RTCD1, my_cb); + + chSysEnable(); + } +} + +#else /* TEST_ALARM_WAKEUP */ + +binary_semaphore_t alarm_sem; + +/* + * Alarm callback. + */ +static void my_cb(RTCDriver *rtcp, rtcevent_t event) { + + (void)rtcp; + + switch (event) { + case RTC_EVENT_OVERFLOW: break; + case RTC_EVENT_SECOND: { + palToggleLine(PORTAB_LINE_LED2); + } break; + case RTC_EVENT_ALARM: { + palToggleLine(PORTAB_LINE_LED1); + osalSysLockFromISR(); + chBSemSignalI(&alarm_sem); + osalSysUnlockFromISR(); + } break; + } +} + +static time_measurement_t sett, gett; + +int main(void) { + + msg_t status = MSG_TIMEOUT; + uint32_t tv_sec; + + halInit(); + chSysInit(); + + /* + * Init LED port and pad. + */ + palSetPadMode(PAL_PORT(PORTAB_LINE_LED1), PAL_PAD(PORTAB_LINE_LED1), PAL_WB32_MODE_OUTPUT | PAL_WB32_OTYPE_PUSHPULL); + palSetPadMode(PAL_PORT(PORTAB_LINE_LED2), PAL_PAD(PORTAB_LINE_LED2), PAL_WB32_MODE_OUTPUT | PAL_WB32_OTYPE_PUSHPULL); + + chBSemObjectInit(&alarm_sem, TRUE); + chTMObjectInit(&sett); + chTMObjectInit(&gett); + + /* compile ability test */ + chTMStartMeasurementX(&gett); + rtcGetTime(&RTCD1, ×pec); + chTMStopMeasurementX(&gett); + + rtcWB32SetSec(&RTCD1, 1414845464); + osalThreadSleepMilliseconds(10); + rtcGetTime(&RTCD1, ×pec); + timespec.month -= 1; + + chTMStartMeasurementX(&sett); + rtcSetTime(&RTCD1, ×pec); + chTMStopMeasurementX(&sett); + osalThreadSleepMilliseconds(10); + + rtcGetTime(&RTCD1, ×pec); + + rtcWB32GetSecMsec(&RTCD1, &tv_sec, NULL); + alarmspec.tv_sec = tv_sec + RTC_ALARMPERIOD; + rtcSetAlarm(&RTCD1, 0, &alarmspec); + + rtcSetCallback(&RTCD1, my_cb); + + while (true){ + /* Wait until alarm callback signaled semaphore.*/ + status = chBSemWaitTimeout(&alarm_sem, TIME_S2I(RTC_ALARMPERIOD + 5)); + + if (status == MSG_TIMEOUT){ + osalSysHalt("time is out"); + } else { + rtcWB32GetSecMsec(&RTCD1, &tv_sec, NULL); + alarmspec.tv_sec = tv_sec + RTC_ALARMPERIOD; + rtcSetAlarm(&RTCD1, 0, &alarmspec); + } + } +} +#endif /* TEST_ALARM_WAKEUP */ + + + diff --git a/demos/WB32/RT-WB32F3G71-RTC/readme.md b/demos/WB32/RT-WB32F3G71-RTC/readme.md new file mode 100644 index 0000000000..78d9433f55 --- /dev/null +++ b/demos/WB32/RT-WB32F3G71-RTC/readme.md @@ -0,0 +1,4 @@ +# WB32F3G71xx Serial MCU Demo + +This is an example. + diff --git a/demos/WB32/RT-WB32FQ95-GENERIC/cfg/mcuconf.h b/demos/WB32/RT-WB32FQ95-GENERIC/cfg/mcuconf.h index a24a1e9543..2e00d1eb1b 100644 --- a/demos/WB32/RT-WB32FQ95-GENERIC/cfg/mcuconf.h +++ b/demos/WB32/RT-WB32FQ95-GENERIC/cfg/mcuconf.h @@ -123,12 +123,12 @@ /* * SERIAL driver system settings. */ -#define WB32_SERIAL_USE_UART1 FALSE -#define WB32_SERIAL_USE_UART2 FALSE -#define WB32_SERIAL_USE_UART3 FALSE -#define WB32_SERIAL_USART1_PRIORITY 12 -#define WB32_SERIAL_USART2_PRIORITY 12 -#define WB32_SERIAL_USART3_PRIORITY 12 +#define WB32_SERIAL_USE_UART1 FALSE +#define WB32_SERIAL_USE_UART2 FALSE +#define WB32_SERIAL_USE_UART3 FALSE +#define WB32_SERIAL_UART1_PRIORITY 12 +#define WB32_SERIAL_UART2_PRIORITY 12 +#define WB32_SERIAL_UART3_PRIORITY 12 /* * SPI driver system settings. diff --git a/demos/WB32/RT-WB32FQ95-GENERIC/keil/ch.uvoptx b/demos/WB32/RT-WB32FQ95-GENERIC/keil/ch.uvoptx index 9adafd96d1..fac19b7670 100644 --- a/demos/WB32/RT-WB32FQ95-GENERIC/keil/ch.uvoptx +++ b/demos/WB32/RT-WB32FQ95-GENERIC/keil/ch.uvoptx @@ -1062,6 +1062,18 @@ 0 0 + + 6 + 70 + 1 + 0 + 0 + 0 + ..\..\..\..\..\ChibiOS\os\oslib\src\chmemchecks.c + chmemchecks.c + 0 + 0 + @@ -1072,7 +1084,7 @@ 0 7 - 70 + 71 1 0 0 @@ -1084,7 +1096,7 @@ 7 - 71 + 72 5 0 0 @@ -1104,7 +1116,7 @@ 0 8 - 72 + 73 5 0 0 @@ -1116,7 +1128,7 @@ 8 - 73 + 74 5 0 0 @@ -1128,7 +1140,7 @@ 8 - 74 + 75 5 0 0 @@ -1140,7 +1152,7 @@ 8 - 75 + 76 5 0 0 @@ -1152,7 +1164,7 @@ 8 - 76 + 77 5 0 0 @@ -1164,7 +1176,7 @@ 8 - 77 + 78 5 0 0 @@ -1176,7 +1188,7 @@ 8 - 78 + 79 5 0 0 @@ -1188,7 +1200,7 @@ 8 - 79 + 80 5 0 0 @@ -1200,7 +1212,7 @@ 8 - 80 + 81 5 0 0 @@ -1212,7 +1224,7 @@ 8 - 81 + 82 5 0 0 @@ -1224,7 +1236,7 @@ 8 - 82 + 83 5 0 0 @@ -1236,7 +1248,7 @@ 8 - 83 + 84 5 0 0 @@ -1248,7 +1260,7 @@ 8 - 84 + 85 5 0 0 @@ -1260,7 +1272,7 @@ 8 - 85 + 86 5 0 0 @@ -1272,7 +1284,7 @@ 8 - 86 + 87 5 0 0 @@ -1284,7 +1296,7 @@ 8 - 87 + 88 5 0 0 @@ -1296,7 +1308,7 @@ 8 - 88 + 89 5 0 0 @@ -1308,7 +1320,7 @@ 8 - 89 + 90 5 0 0 @@ -1320,7 +1332,7 @@ 8 - 90 + 91 5 0 0 @@ -1332,7 +1344,7 @@ 8 - 91 + 92 5 0 0 @@ -1344,7 +1356,7 @@ 8 - 92 + 93 5 0 0 @@ -1356,7 +1368,7 @@ 8 - 93 + 94 5 0 0 @@ -1368,7 +1380,7 @@ 8 - 94 + 95 5 0 0 @@ -1380,7 +1392,7 @@ 8 - 95 + 96 5 0 0 @@ -1392,7 +1404,7 @@ 8 - 96 + 97 5 0 0 @@ -1404,7 +1416,7 @@ 8 - 97 + 98 5 0 0 @@ -1416,7 +1428,7 @@ 8 - 98 + 99 5 0 0 @@ -1428,7 +1440,7 @@ 8 - 99 + 100 5 0 0 @@ -1440,7 +1452,7 @@ 8 - 100 + 101 5 0 0 @@ -1452,7 +1464,7 @@ 8 - 101 + 102 5 0 0 @@ -1464,7 +1476,7 @@ 8 - 102 + 103 1 0 0 @@ -1476,7 +1488,7 @@ 8 - 103 + 104 1 0 0 @@ -1488,7 +1500,7 @@ 8 - 104 + 105 1 0 0 @@ -1500,7 +1512,7 @@ 8 - 105 + 106 1 0 0 @@ -1512,7 +1524,7 @@ 8 - 106 + 107 1 0 0 @@ -1524,7 +1536,7 @@ 8 - 107 + 108 1 0 0 @@ -1536,7 +1548,7 @@ 8 - 108 + 109 1 0 0 @@ -1548,7 +1560,7 @@ 8 - 109 + 110 1 0 0 @@ -1560,7 +1572,7 @@ 8 - 110 + 111 1 0 0 @@ -1572,7 +1584,7 @@ 8 - 111 + 112 1 0 0 @@ -1584,7 +1596,7 @@ 8 - 112 + 113 1 0 0 @@ -1596,7 +1608,7 @@ 8 - 113 + 114 1 0 0 @@ -1608,7 +1620,7 @@ 8 - 114 + 115 1 0 0 @@ -1620,7 +1632,7 @@ 8 - 115 + 116 1 0 0 @@ -1632,7 +1644,7 @@ 8 - 116 + 117 1 0 0 @@ -1644,7 +1656,7 @@ 8 - 117 + 118 1 0 0 @@ -1656,7 +1668,7 @@ 8 - 118 + 119 1 0 0 @@ -1668,7 +1680,7 @@ 8 - 119 + 120 1 0 0 @@ -1680,7 +1692,7 @@ 8 - 120 + 121 1 0 0 @@ -1692,7 +1704,7 @@ 8 - 121 + 122 1 0 0 @@ -1704,7 +1716,7 @@ 8 - 122 + 123 1 0 0 @@ -1716,7 +1728,7 @@ 8 - 123 + 124 1 0 0 @@ -1728,7 +1740,7 @@ 8 - 124 + 125 1 0 0 @@ -1740,7 +1752,7 @@ 8 - 125 + 126 1 0 0 @@ -1752,7 +1764,7 @@ 8 - 126 + 127 5 0 0 @@ -1764,7 +1776,7 @@ 8 - 127 + 128 5 0 0 @@ -1776,7 +1788,7 @@ 8 - 128 + 129 5 0 0 @@ -1788,7 +1800,7 @@ 8 - 129 + 130 5 0 0 @@ -1800,7 +1812,7 @@ 8 - 130 + 131 5 0 0 @@ -1812,7 +1824,7 @@ 8 - 131 + 132 5 0 0 @@ -1824,7 +1836,7 @@ 8 - 132 + 133 5 0 0 @@ -1836,7 +1848,7 @@ 8 - 133 + 134 5 0 0 @@ -1848,7 +1860,7 @@ 8 - 134 + 135 1 0 0 @@ -1860,7 +1872,7 @@ 8 - 135 + 136 1 0 0 @@ -1872,7 +1884,7 @@ 8 - 136 + 137 1 0 0 @@ -1884,7 +1896,7 @@ 8 - 137 + 138 1 0 0 @@ -1896,7 +1908,7 @@ 8 - 138 + 139 1 0 0 @@ -1908,7 +1920,7 @@ 8 - 139 + 140 1 0 0 @@ -1928,7 +1940,7 @@ 0 9 - 140 + 141 1 0 0 @@ -1940,7 +1952,7 @@ 9 - 141 + 142 1 0 0 @@ -1952,7 +1964,7 @@ 9 - 142 + 143 1 0 0 @@ -1964,7 +1976,7 @@ 9 - 143 + 144 1 0 0 @@ -1976,7 +1988,7 @@ 9 - 144 + 145 1 0 0 @@ -1996,7 +2008,7 @@ 0 10 - 145 + 146 1 0 0 @@ -2008,7 +2020,7 @@ 10 - 146 + 147 5 0 0 @@ -2028,7 +2040,7 @@ 0 11 - 147 + 148 1 0 0 @@ -2040,7 +2052,7 @@ 11 - 148 + 149 1 0 0 @@ -2052,7 +2064,7 @@ 11 - 149 + 150 1 0 0 @@ -2064,7 +2076,7 @@ 11 - 150 + 151 1 0 0 @@ -2076,7 +2088,7 @@ 11 - 151 + 152 1 0 0 @@ -2088,7 +2100,7 @@ 11 - 152 + 153 1 0 0 @@ -2100,7 +2112,7 @@ 11 - 153 + 154 1 0 0 @@ -2112,7 +2124,7 @@ 11 - 154 + 155 1 0 0 @@ -2124,7 +2136,7 @@ 11 - 155 + 156 1 0 0 @@ -2136,7 +2148,7 @@ 11 - 156 + 157 1 0 0 @@ -2148,7 +2160,7 @@ 11 - 157 + 158 1 0 0 @@ -2160,7 +2172,7 @@ 11 - 158 + 159 1 0 0 @@ -2172,7 +2184,7 @@ 11 - 159 + 160 1 0 0 @@ -2184,7 +2196,7 @@ 11 - 160 + 161 1 0 0 @@ -2196,7 +2208,7 @@ 11 - 161 + 162 1 0 0 @@ -2208,7 +2220,7 @@ 11 - 162 + 163 1 0 0 @@ -2220,7 +2232,7 @@ 11 - 163 + 164 1 0 0 @@ -2232,7 +2244,7 @@ 11 - 164 + 165 1 0 0 @@ -2244,7 +2256,7 @@ 11 - 165 + 166 1 0 0 @@ -2256,7 +2268,7 @@ 11 - 166 + 167 1 0 0 @@ -2268,7 +2280,7 @@ 11 - 167 + 168 1 0 0 @@ -2280,7 +2292,7 @@ 11 - 168 + 169 1 0 0 @@ -2292,7 +2304,7 @@ 11 - 169 + 170 1 0 0 @@ -2304,7 +2316,7 @@ 11 - 170 + 171 1 0 0 @@ -2316,7 +2328,7 @@ 11 - 171 + 172 1 0 0 @@ -2336,7 +2348,7 @@ 0 12 - 172 + 173 1 0 0 @@ -2348,7 +2360,7 @@ 12 - 173 + 174 5 0 0 @@ -2360,7 +2372,7 @@ 12 - 174 + 175 5 0 0 @@ -2372,7 +2384,7 @@ 12 - 175 + 176 5 0 0 diff --git a/demos/WB32/RT-WB32FQ95-GENERIC/keil/ch.uvprojx b/demos/WB32/RT-WB32FQ95-GENERIC/keil/ch.uvprojx index 7947c2040b..f182a7e70c 100644 --- a/demos/WB32/RT-WB32FQ95-GENERIC/keil/ch.uvprojx +++ b/demos/WB32/RT-WB32FQ95-GENERIC/keil/ch.uvprojx @@ -15,7 +15,7 @@ ARMCM3 ARM - ARM.CMSIS.5.6.0 + ARM.CMSIS.5.1.1 http://www.keil.com/pack/ IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M3") CLOCK(12000000) ESEL ELITTLE @@ -32,7 +32,7 @@ - + $$Device:ARMCM3$Device\ARM\SVD\ARMCM3.svd 0 0 @@ -335,7 +335,7 @@ -UWB32FQ95xx CORTEX_USE_FPU=0 TEST_CFG_SIZE_REPORT=0 __heap_base__=Image$$$$RW_IRAM1$$$$ZI$$$$Limit __heap_end__=Image$$$$RW_IRAM1$$$$Base - ..\;..\cfg;..\..\..\..\..\ChibiOS\os\license;..\..\..\..\..\ChibiOS-Contrib\os\common\startup\ARMCMx\devices\WB32FQ95xx;..\..\..\..\..\ChibiOS\os\common\ext\ARM\CMSIS\Core\Include;..\..\..\..\..\ChibiOS-Contrib\os\common\ext\CMSIS\WB32\WB32FQ95xx;..\..\..\..\..\ChibiOS\os\common\portability\Keil;..\..\..\..\..\ChibiOS\os\common\ports\ARM-common;..\..\..\..\..\ChibiOS\os\common\ports\ARMv7-M;..\..\..\..\..\ChibiOS\os\rt\include;..\..\..\..\..\ChibiOS\os\oslib\include;..\..\..\..\..\ChibiOS\os\hal\osal\rt-nil;..\..\..\..\..\ChibiOS\os\hal\include;..\board;..\..\..\..\..\ChibiOS\os\hal\ports\common\ARMCMx;..\..\..\..\..\ChibiOS-Contrib\os\hal\ports\WB32\WB32FQ95xx;..\..\..\..\..\ChibiOS-Contrib\os\hal\ports\WB32\LLD\GPIOv1;..\..\..\..\os\hal\ports\WB32\LLD\DMAv1;..\..\..\..\os\hal\ports\WB32\LLD\TIMv1;..\..\..\..\..\ChibiOS\os\test\include;..\..\..\..\..\ChibiOS\test\rt\source\test;..\..\..\..\..\ChibiOS\test\oslib\source\test + ..\;..\cfg;..\..\..\..\..\ChibiOS\os\license;..\..\..\..\..\ChibiOS-Contrib\os\common\startup\ARMCMx\devices\WB32FQ95xx;..\..\..\..\..\ChibiOS\os\common\ext\ARM\CMSIS\Core\Include;..\..\..\..\..\ChibiOS-Contrib\os\common\ext\CMSIS\WB32\WB32FQ95xx;..\..\..\..\..\ChibiOS\os\common\portability\Keil;..\..\..\..\..\ChibiOS\os\common\ports\ARM-common;..\..\..\..\..\ChibiOS\os\common\ports\ARMv7-M;..\..\..\..\..\ChibiOS\os\rt\include;..\..\..\..\..\ChibiOS\os\oslib\include;..\..\..\..\..\ChibiOS\os\hal\osal\rt-nil;..\..\..\..\..\ChibiOS\os\hal\include;..\board;..\..\..\..\..\ChibiOS\os\hal\ports\common\ARMCMx;..\..\..\..\..\ChibiOS-Contrib\os\hal\ports\WB32\WB32FQ95xx;..\..\..\..\..\ChibiOS-Contrib\os\hal\ports\WB32\LLD\GPIOv1;..\..\..\..\os\hal\ports\WB32\LLD\DMAv1;..\..\..\..\os\hal\ports\WB32\LLD\TIMv1;..\..\..\..\..\ChibiOS\os\test\include;..\..\..\..\..\ChibiOS\test\rt\source\test;..\..\..\..\..\ChibiOS\test\oslib\source\test;..\..\..\..\os\hal\ports\WB32\LLD\EXTIv1 @@ -749,6 +749,11 @@ 1 ..\..\..\..\..\ChibiOS\os\oslib\src\chpipes.c + + chmemchecks.c + 1 + ..\..\..\..\..\ChibiOS\os\oslib\src\chmemchecks.c + diff --git a/os/hal/ports/WB32/LLD/EXTIv1/driver.mk b/os/hal/ports/WB32/LLD/EXTIv1/driver.mk new file mode 100644 index 0000000000..317b621071 --- /dev/null +++ b/os/hal/ports/WB32/LLD/EXTIv1/driver.mk @@ -0,0 +1,2 @@ +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/EXTIv1/wb32_exti.c +PLATFORMINC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/EXTIv1 diff --git a/os/hal/ports/WB32/LLD/EXTIv1/wb32_exti.c b/os/hal/ports/WB32/LLD/EXTIv1/wb32_exti.c new file mode 100644 index 0000000000..a30a4e9700 --- /dev/null +++ b/os/hal/ports/WB32/LLD/EXTIv1/wb32_exti.c @@ -0,0 +1,145 @@ +/* + Copyright (C) 2023 Westberry Technology Corp., Ltd + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file EXTIv1/WB32_exti.c + * @brief EXTI helper driver code. + * + * @addtogroup WB32_EXTI + * @details EXTI sharing helper driver. + * @{ + */ + +#include "hal.h" + +/* The following macro is only defined if some driver requiring EXTI services + has been enabled.*/ +#if defined(WB32_EXTI_REQUIRED) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief WB32 EXTI group 1 lines initialization. + * + * @param[in] mask mask of group 1 lines to be initialized + * @param[in] mode initialization mode + * + * @api + */ +void extiEnable(uint32_t mask, extimode_t mode) { + uint32_t cmask; + /* Enable EXTI clock.*/ + rccEnableEXTI(); + + /* Mask including only configurable lines.*/ + cmask = mask & ~WB32_EXTI_IMR1_MASK; + + if ((mode & EXTI_MODE_EDGES_MASK) == 0U) { + /* Disabling channels.*/ + EXTI->IMR &= ~mask; + EXTI->EMR &= ~mask; + EXTI->RTSR &= ~cmask; + EXTI->FTSR &= ~cmask; + EXTI->PR = cmask; + } else { + /* Programming edge registers.*/ + if (mode & EXTI_MODE_RISING_EDGE) { + EXTI->RTSR |= cmask; + } + else { + EXTI->RTSR &= ~cmask; + } + if (mode & EXTI_MODE_FALLING_EDGE) { + EXTI->FTSR |= cmask; + } + else { + EXTI->FTSR &= ~cmask; + } + + /* Programming interrupt and event registers.*/ + if ((mode & EXTI_MODE_ACTION_MASK) == EXTI_MODE_ACTION_INTERRUPT) { + EXTI->IMR |= mask; + EXTI->EMR &= ~mask; + } + else { + EXTI->EMR |= mask; + EXTI->IMR &= ~mask; + } + } + + if ((!EXTI->IMR) && (!EXTI->EMR)) { + /* Disable EXTI clock.*/ + rccDisableEXTI(); + } +} + +/** + * @brief WB32 EXTI line initialization. + * + * @param[in] line line to be initialized + * @param[in] mode initialization mode + * + * @api + */ +void extiEnableLine(extiline_t line, extimode_t mode) { + uint32_t mask = (1U << (line & 0x1FU)); + + osalDbgCheck(line < WB32_EXTI_NUM_LINES); + osalDbgCheck((mode & ~EXTI_MODE_MASK) == 0U); + + extiEnable(mask, mode); +} + +/** + * @brief WB32 EXTI line IRQ status clearing. + * + * @param[in] line line to be initialized + * + * @api + */ +void extiClearLine(extiline_t line) { + uint32_t mask = (1U << (line & 0x1FU)); + + osalDbgCheck(line < WB32_EXTI_NUM_LINES); + + extiClear(mask); +} + +#endif /* WB32_EXTI_REQUIRED */ + +/** @} */ diff --git a/os/hal/ports/WB32/LLD/EXTIv1/wb32_exti.h b/os/hal/ports/WB32/LLD/EXTIv1/wb32_exti.h new file mode 100644 index 0000000000..7266915660 --- /dev/null +++ b/os/hal/ports/WB32/LLD/EXTIv1/wb32_exti.h @@ -0,0 +1,117 @@ +/* + Copyright (C) 2023 Westberry Technology Corp., Ltd + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file EXTIv1/WB32_exti.h + * @brief EXTI helper driver header. + * + * @addtogroup WB32_EXTI + * @{ + */ + +#ifndef WB32_EXTI_H +#define WB32_EXTI_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/* EXTI attributes.*/ +#define WB32_EXTI_IMR1_MASK 0xFFF00000U + +/** + * @name EXTI channel modes + * @{ + */ +#define EXTI_MODE_MASK 7U /**< @brief Mode parameter mask. */ +#define EXTI_MODE_EDGES_MASK 3U /**< @brief Edges field mask. */ +#define EXTI_MODE_DISABLED 0U /**< @brief Channel disabled. */ +#define EXTI_MODE_RISING_EDGE 1U /**< @brief Rising edge callback. */ +#define EXTI_MODE_FALLING_EDGE 2U /**< @brief Falling edge callback. */ +#define EXTI_MODE_BOTH_EDGES 3U /**< @brief Both edges callback. */ +#define EXTI_MODE_ACTION_MASK 4U /**< @brief Action field mask. */ +#define EXTI_MODE_ACTION_INTERRUPT 0U /**< @brief Interrupt mode. */ +#define EXTI_MODE_ACTION_EVENT 4U /**< @brief Event mode. */ +/** @} */ + + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !defined(WB32_EXTI_NUM_LINES) +#error "WB32_EXTI_NUM_LINES not defined in registry" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of an EXTI line identifier. + */ +typedef uint32_t extiline_t; + +/** + * @brief Type of an EXTI line mode. + */ +typedef uint32_t extimode_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief From group 1 line number to mask. + * + * @param[in] line line number in range 0..31 + */ +#define EXTI_MASK(line) (uint32_t)(1U << (line)) + +/** + * @brief WB32 EXTI group 1 IRQ status clearing. + * + * @param[in] mask mask of group 1 lines to be initialized + * + * @special + */ + +#define extiClear(mask) do { \ + osalDbgAssert(((mask) & WB32_EXTI_IMR1_MASK) == 0U, "fixed lines"); \ + EXTI->PR = (uint32_t)(mask); \ +} while (false) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void extiEnable(uint32_t mask, extimode_t mode); + void extiEnableLine(extiline_t line, extimode_t mode); + void extiClearLine(extiline_t line); + #ifdef __cplusplus +} +#endif + +#endif /* WB32_EXTI_H */ + +/** @} */ diff --git a/os/hal/ports/WB32/LLD/I2Cv1/hal_i2c_lld.c b/os/hal/ports/WB32/LLD/I2Cv1/hal_i2c_lld.c index 9273cee265..06ed87a9a9 100644 --- a/os/hal/ports/WB32/LLD/I2Cv1/hal_i2c_lld.c +++ b/os/hal/ports/WB32/LLD/I2Cv1/hal_i2c_lld.c @@ -114,7 +114,7 @@ static void i2c_lld_configuration(I2CDriver *i2cp) { osalDbgCheck((i2cp != NULL) && (clock_speed > 0) && - (clock_speed <= 400000)); + (clock_speed <= 3400000)); con_reg = I2C_CON_SLAVE_DISABLE | I2C_CON_RESTART_EN | I2C_CON_MASTER_MODE; @@ -149,6 +149,12 @@ static void i2c_lld_configuration(I2CDriver *i2cp) { dp->FS_SCL_HCNT = (uint32_t)(tval - 7 - dp->FS_SPKLEN); dp->FS_SCL_LCNT = (uint32_t)(tval - 1); } + else if (clock_speed <= 3400000) { + con_reg |= I2C_CON_SPEED_HIGH; + dp->SDA_SETUP = (uint32_t)(WB32_PCLK2 / 1000000 * 0.01); // 10ns + dp->FS_SCL_HCNT = (uint32_t)(tval - 7 - dp->FS_SPKLEN); + dp->FS_SCL_LCNT = (uint32_t)(tval - 1); + } dp->CON = con_reg; } diff --git a/os/hal/ports/WB32/LLD/RTCv1/driver.mk b/os/hal/ports/WB32/LLD/RTCv1/driver.mk new file mode 100644 index 0000000000..55d083207b --- /dev/null +++ b/os/hal/ports/WB32/LLD/RTCv1/driver.mk @@ -0,0 +1,8 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_RTC TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/RTCv1/hal_rtc_lld.c +endif +else +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/RTCv1/hal_rtc_lld.c +endif +PLATFORMINC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/RTCv1 diff --git a/os/hal/ports/WB32/LLD/RTCv1/hal_rtc_lld.c b/os/hal/ports/WB32/LLD/RTCv1/hal_rtc_lld.c new file mode 100644 index 0000000000..a8e20e8819 --- /dev/null +++ b/os/hal/ports/WB32/LLD/RTCv1/hal_rtc_lld.c @@ -0,0 +1,617 @@ +/* + Copyright (C) 2023 Westberry Technology Corp., Ltd + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * @file RTCv1/hal_rtc_lld.c + * @brief WB32 RTC subsystem low level driver header. + * + * @addtogroup RTC + * @{ + */ + +#include "hal.h" + +#if HAL_USE_RTC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ +static bool rtc_mod_flag; +static uint32_t last_rtc_cnt = 0; +/** + * @brief Initializes the backup domain. + * @note WARNING! Changing clock source impossible without resetting + * of the whole BKP domain. + */ +static void hal_lld_backup_domain_init(void) { + + PWR_BackupAccessEnable(); + + rccResetBKP(); + /* Turn on the backup domain clock.*/ + rccEnableBKP(); + +#if HAL_USE_RTC + /* If enabled then the LSE is started.*/ +# if WB32_LSE_ENABLED +# if defined(WB32_LSE_BYPASS) + /* No LSE Bypass.*/ + BKP->BDCR = BKP_LSE_Bypass; +# else + /*LSE Bypass.*/ + BKP->BDCR = BKP_LSE_ON; +# endif + while ((BKP->BDCR & 0x2U) == 0) + ; /* Waits until LSE is stable. */ +# endif /* WB32_LSE_ENABLED */ + +# if WB32_RTCSEL == WB32_RTCSEL_HSEDIV + RCC->HSE2RTCENR = 1; + BKP->BDCR = (BKP->BDCR & (~(WB32_RTCSEL_MASK))) | (WB32_RTCSEL_HSEDIV); +# elif WB32_RTCSEL == WB32_RTCSEL_LSE + BKP->BDCR = (BKP->BDCR & (~(WB32_RTCSEL_MASK))) | (WB32_RTCSEL_LSE); +# elif WB32_RTCSEL == WB32_RTCSEL_LSI || WB32_RTCSEL == WB32_RTCSEL_NOCLOCK +# error 'The LSI clock cannot be used under normal use of the RTC' +# endif + + /* Prescaler value loaded in registers.*/ + rtc_lld_set_prescaler(rtc_mod_flag); + + /* RTC clock enabled.*/ + BKP->BDCR |= (1 << 15); +#endif /* HAL_USE_RTC */ + + rccDisableBKP(); +} +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief RTC driver identifier. + */ +RTCDriver RTCD1; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Wait for synchronization of RTC registers with APB1 bus. + * @details This function must be invoked before trying to read RTC registers + * in the backup domain: DIV, CNT, ALR. CR registers can always + * be read. + * + * @notapi + */ +static void rtc_apb1_sync(void) { + + /* RSF bit must be cleared by software after an APB1 reset or an APB1 clock + stop. Otherwise its value will not be actual. */ + RTCD1.rtc->CRL &= ~RTC_CRL_RSF; + + /* Loop until RSF flag is set */ + while ((RTC->CRL & RTC_CRL_RSF) == 0) + ; +} + +/** + * @brief Wait for for previous write operation complete. + * @details This function must be invoked before writing to any RTC registers + * + * @notapi + */ +static void rtc_wait_write_completed(void) { + + while ((RTC->CRL & RTC_CRL_RTOFF) == 0) + ; +} + +/** + * @brief Acquires write access to RTC registers. + * @details Before writing to the backup domain RTC registers the previous + * write operation must be completed. Use this function before + * writing to PRL, CNT, ALR registers. + * + * @notapi + */ +static void rtc_acquire_access(void) { + + rtc_wait_write_completed(); + RTC->CRL |= RTC_CRL_CNF; +} + +/** + * @brief Releases write access to RTC registers. + * + * @notapi + */ +static void rtc_release_access(void) { + + RTC->CRL &= ~RTC_CRL_CNF; +} + +/** + * @brief Converts time from timespec to seconds counter. + * + * @param[in] timespec pointer to a @p RTCDateTime structure + * @return the TR register encoding. + * + * @notapi + */ +static time_t rtc_encode(const RTCDateTime *timespec) { + struct tm tim; + + rtcConvertDateTimeToStructTm(timespec, &tim, NULL); + return mktime(&tim); +} + +/** + * @brief Converts time from seconds/milliseconds to timespec. + * + * @param[in] tv_sec seconds value + * @param[in] tv_msec milliseconds value + * @param[out] timespec pointer to a @p RTCDateTime structure + * + * @notapi + */ +static void rtc_decode(uint32_t tv_sec, + uint32_t tv_msec, + RTCDateTime *timespec) { + struct tm tim; + struct tm *t; + const time_t time = (time_t)tv_sec; /* Could be 64 bits.*/ + + /* If the conversion is successful the function returns a pointer + to the object the result was written into.*/ +#if defined(__GNUC__) || defined(__CC_ARM) + t = localtime_r(&time, &tim); + osalDbgAssert(t != NULL, "conversion failed"); +#else + t = localtime(&time); + memcpy(&tim, t, sizeof(struct tm)); +#endif + + rtcConvertStructTmToDateTime(&tim, tv_msec, timespec); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief RTC interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(WB32_RTCAlarm_IRQ_VECTOR) { + uint16_t flags; + + OSAL_IRQ_PROLOGUE(); + + /* Code hits this wait only when AHB1 bus was previously powered off by any + reason (standby, reset, etc). In other cases there is no waiting.*/ + rtc_apb1_sync(); + + /* Mask of all enabled and pending sources.*/ + flags = RTCD1.rtc->CRL; + RTCD1.rtc->CRL &= ~(RTC_CRL_SECF | RTC_CRL_ALRF | RTC_CRL_OWF); + + extiClearLine(WB32_RTC_ALARM_EXTI); + + if (flags & RTC_CRL_SECF) + RTCD1.callback(&RTCD1, RTC_EVENT_SECOND); + + if (flags & RTC_CRL_ALRF) + RTCD1.callback(&RTCD1, RTC_EVENT_ALARM); + + if (flags & RTC_CRL_OWF) + RTCD1.callback(&RTCD1, RTC_EVENT_OVERFLOW); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief RTC interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(WB32_RTC_IRQ_VECTOR) { + uint16_t flags; + + OSAL_IRQ_PROLOGUE(); + + /* Code hits this wait only when AHB1 bus was previously powered off by any + reason (standby, reset, etc). In other cases there is no waiting.*/ + rtc_apb1_sync(); + + /* Mask of all enabled and pending sources.*/ + flags = RTCD1.rtc->CRL; + RTCD1.rtc->CRL &= ~(RTC_CRL_SECF | RTC_CRL_ALRF | RTC_CRL_OWF); + + if (flags & RTC_CRL_SECF) + RTCD1.callback(&RTCD1, RTC_EVENT_SECOND); + + if (flags & RTC_CRL_ALRF) + RTCD1.callback(&RTCD1, RTC_EVENT_ALARM); + + if (flags & RTC_CRL_OWF) + RTCD1.callback(&RTCD1, RTC_EVENT_OVERFLOW); + + OSAL_IRQ_EPILOGUE(); +} +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Load value of RTCCLK to prescaler registers. + * @note The pre-scaler must not be set on every reset as RTC clock + * counts are lost when it is set. + * @note This function designed to be called from + * hal_lld_backup_domain_init(). Because there is only place + * where possible to detect BKP domain reset event reliably. + * + * @notapi + */ +void rtc_lld_set_prescaler(bool rtc_mod) { + syssts_t sts; + + /* Entering a reentrant critical zone.*/ + sts = osalSysGetStatusAndLockX(); + + rtc_acquire_access(); + if (rtc_mod != true) { + RTC->PRLH = (uint16_t)((WB32_RTCCLK - 1) >> 16) & 0x000F; + RTC->PRLL = (uint16_t)(((WB32_RTCCLK - 1)) & 0xFFFF); + } else { + RTC->PRLH = (uint16_t)((WB32_RTCLPCLK - 1) >> 16) & 0x000F; + RTC->PRLL = (uint16_t)(((WB32_RTCLPCLK - 1)) & 0xFFFF); + } + rtc_release_access(); + + /* Leaving a reentrant critical zone.*/ + osalSysRestoreStatusX(sts); +} + +/** + * @brief Initialize RTC. + * + * @notapi + */ +void rtc_lld_init(void) { + + /* RTC object initialization.*/ + rtcObjectInit(&RTCD1); + + rtc_mod_flag = false; + + /* RTC pointer initialization.*/ + RTCD1.rtc = RTC; + + last_rtc_cnt = ((uint32_t)(RTCD1.rtc->CNTH) << 16) + RTCD1.rtc->CNTL; + /* Initializes the backup domain.*/ + hal_lld_backup_domain_init(); + + /* Required because access to PRL.*/ + rtc_apb1_sync(); + + /* All interrupts initially disabled.*/ + rtc_wait_write_completed(); + RTCD1.rtc->CRH = 0; + + /* Callback initially disabled.*/ + RTCD1.callback = NULL; + + rtcWB32SetSec(&RTCD1, last_rtc_cnt); + /* IRQ vector permanently assigned to this driver.*/ + nvicEnableVector(WB32_RTC_NUMBER, WB32_RTC_IRQ_PRIORITY); +} + +/** + * @brief Initialize RTC_LP. + * + * @notapi + */ +void rtclp_lld_init(void) { + + /* RTC object initialization.*/ + rtcObjectInit(&RTCD1); + rtc_mod_flag = true; + /* RTC pointer initialization.*/ + RTCD1.rtc = RTC; + + last_rtc_cnt = ((uint32_t)(RTCD1.rtc->CNTH) << 16) + RTCD1.rtc->CNTL; + + PWR_BackupAccessEnable(); + + rccResetBKP(); + /* Turn on the backup domain clock.*/ + rccEnableBKP(); + +#if HAL_USE_RTC +# if WB32_RTCLP_SEL == WB32_RTCSEL_LSE + /* If enabled then the LSE is started.*/ +# if WB32_LSE_ENABLED +# if defined(WB32_LSE_BYPASS) + /* No LSE Bypass.*/ + BKP->BDCR = BKP_LSE_Bypass; +# else + /*LSE Bypass.*/ + BKP->BDCR = (1 << 0); +# endif + while ((BKP->BDCR & 0x2U) == 0) + ; /* Waits until LSE is stable. */ + BKP->BDCR = (BKP->BDCR & (~(WB32_RTCSEL_MASK))) | (WB32_RTCSEL_LSE); +# endif /* WB32_LSE_ENABLED */ +# elif WB32_RTCLP_SEL == WB32_RTCSEL_LSI + RCC->LSI2RTCENR = 1; + /* Select the RTC clock source */ + BKP->BDCR = (BKP->BDCR & (~(WB32_RTCSEL_MASK))) | (WB32_RTCSEL_LSI); + + /* Prescaler value loaded in registers.*/ + rtc_lld_set_prescaler(rtc_mod_flag); +# else +# error 'The RTC LP clock is selected incorrectly' +# endif + /* RTC clock enabled.*/ + BKP->BDCR |= (1 << 15); +#endif + + rccDisableBKP(); + /* RSF bit must be cleared by software after an APB1 reset or an APB1 clock + stop. Otherwise its value will not be actual. */ + RTCD1.rtc->CRL &= ~RTC_CRL_RSF; + + /* Required because access to PRL.*/ + rtc_apb1_sync(); + + /* All interrupts initially disabled.*/ + rtc_wait_write_completed(); + + RTCD1.rtc->CRL &= ~(RTC_CRL_OWF | RTC_CRL_ALRF | RTC_CRL_SECF); + RTCD1.rtc->CRH = 0; + + /* Callback initially disabled.*/ + RTCD1.callback = NULL; + + rtcWB32SetSec(&RTCD1, last_rtc_cnt); + + extiEnableLine(WB32_RTC_ALARM_EXTI, EXTI_MODE_RISING_EDGE | EXTI_MODE_ACTION_INTERRUPT); + + /* IRQ vector permanently assigned to this driver.*/ + nvicEnableVector(WB32_RTCAlarm_NUMBER, WB32_RTCAlarm_IRQ_PRIORITY); +} + +/** + * @brief Set current time. + * @note Fractional part will be silently ignored. There is no possibility + * to change it on STM32F1xx platform. + * @note The function can be called from any context. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] timespec pointer to a @p RTCDateTime structure + * + * @notapi + */ +void rtc_lld_set_time(RTCDriver *rtcp, const RTCDateTime *timespec) { + time_t tv_sec = rtc_encode(timespec); + + rtcWB32SetSec(rtcp, tv_sec); +} + +/** + * @brief Get current time. + * @note The function can be called from any context. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] timespec pointer to a @p RTCDateTime structure + * + * @notapi + */ +void rtc_lld_get_time(RTCDriver *rtcp, RTCDateTime *timespec) { + uint32_t tv_sec, tv_msec; + + rtcWB32GetSecMsec(rtcp, &tv_sec, &tv_msec); + rtc_decode(tv_sec, tv_msec, timespec); +} + +/** + * @brief Set alarm time. + * + * @note Default value after BKP domain reset is 0xFFFFFFFF + * @note The function can be called from any context. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] alarm alarm identifier + * @param[in] alarmspec pointer to a @p RTCAlarm structure + * + * @notapi + */ +void rtc_lld_set_alarm(RTCDriver *rtcp, + rtcalarm_t alarm_number, + const RTCAlarm *alarmspec) { + syssts_t sts; + + (void)alarm_number; + + /* Entering a reentrant critical zone.*/ + sts = osalSysGetStatusAndLockX(); + + rtc_lld_set_prescaler(rtc_mod_flag); + + rtc_acquire_access(); + if (alarmspec != NULL) { + rtcp->rtc->ALRH = (uint16_t)(alarmspec->tv_sec >> 16); + rtcp->rtc->ALRL = (uint16_t)(alarmspec->tv_sec & 0xFFFF); + } else { + rtcp->rtc->ALRH = 0; + rtcp->rtc->ALRL = 0; + } + rtc_release_access(); + + /* Leaving a reentrant critical zone.*/ + osalSysRestoreStatusX(sts); +} + +/** + * @brief Get current alarm. + * @note If an alarm has not been set then the returned alarm specification + * is not meaningful. + * @note The function can be called from any context. + * @note Default value after BKP domain reset is 0xFFFFFFFF. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] alarm alarm identifier + * @param[out] alarmspec pointer to a @p RTCAlarm structure + * + * @notapi + */ +void rtc_lld_get_alarm(RTCDriver *rtcp, + rtcalarm_t alarm_number, + RTCAlarm *alarmspec) { + syssts_t sts; + + (void)alarm_number; + + /* Entering a reentrant critical zone.*/ + sts = osalSysGetStatusAndLockX(); + + /* Required because access to ALR.*/ + rtc_apb1_sync(); + + alarmspec->tv_sec = ((rtcp->rtc->ALRH << 16) + rtcp->rtc->ALRL); + + /* Leaving a reentrant critical zone.*/ + osalSysRestoreStatusX(sts); +} + +/** + * @brief Enables or disables RTC callbacks. + * @details This function enables or disables callbacks, use a @p NULL pointer + * in order to disable a callback. + * @note The function can be called from any context. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] callback callback function pointer or @p NULL + * + * @notapi + */ +void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback) { + syssts_t sts; + + /* Entering a reentrant critical zone.*/ + sts = osalSysGetStatusAndLockX(); + + if (callback != NULL) { + + /* IRQ sources enabled only after setting up the callback.*/ + rtcp->callback = callback; + + rtc_wait_write_completed(); + rtcp->rtc->CRL &= ~(RTC_CRL_OWF | RTC_CRL_ALRF | RTC_CRL_SECF); + rtcp->rtc->CRH = RTC_CRH_OWIE | RTC_CRH_ALRIE | RTC_CRH_SECIE; + } else { + rtc_wait_write_completed(); + rtcp->rtc->CRH = 0; + + /* Callback set to NULL only after disabling the IRQ sources.*/ + rtcp->callback = NULL; + } + + /* Leaving a reentrant critical zone.*/ + osalSysRestoreStatusX(sts); +} + +/** + * @brief Get seconds and (optionally) milliseconds from RTC. + * @note The function can be called from any context. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[out] tv_sec pointer to seconds value + * @param[out] tv_msec pointer to milliseconds value, set it + * to @p NULL if not needed + * + * @api + */ +void rtcWB32GetSecMsec(RTCDriver *rtcp, uint32_t *tv_sec, uint32_t *tv_msec) { + uint32_t time_frac; + syssts_t sts; + + osalDbgCheck((NULL != tv_sec) && (NULL != rtcp)); + + /* Entering a reentrant critical zone.*/ + sts = osalSysGetStatusAndLockX(); + + /* Required because access to CNT and DIV.*/ + rtc_apb1_sync(); + + /* wait for previous write accesses to complete.*/ + rtc_wait_write_completed(); + + /* Loops until two consecutive read returning the same value.*/ + do { + *tv_sec = ((uint32_t)(rtcp->rtc->CNTH) << 16) + rtcp->rtc->CNTL; + time_frac = (((uint32_t)rtcp->rtc->DIVH) << 16) + (uint32_t)rtcp->rtc->DIVL; + } while ((*tv_sec) != (((uint32_t)(rtcp->rtc->CNTH) << 16) + rtcp->rtc->CNTL)); + + /* Leaving a reentrant critical zone.*/ + osalSysRestoreStatusX(sts); + + if (NULL != tv_msec) + *tv_msec = (((uint32_t)WB32_RTCCLK - 1 - time_frac) * 1000) / WB32_RTCCLK; +} + +/** + * @brief Set seconds in RTC. + * @note The function can be called from any context. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] tv_sec seconds value + * + * @api + */ +void rtcWB32SetSec(RTCDriver *rtcp, uint32_t tv_sec) { + syssts_t sts; + + osalDbgCheck(NULL != rtcp); + + /* Entering a reentrant critical zone.*/ + sts = osalSysGetStatusAndLockX(); + + rtc_lld_set_prescaler(rtc_mod_flag); + + rtc_acquire_access(); + rtcp->rtc->CNTH = (uint16_t)(tv_sec >> 16); + rtcp->rtc->CNTL = (uint16_t)(tv_sec & 0xFFFF); + rtc_release_access(); + + /* Leaving a reentrant critical zone.*/ + osalSysRestoreStatusX(sts); +} + +#endif /* HAL_USE_RTC */ + +/** @} */ diff --git a/os/hal/ports/WB32/LLD/RTCv1/hal_rtc_lld.h b/os/hal/ports/WB32/LLD/RTCv1/hal_rtc_lld.h new file mode 100644 index 0000000000..75bc0222f7 --- /dev/null +++ b/os/hal/ports/WB32/LLD/RTCv1/hal_rtc_lld.h @@ -0,0 +1,164 @@ +/* + Copyright (C) 2023 Westberry Technology Corp., Ltd + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * @file RTCv1/hal_rtc_lld.h + * @brief WB32 RTC subsystem low level driver header. + * + * @addtogroup RTC + * @{ + */ + +#ifndef HAL_RTC_LLD_H +#define HAL_RTC_LLD_H + +#if HAL_USE_RTC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Implementation capabilities + */ +/** + * @brief This RTC implementation supports callbacks. + */ +#ifndef RTC_SUPPORTS_CALLBACKS +# define RTC_SUPPORTS_CALLBACKS TRUE +#endif + +/** + * @brief One alarm comparator available. + */ +#ifndef RTC_ALARMS +# define RTC_ALARMS 1 +#endif + +/** + * @brief Presence of a local persistent storage. + */ +#ifndef RTC_HAS_STORAGE +# define RTC_HAS_STORAGE FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/* + * RTC driver system settings. + */ +#ifndef WB32_RTC_IRQ_PRIORITY +# define WB32_RTC_IRQ_PRIORITY 15 +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if HAL_USE_RTC && !WB32_HAS_RTC +#error "RTC not present in the selected device" +#endif + +#if WB32_RTCCLK == 0 +#error "RTC clock not enabled" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of an RTC event. + */ +typedef enum { + RTC_EVENT_SECOND = 0, /** Triggered every second. */ + RTC_EVENT_ALARM = 1, /** Triggered on alarm. */ + RTC_EVENT_OVERFLOW = 2 /** Triggered on counter overflow. */ +} rtcevent_t; + +/** + * @brief Type of a generic RTC callback. + */ +typedef void (*rtccb_t)(RTCDriver *rtcp, rtcevent_t event); + +/** + * @brief Type of a structure representing an RTC alarm time stamp. + */ +typedef struct hal_rtc_alarm { + /** + * @brief Seconds since UNIX epoch. + */ + uint32_t tv_sec; +} RTCAlarm; + +/** + * @brief Implementation-specific @p RTCDriver fields. + */ +#define rtc_lld_driver_fields \ + /* Pointer to the RTC registers block.*/ \ + RTC_TypeDef *rtc; \ + /* Callback pointer.*/ \ + rtccb_t callback + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void rtc_lld_set_prescaler(bool rtc_mod); + void rtc_lld_init(void); + void rtclp_lld_init(void); + void rtc_lld_set_time(RTCDriver *rtcp, const RTCDateTime *timespec); + void rtc_lld_get_time(RTCDriver *rtcp, RTCDateTime *timespec); + void rtc_lld_set_alarm(RTCDriver *rtcp, + rtcalarm_t alarm_number, + const RTCAlarm *alarmspec); + void rtc_lld_get_alarm(RTCDriver *rtcp, + rtcalarm_t alarm_number, + RTCAlarm *alarmspec); + void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback); + void rtcWB32GetSecMsec(RTCDriver *rtcp, uint32_t *tv_sec, uint32_t *tv_msec); + void rtcWB32SetSec(RTCDriver *rtcp, uint32_t tv_sec); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_RTC */ + +#endif /* HAL_RTC_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/WB32/LLD/USBv1/hal_usb_lld.c b/os/hal/ports/WB32/LLD/USBv1/hal_usb_lld.c index 740f943887..6cfb9887bc 100644 --- a/os/hal/ports/WB32/LLD/USBv1/hal_usb_lld.c +++ b/os/hal/ports/WB32/LLD/USBv1/hal_usb_lld.c @@ -501,6 +501,16 @@ OSAL_IRQ_HANDLER(WB32_USB1_IRQ_VECTOR) { /* SOF handling.*/ if (IntrUSB & USB_INTRUSB_SOFIS) { + + /* SOF interrupt was used to detect resume of the USB bus after issuing a + remote wake up of the host, therefore we disable it again.*/ + if (USBD1.config->sof_cb == NULL) { + WB32_USB->INTRUSBE &= ~USB_INTRUSBE_SOFIE; + } + if (USBD1.state == USB_SUSPENDED) { + _usb_wakeup(&USBD1); + } + /* sof hook function */ _usb_isr_invoke_sof_cb(&USBD1); } @@ -517,38 +527,6 @@ OSAL_IRQ_HANDLER(WB32_USB1_IRQ_VECTOR) { } #endif -#if defined(WB32_USB1_DMA_IRQ_VECTOR) -/** - * @brief USB DMA interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(WB32_USB1_DMA_IRQ_VECTOR) { - - OSAL_IRQ_PROLOGUE(); - - /* USB1 DMA handling.*/ - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if defined(WB32_USBP1_WKUP_IRQ_VECTOR) -/** - * @brief USB WKUP interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(WB32_USBP1_WKUP_IRQ_VECTOR) { - - OSAL_IRQ_PROLOGUE(); - - /* USB1 DMA handling.*/ - - OSAL_IRQ_EPILOGUE(); -} -#endif - #endif /* WB32_USB_USE_USB1 */ /*===========================================================================*/ diff --git a/os/hal/ports/WB32/LLD/USBv1/hal_usb_lld.h b/os/hal/ports/WB32/LLD/USBv1/hal_usb_lld.h index 6c052ec4bb..c8ff67469d 100644 --- a/os/hal/ports/WB32/LLD/USBv1/hal_usb_lld.h +++ b/os/hal/ports/WB32/LLD/USBv1/hal_usb_lld.h @@ -469,10 +469,10 @@ struct USBDriver { */ #define usb_lld_wakeup_host(usbp) do { \ /* Remote Wakeup */ \ + WB32_USB->INTRUSBE |= USB_INTRUSBE_SOFIE; \ WB32_USB->POWER |= USB_POWER_RESUME; \ osalThreadSleepMilliseconds(WB32_USB_HOST_WAKEUP_DURATION); \ WB32_USB->POWER &= ~USB_POWER_RESUME; \ - _usb_wakeup(usbp); \ } while (false) /*===========================================================================*/ diff --git a/os/hal/ports/WB32/WB32F3G71xx/hal_lld.c b/os/hal/ports/WB32/WB32F3G71xx/hal_lld.c index e67e4dae35..d336c01f79 100644 --- a/os/hal/ports/WB32/WB32F3G71xx/hal_lld.c +++ b/os/hal/ports/WB32/WB32F3G71xx/hal_lld.c @@ -45,6 +45,27 @@ uint32_t SystemCoreClock = WB32_MAINCLK; /* Driver local functions. */ /*===========================================================================*/ +void wb32_set_main_clock_to_mhsi(void) { + + /* Unlocks write to ANCTL registers */ + PWR->ANAKEY1 = 0x03; + PWR->ANAKEY2 = 0x0C; + + /* Configure Flash prefetch, Cache and wait state */ + CACHE->CR = CACHE_CR_CHEEN | CACHE_CR_PREFEN_ON | CACHE_CR_LATENCY_0WS; + + /* Select FHSI as system clock source */ + RCC->MAINCLKSRC = RCC_MAINCLKSRC_MHSI; + RCC->MAINCLKUEN = RCC_MAINCLKUEN_ENA; + + /* PLL Disable */ + ANCTL->PLLENR = 0x00; + + /* Locks write to ANCTL registers */ + PWR->ANAKEY1 = 0x00; + PWR->ANAKEY2 = 0x00; +} + /*===========================================================================*/ /* Driver interrupt handlers. */ /*===========================================================================*/ @@ -254,6 +275,21 @@ void wb32_clock_init(void) { SetSysClock(); +#if WB32_LSI_ENABLED == TRUE + /* Unlocks write to ANCTL registers */ + PWR->ANAKEY1 = 0x03; + PWR->ANAKEY2 = 0x0C; + + /* LSI activation.*/ + ANCTL->LSIENR |= 0x1; + while ((ANCTL->LSISR & 0x1) == 0) + ; /* Waits until LSI is stable. */ + + /* Locks write to ANCTL registers */ + PWR->ANAKEY1 = 0x00; + PWR->ANAKEY2 = 0x00; +#endif + rccEnableAPB1(RCC_APB1ENR_BMX1EN); rccEnableAPB2(RCC_APB2ENR_BMX2EN); diff --git a/os/hal/ports/WB32/WB32F3G71xx/hal_lld.h b/os/hal/ports/WB32/WB32F3G71xx/hal_lld.h index f9b32529dd..6c84cd9a0c 100644 --- a/os/hal/ports/WB32/WB32F3G71xx/hal_lld.h +++ b/os/hal/ports/WB32/WB32F3G71xx/hal_lld.h @@ -35,6 +35,7 @@ #include "wb32_registry.h" #include "wb32_tim.h" #include "wb32_dma.h" +#include "wb32_exti.h" /*===========================================================================*/ /* Driver constants. */ @@ -59,6 +60,13 @@ * @{ */ +/** + * @brief LSI clock frequency. + */ +#ifndef WB32_LSICLK +#define WB32_LSICLK 40000 +#endif + /** * @brief Maximum HSE clock frequency. */ @@ -140,6 +148,16 @@ #define WB32_USBPRE_DIV3 (0x3U) /** @} */ +/** + * @name RCC_BDCR register bits definitions + * @{ + */ +#define WB32_RTCSEL_MASK (3U << 8) +#define WB32_RTCSEL_NOCLOCK (0U << 8) +#define WB32_RTCSEL_LSE (1U << 8) +#define WB32_RTCSEL_LSI (2U << 8) +#define WB32_RTCSEL_HSEDIV (3U << 8) +/** @} */ /*===========================================================================*/ /* Platform capabilities. */ @@ -229,6 +247,13 @@ #define WB32_PLLSRC WB32_PLLSRC_HSE #endif +/** + * @brief RTC clock source. + */ +#if !defined(WB32_RTCSEL) || defined(__DOXYGEN__) +#define WB32_RTCSEL WB32_RTCSEL_NOCLOCK +#endif + /** * @brief Crystal PLL pre-divider. * @note This setting has only effect if the PLL is selected as the @@ -338,6 +363,10 @@ #error "HSE not enabled, required by WB32_MAINCLKSRC and WB32_PLLSRC" #endif +#if WB32_RTCSEL == WB32_RTCSEL_HSEDIV +#error "HSE not enabled, required by WB32_RTCSEL" +#endif + #endif /* !WB32_HSE_ENABLED */ /* @@ -345,6 +374,11 @@ */ #if WB32_LSI_ENABLED #else /* !WB32_LSI_ENABLED */ + +#if HAL_USE_RTC && (WB32_RTCSEL == WB32_RTCSEL_LSI) +#error "LSI not enabled, required by WB32_RTCSEL" +#endif + #endif /* !WB32_LSI_ENABLED */ /* @@ -361,6 +395,11 @@ #endif #else /* !WB32_LSE_ENABLED */ + +#if WB32_RTCSEL == WB32_RTCSEL_LSE +#error "LSE not enabled, required by WB32_RTCSEL" +#endif + #endif /* !WB32_LSE_ENABLED */ /** @@ -466,6 +505,32 @@ #error "WB32_PCLK2 exceeding maximum frequency (WB32_PCLK2_MAX)" #endif +/** + * @brief RTC clock. + */ +#if (WB32_RTCSEL == WB32_RTCSEL_LSE) || defined(__DOXYGEN__) +#define WB32_RTCCLK WB32_LSECLK +#elif WB32_RTCSEL == WB32_RTCSEL_HSEDIV +#define WB32_RTCCLK (WB32_HSECLK / 128) +#elif WB32_RTCSEL == WB32_RTCSEL_NOCLOCK +#define WB32_RTCCLK 0 +#else +#error "invalid source selected for RTC clock" +#endif + +/** + * @brief RTC Low Power clock. + */ +#if (WB32_RTCLP_SEL == WB32_RTCSEL_LSE) || defined(__DOXYGEN__) +#define WB32_RTCLPCLK WB32_LSECLK +#elif WB32_RTCLP_SEL == WB32_RTCSEL_LSI +#define WB32_RTCLPCLK WB32_LSICLK +#elif WB32_RTCLP_SEL == WB32_RTCSEL_NOCLOCK +#define WB32_RTCLPCLK 0 +#else +#error "invalid source selected for RTC Low Power clock" +#endif + /** * @brief USB frequency. */ @@ -498,6 +563,26 @@ /* Driver macros. */ /*===========================================================================*/ +/** + * @name PWR interface specific BKP operations + * @{ + */ +/** + * @brief Enables the PWR interface. + * + * @api + */ +#define PWR_BackupAccessEnable() (PWR->CR0 |= 0x1U) + +/** + * @brief Disables PWR interface. + * + * @api + */ +#define PWR_BackupAccessDISABLE() (PWR->CR0 &= (~(0x1U))) + +/** @} */ + /*===========================================================================*/ /* External declarations. */ /*===========================================================================*/ @@ -512,6 +597,7 @@ extern "C" { #endif void hal_lld_init(void); void wb32_clock_init(void); + void wb32_set_main_clock_to_mhsi(void); #ifdef __cplusplus } #endif diff --git a/os/hal/ports/WB32/WB32F3G71xx/platform.mk b/os/hal/ports/WB32/WB32F3G71xx/platform.mk index 6ed97ed041..4edcf40a02 100644 --- a/os/hal/ports/WB32/WB32F3G71xx/platform.mk +++ b/os/hal/ports/WB32/WB32F3G71xx/platform.mk @@ -32,6 +32,8 @@ include $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/UARTv1/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/SPIv1/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/USBv1/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/ADCv1/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/RTCv1/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/EXTIv1/driver.mk # Shared variables ALLCSRC += $(PLATFORMSRC_CONTRIB) diff --git a/os/hal/ports/WB32/WB32F3G71xx/wb32_rcc.h b/os/hal/ports/WB32/WB32F3G71xx/wb32_rcc.h index d7038a40d6..06c7a1d034 100644 --- a/os/hal/ports/WB32/WB32F3G71xx/wb32_rcc.h +++ b/os/hal/ports/WB32/WB32F3G71xx/wb32_rcc.h @@ -31,6 +31,32 @@ /* Driver constants. */ /*===========================================================================*/ +/** @defgroup AHB_peripheral + * @{ + */ +#define RCC_AHBPeriph_IWDG ((uint32_t)0x00000004) +#define RCC_AHBPeriph_USB ((uint32_t)0x00000200) +#define RCC_AHBPeriph_ISO ((uint32_t)0x00000400) +#define RCC_AHBPeriph_FLASH ((uint32_t)0x00000800) +#define RCC_AHBPeriph_CACHE ((uint32_t)0x00001000) +#define RCC_AHBPeriph_SYS ((uint32_t)0x00002000) +#define RCC_AHBPeriph_DMAC1Bridge ((uint32_t)0x00004000) +#define RCC_AHBPeriph_DMAC2Bridge ((uint32_t)0x00008000) +#define RCC_AHBPeriph_CRC_SFM ((uint32_t)0x00010000) +#define RCC_AHBPeriph_BKP ((uint32_t)0x04000000) +/** + * @} + */ + +/** @defgroup LSE_Configuration + * @{ + */ +#define BKP_LSE_OFF ((uint32_t)0x00000000) +#define BKP_LSE_ON ((uint32_t)0x00000001) +#define BKP_LSE_Bypass ((uint32_t)0x00000004) +/** + * @} + */ /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ @@ -149,6 +175,30 @@ (void)RCC->AHBENR1; \ } +/** + * @brief Enables the clock of one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * + * @api + */ +#define rccEnableAHB2(mask) { \ + RCC->AHBENR2 |= (mask); \ + (void)RCC->AHBENR2; \ + } + +/** + * @brief Disables the clock of one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * + * @api + */ +#define rccDisableAHB2(mask) { \ + RCC->AHBENR2 &= ~(mask); \ + (void)RCC->AHBENR2; \ + } + /** * @brief Resets one or more peripheral on the AHB bus. * @@ -163,9 +213,6 @@ } /** @} */ - - - /** * @name EXTI peripherals specific RCC operations * @{ @@ -589,6 +636,40 @@ #define rccResetDMAC2() rccResetAPB2(RCC_APB2RSTR_DMAC2RST) /** @} */ +/** + * @name BKP peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the BKP peripheral clock. + * + * @api + */ +#define rccEnableBKP() do { \ + rccEnableAHB2(RCC_AHBPeriph_BKP >> 24); \ + } while (false) + +/** + * @brief Disables the BKP peripheral clock. + * + * @api + */ +#define rccDisableBKP() do { \ + rccDisableAHB2(RCC_AHBPeriph_BKP >> 24); \ + } while (false) + +/** + * @brief Resets the BKP peripheral. + * + * @api + */ +#define rccResetBKP() { \ + RCC->BDRSTR = (uint32_t)ENABLE; \ + RCC->BDRSTR = (uint32_t)DISABLE; \ + (void)RCC->BDRSTR; \ + } +/** @} */ + /*===========================================================================*/ /* External declarations. */ /*===========================================================================*/ diff --git a/os/hal/ports/WB32/WB32F3G71xx/wb32_registry.h b/os/hal/ports/WB32/WB32F3G71xx/wb32_registry.h index 155812719f..e18ab027e4 100644 --- a/os/hal/ports/WB32/WB32F3G71xx/wb32_registry.h +++ b/os/hal/ports/WB32/WB32F3G71xx/wb32_registry.h @@ -137,6 +137,8 @@ /* CRC attributes.*/ #define WB32_HAS_CRC TRUE +/* RTC attributes.*/ +#define WB32_RTC_ALARM_EXTI 17 /** @} */ #endif /* defined(WB32F3G71xx) */ diff --git a/os/hal/ports/WB32/WB32FQ95xx/hal_lld.c b/os/hal/ports/WB32/WB32FQ95xx/hal_lld.c index 62a3ca74e5..c3031258ca 100644 --- a/os/hal/ports/WB32/WB32FQ95xx/hal_lld.c +++ b/os/hal/ports/WB32/WB32FQ95xx/hal_lld.c @@ -45,6 +45,27 @@ uint32_t SystemCoreClock = WB32_MAINCLK; /* Driver local functions. */ /*===========================================================================*/ +void wb32_set_main_clock_to_mhsi(void) { + + /* Unlocks write to ANCTL registers */ + PWR->ANAKEY1 = 0x03; + PWR->ANAKEY2 = 0x0C; + + /* Configure Flash prefetch, Cache and wait state */ + CACHE->CR = CACHE_CR_CHEEN | CACHE_CR_PREFEN_ON | CACHE_CR_LATENCY_0WS; + + /* Select FHSI as system clock source */ + RCC->MAINCLKSRC = RCC_MAINCLKSRC_MHSI; + RCC->MAINCLKUEN = RCC_MAINCLKUEN_ENA; + + /* PLL Disable */ + ANCTL->PLLENR = 0x00; + + /* Locks write to ANCTL registers */ + PWR->ANAKEY1 = 0x00; + PWR->ANAKEY2 = 0x00; +} + /*===========================================================================*/ /* Driver interrupt handlers. */ /*===========================================================================*/ @@ -254,6 +275,21 @@ void wb32_clock_init(void) { SetSysClock(); +#if WB32_LSI_ENABLED == TRUE + /* Unlocks write to ANCTL registers */ + PWR->ANAKEY1 = 0x03; + PWR->ANAKEY2 = 0x0C; + + /* LSI activation.*/ + ANCTL->LSIENR |= 0x1; + while ((ANCTL->LSISR & 0x1) == 0) + ; /* Waits until LSI is stable. */ + + /* Locks write to ANCTL registers */ + PWR->ANAKEY1 = 0x00; + PWR->ANAKEY2 = 0x00; +#endif + rccEnableAPB1(RCC_APB1ENR_BMX1EN); rccEnableAPB2(RCC_APB2ENR_BMX2EN); diff --git a/os/hal/ports/WB32/WB32FQ95xx/hal_lld.h b/os/hal/ports/WB32/WB32FQ95xx/hal_lld.h index ebb0a1b232..269de4692c 100644 --- a/os/hal/ports/WB32/WB32FQ95xx/hal_lld.h +++ b/os/hal/ports/WB32/WB32FQ95xx/hal_lld.h @@ -35,6 +35,7 @@ #include "wb32_registry.h" #include "wb32_tim.h" #include "wb32_dma.h" +#include "wb32_exti.h" /*===========================================================================*/ /* Driver constants. */ @@ -59,6 +60,13 @@ * @{ */ +/** + * @brief LSI clock frequency. + */ +#ifndef WB32_LSICLK +#define WB32_LSICLK 40000 +#endif + /** * @brief Maximum HSE clock frequency. */ @@ -140,6 +148,16 @@ #define WB32_USBPRE_DIV3 (0x3U) /** @} */ +/** + * @name RCC_BDCR register bits definitions + * @{ + */ +#define WB32_RTCSEL_MASK (3U << 8) +#define WB32_RTCSEL_NOCLOCK (0U << 8) +#define WB32_RTCSEL_LSE (1U << 8) +#define WB32_RTCSEL_LSI (2U << 8) +#define WB32_RTCSEL_HSEDIV (3U << 8) +/** @} */ /*===========================================================================*/ /* Platform capabilities. */ @@ -229,6 +247,13 @@ #define WB32_PLLSRC WB32_PLLSRC_HSE #endif +/** + * @brief RTC clock source. + */ +#if !defined(WB32_RTCSEL) || defined(__DOXYGEN__) +#define WB32_RTCSEL WB32_RTCSEL_NOCLOCK +#endif + /** * @brief Crystal PLL pre-divider. * @note This setting has only effect if the PLL is selected as the @@ -338,6 +363,10 @@ #error "HSE not enabled, required by WB32_MAINCLKSRC and WB32_PLLSRC" #endif +#if WB32_RTCSEL == WB32_RTCSEL_HSEDIV +#error "HSE not enabled, required by WB32_RTCSEL" +#endif + #endif /* !WB32_HSE_ENABLED */ /* @@ -345,6 +374,11 @@ */ #if WB32_LSI_ENABLED #else /* !WB32_LSI_ENABLED */ + +#if HAL_USE_RTC && (WB32_RTCSEL == WB32_RTCSEL_LSI) +#error "LSI not enabled, required by WB32_RTCSEL" +#endif + #endif /* !WB32_LSI_ENABLED */ /* @@ -361,6 +395,11 @@ #endif #else /* !WB32_LSE_ENABLED */ + +#if WB32_RTCSEL == WB32_RTCSEL_LSE +#error "LSE not enabled, required by WB32_RTCSEL" +#endif + #endif /* !WB32_LSE_ENABLED */ /** @@ -466,6 +505,32 @@ #error "WB32_PCLK2 exceeding maximum frequency (WB32_PCLK2_MAX)" #endif +/** + * @brief RTC clock. + */ +#if (WB32_RTCSEL == WB32_RTCSEL_LSE) || defined(__DOXYGEN__) +#define WB32_RTCCLK WB32_LSECLK +#elif WB32_RTCSEL == WB32_RTCSEL_HSEDIV +#define WB32_RTCCLK (WB32_HSECLK / 128) +#elif WB32_RTCSEL == WB32_RTCSEL_NOCLOCK +#define WB32_RTCCLK 0 +#else +#error "invalid source selected for RTC clock" +#endif + +/** + * @brief RTC Low Power clock. + */ +#if (WB32_RTCLP_SEL == WB32_RTCSEL_LSE) || defined(__DOXYGEN__) +#define WB32_RTCLPCLK WB32_LSECLK +#elif WB32_RTCLP_SEL == WB32_RTCSEL_LSI +#define WB32_RTCLPCLK WB32_LSICLK +#elif WB32_RTCLP_SEL == WB32_RTCSEL_NOCLOCK +#define WB32_RTCLPCLK 0 +#else +#error "invalid source selected for RTC Low Power clock" +#endif + /** * @brief USB frequency. */ @@ -498,6 +563,26 @@ /* Driver macros. */ /*===========================================================================*/ +/** + * @name PWR interface specific BKP operations + * @{ + */ +/** + * @brief Enables the PWR interface. + * + * @api + */ +#define PWR_BackupAccessEnable() (PWR->CR0 |= 0x1U) + +/** + * @brief Disables PWR interface. + * + * @api + */ +#define PWR_BackupAccessDISABLE() (PWR->CR0 &= (~(0x1U))) + +/** @} */ + /*===========================================================================*/ /* External declarations. */ /*===========================================================================*/ @@ -512,6 +597,7 @@ extern "C" { #endif void hal_lld_init(void); void wb32_clock_init(void); + void wb32_set_main_clock_to_mhsi(void); #ifdef __cplusplus } #endif diff --git a/os/hal/ports/WB32/WB32FQ95xx/platform.mk b/os/hal/ports/WB32/WB32FQ95xx/platform.mk index 9f8a9afcc9..2b0f0589da 100644 --- a/os/hal/ports/WB32/WB32FQ95xx/platform.mk +++ b/os/hal/ports/WB32/WB32FQ95xx/platform.mk @@ -32,6 +32,8 @@ include $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/UARTv1/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/SPIv1/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/USBv1/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/ADCv1/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/RTCv1/driver.mk +include $(CHIBIOS_CONTRIB)/os/hal/ports/WB32/LLD/EXTIv1/driver.mk # Shared variables ALLCSRC += $(PLATFORMSRC_CONTRIB) diff --git a/os/hal/ports/WB32/WB32FQ95xx/wb32_rcc.h b/os/hal/ports/WB32/WB32FQ95xx/wb32_rcc.h index aea6c5af38..e3d7a115cd 100644 --- a/os/hal/ports/WB32/WB32FQ95xx/wb32_rcc.h +++ b/os/hal/ports/WB32/WB32FQ95xx/wb32_rcc.h @@ -31,6 +31,32 @@ /* Driver constants. */ /*===========================================================================*/ +/** @defgroup AHB_peripheral + * @{ + */ +#define RCC_AHBPeriph_IWDG ((uint32_t)0x00000004) +#define RCC_AHBPeriph_USB ((uint32_t)0x00000200) +#define RCC_AHBPeriph_ISO ((uint32_t)0x00000400) +#define RCC_AHBPeriph_FLASH ((uint32_t)0x00000800) +#define RCC_AHBPeriph_CACHE ((uint32_t)0x00001000) +#define RCC_AHBPeriph_SYS ((uint32_t)0x00002000) +#define RCC_AHBPeriph_DMAC1Bridge ((uint32_t)0x00004000) +#define RCC_AHBPeriph_DMAC2Bridge ((uint32_t)0x00008000) +#define RCC_AHBPeriph_CRC_SFM ((uint32_t)0x00010000) +#define RCC_AHBPeriph_BKP ((uint32_t)0x04000000) +/** + * @} + */ + +/** @defgroup LSE_Configuration + * @{ + */ +#define BKP_LSE_OFF ((uint32_t)0x00000000) +#define BKP_LSE_ON ((uint32_t)0x00000001) +#define BKP_LSE_Bypass ((uint32_t)0x00000004) +/** + * @} + */ /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ @@ -149,6 +175,30 @@ (void)RCC->AHBENR1; \ } +/** + * @brief Enables the clock of one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * + * @api + */ +#define rccEnableAHB2(mask) { \ + RCC->AHBENR2 |= (mask); \ + (void)RCC->AHBENR2; \ + } + +/** + * @brief Disables the clock of one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * + * @api + */ +#define rccDisableAHB2(mask) { \ + RCC->AHBENR2 &= ~(mask); \ + (void)RCC->AHBENR2; \ + } + /** * @brief Resets one or more peripheral on the AHB bus. * @@ -163,9 +213,6 @@ } /** @} */ - - - /** * @name EXTI peripherals specific RCC operations * @{ @@ -589,6 +636,40 @@ #define rccResetDMAC2() rccResetAPB2(RCC_APB2RSTR_DMAC2RST) /** @} */ +/** + * @name BKP peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the BKP peripheral clock. + * + * @api + */ +#define rccEnableBKP() do { \ + rccEnableAHB2(RCC_AHBPeriph_BKP >> 24); \ + } while (false) + +/** + * @brief Disables the BKP peripheral clock. + * + * @api + */ +#define rccDisableBKP() do { \ + rccDisableAHB2(RCC_AHBPeriph_BKP >> 24); \ + } while (false) + +/** + * @brief Resets the BKP peripheral. + * + * @api + */ +#define rccResetBKP() { \ + RCC->BDRSTR = (uint32_t)ENABLE; \ + RCC->BDRSTR = (uint32_t)DISABLE; \ + (void)RCC->BDRSTR; \ + } +/** @} */ + /*===========================================================================*/ /* External declarations. */ /*===========================================================================*/ diff --git a/os/hal/ports/WB32/WB32FQ95xx/wb32_registry.h b/os/hal/ports/WB32/WB32FQ95xx/wb32_registry.h index bbc1672634..ab8d897657 100644 --- a/os/hal/ports/WB32/WB32FQ95xx/wb32_registry.h +++ b/os/hal/ports/WB32/WB32FQ95xx/wb32_registry.h @@ -137,6 +137,8 @@ /* CRC attributes.*/ #define WB32_HAS_CRC TRUE +/* RTC attributes.*/ +#define WB32_RTC_ALARM_EXTI 17 /** @} */ #endif /* defined(WB32FQ95xx) */ From b53e3be3eab6fdeee667f815e1afda207875d578 Mon Sep 17 00:00:00 2001 From: Hansem Ro Date: Sat, 4 May 2024 17:47:53 -0700 Subject: [PATCH 05/19] HT32: Rename HT32F523x2 related ld scripts This renames HT32F523x2 linker scripts to prevent reuse for HT32F523x4 models due to differing flash page sizes (512 B vs 1024 B). --- .../ARMCMx/compilers/GCC/ld/{HT32F5234x.ld => HT32F52342.ld} | 4 ++-- .../ARMCMx/compilers/GCC/ld/{HT32F5235x.ld => HT32F52352.ld} | 4 ++-- .../ld/{HT32F523xx_rules_code.ld => HT32F523x2_rules_code.ld} | 0 3 files changed, 4 insertions(+), 4 deletions(-) rename os/common/startup/ARMCMx/compilers/GCC/ld/{HT32F5234x.ld => HT32F52342.ld} (98%) rename os/common/startup/ARMCMx/compilers/GCC/ld/{HT32F5235x.ld => HT32F52352.ld} (98%) rename os/common/startup/ARMCMx/compilers/GCC/ld/{HT32F523xx_rules_code.ld => HT32F523x2_rules_code.ld} (100%) diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/HT32F5234x.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/HT32F52342.ld similarity index 98% rename from os/common/startup/ARMCMx/compilers/GCC/ld/HT32F5234x.ld rename to os/common/startup/ARMCMx/compilers/GCC/ld/HT32F52342.ld index 7a85a29c69..9cdca3ed2d 100644 --- a/os/common/startup/ARMCMx/compilers/GCC/ld/HT32F5234x.ld +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/HT32F52342.ld @@ -23,7 +23,7 @@ /* - * HT32F5234x memory setup + * HT32F52342 memory setup */ MEMORY { @@ -93,7 +93,7 @@ REGION_ALIAS("HEAP_RAM", ram0); INCLUDE rules_stacks.ld /* Code rules inclusion.*/ -INCLUDE HT32F523xx_rules_code.ld +INCLUDE HT32F523x2_rules_code.ld /* Data rules inclusion.*/ INCLUDE rules_data.ld diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/HT32F5235x.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/HT32F52352.ld similarity index 98% rename from os/common/startup/ARMCMx/compilers/GCC/ld/HT32F5235x.ld rename to os/common/startup/ARMCMx/compilers/GCC/ld/HT32F52352.ld index 4cba8957f2..920fb770b6 100644 --- a/os/common/startup/ARMCMx/compilers/GCC/ld/HT32F5235x.ld +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/HT32F52352.ld @@ -23,7 +23,7 @@ /* - * HT32F5235x memory setup + * HT32F52352 memory setup */ MEMORY { @@ -93,7 +93,7 @@ REGION_ALIAS("HEAP_RAM", ram0); INCLUDE rules_stacks.ld /* Code rules inclusion.*/ -INCLUDE HT32F523xx_rules_code.ld +INCLUDE HT32F523x2_rules_code.ld /* Data rules inclusion.*/ INCLUDE rules_data.ld diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/HT32F523xx_rules_code.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/HT32F523x2_rules_code.ld similarity index 100% rename from os/common/startup/ARMCMx/compilers/GCC/ld/HT32F523xx_rules_code.ld rename to os/common/startup/ARMCMx/compilers/GCC/ld/HT32F523x2_rules_code.ld From 4f359bd741919aa98bf0e6c3046bb4d731d041e5 Mon Sep 17 00:00:00 2001 From: Hansem Ro Date: Sat, 4 May 2024 18:44:32 -0700 Subject: [PATCH 06/19] HT32: Add GCC/ld scripts for HT32F1655 and HT32F1656 --- .../ARMCMx/compilers/GCC/ld/HT32F1655.ld | 93 +++++++++++++++++++ .../ARMCMx/compilers/GCC/ld/HT32F1656.ld | 93 +++++++++++++++++++ 2 files changed, 186 insertions(+) create mode 100644 os/common/startup/ARMCMx/compilers/GCC/ld/HT32F1655.ld create mode 100644 os/common/startup/ARMCMx/compilers/GCC/ld/HT32F1656.ld diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/HT32F1655.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/HT32F1655.ld new file mode 100644 index 0000000000..ff32eecc29 --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/HT32F1655.ld @@ -0,0 +1,93 @@ +/* + * Copyright (C) Yaotian Feng, http://github.com/Codetector1374 + * codetector@codetector.cn + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + + +/* + * HT32F1655 memory setup + */ + +MEMORY { + flash0 : org = 0x00000000, len = 128k + flash1 : org = 0x00000000, len = 0 + flash2 : org = 0x00000000, len = 0 + flash3 : org = 0x00000000, len = 0 + flash4 : org = 0x00000000, len = 0 + flash5 : org = 0x00000000, len = 0 + flash6 : org = 0x00000000, len = 0 + flash7 : org = 0x00000000, len = 0 + ram0 : org = 0x20000000, len = 32k + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Generic rules inclusion.*/ +INCLUDE rules.ld diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/HT32F1656.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/HT32F1656.ld new file mode 100644 index 0000000000..3800ec827d --- /dev/null +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/HT32F1656.ld @@ -0,0 +1,93 @@ +/* + * Copyright (C) Yaotian Feng, http://github.com/Codetector1374 + * codetector@codetector.cn + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + + +/* + * HT32F1656 memory setup + */ + +MEMORY { + flash0 : org = 0x00000000, len = 255k + flash1 : org = 0x00000000, len = 0 + flash2 : org = 0x00000000, len = 0 + flash3 : org = 0x00000000, len = 0 + flash4 : org = 0x00000000, len = 0 + flash5 : org = 0x00000000, len = 0 + flash6 : org = 0x00000000, len = 0 + flash7 : org = 0x00000000, len = 0 + ram0 : org = 0x20000000, len = 32k + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Generic rules inclusion.*/ +INCLUDE rules.ld From b5157d3e8f6e3a3aa878f7292fb7828151d8bfc1 Mon Sep 17 00:00:00 2001 From: Hansem Ro Date: Sat, 4 May 2024 21:34:39 -0700 Subject: [PATCH 07/19] HT32: Add generic HT32F1653/4 board --- os/hal/boards/HT_HT32F1653_4/board.c | 99 ++++ os/hal/boards/HT_HT32F1653_4/board.h | 622 ++++++++++++++++++++++++++ os/hal/boards/HT_HT32F1653_4/board.mk | 9 + 3 files changed, 730 insertions(+) create mode 100644 os/hal/boards/HT_HT32F1653_4/board.c create mode 100644 os/hal/boards/HT_HT32F1653_4/board.h create mode 100644 os/hal/boards/HT_HT32F1653_4/board.mk diff --git a/os/hal/boards/HT_HT32F1653_4/board.c b/os/hal/boards/HT_HT32F1653_4/board.c new file mode 100644 index 0000000000..346d60c1d9 --- /dev/null +++ b/os/hal/boards/HT_HT32F1653_4/board.c @@ -0,0 +1,99 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = { + // GPIO A + .setup[0] = + { + .DIR = VAL_GPIOA_DIRCR, + .INE = VAL_GPIOA_INER, + .PU = VAL_GPIOA_PUR, + .PD = VAL_GPIOA_PDR, + .OD = VAL_GPIOA_ODR, + .DRV = VAL_GPIOA_DRVR, + .LOCK = 0x0000, + .OUT = 0x0000, + .CFG[0] = VAL_GPIOA_AFCFGR0, + .CFG[1] = VAL_GPIOA_AFCFGR1, + }, + // GPIO B + .setup[1] = + { + .DIR = VAL_GPIOB_DIRCR, + .INE = VAL_GPIOB_INER, + .PU = VAL_GPIOB_PUR, + .PD = VAL_GPIOB_PDR, + .OD = VAL_GPIOB_ODR, + .DRV = VAL_GPIOB_DRVR, + .LOCK = 0x0000, + .OUT = 0x0000, + .CFG[0] = VAL_GPIOB_AFCFGR0, + .CFG[1] = VAL_GPIOB_AFCFGR1, + }, + // GPIO C + .setup[2] = + { + .DIR = VAL_GPIOC_DIRCR, + .INE = VAL_GPIOC_INER, + .PU = VAL_GPIOC_PUR, + .PD = VAL_GPIOC_PDR, + .OD = VAL_GPIOC_ODR, + .DRV = VAL_GPIOC_DRVR, + .LOCK = 0x0000, + .OUT = 0x0000, + .CFG[0] = VAL_GPIOC_AFCFGR0, + .CFG[1] = VAL_GPIOC_AFCFGR1, + }, + // GPIO D + .setup[3] = + { + .DIR = VAL_GPIOD_DIRCR, + .INE = VAL_GPIOD_INER, + .PU = VAL_GPIOD_PUR, + .PD = VAL_GPIOD_PDR, + .OD = VAL_GPIOD_ODR, + .DRV = VAL_GPIOD_DRVR, + .LOCK = 0x0000, + .OUT = 0x0000, + .CFG[0] = VAL_GPIOD_AFCFGR0, + .CFG[1] = VAL_GPIOD_AFCFGR1, + }, + .ESSR[0] = VAL_ESSR0, + .ESSR[1] = VAL_ESSR1, +}; +#endif + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + ht32_clock_init(); +} + +/* + * Board-specific initialization code. + */ +void boardInit(void) {} diff --git a/os/hal/boards/HT_HT32F1653_4/board.h b/os/hal/boards/HT_HT32F1653_4/board.h new file mode 100644 index 0000000000..29f6e3cd7f --- /dev/null +++ b/os/hal/boards/HT_HT32F1653_4/board.h @@ -0,0 +1,622 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#pragma once + +/* + * Setup for a Generic HT32F1653/4 board. + */ + +/* + * Board identifier. + */ +#define BOARD_HT32_F1653_4 +#define BOARD_NAME "Generic HT32F1653/4 Board" + +/* + * Board frequencies. + */ +#define HT32_LSECLK 32768 +#define HT32_HSECLK 8000000 + +/* + * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h. + */ +#define HT32F1654 + +/* + * IO pins assignments. + */ +#define GPIOA_PIN0 0U +#define GPIOA_PIN1 1U +#define GPIOA_PIN2 2U +#define GPIOA_PIN3 3U +#define GPIOA_PIN4 4U +#define GPIOA_PIN5 5U +#define GPIOA_PIN6 6U +#define GPIOA_PIN7 7U +#define GPIOA_PIN8 8U +#define GPIOA_PIN9 9U +#define GPIOA_PIN10 10U +#define GPIOA_PIN11 11U +#define GPIOA_PIN12 12U +#define GPIOA_PIN13 13U +#define GPIOA_PIN14 14U +#define GPIOA_PIN15 15U + +#define GPIOB_PIN0 0U +#define GPIOB_PIN1 1U +#define GPIOB_PIN2 2U +#define GPIOB_PIN3 3U +#define GPIOB_PIN4 4U +#define GPIOB_PIN5 5U +#define GPIOB_PIN6 6U +#define GPIOB_PIN7 7U +#define GPIOB_PIN8 8U +#define GPIOB_PIN9 9U +#define GPIOB_PIN10 10U +#define GPIOB_PIN11 11U +#define GPIOB_PIN12 12U +#define GPIOB_PIN13 13U +#define GPIOB_PIN14 14U +#define GPIOB_PIN15 15U + +#define GPIOC_PIN0 0U +#define GPIOC_PIN1 1U +#define GPIOC_PIN2 2U +#define GPIOC_PIN3 3U +#define GPIOC_PIN4 4U +#define GPIOC_PIN5 5U +#define GPIOC_PIN6 6U +#define GPIOC_PIN7 7U +#define GPIOC_PIN8 8U +#define GPIOC_PIN9 9U +#define GPIOC_PIN10 10U +#define GPIOC_PIN11 11U +#define GPIOC_PIN12 12U +#define GPIOC_PIN13 13U +#define GPIOC_PIN14 14U +#define GPIOC_PIN15 15U + +#define GPIOD_PIN0 0U +#define GPIOD_PIN1 1U +#define GPIOD_PIN2 2U +#define GPIOD_PIN3 3U +#define GPIOD_PIN4 4U +#define GPIOD_PIN5 5U +#define GPIOD_PIN6 6U +#define GPIOD_PIN7 7U +#define GPIOD_PIN8 8U +#define GPIOD_PIN9 9U +#define GPIOD_PIN10 10U +#define GPIOD_PIN11 11U +#define GPIOD_PIN12 12U +#define GPIOD_PIN13 13U +#define GPIOD_PIN14 14U +#define GPIOD_PIN15 15U + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the HT32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << (n)) +#define PIN_MODE_OUTPUT(n) (1U << (n)) +#define PIN_INPUT_DISABLE(n) (0U << (n)) +#define PIN_INPUT_ENABLE(n) (1U << (n)) +#define PIN_PULLUP_DISABLE(n) (0U << (n)) +#define PIN_PULLUP_ENABLE(n) (1U << (n)) +#define PIN_PULLDOWN_DISABLE(n) (0U << (n)) +#define PIN_PULLDOWN_ENABLE(n) (1U << (n)) +#define PIN_ODR_PUSHPULL(n) (0U << (n)) +#define PIN_ODR_OPENDRAIN(n) (1U << (n)) +#define PIN_DRVR_4MA(n) (0U << (n)) +#define PIN_DRVR_8MA(n) (0U << (n)) +#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) + +/* + * Port A setup. + * Everything GPIO input with pull-up except: + * PA12 - AF0 - SWCLK + * PA13 - AF0 - SWDIO + */ +#define VAL_GPIOA_DIRCR (PIN_MODE_INPUT(GPIOA_PIN0) | \ + PIN_MODE_INPUT(GPIOA_PIN1) | \ + PIN_MODE_INPUT(GPIOA_PIN2) | \ + PIN_MODE_INPUT(GPIOA_PIN3) | \ + PIN_MODE_INPUT(GPIOA_PIN4) | \ + PIN_MODE_INPUT(GPIOA_PIN5) | \ + PIN_MODE_INPUT(GPIOA_PIN6) | \ + PIN_MODE_INPUT(GPIOA_PIN7) | \ + PIN_MODE_INPUT(GPIOA_PIN8) | \ + PIN_MODE_INPUT(GPIOA_PIN9) | \ + PIN_MODE_INPUT(GPIOA_PIN10) | \ + PIN_MODE_INPUT(GPIOA_PIN11) | \ + PIN_MODE_INPUT(GPIOA_PIN12) | \ + PIN_MODE_INPUT(GPIOA_PIN13) | \ + PIN_MODE_INPUT(GPIOA_PIN14) | \ + PIN_MODE_INPUT(GPIOA_PIN15)) +#define VAL_GPIOA_INER (PIN_INPUT_ENABLE(GPIOA_PIN0) | \ + PIN_INPUT_ENABLE(GPIOA_PIN1) | \ + PIN_INPUT_ENABLE(GPIOA_PIN2) | \ + PIN_INPUT_ENABLE(GPIOA_PIN3) | \ + PIN_INPUT_ENABLE(GPIOA_PIN4) | \ + PIN_INPUT_ENABLE(GPIOA_PIN5) | \ + PIN_INPUT_ENABLE(GPIOA_PIN6) | \ + PIN_INPUT_ENABLE(GPIOA_PIN7) | \ + PIN_INPUT_ENABLE(GPIOA_PIN8) | \ + PIN_INPUT_ENABLE(GPIOA_PIN9) | \ + PIN_INPUT_ENABLE(GPIOA_PIN10) | \ + PIN_INPUT_ENABLE(GPIOA_PIN11) | \ + PIN_INPUT_DISABLE(GPIOA_PIN12) | \ + PIN_INPUT_DISABLE(GPIOA_PIN13) | \ + PIN_INPUT_ENABLE(GPIOA_PIN14) | \ + PIN_INPUT_ENABLE(GPIOA_PIN15)) +#define VAL_GPIOA_PUR (PIN_PULLUP_ENABLE(GPIOA_PIN0) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN1) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN2) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN3) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN4) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN5) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN6) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN7) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN8) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN9) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN10) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN11) | \ + PIN_PULLUP_DISABLE(GPIOA_PIN12) | \ + PIN_PULLUP_DISABLE(GPIOA_PIN13) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN14) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN15)) +#define VAL_GPIOA_PDR (PIN_PULLDOWN_DISABLE(GPIOA_PIN0) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN1) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN2) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN3) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN4) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN5) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN6) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN7) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN8) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN9) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN10) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN11) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN12) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN13) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN14) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN15)) +#define VAL_GPIOA_ODR (PIN_ODR_PUSHPULL(GPIOA_PIN0) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN1) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN2) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN3) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN4) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN5) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN6) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN7) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN8) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN9) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN10) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN11) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN12) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN13) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN14) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN15)) +#define VAL_GPIOA_DRVR (PIN_DRVR_4MA(GPIOA_PIN0) | \ + PIN_DRVR_4MA(GPIOA_PIN1) | \ + PIN_DRVR_4MA(GPIOA_PIN2) | \ + PIN_DRVR_4MA(GPIOA_PIN3) | \ + PIN_DRVR_4MA(GPIOA_PIN4) | \ + PIN_DRVR_4MA(GPIOA_PIN5) | \ + PIN_DRVR_4MA(GPIOA_PIN6) | \ + PIN_DRVR_4MA(GPIOA_PIN7) | \ + PIN_DRVR_4MA(GPIOA_PIN8) | \ + PIN_DRVR_4MA(GPIOA_PIN9) | \ + PIN_DRVR_4MA(GPIOA_PIN10) | \ + PIN_DRVR_4MA(GPIOA_PIN11) | \ + PIN_DRVR_4MA(GPIOA_PIN12) | \ + PIN_DRVR_4MA(GPIOA_PIN13) | \ + PIN_DRVR_4MA(GPIOA_PIN14) | \ + PIN_DRVR_4MA(GPIOA_PIN15)) +#define VAL_GPIOA_AFCFGR0 (PIN_AFIO_AF(GPIOA_PIN0, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN1, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN2, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN3, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN4, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN5, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN6, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN7, AFIO_GPIO)) +#define VAL_GPIOA_AFCFGR1 (PIN_AFIO_AF(GPIOA_PIN0, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN8, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN9, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN10, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN11, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN12, AFIO_DEFAULT) | \ + PIN_AFIO_AF(GPIOA_PIN13, AFIO_DEFAULT) | \ + PIN_AFIO_AF(GPIOA_PIN14, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN15, AFIO_GPIO)) + +/* + * Port B setup. + * Everything GPIO input with pull-up except: + * PB12 - AF0 - USBD- + * PB13 - AF0 - USBD+ + * PB14 - AF0 - XTALIN + * PB15 - AF0 - XTALOUT + */ +#define VAL_GPIOB_DIRCR (PIN_MODE_INPUT(GPIOB_PIN0) | \ + PIN_MODE_INPUT(GPIOB_PIN1) | \ + PIN_MODE_INPUT(GPIOB_PIN2) | \ + PIN_MODE_INPUT(GPIOB_PIN3) | \ + PIN_MODE_INPUT(GPIOB_PIN4) | \ + PIN_MODE_INPUT(GPIOB_PIN5) | \ + PIN_MODE_INPUT(GPIOB_PIN6) | \ + PIN_MODE_INPUT(GPIOB_PIN7) | \ + PIN_MODE_INPUT(GPIOB_PIN8) | \ + PIN_MODE_INPUT(GPIOB_PIN9) | \ + PIN_MODE_INPUT(GPIOB_PIN10) | \ + PIN_MODE_INPUT(GPIOB_PIN11) | \ + PIN_MODE_INPUT(GPIOB_PIN12) | \ + PIN_MODE_INPUT(GPIOB_PIN13) | \ + PIN_MODE_INPUT(GPIOB_PIN14) | \ + PIN_MODE_INPUT(GPIOB_PIN15)) +#define VAL_GPIOB_INER (PIN_INPUT_ENABLE(GPIOB_PIN0) | \ + PIN_INPUT_ENABLE(GPIOB_PIN1) | \ + PIN_INPUT_ENABLE(GPIOB_PIN2) | \ + PIN_INPUT_ENABLE(GPIOB_PIN3) | \ + PIN_INPUT_ENABLE(GPIOB_PIN4) | \ + PIN_INPUT_ENABLE(GPIOB_PIN5) | \ + PIN_INPUT_ENABLE(GPIOB_PIN6) | \ + PIN_INPUT_ENABLE(GPIOB_PIN7) | \ + PIN_INPUT_ENABLE(GPIOB_PIN8) | \ + PIN_INPUT_ENABLE(GPIOB_PIN9) | \ + PIN_INPUT_ENABLE(GPIOB_PIN10) | \ + PIN_INPUT_ENABLE(GPIOB_PIN11) | \ + PIN_INPUT_DISABLE(GPIOB_PIN12) | \ + PIN_INPUT_DISABLE(GPIOB_PIN13) | \ + PIN_INPUT_DISABLE(GPIOB_PIN14) | \ + PIN_INPUT_DISABLE(GPIOB_PIN15)) +#define VAL_GPIOB_PUR (PIN_PULLUP_ENABLE(GPIOB_PIN0) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN1) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN2) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN3) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN4) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN5) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN6) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN7) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN8) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN9) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN10) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN11) | \ + PIN_PULLUP_DISABLE(GPIOB_PIN12) | \ + PIN_PULLUP_DISABLE(GPIOB_PIN13) | \ + PIN_PULLUP_DISABLE(GPIOB_PIN14) | \ + PIN_PULLUP_DISABLE(GPIOB_PIN15)) +#define VAL_GPIOB_PDR (PIN_PULLDOWN_DISABLE(GPIOB_PIN0) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN1) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN2) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN3) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN4) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN5) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN6) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN7) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN8) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN9) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN10) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN11) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN12) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN13) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN14) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN15)) +#define VAL_GPIOB_ODR (PIN_ODR_PUSHPULL(GPIOB_PIN0) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN1) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN2) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN3) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN4) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN5) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN6) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN7) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN8) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN9) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN10) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN11) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN12) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN13) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN14) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN15)) +#define VAL_GPIOB_DRVR (PIN_DRVR_4MA(GPIOB_PIN0) | \ + PIN_DRVR_4MA(GPIOB_PIN1) | \ + PIN_DRVR_4MA(GPIOB_PIN2) | \ + PIN_DRVR_4MA(GPIOB_PIN3) | \ + PIN_DRVR_4MA(GPIOB_PIN4) | \ + PIN_DRVR_4MA(GPIOB_PIN5) | \ + PIN_DRVR_4MA(GPIOB_PIN6) | \ + PIN_DRVR_4MA(GPIOB_PIN7) | \ + PIN_DRVR_4MA(GPIOB_PIN8) | \ + PIN_DRVR_4MA(GPIOB_PIN9) | \ + PIN_DRVR_4MA(GPIOB_PIN10) | \ + PIN_DRVR_4MA(GPIOB_PIN11) | \ + PIN_DRVR_4MA(GPIOB_PIN12) | \ + PIN_DRVR_4MA(GPIOB_PIN13) | \ + PIN_DRVR_4MA(GPIOB_PIN14) | \ + PIN_DRVR_4MA(GPIOB_PIN15)) +#define VAL_GPIOB_AFCFGR0 (PIN_AFIO_AF(GPIOB_PIN0, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN1, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN2, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN3, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN4, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN5, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN6, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN7, AFIO_GPIO)) +#define VAL_GPIOB_AFCFGR1 (PIN_AFIO_AF(GPIOB_PIN0, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN8, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN9, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN10, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN11, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN12, AFIO_DEFAULT) | \ + PIN_AFIO_AF(GPIOB_PIN13, AFIO_DEFAULT) | \ + PIN_AFIO_AF(GPIOB_PIN14, AFIO_DEFAULT) | \ + PIN_AFIO_AF(GPIOB_PIN15, AFIO_DEFAULT)) + +/* + * Port C setup. + * Everything GPIO input with pull-up + */ +#define VAL_GPIOC_DIRCR (PIN_MODE_INPUT(GPIOC_PIN0) | \ + PIN_MODE_INPUT(GPIOC_PIN1) | \ + PIN_MODE_INPUT(GPIOC_PIN2) | \ + PIN_MODE_INPUT(GPIOC_PIN3) | \ + PIN_MODE_INPUT(GPIOC_PIN4) | \ + PIN_MODE_INPUT(GPIOC_PIN5) | \ + PIN_MODE_INPUT(GPIOC_PIN6) | \ + PIN_MODE_INPUT(GPIOC_PIN7) | \ + PIN_MODE_INPUT(GPIOC_PIN8) | \ + PIN_MODE_INPUT(GPIOC_PIN9) | \ + PIN_MODE_INPUT(GPIOC_PIN10) | \ + PIN_MODE_INPUT(GPIOC_PIN11) | \ + PIN_MODE_INPUT(GPIOC_PIN12) | \ + PIN_MODE_INPUT(GPIOC_PIN13) | \ + PIN_MODE_INPUT(GPIOC_PIN14) | \ + PIN_MODE_INPUT(GPIOC_PIN15)) +#define VAL_GPIOC_INER (PIN_INPUT_ENABLE(GPIOC_PIN0) | \ + PIN_INPUT_ENABLE(GPIOC_PIN1) | \ + PIN_INPUT_ENABLE(GPIOC_PIN2) | \ + PIN_INPUT_ENABLE(GPIOC_PIN3) | \ + PIN_INPUT_ENABLE(GPIOC_PIN4) | \ + PIN_INPUT_ENABLE(GPIOC_PIN5) | \ + PIN_INPUT_ENABLE(GPIOC_PIN6) | \ + PIN_INPUT_ENABLE(GPIOC_PIN7) | \ + PIN_INPUT_ENABLE(GPIOC_PIN8) | \ + PIN_INPUT_ENABLE(GPIOC_PIN9) | \ + PIN_INPUT_ENABLE(GPIOC_PIN10) | \ + PIN_INPUT_ENABLE(GPIOC_PIN11) | \ + PIN_INPUT_ENABLE(GPIOC_PIN12) | \ + PIN_INPUT_ENABLE(GPIOC_PIN13) | \ + PIN_INPUT_ENABLE(GPIOC_PIN14) | \ + PIN_INPUT_ENABLE(GPIOC_PIN15)) +#define VAL_GPIOC_PUR (PIN_PULLUP_ENABLE(GPIOC_PIN0) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN1) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN2) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN3) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN4) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN5) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN6) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN7) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN8) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN9) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN10) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN11) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN12) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN13) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN14) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN15)) +#define VAL_GPIOC_PDR (PIN_PULLDOWN_DISABLE(GPIOC_PIN0) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN1) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN2) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN3) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN4) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN5) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN6) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN7) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN8) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN9) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN10) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN11) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN12) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN13) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN14) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN15)) +#define VAL_GPIOC_ODR (PIN_ODR_PUSHPULL(GPIOC_PIN0) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN1) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN2) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN3) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN4) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN5) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN6) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN7) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN8) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN9) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN10) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN11) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN12) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN13) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN14) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN15)) +#define VAL_GPIOC_DRVR (PIN_DRVR_4MA(GPIOC_PIN0) | \ + PIN_DRVR_4MA(GPIOC_PIN1) | \ + PIN_DRVR_4MA(GPIOC_PIN2) | \ + PIN_DRVR_4MA(GPIOC_PIN3) | \ + PIN_DRVR_4MA(GPIOC_PIN4) | \ + PIN_DRVR_4MA(GPIOC_PIN5) | \ + PIN_DRVR_4MA(GPIOC_PIN6) | \ + PIN_DRVR_4MA(GPIOC_PIN7) | \ + PIN_DRVR_4MA(GPIOC_PIN8) | \ + PIN_DRVR_4MA(GPIOC_PIN9) | \ + PIN_DRVR_4MA(GPIOC_PIN10) | \ + PIN_DRVR_4MA(GPIOC_PIN11) | \ + PIN_DRVR_4MA(GPIOC_PIN12) | \ + PIN_DRVR_4MA(GPIOC_PIN13) | \ + PIN_DRVR_4MA(GPIOC_PIN14) | \ + PIN_DRVR_4MA(GPIOC_PIN15)) +#define VAL_GPIOC_AFCFGR0 (PIN_AFIO_AF(GPIOC_PIN0, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN1, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN2, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN3, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN4, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN5, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN6, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN7, AFIO_GPIO)) +#define VAL_GPIOC_AFCFGR1 (PIN_AFIO_AF(GPIOC_PIN0, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN8, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN9, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN10, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN11, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN12, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN13, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN14, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN15, AFIO_GPIO)) + +/* + * Port D setup. + * Everything GPIO input with pull-up + */ +#define VAL_GPIOD_DIRCR (PIN_MODE_INPUT(GPIOD_PIN0) | \ + PIN_MODE_INPUT(GPIOD_PIN1) | \ + PIN_MODE_INPUT(GPIOD_PIN2) | \ + PIN_MODE_INPUT(GPIOD_PIN3) | \ + PIN_MODE_INPUT(GPIOD_PIN4) | \ + PIN_MODE_INPUT(GPIOD_PIN5) | \ + PIN_MODE_INPUT(GPIOD_PIN6) | \ + PIN_MODE_INPUT(GPIOD_PIN7) | \ + PIN_MODE_INPUT(GPIOD_PIN8) | \ + PIN_MODE_INPUT(GPIOD_PIN9) | \ + PIN_MODE_INPUT(GPIOD_PIN10) | \ + PIN_MODE_INPUT(GPIOD_PIN11) | \ + PIN_MODE_INPUT(GPIOD_PIN12) | \ + PIN_MODE_INPUT(GPIOD_PIN13) | \ + PIN_MODE_INPUT(GPIOD_PIN14) | \ + PIN_MODE_INPUT(GPIOD_PIN15)) +#define VAL_GPIOD_INER (PIN_INPUT_ENABLE(GPIOD_PIN0) | \ + PIN_INPUT_ENABLE(GPIOD_PIN1) | \ + PIN_INPUT_ENABLE(GPIOD_PIN2) | \ + PIN_INPUT_ENABLE(GPIOD_PIN3) | \ + PIN_INPUT_ENABLE(GPIOD_PIN4) | \ + PIN_INPUT_ENABLE(GPIOD_PIN5) | \ + PIN_INPUT_ENABLE(GPIOD_PIN6) | \ + PIN_INPUT_ENABLE(GPIOD_PIN7) | \ + PIN_INPUT_ENABLE(GPIOD_PIN8) | \ + PIN_INPUT_ENABLE(GPIOD_PIN9) | \ + PIN_INPUT_ENABLE(GPIOD_PIN10) | \ + PIN_INPUT_ENABLE(GPIOD_PIN11) | \ + PIN_INPUT_ENABLE(GPIOD_PIN12) | \ + PIN_INPUT_ENABLE(GPIOD_PIN13) | \ + PIN_INPUT_ENABLE(GPIOD_PIN14) | \ + PIN_INPUT_ENABLE(GPIOD_PIN15)) +#define VAL_GPIOD_PUR (PIN_PULLUP_ENABLE(GPIOD_PIN0) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN1) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN2) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN3) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN4) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN5) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN6) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN7) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN8) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN9) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN10) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN11) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN12) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN13) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN14) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN15)) +#define VAL_GPIOD_PDR (PIN_PULLDOWN_DISABLE(GPIOD_PIN0) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN1) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN2) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN3) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN4) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN5) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN6) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN7) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN8) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN9) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN10) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN11) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN12) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN13) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN14) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN15)) +#define VAL_GPIOD_ODR (PIN_ODR_PUSHPULL(GPIOD_PIN0) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN1) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN2) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN3) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN4) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN5) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN6) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN7) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN8) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN9) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN10) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN11) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN12) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN13) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN14) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN15)) +#define VAL_GPIOD_DRVR (PIN_DRVR_4MA(GPIOD_PIN0) | \ + PIN_DRVR_4MA(GPIOD_PIN1) | \ + PIN_DRVR_4MA(GPIOD_PIN2) | \ + PIN_DRVR_4MA(GPIOD_PIN3) | \ + PIN_DRVR_4MA(GPIOD_PIN4) | \ + PIN_DRVR_4MA(GPIOD_PIN5) | \ + PIN_DRVR_4MA(GPIOD_PIN6) | \ + PIN_DRVR_4MA(GPIOD_PIN7) | \ + PIN_DRVR_4MA(GPIOD_PIN8) | \ + PIN_DRVR_4MA(GPIOD_PIN9) | \ + PIN_DRVR_4MA(GPIOD_PIN10) | \ + PIN_DRVR_4MA(GPIOD_PIN11) | \ + PIN_DRVR_4MA(GPIOD_PIN12) | \ + PIN_DRVR_4MA(GPIOD_PIN13) | \ + PIN_DRVR_4MA(GPIOD_PIN14) | \ + PIN_DRVR_4MA(GPIOD_PIN15)) +#define VAL_GPIOD_AFCFGR0 (PIN_AFIO_AF(GPIOD_PIN0, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN1, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN2, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN3, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN4, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN5, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN6, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN7, AFIO_GPIO)) +#define VAL_GPIOD_AFCFGR1 (PIN_AFIO_AF(GPIOD_PIN0, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN8, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN9, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN10, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN11, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN12, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN13, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN14, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN15, AFIO_GPIO)) + +/* + * EXTI setup. + */ +#define VAL_ESSR0 0x00000000 +#define VAL_ESSR1 0x00000000 + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ diff --git a/os/hal/boards/HT_HT32F1653_4/board.mk b/os/hal/boards/HT_HT32F1653_4/board.mk new file mode 100644 index 0000000000..b8cfd11754 --- /dev/null +++ b/os/hal/boards/HT_HT32F1653_4/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files. +BOARDSRC = $(CHIBIOS_CONTRIB)/os/hal/boards/HT_HT32F1653_4/board.c + +# Required include directories +BOARDINC = $(CHIBIOS_CONTRIB)/os/hal/boards/HT_HT32F1653_4 + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC) From 1018516872d22080b30c678e1d6914d805eb0e4b Mon Sep 17 00:00:00 2001 From: Hansem Ro Date: Sat, 4 May 2024 21:34:50 -0700 Subject: [PATCH 08/19] HT32: Add generic HT32F52342/52 board --- os/hal/boards/HT_HT32F52342_52/board.c | 99 ++++ os/hal/boards/HT_HT32F52342_52/board.h | 630 ++++++++++++++++++++++++ os/hal/boards/HT_HT32F52342_52/board.mk | 9 + 3 files changed, 738 insertions(+) create mode 100644 os/hal/boards/HT_HT32F52342_52/board.c create mode 100644 os/hal/boards/HT_HT32F52342_52/board.h create mode 100644 os/hal/boards/HT_HT32F52342_52/board.mk diff --git a/os/hal/boards/HT_HT32F52342_52/board.c b/os/hal/boards/HT_HT32F52342_52/board.c new file mode 100644 index 0000000000..7c162e3eb4 --- /dev/null +++ b/os/hal/boards/HT_HT32F52342_52/board.c @@ -0,0 +1,99 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = { + // GPIO A + .setup[0] = + { + .DIR = VAL_GPIOA_DIRCR, + .INE = VAL_GPIOA_INER, + .PU = VAL_GPIOA_PUR, + .PD = VAL_GPIOA_PDR, + .OD = VAL_GPIOA_ODR, + .DRV = VAL_GPIOA_DRVR, + .LOCK = 0x0000, + .OUT = 0x0000, + .CFG[0] = VAL_GPIOA_AFCFGR0, + .CFG[1] = VAL_GPIOA_AFCFGR1, + }, + // GPIO B + .setup[1] = + { + .DIR = VAL_GPIOB_DIRCR, + .INE = VAL_GPIOB_INER, + .PU = VAL_GPIOB_PUR, + .PD = VAL_GPIOB_PDR, + .OD = VAL_GPIOB_ODR, + .DRV = VAL_GPIOB_DRVR, + .LOCK = 0x0000, + .OUT = 0x0000, + .CFG[0] = VAL_GPIOB_AFCFGR0, + .CFG[1] = VAL_GPIOB_AFCFGR1, + }, + // GPIO C + .setup[2] = + { + .DIR = VAL_GPIOC_DIRCR, + .INE = VAL_GPIOC_INER, + .PU = VAL_GPIOC_PUR, + .PD = VAL_GPIOC_PDR, + .OD = VAL_GPIOC_ODR, + .DRV = VAL_GPIOC_DRVR, + .LOCK = 0x0000, + .OUT = 0x0000, + .CFG[0] = VAL_GPIOC_AFCFGR0, + .CFG[1] = VAL_GPIOC_AFCFGR1, + }, + // GPIO D + .setup[3] = + { + .DIR = VAL_GPIOD_DIRCR, + .INE = VAL_GPIOD_INER, + .PU = VAL_GPIOD_PUR, + .PD = VAL_GPIOD_PDR, + .OD = VAL_GPIOD_ODR, + .DRV = VAL_GPIOD_DRVR, + .LOCK = 0x0000, + .OUT = 0x0000, + .CFG[0] = VAL_GPIOD_AFCFGR0, + .CFG[1] = VAL_GPIOD_AFCFGR1, + }, + .ESSR[0] = VAL_ESSR0, + .ESSR[1] = VAL_ESSR1, +}; +#endif + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + ht32_clock_init(); +} + +/* + * Board-specific initialization code. + */ +void boardInit(void) {} diff --git a/os/hal/boards/HT_HT32F52342_52/board.h b/os/hal/boards/HT_HT32F52342_52/board.h new file mode 100644 index 0000000000..bcbef1902f --- /dev/null +++ b/os/hal/boards/HT_HT32F52342_52/board.h @@ -0,0 +1,630 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#pragma once + +/* + * Setup for a Generic HT32F52342/52 board. + */ + +/* + * Board identifier. + */ +#define BOARD_HT32_F52342_52 +#define BOARD_NAME "Generic HT32F52342/52 Board" + +/* + * Board frequencies. + */ +#define HT32_LSECLK 32768 +#define HT32_HSECLK 8000000 + +/* + * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h. + */ +#define HT32F52352 + +/* + * IO pins assignments + */ +#define GPIOA_PIN0 0U +#define GPIOA_PIN1 1U +#define GPIOA_PIN2 2U +#define GPIOA_PIN3 3U +#define GPIOA_PIN4 4U +#define GPIOA_PIN5 5U +#define GPIOA_PIN6 6U +#define GPIOA_PIN7 7U +#define GPIOA_PIN8 8U +#define GPIOA_PIN9 9U +#define GPIOA_PIN10 10U +#define GPIOA_PIN11 11U +#define GPIOA_PIN12 12U +#define GPIOA_PIN13 13U +#define GPIOA_PIN14 14U +#define GPIOA_PIN15 15U + +#define GPIOB_PIN0 0U +#define GPIOB_PIN1 1U +#define GPIOB_PIN2 2U +#define GPIOB_PIN3 3U +#define GPIOB_PIN4 4U +#define GPIOB_PIN5 5U +#define GPIOB_PIN6 6U +#define GPIOB_PIN7 7U +#define GPIOB_PIN8 8U +#define GPIOB_PIN9 9U +#define GPIOB_PIN10 10U +#define GPIOB_PIN11 11U +#define GPIOB_PIN12 12U +#define GPIOB_PIN13 13U +#define GPIOB_PIN14 14U +#define GPIOB_PIN15 15U + +#define GPIOC_PIN0 0U +#define GPIOC_PIN1 1U +#define GPIOC_PIN2 2U +#define GPIOC_PIN3 3U +#define GPIOC_PIN4 4U +#define GPIOC_PIN5 5U +#define GPIOC_PIN6 6U +#define GPIOC_PIN7 7U +#define GPIOC_PIN8 8U +#define GPIOC_PIN9 9U +#define GPIOC_PIN10 10U +#define GPIOC_PIN11 11U +#define GPIOC_PIN12 12U +#define GPIOC_PIN13 13U +#define GPIOC_PIN14 14U +#define GPIOC_PIN15 15U + +#define GPIOD_PIN0 0U +#define GPIOD_PIN1 1U +#define GPIOD_PIN2 2U +#define GPIOD_PIN3 3U +#define GPIOD_PIN4 4U +#define GPIOD_PIN5 5U +#define GPIOD_PIN6 6U +#define GPIOD_PIN7 7U +#define GPIOD_PIN8 8U +#define GPIOD_PIN9 9U +#define GPIOD_PIN10 10U +#define GPIOD_PIN11 11U +#define GPIOD_PIN12 12U +#define GPIOD_PIN13 13U +#define GPIOD_PIN14 14U +#define GPIOD_PIN15 15U + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the HT32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << (n)) +#define PIN_MODE_OUTPUT(n) (1U << (n)) +#define PIN_INPUT_DISABLE(n) (0U << (n)) +#define PIN_INPUT_ENABLE(n) (1U << (n)) +#define PIN_PULLUP_DISABLE(n) (0U << (n)) +#define PIN_PULLUP_ENABLE(n) (1U << (n)) +#define PIN_PULLDOWN_DISABLE(n) (0U << (n)) +#define PIN_PULLDOWN_ENABLE(n) (1U << (n)) +#define PIN_ODR_PUSHPULL(n) (0U << (n)) +#define PIN_ODR_OPENDRAIN(n) (1U << (n)) +#define PIN_DRVR_4MA(n) (0U << (n)) +#define PIN_DRVR_8MA(n) (0U << (n)) +#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) + +/* + * Port A setup. + * Everything GPIO input with pull-up except: + * PA12 - AF0 - SWCLK + * PA13 - AF0 - SWDIO + */ +#define VAL_GPIOA_DIRCR (PIN_MODE_INPUT(GPIOA_PIN0) | \ + PIN_MODE_INPUT(GPIOA_PIN1) | \ + PIN_MODE_INPUT(GPIOA_PIN2) | \ + PIN_MODE_INPUT(GPIOA_PIN3) | \ + PIN_MODE_INPUT(GPIOA_PIN4) | \ + PIN_MODE_INPUT(GPIOA_PIN5) | \ + PIN_MODE_INPUT(GPIOA_PIN6) | \ + PIN_MODE_INPUT(GPIOA_PIN7) | \ + PIN_MODE_INPUT(GPIOA_PIN8) | \ + PIN_MODE_INPUT(GPIOA_PIN9) | \ + PIN_MODE_INPUT(GPIOA_PIN10) | \ + PIN_MODE_INPUT(GPIOA_PIN11) | \ + PIN_MODE_INPUT(GPIOA_PIN12) | \ + PIN_MODE_INPUT(GPIOA_PIN13) | \ + PIN_MODE_INPUT(GPIOA_PIN14) | \ + PIN_MODE_INPUT(GPIOA_PIN15)) +#define VAL_GPIOA_INER (PIN_INPUT_ENABLE(GPIOA_PIN0) | \ + PIN_INPUT_ENABLE(GPIOA_PIN1) | \ + PIN_INPUT_ENABLE(GPIOA_PIN2) | \ + PIN_INPUT_ENABLE(GPIOA_PIN3) | \ + PIN_INPUT_ENABLE(GPIOA_PIN4) | \ + PIN_INPUT_ENABLE(GPIOA_PIN5) | \ + PIN_INPUT_ENABLE(GPIOA_PIN6) | \ + PIN_INPUT_ENABLE(GPIOA_PIN7) | \ + PIN_INPUT_ENABLE(GPIOA_PIN8) | \ + PIN_INPUT_ENABLE(GPIOA_PIN9) | \ + PIN_INPUT_ENABLE(GPIOA_PIN10) | \ + PIN_INPUT_ENABLE(GPIOA_PIN11) | \ + PIN_INPUT_DISABLE(GPIOA_PIN12) | \ + PIN_INPUT_DISABLE(GPIOA_PIN13) | \ + PIN_INPUT_ENABLE(GPIOA_PIN14) | \ + PIN_INPUT_ENABLE(GPIOA_PIN15)) +#define VAL_GPIOA_PUR (PIN_PULLUP_ENABLE(GPIOA_PIN0) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN1) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN2) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN3) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN4) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN5) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN6) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN7) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN8) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN9) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN10) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN11) | \ + PIN_PULLUP_DISABLE(GPIOA_PIN12) | \ + PIN_PULLUP_DISABLE(GPIOA_PIN13) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN14) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN15)) +#define VAL_GPIOA_PDR (PIN_PULLDOWN_DISABLE(GPIOA_PIN0) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN1) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN2) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN3) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN4) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN5) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN6) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN7) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN8) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN9) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN10) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN11) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN12) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN13) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN14) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN15)) +#define VAL_GPIOA_ODR (PIN_ODR_PUSHPULL(GPIOA_PIN0) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN1) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN2) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN3) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN4) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN5) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN6) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN7) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN8) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN9) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN10) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN11) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN12) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN13) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN14) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN15)) +#define VAL_GPIOA_DRVR (PIN_DRVR_4MA(GPIOA_PIN0) | \ + PIN_DRVR_4MA(GPIOA_PIN1) | \ + PIN_DRVR_4MA(GPIOA_PIN2) | \ + PIN_DRVR_4MA(GPIOA_PIN3) | \ + PIN_DRVR_4MA(GPIOA_PIN4) | \ + PIN_DRVR_4MA(GPIOA_PIN5) | \ + PIN_DRVR_4MA(GPIOA_PIN6) | \ + PIN_DRVR_4MA(GPIOA_PIN7) | \ + PIN_DRVR_4MA(GPIOA_PIN8) | \ + PIN_DRVR_4MA(GPIOA_PIN9) | \ + PIN_DRVR_4MA(GPIOA_PIN10) | \ + PIN_DRVR_4MA(GPIOA_PIN11) | \ + PIN_DRVR_4MA(GPIOA_PIN12) | \ + PIN_DRVR_4MA(GPIOA_PIN13) | \ + PIN_DRVR_4MA(GPIOA_PIN14) | \ + PIN_DRVR_4MA(GPIOA_PIN15)) +#define VAL_GPIOA_AFCFGR0 (PIN_AFIO_AF(GPIOA_PIN0, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN1, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN2, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN3, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN4, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN5, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN6, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN7, AFIO_GPIO)) +#define VAL_GPIOA_AFCFGR1 (PIN_AFIO_AF(GPIOA_PIN0, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN8, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN9, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN10, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN11, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN12, AFIO_DEFAULT) | \ + PIN_AFIO_AF(GPIOA_PIN13, AFIO_DEFAULT) | \ + PIN_AFIO_AF(GPIOA_PIN14, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN15, AFIO_GPIO)) + +/* + * Port B setup. + * Everything GPIO input with pull-up except: + * PB13 - AF0 - XTALIN + * PB14 - AF0 - XTALOUT + */ +#define VAL_GPIOB_DIRCR (PIN_MODE_INPUT(GPIOB_PIN0) | \ + PIN_MODE_INPUT(GPIOB_PIN1) | \ + PIN_MODE_INPUT(GPIOB_PIN2) | \ + PIN_MODE_INPUT(GPIOB_PIN3) | \ + PIN_MODE_INPUT(GPIOB_PIN4) | \ + PIN_MODE_INPUT(GPIOB_PIN5) | \ + PIN_MODE_INPUT(GPIOB_PIN6) | \ + PIN_MODE_INPUT(GPIOB_PIN7) | \ + PIN_MODE_INPUT(GPIOB_PIN8) | \ + PIN_MODE_INPUT(GPIOB_PIN9) | \ + PIN_MODE_INPUT(GPIOB_PIN10) | \ + PIN_MODE_INPUT(GPIOB_PIN11) | \ + PIN_MODE_INPUT(GPIOB_PIN12) | \ + PIN_MODE_INPUT(GPIOB_PIN13) | \ + PIN_MODE_INPUT(GPIOB_PIN14) | \ + PIN_MODE_INPUT(GPIOB_PIN15)) +#define VAL_GPIOB_INER (PIN_INPUT_ENABLE(GPIOB_PIN0) | \ + PIN_INPUT_ENABLE(GPIOB_PIN1) | \ + PIN_INPUT_ENABLE(GPIOB_PIN2) | \ + PIN_INPUT_ENABLE(GPIOB_PIN3) | \ + PIN_INPUT_ENABLE(GPIOB_PIN4) | \ + PIN_INPUT_ENABLE(GPIOB_PIN5) | \ + PIN_INPUT_ENABLE(GPIOB_PIN6) | \ + PIN_INPUT_ENABLE(GPIOB_PIN7) | \ + PIN_INPUT_ENABLE(GPIOB_PIN8) | \ + PIN_INPUT_ENABLE(GPIOB_PIN9) | \ + PIN_INPUT_ENABLE(GPIOB_PIN10) | \ + PIN_INPUT_ENABLE(GPIOB_PIN11) | \ + PIN_INPUT_ENABLE(GPIOB_PIN12) | \ + PIN_INPUT_DISABLE(GPIOB_PIN13) | \ + PIN_INPUT_DISABLE(GPIOB_PIN14) | \ + PIN_INPUT_ENABLE(GPIOB_PIN15)) +#define VAL_GPIOB_PUR (PIN_PULLUP_ENABLE(GPIOB_PIN0) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN1) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN2) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN3) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN4) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN5) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN6) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN7) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN8) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN9) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN10) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN11) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN12) | \ + PIN_PULLUP_DISABLE(GPIOB_PIN13) | \ + PIN_PULLUP_DISABLE(GPIOB_PIN14) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN15)) +#define VAL_GPIOB_PDR (PIN_PULLDOWN_DISABLE(GPIOB_PIN0) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN1) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN2) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN3) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN4) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN5) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN6) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN7) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN8) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN9) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN10) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN11) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN12) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN13) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN14) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN15)) +#define VAL_GPIOB_ODR (PIN_ODR_PUSHPULL(GPIOB_PIN0) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN1) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN2) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN3) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN4) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN5) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN6) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN7) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN8) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN9) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN10) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN11) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN12) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN13) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN14) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN15)) +#define VAL_GPIOB_DRVR (PIN_DRVR_4MA(GPIOB_PIN0) | \ + PIN_DRVR_4MA(GPIOB_PIN1) | \ + PIN_DRVR_4MA(GPIOB_PIN2) | \ + PIN_DRVR_4MA(GPIOB_PIN3) | \ + PIN_DRVR_4MA(GPIOB_PIN4) | \ + PIN_DRVR_4MA(GPIOB_PIN5) | \ + PIN_DRVR_4MA(GPIOB_PIN6) | \ + PIN_DRVR_4MA(GPIOB_PIN7) | \ + PIN_DRVR_4MA(GPIOB_PIN8) | \ + PIN_DRVR_4MA(GPIOB_PIN9) | \ + PIN_DRVR_4MA(GPIOB_PIN10) | \ + PIN_DRVR_4MA(GPIOB_PIN11) | \ + PIN_DRVR_4MA(GPIOB_PIN12) | \ + PIN_DRVR_4MA(GPIOB_PIN13) | \ + PIN_DRVR_4MA(GPIOB_PIN14) | \ + PIN_DRVR_4MA(GPIOB_PIN15)) +#define VAL_GPIOB_AFCFGR0 (PIN_AFIO_AF(GPIOB_PIN0, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN1, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN2, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN3, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN4, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN5, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN6, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN7, AFIO_GPIO)) +#define VAL_GPIOB_AFCFGR1 (PIN_AFIO_AF(GPIOB_PIN0, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN8, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN9, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN10, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN11, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN12, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN13, AFIO_DEFAULT) | \ + PIN_AFIO_AF(GPIOB_PIN14, AFIO_DEFAULT) | \ + PIN_AFIO_AF(GPIOB_PIN15, AFIO_GPIO)) + +/* + * Port C setup. + * Everything GPIO input with pull-up + * PC6 - AF0 - USBD- + * PC7 - AF0 - USBD+ + */ +#define VAL_GPIOC_DIR 0x0000 /* PC15...PC0 */ +#define VAL_GPIOC_INE 0xFF3F /* PC15...PC0 */ +#define VAL_GPIOC_PU 0xFF3F /* PC15...PC0 */ +#define VAL_GPIOC_PD 0x0000 /* PC15...PC0 */ +#define VAL_GPIOC_OD 0x0000 /* PC15...PC0 */ +#define VAL_GPIOC_DRV 0x0000 /* PC15...PC0 */ +#define VAL_GPIOC_AFCFG0 0x00111111 /* PC7...PC0 */ +#define VAL_GPIOC_AFCFG1 0x11111111 /* PC15...PC8 */ +#define VAL_GPIOC_DIRCR (PIN_MODE_INPUT(GPIOC_PIN0) | \ + PIN_MODE_INPUT(GPIOC_PIN1) | \ + PIN_MODE_INPUT(GPIOC_PIN2) | \ + PIN_MODE_INPUT(GPIOC_PIN3) | \ + PIN_MODE_INPUT(GPIOC_PIN4) | \ + PIN_MODE_INPUT(GPIOC_PIN5) | \ + PIN_MODE_INPUT(GPIOC_PIN6) | \ + PIN_MODE_INPUT(GPIOC_PIN7) | \ + PIN_MODE_INPUT(GPIOC_PIN8) | \ + PIN_MODE_INPUT(GPIOC_PIN9) | \ + PIN_MODE_INPUT(GPIOC_PIN10) | \ + PIN_MODE_INPUT(GPIOC_PIN11) | \ + PIN_MODE_INPUT(GPIOC_PIN12) | \ + PIN_MODE_INPUT(GPIOC_PIN13) | \ + PIN_MODE_INPUT(GPIOC_PIN14) | \ + PIN_MODE_INPUT(GPIOC_PIN15)) +#define VAL_GPIOC_INER (PIN_INPUT_ENABLE(GPIOC_PIN0) | \ + PIN_INPUT_ENABLE(GPIOC_PIN1) | \ + PIN_INPUT_ENABLE(GPIOC_PIN2) | \ + PIN_INPUT_ENABLE(GPIOC_PIN3) | \ + PIN_INPUT_ENABLE(GPIOC_PIN4) | \ + PIN_INPUT_ENABLE(GPIOC_PIN5) | \ + PIN_INPUT_DISABLE(GPIOC_PIN6) | \ + PIN_INPUT_DISABLE(GPIOC_PIN7) | \ + PIN_INPUT_ENABLE(GPIOC_PIN8) | \ + PIN_INPUT_ENABLE(GPIOC_PIN9) | \ + PIN_INPUT_ENABLE(GPIOC_PIN10) | \ + PIN_INPUT_ENABLE(GPIOC_PIN11) | \ + PIN_INPUT_ENABLE(GPIOC_PIN12) | \ + PIN_INPUT_ENABLE(GPIOC_PIN13) | \ + PIN_INPUT_ENABLE(GPIOC_PIN14) | \ + PIN_INPUT_ENABLE(GPIOC_PIN15)) +#define VAL_GPIOC_PUR (PIN_PULLUP_ENABLE(GPIOC_PIN0) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN1) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN2) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN3) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN4) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN5) | \ + PIN_PULLUP_DISABLE(GPIOC_PIN6) | \ + PIN_PULLUP_DISABLE(GPIOC_PIN7) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN8) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN9) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN10) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN11) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN12) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN13) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN14) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN15)) +#define VAL_GPIOC_PDR (PIN_PULLDOWN_DISABLE(GPIOC_PIN0) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN1) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN2) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN3) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN4) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN5) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN6) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN7) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN8) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN9) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN10) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN11) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN12) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN13) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN14) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN15)) +#define VAL_GPIOC_ODR (PIN_ODR_PUSHPULL(GPIOC_PIN0) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN1) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN2) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN3) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN4) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN5) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN6) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN7) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN8) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN9) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN10) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN11) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN12) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN13) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN14) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN15)) +#define VAL_GPIOC_DRVR (PIN_DRVR_4MA(GPIOC_PIN0) | \ + PIN_DRVR_4MA(GPIOC_PIN1) | \ + PIN_DRVR_4MA(GPIOC_PIN2) | \ + PIN_DRVR_4MA(GPIOC_PIN3) | \ + PIN_DRVR_4MA(GPIOC_PIN4) | \ + PIN_DRVR_4MA(GPIOC_PIN5) | \ + PIN_DRVR_4MA(GPIOC_PIN6) | \ + PIN_DRVR_4MA(GPIOC_PIN7) | \ + PIN_DRVR_4MA(GPIOC_PIN8) | \ + PIN_DRVR_4MA(GPIOC_PIN9) | \ + PIN_DRVR_4MA(GPIOC_PIN10) | \ + PIN_DRVR_4MA(GPIOC_PIN11) | \ + PIN_DRVR_4MA(GPIOC_PIN12) | \ + PIN_DRVR_4MA(GPIOC_PIN13) | \ + PIN_DRVR_4MA(GPIOC_PIN14) | \ + PIN_DRVR_4MA(GPIOC_PIN15)) +#define VAL_GPIOC_AFCFGR0 (PIN_AFIO_AF(GPIOC_PIN0, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN1, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN2, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN3, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN4, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN5, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN6, AFIO_DEFAULT) | \ + PIN_AFIO_AF(GPIOC_PIN7, AFIO_DEFAULT)) +#define VAL_GPIOC_AFCFGR1 (PIN_AFIO_AF(GPIOC_PIN0, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN8, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN9, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN10, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN11, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN12, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN13, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN14, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN15, AFIO_GPIO)) + +/* + * Port D setup. + * Everything GPIO input with pull-up + */ +#define VAL_GPIOD_DIRCR (PIN_MODE_INPUT(GPIOD_PIN0) | \ + PIN_MODE_INPUT(GPIOD_PIN1) | \ + PIN_MODE_INPUT(GPIOD_PIN2) | \ + PIN_MODE_INPUT(GPIOD_PIN3) | \ + PIN_MODE_INPUT(GPIOD_PIN4) | \ + PIN_MODE_INPUT(GPIOD_PIN5) | \ + PIN_MODE_INPUT(GPIOD_PIN6) | \ + PIN_MODE_INPUT(GPIOD_PIN7) | \ + PIN_MODE_INPUT(GPIOD_PIN8) | \ + PIN_MODE_INPUT(GPIOD_PIN9) | \ + PIN_MODE_INPUT(GPIOD_PIN10) | \ + PIN_MODE_INPUT(GPIOD_PIN11) | \ + PIN_MODE_INPUT(GPIOD_PIN12) | \ + PIN_MODE_INPUT(GPIOD_PIN13) | \ + PIN_MODE_INPUT(GPIOD_PIN14) | \ + PIN_MODE_INPUT(GPIOD_PIN15)) +#define VAL_GPIOD_INER (PIN_INPUT_ENABLE(GPIOD_PIN0) | \ + PIN_INPUT_ENABLE(GPIOD_PIN1) | \ + PIN_INPUT_ENABLE(GPIOD_PIN2) | \ + PIN_INPUT_ENABLE(GPIOD_PIN3) | \ + PIN_INPUT_ENABLE(GPIOD_PIN4) | \ + PIN_INPUT_ENABLE(GPIOD_PIN5) | \ + PIN_INPUT_ENABLE(GPIOD_PIN6) | \ + PIN_INPUT_ENABLE(GPIOD_PIN7) | \ + PIN_INPUT_ENABLE(GPIOD_PIN8) | \ + PIN_INPUT_ENABLE(GPIOD_PIN9) | \ + PIN_INPUT_ENABLE(GPIOD_PIN10) | \ + PIN_INPUT_ENABLE(GPIOD_PIN11) | \ + PIN_INPUT_ENABLE(GPIOD_PIN12) | \ + PIN_INPUT_ENABLE(GPIOD_PIN13) | \ + PIN_INPUT_ENABLE(GPIOD_PIN14) | \ + PIN_INPUT_ENABLE(GPIOD_PIN15)) +#define VAL_GPIOD_PUR (PIN_PULLUP_ENABLE(GPIOD_PIN0) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN1) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN2) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN3) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN4) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN5) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN6) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN7) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN8) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN9) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN10) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN11) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN12) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN13) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN14) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN15)) +#define VAL_GPIOD_PDR (PIN_PULLDOWN_DISABLE(GPIOD_PIN0) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN1) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN2) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN3) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN4) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN5) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN6) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN7) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN8) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN9) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN10) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN11) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN12) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN13) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN14) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN15)) +#define VAL_GPIOD_ODR (PIN_ODR_PUSHPULL(GPIOD_PIN0) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN1) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN2) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN3) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN4) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN5) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN6) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN7) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN8) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN9) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN10) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN11) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN12) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN13) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN14) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN15)) +#define VAL_GPIOD_DRVR (PIN_DRVR_4MA(GPIOD_PIN0) | \ + PIN_DRVR_4MA(GPIOD_PIN1) | \ + PIN_DRVR_4MA(GPIOD_PIN2) | \ + PIN_DRVR_4MA(GPIOD_PIN3) | \ + PIN_DRVR_4MA(GPIOD_PIN4) | \ + PIN_DRVR_4MA(GPIOD_PIN5) | \ + PIN_DRVR_4MA(GPIOD_PIN6) | \ + PIN_DRVR_4MA(GPIOD_PIN7) | \ + PIN_DRVR_4MA(GPIOD_PIN8) | \ + PIN_DRVR_4MA(GPIOD_PIN9) | \ + PIN_DRVR_4MA(GPIOD_PIN10) | \ + PIN_DRVR_4MA(GPIOD_PIN11) | \ + PIN_DRVR_4MA(GPIOD_PIN12) | \ + PIN_DRVR_4MA(GPIOD_PIN13) | \ + PIN_DRVR_4MA(GPIOD_PIN14) | \ + PIN_DRVR_4MA(GPIOD_PIN15)) +#define VAL_GPIOD_AFCFGR0 (PIN_AFIO_AF(GPIOD_PIN0, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN1, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN2, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN3, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN4, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN5, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN6, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN7, AFIO_GPIO)) +#define VAL_GPIOD_AFCFGR1 (PIN_AFIO_AF(GPIOD_PIN0, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN8, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN9, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN10, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN11, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN12, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN13, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN14, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN15, AFIO_GPIO)) + +/* + * EXTI setup. + */ +#define VAL_ESSR0 0x00000000 +#define VAL_ESSR1 0x00000000 + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ diff --git a/os/hal/boards/HT_HT32F52342_52/board.mk b/os/hal/boards/HT_HT32F52342_52/board.mk new file mode 100644 index 0000000000..c26f0ddfbe --- /dev/null +++ b/os/hal/boards/HT_HT32F52342_52/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files. +BOARDSRC = $(CHIBIOS_CONTRIB)/os/hal/boards/HT_HT32F52342_52/board.c + +# Required include directories +BOARDINC = $(CHIBIOS_CONTRIB)/os/hal/boards/HT_HT32F52342_52 + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC) From 0689ae86297ebb36c0416ee6da9e218ca8c8e030 Mon Sep 17 00:00:00 2001 From: Hansem Ro Date: Sat, 4 May 2024 22:24:30 -0700 Subject: [PATCH 09/19] HT32: Add generic HT32F1655/6 board --- os/hal/boards/HT_HT32F1655_6/board.c | 113 ++++ os/hal/boards/HT_HT32F1655_6/board.h | 757 ++++++++++++++++++++++++++ os/hal/boards/HT_HT32F1655_6/board.mk | 9 + 3 files changed, 879 insertions(+) create mode 100644 os/hal/boards/HT_HT32F1655_6/board.c create mode 100644 os/hal/boards/HT_HT32F1655_6/board.h create mode 100644 os/hal/boards/HT_HT32F1655_6/board.mk diff --git a/os/hal/boards/HT_HT32F1655_6/board.c b/os/hal/boards/HT_HT32F1655_6/board.c new file mode 100644 index 0000000000..a03581b6c6 --- /dev/null +++ b/os/hal/boards/HT_HT32F1655_6/board.c @@ -0,0 +1,113 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = { + // GPIO A + .setup[0] = + { + .DIR = VAL_GPIOA_DIRCR, + .INE = VAL_GPIOA_INER, + .PU = VAL_GPIOA_PUR, + .PD = VAL_GPIOA_PDR, + .OD = VAL_GPIOA_ODR, + .DRV = VAL_GPIOA_DRVR, + .LOCK = 0x0000, + .OUT = 0x0000, + .CFG[0] = VAL_GPIOA_AFCFGR0, + .CFG[1] = VAL_GPIOA_AFCFGR1, + }, + // GPIO B + .setup[1] = + { + .DIR = VAL_GPIOB_DIRCR, + .INE = VAL_GPIOB_INER, + .PU = VAL_GPIOB_PUR, + .PD = VAL_GPIOB_PDR, + .OD = VAL_GPIOB_ODR, + .DRV = VAL_GPIOB_DRVR, + .LOCK = 0x0000, + .OUT = 0x0000, + .CFG[0] = VAL_GPIOB_AFCFGR0, + .CFG[1] = VAL_GPIOB_AFCFGR1, + }, + // GPIO C + .setup[2] = + { + .DIR = VAL_GPIOC_DIRCR, + .INE = VAL_GPIOC_INER, + .PU = VAL_GPIOC_PUR, + .PD = VAL_GPIOC_PDR, + .OD = VAL_GPIOC_ODR, + .DRV = VAL_GPIOC_DRVR, + .LOCK = 0x0000, + .OUT = 0x0000, + .CFG[0] = VAL_GPIOC_AFCFGR0, + .CFG[1] = VAL_GPIOC_AFCFGR1, + }, + // GPIO D + .setup[3] = + { + .DIR = VAL_GPIOD_DIRCR, + .INE = VAL_GPIOD_INER, + .PU = VAL_GPIOD_PUR, + .PD = VAL_GPIOD_PDR, + .OD = VAL_GPIOD_ODR, + .DRV = VAL_GPIOD_DRVR, + .LOCK = 0x0000, + .OUT = 0x0000, + .CFG[0] = VAL_GPIOD_AFCFGR0, + .CFG[1] = VAL_GPIOD_AFCFGR1, + }, + // GPIO E + .setup[4] = + { + .DIR = VAL_GPIOE_DIRCR, + .INE = VAL_GPIOE_INER, + .PU = VAL_GPIOE_PUR, + .PD = VAL_GPIOE_PDR, + .OD = VAL_GPIOE_ODR, + .DRV = VAL_GPIOE_DRVR, + .LOCK = 0x0000, + .OUT = 0x0000, + .CFG[0] = VAL_GPIOE_AFCFGR0, + .CFG[1] = VAL_GPIOE_AFCFGR1, + }, + .ESSR[0] = VAL_ESSR0, + .ESSR[1] = VAL_ESSR1, +}; +#endif + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + ht32_clock_init(); +} + +/* + * Board-specific initialization code. + */ +void boardInit(void) {} diff --git a/os/hal/boards/HT_HT32F1655_6/board.h b/os/hal/boards/HT_HT32F1655_6/board.h new file mode 100644 index 0000000000..fe9ec9c876 --- /dev/null +++ b/os/hal/boards/HT_HT32F1655_6/board.h @@ -0,0 +1,757 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#pragma once + +/* + * Setup for a Generic HT32F1655/6 board. + */ + +/* + * Board identifier. + */ +#define BOARD_HT32_F1655_6 +#define BOARD_NAME "Generic HT32F1655/6 Board" + +/* + * Board frequencies. + */ +#define HT32_LSECLK 32768 +#define HT32_HSECLK 8000000 + +/* + * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h. + */ +#define HT32F1656 + +/* + * IO pins assignments. + */ +#define GPIOA_PIN0 0U +#define GPIOA_PIN1 1U +#define GPIOA_PIN2 2U +#define GPIOA_PIN3 3U +#define GPIOA_PIN4 4U +#define GPIOA_PIN5 5U +#define GPIOA_PIN6 6U +#define GPIOA_PIN7 7U +#define GPIOA_PIN8 8U +#define GPIOA_PIN9 9U +#define GPIOA_PIN10 10U +#define GPIOA_PIN11 11U +#define GPIOA_PIN12 12U +#define GPIOA_PIN13 13U +#define GPIOA_PIN14 14U +#define GPIOA_PIN15 15U + +#define GPIOB_PIN0 0U +#define GPIOB_PIN1 1U +#define GPIOB_PIN2 2U +#define GPIOB_PIN3 3U +#define GPIOB_PIN4 4U +#define GPIOB_PIN5 5U +#define GPIOB_PIN6 6U +#define GPIOB_PIN7 7U +#define GPIOB_PIN8 8U +#define GPIOB_PIN9 9U +#define GPIOB_PIN10 10U +#define GPIOB_PIN11 11U +#define GPIOB_PIN12 12U +#define GPIOB_PIN13 13U +#define GPIOB_PIN14 14U +#define GPIOB_PIN15 15U + +#define GPIOC_PIN0 0U +#define GPIOC_PIN1 1U +#define GPIOC_PIN2 2U +#define GPIOC_PIN3 3U +#define GPIOC_PIN4 4U +#define GPIOC_PIN5 5U +#define GPIOC_PIN6 6U +#define GPIOC_PIN7 7U +#define GPIOC_PIN8 8U +#define GPIOC_PIN9 9U +#define GPIOC_PIN10 10U +#define GPIOC_PIN11 11U +#define GPIOC_PIN12 12U +#define GPIOC_PIN13 13U +#define GPIOC_PIN14 14U +#define GPIOC_PIN15 15U + +#define GPIOD_PIN0 0U +#define GPIOD_PIN1 1U +#define GPIOD_PIN2 2U +#define GPIOD_PIN3 3U +#define GPIOD_PIN4 4U +#define GPIOD_PIN5 5U +#define GPIOD_PIN6 6U +#define GPIOD_PIN7 7U +#define GPIOD_PIN8 8U +#define GPIOD_PIN9 9U +#define GPIOD_PIN10 10U +#define GPIOD_PIN11 11U +#define GPIOD_PIN12 12U +#define GPIOD_PIN13 13U +#define GPIOD_PIN14 14U +#define GPIOD_PIN15 15U + +#define GPIOE_PIN0 0U +#define GPIOE_PIN1 1U +#define GPIOE_PIN2 2U +#define GPIOE_PIN3 3U +#define GPIOE_PIN4 4U +#define GPIOE_PIN5 5U +#define GPIOE_PIN6 6U +#define GPIOE_PIN7 7U +#define GPIOE_PIN8 8U +#define GPIOE_PIN9 9U +#define GPIOE_PIN10 10U +#define GPIOE_PIN11 11U +#define GPIOE_PIN12 12U +#define GPIOE_PIN13 13U +#define GPIOE_PIN14 14U +#define GPIOE_PIN15 15U + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the HT32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << (n)) +#define PIN_MODE_OUTPUT(n) (1U << (n)) +#define PIN_INPUT_DISABLE(n) (0U << (n)) +#define PIN_INPUT_ENABLE(n) (1U << (n)) +#define PIN_PULLUP_DISABLE(n) (0U << (n)) +#define PIN_PULLUP_ENABLE(n) (1U << (n)) +#define PIN_PULLDOWN_DISABLE(n) (0U << (n)) +#define PIN_PULLDOWN_ENABLE(n) (1U << (n)) +#define PIN_ODR_PUSHPULL(n) (0U << (n)) +#define PIN_ODR_OPENDRAIN(n) (1U << (n)) +#define PIN_DRVR_4MA(n) (0U << (n)) +#define PIN_DRVR_8MA(n) (0U << (n)) +#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) + +/* + * Port A setup. + * Everything GPIO input with pull-up except: + * PA12 - AF0 - SWCLK + * PA13 - AF0 - SWDIO + */ +#define VAL_GPIOA_DIRCR (PIN_MODE_INPUT(GPIOA_PIN0) | \ + PIN_MODE_INPUT(GPIOA_PIN1) | \ + PIN_MODE_INPUT(GPIOA_PIN2) | \ + PIN_MODE_INPUT(GPIOA_PIN3) | \ + PIN_MODE_INPUT(GPIOA_PIN4) | \ + PIN_MODE_INPUT(GPIOA_PIN5) | \ + PIN_MODE_INPUT(GPIOA_PIN6) | \ + PIN_MODE_INPUT(GPIOA_PIN7) | \ + PIN_MODE_INPUT(GPIOA_PIN8) | \ + PIN_MODE_INPUT(GPIOA_PIN9) | \ + PIN_MODE_INPUT(GPIOA_PIN10) | \ + PIN_MODE_INPUT(GPIOA_PIN11) | \ + PIN_MODE_INPUT(GPIOA_PIN12) | \ + PIN_MODE_INPUT(GPIOA_PIN13) | \ + PIN_MODE_INPUT(GPIOA_PIN14) | \ + PIN_MODE_INPUT(GPIOA_PIN15)) +#define VAL_GPIOA_INER (PIN_INPUT_ENABLE(GPIOA_PIN0) | \ + PIN_INPUT_ENABLE(GPIOA_PIN1) | \ + PIN_INPUT_ENABLE(GPIOA_PIN2) | \ + PIN_INPUT_ENABLE(GPIOA_PIN3) | \ + PIN_INPUT_ENABLE(GPIOA_PIN4) | \ + PIN_INPUT_ENABLE(GPIOA_PIN5) | \ + PIN_INPUT_ENABLE(GPIOA_PIN6) | \ + PIN_INPUT_ENABLE(GPIOA_PIN7) | \ + PIN_INPUT_ENABLE(GPIOA_PIN8) | \ + PIN_INPUT_ENABLE(GPIOA_PIN9) | \ + PIN_INPUT_ENABLE(GPIOA_PIN10) | \ + PIN_INPUT_ENABLE(GPIOA_PIN11) | \ + PIN_INPUT_DISABLE(GPIOA_PIN12) | \ + PIN_INPUT_DISABLE(GPIOA_PIN13) | \ + PIN_INPUT_ENABLE(GPIOA_PIN14) | \ + PIN_INPUT_ENABLE(GPIOA_PIN15)) +#define VAL_GPIOA_PUR (PIN_PULLUP_ENABLE(GPIOA_PIN0) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN1) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN2) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN3) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN4) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN5) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN6) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN7) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN8) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN9) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN10) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN11) | \ + PIN_PULLUP_DISABLE(GPIOA_PIN12) | \ + PIN_PULLUP_DISABLE(GPIOA_PIN13) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN14) | \ + PIN_PULLUP_ENABLE(GPIOA_PIN15)) +#define VAL_GPIOA_PDR (PIN_PULLDOWN_DISABLE(GPIOA_PIN0) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN1) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN2) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN3) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN4) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN5) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN6) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN7) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN8) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN9) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN10) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN11) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN12) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN13) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN14) | \ + PIN_PULLDOWN_DISABLE(GPIOA_PIN15)) +#define VAL_GPIOA_ODR (PIN_ODR_PUSHPULL(GPIOA_PIN0) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN1) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN2) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN3) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN4) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN5) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN6) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN7) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN8) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN9) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN10) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN11) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN12) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN13) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN14) | \ + PIN_ODR_PUSHPULL(GPIOA_PIN15)) +#define VAL_GPIOA_DRVR (PIN_DRVR_4MA(GPIOA_PIN0) | \ + PIN_DRVR_4MA(GPIOA_PIN1) | \ + PIN_DRVR_4MA(GPIOA_PIN2) | \ + PIN_DRVR_4MA(GPIOA_PIN3) | \ + PIN_DRVR_4MA(GPIOA_PIN4) | \ + PIN_DRVR_4MA(GPIOA_PIN5) | \ + PIN_DRVR_4MA(GPIOA_PIN6) | \ + PIN_DRVR_4MA(GPIOA_PIN7) | \ + PIN_DRVR_4MA(GPIOA_PIN8) | \ + PIN_DRVR_4MA(GPIOA_PIN9) | \ + PIN_DRVR_4MA(GPIOA_PIN10) | \ + PIN_DRVR_4MA(GPIOA_PIN11) | \ + PIN_DRVR_4MA(GPIOA_PIN12) | \ + PIN_DRVR_4MA(GPIOA_PIN13) | \ + PIN_DRVR_4MA(GPIOA_PIN14) | \ + PIN_DRVR_4MA(GPIOA_PIN15)) +#define VAL_GPIOA_AFCFGR0 (PIN_AFIO_AF(GPIOA_PIN0, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN1, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN2, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN3, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN4, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN5, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN6, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN7, AFIO_GPIO)) +#define VAL_GPIOA_AFCFGR1 (PIN_AFIO_AF(GPIOA_PIN0, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN8, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN9, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN10, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN11, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN12, AFIO_DEFAULT) | \ + PIN_AFIO_AF(GPIOA_PIN13, AFIO_DEFAULT) | \ + PIN_AFIO_AF(GPIOA_PIN14, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOA_PIN15, AFIO_GPIO)) + +/* + * Port B setup. + * Everything GPIO input with pull-up except: + * PB12 - AF0 - USBD- + * PB13 - AF0 - USBD+ + * PB14 - AF0 - XTALIN + * PB15 - AF0 - XTALOUT + */ +#define VAL_GPIOB_DIRCR (PIN_MODE_INPUT(GPIOB_PIN0) | \ + PIN_MODE_INPUT(GPIOB_PIN1) | \ + PIN_MODE_INPUT(GPIOB_PIN2) | \ + PIN_MODE_INPUT(GPIOB_PIN3) | \ + PIN_MODE_INPUT(GPIOB_PIN4) | \ + PIN_MODE_INPUT(GPIOB_PIN5) | \ + PIN_MODE_INPUT(GPIOB_PIN6) | \ + PIN_MODE_INPUT(GPIOB_PIN7) | \ + PIN_MODE_INPUT(GPIOB_PIN8) | \ + PIN_MODE_INPUT(GPIOB_PIN9) | \ + PIN_MODE_INPUT(GPIOB_PIN10) | \ + PIN_MODE_INPUT(GPIOB_PIN11) | \ + PIN_MODE_INPUT(GPIOB_PIN12) | \ + PIN_MODE_INPUT(GPIOB_PIN13) | \ + PIN_MODE_INPUT(GPIOB_PIN14) | \ + PIN_MODE_INPUT(GPIOB_PIN15)) +#define VAL_GPIOB_INER (PIN_INPUT_ENABLE(GPIOB_PIN0) | \ + PIN_INPUT_ENABLE(GPIOB_PIN1) | \ + PIN_INPUT_ENABLE(GPIOB_PIN2) | \ + PIN_INPUT_ENABLE(GPIOB_PIN3) | \ + PIN_INPUT_ENABLE(GPIOB_PIN4) | \ + PIN_INPUT_ENABLE(GPIOB_PIN5) | \ + PIN_INPUT_ENABLE(GPIOB_PIN6) | \ + PIN_INPUT_ENABLE(GPIOB_PIN7) | \ + PIN_INPUT_ENABLE(GPIOB_PIN8) | \ + PIN_INPUT_ENABLE(GPIOB_PIN9) | \ + PIN_INPUT_ENABLE(GPIOB_PIN10) | \ + PIN_INPUT_ENABLE(GPIOB_PIN11) | \ + PIN_INPUT_DISABLE(GPIOB_PIN12) | \ + PIN_INPUT_DISABLE(GPIOB_PIN13) | \ + PIN_INPUT_DISABLE(GPIOB_PIN14) | \ + PIN_INPUT_DISABLE(GPIOB_PIN15)) +#define VAL_GPIOB_PUR (PIN_PULLUP_ENABLE(GPIOB_PIN0) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN1) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN2) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN3) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN4) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN5) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN6) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN7) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN8) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN9) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN10) | \ + PIN_PULLUP_ENABLE(GPIOB_PIN11) | \ + PIN_PULLUP_DISABLE(GPIOB_PIN12) | \ + PIN_PULLUP_DISABLE(GPIOB_PIN13) | \ + PIN_PULLUP_DISABLE(GPIOB_PIN14) | \ + PIN_PULLUP_DISABLE(GPIOB_PIN15)) +#define VAL_GPIOB_PDR (PIN_PULLDOWN_DISABLE(GPIOB_PIN0) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN1) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN2) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN3) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN4) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN5) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN6) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN7) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN8) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN9) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN10) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN11) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN12) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN13) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN14) | \ + PIN_PULLDOWN_DISABLE(GPIOB_PIN15)) +#define VAL_GPIOB_ODR (PIN_ODR_PUSHPULL(GPIOB_PIN0) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN1) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN2) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN3) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN4) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN5) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN6) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN7) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN8) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN9) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN10) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN11) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN12) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN13) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN14) | \ + PIN_ODR_PUSHPULL(GPIOB_PIN15)) +#define VAL_GPIOB_DRVR (PIN_DRVR_4MA(GPIOB_PIN0) | \ + PIN_DRVR_4MA(GPIOB_PIN1) | \ + PIN_DRVR_4MA(GPIOB_PIN2) | \ + PIN_DRVR_4MA(GPIOB_PIN3) | \ + PIN_DRVR_4MA(GPIOB_PIN4) | \ + PIN_DRVR_4MA(GPIOB_PIN5) | \ + PIN_DRVR_4MA(GPIOB_PIN6) | \ + PIN_DRVR_4MA(GPIOB_PIN7) | \ + PIN_DRVR_4MA(GPIOB_PIN8) | \ + PIN_DRVR_4MA(GPIOB_PIN9) | \ + PIN_DRVR_4MA(GPIOB_PIN10) | \ + PIN_DRVR_4MA(GPIOB_PIN11) | \ + PIN_DRVR_4MA(GPIOB_PIN12) | \ + PIN_DRVR_4MA(GPIOB_PIN13) | \ + PIN_DRVR_4MA(GPIOB_PIN14) | \ + PIN_DRVR_4MA(GPIOB_PIN15)) +#define VAL_GPIOB_AFCFGR0 (PIN_AFIO_AF(GPIOB_PIN0, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN1, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN2, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN3, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN4, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN5, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN6, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN7, AFIO_GPIO)) +#define VAL_GPIOB_AFCFGR1 (PIN_AFIO_AF(GPIOB_PIN0, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN8, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN9, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN10, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN11, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOB_PIN12, AFIO_DEFAULT) | \ + PIN_AFIO_AF(GPIOB_PIN13, AFIO_DEFAULT) | \ + PIN_AFIO_AF(GPIOB_PIN14, AFIO_DEFAULT) | \ + PIN_AFIO_AF(GPIOB_PIN15, AFIO_DEFAULT)) + +/* + * Port C setup. + * Everything GPIO input with pull-up + */ +#define VAL_GPIOC_DIRCR (PIN_MODE_INPUT(GPIOC_PIN0) | \ + PIN_MODE_INPUT(GPIOC_PIN1) | \ + PIN_MODE_INPUT(GPIOC_PIN2) | \ + PIN_MODE_INPUT(GPIOC_PIN3) | \ + PIN_MODE_INPUT(GPIOC_PIN4) | \ + PIN_MODE_INPUT(GPIOC_PIN5) | \ + PIN_MODE_INPUT(GPIOC_PIN6) | \ + PIN_MODE_INPUT(GPIOC_PIN7) | \ + PIN_MODE_INPUT(GPIOC_PIN8) | \ + PIN_MODE_INPUT(GPIOC_PIN9) | \ + PIN_MODE_INPUT(GPIOC_PIN10) | \ + PIN_MODE_INPUT(GPIOC_PIN11) | \ + PIN_MODE_INPUT(GPIOC_PIN12) | \ + PIN_MODE_INPUT(GPIOC_PIN13) | \ + PIN_MODE_INPUT(GPIOC_PIN14) | \ + PIN_MODE_INPUT(GPIOC_PIN15)) +#define VAL_GPIOC_INER (PIN_INPUT_ENABLE(GPIOC_PIN0) | \ + PIN_INPUT_ENABLE(GPIOC_PIN1) | \ + PIN_INPUT_ENABLE(GPIOC_PIN2) | \ + PIN_INPUT_ENABLE(GPIOC_PIN3) | \ + PIN_INPUT_ENABLE(GPIOC_PIN4) | \ + PIN_INPUT_ENABLE(GPIOC_PIN5) | \ + PIN_INPUT_ENABLE(GPIOC_PIN6) | \ + PIN_INPUT_ENABLE(GPIOC_PIN7) | \ + PIN_INPUT_ENABLE(GPIOC_PIN8) | \ + PIN_INPUT_ENABLE(GPIOC_PIN9) | \ + PIN_INPUT_ENABLE(GPIOC_PIN10) | \ + PIN_INPUT_ENABLE(GPIOC_PIN11) | \ + PIN_INPUT_ENABLE(GPIOC_PIN12) | \ + PIN_INPUT_ENABLE(GPIOC_PIN13) | \ + PIN_INPUT_ENABLE(GPIOC_PIN14) | \ + PIN_INPUT_ENABLE(GPIOC_PIN15)) +#define VAL_GPIOC_PUR (PIN_PULLUP_ENABLE(GPIOC_PIN0) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN1) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN2) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN3) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN4) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN5) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN6) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN7) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN8) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN9) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN10) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN11) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN12) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN13) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN14) | \ + PIN_PULLUP_ENABLE(GPIOC_PIN15)) +#define VAL_GPIOC_PDR (PIN_PULLDOWN_DISABLE(GPIOC_PIN0) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN1) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN2) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN3) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN4) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN5) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN6) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN7) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN8) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN9) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN10) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN11) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN12) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN13) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN14) | \ + PIN_PULLDOWN_DISABLE(GPIOC_PIN15)) +#define VAL_GPIOC_ODR (PIN_ODR_PUSHPULL(GPIOC_PIN0) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN1) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN2) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN3) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN4) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN5) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN6) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN7) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN8) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN9) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN10) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN11) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN12) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN13) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN14) | \ + PIN_ODR_PUSHPULL(GPIOC_PIN15)) +#define VAL_GPIOC_DRVR (PIN_DRVR_4MA(GPIOC_PIN0) | \ + PIN_DRVR_4MA(GPIOC_PIN1) | \ + PIN_DRVR_4MA(GPIOC_PIN2) | \ + PIN_DRVR_4MA(GPIOC_PIN3) | \ + PIN_DRVR_4MA(GPIOC_PIN4) | \ + PIN_DRVR_4MA(GPIOC_PIN5) | \ + PIN_DRVR_4MA(GPIOC_PIN6) | \ + PIN_DRVR_4MA(GPIOC_PIN7) | \ + PIN_DRVR_4MA(GPIOC_PIN8) | \ + PIN_DRVR_4MA(GPIOC_PIN9) | \ + PIN_DRVR_4MA(GPIOC_PIN10) | \ + PIN_DRVR_4MA(GPIOC_PIN11) | \ + PIN_DRVR_4MA(GPIOC_PIN12) | \ + PIN_DRVR_4MA(GPIOC_PIN13) | \ + PIN_DRVR_4MA(GPIOC_PIN14) | \ + PIN_DRVR_4MA(GPIOC_PIN15)) +#define VAL_GPIOC_AFCFGR0 (PIN_AFIO_AF(GPIOC_PIN0, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN1, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN2, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN3, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN4, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN5, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN6, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN7, AFIO_GPIO)) +#define VAL_GPIOC_AFCFGR1 (PIN_AFIO_AF(GPIOC_PIN0, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN8, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN9, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN10, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN11, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN12, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN13, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN14, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOC_PIN15, AFIO_GPIO)) + +/* + * Port D setup. + * Everything GPIO input with pull-up + */ +#define VAL_GPIOD_DIRCR (PIN_MODE_INPUT(GPIOD_PIN0) | \ + PIN_MODE_INPUT(GPIOD_PIN1) | \ + PIN_MODE_INPUT(GPIOD_PIN2) | \ + PIN_MODE_INPUT(GPIOD_PIN3) | \ + PIN_MODE_INPUT(GPIOD_PIN4) | \ + PIN_MODE_INPUT(GPIOD_PIN5) | \ + PIN_MODE_INPUT(GPIOD_PIN6) | \ + PIN_MODE_INPUT(GPIOD_PIN7) | \ + PIN_MODE_INPUT(GPIOD_PIN8) | \ + PIN_MODE_INPUT(GPIOD_PIN9) | \ + PIN_MODE_INPUT(GPIOD_PIN10) | \ + PIN_MODE_INPUT(GPIOD_PIN11) | \ + PIN_MODE_INPUT(GPIOD_PIN12) | \ + PIN_MODE_INPUT(GPIOD_PIN13) | \ + PIN_MODE_INPUT(GPIOD_PIN14) | \ + PIN_MODE_INPUT(GPIOD_PIN15)) +#define VAL_GPIOD_INER (PIN_INPUT_ENABLE(GPIOD_PIN0) | \ + PIN_INPUT_ENABLE(GPIOD_PIN1) | \ + PIN_INPUT_ENABLE(GPIOD_PIN2) | \ + PIN_INPUT_ENABLE(GPIOD_PIN3) | \ + PIN_INPUT_ENABLE(GPIOD_PIN4) | \ + PIN_INPUT_ENABLE(GPIOD_PIN5) | \ + PIN_INPUT_ENABLE(GPIOD_PIN6) | \ + PIN_INPUT_ENABLE(GPIOD_PIN7) | \ + PIN_INPUT_ENABLE(GPIOD_PIN8) | \ + PIN_INPUT_ENABLE(GPIOD_PIN9) | \ + PIN_INPUT_ENABLE(GPIOD_PIN10) | \ + PIN_INPUT_ENABLE(GPIOD_PIN11) | \ + PIN_INPUT_ENABLE(GPIOD_PIN12) | \ + PIN_INPUT_ENABLE(GPIOD_PIN13) | \ + PIN_INPUT_ENABLE(GPIOD_PIN14) | \ + PIN_INPUT_ENABLE(GPIOD_PIN15)) +#define VAL_GPIOD_PUR (PIN_PULLUP_ENABLE(GPIOD_PIN0) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN1) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN2) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN3) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN4) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN5) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN6) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN7) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN8) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN9) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN10) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN11) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN12) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN13) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN14) | \ + PIN_PULLUP_ENABLE(GPIOD_PIN15)) +#define VAL_GPIOD_PDR (PIN_PULLDOWN_DISABLE(GPIOD_PIN0) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN1) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN2) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN3) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN4) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN5) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN6) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN7) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN8) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN9) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN10) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN11) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN12) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN13) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN14) | \ + PIN_PULLDOWN_DISABLE(GPIOD_PIN15)) +#define VAL_GPIOD_ODR (PIN_ODR_PUSHPULL(GPIOD_PIN0) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN1) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN2) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN3) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN4) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN5) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN6) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN7) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN8) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN9) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN10) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN11) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN12) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN13) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN14) | \ + PIN_ODR_PUSHPULL(GPIOD_PIN15)) +#define VAL_GPIOD_DRVR (PIN_DRVR_4MA(GPIOD_PIN0) | \ + PIN_DRVR_4MA(GPIOD_PIN1) | \ + PIN_DRVR_4MA(GPIOD_PIN2) | \ + PIN_DRVR_4MA(GPIOD_PIN3) | \ + PIN_DRVR_4MA(GPIOD_PIN4) | \ + PIN_DRVR_4MA(GPIOD_PIN5) | \ + PIN_DRVR_4MA(GPIOD_PIN6) | \ + PIN_DRVR_4MA(GPIOD_PIN7) | \ + PIN_DRVR_4MA(GPIOD_PIN8) | \ + PIN_DRVR_4MA(GPIOD_PIN9) | \ + PIN_DRVR_4MA(GPIOD_PIN10) | \ + PIN_DRVR_4MA(GPIOD_PIN11) | \ + PIN_DRVR_4MA(GPIOD_PIN12) | \ + PIN_DRVR_4MA(GPIOD_PIN13) | \ + PIN_DRVR_4MA(GPIOD_PIN14) | \ + PIN_DRVR_4MA(GPIOD_PIN15)) +#define VAL_GPIOD_AFCFGR0 (PIN_AFIO_AF(GPIOD_PIN0, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN1, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN2, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN3, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN4, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN5, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN6, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN7, AFIO_GPIO)) +#define VAL_GPIOD_AFCFGR1 (PIN_AFIO_AF(GPIOD_PIN0, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN8, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN9, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN10, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN11, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN12, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN13, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN14, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOD_PIN15, AFIO_GPIO)) + +/* + * Port E setup. + * Everything GPIO input with pull-up + */ +#define VAL_GPIOE_DIRCR (PIN_MODE_INPUT(GPIOE_PIN0) | \ + PIN_MODE_INPUT(GPIOE_PIN1) | \ + PIN_MODE_INPUT(GPIOE_PIN2) | \ + PIN_MODE_INPUT(GPIOE_PIN3) | \ + PIN_MODE_INPUT(GPIOE_PIN4) | \ + PIN_MODE_INPUT(GPIOE_PIN5) | \ + PIN_MODE_INPUT(GPIOE_PIN6) | \ + PIN_MODE_INPUT(GPIOE_PIN7) | \ + PIN_MODE_INPUT(GPIOE_PIN8) | \ + PIN_MODE_INPUT(GPIOE_PIN9) | \ + PIN_MODE_INPUT(GPIOE_PIN10) | \ + PIN_MODE_INPUT(GPIOE_PIN11) | \ + PIN_MODE_INPUT(GPIOE_PIN12) | \ + PIN_MODE_INPUT(GPIOE_PIN13) | \ + PIN_MODE_INPUT(GPIOE_PIN14) | \ + PIN_MODE_INPUT(GPIOE_PIN15)) +#define VAL_GPIOE_INER (PIN_INPUT_ENABLE(GPIOE_PIN0) | \ + PIN_INPUT_ENABLE(GPIOE_PIN1) | \ + PIN_INPUT_ENABLE(GPIOE_PIN2) | \ + PIN_INPUT_ENABLE(GPIOE_PIN3) | \ + PIN_INPUT_ENABLE(GPIOE_PIN4) | \ + PIN_INPUT_ENABLE(GPIOE_PIN5) | \ + PIN_INPUT_ENABLE(GPIOE_PIN6) | \ + PIN_INPUT_ENABLE(GPIOE_PIN7) | \ + PIN_INPUT_ENABLE(GPIOE_PIN8) | \ + PIN_INPUT_ENABLE(GPIOE_PIN9) | \ + PIN_INPUT_ENABLE(GPIOE_PIN10) | \ + PIN_INPUT_ENABLE(GPIOE_PIN11) | \ + PIN_INPUT_ENABLE(GPIOE_PIN12) | \ + PIN_INPUT_ENABLE(GPIOE_PIN13) | \ + PIN_INPUT_ENABLE(GPIOE_PIN14) | \ + PIN_INPUT_ENABLE(GPIOE_PIN15)) +#define VAL_GPIOE_PUR (PIN_PULLUP_ENABLE(GPIOE_PIN0) | \ + PIN_PULLUP_ENABLE(GPIOE_PIN1) | \ + PIN_PULLUP_ENABLE(GPIOE_PIN2) | \ + PIN_PULLUP_ENABLE(GPIOE_PIN3) | \ + PIN_PULLUP_ENABLE(GPIOE_PIN4) | \ + PIN_PULLUP_ENABLE(GPIOE_PIN5) | \ + PIN_PULLUP_ENABLE(GPIOE_PIN6) | \ + PIN_PULLUP_ENABLE(GPIOE_PIN7) | \ + PIN_PULLUP_ENABLE(GPIOE_PIN8) | \ + PIN_PULLUP_ENABLE(GPIOE_PIN9) | \ + PIN_PULLUP_ENABLE(GPIOE_PIN10) | \ + PIN_PULLUP_ENABLE(GPIOE_PIN11) | \ + PIN_PULLUP_ENABLE(GPIOE_PIN12) | \ + PIN_PULLUP_ENABLE(GPIOE_PIN13) | \ + PIN_PULLUP_ENABLE(GPIOE_PIN14) | \ + PIN_PULLUP_ENABLE(GPIOE_PIN15)) +#define VAL_GPIOE_PDR (PIN_PULLDOWN_DISABLE(GPIOE_PIN0) | \ + PIN_PULLDOWN_DISABLE(GPIOE_PIN1) | \ + PIN_PULLDOWN_DISABLE(GPIOE_PIN2) | \ + PIN_PULLDOWN_DISABLE(GPIOE_PIN3) | \ + PIN_PULLDOWN_DISABLE(GPIOE_PIN4) | \ + PIN_PULLDOWN_DISABLE(GPIOE_PIN5) | \ + PIN_PULLDOWN_DISABLE(GPIOE_PIN6) | \ + PIN_PULLDOWN_DISABLE(GPIOE_PIN7) | \ + PIN_PULLDOWN_DISABLE(GPIOE_PIN8) | \ + PIN_PULLDOWN_DISABLE(GPIOE_PIN9) | \ + PIN_PULLDOWN_DISABLE(GPIOE_PIN10) | \ + PIN_PULLDOWN_DISABLE(GPIOE_PIN11) | \ + PIN_PULLDOWN_DISABLE(GPIOE_PIN12) | \ + PIN_PULLDOWN_DISABLE(GPIOE_PIN13) | \ + PIN_PULLDOWN_DISABLE(GPIOE_PIN14) | \ + PIN_PULLDOWN_DISABLE(GPIOE_PIN15)) +#define VAL_GPIOE_ODR (PIN_ODR_PUSHPULL(GPIOE_PIN0) | \ + PIN_ODR_PUSHPULL(GPIOE_PIN1) | \ + PIN_ODR_PUSHPULL(GPIOE_PIN2) | \ + PIN_ODR_PUSHPULL(GPIOE_PIN3) | \ + PIN_ODR_PUSHPULL(GPIOE_PIN4) | \ + PIN_ODR_PUSHPULL(GPIOE_PIN5) | \ + PIN_ODR_PUSHPULL(GPIOE_PIN6) | \ + PIN_ODR_PUSHPULL(GPIOE_PIN7) | \ + PIN_ODR_PUSHPULL(GPIOE_PIN8) | \ + PIN_ODR_PUSHPULL(GPIOE_PIN9) | \ + PIN_ODR_PUSHPULL(GPIOE_PIN10) | \ + PIN_ODR_PUSHPULL(GPIOE_PIN11) | \ + PIN_ODR_PUSHPULL(GPIOE_PIN12) | \ + PIN_ODR_PUSHPULL(GPIOE_PIN13) | \ + PIN_ODR_PUSHPULL(GPIOE_PIN14) | \ + PIN_ODR_PUSHPULL(GPIOE_PIN15)) +#define VAL_GPIOE_DRVR (PIN_DRVR_4MA(GPIOE_PIN0) | \ + PIN_DRVR_4MA(GPIOE_PIN1) | \ + PIN_DRVR_4MA(GPIOE_PIN2) | \ + PIN_DRVR_4MA(GPIOE_PIN3) | \ + PIN_DRVR_4MA(GPIOE_PIN4) | \ + PIN_DRVR_4MA(GPIOE_PIN5) | \ + PIN_DRVR_4MA(GPIOE_PIN6) | \ + PIN_DRVR_4MA(GPIOE_PIN7) | \ + PIN_DRVR_4MA(GPIOE_PIN8) | \ + PIN_DRVR_4MA(GPIOE_PIN9) | \ + PIN_DRVR_4MA(GPIOE_PIN10) | \ + PIN_DRVR_4MA(GPIOE_PIN11) | \ + PIN_DRVR_4MA(GPIOE_PIN12) | \ + PIN_DRVR_4MA(GPIOE_PIN13) | \ + PIN_DRVR_4MA(GPIOE_PIN14) | \ + PIN_DRVR_4MA(GPIOE_PIN15)) +#define VAL_GPIOE_AFCFGR0 (PIN_AFIO_AF(GPIOE_PIN0, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOE_PIN1, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOE_PIN2, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOE_PIN3, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOE_PIN4, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOE_PIN5, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOE_PIN6, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOE_PIN7, AFIO_GPIO)) +#define VAL_GPIOE_AFCFGR1 (PIN_AFIO_AF(GPIOE_PIN0, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOE_PIN8, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOE_PIN9, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOE_PIN10, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOE_PIN11, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOE_PIN12, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOE_PIN13, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOE_PIN14, AFIO_GPIO) | \ + PIN_AFIO_AF(GPIOE_PIN15, AFIO_GPIO)) + +/* + * EXTI setup. + */ +#define VAL_ESSR0 0x00000000 +#define VAL_ESSR1 0x00000000 + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ diff --git a/os/hal/boards/HT_HT32F1655_6/board.mk b/os/hal/boards/HT_HT32F1655_6/board.mk new file mode 100644 index 0000000000..96ce816866 --- /dev/null +++ b/os/hal/boards/HT_HT32F1655_6/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files. +BOARDSRC = $(CHIBIOS_CONTRIB)/os/hal/boards/HT_HT32F1655_6/board.c + +# Required include directories +BOARDINC = $(CHIBIOS_CONTRIB)/os/hal/boards/HT_HT32F1655_6 + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC) From 8a560acd96fcb3561ae972ca003d28a277038df0 Mon Sep 17 00:00:00 2001 From: Hansem Ro Date: Tue, 7 May 2024 00:17:46 -0700 Subject: [PATCH 10/19] HT32: fix PIN_DRVR_8MA macro --- os/hal/boards/HT_HT32F1653_4/board.h | 2 +- os/hal/boards/HT_HT32F1655_6/board.h | 2 +- os/hal/boards/HT_HT32F52342_52/board.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/os/hal/boards/HT_HT32F1653_4/board.h b/os/hal/boards/HT_HT32F1653_4/board.h index 29f6e3cd7f..b414dc3cba 100644 --- a/os/hal/boards/HT_HT32F1653_4/board.h +++ b/os/hal/boards/HT_HT32F1653_4/board.h @@ -124,7 +124,7 @@ #define PIN_ODR_PUSHPULL(n) (0U << (n)) #define PIN_ODR_OPENDRAIN(n) (1U << (n)) #define PIN_DRVR_4MA(n) (0U << (n)) -#define PIN_DRVR_8MA(n) (0U << (n)) +#define PIN_DRVR_8MA(n) (1U << (n)) #define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) /* diff --git a/os/hal/boards/HT_HT32F1655_6/board.h b/os/hal/boards/HT_HT32F1655_6/board.h index fe9ec9c876..52ef5709d4 100644 --- a/os/hal/boards/HT_HT32F1655_6/board.h +++ b/os/hal/boards/HT_HT32F1655_6/board.h @@ -141,7 +141,7 @@ #define PIN_ODR_PUSHPULL(n) (0U << (n)) #define PIN_ODR_OPENDRAIN(n) (1U << (n)) #define PIN_DRVR_4MA(n) (0U << (n)) -#define PIN_DRVR_8MA(n) (0U << (n)) +#define PIN_DRVR_8MA(n) (1U << (n)) #define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) /* diff --git a/os/hal/boards/HT_HT32F52342_52/board.h b/os/hal/boards/HT_HT32F52342_52/board.h index bcbef1902f..2cca557957 100644 --- a/os/hal/boards/HT_HT32F52342_52/board.h +++ b/os/hal/boards/HT_HT32F52342_52/board.h @@ -124,7 +124,7 @@ #define PIN_ODR_PUSHPULL(n) (0U << (n)) #define PIN_ODR_OPENDRAIN(n) (1U << (n)) #define PIN_DRVR_4MA(n) (0U << (n)) -#define PIN_DRVR_8MA(n) (0U << (n)) +#define PIN_DRVR_8MA(n) (1U << (n)) #define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) /* From 374133dfca2e757659b3927dc5b4bf44eb367378 Mon Sep 17 00:00:00 2001 From: liuhy Date: Tue, 7 May 2024 19:07:26 +0800 Subject: [PATCH 11/19] update library. --- os/common/ext/CMSIS/ES32/FS026/md/md_adc.c | 3 +- os/common/ext/CMSIS/ES32/FS026/md/md_i2c.c | 2 - os/common/ext/CMSIS/ES32/FS026/md/md_rcu.c | 89 +++++++++++++++---- .../ARMCMx/compilers/GCC/mk/startup_FS026.mk | 5 ++ 4 files changed, 79 insertions(+), 20 deletions(-) diff --git a/os/common/ext/CMSIS/ES32/FS026/md/md_adc.c b/os/common/ext/CMSIS/ES32/FS026/md/md_adc.c index 62b5d702fc..51a7233275 100644 --- a/os/common/ext/CMSIS/ES32/FS026/md/md_adc.c +++ b/os/common/ext/CMSIS/ES32/FS026/md/md_adc.c @@ -161,7 +161,7 @@ void md_adc_sequence_conversion(ADC_TypeDef *ADCx, md_adc_initial *ADC_InitStruc ErrorStatus md_adc_software_calibration(ADC_TypeDef *ADCx, md_adc_initial *ADC_InitStruct) { //ADC input APB clock 12MHz - uint8_t clkdiv; + uint8_t clkdiv = 1; uint16_t adc_data_1 = 0; uint16_t adc_data_15 = 0; @@ -277,6 +277,7 @@ ErrorStatus md_adc_optionbyte_calibration(ADC_TypeDef *ADCx, md_adc_initial *ADC md_adc_enable_adcpower(ADCx); md_adc_set_gain_factor(ADCx, adc_gain); md_adc_set_offset_factor(ADCx, adc_offset); + (void)ADC_InitStruct; return SUCCESS; } diff --git a/os/common/ext/CMSIS/ES32/FS026/md/md_i2c.c b/os/common/ext/CMSIS/ES32/FS026/md/md_i2c.c index 1250d912af..406fec98af 100644 --- a/os/common/ext/CMSIS/ES32/FS026/md/md_i2c.c +++ b/os/common/ext/CMSIS/ES32/FS026/md/md_i2c.c @@ -337,8 +337,6 @@ void md_i2c_slave_receive(I2C_TypeDef *I2Cx, uint32_t Num, uint8_t *rxbuf) while (!(md_i2c_is_active_flag_busy(I2Cx))); - printf("I2C1->STAT:%x\r\n", I2C1->STAT); - while (Num > 0) { while (!(md_i2c_is_active_flag_rxne(I2Cx))); diff --git a/os/common/ext/CMSIS/ES32/FS026/md/md_rcu.c b/os/common/ext/CMSIS/ES32/FS026/md/md_rcu.c index 3ec9800814..a058f372f8 100644 --- a/os/common/ext/CMSIS/ES32/FS026/md/md_rcu.c +++ b/os/common/ext/CMSIS/ES32/FS026/md/md_rcu.c @@ -151,39 +151,28 @@ void md_rcu_sys_init(RCU_TypeDef *rcu, md_rcu_init_typedef *RCU_InitStruct) { uint32_t PLL0_Frequency; uint32_t PLL0_Ref_Frequency; + uint32_t Current_Frequency; double fration; md_fc_set_read_latency(FC, MD_FC_WAIT_MORE_THAN_72Mhz); if (RCU_InitStruct->HS_Clock & RCU_CON_PLL0ON) md_rcu_enable_pll0(rcu); - else - md_rcu_disable_pll0(rcu); if (RCU_InitStruct->HS_Clock & RCU_CON_HRC48ON) md_rcu_enable_hrc48(rcu); - else - md_rcu_disable_hrc48(rcu); if (RCU_InitStruct->HS_Clock & RCU_CON_HOSCON) md_rcu_enable_hosc(rcu); - else - md_rcu_disable_hosc(rcu); if (RCU_InitStruct->HS_Clock & RCU_CON_HRCON) md_rcu_enable_hrc(rcu); - else - md_rcu_disable_hrc(rcu); if (RCU_InitStruct->LS_Clock & RCU_LCON_LOSCON) md_rcu_enable_losc(rcu); - else - md_rcu_disable_losc(rcu); if (RCU_InitStruct->LS_Clock & RCU_LCON_LRCON) md_rcu_enable_lrc(rcu); - else - md_rcu_disable_lrc(rcu); //make sure HOSC CLK Ready if ((RCU_InitStruct->HS_Clock & RCU_CON_HOSCON)) @@ -200,10 +189,7 @@ void md_rcu_sys_init(RCU_TypeDef *rcu, md_rcu_init_typedef *RCU_InitStruct) md_rcu_set_mco_div(rcu, RCU_InitStruct->Mpre); md_rcu_set_mco_source(rcu, RCU_InitStruct->Msw); - md_rcu_set_pclk_div(rcu, RCU_InitStruct->Ppre); - md_rcu_set_hclk_div(rcu, RCU_InitStruct->Hpre); - md_rcu_set_system_clock_source(rcu, RCU_InitStruct->Sw); - + switch ((RCU_InitStruct->PllSrc)) { case MD_RCU_PLLSRC_HRC : @@ -227,9 +213,58 @@ void md_rcu_sys_init(RCU_TypeDef *rcu, md_rcu_init_typedef *RCU_InitStruct) fration = (double)md_rcu_get_pll0_fn(rcu) + ((double)md_rcu_get_pll0_fk(rcu) / (1 << 19)); PLL0_Frequency = (uint32_t)(PLL0_Ref_Frequency * fration / (1 << (md_rcu_get_pll0_fm(rcu) + 3))); - /* System Frequency */ + /* + Determine whether it is a PLL that needs to be switched. + If it is a PLL, it is a frequency increase buffering process. + Otherwise, if it is not a PLL, it is a frequency decrease buffering process. + */ + if(RCU_InitStruct->Sw==MD_RCU_SW_SYSCLK_PLL0) + { + /* + PLL frequency rise buffer processing, the trigger environment is when it is necessary to + switch to the PLL frequency greater than or equal to 48M, if the current or set HCLK prescaler is 1, + the HCLK prescaler will be set to 2 first and then the system frequency will be switched. + After the switch is completed Will wait for 10us before resetting the HCLK prescaler. + */ + if((PLL0_Frequency>=48000000) && + ((md_rcu_get_hclk_div(RCU)==MD_RCU_HPRE_SYSCLK_DIV_1)|| + (RCU_InitStruct->Hpre==MD_RCU_HPRE_SYSCLK_DIV_1))) + { + SystemFrequency_AHBClk = PLL0_Frequency>>1; + md_tick_init(MD_SYSTICK_CLKSRC_HCLK); + md_rcu_set_hclk_div(rcu,MD_RCU_HPRE_SYSCLK_DIV_2); + md_rcu_set_system_clock_source(rcu, RCU_InitStruct->Sw); + md_tick_wait10us(1,1); + } + } + else + { + /* + PLL frequency reduction buffer processing, the triggering environment is when it is not + necessary to switch the PLL frequency and the current system frequency is higher than 48M, + the HCLK prescaler will first be set to 2 to reduce the HCLK speed, and then the system frequency + will be switched to a low frequency after the reduction is completed. Finally reset the + HCLK prescaler. + */ + Current_Frequency = md_rcu_get_current_system_frequency(RCU)*1000000; + if(Current_Frequency>=48000000) + { + SystemFrequency_AHBClk = Current_Frequency>>1; + md_tick_init(MD_SYSTICK_CLKSRC_HCLK); + md_rcu_set_hclk_div(rcu,MD_RCU_HPRE_SYSCLK_DIV_2); + md_tick_wait10us(1,1); + } + } + + md_rcu_set_system_clock_source(rcu, RCU_InitStruct->Sw); + + md_rcu_set_hclk_div(rcu, RCU_InitStruct->Hpre); + + md_rcu_set_pclk_div(rcu, RCU_InitStruct->Ppre); + switch (md_rcu_get_current_system_clock(rcu)) /* System clock switch(SYSCLK) */ { + case MD_RCU_SWS_SYSCLK_HRC: /*================= HRC selected as system clock*/ SystemCoreClock = (uint32_t)(__HRC); break; @@ -283,6 +318,26 @@ void md_rcu_sys_init(RCU_TypeDef *rcu, md_rcu_init_typedef *RCU_InitStruct) md_fc_set_read_latency(FC, MD_FC_WAIT_BETWEEN_24MHz_AND_48Mhz); else md_fc_set_read_latency(FC, MD_FC_WAIT_LESS_THAN_24MHz); + + if (!(RCU_InitStruct->HS_Clock & RCU_CON_PLL0ON)) + md_rcu_disable_pll0(rcu); + + if (!(RCU_InitStruct->HS_Clock & RCU_CON_HRC48ON)) + md_rcu_disable_hrc48(rcu); + + if (!(RCU_InitStruct->HS_Clock & RCU_CON_HOSCON)) + md_rcu_disable_hosc(rcu); + + if (!(RCU_InitStruct->HS_Clock & RCU_CON_HRCON)) + md_rcu_disable_hrc(rcu); + + if (!(RCU_InitStruct->LS_Clock & RCU_LCON_LOSCON)) + md_rcu_disable_losc(rcu); + + if (!(RCU_InitStruct->LS_Clock & RCU_LCON_LRCON)) + md_rcu_disable_lrc(rcu); + + md_tick_init(MD_SYSTICK_CLKSRC_HCLK); } /** diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_FS026.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_FS026.mk index 00335d09a4..045883cc7a 100644 --- a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_FS026.mk +++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_FS026.mk @@ -6,6 +6,11 @@ STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \ $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/FS026/md/md_rcu.c \ $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/FS026/md/md_gpio.c \ $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/FS026/md/md_uart.c \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/FS026/md/md_spi.c \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/FS026/md/md_adc.c \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/FS026/md/md_i2c.c \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/FS026/md/md_wwdt.c \ + $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/FS026/md/md_dma.c \ $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/ES32/FS026/ald/ald_usb.c STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S \ From 9a62c298d11de85ba6bb709c1196aa3efd558972 Mon Sep 17 00:00:00 2001 From: liuhy Date: Tue, 7 May 2024 19:13:19 +0800 Subject: [PATCH 12/19] update hal. --- os/hal/ports/ES32/FS026/hal_lld.c | 100 ++++------- os/hal/ports/ES32/FS026/hal_lld.h | 49 +++++- os/hal/ports/ES32/LLD/SPIv1/hal_spi_lld.c | 54 +++--- os/hal/ports/ES32/LLD/SPIv1/hal_spi_lld.h | 25 ++- os/hal/ports/ES32/LLD/UARTv1/hal_serial_lld.c | 161 +++++++++++++++++- os/hal/ports/ES32/LLD/UARTv1/hal_serial_lld.h | 24 ++- os/hal/ports/ES32/LLD/USBv1/hal_usb_lld.c | 132 +++++++++++--- os/hal/ports/ES32/LLD/USBv1/hal_usb_lld.h | 10 +- 8 files changed, 411 insertions(+), 144 deletions(-) diff --git a/os/hal/ports/ES32/FS026/hal_lld.c b/os/hal/ports/ES32/FS026/hal_lld.c index a0cea4cc50..ca62a745b7 100644 --- a/os/hal/ports/ES32/FS026/hal_lld.c +++ b/os/hal/ports/ES32/FS026/hal_lld.c @@ -59,64 +59,39 @@ unsigned int PLL0Frequency; /*===========================================================================*/ /* Driver exported functions. */ /*===========================================================================*/ - -void HardFault_Handler(void) +#if ES32_NO_INIT +__attribute__((weak)) void hal_lld_init(void) { - while(1); + } - -uint32_t g_es_systick_time = 0U; - -int es_test_printf(char *pBuffer, int size) +#else +void HardFault_Handler(void) { - for (int i = 0; i < size; i++) - { - while (!((UART1->STAT) & (UART_STAT_TFEMPTY))); // Tx FIFO empty - UART1->TXDATA = pBuffer[i]; // Sent byte - } - - return size; -} - -void gpio_config(void){ - md_gpio_inittypedef gpiox; - /* config gpiob pin6 (Tx) */ - gpiox.Pin = MD_GPIO_PIN_6; - gpiox.Mode = MD_GPIO_MODE_FUNCTION; - gpiox.OutputType = MD_GPIO_OUTPUT_PUSHPULL; - gpiox.Pull = MD_GPIO_PULL_FLOATING; - gpiox.OutDrive = MD_GPIO_DRIVING_8MA; - gpiox.Function = MD_GPIO_AF2; - md_gpio_init(GPIOB, &gpiox); - /* config gpiob pin7 (Rx) */ - gpiox.Pin = MD_GPIO_PIN_7; - gpiox.Mode = MD_GPIO_MODE_FUNCTION; - gpiox.OutputType = MD_GPIO_OUTPUT_PUSHPULL; - gpiox.Pull = MD_GPIO_PULL_UP; - gpiox.OutDrive = MD_GPIO_DRIVING_8MA; - gpiox.Function = MD_GPIO_AF2; - md_gpio_init(GPIOB, &gpiox); + while(1); } -md_rcu_init_typedef rcu_initStruct = /**< RCU init structure */ +const md_rcu_init_typedef rcu_initStruct = /**< RCU init structure */ { MD_RCU_MPRE_MCO_DIV1, MD_RCU_MSW_MCO_DISABLE, - MD_RCU_PLLSRC_HRC48, - MD_RCU_PLLCLK_72M, - MD_RCU_PPRE_HCLK_DIV_1, - MD_RCU_HPRE_SYSCLK_DIV_1, - MD_RCU_SW_SYSCLK_PLL0, - (RCU_CON_HRCON | RCU_CON_PLL0ON | RCU_CON_HRC48ON_MSK), -}; - -md_uart_init_typedef uart_initStruct = /**< UART init structure */ -{ - (921600U), - MD_UART_LCON_LSB_FIRST, - MD_UART_LCON_PS_NONE, - MD_UART_LCON_STOP_1, - MD_UART_LCON_DLS_8, + ES32_PLL_SOURSE_SELECT, + ES32_PLL_CLK_FREQ, + ES32_BUS_DIV_PPRE, + ES32_BUS_DIV_HPRE, + ES32_SYSCLK_SOURSE_SELECT, +#if ES32_PLL_CLK_EN +#if ES32_HOSC_CLK_EN + (RCU_CON_HRCON | RCU_CON_HRC48ON_MSK | RCU_CON_PLL0ON | RCU_CON_HOSCON), +#else + (RCU_CON_HRCON | RCU_CON_HRC48ON_MSK | RCU_CON_PLL0ON), +#endif +#else +#if ES32_HOSC_CLK_EN + (RCU_CON_HRCON | RCU_CON_HRC48ON_MSK | RCU_CON_HOSCON), +#else + (RCU_CON_HRCON | RCU_CON_HRC48ON_MSK), +#endif +#endif }; /** @@ -127,26 +102,23 @@ md_uart_init_typedef uart_initStruct = /**< UART init structure */ void hal_lld_init(void) { __disable_irq(); - md_rcu_pll0_init(RCU, &rcu_initStruct); - md_rcu_sys_init(RCU, &rcu_initStruct); +#if ES32_PLL_CLK_EN + md_rcu_pll0_init(RCU, (md_rcu_init_typedef*)(&rcu_initStruct)); +#endif + md_rcu_sys_init(RCU, (md_rcu_init_typedef*)(&rcu_initStruct)); md_rcu_enable_gpioa(RCU); md_rcu_enable_gpiob(RCU); md_rcu_enable_gpioc(RCU); md_rcu_enable_gpiod(RCU); - md_rcu_enable_uart1(RCU); md_rcu_enable_usb(RCU); - gpio_config(); - -// NVIC->ICER[0] = 0xFFFFFFFFUL; -// md_tick_init(MD_SYSTICK_CLKSRC_HCLK); -// md_mcu_irq_config(UART1_IRQn, 2, ENABLE); - md_uart_init(UART1, &uart_initStruct); -// md_uart_enable_it_rfnempty(UART1); - +#if ES32_USE_USB_SOF_TRIM_HRC48 + /*Using USB_SOF to calibrate the internal clock*/ + md_rcu_enable_csu(RCU); + CSU->CON |= CSU_CON_AUTOEN_MSK; + CSU->CON |= CSU_CON_CNTEN_MSK; +#endif __enable_irq(); - - es_test_printf("hal_lld_init ok\r\n",sizeof("hal_lld_init ok\r\n")); - } +#endif /** @} */ diff --git a/os/hal/ports/ES32/FS026/hal_lld.h b/os/hal/ports/ES32/FS026/hal_lld.h index dc4fa2a6cd..ed25e7b2e8 100644 --- a/os/hal/ports/ES32/FS026/hal_lld.h +++ b/os/hal/ports/ES32/FS026/hal_lld.h @@ -48,6 +48,53 @@ * @name PLATFORM configuration options * @{ */ +/** + * @brief Disables the PWR/RCC initialization in the HAL. + */ +#if !defined(ES32_NO_INIT) || defined(__DOXYGEN__) +#define ES32_NO_INIT FALSE +#endif + +/** + * @brief system_clk select. + */ +#if !defined(ES32_SYSCLK_SOURSE_SELECT) || defined(__DOXYGEN__) +#define ES32_SYSCLK_SOURSE_SELECT MD_RCU_SW_SYSCLK_HRC48 +#endif + +/** + * @brief external clk config. + */ +#if !defined(ES32_HOSC_CLK_EN) || defined(__DOXYGEN__) +#define ES32_HOSC_CLK_EN FALSE +#endif + +/** + * @brief pll clk config. + */ +#if !defined(ES32_PLL_CLK_EN) || defined(__DOXYGEN__) +#define ES32_PLL_CLK_EN FALSE +#endif + +#if !defined(ES32_PLL_SOURSE_SELECT) || defined(__DOXYGEN__) +#define ES32_PLL_SOURSE_SELECT MD_RCU_PLLSRC_HRC48 +#endif + +#if !defined(ES32_PLL_CLK_FREQ) || defined(__DOXYGEN__) +#define ES32_PLL_CLK_FREQ MD_RCU_PLLCLK_72M +#endif + +/** + * @brief bus clk config. + */ +#if !defined(ES32_BUS_DIV_HPRE) || defined(__DOXYGEN__) +#define ES32_BUS_DIV_HPRE MD_RCU_HPRE_SYSCLK_DIV_1 +#endif + +#if !defined(ES32_BUS_DIV_PPRE) || defined(__DOXYGEN__) +#define ES32_BUS_DIV_PPRE MD_RCU_PPRE_HCLK_DIV_1 +#endif + /** @} */ /*===========================================================================*/ @@ -70,7 +117,7 @@ extern "C" { #endif void hal_lld_init(void); -void ht32_clock_init(void); +void es32_clock_init(void); #ifdef __cplusplus } #endif diff --git a/os/hal/ports/ES32/LLD/SPIv1/hal_spi_lld.c b/os/hal/ports/ES32/LLD/SPIv1/hal_spi_lld.c index c3db92cac7..408e6b7f53 100644 --- a/os/hal/ports/ES32/LLD/SPIv1/hal_spi_lld.c +++ b/os/hal/ports/ES32/LLD/SPIv1/hal_spi_lld.c @@ -35,16 +35,18 @@ /* Driver exported variables. */ /*===========================================================================*/ -/** - * @brief SPI0 driver identifier. - */ -#if (ES32_SPI_USE_SPI0 == TRUE) || defined(__DOXYGEN__) - SPIDriver SPID0; + +/** @brief SPI1 driver identifier.*/ +#if STM32_SPI_USE_SPI1 || defined(__DOXYGEN__) +SPIDriver SPID1; #endif -#if (ES32_SPI_USE_SPI1 == TRUE) || defined(__DOXYGEN__) - SPIDriver SPID1; + +/** @brief SPI2 driver identifier.*/ +#if STM32_SPI_USE_SPI2 || defined(__DOXYGEN__) +SPIDriver SPID2; #endif + /*===========================================================================*/ /* Driver local variables and types. */ /*===========================================================================*/ @@ -53,7 +55,7 @@ /* Driver local functions. */ /*===========================================================================*/ -#if (ES32_SPI_USE_SPI0 == TRUE) || (ES32_SPI_USE_SPI1 == TRUE) || defined(__DOXYGEN__) +#if (ES32_SPI_USE_SPI1 == TRUE) || (ES32_SPI_USE_SPI2 == TRUE) || defined(__DOXYGEN__) static void spi_lld_rx(SPIDriver *const spip) { uint32_t fd; @@ -184,20 +186,20 @@ void spi_lld_start(SPIDriver *spip) if (spip->state == SPI_STOP) { /* Enables the peripheral.*/ -#if ES32_SPI_USE_SPI0 == TRUE - if (&SPID0 == spip) +#if ES32_SPI_USE_SPI1 == TRUE + if (&SPID1 == spip) { - CKCU->APBCCR0 |= CKCU_APBCCR0_SPI0EN; - nvicEnableVector(SPI0_IRQn, ES32_SPI0_IRQ_PRIORITY); + md_rcu_enable_spi1(RCU); + nvicEnableVector(SPI1_IRQn, ES32_SPI1_IRQ_PRIORITY); } #endif -#if ES32_SPI_USE_SPI1 == TRUE +#if ES32_SPI_USE_SPI2 == TRUE - if (&SPID1 == spip) + if (&SPID2 == spip) { - CKCU->APBCCR0 |= CKCU_APBCCR0_SPI1EN; - nvicEnableVector(SPI1_IRQn, ES32_SPI1_IRQ_PRIORITY); + md_rcu_enable_spi2(RCU); + nvicEnableVector(SPI2_IRQn, ES32_SPI2_IRQ_PRIORITY); } #endif @@ -224,22 +226,18 @@ void spi_lld_stop(SPIDriver *spip) if (spip->state == SPI_READY) { /* Disables the peripheral.*/ -#if ES32_SPI_USE_SPI0 == TRUE - if (&SPID0 == spip) +#if ES32_SPI_USE_SPI1 == TRUE + if (&SPID1 == spip) { - RSTCU->APBPRSTR0 = RSTCU_APBPRSTR0_SPI0RST; - CKCU->APBCCR0 &= ~CKCU_APBCCR0_SPI0EN; - nvicDisableVector(SPI0_IRQn); + nvicDisableVector(SPI1_IRQn); } #endif -#if ES32_SPI_USE_SPI1 == TRUE +#if ES32_SPI_USE_SPI2 == TRUE - if (&SPID1 == spip) + if (&SPID2 == spip) { - RSTCU->APBPRSTR0 = RSTCU_APBPRSTR0_SPI1RST; - CKCU->APBCCR0 &= ~CKCU_APBCCR0_SPI1EN; - nvicDisableVector(SPI1_IRQn); + nvicDisableVector(SPI2_IRQn); } #endif @@ -255,7 +253,7 @@ void spi_lld_stop(SPIDriver *spip) */ void spi_lld_select(SPIDriver *spip) { - spip->SPI->CR0 |= SPI_CR0_SSELC; + /*hard control*/ } /** @@ -268,7 +266,7 @@ void spi_lld_select(SPIDriver *spip) */ void spi_lld_unselect(SPIDriver *spip) { - spip->SPI->CR0 &= ~SPI_CR0_SSELC; + /*hard control*/ } /** diff --git a/os/hal/ports/ES32/LLD/SPIv1/hal_spi_lld.h b/os/hal/ports/ES32/LLD/SPIv1/hal_spi_lld.h index 2dcab582ca..44e7bca4be 100644 --- a/os/hal/ports/ES32/LLD/SPIv1/hal_spi_lld.h +++ b/os/hal/ports/ES32/LLD/SPIv1/hal_spi_lld.h @@ -40,15 +40,21 @@ * @{ */ /** - * @brief SPI0 driver enable switch. + * @brief SPI1 driver enable switch. * @details If set to @p TRUE the support for SPI0 is included. * @note The default is @p FALSE. */ -#if !defined(ES32_SPI_USE_SPI0) || defined(__DOXYGEN__) - #define ES32_SPI_USE_SPI0 FALSE +#if !defined(STM32_SPI_USE_SPI1) || defined(__DOXYGEN__) +#define STM32_SPI_USE_SPI1 FALSE #endif -#if !defined(ES32_SPI_USE_SPI1) || defined(__DOXYGEN__) - #define ES32_SPI_USE_SPI1 FALSE + +/** + * @brief SPI2 driver enable switch. + * @details If set to @p TRUE the support for SPI2 is included. + * @note The default is @p FALSE. + */ +#if !defined(STM32_SPI_USE_SPI2) || defined(__DOXYGEN__) +#define STM32_SPI_USE_SPI2 FALSE #endif /** @} */ @@ -88,11 +94,12 @@ /* External declarations. */ /*===========================================================================*/ -#if (ES32_SPI_USE_SPI0 == TRUE) && !defined(__DOXYGEN__) - extern SPIDriver SPID0; +#if STM32_SPI_USE_SPI1 && !defined(__DOXYGEN__) +extern SPIDriver SPID1; #endif -#if (ES32_SPI_USE_SPI1 == TRUE) && !defined(__DOXYGEN__) - extern SPIDriver SPID1; + +#if STM32_SPI_USE_SPI2 && !defined(__DOXYGEN__) +extern SPIDriver SPID2; #endif #ifdef __cplusplus diff --git a/os/hal/ports/ES32/LLD/UARTv1/hal_serial_lld.c b/os/hal/ports/ES32/LLD/UARTv1/hal_serial_lld.c index 1a22d76c1e..77586b6c4a 100644 --- a/os/hal/ports/ES32/LLD/UARTv1/hal_serial_lld.c +++ b/os/hal/ports/ES32/LLD/UARTv1/hal_serial_lld.c @@ -34,6 +34,20 @@ /* Driver exported variables. */ /*===========================================================================*/ +/** @brief UART serial driver identifier.*/ +#if ES32_SERIAL_USE_UART1 || defined(__DOXYGEN__) +SerialDriver SD1; +#endif +#if ES32_SERIAL_USE_UART2 || defined(__DOXYGEN__) +SerialDriver SD2; +#endif +#if ES32_SERIAL_USE_UART3 || defined(__DOXYGEN__) +SerialDriver SD3; +#endif +#if ES32_SERIAL_USE_UART4 || defined(__DOXYGEN__) +SerialDriver SD4; +#endif + /*===========================================================================*/ /* Driver local variables and types. */ /*===========================================================================*/ @@ -47,26 +61,129 @@ static const SerialConfig default_config = {SERIAL_DEFAULT_BITRATE}; /* Driver local functions. */ /*===========================================================================*/ -static void load(SerialDriver *sdp) +static void serialInterrupt(SerialDriver *pSd) { - (void)sdp; + uint32_t isr_ifm = (pSd->usart)->IFM; + + (pSd->usart)->ICR = isr_ifm; + + while(((pSd->usart)->STAT) & (UART_STAT_RFNEMPTY_MSK)) + { + sdIncomingDataI(sdp, (pSd->usart)->RXDATA); + } + + if(isr_ifm & UART_IFM_TXE_MSK) + { + msg_t b; + osalSysLockFromISR(); + b = oqGetI(&sdp->oqueue); + if (b < MSG_OK) { + chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); + (pSd->usart)->IDR &= ~(UART_IER_TXE); + } + else + (pSd->usart)->IXDATA = b; + osalSysUnlockFromISR(); + } } -static void serialInterrupt(SerialDriver *pSd) +md_uart_init_typedef uart_initStruct = /**< UART init structure */ { - (void)pSd; -} + MD_UART_BAUDRATE_115200, + MD_UART_LCON_LSB_FIRST, + MD_UART_LCON_PS_NONE, + MD_UART_LCON_STOP_1, + MD_UART_LCON_DLS_8, +}; static void usartInit(SerialDriver *sdp, const SerialConfig *config) { - (void)sdp; - (void)config; + uart_initStruct.BaudRate = config->speed; + md_uart_init(sdp->usart, &uart_initStruct); + (sdp->usart)->IER = UART_IER_RFNEMPTY; +} + + +#if ES32_SERIAL_USE_UART1 || defined(__DOXYGEN__) +static void notify1(io_queue_t *qp) { + + (void)qp; + UART1->IER = UART_IER_TXE; +} +#endif + +#if ES32_SERIAL_USE_UART2 || defined(__DOXYGEN__) +static void notify2(io_queue_t *qp) { + + (void)qp; + UART2->IER = UART_IER_TXE; +} +#endif + +#if ES32_SERIAL_USE_UART3 || defined(__DOXYGEN__) +static void notify3(io_queue_t *qp) { + + (void)qp; + UART3->IER = UART_IER_TXE; +} +#endif + +#if ES32_SERIAL_USE_UART4 || defined(__DOXYGEN__) +static void notify4(io_queue_t *qp) { + + (void)qp; + UART4->IER = UART_IER_TXE; } +#endif + /*===========================================================================*/ /* Driver interrupt handlers. */ /*===========================================================================*/ +#if ES32_SERIAL_USE_UART1 || defined(__DOXYGEN__) +//UART1_HANDLER +OSAL_IRQ_HANDLER(VectorAC) { + + OSAL_IRQ_PROLOGUE(); + + serialInterrupt(&SD1); + + OSAL_IRQ_EPILOGUE(); +} +#endif +#if ES32_SERIAL_USE_UART2 || defined(__DOXYGEN__) +//UART2_HANDLER +OSAL_IRQ_HANDLER(VectorB0) { + + OSAL_IRQ_PROLOGUE(); + + serialInterrupt(&SD2); + + OSAL_IRQ_EPILOGUE(); +} +#endif +#if ES32_SERIAL_USE_UART3 || defined(__DOXYGEN__) +//UART3_HANDLER +OSAL_IRQ_HANDLER(VectorB4) { + + OSAL_IRQ_PROLOGUE(); + serialInterrupt(&SD3); + + OSAL_IRQ_EPILOGUE(); +} +#endif +#if ES32_SERIAL_USE_UART4 || defined(__DOXYGEN__) +//UART4_HANDLER +OSAL_IRQ_HANDLER(VectorB8) { + + OSAL_IRQ_PROLOGUE(); + + serialInterrupt(&SD4); + + OSAL_IRQ_EPILOGUE(); +} +#endif /*===========================================================================*/ /* Driver exported functions. */ /*===========================================================================*/ @@ -78,6 +195,34 @@ static void usartInit(SerialDriver *sdp, const SerialConfig *config) */ void sd_lld_init(void) { +#if ES32_SERIAL_USE_UART1 + md_rcu_enable_uart1(RCU); + sdObjectInit(&SD1, NULL, notify1); + SD1.usart = UART1; + nvicEnableVector(UART1_IRQn, ES32_SERIAL_UART1_PRIORITY); +#endif + +#if ES32_SERIAL_USE_UART2 + md_rcu_enable_uart2(RCU); + sdObjectInit(&SD2, NULL, notify2); + SD2.usart = UART2; + nvicEnableVector(UART2_IRQn, ES32_SERIAL_UART2_PRIORITY); +#endif + +#if ES32_SERIAL_USE_UART3 + md_rcu_enable_uart3(RCU); + sdObjectInit(&SD3, NULL, notify3); + SD3.usart = UART3; + nvicEnableVector(UART3_IRQn, ES32_SERIAL_UART3_PRIORITY); +#endif + +#if ES32_SERIAL_USE_UART4 + md_rcu_enable_uart4(RCU); + sdObjectInit(&SD4, NULL, notify4); + SD4.usart = UART4; + nvicEnableVector(UART4_IRQn, ES32_SERIAL_UART4_PRIORITY); +#endif + } @@ -99,7 +244,7 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) /** * @brief Low level serial driver stop. - * @details De-initializes the USART, stops the associated clock, resets the + * @details De-initializes the UART, stops the associated clock, resets the * interrupt vector. * * @param[in] sdp pointer to a @p SerialDriver object diff --git a/os/hal/ports/ES32/LLD/UARTv1/hal_serial_lld.h b/os/hal/ports/ES32/LLD/UARTv1/hal_serial_lld.h index 6ff1a2525f..85dc917d74 100644 --- a/os/hal/ports/ES32/LLD/UARTv1/hal_serial_lld.h +++ b/os/hal/ports/ES32/LLD/UARTv1/hal_serial_lld.h @@ -40,16 +40,16 @@ * @{ */ /** - * @brief USART0 driver enable switch. - * @details If set to @p TRUE the support for USART0 is included. + * @brief UART0 driver enable switch. + * @details If set to @p TRUE the support for UART0 is included. * @note The default is @p FALSE. */ -#if !defined(PLATFORM_SERIAL_USE_USART0) || defined(__DOXYGEN__) - #define PLATFORM_SERIAL_USE_USART0 FALSE +#if !defined(ES32_SERIAL_USE_UART1) || defined(__DOXYGEN__) + #define ES32_SERIAL_USE_UART1 FALSE #endif -#if !defined(PLATFORM_SERIAL_USE_USART1) || defined(__DOXYGEN__) - #define PLATFORM_SERIAL_USE_USART1 FALSE +#if !defined(ES32_SERIAL_USE_UART1) || defined(__DOXYGEN__) + #define ES32_SERIAL_USE_UART2 FALSE #endif /** @} */ @@ -104,12 +104,18 @@ typedef struct /* External declarations. */ /*===========================================================================*/ -#if (ES32_SERIAL_USE_USART0 == TRUE) && !defined(__DOXYGEN__) - extern SerialDriver SD0; -#endif #if (ES32_SERIAL_USE_USART1 == TRUE) && !defined(__DOXYGEN__) extern SerialDriver SD1; #endif +#if (ES32_SERIAL_USE_USART2 == TRUE) && !defined(__DOXYGEN__) + extern SerialDriver SD2; +#endif +#if (ES32_SERIAL_USE_USART3 == TRUE) && !defined(__DOXYGEN__) + extern SerialDriver SD3; +#endif +#if (ES32_SERIAL_USE_USART4 == TRUE) && !defined(__DOXYGEN__) + extern SerialDriver SD4; +#endif #ifdef __cplusplus extern "C" { diff --git a/os/hal/ports/ES32/LLD/USBv1/hal_usb_lld.c b/os/hal/ports/ES32/LLD/USBv1/hal_usb_lld.c index 20e24bea30..50369d76e7 100644 --- a/os/hal/ports/ES32/LLD/USBv1/hal_usb_lld.c +++ b/os/hal/ports/ES32/LLD/USBv1/hal_usb_lld.c @@ -52,11 +52,6 @@ /** True if the endpoint is an OUT endpoint */ #define USB_EP_DIR_IS_OUT(ep) (USB_EP_GET_DIR(ep) == USB_EP_DIR_OUT) - -extern char g_num_to_char_tx_buf[32]; -extern const char g_num_to_char_table[16]; -extern void ffffff(uint32_t data); - /** * @brief EP0 state. * @note It is an union because IN and OUT endpoints are never used at the @@ -154,6 +149,16 @@ struct musb_udc { struct musb_udc g_musb_udc; static volatile uint8_t usb_ep0_state = USB_EP0_STATE_SETUP; volatile bool zlp_flag = 0; +#if !defined(ES_NO_USB_SUSPEND) +volatile uint16_t g_es_frame_id_last = 0U; +volatile uint16_t g_es_frame_id_need_chang_times = 20U; +uint8_t g_es_usb_state = 0U; + +#if !defined(ES_NO_USB_SUSPEND_CB) +__attribute__((weak)) void es_usb_suspend_wakeup_init_user(void) {} +__attribute__((weak)) void es_usb_suspend_power_down_user(void) {} +#endif +#endif /*===========================================================================*/ /* Driver local definitions. */ @@ -430,12 +435,6 @@ int usbd_ep_start_write(const uint8_t ep, const uint8_t *data, uint32_t data_len { uint8_t ep_idx = USB_EP_GET_IDX(ep); uint8_t old_ep_idx; -// uint32_t wait_cnt; - -// if(ep_idx == 1) -// { -// ep_idx = 1; -// } if (!g_musb_udc.in_ep[ep_idx].ep_enable) return -2; @@ -650,7 +649,9 @@ OSAL_IRQ_HANDLER(VectorBC) uint8_t ep_idx; uint16_t write_count, read_count; uint8_t status; - +#if !defined(ES_NO_USB_SUSPEND) + uint16_t frame_id = ((USB->FRAME2) << 8) | (USB->FRAME1); +#endif USBDriver *usbp = &USBD1; OSAL_IRQ_PROLOGUE(); @@ -658,6 +659,10 @@ OSAL_IRQ_HANDLER(VectorBC) status = USB->IFM & 0x7F; USB->ICR = status; +#if !defined(ES_NO_USB_SUSPEND) + if(((USB->POWER)&ALD_USB_POWER_SUSPENDEN) == 0) + USB->POWER |= ALD_USB_POWER_SUSPENDEN; +#endif old_ep_idx = musb_get_active_ep(); /* Receive a reset signal from the USB bus */ @@ -683,6 +688,37 @@ OSAL_IRQ_HANDLER(VectorBC) if (status & (USB_IFM_SOFIFM_MSK)) { +#if !defined(ES_NO_USB_SUSPEND) + if(g_es_frame_id_need_chang_times) + { + if(frame_id != g_es_frame_id_last) + { + g_es_frame_id_last = frame_id; + g_es_frame_id_need_chang_times--; + } + else + { + g_es_frame_id_need_chang_times = 10; + } + } + else + { + if(((USB->POWER)&0x3) == 0x1) //suspend_en = 1,suspend_flag = 0 + { + USB->IDR = ALD_USB_INTCTRL_SOF; + + if(g_es_usb_state == 0) + { + g_es_usb_state = 1; + _usb_wakeup(usbp); + + #if !defined(ES_NO_USB_SUSPEND_CB) + es_usb_suspend_wakeup_init_user(); + #endif + } + } + } +#endif // _usb_isr_invoke_sof_cb(usbp); } @@ -700,7 +736,21 @@ OSAL_IRQ_HANDLER(VectorBC) if (status & USB_IFM_SUSPDIFM_MSK) { -// _usb_suspend(usbp); +#if !defined(ES_NO_USB_SUSPEND) + g_es_frame_id_need_chang_times = 10; + USB->IER = ALD_USB_INTCTRL_SOF; + + if(g_es_usb_state) + { + g_es_usb_state = 0; + + #if !defined(ES_NO_USB_SUSPEND_CB) + es_usb_suspend_power_down_user(); + #endif + + _usb_suspend(usbp); + } +#endif } while (USB->TXIFM) @@ -736,9 +786,9 @@ OSAL_IRQ_HANDLER(VectorBC) { USB->TXIDR = 1U << ep_idx; - /* Transfer completed, invokes the callback.*/ - usbp->epc[ep_idx]->in_state->txcnt = g_musb_udc.in_ep[ep_idx].actual_xfer_len; - _usb_isr_invoke_in_cb(usbp, ep_idx); + /* Transfer completed, invokes the callback.*/ + usbp->epc[ep_idx]->in_state->txcnt = g_musb_udc.in_ep[ep_idx].actual_xfer_len; + _usb_isr_invoke_in_cb(usbp, ep_idx); } else { @@ -833,10 +883,13 @@ void usb_lld_start(USBDriver *usbp) /* Enable software connect */ for(i = 0;i < 9999;i++){} - - - /* Enable USB interrupts */ - ald_usb_int_enable(ALD_USB_INTCTRL_RESET | ALD_USB_INTCTRL_DISCONNECT | ALD_USB_INTCTRL_RESUME |ALD_USB_INTCTRL_SUSPEND);/*未开å¯SOF中断*/ + + /* Enable USB interrupts */ +#if !defined(ES_NO_USB_SUSPEND) + ald_usb_int_enable(ALD_USB_INTCTRL_RESET | ALD_USB_INTCTRL_DISCONNECT | ALD_USB_INTCTRL_RESUME |ALD_USB_INTCTRL_SUSPEND | ALD_USB_INTCTRL_SOF); +#else + ald_usb_int_enable(ALD_USB_INTCTRL_RESET | ALD_USB_INTCTRL_DISCONNECT | ALD_USB_INTCTRL_RESUME |ALD_USB_INTCTRL_SUSPEND);/*먦ÆôSOFÖжÏ*/ +#endif ald_usb_int_enable_ep(ALD_USB_INTEP_ALL); ald_usb_int_register(); } @@ -920,7 +973,7 @@ void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) } if (ep_idx > (ES_USB_PERH_EP_MAX_INDEX)) { - es_test_printf("Ep addr overflow\r\n",sizeof("Ep addr overflow\r\n")); + /*Ep addr overflow*/ return; } @@ -992,7 +1045,7 @@ void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) */ void usb_lld_disable_endpoints(USBDriver *usbp) { - es_test_printf("usb_lld_disable_endpoints\r\n",sizeof("usb_lld_disable_endpoints\r\n")); + } /** @@ -1009,8 +1062,21 @@ void usb_lld_disable_endpoints(USBDriver *usbp) */ usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep) { + if (!g_musb_udc.out_ep[ep].ep_enable) + return EP_STATUS_DISABLED; - es_test_printf("usb_lld_get_status_out\r\n",sizeof("usb_lld_get_status_out\r\n")); + USB->INDEX = ep; + + if(ep == 0) + { + if((USB->CSR0L_TXCSRL) & (USB_CSR0L_STALL_MSK)) + return EP_STATUS_STALLED; + } + else + { + if((USB->RXCSRL) & (USB_RXCSRL_STALL_MSK)) + return EP_STATUS_STALLED; + } return EP_STATUS_ACTIVE; } @@ -1029,7 +1095,21 @@ usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep) */ usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep) { - es_test_printf("usb_lld_get_status_in\r\n",sizeof("usb_lld_get_status_in\r\n")); + if (!g_musb_udc.in_ep[ep].ep_enable) + return EP_STATUS_DISABLED; + + USB->INDEX = ep; + + if(ep == 0) + { + if((USB->CSR0L_TXCSRL) & (USB_CSR0L_STALL_MSK)) + return EP_STATUS_STALLED; + } + else + { + if((USB->CSR0L_TXCSRL) & (USB_TXCSRL_STALL_MSK)) + return EP_STATUS_STALLED; + } return EP_STATUS_ACTIVE; } @@ -1072,6 +1152,9 @@ void usb_lld_start_out(USBDriver *usbp, usbep_t ep) usbd_ep_start_read(ep,osp->rxbuf,osp->rxsize); } +/*user_callback*/ +__attribute__((weak)) void es_usb_lld_start_in_user_callback(uint8_t ep,uint8_t * buf , uint32_t len) {} + /** * @brief Starts a transmit operation on an IN endpoint. * @@ -1084,6 +1167,7 @@ void usb_lld_start_in(USBDriver *usbp, usbep_t ep) { USBInEndpointState *isp = usbp->epc[ep]->in_state; usbd_ep_start_write(ep,isp->txbuf,isp->txsize); + es_usb_lld_start_in_user_callback(ep,(uint8_t*)(isp->txbuf),isp->txsize); } /** diff --git a/os/hal/ports/ES32/LLD/USBv1/hal_usb_lld.h b/os/hal/ports/ES32/LLD/USBv1/hal_usb_lld.h index 6bc3988e0e..b4a25aff8f 100644 --- a/os/hal/ports/ES32/LLD/USBv1/hal_usb_lld.h +++ b/os/hal/ports/ES32/LLD/USBv1/hal_usb_lld.h @@ -356,7 +356,15 @@ struct USBDriver */ #define usb_lld_wakeup_host(usbp) \ do { \ - \ + if(((USB->POWER)&ALD_USB_POWER_SUSPENDEN) == 0) \ + USB->POWER |= ALD_USB_POWER_SUSPENDEN; \ + \ + if(((USB->POWER)&ALD_USB_POWER_SUSPEND)) \ + { \ + USB->POWER |= 0x4;/*md_usb_enable_resume(USB);*/ \ + chThdSleepMilliseconds(11);/*wait_ms(11);*/ \ + USB->POWER &= 0xFB;/*md_usb_disable_resume(USB);*/ \ + } \ } while (FALSE) From 31071d11a54cdd7696eb96bf016b351966fe9d7c Mon Sep 17 00:00:00 2001 From: liuhy Date: Tue, 7 May 2024 19:14:17 +0800 Subject: [PATCH 13/19] update demo. --- demos/ES32/FS026/cfg/mcuconf.h | 128 +++++++++++++++++++++++---------- 1 file changed, 89 insertions(+), 39 deletions(-) diff --git a/demos/ES32/FS026/cfg/mcuconf.h b/demos/ES32/FS026/cfg/mcuconf.h index a6c050d0b5..a22445513a 100644 --- a/demos/ES32/FS026/cfg/mcuconf.h +++ b/demos/ES32/FS026/cfg/mcuconf.h @@ -17,6 +17,8 @@ #ifndef MCUCONF_H #define MCUCONF_H +#define ES32_FS026_MCUCONF + /** * @name Internal clock sources * @{ @@ -28,22 +30,64 @@ /* * HAL driver system settings. */ -#define ES32_NO_INIT FALSE -#define ES32_MHSI_ENABLED TRUE -#define ES32_FHSI_ENABLED FALSE -#define ES32_LSI_ENABLED FALSE -#define ES32_HSE_ENABLED TRUE -#define ES32_LSE_ENABLED FALSE -#define ES32_PLL_ENABLED TRUE -#define ES32_MAINCLKSRC ES32_MAINCLKSRC_PLL -#define ES32_HSE_STATE ANCTL_HSECR0_HSEON -#define ES32_PLLSRC ES32_PLLSRC_HSE -#define ES32_PLLDIV_VALUE 2 -#define ES32_PLLMUL_VALUE 12 // The allowed range is 12,16,20,24. -#define ES32_HPRE 1 -#define ES32_PPRE1 1 -#define ES32_PPRE2 1 -#define ES32_USBPRE ES32_USBPRE_DIV1P5 +#define ES32_NO_INIT FALSE + +/*system_clk select + +MD_RCU_SW_SYSCLK_HRC = HRC selected as system clock +MD_RCU_SW_SYSCLK_HOSC = HOSC selected as system clock +MD_RCU_SW_SYSCLK_PLL0 = PLL0 selected as system clock +MD_RCU_SW_SYSCLK_HRC48 = HRC48 selected as system clock +*/ +#define ES32_SYSCLK_SOURSE_SELECT MD_RCU_SW_SYSCLK_PLL0 + +/*external clk config*/ +#define ES32_HOSC_CLK_EN FALSE +#define ES32_HOSC_CLK_FREQ 8 + +/*pll clk config + +MD_RCU_PLLSRC_HRC = HRC selected as PLL reference clock +MD_RCU_PLLSRC_HOSC = HOSC selected as PLL reference clock +MD_RCU_PLLSRC_HRC48 = HRC48 selected as PLL reference clock + +MD_RCU_PLLCLK_PASS = 0 +MD_RCU_PLLCLK_4M = 4000000 +MD_RCU_PLLCLK_8M = 8000000 +MD_RCU_PLLCLK_12M = 12000000 +MD_RCU_PLLCLK_16M = 16000000 +MD_RCU_PLLCLK_24M = 24000000 +MD_RCU_PLLCLK_32M = 32000000 +MD_RCU_PLLCLK_36M = 36000000 +MD_RCU_PLLCLK_40M = 40000000 +MD_RCU_PLLCLK_48M = 48000000 +MD_RCU_PLLCLK_64M = 64000000 +MD_RCU_PLLCLK_72M = 72000000 +*/ +#define ES32_PLL_CLK_EN TRUE +#define ES32_PLL_SOURSE_SELECT MD_RCU_PLLSRC_HRC48 +#define ES32_PLL_CLK_FREQ MD_RCU_PLLCLK_72M + +/*bus clk config + +MD_RCU_HPRE_SYSCLK_DIV_1 = SYSCLK not divided +MD_RCU_HPRE_SYSCLK_DIV_2 = SYSCLK divided by 2 +MD_RCU_HPRE_SYSCLK_DIV_4 = SYSCLK divided by 4 +MD_RCU_HPRE_SYSCLK_DIV_8 = SYSCLK divided by 8 +MD_RCU_HPRE_SYSCLK_DIV_16 = SYSCLK divided by 16 +MD_RCU_HPRE_SYSCLK_DIV_64 = SYSCLK divided by 64 +MD_RCU_HPRE_SYSCLK_DIV_128 = SYSCLK divided by 128 +MD_RCU_HPRE_SYSCLK_DIV_256 = SYSCLK divided by 256 +MD_RCU_HPRE_SYSCLK_DIV_512 = @brief SYSCLK divided by 512 + +MD_RCU_PPRE_HCLK_DIV_1 = HCLK not divided +MD_RCU_PPRE_HCLK_DIV_2 = HCLK divided by 2 +MD_RCU_PPRE_HCLK_DIV_4 = HCLK divided by 4 +MD_RCU_PPRE_HCLK_DIV_8 = HCLK divided by 8 +MD_RCU_PPRE_HCLK_DIV_16 = HCLK divided by 16 +*/ +#define ES32_BUS_DIV_HPRE MD_RCU_HPRE_SYSCLK_DIV_1 +#define ES32_BUS_DIV_PPRE MD_RCU_PPRE_HCLK_DIV_1 /* * EXTI driver system settings. @@ -88,15 +132,24 @@ /* * PWM driver system settings. */ -#define ES32_PWM_USE_ADVANCED FALSE -#define ES32_PWM_USE_TIM1 FALSE -#define ES32_PWM_USE_TIM2 FALSE -#define ES32_PWM_USE_TIM3 FALSE -#define ES32_PWM_USE_TIM4 FALSE -#define ES32_PWM_TIM1_IRQ_PRIORITY 7 -#define ES32_PWM_TIM2_IRQ_PRIORITY 7 -#define ES32_PWM_TIM3_IRQ_PRIORITY 7 -#define ES32_PWM_TIM4_IRQ_PRIORITY 7 +#define ES32_PWM_USE_AD16C4T1 TRUE +#define ES32_PWM_USE_GP32C4T1 TRUE +#define ES32_PWM_USE_GP16C4T1 TRUE +#define ES32_PWM_USE_GP16C4T2 TRUE +#define ES32_PWM_USE_GP16C4T3 TRUE +#define ES32_PWM_USE_GP16C2T1 TRUE +#define ES32_PWM_USE_GP16C2T2 TRUE +#define ES32_PWM_USE_GP16C2T3 TRUE +#define ES32_PWM_USE_GP16C2T4 TRUE +#define ES32_PWM_AD16C4T1_IRQ_PRIORITY 7 +#define ES32_PWM_GP32C4T1_IRQ_PRIORITY 7 +#define ES32_PWM_GP16C4T1_IRQ_PRIORITY 7 +#define ES32_PWM_GP16C4T2_IRQ_PRIORITY 7 +#define ES32_PWM_GP16C4T3_IRQ_PRIORITY 7 +#define ES32_PWM_GP16C2T1_IRQ_PRIORITY 7 +#define ES32_PWM_GP16C2T2_IRQ_PRIORITY 7 +#define ES32_PWM_GP16C2T3_IRQ_PRIORITY 7 +#define ES32_PWM_GP16C2T4_IRQ_PRIORITY 7 /* * I2C driver system settings. @@ -110,24 +163,20 @@ /* * SERIAL driver system settings. */ -#define ES32_SERIAL_USE_UART1 FALSE -#define ES32_SERIAL_USE_UART2 FALSE -#define ES32_SERIAL_USE_UART3 FALSE -#define ES32_SERIAL_USART1_PRIORITY 12 -#define ES32_SERIAL_USART2_PRIORITY 12 -#define ES32_SERIAL_USART3_PRIORITY 12 +#define ES32_SERIAL_USE_UART1 TRUE +#define ES32_SERIAL_USE_UART2 TRUE +#define ES32_SERIAL_USE_UART3 TRUE +#define ES32_SERIAL_USE_UART4 TRUE +#define ES32_SERIAL_USART1_PRIORITY 7 +#define ES32_SERIAL_USART1_PRIORITY 7 +#define ES32_SERIAL_USART1_PRIORITY 7 +#define ES32_SERIAL_USART1_PRIORITY 7 /* * SPI driver system settings. */ -#define ES32_SPI_USE_QSPI FALSE -#define ES32_SPI_USE_SPIM2 FALSE -#define ES32_SPI_USE_SPIS1 FALSE -#define ES32_SPI_USE_SPIS2 FALSE -#define ES32_SPI_QSPI_IRQ_PRIORITY 10 -#define ES32_SPI_SPIM2_IRQ_PRIORITY 10 -#define ES32_SPI_SPIS1_IRQ_PRIORITY 10 -#define ES32_SPI_SPIS2_IRQ_PRIORITY 10 +#define ES32_SPI_USE_SPI1 TRUE +#define ES32_SPI_USE_SPI2 TRUE /* * ST driver system settings. @@ -151,6 +200,7 @@ #define ES32_USB_USE_USB1 TRUE #define ES32_USB_USB1_IRQ_PRIORITY 13 #define ES32_USB_HOST_WAKEUP_DURATION 10 +#define ES32_USE_USB_SOF_TRIM_HRC48 TRUE /* * ADC driver system settings. From 24203f90fd4f5e4c7903530ddbd47f237056a142 Mon Sep 17 00:00:00 2001 From: liuhy Date: Wed, 8 May 2024 19:30:29 +0800 Subject: [PATCH 14/19] fix hal bug. --- os/hal/ports/ES32/LLD/GPIOv1/hal_pal_lld.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/os/hal/ports/ES32/LLD/GPIOv1/hal_pal_lld.h b/os/hal/ports/ES32/LLD/GPIOv1/hal_pal_lld.h index ffe0107f5b..ec5e55ebb9 100644 --- a/os/hal/ports/ES32/LLD/GPIOv1/hal_pal_lld.h +++ b/os/hal/ports/ES32/LLD/GPIOv1/hal_pal_lld.h @@ -108,7 +108,7 @@ * @brief Input pad with weak pull down resistor. */ #define PAL_MODE_INPUT_PULLDOWN (PAL_ES32_MODE_INPUT | \ - PAL_ES32_PUPDR_PULLDOWN) + PAL_ES32_PUD_PULLDOWN) /** * @brief Analog input mode. From 1636a60e6b78068612455365e52e229f435ea5c1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Wed, 29 May 2024 20:41:24 +0100 Subject: [PATCH 15/19] Update FatFS diskio to latest from ChibiOS bindings (#403) --- os/various/fatfs_bindings/fatfs_diskio.c | 31 ++++++++++++++++-------- 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/os/various/fatfs_bindings/fatfs_diskio.c b/os/various/fatfs_bindings/fatfs_diskio.c index e3cfd5328b..fb127e4dff 100644 --- a/os/various/fatfs_bindings/fatfs_diskio.c +++ b/os/various/fatfs_bindings/fatfs_diskio.c @@ -69,7 +69,7 @@ DSTATUS disk_initialize ( /* It is initialized externally, just reads the status.*/ if (blkGetDriverState(&FATFS_HAL_DEVICE) != BLK_READY) stat |= STA_NOINIT; - if (sdcIsWriteProtected(&FATFS_HAL_DEVICE)) + if (blkIsWriteProtected(&FATFS_HAL_DEVICE)) stat |= STA_PROTECT; return stat; #endif @@ -112,7 +112,7 @@ DSTATUS disk_status ( /* It is initialized externally, just reads the status.*/ if (blkGetDriverState(&FATFS_HAL_DEVICE) != BLK_READY) stat |= STA_NOINIT; - if (sdcIsWriteProtected(&FATFS_HAL_DEVICE)) + if (blkIsWriteProtected(&FATFS_HAL_DEVICE)) stat |= STA_PROTECT; return stat; #endif @@ -160,7 +160,7 @@ DRESULT disk_read ( case FATFSDEV_MMC: if (blkGetDriverState(&FATFS_HAL_DEVICE) != BLK_READY) return RES_NOTRDY; - if (sdcRead(&FATFS_HAL_DEVICE, sector, buff, count)) + if (blkRead(&FATFS_HAL_DEVICE, sector, buff, count)) return RES_ERROR; return RES_OK; #endif @@ -221,7 +221,7 @@ DRESULT disk_write ( // invalidate cache on buffer cacheBufferFlush(buff, count * MMCSD_BLOCK_SIZE); - if (sdcWrite(&FATFS_HAL_DEVICE, sector, buff, count)) + if (blkWrite(&FATFS_HAL_DEVICE, sector, buff, count)) return RES_ERROR; return RES_OK; @@ -255,6 +255,8 @@ DRESULT disk_ioctl ( void *buff /* Buffer to send/receive control data */ ) { + BlockDeviceInfo bdi; + (void)buff; switch (pdrv) { @@ -282,20 +284,29 @@ DRESULT disk_ioctl ( case CTRL_SYNC: return RES_OK; case GET_SECTOR_COUNT: - *((DWORD *)buff) = mmcsdGetCardCapacity(&FATFS_HAL_DEVICE); - return RES_OK; + if (blkGetInfo(&FATFS_HAL_DEVICE, &bdi)) { + return RES_ERROR; + } + *((DWORD *)buff) = bdi.blk_num; + return RES_OK; #if FF_MAX_SS > FF_MIN_SS case GET_SECTOR_SIZE: - *((WORD *)buff) = MMCSD_BLOCK_SIZE; - return RES_OK; + if (blkGetInfo(&FATFS_HAL_DEVICE, &bdi)) { + return RES_ERROR; + } + *((WORD *)buff) = bdi.blk_size; + return RES_OK; #endif case GET_BLOCK_SIZE: *((DWORD *)buff) = 256; /* 512b blocks in one erase block */ return RES_OK; #if FF_USE_TRIM + case GET_BLOCK_SIZE: + /* unsupported */ + break; case CTRL_TRIM: - sdcErase(&FATFS_HAL_DEVICE, *((DWORD *)buff), *((DWORD *)buff + 1)); - return RES_OK; + /* unsupported */ + break; #endif default: return RES_PARERR; From 86e74c00ba46d5151b98a424ca8fd43e9dfb3d26 Mon Sep 17 00:00:00 2001 From: dexter93 Date: Sat, 1 Jun 2024 23:24:27 +0300 Subject: [PATCH 16/19] sn32: implement UART LLD (#402) --- os/hal/ports/SN32/LLD/SN32F2xx/UART/UART.h | 184 ------ os/hal/ports/SN32/LLD/SN32F2xx/UART/UART0.c | 250 -------- os/hal/ports/SN32/LLD/SN32F2xx/UART/UART1.c | 253 -------- os/hal/ports/SN32/LLD/SN32F2xx/UART/UART2.c | 253 -------- os/hal/ports/SN32/LLD/SN32F2xx/UART/driver.mk | 13 + .../SN32/LLD/SN32F2xx/UART/hal_serial_lld.c | 527 +++++++++++++++++ .../SN32/LLD/SN32F2xx/UART/hal_serial_lld.h | 245 ++++++++ .../SN32/LLD/SN32F2xx/UART/hal_uart_lld.c | 554 ++++++++++++++++++ .../SN32/LLD/SN32F2xx/UART/hal_uart_lld.h | 353 +++++++++++ .../ports/SN32/LLD/SN32F2xx/UART/sn32_uart.h | 322 ++++++++++ os/hal/ports/SN32/SN32F240B/platform.mk | 1 + os/hal/ports/SN32/SN32F260/platform.mk | 1 + 12 files changed, 2016 insertions(+), 940 deletions(-) delete mode 100644 os/hal/ports/SN32/LLD/SN32F2xx/UART/UART.h delete mode 100644 os/hal/ports/SN32/LLD/SN32F2xx/UART/UART0.c delete mode 100644 os/hal/ports/SN32/LLD/SN32F2xx/UART/UART1.c delete mode 100644 os/hal/ports/SN32/LLD/SN32F2xx/UART/UART2.c create mode 100644 os/hal/ports/SN32/LLD/SN32F2xx/UART/driver.mk create mode 100644 os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_serial_lld.c create mode 100644 os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_serial_lld.h create mode 100644 os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_uart_lld.c create mode 100644 os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_uart_lld.h create mode 100644 os/hal/ports/SN32/LLD/SN32F2xx/UART/sn32_uart.h diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/UART/UART.h b/os/hal/ports/SN32/LLD/SN32F2xx/UART/UART.h deleted file mode 100644 index cd33abbe31..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F2xx/UART/UART.h +++ /dev/null @@ -1,184 +0,0 @@ -#ifndef __SN32F2XX_UART_H -#define __SN32F2XX_UART_H - - -/*_____ I N C L U D E S ____________________________________________________*/ -#include - -/*_____ D E F I N I T I O N S ______________________________________________*/ -/* -Base Address: 0x4001 6000 (UART0) - 0x4001 4000 (UART1) - 0x4001 2000 (UART1) -*/ -#define UART0_CLK_EN (0x01<<16) -#define UART1_CLK_EN (0x01<<17) -#define UART2_CLK_EN (0x01<<18) - -/**************Line Control Define******/ -#define UART_CHARACTER_LEN5BIT (0x00) -#define UART_CHARACTER_LEN6BIT (0x01) -#define UART_CHARACTER_LEN7BIT (0x02) -#define UART_CHARACTER_LEN8BIT (0x03) -/***********************/ -#define UART_STOPBIT_1BIT (0x0<<2) -#define UART_STOPBIT_2BIT (0x1<<2) -/***********************/ -#define UART_PARITY_BIT_DISEN (0x0<<3) -#define UART_PARITY_BIT_EN (0x1<<3) -/***********************/ -#define UART_PARITY_SELECTODD (0x00<<4) -#define UART_PARITY_SELECTEVEN (0x01<<4) -#define UART_PARITY_SELECTFORC1 (0x02<<4) -#define UART_PARITY_SELECTFORC0 (0x03<<4) -/***********************/ -#define UART_BREAK_DISEN (0x0<<6) -#define UART_BREAK_EN (0x1<<6) -/***********************/ -#define UART_DIVISOR_DISEN (0x0<<7) -#define UART_DIVISOR_EN (0x1<<7) - -#define UART_OVER_SAMPLE_16 (0x0<<8) -#define UART_OVER_SAMPLE_8 (0x1<<8) -/***Baud rate pre-scaler multilier = MULVAL+1***/ -#define UART_MULVAL_0 (0x0000<<4) -#define UART_MULVAL_1 (0x0001<<4) -#define UART_MULVAL_2 (0x0002<<4) -#define UART_MULVAL_3 (0x0003<<4) -#define UART_MULVAL_4 (0x0004<<4) -#define UART_MULVAL_5 (0x0005<<4) -#define UART_MULVAL_6 (0x0006<<4) -#define UART_MULVAL_7 (0x0007<<4) -#define UART_MULVAL_8 (0x0008<<4) -#define UART_MULVAL_9 (0x0009<<4) -#define UART_MULVAL_10 (0x000A<<4) -#define UART_MULVAL_11 (0x000B<<4) -#define UART_MULVAL_12 (0x000C<<4) -#define UART_MULVAL_13 (0x000D<<4) -#define UART_MULVAL_14 (0x000E<<4) -#define UART_MULVAL_15 (0x000F<<4) -/***Buad rate pre-scaler divisor value********/ -#define UART_DIVADDVAL_0 (0x000) -#define UART_DIVADDVAL_1 (0x001) -#define UART_DIVADDVAL_2 (0x002) -#define UART_DIVADDVAL_3 (0x003) -#define UART_DIVADDVAL_4 (0x004) -#define UART_DIVADDVAL_5 (0x005) -#define UART_DIVADDVAL_6 (0x006) -#define UART_DIVADDVAL_7 (0x007) -#define UART_DIVADDVAL_8 (0x008) -#define UART_DIVADDVAL_9 (0x009) -#define UART_DIVADDVAL_10 (0x00A) -#define UART_DIVADDVAL_11 (0x00B) -#define UART_DIVADDVAL_12 (0x00C) -#define UART_DIVADDVAL_13 (0x00D) -#define UART_DIVADDVAL_14 (0x00E) -#define UART_DIVADDVAL_15 (0x00F) -/***UART divisor latch MSB reg[7:0]. determines the baud rate***/ - - -/***UART divisor latch LSB reg[7:0]. determines the baud rate***/ - - -#define UART_FIFO_ENABLE (0x01) -#define UART_RXFIFO_RESET (0x01<<1) -#define UART_TXFIFO_RESET (0x01<<2) - -#define UART_RXTRIGGER_LEVEL1 (0x00<<6) - - -/***UART Interrupt Enable register***/ -#define UART_ABTOIE_EN (0x01<<9) //auto-buad time out INT -#define UART_ABEOIE_EN (0x01<<8) //End of auto-buad INT -#define UART_TEMTIE_EN (0x01<<4) //Transmitter empty flag -#define UART_RLSIE_EN (0x01<<2) //Rx Receive line status(RLS) INT -#define UART_THREIE_EN (0x01<<1) //Transmitter holding register empty flag INT -#define UART_RDAIE_EN (0x01) //character receive(RDA) time-out INT - -/*** UARTn_CTRL************/ -#define UART_EN (0x01) -#define UART_RX_EN (0x01<<6) -#define UART_TX_EN (0x01<<7) -#define UART_CTRL_EN 1 -#define UART_CTRL_DIS 0 -#define UART_FIFOCTRL_RESET 1 - -/*** UARTn_ABCCTRL************/ -#define UART_ABCCTRL_START (0x01) //START:1(Auto-baud is running), START:0(Auto-baud is not running) -#define UART_ABCCTRL_MODE0 (0x00<<1) -#define UART_ABCCTRL_MODE1 (0x01<<1) -#define UART_ABCCTRL_RESTART (0x01<<2) -#define UART_ABEO_EN (0x01<<8) -#define UART_ABTO_EN (0x01<<9) - -/*** Line status register************/ -#define UART_LS_RDR (0x01) //receiver data ready flag -#define UART_LS_OE (0x01<<1) //overrun error flag -#define UART_LS_PE (0x01<<2) //parity error flag -#define UART_LS_FE (0x01<<3) //framing error flag -#define UART_LS_BI (0x01<<4) //break interrupt flag -#define UART_LS_THRE (0x01<<5) //transmitter holding register empty flag -#define UART_LS_TEMT (0x01<<6) //transmitter empty flag -#define UART_LS_RXFE (0x01<<7) //error in RX FIFO flag -#define mskUART_LS_RDR (0x01) -#define mskUART_LS_OE (0x01<<1) -#define mskUART_LS_PE (0x01<<2) -#define mskUART_LS_FE (0x01<<3) -#define mskUART_LS_BI (0x01<<4) -#define mskUART_LS_THRE (0x01<<5) -#define mskUART_LS_TEMT (0x01<<6) -#define mskUART_LS_RXFE (0x01<<7) - -/*** Interrupt Identification register************/ -#define UART_RLS 3 -#define UART_RDA 2 -#define UART_THRE 1 -#define UART_TEMT 7 -#define UART_II_STATUS 0 //the INTstatus can be determined by UARTn_II[3:1] -#define UART_II_ABEOIF (0x01<<8) //end of auto-baud interrupt flag -#define UART_II_ABTOIF (0x01<<9) //auto-baud time-out interrupt flag -#define mskUART_INTID_STATUS 7 //interrupt corresponding to the UARTn RX FIFO -#define mskUART_II_STATUS (0x01) -#define mskUART_II_ABEOIF (0x01<<8) -#define mskUART_II_ABTOIF (0x01<<9) - - -/*_____ M A C R O S ________________________________________________________*/ - - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -extern uint32_t GulNum; -extern uint8_t bUART0_RecvFIFO[]; -extern uint32_t GulNum1; -extern uint8_t bUART1_RecvFIFO[]; -extern uint32_t GulNum2; -extern uint8_t bUART2_RecvFIFO[]; -extern volatile uint8_t bUART0_RecvNew; -extern volatile uint8_t bUART1_RecvNew; -extern volatile uint8_t bUART2_RecvNew; - - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -extern void UART0_Init(void); -extern void UART0_SendByte (uint8_t ucDat); -extern void UART0_Enable(void); -extern void UART0_Disable(void); -extern void UART0_InterruptEnable(void); -extern void UART0_AutoBaudrateInit(void); - -extern void UART1_Init(void); -extern void UART1_SendByte (uint8_t ucDat); -extern void UART1_Enable(void); -extern void UART1_Disable(void); -extern void UART1_InterruptEnable(void); -extern void UART1_AutoBaudrateInit(void); - -void UART2_Init(void); -void UART2_SendByte (uint8_t ucDat); -void UART2_Enable(void); -void UART2_Disable(void); -void UART2_InterruptEnable(void); -void UART2_AutoBaudrateInit(void); - -#endif /*__SN32F2XX_UART_H*/ - diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/UART/UART0.c b/os/hal/ports/SN32/LLD/SN32F2xx/UART/UART0.c deleted file mode 100644 index 960affc674..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F2xx/UART/UART0.c +++ /dev/null @@ -1,250 +0,0 @@ -/******************** (C) COPYRIGHT 2017 SONiX ******************************* -* COMPANY: SONiX -* DATE: 2017/07 -* AUTHOR: SA1 -* IC: SN32F240B -* DESCRIPTION: UART0 related functions. -*____________________________________________________________________________ -* REVISION Date User Description -* 1.0 2017/07/07 SA1 First release -* -*____________________________________________________________________________ -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. -* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL -* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE -* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN -* IN CONNECTION WITH THEIR PRODUCTS. -*****************************************************************************/ - -/*_____ I N C L U D E S ____________________________________________________*/ -#include -#include "UART.h" - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -volatile uint8_t bUART0_RecvNew; -uint32_t GulNum; -uint8_t bUART0_RecvFIFO[56]; - - -/*_____ D E F I N I T I O N S ______________________________________________*/ - - -/*_____ M A C R O S ________________________________________________________*/ - - -/*_____ F U N C T I O N S __________________________________________________*/ - -/***************************************************************************** -* Function : UART0_IRQHandler -* Description : UART0 interrupt service routine -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -__irq void UART0_IRQHandler (void) -{ - uint32_t II_Buf, LS_Buf; - volatile uint32_t Null_Buf; - - II_Buf = SN_UART0->II; - while ((II_Buf & mskUART_II_STATUS) == UART_II_STATUS) //check interrupt status, the INT can be determined by USARTn_II[3:1] - { - switch ((II_Buf>>1) & mskUART_INTID_STATUS) - { - case UART_RLS: //Receive Line Status - LS_Buf = SN_UART0->LS; - if((LS_Buf & mskUART_LS_OE) == UART_LS_OE) //Overrun Error - { } - if((LS_Buf & mskUART_LS_RXFE) == UART_LS_RXFE)//RX FIFO Error - { - if((LS_Buf & mskUART_LS_PE) == UART_LS_PE)//Parity Error - Null_Buf = SN_UART0->RB; //Clear interrupt - if((LS_Buf & mskUART_LS_FE) == UART_LS_FE) //Framing Error - Null_Buf = SN_UART0->RB; //Clear interrupt - if((LS_Buf & mskUART_LS_BI) == UART_LS_BI) //Break Interrupt - Null_Buf = SN_UART0->RB; //Clear interrupt - } - break; - - case UART_RDA: //Receive Data Available - LS_Buf = SN_UART0->LS; - bUART0_RecvNew = 1; - if((LS_Buf & mskUART_LS_RDR) == UART_LS_RDR)//Receiver Data Ready - { - bUART0_RecvFIFO[GulNum] = SN_UART0->RB; - GulNum++; - } - if(GulNum == 56) - GulNum = 0; - break; - - case UART_THRE: //THRE interrupt - LS_Buf = SN_UART0->LS; - if((LS_Buf & mskUART_LS_THRE) == UART_LS_THRE)//THRE empty - { //SN_UART0->TH = Null_Buf; //Clear interrupt - } - break; - - case UART_TEMT: //TEMT interrupt - LS_Buf = SN_UART0->LS; - if((LS_Buf & mskUART_LS_TEMT) == UART_LS_TEMT) - { //SN_UART0->TH = Null_Buf; //Clear interrupt - } - break; - - default: - break; - } //end switch ((II_Buf>>1) & mskUART_INTID_STATUS) - - II_Buf = SN_UART0->II; - } //end while ((II_Buf&0x01) == mskUART_II_STATUS) - - if ((II_Buf & mskUART_II_ABEOIF) == UART_II_ABEOIF) //Auto Baud interrupt - SN_UART0->ABCTRL |= UART_ABEO_EN; - else if((II_Buf & mskUART_II_ABTOIF) == UART_II_ABTOIF) //Auto Baud time-out interrupt - SN_UART0->ABCTRL |= UART_ABTO_EN; -} - - -/***************************************************************************** -* Function : UART0_Init -* Description : Initialization of UART0 -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void UART0_Init (void) -{ - SN_SYS1->AHBCLKEN |= UART0_CLK_EN; //Enables clock for UART0 - - //===Line Control=== - //setting character Word length(5/6/7/8 bit) - SN_UART0->LC = (UART_CHARACTER_LEN8BIT //8bit character length. - | UART_STOPBIT_1BIT //stop bit of 1 bit - | UART_PARITY_BIT_DISEN //parity bit is disable - | UART_PARITY_SELECTODD //parity bit is odd - | UART_BREAK_DISEN //Break Transmission control disable - | UART_DIVISOR_EN); //Divisor Latch Access enable - - //===Baud Rate Calculation=== - //UART PCLK = 12MHz, Baud rate = 115200 - SN_UART0->FD = (UART_OVER_SAMPLE_16|UART_MULVAL_7|UART_DIVADDVAL_5); - SN_UART0->DLM = 0; - SN_UART0->DLL = 4; - /* - //UART PCLK = 12MHz, Baud rate = 57600 - SN_UART0->FD = (OVER_SAMPLE_16|UART_MULVAL_7|UART_DIVADDVAL_5); - SN_UART0->DLM = 0; - SN_UART0->DLL = 8; - */ - SN_UART0->LC &= ~(UART_DIVISOR_EN); //Disable divisor latch - - //===Auto Baud Rate=== - //UART0_Autobaudrate_Init(); //Auto buad rate initial - - //===FIFO Control=== - SN_UART0->FIFOCTRL =(UART_FIFO_ENABLE //Enable USART FIFOs - | UART_RXFIFO_RESET //RX FIFO Reset - | UART_TXFIFO_RESET //TX FIFO Reset - | UART_RXTRIGGER_LEVEL1); //RX Trigger Level(1 characters) - - //===Oversampling=== - //SN_UART0->FD |= UART_OVER_SAMPLE_8; //OVER8(Oversampling Value), 1:Oversampling by 8. 0:Oversampling by 16 - - //===Half-duplex=== - //SN_UART0->HDEN = 1; //Half-duplex mode enable - - //===Interrupt Enable=== - UART0_InterruptEnable(); - - //===UART Control=== - SN_UART0->CTRL =(UART_EN //Enable USART0 - | UART_RX_EN //Enable RX - | UART_TX_EN); //Enable TX - //===NVIC=== - NVIC_EnableIRQ(UART0_IRQn); //Enable USART0 INT - -} - -/***************************************************************************** -* Function : UART0_SendByte -* Description : MCU sends Byte through UTXD0 -* Input : ucDat - data to be sent -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void UART0_SendByte (uint8_t ucDat) -{ - SN_UART0->TH = ucDat; - while ((SN_UART0->LS & 0x40) == 0); -} - -/***************************************************************************** -* Function : UART0_AutoBaudrateInit -* Description : Initialization of UART0 Auto baud rate. -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void UART0_AutoBaudrateInit(void) -{ - SN_UART0->ABCTRL =(UART_ABTO_EN //Clear Auto Baud Time-out interrupt - | UART_ABEO_EN //Clear Auto Baud interrupt - | UART_ABCCTRL_RESTART //Restart in case of time-out - | UART_ABCCTRL_MODE1 //Auto Baud mode, 0:mode 0, 1:mode 1 - | UART_ABCCTRL_START); //Auto Baud start, 0:stop(not running), 1:start(running) -} - -/***************************************************************************** -* Function : UART0_Enable -* Description : Enable UART0 -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void UART0_Enable(void) -{ - //Enable HCLK for UART0 - SN_SYS1->AHBCLKEN |= UART0_CLK_EN; //Enables clock for UART0 - SN_UART0->CTRL_b.UARTEN = UART_CTRL_EN; //UART enable bit -} - -/***************************************************************************** -* Function : UART0_Disable -* Description : Disable UART0 -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void UART0_Disable(void) -{ - SN_UART0->CTRL_b.UARTEN = UART_CTRL_DIS; //UART disable - //Disable HCLK for UART0 - SN_SYS1->AHBCLKEN &= ~(UART0_CLK_EN); //Disable clock for UART0 -} - -/***************************************************************************** -* Function : UART0_InterruptEnable -* Description : Interrupt Enable -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void UART0_InterruptEnable(void) -{ - SN_UART0->IE =(UART_RDAIE_EN //Enables the Receive Data Available(RDA) interrupt - | UART_THREIE_EN //Enable THRE interrupt - | UART_RLSIE_EN //Enable Receive Line Status(RLS) interrupt - | UART_TEMTIE_EN //Enable TEMT interrupt - | UART_ABEOIE_EN //Enable Auto Baud interrupt - | UART_ABTOIE_EN); //Enable Auto Baud time-out interrupt -} - diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/UART/UART1.c b/os/hal/ports/SN32/LLD/SN32F2xx/UART/UART1.c deleted file mode 100644 index 18a55c5ead..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F2xx/UART/UART1.c +++ /dev/null @@ -1,253 +0,0 @@ -/******************** (C) COPYRIGHT 2017 SONiX ******************************* -* COMPANY: SONiX -* DATE: 2017/07 -* AUTHOR: SA1 -* IC: SN32F240B -* DESCRIPTION: UART1 related functions. -*____________________________________________________________________________ -* REVISION Date User Description -* 1.0 2017/07/07 SA1 First release -* -*____________________________________________________________________________ -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. -* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL -* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE -* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN -* IN CONNECTION WITH THEIR PRODUCTS. -*****************************************************************************/ - -/*_____ I N C L U D E S ____________________________________________________*/ -#include -#include "UART.h" - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -volatile uint8_t bUART1_RecvNew; -uint32_t GulNum1; -uint8_t bUART1_RecvFIFO[56]; - - -/*_____ D E F I N I T I O N S ______________________________________________*/ - - -/*_____ M A C R O S ________________________________________________________*/ - - -/*_____ F U N C T I O N S __________________________________________________*/ - -/***************************************************************************** -* Function : UART1_IRQHandler -* Description : UART1 interrupt service routine -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -__irq void UART1_IRQHandler (void) -{ - uint32_t II_Buf, LS_Buf; - volatile uint32_t Null_Buf; - - II_Buf = SN_UART1->II; - while ((II_Buf & mskUART_II_STATUS) == UART_II_STATUS) //check interrupt status, the INT can be determined by UARTn_II[3:1] - { - switch ((II_Buf>>1) & mskUART_INTID_STATUS) - { - case UART_RLS: //Receive Line Status - LS_Buf = SN_UART1->LS; - if((LS_Buf & mskUART_LS_OE) == UART_LS_OE) //Overrun Error - { } - if((LS_Buf & mskUART_LS_RXFE) == UART_LS_RXFE)//RX FIFO Error - { - if((LS_Buf & mskUART_LS_PE) == UART_LS_PE)//Parity Error - Null_Buf = SN_UART1->RB; //Clear interrupt - if((LS_Buf & mskUART_LS_FE) == UART_LS_FE) //Framing Error - Null_Buf = SN_UART1->RB; //Clear interrupt - if((LS_Buf & mskUART_LS_BI) == UART_LS_BI) //Break Interrupt - Null_Buf = SN_UART1->RB; //Clear interrupt - } - break; - - case UART_RDA: //Receive Data Available - LS_Buf = SN_UART1->LS; - bUART1_RecvNew = 1; - if((LS_Buf & mskUART_LS_RDR) == UART_LS_RDR)//Receiver Data Ready - { - bUART1_RecvFIFO[GulNum1] = SN_UART1->RB; - GulNum1++; - } - if(GulNum1 == 56) - GulNum1 = 0; - break; - - case UART_THRE: //THRE interrupt - LS_Buf = SN_UART1->LS; - if((LS_Buf & mskUART_LS_THRE) == UART_LS_THRE)//THRE empty - { //SN_UART1->TH = Null_Buf; //Clear interrupt - } - break; - - case UART_TEMT: //TEMT interrupt - LS_Buf = SN_UART1->LS; - if((LS_Buf & mskUART_LS_TEMT) == UART_LS_TEMT) - { //SN_UART1->TH = Null_Buf; //Clear interrupt - } - break; - - default: - break; - } //end switch ((II_Buf>>1) & mskUART_INTID_STATUS) - - II_Buf = SN_UART1->II; - } //end while ((II_Buf&0x01) == mskUART_II_STATUS) - - if ((II_Buf & mskUART_II_ABEOIF) == UART_II_ABEOIF) //Auto Baud interrupt - SN_UART1->ABCTRL |= UART_ABEO_EN; - else if((II_Buf & mskUART_II_ABTOIF) == UART_II_ABTOIF) //Auto Baud time-out interrupt - SN_UART1->ABCTRL |= UART_ABTO_EN; -} - - -/***************************************************************************** -* Function : UART1_Init -* Description : Initialization of UART1 -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void UART1_Init (void) -{ - SN_SYS1->AHBCLKEN |= UART1_CLK_EN; //Enables clock for UART1 - - //===Line Control=== - //setting character Word length(5/6/7/8 bit) - SN_UART1->LC = (UART_CHARACTER_LEN8BIT //8bit character length. - | UART_STOPBIT_1BIT //stop bit of 1 bit - | UART_PARITY_BIT_DISEN //parity bit is disable - | UART_PARITY_SELECTODD //parity bit is odd - | UART_BREAK_DISEN //Break Transmission control disable - | UART_DIVISOR_EN); //Divisor Latch Access enable - - //===Baud Rate Calculation=== - //UART PCLK = 12MHz, Baud rate = 115200 - SN_UART1->FD = (UART_OVER_SAMPLE_16|UART_MULVAL_7|UART_DIVADDVAL_5); - SN_UART1->DLM = 0; - SN_UART1->DLL = 4; - /* - //UART PCLK = 12MHz, Baud rate = 57600 - SN_UART1->FD = (OVER_SAMPLE_16|UART_MULVAL_7|UART_DIVADDVAL_5); - SN_UART1->DLM = 0; - SN_UART1->DLL = 8; - */ - SN_UART1->LC &= ~(UART_DIVISOR_EN); //Disable divisor latch - - //===Auto Baud Rate=== - //UART1_Autobaudrate_Init(); //Auto buad rate initial - - //===FIFO Control=== - SN_UART1->FIFOCTRL =(UART_FIFO_ENABLE //Enable UART FIFOs - | UART_RXFIFO_RESET //RX FIFO Reset - | UART_TXFIFO_RESET //TX FIFO Reset - | UART_RXTRIGGER_LEVEL1); //RX Trigger Level(1/4/8/14 characters) - - //===Scratch Pad=== - //SN_UART1->SP = 0; //A readable, writable byte - - //===Oversampling=== - //SN_UART1->FD |= UART_OVER_SAMPLE_8; //OVER8(Oversampling Value), 1:Oversampling by 8. 0:Oversampling by 16 - - //===Half-duplex=== - //SN_UART1->HDEN = 1; //Half-duplex mode enable - - //===Interrupt Enable=== - UART1_InterruptEnable(); - - //===UART Control=== - SN_UART1->CTRL =(UART_EN //Enable UART0 - | UART_RX_EN //Enable RX - | UART_TX_EN); //Enable TX - //===NVIC=== - NVIC_EnableIRQ(UART1_IRQn); //Enable UART1 INT - -} - -/***************************************************************************** -* Function : UART1_SendByte -* Description : MCU sends Byte through UTXD1 -* Input : ucDat - data to be sent -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void UART1_SendByte (uint8_t ucDat) -{ - SN_UART1->TH = ucDat; - while ((SN_UART1->LS & 0x40) == 0); -} - -/***************************************************************************** -* Function : UART1_AutoBaudrateInit -* Description : Initialization of UART1 Auto baud rate. -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void UART1_AutoBaudrateInit(void) -{ - SN_UART1->ABCTRL =(UART_ABTO_EN //Clear Auto Baud Time-out interrupt - | UART_ABEO_EN //Clear Auto Baud interrupt - | UART_ABCCTRL_RESTART //Restart in case of time-out - | UART_ABCCTRL_MODE1 //Auto Baud mode, 0:mode 0, 1:mode 1 - | UART_ABCCTRL_START); //Auto Baud start, 0:stop(not running), 1:start(running) -} - -/***************************************************************************** -* Function : UART1_Enable -* Description : Enable UART1 -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void UART1_Enable(void) -{ - //Enable HCLK for UART1 - SN_SYS1->AHBCLKEN |= UART1_CLK_EN; //Enables clock for UART1 - SN_UART1->CTRL_b.UARTEN = UART_CTRL_EN; //UART enable bit -} - -/***************************************************************************** -* Function : UART1_Disable -* Description : Disable UART1 -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void UART1_Disable(void) -{ - SN_UART1->CTRL_b.UARTEN = UART_CTRL_DIS; //UART disable - //Disable HCLK for UART1 - SN_SYS1->AHBCLKEN &= ~(UART1_CLK_EN); //Disable clock for UART1 -} - -/***************************************************************************** -* Function : UART1_InterruptEnable -* Description : Interrupt Enable -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void UART1_InterruptEnable(void) -{ - SN_UART1->IE =(UART_RDAIE_EN //Enables the Receive Data Available(RDA) interrupt - | UART_THREIE_EN //Enable THRE interrupt - | UART_RLSIE_EN //Enable Receive Line Status(RLS) interrupt - | UART_TEMTIE_EN //Enable TEMT interrupt - | UART_ABEOIE_EN //Enable Auto Baud interrupt - | UART_ABTOIE_EN); //Enable Auto Baud time-out interrupt -} - diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/UART/UART2.c b/os/hal/ports/SN32/LLD/SN32F2xx/UART/UART2.c deleted file mode 100644 index f46091b6f6..0000000000 --- a/os/hal/ports/SN32/LLD/SN32F2xx/UART/UART2.c +++ /dev/null @@ -1,253 +0,0 @@ -/******************** (C) COPYRIGHT 2017 SONiX ******************************* -* COMPANY: SONiX -* DATE: 2017/07 -* AUTHOR: SA1 -* IC: SN32F240B -* DESCRIPTION: UART2 related functions. -*____________________________________________________________________________ -* REVISION Date User Description -* 1.0 2017/07/07 SA1 First release -* -*____________________________________________________________________________ -* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET. -* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL -* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE -* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN -* IN CONNECTION WITH THEIR PRODUCTS. -*****************************************************************************/ - -/*_____ I N C L U D E S ____________________________________________________*/ -#include -#include "UART.h" - -/*_____ D E C L A R A T I O N S ____________________________________________*/ -volatile uint8_t bUART2_RecvNew; -uint32_t GulNum2; -uint8_t bUART2_RecvFIFO[56]; - - -/*_____ D E F I N I T I O N S ______________________________________________*/ - - -/*_____ M A C R O S ________________________________________________________*/ - - -/*_____ F U N C T I O N S __________________________________________________*/ - -/***************************************************************************** -* Function : UART2_IRQHandler -* Description : UART2 interrupt service routine -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -__irq void UART2_IRQHandler (void) -{ - uint32_t II_Buf, LS_Buf; - volatile uint32_t Null_Buf; - - II_Buf = SN_UART2->II; - while ((II_Buf & mskUART_II_STATUS) == UART_II_STATUS) //check interrupt status, the INT can be determined by UARTn_II[3:1] - { - switch ((II_Buf>>1) & mskUART_INTID_STATUS) - { - case UART_RLS: //Receive Line Status - LS_Buf = SN_UART2->LS; - if((LS_Buf & mskUART_LS_OE) == UART_LS_OE) //Overrun Error - { } - if((LS_Buf & mskUART_LS_RXFE) == UART_LS_RXFE)//RX FIFO Error - { - if((LS_Buf & mskUART_LS_PE) == UART_LS_PE)//Parity Error - Null_Buf = SN_UART2->RB; //Clear interrupt - if((LS_Buf & mskUART_LS_FE) == UART_LS_FE) //Framing Error - Null_Buf = SN_UART2->RB; //Clear interrupt - if((LS_Buf & mskUART_LS_BI) == UART_LS_BI) //Break Interrupt - Null_Buf = SN_UART2->RB; //Clear interrupt - } - break; - - case UART_RDA: //Receive Data Available - LS_Buf = SN_UART2->LS; - bUART2_RecvNew = 1; - if((LS_Buf & mskUART_LS_RDR) == UART_LS_RDR)//Receiver Data Ready - { - bUART2_RecvFIFO[GulNum2] = SN_UART2->RB; - GulNum2++; - } - if(GulNum2 == 56) - GulNum2 = 0; - break; - - case UART_THRE: //THRE interrupt - LS_Buf = SN_UART2->LS; - if((LS_Buf & mskUART_LS_THRE) == UART_LS_THRE)//THRE empty - { //SN_UART2->TH = Null_Buf; //Clear interrupt - } - break; - - case UART_TEMT: //TEMT interrupt - LS_Buf = SN_UART2->LS; - if((LS_Buf & mskUART_LS_TEMT) == UART_LS_TEMT) - { //SN_UART2->TH = Null_Buf; //Clear interrupt - } - break; - - default: - break; - } //end switch ((II_Buf>>1) & mskUART_INTID_STATUS) - - II_Buf = SN_UART2->II; - } //end while ((II_Buf&0x01) == mskUART_II_STATUS) - - if ((II_Buf & mskUART_II_ABEOIF) == UART_II_ABEOIF) //Auto Baud interrupt - SN_UART2->ABCTRL |= UART_ABEO_EN; - else if((II_Buf & mskUART_II_ABTOIF) == UART_II_ABTOIF) //Auto Baud time-out interrupt - SN_UART2->ABCTRL |= UART_ABTO_EN; -} - - -/***************************************************************************** -* Function : UART2_Init -* Description : Initialization of UART2 -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void UART2_Init (void) -{ - SN_SYS1->AHBCLKEN |= UART2_CLK_EN; //Enables clock for UART2 - - //===Line Control=== - //setting character Word length(5/6/7/8 bit) - SN_UART2->LC = (UART_CHARACTER_LEN8BIT //8bit character length. - | UART_STOPBIT_1BIT //stop bit of 1 bit - | UART_PARITY_BIT_DISEN //parity bit is disable - | UART_PARITY_SELECTODD //parity bit is odd - | UART_BREAK_DISEN //Break Transmission control disable - | UART_DIVISOR_EN); //Divisor Latch Access enable - - //===Baud Rate Calculation=== - //UART PCLK = 12MHz, Baud rate = 115200 - SN_UART2->FD = (UART_OVER_SAMPLE_16|UART_MULVAL_7|UART_DIVADDVAL_5); - SN_UART2->DLM = 0; - SN_UART2->DLL = 4; - /* - //UART PCLK = 12MHz, Baud rate = 57600 - SN_UART2->FD = (OVER_SAMPLE_16|UART_MULVAL_7|UART_DIVADDVAL_5); - SN_UART2->DLM = 0; - SN_UART2->DLL = 8; - */ - SN_UART2->LC &= ~(UART_DIVISOR_EN); //Disable divisor latch - - //===Auto Baud Rate=== - //UART2_Autobaudrate_Init(); //Auto buad rate initial - - //===FIFO Control=== - SN_UART2->FIFOCTRL =(UART_FIFO_ENABLE //Enable UART FIFOs - | UART_RXFIFO_RESET //RX FIFO Reset - | UART_TXFIFO_RESET //TX FIFO Reset - | UART_RXTRIGGER_LEVEL1); //RX Trigger Level(1/4/8/14 characters) - - //===Scratch Pad=== - //SN_UART2->SP = 0; //A readable, writable byte - - //===Oversampling=== - //SN_UART2->FD |= UART_OVER_SAMPLE_8; //OVER8(Oversampling Value), 1:Oversampling by 8. 0:Oversampling by 16 - - //===Half-duplex=== - //SN_UART2->HDEN = 1; //Half-duplex mode enable - - //===Interrupt Enable=== - UART2_InterruptEnable(); - - //===UART Control=== - SN_UART2->CTRL =(UART_EN //Enable UART0 - | UART_RX_EN //Enable RX - | UART_TX_EN); //Enable TX - //===NVIC=== - NVIC_EnableIRQ(UART2_IRQn); //Enable UART2 INT - -} - -/***************************************************************************** -* Function : UART2_SendByte -* Description : MCU sends Byte through UTXD1 -* Input : ucDat - data to be sent -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void UART2_SendByte (uint8_t ucDat) -{ - SN_UART2->TH = ucDat; - while ((SN_UART2->LS & 0x40) == 0); -} - -/***************************************************************************** -* Function : UART2_AutoBaudrateInit -* Description : Initialization of UART2 Auto baud rate. -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void UART2_AutoBaudrateInit(void) -{ - SN_UART2->ABCTRL =(UART_ABTO_EN //Clear Auto Baud Time-out interrupt - | UART_ABEO_EN //Clear Auto Baud interrupt - | UART_ABCCTRL_RESTART //Restart in case of time-out - | UART_ABCCTRL_MODE1 //Auto Baud mode, 0:mode 0, 1:mode 1 - | UART_ABCCTRL_START); //Auto Baud start, 0:stop(not running), 1:start(running) -} - -/***************************************************************************** -* Function : UART2_Enable -* Description : Enable UART2 -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void UART2_Enable(void) -{ - //Enable HCLK for UART2 - SN_SYS1->AHBCLKEN |= UART2_CLK_EN; //Enables clock for UART2 - SN_UART2->CTRL_b.UARTEN = UART_CTRL_EN; //UART enable bit -} - -/***************************************************************************** -* Function : UART2_Disable -* Description : Disable UART2 -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void UART2_Disable(void) -{ - SN_UART2->CTRL_b.UARTEN = UART_CTRL_DIS; //UART disable - //Disable HCLK for UART2 - SN_SYS1->AHBCLKEN &= ~(UART2_CLK_EN); //Disable clock for UART2 -} - -/***************************************************************************** -* Function : UART2_InterruptEnable -* Description : Interrupt Enable -* Input : None -* Output : None -* Return : None -* Note : None -*****************************************************************************/ -void UART2_InterruptEnable(void) -{ - SN_UART2->IE =(UART_RDAIE_EN //Enables the Receive Data Available(RDA) interrupt - | UART_THREIE_EN //Enable THRE interrupt - | UART_RLSIE_EN //Enable Receive Line Status(RLS) interrupt - | UART_TEMTIE_EN //Enable TEMT interrupt - | UART_ABEOIE_EN //Enable Auto Baud interrupt - | UART_ABTOIE_EN); //Enable Auto Baud time-out interrupt -} - diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/UART/driver.mk b/os/hal/ports/SN32/LLD/SN32F2xx/UART/driver.mk new file mode 100644 index 0000000000..fb9381a036 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/UART/driver.mk @@ -0,0 +1,13 @@ +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_serial_lld.c +endif +ifneq ($(findstring HAL_USE_UART TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_uart_lld.c +endif +else +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_serial_lld.c +PLATFORMSRC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_uart_lld.c +endif + +PLATFORMINC_CONTRIB += $(CHIBIOS_CONTRIB)/os/hal/ports/SN32/LLD/SN32F2xx/UART diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_serial_lld.c b/os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_serial_lld.c new file mode 100644 index 0000000000..3c3748ed2a --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_serial_lld.c @@ -0,0 +1,527 @@ +/* + Copyright (C) 2024 Dimitris Mantzouranis + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file UART/hal_serial_lld.c + * @brief SN32 low level serial driver code. + * + * @addtogroup SERIAL + * @{ + */ + +#include "hal.h" +#include "matrix.h" +#include "print.h" +#include +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief UART0 serial driver identifier.*/ +#if SN32_SERIAL_USE_UART0 || defined(__DOXYGEN__) +SerialDriver SD0; +#endif + +/** @brief UART1 serial driver identifier.*/ +#if SN32_SERIAL_USE_UART1 || defined(__DOXYGEN__) +SerialDriver SD1; +#endif + +/** @brief UART2 serial driver identifier.*/ +#if SN32_SERIAL_USE_UART2 || defined(__DOXYGEN__) +SerialDriver SD2; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/* Driver default configuration.*/ +static const SerialConfig default_config = {SERIAL_DEFAULT_BITRATE, + UART_WordLength_8b, + UART_StopBits_One, + UART_Parity_None, + (UART_FIFO_Enable | UART_RxFIFOThreshold_1), + UART_AutoBaudControl_None, + UART_Oversample_16, + UART_FullDuplexEnable}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ +void UART_divisor_CAL(uint32_t baudrate,uint32_t UART_PCLK,uint8_t Oversampling,uint8_t *dlm,uint8_t *dll,uint8_t *d_divaddval,uint8_t *d_mulval) +{ + float expected_val; + uint8_t divaddval[2],mulval[2]; + uint8_t divider_Index = 0; + uint8_t f_divider_new=0; + uint16_t divisor=0; + float divider_plus,divider_minus,divider_expected; + uint32_t i,j,k; + + //Init + for(i=0;i<2;i++) { + mulval[i] = 0; + divaddval[i] = 0; + } + + expected_val = (float)(UART_PCLK/Oversampling/baudrate); + + if((int)expected_val == expected_val) { + divisor = expected_val; + // no fractional divider needed + divaddval[0] = 0; + mulval[0] = 1; + } else { + // we have to use the fractional divider + // generate a lookup table + uint8_t mulval_limit = 16; + uint8_t divaddval_limit =15; + float tab_D_div_M[mulval_limit][divaddval_limit]; + for (uint8_t i = 0; i < mulval_limit; i++) { + for (uint8_t j = 0; j < divaddval_limit; j++) { + tab_D_div_M[i][j] = (float)j / (i + 1); + } + } + // go through the table until we have a match + for(i=expected_val/2;ik) { + if(tab_D_div_M[j][k]>divider_minus && tab_D_div_M[j][k]>8)&0xff; + *dll = divisor&0xff; + *d_mulval = mulval[0]; + *d_divaddval = divaddval[0]; + } +} +/** + * @brief UART initialization. + * @details This function must be invoked with interrupts disabled. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration + */ +static void uart_init(SerialDriver *sdp, const SerialConfig *config) { + uint32_t apbclock; + uint8_t dlm, dll, divaddval, mulval, oversampling; + sn32_uart_t *u = sdp->uart; + + // Default to oversampling by 16 + oversampling = (config->UART_Oversampling == UART_Oversample_8) ? 8 : 16; + apbclock = (SN32_HCLK); + + // Calculate divider + UART_divisor_CAL(config->speed,apbclock,oversampling,&dlm,&dll,&divaddval,&mulval); + + // Update the registers + u->LC = UART_Divisor_Latch_Access_Enable; + u->LC |= (config->UART_WordLength + | config->UART_StopBits + | config->UART_Parity + | UART_Break_Control_Disable); + + u->FD_b.MULVAL = mulval; + u->FD_b.DIVADDVAL = divaddval; + u->FD_b.OVER8 = (oversampling == 8) ? 1 : 0; + u->DLM = dlm; + u->DLL = dll; + + u->LC &= ~(UART_Divisor_Latch_Access_Enable); + // Disable AutoBaud for serial - not useful + u->ABCTRL = UART_AutoBaudControl_None; + + // Configure full or half duplex mode + u->HDEN = config->UART_HalfDuplexMode; + + // Reset FIFO and enable + // Set RX trigger level + u->FIFOCTRL = (UART_FIFO_Enable + | UART_RxFIFO_Reset + | UART_TxFIFO_Reset + | config->UART_FIFOControl); + + /* Enable Interrupts*/ + u->IE = (UART_ReceiveDataAvailable | UART_ReceiveLine); + + // Enable UART + u->CTRL = (UART_Enable| UART_RxEnable | UART_TxEnable); +} + +/** + * @brief UART de-initialization. + * @details This function must be invoked with interrupts disabled. + * + * @param[in] u pointer to an UART I/O block + */ +static void uart_deinit(sn32_uart_t *u) { + // disable FIFOs + u->FIFOCTRL_b.FIFOEN =0; + // disable interrupts + u->IE =0; + // disable UART peripheral + u->CTRL =0; +} + +/** + * @brief Error handling routine. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] ls UART LS register value +*/ +static void set_error(SerialDriver *sdp, uint8_t ls) { + eventflags_t sts = 0; + + if(ls & UART_LineStatus_BI) + sts |= SD_BREAK_DETECTED; + if (ls & UART_LineStatus_PE) + sts |= SD_PARITY_ERROR; + if (ls & UART_LineStatus_FE) + sts |= SD_FRAMING_ERROR; + + osalSysLockFromISR(); + chnAddFlagsI(sdp, sts); + osalSysUnlockFromISR(); +} + +/** + * @brief Common IRQ handler. + * + * @param[in] sdp communication channel associated to the UART + */ +static void serve_interrupt(SerialDriver *sdp) { + #define UART_LS_STATUS (UART_LineStatus_PE | UART_LineStatus_FE | UART_LineStatus_BI | UART_LineStatus_RxError) + sn32_uart_t *u = sdp->uart; + uint32_t ii=u->II; + + while ((ii & UART_Interrupt_Status) == UART_Interrupt_Pending) { + uint32_t ls = u->LS; + if (ls & UART_LineStatus_BI) { + set_error(sdp,UART_LineStatus_BI); + u-> IE &= ~(UART_ReceiveLine); + (void)u->RB; + ii=u->II; + break; + } + + if(ls & UART_LS_STATUS) set_error(sdp, ls); + + while (ls & UART_LineStatus_RDR) { + osalSysLockFromISR(); + if (iqIsEmptyI(&sdp->iqueue)) + chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE); + osalSysUnlockFromISR(); + osalSysLockFromISR(); + if (iqPutI(&sdp->iqueue, u->RB) < MSG_OK) + chnAddFlagsI(sdp, SD_OVERRUN_ERROR); + osalSysUnlockFromISR(); + ls = u->LS; + } + uint32_t ie = u->IE; + + if (ie & UART_TransmitterHoldingEmpty) { + while (ls & UART_LineStatus_THRE) { + msg_t b; + + osalSysLockFromISR(); + b = oqGetI(&sdp->oqueue); + osalSysUnlockFromISR(); + if (b < MSG_OK) { + osalSysLockFromISR(); + chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); + osalSysUnlockFromISR(); + u->IE &= ~(UART_TransmitterHoldingEmpty); + break; + } + u->TH = b; + osalSysUnlockFromISR(); + ls = u->LS; + } + } + + if ((ie & UART_TransmitterEmpty) && (ls & UART_LineStatus_TEMT)) { + osalSysLockFromISR(); + if (oqIsEmptyI(&sdp->oqueue)) { + chnAddFlagsI(sdp, CHN_TRANSMISSION_END); + u->IE &= ~(UART_TransmitterEmpty); + } + osalSysUnlockFromISR(); + } + ii=u->II; + } +} + +static void load(SerialDriver *sdp) { + sn32_uart_t *u = sdp->uart; + if (u->LS & UART_LineStatus_THRE) { + osalSysLock(); + msg_t b = oqGetI(&sdp->oqueue); + osalSysUnlock(); + if (b < MSG_OK) { + osalSysLock(); + chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); + osalSysUnlock(); + return; + } + u->TH = b; + } + u->IE |= (UART_TransmitterHoldingEmpty | UART_TransmitterEmpty); +} +#if SN32_SERIAL_USE_UART0 || defined(__DOXYGEN__) +static void notify0(io_queue_t *qp) { + + (void)qp; + load(&SD0); +} +#endif + +#if SN32_SERIAL_USE_UART1 || defined(__DOXYGEN__) +static void notify1(io_queue_t *qp) { + + (void)qp; + load(&SD1); +} +#endif + +#if SN32_SERIAL_USE_UART2 || defined(__DOXYGEN__) +static void notify2(io_queue_t *qp) { + + (void)qp; + load(&SD2); +} +#endif +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if SN32_SERIAL_USE_UART0 || defined(__DOXYGEN__) +#if !defined(SN32_UART0_HANDLER) +#error "SN32_UART0_HANDLER not defined" +#endif +/** + * @brief UART0 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(SN32_UART0_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + serve_interrupt(&SD0); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if SN32_SERIAL_USE_UART1 || defined(__DOXYGEN__) +#if !defined(SN32_UART1_HANDLER) +#error "SN32_UART1_HANDLER not defined" +#endif +/** + * @brief UART1 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(SN32_UART1_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + serve_interrupt(&SD1); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if SN32_SERIAL_USE_UART2 || defined(__DOXYGEN__) +#if !defined(SN32_UART2_HANDLER) +#error "SN32_UART2_HANDLER not defined" +#endif +/** + * @brief UART2 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(SN32_UART2_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + serve_interrupt(&SD2); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level serial driver initialization. + * + * @notapi + */ +void sd_lld_init(void) { + +#if SN32_SERIAL_USE_UART0 + sdObjectInit(&SD0, NULL, notify0); + SD0.uart = SN32_UART0; +#endif + +#if SN32_SERIAL_USE_UART1 + sdObjectInit(&SD1, NULL, notify1); + SD1.uart = SN32_UART1; +#endif + +#if SN32_SERIAL_USE_UART2 + sdObjectInit(&SD2, NULL, notify2); + SD2.uart = SN32_UART2; +#endif +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + * + * @notapi + */ +void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { + + if (config == NULL) + config = &default_config; + + if (sdp->state == SD_STOP) { +#if SN32_SERIAL_USE_UART0 + if (&SD0 == sdp) { + /* UART0 clock enable.*/ + sys1EnableUART0(); + uart_init(sdp, config); + nvicEnableVector(SN32_UART0_NUMBER, SN32_SERIAL_UART0_PRIORITY); + } +#endif +#if SN32_SERIAL_USE_UART1 + if (&SD1 == sdp) { + /* UART1 clock enable.*/ + sys1EnableUART1(); + uart_init(sdp, config); + nvicEnableVector(SN32_UART1_NUMBER, SN32_SERIAL_UART1_PRIORITY); + } +#endif +#if SN32_SERIAL_USE_UART2 + if (&SD2 == sdp) { + /* UART2 clock enable.*/ + sys1EnableUART2(); + uart_init(sdp, config); + nvicEnableVector(SN32_UART2_NUMBER, SN32_SERIAL_UART2_PRIORITY); + } +#endif + } +} + +/** + * @brief Low level serial driver stop. + * @details De-initializes the UART, stops the associated clock, resets the + * interrupt vector. + * + * @param[in] sdp pointer to a @p SerialDriver object + * + * @notapi + */ +void sd_lld_stop(SerialDriver *sdp) { + + if (sdp->state == SD_READY) { + uart_deinit(sdp->uart); +#if SN32_SERIAL_USE_UART0 + if (&SD0 == sdp) { + /* UART0 DeInit.*/ + sys1DisableUART0(); + nvicDisableVector(SN32_UART0_NUMBER); + return; + } +#endif +#if SN32_SERIAL_USE_UART1 + if (&SD1 == sdp) { + /* UART1 DeInit.*/ + sys1DisableUART1(); + nvicDisableVector(SN32_UART1_NUMBER); + return; + } +#endif +#if SN32_SERIAL_USE_UART2 + if (&SD2 == sdp) { + /* UART2 DeInit.*/ + sys1DisableUART2(); + nvicDisableVector(SN32_UART2_NUMBER); + return; + } +#endif + } +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_serial_lld.h b/os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_serial_lld.h new file mode 100644 index 0000000000..ec37948f2f --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_serial_lld.h @@ -0,0 +1,245 @@ +/* + Copyright (C) 2024 Dimitris Mantzouranis + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file UART/hal_serial_lld.h + * @brief SN32 low level serial driver header. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef HAL_SERIAL_LLD_H +#define HAL_SERIAL_LLD_H + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +#include "sn32_uart.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief UART0 driver enable switch. + * @details If set to @p TRUE the support for UART0 is included. + * @note The default is @p FALSE. + */ +#if !defined(SN32_SERIAL_USE_UART0) || defined(__DOXYGEN__) +#define SN32_SERIAL_USE_UART0 FALSE +#endif + +/** + * @brief UART1 driver enable switch. + * @details If set to @p TRUE the support for UART1 is included. + * @note The default is @p FALSE. + */ +#if !defined(SN32_SERIAL_USE_UART1) || defined(__DOXYGEN__) +#define SN32_SERIAL_USE_UART1 FALSE +#endif + +/** + * @brief UART2 driver enable switch. + * @details If set to @p TRUE the support for UART2 is included. + * @note The default is @p FALSE. + */ +#if !defined(SN32_SERIAL_USE_UART2) || defined(__DOXYGEN__) +#define SN32_SERIAL_USE_UART2 FALSE +#endif + +/** + * @brief UART0 interrupt priority level setting. + */ +#if !defined(SN32_SERIAL_UART0_PRIORITY) || defined(__DOXYGEN__) +#define SN32_SERIAL_UART0_PRIORITY 3 +#endif + +/** + * @brief UART1 interrupt priority level setting. + */ +#if !defined(SN32_SERIAL_UART1_PRIORITY) || defined(__DOXYGEN__) +#define SN32_SERIAL_UART1_PRIORITY 3 +#endif + +/** + * @brief UART2 interrupt priority level setting. + */ +#if !defined(SN32_SERIAL_UART2_PRIORITY) || defined(__DOXYGEN__) +#define SN32_SERIAL_UART2_PRIORITY 3 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if SN32_SERIAL_USE_UART0 && !SN32_HAS_UART0 +#error "UART0 not present in the selected device" +#endif + +#if SN32_SERIAL_USE_UART1 && !SN32_HAS_UART1 +#error "UART1 not present in the selected device" +#endif + +#if SN32_SERIAL_USE_UART2 && !SN32_HAS_UART2 +#error "UART2 not present in the selected device" +#endif + +#if !SN32_SERIAL_USE_UART0 && !SN32_SERIAL_USE_UART1 && \ + !SN32_SERIAL_USE_UART2 +#error "SERIAL driver activated but no UART/UART peripheral assigned" +#endif + +#if SN32_SERIAL_USE_UART0 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(SN32_SERIAL_UART0_PRIORITY) +#error "Invalid IRQ priority assigned to UART0" +#endif + +#if SN32_SERIAL_USE_UART1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(SN32_SERIAL_UART1_PRIORITY) +#error "Invalid IRQ priority assigned to UART1" +#endif + +#if SN32_SERIAL_USE_UART2 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(SN32_SERIAL_UART2_PRIORITY) +#error "Invalid IRQ priority assigned to UART2" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +#if SN32_HAS_UART0 +#define SN32_UART0_BASE SN_UART0_BASE +#define SN32_UART0 ((sn32_uart_t *)SN_UART0_BASE) +#endif + +#if SN32_HAS_UART1 +#define SN32_UART1_BASE SN_UART1_BASE +#define SN32_UART1 ((sn32_uart_t *)SN_UART1_BASE) +#endif + +#if SN32_HAS_UART2 +#define SN32_UART2_BASE SN_UART2_BASE +#define SN32_UART2 ((sn32_uart_t *)SN_UART2_BASE) +#endif + +/** + * @brief SN32 Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + * @note This structure content is architecture dependent, each driver + * implementation defines its own version and the custom static + * initializers. + */ +typedef struct { + /** + * @brief This member configures the UART communication baud rate. + */ + uint32_t speed; + /** + * @brief Specifies the number of data bits transmitted or received in a frame. + * This parameter can be a value of @ref UART_Word_Length + */ + uint8_t UART_WordLength; + /** + * @brief Specifies the number of stop bits transmitted. + * This parameter can be a value of @ref UART_Stop_Bits + */ + uint8_t UART_StopBits; + /** + * @brief Specifies the parity mode. + * This parameter can be a value of @ref UART_Parity + */ + uint8_t UART_Parity; + /** + * @brief Controls the operation of the UART RX and TX FIFOs. + */ + uint32_t UART_FIFOControl; + /** + * @brief Specifies the auto flow control mode and configures functionality. + */ + uint32_t UART_AutoBaudControl; + /** + * @brief Specifies the oversampling rate. + * This parameter can be a value of @ref UART_Oversample + */ + uint16_t UART_Oversampling; + /** + * @brief Enables half-duplex mode. + */ + uint8_t UART_HalfDuplexMode; +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + input_queue_t iqueue; \ + /* Output queue.*/ \ + output_queue_t oqueue; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ \ + /* Pointer to the UART registers block.*/ \ + sn32_uart_t *uart; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if SN32_SERIAL_USE_UART0 && !defined(__DOXYGEN__) +extern SerialDriver SD0; +#endif +#if SN32_SERIAL_USE_UART1 && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif +#if SN32_SERIAL_USE_UART2 && !defined(__DOXYGEN__) +extern SerialDriver SD2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* HAL_SERIAL_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_uart_lld.c b/os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_uart_lld.c new file mode 100644 index 0000000000..1a9caea3af --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_uart_lld.c @@ -0,0 +1,554 @@ +/* + Copyright (C) 2024 Dimitris Mantzouranis + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file UART/hal_uart_lld.c + * @brief SN32 low level UART driver code. + * + * @addtogroup UART + * @{ + */ + +#include "hal.h" + +#if HAL_USE_UART || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief UART0 UART driver identifier.*/ +#if SN32_UART_USE_UART0 || defined(__DOXYGEN__) +UARTDriver UARTD0; +#endif + +/** @brief UART1 UART driver identifier.*/ +#if SN32_UART_USE_UART1 || defined(__DOXYGEN__) +UARTDriver UARTD1; +#endif + +/** @brief UART2 UART driver identifier.*/ +#if SN32_UART_USE_UART2 || defined(__DOXYGEN__) +UARTDriver UARTD2; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Status bits translation. + * + * @param[in] ls UART LS register value + * + * @return The error flags. + */ +static uartflags_t translate_errors(uint32_t ls) { + uartflags_t sts = 0; + + if (ls & UART_LineStatus_OE) + sts |= UART_OVERRUN_ERROR; + if (ls & UART_LineStatus_PE) + sts |= UART_PARITY_ERROR; + if (ls & UART_LineStatus_FE) + sts |= UART_FRAMING_ERROR; + if (ls & UART_LineStatus_BI) + sts |= UART_BREAK_DETECTED; + if (ls & UART_LineStatus_RDR) + sts |= UART_NOISE_ERROR; + return sts; +} + +/** + * @brief Puts the receiver in the UART_RX_IDLE state. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +static void uart_enter_rx_idle_loop(UARTDriver *uartp) { + + uartp->xfer.rx_len = 1; + uartp->xfer.rx_buf = (uint8_t *)&uartp->rxbuf; + + uartp->uart->IE |= UART_ReceiveDataAvailable; +} + +/** + * @brief UART de-initialization. + * @details This function must be invoked with interrupts disabled. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +static void uart_stop(UARTDriver *uartp) { + + /* Disable the UART Interrupt.*/ + uartp->uart->IE &= ~(0x7FF); +} + +/** + * @brief UART initialization. + * @details This function must be invoked with interrupts disabled. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +static void uart_start(UARTDriver *uartp) { + uint32_t divider, apbclock; + uint8_t dlm, dll, divaddval, mulval, oversampling; + sn32_uart_t *u = uartp->uart; + + uart_stop(uartp); + + u->ABCTRL = uartp->config->UART_AutoBaudControl; + + apbclock = SN32_HCLK; + + // Default to oversampling by 16 + oversampling = (config->UART_Oversampling == UART_Oversample_8) ? 8 : 16; + + // Check constraints based on oversampling value + if (oversampling == 8) { + chDbgAssert(oversampling * uartp->config->UART_BaudRate <= apbclock / 8, + "Invalid oversampling configuration for requested baud rate"); + } else if (oversampling == 16) { + chDbgAssert(oversampling * uartp->config->UART_BaudRate <= apbclock / 16, + "Invalid oversampling configuration for requested baud rate"); + } + + // Calculate divider + uint32_t rounded_sum = apbclock + (uartp->config->UART_BaudRate >> 1); + divider = rounded_sum / (uartp->config->UART_BaudRate * oversampling); + + // Calculate DLM and DLL + dlm = (uint8_t)(divider >> 8); + dll = (uint8_t)(divider & 0xFF); + + // Calculate fractional part + uint32_t fractional_part = (rounded_sum % (uartp->config->UART_BaudRate * + oversampling)) * (uartp->config->UART_WordLength + 1) * oversampling; + + // Calculate DIVADDVAL and MULVAL + divaddval = (uint8_t)((fractional_part >> 4) & 0x0F); + mulval = (uint8_t)(fractional_part & 0x0F); + + // Check and adjust DLL value if needed + if (divaddval > 0 && dlm == 0 && dll < 3) { + dll = 3; // Set to the minimum value + } + + // Check and adjust MULVAL if needed + if (mulval - divaddval == 2) { + mulval++; // Adjust mulval to satisfy the condition + } + + // Update the registers + u->LC = UART_Divisor_Latch_Access_Enable; + u->LC |= (config->UART_WordLength + | config->UART_StopBits + | config->UART_Parity + | UART_Break_Control_Disable); + + u->FD_b.MULVAL = mulval; + u->FD_b.DIVADDVAL = divaddval; + u->FD_b.OVER8 = (oversampling == 8) ? 1 : 0; + u->DLM = dlm; + u->DLL = dll; + + u->LC &= ~(UART_Divisor_Latch_Access_Enable); + // Configure full or half duplex mode + u->HDEN = config->UART_HalfDuplexMode; + + // Set RX trigger level + u->FIFOCTRL |= uartp->config->UART_FIFOControl; + + // AutoBaud reset and init + u->ABCTRL |= (UART_AutoBaudControl_Timeout | UART_AutoBaudControl_Timeout | + UART_AutoBaudControl_Restart | UART_AutoBaudControl_Start); + + // Reset FIFO and enable + u->FIFOCTRL |= (UART_TxFIFO_Reset | UART_RxFIFO_Reset | UART_FIFO_Enable); + + // Enable AutoBaud Interrupts + u->IE |= (UART_AutoBaudTimeout | UART_AutoBaudEnd); + + // Enable UART + u->CTRL = (UART_TxEnable | UART_RxEnable | UART_Enable); + + /* Starting the receiver idle loop.*/ + uart_enter_rx_idle_loop(uartp); +} + +/** + * @brief UART common service routine. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +static void serve_uart_irq(UARTDriver *uartp) { + sn32_uart_t *u = uartp->uart; + uint32_t ls; + uint8_t rbyte; + uint32_t int_ii; + + int_ii = u->II; + // Check for pending interrupts + while((int_ii & UART_Interrupt_Status) == UART_Interrupt_Pending) { + // Check INTID + switch ((int_ii>>1) & UART_InterruptID_Status) { + case UART_InterruptID_RLS: + ls = (uint32_t)u->LS; + if (ls & (UART_LineStatus_PE | UART_LineStatus_FE | UART_LineStatus_OE | + UART_LineStatus_RDR | UART_LineStatus_BI)) { + _uart_rx_error_isr_code(uartp, translate_errors(ls)); + } + break; + case UART_InterruptID_RDA: + /* Receive One Byte.*/ + rbyte = (uint16_t)u->RB; + if (uartp->xfer.rx_len) { + *uartp->xfer.rx_buf = rbyte; + uartp->xfer.rx_buf++; + uartp->xfer.rx_len--; + if (uartp->xfer.rx_len == 0) { + if (uartp->rxstate == UART_RX_IDLE) { + /* Receiver in idle state, a callback is generated, if enabled, + for each received character and then the driver stays in the + same state.*/ + _uart_rx_idle_code(uartp); + } + else { + _uart_rx_complete_isr_code(uartp); + } + } + } + break; + case UART_InterruptID_CTI: + /* FIFO Time out.*/ + while ((u->LS & UART_LineStatus_RDR) == UART_LineStatus_RDR) { + rbyte = (uint16_t)u->RB; + if (uartp->xfer.rx_len) { + *uartp->xfer.rx_buf = rbyte; + uartp->xfer.rx_buf++; + uartp->xfer.rx_len--; + if (uartp->xfer.rx_len == 0) { + if (uartp->rxstate == UART_RX_IDLE) { + /* Receiver in idle state, a callback is generated, + if enabled, for each received character and then the + driver stays in the same state.*/ + _uart_rx_idle_code(uartp); + } + else { + _uart_rx_complete_isr_code(uartp); + } + } + } + } + /* Timeout interrupt sources are only checked if enabled in IE.*/ + _uart_timeout_isr_code(uartp); + break; + case UART_InterruptID_THRE: + /* Send One Byte.*/ + if (uartp->xfer.tx_len) { + u->TH = (uint16_t)*uartp->xfer.tx_buf; + uartp->xfer.tx_buf++; + uartp->xfer.tx_len--; + if (uartp->xfer.tx_len == 0) { + /* A callback is generated, if enabled, after a completed + transfer.*/ + _uart_tx1_isr_code(uartp); + /* End of transmission, a callback is generated.*/ + _uart_tx2_isr_code(uartp); + /* Disable tx interrupt.*/ + u->IE &= ~UART_TransmitterHoldingEmpty; + } + } + break; + case UART_InterruptID_TEMT: + /* Physical transmission end.*/ + /* A callback is generated, if enabled, after a completed + transfer.*/ + _uart_tx1_isr_code(uartp); + /* End of transmission, a callback is generated.*/ + _uart_tx2_isr_code(uartp); + break; + default: + break; + } + // Update II status + int_ii = u->II; + } + // AutoBaud interrupts + if ((int_ii & UART_AutoBaudEnd) == UART_InterruptEnable) + u->ABCTRL |= UART_AutoBaudControl_End; + else if((int_ii & UART_AutoBaudTimeout) == UART_InterruptEnable) + u->ABCTRL |= UART_AutoBaudControl_Timeout; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if SN32_UART_USE_UART0 || defined(__DOXYGEN__) +#if !defined(SN32_UART0_HANDLER) +#error "SN32_UART0_HANDLER not defined" +#endif +/** + * @brief UART0 IRQ handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(SN32_UART0_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + serve_uart_irq(&UARTD0); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* SN32_UART_USE_UART0 */ + +#if SN32_UART_USE_UART1 || defined(__DOXYGEN__) +#if !defined(SN32_UART1_HANDLER) +#error "SN32_UART0_HANDLER not defined" +#endif +/** + * @brief UART1 IRQ handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(SN32_UART1_IRQ_VECTOR) { + + OSAL_IRQ_PROLOGUE(); + + serve_uart_irq(&UARTD1); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* SN32_UART_USE_UART1 */ + +#if SN32_UART_USE_UART2 || defined(__DOXYGEN__) +#if !defined(SN32_UART2_HANDLER) +#error "SN32_UART2_HANDLER not defined" +#endif +/** + * @brief UART2 IRQ handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(SN32_UART2_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + serve_uart_irq(&UARTD2); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* SN32_UART_USE_UART2 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level UART driver initialization. + * + * @notapi + */ +void uart_lld_init(void) { + +#if SN32_UART_USE_UART0 + uartObjectInit(&UARTD0); + UARTD0.uart = SN32_UART0; +#endif + +#if SN32_UART_USE_UART1 + uartObjectInit(&UARTD1); + UARTD1.uart = SN32_UART1; +#endif + +#if SN32_UART_USE_UART2 + uartObjectInit(&UARTD2); + UARTD2.uart = SN32_UART2; +#endif +} + +/** + * @brief Configures and activates the UART peripheral. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @notapi + */ +void uart_lld_start(UARTDriver *uartp) { + + if (uartp->state == UART_STOP) { +#if SN32_UART_USE_UART0 + if (&UARTD0 == uartp) { + /* UART0 clock enable.*/ + sys1EnableUART0(); + nvicClearPending(SN32_UART0_NUMBER); + nvicEnableVector(SN32_UART0_NUMBER, SN32_UART_UART0_IRQ_PRIORITY); + } +#endif + +#if SN32_UART_USE_UART1 + if (&UARTD1 == uartp) { + /* UART1 clock enable.*/ + sys1EnableUART1(); + nvicClearPending(SN32_UART1_NUMBER); + nvicEnableVector(SN32_UART1_NUMBER, SN32_UART_UART1_IRQ_PRIORITY); + } +#endif + +#if SN32_UART_USE_UART2 + if (&UARTD2 == uartp) { + /* UART2 clock enable.*/ + sys1EnableUART2(); + nvicClearPending(SN32_UART2_NUMBER); + nvicEnableVector(SN32_UART2_NUMBER, SN32_UART_UART2_IRQ_PRIORITY); + } +#endif + } + uartp->rxstate = UART_RX_IDLE; + uartp->txstate = UART_TX_IDLE; + uart_start(uartp); +} + +/** + * @brief Deactivates the UART peripheral. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @notapi + */ +void uart_lld_stop(UARTDriver *uartp) { + + if (uartp->state == UART_READY) { + uartp->xfer.tx_len = 0; + uartp->xfer.rx_len = 0; + uartp->xfer.tx_buf = NULL; + uartp->xfer.rx_buf = NULL; + uartp->xfer.tx_abrt_source = 0; + + uart_stop(uartp); + +#if SN32_UART_USE_UART0 + if (&UARTD0 == uartp) { + nvicDisableVector(SN32_UART0_NUMBER); + sys1DisableUART0(); + return; + } +#endif + +#if SN32_UART_USE_UART1 + if (&UARTD1 == uartp) { + nvicDisableVector(SN32_UART1_NUMBER); + sys1DisableUART1(); + return; + } +#endif + +#if SN32_UART_USE_UART2 + if (&UARTD2 == uartp) { + nvicDisableVector(SN32_UART2_NUMBER); + sys1DisableUART2(); + return; + } +#endif + } +} + +/** + * @brief Starts a transmission on the UART peripheral. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] n number of data frames to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) { + + uartp->xfer.tx_len = n; + uartp->xfer.tx_buf = txbuf; + + uartp->uart->IE |= UART_TransmitterHoldingEmpty; +} + +/** + * @brief Stops any ongoing transmission. + * @note Stopping a transmission also suppresses the transmission callbacks. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @return The number of data frames not transmitted by the + * stopped transmit operation. + * + * @notapi + */ +size_t uart_lld_stop_send(UARTDriver *uartp) { + + uartp->uart->IE &= ~(UART_TransmitterHoldingEmpty); + + return (size_t)(uartp->xfer.tx_len); +} + +/** + * @brief Starts a receive operation on the UART peripheral. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] n number of data frames to send + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) { + + uartp->xfer.rx_len = n; + uartp->xfer.rx_buf = rxbuf; + + uartp->uart->IE |= UART_ReceiveDataAvailable; +} + +/** + * @brief Stops any ongoing receive operation. + * @note Stopping a receive operation also suppresses the receive callbacks. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @return The number of data frames not received by the + * stopped receive operation. + * + * @notapi + */ +size_t uart_lld_stop_receive(UARTDriver *uartp) { + uartp->uart->IE &= ~(UART_ReceiveDataAvailable); + + return (size_t)(uartp->xfer.rx_len); +} + +#endif /* HAL_USE_UART */ + +/** @} */ \ No newline at end of file diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_uart_lld.h b/os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_uart_lld.h new file mode 100644 index 0000000000..608515fa65 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_uart_lld.h @@ -0,0 +1,353 @@ +/* + Copyright (C) 2024 Dimitris Mantzouranis + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file UART/hal_uart_lld.h + * @brief SN32 low level UART driver header. + * + * @addtogroup UART + * @{ + */ + +#ifndef HAL_UART_LLD_H +#define HAL_UART_LLD_H + +#if HAL_USE_UART || defined(__DOXYGEN__) + +#include "sn32_uart.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief UART driver on UART0 enable switch. + * @details If set to @p TRUE the support for UART0 is included. + * @note The default is @p FALSE. + */ +#if !defined(SN32_UART_USE_UART0) || defined(__DOXYGEN__) +#define SN32_UART_USE_UART0 FALSE +#endif + +/** + * @brief UART driver on UART1 enable switch. + * @details If set to @p TRUE the support for UART1 is included. + * @note The default is @p FALSE. + */ +#if !defined(SN32_UART_USE_UART1) || defined(__DOXYGEN__) +#define SN32_UART_USE_UART1 FALSE +#endif + +/** + * @brief UART driver on UART2 enable switch. + * @details If set to @p TRUE the support for UART2 is included. + * @note The default is @p FALSE. + */ +#if !defined(SN32_UART_USE_UART2) || defined(__DOXYGEN__) +#define SN32_UART_USE_UART2 FALSE +#endif + +/** + * @brief UART0 interrupt priority level setting. + */ +#if !defined(SN32_UART_UART0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define SN32_UART_UART0_IRQ_PRIORITY 3 +#endif + +/** + * @brief UART1 interrupt priority level setting. + */ +#if !defined(SN32_UART_UART1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define SN32_UART_UART1_IRQ_PRIORITY 3 +#endif + +/** + * @brief UART2 interrupt priority level setting. + */ +#if !defined(SN32_UART_UART2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define SN32_UART_UART2_IRQ_PRIORITY 3 +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if SN32_UART_USE_UART0 && !SN32_HAS_UART0 +#error "UART0 not present in the selected device" +#endif + +#if SN32_UART_USE_UART1 && !SN32_HAS_UART1 +#error "UART1 not present in the selected device" +#endif + +#if SN32_UART_USE_UART2 && !SN32_HAS_UART2 +#error "UART2 not present in the selected device" +#endif + +#if !SN32_UART_USE_UART0 && !SN32_UART_USE_UART1 && \ + !SN32_UART_USE_UART2 +#error "UART driver activated but no UART/UART peripheral assigned" +#endif + +#if SN32_UART_USE_UART0 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(SN32_UART_UART0_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to UART0" +#endif + +#if SN32_UART_USE_UART1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(SN32_UART_UART1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to UART1" +#endif + +#if SN32_UART_USE_UART2 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(SN32_UART_UART2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to UART2" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +#if SN32_HAS_UART0 +#define SN32_UART0_BASE SN_UART0_BASE +#define SN32_UART0 ((sn32_uart_t *)SN_UART0_BASE) +#endif + +#if SN32_HAS_UART1 +#define SN32_UART1_BASE SN_UART1_BASE +#define SN32_UART1 ((sn32_uart_t *)SN_UART1_BASE) +#endif + +#if SN32_HAS_UART2 +#define SN32_UART2_BASE SN_UART2_BASE +#define SN32_UART2 ((sn32_uart_t *)SN_UART2_BASE) +#endif + +/** + * @brief UART driver condition flags type. + */ +typedef uint32_t uartflags_t; + +/** + * @brief Structure representing an UART driver. + */ +typedef struct UARTDriver UARTDriver; + +/** + * @brief Generic UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +typedef void (*uartcb_t)(UARTDriver *uartp); + +/** + * @brief Character received UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] c received character + */ +typedef void (*uartccb_t)(UARTDriver *uartp, uint16_t c); + +/** + * @brief Receive error UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] e receive error mask + */ +typedef void (*uartecb_t)(UARTDriver *uartp, uartflags_t e); + +typedef struct { + const uint8_t *tx_buf; + volatile uint32_t tx_len; + uint8_t *rx_buf; + volatile uint32_t rx_len; + uint32_t tx_abrt_source; +} uart_xfer_info_t; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief End of transmission buffer callback. + */ + uartcb_t txend1_cb; + /** + * @brief Physical end of transmission callback. + */ + uartcb_t txend2_cb; + /** + * @brief Receive buffer filled callback. + */ + uartcb_t rxend_cb; + /** + * @brief Character received while out if the @p UART_RECEIVE state. + */ + uartccb_t rxchar_cb; + /** + * @brief Receive error callback. + */ + uartecb_t rxerr_cb; + /* End of the mandatory fields.*/ + /** + * @brief Receiver timeout callback. + * @details Handles idle interrupts depending on configured + * flags in CR registers and supported hardware features. + */ + uartcb_t timeout_cb; + /** + * @brief Controls the clock prescaler for baud rate generation. + */ + uint32_t UART_BaudRate; + /** + * @brief Specifies the number of data bits transmitted or received in a frame. + * This parameter can be a value of @ref UART_Word_Length + */ + uint8_t UART_WordLength; + /** + * @brief Specifies the number of stop bits transmitted. + * This parameter can be a value of @ref UART_Stop_Bits + */ + uint8_t UART_StopBits; + /** + * @brief Specifies the parity mode. + * This parameter can be a value of @ref UART_Parity + */ + uint8_t UART_Parity; + /** + * @brief Controls the operation of the UART RX and TX FIFOs. + */ + uint32_t UART_FIFOControl; + /** + * @brief Specifies the auto flow control mode and configures functionality. + */ + uint32_t UART_AutoBaudControl; + /** + * @brief Specifies the oversampling rate. + * This parameter can be a value of @ref UART_Oversample + */ + uint16_t UART_Oversampling; + /** + * @brief Enables half-duplex mode. + */ + uint8_t UART_HalfDuplexMode; +} UARTConfig; + +/** + * @brief Structure representing an UART driver. + */ +struct UARTDriver { + /** + * @brief Driver state. + */ + uartstate_t state; + /** + * @brief Transmitter state. + */ + uarttxstate_t txstate; + /** + * @brief Receiver state. + */ + uartrxstate_t rxstate; + /** + * @brief Current configuration data. + */ + const UARTConfig *config; +#if (UART_USE_WAIT == TRUE) || defined(__DOXYGEN__) + /** + * @brief Synchronization flag for transmit operations. + */ + bool early; + /** + * @brief Waiting thread on RX. + */ + thread_reference_t threadrx; + /** + * @brief Waiting thread on TX. + */ + thread_reference_t threadtx; +#endif /* UART_USE_WAIT */ +#if (UART_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the peripheral. + */ + mutex_t mutex; +#endif /* UART_USE_MUTUAL_EXCLUSION */ +#if defined(UART_DRIVER_EXT_FIELDS) + UART_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the UART registers block. + */ + sn32_uart_t *uart; + /** + * @brief Default receive buffer while into @p UART_RX_IDLE state. + */ + volatile uint16_t rxbuf; + uart_xfer_info_t xfer; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if SN32_UART_USE_UART0 && !defined(__DOXYGEN__) +extern UARTDriver UARTD0; +#endif + +#if SN32_UART_USE_UART1 && !defined(__DOXYGEN__) +extern UARTDriver UARTD1; +#endif + +#if SN32_UART_USE_UART2 && !defined(__DOXYGEN__) +extern UARTDriver UARTD2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void uart_lld_init(void); + void uart_lld_start(UARTDriver *uartp); + void uart_lld_stop(UARTDriver *uartp); + void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf); + size_t uart_lld_stop_send(UARTDriver *uartp); + void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf); + size_t uart_lld_stop_receive(UARTDriver *uartp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_UART */ + +#endif /* HAL_UART_LLD_H */ + +/** @} */ \ No newline at end of file diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/UART/sn32_uart.h b/os/hal/ports/SN32/LLD/SN32F2xx/UART/sn32_uart.h new file mode 100644 index 0000000000..ab3c75af16 --- /dev/null +++ b/os/hal/ports/SN32/LLD/SN32F2xx/UART/sn32_uart.h @@ -0,0 +1,322 @@ +/* + Copyright (C) 2024 Dimitris Mantzouranis + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef SN32_UART_H +# define SN32_UART_H + +typedef struct { + union { + union { + __IM uint32_t RB; + + struct { + __IM uint32_t RB : 8; + } RB_b; + }; + + union { + __OM uint32_t TH; + + struct { + __OM uint32_t TH : 8; + } TH_b; + }; + + union { + __IOM uint32_t DLL; + + struct { + __IOM uint32_t DLL : 8; + } DLL_b; + }; + }; + + union { + union { + __IOM uint32_t DLM; + + struct { + __IOM uint32_t DLM : 8; + } DLM_b; + }; + + union { + __IOM uint32_t IE; + + struct { + __IOM uint32_t RDAIE : 1; + __IOM uint32_t THREIE : 1; + __IOM uint32_t RLSIE : 1; + __IM uint32_t : 1; + __IOM uint32_t TEMTIE : 1; + __IM uint32_t : 3; + __IOM uint32_t ABEOIE : 1; + __IOM uint32_t ABTOIE : 1; + } IE_b; + }; + }; + + union { + union { + __IM uint32_t II; + + struct { + __IM uint32_t INTSTATUS : 1; + __IM uint32_t INTID : 3; + __IM uint32_t : 2; + __IM uint32_t FIFOEN : 2; + __IM uint32_t ABEOIF : 1; + __IM uint32_t ABTOIF : 1; + } II_b; + }; + + union { + __OM uint32_t FIFOCTRL; + + struct { + __OM uint32_t FIFOEN : 1; + __IM uint32_t : 5; + __OM uint32_t RXTL : 2; + } FIFOCTRL_b; + }; + }; + + union { + __IOM uint32_t LC; + + struct { + __IOM uint32_t WLS : 2; + __IOM uint32_t SBS : 1; + __IOM uint32_t PE : 1; + __IOM uint32_t PS : 2; + __IOM uint32_t BC : 1; + __IOM uint32_t DLAB : 1; + } LC_b; + }; + __IM uint32_t RESERVED; + + union { + __IM uint32_t LS; + + struct { + __IM uint32_t RDR : 1; + __IM uint32_t OE : 1; + __IM uint32_t PE : 1; + __IM uint32_t FE : 1; + __IM uint32_t BI : 1; + __IM uint32_t THRE : 1; + __IM uint32_t TEMT : 1; + __IM uint32_t RXFE : 1; + } LS_b; + }; + __IM uint32_t RESERVED1; + + union { + __IOM uint32_t SP; + + struct { + __IOM uint32_t PAD : 8; + } SP_b; + }; + + union { + __IOM uint32_t ABCTRL; + + struct { + __IOM uint32_t START : 1; + __IOM uint32_t MODE : 1; + __IOM uint32_t AUTORESTART : 1; + __IM uint32_t : 5; + __OM uint32_t ABEOIFC : 1; + __OM uint32_t ABTOIFC : 1; + } ABCTRL_b; + }; + __IM uint32_t RESERVED2; + + union { + __IOM uint32_t FD; + + struct { + __IOM uint32_t DIVADDVAL : 4; + __IOM uint32_t MULVAL : 4; + __IOM uint32_t OVER8 : 1; + } FD_b; + }; + __IM uint32_t RESERVED3; + + union { + __IOM uint32_t CTRL; + + struct { + __IOM uint32_t UARTEN : 1; + __IOM uint32_t MODE : 3; + __IM uint32_t : 2; + __IOM uint32_t RXEN : 1; + __IOM uint32_t TXEN : 1; + } CTRL_b; + }; + + union { + __IOM uint32_t HDEN; + + struct { + __IOM uint32_t HDEN : 1; + } HDEN_b; + }; +} sn32_uart_t; + +/** @defgroup UART_Exported_Constants + * @{ + */ + +/** @defgroup UART_LineControl + * @{ + */ +#define UART_Break_Control_Disable (0x0<<6) +#define UART_Break_Control_Enable (0x1<<6) +#define UART_Divisor_Latch_Access_Disable (0x0<<7) +#define UART_Divisor_Latch_Access_Enable (0x1<<7) +#define UART_Parity_None (0x0<<3) +#define UART_Parity_Enable (0x1<<3) +#define UART_Parity_Odd (0x00<<4) +#define UART_Parity_Even (0x01<<4) +#define UART_Parity_Mark (0x02<<4) +#define UART_Parity_Space (0x03<<4) +#define UART_StopBits_One (0x0<<2) +#define UART_StopBits_Two (0x1<<2) +#define UART_WordLength_5b (0x00) +#define UART_WordLength_6b (0x01) +#define UART_WordLength_7b (0x02) +#define UART_WordLength_8b (0x03) +/** + * @} + */ + + +/** @defgroup UART_AutoBaudControl + * @{ + */ +#define UART_AutoBaudControl_None 0 +#define UART_AutoBaudControl_Start (0x01) +#define UART_AutoBaudControl_Restart (UART_AutoBaudControl_Start <<2) +#define UART_AutoBaudControl_End (UART_AutoBaudControl_Start <<8) +#define UART_AutoBaudControl_Timeout (UART_AutoBaudControl_Start <<9) +#define UART_ABCTRL_MODE(x) ((0x00 + x) << 1) +/** + * @} + */ + + +/** @defgroup UART_FIFOControl + * @{ + */ +#define UART_FIFO_Enable (0x01) +#define UART_RxFIFO_Reset (0x01<<1) +#define UART_TxFIFO_Reset (0x01<<2) +#define UART_RxFIFOThreshold_1 (0x00<<6) +#define UART_RxFIFOThreshold_4 (0x01<<6) +#define UART_RxFIFOThreshold_8 (0x02<<6) +#define UART_RxFIFOThreshold_14 (0x03<<6) +/** + * @} + */ + + +/** @defgroup UART_FractionalDivider + * @{ + */ +#define UART_Oversample_8 (0x1<<8) +#define UART_Oversample_16 (0x0<<8) +#define UART_FD_MULVAL(x) (((0x0000 + x) - 1) << 4) +#define UART_FD_DIVADDVAL(x) (0x000 +x) +/** + * @} + */ + +/** @defgroup UART_InterruptEnable + * @{ + */ +#define UART_InterruptEnable (0x01) +#define UART_TxError (UART_InterruptEnable <<10) +#define UART_AutoBaudTimeout (UART_InterruptEnable <<9) +#define UART_AutoBaudEnd (UART_InterruptEnable <<8) +#define UART_TransmitterEmpty (UART_InterruptEnable <<4) +#define UART_ModemStatus (UART_InterruptEnable <<3) +#define UART_ReceiveLine (UART_InterruptEnable <<2) +#define UART_TransmitterHoldingEmpty (UART_InterruptEnable <<1) +#define UART_ReceiveDataAvailable (UART_InterruptEnable <<0) +/** + * @} + */ + +/** @defgroup UART_InterruptIdentification + * @{ + */ +#define UART_Interrupt_Pending 0 +#define UART_InterruptID_THRE 1 +#define UART_InterruptID_RDA 2 +#define UART_InterruptID_RLS 3 +#define UART_InterruptID_CTI 6 +#define UART_InterruptID_TEMT 7 +#define UART_Interrupt_TxError (0x01<<10) +#define UART_Interrupt_ABTO (0x01<<9) +#define UART_Interrupt_ABEO (0x01<<8) +#define UART_Interrupt_Status (0x01) +#define UART_InterruptID_Status 7 + +/** + * @} + */ + +/** @defgroup UART_LineStatus + * @{ + */ +#define UART_LineStatus_TxError (0x01<<8) +#define UART_LineStatus_RxError (0x01<<7) +#define UART_LineStatus_TEMT (0x01<<6) +#define UART_LineStatus_THRE (0x01<<5) +#define UART_LineStatus_BI (0x01<<4) +#define UART_LineStatus_FE (0x01<<3) +#define UART_LineStatus_PE (0x01<<2) +#define UART_LineStatus_OE (0x01<<1) +#define UART_LineStatus_RDR (0x01) + +/** + * @} + */ + +/** @defgroup UART_Control + * @{ + */ +#define UART_Enable (0x01) +#define UART_RxEnable (UART_Enable <<6) +#define UART_TxEnable (UART_Enable <<7) +/** + * @} + */ + +/** @defgroup UART_HalfDuplexMode + * @{ + */ +#define UART_HalfDuplexEnable (0x01) +#define UART_FullDuplexEnable 0 +/** + * @} + */ + +#endif /* SN32_UART_H */ + +/** @} */ diff --git a/os/hal/ports/SN32/SN32F240B/platform.mk b/os/hal/ports/SN32/SN32F240B/platform.mk index 24ad660945..62710aa7e4 100644 --- a/os/hal/ports/SN32/SN32F240B/platform.mk +++ b/os/hal/ports/SN32/SN32F240B/platform.mk @@ -27,6 +27,7 @@ include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/driver.mk include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/SPI/driver.mk include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/I2C/driver.mk include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/WDT/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/UART/driver.mk # Shared variables ALLCSRC += $(PLATFORMSRC_CONTRIB) diff --git a/os/hal/ports/SN32/SN32F260/platform.mk b/os/hal/ports/SN32/SN32F260/platform.mk index 1b8774133b..1c0e8cc196 100644 --- a/os/hal/ports/SN32/SN32F260/platform.mk +++ b/os/hal/ports/SN32/SN32F260/platform.mk @@ -27,6 +27,7 @@ include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/driver.mk include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/SPI/driver.mk include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/I2C/driver.mk include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/WDT/driver.mk +include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/UART/driver.mk # Shared variables ALLCSRC += $(PLATFORMSRC_CONTRIB) From 8b1541808bfe51bbd5b2cbf01c60cc8326de270b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Sim=C3=B5es?= Date: Fri, 7 Jun 2024 04:42:04 +0100 Subject: [PATCH 17/19] Update fatfs_diskio - Moved local declaration close to usage to prevent compiler warning as not used if that media type is not enabled. - Fix code alignment. - Fix typo in comment. --- os/various/fatfs_bindings/fatfs_diskio.c | 162 +++++++++++------------ 1 file changed, 75 insertions(+), 87 deletions(-) diff --git a/os/various/fatfs_bindings/fatfs_diskio.c b/os/various/fatfs_bindings/fatfs_diskio.c index fb127e4dff..7b27b469a1 100644 --- a/os/various/fatfs_bindings/fatfs_diskio.c +++ b/os/various/fatfs_bindings/fatfs_diskio.c @@ -45,7 +45,7 @@ extern RTCDriver RTCD1; /*-----------------------------------------------------------------------*/ -/* Inidialize a Drive */ +/* Initialize a Drive */ DSTATUS disk_initialize ( BYTE pdrv /* Physical drive number (0..) */ @@ -55,38 +55,36 @@ DSTATUS disk_initialize ( switch (pdrv) { #if HAL_USE_MMC_SPI - case FATFSDEV_MMC: - stat = 0; - /* It is initialized externally, just reads the status.*/ - if (blkGetDriverState(&FATFS_HAL_DEVICE) != BLK_READY) - stat |= STA_NOINIT; - if (mmcIsWriteProtected(&FATFS_HAL_DEVICE)) - stat |= STA_PROTECT; - return stat; + case FATFSDEV_MMC: + stat = 0; + /* It is initialized externally, just reads the status.*/ + if (blkGetDriverState(&FATFS_HAL_DEVICE) != BLK_READY) + stat |= STA_NOINIT; + if (mmcIsWriteProtected(&FATFS_HAL_DEVICE)) + stat |= STA_PROTECT; + return stat; #elif HAL_USE_SDC - case FATFSDEV_MMC: - stat = 0; - /* It is initialized externally, just reads the status.*/ - if (blkGetDriverState(&FATFS_HAL_DEVICE) != BLK_READY) - stat |= STA_NOINIT; - if (blkIsWriteProtected(&FATFS_HAL_DEVICE)) - stat |= STA_PROTECT; - return stat; + case FATFSDEV_MMC: + stat = 0; + /* It is initialized externally, just reads the status.*/ + if (blkGetDriverState(&FATFS_HAL_DEVICE) != BLK_READY) + stat |= STA_NOINIT; + if (blkIsWriteProtected(&FATFS_HAL_DEVICE)) + stat |= STA_PROTECT; + return stat; #endif #if HAL_USBH_USE_MSD - case FATFSDEV_MSD: - stat = 0; - /* It is initialized externally, just reads the status.*/ - if (blkGetDriverState(&MSBLKD[0]) != BLK_READY) - stat |= STA_NOINIT; - return stat; + case FATFSDEV_MSD: + stat = 0; + /* It is initialized externally, just reads the status.*/ + if (blkGetDriverState(&MSBLKD[0]) != BLK_READY) + stat |= STA_NOINIT; + return stat; #endif } return STA_NOINIT; } - - /*-----------------------------------------------------------------------*/ /* Return Disk Status */ @@ -117,19 +115,17 @@ DSTATUS disk_status ( return stat; #endif #if HAL_USBH_USE_MSD - case FATFSDEV_MSD: - stat = 0; - /* It is initialized externally, just reads the status.*/ - if (blkGetDriverState(&MSBLKD[0]) != BLK_READY) - stat |= STA_NOINIT; - return stat; + case FATFSDEV_MSD: + stat = 0; + /* It is initialized externally, just reads the status.*/ + if (blkGetDriverState(&MSBLKD[0]) != BLK_READY) + stat |= STA_NOINIT; + return stat; #endif } return STA_NOINIT; } - - /*-----------------------------------------------------------------------*/ /* Read Sector(s) */ @@ -165,20 +161,18 @@ DRESULT disk_read ( return RES_OK; #endif #if HAL_USBH_USE_MSD - case FATFSDEV_MSD: - /* It is initialized externally, just reads the status.*/ - if (blkGetDriverState(&MSBLKD[0]) != BLK_READY) - return RES_NOTRDY; - if (usbhmsdLUNRead(&MSBLKD[0], sector, buff, count)) - return RES_ERROR; - return RES_OK; + case FATFSDEV_MSD: + /* It is initialized externally, just reads the status.*/ + if (blkGetDriverState(&MSBLKD[0]) != BLK_READY) + return RES_NOTRDY; + if (usbhmsdLUNRead(&MSBLKD[0], sector, buff, count)) + return RES_ERROR; + return RES_OK; #endif } return RES_PARERR; } - - /*-----------------------------------------------------------------------*/ /* Write Sector(s) */ @@ -190,7 +184,6 @@ DRESULT disk_write ( UINT count /* Number of sectors to write (1..255) */ ) { - switch (pdrv) { #if HAL_USE_MMC_SPI case FATFSDEV_MMC: @@ -228,24 +221,22 @@ DRESULT disk_write ( #endif #if HAL_USBH_USE_MSD case FATFSDEV_MSD: - /* It is initialized externally, just reads the status.*/ - if (blkGetDriverState(&MSBLKD[0]) != BLK_READY) - return RES_NOTRDY; + /* It is initialized externally, just reads the status.*/ + if (blkGetDriverState(&MSBLKD[0]) != BLK_READY) + return RES_NOTRDY; // invalidate cache on buffer cacheBufferFlush(buff, count * MSBLKD[0].info.blk_size); - if (usbhmsdLUNWrite(&MSBLKD[0], sector, buff, count)) - return RES_ERROR; - return RES_OK; + if (usbhmsdLUNWrite(&MSBLKD[0], sector, buff, count)) + return RES_ERROR; + return RES_OK; #endif } return RES_PARERR; } #endif /* _FS_READONLY */ - - /*-----------------------------------------------------------------------*/ /* Miscellaneous Functions */ @@ -255,8 +246,6 @@ DRESULT disk_ioctl ( void *buff /* Buffer to send/receive control data */ ) { - BlockDeviceInfo bdi; - (void)buff; switch (pdrv) { @@ -280,50 +269,49 @@ DRESULT disk_ioctl ( } #elif HAL_USE_SDC case FATFSDEV_MMC: + BlockDeviceInfo bdi; + switch (cmd) { - case CTRL_SYNC: + case CTRL_SYNC: + return RES_OK; + case GET_SECTOR_COUNT: + if (blkGetInfo(&FATFS_HAL_DEVICE, &bdi)) { + return RES_ERROR; + } + *((DWORD *)buff) = bdi.blk_num; return RES_OK; - case GET_SECTOR_COUNT: - if (blkGetInfo(&FATFS_HAL_DEVICE, &bdi)) { - return RES_ERROR; - } - *((DWORD *)buff) = bdi.blk_num; - return RES_OK; #if FF_MAX_SS > FF_MIN_SS - case GET_SECTOR_SIZE: - if (blkGetInfo(&FATFS_HAL_DEVICE, &bdi)) { - return RES_ERROR; - } - *((WORD *)buff) = bdi.blk_size; - return RES_OK; -#endif - case GET_BLOCK_SIZE: - *((DWORD *)buff) = 256; /* 512b blocks in one erase block */ + case GET_SECTOR_SIZE: + if (blkGetInfo(&FATFS_HAL_DEVICE, &bdi)) { + return RES_ERROR; + } + *((WORD *)buff) = bdi.blk_size; return RES_OK; +#endif #if FF_USE_TRIM - case GET_BLOCK_SIZE: - /* unsupported */ - break; - case CTRL_TRIM: - /* unsupported */ - break; + case GET_BLOCK_SIZE: + /* unsupported */ + break; + case CTRL_TRIM: + /* unsupported */ + break; #endif - default: - return RES_PARERR; + default: + return RES_PARERR; } #endif #if HAL_USBH_USE_MSD case FATFSDEV_MSD: switch (cmd) { - case CTRL_SYNC: - return RES_OK; - case GET_SECTOR_COUNT: - *((DWORD *)buff) = MSBLKD[0].info.blk_num; - return RES_OK; + case CTRL_SYNC: + return RES_OK; + case GET_SECTOR_COUNT: + *((DWORD *)buff) = MSBLKD[0].info.blk_num; + return RES_OK; #if FF_MAX_SS > FF_MIN_SS - case GET_SECTOR_SIZE: - *((WORD *)buff) = MSBLKD[0].info.blk_size; - return RES_OK; + case GET_SECTOR_SIZE: + *((WORD *)buff) = MSBLKD[0].info.blk_size; + return RES_OK; #endif #if FF_USE_TRIM #error "unimplemented yet!" @@ -331,8 +319,8 @@ DRESULT disk_ioctl ( // .... // return RES_OK; #endif - default: - return RES_PARERR; + default: + return RES_PARERR; } #endif } From a377b21825cd79e3a75824214d46d743a69ac6ce Mon Sep 17 00:00:00 2001 From: Dimitris Mantzouranis Date: Mon, 10 Jun 2024 14:20:28 +0300 Subject: [PATCH 18/19] SN32: serial: only calculate FD if required High precision is not always required. Since the chip doesn't have an FPU, calculating the FD precisely is expensive on resources. Make FD usage optional --- os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_serial_lld.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_serial_lld.c b/os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_serial_lld.c index 3c3748ed2a..16a22a933c 100644 --- a/os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_serial_lld.c +++ b/os/hal/ports/SN32/LLD/SN32F2xx/UART/hal_serial_lld.c @@ -68,6 +68,7 @@ static const SerialConfig default_config = {SERIAL_DEFAULT_BITRATE, /*===========================================================================*/ /* Driver local functions. */ /*===========================================================================*/ +#if SN32_UART_USE_FD || defined(__DOXYGEN__) void UART_divisor_CAL(uint32_t baudrate,uint32_t UART_PCLK,uint8_t Oversampling,uint8_t *dlm,uint8_t *dll,uint8_t *d_divaddval,uint8_t *d_mulval) { float expected_val; @@ -156,6 +157,8 @@ void UART_divisor_CAL(uint32_t baudrate,uint32_t UART_PCLK,uint8_t Oversampling, *d_divaddval = divaddval[0]; } } +#endif + /** * @brief UART initialization. * @details This function must be invoked with interrupts disabled. @@ -173,7 +176,15 @@ static void uart_init(SerialDriver *sdp, const SerialConfig *config) { apbclock = (SN32_HCLK); // Calculate divider +#if SN32_UART_USE_FD || defined(__DOXYGEN__) UART_divisor_CAL(config->speed,apbclock,oversampling,&dlm,&dll,&divaddval,&mulval); +#else + uint32_t divisor = (uint32_t)(apbclock/oversampling/config->speed); + dlm = (divisor>>8)&0xff; + dll = divisor&0xff; + divaddval = 0; + mulval = 1; +#endif // SN32_UART_USE_FD // Update the registers u->LC = UART_Divisor_Latch_Access_Enable; From 1496db37a73102cb35130ff1bd87c0b1d9db1170 Mon Sep 17 00:00:00 2001 From: Dimitris Mantzouranis Date: Mon, 10 Jun 2024 16:19:30 +0300 Subject: [PATCH 19/19] sn32: sn32f260: don't build UART The peripheral is not present at all on this chip --- os/hal/ports/SN32/SN32F260/platform.mk | 1 - 1 file changed, 1 deletion(-) diff --git a/os/hal/ports/SN32/SN32F260/platform.mk b/os/hal/ports/SN32/SN32F260/platform.mk index 1c0e8cc196..1b8774133b 100644 --- a/os/hal/ports/SN32/SN32F260/platform.mk +++ b/os/hal/ports/SN32/SN32F260/platform.mk @@ -27,7 +27,6 @@ include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/SysTick/driver.mk include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/SPI/driver.mk include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/I2C/driver.mk include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/WDT/driver.mk -include ${CHIBIOS_CONTRIB}/os/hal/ports/SN32/LLD/SN32F2xx/UART/driver.mk # Shared variables ALLCSRC += $(PLATFORMSRC_CONTRIB)