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The baseline CPU performance design simply falls back on sequential loops, and cannot benefit from code hoisting. One issue, it seems, when trying to fuse kernels to leverage code hoisting is that inlining seems to fail (which kills SIMD).
The text was updated successfully, but these errors were encountered:
The baseline CPU performance design simply falls back on sequential loops, and cannot benefit from code hoisting. One issue, it seems, when trying to fuse kernels to leverage code hoisting is that inlining seems to fail (which kills SIMD).
The text was updated successfully, but these errors were encountered: