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Instruction.cpp
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Instruction.cpp
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/*
Copyright (c) 2024, Technology Innovation Institute, Yas Island, Abu Dhabi, United Arab Emirates.
Copyright (c) 2017, The University of Bristol, Senate House, Tyndall Avenue, Bristol, BS8 1TH, United Kingdom.
Copyright (c) 2021, COSIC-KU Leuven, Kasteelpark Arenberg 10, bus 2452, B-3001 Leuven-Heverlee, Belgium.
*/
#include "Processor/Instruction.h"
#include "Exceptions/Exceptions.h"
#include "Local/Float.h"
#include "Offline/offline_data.h"
#include "Processor/Processor.h"
#include "Tools/Crypto.h"
#include "Tools/parse.h"
#include "Tools/util_containers.h"
#include <algorithm>
#include <limits>
#include <map>
#include <mutex>
#include <sstream>
#include <stdlib.h>
#include <unistd.h>
#include "Mod2Engine/Mod2Maurer.h"
#include "Mod2Engine/Mod2_Thread.h"
#include "OT/OT_Thread_Data.h"
extern OT_Thread_Data OTD;
extern Mod2_Thread_Data MTD;
extern Base_Circuits Global_Circuit_Store;
extern vector<sacrificed_data> SacrificeD;
using namespace std;
template <class SRegint, class SBit> void Instruction<SRegint, SBit>::parse(istream &s)
{
n = 0;
start.resize(0);
r[0] = 0;
r[1] = 0;
r[2] = 0;
r[3] = 0;
int pos = s.tellg();
opcode = get_int(s);
size = opcode >> 9;
opcode &= 0x1FF;
if (size == 0)
size = 1;
parse_operands(s, pos);
}
void BaseInstruction::parse_operands(istream &s, int pos)
{
int num_var_args = 0;
switch (opcode)
{
// instructions with 3 register (or 3 integer) operands
case ADDC:
case ADDS:
case ADDM:
case SUBC:
case SUBS:
case SUBML:
case SUBMR:
case MULC:
case MULM:
case DIVC:
case MODC:
case ANDC:
case XORC:
case ORC:
case SHLC:
case SHRC:
case LTINT:
case GTINT:
case EQINT:
case ADDINT:
case SUBINT:
case MULINT:
case DIVINT:
case MODINT:
case ADDSINT:
case ADDSINTC:
case SUBSINT:
case SUBSINTC:
case SUBCINTS:
case MULSINT:
case MULSINTC:
case DIVSINT:
case SAND:
case XORSB:
case ANDSB:
case ORSB:
case ANDSINT:
case ANDSINTC:
case ORSINT:
case ORSINTC:
case XORSINT:
case XORSINTC:
case ANDINT:
case ORINT:
case XORINT:
case SHLINT:
case SHRINT:
case MREVC:
case MREVS:
case MBITDECC:
case MBITDECINT:
r[0] = get_int(s);
r[1] = get_int(s);
r[2] = get_int(s);
break;
// instructions with 4 register (or integer) operands
case RUN_TAPE:
case MADDC:
case MADDS:
case MADDM:
case MSUBC:
case MSUBS:
case MSUBML:
case MSUBMR:
case MMULC:
case MMULM:
case MDIVC:
case MMODC:
case MEVALCC:
case MEVALSC:
r[0] = get_int(s);
r[1] = get_int(s);
r[2] = get_int(s);
n = get_int(s);
break;
// instructions with 2 register operands
case LDMCI:
case LDMSI:
case STMCI:
case STMSI:
case MOVC:
case MOVS:
case MOVINT:
case MOVSB:
case LDMINTI:
case STMINTI:
case LEGENDREC:
case DABIT:
case CONVINT:
case LTZINT:
case EQZINT:
case RAND:
case DIGESTC:
case NEG:
case NEGB:
case CONVSINTSREG:
case CONVREGSREG:
case CONVSREGSINT:
case CONVSUREGSINT:
case CONVSINTSBIT:
case CONVSBITSINT:
case OPENSINT:
case OPENSBIT:
case LDMSINTI:
case STMSINTI:
case MOVSINT:
case INVSINT:
case INVINT:
case EQZSINT:
case LTZSINT:
case PEEKINT:
case PEEKSINT:
case PEEKC:
case PEEKS:
case PEEKSBIT:
case POKEINT:
case POKESINT:
case POKEC:
case POKES:
case POKESBIT:
case RPEEKINT:
case RPEEKSINT:
case RPEEKC:
case RPEEKS:
case RPEEKSBIT:
case RPOKEINT:
case RPOKESINT:
case RPOKEC:
case RPOKES:
case RPOKESBIT:
case NEWC:
case NEWS:
case NEWINT:
case NEWSINT:
r[0] = get_int(s);
r[1] = get_int(s);
break;
// instructions with 1 register operand
case PRINT_REG:
case LDTN:
case LDARG:
case STARG:
case PUSHINT:
case PUSHSINT:
case PUSHC:
case PUSHS:
case PUSHSBIT:
case POPINT:
case POPSINT:
case POPC:
case POPS:
case POPSBIT:
case GETSPINT:
case GETSPSINT:
case GETSPC:
case GETSPS:
case GETSPSBIT:
case PRINT_CHAR_REGINT:
case PRINT_CHAR4_REGINT:
case PRINT_INT:
case PRINT_IEEE_FLOAT:
case CALLR:
case JMPR:
case DELETEC:
case DELETES:
case DELETEINT:
case DELETESINT:
case RANDC:
case RANDINT:
case RANDSINT:
case RANDFLOAT:
case RANDSBIT:
r[0] = get_int(s);
break;
case OTRIPLE:
n = get_int(s);
break;
case LOADTRIPLE:
n = get_int(s);
break;
// instructions with 2 registers + 1 integer operand
case OSRAND:
n = get_int(s);
m = get_int(s);
break;
case LOADSRAND:
n = get_int(s);
m = get_int(s);
break;
case ODABIT:
n = get_int(s);
break;
case LOADDABIT:
n = get_int(s);
break;
case ADDCI:
case ADDSI:
case SUBCI:
case SUBSI:
case SUBCFI:
case SUBSFI:
case MULCI:
case MULSI:
case DIVCI:
case MODCI:
case ANDCI:
case XORCI:
case ORCI:
case SHLCI:
case SHRCI:
case SHLSINT:
case SHRSINT:
case NOTC:
case CONVMODP:
case BITSINT:
r[0] = get_int(s);
r[1] = get_int(s);
n = get_int(s);
break;
// instructions with 2 registers + 1 integer operand
case SINTBIT:
r[0] = get_int(s);
r[1] = get_int(s);
r[2] = get_int(s);
n = get_int(s);
break;
// instructions with 1 register + 1 integer operand
case LDI:
case LDSI:
case LDMC:
case LDMS:
case STMC:
case STMS:
case LDMINT:
case STMINT:
case LDINT:
case INPUT_CLEAR:
case OUTPUT_CLEAR:
case INPUT_INT:
case OPEN_CHANNEL:
case OUTPUT_INT:
case LDMSINT:
case STMSINT:
case LDSINT:
case LDSBIT:
r[0] = get_int(s);
n = get_int(s);
break;
// instructions with 1 reg + 1 player + 1 integer operand
case PRIVATE_INPUT:
case PRIVATE_OUTPUT:
r[0] = get_int(s);
p = get_int(s);
m = get_int(s);
break;
// instructions with 2 reg + 1 player + 1 integer
case MPRIVATE_INPUT:
case MPRIVATE_OUTPUT:
r[0] = get_int(s);
r[1] = get_int(s);
p = get_int(s);
m = get_int(s);
break;
// instructions with 1 reg + 2 integer operand
case PRINT_FIX:
case JMPNE:
case JMPEQ:
r[0] = get_int(s);
n = get_int(s);
m = get_int(s);
break;
// instructions with 1 integer operand
case PRINT_CHAR4:
case PRINT_CHAR:
case JMP:
case CALL:
case START_CLOCK:
case STOP_CLOCK:
case CLOSE_CHANNEL:
case PRINT_MEM:
case JOIN_TAPE:
case GC:
case EGC:
case LF:
n = get_int(s);
break;
case OGC:
n = get_int(s);
m = get_int(s);
break;
case LOADGC:
n = get_int(s);
m = get_int(s);
break;
// instructions with no operand
case CLEAR_MEMORY:
case CLEAR_REGISTERS:
case RESTART:
case CRASH:
case RETURN:
break;
// instructions with 4 register operands
case MUL2SINT:
get_vector(4, start, s);
break;
// instructions with 5 register operands
case PRINT_FLOAT:
get_vector(5, start, s);
break;
// open instructions instructions with variable length args
case BIT:
case TRIPLE:
case SQUARE:
case STARTOPEN:
case STOPOPEN:
num_var_args = get_int(s);
get_vector(num_var_args, start, s);
break;
// As above, but with a trailing int argument
case OUTPUT_SHARES:
case INPUT_SHARES:
// subtract player/channel number from the number of arguments
num_var_args = get_int(s) - 1;
p = get_int(s);
get_vector(num_var_args, start, s);
break;
case REQBL:
n = get_int(s);
if (n > 0 && gfp::pr() < bigint(1) << (n - 1))
{
cout << "Tape requires prime of bit length " << n << endl;
throw invalid_params();
}
break;
// below the new summation bytecodes
case SUMS:
r[0] = get_int(s);
r[1] = get_int(s);
n = get_int(s);
break;
case SUMC:
r[0] = get_int(s);
r[1] = get_int(s);
n = get_int(s);
break;
case LOADCT:
n = get_int(s);
m = get_int(s);
break;
case CTRIPLE:
n = get_int(s);
get_vector(n, start, s);
break;
case CT_DYN:
n = get_int(s);
m = get_int(s);
get_vector(n - 1, start, s);
break;
case SRAND:
n = get_int(s);
m = get_int(s);
get_vector(n - 1, start, s);
break;
default:
ostringstream os;
os << "Invalid instruction :'( " << hex << showbase << opcode << " at " << dec << pos
<< " the opcode is: " << opcode << " the end";
throw Invalid_Instruction(os.str());
}
}
RegType BaseInstruction::get_reg_type() const
{
switch (opcode)
{ // List here commands which write to a specific type of register or a direct memory access
case LDMINT:
case LDMINTI:
case MOVINT:
case POPINT:
case PEEKSINT:
case RPEEKSINT:
case PUSHINT:
case PUSHSINT:
case POKEINT:
case RPOKEINT:
case POKESINT:
case RPOKESINT:
case GETSPINT:
case GETSPSINT:
case GETSPS:
case GETSPC:
case GETSPSBIT:
case LDTN:
case LDARG:
case INPUT_INT:
case RAND:
case LDINT:
case CONVMODP:
case ADDINT:
case SUBINT:
case MULINT:
case DIVINT:
case MODINT:
case LTZINT:
case LTINT:
case GTINT:
case EQINT:
case EQZINT:
case STMINT:
case STMSINT:
case STMSINTI:
case LDMSINT:
case LDMSINTI:
case MOVSINT:
case LDSINT:
case ADDSINT:
case ADDSINTC:
case SUBSINT:
case SUBSINTC:
case SUBCINTS:
case MULSINT:
case MULSINTC:
case DIVSINT:
case SHLSINT:
case SHRSINT:
case NEG:
case SAND:
case SINTBIT:
case CONVSINTSREG:
case CONVREGSREG:
case OPENSINT:
case OPENSBIT:
case ANDSINT:
case ANDSINTC:
case ORSINT:
case ORSINTC:
case XORSINT:
case XORSINTC:
case INVSINT:
case ANDINT:
case ORINT:
case XORINT:
case INVINT:
case SHLINT:
case SHRINT:
case MUL2SINT:
case OPEN_CHANNEL:
case NEWC:
case NEWS:
case NEWINT:
case NEWSINT:
case DELETEC:
case DELETES:
case DELETEINT:
case DELETESINT:
case RANDINT:
case RANDSINT:
case RANDFLOAT:
return INT;
case MOVSB:
case XORSB:
case ANDSB:
case ORSB:
case NEGB:
case LTZSINT:
case EQZSINT:
case BITSINT:
case POPSBIT:
case PUSHSBIT:
case PEEKSBIT:
case RPEEKSBIT:
case POKESBIT:
case RPOKESBIT:
case CONVSINTSBIT:
case LDSBIT:
case RANDSBIT:
return SBIT;
case OTRIPLE:
case LOADTRIPLE:
case ODABIT:
case LOADDABIT:
case STARG:
case REQBL:
case RUN_TAPE:
case JOIN_TAPE:
case CRASH:
case CLEAR_MEMORY:
case CLEAR_REGISTERS:
case PRINT_MEM:
case PRINT_REG:
case PRINT_CHAR:
case PRINT_CHAR4:
case PRINT_CHAR_REGINT:
case PRINT_CHAR4_REGINT:
case PRINT_FLOAT:
case PRINT_FIX:
case PRINT_INT:
case PRINT_IEEE_FLOAT:
case CLOSE_CHANNEL:
case OUTPUT_SHARES:
case OUTPUT_INT:
case PRIVATE_OUTPUT:
case MPRIVATE_OUTPUT:
case JMP:
case JMPNE:
case JMPEQ:
case STARTOPEN:
case START_CLOCK:
case STOP_CLOCK:
case CALL:
case CALLR:
case JMPR:
case RETURN:
case GC:
case OGC:
case LOADGC:
case EGC:
case LF:
return NONE;
case SUMS:
case SUMC:
case LOADCT:
case CTRIPLE:
case CT_DYN:
case SRAND:
case DABIT:
return DUAL;
default:
return MODP;
}
}
/* This does an overestimate as it counts ALL values, even
* if they are reading. But the reg_type looks only at
* the RETURN value type. So we will overcount some register
* usage. If we got the exact register usage it would cost
* more logic, and would save little in terms of memeory
*
* The trick is that if a register is read it must be
* written so if we only count the instructions which
* write, and then take the max register in that
* instruction it will be OK
*
* So if we had
* blah with c0,c1,s0,s1 registers
* c5 <- add c0, c1
* s3 <- add c5, s1
* Then the max registers *should* be
* c : 5 s: 3
* But we actually count
* c : 5 s: 5
* due to the c5 read in the last instruction. But we only
* need a max and 3<5 so all is OK
*
* Dual is a weird one to catch the different write types
* of the DABIT instruction
*
*/
int BaseInstruction::get_max_reg(RegType reg_type) const
{
if ((get_reg_type() == reg_type) || (get_reg_type() == DUAL && (reg_type == SBIT || reg_type == MODP)))
{
if (start.size())
return *max_element(start.begin(), start.end()) + size;
else
return *max_element(r, r + 3) + size;
}
return 0;
}
template <class SRegint, class SBit> ostream &operator<<(ostream &s, const Instruction<SRegint, SBit> &instr)
{
// Is it vectorized?
if (instr.size != 1)
{
s << "V";
}
// Then the main opcode
switch (instr.opcode)
{
case LDI:
s << "LDI";
break;
case LDSI:
s << "LDSI";
break;
case LDMC:
s << "LDMC";
break;
case LDMS:
s << "LDMS";
break;
case STMC:
s << "STMC";
break;
case STMS:
s << "STMS";
break;
case LDMCI:
s << "LDMCI";
break;
case LDMSI:
s << "LDMSI";
break;
case STMCI:
s << "STMCI";
break;
case STMSI:
s << "STMSI";
break;
case MOVC:
s << "MOVC";
break;
case MOVS:
s << "MOVS";
break;
case LDMINT:
s << "LDMINT";
break;
case MOVSB:
s << "MOVSB";
break;
case STMINT:
s << "STMINT";
break;
case LDMINTI:
s << "LDMINTI";
break;
case STMINTI:
s << "STMINTI";
break;
case NEWC:
s << "NEWC";
break;
case DELETEC:
s << "DELETEC";
break;
case NEWS:
s << "NEWS";
break;
case DELETES:
s << "DELETES";
break;
case NEWINT:
s << "NEWINT";
break;
case DELETEINT:
s << "DELETEINT";
break;
case NEWSINT:
s << "NEWSINT";
break;
case DELETESINT:
s << "DELETESINT";
break;
case PUSHINT:
s << "PUSHINT";
break;
case PUSHSINT:
s << "PUSHSINT";
break;
case PUSHS:
s << "PUSHS";
break;
case PUSHC:
s << "PUSHC";
break;
case PUSHSBIT:
s << "PUSHSBIT";
break;
case POPINT:
s << "POPINT";
break;
case POPSINT:
s << "POPSINT";
break;
case POPS:
s << "POPS";
break;
case POPC:
s << "POPC";
break;
case POPSBIT:
s << "POPSBIT";
break;
case PEEKINT:
s << "PEEKINT";
break;
case PEEKSINT:
s << "PEEKSINT";
break;
case PEEKS:
s << "PEEKS";
break;
case PEEKC:
s << "PEEKC";
break;
case PEEKSBIT:
s << "PEEKSBIT";
break;
case RPEEKINT:
s << "RPEEKINT";
break;
case RPEEKSINT:
s << "RPEEKSINT";
break;
case RPEEKS:
s << "RPEEKS";
break;
case RPEEKC:
s << "RPEEKC";
break;
case RPEEKSBIT:
s << "RPEEKSBIT";
break;
case POKEINT:
s << "POKEINT";
break;
case POKESINT:
s << "POKESINT";
break;
case POKES:
s << "POKES";
break;
case POKEC:
s << "POKEC";
break;
case POKESBIT:
s << "POKESBIT";
break;
case RPOKEINT:
s << "RPOKEINT";
break;
case RPOKESINT:
s << "RPOKESINT";
break;
case RPOKES:
s << "RPOKES";
break;
case RPOKEC:
s << "RPOKEC";
break;
case RPOKESBIT:
s << "RPOKESBIT";
break;
case GETSPINT:
s << "GETSPINT";
break;
case GETSPSINT:
s << "GETSPSINT";
break;
case GETSPS:
s << "GETSPS";
break;
case GETSPC:
s << "GETSPC";
break;
case GETSPSBIT:
s << "GETSPSBIT";
break;
case MOVINT:
s << "MOVINT";
break;
case LDTN:
s << "LDTN";
break;
case LDARG:
s << "LDARG";
break;
case REQBL:
s << "REQBL";
break;
case STARG:
s << "STARG";
break;
case CALL:
s << "CALL";
break;
case RETURN:
s << "RETURN";
break;
case CALLR:
s << "CALLR";
break;
case JMPR:
s << "JMPR";
break;
case RUN_TAPE:
s << "RUN_TAPE";
break;
case JOIN_TAPE:
s << "JOIN_TAPE";
break;
case CRASH:
s << "CRASH";
break;
case RESTART:
s << "RESTART";
break;
case CLEAR_MEMORY:
s << "CLEAR_MEMORY";
break;
case CLEAR_REGISTERS:
s << "CLEAR_REGISTERS";
break;
case ADDC:
s << "ADDC";
break;
case ADDS:
s << "ADDS";
break;
case ADDM:
s << "ADDM";
break;
case ADDCI:
s << "ADDCI";
break;
case ADDSI:
s << "ADDSI";
break;
case SUBC:
s << "SUBC";
break;
case SUBS:
s << "SUBS";
break;
case SUBML:
s << "SUBML";
break;
case SUBMR:
s << "SUBMR";
break;
case SUBCI:
s << "SUBCI";
break;
case SUBSI:
s << "SUBSI";
break;
case SUBCFI:
s << "SUBCFI";
break;
case SUBSFI:
s << "SUBSFI";
break;
case MULC:
s << "MULC";
break;
case MULM:
s << "MULM";
break;
case MULCI:
s << "MULCI";
break;
case MULSI:
s << "MULSI";
break;
case DIVC:
s << "DIVC";
break;
case DIVCI:
s << "DIVCI";
break;
case MODC:
s << "MODC";
break;
case MODCI:
s << "MODCI";
break;
case LEGENDREC:
s << "LEGENDREC";
break;
case DIGESTC:
s << "DIGESTC";
break;
case MADDC:
s << "MADDC";
break;
case MADDS:
s << "MADDS";
break;
case MADDM:
s << "MADDM";
break;
case MSUBC:
s << "MSUBC";
break;
case MSUBS:
s << "MSUBS";
break;
case MSUBML:
s << "MSUBML";
break;
case MSUBMR:
s << "MSUBMR";
break;
case MMULC:
s << "MMULC";
break;
case MMULM:
s << "MMULM";
break;
case MDIVC:
s << "MDIVC";
break;
case MMODC:
s << "MMODC";
break;
case MREVC:
s << "MREVC";
break;
case MREVS:
s << "MREVS";
break;
case MEVALCC:
s << "MEVALCC";
break;
case MEVALSC:
s << "MEVALSC";
break;
case MBITDECC:
s << "MBITDECC";
break;
case MBITDECINT:
s << "MBITDECINT";
break;
case OUTPUT_CLEAR:
s << "OUTPUT_CLEAR";
break;
case INPUT_CLEAR:
s << "INPUT_CLEAR";
break;
case OUTPUT_SHARES:
s << "OUTPUT_SHARES";
break;
case INPUT_SHARES: