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SPI-24PIN.md

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EPD PINOUT (24 PIN)

Reference design

Connector

  • FH12-24S-0.5SH
  • FH12-34S-0.5SH

Definition

# Type Name Description Note
01 NC NC No connection
02 O GDR N-Channel MOS-FET gate drive control
03 O RESE Current sense input for the control loop RESE
04 PWR VGL Negative gate driving voltage Driving voltage
05 PWR VGH Positive gate driving voltage Driving voltage
06 O TSCL (I2C) Sensor Clock Digital Temperature
07 I/O TSDA (I2C) Sensor Data Digital Temperature
08 I BS1 Bus selection BS1
09 O BUSY Busy state output BUSY
10 I RES# Global reset pin SPI, RES#
11 I D/C# (SPI) Data/Command control SPI, D/C#
12 I CS# (SPI SS) Chip select SPI, CS#
13 I/O D0 (SPI SCLK) Serial clock SPI
14 I/O D1 (SPI MOSI) Serial data in SPI
15 I VDDIO (SPI VCC) Power Supply for interface logic Power Supply
16 I VDI Power Supply for the chip Power Supply
17 GND VSS (GND) Ground
18 PWR VDD Corelogic power
19 PWR VPP Power Supply for OTP programming Power Supply
20 PWR VSH Positive source driving voltage Driving voltage
21 PWR PRE VGH Power Supply for VGH and VSH Power Supply
22 PWR VSL Negative source driving voltage Driving voltage
23 PWR PRE VGL Power Supply for VCOM, VGL and VSL Power Supply
24 PWR VCOM VCOM driving voltage Driving voltage

Note

CSn

This pin (CS#) is the Chip select connecting to the MCU.
The chip is enabled for MCU communication only when CS# is pulled LOW.

D/Cn

D/C# Think of the data as
LOW Command
HIGH Data

RESn

This pin (RES#) is reset signal input.
The Reset is active LOW.

BUSY

This pin (BUSY) is Busy state output pin.
When Busy is HIGH, the operation of chip should not be interrupted and any commands should not be issued to the module.
The driver IC will put Busy pin HIGH when the driver IC is working such as:

  • Outputting display waveform
  • Programming with OTP
  • Communicating with digital temperature sensor

Panel break detection

The panel break detection function is used to detect the breakage at panel edge.
When the panel break detection command is issued, the panel break detection will be executed.
During the detection period, BUSY output is at HIGH level.
BUSY output is at LOW level when the detection is completed.
Then, user can issue the Status Bit Read command to check the status bit for the result of panel break.

BS1

SPI Mode BS1 RES# CS# D/C#
4-wire Connect to VSS Required Required Required
3-wire Connect to VDDIO Required Required Connect to VSS

* 3-wire: 9 bits SPI, first bit is D/C#

RESE

While shorting RESE and resistor, this model is suitable for the following E-Paper displays:

Resistor Driver IC Provided
0.47 Ω Solomon Systech
3.00 Ω Ultra Chip

References:

SPI

3-wire SPI caveats:
The operation is similar to 4-wire SPI while D/C# pin is not used and it must be tied to LOW.
In the write operation, a 9-bit data will be shifted into the shift register on every clock rising edge.
The bit shifting sequence is D/C# bit, D7 bit, D6 bit to D0 bit.
The first bit is D/C# bit which determines the following byte is command or data.
When D/C# bit is 0, the following byte is command.
When D/C# bit is 1, the following byte is data.

SPI Mode Function D0 (SCLK) PIN D1 (MOSI) PIN D/C# PIN CS# PIN
4-wire Write Command ↑ Command bit LOW LOW
4-wire Write Data ↑ Data bit HIGH LOW
3-wire Write Command ↑ Command bit Tie LOW LOW
3-wire Write Data ↑ Data bit Tie LOW LOW
  • LOW is connected to VSS and HIGH is connected to VDDIO
  • ↑ stands for rising edge of signal
  • MOSI is shifted into an 8-bit shift register on every rising edge of SCLK in the order of D7, D6, ... D0.
    The level of D/C# should be kept over the whole byte.
    The data byte in the shift register is written to the Graphic Display Data RAM (RAM)
    or Data Byte register or command Byte register according to D/C# pin.