How to run testbench in widows

[hee12343]

Hi, I'm going to tune and use your project.
However, I don't understand the behavior of some signals, so I want to run the simulation.
Several problems arise here.

First, the biggest problem is the OS.
I am developing in a window environment, and I don't have a PC or virtual machine in the Linux system.
Accordingly, the make command could not be used. I succeeded in opening the make file and constructing the project using the editor.
Simulation also opened the make file and confirmed that only test20 was activated, and test20 was compiled by vivado to proceed with the test.
However, in NVMeWrite.vhd, the "buffers" signal encountered a "multiple driving net" error.
It seems to me that the problem was caused by the initial value-giving part of the buffer signal, so after deactivating this part, simulation was attempted again, but the error did not disappear.
I wonder if other additional actions are needed, not just adding a test bench to turn the simulation.

The second question is...I'm curious about the usage of the .sav file in \pl-intermediate-master\sim\testbench.

Finally, some of the testbench use AXIl, a library that does not exist in compressed files.
In addition, the port of NvmE Storage is different.
It looks like a testbench made in the previous version, but there is a testbench that I want to do a double test.
I'm curious about the method.

PS. Can I get the entire project file by any chance....?

[ademgolcuk]

Hi,

I'm going to use the environment here. Any progress in your work?
I'm going to work it on windows machine. Did you run the test env. without any problems?
Are there any known bugs of the IP?
I plan to contribute by working on the items described under the heading "Ideas for Future Work" in the design document.

Best Regards,
Adem

[xujiangyu0619]

This code cannot compile completely. I don't know why.