From ad4fca2ad0bd8e1151461a74812f8d630aa06896 Mon Sep 17 00:00:00 2001
From: vengin <41512424+vengin@users.noreply.github.com>
Date: Mon, 11 Feb 2019 10:37:16 +0300
Subject: [PATCH] Fixed Zybo preset for Eth0 MDIO pins

On Zybo board ETH0 MDIO pins are connected not via EMIO, but via MIO[52..53].
![alt text](http://s3.amazonaws.com/igorfreire-personal-page/wp-content/uploads/2016/11/20181847/zybo_phy_signals.png "Zybo Ethernet PHY signals")
---
 new/board_files/zybo/B.3/preset.xml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/new/board_files/zybo/B.3/preset.xml b/new/board_files/zybo/B.3/preset.xml
index 110a617..9ee516d 100644
--- a/new/board_files/zybo/B.3/preset.xml
+++ b/new/board_files/zybo/B.3/preset.xml
@@ -7,6 +7,7 @@
         <user_parameter name="CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ" value="50.000000"/> 
         <user_parameter name="CONFIG.PCW_ENET0_ENET0_IO" value="MIO 16 .. 27"/> 
         <user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_ENABLE" value="1"/> 
+        <user_parameter name="CONFIG.PCW_ENET0_GRP_MDIO_IO" value="MIO 52 .. 53"/> 
         <user_parameter name="CONFIG.PCW_ENET0_PERIPHERAL_ENABLE" value="1"/> 
         <user_parameter name="CONFIG.PCW_ENET0_RESET_ENABLE" value="0"/> 
         <user_parameter name="CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ" value="100"/>