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CHANGELOG.md

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Changelog

All notable changes to this project will be documented in this file.

The format is based on Keep a Changelog, and this project adheres to Semantic Versioning.

0.16.0 - 2024-02-07

Added

  • Added interpreter break reason in run response

0.15.0 - 2023-12-06

Added

  • Added memory range introspection on cartesi-machine
  • Added init and entrypoint fields to machine DTB on cartesi-machine

Changed

  • Replaced proof with sibling_hashes on cartesi-machine
  • Refactored uarch reset on cartesi-machine
  • Removed DumpPmas on cartesi-machine
  • Renamed ROM to DTB on cartesi-machine

0.14.0 - 2023-08-02

Added

  • Added new reject reason for larger payloads on the server-manager

Changed

  • Updated license/copyright notice in all source code

Fixed

  • Fixed typos on the server-manager documentation

0.13.0 - 2023-07-13

Changed

  • Renamed fields in output validity proof in server-manager interface
  • Adjusted server manager documentation

Fixed

  • Fixed build of machine-manager with uarch

0.12.0 - 2023-04-28

Changed

  • Changed processed input count in finish epoch request

0.11.0 - 2023-04-18

Added

  • Added new proof structure to finish epoch
  • Added DeleteEpoch method to server manager
  • Added SessionReplaceMemoryRange method on machine-manager
  • Added ResetUarchState on Cartesi Machine
  • Added GetUarchXAddress on Cartesi Machine
  • Added Uarch halt flag on Cartesi Machine

Changed

  • Replaced epoch input index with global input index
  • Moved hashes from get epoch status to finish epoch
  • Renamed voucher.address to voucher.destination
  • Renamed machine Step to StepUarch on Cartesi Machine
  • Renamed machine UarchRun to RunUarch on Cartesi Machine
  • Removed Uarch ROM on Cartesi Machine

Removed

  • Removed keccak fields from vouchers and notices

0.10.0 - 2023-02-16

Changed

  • Removed brkflag CSR
  • Replaced minstret by icycleinstret CSR

0.9.0 - 2022-11-17

Added

  • Added microarchitecture configs
  • Added TLB configs
  • Added read/write virtual memory methods
  • Added new CSRs related to the RISC-V specification

Changed

  • Removed DHD device

[Previous Versions]