Reset

[schoeberl]

I think we can handle the async neg reset to a synchronous pos reset in Chisel. No need for SV:

val syncReset = RegNext(RegNext(!asynReset))

[schoeberl]

I tried to change it, but now all tests fail. I assume that the tests do not simulate the low active reset.

[Kyrhe]

If you want to keep chisel code intact, one solution is to insert inverter for the reset line. I've done synthesis experiments like it and it should not cause any issues. Due to being on reset lane, it needs to be instantiated from tech library. If such is desirable, we can add tech_not to Didactic level which could be used to flip reset outside chisel code.

Alternatively we can also force register bit for the reset to be reversed.

[schoeberl]

If we move the reset polarity change out of our design into the Didactic, that would simplify it a bit on our side.

BTW, what kind of reset polarity do other groups want? For me negative reset is just for historical reasons, no benefit at the chip level. Maybe it's just confusing.