From c1d85e313d5f0482a5a550a9c14327aeeec4db4c Mon Sep 17 00:00:00 2001 From: Elizabeth Esparza Date: Thu, 24 Oct 2024 14:20:42 -0600 Subject: [PATCH] feat: clock update --- build/a.out1 | 8 ++++---- src/tt_um_waves.v | 8 +------- 2 files changed, 5 insertions(+), 11 deletions(-) diff --git a/build/a.out1 b/build/a.out1 index 33a5c13..a572eaa 100644 --- a/build/a.out1 +++ b/build/a.out1 @@ -10,12 +10,12 @@ LOG[14]: 1 unaccounted **** module/scope: tt_um_waves.adsr_gen Flip-Flops : 20 - Logic Gates : 220 + Logic Gates : 263 ADDER[8]: 3 units EQUALITY[8]: 2 units MAGNITUDE[8]: 2 units MAGNITUDE[32]: 1 units - MUX[2]: 16 slices + MUX[2]: 36 slices LPM[5]: 6 unaccounted LPM[8]: 2 unaccounted LOG[13]: 3 unaccounted @@ -88,13 +88,13 @@ LOG[14]: 1 unaccounted **** TOTALS Flip-Flops : 151 - Logic Gates : 1481 + Logic Gates : 1524 ADDER[8]: 6 units ADDER[32]: 9 units EQUALITY[8]: 2 units MAGNITUDE[8]: 4 units MAGNITUDE[32]: 4 units - MUX[2]: 214 slices + MUX[2]: 234 slices LPM[4]: 1 unaccounted LPM[5]: 12 unaccounted LPM[8]: 11 unaccounted diff --git a/src/tt_um_waves.v b/src/tt_um_waves.v index 12b0f38..6855057 100644 --- a/src/tt_um_waves.v +++ b/src/tt_um_waves.v @@ -11,15 +11,9 @@ module tt_um_waves ( input wire [7:0] uio_in, // IOs: Input path output wire [7:0] uio_out, // IOs: Output path output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output) - input wire ena, // Will go high when the design is enabled - input wire clk, // Clock input wire rst_n // Reset_n - low to reset ); - /* verilator lint_off UNUSEDSIGNAL */ - // The `ena` signal is currently not used in this design - /* verilator lint_on UNUSEDSIGNAL */ - // Internal signals wire [5:0] freq_select = ui_in[5:0]; // Frequency selection from the first 6 bits of ui_in wire [1:0] wave_select = ui_in[7:6]; // Wave type selection from the last 2 bits of ui_in @@ -540,7 +534,7 @@ module adsr_generator ( localparam STATE_SUSTAIN = 4'd3; localparam STATE_RELEASE = 4'd4; - always @(posedge clk or negedge rst_n) begin + always @(posedge clk) begin if (!rst_n) begin state <= STATE_IDLE; amplitude <= 8'd0;