From d60ff5f8b6e88598268620899d4e7c9ab4f61cda Mon Sep 17 00:00:00 2001 From: Elizabeth Esparza Date: Fri, 8 Nov 2024 15:27:58 -0600 Subject: [PATCH] feat: slice bit by bit --- test/test.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/test/test.py b/test/test.py index e28e67a..7fbbc22 100644 --- a/test/test.py +++ b/test/test.py @@ -37,10 +37,10 @@ async def test_tt_um_waves(dut): await ClockCycles(dut.clk, 10) # Track wave selection by observing UART changes - initial_wave_selection = dut.uo_out[0:3].value + initial_wave_selection = (dut.uo_out[0].value, dut.uo_out[1].value, dut.uo_out[2].value) await send_uart_byte(dut, 0x31) # Send UART byte '1' to change frequency await ClockCycles(dut.clk, 500) - new_wave_selection = dut.uo_out[0:3].value + new_wave_selection = (dut.uo_out[0].value, dut.uo_out[1].value, dut.uo_out[2].value) assert new_wave_selection != initial_wave_selection, "Expected change in wave selection after UART command" # Simulate ADSR modulation by setting attack, decay, sustain, release