Trying to replicate the circuit - diagram?

[the-kenny]

Hello there,

I'm trying to replicate your project - while the software part is easy I've got a few issues with the ADC conversion on the hardware side. My signals are either way out of the range of the ADC or too attenuated to get decoded :-)

Could you provide a simple description of the audio input circuit?

Cheers

[EvanKrall]

I can get you exact values I used in a few hours, but the gist of it is:

• Pin 36 gets the audio, voltage-divided; Audio out from the baofeng is centered around ~3.6v (I'm guessing this is Vbat/2) and at max volume can go down to 0V and up to 7.4V, so you need to voltage divide this. I think I'm using 33k and 10k.
• Pin 37 gets the audio, but clipped to 2.5V < clamp < 3.6V. I'm using a resistor (I think 10k) and two red LEDs -- their forward bias voltage is around 1.6V each, so this tends to clamp to 0-3.3V. You could also potentially use a comparator. This doesn't need to be high the entire time the radio is outputting audio, just needs to be high when the audio begins to trigger gpio_isr_handler.

[the-kenny]

Thank you so much for the diagram! I managed to figure out most of the stuff, but couldn't get it to work. However, I went with different values for the voltage divider and didn't clamp the voltage for pin 37. I'll try it again with your circuit tomorrow.

Until now I was looking for a circuit to remove the 3.3V DC bias from the signal. This would also allow us to use the full range of the 12bit ADC.

[EvanKrall]

You don't want to entirely remove the DC bias (or you want to re-add some of your own bias) because I think the ADC only reads positive voltage values.

[the-kenny]

Absolutely right. My plan was to reintroduce some bias to go into positive values again. Anyway - I'll let you know if the circuit works somewhen tomorrow. Thanks!

[the-kenny]

Unfortunately I still can’t decide any packages :-/ The samples look better (the code passes Galesburg the range of about -100 to 100) to LibAPRS. It’s just that the callback is never called.

Could you tell me how the samples are supposed to look, or maybe send me a sample dump of a successfully decoded package to make sure everything else is set up correctly? (I would just hardcode that sample in an array and pass that array into libaprs on start-up)

[the-kenny]

Also note that I get the following log output which might indicate an issue with the sample rate of the ADC?

(40719) I2S: PLL_D2: Req RATE: 96000, real rate: 6410.000, BITS: 16, CLKM: 13, BCK: 60, MCLK: 13.889, SCLK: 205120.000000, diva: 64, divb: 56

[EvanKrall]

I did have a lot of trouble getting the sample rate to behave when I set .use_apll = 1, which is why I disabled it. Seems to be a bug in ESP-IDF. It was supposed to be fixed by espressif/esp-idf@430d9c6 but I didn't have any better luck after upgrading.

I haven't yet tried out the patch defined here espressif/esp-idf#3380 (comment), but it seems promising.

[EvanKrall]

Oh, I also double checked the resistor values on my divider: I'm using a 10k and 3.3k resistor instead of the 33k and 10k that my diagram says. This shouldn't make a difference - the code doesn't seem particularly sensitive to amplitude, and I'm already using a HPF to cut out any DC offset.

[the-kenny]

Thanks for re-checking. I'll also give these new resistor values a try :-)

[the-kenny]

just to clarify: The 10k instead of the 33k at the baofeng side and the 3.3k instead of the 10k to ground?

[EvanKrall]

Yes, to cut voltage to ~25% of its original value.

[EvanKrall]

Here's the full output of me receiving a packet, with these printfs uncommented.

Looks like the I (42927) I2S: PLL_D2: Req RATE: 96000, real rate: 6410.000, BITS: 16, CLKM: 13, BCK: 60, MCLK: 13.889, SCLK: 205120.000000, diva: 64, divb: 56 is normal.