.github:workflows: Add VHDL build and test workflow

 Rename old workflow to fabric_gen_verilog.
 Add a workflow to build and simulate a VHDL fabric.

Signed-off-by: Jonas K. <[email protected]>

.github/workflows/fabric_gen.yml → .github/workflows/fabric_gen_verilog.yml

@@ -30,7 +30,7 @@ jobs:
       - name: Install FABulous
         run: |
           pip3 install -e .
-      - name: Run fabric generator flow and simulation
+      - name: Run fabric generator flow and simulation for verilog
         run: |
-          FABulous -c demo
-          FABulous demo -fs ./demo/FABulous.tcl
+          FABulous -c demo_verilog
+          FABulous demo_verilog -fs ./demo_verilog/FABulous.tcl

.github/workflows/fabric_gen_vhdl.yml

@@ -0,0 +1,37 @@
+name: Test fabric_gen.py
+
+on: [push, pull_request]
+
+jobs:
+  build_and_run:
+    runs-on: ubuntu-latest
+
+    steps:
+      - uses: actions/checkout@v4
+        with:
+          submodules: recursive
+      - name: Set up Python 3.12
+        uses: actions/setup-python@v4
+        with:
+          python-version: "3.12"
+      - name: Set up OSS CAD suite
+        uses: YosysHQ/setup-oss-cad-suite@v2
+      - name: Install dependencies
+        run: |
+          apt update && apt install -y make
+          python3 -m pip install --upgrade pip
+          pip3 install flake8 pytest
+          if [ -f requirements.txt ]; then pip3 install -r requirements.txt; fi
+      - name: Lint with flake8
+        run: |
+          # stop the build if there are Python syntax errors or undefined names
+          flake8 FABulous/**/*.py --count --select=E9,F63,F7,F82 --show-source --statistics
+          # exit-zero treats all errors as warnings. The GitHub editor is 127 chars wide
+          flake8 FABulous/**/*.py --count --exit-zero --max-complexity=10 --max-line-length=127 --statistics
+      - name: Install FABulous
+        run: |
+          pip3 install -e .
+      - name: Run fabric generator flow and simulation for VHDL
+        run: |
+          FABulous -c demo_vhdl -w vhdl
+          cd demo_vhdl/Test && make full_sim