format

FPGA-Research · Feb 10, 2025 · c23db7e · c23db7e
1 parent f3350d2
commit c23db7e
Showing 1 changed file with 3 additions and 1 deletion.
diff --git a/tests/CLI_test/conftest.py b/tests/CLI_test/conftest.py
@@ -40,7 +40,9 @@ def cli(tmp_path):
     os.environ["FAB_ROOT"] = fabulousRoot
     create_project(projectDir)
     setup_logger(0)
-    cli = FABulous_CLI(writerType="verilog", projectDir=projectDir, enteringDir=tmp_path)
+    cli = FABulous_CLI(
+        writerType="verilog", projectDir=projectDir, enteringDir=tmp_path
+    )
     run_cmd(cli, "load_fabric")
     return cli