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Merge Verilog and VHDL project templates #155
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The main problem would be that the single template would contain both the VHDL and Verilog files, which might confuse the users. We can solve this by copying only the VHDL or Verilog files according to which writer is used. Another potential problem is that the VHDL side Ultimately, we need to find a better way to maintain and handle both Verilog and VHDL backend to avoid problems like #153 |
Speaking as a user, I wouldn't find this so confusing as I know which backend I am using (Verilog/VHDL) and I could easily switch between the two. But yeah, selectively copying the files would be an option to avoid that. What way would you think of to improve maintainability? I think it would be worthwhile to setup the CI with a test suite for both Verilog and VHDL, covering various fabrics and features such as supertiles. Every time a new feature PR is opened, the CI runs all the tests to make sure no regressions have occurred. Simple regressions like in #153 should then not be possible. But I guess that's for another issue ;) |
Yes, this should improve maintainability, less duplication is always better. |
I'll open an issue regarding the CI then, if that's okay. I'll also open some other issues that improve maintainablity of FABulous or make it easier for new users to get started. |
To ease maintainability, it would make sense to merge
FABulous_project_template_verilog
andFABulous_project_template_vhdl
into a singleFABulous_project_template
.Many files in both directories are duplicated and some files/filenames already diverge.
My idea is that after merging #154, the logic for reading the tile configuration can be changed a bit:
Instead of specifying file extensions for HDL sources in
BEL
entries inside tile configs, omit them:Depending on whether a Verilog/VHDL writer is used, append the correct file ending (
.v
,.vhdl
). Since both Verilog and VHDL files are in the tile directory, the correct one can be picked up.What do you think? Am I missing something?
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