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Fix VHDL simulation, cleanup VHDL project template, add VHDL action #312

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merged 4 commits into from
Feb 11, 2025
Merged

Fix VHDL simulation, cleanup VHDL project template, add VHDL action #312

merged 4 commits into from
Feb 11, 2025

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EverythingElseWasAlreadyTaken
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@EverythingElseWasAlreadyTaken EverythingElseWasAlreadyTaken commented Feb 3, 2025 •
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  • Cleanup VHDL project template.
  • Update VHDL project files, which are mostly based on @Biswajitks1 work from Vhdl simulation #214
  • Update VHDL simulation files and testbench.
  • Add makefile for simulation.
  • Add workflow to test VHDL builds.

@KelvinChung2000
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This is nice. We finally have something to verify VHDL.

@EverythingElseWasAlreadyTaken
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This is nice. We finally have something to verify VHDL.

Thanks, but please wait with the merge, since the action is taking more than an hour to complete a run.

I figured out that the oss cad suite version of GHDL uses the LLVM backend, which is much slower than the mcode backend. I have to update the actions to speed up the runs.

On my local machine, the simulation with mcode takes about 2,5 minutes and with the llvm backend it is currently running 35 minutes, and isn't done yet...

@EverythingElseWasAlreadyTaken EverythingElseWasAlreadyTaken force-pushed the WIP/fix_VHDL_sim_init branch 3 times, most recently from 3b3637e to 408ad1f Compare February 3, 2025 12:26
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I've added GHDL mcode to the action, which reduced the runtime of the action from >1h with LLVM backend to ~7 min with mcode backend. I've also updated the docs, to suggest GHDL mcode.

Whenever this PR is merged, I'll open an Issue at GHDL, this could be maybe interesting for them.

KelvinChung2000
KelvinChung2000 reviewed Feb 3, 2025
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Other than mixing the Verilog wrapper with VHDL, which I personally don't like, but functionally is fine.

I assume all the VHDL is regenerated, so I don't look in details.

The rest is looking fine for me.

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Other than mixing the Verilog wrapper with VHDL, which I personally don't like, but functionally is fine.

Yes, I know, but this is mostly the problem, that we're currently not having proper constraint file support and i didn't find a way to replace the top wrapper with VHDL.

I assume all the VHDL is regenerated, so I don't look in details.

It's mostly generated, but there were some manual corrections for the datatypes and so on.
I took it mostly form #214 since Biswajit already did all this.

@EverythingElseWasAlreadyTaken EverythingElseWasAlreadyTaken changed the title Fix VHDL simulation, add cleanup VHDL porject tempate, add VHDL action Fix VHDL simulation, cleanup VHDL porject tempate, add VHDL action Feb 4, 2025
@EverythingElseWasAlreadyTaken EverythingElseWasAlreadyTaken changed the title Fix VHDL simulation, cleanup VHDL porject tempate, add VHDL action Fix VHDL simulation, cleanup VHDL project template, add VHDL action Feb 4, 2025
@EverythingElseWasAlreadyTaken
fabric_files:proj_template_vhdl: Remove legacy files
78cc51c 
Remove unused and legacy files from VHDL project template.

Signed-off-by: Jonas K. <[email protected]>
@EverythingElseWasAlreadyTaken
fabric_files:proj_template_vhdl: Update Fabric Files
7f1d7d0 
Updated Fabric files in VHDL project template.
These files were generated from the Fabric files from verilog project
template and are based on Biswajits work:
FPGA-Research#214

Signed-off-by: Jonas K. <[email protected]>
@EverythingElseWasAlreadyTaken
fabric_files:template_vhdl: Fix VHDL simulation and synthesis + add M…
a08bd26 
…akefile.

Fix the broken VHDL simulation and VHDL user design synthesis.
Replace old simulation scripts with a Makefile.

Add README for `Test`.
Add .gitignore in `Test`.
Update testbench, user_design and top_wrapper for simulation.

Remove old floorplaning information from fabric.csv

Signed-off-by: Jonas K. <[email protected]>
@EverythingElseWasAlreadyTaken EverythingElseWasAlreadyTaken force-pushed the WIP/fix_VHDL_sim_init branch 2 times, most recently from 78e930f to 8f293f8 Compare February 10, 2025 11:10
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Rebased to current dev branch and make use of composite workflow.

@EverythingElseWasAlreadyTaken
.github:workflows: Add VHDL build and test workflow
54cb221 
 Rename old workflow to fabric_gen_verilog.
 Add a workflow to build and simulate a VHDL fabric.

Signed-off-by: Jonas K. <[email protected]>
@EverythingElseWasAlreadyTaken EverythingElseWasAlreadyTaken merged commit 34e96bd into FPGA-Research:FABulous2.0-development Feb 11, 2025
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@EverythingElseWasAlreadyTaken EverythingElseWasAlreadyTaken mentioned this pull request Feb 19, 2025
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