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kernel32.7.2.patch
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diff -ruN tx2nxorig/kernel/nvidia/drivers/media/i2c/imx219_mode_tbls.h tx2nx/kernel/nvidia/drivers/media/i2c/imx219_mode_tbls.h
--- tx2nxorig/kernel/nvidia/drivers/media/i2c/imx219_mode_tbls.h 2022-02-16 00:20:23.000000000 -0600
+++ tx2nx/kernel/nvidia/drivers/media/i2c/imx219_mode_tbls.h 2022-09-20 23:59:28.863491815 -0500
@@ -93,8 +93,10 @@
{0x0171, 0x01},
{0x0174, 0x00},
{0x0175, 0x00},
- {0x018C, 0x0A},
- {0x018D, 0x0A},
+ //{0x018C, 0x0A}, // 10 bit
+ //{0x018D, 0x0A}, // 10 bit
+ {0x018C, 0x08}, // 8 bit
+ {0x018D, 0x08}, // 8 bit
{0x0264, 0x00},
{0x0265, 0x08},
{0x0266, 0x0C},
@@ -108,7 +110,8 @@
{0x0305, 0x03},
{0x0306, 0x00},
{0x0307, 0x39},
- {0x0309, 0x0A},
+ //{0x0309, 0x0A}, // 10 bit
+ {0x0309, 0x08}, // 8 bit
{0x030B, 0x01},
{0x030C, 0x00},
{0x030D, 0x72},
@@ -141,8 +144,10 @@
{0x0171, 0x01},
{0x0174, 0x00},
{0x0175, 0x00},
- {0x018C, 0x0A},
- {0x018D, 0x0A},
+ //{0x018C, 0x0A}, // 10 bit
+ //{0x018D, 0x0A}, // 10 bit
+ {0x018C, 0x08}, // 8 bit
+ {0x018D, 0x08}, // 8 bit
{0x0264, 0x00},
{0x0265, 0x08},
{0x0266, 0x0C},
@@ -156,7 +161,8 @@
{0x0305, 0x03},
{0x0306, 0x00},
{0x0307, 0x39},
- {0x0309, 0x0A},
+ //{0x0309, 0x0A}, // 10 bit
+ {0x0309, 0x08}, // 8 bit
{0x030B, 0x01},
{0x030C, 0x00},
{0x030D, 0x72},
@@ -189,8 +195,10 @@
{0x0171, 0x01},
{0x0174, 0x00},
{0x0175, 0x00},
- {0x018C, 0x0A},
- {0x018D, 0x0A},
+ //{0x018C, 0x0A}, // 10 bit
+ //{0x018D, 0x0A}, // 10 bit
+ {0x018C, 0x08}, // 8 bit
+ {0x018D, 0x08}, // 8 bit
/* clocks dividers */
{0x0301, 0x05},
{0x0303, 0x01},
@@ -198,7 +206,8 @@
{0x0305, 0x03},
{0x0306, 0x00},
{0x0307, 0x39},
- {0x0309, 0x0A},
+ //{0x0309, 0x0A}, // 10 bit
+ {0x0309, 0x08}, // 8 bit
{0x030B, 0x01},
{0x030C, 0x00},
{0x030D, 0x72},
@@ -231,8 +240,10 @@
{0x0171, 0x01},
{0x0174, 0x01},
{0x0175, 0x01},
- {0x018C, 0x0A},
- {0x018D, 0x0A},
+ //{0x018C, 0x0A}, // 10 bit
+ //{0x018D, 0x0A}, // 10 bit
+ {0x018C, 0x08}, // 8 bit
+ {0x018D, 0x08}, // 8 bit
/* clocks dividers */
{0x0301, 0x05},
{0x0303, 0x01},
@@ -240,23 +251,25 @@
{0x0305, 0x03},
{0x0306, 0x00},
{0x0307, 0x39},
- {0x0309, 0x0A},
+ //{0x0309, 0x0A}, // 10 bit
+ {0x0309, 0x08}, // 8 bit
{0x030B, 0x01},
{0x030C, 0x00},
{0x030D, 0x72},
{IMX219_TABLE_END, 0x00}
};
+/*
static imx219_reg imx219_mode_1280x720_60fps[] = {
- /* capture settings */
- {0x0157, 0x00}, /* ANALOG_GAIN_GLOBAL[7:0] */
- {0x015A, 0x03}, /* COARSE_INTEG_TIME[15:8] */
- {0x015B, 0x6c}, /* COARSE_INTEG_TIME[7:0] */
- /* format settings */
- {0x0160, 0x03}, /* FRM_LENGTH[15:8] */
- {0x0161, 0x70}, /* FRM_LENGTH[7:0] */
- {0x0162, 0x0D}, /* LINE_LENGTH[15:8] */
- {0x0163, 0x78}, /* LINE_LENGTH[7:0] */
+ // capture settings
+ {0x0157, 0x00}, // ANALOG_GAIN_GLOBAL[7:0]
+ {0x015A, 0x03}, // COARSE_INTEG_TIME[15:8]
+ {0x015B, 0x6c}, // COARSE_INTEG_TIME[7:0]
+ // format settings
+ {0x0160, 0x03}, // FRM_LENGTH[15:8]
+ {0x0161, 0x70}, // FRM_LENGTH[7:0]
+ {0x0162, 0x0D}, // LINE_LENGTH[15:8]
+ {0x0163, 0x78}, // LINE_LENGTH[7:0]
{0x0164, 0x01},
{0x0165, 0x68},
{0x0166, 0x0B},
@@ -273,33 +286,37 @@
{0x0171, 0x01},
{0x0174, 0x01},
{0x0175, 0x01},
- {0x018C, 0x0A},
- {0x018D, 0x0A},
- /* clocks dividers */
+ //{0x018C, 0x0A}, // 10 bit
+ //{0x018D, 0x0A}, // 10 bit
+ {0x018C, 0x08}, // 8 bit
+ {0x018D, 0x08}, // 8 bit
+ // clocks dividers
{0x0301, 0x05},
{0x0303, 0x01},
{0x0304, 0x03},
{0x0305, 0x03},
{0x0306, 0x00},
{0x0307, 0x39},
- {0x0309, 0x0A},
+ //{0x0309, 0x0A}, // 10 bit
+ {0x0309, 0x08}, // 8 bit
{0x030B, 0x01},
{0x030C, 0x00},
{0x030D, 0x72},
{IMX219_TABLE_END, 0x00}
};
+*/
-/*
static imx219_reg imx219_mode_1280x720_120fps[] = {
// capture settings
- {0x0157, 0x00}, // ANALOG_GAIN_GLOBAL[7:0]
- {0x015A, 0x01}, // COARSE_INTEG_TIME[15:8]
- {0x015B, 0x85}, // COARSE_INTEG_TIME[7:0]
+ //{0x0157, 0x00}, // ANALOG_GAIN_GLOBAL[7:0]
+ {0x0157, 0xe7}, // ANALOG_GAIN_GLOBAL[7:0]
+ {0x015A, 0x01}, // COARSE_INTEG_TIME[15:8] //diff
+ {0x015B, 0x85}, // COARSE_INTEG_TIME[7:0] //diff
// format settings
- {0x0160, 0x01}, // FRM_LENGTH[15:8]
- {0x0161, 0x89}, // FRM_LENGTH[7:0]
+ {0x0160, 0x01}, // FRM_LENGTH[15:8] //diff
+ {0x0161, 0x89}, // FRM_LENGTH[7:0] //diff
{0x0162, 0x0D}, // LINE_LENGTH[15:8]
- {0x0163, 0xE8}, // LINE_LENGTH[7:0]
+ {0x0163, 0xE8}, // LINE_LENGTH[7:0] //diff
{0x0164, 0x01},
{0x0165, 0x68},
{0x0166, 0x0B},
@@ -313,31 +330,35 @@
{0x016E, 0x02},
{0x016F, 0xD0},
{0x0170, 0x01},
- {0x0171, 0x01},
- {0x0174, 0x03},
- {0x0175, 0x03},
- {0x018C, 0x0A},
- {0x018D, 0x0A},
+ {0x0171, 0x01},
+ {0x0174, 0x03}, //diff
+ {0x0175, 0x03}, //diff
+ //{0x018C, 0x0A}, // 10 bit
+ //{0x018D, 0x0A}, // 10 bit
+ {0x018C, 0x08}, // 8 bit
+ {0x018D, 0x08}, // 8 bit
// clocks dividers
{0x0301, 0x05},
+ //{0x0301, 0x04}, // ?8 bit unclear this is needed
{0x0303, 0x01},
{0x0304, 0x03},
{0x0305, 0x03},
{0x0306, 0x00},
- {0x0307, 0x35},
- {0x0309, 0x0A},
+ {0x0307, 0x35}, //diff
+ //{0x0309, 0x0A}, // 10 bit
+ {0x0309, 0x08}, // 8 bit
{0x030B, 0x01},
{0x030C, 0x00},
- {0x030D, 0x66},
+ {0x030D, 0x66}, //diff
{IMX219_TABLE_END, 0x00}
};
-*/
enum {
IMX219_MODE_3264x2464_21FPS,
IMX219_MODE_3264x1848_28FPS,
IMX219_MODE_1920x1080_30FPS,
IMX219_MODE_1640x1232_30FPS,
- IMX219_MODE_1280x720_60FPS,
+ //IMX219_MODE_1280x720_60FPS,
+ IMX219_MODE_1280x720_120FPS,
IMX219_MODE_COMMON,
IMX219_START_STREAM,
@@ -349,7 +370,8 @@
[IMX219_MODE_3264x1848_28FPS] = imx219_mode_3264x1848_28fps,
[IMX219_MODE_1920x1080_30FPS] = imx219_mode_1920x1080_30fps,
[IMX219_MODE_1640x1232_30FPS] = imx219_mode_1640x1232_30fps,
- [IMX219_MODE_1280x720_60FPS] = imx219_mode_1280x720_60fps,
+ //[IMX219_MODE_1280x720_60FPS] = imx219_mode_1280x720_60fps,
+ [IMX219_MODE_1280x720_120FPS] = imx219_mode_1280x720_120fps,
[IMX219_MODE_COMMON] = imx219_mode_common,
[IMX219_START_STREAM] = imx219_start_stream,
@@ -368,9 +390,15 @@
30,
};
+/*
static const int imx219_60fps[] = {
60,
};
+*/
+
+static const int imx219_120fps[] = {
+ 120,
+};
/*
* WARNING: frmfmt ordering need to match mode definition in
@@ -382,7 +410,8 @@
{{3264, 1848}, imx219_28fps, 1, 0, IMX219_MODE_3264x1848_28FPS},
{{1920, 1080}, imx219_30fps, 1, 0, IMX219_MODE_1920x1080_30FPS},
{{1640, 1232}, imx219_30fps, 1, 0, IMX219_MODE_1640x1232_30FPS},
- {{1280, 720}, imx219_60fps, 1, 0, IMX219_MODE_1280x720_60FPS},
+ //{{1280, 720}, imx219_60fps, 1, 0, IMX219_MODE_1280x720_60FPS},
+ {{1280, 720}, imx219_120fps, 1, 0, IMX219_MODE_1280x720_120FPS},
};
#endif /* __IMX219_I2C_TABLES__ */
diff -ruN tx2nxorig/kernel/nvidia/drivers/media/i2c/ov9281.c tx2nx/kernel/nvidia/drivers/media/i2c/ov9281.c
--- tx2nxorig/kernel/nvidia/drivers/media/i2c/ov9281.c 2022-02-16 00:20:23.000000000 -0600
+++ tx2nx/kernel/nvidia/drivers/media/i2c/ov9281.c 2022-11-08 13:12:15.900264012 -0600
@@ -15,10 +15,12 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
+/*#define DEBUG */
#include <linux/slab.h>
#include <linux/uaccess.h>
#include <linux/gpio.h>
#include <linux/module.h>
+#include <linux/i2c.h>
#include <linux/seq_file.h>
#include <linux/of.h>
@@ -102,13 +104,32 @@
#define OV9281_DEFAULT_MODE OV9281_MODE_1280X800
#define OV9281_DEFAULT_WIDTH OV9281_MAX_WIDTH
#define OV9281_DEFAULT_HEIGHT OV9281_MAX_HEIGHT
-#define OV9281_DEFAULT_DATAFMT MEDIA_BUS_FMT_SBGGR10_1X10
-#define OV9281_DEFAULT_CLK_FREQ 26000000
+/*#define OV9281_DEFAULT_DATAFMT MEDIA_BUS_FMT_SBGGR10_1X10 */
+#define OV9281_DEFAULT_DATAFMT MEDIA_BUS_FMT_SRGGB8_1X8
+/*#define OV9281_DEFAULT_DATAFMT MEDIA_BUS_FMT_Y8_1X8*/
+#define OV9281_DEFAULT_CLK_FREQ 24000000
#define OV9281_DEFAULT_I2C_ADDRESS_C0 (0xc0 >> 1)
#define OV9281_DEFAULT_I2C_ADDRESS_20 (0x20 >> 1)
#define OV9281_DEFAULT_I2C_ADDRESS_PROGRAMMABLE (0xe0 >> 1)
+static int sensor_mode = 1;
+
+struct inno_rom_table {
+ char magic[12];
+ char manuf[32];
+ u16 manuf_id;
+ char sen_manuf[8];
+ char sen_type[16];
+ u16 mod_id;
+ u16 mod_rev;
+ char regs[56];
+ u16 nr_modes;
+ u16 bytes_per_mode;
+ char mode1[16];
+ char mode2[16];
+};
+
struct ov9281 {
struct camera_common_power_rail power;
int num_ctrls;
@@ -129,9 +150,128 @@
struct regmap *regmap;
struct camera_common_data *s_data;
struct camera_common_pdata *pdata;
+ struct i2c_client *rom;
+ struct inno_rom_table rom_table;
struct v4l2_ctrl *ctrls[];
};
+/*
+static int reg_write(struct i2c_client *client, const u16 addr, const u8 data)
+{
+ struct i2c_adapter *adap = client->adapter;
+ struct i2c_msg msg;
+ u8 tx[3];
+ int ret;
+
+ msg.addr = client->addr;
+ msg.buf = tx;
+ msg.len = 3;
+ msg.flags = 0;
+ tx[0] = addr >> 8;
+ tx[1] = addr & 0xff;
+ tx[2] = data;
+ ret = i2c_transfer(adap, &msg, 1);
+ mdelay(2);
+
+ return ret == 1 ? 0 : -EIO;
+}
+*/
+
+static int rom_write(struct i2c_client *client, const u8 addr, const u8 data)
+{
+ struct i2c_adapter *adap = client->adapter;
+ struct i2c_msg msg;
+ u8 tx[2];
+ int ret;
+
+ msg.addr = client->addr;
+ msg.buf = tx;
+ msg.len = 2;
+ msg.flags = 0;
+ tx[0] = addr;
+ tx[1] = data;
+ ret = i2c_transfer(adap, &msg, 1);
+ mdelay(2);
+
+ return ret == 1 ? 0 : -EIO;
+}
+
+/*
+static int reg_read(struct i2c_client *client, const u16 addr)
+{
+ u8 buf[2] = {addr >> 8, addr & 0xff};
+ int ret;
+ struct i2c_msg msgs[] = {
+ {
+ .addr = client->addr,
+ .flags = 0,
+ .len = 2,
+ .buf = buf,
+ }, {
+ .addr = client->addr,
+ .flags = I2C_M_RD,
+ .len = 1,
+ .buf = buf,
+ },
+ };
+
+ ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
+ if (ret < 0) {
+ dev_warn(&client->dev, "Reading register %x from %x failed\n",
+ addr, client->addr);
+ return ret;
+ }
+
+ return buf[0];
+}
+*/
+
+static int rom_read(struct i2c_client *client, const u8 addr)
+{
+ u8 buf[1]={ addr };
+ int ret;
+ struct i2c_msg msgs[] = {
+ {
+ .addr = client->addr,
+ .flags = 0,
+ .len = 1,
+ .buf = buf,
+ }, {
+ .addr = client->addr,
+ .flags = I2C_M_RD,
+ .len = 1,
+ .buf = buf,
+ },
+ };
+
+ ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
+ if (ret < 0) {
+ dev_warn(&client->dev, "Reading register %x from %x failed\n",
+ addr, client->addr);
+ return ret;
+ }
+
+ return buf[0];
+}
+
+/*
+static int reg_write_table(struct i2c_client *client,
+ const struct ov9281_reg table[])
+{
+ const struct ov9281_reg *reg;
+ int ret;
+
+ for (reg = table; reg->addr != OV9281_TABLE_END; reg++) {
+ ret = reg_write(client, reg->addr, reg->val);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+*/
+
+
/* Register/regmap stuff */
static int ov9281_read_reg(struct camera_common_data *s_data, u16 addr, u8 *val)
{
@@ -1146,9 +1286,16 @@
struct camera_common_data *common_data;
struct device *dev = &client->dev;
struct ov9281 *priv;
+ struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
+
int err;
- dev_info(dev, "probing v4l2 sensor.\n");
+ dev_info(dev, "probing v4l2 sensor at addr 0x%0x\n", client->addr);
+
+ if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
+ dev_warn(&adapter->dev,
+ "I2C-Adapter doesn't support I2C_FUNC_SMBUS_BYTE\n");
+ }
common_data = devm_kzalloc(dev, sizeof(*common_data), GFP_KERNEL);
@@ -1162,6 +1309,82 @@
return -ENOMEM;
}
+
+ priv->rom = i2c_new_dummy(adapter,0x10); /*_device*/
+ if ( priv->rom )
+ {
+ static int i=1;
+ int addr,reg,data;
+ dev_info(&client->dev, "InnoMaker Camera controller found!\n");
+#if 1
+ for (addr=0; addr<sizeof(priv->rom_table); addr++)
+ {
+ reg = rom_read(priv->rom, addr);
+ *((char *)(&(priv->rom_table))+addr)=(char)reg;
+ dev_dbg(&client->dev, "addr=0x%04x reg=0x%02x\n",addr,reg);
+ }
+
+ dev_info(&client->dev, "[ MAGIC ] [ %s ]\n",
+ priv->rom_table.magic);
+
+ dev_info(&client->dev, "[ MANUF. ] [ %s ] [ MID=0x%04x ]\n",
+ priv->rom_table.manuf,
+ priv->rom_table.manuf_id);
+
+ dev_info(&client->dev, "[ SENSOR ] [ %s %s ]\n",
+ priv->rom_table.sen_manuf,
+ priv->rom_table.sen_type);
+
+ dev_info(&client->dev, "[ MODULE ] [ ID=0x%04x ] [ REV=0x%04x ]\n",
+ priv->rom_table.mod_id,
+ priv->rom_table.mod_rev);
+
+ dev_info(&client->dev, "[ MODES ] [ NR=0x%04x ] [ BPM=0x%04x ]\n",
+ priv->rom_table.nr_modes,
+ priv->rom_table.bytes_per_mode);
+#endif
+ addr = 200; // reset
+ data = 2; // powerdown sensor
+ reg = rom_write(priv->rom, addr, data);
+
+ addr = 202; // mode
+ data = sensor_mode; // default 8-bit streaming
+ reg = rom_write(priv->rom, addr, data);
+
+ //addr = 200; // reset
+ //data = 0; // powerup sensor
+ //reg = reg_write(priv->rom, addr, data);
+
+ while(1)
+ {
+ mdelay(100); // wait 100ms
+
+ addr = 201; // status
+ reg = rom_read(priv->rom, addr);
+
+ if(reg & 0x80)
+ break;
+
+ if(reg & 0x01)
+ dev_err(&client->dev, "!!! ERROR !!! setting Sensor MODE=%d STATUS=0x%02x i=%d\n",sensor_mode,reg,i);
+
+ if(i++ > 4)
+ break;
+ }
+
+ dev_info(&client->dev, " Sensor MODE=%d PowerOn STATUS=0x%02x i=%d\n",sensor_mode,reg,i);
+
+ }
+ else
+ {
+
+ dev_err(&client->dev, "NOTE !!! External Camera controller not found !!!\n");
+ dev_info(&client->dev, "Sensor MODE=%d \n",sensor_mode);
+ return -EIO;
+ }
+
+
+
priv->regmap = devm_regmap_init_i2c(client, &ov9281_regmap_config);
if (IS_ERR(priv->regmap)) {
dev_err(dev, "regmap init failed %ld\n", PTR_ERR(priv->regmap));
diff -ruN tx2nxorig/kernel/nvidia/drivers/media/i2c/ov9281_mode_tbls.h tx2nx/kernel/nvidia/drivers/media/i2c/ov9281_mode_tbls.h
--- tx2nxorig/kernel/nvidia/drivers/media/i2c/ov9281_mode_tbls.h 2022-02-16 00:20:23.000000000 -0600
+++ tx2nx/kernel/nvidia/drivers/media/i2c/ov9281_mode_tbls.h 2022-11-07 21:12:00.370616961 -0600
@@ -28,8 +28,8 @@
enum {
OV9281_MODE_1280X800,
- OV9281_MODE_1280X720,
- OV9281_MODE_640X400,
+/* OV9281_MODE_1280X720,
+ OV9281_MODE_640X400, */
OV9281_MODE_START_STREAM,
OV9281_MODE_STOP_STREAM,
};
@@ -74,6 +74,7 @@
{ OV9281_TABLE_END, 0x00 }
};
+#if 0
static const ov9281_reg ov9281_mode_1280x800_26MhzMCLK[] = {
/* PLL control */
{ 0x0302, 0x32 },
@@ -225,7 +226,116 @@
{ 0x3827, 0x8a },
{ OV9281_TABLE_END, 0x00 }
};
+#endif
+static const ov9281_reg ov9281_mode_1280x800_24MhzMCLK_fsync_slave[] = {
+ { 0x3826, 0x03 }, /* R reset value on fsin. VTS - 4 */
+ { 0x3827, 0x8a },
+ { OV9281_TABLE_END, 0x00 }
+};
+
+static const ov9281_reg ov9281_mode_1280x800_24MhzMCLK[] = {
+ /*
+ {0x0103, 0x01},
+ {0x0302, 0x32},
+ {0x030d, 0x50},
+ {0x030e, 0x02},
+ {0x3001, 0x00},
+ {0x3004, 0x00},
+ {0x3005, 0x00},
+ {0x3006, 0x04},
+ {0x3011, 0x0a},
+ {0x3013, 0x18},
+ {0x3022, 0x01},
+ {0x3023, 0x00},
+ {0x302c, 0x00},
+ {0x302f, 0x00},
+ {0x3030, 0x04},
+ {0x3039, 0x32},
+ {0x303a, 0x00},
+ {0x303f, 0x01},
+ {0x3500, 0x00},
+ {0x3501, 0x2a},
+ {0x3502, 0x90},
+ {0x3503, 0x08},
+ {0x3505, 0x8c},
+ {0x3507, 0x03},
+ {0x3508, 0x00},
+ {0x3509, 0x10},
+ {0x3610, 0x80},
+ {0x3611, 0xa0},
+ {0x3620, 0x6f},
+ {0x3632, 0x56},
+ {0x3633, 0x78},
+ {0x3662, 0x05},
+ {0x3666, 0x00},
+ {0x366f, 0x5a},
+ {0x3680, 0x84},
+ {0x3712, 0x80},
+ {0x372d, 0x22},
+ {0x3731, 0x80},
+ {0x3732, 0x30},
+ {0x3778, 0x00},
+ {0x377d, 0x22},
+ {0x3788, 0x02},
+ {0x3789, 0xa4},
+ {0x378a, 0x00},
+ {0x378b, 0x4a},
+ {0x3799, 0x20},
+ {0x3800, 0x00},
+ {0x3801, 0x00},
+ {0x3802, 0x00},
+ {0x3803, 0x00},
+ {0x3804, 0x05},
+ {0x3805, 0x0f},
+ {0x3806, 0x03},
+ {0x3807, 0x2f},
+ {0x3808, 0x05},
+ {0x3809, 0x00},
+ {0x380a, 0x03},
+ {0x380b, 0x20},
+ {0x380c, 0x02},
+ {0x380d, 0xd8},
+ {0x380e, 0x03},
+ {0x380f, 0x8e},
+ {0x3810, 0x00},
+ {0x3811, 0x08},
+ {0x3812, 0x00},
+ {0x3813, 0x08},
+ {0x3814, 0x11},
+ {0x3815, 0x11},
+ {0x3820, 0x40},
+ {0x3821, 0x00},
+ {0x3881, 0x42},
+ {0x38b1, 0x00},
+ {0x3920, 0xff},
+ {0x4003, 0x40},
+ {0x4008, 0x04},
+ {0x4009, 0x0b},
+ {0x400c, 0x00},
+ {0x400d, 0x07},
+ {0x4010, 0x40},
+ {0x4043, 0x40},
+ {0x4307, 0x30},
+ {0x4317, 0x00},
+ {0x4501, 0x00},
+ {0x4507, 0x00},
+ {0x4509, 0x00},
+ {0x450a, 0x08},
+ {0x4601, 0x04},
+ {0x470f, 0x00},
+ {0x4f07, 0x00},
+ {0x4800, 0x00},
+ {0x5000, 0x9f},
+ {0x5001, 0x00},
+ {0x5e00, 0x00},
+ {0x5d00, 0x07},
+ {0x5d01, 0x00},
+ */
+ {OV9281_TABLE_END, 0x00 }
+};
+
+#if 0
static const ov9281_reg ov9281_mode_1280x720_26MhzMCLK[] = {
{ 0x0302, 0x32 },
{ 0x030d, 0x50 },
@@ -437,19 +547,22 @@
{ 0x3827, 0x04 },
{ OV9281_TABLE_END, 0x00 }
};
+#endif
static const ov9281_reg *ov9281_mode_table[] = {
- [OV9281_MODE_1280X800] = ov9281_mode_1280x800_26MhzMCLK,
+ [OV9281_MODE_1280X800] = ov9281_mode_1280x800_24MhzMCLK,
+/* [OV9281_MODE_1280X800] = ov9281_mode_1280x800_26MhzMCLK,
[OV9281_MODE_1280X720] = ov9281_mode_1280x720_26MhzMCLK,
- [OV9281_MODE_640X400] = ov9281_mode_640x400_26MhzMCLK,
+ [OV9281_MODE_640X400] = ov9281_mode_640x400_26MhzMCLK, */
[OV9281_MODE_START_STREAM] = ov9281_start,
[OV9281_MODE_STOP_STREAM] = ov9281_stop,
};
static const ov9281_reg *ov9281_fsync_slave_mode_table[] = {
- [OV9281_MODE_1280X800] = ov9281_mode_1280x800_26MhzMCLK_fsync_slave,
+ [OV9281_MODE_1280X800] = ov9281_mode_1280x800_24MhzMCLK_fsync_slave,
+/* [OV9281_MODE_1280X800] = ov9281_mode_1280x800_26MhzMCLK_fsync_slave,
[OV9281_MODE_1280X720] = ov9281_mode_1280x720_26MhzMCLK_fsync_slave,
- [OV9281_MODE_640X400] = ov9281_mode_640x400_26MhzMCLK_fsync_slave,
+ [OV9281_MODE_640X400] = ov9281_mode_640x400_26MhzMCLK_fsync_slave, */
};
static const ov9281_reg *ov9281_fsync_table[] = {
@@ -462,13 +575,19 @@
60,
};
+static const int ov9281_120fps[] = {
+ 120,
+};
+
static const struct camera_common_frmfmt ov9281_frmfmt[] = {
- { { 1280, 800 }, ov9281_60fps, ARRAY_SIZE(ov9281_60fps), 0,
+ { { 1280, 800 }, ov9281_120fps, ARRAY_SIZE(ov9281_120fps), 0,
+ OV9281_MODE_1280X800 },
+ /*{ { 1280, 800 }, ov9281_60fps, ARRAY_SIZE(ov9281_60fps), 0,
OV9281_MODE_1280X800 },
{ { 1280, 720 }, ov9281_60fps, ARRAY_SIZE(ov9281_60fps), 0,
OV9281_MODE_1280X720 },
{ { 640, 400 }, ov9281_60fps, ARRAY_SIZE(ov9281_60fps), 0,
- OV9281_MODE_640X400 },
+ OV9281_MODE_640X400 }, */
};
#endif /* __OV9281_I2C_TABLES__ */
diff -ruN tx2nxorig/kernel/nvidia/drivers/media/platform/tegra/camera/camera_common.c tx2nx/kernel/nvidia/drivers/media/platform/tegra/camera/camera_common.c
--- tx2nxorig/kernel/nvidia/drivers/media/platform/tegra/camera/camera_common.c 2022-02-16 00:20:23.000000000 -0600
+++ tx2nx/kernel/nvidia/drivers/media/platform/tegra/camera/camera_common.c 2022-11-08 13:22:37.893472298 -0600
@@ -126,6 +126,24 @@
V4L2_COLORSPACE_SRGB,
V4L2_PIX_FMT_VYUY,
},
+ // Grayscale 8bit support
+ {
+ MEDIA_BUS_FMT_Y8_1X8,
+ V4L2_COLORSPACE_RAW,
+ V4L2_PIX_FMT_GREY,
+ },
+ // Grayscale 10bit support
+ {
+ MEDIA_BUS_FMT_Y10_1X10,
+ V4L2_COLORSPACE_RAW,
+ V4L2_PIX_FMT_Y10,
+ },
+ // Grayscale 12bit support
+ {
+ MEDIA_BUS_FMT_Y12_1X12,
+ V4L2_COLORSPACE_RAW,
+ V4L2_PIX_FMT_Y12,
+ },
/*
* The below two formats are not supported by VI4,
* keep them at the last to ensure they get discarded
diff -ruN tx2nxorig/kernel/nvidia/drivers/media/platform/tegra/camera/sensor_common.c tx2nx/kernel/nvidia/drivers/media/platform/tegra/camera/sensor_common.c
--- tx2nxorig/kernel/nvidia/drivers/media/platform/tegra/camera/sensor_common.c 2022-02-16 00:20:23.000000000 -0600
+++ tx2nx/kernel/nvidia/drivers/media/platform/tegra/camera/sensor_common.c 2022-11-08 13:20:58.838432234 -0600
@@ -197,7 +197,9 @@
{
size_t size = strnlen(pixel_t, OF_MAX_STR_LEN);
- if (strncmp(pixel_t, "bayer_bggr10", size) == 0)
+ if (strncmp(pixel_t, "bayer_rggb", size) == 0)
+ *format = V4L2_PIX_FMT_SRGGB8;
+ else if (strncmp(pixel_t, "bayer_bggr10", size) == 0)
*format = V4L2_PIX_FMT_SBGGR10;
else if (strncmp(pixel_t, "bayer_rggb10", size) == 0)
*format = V4L2_PIX_FMT_SRGGB10;
@@ -235,6 +237,12 @@
*format = V4L2_PIX_FMT_UYVY;
else if (strncmp(pixel_t, "yuv_vyuy16", size) == 0)
*format = V4L2_PIX_FMT_VYUY;
+ else if (strncmp(pixel_t, "raw_y88", size) == 0)
+ *format = V4L2_PIX_FMT_GREY;
+ else if (strncmp(pixel_t, "raw_y1010", size) == 0)
+ *format = V4L2_PIX_FMT_Y10;
+ else if (strncmp(pixel_t, "raw_y1212", size) == 0)
+ *format = V4L2_PIX_FMT_Y12;
else {
pr_err("%s: Need to extend format%s\n", __func__, pixel_t);
return -EINVAL;