From 54b3b75ba10be58e7b1bf1886663c01eee245042 Mon Sep 17 00:00:00 2001 From: Devaraj Ranganna Date: Mon, 9 Oct 2023 09:13:11 +0000 Subject: [PATCH] aarch64: Rename ARM_CA53_64_BIT/_SRE to Arm_AARCH64/_SRE The Cortex-A53 ports are generic and can be used as a starting point for other Armv8-A application processors. Therefore, rename `ARM_CA53_64_BIT` to `Arm_AARCH64` and `ARM_CA53_64_BIT_SRE` to `Arm_AARCH64_SRE`. With this renaming, existing projects that use old port, should migrate to renamed port as follows: * `ARM_CA53_64_BIT` -> `Arm_AARCH64` * `ARM_CA53_64_BIT_SRE` -> `Arm_AARCH64_SRE` Signed-off-by: Devaraj Ranganna --- CMakeLists.txt | 4 ++-- portable/CMakeLists.txt | 16 ++++++------- portable/GCC/ARM_CA53_64_BIT/README.md | 16 +++++++++++++ portable/GCC/ARM_CA53_64_BIT_SRE/README.md | 16 +++++++++++++ portable/GCC/Arm_AARCH64/README.md | 23 +++++++++++++++++++ .../{ARM_CA53_64_BIT => Arm_AARCH64}/port.c | 0 .../portASM.S | 0 .../portmacro.h | 0 portable/GCC/Arm_AARCH64_SRE/README.md | 23 +++++++++++++++++++ .../port.c | 0 .../portASM.S | 0 .../portmacro.h | 0 12 files changed, 88 insertions(+), 10 deletions(-) create mode 100644 portable/GCC/ARM_CA53_64_BIT/README.md create mode 100644 portable/GCC/ARM_CA53_64_BIT_SRE/README.md create mode 100644 portable/GCC/Arm_AARCH64/README.md rename portable/GCC/{ARM_CA53_64_BIT => Arm_AARCH64}/port.c (100%) rename portable/GCC/{ARM_CA53_64_BIT => Arm_AARCH64}/portASM.S (100%) rename portable/GCC/{ARM_CA53_64_BIT => Arm_AARCH64}/portmacro.h (100%) create mode 100644 portable/GCC/Arm_AARCH64_SRE/README.md rename portable/GCC/{ARM_CA53_64_BIT_SRE => Arm_AARCH64_SRE}/port.c (100%) rename portable/GCC/{ARM_CA53_64_BIT_SRE => Arm_AARCH64_SRE}/portASM.S (100%) rename portable/GCC/{ARM_CA53_64_BIT_SRE => Arm_AARCH64_SRE}/portmacro.h (100%) diff --git a/CMakeLists.txt b/CMakeLists.txt index 984e36ecd2c..d44d047b32d 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -58,8 +58,8 @@ if(NOT FREERTOS_PORT) " CODEWARRIOR_COLDFIRE_V2 - Compiler: CoreWarrior Target: ColdFire V2\n" " CODEWARRIOR_HCS12 - Compiler: CoreWarrior Target: HCS12\n" " GCC_ARM_CA9 - Compiler: GCC Target: ARM Cortex-A9\n" - " GCC_ARM_CA53_64_BIT - Compiler: GCC Target: ARM Cortex-A53 64 bit\n" - " GCC_ARM_CA53_64_BIT_SRE - Compiler: GCC Target: ARM Cortex-A53 64 bit SRE\n" + " GCC_ARM_AARCH64 - Compiler: GCC Target: ARM v8-A\n" + " GCC_ARM_AARCH64_SRE - Compiler: GCC Target: ARM v8-A SRE\n" " GCC_ARM_CM0 - Compiler: GCC Target: ARM Cortex-M0\n" " GCC_ARM_CM3 - Compiler: GCC Target: ARM Cortex-M3\n" " GCC_ARM_CM3_MPU - Compiler: GCC Target: ARM Cortex-M3 with MPU\n" diff --git a/portable/CMakeLists.txt b/portable/CMakeLists.txt index 327e9236b5a..64f5e9b0d87 100644 --- a/portable/CMakeLists.txt +++ b/portable/CMakeLists.txt @@ -59,13 +59,13 @@ add_library(freertos_kernel_port STATIC GCC/ARM_CA9/portASM.S> # ARMv8-A ports for GCC - $<$: - GCC/ARM_CA53_64_BIT/port.c - GCC/ARM_CA53_64_BIT/portASM.S> + $<$: + GCC/Arm_AARCH64/port.c + GCC/Arm_AARCH64/portASM.S> - $<$: - GCC/ARM_CA53_64_BIT_SRE/port.c - GCC/ARM_CA53_64_BIT_SRE/portASM.S> + $<$: + GCC/Arm_AARCH64_SRE/port.c + GCC/Arm_AARCH64_SRE/portASM.S> # ARMv6-M port for GCC $<$: @@ -745,8 +745,8 @@ target_include_directories(freertos_kernel_port PUBLIC $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CA9> # ARMv8-A ports for GCC - $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CA53_64_BIT> - $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CA53_64_BIT_SRE> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/Arm_AARCH64> + $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/Arm_AARCH64_SRE> # ARMv6-M port for GCC $<$:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CM0> diff --git a/portable/GCC/ARM_CA53_64_BIT/README.md b/portable/GCC/ARM_CA53_64_BIT/README.md new file mode 100644 index 00000000000..b3d56c0407c --- /dev/null +++ b/portable/GCC/ARM_CA53_64_BIT/README.md @@ -0,0 +1,16 @@ +# ARM_CA53_64_BIT port + +Initial port to support Armv8-A architecture in FreeRTOS kernel was written for +Arm Cortex-A53 processor. + +* ARM_CA53_64_BIT + * Memory mapped interace to access Arm GIC registers + +This port is generic and can be used as a starting point for other Armv8-A +application processors. Therefore, the port `ARM_CA53_64_BIT` is renamed as +`Arm_AARCH64`. The existing projects that use old port `ARM_CA53_64_BIT`, +should migrate to renamed port `Arm_AARCH64`. + +**NOTE** + +This port uses memory mapped interace to access Arm GIC registers. diff --git a/portable/GCC/ARM_CA53_64_BIT_SRE/README.md b/portable/GCC/ARM_CA53_64_BIT_SRE/README.md new file mode 100644 index 00000000000..fb5d7936a1a --- /dev/null +++ b/portable/GCC/ARM_CA53_64_BIT_SRE/README.md @@ -0,0 +1,16 @@ +# ARM_CA53_64_BIT_SRE port + +Initial port to support Armv8-A architecture in FreeRTOS kernel was written for +Arm Cortex-A53 processor. + +* ARM_CA53_64_BIT_SRE + * System Register interace to access Arm GIC registers + +This port is generic and can be used as a starting point for other Armv8-A +application processors. Therefore, the port `Arm_AARCH64_SRE` is renamed as +`Arm_AARCH64_SRE`. The existing projects that use old port `Arm_AARCH64_SRE`, +should migrate to renamed port `Arm_AARCH64_SRE`. + +**NOTE** + +This port uses System Register interace to access Arm GIC registers. diff --git a/portable/GCC/Arm_AARCH64/README.md b/portable/GCC/Arm_AARCH64/README.md new file mode 100644 index 00000000000..70552c202dd --- /dev/null +++ b/portable/GCC/Arm_AARCH64/README.md @@ -0,0 +1,23 @@ +# Armv8-A architecture support + +The Armv8-A architecture introduces the ability to use 64-bit and 32-bit +Execution states, known as AArch64 and AArch32 respectively. The AArch64 +Execution state supports the A64 instruction set. It holds addresses in 64-bit +registers and allows instructions in the base instruction set to use 64-bit +registers for their processing. + +The AArch32 Execution state is a 32-bit Execution state that preserves +backwards compatibility with the Armv7-A architecture, enhancing that profile +so that it can support some features included in the AArch64 state. It supports +the T32 and A32 instruction sets. Follow the +[link](https://developer.arm.com/Architectures/A-Profile%20Architecture) +for more information. + +## Arm_AARCH64 port + +This port adds support for Armv8-A architecture AArch64 execution state. +This port is generic and can be used as a starting point for Armv8-A +application processors. + +* Arm_AARCH64 + * Memory mapped interace to access Arm GIC registers diff --git a/portable/GCC/ARM_CA53_64_BIT/port.c b/portable/GCC/Arm_AARCH64/port.c similarity index 100% rename from portable/GCC/ARM_CA53_64_BIT/port.c rename to portable/GCC/Arm_AARCH64/port.c diff --git a/portable/GCC/ARM_CA53_64_BIT/portASM.S b/portable/GCC/Arm_AARCH64/portASM.S similarity index 100% rename from portable/GCC/ARM_CA53_64_BIT/portASM.S rename to portable/GCC/Arm_AARCH64/portASM.S diff --git a/portable/GCC/ARM_CA53_64_BIT/portmacro.h b/portable/GCC/Arm_AARCH64/portmacro.h similarity index 100% rename from portable/GCC/ARM_CA53_64_BIT/portmacro.h rename to portable/GCC/Arm_AARCH64/portmacro.h diff --git a/portable/GCC/Arm_AARCH64_SRE/README.md b/portable/GCC/Arm_AARCH64_SRE/README.md new file mode 100644 index 00000000000..0b2e0e4853a --- /dev/null +++ b/portable/GCC/Arm_AARCH64_SRE/README.md @@ -0,0 +1,23 @@ +# Armv8-A architecture support + +The Armv8-A architecture introduces the ability to use 64-bit and 32-bit +Execution states, known as AArch64 and AArch32 respectively. The AArch64 +Execution state supports the A64 instruction set. It holds addresses in 64-bit +registers and allows instructions in the base instruction set to use 64-bit +registers for their processing. + +The AArch32 Execution state is a 32-bit Execution state that preserves +backwards compatibility with the Armv7-A architecture, enhancing that profile +so that it can support some features included in the AArch64 state. It supports +the T32 and A32 instruction sets. Follow the +[link](https://developer.arm.com/Architectures/A-Profile%20Architecture) +for more information. + +## Arm_AARCH64_SRE port + +This port adds support for Armv8-A architecture AArch64 execution state. +This port is generic and can be used as a starting point for Armv8-A +application processors. + +* Arm_AARCH64_SRE + * System Register interace to access Arm GIC registers diff --git a/portable/GCC/ARM_CA53_64_BIT_SRE/port.c b/portable/GCC/Arm_AARCH64_SRE/port.c similarity index 100% rename from portable/GCC/ARM_CA53_64_BIT_SRE/port.c rename to portable/GCC/Arm_AARCH64_SRE/port.c diff --git a/portable/GCC/ARM_CA53_64_BIT_SRE/portASM.S b/portable/GCC/Arm_AARCH64_SRE/portASM.S similarity index 100% rename from portable/GCC/ARM_CA53_64_BIT_SRE/portASM.S rename to portable/GCC/Arm_AARCH64_SRE/portASM.S diff --git a/portable/GCC/ARM_CA53_64_BIT_SRE/portmacro.h b/portable/GCC/Arm_AARCH64_SRE/portmacro.h similarity index 100% rename from portable/GCC/ARM_CA53_64_BIT_SRE/portmacro.h rename to portable/GCC/Arm_AARCH64_SRE/portmacro.h