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Update Zynq Ultrascale port for V4.x and Clean up (#1187)
* Update Zynq Ultrascale port for V4.x This is basically a merge of the previous port, the Zynq7000 port and the port suggested by Pete Bone <[email protected]>. * Use MAC hash table for IPv4 LLMNR This is how it is supposed to be used. Also the set of the multi-cast hash enable bit was missing. * Use XEmacPs_DMABLengthUpdate() API The same effect can be achieved but the code is simpler. * Remove Zynq7000 support from Ultrascale port There are already a lot of differences between Zynq and xilinx_ultrascale port, so there is no need to keep compatibility. * Add x_emac_map to xilinx_ultrascale port This map makes sure the correct interrupt id is registered in the interrupt controller. E.g. 'XPAR_XEMACPS_0_BASEADDR' is Canonical for the first interface and can be mapped to any of the GEMs. 'XPAR_XEMACPS_0_INTR' on the other hand is fixed to GEM0. This is why this mapping is needed. * Add Micrel PHY support to xilinx_ultrascale port Authored-by: Pete Bone <[email protected] > * Fix Zynq7000 EMAC MAC address setup Set solicited-node addresses independent of LLMNR. For mDNS set IPv4/6 MAC depending on ipconfigUSE_IPv6. * Uncrustify * Fix CI spelling errors * Fix IPv4/6 preprocessor logic in Zynq/Ultrascale port * Add missing return in xilinx_ultrascale/NetworkInterface.c Co-authored-by: ActoryOu <[email protected]> --------- Co-authored-by: Tony Josi <[email protected]> Co-authored-by: ActoryOu <[email protected]>
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