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clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] acc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + acc <= 16'b0; + end else begin + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, + input wire reset, + input wire jump, + input wire [15:0] jump_addr, + output reg [15:0] pc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register + module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [2:0] opcode, + input wire [15:0] operand1, + input wire [15:0] operand2, + output reg [15:0] result +); + +always @(*) begin + case (opcode) + 3'b000: result = operand1 + operand2; // Addition + 3'b001: result = operand1 - operand2; // Subtraction + 3'b010: result = operand1 & operand2; // Bitwise AND + 3'b011: result = operand1 | operand2; // Bitwise OR + 3'b100: result = operand1 ^ operand2; // Bitwise XOR + default: result = 16'b0; // Default case + endcase +end + +endmodule + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231129171140.sv b/.history/verilog files/design_20231129171140.sv new file mode 100644 index 0000000..6efe2bb --- /dev/null +++ b/.history/verilog files/design_20231129171140.sv @@ -0,0 +1,143 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] acc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + acc <= 16'b0; + end else begin + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, + input wire reset, + input wire jump, + input wire [15:0] jump_addr, + output reg [15:0] pc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register + module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [2:0] opcode, + input wire [15:0] operand1, + input wire [15:0] operand2, + output reg [15:0] result +); + +always @(*) begin + case (opcode) + 3'b000: result = operand1 + operand2; // Addition + 3'b001: result = operand1 - operand2; // Subtraction + 3'b010: result = operand1 & operand2; // Bitwise AND + 3'b011: result = operand1 | operand2; // Bitwise OR + 3'b100: result = operand1 ^ operand2; // Bitwise XOR + default: result = 16'b0; // Default case + endcase +end + +endmodule + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end +endmodule diff --git a/.history/verilog files/design_20231129171145.sv b/.history/verilog files/design_20231129171145.sv new file mode 100644 index 0000000..0afbc9f --- /dev/null +++ b/.history/verilog files/design_20231129171145.sv @@ -0,0 +1,142 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] acc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + acc <= 16'b0; + end else begin + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, + input wire reset, + input wire jump, + input wire [15:0] jump_addr, + output reg [15:0] pc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register + module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [2:0] opcode, + input wire [15:0] operand1, + input wire [15:0] operand2, + output reg [15:0] result +); + +always @(*) begin + case (opcode) + 3'b000: result = operand1 + operand2; // Addition + 3'b001: result = operand1 - operand2; // Subtraction + 3'b010: result = operand1 & operand2; // Bitwise AND + 3'b011: result = operand1 | operand2; // Bitwise OR + 3'b100: result = operand1 ^ operand2; // Bitwise XOR + default: result = 16'b0; // Default case + endcase +end +endmodule + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end +endmodule diff --git a/.history/verilog files/design_20231129171148.sv b/.history/verilog files/design_20231129171148.sv new file mode 100644 index 0000000..ba643d9 --- /dev/null +++ b/.history/verilog files/design_20231129171148.sv @@ -0,0 +1,141 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] acc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + acc <= 16'b0; + end else begin + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, + input wire reset, + input wire jump, + input wire [15:0] jump_addr, + output reg [15:0] pc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register + module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [2:0] opcode, + input wire [15:0] operand1, + input wire [15:0] operand2, + output reg [15:0] result +); + +always @(*) begin + case (opcode) + 3'b000: result = operand1 + operand2; // Addition + 3'b001: result = operand1 - operand2; // Subtraction + 3'b010: result = operand1 & operand2; // Bitwise AND + 3'b011: result = operand1 | operand2; // Bitwise OR + 3'b100: result = operand1 ^ operand2; // Bitwise XOR + default: result = 16'b0; // Default case + endcase +end +endmodule + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end +endmodule diff --git a/.history/verilog files/design_20231129171151.sv b/.history/verilog files/design_20231129171151.sv new file mode 100644 index 0000000..6efe2bb --- /dev/null +++ b/.history/verilog files/design_20231129171151.sv @@ -0,0 +1,143 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] acc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + acc <= 16'b0; + end else begin + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, + input wire reset, + input wire jump, + input wire [15:0] jump_addr, + output reg [15:0] pc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register + module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [2:0] opcode, + input wire [15:0] operand1, + input wire [15:0] operand2, + output reg [15:0] result +); + +always @(*) begin + case (opcode) + 3'b000: result = operand1 + operand2; // Addition + 3'b001: result = operand1 - operand2; // Subtraction + 3'b010: result = operand1 & operand2; // Bitwise AND + 3'b011: result = operand1 | operand2; // Bitwise OR + 3'b100: result = operand1 ^ operand2; // Bitwise XOR + default: result = 16'b0; // Default case + endcase +end + +endmodule + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end +endmodule diff --git a/.history/verilog files/design_20231129171153.sv b/.history/verilog files/design_20231129171153.sv new file mode 100644 index 0000000..8c38235 --- /dev/null +++ b/.history/verilog files/design_20231129171153.sv @@ -0,0 +1,144 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] acc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + acc <= 16'b0; + end else begin + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, + input wire reset, + input wire jump, + input wire [15:0] jump_addr, + output reg [15:0] pc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register + module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [2:0] opcode, + input wire [15:0] operand1, + input wire [15:0] operand2, + output reg [15:0] result +); + +always @(*) begin + case (opcode) + 3'b000: result = operand1 + operand2; // Addition + 3'b001: result = operand1 - operand2; // Subtraction + 3'b010: result = operand1 & operand2; // Bitwise AND + 3'b011: result = operand1 | operand2; // Bitwise OR + 3'b100: result = operand1 ^ operand2; // Bitwise XOR + default: result = 16'b0; // Default case + endcase +end + +endmodule + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231129171155.sv b/.history/verilog files/design_20231129171155.sv new file mode 100644 index 0000000..01d0552 --- /dev/null +++ b/.history/verilog files/design_20231129171155.sv @@ -0,0 +1,144 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] acc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + acc <= 16'b0; + end else begin + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, + input wire reset, + input wire jump, + input wire [15:0] jump_addr, + output reg [15:0] pc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register + module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [2:0] opcode, + input wire [15:0] operand1, + input wire [15:0] operand2, + output reg [15:0] result +); + +always @(*) begin + case (opcode) + 3'b000: result = operand1 + operand2; // Addition + 3'b001: result = operand1 - operand2; // Subtraction + 3'b010: result = operand1 & operand2; // Bitwise AND + 3'b011: result = operand1 | operand2; // Bitwise OR + 3'b100: result = operand1 ^ operand2; // Bitwise XOR + default: result = 16'b0; // Default case + endcase +end + +endmodule + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231129171200.sv b/.history/verilog files/design_20231129171200.sv new file mode 100644 index 0000000..422f03f --- /dev/null +++ b/.history/verilog files/design_20231129171200.sv @@ -0,0 +1,144 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] acc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + acc <= 16'b0; + end else begin + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, + input wire reset, + input wire jump, + input wire [15:0] jump_addr, + output reg [15:0] pc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [2:0] opcode, + input wire [15:0] operand1, + input wire [15:0] operand2, + output reg [15:0] result +); + +always @(*) begin + case (opcode) + 3'b000: result = operand1 + operand2; // Addition + 3'b001: result = operand1 - operand2; // Subtraction + 3'b010: result = operand1 & operand2; // Bitwise AND + 3'b011: result = operand1 | operand2; // Bitwise OR + 3'b100: result = operand1 ^ operand2; // Bitwise XOR + default: result = 16'b0; // Default case + endcase +end + +endmodule + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231129171201.sv b/.history/verilog files/design_20231129171201.sv new file mode 100644 index 0000000..a251b58 --- /dev/null +++ b/.history/verilog files/design_20231129171201.sv @@ -0,0 +1,144 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] acc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + acc <= 16'b0; + end else begin + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, + input wire reset, + input wire jump, + input wire [15:0] jump_addr, + output reg [15:0] pc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [2:0] opcode, + input wire [15:0] operand1, + input wire [15:0] operand2, + output reg [15:0] result +); + +always @(*) begin + case (opcode) + 3'b000: result = operand1 + operand2; // Addition + 3'b001: result = operand1 - operand2; // Subtraction + 3'b010: result = operand1 & operand2; // Bitwise AND + 3'b011: result = operand1 | operand2; // Bitwise OR + 3'b100: result = operand1 ^ operand2; // Bitwise XOR + default: result = 16'b0; // Default case + endcase +end + +endmodule + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133156.sv b/.history/verilog files/design_20231130133156.sv new file mode 100644 index 0000000..6bb2a0b --- /dev/null +++ b/.history/verilog files/design_20231130133156.sv @@ -0,0 +1,159 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] acc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + acc <= 16'b0; + end else begin + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, + input wire reset, + input wire jump, + input wire [15:0] jump_addr, + output reg [15:0] pc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +/* ALU Arithmetic and Logic Operations +---------------------------------------------------------------------- +|ALU_Sel| ALU Operation +---------------------------------------------------------------------- +| 0000 | ALU_Out = A + B; +---------------------------------------------------------------------- +| 0001 | ALU_Out = A - B; +---------------------------------------------------------------------- +| 0010 | ALU_Out = A * B; +---------------------------------------------------------------------- +| 0011 | ALU_Out = A / B; +---------------------------------------------------------------------- +| 0100 | ALU_Out = A << 1; +---------------------------------------------------------------------- +| 0101 | ALU_Out = A >> 1; +---------------------------------------------------------------------- +| 0110 | ALU_Out = A rotated left by 1; +---------------------------------------------------------------------- +| 0111 | ALU_Out = A rotated right by 1; +---------------------------------------------------------------------- +| 1000 | ALU_Out = A and B; +---------------------------------------------------------------------- +| 1001 | ALU_Out = A or B; +---------------------------------------------------------------------- +| 1010 | ALU_Out = A xor B; +---------------------------------------------------------------------- +| 1011 | ALU_Out = A nor B; +---------------------------------------------------------------------- +| 1100 | ALU_Out = A nand B; +---------------------------------------------------------------------- +| 1101 | ALU_Out = A xnor B; +---------------------------------------------------------------------- +| 1110 | ALU_Out = 1 if A>B else 0; +---------------------------------------------------------------------- +| 1111 | ALU_Out = 1 if A=B else 0; + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133201.sv b/.history/verilog files/design_20231130133201.sv new file mode 100644 index 0000000..a251b58 --- /dev/null +++ b/.history/verilog files/design_20231130133201.sv @@ -0,0 +1,144 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] acc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + acc <= 16'b0; + end else begin + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, + input wire reset, + input wire jump, + input wire [15:0] jump_addr, + output reg [15:0] pc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [2:0] opcode, + input wire [15:0] operand1, + input wire [15:0] operand2, + output reg [15:0] result +); + +always @(*) begin + case (opcode) + 3'b000: result = operand1 + operand2; // Addition + 3'b001: result = operand1 - operand2; // Subtraction + 3'b010: result = operand1 & operand2; // Bitwise AND + 3'b011: result = operand1 | operand2; // Bitwise OR + 3'b100: result = operand1 ^ operand2; // Bitwise XOR + default: result = 16'b0; // Default case + endcase +end + +endmodule + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133211.sv b/.history/verilog files/design_20231130133211.sv new file mode 100644 index 0000000..fdccbec --- /dev/null +++ b/.history/verilog files/design_20231130133211.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] acc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + acc <= 16'b0; + end else begin + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, + input wire reset, + input wire jump, + input wire [15:0] jump_addr, + output reg [15:0] pc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Increase the size of opcode to 4 bits + input wire [15:0] operand1, + input wire [15:0] operand2, + output reg [15:0] result +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133219.sv b/.history/verilog files/design_20231130133219.sv new file mode 100644 index 0000000..1dad8d9 --- /dev/null +++ b/.history/verilog files/design_20231130133219.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] acc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + acc <= 16'b0; + end else begin + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, + input wire reset, + input wire jump, + input wire [15:0] jump_addr, + output reg [15:0] pc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, + input wire [15:0] operand1, + input wire [15:0] operand2, + output reg [15:0] result +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133223.sv b/.history/verilog files/design_20231130133223.sv new file mode 100644 index 0000000..69281ee --- /dev/null +++ b/.history/verilog files/design_20231130133223.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] acc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + acc <= 16'b0; + end else begin + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, + input wire reset, + input wire jump, + input wire [15:0] jump_addr, + output reg [15:0] pc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code s + input wire [15:0] operand1, + input wire [15:0] operand2, + output reg [15:0] result +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133225.sv b/.history/verilog files/design_20231130133225.sv new file mode 100644 index 0000000..fbf0323 --- /dev/null +++ b/.history/verilog files/design_20231130133225.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] acc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + acc <= 16'b0; + end else begin + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, + input wire reset, + input wire jump, + input wire [15:0] jump_addr, + output reg [15:0] pc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size + input wire [15:0] operand1, + input wire [15:0] operand2, + output reg [15:0] result +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133226.sv b/.history/verilog files/design_20231130133226.sv new file mode 100644 index 0000000..1f81915 --- /dev/null +++ b/.history/verilog files/design_20231130133226.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] acc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + acc <= 16'b0; + end else begin + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, + input wire reset, + input wire jump, + input wire [15:0] jump_addr, + output reg [15:0] pc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, + input wire [15:0] operand2, + output reg [15:0] result +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133227.sv b/.history/verilog files/design_20231130133227.sv new file mode 100644 index 0000000..743c25c --- /dev/null +++ b/.history/verilog files/design_20231130133227.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] acc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + acc <= 16'b0; + end else begin + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, + input wire reset, + input wire jump, + input wire [15:0] jump_addr, + output reg [15:0] pc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // + input wire [15:0] operand2, + output reg [15:0] result +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133231.sv b/.history/verilog files/design_20231130133231.sv new file mode 100644 index 0000000..b057873 --- /dev/null +++ b/.history/verilog files/design_20231130133231.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] acc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + acc <= 16'b0; + end else begin + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, + input wire reset, + input wire jump, + input wire [15:0] jump_addr, + output reg [15:0] pc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // + output reg [15:0] result +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133232.sv b/.history/verilog files/design_20231130133232.sv new file mode 100644 index 0000000..ce7e549 --- /dev/null +++ b/.history/verilog files/design_20231130133232.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] acc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + acc <= 16'b0; + end else begin + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, + input wire reset, + input wire jump, + input wire [15:0] jump_addr, + output reg [15:0] pc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133235.sv b/.history/verilog files/design_20231130133235.sv new file mode 100644 index 0000000..5e22ade --- /dev/null +++ b/.history/verilog files/design_20231130133235.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] acc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + acc <= 16'b0; + end else begin + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, + input wire reset, + input wire jump, + input wire [15:0] jump_addr, + output reg [15:0] pc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133304.sv b/.history/verilog files/design_20231130133304.sv new file mode 100644 index 0000000..3074337 --- /dev/null +++ b/.history/verilog files/design_20231130133304.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // + input wire reset, + input wire [15:0] data_in, + output reg [15:0] acc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + acc <= 16'b0; + end else begin + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, + input wire reset, + input wire jump, + input wire [15:0] jump_addr, + output reg [15:0] pc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133305.sv b/.history/verilog files/design_20231130133305.sv new file mode 100644 index 0000000..91148a3 --- /dev/null +++ b/.history/verilog files/design_20231130133305.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, + input wire [15:0] data_in, + output reg [15:0] acc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + acc <= 16'b0; + end else begin + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, + input wire reset, + input wire jump, + input wire [15:0] jump_addr, + output reg [15:0] pc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133308.sv b/.history/verilog files/design_20231130133308.sv new file mode 100644 index 0000000..229d11f --- /dev/null +++ b/.history/verilog files/design_20231130133308.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, + output reg [15:0] acc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + acc <= 16'b0; + end else begin + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, + input wire reset, + input wire jump, + input wire [15:0] jump_addr, + output reg [15:0] pc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133310.sv b/.history/verilog files/design_20231130133310.sv new file mode 100644 index 0000000..be5f583 --- /dev/null +++ b/.history/verilog files/design_20231130133310.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input + output reg [15:0] acc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + acc <= 16'b0; + end else begin + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, + input wire reset, + input wire jump, + input wire [15:0] jump_addr, + output reg [15:0] pc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133312.sv b/.history/verilog files/design_20231130133312.sv new file mode 100644 index 0000000..043117d --- /dev/null +++ b/.history/verilog files/design_20231130133312.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + acc <= 16'b0; + end else begin + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, + input wire reset, + input wire jump, + input wire [15:0] jump_addr, + output reg [15:0] pc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133315.sv b/.history/verilog files/design_20231130133315.sv new file mode 100644 index 0000000..5e8a061 --- /dev/null +++ b/.history/verilog files/design_20231130133315.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + acc <= 16'b0; + end else begin + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, + input wire reset, + input wire jump, + input wire [15:0] jump_addr, + output reg [15:0] pc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133317.sv b/.history/verilog files/design_20231130133317.sv new file mode 100644 index 0000000..dd532a2 --- /dev/null +++ b/.history/verilog files/design_20231130133317.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // + acc <= 16'b0; + end else begin + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, + input wire reset, + input wire jump, + input wire [15:0] jump_addr, + output reg [15:0] pc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133318.sv b/.history/verilog files/design_20231130133318.sv new file mode 100644 index 0000000..dc0e9c3 --- /dev/null +++ b/.history/verilog files/design_20231130133318.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // Reset the accumulator + acc <= 16'b0; + end else begin + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, + input wire reset, + input wire jump, + input wire [15:0] jump_addr, + output reg [15:0] pc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133324.sv b/.history/verilog files/design_20231130133324.sv new file mode 100644 index 0000000..929258a --- /dev/null +++ b/.history/verilog files/design_20231130133324.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If + acc <= 16'b0; + end else begin + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, + input wire reset, + input wire jump, + input wire [15:0] jump_addr, + output reg [15:0] pc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133328.sv b/.history/verilog files/design_20231130133328.sv new file mode 100644 index 0000000..8d0b1a3 --- /dev/null +++ b/.history/verilog files/design_20231130133328.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, + input wire reset, + input wire jump, + input wire [15:0] jump_addr, + output reg [15:0] pc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133331.sv b/.history/verilog files/design_20231130133331.sv new file mode 100644 index 0000000..296eb5e --- /dev/null +++ b/.history/verilog files/design_20231130133331.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, + input wire reset, + input wire jump, + input wire [15:0] jump_addr, + output reg [15:0] pc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133333.sv b/.history/verilog files/design_20231130133333.sv new file mode 100644 index 0000000..dc066c3 --- /dev/null +++ b/.history/verilog files/design_20231130133333.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, + input wire reset, + input wire jump, + input wire [15:0] jump_addr, + output reg [15:0] pc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133336.sv b/.history/verilog files/design_20231130133336.sv new file mode 100644 index 0000000..d36683d --- /dev/null +++ b/.history/verilog files/design_20231130133336.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin // + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, + input wire reset, + input wire jump, + input wire [15:0] jump_addr, + output reg [15:0] pc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133340.sv b/.history/verilog files/design_20231130133340.sv new file mode 100644 index 0000000..3ab6376 --- /dev/null +++ b/.history/verilog files/design_20231130133340.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin // Synchronous reset + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, + input wire reset, + input wire jump, + input wire [15:0] jump_addr, + output reg [15:0] pc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133346.sv b/.history/verilog files/design_20231130133346.sv new file mode 100644 index 0000000..f12e314 --- /dev/null +++ b/.history/verilog files/design_20231130133346.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin // fun + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, + input wire reset, + input wire jump, + input wire [15:0] jump_addr, + output reg [15:0] pc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133350.sv b/.history/verilog files/design_20231130133350.sv new file mode 100644 index 0000000..dc066c3 --- /dev/null +++ b/.history/verilog files/design_20231130133350.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, + input wire reset, + input wire jump, + input wire [15:0] jump_addr, + output reg [15:0] pc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133401.sv b/.history/verilog files/design_20231130133401.sv new file mode 100644 index 0000000..acb6c26 --- /dev/null +++ b/.history/verilog files/design_20231130133401.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address + output reg [15:0] pc +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133403.sv b/.history/verilog files/design_20231130133403.sv new file mode 100644 index 0000000..ba8a56d --- /dev/null +++ b/.history/verilog files/design_20231130133403.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133406.sv b/.history/verilog files/design_20231130133406.sv new file mode 100644 index 0000000..dee7116 --- /dev/null +++ b/.history/verilog files/design_20231130133406.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133423.sv b/.history/verilog files/design_20231130133423.sv new file mode 100644 index 0000000..042386b --- /dev/null +++ b/.history/verilog files/design_20231130133423.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133424.sv b/.history/verilog files/design_20231130133424.sv new file mode 100644 index 0000000..3c1d0bf --- /dev/null +++ b/.history/verilog files/design_20231130133424.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133428.sv b/.history/verilog files/design_20231130133428.sv new file mode 100644 index 0000000..4770c4d --- /dev/null +++ b/.history/verilog files/design_20231130133428.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133430.sv b/.history/verilog files/design_20231130133430.sv new file mode 100644 index 0000000..45ff827 --- /dev/null +++ b/.history/verilog files/design_20231130133430.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133432.sv b/.history/verilog files/design_20231130133432.sv new file mode 100644 index 0000000..f44e998 --- /dev/null +++ b/.history/verilog files/design_20231130133432.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133433.sv b/.history/verilog files/design_20231130133433.sv new file mode 100644 index 0000000..08079d2 --- /dev/null +++ b/.history/verilog files/design_20231130133433.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133438.sv b/.history/verilog files/design_20231130133438.sv new file mode 100644 index 0000000..b6220e4 --- /dev/null +++ b/.history/verilog files/design_20231130133438.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133441.sv b/.history/verilog files/design_20231130133441.sv new file mode 100644 index 0000000..47216ae --- /dev/null +++ b/.history/verilog files/design_20231130133441.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133444.sv b/.history/verilog files/design_20231130133444.sv new file mode 100644 index 0000000..b6220e4 --- /dev/null +++ b/.history/verilog files/design_20231130133444.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133456.sv b/.history/verilog files/design_20231130133456.sv new file mode 100644 index 0000000..88b7e46 --- /dev/null +++ b/.history/verilog files/design_20231130133456.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133458.sv b/.history/verilog files/design_20231130133458.sv new file mode 100644 index 0000000..eb350d0 --- /dev/null +++ b/.history/verilog files/design_20231130133458.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133503.sv b/.history/verilog files/design_20231130133503.sv new file mode 100644 index 0000000..9d4fa37 --- /dev/null +++ b/.history/verilog files/design_20231130133503.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, + input wire reset, + input wire [15:0] addr_in, + output reg [15:0] addr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133512.sv b/.history/verilog files/design_20231130133512.sv new file mode 100644 index 0000000..c8c1960 --- /dev/null +++ b/.history/verilog files/design_20231130133512.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133518.sv b/.history/verilog files/design_20231130133518.sv new file mode 100644 index 0000000..c15bea0 --- /dev/null +++ b/.history/verilog files/design_20231130133518.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133523.sv b/.history/verilog files/design_20231130133523.sv new file mode 100644 index 0000000..878a5f0 --- /dev/null +++ b/.history/verilog files/design_20231130133523.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133524.sv b/.history/verilog files/design_20231130133524.sv new file mode 100644 index 0000000..e1aefb8 --- /dev/null +++ b/.history/verilog files/design_20231130133524.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, + input wire reset, + input wire [15:0] data_in, + output reg [15:0] data_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133541.sv b/.history/verilog files/design_20231130133541.sv new file mode 100644 index 0000000..12bf7ce --- /dev/null +++ b/.history/verilog files/design_20231130133541.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133543.sv b/.history/verilog files/design_20231130133543.sv new file mode 100644 index 0000000..b80638f --- /dev/null +++ b/.history/verilog files/design_20231130133543.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133544.sv b/.history/verilog files/design_20231130133544.sv new file mode 100644 index 0000000..db38b11 --- /dev/null +++ b/.history/verilog files/design_20231130133544.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133546.sv b/.history/verilog files/design_20231130133546.sv new file mode 100644 index 0000000..ffea1a4 --- /dev/null +++ b/.history/verilog files/design_20231130133546.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133547.sv b/.history/verilog files/design_20231130133547.sv new file mode 100644 index 0000000..cb862e1 --- /dev/null +++ b/.history/verilog files/design_20231130133547.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, + input wire reset, + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133554.sv b/.history/verilog files/design_20231130133554.sv new file mode 100644 index 0000000..78e7b45 --- /dev/null +++ b/.history/verilog files/design_20231130133554.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, + output reg [15:0] instr_out +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133558.sv b/.history/verilog files/design_20231130133558.sv new file mode 100644 index 0000000..624611a --- /dev/null +++ b/.history/verilog files/design_20231130133558.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133601.sv b/.history/verilog files/design_20231130133601.sv new file mode 100644 index 0000000..f38e2b3 --- /dev/null +++ b/.history/verilog files/design_20231130133601.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133602.sv b/.history/verilog files/design_20231130133602.sv new file mode 100644 index 0000000..ec8b1eb --- /dev/null +++ b/.history/verilog files/design_20231130133602.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133610.sv b/.history/verilog files/design_20231130133610.sv new file mode 100644 index 0000000..fe9a8ad --- /dev/null +++ b/.history/verilog files/design_20231130133610.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; // Reset the instruction output + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133614.sv b/.history/verilog files/design_20231130133614.sv new file mode 100644 index 0000000..ec8b1eb --- /dev/null +++ b/.history/verilog files/design_20231130133614.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133616.sv b/.history/verilog files/design_20231130133616.sv new file mode 100644 index 0000000..c14cd0e --- /dev/null +++ b/.history/verilog files/design_20231130133616.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133619.sv b/.history/verilog files/design_20231130133619.sv new file mode 100644 index 0000000..865a5b4 --- /dev/null +++ b/.history/verilog files/design_20231130133619.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // Otherwise, set the instruction output to the instruction input + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133625.sv b/.history/verilog files/design_20231130133625.sv new file mode 100644 index 0000000..f690e11 --- /dev/null +++ b/.history/verilog files/design_20231130133625.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // Otherwise, set the instruction output to the instruction input + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133626.sv b/.history/verilog files/design_20231130133626.sv new file mode 100644 index 0000000..c433a27 --- /dev/null +++ b/.history/verilog files/design_20231130133626.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // Otherwise, set the instruction output to the instruction input + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case is to set the result to 0 + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133629.sv b/.history/verilog files/design_20231130133629.sv new file mode 100644 index 0000000..8cf1f2f --- /dev/null +++ b/.history/verilog files/design_20231130133629.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // Otherwise, set the instruction output to the instruction input + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case is to set the result to 0 + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, // + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133630.sv b/.history/verilog files/design_20231130133630.sv new file mode 100644 index 0000000..4c3e901 --- /dev/null +++ b/.history/verilog files/design_20231130133630.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // Otherwise, set the instruction output to the instruction input + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case is to set the result to 0 + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, // Clock + input wire [15:0] addr, + input wire [15:0] data_in, + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133637.sv b/.history/verilog files/design_20231130133637.sv new file mode 100644 index 0000000..705763a --- /dev/null +++ b/.history/verilog files/design_20231130133637.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // Otherwise, set the instruction output to the instruction input + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case is to set the result to 0 + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, // Clock + input wire [15:0] addr, // Address (16 bits) + input wire [15:0] data_in, // + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133639.sv b/.history/verilog files/design_20231130133639.sv new file mode 100644 index 0000000..c9e8275 --- /dev/null +++ b/.history/verilog files/design_20231130133639.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // Otherwise, set the instruction output to the instruction input + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case is to set the result to 0 + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, // Clock + input wire [15:0] addr, // Address (16 bits) + input wire [15:0] data_in, // Data input (16 bits) + input wire write_enable, + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133641.sv b/.history/verilog files/design_20231130133641.sv new file mode 100644 index 0000000..34c5b42 --- /dev/null +++ b/.history/verilog files/design_20231130133641.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // Otherwise, set the instruction output to the instruction input + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case is to set the result to 0 + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, // Clock + input wire [15:0] addr, // Address (16 bits) + input wire [15:0] data_in, // Data input (16 bits) + input wire write_enable, // Write enable + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133643.sv b/.history/verilog files/design_20231130133643.sv new file mode 100644 index 0000000..3bb07a3 --- /dev/null +++ b/.history/verilog files/design_20231130133643.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // Otherwise, set the instruction output to the instruction input + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case is to set the result to 0 + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, // Clock + input wire [15:0] addr, // Address (16 bits) + input wire [15:0] data_in, // Data input (16 bits) + input wire write_enable, // Write enable + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133646.sv b/.history/verilog files/design_20231130133646.sv new file mode 100644 index 0000000..b426efb --- /dev/null +++ b/.history/verilog files/design_20231130133646.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // Otherwise, set the instruction output to the instruction input + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case is to set the result to 0 + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, // Clock + input wire [15:0] addr, // Address (16 bits) + input wire [15:0] data_in, // Data input (16 bits) + input wire write_enable, // Write enable (1 bit) + output reg [15:0] data_out +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133648.sv b/.history/verilog files/design_20231130133648.sv new file mode 100644 index 0000000..e9669f7 --- /dev/null +++ b/.history/verilog files/design_20231130133648.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // Otherwise, set the instruction output to the instruction input + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case is to set the result to 0 + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, // Clock + input wire [15:0] addr, // Address (16 bits) + input wire [15:0] data_in, // Data input (16 bits) + input wire write_enable, // Write enable (1 bit) + output reg [15:0] data_out // Data output (16 bits) +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin + // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133657.sv b/.history/verilog files/design_20231130133657.sv new file mode 100644 index 0000000..9a7b7b6 --- /dev/null +++ b/.history/verilog files/design_20231130133657.sv @@ -0,0 +1,155 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // Otherwise, set the instruction output to the instruction input + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case is to set the result to 0 + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, // Clock + input wire [15:0] addr, // Address (16 bits) + input wire [15:0] data_in, // Data input (16 bits) + input wire write_enable, // Write enable (1 bit) + output reg [15:0] data_out // Data output (16 bits) +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin + // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133700.sv b/.history/verilog files/design_20231130133700.sv new file mode 100644 index 0000000..3a30f1f --- /dev/null +++ b/.history/verilog files/design_20231130133700.sv @@ -0,0 +1,154 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // Otherwise, set the instruction output to the instruction input + instr_out <= instr_in; + end +end + +endmodule + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case is to set the result to 0 + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, // Clock + input wire [15:0] addr, // Address (16 bits) + input wire [15:0] data_in, // Data input (16 bits) + input wire write_enable, // Write enable (1 bit) + output reg [15:0] data_out // Data output (16 bits) +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133707.sv b/.history/verilog files/design_20231130133707.sv new file mode 100644 index 0000000..18eb4a2 --- /dev/null +++ b/.history/verilog files/design_20231130133707.sv @@ -0,0 +1,155 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // Otherwise, set the instruction output to the instruction input + instr_out <= instr_in; + end +end + +endmodule + + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case is to set the result to 0 + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, // Clock + input wire [15:0] addr, // Address (16 bits) + input wire [15:0] data_in, // Data input (16 bits) + input wire write_enable, // Write enable (1 bit) + output reg [15:0] data_out // Data output (16 bits) +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133710.sv b/.history/verilog files/design_20231130133710.sv new file mode 100644 index 0000000..595d6b5 --- /dev/null +++ b/.history/verilog files/design_20231130133710.sv @@ -0,0 +1,156 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // Otherwise, set the instruction output to the instruction input + instr_out <= instr_in; + end +end + +endmodule + + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case is to set the result to 0 + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, // Clock + input wire [15:0] addr, // Address (16 bits) + input wire [15:0] data_in, // Data input (16 bits) + input wire write_enable, // Write enable (1 bit) + output reg [15:0] data_out // Data output (16 bits) +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133712.sv b/.history/verilog files/design_20231130133712.sv new file mode 100644 index 0000000..2ec01c7 --- /dev/null +++ b/.history/verilog files/design_20231130133712.sv @@ -0,0 +1,157 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // Otherwise, set the instruction output to the instruction input + instr_out <= instr_in; + end +end + +endmodule + + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case is to set the result to 0 + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, // Clock + input wire [15:0] addr, // Address (16 bits) + input wire [15:0] data_in, // Data input (16 bits) + input wire write_enable, // Write enable (1 bit) + output reg [15:0] data_out // Data output (16 bits) +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133714.sv b/.history/verilog files/design_20231130133714.sv new file mode 100644 index 0000000..b923c3e --- /dev/null +++ b/.history/verilog files/design_20231130133714.sv @@ -0,0 +1,158 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // Otherwise, set the instruction output to the instruction input + instr_out <= instr_in; + end +end + +endmodule + + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case is to set the result to 0 + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, // Clock + input wire [15:0] addr, // Address (16 bits) + input wire [15:0] data_in, // Data input (16 bits) + input wire write_enable, // Write enable (1 bit) + output reg [15:0] data_out // Data output (16 bits) +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133717.sv b/.history/verilog files/design_20231130133717.sv new file mode 100644 index 0000000..0538987 --- /dev/null +++ b/.history/verilog files/design_20231130133717.sv @@ -0,0 +1,159 @@ +`timescale 1ns / 1ps + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // Otherwise, set the instruction output to the instruction input + instr_out <= instr_in; + end +end + +endmodule + + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case is to set the result to 0 + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, // Clock + input wire [15:0] addr, // Address (16 bits) + input wire [15:0] data_in, // Data input (16 bits) + input wire write_enable, // Write enable (1 bit) + output reg [15:0] data_out // Data output (16 bits) +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133721.sv b/.history/verilog files/design_20231130133721.sv new file mode 100644 index 0000000..0f10106 --- /dev/null +++ b/.history/verilog files/design_20231130133721.sv @@ -0,0 +1,159 @@ +`timescale 1ns / 1ps / + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // Otherwise, set the instruction output to the instruction input + instr_out <= instr_in; + end +end + +endmodule + + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case is to set the result to 0 + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, // Clock + input wire [15:0] addr, // Address (16 bits) + input wire [15:0] data_in, // Data input (16 bits) + input wire write_enable, // Write enable (1 bit) + output reg [15:0] data_out // Data output (16 bits) +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133722.sv b/.history/verilog files/design_20231130133722.sv new file mode 100644 index 0000000..3ecfff0 --- /dev/null +++ b/.history/verilog files/design_20231130133722.sv @@ -0,0 +1,159 @@ +`timescale 1ns / 1ps // + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // Otherwise, set the instruction output to the instruction input + instr_out <= instr_in; + end +end + +endmodule + + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case is to set the result to 0 + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, // Clock + input wire [15:0] addr, // Address (16 bits) + input wire [15:0] data_in, // Data input (16 bits) + input wire write_enable, // Write enable (1 bit) + output reg [15:0] data_out // Data output (16 bits) +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130133724.sv b/.history/verilog files/design_20231130133724.sv new file mode 100644 index 0000000..c922416 --- /dev/null +++ b/.history/verilog files/design_20231130133724.sv @@ -0,0 +1,159 @@ +`timescale 1ns / 1ps // Set the timescale to 1 nanosecond / 1 picosecond + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // Otherwise, set the instruction output to the instruction input + instr_out <= instr_in; + end +end + +endmodule + + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case is to set the result to 0 + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, // Clock + input wire [15:0] addr, // Address (16 bits) + input wire [15:0] data_in, // Data input (16 bits) + input wire write_enable, // Write enable (1 bit) + output reg [15:0] data_out // Data output (16 bits) +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/testbench_20231129171011.sv b/.history/verilog files/testbench_20231129171011.sv new file mode 100644 index 0000000..e69de29 diff --git a/.history/verilog files/testbench_20231129171102.sv b/.history/verilog files/testbench_20231129171102.sv new file mode 100644 index 0000000..88576ef --- /dev/null +++ b/.history/verilog files/testbench_20231129171102.sv @@ -0,0 +1,55 @@ +// Testbench +module Testbench; + reg clk; + reg reset; + reg jump; + reg [15:0] jump_addr; + reg [15:0] data_in; + wire [15:0] acc; + wire [15:0] pc; + + // Instantiate the Accumulator and ProgramCounter + Accumulator u1 ( + .clk(clk), + .reset(reset), + .data_in(data_in), + .acc(acc) + ); + + ProgramCounter u2 ( + .clk(clk), + .reset(reset), + .jump(jump), + .jump_addr(jump_addr), + .pc(pc) + ); + + // Clock process + initial begin + clk = 0; + forever #10 clk = ~clk; + end + + // Stimulus process + initial begin + // Initialize inputs + reset = 1; + jump = 0; + jump_addr = 0; + data_in = 0; + #20 reset = 0; + #20 data_in = 16'h1234; + #20 jump = 1; jump_addr = 16'h5678; + #20 data_in = 16'h9abc; + #20 jump = 0; + #20 data_in = 16'hdef0; + #20 jump = 1; jump_addr = 16'h1234; + #20 $finish; + end + + // Monitor process + initial begin + $monitor("At time %d, data_in = %h, acc = %h, jump = %b, jump_addr = %h, pc = %h", $time, data_in, acc, jump, jump_addr, pc); + end + +endmodule \ No newline at end of file diff --git a/verilog files/design.sv b/verilog files/design.sv new file mode 100644 index 0000000..c922416 --- /dev/null +++ b/verilog files/design.sv @@ -0,0 +1,159 @@ +`timescale 1ns / 1ps // Set the timescale to 1 nanosecond / 1 picosecond + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // Otherwise, set the instruction output to the instruction input + instr_out <= instr_in; + end +end + +endmodule + + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case is to set the result to 0 + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, // Clock + input wire [15:0] addr, // Address (16 bits) + input wire [15:0] data_in, // Data input (16 bits) + input wire write_enable, // Write enable (1 bit) + output reg [15:0] data_out // Data output (16 bits) +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/verilog files/testbench.sv b/verilog files/testbench.sv new file mode 100644 index 0000000..88576ef --- /dev/null +++ b/verilog files/testbench.sv @@ -0,0 +1,55 @@ +// Testbench +module Testbench; + reg clk; + reg reset; + reg jump; + reg [15:0] jump_addr; + reg [15:0] data_in; + wire [15:0] acc; + wire [15:0] pc; + + // Instantiate the Accumulator and ProgramCounter + Accumulator u1 ( + .clk(clk), + .reset(reset), + .data_in(data_in), + .acc(acc) + ); + + ProgramCounter u2 ( + .clk(clk), + .reset(reset), + .jump(jump), + .jump_addr(jump_addr), + .pc(pc) + ); + + // Clock process + initial begin + clk = 0; + forever #10 clk = ~clk; + end + + // Stimulus process + initial begin + // Initialize inputs + reset = 1; + jump = 0; + jump_addr = 0; + data_in = 0; + #20 reset = 0; + #20 data_in = 16'h1234; + #20 jump = 1; jump_addr = 16'h5678; + #20 data_in = 16'h9abc; + #20 jump = 0; + #20 data_in = 16'hdef0; + #20 jump = 1; jump_addr = 16'h1234; + #20 $finish; + end + + // Monitor process + initial begin + $monitor("At time %d, data_in = %h, acc = %h, jump = %b, jump_addr = %h, pc = %h", $time, data_in, acc, jump, jump_addr, pc); + end + +endmodule \ No newline at end of file From 3cc3c871d3e028c56284dcfc09beb538829832e7 Mon Sep 17 00:00:00 2001 From: Michael Halpern <100871194+michaelhelper@users.noreply.github.com> Date: Thu, 30 Nov 2023 16:50:15 -0500 Subject: [PATCH 3/3] added assert test cases --- .history/verilog files/CUP_20231130142330.sv | 0 .history/verilog files/CUP_20231130142427.sv | 81 +++++ .../CUP_testbench_20231130142341.sv | 0 .../CUP_testbench_20231130142403.sv | 15 + .../CUP_testbench_20231130142411.sv | 17 + .../CUP_testbench_20231130142412.sv | 20 ++ .../CUP_testbench_20231130142416.sv | 20 ++ .../verilog files/design_20231130135157.sv | 201 ++++++++++++ .../verilog files/design_20231130135220.sv | 202 ++++++++++++ .../verilog files/design_20231130135438.sv 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.history/verilog files/testbench_20231130164958.sv diff --git a/.history/verilog files/CUP_20231130142330.sv b/.history/verilog files/CUP_20231130142330.sv new file mode 100644 index 0000000..e69de29 diff --git a/.history/verilog files/CUP_20231130142427.sv b/.history/verilog files/CUP_20231130142427.sv new file mode 100644 index 0000000..5cea244 --- /dev/null +++ b/.history/verilog files/CUP_20231130142427.sv @@ -0,0 +1,81 @@ +module CPU ( + input wire clk, + input wire reset, + inout wire [15:0] AC, // Accumulator + inout wire [15:0] M[0:16383] // Main memory +); + + // Declare the necessary registers + reg [15:0] PC; // Program Counter + reg [15:0] IR; // Instruction Register + reg [15:0] MAR; // Memory Address Register + reg [15:0] MBR; // Memory Buffer Register + + // Fetch instruction + always @(posedge clk or posedge reset) begin + if (reset) begin + PC <= 16'b0; + end else begin + MAR <= PC; + IR <= M[MAR]; + PC <= PC + 1; + end + end + + // Decode and execute instruction + always @(posedge clk or posedge reset) begin + if (reset) begin + AC <= 16'b0; + end else begin + case (IR[15:12]) // Assume the opcode is in the upper 4 bits of the instruction + 4'b0000: begin // LOAD X + MAR <= IR[11:0]; // Assume the operand is in the lower 12 bits of the instruction + MBR <= M[MAR]; + AC <= MBR; + end + 4'b0001: begin // STORE X + MAR <= IR[11:0]; + M[MAR] <= AC; + end + 4'b0010: begin // ADD X + MAR <= IR[11:0]; + MBR <= M[MAR]; + AC <= AC + MBR; + end + 4'b0011: begin // SUB X + MAR <= IR[11:0]; + MBR <= M[MAR]; + AC <= AC - MBR; + end + 4'b0100: begin // AND X + MAR <= IR[11:0]; + MBR <= M[MAR]; + AC <= AC & MBR; + end + 4'b0101: begin // OR X + MAR <= IR[11:0]; + MBR <= M[MAR]; + AC <= AC | MBR; + end + 4'b0110: begin // NOT + AC <= ~AC; + end + 4'b0111: begin // JUMP X + PC <= IR[11:0]; + end + 4'b1000: begin // JZ X + if (AC == 16'b0) begin + PC <= IR[11:0]; + end + end + 4'b1001: begin // HALT + PC <= PC - 1; + end + default: begin // NOP + // Do nothing + end + endcase + end + end + +endmodule diff --git a/.history/verilog files/CUP_testbench_20231130142341.sv b/.history/verilog files/CUP_testbench_20231130142341.sv new file mode 100644 index 0000000..e69de29 diff --git a/.history/verilog files/CUP_testbench_20231130142403.sv b/.history/verilog files/CUP_testbench_20231130142403.sv new file mode 100644 index 0000000..add8739 --- /dev/null +++ b/.history/verilog files/CUP_testbench_20231130142403.sv @@ -0,0 +1,15 @@ +initial begin + // Initialize signals + clk = 0; + reset = 1; + AC = 16'b0; + // Initialize main memory with the binary representation of the assembly program + M[0] = 16'b0000_0000_0010; // LOAD 0x2 + M[1] = 16'b0010_0000_0011; // ADD 0x3 + M[2] = 16'b0001_0000_0100; // STORE 0x4 + M[3] = 16'b1001_0000_0000; // HALT + // Initialize the rest of main memory to zero + for (integer i = 4; i < 16384; i = i + 1) begin + M[i] = 16'b0; + end +end diff --git a/.history/verilog files/CUP_testbench_20231130142411.sv b/.history/verilog files/CUP_testbench_20231130142411.sv new file mode 100644 index 0000000..a9ea629 --- /dev/null +++ b/.history/verilog files/CUP_testbench_20231130142411.sv @@ -0,0 +1,17 @@ + + +initial begin + // Initialize signals + clk = 0; + reset = 1; + AC = 16'b0; + // Initialize main memory with the binary representation of the assembly program + M[0] = 16'b0000_0000_0010; // LOAD 0x2 + M[1] = 16'b0010_0000_0011; // ADD 0x3 + M[2] = 16'b0001_0000_0100; // STORE 0x4 + M[3] = 16'b1001_0000_0000; // HALT + // Initialize the rest of main memory to zero + for (integer i = 4; i < 16384; i = i + 1) begin + M[i] = 16'b0; + end +end diff --git a/.history/verilog files/CUP_testbench_20231130142412.sv b/.history/verilog files/CUP_testbench_20231130142412.sv new file mode 100644 index 0000000..caac8cc --- /dev/null +++ b/.history/verilog files/CUP_testbench_20231130142412.sv @@ -0,0 +1,20 @@ +LOAD 0x2 +ADD 0x3 +STORE 0x4 +HALT + +initial begin + // Initialize signals + clk = 0; + reset = 1; + AC = 16'b0; + // Initialize main memory with the binary representation of the assembly program + M[0] = 16'b0000_0000_0010; // LOAD 0x2 + M[1] = 16'b0010_0000_0011; // ADD 0x3 + M[2] = 16'b0001_0000_0100; // STORE 0x4 + M[3] = 16'b1001_0000_0000; // HALT + // Initialize the rest of main memory to zero + for (integer i = 4; i < 16384; i = i + 1) begin + M[i] = 16'b0; + end +end diff --git a/.history/verilog files/CUP_testbench_20231130142416.sv b/.history/verilog files/CUP_testbench_20231130142416.sv new file mode 100644 index 0000000..7c92e82 --- /dev/null +++ b/.history/verilog files/CUP_testbench_20231130142416.sv @@ -0,0 +1,20 @@ +// LOAD 0x2 +// ADD 0x3 +// STORE 0x4 +// HALT + +initial begin + // Initialize signals + clk = 0; + reset = 1; + AC = 16'b0; + // Initialize main memory with the binary representation of the assembly program + M[0] = 16'b0000_0000_0010; // LOAD 0x2 + M[1] = 16'b0010_0000_0011; // ADD 0x3 + M[2] = 16'b0001_0000_0100; // STORE 0x4 + M[3] = 16'b1001_0000_0000; // HALT + // Initialize the rest of main memory to zero + for (integer i = 4; i < 16384; i = i + 1) begin + M[i] = 16'b0; + end +end diff --git a/.history/verilog files/design_20231130135157.sv b/.history/verilog files/design_20231130135157.sv new file mode 100644 index 0000000..1ae569d --- /dev/null +++ b/.history/verilog files/design_20231130135157.sv @@ -0,0 +1,201 @@ +`timescale 1ns / 1ps // Set the timescale to 1 nanosecond / 1 picosecond + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // Otherwise, set the instruction output to the instruction input + instr_out <= instr_in; + end +end + +endmodule + + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case is to set the result to 0 + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, // Clock + input wire [15:0] addr, // Address (16 bits) + input wire [15:0] data_in, // Data input (16 bits) + input wire write_enable, // Write enable (1 bit) + output reg [15:0] data_out // Data output (16 bits) +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule + +// Add X operation +module AddX ( + input wire clk, + input wire reset, + input wire [15:0] X, // The value to add + inout wire [15:0] AC, // Accumulator + inout wire [15:0] M[0:16383] // Main memory +); + + // Declare the necessary registers + reg [15:0] MAR; // Memory Address Register + reg [15:0] MBR; // Memory Buffer Register + + // Load X into MAR + always @(posedge clk or posedge reset) begin + if (reset) begin + MAR <= 16'b0; + end else begin + MAR <= X; + end + end + + // Load value stored at address X into MBR + always @(posedge clk or posedge reset) begin + if (reset) begin + MBR <= 16'b0; + end else begin + MBR <= M[MAR]; + end + end + + // Add value in AC with MBR value and store it back into AC + always @(posedge clk or posedge reset) begin + if (reset) begin + AC <= 16'b0; + end else begin + AC <= AC + MBR; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130135220.sv b/.history/verilog files/design_20231130135220.sv new file mode 100644 index 0000000..bc5b225 --- /dev/null +++ b/.history/verilog files/design_20231130135220.sv @@ -0,0 +1,202 @@ +`timescale 1ns / 1ps // Set the timescale to 1 nanosecond / 1 picosecond + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // Otherwise, set the instruction output to the instruction input + instr_out <= instr_in; + end +end + +endmodule + + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case is to set the result to 0 + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, // Clock + input wire [15:0] addr, // Address (16 bits) + input wire [15:0] data_in, // Data input (16 bits) + input wire write_enable, // Write enable (1 bit) + output reg [15:0] data_out // Data output (16 bits) +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule + +// Add X operation +module AddX ( + input wire clk, + input wire reset, + input wire [15:0] X, // The value to add + inout wire [15:0] AC, // Accumulator + inout wire [15:0] M[0:16383] // Main memory +); + + // Declare the necessary registers + reg [15:0] MAR; // Memory Address Register + reg [15:0] MBR; // Memory Buffer Register + + // Load X into MAR + always @(posedge clk or posedge reset) begin + if (reset) begin + MAR <= 16'b0; + end else begin + MAR <= X; + end + end + + // Load value stored at address X into MBR + always @(posedge clk or posedge reset) begin + if (reset) begin + MBR <= 16'b0; + end else begin + MBR <= M[MAR]; + end + end + + // Add value in AC with MBR value and store it back into AC + always @(posedge clk or posedge reset) begin + if (reset) begin + AC <= 16'b0; + end else begin + AC <= AC + MBR; + end + end + +endmodule + diff --git a/.history/verilog files/design_20231130135438.sv b/.history/verilog files/design_20231130135438.sv new file mode 100644 index 0000000..4a82de4 --- /dev/null +++ b/.history/verilog files/design_20231130135438.sv @@ -0,0 +1,244 @@ +`timescale 1ns / 1ps // Set the timescale to 1 nanosecond / 1 picosecond + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // Otherwise, set the instruction output to the instruction input + instr_out <= instr_in; + end +end + +endmodule + + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case is to set the result to 0 + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, // Clock + input wire [15:0] addr, // Address (16 bits) + input wire [15:0] data_in, // Data input (16 bits) + input wire write_enable, // Write enable (1 bit) + output reg [15:0] data_out // Data output (16 bits) +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule + +// Add X operation +module AddX ( + input wire clk, + input wire reset, + input wire [15:0] X, // The value to add + inout wire [15:0] AC, // Accumulator + inout wire [15:0] M[0:16383] // Main memory +); + + // Declare the necessary registers + reg [15:0] MAR; // Memory Address Register + reg [15:0] MBR; // Memory Buffer Register + + // Load X into MAR + always @(posedge clk or posedge reset) begin + if (reset) begin + MAR <= 16'b0; + end else begin + MAR <= X; + end + end + + // Load value stored at address X into MBR + always @(posedge clk or posedge reset) begin + if (reset) begin + MBR <= 16'b0; + end else begin + MBR <= M[MAR]; + end + end + + // Add value in AC with MBR value and store it back into AC + always @(posedge clk or posedge reset) begin + if (reset) begin + AC <= 16'b0; + end else begin + AC <= AC + MBR; + end + end + +endmodule + + +// Subtract X operation +module SubtractX ( + input wire clk, + input wire reset, + input wire [15:0] X, // The value to subtract + inout wire [15:0] AC, // Accumulator + inout wire [15:0] M[0:16383] // Main memory +); + + // Declare the necessary registers + reg [15:0] MAR; // Memory Address Register + reg [15:0] MBR; // Memory Buffer Register + + // Load X into MAR + always @(posedge clk or posedge reset) begin + if (reset) begin + MAR <= 16'b0; + end else begin + MAR <= X; + end + end + + // Load value stored at address X into MBR + always @(posedge clk or posedge reset) begin + if (reset) begin + MBR <= 16'b0; + end else begin + MBR <= M[MAR]; + end + end + + // Subtract MBR value from AC and store it back into AC + always @(posedge clk or posedge reset) begin + if (reset) begin + AC <= 16'b0; + end else begin + AC <= AC - MBR; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130135735.sv b/.history/verilog files/design_20231130135735.sv new file mode 100644 index 0000000..34348c5 --- /dev/null +++ b/.history/verilog files/design_20231130135735.sv @@ -0,0 +1,287 @@ +`timescale 1ns / 1ps // Set the timescale to 1 nanosecond / 1 picosecond + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // Otherwise, set the instruction output to the instruction input + instr_out <= instr_in; + end +end + +endmodule + + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case is to set the result to 0 + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, // Clock + input wire [15:0] addr, // Address (16 bits) + input wire [15:0] data_in, // Data input (16 bits) + input wire write_enable, // Write enable (1 bit) + output reg [15:0] data_out // Data output (16 bits) +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule + +// Add X operation +module AddX ( + input wire clk, + input wire reset, + input wire [15:0] X, // The value to add + inout wire [15:0] AC, // Accumulator + inout wire [15:0] M[0:16383] // Main memory +); + + // Declare the necessary registers + reg [15:0] MAR; // Memory Address Register + reg [15:0] MBR; // Memory Buffer Register + + // Load X into MAR + always @(posedge clk or posedge reset) begin + if (reset) begin + MAR <= 16'b0; + end else begin + MAR <= X; + end + end + + // Load value stored at address X into MBR + always @(posedge clk or posedge reset) begin + if (reset) begin + MBR <= 16'b0; + end else begin + MBR <= M[MAR]; + end + end + + // Add value in AC with MBR value and store it back into AC + always @(posedge clk or posedge reset) begin + if (reset) begin + AC <= 16'b0; + end else begin + AC <= AC + MBR; + end + end + +endmodule + + +// Subtract X operation +module SubtractX ( + input wire clk, + input wire reset, + input wire [15:0] X, // The value to subtract + inout wire [15:0] AC, // Accumulator + inout wire [15:0] M[0:16383] // Main memory +); + + // Declare the necessary registers + reg [15:0] MAR; // Memory Address Register + reg [15:0] MBR; // Memory Buffer Register + + // Load X into MAR + always @(posedge clk or posedge reset) begin + if (reset) begin + MAR <= 16'b0; + end else begin + MAR <= X; + end + end + + // Load value stored at address X into MBR + always @(posedge clk or posedge reset) begin + if (reset) begin + MBR <= 16'b0; + end else begin + MBR <= M[MAR]; + end + end + + // Subtract MBR value from AC and store it back into AC + always @(posedge clk or posedge reset) begin + if (reset) begin + AC <= 16'b0; + end else begin + AC <= AC - MBR; + end + end + +endmodule + + +// And X operation +module AndX ( + input wire clk, + input wire reset, + input wire [15:0] X, // The value to AND with + inout wire [15:0] AC, // Accumulator + inout wire [15:0] M[0:16383] // Main memory +); + + // Declare the necessary registers + reg [15:0] MAR; // Memory Address Register + reg [15:0] MBR; // Memory Buffer Register + + // Load X into MAR + always @(posedge clk or posedge reset) begin + if (reset) begin + MAR <= 16'b0; + end else begin + MAR <= X; + end + end + + // Load value stored at address X into MBR + always @(posedge clk or posedge reset) begin + if (reset) begin + MBR <= 16'b0; + end else begin + MBR <= M[MAR]; + end + end + + // Perform bitwise AND operation on AC and MBR value and store it back into AC + always @(posedge clk or posedge reset) begin + if (reset) begin + AC <= 16'b0; + end else begin + AC <= AC & MBR; + end + end + +endmodule diff --git a/.history/verilog files/design_20231130140123.sv b/.history/verilog files/design_20231130140123.sv new file mode 100644 index 0000000..34cecaa --- /dev/null +++ b/.history/verilog files/design_20231130140123.sv @@ -0,0 +1,291 @@ +`timescale 1ns / 1ps // Set the timescale to 1 nanosecond / 1 picosecond + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // Otherwise, set the instruction output to the instruction input + instr_out <= instr_in; + end +end + +endmodule + + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case is to set the result to 0 + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, // Clock + input wire [15:0] addr, // Address (16 bits) + input wire [15:0] data_in, // Data input (16 bits) + input wire write_enable, // Write enable (1 bit) + output reg [15:0] data_out // Data output (16 bits) +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule + +// Add X operation +module AddX ( + input wire clk, + input wire reset, + input wire [15:0] X, // The value to add + inout wire [15:0] AC, // Accumulator + inout wire [15:0] M[0:16383] // Main memory +); + + // Declare the necessary registers + reg [15:0] MAR; // Memory Address Register + reg [15:0] MBR; // Memory Buffer Register + + // Load X into MAR + always @(posedge clk or posedge reset) begin + if (reset) begin + MAR <= 16'b0; + end else begin + MAR <= X; + end + end + + // Load value stored at address X into MBR + always @(posedge clk or posedge reset) begin + if (reset) begin + MBR <= 16'b0; + end else begin + MBR <= M[MAR]; + end + end + + // Add value in AC with MBR value and store it back into AC + always @(posedge clk or posedge reset) begin + if (reset) begin + AC <= 16'b0; + end else begin + AC <= AC + MBR; + end + end + +endmodule + + +// Subtract X operation +module SubtractX ( + input wire clk, + input wire reset, + input wire [15:0] X, // The value to subtract + inout wire [15:0] AC, // Accumulator + inout wire [15:0] M[0:16383] // Main memory +); + + // Declare the necessary registers + reg [15:0] MAR; // Memory Address Register + reg [15:0] MBR; // Memory Buffer Register + + // Load X into MAR + always @(posedge clk or posedge reset) begin + if (reset) begin + MAR <= 16'b0; + end else begin + MAR <= X; + end + end + + // Load value stored at address X into MBR + always @(posedge clk or posedge reset) begin + if (reset) begin + MBR <= 16'b0; + end else begin + MBR <= M[MAR]; + end + end + + // Subtract MBR value from AC and store it back into AC + always @(posedge clk or posedge reset) begin + if (reset) begin + AC <= 16'b0; + end else begin + AC <= AC - MBR; + end + end + +endmodule + + +// And X operation +module AndX ( + input wire clk, + input wire reset, + input wire [15:0] X, // The value to AND with + inout wire [15:0] AC, // Accumulator + inout wire [15:0] M[0:16383] // Main memory +); + + // Declare the necessary registers + reg [15:0] MAR; // Memory Address Register + reg [15:0] MBR; // Memory Buffer Register + + // Load X into MAR + always @(posedge clk or posedge reset) begin + if (reset) begin + MAR <= 16'b0; + end else begin + MAR <= X; + end + end + + // Load value stored at address X into MBR + always @(posedge clk or posedge reset) begin + if (reset) begin + MBR <= 16'b0; + end else begin + MBR <= M[MAR]; + end + end + + // Perform bitwise AND operation on AC and MBR value and store it back into AC + always @(posedge clk or posedge reset) begin + if (reset) begin + AC <= 16'b0; + end else begin + AC <= AC & MBR; + end + end + +endmodule + + +not +AC  not AC \ No newline at end of file diff --git a/.history/verilog files/design_20231130140124.sv b/.history/verilog files/design_20231130140124.sv new file mode 100644 index 0000000..5a9ca8f --- /dev/null +++ b/.history/verilog files/design_20231130140124.sv @@ -0,0 +1,291 @@ +`timescale 1ns / 1ps // Set the timescale to 1 nanosecond / 1 picosecond + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // Otherwise, set the instruction output to the instruction input + instr_out <= instr_in; + end +end + +endmodule + + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case is to set the result to 0 + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, // Clock + input wire [15:0] addr, // Address (16 bits) + input wire [15:0] data_in, // Data input (16 bits) + input wire write_enable, // Write enable (1 bit) + output reg [15:0] data_out // Data output (16 bits) +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule + +// Add X operation +module AddX ( + input wire clk, + input wire reset, + input wire [15:0] X, // The value to add + inout wire [15:0] AC, // Accumulator + inout wire [15:0] M[0:16383] // Main memory +); + + // Declare the necessary registers + reg [15:0] MAR; // Memory Address Register + reg [15:0] MBR; // Memory Buffer Register + + // Load X into MAR + always @(posedge clk or posedge reset) begin + if (reset) begin + MAR <= 16'b0; + end else begin + MAR <= X; + end + end + + // Load value stored at address X into MBR + always @(posedge clk or posedge reset) begin + if (reset) begin + MBR <= 16'b0; + end else begin + MBR <= M[MAR]; + end + end + + // Add value in AC with MBR value and store it back into AC + always @(posedge clk or posedge reset) begin + if (reset) begin + AC <= 16'b0; + end else begin + AC <= AC + MBR; + end + end + +endmodule + + +// Subtract X operation +module SubtractX ( + input wire clk, + input wire reset, + input wire [15:0] X, // The value to subtract + inout wire [15:0] AC, // Accumulator + inout wire [15:0] M[0:16383] // Main memory +); + + // Declare the necessary registers + reg [15:0] MAR; // Memory Address Register + reg [15:0] MBR; // Memory Buffer Register + + // Load X into MAR + always @(posedge clk or posedge reset) begin + if (reset) begin + MAR <= 16'b0; + end else begin + MAR <= X; + end + end + + // Load value stored at address X into MBR + always @(posedge clk or posedge reset) begin + if (reset) begin + MBR <= 16'b0; + end else begin + MBR <= M[MAR]; + end + end + + // Subtract MBR value from AC and store it back into AC + always @(posedge clk or posedge reset) begin + if (reset) begin + AC <= 16'b0; + end else begin + AC <= AC - MBR; + end + end + +endmodule + + +// And X operation +module AndX ( + input wire clk, + input wire reset, + input wire [15:0] X, // The value to AND with + inout wire [15:0] AC, // Accumulator + inout wire [15:0] M[0:16383] // Main memory +); + + // Declare the necessary registers + reg [15:0] MAR; // Memory Address Register + reg [15:0] MBR; // Memory Buffer Register + + // Load X into MAR + always @(posedge clk or posedge reset) begin + if (reset) begin + MAR <= 16'b0; + end else begin + MAR <= X; + end + end + + // Load value stored at address X into MBR + always @(posedge clk or posedge reset) begin + if (reset) begin + MBR <= 16'b0; + end else begin + MBR <= M[MAR]; + end + end + + // Perform bitwise AND operation on AC and MBR value and store it back into AC + always @(posedge clk or posedge reset) begin + if (reset) begin + AC <= 16'b0; + end else begin + AC <= AC & MBR; + end + end + +endmodule + + +not +AC  not A \ No newline at end of file diff --git a/.history/verilog files/design_20231130140126.sv b/.history/verilog files/design_20231130140126.sv new file mode 100644 index 0000000..e95f8c1 --- /dev/null +++ b/.history/verilog files/design_20231130140126.sv @@ -0,0 +1,289 @@ +`timescale 1ns / 1ps // Set the timescale to 1 nanosecond / 1 picosecond + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // Otherwise, set the instruction output to the instruction input + instr_out <= instr_in; + end +end + +endmodule + + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case is to set the result to 0 + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, // Clock + input wire [15:0] addr, // Address (16 bits) + input wire [15:0] data_in, // Data input (16 bits) + input wire write_enable, // Write enable (1 bit) + output reg [15:0] data_out // Data output (16 bits) +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule + +// Add X operation +module AddX ( + input wire clk, + input wire reset, + input wire [15:0] X, // The value to add + inout wire [15:0] AC, // Accumulator + inout wire [15:0] M[0:16383] // Main memory +); + + // Declare the necessary registers + reg [15:0] MAR; // Memory Address Register + reg [15:0] MBR; // Memory Buffer Register + + // Load X into MAR + always @(posedge clk or posedge reset) begin + if (reset) begin + MAR <= 16'b0; + end else begin + MAR <= X; + end + end + + // Load value stored at address X into MBR + always @(posedge clk or posedge reset) begin + if (reset) begin + MBR <= 16'b0; + end else begin + MBR <= M[MAR]; + end + end + + // Add value in AC with MBR value and store it back into AC + always @(posedge clk or posedge reset) begin + if (reset) begin + AC <= 16'b0; + end else begin + AC <= AC + MBR; + end + end + +endmodule + + +// Subtract X operation +module SubtractX ( + input wire clk, + input wire reset, + input wire [15:0] X, // The value to subtract + inout wire [15:0] AC, // Accumulator + inout wire [15:0] M[0:16383] // Main memory +); + + // Declare the necessary registers + reg [15:0] MAR; // Memory Address Register + reg [15:0] MBR; // Memory Buffer Register + + // Load X into MAR + always @(posedge clk or posedge reset) begin + if (reset) begin + MAR <= 16'b0; + end else begin + MAR <= X; + end + end + + // Load value stored at address X into MBR + always @(posedge clk or posedge reset) begin + if (reset) begin + MBR <= 16'b0; + end else begin + MBR <= M[MAR]; + end + end + + // Subtract MBR value from AC and store it back into AC + always @(posedge clk or posedge reset) begin + if (reset) begin + AC <= 16'b0; + end else begin + AC <= AC - MBR; + end + end + +endmodule + + +// And X operation +module AndX ( + input wire clk, + input wire reset, + input wire [15:0] X, // The value to AND with + inout wire [15:0] AC, // Accumulator + inout wire [15:0] M[0:16383] // Main memory +); + + // Declare the necessary registers + reg [15:0] MAR; // Memory Address Register + reg [15:0] MBR; // Memory Buffer Register + + // Load X into MAR + always @(posedge clk or posedge reset) begin + if (reset) begin + MAR <= 16'b0; + end else begin + MAR <= X; + end + end + + // Load value stored at address X into MBR + always @(posedge clk or posedge reset) begin + if (reset) begin + MBR <= 16'b0; + end else begin + MBR <= M[MAR]; + end + end + + // Perform bitwise AND operation on AC and MBR value and store it back into AC + always @(posedge clk or posedge reset) begin + if (reset) begin + AC <= 16'b0; + end else begin + AC <= AC & MBR; + end + end + +endmodule + + diff --git a/.history/verilog files/design_20231130140132.sv b/.history/verilog files/design_20231130140132.sv new file mode 100644 index 0000000..e95f8c1 --- /dev/null +++ b/.history/verilog files/design_20231130140132.sv @@ -0,0 +1,289 @@ +`timescale 1ns / 1ps // Set the timescale to 1 nanosecond / 1 picosecond + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // Otherwise, set the instruction output to the instruction input + instr_out <= instr_in; + end +end + +endmodule + + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case is to set the result to 0 + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, // Clock + input wire [15:0] addr, // Address (16 bits) + input wire [15:0] data_in, // Data input (16 bits) + input wire write_enable, // Write enable (1 bit) + output reg [15:0] data_out // Data output (16 bits) +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule + +// Add X operation +module AddX ( + input wire clk, + input wire reset, + input wire [15:0] X, // The value to add + inout wire [15:0] AC, // Accumulator + inout wire [15:0] M[0:16383] // Main memory +); + + // Declare the necessary registers + reg [15:0] MAR; // Memory Address Register + reg [15:0] MBR; // Memory Buffer Register + + // Load X into MAR + always @(posedge clk or posedge reset) begin + if (reset) begin + MAR <= 16'b0; + end else begin + MAR <= X; + end + end + + // Load value stored at address X into MBR + always @(posedge clk or posedge reset) begin + if (reset) begin + MBR <= 16'b0; + end else begin + MBR <= M[MAR]; + end + end + + // Add value in AC with MBR value and store it back into AC + always @(posedge clk or posedge reset) begin + if (reset) begin + AC <= 16'b0; + end else begin + AC <= AC + MBR; + end + end + +endmodule + + +// Subtract X operation +module SubtractX ( + input wire clk, + input wire reset, + input wire [15:0] X, // The value to subtract + inout wire [15:0] AC, // Accumulator + inout wire [15:0] M[0:16383] // Main memory +); + + // Declare the necessary registers + reg [15:0] MAR; // Memory Address Register + reg [15:0] MBR; // Memory Buffer Register + + // Load X into MAR + always @(posedge clk or posedge reset) begin + if (reset) begin + MAR <= 16'b0; + end else begin + MAR <= X; + end + end + + // Load value stored at address X into MBR + always @(posedge clk or posedge reset) begin + if (reset) begin + MBR <= 16'b0; + end else begin + MBR <= M[MAR]; + end + end + + // Subtract MBR value from AC and store it back into AC + always @(posedge clk or posedge reset) begin + if (reset) begin + AC <= 16'b0; + end else begin + AC <= AC - MBR; + end + end + +endmodule + + +// And X operation +module AndX ( + input wire clk, + input wire reset, + input wire [15:0] X, // The value to AND with + inout wire [15:0] AC, // Accumulator + inout wire [15:0] M[0:16383] // Main memory +); + + // Declare the necessary registers + reg [15:0] MAR; // Memory Address Register + reg [15:0] MBR; // Memory Buffer Register + + // Load X into MAR + always @(posedge clk or posedge reset) begin + if (reset) begin + MAR <= 16'b0; + end else begin + MAR <= X; + end + end + + // Load value stored at address X into MBR + always @(posedge clk or posedge reset) begin + if (reset) begin + MBR <= 16'b0; + end else begin + MBR <= M[MAR]; + end + end + + // Perform bitwise AND operation on AC and MBR value and store it back into AC + always @(posedge clk or posedge reset) begin + if (reset) begin + AC <= 16'b0; + end else begin + AC <= AC & MBR; + end + end + +endmodule + + diff --git a/.history/verilog files/design_20231130140134.sv b/.history/verilog files/design_20231130140134.sv new file mode 100644 index 0000000..e51d724 --- /dev/null +++ b/.history/verilog files/design_20231130140134.sv @@ -0,0 +1,307 @@ +`timescale 1ns / 1ps // Set the timescale to 1 nanosecond / 1 picosecond + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // Otherwise, set the instruction output to the instruction input + instr_out <= instr_in; + end +end + +endmodule + + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case is to set the result to 0 + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, // Clock + input wire [15:0] addr, // Address (16 bits) + input wire [15:0] data_in, // Data input (16 bits) + input wire write_enable, // Write enable (1 bit) + output reg [15:0] data_out // Data output (16 bits) +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule + +// Add X operation +module AddX ( + input wire clk, + input wire reset, + input wire [15:0] X, // The value to add + inout wire [15:0] AC, // Accumulator + inout wire [15:0] M[0:16383] // Main memory +); + + // Declare the necessary registers + reg [15:0] MAR; // Memory Address Register + reg [15:0] MBR; // Memory Buffer Register + + // Load X into MAR + always @(posedge clk or posedge reset) begin + if (reset) begin + MAR <= 16'b0; + end else begin + MAR <= X; + end + end + + // Load value stored at address X into MBR + always @(posedge clk or posedge reset) begin + if (reset) begin + MBR <= 16'b0; + end else begin + MBR <= M[MAR]; + end + end + + // Add value in AC with MBR value and store it back into AC + always @(posedge clk or posedge reset) begin + if (reset) begin + AC <= 16'b0; + end else begin + AC <= AC + MBR; + end + end + +endmodule + + +// Subtract X operation +module SubtractX ( + input wire clk, + input wire reset, + input wire [15:0] X, // The value to subtract + inout wire [15:0] AC, // Accumulator + inout wire [15:0] M[0:16383] // Main memory +); + + // Declare the necessary registers + reg [15:0] MAR; // Memory Address Register + reg [15:0] MBR; // Memory Buffer Register + + // Load X into MAR + always @(posedge clk or posedge reset) begin + if (reset) begin + MAR <= 16'b0; + end else begin + MAR <= X; + end + end + + // Load value stored at address X into MBR + always @(posedge clk or posedge reset) begin + if (reset) begin + MBR <= 16'b0; + end else begin + MBR <= M[MAR]; + end + end + + // Subtract MBR value from AC and store it back into AC + always @(posedge clk or posedge reset) begin + if (reset) begin + AC <= 16'b0; + end else begin + AC <= AC - MBR; + end + end + +endmodule + + +// And X operation +module AndX ( + input wire clk, + input wire reset, + input wire [15:0] X, // The value to AND with + inout wire [15:0] AC, // Accumulator + inout wire [15:0] M[0:16383] // Main memory +); + + // Declare the necessary registers + reg [15:0] MAR; // Memory Address Register + reg [15:0] MBR; // Memory Buffer Register + + // Load X into MAR + always @(posedge clk or posedge reset) begin + if (reset) begin + MAR <= 16'b0; + end else begin + MAR <= X; + end + end + + // Load value stored at address X into MBR + always @(posedge clk or posedge reset) begin + if (reset) begin + MBR <= 16'b0; + end else begin + MBR <= M[MAR]; + end + end + + // Perform bitwise AND operation on AC and MBR value and store it back into AC + always @(posedge clk or posedge reset) begin + if (reset) begin + AC <= 16'b0; + end else begin + AC <= AC & MBR; + end + end + +endmodule + + +// Not operation +module Not ( + input wire clk, + input wire reset, + inout wire [15:0] AC // Accumulator +); + + // Perform bitwise NOT operation on AC and store it back into AC + always @(posedge clk or posedge reset) begin + if (reset) begin + AC <= 16'b0; + end else begin + AC <= ~AC; + end + end + +endmodule + diff --git a/.history/verilog files/design_20231130162758.sv b/.history/verilog files/design_20231130162758.sv new file mode 100644 index 0000000..71fe6d6 --- /dev/null +++ b/.history/verilog files/design_20231130162758.sv @@ -0,0 +1,160 @@ +`timescale 1ns / 1ps // Set the timescale to 1 nanosecond / 1 picosecond + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // Otherwise, set the instruction output to the instruction input + instr_out <= instr_in; + end +end + +endmodule + + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case is to set the result to 0 + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, // Clock + input wire [15:0] addr, // Address (16 bits) + input wire [15:0] data_in, // Data input (16 bits) + input wire write_enable, // Write enable (1 bit) + output reg [15:0] data_out // Data output (16 bits) +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule + diff --git a/.history/verilog files/design_20231130162818.sv b/.history/verilog files/design_20231130162818.sv new file mode 100644 index 0000000..9a91719 --- /dev/null +++ b/.history/verilog files/design_20231130162818.sv @@ -0,0 +1,167 @@ +`timescale 1ns / 1ps // Set the timescale to 1 nanosecond / 1 picosecond + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // Otherwise, set the instruction output to the instruction input + instr_out <= instr_in; + end +end + +endmodule + + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case is to set the result to 0 + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, // Clock + input wire [15:0] addr, // Address (16 bits) + input wire [15:0] data_in, // Data input (16 bits) + input wire write_enable, // Write enable (1 bit) + output reg [15:0] data_out // Data output (16 bits) +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule + +// Add function +function automatic int add(input int address); + int result; + // Perform addition operation using the address + result = address + 1; + return result; +endfunction diff --git a/.history/verilog files/design_20231130162823.sv b/.history/verilog files/design_20231130162823.sv new file mode 100644 index 0000000..99c12d8 --- /dev/null +++ b/.history/verilog files/design_20231130162823.sv @@ -0,0 +1,168 @@ +`timescale 1ns / 1ps // Set the timescale to 1 nanosecond / 1 picosecond + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // Otherwise, set the instruction output to the instruction input + instr_out <= instr_in; + end +end + +endmodule + + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case is to set the result to 0 + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, // Clock + input wire [15:0] addr, // Address (16 bits) + input wire [15:0] data_in, // Data input (16 bits) + input wire write_enable, // Write enable (1 bit) + output reg [15:0] data_out // Data output (16 bits) +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule + +// Add function +function automatic int add(input int address); + int result; + // Perform addition operation using the address + result = address + 1; + return result; +endfunction + diff --git a/.history/verilog files/design_20231130162849.sv b/.history/verilog files/design_20231130162849.sv new file mode 100644 index 0000000..71fe6d6 --- /dev/null +++ b/.history/verilog files/design_20231130162849.sv @@ -0,0 +1,160 @@ +`timescale 1ns / 1ps // Set the timescale to 1 nanosecond / 1 picosecond + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // Otherwise, set the instruction output to the instruction input + instr_out <= instr_in; + end +end + +endmodule + + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case is to set the result to 0 + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, // Clock + input wire [15:0] addr, // Address (16 bits) + input wire [15:0] data_in, // Data input (16 bits) + input wire write_enable, // Write enable (1 bit) + output reg [15:0] data_out // Data output (16 bits) +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule + diff --git a/.history/verilog files/design_20231130162854.sv b/.history/verilog files/design_20231130162854.sv new file mode 100644 index 0000000..8dedae6 --- /dev/null +++ b/.history/verilog files/design_20231130162854.sv @@ -0,0 +1,164 @@ +`timescale 1ns / 1ps // Set the timescale to 1 nanosecond / 1 picosecond + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // Otherwise, set the instruction output to the instruction input + instr_out <= instr_in; + end +end + +endmodule + + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case is to set the result to 0 + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, // Clock + input wire [15:0] addr, // Address (16 bits) + input wire [15:0] data_in, // Data input (16 bits) + input wire write_enable, // Write enable (1 bit) + output reg [15:0] data_out // Data output (16 bits) +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule + +// Add X +MAR <= X; // load X into MAR +MBR <= M[MAR]; // load value stored at address X into MBR +AC <= AC + MBR; // add value in AC with MBR value and store it back into AC diff --git a/.history/verilog files/design_20231130162857.sv b/.history/verilog files/design_20231130162857.sv new file mode 100644 index 0000000..71fe6d6 --- /dev/null +++ b/.history/verilog files/design_20231130162857.sv @@ -0,0 +1,160 @@ +`timescale 1ns / 1ps // Set the timescale to 1 nanosecond / 1 picosecond + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // Otherwise, set the instruction output to the instruction input + instr_out <= instr_in; + end +end + +endmodule + + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case is to set the result to 0 + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, // Clock + input wire [15:0] addr, // Address (16 bits) + input wire [15:0] data_in, // Data input (16 bits) + input wire write_enable, // Write enable (1 bit) + output reg [15:0] data_out // Data output (16 bits) +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule + diff --git a/.history/verilog files/design_20231130162859.sv b/.history/verilog files/design_20231130162859.sv new file mode 100644 index 0000000..f737f7f --- /dev/null +++ b/.history/verilog files/design_20231130162859.sv @@ -0,0 +1,164 @@ +`timescale 1ns / 1ps // Set the timescale to 1 nanosecond / 1 picosecond + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // Otherwise, set the instruction output to the instruction input + instr_out <= instr_in; + end +end + +endmodule + + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case is to set the result to 0 + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, // Clock + input wire [15:0] addr, // Address (16 bits) + input wire [15:0] data_in, // Data input (16 bits) + input wire write_enable, // Write enable (1 bit) + output reg [15:0] data_out // Data output (16 bits) +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule +// Add X +MAR <= X; // load X into MAR +MBR <= M[MAR]; // load value stored at address X into MBR +AC <= AC + MBR; // add value in AC with MBR value and store it back into AC + diff --git a/.history/verilog files/design_20231130162919.sv b/.history/verilog files/design_20231130162919.sv new file mode 100644 index 0000000..3642687 --- /dev/null +++ b/.history/verilog files/design_20231130162919.sv @@ -0,0 +1,181 @@ +`timescale 1ns / 1ps // Set the timescale to 1 nanosecond / 1 picosecond + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // Otherwise, set the instruction output to the instruction input + instr_out <= instr_in; + end +end + +endmodule + + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case is to set the result to 0 + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, // Clock + input wire [15:0] addr, // Address (16 bits) + input wire [15:0] data_in, // Data input (16 bits) + input wire write_enable, // Write enable (1 bit) + output reg [15:0] data_out // Data output (16 bits) +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule +// Add X +MAR <= X; // load X into MAR +MBR <= M[MAR]; // load value stored at address X into MBR +AC <= AC + MBR; // add value in AC with MBR value and store it back into AC +function automatic void add_X; + input wire [15:0] X; + input wire [15:0] M[16383]; + inout wire [15:0] AC; + + reg [15:0] MAR; + reg [15:0] MBR; + + // load X into MAR + MAR <= X; + + // load value stored at address X into MBR + MBR <= M[MAR]; + + // add value in AC with MBR value and store it back into AC + AC <= AC + MBR; +endfunction + diff --git a/.history/verilog files/design_20231130162948.sv b/.history/verilog files/design_20231130162948.sv new file mode 100644 index 0000000..c922416 --- /dev/null +++ b/.history/verilog files/design_20231130162948.sv @@ -0,0 +1,159 @@ +`timescale 1ns / 1ps // Set the timescale to 1 nanosecond / 1 picosecond + +// Accumulator +module Accumulator ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] acc // Accumulator (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the accumulator + acc <= 16'b0; + end else begin // Otherwise, add data_in to the accumulator + acc <= acc + data_in; + end +end + +endmodule + + +// Program Counter +module ProgramCounter ( + input wire clk, // Clock + input wire reset, // Reset + input wire jump, // Jump enable + input wire [15:0] jump_addr, // Jump address (16 bits) + output reg [15:0] pc // Program counter (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the program counter + pc <= 16'b0; + end else if (jump) begin // If jump is asserted, jump to the address specified by jump_addr + pc <= jump_addr; + end else begin // Otherwise, increment the program counter + if (pc == 16'hFFFF) begin // If the program counter is at its maximum value, wrap around to 0 + $display("Warning: Program Counter overflow"); + pc <= 16'b0; + end else begin // Otherwise, increment the program counter + pc <= pc + 1; + end + end +end + +endmodule + + +// Memory Access Register +module MAR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] addr_in, // Address input (16 bits) + output reg [15:0] addr_out // Address output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the address output + addr_out <= 16'b0; + end else begin // Otherwise, set the address output to the address input + addr_out <= addr_in; + end +end + +endmodule + + +// Memory Buffer Register +module MBR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] data_in, // Data input (16 bits) + output reg [15:0] data_out // Data output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the data output + data_out <= 16'b0; + end else begin // Otherwise, set the data output to the data input + data_out <= data_in; + end +end + +endmodule + + +// Instruction Register +module IR ( + input wire clk, // Clock + input wire reset, // Reset + input wire [15:0] instr_in, // Instruction input (16 bits) + output reg [15:0] instr_out // Instruction output (16 bits) +); + +always @(posedge clk or posedge reset) begin + if (reset) begin // If reset is asserted, reset the instruction output + instr_out <= 16'b0; + end else begin // Otherwise, set the instruction output to the instruction input + instr_out <= instr_in; + end +end + +endmodule + + +// Arithmetic and Logic Unit +module ALU ( + input wire [3:0] opcode, // Operation code size is 4 bits + input wire [15:0] operand1, // Operands are 16 bits + input wire [15:0] operand2, // Operands are 16 bits + output reg [15:0] result // Result is 16 bits +); + +always @(*) begin + case (opcode) + 4'b0000: result = operand1 + operand2; // Addition + 4'b0001: result = operand1 - operand2; // Subtraction + 4'b0010: result = operand1 * operand2; // Multiplication + 4'b0011: result = operand1 / operand2; // Division + 4'b0100: result = operand1 << 1; // Left shift + 4'b0101: result = operand1 >> 1; // Right shift + 4'b0110: result = {operand1[14:0], operand1[15]}; // Rotate left + 4'b0111: result = {operand1[0], operand1[15:1]}; // Rotate right + 4'b1000: result = operand1 & operand2; // Bitwise AND + 4'b1001: result = operand1 | operand2; // Bitwise OR + 4'b1010: result = operand1 ^ operand2; // Bitwise XOR + 4'b1011: result = ~(operand1 | operand2); // NOR + 4'b1100: result = ~(operand1 & operand2); // NAND + 4'b1101: result = ~(operand1 ^ operand2); // XNOR + 4'b1110: result = operand1 > operand2 ? 16'd1 : 16'd0; // Greater than + 4'b1111: result = operand1 == operand2 ? 16'd1 : 16'd0; // Equal to + default: result = 16'b0; // Default case is to set the result to 0 + endcase +end + +endmodule + + +// Main memory +module MainMemory ( + input wire clk, // Clock + input wire [15:0] addr, // Address (16 bits) + input wire [15:0] data_in, // Data input (16 bits) + input wire write_enable, // Write enable (1 bit) + output reg [15:0] data_out // Data output (16 bits) +); + + // Declare a 16Ki x 16 memory array + reg [15:0] memory [0:16383]; + + always @(posedge clk) begin + if (write_enable) begin // Write data_in to the memory location specified by addr + memory[addr] <= data_in; + end else begin // Read data from the memory location specified by addr + data_out <= memory[addr]; + end + end + +endmodule diff --git a/.history/verilog files/testbench_20231130164947.sv b/.history/verilog files/testbench_20231130164947.sv new file mode 100644 index 0000000..063606e --- /dev/null +++ b/.history/verilog files/testbench_20231130164947.sv @@ -0,0 +1,65 @@ +// Testbench +module Testbench; + reg clk; + reg reset; + reg jump; + reg [15:0] jump_addr; + reg [15:0] data_in; + wire [15:0] acc; + wire [15:0] pc; + + // Instantiate the Accumulator and ProgramCounter + Accumulator u1 ( + .clk(clk), + .reset(reset), + .data_in(data_in), + .acc(acc) + ); + + ProgramCounter u2 ( + .clk(clk), + .reset(reset), + .jump(jump), + .jump_addr(jump_addr), + .pc(pc) + ); + + // Clock process + initial begin + clk = 0; + forever #10 clk = ~clk; + end + + // Stimulus process + initial begin + // Initialize inputs + reset = 1; + jump = 0; + jump_addr = 0; + data_in = 0; + #20 reset = 0; + #20 data_in = 16'h1234; + #20 jump = 1; jump_addr = 16'h5678; + #20 data_in = 16'h9abc; + #20 jump = 0; + #20 data_in = 16'hdef0; + #20 jump = 1; jump_addr = 16'h1234; + #20 $finish; + end + + // Monitor process + initial begin + $monitor("At time %d, data_in = %h, acc = %h, jump = %b, jump_addr = %h, pc = %h", $time, data_in, acc, jump, jump_addr, pc); + end + + // Assertion process + initial begin + #60; // Wait for 60 time units + if (acc !== 16'h1234) $error("Error: acc != 16'h1234"); + #20 // Wait for 20 time units + if (pc !== 16'h5678) $error("Error: pc != 16'h5678"); + // Continue with other assertions... + end + + +endmodule \ No newline at end of file diff --git a/.history/verilog files/testbench_20231130164958.sv b/.history/verilog files/testbench_20231130164958.sv new file mode 100644 index 0000000..063606e --- /dev/null +++ b/.history/verilog files/testbench_20231130164958.sv @@ -0,0 +1,65 @@ +// Testbench +module Testbench; + reg clk; + reg reset; + reg jump; + reg [15:0] jump_addr; + reg [15:0] data_in; + wire [15:0] acc; + wire [15:0] pc; + + // Instantiate the Accumulator and ProgramCounter + Accumulator u1 ( + .clk(clk), + .reset(reset), + .data_in(data_in), + .acc(acc) + ); + + ProgramCounter u2 ( + .clk(clk), + .reset(reset), + .jump(jump), + .jump_addr(jump_addr), + .pc(pc) + ); + + // Clock process + initial begin + clk = 0; + forever #10 clk = ~clk; + end + + // Stimulus process + initial begin + // Initialize inputs + reset = 1; + jump = 0; + jump_addr = 0; + data_in = 0; + #20 reset = 0; + #20 data_in = 16'h1234; + #20 jump = 1; jump_addr = 16'h5678; + #20 data_in = 16'h9abc; + #20 jump = 0; + #20 data_in = 16'hdef0; + #20 jump = 1; jump_addr = 16'h1234; + #20 $finish; + end + + // Monitor process + initial begin + $monitor("At time %d, data_in = %h, acc = %h, jump = %b, jump_addr = %h, pc = %h", $time, data_in, acc, jump, jump_addr, pc); + end + + // Assertion process + initial begin + #60; // Wait for 60 time units + if (acc !== 16'h1234) $error("Error: acc != 16'h1234"); + #20 // Wait for 20 time units + if (pc !== 16'h5678) $error("Error: pc != 16'h5678"); + // Continue with other assertions... + end + + +endmodule \ No newline at end of file diff --git a/verilog files/testbench.sv b/verilog files/testbench.sv index 88576ef..063606e 100644 --- a/verilog files/testbench.sv +++ b/verilog files/testbench.sv @@ -52,4 +52,14 @@ module Testbench; $monitor("At time %d, data_in = %h, acc = %h, jump = %b, jump_addr = %h, pc = %h", $time, data_in, acc, jump, jump_addr, pc); end + // Assertion process + initial begin + #60; // Wait for 60 time units + if (acc !== 16'h1234) $error("Error: acc != 16'h1234"); + #20 // Wait for 20 time units + if (pc !== 16'h5678) $error("Error: pc != 16'h5678"); + // Continue with other assertions... + end + + endmodule \ No newline at end of file