Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Design 1 & 2 Specifications Per Team ID. #3

Open
GhostOf0days opened this issue Nov 22, 2023 · 0 comments
Open

Design 1 & 2 Specifications Per Team ID. #3

GhostOf0days opened this issue Nov 22, 2023 · 0 comments

Comments

@GhostOf0days
Copy link
Owner

GhostOf0days commented Nov 22, 2023

Our Team ID is 90. 90 % 32 = 26. 90 % 4 = 2.

Therefore, for design 1:

Team ID mod 32 Word size, bits Main memory size, bytes Main memory organization Max number of bits to be used by L1 cache Additional addressing mode
26 16 64Ki 16Ki x 8 75,000 Indirect

and for design 2:

Team ID mod 4 Architecture Addressing modes
2 General purpose register Register addressing, based addressing, register indirect addressing
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

No branches or pull requests

1 participant