From 973e9d9c1d914972553db656fdba36d29cbae088 Mon Sep 17 00:00:00 2001
From: Carson Bush <hyperdriveguy@gmail.com>
Date: Mon, 1 Apr 2024 16:11:29 -0600
Subject: [PATCH 1/7] Add beginnings of top level CPU module

---
 .../eight_bit_console.cache/wt/project.wpc    |  2 +-
 .../sources_1/new/cpu.v                       | 79 +++++++++++++++++++
 .../sources_1/new/register_file.v             |  2 +-
 eight_bit_console/eight_bit_console.xpr       | 76 +++++++++++++++---
 4 files changed, 148 insertions(+), 11 deletions(-)
 create mode 100644 eight_bit_console/eight_bit_console.srcs/sources_1/new/cpu.v

diff --git a/eight_bit_console/eight_bit_console.cache/wt/project.wpc b/eight_bit_console/eight_bit_console.cache/wt/project.wpc
index 2599f42..d5e2b40 100644
--- a/eight_bit_console/eight_bit_console.cache/wt/project.wpc
+++ b/eight_bit_console/eight_bit_console.cache/wt/project.wpc
@@ -1,3 +1,3 @@
 version:1
-6d6f64655f636f756e7465727c4755494d6f6465:7
+6d6f64655f636f756e7465727c4755494d6f6465:8
 eof:
diff --git a/eight_bit_console/eight_bit_console.srcs/sources_1/new/cpu.v b/eight_bit_console/eight_bit_console.srcs/sources_1/new/cpu.v
new file mode 100644
index 0000000..8560900
--- /dev/null
+++ b/eight_bit_console/eight_bit_console.srcs/sources_1/new/cpu.v
@@ -0,0 +1,79 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 04/01/2024 11:14:34 AM
+// Design Name: 
+// Module Name: cpu
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module cpu(
+    input clk
+    );
+    
+    wire rfile_bit_mode;
+    wire rfile_we;
+    wire rfile_data_in;
+    wire rfile_data_in_wide;
+    wire rfile_write_sel;
+    wire rfile_sel_a;
+    wire rfile_sel_b;
+    wire rfile_output_a;
+    wire rfile_output_a_wide;
+    wire rfile_output_b;
+    wire rfile_output_b_wide;
+    wire rfile_flags_we;
+    wire rfile_new_flags;
+    wire rfile_cur_flags;
+    
+    
+    register_file rfile (
+        .clk(clk),
+        .wide_mode(rfile_bit_mode),
+        .we(rfile_we),
+        .data(rfile_data_in),
+        .data_wide(rfile_data_in_wide),
+        .dest_sel(rfile_write_sel),
+        .src_a_sel(rfile_sel_a),
+        .src_b_sel(rfile_sel_b),
+        .port_a(rfile_output_a),
+        .port_a_wide(rfile_output_a_wide),
+        .port_b(rfile_output_b),
+        .port_b_wide(rfile_output_b_wide),
+        .we_flags(rfile_flags_we),
+        .new_flags(rfile_new_flags),
+        .flags(rfile_cur_flags)
+    );
+    
+    
+    wire enable_pc;
+    wire pc_we;
+    wire pc_j_addr;
+    wire pc_cur_count;
+    
+    program_counter prog_count (
+        .clk(clk),
+        .enable(enable_pc),
+        .we(pc_we),
+        .j_addr(pc_j_addr),
+        .count(pc_cur_count)
+    );
+    
+    
+    
+    
+endmodule
+
diff --git a/eight_bit_console/eight_bit_console.srcs/sources_1/new/register_file.v b/eight_bit_console/eight_bit_console.srcs/sources_1/new/register_file.v
index a7780df..3709699 100644
--- a/eight_bit_console/eight_bit_console.srcs/sources_1/new/register_file.v
+++ b/eight_bit_console/eight_bit_console.srcs/sources_1/new/register_file.v
@@ -30,8 +30,8 @@ module register_file(
     input [3:0] src_a_sel,
     input [3:0] src_b_sel,
     output [7:0] port_a,
-    output [7:0] port_b,
     output [7:0] port_a_wide,
+    output [7:0] port_b,
     output [7:0] port_b_wide,
     input we_flags,
     input [7:0] new_flags,
diff --git a/eight_bit_console/eight_bit_console.xpr b/eight_bit_console/eight_bit_console.xpr
index 1a89958..10bceb6 100644
--- a/eight_bit_console/eight_bit_console.xpr
+++ b/eight_bit_console/eight_bit_console.xpr
@@ -44,7 +44,7 @@
     <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
     <Option Name="BoardPart" Val=""/>
-    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="ActiveSimSet" Val="io_standalone_test"/>
     <Option Name="DefaultLib" Val="xil_defaultlib"/>
     <Option Name="ProjectType" Val="Default"/>
     <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
@@ -52,14 +52,14 @@
     <Option Name="IPCachePermission" Val="read"/>
     <Option Name="IPCachePermission" Val="write"/>
     <Option Name="EnableCoreContainer" Val="FALSE"/>
-    <Option Name="EnableResourceEstimation" Val="FALSE"/>
+    <Option Name="EnableResourceEstimation" Val="TRUE"/>
     <Option Name="SimCompileState" Val="TRUE"/>
     <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
-    <Option Name="WTXSimLaunchSim" Val="5"/>
+    <Option Name="WTXSimLaunchSim" Val="8"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -90,14 +90,14 @@
   <FileSets Version="1" Minor="32">
     <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
       <Filter Type="Srcs"/>
-      <File Path="$PSRCDIR/sources_1/new/alu.v">
+      <File Path="$PSRCDIR/sources_1/new/eight_bit_console_top.v">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="implementation"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PSRCDIR/sources_1/new/eight_bit_console_top.v">
+      <File Path="$PSRCDIR/sources_1/new/alu.v">
         <FileInfo>
           <Attr Name="AutoDisabled" Val="1"/>
           <Attr Name="UsedIn" Val="synthesis"/>
@@ -129,10 +129,33 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PSRCDIR/sources_1/new/bootloader_rom.v">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/io_controller.v">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/cpu.v">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="add_8bit"/>
-        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TopModule" Val="eight_bit_console_top"/>
       </Config>
     </FileSet>
     <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
@@ -184,6 +207,37 @@
         <Option Name="TopAutoSet" Val="TRUE"/>
       </Config>
     </FileSet>
+    <FileSet Name="io_standalone_test" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/io_standalone_test" RelGenDir="$PGENDIR/io_standalone_test">
+      <Filter Type="Srcs"/>
+      <File Path="$PSRCDIR/sources_1/new/io_controller.v">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/io_standalone_test/new/io_controller_tb.v">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val=""/>
+      </Config>
+    </FileSet>
   </FileSets>
   <Simulators>
     <Simulator Name="XSim">
@@ -209,7 +263,9 @@
   <Runs Version="1" Minor="21">
     <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
@@ -218,7 +274,9 @@
     </Run>
     <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>

From 084949fcc3ea9c779ba9bd8df28022106bc9ddb6 Mon Sep 17 00:00:00 2001
From: Carson Bush <hyperdriveguy@gmail.com>
Date: Tue, 2 Apr 2024 22:17:42 -0600
Subject: [PATCH 2/7] Beginnings of a fetch-execute unit

---
 .../eight_bit_console.cache/wt/project.wpc    |  2 +-
 .../sources_1/new/cpu.v                       | 26 +++----
 .../sources_1/new/fetch_execute.sv            | 74 +++++++++++++++++++
 eight_bit_console/eight_bit_console.xpr       | 16 ++--
 4 files changed, 98 insertions(+), 20 deletions(-)
 create mode 100644 eight_bit_console/eight_bit_console.srcs/sources_1/new/fetch_execute.sv

diff --git a/eight_bit_console/eight_bit_console.cache/wt/project.wpc b/eight_bit_console/eight_bit_console.cache/wt/project.wpc
index d5e2b40..ccef59f 100644
--- a/eight_bit_console/eight_bit_console.cache/wt/project.wpc
+++ b/eight_bit_console/eight_bit_console.cache/wt/project.wpc
@@ -1,3 +1,3 @@
 version:1
-6d6f64655f636f756e7465727c4755494d6f6465:8
+6d6f64655f636f756e7465727c4755494d6f6465:9
 eof:
diff --git a/eight_bit_console/eight_bit_console.srcs/sources_1/new/cpu.v b/eight_bit_console/eight_bit_console.srcs/sources_1/new/cpu.v
index 8560900..62ca987 100644
--- a/eight_bit_console/eight_bit_console.srcs/sources_1/new/cpu.v
+++ b/eight_bit_console/eight_bit_console.srcs/sources_1/new/cpu.v
@@ -21,7 +21,12 @@
 
 
 module cpu(
-    input clk
+    input clk,
+    input [7:0] mem_data_in,
+    output [7:0] mem_data_out,
+    output [15:0] mem_addr,
+    output mem_read,
+    output mem_write
     );
     
     wire rfile_bit_mode;
@@ -57,21 +62,16 @@ module cpu(
         .new_flags(rfile_new_flags),
         .flags(rfile_cur_flags)
     );
+
+
+    // Memory data bus logic
+    wire mem_select;
     
     
-    wire enable_pc;
-    wire pc_we;
-    wire pc_j_addr;
-    wire pc_cur_count;
-    
-    program_counter prog_count (
-        .clk(clk),
-        .enable(enable_pc),
-        .we(pc_we),
-        .j_addr(pc_j_addr),
-        .count(pc_cur_count)
-    );
     
+    // Instruction pipeline and decoder
+    wire [15:0] fetcher_addr;
+    wire [7:0] fetcher_next_i;
     
     
     
diff --git a/eight_bit_console/eight_bit_console.srcs/sources_1/new/fetch_execute.sv b/eight_bit_console/eight_bit_console.srcs/sources_1/new/fetch_execute.sv
new file mode 100644
index 0000000..8360eee
--- /dev/null
+++ b/eight_bit_console/eight_bit_console.srcs/sources_1/new/fetch_execute.sv
@@ -0,0 +1,74 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 04/02/2024 07:26:16 PM
+// Design Name:
+// Module Name: fetch_decode
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module fetch_execute(
+    input clk,
+    input [3:0] exec_flags,
+    input [7:0] op_part_data,
+    output [15:0] op_part_addr,
+    output [5:0] function_sel,
+    output mem_sel
+    );
+    
+    typedef logic [15:0] addr_t;
+
+    wire pc_enable;
+    wire pc_we;
+    wire pc_j_addr;
+    wire pc_cur_count;
+
+    program_counter prog_count (
+        .clk(clk),
+        .enable(pc_enable),
+        .we(pc_we),
+        .j_addr(pc_j_addr),
+        .count(pc_cur_count)
+    );
+
+
+    // Pipeline
+    byte stage_in, int_stage_a, int_stage_b, stage_out;
+    
+    // Fetch logic
+    addr_t cur_inst_addr = 0;
+    logic [1:0] to_next_op = 0;
+    logic mem_op_pending = 0;
+    logic dirty_pipeline = 0;
+    
+    // Decode logic
+    
+    
+    assign mem_sel = mem_op_pending;
+    assign op_part_addr = pc_cur_count;
+    assign pc_we = !mem_op_pending;
+    
+    
+    always @(clk) begin
+        if (!mem_op_pending) begin
+            stage_in <= op_part_data;
+            int_stage_a <= stage_in;
+            int_stage_b <= int_stage_a;
+            stage_out <= int_stage_b;
+        end
+    end
+
+endmodule
diff --git a/eight_bit_console/eight_bit_console.xpr b/eight_bit_console/eight_bit_console.xpr
index 10bceb6..a76ccae 100644
--- a/eight_bit_console/eight_bit_console.xpr
+++ b/eight_bit_console/eight_bit_console.xpr
@@ -153,6 +153,14 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PSRCDIR/sources_1/new/fetch_execute.sv">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
         <Option Name="TopModule" Val="eight_bit_console_top"/>
@@ -263,9 +271,7 @@
   <Runs Version="1" Minor="21">
     <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
         <Step Id="synth_design"/>
       </Strategy>
       <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
@@ -274,9 +280,7 @@
     </Run>
     <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>

From 272cd314aa8800c7e6f46f01131f69b229cfdcdb Mon Sep 17 00:00:00 2001
From: Carson Bush <hyperdriveguy@gmail.com>
Date: Wed, 3 Apr 2024 17:06:33 -0600
Subject: [PATCH 3/7] Add instruction decoder module skeleton

---
 .../eight_bit_console.cache/wt/project.wpc    |  2 +-
 .../sources_1/new/fetch_execute.sv            | 16 ++++----
 .../sources_1/new/instruction_decoder.sv      | 38 +++++++++++++++++++
 eight_bit_console/eight_bit_console.xpr       |  8 ++++
 4 files changed, 56 insertions(+), 8 deletions(-)
 create mode 100644 eight_bit_console/eight_bit_console.srcs/sources_1/new/instruction_decoder.sv

diff --git a/eight_bit_console/eight_bit_console.cache/wt/project.wpc b/eight_bit_console/eight_bit_console.cache/wt/project.wpc
index ccef59f..24316b6 100644
--- a/eight_bit_console/eight_bit_console.cache/wt/project.wpc
+++ b/eight_bit_console/eight_bit_console.cache/wt/project.wpc
@@ -1,3 +1,3 @@
 version:1
-6d6f64655f636f756e7465727c4755494d6f6465:9
+6d6f64655f636f756e7465727c4755494d6f6465:11
 eof:
diff --git a/eight_bit_console/eight_bit_console.srcs/sources_1/new/fetch_execute.sv b/eight_bit_console/eight_bit_console.srcs/sources_1/new/fetch_execute.sv
index 8360eee..2e91b87 100644
--- a/eight_bit_console/eight_bit_console.srcs/sources_1/new/fetch_execute.sv
+++ b/eight_bit_console/eight_bit_console.srcs/sources_1/new/fetch_execute.sv
@@ -46,11 +46,12 @@ module fetch_execute(
 
 
     // Pipeline
-    byte stage_in, int_stage_a, int_stage_b, stage_out;
+    byte op_part_3, op_part_2, op_part_1, op_part_0;
+    logic [3:0] dirty_pipe;
     
     // Fetch logic
     addr_t cur_inst_addr = 0;
-    logic [1:0] to_next_op = 0;
+    logic [1:0] op_length = 0;
     logic mem_op_pending = 0;
     logic dirty_pipeline = 0;
     
@@ -59,16 +60,17 @@ module fetch_execute(
     
     assign mem_sel = mem_op_pending;
     assign op_part_addr = pc_cur_count;
-    assign pc_we = !mem_op_pending;
+    assign pc_enable = !mem_op_pending;
     
     
     always @(clk) begin
         if (!mem_op_pending) begin
-            stage_in <= op_part_data;
-            int_stage_a <= stage_in;
-            int_stage_b <= int_stage_a;
-            stage_out <= int_stage_b;
+            op_part_3 <= op_part_data;
+            op_part_2 <= op_part_3;
+            op_part_1 <= op_part_2;
+            op_part_0 <= op_part_1;
         end
+        
     end
 
 endmodule
diff --git a/eight_bit_console/eight_bit_console.srcs/sources_1/new/instruction_decoder.sv b/eight_bit_console/eight_bit_console.srcs/sources_1/new/instruction_decoder.sv
new file mode 100644
index 0000000..361dc07
--- /dev/null
+++ b/eight_bit_console/eight_bit_console.srcs/sources_1/new/instruction_decoder.sv
@@ -0,0 +1,38 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 04/03/2024 05:05:31 PM
+// Design Name: 
+// Module Name: instruction_decoder
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module instruction_decoder(
+    input [31:0] op_parts,
+    input [7:0] cur_flags,
+    input [1:0] op_length,
+    input is_dirty_op,
+    output [3:1] part_dirty,
+    output [11:0] sel_reg,
+    output [3:0] sel_alu,
+    output bit_mode,
+    output jump_en,
+    output [15:0] jump_addr,
+    output mem_access,
+    output pause_exec,
+    output [7:0] new_flags
+    );
+endmodule
diff --git a/eight_bit_console/eight_bit_console.xpr b/eight_bit_console/eight_bit_console.xpr
index a76ccae..95cc6ba 100644
--- a/eight_bit_console/eight_bit_console.xpr
+++ b/eight_bit_console/eight_bit_console.xpr
@@ -161,6 +161,14 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PSRCDIR/sources_1/new/instruction_decoder.sv">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
         <Option Name="TopModule" Val="eight_bit_console_top"/>

From 4230d8aad8950d73040f234dfffca1ccb5d50fdf Mon Sep 17 00:00:00 2001
From: Carson Bush <hyperdriveguy@gmail.com>
Date: Wed, 3 Apr 2024 21:57:50 -0600
Subject: [PATCH 4/7] Start adding the units in the CPU hierarchy

---
 .../eight_bit_console.cache/wt/project.wpc    |  2 +-
 .../sources_1/new/cpu.v                       | 14 +++++
 .../sources_1/new/fetch_execute.sv            | 57 ++++++++++++++-----
 eight_bit_console/eight_bit_console.xpr       | 16 ------
 4 files changed, 57 insertions(+), 32 deletions(-)

diff --git a/eight_bit_console/eight_bit_console.cache/wt/project.wpc b/eight_bit_console/eight_bit_console.cache/wt/project.wpc
index 24316b6..94ba00c 100644
--- a/eight_bit_console/eight_bit_console.cache/wt/project.wpc
+++ b/eight_bit_console/eight_bit_console.cache/wt/project.wpc
@@ -1,3 +1,3 @@
 version:1
-6d6f64655f636f756e7465727c4755494d6f6465:11
+6d6f64655f636f756e7465727c4755494d6f6465:12
 eof:
diff --git a/eight_bit_console/eight_bit_console.srcs/sources_1/new/cpu.v b/eight_bit_console/eight_bit_console.srcs/sources_1/new/cpu.v
index 62ca987..8620379 100644
--- a/eight_bit_console/eight_bit_console.srcs/sources_1/new/cpu.v
+++ b/eight_bit_console/eight_bit_console.srcs/sources_1/new/cpu.v
@@ -72,6 +72,20 @@ module cpu(
     // Instruction pipeline and decoder
     wire [15:0] fetcher_addr;
     wire [7:0] fetcher_next_i;
+
+    wire [3:0] alu_function;
+    wire [11:0] reg_file_full_sel;
+    wire bit_mode;
+
+    fetch_execute executor_1 (
+        .clk(clk),
+        .mem_sel(mem_select),
+        .op_part_data(fetcher_next_i),
+        .op_part_addr(fetcher_addr),
+        .alu_sel(alu_function),
+        .reg_file_sel(reg_file_full_sel),
+        .bit_mode(bit_mode)
+    );
     
     
     
diff --git a/eight_bit_console/eight_bit_console.srcs/sources_1/new/fetch_execute.sv b/eight_bit_console/eight_bit_console.srcs/sources_1/new/fetch_execute.sv
index 2e91b87..e070170 100644
--- a/eight_bit_console/eight_bit_console.srcs/sources_1/new/fetch_execute.sv
+++ b/eight_bit_console/eight_bit_console.srcs/sources_1/new/fetch_execute.sv
@@ -22,11 +22,12 @@
 
 module fetch_execute(
     input clk,
-    input [3:0] exec_flags,
     input [7:0] op_part_data,
     output [15:0] op_part_addr,
-    output [5:0] function_sel,
-    output mem_sel
+    output mem_sel,
+    output [3:0] alu_sel,
+    output [11:0] reg_file_sel,
+    output bit_mode
     );
     
     typedef logic [15:0] addr_t;
@@ -46,29 +47,55 @@ module fetch_execute(
 
 
     // Pipeline
-    byte op_part_3, op_part_2, op_part_1, op_part_0;
+    byte op_part [3:0];
     logic [3:0] dirty_pipe;
     
     // Fetch logic
-    addr_t cur_inst_addr = 0;
-    logic [1:0] op_length = 0;
-    logic mem_op_pending = 0;
-    logic dirty_pipeline = 0;
+    // addr_t cur_inst_addr = 0;
     
     // Decode logic
+    logic [31:0] deco_op_parts = {op_part[0], op_part[1], op_part[2], op_part[3]};
+    logic [7:0] deco_cur_flags;
+    logic [1:0] deco_op_length;
+    logic deco_is_dirty_op;
+    logic [3:1] deco_part_dirty;
+    logic deco_jump_en;
+    logic [15:0] deco_jump_addr;
+    logic instr_mem_access;
+    logic deco_pause_exec;
+    logic [7:0] deco_new_flags;
+
+    instruction_decoder inst_decode (
+        .op_parts(deco_op_parts),
+        .cur_flags(deco_cur_flags),
+        .op_length(deco_op_length),
+        .is_dirty_op(deco_is_dirty_op),
+        .part_dirty(deco_part_dirty),
+
+        // These are directly routed to the top level
+        .sel_reg(reg_file_sel),
+        .sel_alu(alu_sel),
+        .bit_mode(bit_mode),
+
+        .jump_en(deco_jump_en),
+        .jump_addr(deco_jump_addr),
+        .mem_access(instr_mem_access),
+        .pause_exec(deco_pause_exec),
+        .new_flags(deco_new_flags)
+    );
     
     
-    assign mem_sel = mem_op_pending;
+    assign mem_sel = instr_mem_access;
     assign op_part_addr = pc_cur_count;
-    assign pc_enable = !mem_op_pending;
+    assign pc_enable = !instr_mem_access;
     
     
     always @(clk) begin
-        if (!mem_op_pending) begin
-            op_part_3 <= op_part_data;
-            op_part_2 <= op_part_3;
-            op_part_1 <= op_part_2;
-            op_part_0 <= op_part_1;
+        if (!instr_mem_access) begin
+            op_part[3] <= op_part_data;
+            op_part[2] <= op_part[3];
+            op_part[1] <= op_part[2];
+            op_part[0] <= op_part[1];
         end
         
     end
diff --git a/eight_bit_console/eight_bit_console.xpr b/eight_bit_console/eight_bit_console.xpr
index 95cc6ba..8312345 100644
--- a/eight_bit_console/eight_bit_console.xpr
+++ b/eight_bit_console/eight_bit_console.xpr
@@ -129,22 +129,6 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PSRCDIR/sources_1/new/bootloader_rom.v">
-        <FileInfo>
-          <Attr Name="AutoDisabled" Val="1"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="implementation"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
-      <File Path="$PSRCDIR/sources_1/new/io_controller.v">
-        <FileInfo>
-          <Attr Name="AutoDisabled" Val="1"/>
-          <Attr Name="UsedIn" Val="synthesis"/>
-          <Attr Name="UsedIn" Val="implementation"/>
-          <Attr Name="UsedIn" Val="simulation"/>
-        </FileInfo>
-      </File>
       <File Path="$PSRCDIR/sources_1/new/cpu.v">
         <FileInfo>
           <Attr Name="AutoDisabled" Val="1"/>

From 00cf3ad8070cd0b9c3d24bf0788e7a37b8243010 Mon Sep 17 00:00:00 2001
From: Carson Bush <hyperdriveguy@gmail.com>
Date: Fri, 5 Apr 2024 23:59:20 -0600
Subject: [PATCH 5/7] Add decoder logic

---
 .../eight_bit_console.cache/wt/project.wpc    |   2 +-
 .../sources_1/new/fetch_execute.sv            |   5 +-
 .../sources_1/new/instruction_decoder.sv      | 159 +++++++++++++++++-
 3 files changed, 156 insertions(+), 10 deletions(-)

diff --git a/eight_bit_console/eight_bit_console.cache/wt/project.wpc b/eight_bit_console/eight_bit_console.cache/wt/project.wpc
index 94ba00c..101cd88 100644
--- a/eight_bit_console/eight_bit_console.cache/wt/project.wpc
+++ b/eight_bit_console/eight_bit_console.cache/wt/project.wpc
@@ -1,3 +1,3 @@
 version:1
-6d6f64655f636f756e7465727c4755494d6f6465:12
+6d6f64655f636f756e7465727c4755494d6f6465:14
 eof:
diff --git a/eight_bit_console/eight_bit_console.srcs/sources_1/new/fetch_execute.sv b/eight_bit_console/eight_bit_console.srcs/sources_1/new/fetch_execute.sv
index e070170..421b69a 100644
--- a/eight_bit_console/eight_bit_console.srcs/sources_1/new/fetch_execute.sv
+++ b/eight_bit_console/eight_bit_console.srcs/sources_1/new/fetch_execute.sv
@@ -56,8 +56,6 @@ module fetch_execute(
     // Decode logic
     logic [31:0] deco_op_parts = {op_part[0], op_part[1], op_part[2], op_part[3]};
     logic [7:0] deco_cur_flags;
-    logic [1:0] deco_op_length;
-    logic deco_is_dirty_op;
     logic [3:1] deco_part_dirty;
     logic deco_jump_en;
     logic [15:0] deco_jump_addr;
@@ -68,8 +66,7 @@ module fetch_execute(
     instruction_decoder inst_decode (
         .op_parts(deco_op_parts),
         .cur_flags(deco_cur_flags),
-        .op_length(deco_op_length),
-        .is_dirty_op(deco_is_dirty_op),
+        .cur_op_dirty(dirty_pipe[0]),
         .part_dirty(deco_part_dirty),
 
         // These are directly routed to the top level
diff --git a/eight_bit_console/eight_bit_console.srcs/sources_1/new/instruction_decoder.sv b/eight_bit_console/eight_bit_console.srcs/sources_1/new/instruction_decoder.sv
index 361dc07..1e39e34 100644
--- a/eight_bit_console/eight_bit_console.srcs/sources_1/new/instruction_decoder.sv
+++ b/eight_bit_console/eight_bit_console.srcs/sources_1/new/instruction_decoder.sv
@@ -18,21 +18,170 @@
 // Additional Comments:
 // 
 //////////////////////////////////////////////////////////////////////////////////
+typedef enum logic [2:0] {
+    CC_NONE = 3'h0,       // No condition applied
+    CC_CARRY = 3'h1,      // Handle carryout
+    CC_ZERO = 3'h2,       // Check if equal
+    CC_SIGN = 3'h3,       // Check negative signed
+    CC_PARITY = 3'h4,     // Check odd
+    CC_OVERFLOW = 3'h5   // Handle overflow
+} ConditionCode;
 
+typedef enum logic [2:0] {
+    MIN_OP_NOP = 4'h0,         // No operation
+    MIN_OP_RET = 4'h1,         // Jump back to popped address from stack
+    MIN_OP_EI = 4'h2,          // Enable interrupt
+    MIN_OP_DI = 4'h3,          // Disable interrupt
+    MIN_OP_WAIT = 4'h4,        // CPU in wait mode (stop execution)
+    MIN_OP_INC_R5 = 4'h5,      // Increment accumulator
+    MIN_OP_PUSH_R5 = 4'h6,    // Push accumulator to stack
+    MIN_OP_POP_R5 = 4'h7      // Pop accumulator from stack
+} MinOpcode;
+
+typedef enum logic [6:0] {
+    // Memory Operations
+    OP_MOV = 7'h00,       // Moves values between registers
+    OP_LD = 7'h01,        // Fetch data from memory at a given address
+    OP_STR = 7'h02,       // Store data to memory at a given address
+    OP_MOVW = 7'h03,      // Moves values between registers in wide bit mode
+    OP_LDI = 7'h04,       // Load immediate into register
+    OP_STI = 7'h05,       // Load immediate into memory location
+    OP_PUSH = 7'h06,      // Pushes contents of a register onto the stack
+    OP_POP = 7'h07,       // Pop contents of the stack into a register
+
+    // Control Flow Operations
+    OP_JP = 7'h08,        // Jump to a given immediate address
+    OP_JMP = 7'h09,       // Jump to address pointed to by a register pair
+    OP_CALL = 7'h0A,      // Push next instruction location onto the stack, jump to given immediate address
+    OP_CALR = 7'h0B,      // Push next instruction location onto the stack, jump to address pointed to by a register pair
+    OP_RET_CTRL = 7'h01,  // Jump back to popped address from stack
+
+    // ALU Operations
+    OP_ADD = 7'h10,       // d <= op1 + op2
+    OP_SUB = 7'h11,       // d <= op1 - op2
+    OP_MUL = 7'h12,       // d <= op1 * op2
+    OP_DIV = 7'h13,       // d <= op1 / op2
+    OP_XOR = 7'h14,       // d <= op1 xor op2
+    OP_OR = 7'h15,        // d <= op1 or op2
+    OP_AND = 7'h16,       // d <= op1 and op2
+    OP_LSL = 7'h17,       // d <= op1 << op2
+    OP_ASL = 7'h17,       // d <= op1 << op2
+    OP_LSR = 7'h18,       // d <= op1 >> op2 (Logical)
+    OP_ASR = 7'h19,       // d <= op1 >> op2 (Arithmetic)
+    OP_ADDW = 7'h1A,      // d <= op1 + op2 (16-bit)
+    OP_SUBW = 7'h1B,      // d <= op1 - op2 (16-bit)
+
+    // Special Operations
+    OP_COM = 7'h1C,       // r <= ~r
+    OP_INC = 7'h1D,       // r <= r + 1
+    OP_DEC = 7'h1E,       // r <= r - 1
+    OP_INCW = 7'h1F,      // r <= r + 1
+    OP_DECW = 7'h20,      // r <= r - 1
+    OP_CP = 7'h21,        // Set flags based on comparison
+    OP_CPW = 7'h22,       // Set flags based on comparison
+    OP_LEA = 7'h23       // Load effective address
+} Opcode;
+
+typedef enum logic {
+    OPTYPE_MIN = 0,
+    OPTYPE_MAX = 1
+} OpType;
+
+typedef enum logic [3:0] {
+    ALU_ADD = 4'h0,
+    ALU_SUB = 4'h1,
+    ALU_MUL = 4'h2,
+    ALU_DIV = 4'h3,
+    ALU_XOR = 4'h4,
+    ALU_OR = 4'h5,
+    ALU_AND = 4'h6,
+    ALU_LSL = 4'h7,
+    ALU_ASL = 4'h7,
+    ALU_LSR = 4'h8,
+    ALU_ASR = 4'h9,
+    ALU_COM = 4'ha,
+    ALU_INC = 4'hb,
+    ALU_DEC = 4'hc,
+    ALU_CP = 4'hd
+} AluOp;
 
 module instruction_decoder(
     input [31:0] op_parts,
     input [7:0] cur_flags,
-    input [1:0] op_length,
-    input is_dirty_op,
+    input cur_op_dirty,
     output [3:1] part_dirty,
-    output [11:0] sel_reg,
+    output [3:0] dest_sel_reg,
+    output [3:0] a_sel_reg,
+    output [3:0] b_sel_reg,
     output [3:0] sel_alu,
     output bit_mode,
     output jump_en,
     output [15:0] jump_addr,
-    output mem_access,
+    output data_mem_access,
     output pause_exec,
-    output [7:0] new_flags
+    output no_op,
+    output enable_int,
+    output disable_int
     );
+    
+    logic cond_inverse = op_parts[31];
+    logic [2:0] cond_code = op_parts[30:28];
+    logic op_type = op_parts[27];
+    logic [2:0] min_op_code = op_parts[26:24];
+    logic [6:0] full_op_code = op_parts[26:20];
+    logic [3:0] dest_reg_sel = op_parts[19:16];
+    logic [3:0] operand_a_reg_sel = op_parts[15:12];
+    logic [3:0] operand_b_reg_sel = op_parts[11:8];
+    logic [3:0] lea_shift_mul = op_parts[7:4];
+    logic [7:0] immed_offset = op_parts[7:0];
+    logic [15:0] jump_target = op_parts[15:0];
+    
+    // Condition checking logic
+    logic cond_met;
+    
+    always_comb begin
+        if (cond_inverse)
+            case (cond_code)
+                CC_NONE: cond_met = 0;
+                CC_CARRY: cond_met = !cur_flags[0];
+                CC_ZERO: cond_met = !cur_flags[1];
+                CC_SIGN: cond_met = !cur_flags[2];
+                CC_PARITY: cond_met = !cur_flags[3];
+                CC_OVERFLOW: cond_met = !cur_flags[4];
+                default: cond_met = 0;
+            endcase
+        else
+            case (cond_code)
+                CC_NONE: cond_met = 1;
+                CC_CARRY: cond_met = cur_flags[0];
+                CC_ZERO: cond_met = cur_flags[1];
+                CC_SIGN: cond_met = cur_flags[2];
+                CC_PARITY: cond_met = cur_flags[3];
+                CC_OVERFLOW: cond_met = cur_flags[4];
+                default: cond_met = 1;
+            endcase
+    end
+    
+    assign no_op = cur_op_dirty | !cond_met | (min_op_code == MIN_OP_NOP);
+    
+    // Operation to output decoding
+    always_comb begin
+        if (op_type == OPTYPE_MIN)
+            case (min_op_code)
+                MIN_OP_RET:
+                MIN_OP_EI: enable_int = 1;
+                MIN_OP_DI: disable_int = 1;
+                MIN_OP_WAIT: pause_exec = 1;
+                MIN_OP_INC_R5: begin
+                    sel_alu = ALU_INC;
+                    dest_sel_reg = 5;
+                    a_sel_reg = 5;
+                    bit_mode = 0;
+                end
+            endcase
+    end
+    
+    
+    
 endmodule
+

From cb9a7518772364d84204116565e8dfb02a0a5d5c Mon Sep 17 00:00:00 2001
From: Carson Bush <hyperdriveguy@gmail.com>
Date: Sun, 7 Apr 2024 21:24:20 -0600
Subject: [PATCH 6/7] Begin the operation decoding

---
 .../eight_bit_console.cache/wt/project.wpc    |   2 +-
 .../sources_1/new/instruction_decoder.sv      | 226 ++++++++++++++++--
 2 files changed, 203 insertions(+), 25 deletions(-)

diff --git a/eight_bit_console/eight_bit_console.cache/wt/project.wpc b/eight_bit_console/eight_bit_console.cache/wt/project.wpc
index 101cd88..b3f0e4d 100644
--- a/eight_bit_console/eight_bit_console.cache/wt/project.wpc
+++ b/eight_bit_console/eight_bit_console.cache/wt/project.wpc
@@ -1,3 +1,3 @@
 version:1
-6d6f64655f636f756e7465727c4755494d6f6465:14
+6d6f64655f636f756e7465727c4755494d6f6465:15
 eof:
diff --git a/eight_bit_console/eight_bit_console.srcs/sources_1/new/instruction_decoder.sv b/eight_bit_console/eight_bit_console.srcs/sources_1/new/instruction_decoder.sv
index 1e39e34..b2c98e1 100644
--- a/eight_bit_console/eight_bit_console.srcs/sources_1/new/instruction_decoder.sv
+++ b/eight_bit_console/eight_bit_console.srcs/sources_1/new/instruction_decoder.sv
@@ -54,7 +54,6 @@ typedef enum logic [6:0] {
     OP_JMP = 7'h09,       // Jump to address pointed to by a register pair
     OP_CALL = 7'h0A,      // Push next instruction location onto the stack, jump to given immediate address
     OP_CALR = 7'h0B,      // Push next instruction location onto the stack, jump to address pointed to by a register pair
-    OP_RET_CTRL = 7'h01,  // Jump back to popped address from stack
 
     // ALU Operations
     OP_ADD = 7'h10,       // d <= op1 + op2
@@ -99,29 +98,63 @@ typedef enum logic [3:0] {
     ALU_ASL = 4'h7,
     ALU_LSR = 4'h8,
     ALU_ASR = 4'h9,
-    ALU_COM = 4'ha,
+    ALU_NOT = 4'ha,
     ALU_INC = 4'hb,
     ALU_DEC = 4'hc,
     ALU_CP = 4'hd
 } AluOp;
 
+typedef enum logic [3:0] {
+    REG_R0 = 4'h0,
+    REG_R1 = 4'h1,
+    REG_R2 = 4'h2,
+    REG_R3 = 4'h3,
+    REG_R4 = 4'h4,
+    REG_R5 = 4'h5,
+    REG_R6 = 4'h6,
+    REG_R7 = 4'h7,
+    REG_R8 = 4'h8,
+    REG_R9 = 4'h9,
+    REG_RA = 4'ha,
+    REG_RB = 4'hb,
+    REG_RC = 4'hc,
+    REG_RD = 4'hd,
+    REG_RE = 4'he,
+    REG_RF = 4'hf,
+    REG_RIH = 4'hc,
+    REG_RIL = 4'hd,
+    REG_RSH = 4'he,
+    REG_RSL = 4'hf,
+    REG_RIP = 4'hc,
+    REG_RSP = 4'he
+} RegSelect;
+
+typedef enum logic {
+    SEL_MEM_EXEC = 0,
+    SEL_MEM_REG = 1
+} MemSelect;
+
 module instruction_decoder(
     input [31:0] op_parts,
     input [7:0] cur_flags,
     input cur_op_dirty,
-    output [3:1] part_dirty,
-    output [3:0] dest_sel_reg,
-    output [3:0] a_sel_reg,
-    output [3:0] b_sel_reg,
-    output [3:0] sel_alu,
-    output bit_mode,
-    output jump_en,
-    output [15:0] jump_addr,
-    output data_mem_access,
-    output pause_exec,
-    output no_op,
-    output enable_int,
-    output disable_int
+    output logic reg_we,
+    output logic [3:0] dest_sel_reg,
+    output logic [3:0] a_sel_reg,
+    output logic [3:0] b_sel_reg,
+    output logic [3:0] sel_alu,
+    output logic bit_mode,
+    output logic jump_en,
+    output logic [15:0] jump_addr,
+    output logic data_mem_read,
+    output logic data_mem_write,
+    output logic no_op,
+    output logic pop_jump,
+    output logic enable_int,
+    output logic disable_int,
+    output logic stop_exec,
+    output logic ld_immediate,
+    output logic [7:0] immediate
     );
     
     logic cond_inverse = op_parts[31];
@@ -132,6 +165,7 @@ module instruction_decoder(
     logic [3:0] dest_reg_sel = op_parts[19:16];
     logic [3:0] operand_a_reg_sel = op_parts[15:12];
     logic [3:0] operand_b_reg_sel = op_parts[11:8];
+    logic [7:0] immed_mem_src = op_parts[15:8];
     logic [3:0] lea_shift_mul = op_parts[7:4];
     logic [7:0] immed_offset = op_parts[7:0];
     logic [15:0] jump_target = op_parts[15:0];
@@ -162,26 +196,170 @@ module instruction_decoder(
             endcase
     end
     
-    assign no_op = cur_op_dirty | !cond_met | (min_op_code == MIN_OP_NOP);
+    logic do_no_op = 0;
+    
+    assign no_op = cur_op_dirty | !cond_met | (do_no_op);
     
     // Operation to output decoding
     always_comb begin
+        reg_we = 0;
+        dest_sel_reg = 0;
+        a_sel_reg = 0;
+        b_sel_reg = 0;
+        sel_alu = 0;
+        bit_mode = 0;
+        jump_en = 0;
+        jump_addr = 0;
+        data_mem_read = 0;
+        data_mem_write = 0;
+        do_no_op = 0;
+        pop_jump = 0;
+        enable_int = 0;
+        disable_int = 0;
+        stop_exec = 0;
+        ld_immediate 0;
+        immediate = 0;
         if (op_type == OPTYPE_MIN)
             case (min_op_code)
-                MIN_OP_RET:
+                MIN_OP_NOP: do_no_op = 1;
+                MIN_OP_RET: pop_jump = 1;
                 MIN_OP_EI: enable_int = 1;
                 MIN_OP_DI: disable_int = 1;
-                MIN_OP_WAIT: pause_exec = 1;
+                MIN_OP_WAIT: stop_exec = 1;
                 MIN_OP_INC_R5: begin
+                    dest_sel_reg = 4'h5;
+                    a_sel_reg = 4'h5;
                     sel_alu = ALU_INC;
-                    dest_sel_reg = 5;
-                    a_sel_reg = 5;
-                    bit_mode = 0;
+                    reg_we = 1;
                 end
+                MIN_OP_PUSH_R5: begin
+                    data_mem_write = SEL_MEM_REG;
+                    a_sel_reg = 4'h5;
+                end
+                MIN_OP_POP_R5: begin
+                    data_mem_read = SEL_MEM_REG;
+                    a_sel_reg = 4'h5;
+                end
+                default: do_no_op = 1;
             endcase
+        else
+             case (full_op_code)
+                OP_MOV: begin
+                    dest_sel_reg = dest_reg_sel;
+                    a_sel_reg = operand_a_reg_sel;
+                    reg_we = 1;
+                end
+                OP_LD: begin
+                    dest_sel_reg = dest_reg_sel;
+                    a_sel_reg = operand_a_reg_sel;
+                    data_mem_read = SEL_MEM_REG;
+                    reg_we = 1;
+                end
+                OP_STR: begin
+                    a_sel_reg = dest_reg_sel;
+                    b_sel_reg = operand_a_reg_sel;
+                    data_mem_write = SEL_MEM_REG;
+                end
+                OP_MOVW: begin
+                    dest_sel_reg = dest_reg_sel;
+                    a_sel_reg = operand_a_reg_sel;
+                    reg_we = 1;
+                    bit_mode = 1;
+                end
+                OP_LDI: begin
+                    dest_sel_reg = dest_reg_sel;
+                    ld_immediate = 1;
+                    reg_we = 1;
+                    immediate = immed_mem_src;
+                end
+                OP_PUSH: begin
+                    a_sel_reg = dest_reg_sel;
+                    b_sel_reg = REG_RSP;
+                    data_mem_write = SEL_MEM_REG;
+                end
+                OP_POP: begin
+                    dest_sel_reg = dest_reg_sel;
+                    a_sel_reg = REG_RSP;
+                    data_mem_read = SEL_MEM_REG;
+                    reg_we = 1;
+                end
+                OP_JP: begin
+
+                end
+                OP_JMP: begin
+
+                end
+                OP_CALL: begin
+
+                end
+                OP_CALR: begin
+
+                end
+                OP_ADD: begin
+
+                end
+                OP_SUB: begin
+
+                end
+                OP_MUL: begin
+
+                end
+                OP_DIV: begin
+
+                end
+                OP_XOR: begin
+
+                end
+                OP_OR: begin
+
+                end
+                OP_AND: begin
+
+                end
+                OP_LSL: begin
+
+                end
+                OP_ASL: begin
+
+                end
+                OP_LSR: begin
+
+                end
+                OP_ASR: begin
+
+                end
+                OP_ADDW: begin
+
+                end
+                OP_SUBW: begin
+
+                end
+                OP_COM: begin
+
+                end
+                OP_INC: begin
+
+                end
+                OP_DEC: begin
+
+                end
+                OP_INCW: begin
+
+                end
+                OP_DECW: begin
+
+                end
+                OP_CP: begin
+
+                end
+                OP_CPW: begin
+
+                end
+                OP_LEA: begin
+
+                end
+             endcase
     end
-    
-    
-    
+
 endmodule
 

From 493f5d5ee2828345c6058f25b37079f642a76ed9 Mon Sep 17 00:00:00 2001
From: Carson Bush <hyperdriveguy@gmail.com>
Date: Tue, 9 Apr 2024 22:26:19 -0600
Subject: [PATCH 7/7] Fix error

---
 eight_bit_console/eight_bit_console.cache/wt/project.wpc        | 2 +-
 .../eight_bit_console.srcs/sources_1/new/instruction_decoder.sv | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/eight_bit_console/eight_bit_console.cache/wt/project.wpc b/eight_bit_console/eight_bit_console.cache/wt/project.wpc
index b3f0e4d..f16dd14 100644
--- a/eight_bit_console/eight_bit_console.cache/wt/project.wpc
+++ b/eight_bit_console/eight_bit_console.cache/wt/project.wpc
@@ -1,3 +1,3 @@
 version:1
-6d6f64655f636f756e7465727c4755494d6f6465:15
+6d6f64655f636f756e7465727c4755494d6f6465:16
 eof:
diff --git a/eight_bit_console/eight_bit_console.srcs/sources_1/new/instruction_decoder.sv b/eight_bit_console/eight_bit_console.srcs/sources_1/new/instruction_decoder.sv
index b2c98e1..72f175b 100644
--- a/eight_bit_console/eight_bit_console.srcs/sources_1/new/instruction_decoder.sv
+++ b/eight_bit_console/eight_bit_console.srcs/sources_1/new/instruction_decoder.sv
@@ -217,7 +217,7 @@ module instruction_decoder(
         enable_int = 0;
         disable_int = 0;
         stop_exec = 0;
-        ld_immediate 0;
+        ld_immediate = 0;
         immediate = 0;
         if (op_type == OPTYPE_MIN)
             case (min_op_code)