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Verilator for testing #9

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Nic30 opened this issue Feb 25, 2019 · 0 comments
Open

Verilator for testing #9

Nic30 opened this issue Feb 25, 2019 · 0 comments

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@Nic30
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Nic30 commented Feb 25, 2019

In future it will be very usefull to simulate generated circuits in verilator. However this will take some time. But for now it would be very useful if we can just check the generated code for the syntax correctness. The Verilator is a good tool for this job.
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