diff --git a/sys/src/9/amd64/archamd64.c b/sys/src/9/amd64/archamd64.c
index 30e8cf5dbe..9118f6dee8 100644
--- a/sys/src/9/amd64/archamd64.c
+++ b/sys/src/9/amd64/archamd64.c
@@ -119,7 +119,7 @@ cpuidhz_hypervisor()
 static int64_t
 cpuidhz(uint32_t *info0, uint32_t *info1, CpuHypervisor hypervisor)
 {
-	int f, r;
+	int f = -1, r;
 	int64_t hz;
 	uint64_t msr;
 	char *vendorid;
@@ -191,6 +191,14 @@ cpuidhz(uint32_t *info0, uint32_t *info1, CpuHypervisor hypervisor)
 			hz = ((rdmsr(0x2a)>>22) & 0x1f)*100 * 1000000ll;
 //print("msr 2a is 0x%x >> 22 0x%x\n", rdmsr(0x2a), rdmsr(0x2a)>>22);
 			break;
+		case 0x000306a0:		/* i7,5,3 3xxx */
+			// reading msr 0xcd gets a GPF on this CPU.
+			// per the coreboot irc:
+			// <icon[m]> rminnich: if you need the base for the core's clock multiplier, it's 100MHz since sandybridge
+			// Which, going by the Good Book (35-46 volume 3C) is index 5.
+			f = 5;
+			// This will likely be true of many of the CPUs below. FSB did a *long* time ago.
+			// fallthrough
 		case 0x000006e0:		/* Core Duo */
 		case 0x000006f0:		/* Core 2 Duo/Quad/Extreme */
 		case 0x00000660:		/* kvm over i5 */
@@ -203,7 +211,6 @@ cpuidhz(uint32_t *info0, uint32_t *info1, CpuHypervisor hypervisor)
 		case 0x000106e0:		/* i7,5,3 8xx */
 		case 0x000206a0:		/* i7,5,3 2xxx */
 		case 0x000206c0:		/* i7,5,3 4xxx */
-		case 0x000306a0:		/* i7,5,3 3xxx */
 		case 0x000306f0:		/* i7,5,3 5xxx */
 		case 0x000506e0:		/* i7,5,3 6xxx */
 		case 0x00050650:		/* i9 7900X */
@@ -221,7 +228,8 @@ cpuidhz(uint32_t *info0, uint32_t *info1, CpuHypervisor hypervisor)
 				msr = 0;
 				r = rdmsr(0x2a) & 0x1f;
 			}
-			f = rdmsr(0xcd) & 0x07;
+			if (f < 0)
+				f = rdmsr(0xcd) & 0x07;
 //iprint("rdmsr Intel: %d\n", rdmsr(0x2a));
 //iprint("Intel msr.lo %d\n", r);
 //iprint("Intel msr.hi %d\n", f);