-
Notifications
You must be signed in to change notification settings - Fork 1
/
STi5518_RegisterDB.h
1254 lines (1251 loc) · 82.8 KB
/
STi5518_RegisterDB.h
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
//////////////////////////////////////////////////////////////////////////
// 16/12/2011 MrCODE
// Include file for a more descriptive system added to "st20emu2.exe"
//////////////////////////////////////////////////////////////////////////
/****************/
/* BASE ADDRESS */
/****************/
#define VideoBaseAddress 0x00000000 // MPEG video decoder
#define ClockGenBaseAddress 0x00000100 // Clock Generator
#define AudioBaseAddress 0x00000200 // Audio decoder
#define SubPictureBaseAddress 0x00000400 // Sub-picture decoder
#define DencBaseAddress 0x00000600 // Digital Encoder
#define MPEGCtrlBaseAddress 0x00000E00 // MPEG Control (0xE00 0xE01)
#define EMIBaseAddress 0x00002000 // Programmable CPU Memory Interface
#define CacheBaseAddress 0x00004000 // Cache configuration
#define IntControllerBase 0x20000000 // Interrupt controller
#define DKEYBaseAddress 0x20002500 // Descrambling KEYS
#define LPCBaseAddress 0x20000400 // Low power and Watchdog
#define ASC0BaseAddress 0x20003000 // Asynchronous serial controller ASC0 / SmartCard 0
#define ASC1BaseAddress 0x20004000 // Asynchronous serial controller ASC1
#define ASC2BaseAddress 0x20005000 // Asynchronous serial controller ASC2
#define ASC3BaseAddress 0x20006000 // Asynchronous serial controller ASC3 / SmartCard 1
#define SSC0BaseAddress 0x20009000 // Synchronous serial controller SSC0
#define SSC1BaseAddress 0x2000A000 // Synchronous serial controller SSC1
#define PIO5BaseAddress 0x2000A100 // PIO port 5 controller
#define IRBBaseAddress 0x2000A200 // Infra red blaster
#define TTxtBaseAddress 0x2000A300 // Teletext
#define PWMBaseAddress 0x2000B000 // PWM and counter module
#define PIO0BaseAddress 0x2000C000 // PIO port 0 controller
#define PIO1BaseAddress 0x2000D000 // PIO port 1 controller
#define PIO2BaseAddress 0x2000E000 // PIO port 2 controller
#define PIO3BaseAddress 0x2000F000 // PIO port 3 controller
#define PIO4BaseAddress 0x20010000 // PIO port 4 controller
#define InterruptLevelBase 0x20011000 // Interrupt level controller
#define MPEGDMA0BaseAddress 0x20024000 // MPEGDMA controller
#define MPEGDMA1BaseAddress 0x20025000 // MPEGDMA controller
#define BMBaseAddress 0x20026000 // Block move DMA controller
#define ModemBaseAddress 0x20027000 // Modem control
#define MPEGDMA2BaseAddress 0x20030000 // LINK (SDAV MPEGDMA2) controller
#define LinkBaseAddress 0x20038000 // Link and front-end interface
typedef struct Register_Description{
char* regname; //REGISTER
unsigned long addr; //Address
char bits; //How many bits in the register
char* access; //Type of access allowed
char* description;//Short description for the register
}REGDESCR;
// The Reg's Database
static REGDESCR DBREGS_Entry[] = {
/************************/
/* VIDEO DECODER (VID) */
/************************/
{"VID_CFG_MCF",0x00000000 ,7,"R/W","Memory refresh interval"},
{"VID_CFG_CCF",0x00000001 ,7,"R/W","Chip configuration"},
{"VID_CTL",0x00000002,5,"R/W","Decoding Control"},
{"VID_TIS",0x00000003,6,"W","Task Instruction"},
{"VID_PFH",0x00000004,8,"R/W","Picture F-parameters Horizontal"},
{"VID_PFV",0x00000005,8,"R/W","Picture F-parameters Vertical"},
{"VID_PPR1",0x00000006,7,"R/W","Picture Parameters 1"},
{"VID_PPR2",0x00000007,7,"R/W","Picture Parameters 2"},
//SDRAM BLOCK MOVE (USD)
{"USD_BMS_15_0",0x00000009,8,"R/W","Block move size"},
//----------------------
{"VID_DFP_14_8",0x0000000C,7,"R/W","Displayed Luma Frame Pointer"},
{"VID_DFP_7_0",0x0000000D,8,"R/W","Displayed Luma Frame Pointer"},
{"VID_RFP_14_8",0x0000000E,7,"R/W","Reconstructed Frame Pointer"},
{"VID_RFP_7_0",0x0000000F,8,"R/W","Reconstructed Frame Pointer"},
{"VID_FFP_13_8",0x00000010,6,"R/W","Forward Luma Frame Pointer"},
{"VID_FFP_7_0",0x00000011,8,"R/W","Forward Luma Frame Pointer"},
{"VID_BFP_14_8",0x00000012,7,"R/W","Backward Frame Pointer"},
{"VID_BFP7_0",0x00000013,8,"R/W","Backward Frame Pointer"},
{"VID_VBG_14_8",0x00000014,7,"R/W","Start of Video Bit Buffer"},
{"VID_VBG_7_0",0x00000015,8,"R/W","Start of Video Bit Buffer"},
{"VID_VBL_14_8",0x00000016,7,"R","Video Bit Buffer Level"},
{"VID_VBL_7_0",0x00000017,8,"R","Video Bit Buffer Level"},
{"VID_VBS_14_8",0x00000018,7,"R/W","Video Bit Buffer Stop"},
{"VID_VBS_7_0",0x00000019,8,"R/W","Video Bit Buffer Stop"},
{"VID_VBT_14_8",0x0000001A,7,"R/W","Video Bit Buffer Threshold"},
{"VID_VBT_7_0",0x0000001B,8,"R/W","Video Bit Buffer Threshold"},
{"VID_ABG_14_8",0x0000001C,7,"R/W","Start of audio bit buffer"},
{"VID_ABG_7_0",0x0000001D,8,"R/W","Start of audio bit buffer"},
{"VID_ABL_14_8",0x0000001E,7,"R","Audio Bit Buffer Level"},
{"VID_ABL_7_0",0x0000001F,8,"R","Audio Bit Buffer Level"},
{"VID_ABS_14_8",0x00000020,7,"R/W","Audio Bit Buffer Stop"},
{"VID_ABS_7_0",0x00000021,8,"R/W","Audio Bit Buffer Stop"},
{"VID_ABT_14_8",0x00000022,7,"R/W","Audio Bit Buffer Threshold"},
{"VID_ABT_7_0",0x00000023,8,"R/W","Audio Bit Buffer Threshold"},
{"VID_DFS",0x00000024,15,"R/W","Serial Decoded Frame Size"},
{"VID_DFW",0x00000025,8,"R/W","Decoded Frame Width"},
{"VID_XFW",0x00000028,8,"R/W","Displayed Frame Width"},
//ON SCREEN DISPLAY (OSD)
{"OSD_OTP",0x0000002A,14,"Serial R/W","OSD Top Field Pointer"},
{"OSD_OBP",0x0000002B,14,"Serial R/W","OSD Bottom Field Pointer"},
//----------------------
{"VID_PAN_10_8",0x0000002C,3,"R/W","Pan/scan horizontal vector integer part"},
{"VID_PAN_7_0",0x0000002D,8,"R/W","Pan/scan horizontal vector integer part"},
{"VID_PTH_13_8",0x0000002E,6,"R/W","Panic threshold"},
{"VID_PTH_7_0",0x0000002F,8,"R/W","Panic threshold"},
{"VID_STL",0x00000030,2,"R/W","Launch start-code detector FIFO"},
{"VID_CWL",0x00000031,1,"R/W","Launch compress data write"},
{"VID_656",0x00000032,1,"R/W","Enable 656 mode"},
{"VID_SRA",0x00000035,1,"R/W","Audio Soft Reset"},
{"VID_CFG_DRC",0x00000038,6,"R/W","SDRAM configuration"},
{"VID_SRV",0x00000039,1,"R/W","Video Soft Reset"},
{"VID_CFG_GCF",0x0000003A,8,"R/W","General configuration"},
{"VID_STA",0x0000003B,8,"R","Status"},
{"VID_ITM",0x0000003C,8,"R/W","Interrupt Mask"},
{"VID_ITS",0x0000003D,8,"R","Interrupt Status"},
//ON SCREEN DISPLAY (OSD)
{"OSD_ACT",0x0000003E,7,"R/W","Active Signal"},
//----------------------
{"VID_TP_VID_LDP",0x0000003F,3,"R/W","Load Pointer"},
//PES PARSER (PES)
{"PES_CF1",0x00000040,7,"R/W","PES Audio Decoding Control"},
{"PES_CF2",0x00000041,8,"R/W","PES Video Parser Control"},
{"PES_TM1",0x00000042,8,"RO","DSM Trick Mode"},
{"PES_TM2",0x00000043,2,"RO","PES Parser Status"},
//----------------------
{"VID_YDS_8",0x00000046,1,"R/W","Display Y End"},
{"VID_YDS_7_0",0x00000047,8,"R/W","Display Y End"},
//PES PARSER (PES)
{"PES_TS_7_0",0x00000049,8,"RO","PES Time Stamps"},
{"PES_TS_15_8",0x0000004A,8,"RO","PES Time Stamps"},
{"PES_TS_23_16",0x0000004B,8,"RO","PES Time Stamps"},
{"PES_TS_31_24",0x0000004C,8,"RO","PES Time Stamps"},
{"PES_TS_32_TSA",0x0000004D,2,"RO","PES Time Stamps"},
//----------------------
{"VID_SPREAD",0x0000004E,20,"R/W","Serial Sub-picture Read Pointer"},
{"VID_SPWRITE",0x0000004F,20,"R/W","Serial Sub-picture Write Pointer"},
{"VID_SPB_10_8",0x00000050,3, "R/W","Sub-picture Buffer Begin"},
{"VID_SPB_7_0",0x00000051,8,"R/W","Sub-picture Buffer Begin"},
{"VID_SPE_11_8",0x00000052,4,"R/W","Sub-picture Buffer End"},
{"VID_SPE_7_0",0x00000053,8,"R/W","Sub-picture Buffer End"},
{"VID_TRF_12_8",0x00000056,4,"R/W","Temporal Reference"},
{"VID_TRF_7_0",0x00000057,8,"R/W","Temporal Reference"},
{"VID_DFC_14_8",0x00000058,7,"R/W","Displayed Chroma Frame Pointer"},
{"VID_DFC_7_0",0x00000059,8,"R/W","Displayed Chroma Frame Pointer"},
{"VID_RFC_14_8",0x0000005A,7,"R/W","Reconstructed Chroma Frame Pointer"},
{"VID_RFC_7_0",0x0000005B,8,"R/W","Reconstructed Chroma Frame Pointer"},
{"VID_FFC_14_8",0x0000005C,7,"R/W","Forward Chroma Frame Pointer"},
{"VID_FFC_7_0",0x0000005D,8,"R/W","Forward Chroma Frame Pointer"},
{"VID_BFC_14_8",0x0000005E,7,"R/W","Backward Chroma Pointer"},
{"VID_BFC_7_0",0x0000005F,8,"R/W","Backward Chroma Pointer"},
{"VID_ITM1",0x00000060,8,"R/W","Interrupt Mask"},
{"VID_ITM2",0x00000061,8,"R/W","Interrupt Mask"},
{"VID_ITS1",0x00000062,8,"R","Interrupt Status"},
{"VID_ITS2",0x00000063,8,"R","Interrupt Status"},
{"VID_STA2",0x00000064,8,"R","Status"},
{"VID_STA3",0x00000065,8,"R","Status"},
{"VID_HDF",0x00000066,16,"R","Serial Header Data FIFO"},
{"VID_CDCOUNT",0x00000067,24,"R","Serial Bit Buffer Input Counter"},
{"VID_SCDCOUNT",0x00000068,24,"R","Serial Bit Buffer Output Counter"},
{"VID_HDS",0x00000069,4,"R/W","Header Search"},
{"VID_LSO",0x0000006A,8,"R/W","SRC Luminance Offset"},
{"VID_LSR_7_0",0x0000006B,8,"R/W","SRC Luma Resolution"},
{"VID_CSO",0x0000006C,8,"R/W","SRC Chrominance Offset"},
{"VID_LSR_8",0x0000006D,1,"R/W","SRC Luma Resolution"},
{"VID_YDO_8",0x0000006E,1,"R/W","Display Y Offset"},
{"VID_YDO_7_0",0x0000006F,8,"R/W","Display Y Offset"},
{"VID_XDO_9_8",0x00000070,2,"R/W","Display X Offset"},
{"VID_XDO_7_0",0x00000071,8,"R/W","Display X Offset"},
{"VID_XDS_9_8",0x00000072,2,"R/W","Display X End"},
{"VID_XDS_7_0",0x00000073,8,"R/W","Display X End"},
{"VID_DCF1",0x00000074,6,"R/W","Display Configuration"},
{"VID_DCF2",0x00000075,6,"R/W","Display Configuration"},
{"VID_QMW",0x00000076,8,"W","Quantization Matrix Data"},
{"VID_TST",0x00000077,1,"R/W","Test register"},
{"VID_REV",0x00000078,8,"R","Device revision"},
{"VID_LCK",0x0000007B,1,"R/W","Locks registers VID_CFG_MCF, VID_CFG_CCF and VID_CFG_DRC"},
{"VID_TP_SCD_RD_15_8",0x00000081,8,"RO","Read only SCD pointer VLD load address"},
{"VID_TP_SCD_RD_7_0",0x00000082,8,"RO","Read only SCD pointer VLD load address"},
{"VID_TP_CD_RD_19_16",0x00000083,4,"RO","Read only CD pointer current address"},
{"VID_TP_CD_RD_15_8",0x00000084,8,"RO","Read only CD pointer current address"},
{"VID_TP_CD_RD_0_7",0x00000085,8,"RO","Read only CD pointer current address"},
{"VID_SCN",0x00000087,6,"R/W","Pan/Scan Vertical Vector"},
//SDRAM BLOCK MOVE (USD)
{"USD_BRP_19_16",0x00000088,4,"R/W","Memory Read Pointer"},
{"USD_BRP_15_8",0x00000089,8,"R/W","Memory Read Pointer"},
{"USD_BRP_7_0",0x0000008A,8,"R/W","Memory Read Pointer"},
{"USD_BWP_19_16",0x0000008C,4,"R/W","Memory write pointer"},
{"USD_BWP_15_8",0x0000008D,8,"R/W","Memory write pointer"},
{"USD_BWP_7_0",0x0000008E,8,"R/W","Memory write pointer"},
//----------------------
{"VID_OUT",0x00000090,4,"R/W","Output of 4:2:2 display"},
//ON SCREEN DISPLAY (OSD)
{"OSD_CFG",0x00000091,3,"R/W","OSD Configuration"},
{"OSD_BDW",0x00000092,6,"R/W","OSD Boundary Weight"},
//----------------------
{"VID_BCK_Y",0x00000098,8,"R/W","Background color Y"},
{"VID_BCK_V",0x00000099,8,"R/W","Background color V"},
{"VID_BCK_U",0x0000009A,8,"R/W","Background color U"},
{"VID_MWV",0x0000009B,8,"R/W","Color mix between background color and video"},
//SDRAM BLOCK MOVE (USD)
{"USD_BSK_19_16",0x000000A4,8,"R/W","Block skip"},
{"USD_BSK_15_8",0x000000A5,8,"R/W","Block skip"},
{"USD_BSK_7_0",0x000000A6,8,"R/W","Block skip"},
//----------------------
{"VID_TP_SCD_16",0x000000C0,1,"R/W","SCD pointer load address"},
{"VID_TP_SCD_15_8",0x000000C1,8,"R/W","SCD pointer load address"},
{"VID_TP_SCD_7_0",0x000000C2,8,"R/W","SCD pointer load address"},
{"VID_TP_VLD_RD_19_16",0x000000C3,4,"RO","Read only VLD pointer current address"},
{"VID_TP_VLD_RD_15_8",0x000000C4,8,"RO","Read only VLD pointer current address"},
{"VID_TP_VLD_RD_7_0",0x000000C5,8,"RO","Read only VLD pointer current address"},
{"VID_TP_CD_16",0x000000CA,1,"R/W","CD pointer load address bit 16"},
{"VID_TP_CD_15_8",0x000000CB,8,"R/W","CD pointer load address bits 15-8"},
{"VID_TP_CD_7_0",0x000000CC,8,"R/W","CD pointer load address bits 0-7"},
{"VID_TP_SCD_CURRENT_19_16",0x000000CD,4,"RO","Read only SCD pointer current address"},
{"VID_TP_SCD_CURRENT_15_8",0x000000CE,8,"RO","Read only SCD pointer current address"},
{"VID_TP_SCD_CURRENT",0x000000CF,8,"RO","Read only SCD pointer current address"},
{"VID_TP_VLD_15_8",0x000000D4,8,"R/W","VLD pointer load address"},
{"VID_TP_VLD_7_0",0x000000D5,8,"R/W","VLD pointer load address"},
{"VID_DCF",0x000000D6,3,"R/W","Display Configuration"},
{"VID_TP_CDLIMIT_16",0x000000E0,1,"R/W","CD write limit address"},
{"VID_TP_CDLIMIT_15_8",0x000000E1,8,"R/W","CD write limit address"},
{"VID_TP_CDLIMIT_7_0",0x000000E2,8,"R/W","CD write limit address"},
{"VID_CMOD",0x000000EA,40,"R/W","to->0x000000EE Configure chrominance of block-row"},
{"VID_YMOD",0x000000EF,40,"R/W","to->0x000000F3 Configure luminance of block-row"},
/*****************************/
/* CLOCK GENERATOR (CKG) */
/*****************************/
{"CKG_LPC_DIV",0x000001CE,8,"R/W","Low-power clock divider"},
{"CKG_PLL_CNT",0x000001CF,6,"R/W","Clock bypass PLL phase and PLL controller"},
{"CKG_CCAUD",0x000001D0,3,"R/W","Clock controller for audio clock"},
{"CKG_DIVAUD",0x000001D1,4,"R/W","Clock divider for audio clock"},
{"CKG_CCAUXDENC",0x000001D2,3,"R/W","Auxiliary clock controller"},
{"CKG_DIVAUXDENC",0x000001D3,4,"R/W","Denc Test clock divider"},
{"CKG_CCMCK",0x000001D4,3,"R/W","Clock controller for MEMCLK"},
{"CKG_DIVMCK",0x000001D5,4,"R/W","Clock divider for MEMCLK"},
{"CKG_SFREQSMC_SDIV",0x000001D6,3,"R/W","SDIV reg: SMC frequency synthesizer"},
{"CKG_SFREQSMC_PE0",0x000001D7,8,"R/W","PE reg (LSB): SMC frequency synthesizer"},
{"CKG_SFREQSMC_PE1",0x000001D8,8,"R/W","PE reg (MSB): SMC frequency synthesizer"},
{"CKG_SFREQSMC_MD",0x000001D9,5,"R/W","MD reg: SMC frequency synthesizer"},
{"CKG_SMC_CNT",0x000001DA,2,"R/W","Smart card clock control"},
{"CKG_CCDENC",0x000001DC,3,"R/W","Clock Control for the DENC Clock"},
{"CKG_CCST20",0x000001DD,3,"R/W","Clock controller for ST20 clock"},
{"CKG_DIVST20",0x000001DE,4,"R/W","Clock divider for ST20 clock"},
{"CKG_PREDIVPLL",0x000001DF,8,"R/W","Pre-divider ratio set-up of the PLL"},
{"CKG_FBKDIVPLL",0x000001E0,8,"R/W","Feedback divider ratio set-up of the PLL"},
{"CKG_POSTDIVPLL",0x000001E1,6,"R/W","Post divider ratio and lock detector"},
{"CKG_PLLSETUP",0x000001E2,6,"R/W","PLL start-up control and charge pump control"},
{"CKG_IDDQPAD_C",0x000001E3,4,"R/W","Iddq mode, I/O hsync, vsync"},
{"CKG_SFREQAUD_SDIV",0x000001E4,3,"R/W","SDIV reg: AUD frequency synthesizer"},
{"CKG_SFREQAUD_PE0",0x000001E5,8,"R/W","PE reg (LSB): AUD frequency synthesizer"},
{"CKG_SFREQAUD_PE1",0x000001E6,8,"R/W","PE reg (MSB): AUD frequency synthesizer"},
{"CKG_SFREQAUD_MD",0x000001E7,5,"R/W","MD reg: AUD frequency synthesizer"},
{"CKG_AUD_CNT",0x000001E8,1,"R/W","Sets audio frequency control through ST20 or MMDSP"},
{"CKG_SFREQAUX_SDIV",0x000001E9,3,"R/W","SDIV reg: AUX frequency synthesizer"},
{"CKG_SFREQAUX_PE0",0x000001EA,8,"R/W","PE reg (LSB): AUX frequency synthesizer"},
{"CKG_SFREQAUX_PE1",0x000001EB,8,"R/W","PE reg (MSB): AUX frequency synthesizer"},
{"CKG_SFREQAUX_MD",0x000001EC,5,"R/W","MD reg: AUX frequency synthesizer"},
{"CKG_AUX_CNT",0x000001ED,1,"R/W","Enable AUX frequency synthesizer"},
//Digital ENCoder (DENC)
{"DEN_YCOUT",0x000001F9,1,"R/W","Make YC data bus accessible on PIO4"},
/********************/
/* AUDIO DECODER */
/********************/
{"AUD_VERSION",0x00000200,8,"RO","Hardware version"},
{"AUD_IDENT",0x00000201,8,"RO","Identify"},
{"AUD_SFREQ",0x00000205,8,"R/W","Sampling frequency"},
{"AUD_EMPH",0x00000206,2,"R/W","Emphasis"},
{"AUD_INTEL_7_0",0x00000207,16,"R/W","Interrupt enable"},
{"AUD_INTE_15_8",0x00000208,16,"R/W","Interrupt enable"},
{"AUD_INT_7_0",0x00000209,16,"R/W","Interrupt"},
{"AUD_INT_15_8",0x0000020A,16,"R/W","Interrupt"},
{"AUD_SIN_SETUP",0x0000020C,8,"R/W","Input data setup"},
{"AUD_CAN_SETUP",0x0000020D,8,"R/W","A/D converter setup"},
{"AUD_ERROR",0x0000020F,8,"RO","ERROR code"},
{"AUD_SOFTRESET",0x00000210,8,"W","Soft reset"},
{"AUD_PLLPCM",0x00000212,3,"R/W","PCM PLL disable"},
{"AUD_PLAY",0x00000213,1,"R/W","Play"},
{"AUD_MUTE",0x00000214,1,"R/W","Mute"},
{"AUD_PLLMASK",0x00000218,1,"W","PCMCLK mask for half sampling frequency"},
{"AUD_SYNCSTATUS",0x00000240,4,"RO","Synchronization status"},
{"AUD_ANCCOUNT",0x00000241,8,"RO","Ancillary data"},
{"AUD_HEAD_31_24",0x00000242,8,"RO","HEADER 4 register"},
{"AUD_HEAD_23_16",0x00000243,8,"RO","HEADER 3 register"},
{"AUD_HEADLEN_15_8",0x00000244,8,"RO","Frame length"},
{"AUD_HEADLEN_7_0",0x00000245,8,"RO","Frame length"},
{"AUD_PTS_32",0x00000246,8,"R/W","PTS"},
{"AUD_PTS_31_24",0x00000247,8,"R/W","PTS"},
{"AUD_PTS_23_16",0x00000248,8,"R/W","PTS"},
{"AUD_PTS_15_8",0x00000249,8,"R/W","PTS"},
{"AUD_PTS_7_0",0x0000024A,8,"R/W","PTS"},
{"AUD_STREAMSEL",0x0000024C,3,"R/W","STREAM selection"},
{"AUD_DECODESEL",0x0000024D,5,"R/W","Decoding algorithm"},
{"AUD_VOLUME0",0x0000024E,8,"R/W","Left/right balance"},
{"AUD_PACKET_LOCK",0x0000024F,8,"R/W","Packet lock"},
{"AUD_AUDIO_ID_EN",0x00000250,8,"R/W","Enable audio ID"},
{"AUD_AUDIO_ID",0x00000251,8,"R/W","Audio ID"},
{"AUD_AUDIO_ID_EXT",0x00000252,8,"R/W","Audio extension"},
{"AUD_SYNC_LOCK",0x00000253,8,"R/W","SYNC lock"},
{"AUD_PCMDIVIDER",0x00000254,8,"R/W","Divider for PCM clock"},
{"AUD_PCM_CONF",0x00000255,7,"R/W","PCM configuration"},
{"AUD_PCM_CROSS",0x00000256,6,"R/W","Cross PCM channels"},
{"AUD_LDLY_TM_SPEED",0x00000257,8,"R/W","Left channel - Audio trick-mode speed"},
//{"AUD_TM_SPEED",0x00000257,8,"R/W","Audio trick-mode speed"},
{"AUD_RDLY",0x00000258,8,"R/W","Right channel"},
{"AUD_CDLY",0x00000259,8,"R/W","Centre channel"},
{"AUD_SUBDLY",0x0000025A,8,"R/W","Subwoofer channel"},
{"AUD_LSDLY",0x0000025B,8,"R/W","Left surround channel"},
{"AUD_RSDLY",0x0000025C,8,"R/W","Right surround channel"},
{"AUD_DLYUPDATE",0x0000025D,8,"R/W","PCM delay update"},
{"AUD_SPDIF_CMD",0x0000025E,8,"R/W","IEC958 control"},
{"AUD_SPDIF_CAT",0x0000025F,8,"R/W","Category code"},
{"AUD_SPDIF_CONF",0x00000260,8,"R/W","IEC958 PCMCLK divider"},
{"AUD_SPDIF_STATUS",0x00000261,7,"R/W","IEC status bit"},
{"AUD_PDEC",0x00000262,3,"R/W","Post decoder register"},
{"AUD_VOLUME1",0x00000263,8,"R/W","L/R surround balance"},
{"AUD_PL_AB",0x00000264,8,"R/W","Pro logic auto balance"},
{"AUD_PL_DWNX",0x00000265,8,"R/W","Pro logic decoder downmix"},
{"AUD_OCFG",0x00000266,4,"R/W","Output configuration"},
{"AUD_CHAN_IDX",0x00000267,3,"R/W","PCM scale factor"},
{"AUD_PCM_BTONE",0x00000268,8,"R/W","PCM beep tone frequency - Decode LFE for AC3 setup - Channel skip for MPEG setup"},
//{"AUD_DECODE_LFE",0x00000268,8,"R/W","Decode LFE for AC3 setup"},
//{"AUD_MP_SKIP_LFE",0x00000268,8,"R/W","Channel skip for MPEG setup"},
{"AUD_COMP_MOD",0x00000269,8,"R/W","Compression mode for AC3 setup - Program number for MPEG setup"},
//{"AUD_MP_PROG_NO",0x00000269,8,"R/W","Program number for MPEG setup"},
{"AUD_AC3_HDR",0x0000026A,8,"R/W","High dynamic range for AC3 setup - High dynamic range for MPEG setup"},
//{"AUD_MP_DRC",0x0000026A,1,"R/W","High dynamic range for MPEG setup"},
{"AUD_AC3_LDR",0x0000026B,8,"R/W","Low dynamic range"},
{"AUD_AC3_CRC_OFF",0x0000026C,8,"R/W","Repeat count for AC3 setup - CRC check-off for MPEG setup"},
//{"AUD_MP_CRC_OFF",0x0000026C,8,"R/W","CRC check-off for MPEG setup"},
{"AUD_AC3_KARAMODE",0x0000026D,8,"R/W","Karaoke downmix for AC3 setup - Multichannel for MPEG setup"},
//{"AUD_MP_MC_OFF",0x0000026D,2,"R/W","Multichannel for MPEG setup"},
{"AUD_AC3_DUALMODE",0x0000026E,8,"R/W","Dual downmix for AC3 setup - Dual downmix for MPEG setup"},
//{"AUD_MP_DUAL",0x0000026E,8,"R/W","Dual downmix for MPEG setup"},
{"AUD_AC3_DOWNMIX",0x0000026F,8,"R/W","Downmix for AC3 setup - Downmix for MPEG setup"},
//{"AUD_MP_DOWNMIX",0x0000026F,6,"R/W","Downmix for MPEG setup"},
{"AUD_DWSMODE",0x00000270,8,"R/W","Downsampling filter"},
{"AUD_SOFTVER",0x00000271,8,"R/W","Software version"},
{"AUD_RUN",0x00000272,1,"R/W","RUN decoding"},
{"AUD_SKIP_MUTE_CMD",0x00000273,5,"R/W","Skip or mute commands"},
{"AUD_SKIP_MUTE_VALUE",0x00000274,8,"R/W","Skip frames or mutes blocks of frame"},
{"AUD_SPDIF_REP_TIME",0x00000275,8,"R/W","IEC958 repetition time of a pause frame"},
{"AUD_STATUS0",0x00000276,8,"RO","AC-3 status register 0 - MPEG status register0"},
//{"AUD_MP_STATUS0",0x00000276,8,"RO","MPEG status register0"},
//{"AUD_LPCM_STATUS0",0x00000276,7,"RW","LPMC status register0"},
{"AUD_STATUS1",0x00000277,4,"RO","AC-3 status register 1 - MPEG status register1"},
//{"AUD_MP_STATUS1",0x00000277,4,"RO","MPEG status register1"},
//{"AUD_LPCM_STATUS1",0x00000277,7,"RW","LPMC status register1"},
{"AUD_STATUS2",0x00000278,8,"RO","AC-3 status register 2 - MPEG status register2"},
//{"AUD_MP_STATUS2",0x00000278,4,"RO","MPEG status register2"},
//{"AUD_LPCM_STATUS2",0x00000278,8,"RW","LPMC status register3"},
{"AUD_STATUS3",0x00000279,4,"RO","AC-3 status register 3 - MPEG status register3"},
//{"AUD_MP_STATUS3",0x00000279,8,"RO","MPEG status register3"},
{"AUD_STATUS4",0x0000027A,5,"RO","AC-3 status register 4 - MPEG status register4"},
//{"AUD_MP_STATUS4",0x0000027A,8,"RO","MPEG status register4"},
{"AUD_STATUS5",0x0000027B,8,"RO","AC-3 status register 5 - MPEG status register5"},
//{"AUD_MP_STATUS5",0x0000027B,8,"RO","MPEG status register5"},
{"AUD_STATUS6",0x0000027C,5,"RO","AC-3 status register 6"},
{"AUD_STATUS7",0x0000027D,8,"RO","AC-3 status register 7"},
{"AUD_SPDIF_LATENCY",0x0000027E ,8,"R/W","Latency value"},
{"AUD_SPDIF_DTDI",0x0000027F,8,"R/W","IEC958 data type information"},
/********************************/
/* Sub-picture decoder (SPD) */
/********************************/
{"SPD_CTL1",0x00000400,6,"R/W","Control Register 1"},
{"SPD_SPR",0x00000401,1,"R/W","Soft Reset"},
{"SPD_CTL2",0x00000402,2,"R/W","Control Register 2"},
{"SPD_LUT",0x00000403,8,"W","Main Lookup Table"},
{"SPD_XD0_9_8",0x00000404,2,"R/W","Sub-picture X Offset"},
{"SPD_XD0_7_0",0x00000405,8,"R/W","Sub-picture X Offset"},
{"SPD_YD0_1_9_8",0x00000406,2,"R/W","Sub-picture Y Offset"},
{"SPD_YD0_2_7_0",0x00000407,8,"R/W","Sub-picture Y Offset"},
{"SPD_HLSX_9_8",0x0000040C,2,"R/W","Highlight Region Start X"},
{"SPD_HLSX_7_0",0x0000040D,8,"R/W","Highlight Region Start X"},
{"SPD_HLSY_9_8",0x0000040E,2,"R/W","Highlight Region Start Y"},
{"SPD_HLSY_7_0",0x0000040F,8,"R/W","Highlight Region Start Y"},
{"SPD_HLEX_9_8",0x00000410,2,"R/W","Highlight Region End X"},
{"SPD_HLEX_7_0",0x00000411,8,"R/W","Highlight Region End X"},
{"SPD_HLEY_9_8",0x00000412,2,"R/W","Highlight Region End Y"},
{"SPD_HLEY_7_0",0x00000413,8,"R/W","Highlight Region End Y"},
{"SPD_HCOL",0x00000414,8,"R/W","Highlight Region Color"},
{"SPD_HCOL",0x00000415,8,"R/W","Highlight Region Color"},
{"SPD_HCN",0x00000416,8,"R/W","Highlight Region Contrast"},
{"SPD_HCN",0x00000417,8,"R/W","Highlight Region Contrast"},
{"SPD_SXD0_9_8",0x00000424,2,"R/W","Sub-picture Display Area"},
{"SPD_SXD0_7_0",0x00000425,8,"R/W","Sub-picture Display Area"},
{"SPD_SYD0_9_8",0x00000426,2,"R/W","Sub-picture Display Area"},
{"SPD_SYD0_7_0",0x00000427,8,"R/W","Sub-picture Display Area"},
{"SPD_SXD1_9_8",0x00000428,2,"R/W","Sub-picture Display Area"},
{"SPD_SXD1_7_0",0x00000429,8,"R/W","Sub-picture Display Area"},
{"SPD_SYD1_9_8",0x0000042A,2,"R/W","Sub-picture Display Area"},
{"SPD_SYD1_7_0",0x0000042B,8,"R/W","Sub-picture Display Area"},
/************************************/
/* Overlay graphics and text (OGT) */
/************************************/
{"OGT_CTL",SubPictureBaseAddress+0x000040,7,"R/W","Control register"},
{"OGT_LUT",SubPictureBaseAddress+0x000041,8,"R/W","Main look-up table"},
{"OGT_LUT_H1",SubPictureBaseAddress+0x000042,8,"R/W","Highlight 1 look-up table"},
{"OGT_LUT_H2",SubPictureBaseAddress+0x000043,8,"R/W","Highlight 2 look-up table"},
{"OGT_XDI",SubPictureBaseAddress+0x000044,2,"R/W","Active area horizontal position offset"},
{"OGT_XDI",SubPictureBaseAddress+0x000045,8,"R/W","Active area horizontal position offset"},
{"OGT_YDI",SubPictureBaseAddress+0x000046,2,"R/W","Active area vertical position offset"},
{"OGT_YDI",SubPictureBaseAddress+0x000047,8,"R/W","Active area vertical position offset"},
{"OGT_HL2XO",SubPictureBaseAddress+0x000048,2,"R/W","Active area vertical position offset"},
{"OGT_HL2XO",SubPictureBaseAddress+0x000049,8,"R/W","Active area vertical position offset"},
{"OGT_HL2YO",SubPictureBaseAddress+0x00004A,2,"R/W","Highlight 2 area, start Y"},
{"OGT_HL2YO",SubPictureBaseAddress+0x00004B,8,"R/W","Highlight 2 area, start Y"},
{"OGT_HL2XI",SubPictureBaseAddress+0x00004C,2,"R/W","Highlight 2 area, end X"},
{"OGT_HL2XI",SubPictureBaseAddress+0x00004D,8,"R/W","Highlight 2 area, end X"},
{"OGT_HL2YI",SubPictureBaseAddress+0x00004E,2,"R/W","Highlight 2 area, end Y"},
{"OGT_HL2YI",SubPictureBaseAddress+0x00004F,8,"R/W","Highlight 2 area, end Y"},
{"OGT_STAT",SubPictureBaseAddress+0x000050,2,"R","Status register"},
/****************************/
/* DIGITAL ENCODER (DEN) */
/****************************/
{"DEN_CFG0",0x00000600,8,"R/W","DENC configuration 0"},
{"DEN_CFG1",0x00000601,8,"R/W","DENC configuration 1"},
{"DEN_CFG2",0x00000602,8,"R/W","DENC configuration 2"},
{"DEN_CFG3",0x00000603,8,"R/W","DENC configuration 3"},
{"DEN_CFG4",0x00000604,8,"R/W","DENC configuration 4"},
{"DEN_CFG5",0x00000605,7,"R/W","DENC configuration 5"},
{"DEN_CFG6",0x00000606,8,"R/W","DENC configuration 6"},
{"DEN_CFG7",0x00000607,8,"R/W","DENC configuration 7"},
{"DEN_CFG8",0x00000608,8,"R/W","DENC configuration 8"},
{"DEN_STA",0x00000609,8,"R","DENC Status"},
{"DEN_IDFS1",0x0000060A,8,"R/W","DENC Increment for Digital Frequency Synthesizer"},
{"DEN_IDFS2",0x0000060B,8,"R/W","DENC Increment for Digital Frequency Synthesizer"},
{"DEN_IDFS3",0x0000060C,8,"R/W","DENC Increment for Digital Frequency Synthesizer"},
{"DEN_PDFS1",0x0000060D,8,"R/W","Static phase offset for digital frequency synthesizer"},
{"DEN_PDFS2",0x0000060E,8,"R/W","Static phase offset for digital frequency synthesizer"},
{"DEN_WSS1",0x0000060F,8,"R/W","WSS data registers"},
{"DEN_WSS2",0x00000610,8,"R/W","WSS data registers"},
{"DEN_DAC13",0x00000611,8,"R/W","DAC1 and DAC3 multiplying factors"},
{"DEN_DAC45",0x00000612,8,"R/W","DAC4 and DAC5 multiplying factors"},
{"DEN_DAC6C",0x00000613,8,"R/W","DAC6 and C multiplying factors"},
{"DEN_LJMP1",0x00000615,8,"R/W","Line jump"},
{"DEN_LJMP2",0x00000616,8,"R/W","Line jump"},
{"DEN_LJMP3",0x00000617,8,"R/W","Line jump"},
{"DEN_CID",0x00000618,8,"R","DENC identification number"},
{"DEN_VPS1",0x00000619,8,"R/W","VPS data registers"},
{"DEN_VPS2",0x0000061A,8,"R/W","VPS data registers"},
{"DEN_VPS3",0x0000061B,8,"R/W","VPS data registers"},
{"DEN_VPS4",0x0000061C,8,"R/W","VPS data registers"},
{"DEN_VPS5",0x0000061D,8,"R/W","VPS data registers"},
{"DEN_VPS6",0x0000061E,8,"R/W","VPS data registers"},
{"DEN_CGMS1",0x0000061F,4,"R/W","CGMS data registers"},
{"DEN_CGMS2",0x00000620,8,"R/W","CGMS data registers"},
{"DEN_CGMS3",0x00000621,8,"R/W","CGMS data registers"},
{"DEN_TTX1",0x00000622,8,"R/W","Teletext block definition"},
{"DEN_TTX2",0x00000623,8,"R/W","Teletext block definition"},
{"DEN_TTX3",0x00000624,8,"R/W","Teletext block definition"},
{"DEN_TTX4",0x00000625,8,"R/W","Teletext block definition"},
{"DEN_TTXM",0x00000626,8,"R/W","Teletext block mapping"},
{"DEN_CCF1",0x00000627,8,"R/W","Closed caption characters/extended data for field 1"},
{"DEN_CCF1B",0x00000628,8,"R/W","Closed caption characters/extended data for field 1"},
{"DEN_CCF2",0x00000629,8,"R/W","Closed caption characters/extended data for field 2"},
{"DEN_CCF2B",0x0000062A,8,"R/W","Closed caption characters/extended data for field 2"},
{"DEN_CLF1",0x0000062B,5,"R/W","Closed caption/extended data line insert for field 1"},
{"DEN_CLF2",0x0000062C,5,"R/W","Closed caption/extended data line insert for field 2"},
{"DEN_REG_45",0x0000062D,0,"??","RESERVED"},
{"DEN_REG_46",0x0000062E,0,"??","RESERVED"},
{"DEN_REG_47",0x0000062F,0,"??","RESERVED"},
{"DEN_REG_48",0x00000630,0,"??","RESERVED"},
{"DEN_REG_49",0x00000631,0,"??","RESERVED"},
{"DEN_REG_50",0x00000632,0,"??","RESERVED"},
{"DEN_REG_51",0x00000633,0,"??","RESERVED"},
{"DEN_REG_52",0x00000634,0,"??","RESERVED"},
{"DEN_REG_53",0x00000635,0,"??","RESERVED"},
{"DEN_REG_54",0x00000636,0,"??","RESERVED"},
{"DEN_REG_55",0x00000637,0,"??","RESERVED"},
{"DEN_REG_56",0x00000638,0,"??","RESERVED"},
{"DEN_REG_57",0x00000639,0,"??","RESERVED"},
{"DEN_REG_58",0x0000063A,0,"??","RESERVED"},
{"DEN_REG_59",0x0000063B,0,"??","RESERVED"},
{"DEN_REG_60",0x0000063C,0,"??","RESERVED"},
{"DEN_REG_61",0x0000063D,0,"??","RESERVED"},
{"DEN_REG_62",0x0000063E,0,"??","RESERVED"},
{"DEN_REG_63",0x0000063F,0,"??","RESERVED"},
{"DEN_REG_64",0x00000640,3,"R/W","TTX_conf"},
{"DEN_REG_65",0x00000641,8,"R/W","DAC2MULT&TTXS"},
{"DEN_REG_66",0x00000642,0,"??","RESERVED"},
{"DEN_REG_67",0x00000643,0,"??","RESERVED"},
{"DEN_REG_68",0x00000644,0,"??","RESERVED"},
{"DEN_REG_69",0x00000645,8,"R/W","Brightness"},
{"DEN_REG_70",0x00000646,8,"R/W","Contrast"},
{"DEN_REG_71",0x00000647,8,"R/W","Saturation"},
//{"DEN_YCOUT",0x000001F9,1,"R/W","Make YC data bus accessible on PIO4"},
/************************/
/* MPEG_CONTROL REGISTER*
/************************/
{"MPEG_CONTROL_7_0",0x00000E00,8,"R/W","MPEG Audio/Video buffer control register"},
{"MPEG_CONTROL_14_8",0x00000E01,8,"R/W","MPEG Audio/Video buffer control register"},
/********************************************/
/* Programmable CPU Memory Interface (EMI) */
/********************************************/
{"EMI_CONFIGDATA0BANK0",0x00002000,16,"R/W","EMI bank 0 configuration data register 0 SDRAM, DRAM and peripheral memory formats"},
{"EMI_CONFIGDATA1BANK0",0x00002004,16,"R/W","EMI bank 0 configuration data register 1 SDRAM, DRAM and peripheral memory formats"},
{"EMI_CONFIGDATA2BANK0",0x00002008,16,"R/W","EMI bank 0 configuration data register 2 SDRAM, DRAM and peripheral memory formats"},
{"EMI_CONFIGDATA3BANK0",0x0000200c,16,"R/W","EMI bank 0 configuration data register 3 SDRAM, DRAM and peripheral memory formats"},
{"EMI_CONFIGDATA0BANK1",0x00002010,16,"R/W","EMI bank 1 configuration data register 0 SDRAM, DRAM and peripheral memory formats"},
{"EMI_CONFIGDATA1BANK1",0x00002014,16,"R/W","EMI bank 1 configuration data register 1 SDRAM, DRAM and peripheral memory formats"},
{"EMI_CONFIGDATA2BANK1",0x00002018,16,"R/W","EMI bank 1 configuration data register 2 SDRAM, DRAM and peripheral memory formats"},
{"EMI_CONFIGDATA3BANK1",0x0000201c,16,"R/W","EMI bank 1 configuration data register 3 SDRAM, DRAM and peripheral memory formats"},
{"EMI_CONFIGDATA0BANK2",0x00002020,16,"R/W","EMI bank 2 configuration data register 0 SDRAM, DRAM and peripheral memory formats"},
{"EMI_CONFIGDATA1BANK2",0x00002024,16,"R/W","EMI bank 2 configuration data register 1 SDRAM, DRAM and peripheral memory formats"},
{"EMI_CONFIGDATA2BANK2",0x00002028,16,"R/W","EMI bank 2 configuration data register 2 SDRAM, DRAM and peripheral memory formats"},
{"EMI_CONFIGDATA3BANK2",0x0000202c,16,"R/W","EMI bank 2 configuration data register 3 SDRAM, DRAM and peripheral memory formats"},
{"EMI_CONFIGDATA0BANK3",0x00002030,16,"R/W","EMI bank 3 configuration data register 0 SDRAM, DRAM and peripheral memory formats"},
{"EMI_CONFIGDATA1BANK3",0x00002034,16,"R/W","EMI bank 3 configuration data register 1 SDRAM, DRAM and peripheral memory formats"},
{"EMI_CONFIGDATA2BANK3",0x00002038,16,"R/W","EMI bank 3 configuration data register 2 SDRAM, DRAM and peripheral memory formats"},
{"EMI_CONFIGDATA3BANK3",0x0000203c,16,"R/W","EMI bank 3 configuration data register 3 SDRAM, DRAM and peripheral memory formats"},
{"EMI_CONFIGLOCKBANK0",0x00002040,1,"W","Write protection bit. When set, makes EMI_ConfigData 0-3 for Bank0 read only"},
{"EMI_CONFIGLOCKBANK0",0x00002044,1,"W","Write protection bit. When set, makes EMI_ConfigData 0-3 for Bank1 read only"},
{"EMI_CONFIGLOCKBANK0",0x00002048,1,"W","Write protection bit. When set, makes EMI_ConfigData 0-3 for Bank2 read only"},
{"EMI_CONFIGLOCKBANK0",0x0000204C,1,"W","Write protection bit. When set, makes EMI_ConfigData 0-3 for Bank3 read only"},
{"EMI_CONFIGSTATUS",0x00002050,8,"R","Status information"},
{"EMI_SDRAMMODEREG0",0x00002058,7,"W","SDRAM Mode Register for either the case of one SDRAM bank or SDRAM in bank0, when two SDRAM banks."},
{"EMI_SDRAMMODEREG1",0x0000205C,7,"W","SDRAM Mode Register in the case"},
{"EMI_DRAMINITIALIZE",0x00002060,1,"W","Initialize any (S)DRAM in the system."},
{"EMI_CONFIGPADLOGIC",0x00002070,14,"R/W","Padlogic configuration data register."},
/************************************/
/* DIAGNOSTIC CONTROL UNIT (DCU) */
/************************************/
{"DCU",0x00003004,8,"R/W","Diagnostic Control Unit Register."},
/************************/
/* CACHE CONTROL (CAC) */
/************************/
{"CAC_CACHECONTROL0",0x00004000,8,"R/W","Cacheability of 0xC0000000 to 0xC007FFFF"},
{"CAC_CACHECONTROL1",0x00004100,8,"R/W","Cacheability of 0xC0200000 to 0xC027FFFF"},
{"CAC_CACHECONTROL2",0x00004200,8,"R/W","Cacheability of 0x40000000 to 0x4007FFFF"},
{"CAC_CACHECONTROL3",0x00004300,4,"R/W","Cacheability of 0x40000000 to 0x7FFFFFFF"},
{"CAC_DCACHENOTSRAM",0x00004400,1,"W","Select data cache or extra SRAM"},
{"CAC_INVALIDATEDCACHE",0x00004500,1,"W","Invalidate the data cache"},
{"CAC_FLUSHDCACHE",0x00004600,1,"W","Flush the data cache"},
{"CAC_ENABLEICACHE",0x00004700,1,"W","Enable the instruction cache"},
{"CAC_INVALIDATEICACHE",0x00004800,1,"W","Invalidate the instruction cache"},
{"CAC_CACHESTATUS",0x00004900,7,"R","Cache status"},
{"CAC_CACHECONTROLLOCK",0x00004A00,1,"R/W","Lock the cache configuration"},
/*****************************/
/* INTERRUPT CONTROLLER (INC)*/
/*****************************/
{"INC_HANDLERWPTR0",0x20000000,32,"R/W","Interrupt handler 0 work space pointer"},
{"INC_HANDLERWPTR1",0x20000004,32,"R/W","Interrupt handler 1 work space pointer"},
{"INC_HANDLERWPTR2",0x20000008,32,"R/W","Interrupt handler 2 work space pointer"},
{"INC_HANDLERWPTR3",0x2000000C,32,"R/W","Interrupt handler 3 work space pointer"},
{"INC_HANDLERWPTR4",0x20000010,32,"R/W","Interrupt handler 4 work space pointer"},
{"INC_HANDLERWPTR5",0x20000014,32,"R/W","Interrupt handler 5 work space pointer"},
{"INC_HANDLERWPTR6",0x20000018,32,"R/W","Interrupt handler 6 work space pointer"},
{"INC_HANDLERWPTR7",0x2000001C,32,"R/W","Interrupt handler 7 work space pointer"},
{"INC_TRIGGERMODE0",0x20000040,3,"R/W","Interrupt 0 trigger mode"},
{"INC_TRIGGERMODE1",0x20000044,3,"R/W","Interrupt 1 trigger mode"},
{"INC_TRIGGERMODE2",0x20000048,3,"R/W","Interrupt 2 trigger mode"},
{"INC_TRIGGERMODE3",0x2000004C,3,"R/W","Interrupt trigger mode"},
{"INC_TRIGGERMODE4",0x20000050,3,"R/W","Interrupt 3 trigger mode"},
{"INC_TRIGGERMODE5",0x20000054,3,"R/W","Interrupt 4 trigger mode"},
{"INC_TRIGGERMODE6",0x20000058,3,"R/W","Interrupt 5 trigger mode"},
{"INC_TRIGGERMODE7",0x2000005C,3,"R/W","Interrupt 6 trigger mode"},
{"INC_PENDING",0x20000080,8,"R/W","Interrupt pending"},
{"INC_SET_PENDING",0x20000084,8,"W","Set a bit of the Pending register"},
{"INC_CLEAR_PENDING",0x20000088,8,"W","Clear a bit of the Pending register"},
{"INC_MASK",0x200000C0,17,"R/W","Interrupt enable mask"},
{"INC_SET_MASK",0x200000C4,17,"W","Set a bit of the interrupt enable mask"},
{"INC_CLEAR_MASK",0x200000C8,17,"W","Clear a bit of the interrupt enable mask"},
{"INC_EXEC",0x20000100,8,"R/W","Interrupts executing"},
{"INC_SET_EXEC",0x20000104,8,"W","Set a bit of the Exec register"},
{"INC_CLEAR_EXEC",0x20000108,8,"W","Clear a bit of the Exec register"},
/****************************/
/* Low Power Module (LPM) */
/****************************/
{"LPM_TIMER_31_0",0x20000400,32,"R/W","Low power timer least significant word"},
{"LPM_TIMER_32_63",0x20000404,32,"R/W","Low power timer most significant word"},
{"LPM_TIMERSTART",0x20000408,1,"W","Low power timer start"},
{"LPM_ALARM_31_0",0x20000410,32,"R/W","Low power alarm least significant word"},
{"LPM_ALARM_32_39",0x20000414,8,"R/W","Low power alarm most significant word"},
{"LPM_ALARMSTART",0x20000418,1,"W","Low power alarm start"},
{"LPM_SYSPLL",0x20000420,2,"R/W","System clock PLL"},
{"LPM_SYSRATIO",0x20000500,6,"R","System clock ratio"},
{"LPM_WDENABLE",0x20000510,1,"R/W","Watchdog enable"},
{"LPM_WDFLAG",0x20000514,1,"R","Watchdog flag"},
/************************************/
/*Eight different keys set are defined. */
/*Each key set contains 2 keys of 64 bit each*/
/************************************/
{"DESC_KEY0_EVEN_LSW",0x20002500,32,"R/W","DESCRAMBLER KEY 0 EVEN 31:0 (LSW)"},
{"DESC_KEY0_EVEN_MSW",0x20002504,32,"R/W","DESCRAMBLER KEY 0 EVEN 63:32 (MSW)"},
{"DESC_KEY0_ODD_LSW",0x20002508,32,"R/W","DESCRAMBLER KEY 0 ODD 31:0 (LSW)"},
{"DESC_KEY0_ODD_MSW",0x2000250C,32,"R/W","DESCRAMBLER KEY 0 ODD 63:32 (MSW)"},
{"DESC_KEY1_EVEN_LSW",0x20002510,32,"R/W","DESCRAMBLER KEY 1 EVEN 31:0 (LSW)"},
{"DESC_KEY1_EVEN_MSW",0x20002514,32,"R/W","DESCRAMBLER KEY 1 EVEN 63:32 (MSW)"},
{"DESC_KEY1_ODD_LSW",0x20002518,32,"R/W","DESCRAMBLER KEY 1 ODD 31:0 (LSW)"},
{"DESC_KEY1_ODD_MSW",0x2000251C,32,"R/W","DESCRAMBLER KEY 1 ODD 63:32 (MSW)"},
{"DESC_KEY2_EVEN_LSW",0x20002520,32,"R/W","DESCRAMBLER KEY 2 EVEN 31:0 (LSW)"},
{"DESC_KEY2_EVEN_MSW",0x20002524,32,"R/W","DESCRAMBLER KEY 2 EVEN 63:32 (MSW)"},
{"DESC_KEY2_ODD_LSW",0x20002528,32,"R/W","DESCRAMBLER KEY 2 ODD 31:0 (LSW)"},
{"DESC_KEY2_ODD_MSW",0x2000252C,32,"R/W","DESCRAMBLER KEY 2 ODD 63:32 (MSW)"},
{"DESC_KEY3_EVEN_LSW",0x20002530,32,"R/W","DESCRAMBLER KEY 3 EVEN 31:0 (LSW)"},
{"DESC_KEY3_EVEN_MSW",0x20002534,32,"R/W","DESCRAMBLER KEY 3 EVEN 63:32 (MSW)"},
{"DESC_KEY3_ODD_LSW",0x20002538,32,"R/W","DESCRAMBLER KEY 3 ODD 31:0 (LSW)"},
{"DESC_KEY3_ODD_MSW",0x2000253C,32,"R/W","DESCRAMBLER KEY 3 ODD 63:32 (MSW)"},
{"DESC_KEY4_EVEN_LSW",0x20002540,32,"R/W","DESCRAMBLER KEY 4 EVEN 31:0 (LSW)"},
{"DESC_KEY4_EVEN_MSW",0x20002544,32,"R/W","DESCRAMBLER KEY 4 EVEN 63:32 (MSW)"},
{"DESC_KEY4_ODD_LSW",0x20002548,32,"R/W","DESCRAMBLER KEY 4 ODD 31:0 (LSW)"},
{"DESC_KEY4_ODD_MSW",0x2000254C,32,"R/W","DESCRAMBLER KEY 4 ODD 63:32 (MSW)"},
{"DESC_KEY5_EVEN_LSW",0x20002550,32,"R/W","DESCRAMBLER KEY 5 EVEN 31:0 (LSW)"},
{"DESC_KEY5_EVEN_MSW",0x20002554,32,"R/W","DESCRAMBLER KEY 5 EVEN 63:32 (MSW)"},
{"DESC_KEY5_ODD_LSW",0x20002558,32,"R/W","DESCRAMBLER KEY 5 ODD 31:0 (LSW)"},
{"DESC_KEY5_ODD_MSW",0x2000255C,32,"R/W","DESCRAMBLER KEY 5 ODD 63:32 (MSW)"},
{"DESC_KEY6_EVEN_LSW",0x20002560,32,"R/W","DESCRAMBLER KEY 6 EVEN 31:0 (LSW)"},
{"DESC_KEY6_EVEN_MSW",0x20002564,32,"R/W","DESCRAMBLER KEY 6 EVEN 63:32 (MSW)"},
{"DESC_KEY6_ODD_LSW",0x20002568,32,"R/W","DESCRAMBLER KEY 6 ODD 31:0 (LSW)"},
{"DESC_KEY6_ODD_MSW",0x2000256C,32,"R/W","DESCRAMBLER KEY 6 ODD 63:32 (MSW)"},
{"DESC_KEY7_EVEN_LSW",0x20002570,32,"R/W","DESCRAMBLER KEY 7 EVEN 31:0 (LSW)"},
{"DESC_KEY7_EVEN_MSW",0x20002574,32,"R/W","DESCRAMBLER KEY 7 EVEN 63:32 (MSW)"},
{"DESC_KEY7_ODD_LSW",0x20002578,32,"R/W","DESCRAMBLER KEY 7 ODD 31:0 (LSW)"},
{"DESC_KEY7_ODD_MSW",0x2000257C,32,"R/W","DESCRAMBLER KEY 7 ODD 63:32 (MSW)"},
/************************************/
/* ASYNCRONOUS SERIAL CONTROLLER 0 */
/* SMARTCARD READER 0 */
/************************************/
{"ASC_0_BAUDRATE",0x20003000,16,"R/W","ASC 0 Baud rate generator/reload"},
{"ASC_0_TXBUFFER",0x20003004,9,"W","ASC 0 Output buffer"},
{"ASC_0_RXBUFFER",0x20003008,9,"R","ASC 0 Input buffer"},
{"ASC_0_CONTROL",0x2000300C,13,"R/W","ASC 0 Control register"},
{"ASC_0_INTENABLE",0x20003010,9,"R/W","ASC 0 Enable interrupts"},
{"ASC_0_STATUS",0x20003014,11,"R","ASC 0 Interrupt status"},
{"ASC_0_GUARDTIME",0x20003018,8,"R/W","ASC 0 Delay before transmitter empty flag"},
{"ASC_0_TIMEOUT",0x2000301C,8,"R/W","ASC 0 Time out register"},
{"ASC_0_TXRESET",0x20003020,0,"W","ASC 0 Reset output FIFO"},
{"ASC_0_RXRESET",0x20003024,0,"W","ASC 0 Reset input FIFO"},
{"ASC_0_RETRIES",0x20003028,8,"R/W","ASC 0 number of retries on transmission"},
/************************************/
/* ASYNCRONOUS SERIAL CONTROLLER 1 *
/************************************/
{"ASC_1_BAUDRATE",0x20004000,16,"R/W","ASC 1 Baud rate generator/reload"},
{"ASC_1_TXBUFFER",0x20004004,9,"W","ASC 1 Output buffer"},
{"ASC_1_RXBUFFER",0x20004008,9,"R","ASC 1 Input buffer"},
{"ASC_1_CONTROL",0x2000400C,13,"R/W","ASC 1 Control register"},
{"ASC_1_INTENABLE",0x20004010,9,"R/W","ASC 1 Enable interrupts"},
{"ASC_1_STATUS",0x20004014,11,"R","ASC 1 Interrupt status"},
{"ASC_1_GUARDTIME",0x20004018,8,"R/W","ASC 1 Delay before transmitter empty flag"},
{"ASC_1_TIMEOUT",0x2000401C,8,"R/W","ASC 1 Time out register"},
{"ASC_1_TXRESET",0x20004020,0,"W","ASC 1 Reset output FIFO"},
{"ASC_1_RXRESET",0x20004024,0,"W","ASC 1 Reset input FIFO"},
{"ASC_1_RETRIES",0x20004028,8,"R/W","ASC 1 number of retries on transmission"},
/************************************/
/* ASYNCRONOUS SERIAL CONTROLLER 2 *
/************************************/
{"ASC_2_BAUDRATE",0x20005000,16,"R/W","ASC 2 Baud rate generator/reload"},
{"ASC_2_TXBUFFER",0x20005004,9,"W","ASC 2 Output buffer"},
{"ASC_2_RXBUFFER",0x20005008,9,"R","ASC 2 Input buffer"},
{"ASC_2_CONTROL",0x2000500C,13,"R/W","ASC 2 Control register"},
{"ASC_2_INTENABLE",0x20005010,9,"R/W","ASC 2 Enable interrupts"},
{"ASC_2_STATUS",0x20005014,11,"R","ASC 2 Interrupt status"},
{"ASC_2_GUARDTIME",0x20005018,8,"R/W","ASC 2 Delay before transmitter empty flag"},
{"ASC_2_TIMEOUT",0x2000501C,8,"R/W","ASC 2 Time out register"},
{"ASC_2_TXRESET",0x20005020,0,"W","ASC 2 Reset output FIFO"},
{"ASC_2_RXRESET",0x20005024,0,"W","ASC 2 Reset input FIFO"},
{"ASC_2_RETRIES",0x20005028,8,"R/W","ASC 2 number of retries on transmission"},
/************************************/
/* ASYNCRONOUS SERIAL CONTROLLER 3 */
/* SMARTCARD READER 1 */
/************************************/
{"ASC_3_BAUDRATE",0x20006000,16,"R/W","ASC 3 Baud rate generator/reload"},
{"ASC_3_TXBUFFER",0x20006004,9,"W","ASC 3 Output buffer"},
{"ASC_3_RXBUFFER",0x20006008,9,"R","ASC 3 Input buffer"},
{"ASC_3_CONTROL",0x2000600C,13,"R/W","ASC 3 Control register"},
{"ASC_3_INTENABLE",0x20006010,9,"R/W","ASC 3 Enable interrupts"},
{"ASC_3_STATUS",0x20006014,11,"R","ASC 3 Interrupt status"},
{"ASC_3_GUARDTIME",0x20006018,8,"R/W","ASC 3 Delay before transmitter empty flag"},
{"ASC_3_TIMEOUT",0x2000601C,8,"R/W","ASC 3 Time out register"},
{"ASC_3_TXRESET",0x20006020,0,"W","ASC 3 Reset output FIFO"},
{"ASC_3_RXRESET",0x20006024,0,"W","ASC 3 Reset input FIFO"},
{"ASC_3_RETRIES",0x20006028,8,"R/W","ASC 3 number of retries on transmission"},
/*************************/
/* SMARTCARD INTERFACE 0 *
/*************************/
{"SCI_SC0CLKVAL",0x20007000,5,"W","SmartCard 0 clock"},
{"SCI_SC0CLKCON",0x20007004,2,"W","SmartCard 0 clock control"},
/*************************/
/* SMARTCARD INTERFACE 1 *
/*************************/
{"SCI_SC1CLKVAL",0x20008000,5,"W","SmartCard 1 clock"},
{"SCI_SC1CLKCON",0x20008004,2,"W","SmartCard 1 clock control"},
/*****************************************/
/* Synchronous serial controller 0 (SSC) *
/*****************************************/
{"SSC_0_BRG",0x20009000,10,"R/W","SSC 0 baud rate generation"},
{"SSC_0_TBuf",0x20009004,16,"W","SSC 0 transmit buffer"},
{"SSC_0_RBuf",0x20009008,16,"R","SSC 0 receive buffer"},
{"SSC_0_Con",0x2000900C,11,"R/W","SSC 0 control"},
{"SSC_0_IEn",0x20009010,9,"R/W","SSC 0 interrupt enable"},
{"SSC_0_Stat",0x20009014,10,"R","SSC 0 status"},
{"SSC_0_I2C",0x20009018,5,"R/W","SSC 0 I2C control"},
{"SSC_0_SlAd",0x2000901C,16,"W","SSC 0 slave address"},
/*****************************************/
/* Synchronous serial controller 1 (SSC) *
/*****************************************/
{"SSC_1_BRG",0x2000A000,10,"R/W","SSC 1 baud rate generation"},
{"SSC_1_TBuf",0x2000A004,16,"W","SSC 1 transmit buffer"},
{"SSC_1_RBuf",0x2000A008,16,"R","SSC 1 receive buffer"},
{"SSC_1_Con",0x2000A00C,11,"R/W","SSC 1 control"},
{"SSC_1_IEn",0x2000A010,9,"R/W","SSC 1 interrupt enable"},
{"SSC_1_Stat",0x2000A014,10,"R","SSC 1 status"},
{"SSC_1_I2C",0x2000A018,5,"R/W","SSC 1 I2C control"},
{"SSC_1_SlAd",0x2000A01C,16,"W","SSC 1 slave address"},
/****************************/
/* PARALLEL I/O CONTROLLER 5*
/****************************/
{"PIO_P5OUT",0x2000A100 ,8,"R/W","PIO 5 output"},
{"PIO_SET_P5OUT",0x2000A104 ,8,"W","Set bits of P5Out"},
{"PIO_CLEAR_P5OUT",0x2000A108 ,8,"W","Clear bits of P5Out"},
{"PIO_P5IN",0x2000A110 ,8,"R","PIO 5 input"},
{"PIO_P5C0",0x2000A120 ,8,"R/W","PIO 5 configuration 0"},
{"PIO_SET_P5C0",0x2000A124 ,8,"W","Set bits of P5C0"},
{"PIO_CLEAR_P5C0",0x2000A128 ,8,"W","Clear bits of P5C0"},
{"PIO_P5C1",0x2000A130 ,8,"R/W","PIO 5 configuration 1"},
{"PIO_SET_P5C1",0x2000A134 ,8,"W","Set bits of P5C1"},
{"PIO_CLEAR_P5C1",0x2000A138 ,8,"W","Clear bits of P5C1"},
{"PIO_P5C2",0x2000A140 ,8,"R/W","PIO 5 configuration 2"},
{"PIO_SET_P5C2",0x2000A144 ,8,"W","Set bits of P5C2"},
{"PIO_CLEAR_P5C2",0x2000A148 ,8,"W","Clear bits of P5C2"},
{"PIO_P5COMP",0x2000A150 ,8,"R/W","PIO 5 input comparison"},
{"PIO_SET_P5COMP",0x2000A154 ,8,"W","Set bits of P5Comp"},
{"PIO_CLEAR_P5COMP",0x2000A158 ,8,"W","Clear bits of P5Comp."},
{"PIO_P5MASK",0x2000A160 ,8,"R/W","PIO 5 input comparison mask"},
{"PIO_SET_P5MASK",0x2000A164 ,8,"W","Set bits of P5Mask"},
{"PIO_CLEAR_P5MASK",0x2000A168 ,8,"W","Clear bits of P5Mask"},
/****************************/
/* INFRARED BLASTER (IRB) */
/****************************/
{"IRB_TX_PRE_SCALER_IR",IRBBaseAddress+0x00,8,"W/R","Clock pre-scaler selection"},
{"IRB_TX_SUB_CARRIER_IR",IRBBaseAddress+0x04,16,"W/R","sub-carrier freq. programming"},
{"IRB_TX_SYM_TIME_IR1",IRBBaseAddress+0x08,16,"W","symbol time programming"},
{"IRB_TX_ON_TIME_IR1",IRBBaseAddress+0x0C,16,"W","symbol on time programming"},
{"IRB_TX_INT_EN_IR",IRBBaseAddress+0x10,3,"W/R","Transmit Interrupt enable register"},
{"IRB_TX_INT_STATUS_IR",IRBBaseAddress+0x14,4,"R","Transmit Interrupt status register"},
{"IRB_TX_EN_IR", IRBBaseAddress+0x18,1,"W/R","RC transmit enable register"},
{"IRB_TX_CLR_UNDERRUN_IR", IRBBaseAddress+0x1C,1,"W","Clears the underrun status"},
{"IRB_RX_ON_TIME_IR1", IRBBaseAddress+0x40,16,"R","Received pulse time capture RC"},
{"IRB_RX_SYM_TIME_IR1", IRBBaseAddress+0x44,16,"R","Received symbol time capture"},
{"IRB_RX_INT_EN_IR", IRBBaseAddress+0x48,4,"W/R","Receive Interrupt enable register"},
{"IRB_RX_INT_STATUS_IR", IRBBaseAddress+0x4C,5,"R","Receive Interrupt status register"},
{"IRB_RX_EN_IR", IRBBaseAddress+0x50,1,"W/R","RC receive enable register"},
{"IRB_RX_MAX_SYM_TIME_IR", IRBBaseAddress+0x54,16,"W/R","Maximum RC symbol time register"},
{"IRB_RX_CLR_OVERRUN_IR", IRBBaseAddress+0x58,1,"W","Clears the overrun status"},
{"IRB_RX_NOISE_SUPPRESS_WIDTH_IR", IRBBaseAddress+0x5C,8,"W/R","Reserved"},
{"IRB_RC_IRDA_CONTROL", IRBBaseAddress+0x60,1,"W/R","Reserved"},
{"IRB_RX_SAMPLING_RATE_COMMON", IRBBaseAddress+0x64,4,"W/R","Sampling frequency division for UHF and IR frequencies."},
{"IRB_RX_ON_TIME_UHF1", IRBBaseAddress+0x80,16,"R","Received pulse time capture"},
{"IRB_RX_SYM_TIME_UHF1", IRBBaseAddress+0x84,16,"R","Received symbol time capture"},
{"IRB_RX_INT_EN_UHF", IRBBaseAddress+0x88,4,"W/R","Receive Interrupt enable register"},
{"IRB_RX_INT_STATUS_UHF", IRBBaseAddress+0x8C,5,"R","Receive Interrupt status register"},
{"IRB_RX_EN_UHF", IRBBaseAddress+0x90,1,"W/R","RC receive enable register"},
{"IRB_RX_MAX_SYM_TIME_UHF", IRBBaseAddress+0x94,16,"W/R","Maximum RC symbol time register"},
{"IRB_RX_CLR_OVERRUN_UHF", IRBBaseAddress+0x98,1,"W","Clears the overrun status"},
{"IRB_RX_NOISE_SUPPRESS_WIDTH_UHF", IRBBaseAddress+0x9C,8,"W/R","Noise suppression width"},
/******************/
/* Teletext (TTXT)*
/******************/
{"TTXT_DMAADDRESS",0x2000A300,32,"R/W","Teletext DMA address"},
{"TTXT_DMACOUNT",0x2000A304,11,"R/W","Teletext DMA count"},
{"TTXT_OUTDELAY",0x2000A308,9,"R/W","Teletext output delay"},
{"TTXT_INTSTATUS",0x2000A318,3,"R","Teletext interrupt status"},
{"TTXT_INTENABLE",0x2000A31C,3,"R/W","Teletext interrupt enable"},
{"TTXT_ACKODDEVEN",0x2000A320,1,"W","Teletext acknowledge odd or even"},
{"TTXT_ABORT",0x2000A324,1,"W","Teletext abort"},
/*******************************/
/* PWM and counter module (PWM)*
/*******************************/
{"PWM_0VAL",0x2000B000,9,"R/W","PWM 0 pulse width"},
{"PWM_1VAL",0x2000B004,9,"R/W","PWM 1 pulse width"},
{"PWM_2VAL",0x2000B008,9,"R/W","PWM 2 pulse width"},
{"PWM_3VAL",0x2000B00C,9,"R/W","PWM 3 pulse width"},
{"PWM_0CAPTUREVAL",0x2000B010,32,"R","PWM 0 capture value"},
{"PWM_1CAPTUREVAL",0x2000B014,32,"R","PWM 1 capture value"},
{"PWM_2CAPTUREVAL",0x2000B018,32,"R","PWM 2 capture value"},
{"PWM_3CAPTUREVAL",0x2000B01C,32,"R","PWM 3 capture value"},
{"PWM_0COMPAREVAL",0x2000B020,32,"R/W","PWM 0 compare value"},
{"PWM_1COMPAREVAL",0x2000B024,32,"R/W","PWM 1 compare value"},
{"PWM_2COMPAREVAL",0x2000B028,32,"R/W","PWM 2 compare value"},
{"PWM_3COMPAREVAL",0x2000B02C,32,"R/W","PWM 3 compare value"},
{"PWM_0CAPTUREEDGE",0x2000B030,2,"R/W","PWM 0 capture event definition"},
{"PWM_1CAPTUREEDGE",0x2000B034,2,"R/W","PWM 1 capture event definition"},
{"PWM_2CAPTUREEDGE",0x2000B038,2,"R/W","PWM 2 capture event definition"},
{"PWM_3CAPTUREEDGE",0x2000B03C,2,"R/W","PWM 3 capture event definition"},
{"PWM_0COMPAREOUTVAL",0x2000B040,1,"R/W","PWM 0 compare output value"},
{"PWM_CONTROL",0x2000B050,11,"R/W","PWM control register"},
{"PWM_INTENABLE",0x2000B054,9,"R/W","PWM interrupt enable"},
{"PWM_INTSTATUS",0x2000B058,9,"R","PWM interrupt status"},
{"PWM_INTACK",0x2000B05C,9,"W","PWM interrupt acknowledge"},
{"PWM_COUNT",0x2000B060,8,"R/W","PWM output counter"},
/****************************/
/* PARALLEL I/O CONTROLLER 0*
/****************************/
{"PIO_P0OUT",0x2000C000 ,8,"R/W","PIO 0 output"},
{"PIO_SET_P0OUT",0x2000C004 ,8,"W","Set bits of P0Out"},
{"PIO_CLEAR_P0OUT",0x2000C008 ,8,"W","Clear bits of P0Out"},
{"PIO_P0IN",0x2000C010 ,8,"R","PIO 0 input"},
{"PIO_P0C0",0x2000C020 ,8,"R/W","PIO 0 configuration 0"},
{"PIO_SET_P0C0",0x2000C024 ,8,"W","Set bits of P0C0"},
{"PIO_CLEAR_P0C0",0x2000C028 ,8,"W","Clear bits of P0C0"},
{"PIO_P0C1",0x2000C030 ,8,"R/W","PIO 0 configuration 1"},
{"PIO_SET_P0C1",0x2000C034 ,8,"W","Set bits of P0C1"},
{"PIO_CLEAR_P0C1",0x2000C038 ,8,"W","Clear bits of P0C1"},
{"PIO_P0C2",0x2000C040 ,8,"R/W","PIO 0 configuration 2"},
{"PIO_SET_P0C2",0x2000C044 ,8,"W","Set bits of P0C2"},
{"PIO_CLEAR_P0C2",0x2000C048 ,8,"W","Clear bits of P0C2"},
{"PIO_P0COMP",0x2000C050 ,8,"R/W","PIO 0 input comparison"},
{"PIO_SET_P0COMP",0x2000C054 ,8,"W","Set bits of P0Comp"},
{"PIO_CLEAR_P0COMP",0x2000C058 ,8,"W","Clear bits of P0Comp."},
{"PIO_P0MASK",0x2000C060 ,8,"R/W","PIO 0 input comparison mask"},
{"PIO_SET_P0MASK",0x2000C064 ,8,"W","Set bits of P0Mask"},
{"PIO_CLEAR_P0MASK",0x2000C068 ,8,"W","Clear bits of P0Mask"},
/****************************/
/* PARALLEL I/O CONTROLLER 1*
/****************************/
{"PIO_P1OUT",0x2000D000 ,8,"R/W","PIO 1 output"},
{"PIO_SET_P1OUT",0x2000D004 ,8,"W","Set bits of P1Out"},
{"PIO_CLEAR_P1OUT",0x2000D008 ,8,"W","Clear bits of P1Out"},
{"PIO_P1IN",0x2000D010 ,8,"R","PIO 1 input"},
{"PIO_P1C0",0x2000D020 ,8,"R/W","PIO 1 configuration 0"},
{"PIO_SET_P1C0",0x2000D024 ,8,"W","Set bits of P1C0"},
{"PIO_CLEAR_P1C0",0x2000D028 ,8,"W","Clear bits of P1C0"},
{"PIO_P1C1",0x2000D030 ,8,"R/W","PIO 1 configuration 1"},
{"PIO_SET_P1C1",0x2000D034 ,8,"W","Set bits of P1C1"},
{"PIO_CLEAR_P1C1",0x2000D038 ,8,"W","Clear bits of P1C1"},
{"PIO_P1C2",0x2000D040 ,8,"R/W","PIO 1 configuration 2"},
{"PIO_SET_P1C2",0x2000D044 ,8,"W","Set bits of P1C2"},
{"PIO_CLEAR_P1C2",0x2000D048 ,8,"W","Clear bits of P1C2"},
{"PIO_P1COMP",0x2000D050 ,8,"R/W","PIO 1 input comparison"},
{"PIO_SET_P1COMP",0x2000D054 ,8,"W","Set bits of P1Comp"},
{"PIO_CLEAR_P1COMP",0x2000D058 ,8,"W","Clear bits of P1Comp."},
{"PIO_P1MASK",0x2000D060 ,8,"R/W","PIO 1 input comparison mask"},
{"PIO_SET_P1MASK",0x2000D064 ,8,"W","Set bits of P1Mask"},
{"PIO_CLEAR_P1MASK",0x2000D068 ,8,"W","Clear bits of P1Mask"},
/****************************/
/* PARALLEL I/O CONTROLLER 2*
/****************************/
{"PIO_P2OUT",0x2000E000 ,8,"R/W","PIO 2 output"},
{"PIO_SET_P2OUT",0x2000E004 ,8,"W","Set bits of P2Out"},
{"PIO_CLEAR_P2OUT",0x2000E008 ,8,"W","Clear bits of P2Out"},
{"PIO_P2IN",0x2000E010 ,8,"R","PIO 2 input"},
{"PIO_P2C0",0x2000E020 ,8,"R/W","PIO 2 configuration 0"},
{"PIO_SET_P2C0",0x2000E024 ,8,"W","Set bits of P2C0"},
{"PIO_CLEAR_P2C0",0x2000E028 ,8,"W","Clear bits of P2C0"},
{"PIO_P2C1",0x2000E030 ,8,"R/W","PIO 2 configuration 1"},
{"PIO_SET_P2C1",0x2000E034 ,8,"W","Set bits of P2C1"},
{"PIO_CLEAR_P2C1",0x2000E038 ,8,"W","Clear bits of P2C1"},
{"PIO_P2C2",0x2000E040 ,8,"R/W","PIO 2 configuration 2"},
{"PIO_SET_P2C2",0x2000E044 ,8,"W","Set bits of P2C2"},
{"PIO_CLEAR_P2C2",0x2000E048 ,8,"W","Clear bits of P2C2"},
{"PIO_P2COMP",0x2000E050 ,8,"R/W","PIO 2 input comparison"},
{"PIO_SET_P2COMP",0x2000E054 ,8,"W","Set bits of P2Comp"},
{"PIO_CLEAR_P2COMP",0x2000E058 ,8,"W","Clear bits of P2Comp."},
{"PIO_P2MASK",0x2000E060 ,8,"R/W","PIO 2 input comparison mask"},
{"PIO_SET_P2MASK",0x2000E064 ,8,"W","Set bits of P2Mask"},
{"PIO_CLEAR_P2MASK",0x2000E068 ,8,"W","Clear bits of P2Mask"},
/****************************/
/* PARALLEL I/O CONTROLLER 3*
/****************************/
{"PIO_P3OUT",0x2000F000 ,8,"R/W","PIO 3 output"},
{"PIO_SET_P3OUT",0x2000F004 ,8,"W","Set bits of P3Out"},
{"PIO_CLEAR_P3OUT",0x2000F008 ,8,"W","Clear bits of P3Out"},
{"PIO_P3IN",0x2000F010 ,8,"R","PIO 3 input"},
{"PIO_P3C0",0x2000F020 ,8,"R/W","PIO 3 configuration 0"},
{"PIO_SET_P3C0",0x2000F024 ,8,"W","Set bits of P3C0"},
{"PIO_CLEAR_P3C0",0x2000F028 ,8,"W","Clear bits of P3C0"},
{"PIO_P3C1",0x2000F030 ,8,"R/W","PIO 3 configuration 1"},
{"PIO_SET_P3C1",0x2000F034 ,8,"W","Set bits of P3C1"},
{"PIO_CLEAR_P3C1",0x2000F038 ,8,"W","Clear bits of P3C1"},
{"PIO_P3C2",0x2000F040 ,8,"R/W","PIO 3 configuration 2"},
{"PIO_SET_P3C2",0x2000F044 ,8,"W","Set bits of P3C2"},
{"PIO_CLEAR_P3C2",0x2000F048 ,8,"W","Clear bits of P3C2"},
{"PIO_P3COMP",0x2000F050 ,8,"R/W","PIO 3 input comparison"},
{"PIO_SET_P3COMP",0x2000F054 ,8,"W","Set bits of P3Comp"},
{"PIO_CLEAR_P3COMP",0x2000F058 ,8,"W","Clear bits of P3Comp."},
{"PIO_P3MASK",0x2000F060 ,8,"R/W","PIO 3 input comparison mask"},
{"PIO_SET_P3MASK",0x2000F064 ,8,"W","Set bits of P3Mask"},
{"PIO_CLEAR_P3MASK",0x2000F068 ,8,"W","Clear bits of P3Mask"},
/****************************/
/* PARALLEL I/O CONTROLLER 4*
/****************************/
{"PIO_P4OUT",0x20010000 ,8,"R/W","PIO 4 output"},
{"PIO_SET_P4OUT",0x20010004 ,8,"W","Set bits of P4Out"},
{"PIO_CLEAR_P4OUT",0x20010008 ,8,"W","Clear bits of P4Out"},
{"PIO_P4IN",0x20010010 ,8,"R","PIO 4 input"},
{"PIO_P4C0",0x20010020 ,8,"R/W","PIO 4 configuration 0"},
{"PIO_SET_P4C0",0x20010024 ,8,"W","Set bits of P4C0"},
{"PIO_CLEAR_P4C0",0x20010028 ,8,"W","Clear bits of P4C0"},
{"PIO_P4C1",0x20010030 ,8,"R/W","PIO 4 configuration 1"},
{"PIO_SET_P4C1",0x20010034 ,8,"W","Set bits of P4C1"},
{"PIO_CLEAR_P4C1",0x20010038 ,8,"W","Clear bits of P4C1"},
{"PIO_P4C2",0x20010040 ,8,"R/W","PIO 4 configuration 2"},
{"PIO_SET_P4C2",0x20010044 ,8,"W","Set bits of P4C2"},
{"PIO_CLEAR_P4C2",0x20010048 ,8,"W","Clear bits of P4C2"},
{"PIO_P4COMP",0x20010050 ,8,"R/W","PIO 4 input comparison"},
{"PIO_SET_P4COMP",0x20010054 ,8,"W","Set bits of P4Comp"},
{"PIO_CLEAR_P4COMP",0x20010058 ,8,"W","Clear bits of P4Comp."},
{"PIO_P4MASK",0x20010060 ,8,"R/W","PIO 4 input comparison mask"},
{"PIO_SET_P4MASK",0x20010064 ,8,"W","Set bits of P4Mask"},
{"PIO_CLEAR_P4MASK",0x20010068 ,8,"W","Clear bits of P4Mask"},
/************************/
/* INTERRUPT LEVEL (INL)*/
/************************/
{"INC_INT0PRIORITY",0x20011000,3,"R/W","Internal interrupt 0 priority"},
{"INC_INT1PRIORITY",0x20011004,3,"R/W","Internal interrupt 1 priority"},
{"INC_INT2PRIORITY",0x20011008,3,"R/W","Internal interrupt 2 priority"},
{"INC_INT3PRIORITY",0x2001100C,3,"R/W","Internal interrupt 3 priority"},
{"INC_INT4PRIORITY",0x20011010,3,"R/W","Internal interrupt 4 priority"},
{"INC_INT5PRIORITY",0x20011014,3,"R/W","Internal interrupt 5 priority"},
{"INC_INT6PRIORITY",0x20011018,3,"R/W","Internal interrupt 6 priority"},
{"INC_INT7PRIORITY",0x2001101C,3,"R/W","Internal interrupt 7 priority"},
{"INC_INT8PRIORITY",0x20011020,3,"R/W","Internal interrupt 8 priority"},
{"INC_INT9PRIORITY",0x20011024,3,"R/W","Internal interrupt 9 priority"},
{"INC_INT10PRIORITY",0x20011028,3,"R/W","Internal interrupt 10 priority"},
{"INC_INT11PRIORITY",0x2001102C,3,"R/W","Internal interrupt 11 priority"},
{"INC_INT12PRIORITY",0x20011030,3,"R/W","Internal interrupt 12 priority"},
{"INC_INT13PRIORITY",0x20011034,3,"R/W","Internal interrupt 13 priority"},
{"INC_INT14PRIORITY",0x20011038,3,"R/W","Internal interrupt 14 priority"},
{"INC_INT15PRIORITY",0x2001103C,3,"R/W","Internal interrupt 15 priority"},
{"INC_INT16PRIORITY",0x20011040,3," R/W","Internal interrupt 16 priority"},
{"INC_INT17PRIORITY",0x20011044,3," R/W","Internal interrupt 17 priority"},
{"INC_INT18PRIORITY",0x20011048,3," R/W","Internal interrupt 18 priority"},
{"INC_INT19PRIORITY",0x2001104C,3," R/W","Internal interrupt 19 priority"},
{"INC_INT20PRIORITY",0x20011050,3," R/W","Internal interrupt 20 priority (reserved)"},
{"INC_INT21PRIORITY",0x20011054,3," R/W","Internal interrupt 21 priority (reserved)"},
{"INC_INT22PRIORITY",0x20011058,3," R/W","Internal interrupt 22 priority (reserved)"},
{"INC_INT23PRIORITY",0x2001105C,3," R/W","Internal interrupt 23 priority (reserved)"},
{"INC_INT24PRIORITY",0x20011060,3," R/W","External interrupt 0 priority"},
{"INC_INT25PRIORITY",0x20011064,3," R/W","External interrupt 1 priority"},
{"INC_INT26PRIORITY",0x20011068,3," R/W","External interrupt 2 priority"},
{"INC_INT27PRIORITY",0x2001106C,3," R/W","External interrupt 3 priority"},
{"INC_INT28PRIORITY",0x20011070,3," R/W","External interrupt 4 priority"},
{"INC_INT29PRIORITY",0x20011074,3," R/W","External interrupt 5 priority"},
{"INC_INT30PRIORITY",0x20011078,3,"R/W","External interrupt 6 priority"},
{"INC_INPUTINTERRUPTS",0x2001107C,23,"R","Input interrupt status"},
{"INC_SRC0_TRIGGERMODE",0x200110BC,3,"R/W","Interrupt source 0 trigger mode"},
{"INC_SRC1_TRIGGERMODE",0x200110C0,3,"R/W","Interrupt source 1 trigger mode"},
{"INC_SRC2_TRIGGERMODE",0x200110C4,3,"R/W","Interrupt source 2 trigger mode"},
{"INC_SRC3_TRIGGERMODE",0x200110C8,3,"R/W","Interrupt source 3 trigger mode"},
{"INC_SRC4_TRIGGERMODE",0x200110CC,3,"R/W","Interrupt source 4 trigger mode"},
{"INC_SRC5_TRIGGERMODE",0x200110D0,3,"R/W","Interrupt source 5 trigger mode"},
{"INC_SRC6_TRIGGERMODE",0x200110D4,3,"R/W","Interrupt source 6 trigger mode"},
{"INC_SRC7_TRIGGERMODE",0x200110D8,3,"R/W","Interrupt source 7 trigger mode"},
{"INC_SRC8_TRIGGERMODE",0x200110DC,3,"R/W","Interrupt source 8 trigger mode"},
{"INC_SRC9_TRIGGERMODE",0x200110E0,3,"R/W","Interrupt source 9 trigger mode"},
{"INC_SRC10_TRIGGERMODE",0x200110E4,3,"R/W","Interrupt source 10 trigger mode"},
{"INC_SRC11_TRIGGERMODE",0x200110E8,3,"R/W","Interrupt source 11 trigger mode"},
{"INC_SRC12_TRIGGERMODE",0x200110EC,3,"R/W","Interrupt source 12 trigger mode"},
{"INC_SRC13_TRIGGERMODE",0x200110F0,3,"R/W","Interrupt source 13 trigger mode"},
{"INC_SRC14_TRIGGERMODE",0x200110F4,3,"R/W","Interrupt source 14 trigger mode"},
{"INC_SRC15_TRIGGERMODE",0x200110F8,3,"R/W","Interrupt source 15 trigger mode"},
{"INC_SRC16_TRIGGERMODE",0x200110FC,3,"R/W","Interrupt source 16 trigger mode"},
{"INC_SRC17_TRIGGERMODE",0x20011100,3,"R/W","Interrupt source 17 trigger mode"},
{"INC_SRC18_TRIGGERMODE",0x20011104,3,"R/W","Interrupt source 18 trigger mode"},
{"INC_SRC19_TRIGGERMODE",0x20011108,3,"R/W","Interrupt source 19 trigger mode"},
{"INC_SRC20_TRIGGERMODE",0x2001110C,3,"R/W","Interrupt source 20 trigger mode (reserved)"},
{"INC_SRC21_TRIGGERMODE",0x20011110,3,"R/W","Interrupt source 21 trigger mode (reserved)"},
{"INC_SRC22_TRIGGERMODE",0x20011114,3,"R/W","Interrupt source 22 trigger mode (reserved)"},
{"INC_SRC23_TRIGGERMODE",0x20011118,3,"R/W","Interrupt source 23 trigger mode (reserved)"},
{"INC_SRC24_TRIGGERMODE",0x2001111C,3,"R/W","External interrupt source 0 trigger mode"},
{"INC_SRC25_TRIGGERMODE",0x20011120,3,"R/W","External interrupt source 1 trigger mode"},
{"INC_SRC26_TRIGGERMODE",0x20011124,3,"R/W","External interrupt source 2 trigger mode"},
{"INC_SRC27_TRIGGERMODE",0x20011128,3,"R/W","External interrupt source 3 trigger mode"},
{"INC_SRC28_TRIGGERMODE",0x2001112C,3,"R/W","External interrupt source 4 trigger mode"},
{"INC_SRC29_TRIGGERMODE",0x20011130,3,"R/W","External interrupt source 5 trigger mode"},
{"INC_SRC30_TRIGGERMODE",0x20011134,3,"R/W","External interrupt source 6 trigger mode"},
{"INC_SRC_CLEAR_MASK",0x200111B4,31,"W","Clear interrupt-source enable register"},
{"INC_SRC_SET_MASK",0x200111B8,31,"W","Set interrupt-source enable mask"},
{"INC_SRC_MASK",0x200111BC,31,"R/W","Interrupt-source enable mask"},
{"INC_SELNOTINV",0x200111C8,3,"R/W","External interrupt pin is set to active high or active low"},
{"INC_EN_INT",0x200111CC,3,"R/W","Enable external interrupt to wake-up the low-power controller"},
{"INC_SRC_STATUS",0x200111DC,31,"R","Gives the latched status of an interrupt source"},
{"INC_SRC_CLEAR",0x200111EC,31,"R","Clears the INC_SRC_STATUS register"},
/************************/
/* MPEGDMA0 (MPEGDMA) */
/************************/
{"MPEGDMA0_BURSTSIZE",0x20024000,5,"W","The number of bytes to be transferred in one burst"},
{"MPEGDMA0_HOLDOFF",0x20024004,5,"W","Holdoff for MPEG decoder: range 0 to 31, where 0=0 delay cycles"},
{"MPEGDMA0_ABORT",0x20024008,1,"W","Abort all operation"},
{"MPEGDMA0_WHICHDEC",0x2002400C,2,"W","DMA destination pointer"},
{"MPEGDMA0_STATUS",0x20024010,2,"R","Interrupt status register"},
{"MPEGDMA0_INTACK",0x20024014,1,"W","Interrupt acknowledge register"},
{"MPEGDMA0_SRCADD",0x20024018,32,"W","DMA source pointer"},
{"MPEGDMA0_CNTRL",0x2002401C,2,"R/W","Interrupt control register"},
{"MPEGDMA0_BLSIZE",0x20024020,16,"W","Data block dimension to be transferred"},
/************************/
/* MPEGDMA1 (MPEGDMA) */
/************************/
{"MPEGDMA1_BURSTSIZE",0x20025000,5,"W","The number of bytes to be transferred in one burst"},
{"MPEGDMA1_HOLDOFF",0x20025004,5,"W","Holdoff for MPEG decoder: range 0 to 31, where 0=0 delay cycles"},
{"MPEGDMA1_ABORT",0x20025008,1,"W","Abort all operation"},
{"MPEGDMA1_WHICHDEC",0x2002500C,2,"W","DMA destination pointer"},
{"MPEGDMA1_STATUS",0x20025010,2,"R","Interrupt status register"},
{"MPEGDMA1_INTACK",0x20025014,1,"W","Interrupt acknowledge register"},
{"MPEGDMA1_SRCADD",0x20025018,32,"W","DMA source pointer"},
{"MPEGDMA1_CNTRL",0x2002501C,2,"R/W","Interrupt control register"},
{"MPEGDMA1_BLSIZE",0x20025020,16,"W","Data block dimension to be transferred"},
/****************************/
/* BLOCK MOVE DMA (BMDMA) */
/****************************/
{"BMDMA_SRCADDRESS ",0x20026000,32,"W","Block move DMA source address"},
{"BMDMA_DESTADDRESS",0x20026004,32,"W","Block move DMA destination address"},
{"BMDMA_COUNT",0x20026008,16,"W","Block move DMA counts"},
{"BMDMA_INTEN",0x2002600C,1,"R/W","Block move DMA interrupt enable"},