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st20.c
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st20.c
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/********************************************************************/
/* 16/12/2011 -Fixed 'bitcnt' instruction */
/* -Added some detailed instruction comment */
/* 19/12/2011 -Added 'db' (query database) command */
/* 20/12/2011 -Added 'vra' (verbose register access) command */
/* that show info's also in 'go' mode */
/* (added a status flag into struct cmdState_struct) */
/* -fixed some C4996 warnings about float->long and */
/* long->float. A cast has been enough. */
/* -implemented binary search trough db entries */
/* and put all registers in a more suitable form */
/* 23/12/2011 -check all registers entries order. */
/* -create Defines for 'h2idc.idc' IDA Script */
/* -compiled with static libraries. */
/* 26/12/2011 -'g' command can be interrupted hitting the 'g' key */
/* -added a less detailed description based upon the */
/* STi5518 memory map */
/* 31/12/2011 -new year's eve :) */
/* -added 'omr' command (OtherMachineRegisters) */
/* -added 'ver' command (View Enables Register) */
/* -added cpucycles quasi-precise clock */
/* -added these instructions: */
/* 'gintenb/gintdis' */
/* 'trapenb/trapdis' */
/* 'ldclock/clockenb/clockdis' */
/* 'timerenb/timerdis' */
/* 04/01/2012 -various bug fixed around the code */
/* -emulation cycle now is better */
/* -HighPriority and LowPriority ClockReg more precise */
/********************************************************************/
#include "stdafx.h"
#include "defines.h"
#include "memory.h"
#include "commands.h"
#include "st20.h"
//my new includes
#include "STi5518_SearchDB.h" //Internal DB facility
#include "OMR.h" //Other Machine Registers include file
static OMRSTATE omrState; //The OMR register itself
static CPUSTATE cpuState;
static WATCH watch;
static long instrCode=0;
static long operand=(long)START_ADDR;
static unsigned char instrBytes[100];
static int instrLength=0;
static long st20ProductId=ST20_PRODUCT_ID;
static long memStartVal=MEM_START_VAL;
static long timerGuess=TIMER_GUESS;
static long startAddr=START_ADDR;
static long wptrEndAddr=WPTR_END_ADDR;
static INSTRENTRY instrEntry[] = {
/*00*/ {"j", j_,5},
{"ldlp", ldlp_,1},
{"invalidop", invalidOp_,0},
{"ldnl", ldnl_,2},
{"ldc", ldc_,1},
{"ldnlp", ldnlp_,1},
{"invalidop", invalidOp_,0},
{"ldl", ldl_,1},
{"adc", adc_,1},
{"call", call_,8},
{"cj", cj_,5},
{"ajw", ajw_,2},
{"eqc", eqc_,1},
{"stl", stl_,1},
{"stnl", stnl_,2},
{"invalidop", invalidOp_,0},
/*000*/ {"rev", rev_,1},
{"lb", lb_,1},
{"bsub", bsub_,1},
{"endp", invalidOp_,0},
{"diff", diff_,1},
{"add", add_,1},
{"gcall", gcall_,6},
{"in", invalidOp_,0},
{"prod", prod_,4},
{"gt", gt_,1},
{"wsub", wsub_,1},
{"out", invalidOp_,0},
{"sub", sub_,1},
{"startp", startp_,5},
{"outbyte", invalidOp_,0},
{"outword", invalidOp_,0},
/*010*/ {"seterr", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"resetch", resetch_,3},
{"csub0", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"stopp", stopp_,2},
{"ladd", ladd_,2},
{"stlb", invalidOp_,0},
{"sthf", invalidOp_,0},
{"norm", invalidOp_,0},
{"ldiv", ldiv_,39}, // 5 to 39
{"ldpi", ldpi_,1},
{"stlf", invalidOp_,0},
{"xdble", xdble_,2},
{"ldpri", ldpri_,1},
{"rem", invalidOp_,0},
/*020*/ {"ret", ret_,3},
{"lend", invalidOp_,0},
{"ldtimer", ldtimer_,1},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"testerr", invalidOp_,0},
{"testpranal", invalidOp_,0},
{"tin", invalidOp_,0},
{"div", div_,37}, // 5 to 37
{"invalidop", invalidOp_,0},
{"dist", invalidOp_,0},
{"disc", invalidOp_,0},
/*030*/ {"diss", invalidOp_,0},
{"lmul", lmul_,6}, // 5 to 6
{"not", not_,1},
{"xor", xor_,1},
{"bcnt", bcnt_,1},
{"lshr", lshr_,2},
{"lshl", lshl_,2},
{"lsum", lsum_,2},
{"lsub", lsub_,2},
{"runp", runp_,3},
{"xword", invalidOp_,0},
{"sb", sb_,2},
{"gajw", gajw_,3},
{"savel", invalidOp_,0},
{"saveh", invalidOp_,0},
{"wcnt", wcnt_,1},
/*040*/ {"shr", shr_,1},
{"shl", shl_,1},
{"mint", mint_,1},
{"alt", invalidOp_,0},
{"altwt", invalidOp_,0},
{"altend", invalidOp_,0},
{"and", and_,1},
{"enbt", invalidOp_,0},
{"enbc", invalidOp_,0},
{"enbs", invalidOp_,0},
{"move", move_,1}, //CPUCycles not reported in Datasheet
{"or", or_,1},
{"csngl", invalidOp_,0},
{"ccnt1", invalidOp_,0},
{"talt", invalidOp_,0},
{"ldiff", ldiff_,2},
/*050*/ {"sthb", invalidOp_,0},
{"taltwt", invalidOp_,0},
{"sum", sum_,1},
{"mul", mul_,4},
{"sttimer", sttimer_,2},
{"stoperr", invalidOp_,0},
{"cword", invalidOp_,0},
{"clrhalterr", invalidOp_,0},
{"sethalterr", invalidOp_,0},
{"testhalterr", invalidOp_,0},
{"dup", dup_,1},
{"move2dinit", invalidOp_,0},
{"move2dall", invalidOp_,0},
{"move2dnonzero", invalidOp_,0},
{"move2dzero", invalidOp_,0},
{"gtu", gtu_,1},
/*060*/ {"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"unpacksn", invalidOp_,0},
{"slmul", invalidOp_,0},
{"sulmul", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"satadd", invalidOp_,0},
{"satsub", invalidOp_,0},
{"satmul", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"postnormsn", invalidOp_,0},
{"roundsn", invalidOp_,0},
{"ldtraph", ldtraph_,12},
{"sttraph", invalidOp_,0},
/*070*/ {"invalidop", invalidOp_,0},
{"ldinf", invalidOp_,0},
{"fmul", invalidOp_,0},
{"cflerr", invalidOp_,0},
{"crcword", invalidOp_,0},
{"crcbyte", invalidOp_,0},
{"bitcnt", bitcnt_,3},
{"bitrevword", invalidOp_,0},
{"bitrevnbits", invalidOp_,0},
{"pop", pop_,1},
{"invalidop", invalidOp_,0},
{"ldprodid", ldprodid_,1},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"ldmemstartval", ldmemstartval_,1},
{"invalidop", invalidOp_,0},
/*080*/ {"invalidop", invalidOp_,0},
{"wsubdb", wsubdb_,1},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
/*090*/ {"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"fptesterr", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
/*0A0*/ {"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
/*0B0*/ {"settimeslice", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"xbword", invalidOp_,0},
{"lbx", lbx_,1},
{"cb", invalidOp_,0},
{"cbu", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
/*0C0*/ {"invalidop", invalidOp_,0},
{"ssub", ssub_,1},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"intdis", invalidOp_,0},
{"intenb", invalidOp_,0},
{"ldtrapped", invalidOp_,0},
{"cir", invalidOp_,0},
{"ss", ss_,2},
{"invalidop", invalidOp_,0},
{"ls", ls_,1},
{"sttrapped", invalidOp_,0},
{"ciru", invalidOp_,0},
{"gintdis", gintdis_,5},
{"gintenb", gintenb_,5},
{"invalidop", invalidOp_,0},
/*0D0*/ {"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
/*0E0*/ {"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
/*0F0*/ {"devlb", devlb_,3},
{"devsb", devsb_,3},
{"devls", devls_,3},
{"devss", devss_,3},
{"devlw", devlw_,3},
{"devsw", devsw_,3},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"xsword", xsword_,3},
{"lsx", invalidOp_,0},
{"cs", invalidOp_,0},
{"csu", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
/*100*/ {"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
/*110*/ {"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
/*120*/ {"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
/*130*/ {"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
/*140*/ {"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
/*150*/ {"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
/*160*/ {"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
/*170*/ {"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"ldprodid", ldprodid_,1},
{"reboot", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
/*180*/ {"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
/*190*/ {"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
/*1A0*/ {"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
/*1B0*/ {"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"stclock", stclock_,2},
{"ldclock", ldclock_,2},
{"clockdis", clockdis_,2},
{"clockenb", clockenb_,2},
/*1C0*/ {"nop", nop_,1},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
/*1D0*/ {"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"devmove", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"restart", invalidOp_,0},
{"causeerror", invalidOp_,0},
/*1E0*/ {"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"iret", invalidOp_,0},
/*1F0*/ {"swapqueue", invalidOp_,0},
{"swaptimer", invalidOp_,0},
{"insertqueue", invalidOp_,0},
{"timeslice", invalidOp_,0},
{"signal", signal_,12}, // 7 to 12
{"wait", wait_,11}, // 5 to 11
{"trapdis", trapdis_,4},
{"trapenb", trapenb_,4},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"tret", invalidOp_,0},
{"ldshadow", invalidOp_,0},
{"stshadow", invalidOp_,0},
{"invalidop", invalidOp_,0},
{"invalidop", invalidOp_,0},
/*200*/ {"lddevid", lddevid_,1}
};
int st20Init (PARMS *userParms, FILE *outFp) {
int i;
long value;
for (i=0; i < userParms->nParms; i++) {
if (!stricmp(userParms->parameter[i], ST20_PRODUCT_ID_CH)) {
if (sscanf (userParms->value[i], "%x", &value) == 1) {
st20ProductId = value;
}
}
else if (!stricmp(userParms->parameter[i], MEM_START_VAL_CH)) {
if (sscanf (userParms->value[i], "%x", &value) == 1) {
memStartVal = value;
}
}
else if (!stricmp(userParms->parameter[i], TIMER_GUESS_CH)) {
if (sscanf (userParms->value[i], "%x", &value) == 1) {
timerGuess = value;
}
}
else if (!stricmp(userParms->parameter[i], WPTR_END_ADDR_CH)) {
if (sscanf (userParms->value[i], "%x", &value) == 1) {
wptrEndAddr = value;
}
}
else if (!stricmp(userParms->parameter[i], START_ADDR_CH)) {
if (sscanf (userParms->value[i], "%x", &value) == 1) {
startAddr = value;
}
}
}
fprintf (outFp, "START_ADDR=0x%08x\nMEM_START_VAL=0x%08x\nST20_PRODUCT_ID=0x%08x\n\
TIMER_GUESS=0x%08x\nWPTR_END_ADDR=0x%08x\n",
startAddr, memStartVal, st20ProductId, timerGuess, wptrEndAddr);
initCPUState();
initWatch();
// added for timers
initTimer(outFp);
return (0);
}
/**************************
* Initialize the processor
*/
int initCPUState (void) {
int i;
int result=0;
long address;
/* prepare to start the processing at 0x7FFFFFFE */
instrCode = 0;
operand = (long) startAddr;
instrLength = 0;
/* initialize the state of the processor */
cpuState.nWptr = 7;
cpuState.wptrUsed[0] = TRUE;
cpuState.wptrUsed[1] = TRUE;
cpuState.wptrUsed[2] = TRUE;
cpuState.wptrUsed[3] = TRUE;
cpuState.wptrUsed[4] = TRUE;
cpuState.wptrUsed[5] = TRUE;
cpuState.wptrUsed[6] = TRUE;
addrWptrWord ((int) 0, &address);
result = allocBytes (address-4*7, 4*7);
/* cpuState.wptr[0] = UNDEFINED_WORD;*/
for (i=7; i < MAX_WPTR; i++) {
cpuState.wptrUsed[i] = FALSE;
}
cpuState.areg = cpuState.breg = cpuState.creg = UNDEFINED_WORD;
cpuState.iptr = 0;
return (result);
}
int initWatch (void) {
watch.watchAreg = FALSE;
watch.watchBreg = FALSE;
watch.watchCreg = FALSE;
watch.watchIptr = FALSE;
watch.watchNWptr = FALSE;
return (0);
}
int saveCPUState (char *dirName, FILE *outFp) {
char cpuFileName[NAME_SIZE];
int cpuFileFd=-1;
if (sprintf (cpuFileName, "%s/cpu.bin", dirName) == EOF) {
return (INVALID_CPU_FILENAME);
}
if ((cpuFileFd = open(cpuFileName,
O_BINARY|O_WRONLY|O_CREAT|O_TRUNC,
S_IREAD|S_IWRITE)) < 0) {
perror ("CPU state save file cannot be opened");
return (INVALID_CPU_FILE);
}
if (write (cpuFileFd, (void *) &cpuState, sizeof (CPUSTATE)) < 0) {
return (INVALID_CPU_WRITE);
}
if (write (cpuFileFd, (void *) &wptrEndAddr, 4) < 0) {
return (INVALID_CPU_WRITE);
}
if (write (cpuFileFd, (void *) &watch, sizeof (WATCH)) < 0) {
return (INVALID_CPU_WRITE);
}
close (cpuFileFd);
return (0);
}
long get_iptr (void) {
return(cpuState.iptr);
}
int loadCPUState (char *dirName, FILE *outFp) {
char cpuFileName[NAME_SIZE];
int cpuFileFd=-1;
if (sprintf (cpuFileName, "%s/cpu.bin", dirName) == EOF) {
return (INVALID_CPU_FILENAME);
}
if ((cpuFileFd = open(cpuFileName,
O_BINARY|O_RDONLY,
S_IREAD|S_IWRITE)) < 0) {
perror ("CPU state save file cannot be opened");
return (INVALID_CPU_FILE);
}
if (read (cpuFileFd, &cpuState, sizeof (CPUSTATE)) <= 0) {
return (INVALID_CPU_READ);
}
if (read (cpuFileFd, &wptrEndAddr, 4) <= 0) {
return (INVALID_CPU_READ);
}
if (read (cpuFileFd, &watch, sizeof (WATCH)) <= 0) {
return (INVALID_CPU_READ);
}
close (cpuFileFd);
return (0);
}
int setWatch (char *reg, char *parm) {
int enable;
long value;
if (strcmpi (parm, "clear")) {
enable = TRUE;
}
else {
enable = FALSE;
}
sscanf (parm, "%x", &value);
switch (reg[0]) {
case 'a':
case 'A': watch.watchAreg = enable;
watch.areg = value;
break;
case 'b':
case 'B': watch.watchBreg = enable;
watch.breg = value;
break;
case 'c':
case 'C': watch.watchCreg = enable;
watch.creg = value;
break;
case 'i':
case 'I': watch.watchIptr = enable;
watch.iptr = value;
break;
case 'w':
case 'W': watch.watchNWptr = enable;
watch.nWptr = value;
break;
default: return (BAD_WATCH_CONDITION);
break;
}
return (0);
}
int anyWatch () {
return (watch.watchAreg || watch.watchBreg || watch.watchCreg ||
watch.watchIptr || watch.watchNWptr);
}
int checkWatch () {
int result=FALSE;
result |= (int) (watch.watchAreg && (cpuState.areg == watch.areg));
result |= (int) (watch.watchBreg && (cpuState.breg == watch.breg));
result |= (int) (watch.watchCreg && (cpuState.creg == watch.creg));
result |= (int) (watch.watchIptr && (cpuState.iptr == watch.iptr));
result |= (int) (watch.watchNWptr && (cpuState.nWptr == watch.nWptr));
return (result);
}
/**************************
* Print the values in the processor state
*/
int printCPUState (FILE *outFp) {
int i;
int result=0;
long address;
long value;
fprintf (outFp, "A=0x%08x B=0x%08x C=0x%08x Iptr=0x%08x \n",
cpuState.areg, cpuState.breg, cpuState.creg, cpuState.iptr);
for (i=0; i < cpuState.nWptr; i++) {
if (i == 0) {
fprintf (outFp, "Wptr");
}
addrWptrWord (i, &address);
result = readBytes (address, 4, &value);
fprintf (outFp, " %2x=0x%08x", i, value);
if (i%WPTR_PRINT_COLS == WPTR_PRINT_COLS-1) {
fprintf (outFp, "\n ");
}
}
fprintf (outFp, "\n\n");
return (result);
}
/**************************
* Print the values of the OMR
*/
int printOMRState (FILE *outFp) {
//show the OMR Enables register
fprintf(outFp, "OTHER MACHINE REGISTERS\n");
fprintf(outFp, "-----------------------\n");
fprintf(outFp, "Enables=0x%08x\n",omrState.Enables);
fprintf(outFp, "ClockRegHP=0x%08x ",omrState.ClockRegHP);
fprintf(outFp, "ClockRegLP=0x%08x ",omrState.ClockRegLP);
fprintf(outFp, "ClockEnables=0x%02x \n",omrState.ClockEnables);
fprintf(outFp, "HP_ErrFlag=0x%02x ",omrState.HP_ErrorFlag);
fprintf(outFp, "LP_ErrFlag=0x%02x ",omrState.LP_ErrorFlag);
fprintf(outFp, "HaltOnError=0x%02x\n",omrState.HaltOnErrorFlag);
return(0);
}
/**************************
* Print the values in the Enables Register
*/
int printEnablesRegState (FILE *outFp) {
fprintf(outFp, "Enables Register Value=0x%08x\n",omrState.Enables);
//fprintf(outFp,"-GLOBAL INTERRUPTS ENABLES VALUES-\n");
if(omrState.Enables & LP_PROCESS_INT_ENB)
fprintf(outFp," LP_PROCESS_INT_ENB is set\n");
if(omrState.Enables & LP_TIMESLICE_ENB)
fprintf(outFp," LP_TIMESLICE_ENB is set\n");
if(omrState.Enables & LP_EXTERNALEVENT_ENB)
fprintf(outFp," LP_EXTERNALEVENT_ENB is set\n");
if(omrState.Enables & LP_TIMER_ALRM_ENB)
fprintf(outFp," LP_TIMER_ALRM_ENB is set\n");
if(omrState.Enables & HP_PROCESS_INT_ENB)
fprintf(outFp," HP_PROCESS_INT_ENB is set\n");
if(omrState.Enables & HP_TIMESLICE_ENB)
fprintf(outFp," HP_TIMESLICE_ENB is set\n");
if(omrState.Enables & HP_EXTERNALEVENT_ENB)
fprintf(outFp," HP_EXTERNALEVENT_ENB is set\n");
if(omrState.Enables & HP_TIMER_ALRM_ENB)
fprintf(outFp," HP_TIMER_ALRM_ENB is set\n");
//fprintf(outFp,"-TRAP ENABLES VALUES-\n");
if(omrState.Enables & BREAKPOINT_TRAPENB)
fprintf(outFp," BREAKPOINT_TRAPENB is set\n");
if(omrState.Enables & INTEGER_ERR_TRAPENB)
fprintf(outFp," INTEGER_ERR_TRAPENB is set\n");
if(omrState.Enables & INTEGER_OVF_TRAPENB)
fprintf(outFp," INTEGER_OVF_TRAPENB is set\n");
if(omrState.Enables & ILL_OPCODE_TRAPENB)
fprintf(outFp," ILL_OPCODE_TRAPENB is set\n");
if(omrState.Enables & LOADTRAP_TRAPENB)
fprintf(outFp," LOADTRAP_TRAPENB is set\n");
if(omrState.Enables & STORETRAP_TRAPENB)
fprintf(outFp," STORETRAP_TRAPENB is set\n");
if(omrState.Enables & INTERNALCH_TRAPENB)
fprintf(outFp," INTERNALCH_TRAPENB is set\n");
if(omrState.Enables & EXTERNALCH_TRAPENB)
fprintf(outFp," EXTERNALCH_TRAPENB is set\n");
if(omrState.Enables & TIMER_TRAPENB)
fprintf(outFp," TIMER_TRAPENB is set\n");
if(omrState.Enables & TIMESLICE_TRAPENB)
fprintf(outFp," TIMESLICE_TRAPENB is set\n");
if(omrState.Enables & RUN_TRAPENB)
fprintf(outFp," RUN_TRAPENB is set\n");
if(omrState.Enables & SIGNAL_TRAPENB)
fprintf(outFp," SIGNAL_TRAPENB is set\n");
if(omrState.Enables & PROCESS_TRAPENB)
fprintf(outFp," PROCESS_TRAPENB is set\n");
if(omrState.Enables & QUEUE_EMPTY_TRAPENB)
fprintf(outFp," QUEUE_EMPTY_TRAPENB is set\n");
return (0);
}
/**************************
* Get the bytes for the next instruction and determine what the instruction
* code and operand are
*/
int decodeNextInstr(FILE *outFp) {
int foundInstr=FALSE;
unsigned long cByte;
int result;
instrCode = 0;
operand = 0;
instrLength = 0;
/* keep reading a byte until we've found a non-prefix byte */
while (!foundInstr) {
/* read the next byte of the current instruction */
result = readBytes (cpuState.iptr + instrLength, 1, &cByte);
if (result) {
fprintf (outFp, "%s\n", memoryError (result));
fprintf (outFp, "Error occurred when reading instruction at %8x, offset %2x\n",
cpuState.iptr, instrLength);
return (-1);
}
/* save the bytes that comprise the current instruction */
instrBytes[instrLength++] = (char) (cByte & 0xFF);
/* extract the data part of the current instruction byte */
operand <<= 4;
operand += cByte & 0x0F;
/* extract the instruction part of the current byte */
instrCode = cByte & 0xF0;
instrCode >>= 4;
/*
* The prefix encoded instructions are multi-byte instructions
* (either the data or the instruction is composed of multiple bytes).
* We have to accumulate all of the bytes in the instruction before
* we can determine what the instruction and the operand are.
*/
switch (instrCode) {
case 0x02: foundInstr = FALSE;
break;
case 0x06: operand = ~operand;
foundInstr = FALSE;
break;
/*
* All multibyte instruction codes use Fx as the final byte in the
* instruction. These instructions require no operands so the
* operand is used as an extended instruction code.
* We add 0x10 to the instruction code to avoid conflicts with
* the opcodes from the non-extended instructions.
* The lddevid code will end up with the same code as ldprodid.
* So we'll map it to 0x200 to avoid the conflict.
*/
case 0x0F: if (operand == 0x17C) {
instrCode = LDDEVID;
}
else {
instrCode = (operand & 0x1FF) + 0x10;
}
foundInstr=TRUE;
break;
/* all of the non-Fx single byte instructions are handled here */
default: foundInstr=TRUE;
break;
}
}
return (0);
}
/**************************
* Print out the address, bytes and decoded instruction to be executed next
*/
int printNextInstr (FILE *outFp) {
int i;
char operandCh[100];
fprintf (outFp, "%08x ", cpuState.iptr);
for (i=0; i < instrLength; i++) {
fprintf (outFp, "%2x ", instrBytes[i]);