From ad9f613c57923cb09ae7e38bf73887a81c12b9c1 Mon Sep 17 00:00:00 2001 From: IFX-Anusha Date: Mon, 21 Oct 2024 15:01:48 +0530 Subject: [PATCH] ports/psoc6: I2S test modify. Signed-off-by: IFX-Anusha --- ports/psoc6/machine_i2s.c | 33 +++--- ports/psoc6/modmachine.c | 105 +++++++++++++++++- .../ports/psoc6/board_ext_hw/multi/i2s_rx.py | 6 + 3 files changed, 126 insertions(+), 18 deletions(-) diff --git a/ports/psoc6/machine_i2s.c b/ports/psoc6/machine_i2s.c index 60157871b73a..e359f4d28209 100644 --- a/ports/psoc6/machine_i2s.c +++ b/ports/psoc6/machine_i2s.c @@ -367,20 +367,20 @@ static void mp_machine_i2s_init_helper(machine_i2s_obj_t *self, mp_arg_val_t *ar mp_raise_ValueError(MP_ERROR_TEXT("invalid format")); } - // is valid clock freq? - uint32_t audio_clock_freq_hz; - uint32_t rate = args[ARG_rate].u_int; - if (rate == 8000 || - rate == 16000 || - rate == 32000 || - rate == 48000) { - audio_clock_freq_hz = AUDIO_SYS_CLOCK_98_304_000_HZ; - } else if (rate == 22050 || - rate == 44100) { - audio_clock_freq_hz = AUDIO_SYS_CLOCK_90_300_000_HZ; - } else { - mp_raise_ValueError(MP_ERROR_TEXT("rate not supported")); - } + // // is valid clock freq? + // uint32_t audio_clock_freq_hz; + // uint32_t rate = args[ARG_rate].u_int; + // if (rate == 8000 || + // rate == 16000 || + // rate == 32000 || + // rate == 48000) { + // audio_clock_freq_hz = AUDIO_SYS_CLOCK_98_304_000_HZ; + // } else if (rate == 22050 || + // rate == 44100) { + // audio_clock_freq_hz = AUDIO_SYS_CLOCK_90_300_000_HZ; + // } else { + // mp_raise_ValueError(MP_ERROR_TEXT("rate not supported")); + // } // is valid buf size ? int32_t ring_buffer_len = args[ARG_ibuf].u_int; @@ -395,7 +395,7 @@ static void mp_machine_i2s_init_helper(machine_i2s_obj_t *self, mp_arg_val_t *ar self->bits = i2s_bits; self->channel_resolution_bits = i2s_bits_resolution; self->format = i2s_format; - self->rate = rate; + self->rate = args[ARG_rate].u_int; self->ibuf = ring_buffer_len; self->callback_for_non_blocking = MP_OBJ_NULL; self->io_mode = BLOCKING; @@ -403,7 +403,8 @@ static void mp_machine_i2s_init_helper(machine_i2s_obj_t *self, mp_arg_val_t *ar ringbuf_init(&self->ring_buffer, self->ring_buffer_storage, ring_buffer_len); // i2s_audio_clock_init(audio_clock_freq_hz); - audio_i2s_set_frequency(audio_clock_freq_hz); + // audio_i2s_set_frequency(audio_clock_freq_hz, &audio_clock); + // mp_printf(&mp_plat_print, "clock pointer: %p\n", audio_clock); i2s_init(self, &audio_clock); i2s_dma_init(self); } diff --git a/ports/psoc6/modmachine.c b/ports/psoc6/modmachine.c index 9d34f412f194..bc8815c5b145 100644 --- a/ports/psoc6/modmachine.c +++ b/ports/psoc6/modmachine.c @@ -65,7 +65,8 @@ enum { enum clock_freq_type { AUDIO_I2S, AUDIO_PDM, - CM4 + CM4, + CM4_FLL }; uint32_t reset_cause; @@ -325,6 +326,103 @@ void cm4_set_frequency(uint32_t freq) { } +void cm4_fll_set_frequency(uint32_t freq) { + cyhal_clock_t clock_fast; + cyhal_clock_t clock_slow; + cyhal_clock_t clock_fll; + cyhal_clock_t clock_hf0; + cyhal_clock_t clock_peri; + + // deinitialize retarget-io before changing the clock frequency + cy_retarget_io_deinit(); + + /* Initialize, take ownership of PLL0/PLL */ + cyhal_clock_reserve(&clock_pll, &CYHAL_CLOCK_FLL[0]); + + /* Set the PLL0/PLL frequency to PLL_CLOCK_HZ =150 MHZ*/ + cy_rslt_t result = cyhal_clock_set_frequency(&clock_fll, freq, NULL); + clock_assert_raise_val("PLL clock reserve failed with error code: %lx", result); + + /* If the PLL0/PLL clock is not already enabled, enable it */ + if (!cyhal_clock_is_enabled(&clock_fll)) { + result = cyhal_clock_set_enabled(&clock_fll, true, true); + clock_assert_raise_val("PLL clock enable failed with error code: %lx", result); + } + + // HF0 + /* Initialize, take ownership of CLK_HF0 */ + result = cyhal_clock_reserve(&clock_hf0, &CYHAL_CLOCK_HF[0]); + clock_assert_raise_val("HF0 clock reserve failed with error code: %lx", result); + + /* Source the (CLK_HF0) from PLL0/PLL */ + result = cyhal_clock_set_source(&clock_hf0, &clock_fll); + clock_assert_raise_val("HF0 clock source failed with error code: %lx", result); + + /* Set the divider for (CLK_HF0) */ + result = cyhal_clock_set_divider(&clock_hf0, 1); + clock_assert_raise_val("HF0 clock set divider failed with error code: %lx", result); + + /* (CLK_HF0) is not already enabled, enable it */ + if (!cyhal_clock_is_enabled(&clock_hf0)) { + result = cyhal_clock_set_enabled(&clock_hf0, true, true); + clock_assert_raise_val("HF0 clock enable failed with error code: %lx", result); + } + // HF0 + + // Fast clock + result = cyhal_clock_reserve(&clock_fast, &CYHAL_CLOCK_FAST); + clock_assert_raise_val("Fast clock reserve failed with error code: %lx", result); + + result = cyhal_clock_set_divider(&clock_fast, 1); + clock_assert_raise_val("Fast clock set divider failed with error code: %lx", result); + + + + if (!cyhal_clock_is_enabled(&clock_fast)) { + result = cyhal_clock_set_enabled(&clock_fast, true, true); + clock_assert_raise_val("Fast clock enable failed with error code: %lx", result); + } + // Fast clock + + // Peri clock + result = cyhal_clock_reserve(&clock_peri, &CYHAL_CLOCK_PERI); + clock_assert_raise_val("Peri clock reserve failed with error code: %lx", result); + + result = cyhal_clock_set_divider(&clock_peri, 2); + + if (!cyhal_clock_is_enabled(&clock_peri)) { + result = cyhal_clock_set_enabled(&clock_peri, true, true); + clock_assert_raise_val("Peri clock enable failed with error code: %lx", result); + } + // peri clock + + + // slow clock + result = cyhal_clock_reserve(&clock_slow, &CYHAL_CLOCK_SLOW); + clock_assert_raise_val("Slow clock reserve failed with error code: %lx", result); + + result = cyhal_clock_set_divider(&clock_slow, 1); + clock_assert_raise_val("Slow clock set divider failed with error code: %lx", result); + + if (!cyhal_clock_is_enabled(&clock_slow)) { + result = cyhal_clock_set_enabled(&clock_slow, true, true); + clock_assert_raise_val("Slow clock enable failed with error code: %lx", result); + } + // slow clock + + cyhal_clock_free(&clock_fast); + cyhal_clock_free(&clock_slow); + cyhal_clock_free(&clock_pll); + cyhal_clock_free(&clock_hf0); + cyhal_clock_free(&clock_peri); + + // Initialize retarget-io to use the debug UART port + result = cy_retarget_io_init(CYBSP_DEBUG_UART_TX, CYBSP_DEBUG_UART_RX, CY_RETARGET_IO_BAUDRATE); + if (result != CY_RSLT_SUCCESS) { + mp_raise_ValueError(MP_ERROR_TEXT("cy_retarget_io_init failed !\n")); + } +} + void audio_i2s_set_frequency(uint32_t freq) { if (freq != 98000000 && freq != 90000000) { @@ -427,7 +525,7 @@ void audio_pdm_set_frequency(uint32_t freq) { static void mp_machine_set_freq(size_t n_args, const mp_obj_t *args) { mp_int_t freq = mp_obj_get_int(args[0]); if (n_args == 1) { - cm4_set_frequency(freq); // core m4 fz + cm4_set_frequency(freq); // core m4 fz sourced by PLL } else if (n_args > 1) { enum clock_freq_type freq_peri = mp_obj_get_int(args[1]); // Assuming the enum values are used as integers switch (freq_peri) { @@ -437,6 +535,9 @@ static void mp_machine_set_freq(size_t n_args, const mp_obj_t *args) { case AUDIO_PDM: audio_pdm_set_frequency(freq); // pdm audio fz break; + case CM4_FLL: + cm4_fll_set_frequency(freq); // core m4 fz sourced by FLL + break; default: mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("Invalid frequency type %d"), freq_peri); break; diff --git a/tests/ports/psoc6/board_ext_hw/multi/i2s_rx.py b/tests/ports/psoc6/board_ext_hw/multi/i2s_rx.py index 8ec87932350c..469b89ccb23c 100644 --- a/tests/ports/psoc6/board_ext_hw/multi/i2s_rx.py +++ b/tests/ports/psoc6/board_ext_hw/multi/i2s_rx.py @@ -4,6 +4,7 @@ import time import array import struct +import machine # Allocate pin based on board board = os.uname().machine @@ -110,6 +111,11 @@ def print_i2s_format(raw_buf, bits): for _format in test_formats: for _bits in test_bits: for _rate in test_rates: + if test_rates == 22050 or test_rates == 44100: + freq = 98000000 + else: + freq = 90000000 + machine.freq(freq, machine.AUDIO_I2S) audio_in = I2S( 0, sck=sck_rx_pin,