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vivado.log
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#-----------------------------------------------------------
# Vivado v2019.1 (64-bit)
# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
# Start of session at: Wed May 4 20:12:07 2022
# Process ID: 54548
# Current directory: D:/ComputerArchitecture/pipeline_cpu
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent51288 D:\ComputerArchitecture\pipeline_cpu\pipeline_cpu.xpr
# Log file: D:/ComputerArchitecture/pipeline_cpu/vivado.log
# Journal file: D:/ComputerArchitecture/pipeline_cpu\vivado.jou
#-----------------------------------------------------------
start_gui
open_project D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.xpr
INFO: [Project 1-313] Project file moved from 'D:/computer structure/pipeline_cpu' since last save.
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2019.1/data/ip'.
open_project: Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 807.445 ; gain = 159.715
update_compile_order -fileset sources_1
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'testbench' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj testbench_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/adder.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module adder
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/alu.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module alu
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/aludec.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module aludec
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/controller.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module controller
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/datapath.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module datapath
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/dmem.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module dmem
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/eqcmp.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module eqcmp
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/flopenr.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module flopenr
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/flopenrc.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module flopenrc
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/flopr.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module flopr
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/floprc.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module floprc
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/hazard.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module hazard
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/imem.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module imem
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/maindec.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module maindec
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/mips.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module mips
INFO: [VRFC 10-2458] undeclared symbol branchD, assumed default net type wire [D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/mips.v:36]
INFO: [VRFC 10-2458] undeclared symbol jumpD, assumed default net type wire [D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/mips.v:36]
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/mux2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module mux2
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/mux3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module mux3
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/regfile.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module regfile
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/signext.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module signext
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/sl2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module sl2
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/top.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module top
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sim_1/new/testbench.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module testbench
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.sim/sim_1/behav/xsim'
"xelab -wto 3dee6fbea59345188b10480d1b248e35 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator 2019.1
Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2019.1/bin/unwrapped/win64.o/xelab.exe -wto 3dee6fbea59345188b10480d1b248e35 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.maindec
Compiling module xil_defaultlib.aludec
Compiling module xil_defaultlib.floprc
Compiling module xil_defaultlib.flopr(WIDTH=3)
Compiling module xil_defaultlib.flopr(WIDTH=2)
Compiling module xil_defaultlib.controller
Compiling module xil_defaultlib.hazard
Compiling module xil_defaultlib.mux2(WIDTH=32)
Compiling module xil_defaultlib.regfile
Compiling module xil_defaultlib.flopenr(WIDTH=32)
Compiling module xil_defaultlib.adder
Compiling module xil_defaultlib.flopenrc(WIDTH=32)
Compiling module xil_defaultlib.signext
Compiling module xil_defaultlib.sl2
Compiling module xil_defaultlib.eqcmp
Compiling module xil_defaultlib.floprc(WIDTH=32)
Compiling module xil_defaultlib.floprc(WIDTH=5)
Compiling module xil_defaultlib.mux3(WIDTH=32)
Compiling module xil_defaultlib.alu
Compiling module xil_defaultlib.mux2(WIDTH=5)
Compiling module xil_defaultlib.flopr(WIDTH=32)
Compiling module xil_defaultlib.flopr(WIDTH=5)
Compiling module xil_defaultlib.datapath
Compiling module xil_defaultlib.mips
Compiling module xil_defaultlib.imem
Compiling module xil_defaultlib.dmem
Compiling module xil_defaultlib.top
Compiling module xil_defaultlib.testbench
Compiling module xil_defaultlib.glbl
Built simulation snapshot testbench_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "testbench_behav -key {Behavioral:sim_1:Functional:testbench} -tclbatch {testbench.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2019.1
Time resolution is 1 ps
source testbench.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
WARNING: File D:/computer structure/pipeline_cpu/memfile.dat referenced on D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/imem.v at line 28 cannot be opened for reading. Please ensure that this file is available in the current working directory.
INFO: [USF-XSim-96] XSim completed. Design snapshot 'testbench_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 850.297 ; gain = 16.223
close [ open D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/memfile.mem w ]
add_files D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/memfile.mem
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'testbench' in fileset 'sim_1'...
INFO: [SIM-utils-43] Exported 'D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.sim/sim_1/behav/xsim/memfile.mem'
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj testbench_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/adder.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module adder
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/alu.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module alu
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/aludec.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module aludec
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/controller.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module controller
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/datapath.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module datapath
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/dmem.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module dmem
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/eqcmp.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module eqcmp
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/flopenr.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module flopenr
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/flopenrc.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module flopenrc
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/flopr.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module flopr
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/floprc.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module floprc
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/hazard.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module hazard
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/imem.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module imem
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/maindec.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module maindec
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/mips.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module mips
INFO: [VRFC 10-2458] undeclared symbol branchD, assumed default net type wire [D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/mips.v:36]
INFO: [VRFC 10-2458] undeclared symbol jumpD, assumed default net type wire [D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/mips.v:36]
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/mux2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module mux2
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/mux3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module mux3
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/regfile.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module regfile
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/signext.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module signext
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/sl2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module sl2
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/top.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module top
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sim_1/new/testbench.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module testbench
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.sim/sim_1/behav/xsim'
"xelab -wto 3dee6fbea59345188b10480d1b248e35 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator 2019.1
Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2019.1/bin/unwrapped/win64.o/xelab.exe -wto 3dee6fbea59345188b10480d1b248e35 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.maindec
Compiling module xil_defaultlib.aludec
Compiling module xil_defaultlib.floprc
Compiling module xil_defaultlib.flopr(WIDTH=3)
Compiling module xil_defaultlib.flopr(WIDTH=2)
Compiling module xil_defaultlib.controller
Compiling module xil_defaultlib.hazard
Compiling module xil_defaultlib.mux2(WIDTH=32)
Compiling module xil_defaultlib.regfile
Compiling module xil_defaultlib.flopenr(WIDTH=32)
Compiling module xil_defaultlib.adder
Compiling module xil_defaultlib.flopenrc(WIDTH=32)
Compiling module xil_defaultlib.signext
Compiling module xil_defaultlib.sl2
Compiling module xil_defaultlib.eqcmp
Compiling module xil_defaultlib.floprc(WIDTH=32)
Compiling module xil_defaultlib.floprc(WIDTH=5)
Compiling module xil_defaultlib.mux3(WIDTH=32)
Compiling module xil_defaultlib.alu
Compiling module xil_defaultlib.mux2(WIDTH=5)
Compiling module xil_defaultlib.flopr(WIDTH=32)
Compiling module xil_defaultlib.flopr(WIDTH=5)
Compiling module xil_defaultlib.datapath
Compiling module xil_defaultlib.mips
Compiling module xil_defaultlib.imem
Compiling module xil_defaultlib.dmem
Compiling module xil_defaultlib.top
Compiling module xil_defaultlib.testbench
Compiling module xil_defaultlib.glbl
Built simulation snapshot testbench_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "testbench_behav -key {Behavioral:sim_1:Functional:testbench} -tclbatch {testbench.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2019.1
Time resolution is 1 ps
source testbench.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
Simulation failed
$stop called at time : 145 ns : File "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sim_1/new/testbench.v" Line 49
INFO: [USF-XSim-96] XSim completed. Design snapshot 'testbench_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1182.242 ; gain = 0.000
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'testbench' in fileset 'sim_1'...
INFO: [SIM-utils-43] Exported 'D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.sim/sim_1/behav/xsim/memfile.mem'
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj testbench_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/adder.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module adder
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/alu.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module alu
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/aludec.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module aludec
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/controller.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module controller
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/datapath.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module datapath
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/dmem.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module dmem
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/eqcmp.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module eqcmp
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/flopenr.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module flopenr
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/flopenrc.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module flopenrc
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/flopr.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module flopr
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/floprc.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module floprc
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/hazard.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module hazard
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/imem.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module imem
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/maindec.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module maindec
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/mips.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module mips
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/mux2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module mux2
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/mux3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module mux3
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/regfile.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module regfile
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/signext.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module signext
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/sl2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module sl2
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/top.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module top
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sim_1/new/testbench.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module testbench
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.sim/sim_1/behav/xsim'
"xelab -wto 3dee6fbea59345188b10480d1b248e35 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator 2019.1
Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2019.1/bin/unwrapped/win64.o/xelab.exe -wto 3dee6fbea59345188b10480d1b248e35 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.maindec
Compiling module xil_defaultlib.aludec
Compiling module xil_defaultlib.floprc
Compiling module xil_defaultlib.flopr(WIDTH=3)
Compiling module xil_defaultlib.flopr(WIDTH=2)
Compiling module xil_defaultlib.controller
Compiling module xil_defaultlib.hazard
Compiling module xil_defaultlib.mux2(WIDTH=32)
Compiling module xil_defaultlib.regfile
Compiling module xil_defaultlib.flopenr(WIDTH=32)
Compiling module xil_defaultlib.adder
Compiling module xil_defaultlib.flopenrc(WIDTH=32)
Compiling module xil_defaultlib.signext
Compiling module xil_defaultlib.sl2
Compiling module xil_defaultlib.eqcmp
Compiling module xil_defaultlib.floprc(WIDTH=32)
Compiling module xil_defaultlib.floprc(WIDTH=5)
Compiling module xil_defaultlib.mux3(WIDTH=32)
Compiling module xil_defaultlib.alu
Compiling module xil_defaultlib.mux2(WIDTH=5)
Compiling module xil_defaultlib.flopr(WIDTH=32)
Compiling module xil_defaultlib.flopr(WIDTH=5)
Compiling module xil_defaultlib.datapath
Compiling module xil_defaultlib.mips
Compiling module xil_defaultlib.imem
Compiling module xil_defaultlib.dmem
Compiling module xil_defaultlib.top
Compiling module xil_defaultlib.testbench
Compiling module xil_defaultlib.glbl
Built simulation snapshot testbench_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "testbench_behav -key {Behavioral:sim_1:Functional:testbench} -tclbatch {testbench.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2019.1
Time resolution is 1 ps
source testbench.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
Simulation failed
$stop called at time : 145 ns : File "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sim_1/new/testbench.v" Line 49
INFO: [USF-XSim-96] XSim completed. Design snapshot 'testbench_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1182.242 ; gain = 0.000
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'testbench' in fileset 'sim_1'...
INFO: [SIM-utils-43] Exported 'D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.sim/sim_1/behav/xsim/memfile.mem'
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj testbench_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/adder.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module adder
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/alu.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module alu
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/aludec.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module aludec
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/controller.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module controller
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/datapath.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module datapath
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/dmem.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module dmem
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/eqcmp.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module eqcmp
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/flopenr.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module flopenr
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/flopenrc.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module flopenrc
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/flopr.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module flopr
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/floprc.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module floprc
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/hazard.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module hazard
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/imem.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module imem
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/maindec.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module maindec
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/mips.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module mips
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/mux2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module mux2
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/mux3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module mux3
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/regfile.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module regfile
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/signext.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module signext
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/sl2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module sl2
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/top.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module top
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sim_1/new/testbench.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module testbench
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.sim/sim_1/behav/xsim'
"xelab -wto 3dee6fbea59345188b10480d1b248e35 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator 2019.1
Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2019.1/bin/unwrapped/win64.o/xelab.exe -wto 3dee6fbea59345188b10480d1b248e35 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.maindec
Compiling module xil_defaultlib.aludec
Compiling module xil_defaultlib.floprc
Compiling module xil_defaultlib.flopr(WIDTH=3)
Compiling module xil_defaultlib.flopr(WIDTH=2)
Compiling module xil_defaultlib.controller
Compiling module xil_defaultlib.hazard
Compiling module xil_defaultlib.mux2(WIDTH=32)
Compiling module xil_defaultlib.regfile
Compiling module xil_defaultlib.flopenr(WIDTH=32)
Compiling module xil_defaultlib.adder
Compiling module xil_defaultlib.flopenrc(WIDTH=32)
Compiling module xil_defaultlib.signext
Compiling module xil_defaultlib.sl2
Compiling module xil_defaultlib.eqcmp
Compiling module xil_defaultlib.floprc(WIDTH=32)
Compiling module xil_defaultlib.floprc(WIDTH=5)
Compiling module xil_defaultlib.mux3(WIDTH=32)
Compiling module xil_defaultlib.alu
Compiling module xil_defaultlib.mux2(WIDTH=5)
Compiling module xil_defaultlib.flopr(WIDTH=32)
Compiling module xil_defaultlib.flopr(WIDTH=5)
Compiling module xil_defaultlib.datapath
Compiling module xil_defaultlib.mips
Compiling module xil_defaultlib.imem
Compiling module xil_defaultlib.dmem
Compiling module xil_defaultlib.top
Compiling module xil_defaultlib.testbench
Compiling module xil_defaultlib.glbl
Built simulation snapshot testbench_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "testbench_behav -key {Behavioral:sim_1:Functional:testbench} -tclbatch {testbench.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2019.1
Time resolution is 1 ps
source testbench.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
Simulation failed
$stop called at time : 145 ns : File "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sim_1/new/testbench.v" Line 49
INFO: [USF-XSim-96] XSim completed. Design snapshot 'testbench_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 1322.051 ; gain = 0.000
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'testbench' in fileset 'sim_1'...
INFO: [SIM-utils-43] Exported 'D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.sim/sim_1/behav/xsim/memfile.mem'
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj testbench_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/adder.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module adder
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/alu.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module alu
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/aludec.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module aludec
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/controller.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module controller
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/datapath.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module datapath
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/dmem.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module dmem
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/eqcmp.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module eqcmp
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/flopenr.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module flopenr
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/flopenrc.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module flopenrc
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/flopr.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module flopr
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/floprc.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module floprc
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/hazard.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module hazard
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/imem.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module imem
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/maindec.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module maindec
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/mips.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module mips
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/mux2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module mux2
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/mux3.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module mux3
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/regfile.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module regfile
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/signext.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module signext
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/sl2.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module sl2
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sources_1/new/top.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module top
INFO: [VRFC 10-2263] Analyzing Verilog file "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sim_1/new/testbench.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module testbench
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.sim/sim_1/behav/xsim'
"xelab -wto 3dee6fbea59345188b10480d1b248e35 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator 2019.1
Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2019.1/bin/unwrapped/win64.o/xelab.exe -wto 3dee6fbea59345188b10480d1b248e35 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.maindec
Compiling module xil_defaultlib.aludec
Compiling module xil_defaultlib.floprc
Compiling module xil_defaultlib.flopr(WIDTH=3)
Compiling module xil_defaultlib.flopr(WIDTH=2)
Compiling module xil_defaultlib.controller
Compiling module xil_defaultlib.hazard
Compiling module xil_defaultlib.mux2(WIDTH=32)
Compiling module xil_defaultlib.regfile
Compiling module xil_defaultlib.flopenr(WIDTH=32)
Compiling module xil_defaultlib.adder
Compiling module xil_defaultlib.flopenrc(WIDTH=32)
Compiling module xil_defaultlib.signext
Compiling module xil_defaultlib.sl2
Compiling module xil_defaultlib.eqcmp
Compiling module xil_defaultlib.floprc(WIDTH=32)
Compiling module xil_defaultlib.floprc(WIDTH=5)
Compiling module xil_defaultlib.mux3(WIDTH=32)
Compiling module xil_defaultlib.alu
Compiling module xil_defaultlib.mux2(WIDTH=5)
Compiling module xil_defaultlib.flopr(WIDTH=32)
Compiling module xil_defaultlib.flopr(WIDTH=5)
Compiling module xil_defaultlib.datapath
Compiling module xil_defaultlib.mips
Compiling module xil_defaultlib.imem
Compiling module xil_defaultlib.dmem
Compiling module xil_defaultlib.top
Compiling module xil_defaultlib.testbench
Compiling module xil_defaultlib.glbl
Built simulation snapshot testbench_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "testbench_behav -key {Behavioral:sim_1:Functional:testbench} -tclbatch {testbench.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2019.1
Time resolution is 1 ps
source testbench.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
Simulation succeeded
$stop called at time : 245 ns : File "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sim_1/new/testbench.v" Line 46
INFO: [USF-XSim-96] XSim completed. Design snapshot 'testbench_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 1562.348 ; gain = 0.000
close_sim
INFO: [Simtcl 6-16] Simulation closed
launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'testbench' in fileset 'sim_1'...
INFO: [SIM-utils-43] Exported 'D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.sim/sim_1/behav/xsim/memfile.mem'
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.sim/sim_1/behav/xsim'
"xvlog --incr --relax -prj testbench_vlog.prj"
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.sim/sim_1/behav/xsim'
"xelab -wto 3dee6fbea59345188b10480d1b248e35 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log"
Vivado Simulator 2019.1
Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2019.1/bin/unwrapped/win64.o/xelab.exe -wto 3dee6fbea59345188b10480d1b248e35 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot testbench_behav xil_defaultlib.testbench xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "testbench_behav -key {Behavioral:sim_1:Functional:testbench} -tclbatch {testbench.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2019.1
Time resolution is 1 ps
source testbench.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
Simulation succeeded
$stop called at time : 245 ns : File "D:/ComputerArchitecture/pipeline_cpu/pipeline_cpu.srcs/sim_1/new/testbench.v" Line 46
INFO: [USF-XSim-96] XSim completed. Design snapshot 'testbench_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 1562.348 ; gain = 0.000
close_sim
INFO: [Simtcl 6-16] Simulation closed
exit
INFO: [Common 17-206] Exiting Vivado at Thu May 5 12:15:30 2022...