diff --git a/bench/verilog/GPIA_BIT.v b/bench/verilog/GPIA_BIT.v
index 224a56c..0ec4e3b 100644
--- a/bench/verilog/GPIA_BIT.v
+++ b/bench/verilog/GPIA_BIT.v
@@ -5,7 +5,7 @@
  * identified by a number on the `scenario_o` bus.
  */
 
-module test();
+module test_bit();
 
 reg clk_o;
 reg rst_o;
diff --git a/bench/verilog/GPIA_BIT_IN.v b/bench/verilog/GPIA_BIT_IN.v
index 39df5fd..fe9e701 100644
--- a/bench/verilog/GPIA_BIT_IN.v
+++ b/bench/verilog/GPIA_BIT_IN.v
@@ -8,7 +8,7 @@
  * read the current state of the external signal attached to it.
  */
 
-module test();
+module test_bit_in();
 
 reg out_o;
 reg inp_o;
diff --git a/bench/verilog/GPIA_BYTE.v b/bench/verilog/GPIA_BYTE.v
index 493d3e7..8d631b1 100644
--- a/bench/verilog/GPIA_BYTE.v
+++ b/bench/verilog/GPIA_BYTE.v
@@ -16,7 +16,7 @@
  * - Toggle an arbitrary set of bits truth value in a single cycle.
  */
 
-module test();
+module test_byte();
 
 reg clk_o;
 reg rst_o;
diff --git a/bench/verilog/GPIA_DWORD.v b/bench/verilog/GPIA_DWORD.v
index b118dac..62eb639 100644
--- a/bench/verilog/GPIA_DWORD.v
+++ b/bench/verilog/GPIA_DWORD.v
@@ -19,7 +19,7 @@
  * stb_i inputs.
  */
 
-module test();
+module test_dword();
 
 reg clk_o;
 reg rst_o;