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cmos-logic.lbr
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cmos-logic.lbr
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<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE eagle SYSTEM "eagle.dtd">
<eagle version="9.0.1">
<drawing>
<settings>
<setting alwaysvectorfont="no"/>
<setting keepoldvectorfont="yes"/>
<setting verticaltext="up"/>
</settings>
<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/>
<layers>
<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>
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<layer number="17" name="Pads" color="2" fill="1" visible="yes" active="yes"/>
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<layer number="91" name="Nets" color="2" fill="1" visible="yes" active="yes"/>
<layer number="92" name="Busses" color="1" fill="1" visible="yes" active="yes"/>
<layer number="93" name="Pins" color="2" fill="1" visible="yes" active="yes"/>
<layer number="94" name="Symbols" color="4" fill="1" visible="yes" active="yes"/>
<layer number="95" name="Names" color="7" fill="1" visible="yes" active="yes"/>
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<layer number="99" name="SpiceOrder" color="5" fill="1" visible="yes" active="yes"/>
</layers>
<library>
<description><b>CMOS Logic IC EAGLE Library</b>
<p>This library includes package footprints for selected types of CMOS logic IC.</p>
<hr />
<br />
<b>Author: </b>
<a href="https://github.com/MacroYau">Macro Yau</a>
<br />
<br />
<b>License: </b>
<a href="https://creativecommons.org/licenses/by-sa/4.0/">Creative Commons Attribution-ShareAlike 4.0 International</a></description>
<packages>
<package name="DCK_R-PDSO-G5">
<description><b>DCK (R-PDSO-G5)</b> SC-70<p>
Source: http://focus.ti.com/lit/ds/slcs146e/slcs146e.pdf</description>
<wire x1="0.975" y1="-0.6" x2="-0.975" y2="-0.6" width="0.2032" layer="51"/>
<wire x1="-0.975" y1="-0.6" x2="-0.975" y2="0.6" width="0.2032" layer="21"/>
<wire x1="-0.975" y1="0.6" x2="0.975" y2="0.6" width="0.2032" layer="51"/>
<wire x1="0.975" y1="0.6" x2="0.975" y2="-0.6" width="0.2032" layer="21"/>
<smd name="4" x="0.65" y="0.95" dx="0.35" dy="0.8" layer="1"/>
<smd name="5" x="-0.65" y="0.95" dx="0.35" dy="0.8" layer="1"/>
<smd name="1" x="-0.65" y="-0.95" dx="0.35" dy="0.8" layer="1"/>
<smd name="2" x="0" y="-0.95" dx="0.35" dy="0.8" layer="1"/>
<smd name="3" x="0.65" y="-0.95" dx="0.35" dy="0.8" layer="1"/>
<text x="-1.27" y="1.397" size="1.016" layer="25">>NAME</text>
<text x="-1.27" y="-2.54" size="1.016" layer="27">>VALUE</text>
<rectangle x1="0.5" y1="0.675" x2="0.8" y2="1.2" layer="51"/>
<rectangle x1="-0.8" y1="0.675" x2="-0.5" y2="1.2" layer="51"/>
<rectangle x1="-0.8" y1="-1.2" x2="-0.5" y2="-0.675" layer="51"/>
<rectangle x1="-0.15" y1="-1.2" x2="0.15" y2="-0.675" layer="51"/>
<rectangle x1="0.5" y1="-1.2" x2="0.8" y2="-0.675" layer="51"/>
<rectangle x1="-1.016" y1="-0.508" x2="-0.127" y2="0" layer="21"/>
</package>
<package name="DBV_R-PDSO-G5" urn="urn:adsk.eagle:footprint:2402/1">
<description><b>DBV (R-PDSO-G5)</b> PLASTIC SMALL-OUTLINE PACKAGE<p>
SOT (SOT-23) - DBV<br>
Source: http://focus.ti.com/lit/ds/symlink/sn74lvc1g66.pdf</description>
<wire x1="0" y1="-1.29" x2="0" y2="-1.3" width="0.01" layer="21"/>
<wire x1="1.42" y1="0.8" x2="1.42" y2="-0.8" width="0.127" layer="21"/>
<wire x1="1.42" y1="-0.8" x2="-1.42" y2="-0.8" width="0.127" layer="51"/>
<wire x1="-1.42" y1="-0.8" x2="-1.42" y2="0.8" width="0.127" layer="21"/>
<wire x1="-1.42" y1="0.8" x2="1.42" y2="0.8" width="0.127" layer="51"/>
<smd name="1" x="-0.95" y="-1.29" dx="0.69" dy="0.99" layer="1" stop="no"/>
<smd name="2" x="0" y="-1.29" dx="0.69" dy="0.99" layer="1" stop="no"/>
<smd name="3" x="0.95" y="-1.29" dx="0.69" dy="0.99" layer="1" stop="no"/>
<smd name="4" x="0.95" y="1.3" dx="0.69" dy="0.99" layer="1" stop="no"/>
<smd name="5" x="-0.95" y="1.3" dx="0.69" dy="0.99" layer="1" stop="no"/>
<text x="-1.905" y="1.905" size="1.27" layer="25">>NAME</text>
<text x="-1.905" y="-3.175" size="1.27" layer="27">>VALUE</text>
<rectangle x1="-1.11" y1="0.8" x2="-0.78" y2="1.43" layer="51"/>
<rectangle x1="0.79" y1="0.8" x2="1.12" y2="1.42" layer="51"/>
<rectangle x1="-1.11" y1="-1.42" x2="-0.78" y2="-0.8" layer="51"/>
<rectangle x1="-0.16" y1="-1.42" x2="0.17" y2="-0.8" layer="51"/>
<rectangle x1="0.79" y1="-1.42" x2="1.12" y2="-0.8" layer="51"/>
<rectangle x1="-1.35" y1="0.75" x2="-0.55" y2="1.85" layer="29"/>
<rectangle x1="0.55" y1="0.75" x2="1.35" y2="1.85" layer="29"/>
<rectangle x1="0.55" y1="-1.85" x2="1.35" y2="-0.75" layer="29" rot="R180"/>
<rectangle x1="-0.4" y1="-1.85" x2="0.4" y2="-0.75" layer="29" rot="R180"/>
<rectangle x1="-1.35" y1="-1.85" x2="-0.55" y2="-0.75" layer="29" rot="R180"/>
<rectangle x1="-1.375" y1="-0.75" x2="-0.625" y2="0" layer="21"/>
</package>
</packages>
<symbols>
<symbol name="NOT">
<wire x1="-5.08" y1="-5.08" x2="5.08" y2="0" width="0.4064" layer="94"/>
<wire x1="5.08" y1="0" x2="-5.08" y2="5.08" width="0.4064" layer="94"/>
<wire x1="-5.08" y1="5.08" x2="-5.08" y2="-5.08" width="0.4064" layer="94"/>
<text x="2.54" y="3.175" size="1.778" layer="95">>NAME</text>
<text x="2.54" y="-5.08" size="1.778" layer="96">>VALUE</text>
<pin name="O" x="10.16" y="0" visible="pad" length="middle" direction="out" function="dot" rot="R180"/>
<pin name="I" x="-10.16" y="0" visible="pad" length="middle" direction="in"/>
</symbol>
<symbol name="PWR">
<text x="-1.27" y="-0.635" size="1.778" layer="95">>NAME</text>
<text x="1.905" y="2.54" size="1.27" layer="95" rot="R90">VDD</text>
<text x="1.905" y="-5.842" size="1.27" layer="95" rot="R90">VSS</text>
<pin name="VSS" x="0" y="-7.62" visible="pad" length="middle" direction="pwr" rot="R90"/>
<pin name="VDD" x="0" y="7.62" visible="pad" length="middle" direction="pwr" rot="R270"/>
</symbol>
<symbol name="NOT_PWR">
<wire x1="-5.08" y1="-5.08" x2="5.08" y2="0" width="0.4064" layer="94"/>
<wire x1="5.08" y1="0" x2="-5.08" y2="5.08" width="0.4064" layer="94"/>
<wire x1="-5.08" y1="5.08" x2="-5.08" y2="-5.08" width="0.4064" layer="94"/>
<text x="2.54" y="3.175" size="1.778" layer="95">>NAME</text>
<text x="2.54" y="-5.08" size="1.778" layer="96">>VALUE</text>
<pin name="O" x="10.16" y="0" visible="pad" length="middle" direction="out" function="dot" rot="R180"/>
<pin name="I" x="-10.16" y="0" visible="pad" length="middle" direction="in"/>
<pin name="VCC" x="0" y="10.16" visible="pad" direction="pwr" rot="R270"/>
<pin name="GND" x="0" y="-10.16" visible="pad" direction="pwr" rot="R90"/>
</symbol>
<symbol name="AND2">
<wire x1="-2.54" y1="5.08" x2="-2.54" y2="-5.08" width="0.4064" layer="94"/>
<wire x1="-2.54" y1="5.08" x2="-2.54" y2="-5.08" width="0.4064" layer="94" curve="-180"/>
<text x="2.54" y="3.175" size="1.778" layer="95">>NAME</text>
<text x="2.54" y="-5.08" size="1.778" layer="96">>VALUE</text>
<pin name="I0" x="-7.62" y="2.54" visible="pad" length="middle" direction="in" swaplevel="1"/>
<pin name="I1" x="-7.62" y="-2.54" visible="pad" length="middle" direction="in" swaplevel="1"/>
<pin name="O" x="7.62" y="0" visible="pad" length="middle" direction="out" rot="R180"/>
</symbol>
<symbol name="BUF">
<wire x1="-5.08" y1="-5.08" x2="5.08" y2="0" width="0.4064" layer="94"/>
<wire x1="5.08" y1="0" x2="-5.08" y2="5.08" width="0.4064" layer="94"/>
<wire x1="-5.08" y1="5.08" x2="-5.08" y2="-5.08" width="0.4064" layer="94"/>
<text x="2.54" y="3.175" size="1.778" layer="95">>NAME</text>
<text x="2.54" y="-5.08" size="1.778" layer="96">>VALUE</text>
<pin name="O" x="10.16" y="0" visible="pad" length="middle" direction="out" rot="R180"/>
<pin name="I" x="-10.16" y="0" visible="pad" length="middle" direction="in"/>
</symbol>
<symbol name="TRISTATE">
<wire x1="-10.16" y1="2.54" x2="0" y2="7.62" width="0.4064" layer="94"/>
<wire x1="0" y1="7.62" x2="-10.16" y2="12.7" width="0.4064" layer="94"/>
<wire x1="-10.16" y1="12.7" x2="-10.16" y2="2.54" width="0.4064" layer="94"/>
<text x="7.62" y="-4.445" size="1.778" layer="95">>NAME</text>
<text x="7.62" y="-12.7" size="1.778" layer="96">>VALUE</text>
<pin name="!OE" x="-15.24" y="7.62" visible="pad" length="middle" direction="in"/>
<wire x1="0" y1="-12.7" x2="10.16" y2="-7.62" width="0.4064" layer="94"/>
<wire x1="10.16" y1="-7.62" x2="5.08" y2="-5.08" width="0.4064" layer="94"/>
<wire x1="5.08" y1="-5.08" x2="0" y2="-2.54" width="0.4064" layer="94"/>
<wire x1="0" y1="-2.54" x2="0" y2="-7.62" width="0.4064" layer="94"/>
<pin name="O" x="15.24" y="-7.62" visible="pad" length="middle" direction="out" rot="R180"/>
<pin name="I" x="-15.24" y="-7.62" visible="pad" length="middle" direction="in"/>
<wire x1="0" y1="-7.62" x2="0" y2="-12.7" width="0.4064" layer="94"/>
<wire x1="-10.16" y1="-7.62" x2="0" y2="-7.62" width="0.1524" layer="94"/>
<circle x="1.27" y="7.62" radius="1.27" width="0.4064" layer="94"/>
<wire x1="2.54" y1="7.62" x2="5.08" y2="7.62" width="0.1524" layer="94"/>
<wire x1="5.08" y1="7.62" x2="5.08" y2="-5.08" width="0.1524" layer="94"/>
</symbol>
</symbols>
<devicesets>
<deviceset name="SN74AUP1G04" prefix="U">
<description><b>Low-Power Single Inverter Gate</b>
<p>The SN74AUP1G04 device is a single inverter gate performs the Boolean function Y = !A.</p>
<p>Source: http://www.ti.com/product/SN74AUP1G04</p></description>
<gates>
<gate name="G$1" symbol="NOT_PWR" x="0" y="0"/>
</gates>
<devices>
<device name="DBV" package="DBV_R-PDSO-G5">
<connects>
<connect gate="G$1" pin="GND" pad="3"/>
<connect gate="G$1" pin="I" pad="2"/>
<connect gate="G$1" pin="O" pad="4"/>
<connect gate="G$1" pin="VCC" pad="5"/>
</connects>
<technologies>
<technology name=""/>
</technologies>
</device>
<device name="DCK" package="DCK_R-PDSO-G5">
<connects>
<connect gate="G$1" pin="GND" pad="3"/>
<connect gate="G$1" pin="I" pad="2"/>
<connect gate="G$1" pin="O" pad="4"/>
<connect gate="G$1" pin="VCC" pad="5"/>
</connects>
<technologies>
<technology name=""/>
</technologies>
</device>
</devices>
</deviceset>
<deviceset name="SN74AUP1G125" prefix="U">
<description><b>Low-Power Single Bus Buffer Gate with 3-State Output</b>
<p>The SN74AUP1G125 bus buffer gate is a single line driver with a 3-state output. The output is disabled when the output-enable (!OE) input is high. This device has the input-disable feature, which allows floating input signals.</p>
<p>Source: http://www.ti.com/product/sn74aup1g125</p></description>
<gates>
<gate name="G$1" symbol="TRISTATE" x="0" y="0"/>
<gate name="G$2" symbol="PWR" x="-30.48" y="0"/>
</gates>
<devices>
<device name="DBV" package="DBV_R-PDSO-G5">
<connects>
<connect gate="G$1" pin="!OE" pad="1"/>
<connect gate="G$1" pin="I" pad="2"/>
<connect gate="G$1" pin="O" pad="4"/>
<connect gate="G$2" pin="VDD" pad="5"/>
<connect gate="G$2" pin="VSS" pad="3"/>
</connects>
<technologies>
<technology name=""/>
</technologies>
</device>
</devices>
</deviceset>
</devicesets>
</library>
</drawing>
<compatibility>
<note version="8.3" severity="warning">
Since Version 8.3, EAGLE supports URNs for individual library
assets (packages, symbols, and devices). The URNs of those assets
will not be understood (or retained) with this version.
</note>
</compatibility>
</eagle>