diff --git a/platform/mellanox/hw-management.mk b/platform/mellanox/hw-management.mk index 8c57fb63992a..b46d67307fec 100644 --- a/platform/mellanox/hw-management.mk +++ b/platform/mellanox/hw-management.mk @@ -16,7 +16,7 @@ # # Mellanox HW Management -MLNX_HW_MANAGEMENT_VERSION = 7.0030.1011 +MLNX_HW_MANAGEMENT_VERSION = 7.0030.2008 export MLNX_HW_MANAGEMENT_VERSION diff --git a/platform/mellanox/hw-management/hw-mgmt b/platform/mellanox/hw-management/hw-mgmt index c7d4c31a212e..f0cbd0e61f77 160000 --- a/platform/mellanox/hw-management/hw-mgmt +++ b/platform/mellanox/hw-management/hw-mgmt @@ -1 +1 @@ -Subproject commit c7d4c31a212eec6a5543f554ffb2c63c5cb621e3 +Subproject commit f0cbd0e61f77ca0d8ca37612abc5fe8339e0f884 diff --git a/platform/mellanox/hw-management/hwmgmt_nonup_patches b/platform/mellanox/hw-management/hwmgmt_nonup_patches index 36d1d3bd8bdd..f3cd270a0d95 100644 --- a/platform/mellanox/hw-management/hwmgmt_nonup_patches +++ b/platform/mellanox/hw-management/hwmgmt_nonup_patches @@ -66,26 +66,8 @@ 0167-DS-lan743x-Add-support-for-fixed-phy.patch 0168-TMP-mlxsw-minimal-Ignore-error-reading-SPAD-register.patch 0171-platform-mellanox-mlxreg-lc-Fix-cleanup-on-failure-a.patch -0172-DS-platform-mlx-platform-Add-SPI-path-for-rack-switc.patch 0174-DS-mlxsw-core_linecards-Skip-devlink-and-provisionin.patch 0181-Revert-Fix-out-of-bounds-memory-accesses-in-thermal.patch -0182-platform-mellanox-Introduce-support-of-new-Nvidia-L1.patch -0183-platform-mellanox-Split-initialization-procedure.patch -0184-platform-mellanox-Split-logic-in-init-and-exit-flow.patch -0185-platform-mellanox-Extend-all-systems-with-I2C-notifi.patch -0187-platform_data-mlxreg-Add-field-with-mapped-resource-.patch -0188-i2c-mux-Add-register-map-based-mux-driver.patch -0189-i2c-mlxcpld-Allow-driver-to-run-on-ARM64-architectur.patch -0190-i2c-mlxcpld-Modify-base-address-type.patch -0191-i2c-mlxcpld-Allow-to-configure-base-address-of-regis.patch -0192-i2c-mlxcpld-Add-support-for-extended-transaction-len.patch -0193-platform-mellanox-mlx-platform-Add-mux-selection-reg.patch -0194-platform-mellanox-mlx-platform-Move-bus-shift-assign.patch -0195-platform-mellanox-Add-support-for-dynamic-I2C-channe.patch -0196-platform-mellanox-Relocate-mlx-platform-driver.patch -0197-platform-mellanox-Add-initial-support-for-PCIe-based.patch -0198-platform-mellanox-Introduce-support-for-switches-bas.patch -0199-platform-mellanox-mlx-platform-Add-reset-and-extend-.patch 0200-dt-bindings-i2c-mellanox-i2c-mlxbf-convert-txt-to-YA.patch 0203-i2c-mlxbf-remove-IRQF_ONESHOT.patch 0206-i2c-mlxbf-add-multi-slave-functionality.patch @@ -116,15 +98,11 @@ 0231-mlxbf_gige-remove-own-module-name-define-and-use-KBU.patch 0232-UBUNTU-SAUCE-mlxbf_gige-add-ethtool-mlxbf_gige_set_r.patch 0233-UBUNTU-SAUCE-Fix-OOB-handling-RX-packets-in-heavy-tr.patch -0234-UBUNTU-SAUCE-mlxbf_gige-add-validation-of-ACPI-table.patch -0235-UBUNTU-SAUCE-mlxbf_gige-set-driver-version-to-1.27.patch 0236-UBUNTU-SAUCE-mlxbf_gige-clear-MDIO-gateway-lock-afte.patch 0237-mlxbf_gige-compute-MDIO-period-based-on-i1clk.patch 0238-net-mlxbf_gige-Fix-an-IS_ERR-vs-NULL-bug-in-mlxbf_gi.patch 0239-UBUNTU-SAUCE-mlxbf_gige-add-MDIO-support-for-BlueFie.patch 0240-UBUNTU-SAUCE-mlxbf_gige-support-10M-100M-1G-speeds-o.patch -0241-UBUNTU-SAUCE-mlxbf_gige-add-BlueField-3-Serdes-confi.patch -0242-UBUNTU-SAUCE-mlxbf_gige-add-BlueField-3-ethtool_ops.patch 0243-UBUNTU-SAUCE-bluefield_edac-Add-SMC-support.patch 0244-UBUNTU-SAUCE-bluefield_edac-Update-license-and-copyr.patch 0245-gpio-mlxbf2-Convert-to-device-PM-ops.patch @@ -150,20 +128,40 @@ 0266-UBUNTU-SAUCE-mlxbf-pmc-Bug-fix-for-BlueField-3-count.patch 0267-UBUNTU-SAUCE-mmc-sdhci-of-dwcmshc-add-the-missing-de.patch 0268-DS-mlxsw-core_linecards-Disable-firmware-bundling-ma.patch -0269-platform-mellanox-Cosmetic-changes.patch -0270-platform-mellanox-Fix-order-in-exit-flow.patch -0271-platform-mellanox-Add-new-attributes.patch -0272-platform-mellanox-Change-register-offset-addresses.patch -0273-platform-mellanox-Add-field-upgrade-capability-regis.patch -0274-platform-mellanox-Modify-reset-causes-description.patch 0275-mlxsw-Use-u16-for-local_port-field-instead-of-u8.patch 0276-mlxsw-minimal-Change-type-for-local-port.patch 0277-mlxsw-i2c-Fix-chunk-size-setting-in-output-mailbox-b.patch -0278-platform-mellanox-mlx-platform-Modify-graceful-shutd.patch -0279-platform-mellanox-mlx-platform-Fix-signals-polarity-.patch -0280-platform-mellanox-mlxreg-hotplug-Extend-condition-fo.patch -0281-platform-mellanox-mlx-platform-Modify-health-and-pow.patch -0282-platform-mellanox-mlx-platform-add-support-of-5th-CP.patch -0283-mlxsw-core_hwmon-Align-modules-label-name-assignment.patch -0284-platform-mellanox-mlx-platform-fix-CPLD4-PN-report.patch +0285-UBUNTU-SAUCE-mlxbf-gige-Fix-intermittent-no-ip-issue.patch +0286-pinctrl-Introduce-struct-pinfunction-and-PINCTRL_PIN.patch +0287-pinctrl-mlxbf3-Add-pinctrl-driver-support.patch +0288-UBUNTU-SAUCE-gpio-mmio-handle-ngpios-properly-in-bgp.patch +0289-UBUNTU-SAUCE-gpio-mlxbf3-Add-gpio-driver-support.patch +0291-mlxsw-core_hwmon-Align-modules-label-name-assignment.patch +0292-mlxsw-i2c-Limit-single-transaction-buffer-size.patch +0293-mlxsw-reg-Limit-MTBR-register-records-buffer-by-one-.patch +0296-UBUNTU-SAUCE-mmc-sdhci-of-dwcmshc-Add-runtime-PM-ope.patch +0298-UBUNTU-SAUCE-mlxbf-ptm-use-0444-instead-of-S_IRUGO.patch +0299-UBUNTU-SAUCE-mlxbf-ptm-add-atx-debugfs-nodes.patch +0300-UBUNTU-SAUCE-mlxbf-ptm-update-module-version.patch +0301-UBUNTU-SAUCE-mlxbf-gige-Fix-kernel-panic-at-shutdown.patch +0302-UBUNTU-SAUCE-mlxbf-bootctl-support-SMC-call-for-sett.patch +0303-UBUNTU-SAUCE-Add-BF3-related-ACPI-config-and-Ring-de.patch +0306-dt-bindings-trivial-devices-Add-infineon-xdpe1a2g7.patch +0307-leds-mlxreg-Add-support-for-new-flavour-of-capabilit.patch +0308-leds-mlxreg-Remove-code-for-amber-LED-colour.patch +0308-platform_data-mlxreg-Add-capability-bit-and-mask-fie.patch +0309-hwmon-mlxreg-fan-Add-support-for-new-flavour-of-capa.patch +0310-hwmon-mlxreg-fan-Extend-number-of-supporetd-fans.patch +0317-platform-mellanox-Introduce-support-for-switches-equ.patch +0318-mellanox-Relocate-mlx-platform-driver.patch +0319-UBUNTU-SAUCE-mlxbf-tmfifo-fix-potential-race.patch +0320-UBUNTU-SAUCE-mlxbf-tmfifo-Drop-the-Rx-packet-if-no-m.patch +0321-UBUNTU-SAUCE-mlxbf-tmfifo-Drop-jumbo-frames.patch +0322-UBUNTU-SAUCE-mlxbf-tmfifo.c-Amend-previous-tmfifo-pa.patch +0323-mlxbf_gige-add-set_link_ksettings-ethtool-callback.patch +0324-mlxbf_gige-fix-white-space-in-mlxbf_gige_eth_ioctl.patch +0325-UBUNTU-SAUCE-mlxbf-bootctl-Fix-kernel-panic-due-to-b.patch +0326-platform-mellanox-mlxreg-hotplug-Add-support-for-new.patch +0327-platform-mellanox-mlx-platform-Change-register-name.patch +0328-platform-mellanox-mlx-platform-Add-support-for-new-X.patch 9002-TMP-fix-for-fan-minimum-speed.patch diff --git a/platform/mellanox/integration-scripts.mk b/platform/mellanox/integration-scripts.mk index e902a1f06e80..10282555b010 100644 --- a/platform/mellanox/integration-scripts.mk +++ b/platform/mellanox/integration-scripts.mk @@ -98,15 +98,16 @@ endif --kernel_version $(KERNEL_VERSION) \ --hw_mgmt_ver ${MLNX_HW_MANAGEMENT_VERSION} $(LOG_SIMPLE) - $(BUILD_WORKDIR)/$($(MLNX_HW_MANAGEMENT)_SRC_PATH)/hw-mgmt/recipes-kernel/linux/deploy_kernel_patches.py \ - --dst_accepted_folder $(PTCH_DIR) \ - --dst_candidate_folder $(NON_UP_PTCH_DIR) \ - --series_file $(PTCH_LIST) \ - --config_file $(KCFG_LIST_ARM) \ - --config_file_downstream $(KCFG_DOWN_LIST_ARM) \ - --kernel_version $(KERNEL_VERSION) \ - --arch arm64 \ - --os_type sonic $(LOG_SIMPLE) + # Disable Writing KConfigs for arm64 platform + # $(BUILD_WORKDIR)/$($(MLNX_HW_MANAGEMENT)_SRC_PATH)/hw-mgmt/recipes-kernel/linux/deploy_kernel_patches.py \ + # --dst_accepted_folder $(PTCH_DIR) \ + # --dst_candidate_folder $(NON_UP_PTCH_DIR) \ + # --series_file $(PTCH_LIST) \ + # --config_file $(KCFG_LIST_ARM) \ + # --config_file_downstream $(KCFG_DOWN_LIST_ARM) \ + # --kernel_version $(KERNEL_VERSION) \ + # --arch arm64 \ + # --os_type sonic $(LOG_SIMPLE) $(BUILD_WORKDIR)/$($(MLNX_HW_MANAGEMENT)_SRC_PATH)/hw-mgmt/recipes-kernel/linux/deploy_kernel_patches.py \ --dst_accepted_folder $(PTCH_DIR) \ diff --git a/platform/mellanox/mlnx-platform-api/sonic_platform/fan.py b/platform/mellanox/mlnx-platform-api/sonic_platform/fan.py index 9567c65ce6c8..40dadb0f4000 100644 --- a/platform/mellanox/mlnx-platform-api/sonic_platform/fan.py +++ b/platform/mellanox/mlnx-platform-api/sonic_platform/fan.py @@ -216,7 +216,10 @@ def get_target_speed(self): """ try: # Get PSU fan target speed according to current system cooling level - cooling_level = utils.read_int_from_file('/run/hw-management/thermal/cooling_cur_state', log_func=None) + pwm = utils.read_int_from_file('/run/hw-management/thermal/pwm1', log_func=None) + if pwm >= PWM_MAX: + pwm = PWM_MAX - 1 + cooling_level = int(pwm / PWM_MAX * 10) return int(self.PSU_FAN_SPEED[cooling_level], 16) except Exception: return self.get_speed() diff --git a/platform/mellanox/mlnx-platform-api/sonic_platform/psu.py b/platform/mellanox/mlnx-platform-api/sonic_platform/psu.py index cc5bb61b9608..6b42fad6d9ae 100644 --- a/platform/mellanox/mlnx-platform-api/sonic_platform/psu.py +++ b/platform/mellanox/mlnx-platform-api/sonic_platform/psu.py @@ -242,8 +242,8 @@ def __init__(self, psu_index): self.psu_power_max_capacity = os.path.join(PSU_PATH, "config/psu{}_power_capacity".format(self.index)) - self.psu_temp = os.path.join(PSU_PATH, 'thermal/psu{}_temp'.format(self.index)) - self.psu_temp_threshold = os.path.join(PSU_PATH, 'thermal/psu{}_temp_max'.format(self.index)) + self.psu_temp = os.path.join(PSU_PATH, 'thermal/psu{}_temp1'.format(self.index)) + self.psu_temp_threshold = os.path.join(PSU_PATH, 'thermal/psu{}_temp1_max'.format(self.index)) self.psu_power_slope = os.path.join(PSU_PATH, self.PSU_POWER_SLOPE.format(self.index)) diff --git a/platform/mellanox/mlnx-platform-api/sonic_platform/thermal.py b/platform/mellanox/mlnx-platform-api/sonic_platform/thermal.py index 4786b1f74049..1a6b45da63ac 100644 --- a/platform/mellanox/mlnx-platform-api/sonic_platform/thermal.py +++ b/platform/mellanox/mlnx-platform-api/sonic_platform/thermal.py @@ -65,16 +65,16 @@ "psu thermals": { "name": "PSU-{} Temp", - "temperature": "psu{}_temp", - "high_threshold": "psu{}_temp_max", + "temperature": "psu{}_temp1", + "high_threshold": "psu{}_temp1_max", "type": "indexable" }, "chassis thermals": [ { "name": "ASIC", "temperature": "asic", - "high_threshold": "mlxsw/temp_trip_hot", - "high_critical_threshold": "mlxsw/temp_trip_crit" + "high_threshold": "asic_temp_emergency", + "high_critical_threshold": "asic_temp_trip_crit" }, { "name": "Ambient Port Side Temp", @@ -105,8 +105,8 @@ { "name": "Gearbox {} Temp", "temperature": "gearbox{}_temp_input", - "high_threshold": "mlxsw-gearbox{}/temp_trip_hot", - "high_critical_threshold": "mlxsw-gearbox{}/temp_trip_crit", + "high_threshold": "gearbox{}_temp_emergency", + "high_critical_threshold": "gearbox{}_temp_trip_crit", "type": "indexable" }, { @@ -135,8 +135,8 @@ 'linecard thermals': { "name": "Gearbox {} Temp", "temperature": "gearbox{}_temp_input", - "high_threshold": "mlxsw-gearbox{}/temp_trip_hot", - "high_critical_threshold": "mlxsw-gearbox{}/temp_trip_crit", + "high_threshold": "gearbox{}_temp_emergency", + "high_critical_threshold": "gearbox{}_temp_trip_crit", "type": "indexable" } } @@ -268,16 +268,6 @@ def _check_thermal_sysfs_existence(file_path): class Thermal(ThermalBase): - thermal_algorithm_status = False - # Expect cooling level, used for caching the cooling level value before commiting to hardware - expect_cooling_level = None - # Expect cooling state - expect_cooling_state = None - # Last committed cooling level - last_set_cooling_level = None - last_set_cooling_state = None - last_set_psu_cooling_level = None - def __init__(self, name, temp_file, high_th_file, high_crit_th_file, position): """ index should be a string for category ambient and int for other categories diff --git a/platform/mellanox/mlnx-platform-api/tests/conftest.py b/platform/mellanox/mlnx-platform-api/tests/conftest.py index b69fdd6c75f0..56888c6512cf 100644 --- a/platform/mellanox/mlnx-platform-api/tests/conftest.py +++ b/platform/mellanox/mlnx-platform-api/tests/conftest.py @@ -1,5 +1,5 @@ # -# Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. +# Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. # Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -42,14 +42,3 @@ def auto_recover_mock(): utils.read_str_from_file = origin_read_str_from_file utils.write_file = origin_write_file utils.read_float_from_file = origin_read_float_from_file - - -@pytest.fixture(scope='function', autouse=True) -def auto_reset_cooling_level(): - from sonic_platform.thermal import Thermal - yield - Thermal.expect_cooling_level = None - Thermal.expect_cooling_state = None - Thermal.last_set_cooling_level = None - Thermal.last_set_cooling_state = None - Thermal.last_set_psu_cooling_level = None diff --git a/platform/mellanox/mlnx-platform-api/tests/test_fan_api.py b/platform/mellanox/mlnx-platform-api/tests/test_fan_api.py index 151b197e0836..bb643f211e0a 100644 --- a/platform/mellanox/mlnx-platform-api/tests/test_fan_api.py +++ b/platform/mellanox/mlnx-platform-api/tests/test_fan_api.py @@ -124,8 +124,8 @@ def test_psu_fan_basic(self, mock_path_exists, mock_powergood, mock_presence, mo assert fan.get_presence() is False mock_path_exists.return_value = True assert fan.get_presence() is True - mock_read_int.return_value = 7 - assert fan.get_target_speed() == 70 + mock_read_int.return_value = int(255 / 10 * 7) + assert fan.get_target_speed() == 60 mock_read_int.return_value = FAN_DIR_VALUE_INTAKE assert fan.get_direction() == Fan.FAN_DIRECTION_INTAKE mock_read_int.return_value = FAN_DIR_VALUE_EXHAUST diff --git a/platform/mellanox/non-upstream-patches/external-changes.patch b/platform/mellanox/non-upstream-patches/external-changes.patch index 786c33ea9bbb..245d500ea276 100644 --- a/platform/mellanox/non-upstream-patches/external-changes.patch +++ b/platform/mellanox/non-upstream-patches/external-changes.patch @@ -79,7 +79,7 @@ 0157-platform-x86-mlx-platform-Make-activation-of-some-dr.patch 0158-platform-x86-mlx-platform-Add-cosmetic-changes-for-a.patch 0159-mlx-platform-Add-support-for-systems-equipped-with-t.patch -@@ -166,21 +230,125 @@ +@@ -166,14 +230,19 @@ 0164-hwmon-jc42-Add-support-for-Seiko-Instruments-S-34TS0.patch 0165-platform-mellanox-mlxreg-io-Add-locking-for-io-opera.patch 0166-DS-leds-leds-mlxreg-Send-udev-event-from-leds-mlxreg.patch @@ -87,7 +87,7 @@ +0168-TMP-mlxsw-minimal-Ignore-error-reading-SPAD-register.patch 0170-i2c-mlxcpld-Fix-register-setting-for-400KHz-frequenc.patch +0171-platform-mellanox-mlxreg-lc-Fix-cleanup-on-failure-a.patch -+0172-DS-platform-mlx-platform-Add-SPI-path-for-rack-switc.patch + 0172-DS-platform-mlx-platform-Add-SPI-path-for-rack-switc.patch 0173-mlxsw-core-Add-support-for-OSFP-transceiver-modules.patch +0174-DS-mlxsw-core_linecards-Skip-devlink-and-provisionin.patch 0175-hwmon-pmbus-Add-support-for-Infineon-Digital-Multi-p.patch @@ -96,31 +96,15 @@ 0178-platform-mellanox-Introduce-support-for-next-generat.patch 0180-hwmon-pmbus-Fix-sensors-readouts-for-MPS-Multi-phase.patch +0181-Revert-Fix-out-of-bounds-memory-accesses-in-thermal.patch -+0182-platform-mellanox-Introduce-support-of-new-Nvidia-L1.patch -+0183-platform-mellanox-Split-initialization-procedure.patch -+0184-platform-mellanox-Split-logic-in-init-and-exit-flow.patch -+0185-platform-mellanox-Extend-all-systems-with-I2C-notifi.patch - 0186-platform-mellanox-mlxreg-hotplug-Allow-more-flexible.patch -+0187-platform_data-mlxreg-Add-field-with-mapped-resource-.patch -+0188-i2c-mux-Add-register-map-based-mux-driver.patch -+0189-i2c-mlxcpld-Allow-driver-to-run-on-ARM64-architectur.patch -+0190-i2c-mlxcpld-Modify-base-address-type.patch -+0191-i2c-mlxcpld-Allow-to-configure-base-address-of-regis.patch -+0192-i2c-mlxcpld-Add-support-for-extended-transaction-len.patch -+0193-platform-mellanox-mlx-platform-Add-mux-selection-reg.patch -+0194-platform-mellanox-mlx-platform-Move-bus-shift-assign.patch -+0195-platform-mellanox-Add-support-for-dynamic-I2C-channe.patch - 0195-platform-x86-MLX_PLATFORM-select-REGMAP-instead-of-d.patch -+0196-platform-mellanox-Relocate-mlx-platform-driver.patch -+0197-platform-mellanox-Add-initial-support-for-PCIe-based.patch -+0198-platform-mellanox-Introduce-support-for-switches-bas.patch -+0199-platform-mellanox-mlx-platform-Add-reset-and-extend-.patch + 0182-platform-mellanox-Introduce-support-of-new-Nvidia-L1.patch + 0183-platform-mellanox-Split-initialization-procedure.patch + 0184-platform-mellanox-Split-logic-in-init-and-exit-flow.patch +@@ -191,24 +260,121 @@ + 0197-platform-mellanox-Fix-order-in-exit-flow.patch + 0198-platform-mellanox-Add-new-attributes.patch + 0199-platform-mellanox-Change-register-offset-addresses.patch +0200-dt-bindings-i2c-mellanox-i2c-mlxbf-convert-txt-to-YA.patch - 0201-i2c-mlxbf-incorrect-base-address-passed-during-io-wr.patch - 0202-i2c-mlxbf-prevent-stack-overflow-in-mlxbf_i2c_smbus_.patch +0203-i2c-mlxbf-remove-IRQF_ONESHOT.patch - 0204-i2c-mlxbf-Fix-frequency-calculation.patch - 0205-i2c-mlxbf-support-lock-mechanism.patch +0206-i2c-mlxbf-add-multi-slave-functionality.patch +0207-i2c-mlxbf-support-BlueField-3-SoC.patch +0208-i2c-mlxbf-remove-device-tree-support.patch @@ -149,15 +133,11 @@ +0231-mlxbf_gige-remove-own-module-name-define-and-use-KBU.patch +0232-UBUNTU-SAUCE-mlxbf_gige-add-ethtool-mlxbf_gige_set_r.patch +0233-UBUNTU-SAUCE-Fix-OOB-handling-RX-packets-in-heavy-tr.patch -+0234-UBUNTU-SAUCE-mlxbf_gige-add-validation-of-ACPI-table.patch -+0235-UBUNTU-SAUCE-mlxbf_gige-set-driver-version-to-1.27.patch +0236-UBUNTU-SAUCE-mlxbf_gige-clear-MDIO-gateway-lock-afte.patch +0237-mlxbf_gige-compute-MDIO-period-based-on-i1clk.patch +0238-net-mlxbf_gige-Fix-an-IS_ERR-vs-NULL-bug-in-mlxbf_gi.patch +0239-UBUNTU-SAUCE-mlxbf_gige-add-MDIO-support-for-BlueFie.patch +0240-UBUNTU-SAUCE-mlxbf_gige-support-10M-100M-1G-speeds-o.patch -+0241-UBUNTU-SAUCE-mlxbf_gige-add-BlueField-3-Serdes-confi.patch -+0242-UBUNTU-SAUCE-mlxbf_gige-add-BlueField-3-ethtool_ops.patch +0243-UBUNTU-SAUCE-bluefield_edac-Add-SMC-support.patch +0244-UBUNTU-SAUCE-bluefield_edac-Update-license-and-copyr.patch +0245-gpio-mlxbf2-Convert-to-device-PM-ops.patch @@ -180,28 +160,65 @@ +0262-UBUNTU-SAUCE-mlxbf-pmc-Fix-event-string-typo.patch +0263-UBUNTU-SAUCE-mlxbf-pmc-Support-for-BlueField-3-perfo.patch +0264-UBUNTU-SAUCE-platform-mellanox-Add-ctrl-message-and-.patch - 0265-hwmon-mlxreg-fan-Return-zero-speed-for-broken-fan.patch +0266-UBUNTU-SAUCE-mlxbf-pmc-Bug-fix-for-BlueField-3-count.patch +0267-UBUNTU-SAUCE-mmc-sdhci-of-dwcmshc-add-the-missing-de.patch +0268-DS-mlxsw-core_linecards-Disable-firmware-bundling-ma.patch -+0269-platform-mellanox-Cosmetic-changes.patch -+0270-platform-mellanox-Fix-order-in-exit-flow.patch -+0271-platform-mellanox-Add-new-attributes.patch -+0272-platform-mellanox-Change-register-offset-addresses.patch -+0273-platform-mellanox-Add-field-upgrade-capability-regis.patch -+0274-platform-mellanox-Modify-reset-causes-description.patch + 0269-platform-mellanox-Add-field-upgrade-capability-regis.patch + 0270-platform-mellanox-Modify-reset-causes-description.patch +0275-mlxsw-Use-u16-for-local_port-field-instead-of-u8.patch +0276-mlxsw-minimal-Change-type-for-local-port.patch +0277-mlxsw-i2c-Fix-chunk-size-setting-in-output-mailbox-b.patch -+0278-platform-mellanox-mlx-platform-Modify-graceful-shutd.patch -+0279-platform-mellanox-mlx-platform-Fix-signals-polarity-.patch -+0280-platform-mellanox-mlxreg-hotplug-Extend-condition-fo.patch -+0281-platform-mellanox-mlx-platform-Modify-health-and-pow.patch -+0282-platform-mellanox-mlx-platform-add-support-of-5th-CP.patch -+0283-mlxsw-core_hwmon-Align-modules-label-name-assignment.patch -+0284-platform-mellanox-mlx-platform-fix-CPLD4-PN-report.patch - 0285-platform-mellanox-nvsw-sn2201-change-fans-i2c-busses.patch + 0278-platform-mellanox-mlx-platform-Modify-graceful-shutd.patch + 0279-platform-mellanox-mlx-platform-Fix-signals-polarity-.patch + 0280-platform-mellanox-mlxreg-hotplug-Extend-condition-fo.patch + 0281-platform-mellanox-mlx-platform-Modify-health-and-pow.patch + 0282-platform-mellanox-mlx-platform-Add-reset-cause-attri.patch + 0284-platform-mellanox-mlx-platform-add-support-for-addit.patch ++0285-UBUNTU-SAUCE-mlxbf-gige-Fix-intermittent-no-ip-issue.patch ++0286-pinctrl-Introduce-struct-pinfunction-and-PINCTRL_PIN.patch ++0287-pinctrl-mlxbf3-Add-pinctrl-driver-support.patch ++0288-UBUNTU-SAUCE-gpio-mmio-handle-ngpios-properly-in-bgp.patch ++0289-UBUNTU-SAUCE-gpio-mlxbf3-Add-gpio-driver-support.patch ++0291-mlxsw-core_hwmon-Align-modules-label-name-assignment.patch ++0292-mlxsw-i2c-Limit-single-transaction-buffer-size.patch ++0293-mlxsw-reg-Limit-MTBR-register-records-buffer-by-one-.patch + 0294-hwmon-pmbus-Add-support-for-MPS-Multi-phase-mp2891-c.patch + 0295-dt-bindings-trivial-devices-Add-mps-mp2891.patch ++0296-UBUNTU-SAUCE-mmc-sdhci-of-dwcmshc-Add-runtime-PM-ope.patch ++0298-UBUNTU-SAUCE-mlxbf-ptm-use-0444-instead-of-S_IRUGO.patch ++0299-UBUNTU-SAUCE-mlxbf-ptm-add-atx-debugfs-nodes.patch ++0300-UBUNTU-SAUCE-mlxbf-ptm-update-module-version.patch ++0301-UBUNTU-SAUCE-mlxbf-gige-Fix-kernel-panic-at-shutdown.patch ++0302-UBUNTU-SAUCE-mlxbf-bootctl-support-SMC-call-for-sett.patch ++0303-UBUNTU-SAUCE-Add-BF3-related-ACPI-config-and-Ring-de.patch + 0304-platform-mellanox-mlx-platform-Modify-power-off-call.patch + 0305-Extend-driver-to-support-Infineon-Digital-Multi-phas.patch ++0306-dt-bindings-trivial-devices-Add-infineon-xdpe1a2g7.patch ++0307-leds-mlxreg-Add-support-for-new-flavour-of-capabilit.patch ++0308-leds-mlxreg-Remove-code-for-amber-LED-colour.patch ++0308-platform_data-mlxreg-Add-capability-bit-and-mask-fie.patch ++0309-hwmon-mlxreg-fan-Add-support-for-new-flavour-of-capa.patch ++0310-hwmon-mlxreg-fan-Extend-number-of-supporetd-fans.patch + 0311-platform-mellanox-nvsw-sn2201-change-fans-i2c-busses.patch + 0312-platform-mellanox-mlx-platform-Add-reset-callback.patch + 0313-platform-mellanox-mlx-platform-Prepare-driver-to-all.patch + 0314-platform-mellanox-mlx-platform-Introduce-ACPI-init-f.patch + 0315-platform-mellanox-mlx-platform-Get-interrupt-line-th.patch + 0316-platform-mellanox-Add-initial-support-for-PCIe-based.patch ++0317-platform-mellanox-Introduce-support-for-switches-equ.patch ++0318-mellanox-Relocate-mlx-platform-driver.patch ++0319-UBUNTU-SAUCE-mlxbf-tmfifo-fix-potential-race.patch ++0320-UBUNTU-SAUCE-mlxbf-tmfifo-Drop-the-Rx-packet-if-no-m.patch ++0321-UBUNTU-SAUCE-mlxbf-tmfifo-Drop-jumbo-frames.patch ++0322-UBUNTU-SAUCE-mlxbf-tmfifo.c-Amend-previous-tmfifo-pa.patch ++0323-mlxbf_gige-add-set_link_ksettings-ethtool-callback.patch ++0324-mlxbf_gige-fix-white-space-in-mlxbf_gige_eth_ioctl.patch ++0325-UBUNTU-SAUCE-mlxbf-bootctl-Fix-kernel-panic-due-to-b.patch ++0326-platform-mellanox-mlxreg-hotplug-Add-support-for-new.patch ++0327-platform-mellanox-mlx-platform-Change-register-name.patch ++0328-platform-mellanox-mlx-platform-Add-support-for-new-X.patch +9002-TMP-fix-for-fan-minimum-speed.patch ###-> mellanox_hw_mgmt-end # Cisco patches for 5.10 kernel + diff --git a/platform/mellanox/non-upstream-patches/patches/0172-DS-platform-mlx-platform-Add-SPI-path-for-rack-switc.patch b/platform/mellanox/non-upstream-patches/patches/0172-DS-platform-mlx-platform-Add-SPI-path-for-rack-switc.patch deleted file mode 100644 index b5ec0ea19a6f..000000000000 --- a/platform/mellanox/non-upstream-patches/patches/0172-DS-platform-mlx-platform-Add-SPI-path-for-rack-switc.patch +++ /dev/null @@ -1,84 +0,0 @@ -From b1e9734f4dc29c65e05a8f35ec67efb7784d321f Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Sun, 15 May 2022 14:31:10 +0300 -Subject: [PATCH backport 5.10 172/182] DS: platform: mlx-platform: Add SPI - path for rack switch for EROT access - -Create spidev for OOB access to External Root of Trusts devices. - -Signed-off-by: Vadim Pasternak ---- - drivers/platform/x86/mlx-platform.c | 16 ++++++++++++++++ - drivers/spi/spi.c | 1 + - 2 files changed, 17 insertions(+) - -diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c -index 3ad85934d6e3..135ccea3a34e 100644 ---- a/drivers/platform/x86/mlx-platform.c -+++ b/drivers/platform/x86/mlx-platform.c -@@ -16,6 +16,7 @@ - #include - #include - #include -+#include - - #define MLX_PLAT_DEVICE_NAME "mlxplat" - -@@ -2299,6 +2300,16 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_rack_switch_data = { - .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, - }; - -+static struct spi_board_info rack_switch_switch_spi_board_info[] = { -+ { -+ .modalias = "spidev", -+ .irq = -1, -+ .max_speed_hz = 20000000, -+ .bus_num = 0, -+ .chip_select = 0, -+ }, -+}; -+ - /* Platform led default data */ - static struct mlxreg_core_data mlxplat_mlxcpld_default_led_data[] = { - { -@@ -5254,6 +5265,7 @@ static struct mlxreg_core_platform_data *mlxplat_fan; - static struct mlxreg_core_platform_data - *mlxplat_wd_data[MLXPLAT_CPLD_WD_MAX_DEVS]; - static const struct regmap_config *mlxplat_regmap_config; -+static struct spi_board_info *mlxplat_spi; - - static int __init mlxplat_dmi_default_matched(const struct dmi_system_id *dmi) - { -@@ -5551,6 +5563,7 @@ static int __init mlxplat_dmi_rack_switch_matched(const struct dmi_system_id *dm - mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; - mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; - mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_rack_switch; -+ mlxplat_spi = rack_switch_switch_spi_board_info; - - return 1; - } -@@ -5917,6 +5930,9 @@ static int __init mlxplat_init(void) - } - } - -+ if (mlxplat_spi) -+ spi_register_board_info(mlxplat_spi, 1); -+ - /* Add WD drivers. */ - err = mlxplat_mlxcpld_check_wd_capability(priv->regmap); - if (err) -diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c -index 857a1399850c..2efafa34ff22 100644 ---- a/drivers/spi/spi.c -+++ b/drivers/spi/spi.c -@@ -790,6 +790,7 @@ int spi_register_board_info(struct spi_board_info const *info, unsigned n) - - return 0; - } -+EXPORT_SYMBOL(spi_register_board_info); - - /*-------------------------------------------------------------------------*/ - --- -2.20.1 - diff --git a/platform/mellanox/non-upstream-patches/patches/0182-platform-mellanox-Introduce-support-of-new-Nvidia-L1.patch b/platform/mellanox/non-upstream-patches/patches/0182-platform-mellanox-Introduce-support-of-new-Nvidia-L1.patch deleted file mode 100644 index 40e28f821fef..000000000000 --- a/platform/mellanox/non-upstream-patches/patches/0182-platform-mellanox-Introduce-support-of-new-Nvidia-L1.patch +++ /dev/null @@ -1,647 +0,0 @@ -From 74ab8a216510df924ca88d2f3d5944eb107264d0 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Sun, 11 Dec 2022 09:26:48 +0200 -Subject: [PATCH backport 5.10 1/5] platform: mellanox: Introduce support of - new Nvidia L1 switch - -Add support for new L1 switch nodes providing L1 connectivity for -multi-node networking chassis. - -The purpose is to provide compute server with full management and IO -subsystems with connections to L1 switches. - -System contains the following components: -- COMe module based on Intel Coffee Lake CPU -- Switch baseboard with two ASICs, while - 24 ports of each ASICs are connected to one backplane connector - 32 ports of each ASIC are connected to 8 OSFPs -- Integrated 60mm dual-rotor FANs inside L1 node (N+2 redundancy) -- Support 48V or 54V DC input from the external power server. - -Add the structures related to the new systems to allow proper activation -of the all required platform driver. - -Add poweroff callback to support deep power cycle flow, which should -include special actions against CPLD device for performing graceful -operation. - -Signed-off-by: Vadim Pasternak ---- - drivers/platform/x86/mlx-platform.c | 395 +++++++++++++++++++++++++++- - 1 file changed, 393 insertions(+), 2 deletions(-) - -diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c -index 4bbe1d8f0..a2addd1b3 100644 ---- a/drivers/platform/x86/mlx-platform.c -+++ b/drivers/platform/x86/mlx-platform.c -@@ -15,6 +15,7 @@ - #include - #include - #include -+#include - #include - #include - -@@ -62,12 +63,19 @@ - #define MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET 0x37 - #define MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET 0x3a - #define MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET 0x3b -+#define MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET 0x3c -+#define MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET 0x3d -+#define MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET 0x3e -+#define MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET 0x3f - #define MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET 0x40 - #define MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET 0x41 - #define MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET 0x42 - #define MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET 0x43 - #define MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET 0x44 - #define MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET 0x45 -+#define MLXPLAT_CPLD_LPC_REG_BRD_OFFSET 0x47 -+#define MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET 0x48 -+#define MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET 0x49 - #define MLXPLAT_CPLD_LPC_REG_GWP_OFFSET 0x4a - #define MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET 0x4b - #define MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET 0x4c -@@ -97,6 +105,9 @@ - #define MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET 0x94 - #define MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET 0x95 - #define MLXPLAT_CPLD_LPC_REG_EROTE_MASK_OFFSET 0x96 -+#define MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET 0x97 -+#define MLXPLAT_CPLD_LPC_REG_PWRB_EVENT_OFFSET 0x98 -+#define MLXPLAT_CPLD_LPC_REG_PWRB_MASK_OFFSET 0x99 - #define MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET 0x9a - #define MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET 0x9b - #define MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET 0x9c -@@ -128,6 +139,7 @@ - #define MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET 0xd1 - #define MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET 0xd2 - #define MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET 0xd3 -+#define MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET 0xd9 - #define MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET 0xde - #define MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET 0xdf - #define MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET 0xe0 -@@ -211,6 +223,7 @@ - MLXPLAT_CPLD_AGGR_MASK_LC_SDWN) - #define MLXPLAT_CPLD_LOW_AGGR_MASK_LOW 0xc1 - #define MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2 BIT(2) -+#define MLXPLAT_CPLD_LOW_AGGR_MASK_PWR_BUT BIT(4) - #define MLXPLAT_CPLD_LOW_AGGR_MASK_I2C BIT(6) - #define MLXPLAT_CPLD_PSU_MASK GENMASK(1, 0) - #define MLXPLAT_CPLD_PWR_MASK GENMASK(1, 0) -@@ -225,6 +238,16 @@ - #define MLXPLAT_CPLD_VOLTREG_UPD_MASK GENMASK(5, 4) - #define MLXPLAT_CPLD_GWP_MASK GENMASK(0, 0) - #define MLXPLAT_CPLD_EROT_MASK GENMASK(1, 0) -+#define MLXPLAT_CPLD_PWR_BUTTON_MASK BIT(0) -+#define MLXPLAT_CPLD_LATCH_RST_MASK BIT(5) -+#define MLXPLAT_CPLD_THERMAL1_PDB_MASK BIT(3) -+#define MLXPLAT_CPLD_THERMAL2_PDB_MASK BIT(4) -+#define MLXPLAT_CPLD_INTRUSION_MASK BIT(6) -+#define MLXPLAT_CPLD_PWM_PG_MASK BIT(7) -+#define MLXPLAT_CPLD_L1_CHA_HEALTH_MASK (MLXPLAT_CPLD_THERMAL1_PDB_MASK | \ -+ MLXPLAT_CPLD_THERMAL2_PDB_MASK | \ -+ MLXPLAT_CPLD_INTRUSION_MASK |\ -+ MLXPLAT_CPLD_PWM_PG_MASK) - #define MLXPLAT_CPLD_I2C_CAP_BIT 0x04 - #define MLXPLAT_CPLD_I2C_CAP_MASK GENMASK(5, MLXPLAT_CPLD_I2C_CAP_BIT) - -@@ -237,6 +260,8 @@ - /* Masks for aggregation for modular systems */ - #define MLXPLAT_CPLD_LPC_LC_MASK GENMASK(7, 0) - -+#define MLXPLAT_CPLD_HALT_MASK BIT(3) -+ - /* Default I2C parent bus number */ - #define MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR 1 - -@@ -317,6 +342,8 @@ struct mlxplat_priv { - void *regmap; - }; - -+static struct platform_device *mlxplat_dev; -+ - /* Regions for LPC I2C controller and LPC base register space */ - static const struct resource mlxplat_lpc_resources[] = { - [0] = DEFINE_RES_NAMED(MLXPLAT_CPLD_LPC_I2C_BASE_ADRR, -@@ -476,7 +503,7 @@ static struct i2c_mux_reg_platform_data mlxplat_modular_mux_data[] = { - }, - }; - --/* Platform channels for rack swicth system family */ -+/* Platform channels for rack switch system family */ - static const int mlxplat_rack_switch_channels[] = { - 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, - }; -@@ -2409,6 +2436,156 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_rack_switch_data = { - .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW, - }; - -+/* Callback performs graceful shutdown after notification about power button event */ -+static int -+mlxplat_mlxcpld_l1_switch_pwr_events_handler(void *handle, enum mlxreg_hotplug_kind kind, -+ u8 action) -+{ -+ dev_info(&mlxplat_dev->dev, "System shutdown due to short press of power button"); -+ kernel_halt(); -+ return 0; -+} -+ -+static struct mlxreg_core_hotplug_notifier mlxplat_mlxcpld_l1_switch_pwr_events_notifier = { -+ .user_handler = mlxplat_mlxcpld_l1_switch_pwr_events_handler, -+}; -+ -+/* Platform hotplug for l1 switch systems family data */ -+static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_pwr_events_items_data[] = { -+ { -+ .label = "power_button", -+ .reg = MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET, -+ .mask = MLXPLAT_CPLD_PWR_BUTTON_MASK, -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ .hpdev.notifier = &mlxplat_mlxcpld_l1_switch_pwr_events_notifier, -+ }, -+}; -+ -+/* Callback activates latch reset flow after notification about intrusion event */ -+static int -+mlxplat_mlxcpld_l1_switch_intrusion_events_handler(void *handle, enum mlxreg_hotplug_kind kind, -+ u8 action) -+{ -+ struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev); -+ u32 regval; -+ int err; -+ -+ err = regmap_read(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ®val); -+ if (err) -+ goto fail_regmap_read; -+ -+ if (action) { -+ dev_info(&mlxplat_dev->dev, "Detected intrusion - system latch is opened"); -+ err = regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, -+ regval | MLXPLAT_CPLD_LATCH_RST_MASK); -+ } else { -+ dev_info(&mlxplat_dev->dev, "System latch is properly closed"); -+ err = regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, -+ regval & ~MLXPLAT_CPLD_LATCH_RST_MASK); -+ } -+ -+ if (err) -+ goto fail_regmap_write; -+ -+ return 0; -+ -+fail_regmap_read: -+fail_regmap_write: -+ dev_err(&mlxplat_dev->dev, "Register access failed"); -+ return err; -+} -+ -+static struct mlxreg_core_hotplug_notifier mlxplat_mlxcpld_l1_switch_intrusion_events_notifier = { -+ .user_handler = mlxplat_mlxcpld_l1_switch_intrusion_events_handler, -+}; -+ -+static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_health_events_items_data[] = { -+ { -+ .label = "thermal1_pdb", -+ .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, -+ .mask = MLXPLAT_CPLD_THERMAL1_PDB_MASK, -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ }, -+ { -+ .label = "thermal2_pdb", -+ .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, -+ .mask = MLXPLAT_CPLD_THERMAL2_PDB_MASK, -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ }, -+ { -+ .label = "intrusion", -+ .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, -+ .mask = MLXPLAT_CPLD_INTRUSION_MASK, -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ .hpdev.notifier = &mlxplat_mlxcpld_l1_switch_intrusion_events_notifier, -+ }, -+ { -+ .label = "pwm_pg", -+ .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, -+ .mask = MLXPLAT_CPLD_PWM_PG_MASK, -+ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ }, -+}; -+ -+static struct mlxreg_core_item mlxplat_mlxcpld_l1_switch_events_items[] = { -+ { -+ .data = mlxplat_mlxcpld_default_ng_fan_items_data, -+ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, -+ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, -+ .mask = MLXPLAT_CPLD_FAN_NG_MASK, -+ .count = ARRAY_SIZE(mlxplat_mlxcpld_default_ng_fan_items_data), -+ .inversed = 1, -+ .health = false, -+ }, -+ { -+ .data = mlxplat_mlxcpld_erot_ap_items_data, -+ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, -+ .reg = MLXPLAT_CPLD_LPC_REG_EROT_OFFSET, -+ .mask = MLXPLAT_CPLD_EROT_MASK, -+ .count = ARRAY_SIZE(mlxplat_mlxcpld_erot_ap_items_data), -+ .inversed = 1, -+ .health = false, -+ }, -+ { -+ .data = mlxplat_mlxcpld_erot_error_items_data, -+ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, -+ .reg = MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET, -+ .mask = MLXPLAT_CPLD_EROT_MASK, -+ .count = ARRAY_SIZE(mlxplat_mlxcpld_erot_error_items_data), -+ .inversed = 1, -+ .health = false, -+ }, -+ { -+ .data = mlxplat_mlxcpld_l1_switch_pwr_events_items_data, -+ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, -+ .reg = MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET, -+ .mask = MLXPLAT_CPLD_PWR_BUTTON_MASK, -+ .count = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_pwr_events_items_data), -+ .inversed = 0, -+ .health = false, -+ }, -+ { -+ .data = mlxplat_mlxcpld_l1_switch_health_events_items_data, -+ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, -+ .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, -+ .mask = MLXPLAT_CPLD_L1_CHA_HEALTH_MASK, -+ .count = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_health_events_items_data), -+ .inversed = 0, -+ .health = false, -+ .ind = 8, -+ }, -+}; -+ -+static -+struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_l1_switch_data = { -+ .items = mlxplat_mlxcpld_l1_switch_events_items, -+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_events_items), -+ .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, -+ .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, -+ .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, -+ .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_PWR_BUT, -+}; -+ - static struct spi_board_info rack_switch_switch_spi_board_info[] = { - { - .modalias = "spidev", -@@ -3066,6 +3243,114 @@ static struct mlxreg_core_platform_data mlxplat_qmb8700_led_data = { - .counter = ARRAY_SIZE(mlxplat_mlxcpld_qmb8700_led_data), - }; - -+/* Platform led data for chassis system */ -+static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_led_data[] = { -+ { -+ .label = "status:green", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, -+ }, -+ { -+ .label = "status:orange", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK -+ }, -+ { -+ .label = "fan1:green", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .bit = BIT(0), -+ }, -+ { -+ .label = "fan1:orange", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .bit = BIT(0), -+ }, -+ { -+ .label = "fan2:green", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .bit = BIT(1), -+ }, -+ { -+ .label = "fan2:orange", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .bit = BIT(1), -+ }, -+ { -+ .label = "fan3:green", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .bit = BIT(2), -+ }, -+ { -+ .label = "fan3:orange", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .bit = BIT(2), -+ }, -+ { -+ .label = "fan4:green", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .bit = BIT(3), -+ }, -+ { -+ .label = "fan4:orange", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .bit = BIT(3), -+ }, -+ { -+ .label = "fan5:green", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .bit = BIT(4), -+ }, -+ { -+ .label = "fan5:orange", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .bit = BIT(4), -+ }, -+ { -+ .label = "fan6:green", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .bit = BIT(5), -+ }, -+ { -+ .label = "fan6:orange", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, -+ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, -+ .bit = BIT(5), -+ }, -+ { -+ .label = "uid:blue", -+ .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, -+ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, -+ }, -+}; -+ -+static struct mlxreg_core_platform_data mlxplat_l1_switch_led_data = { -+ .data = mlxplat_mlxcpld_l1_switch_led_data, -+ .counter = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_led_data), -+}; -+ - /* Platform register access default */ - static struct mlxreg_core_data mlxplat_mlxcpld_default_regs_io_data[] = { - { -@@ -3594,12 +3879,48 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { - .mask = GENMASK(7, 0) & ~BIT(3), - .mode = 0200, - }, -+ { -+ .label = "deep_pwr_cycle", -+ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(5), -+ .mode = 0200, -+ }, -+ { -+ .label = "latch_reset", -+ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(5), -+ .mode = 0200, -+ }, - { - .label = "jtag_enable", - .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, - .mask = GENMASK(7, 0) & ~BIT(4), - .mode = 0644, - }, -+ { -+ .label = "dbg1", -+ .reg = MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0644, -+ }, -+ { -+ .label = "dbg2", -+ .reg = MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0644, -+ }, -+ { -+ .label = "dbg3", -+ .reg = MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0644, -+ }, -+ { -+ .label = "dbg4", -+ .reg = MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0644, -+ }, - { - .label = "asic_health", - .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, -@@ -4913,11 +5234,18 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET: - case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_BRD_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET: -@@ -4932,6 +5260,8 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_EROTE_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_PWRB_EVENT_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_PWRB_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET: -@@ -4960,6 +5290,7 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: - case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET: -@@ -5010,6 +5341,10 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET: -@@ -5019,6 +5354,9 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_GWP_OFFSET: - case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_BRD_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET: - case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: -@@ -5040,6 +5378,9 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET: - case MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_EROTE_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_PWRB_EVENT_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_PWRB_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET: -@@ -5076,6 +5417,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: - case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET: -@@ -5152,6 +5494,10 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET: -@@ -5161,6 +5507,9 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_GWP_OFFSET: - case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_BRD_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET: - case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: -@@ -5182,6 +5531,9 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET: - case MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_EROTE_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_PWRB_EVENT_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_PWRB_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET: - case MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET: -@@ -5212,6 +5564,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: - case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET: -@@ -5407,7 +5760,6 @@ static struct resource mlxplat_mlxcpld_resources[] = { - [0] = DEFINE_RES_IRQ_NAMED(MLXPLAT_CPLD_LPC_SYSIRQ, "mlxreg-hotplug"), - }; - --static struct platform_device *mlxplat_dev; - static struct mlxreg_core_hotplug_platform_data *mlxplat_i2c; - static struct mlxreg_core_hotplug_platform_data *mlxplat_hotplug; - static struct mlxreg_core_platform_data *mlxplat_led; -@@ -5418,6 +5770,14 @@ static struct mlxreg_core_platform_data - static const struct regmap_config *mlxplat_regmap_config; - static struct spi_board_info *mlxplat_spi; - -+/* Platform default poweroff function */ -+static void mlxplat_poweroff(void) -+{ -+ struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev); -+ -+ regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, MLXPLAT_CPLD_HALT_MASK); -+} -+ - static int __init mlxplat_dmi_default_matched(const struct dmi_system_id *dmi) - { - int i; -@@ -5740,6 +6100,29 @@ static int __init mlxplat_dmi_ng800_matched(const struct dmi_system_id *dmi) - return 1; - } - -+static int __init mlxplat_dmi_l1_switch_matched(const struct dmi_system_id *dmi) -+{ -+ int i; -+ -+ mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; -+ mlxplat_mux_num = ARRAY_SIZE(mlxplat_rack_switch_mux_data); -+ mlxplat_mux_data = mlxplat_rack_switch_mux_data; -+ mlxplat_hotplug = &mlxplat_mlxcpld_l1_switch_data; -+ mlxplat_hotplug->deferred_nr = -+ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; -+ mlxplat_led = &mlxplat_l1_switch_led_data; -+ mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; -+ mlxplat_fan = &mlxplat_default_fan_data; -+ for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) -+ mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; -+ mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; -+ mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_rack_switch; -+ pm_power_off = mlxplat_poweroff; -+ mlxplat_spi = rack_switch_switch_spi_board_info; -+ -+ return 1; -+} -+ - static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { - { - .callback = mlxplat_dmi_default_wc_matched, -@@ -5835,6 +6218,12 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { - DMI_MATCH(DMI_BOARD_NAME, "VMOD0015"), - }, - }, -+ { -+ .callback = mlxplat_dmi_l1_switch_matched, -+ .matches = { -+ DMI_MATCH(DMI_BOARD_NAME, "VMOD0017"), -+ }, -+ }, - { - .callback = mlxplat_dmi_msn274x_matched, - .matches = { -@@ -6167,6 +6556,8 @@ static void __exit mlxplat_exit(void) - struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev); - int i; - -+ if (pm_power_off) -+ pm_power_off = NULL; - for (i = MLXPLAT_CPLD_WD_MAX_DEVS - 1; i >= 0 ; i--) - platform_device_unregister(priv->pdev_wd[i]); - if (priv->pdev_fan) --- -2.20.1 - diff --git a/platform/mellanox/non-upstream-patches/patches/0183-platform-mellanox-Split-initialization-procedure.patch b/platform/mellanox/non-upstream-patches/patches/0183-platform-mellanox-Split-initialization-procedure.patch deleted file mode 100644 index deb8591ae1c3..000000000000 --- a/platform/mellanox/non-upstream-patches/patches/0183-platform-mellanox-Split-initialization-procedure.patch +++ /dev/null @@ -1,168 +0,0 @@ -From 5a2cfa144640a047ab17de5ef12dfefbe7e2f8c3 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Sun, 11 Dec 2022 10:44:43 +0200 -Subject: [PATCH backport 5.10 2/5] platform: mellanox: Split initialization - procedure - -Split mlxplat_init() into two by adding mlxplat_pre_init(). - -Motivation is to prepare 'mlx-platform' driver to support systems -equipped PCIe based programming logic device. - -Such systems are supposed to use different system resources, thus this -commit separates resources allocation related code. - -Signed-off-by: Vadim Pasternak ---- - drivers/platform/x86/mlx-platform.c | 78 ++++++++++++++++++++++------- - 1 file changed, 60 insertions(+), 18 deletions(-) - -diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c -index a2addd1b3..199f22d72 100644 ---- a/drivers/platform/x86/mlx-platform.c -+++ b/drivers/platform/x86/mlx-platform.c -@@ -330,6 +330,8 @@ - * @pdev_fan - FAN platform devices - * @pdev_wd - array of watchdog platform devices - * @regmap: device register map -+ * @hotplug_resources: system hotplug resources -+ * @hotplug_resources_size: size of system hotplug resources - */ - struct mlxplat_priv { - struct platform_device *pdev_i2c; -@@ -340,6 +342,8 @@ struct mlxplat_priv { - struct platform_device *pdev_fan; - struct platform_device *pdev_wd[MLXPLAT_CPLD_WD_MAX_DEVS]; - void *regmap; -+ struct resource *hotplug_resources; -+ unsigned int hotplug_resources_size; - }; - - static struct platform_device *mlxplat_dev; -@@ -6365,20 +6369,63 @@ static int mlxplat_mlxcpld_check_wd_capability(void *regmap) - return 0; - } - -+static int mlxplat_lpc_cpld_device_init(struct resource **hotplug_resources, -+ unsigned int *hotplug_resources_size) -+{ -+ int err; -+ -+ mlxplat_dev = platform_device_register_simple(MLX_PLAT_DEVICE_NAME, PLATFORM_DEVID_NONE, -+ mlxplat_lpc_resources, -+ ARRAY_SIZE(mlxplat_lpc_resources)); -+ if (IS_ERR(mlxplat_dev)) -+ return PTR_ERR(mlxplat_dev); -+ -+ mlxplat_mlxcpld_regmap_ctx.base = devm_ioport_map(&mlxplat_dev->dev, -+ mlxplat_lpc_resources[1].start, 1); -+ if (!mlxplat_mlxcpld_regmap_ctx.base) { -+ err = -ENOMEM; -+ goto fail_devm_ioport_map; -+ } -+ -+ *hotplug_resources = mlxplat_mlxcpld_resources; -+ *hotplug_resources_size = ARRAY_SIZE(mlxplat_mlxcpld_resources); -+ -+ return 0; -+ -+fail_devm_ioport_map: -+ platform_device_unregister(mlxplat_dev); -+ return err; -+} -+ -+static void mlxplat_lpc_cpld_device_exit(void) -+{ -+ platform_device_unregister(mlxplat_dev); -+} -+ -+static int -+mlxplat_pre_init(struct resource **hotplug_resources, unsigned int *hotplug_resources_size) -+{ -+ return mlxplat_lpc_cpld_device_init(hotplug_resources, hotplug_resources_size); -+} -+ -+static void mlxplat_post_exit(void) -+{ -+ mlxplat_lpc_cpld_device_exit(); -+} -+ - static int __init mlxplat_init(void) - { -+ unsigned int hotplug_resources_size; -+ struct resource *hotplug_resources; - struct mlxplat_priv *priv; - int i, j, nr, err; - - if (!dmi_check_system(mlxplat_dmi_table)) - return -ENODEV; - -- mlxplat_dev = platform_device_register_simple(MLX_PLAT_DEVICE_NAME, -1, -- mlxplat_lpc_resources, -- ARRAY_SIZE(mlxplat_lpc_resources)); -- -- if (IS_ERR(mlxplat_dev)) -- return PTR_ERR(mlxplat_dev); -+ err = mlxplat_pre_init(&hotplug_resources, &hotplug_resources_size); -+ if (err) -+ return err; - - priv = devm_kzalloc(&mlxplat_dev->dev, sizeof(struct mlxplat_priv), - GFP_KERNEL); -@@ -6388,12 +6435,8 @@ static int __init mlxplat_init(void) - } - platform_set_drvdata(mlxplat_dev, priv); - -- mlxplat_mlxcpld_regmap_ctx.base = devm_ioport_map(&mlxplat_dev->dev, -- mlxplat_lpc_resources[1].start, 1); -- if (!mlxplat_mlxcpld_regmap_ctx.base) { -- err = -ENOMEM; -- goto fail_alloc; -- } -+ priv->hotplug_resources = hotplug_resources; -+ priv->hotplug_resources_size = hotplug_resources_size; - - if (!mlxplat_regmap_config) - mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config; -@@ -6414,8 +6457,8 @@ static int __init mlxplat_init(void) - if (mlxplat_i2c) - mlxplat_i2c->regmap = priv->regmap; - priv->pdev_i2c = platform_device_register_resndata(&mlxplat_dev->dev, "i2c_mlxcpld", -- nr, mlxplat_mlxcpld_resources, -- ARRAY_SIZE(mlxplat_mlxcpld_resources), -+ nr, priv->hotplug_resources, -+ priv->hotplug_resources_size, - mlxplat_i2c, sizeof(*mlxplat_i2c)); - if (IS_ERR(priv->pdev_i2c)) { - err = PTR_ERR(priv->pdev_i2c); -@@ -6439,8 +6482,8 @@ static int __init mlxplat_init(void) - priv->pdev_hotplug = - platform_device_register_resndata(&mlxplat_dev->dev, - "mlxreg-hotplug", PLATFORM_DEVID_NONE, -- mlxplat_mlxcpld_resources, -- ARRAY_SIZE(mlxplat_mlxcpld_resources), -+ priv->hotplug_resources, -+ priv->hotplug_resources_size, - mlxplat_hotplug, sizeof(*mlxplat_hotplug)); - if (IS_ERR(priv->pdev_hotplug)) { - err = PTR_ERR(priv->pdev_hotplug); -@@ -6545,7 +6588,6 @@ static int __init mlxplat_init(void) - platform_device_unregister(priv->pdev_mux[i]); - platform_device_unregister(priv->pdev_i2c); - fail_alloc: -- platform_device_unregister(mlxplat_dev); - - return err; - } -@@ -6573,7 +6615,7 @@ static void __exit mlxplat_exit(void) - platform_device_unregister(priv->pdev_mux[i]); - - platform_device_unregister(priv->pdev_i2c); -- platform_device_unregister(mlxplat_dev); -+ mlxplat_post_exit(); - } - module_exit(mlxplat_exit); - --- -2.20.1 - diff --git a/platform/mellanox/non-upstream-patches/patches/0184-platform-mellanox-Split-logic-in-init-and-exit-flow.patch b/platform/mellanox/non-upstream-patches/patches/0184-platform-mellanox-Split-logic-in-init-and-exit-flow.patch deleted file mode 100644 index 3810a2dc03a9..000000000000 --- a/platform/mellanox/non-upstream-patches/patches/0184-platform-mellanox-Split-logic-in-init-and-exit-flow.patch +++ /dev/null @@ -1,455 +0,0 @@ -From f00081a6e0b7af5a0b85db3121afe3cc6a62f9e7 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Sun, 11 Dec 2022 11:08:07 +0200 -Subject: [PATCH backport 5.10 072/150] platform: mellanox: Split logic in init - and exit flow - -Split logic in mlxplat_init()/mlxplat_exit() routines. -Separate initialization of I2C infrastructure and others platform -drivers. - -Motivation is to provide synchronization between I2C bus and mux -drivers and other drivers using this infrastructure. -I2C main bus and MUX busses are implemented in FPGA logic. On some new -systems the numbers allocated for these busses could be variable -depending on order of initialization of I2C native busses. Since bus -numbers are passed to some other platform drivers during initialization -flow, it is necessary to synchronize completion of I2C infrastructure -drivers and activation of rest of drivers. - -Thus initialization flow will be performed in synchronized order. - -Signed-off-by: Vadim Pasternak ---- - drivers/platform/x86/mlx-platform.c | 313 ++++++++++++++++++---------- - 1 file changed, 204 insertions(+), 109 deletions(-) - -diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c -index 199f22d72..05a630135 100644 ---- a/drivers/platform/x86/mlx-platform.c -+++ b/drivers/platform/x86/mlx-platform.c -@@ -321,6 +321,9 @@ - /* Default value for PWM control register for rack switch system */ - #define MLXPLAT_REGMAP_NVSWITCH_PWM_DEFAULT 0xf4 - -+#define MLXPLAT_I2C_MAIN_BUS_NOTIFIED 0x01 -+#define MLXPLAT_I2C_MAIN_BUS_HANDLE_CREATED 0x02 -+ - /* mlxplat_priv - platform private data - * @pdev_i2c - i2c controller platform device - * @pdev_mux - array of mux platform devices -@@ -332,6 +335,7 @@ - * @regmap: device register map - * @hotplug_resources: system hotplug resources - * @hotplug_resources_size: size of system hotplug resources -+ * @hi2c_main_init_status: init status of I2C main bus - */ - struct mlxplat_priv { - struct platform_device *pdev_i2c; -@@ -344,9 +348,11 @@ struct mlxplat_priv { - void *regmap; - struct resource *hotplug_resources; - unsigned int hotplug_resources_size; -+ u8 i2c_main_init_status; - }; - - static struct platform_device *mlxplat_dev; -+static int mlxplat_i2c_main_complition_notify(void *handle, int id); - - /* Regions for LPC I2C controller and LPC base register space */ - static const struct resource mlxplat_lpc_resources[] = { -@@ -381,6 +387,7 @@ static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_i2c_ng_data = { - .mask = MLXPLAT_CPLD_AGGR_MASK_COMEX, - .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET, - .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_I2C, -+ .completion_notify = mlxplat_i2c_main_complition_notify, - }; - - /* Platform default channels */ -@@ -6413,68 +6420,9 @@ static void mlxplat_post_exit(void) - mlxplat_lpc_cpld_device_exit(); - } - --static int __init mlxplat_init(void) -+static int mlxplat_post_init(struct mlxplat_priv *priv) - { -- unsigned int hotplug_resources_size; -- struct resource *hotplug_resources; -- struct mlxplat_priv *priv; -- int i, j, nr, err; -- -- if (!dmi_check_system(mlxplat_dmi_table)) -- return -ENODEV; -- -- err = mlxplat_pre_init(&hotplug_resources, &hotplug_resources_size); -- if (err) -- return err; -- -- priv = devm_kzalloc(&mlxplat_dev->dev, sizeof(struct mlxplat_priv), -- GFP_KERNEL); -- if (!priv) { -- err = -ENOMEM; -- goto fail_alloc; -- } -- platform_set_drvdata(mlxplat_dev, priv); -- -- priv->hotplug_resources = hotplug_resources; -- priv->hotplug_resources_size = hotplug_resources_size; -- -- if (!mlxplat_regmap_config) -- mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config; -- -- priv->regmap = devm_regmap_init(&mlxplat_dev->dev, NULL, -- &mlxplat_mlxcpld_regmap_ctx, -- mlxplat_regmap_config); -- if (IS_ERR(priv->regmap)) { -- err = PTR_ERR(priv->regmap); -- goto fail_alloc; -- } -- -- err = mlxplat_mlxcpld_verify_bus_topology(&nr); -- if (nr < 0) -- goto fail_alloc; -- -- nr = (nr == mlxplat_max_adap_num) ? -1 : nr; -- if (mlxplat_i2c) -- mlxplat_i2c->regmap = priv->regmap; -- priv->pdev_i2c = platform_device_register_resndata(&mlxplat_dev->dev, "i2c_mlxcpld", -- nr, priv->hotplug_resources, -- priv->hotplug_resources_size, -- mlxplat_i2c, sizeof(*mlxplat_i2c)); -- if (IS_ERR(priv->pdev_i2c)) { -- err = PTR_ERR(priv->pdev_i2c); -- goto fail_alloc; -- } -- -- for (i = 0; i < mlxplat_mux_num; i++) { -- priv->pdev_mux[i] = platform_device_register_resndata(&priv->pdev_i2c->dev, -- "i2c-mux-reg", i, NULL, 0, -- &mlxplat_mux_data[i], -- sizeof(mlxplat_mux_data[i])); -- if (IS_ERR(priv->pdev_mux[i])) { -- err = PTR_ERR(priv->pdev_mux[i]); -- goto fail_platform_mux_register; -- } -- } -+ int i = 0, err; - - /* Add hotplug driver */ - if (mlxplat_hotplug) { -@@ -6487,19 +6435,10 @@ static int __init mlxplat_init(void) - mlxplat_hotplug, sizeof(*mlxplat_hotplug)); - if (IS_ERR(priv->pdev_hotplug)) { - err = PTR_ERR(priv->pdev_hotplug); -- goto fail_platform_mux_register; -+ goto fail_platform_hotplug_register; - } - } - -- /* Set default registers. */ -- for (j = 0; j < mlxplat_regmap_config->num_reg_defaults; j++) { -- err = regmap_write(priv->regmap, -- mlxplat_regmap_config->reg_defaults[j].reg, -- mlxplat_regmap_config->reg_defaults[j].def); -- if (err) -- goto fail_platform_mux_register; -- } -- - /* Add LED driver. */ - if (mlxplat_led) { - mlxplat_led->regmap = priv->regmap; -@@ -6509,7 +6448,7 @@ static int __init mlxplat_init(void) - sizeof(*mlxplat_led)); - if (IS_ERR(priv->pdev_led)) { - err = PTR_ERR(priv->pdev_led); -- goto fail_platform_hotplug_register; -+ goto fail_platform_leds_register; - } - } - -@@ -6523,7 +6462,7 @@ static int __init mlxplat_init(void) - sizeof(*mlxplat_regs_io)); - if (IS_ERR(priv->pdev_io_regs)) { - err = PTR_ERR(priv->pdev_io_regs); -- goto fail_platform_led_register; -+ goto fail_platform_io_register; - } - } - -@@ -6536,7 +6475,7 @@ static int __init mlxplat_init(void) - sizeof(*mlxplat_fan)); - if (IS_ERR(priv->pdev_fan)) { - err = PTR_ERR(priv->pdev_fan); -- goto fail_platform_io_regs_register; -+ goto fail_platform_fan_register; - } - } - -@@ -6547,59 +6486,42 @@ static int __init mlxplat_init(void) - err = mlxplat_mlxcpld_check_wd_capability(priv->regmap); - if (err) - goto fail_platform_wd_register; -- for (j = 0; j < MLXPLAT_CPLD_WD_MAX_DEVS; j++) { -- if (mlxplat_wd_data[j]) { -- mlxplat_wd_data[j]->regmap = priv->regmap; -- priv->pdev_wd[j] = -- platform_device_register_resndata(&mlxplat_dev->dev, "mlx-wdt", j, -- NULL, 0, mlxplat_wd_data[j], -- sizeof(*mlxplat_wd_data[j])); -- if (IS_ERR(priv->pdev_wd[j])) { -- err = PTR_ERR(priv->pdev_wd[j]); -+ for (i = 0; i < MLXPLAT_CPLD_WD_MAX_DEVS; i++) { -+ if (mlxplat_wd_data[i]) { -+ mlxplat_wd_data[i]->regmap = priv->regmap; -+ priv->pdev_wd[i] = -+ platform_device_register_resndata(&mlxplat_dev->dev, "mlx-wdt", i, -+ NULL, 0, mlxplat_wd_data[i], -+ sizeof(*mlxplat_wd_data[i])); -+ if (IS_ERR(priv->pdev_wd[i])) { -+ err = PTR_ERR(priv->pdev_wd[i]); - goto fail_platform_wd_register; - } - } - } - -- /* Sync registers with hardware. */ -- regcache_mark_dirty(priv->regmap); -- err = regcache_sync(priv->regmap); -- if (err) -- goto fail_platform_wd_register; -- - return 0; - - fail_platform_wd_register: -- while (--j >= 0) -- platform_device_unregister(priv->pdev_wd[j]); -- if (mlxplat_fan) -- platform_device_unregister(priv->pdev_fan); --fail_platform_io_regs_register: -+ while (--i >= 0) -+ platform_device_unregister(priv->pdev_wd[i]); -+fail_platform_fan_register: - if (mlxplat_regs_io) - platform_device_unregister(priv->pdev_io_regs); --fail_platform_led_register: -+fail_platform_io_register: - if (mlxplat_led) - platform_device_unregister(priv->pdev_led); --fail_platform_hotplug_register: -+fail_platform_leds_register: - if (mlxplat_hotplug) - platform_device_unregister(priv->pdev_hotplug); --fail_platform_mux_register: -- while (--i >= 0) -- platform_device_unregister(priv->pdev_mux[i]); -- platform_device_unregister(priv->pdev_i2c); --fail_alloc: -- -+fail_platform_hotplug_register: - return err; - } --module_init(mlxplat_init); - --static void __exit mlxplat_exit(void) -+static void mlxplat_pre_exit(struct mlxplat_priv *priv) - { -- struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev); - int i; - -- if (pm_power_off) -- pm_power_off = NULL; - for (i = MLXPLAT_CPLD_WD_MAX_DEVS - 1; i >= 0 ; i--) - platform_device_unregister(priv->pdev_wd[i]); - if (priv->pdev_fan) -@@ -6610,13 +6532,186 @@ static void __exit mlxplat_exit(void) - platform_device_unregister(priv->pdev_led); - if (priv->pdev_hotplug) - platform_device_unregister(priv->pdev_hotplug); -+} -+ -+static int -+mlxplat_i2c_mux_complition_notify(void *handle, struct i2c_adapter *parent, -+ struct i2c_adapter *adapters[]) -+{ -+ struct mlxplat_priv *priv = handle; -+ -+ return mlxplat_post_init(priv); -+} - -- for (i = mlxplat_mux_num - 1; i >= 0 ; i--) -+static int mlxplat_i2c_mux_topolgy_init(struct mlxplat_priv *priv) -+{ -+ int i, err; -+ -+ if (!priv->pdev_i2c) { -+ priv->i2c_main_init_status = MLXPLAT_I2C_MAIN_BUS_NOTIFIED; -+ return 0; -+ } -+ -+ priv->i2c_main_init_status = MLXPLAT_I2C_MAIN_BUS_HANDLE_CREATED; -+ for (i = 0; i < mlxplat_mux_num; i++) { -+ priv->pdev_mux[i] = platform_device_register_resndata(&priv->pdev_i2c->dev, -+ "i2c-mux-reg", i, NULL, 0, -+ &mlxplat_mux_data[i], -+ sizeof(mlxplat_mux_data[i])); -+ if (IS_ERR(priv->pdev_mux[i])) { -+ err = PTR_ERR(priv->pdev_mux[i]); -+ goto fail_platform_mux_register; -+ } -+ } -+ -+ return mlxplat_i2c_mux_complition_notify(priv, NULL, NULL); -+ -+fail_platform_mux_register: -+ while (--i >= 0) - platform_device_unregister(priv->pdev_mux[i]); -+ return err; -+} -+ -+static void mlxplat_i2c_mux_topolgy_exit(struct mlxplat_priv *priv) -+{ -+ int i; -+ -+ for (i = mlxplat_mux_num - 1; i >= 0 ; i--) { -+ if (priv->pdev_mux[i]) -+ platform_device_unregister(priv->pdev_mux[i]); -+ } - -- platform_device_unregister(priv->pdev_i2c); - mlxplat_post_exit(); - } -+ -+static int mlxplat_i2c_main_complition_notify(void *handle, int id) -+{ -+ struct mlxplat_priv *priv = handle; -+ -+ return mlxplat_i2c_mux_topolgy_init(priv); -+} -+ -+static int mlxplat_i2c_main_init(struct mlxplat_priv *priv) -+{ -+ int nr, err; -+ -+ if (!mlxplat_i2c) -+ return 0; -+ -+ err = mlxplat_mlxcpld_verify_bus_topology(&nr); -+ if (nr < 0) -+ goto fail_mlxplat_mlxcpld_verify_bus_topology; -+ -+ nr = (nr == mlxplat_max_adap_num) ? -1 : nr; -+ mlxplat_i2c->regmap = priv->regmap; -+ mlxplat_i2c->handle = priv; -+ -+ priv->pdev_i2c = platform_device_register_resndata(&mlxplat_dev->dev, "i2c_mlxcpld", -+ nr, priv->hotplug_resources, -+ priv->hotplug_resources_size, -+ mlxplat_i2c, sizeof(*mlxplat_i2c)); -+ if (IS_ERR(priv->pdev_i2c)) { -+ err = PTR_ERR(priv->pdev_i2c); -+ goto fail_platform_i2c_register; -+ } -+ -+ if (priv->i2c_main_init_status == MLXPLAT_I2C_MAIN_BUS_NOTIFIED) { -+ err = mlxplat_i2c_mux_topolgy_init(priv); -+ if (err) -+ goto fail_mlxplat_i2c_mux_topolgy_init; -+ } -+ -+ return 0; -+ -+fail_mlxplat_i2c_mux_topolgy_init: -+fail_platform_i2c_register: -+fail_mlxplat_mlxcpld_verify_bus_topology: -+ return err; -+} -+ -+static void mlxplat_i2c_main_exit(struct mlxplat_priv *priv) -+{ -+ mlxplat_i2c_mux_topolgy_exit(priv); -+ if (priv->pdev_i2c) -+ platform_device_unregister(priv->pdev_i2c); -+} -+ -+static int __init mlxplat_init(void) -+{ -+ unsigned int hotplug_resources_size; -+ struct resource *hotplug_resources; -+ struct mlxplat_priv *priv; -+ int i, err; -+ -+ if (!dmi_check_system(mlxplat_dmi_table)) -+ return -ENODEV; -+ -+ err = mlxplat_pre_init(&hotplug_resources, &hotplug_resources_size); -+ if (err) -+ return err; -+ -+ priv = devm_kzalloc(&mlxplat_dev->dev, sizeof(struct mlxplat_priv), -+ GFP_KERNEL); -+ if (!priv) { -+ err = -ENOMEM; -+ goto fail_alloc; -+ } -+ platform_set_drvdata(mlxplat_dev, priv); -+ priv->hotplug_resources = hotplug_resources; -+ priv->hotplug_resources_size = hotplug_resources_size; -+ -+ if (!mlxplat_regmap_config) -+ mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config; -+ -+ priv->regmap = devm_regmap_init(&mlxplat_dev->dev, NULL, -+ &mlxplat_mlxcpld_regmap_ctx, -+ mlxplat_regmap_config); -+ if (IS_ERR(priv->regmap)) { -+ err = PTR_ERR(priv->regmap); -+ goto fail_alloc; -+ } -+ -+ /* Set default registers. */ -+ for (i = 0; i < mlxplat_regmap_config->num_reg_defaults; i++) { -+ err = regmap_write(priv->regmap, -+ mlxplat_regmap_config->reg_defaults[i].reg, -+ mlxplat_regmap_config->reg_defaults[i].def); -+ if (err) -+ goto fail_regmap_write; -+ } -+ -+ err = mlxplat_i2c_main_init(priv); -+ if (err) -+ goto fail_mlxplat_i2c_main_init; -+ -+ /* Sync registers with hardware. */ -+ regcache_mark_dirty(priv->regmap); -+ err = regcache_sync(priv->regmap); -+ if (err) -+ goto fail_regcache_sync; -+ -+ return 0; -+ -+fail_regcache_sync: -+ mlxplat_pre_exit(priv); -+fail_mlxplat_i2c_main_init: -+fail_regmap_write: -+fail_alloc: -+ mlxplat_post_exit(); -+ -+ return err; -+} -+module_init(mlxplat_init); -+ -+static void __exit mlxplat_exit(void) -+{ -+ struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev); -+ -+ if (pm_power_off) -+ pm_power_off = NULL; -+ mlxplat_pre_exit(priv); -+ mlxplat_i2c_main_exit(priv); -+} - module_exit(mlxplat_exit); - - MODULE_AUTHOR("Vadim Pasternak (vadimp@mellanox.com)"); --- -2.20.1 - diff --git a/platform/mellanox/non-upstream-patches/patches/0185-platform-mellanox-Extend-all-systems-with-I2C-notifi.patch b/platform/mellanox/non-upstream-patches/patches/0185-platform-mellanox-Extend-all-systems-with-I2C-notifi.patch deleted file mode 100644 index 6209d60352a7..000000000000 --- a/platform/mellanox/non-upstream-patches/patches/0185-platform-mellanox-Extend-all-systems-with-I2C-notifi.patch +++ /dev/null @@ -1,81 +0,0 @@ -From 3a61ad447e2ec437079c86c277b80acde19e9173 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Mon, 26 Dec 2022 22:28:33 +0200 -Subject: [PATCH backport 5.10 073/150] platform: mellanox: Extend all systems - with I2C notification callback - -Motivation is to provide synchronization between I2C main bus and other -platform drivers using this notification callback. - -Signed-off-by: Vadim Pasternak ---- - drivers/platform/x86/mlx-platform.c | 11 +++++++++++ - 1 file changed, 11 insertions(+) - -diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c -index 05a630135..1ef0bb975 100644 ---- a/drivers/platform/x86/mlx-platform.c -+++ b/drivers/platform/x86/mlx-platform.c -@@ -365,6 +365,11 @@ static const struct resource mlxplat_lpc_resources[] = { - IORESOURCE_IO), - }; - -+/* Platform systems default i2c data */ -+static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_i2c_default_data = { -+ .completion_notify = mlxplat_i2c_main_complition_notify, -+}; -+ - /* Platform i2c next generation systems data */ - static struct mlxreg_core_data mlxplat_mlxcpld_i2c_ng_items_data[] = { - { -@@ -5807,6 +5812,7 @@ static int __init mlxplat_dmi_default_matched(const struct dmi_system_id *dmi) - mlxplat_led = &mlxplat_default_led_data; - mlxplat_regs_io = &mlxplat_default_regs_io_data; - mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; -+ mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; - - return 1; - } -@@ -5829,6 +5835,7 @@ static int __init mlxplat_dmi_default_wc_matched(const struct dmi_system_id *dmi - mlxplat_led = &mlxplat_default_led_wc_data; - mlxplat_regs_io = &mlxplat_default_regs_io_data; - mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; -+ mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; - - return 1; - } -@@ -5876,6 +5883,7 @@ static int __init mlxplat_dmi_msn21xx_matched(const struct dmi_system_id *dmi) - mlxplat_led = &mlxplat_msn21xx_led_data; - mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data; - mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; -+ mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; - - return 1; - } -@@ -5898,6 +5906,7 @@ static int __init mlxplat_dmi_msn274x_matched(const struct dmi_system_id *dmi) - mlxplat_led = &mlxplat_default_led_data; - mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data; - mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; -+ mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; - - return 1; - } -@@ -5920,6 +5929,7 @@ static int __init mlxplat_dmi_msn201x_matched(const struct dmi_system_id *dmi) - mlxplat_led = &mlxplat_msn21xx_led_data; - mlxplat_regs_io = &mlxplat_msn21xx_regs_io_data; - mlxplat_wd_data[0] = &mlxplat_mlxcpld_wd_set_type1[0]; -+ mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; - - return 1; - } -@@ -5969,6 +5979,7 @@ static int __init mlxplat_dmi_comex_matched(const struct dmi_system_id *dmi) - mlxplat_fan = &mlxplat_default_fan_data; - for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) - mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; -+ mlxplat_i2c = &mlxplat_mlxcpld_i2c_default_data; - mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_comex; - - return 1; --- -2.20.1 - diff --git a/platform/mellanox/non-upstream-patches/patches/0187-platform_data-mlxreg-Add-field-with-mapped-resource-.patch b/platform/mellanox/non-upstream-patches/patches/0187-platform_data-mlxreg-Add-field-with-mapped-resource-.patch deleted file mode 100644 index 2677a484f726..000000000000 --- a/platform/mellanox/non-upstream-patches/patches/0187-platform_data-mlxreg-Add-field-with-mapped-resource-.patch +++ /dev/null @@ -1,37 +0,0 @@ -From e1d1afba7f7285bebb2d30fce961901ee944d201 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Wed, 9 Nov 2022 09:43:28 +0200 -Subject: [PATCH backport 5.10 01/10] platform_data/mlxreg: Add field with - mapped resource address - -Add field with PCIe remapped based address for passing it across -relevant platform drivers sharing common system resources. - -Signed-off-by: Vadim Pasternak ---- - include/linux/platform_data/mlxreg.h | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/include/linux/platform_data/mlxreg.h b/include/linux/platform_data/mlxreg.h -index a6bd74e29..0b9f81a6f 100644 ---- a/include/linux/platform_data/mlxreg.h -+++ b/include/linux/platform_data/mlxreg.h -@@ -216,6 +216,7 @@ struct mlxreg_core_platform_data { - * @mask_low: low aggregation interrupt common mask; - * @deferred_nr: I2C adapter number must be exist prior probing execution; - * @shift_nr: I2C adapter numbers must be incremented by this value; -+ * @addr: mapped resource address; - * @handle: handle to be passed by callback; - * @completion_notify: callback to notify when platform driver probing is done; - */ -@@ -230,6 +231,7 @@ struct mlxreg_core_hotplug_platform_data { - u32 mask_low; - int deferred_nr; - int shift_nr; -+ void __iomem *addr; - void *handle; - int (*completion_notify)(void *handle, int id); - }; --- -2.20.1 - diff --git a/platform/mellanox/non-upstream-patches/patches/0188-i2c-mux-Add-register-map-based-mux-driver.patch b/platform/mellanox/non-upstream-patches/patches/0188-i2c-mux-Add-register-map-based-mux-driver.patch deleted file mode 100644 index 7912bf187352..000000000000 --- a/platform/mellanox/non-upstream-patches/patches/0188-i2c-mux-Add-register-map-based-mux-driver.patch +++ /dev/null @@ -1,253 +0,0 @@ -From 03195e7418ec41d0a118973a392165f11ba881cf Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Wed, 9 Nov 2022 12:22:12 +0200 -Subject: [PATCH backport 5.10 026/100] i2c: mux: Add register map based mux - driver - -Add 'regmap' mux driver to allow virtual bus switching by setting a -single selector register. -The 'regmap' is supposed to be passed to driver within a platform data -by parent platform driver. - -Motivation is to support indirect access to register space where -selector register is located. -For example, Lattice FPGA LFD2NX-40 device, being connected through -PCIe bus provides SPI or LPC bus logic through PCIe-to-SPI or -PCIe-to-LPC bridging. Thus, FPGA operates a as host controller and -some slave devices can be connected to it. For example: -- CPU (PCIe) -> FPGA (PCIe-to-SPI bridge) -> CPLD or another FPGA. -- CPU (PCIe) -> FPGA (PCIe-to-LPC bridge) -> CPLD or another FPGA. -Where 1-st FPGA connected to PCIe is located on carrier board, while -2-nd programming logic device is located on some switch board and -cannot be connected to CPU PCIe root complex. - -In case mux selector register is located within the 2-nd device, SPI or -LPC transactions are sent indirectly through pre-defined protocol. - -To support such protocol reg_read()/reg_write() callbacks are provided -to 'regmap' object and these callback implements required indirect -access. - -For example, flow in reg_write() will be as following: -- Verify there is no pending transactions. -- Set address in PCIe register space. -- Set data to be written in PCIe register space. -- Activate write operation in PCIe register space. -- LPC or SPI write transaction is performed. - -Signed-off-by: Vadim Pasternak ---- - drivers/i2c/muxes/Kconfig | 12 ++ - drivers/i2c/muxes/Makefile | 1 + - drivers/i2c/muxes/i2c-mux-regmap.c | 123 +++++++++++++++++++ - include/linux/platform_data/i2c-mux-regmap.h | 34 +++++ - 4 files changed, 170 insertions(+) - create mode 100644 drivers/i2c/muxes/i2c-mux-regmap.c - create mode 100644 include/linux/platform_data/i2c-mux-regmap.h - -diff --git a/drivers/i2c/muxes/Kconfig b/drivers/i2c/muxes/Kconfig -index 1708b1a82..48becd945 100644 ---- a/drivers/i2c/muxes/Kconfig -+++ b/drivers/i2c/muxes/Kconfig -@@ -99,6 +99,18 @@ config I2C_MUX_REG - This driver can also be built as a module. If so, the module - will be called i2c-mux-reg. - -+config I2C_MUX_REGMAP -+ tristate "Register map based I2C multiplexer" -+ depends on REGMAP -+ help -+ If you say yes to this option, support will be included for a -+ register map based I2C multiplexer. This driver provides access to -+ I2C busses connected through a MUX, which is controlled -+ by a single register through the regmap. -+ -+ This driver can also be built as a module. If so, the module -+ will be called i2c-mux-regmap. -+ - config I2C_DEMUX_PINCTRL - tristate "pinctrl-based I2C demultiplexer" - depends on PINCTRL && OF -diff --git a/drivers/i2c/muxes/Makefile b/drivers/i2c/muxes/Makefile -index 6d9d865e8..092dca428 100644 ---- a/drivers/i2c/muxes/Makefile -+++ b/drivers/i2c/muxes/Makefile -@@ -14,5 +14,6 @@ obj-$(CONFIG_I2C_MUX_PCA9541) += i2c-mux-pca9541.o - obj-$(CONFIG_I2C_MUX_PCA954x) += i2c-mux-pca954x.o - obj-$(CONFIG_I2C_MUX_PINCTRL) += i2c-mux-pinctrl.o - obj-$(CONFIG_I2C_MUX_REG) += i2c-mux-reg.o -+obj-$(CONFIG_I2C_MUX_REGMAP) += i2c-mux-regmap.o - - ccflags-$(CONFIG_I2C_DEBUG_BUS) := -DDEBUG -diff --git a/drivers/i2c/muxes/i2c-mux-regmap.c b/drivers/i2c/muxes/i2c-mux-regmap.c -new file mode 100644 -index 000000000..e155c039a ---- /dev/null -+++ b/drivers/i2c/muxes/i2c-mux-regmap.c -@@ -0,0 +1,123 @@ -+// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 -+/* -+ * Regmap i2c mux driver -+ * -+ * Copyright (C) 2023 Nvidia Technologies Ltd. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* i2c_mux_regmap - mux control structure: -+ * @last_val - last selected register value or -1 if mux deselected; -+ * @pdata: platform data; -+ */ -+struct i2c_mux_regmap { -+ int last_val; -+ struct i2c_mux_regmap_platform_data pdata; -+}; -+ -+static int i2c_mux_regmap_select_chan(struct i2c_mux_core *muxc, u32 chan) -+{ -+ struct i2c_mux_regmap *mux = i2c_mux_priv(muxc); -+ int err = 0; -+ -+ /* Only select the channel if its different from the last channel */ -+ if (mux->last_val != chan) { -+ err = regmap_write(mux->pdata.regmap, mux->pdata.sel_reg_addr, chan); -+ mux->last_val = err < 0 ? -1 : chan; -+ } -+ -+ return err; -+} -+ -+static int i2c_mux_regmap_deselect(struct i2c_mux_core *muxc, u32 chan) -+{ -+ struct i2c_mux_regmap *mux = i2c_mux_priv(muxc); -+ -+ /* Deselect active channel */ -+ mux->last_val = -1; -+ -+ return regmap_write(mux->pdata.regmap, mux->pdata.sel_reg_addr, 0); -+} -+ -+/* Probe/reomove functions */ -+static int i2c_mux_regmap_probe(struct platform_device *pdev) -+{ -+ struct i2c_mux_regmap_platform_data *pdata = dev_get_platdata(&pdev->dev); -+ struct i2c_mux_regmap *mux; -+ struct i2c_adapter *parent; -+ struct i2c_mux_core *muxc; -+ int num, err; -+ -+ if (!pdata) -+ return -EINVAL; -+ -+ mux = devm_kzalloc(&pdev->dev, sizeof(*mux), GFP_KERNEL); -+ if (!mux) -+ return -ENOMEM; -+ -+ memcpy(&mux->pdata, pdata, sizeof(*pdata)); -+ parent = i2c_get_adapter(mux->pdata.parent); -+ if (!parent) -+ return -EPROBE_DEFER; -+ -+ muxc = i2c_mux_alloc(parent, &pdev->dev, pdata->num_adaps, sizeof(*mux), 0, -+ i2c_mux_regmap_select_chan, i2c_mux_regmap_deselect); -+ if (!muxc) -+ return -ENOMEM; -+ -+ platform_set_drvdata(pdev, muxc); -+ muxc->priv = mux; -+ mux->last_val = -1; /* force the first selection */ -+ -+ /* Create an adapter for each channel. */ -+ for (num = 0; num < pdata->num_adaps; num++) { -+ err = i2c_mux_add_adapter(muxc, 0, pdata->chan_ids[num], 0); -+ if (err) -+ goto err_i2c_mux_add_adapter; -+ } -+ -+ /* Notify caller when all channels' adapters are created. */ -+ if (pdata->completion_notify) -+ pdata->completion_notify(pdata->handle, muxc->parent, muxc->adapter); -+ -+ return 0; -+ -+err_i2c_mux_add_adapter: -+ i2c_mux_del_adapters(muxc); -+ return err; -+} -+ -+static int i2c_mux_regmap_remove(struct platform_device *pdev) -+{ -+ struct i2c_mux_core *muxc = platform_get_drvdata(pdev); -+ -+ i2c_mux_del_adapters(muxc); -+ i2c_put_adapter(muxc->parent); -+ -+ return 0; -+} -+ -+static struct platform_driver i2c_mux_regmap_driver = { -+ .driver = { -+ .name = "i2c-mux-regmap", -+ }, -+ .probe = i2c_mux_regmap_probe, -+ .remove = i2c_mux_regmap_remove, -+}; -+ -+module_platform_driver(i2c_mux_regmap_driver); -+ -+MODULE_AUTHOR("Vadim Pasternak (vadimp@nvidia.com)"); -+MODULE_DESCRIPTION("Regmap I2C multiplexer driver"); -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_ALIAS("platform:i2c-mux-regmap"); -diff --git a/include/linux/platform_data/i2c-mux-regmap.h b/include/linux/platform_data/i2c-mux-regmap.h -new file mode 100644 -index 000000000..a06614e5e ---- /dev/null -+++ b/include/linux/platform_data/i2c-mux-regmap.h -@@ -0,0 +1,34 @@ -+/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ -+/* -+ * Regmap i2c mux driver -+ * -+ * Copyright (C) 2023 Nvidia Technologies Ltd. -+ */ -+ -+#ifndef __LINUX_PLATFORM_DATA_I2C_MUX_REGMAP_H -+#define __LINUX_PLATFORM_DATA_I2C_MUX_REGMAP_H -+ -+/** -+ * struct i2c_mux_regmap_platform_data - Platform-dependent data for i2c-mux-regmap -+ * @regmap: register map of parent device; -+ * @parent: Parent I2C bus adapter number -+ * @chan_ids - channels array -+ * @num_adaps - number of adapters -+ * @sel_reg_addr - mux select register offset in CPLD space -+ * @reg_size: register size in bytes -+ * @handle: handle to be passed by callback -+ * @completion_notify: callback to notify when all the adapters are created -+ */ -+struct i2c_mux_regmap_platform_data { -+ void *regmap; -+ int parent; -+ const unsigned int *chan_ids; -+ int num_adaps; -+ int sel_reg_addr; -+ u8 reg_size; -+ void *handle; -+ int (*completion_notify)(void *handle, struct i2c_adapter *parent, -+ struct i2c_adapter *adapters[]); -+}; -+ -+#endif /* __LINUX_PLATFORM_DATA_I2C_MUX_REGMAP_H */ --- -2.20.1 - diff --git a/platform/mellanox/non-upstream-patches/patches/0189-i2c-mlxcpld-Allow-driver-to-run-on-ARM64-architectur.patch b/platform/mellanox/non-upstream-patches/patches/0189-i2c-mlxcpld-Allow-driver-to-run-on-ARM64-architectur.patch deleted file mode 100644 index b5c0e006e3de..000000000000 --- a/platform/mellanox/non-upstream-patches/patches/0189-i2c-mlxcpld-Allow-driver-to-run-on-ARM64-architectur.patch +++ /dev/null @@ -1,29 +0,0 @@ -From c4d1a7d7f51a8315f727c9210961ed93b922d440 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Mon, 7 Nov 2022 12:00:37 +0200 -Subject: [PATCH backport 5.10 03/10] i2c: mlxcpld: Allow driver to run on - ARM64 architecture - -Extend driver dependency by ARM64 architecture. - -Signed-off-by: Vadim Pasternak ---- - drivers/i2c/busses/Kconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig -index 7e693dcbd..c984305ee 100644 ---- a/drivers/i2c/busses/Kconfig -+++ b/drivers/i2c/busses/Kconfig -@@ -1328,7 +1328,7 @@ config I2C_ICY - - config I2C_MLXCPLD - tristate "Mellanox I2C driver" -- depends on X86_64 || COMPILE_TEST -+ depends on X86_64 || ARM64 || COMPILE_TEST - help - This exposes the Mellanox platform I2C busses to the linux I2C layer - for X86 based systems. --- -2.20.1 - diff --git a/platform/mellanox/non-upstream-patches/patches/0190-i2c-mlxcpld-Modify-base-address-type.patch b/platform/mellanox/non-upstream-patches/patches/0190-i2c-mlxcpld-Modify-base-address-type.patch deleted file mode 100644 index 36c3178e6ce2..000000000000 --- a/platform/mellanox/non-upstream-patches/patches/0190-i2c-mlxcpld-Modify-base-address-type.patch +++ /dev/null @@ -1,49 +0,0 @@ -From d2130ff4d3aed72611f07213e9eceeb084f0fc65 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Wed, 9 Nov 2022 10:29:22 +0200 -Subject: [PATCH backport 5.10 04/10] i2c: mlxcpld: Modify base address type - -Change type of base address from 'u32' to 'u64'. - -Motivation is to support memory mapped virtual base address on ARM64 -architecture. - -Signed-off-by: Vadim Pasternak ---- - drivers/i2c/busses/i2c-mlxcpld.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - -diff --git a/drivers/i2c/busses/i2c-mlxcpld.c b/drivers/i2c/busses/i2c-mlxcpld.c -index 72fcfb17d..57aea396c 100644 ---- a/drivers/i2c/busses/i2c-mlxcpld.c -+++ b/drivers/i2c/busses/i2c-mlxcpld.c -@@ -68,7 +68,7 @@ struct mlxcpld_i2c_curr_xfer { - - struct mlxcpld_i2c_priv { - struct i2c_adapter adap; -- u32 base_addr; -+ u64 base_addr; - struct mutex lock; - struct mlxcpld_i2c_curr_xfer xfer; - struct device *dev; -@@ -99,7 +99,7 @@ static void mlxcpld_i2c_lpc_read_buf(u8 *data, u8 len, u32 addr) - static void mlxcpld_i2c_read_comm(struct mlxcpld_i2c_priv *priv, u8 offs, - u8 *data, u8 datalen) - { -- u32 addr = priv->base_addr + offs; -+ u64 addr = priv->base_addr + offs; - - switch (datalen) { - case 1: -@@ -124,7 +124,7 @@ static void mlxcpld_i2c_read_comm(struct mlxcpld_i2c_priv *priv, u8 offs, - static void mlxcpld_i2c_write_comm(struct mlxcpld_i2c_priv *priv, u8 offs, - u8 *data, u8 datalen) - { -- u32 addr = priv->base_addr + offs; -+ u64 addr = priv->base_addr + offs; - - switch (datalen) { - case 1: --- -2.20.1 - diff --git a/platform/mellanox/non-upstream-patches/patches/0191-i2c-mlxcpld-Allow-to-configure-base-address-of-regis.patch b/platform/mellanox/non-upstream-patches/patches/0191-i2c-mlxcpld-Allow-to-configure-base-address-of-regis.patch deleted file mode 100644 index 245bcaa4f1bc..000000000000 --- a/platform/mellanox/non-upstream-patches/patches/0191-i2c-mlxcpld-Allow-to-configure-base-address-of-regis.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 0fcfc9b2eb7f071f3aa64845d262f1e8e4f741e7 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Wed, 9 Nov 2022 10:35:58 +0200 -Subject: [PATCH backport 5.10 05/10] i2c: mlxcpld: Allow to configure base - address of register space - -Allow to use configured base address. - -Currently driver uses constant base address of register space. -On new systems this base address could be different, thus it could be -passed to the driver through platform data. - -Signed-off-by: Vadim Pasternak ---- - drivers/i2c/busses/i2c-mlxcpld.c | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/drivers/i2c/busses/i2c-mlxcpld.c b/drivers/i2c/busses/i2c-mlxcpld.c -index 57aea396c..cd5401ce4 100644 ---- a/drivers/i2c/busses/i2c-mlxcpld.c -+++ b/drivers/i2c/busses/i2c-mlxcpld.c -@@ -538,6 +538,9 @@ static int mlxcpld_i2c_probe(struct platform_device *pdev) - err = mlxcpld_i2c_set_frequency(priv, pdata); - if (err) - goto mlxcpld_i2_probe_failed; -+ -+ if (pdata->addr) -+ priv->base_addr = (*(u64 __force *)pdata->addr); - } - - /* Register with i2c layer */ --- -2.20.1 - diff --git a/platform/mellanox/non-upstream-patches/patches/0192-i2c-mlxcpld-Add-support-for-extended-transaction-len.patch b/platform/mellanox/non-upstream-patches/patches/0192-i2c-mlxcpld-Add-support-for-extended-transaction-len.patch deleted file mode 100644 index 282ef9312999..000000000000 --- a/platform/mellanox/non-upstream-patches/patches/0192-i2c-mlxcpld-Add-support-for-extended-transaction-len.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 22447625fff0e742b3dc9c2f78bbaac29b1f1031 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Sun, 27 Nov 2022 10:43:23 +0200 -Subject: [PATCH backport 5.10 06/10] i2c: mlxcpld: Add support for extended - transaction length for i2c-mlxcpld - -Add support for extended length of read and write transactions. -New FPGA logic allows to increase size of the read and write -transactions length. This feature is verified through capability -register 'CPBLTY_REG'. Two bits 5 and 6 of the register are used for -length capability detection. Value '10' indicates support of extended -transaction length - 128 bytes for read transactions and 132 for write -transactions. - -Signed-off-by: Vadim Pasternak ---- - drivers/i2c/busses/i2c-mlxcpld.c | 10 ++++++++++ - 1 file changed, 10 insertions(+) - -diff --git a/drivers/i2c/busses/i2c-mlxcpld.c b/drivers/i2c/busses/i2c-mlxcpld.c -index cd5401ce4..0e1807be7 100644 ---- a/drivers/i2c/busses/i2c-mlxcpld.c -+++ b/drivers/i2c/busses/i2c-mlxcpld.c -@@ -22,6 +22,7 @@ - #define MLXCPLD_I2C_BUS_NUM 1 - #define MLXCPLD_I2C_DATA_REG_SZ 36 - #define MLXCPLD_I2C_DATA_SZ_BIT BIT(5) -+#define MLXCPLD_I2C_DATA_EXT2_SZ_BIT BIT(6) - #define MLXCPLD_I2C_DATA_SZ_MASK GENMASK(6, 5) - #define MLXCPLD_I2C_SMBUS_BLK_BIT BIT(7) - #define MLXCPLD_I2C_MAX_ADDR_LEN 4 -@@ -466,6 +467,13 @@ static const struct i2c_adapter_quirks mlxcpld_i2c_quirks_ext = { - .max_comb_1st_msg_len = 4, - }; - -+static const struct i2c_adapter_quirks mlxcpld_i2c_quirks_ext2 = { -+ .flags = I2C_AQ_COMB_WRITE_THEN_READ, -+ .max_read_len = (MLXCPLD_I2C_DATA_REG_SZ - 4) * 4, -+ .max_write_len = (MLXCPLD_I2C_DATA_REG_SZ - 4) * 4 + MLXCPLD_I2C_MAX_ADDR_LEN, -+ .max_comb_1st_msg_len = 4, -+}; -+ - static struct i2c_adapter mlxcpld_i2c_adapter = { - .owner = THIS_MODULE, - .name = "i2c-mlxcpld", -@@ -550,6 +558,8 @@ static int mlxcpld_i2c_probe(struct platform_device *pdev) - /* Check support for extended transaction length */ - if ((val & MLXCPLD_I2C_DATA_SZ_MASK) == MLXCPLD_I2C_DATA_SZ_BIT) - mlxcpld_i2c_adapter.quirks = &mlxcpld_i2c_quirks_ext; -+ else if ((val & MLXCPLD_I2C_DATA_SZ_MASK) == MLXCPLD_I2C_DATA_EXT2_SZ_BIT) -+ mlxcpld_i2c_adapter.quirks = &mlxcpld_i2c_quirks_ext2; - /* Check support for smbus block transaction */ - if (val & MLXCPLD_I2C_SMBUS_BLK_BIT) - priv->smbus_block = true; --- -2.20.1 - diff --git a/platform/mellanox/non-upstream-patches/patches/0193-platform-mellanox-mlx-platform-Add-mux-selection-reg.patch b/platform/mellanox/non-upstream-patches/patches/0193-platform-mellanox-mlx-platform-Add-mux-selection-reg.patch deleted file mode 100644 index 79a4cafb6895..000000000000 --- a/platform/mellanox/non-upstream-patches/patches/0193-platform-mellanox-mlx-platform-Add-mux-selection-reg.patch +++ /dev/null @@ -1,99 +0,0 @@ -From e1d377039ba9a364f4e7f9816f5f0b7a3b165b43 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Wed, 18 Jan 2023 15:08:46 +0200 -Subject: [PATCH backport 5.10 07/10] platform: mellanox: mlx-platform: Add mux - selection register to regmap -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Extend writeable, readable, volatile registers of the 'regmap' object -with for I2C mux selector registers. - -The motivation is to pass this object extended with selector registers -to I2C mux driver working over ‘regmap’. - -Signed-off-by: Vadim Pasternak ---- - drivers/platform/x86/mlx-platform.c | 28 ++++++++++++++++++++-------- - 1 file changed, 20 insertions(+), 8 deletions(-) - -diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c -index e8c656d6e..03c744f37 100644 ---- a/drivers/platform/x86/mlx-platform.c -+++ b/drivers/platform/x86/mlx-platform.c -@@ -140,6 +140,10 @@ - #define MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET 0xd2 - #define MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET 0xd3 - #define MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET 0xd9 -+#define MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET 0xdb -+#define MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET 0xda -+#define MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET 0xdc -+#define MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET 0xdd - #define MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET 0xde - #define MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET 0xdf - #define MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET 0xe0 -@@ -173,23 +177,19 @@ - #define MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET 0xfc - #define MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET 0xfd - #define MLXPLAT_CPLD_LPC_IO_RANGE 0x100 --#define MLXPLAT_CPLD_LPC_I2C_CH1_OFF 0xdb --#define MLXPLAT_CPLD_LPC_I2C_CH2_OFF 0xda --#define MLXPLAT_CPLD_LPC_I2C_CH3_OFF 0xdc --#define MLXPLAT_CPLD_LPC_I2C_CH4_OFF 0xdd - - #define MLXPLAT_CPLD_LPC_PIO_OFFSET 0x10000UL - #define MLXPLAT_CPLD_LPC_REG1 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ -- MLXPLAT_CPLD_LPC_I2C_CH1_OFF) | \ -+ MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET) | \ - MLXPLAT_CPLD_LPC_PIO_OFFSET) - #define MLXPLAT_CPLD_LPC_REG2 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ -- MLXPLAT_CPLD_LPC_I2C_CH2_OFF) | \ -+ MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET) | \ - MLXPLAT_CPLD_LPC_PIO_OFFSET) - #define MLXPLAT_CPLD_LPC_REG3 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ -- MLXPLAT_CPLD_LPC_I2C_CH3_OFF) | \ -+ MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET) | \ - MLXPLAT_CPLD_LPC_PIO_OFFSET) - #define MLXPLAT_CPLD_LPC_REG4 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \ -- MLXPLAT_CPLD_LPC_I2C_CH4_OFF) | \ -+ MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET) | \ - MLXPLAT_CPLD_LPC_PIO_OFFSET) - - /* Masks for aggregation, psu, pwr and fan event in CPLD related registers. */ -@@ -5307,6 +5307,10 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET: -@@ -5434,6 +5438,10 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET: -@@ -5581,6 +5589,10 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: - case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: - case MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET: --- -2.20.1 - diff --git a/platform/mellanox/non-upstream-patches/patches/0194-platform-mellanox-mlx-platform-Move-bus-shift-assign.patch b/platform/mellanox/non-upstream-patches/patches/0194-platform-mellanox-mlx-platform-Move-bus-shift-assign.patch deleted file mode 100644 index 154f02d705d6..000000000000 --- a/platform/mellanox/non-upstream-patches/patches/0194-platform-mellanox-mlx-platform-Move-bus-shift-assign.patch +++ /dev/null @@ -1,35 +0,0 @@ -From deb8517499160d77e94b2969a98b3c01bed1a649 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Wed, 18 Jan 2023 15:25:37 +0200 -Subject: [PATCH backport 5.10 082/150] platform: mellanox: mlx-platform: Move - bus shift assignment out of the loop - -Move assignment of bus shift setting out of the loop to avoid redundant -operation. - -Signed-off-by: Vadim Pasternak ---- - drivers/platform/x86/mlx-platform.c | 5 +++-- - 1 file changed, 3 insertions(+), 2 deletions(-) - -diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c -index de8fd0886..9d4cab937 100644 ---- a/drivers/platform/x86/mlx-platform.c -+++ b/drivers/platform/x86/mlx-platform.c -@@ -6371,10 +6371,11 @@ static int mlxplat_mlxcpld_verify_bus_topology(int *nr) - shift = *nr - mlxplat_mux_data[i].parent; - mlxplat_mux_data[i].parent = *nr; - mlxplat_mux_data[i].base_nr += shift; -- if (shift > 0) -- mlxplat_hotplug->shift_nr = shift; - } - -+ if (shift > 0) -+ mlxplat_hotplug->shift_nr = shift; -+ - return 0; - } - --- -2.20.1 - diff --git a/platform/mellanox/non-upstream-patches/patches/0195-platform-mellanox-Add-support-for-dynamic-I2C-channe.patch b/platform/mellanox/non-upstream-patches/patches/0195-platform-mellanox-Add-support-for-dynamic-I2C-channe.patch deleted file mode 100644 index fa24430325fd..000000000000 --- a/platform/mellanox/non-upstream-patches/patches/0195-platform-mellanox-Add-support-for-dynamic-I2C-channe.patch +++ /dev/null @@ -1,158 +0,0 @@ -From d1fbdc9c5bd0939362ebdb4d76a701cb938f3837 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Wed, 18 Jan 2023 19:12:12 +0200 -Subject: [PATCH backport 5.10 083/150] platform/mellanox: Add support for - dynamic I2C channels infrastructure - -Allow to support platform configuration for dynamically allocated I2C -channels. -Motivation is to support I2C channels allocated in a non-continuous -way. - -Currently hotplug platform driver data structure contains static mux -channels for I2C hotplug devices. These channels numbers can be updated -dynamically and returned by mux driver's callback through the adapters -array. -Thus, hotplug mux channels will be aligned according to the dynamic -adapters data. - -Signed-off-by: Vadim Pasternak ---- - drivers/platform/x86/mlx-platform.c | 69 ++++++++++++++++++++++++----- - 1 file changed, 59 insertions(+), 10 deletions(-) - -diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c -index 9d4cab937..773d110c9 100644 ---- a/drivers/platform/x86/mlx-platform.c -+++ b/drivers/platform/x86/mlx-platform.c -@@ -14,6 +14,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -336,6 +337,7 @@ - * @hotplug_resources: system hotplug resources - * @hotplug_resources_size: size of system hotplug resources - * @hi2c_main_init_status: init status of I2C main bus -+ * @mux_added: number of added mux segments - */ - struct mlxplat_priv { - struct platform_device *pdev_i2c; -@@ -349,6 +351,7 @@ struct mlxplat_priv { - struct resource *hotplug_resources; - unsigned int hotplug_resources_size; - u8 i2c_main_init_status; -+ int mux_added; - }; - - static struct platform_device *mlxplat_dev; -@@ -436,7 +439,9 @@ static struct i2c_mux_reg_platform_data mlxplat_default_mux_data[] = { - /* Platform mux configuration variables */ - static int mlxplat_max_adap_num; - static int mlxplat_mux_num; -+static int mlxplat_mux_hotplug_num; - static struct i2c_mux_reg_platform_data *mlxplat_mux_data; -+static struct i2c_mux_regmap_platform_data *mlxplat_mux_regmap_data; - - /* Platform extended mux data */ - static struct i2c_mux_reg_platform_data mlxplat_extended_mux_data[] = { -@@ -6368,12 +6373,17 @@ static int mlxplat_mlxcpld_verify_bus_topology(int *nr) - /* Shift adapter ids, since expected parent adapter is not free. */ - *nr = i; - for (i = 0; i < mlxplat_mux_num; i++) { -- shift = *nr - mlxplat_mux_data[i].parent; -- mlxplat_mux_data[i].parent = *nr; -- mlxplat_mux_data[i].base_nr += shift; -+ if (mlxplat_mux_data) { -+ shift = *nr - mlxplat_mux_data[i].parent; -+ mlxplat_mux_data[i].parent = *nr; -+ mlxplat_mux_data[i].base_nr += shift; -+ } else if (mlxplat_mux_regmap_data) { -+ mlxplat_mux_regmap_data[i].parent = *nr; -+ } - } - -- if (shift > 0) -+ /* Shift bus only if mux provided by 'mlxplat_mux_data'. */ -+ if (shift > 0 && mlxplat_mux_data) - mlxplat_hotplug->shift_nr = shift; - - return 0; -@@ -6563,8 +6573,31 @@ mlxplat_i2c_mux_complition_notify(void *handle, struct i2c_adapter *parent, - struct i2c_adapter *adapters[]) - { - struct mlxplat_priv *priv = handle; -+ struct mlxreg_core_item *item; -+ int i, j; -+ -+ /* -+ * Hotplug platform driver data structure contains static mux channels for I2C hotplug -+ * devices. These channels numbers can be updated dynamically and returned by mux callback -+ * through the adapters array. Update mux channels according to the dynamic adapters data. -+ */ -+ if (priv->mux_added == mlxplat_mux_hotplug_num) { -+ item = mlxplat_hotplug->items; -+ for (i = 0; i < mlxplat_hotplug->counter; i++, item++) { -+ struct mlxreg_core_data *data = item->data; -+ -+ for (j = 0; j < item->count; j++, data++) { -+ if (data->hpdev.nr != MLXPLAT_CPLD_NR_NONE) -+ data->hpdev.nr = adapters[data->hpdev.nr - 2]->nr; -+ } -+ } -+ } - -- return mlxplat_post_init(priv); -+ /* Start post initialization only after last nux segment is added */ -+ if (++priv->mux_added == mlxplat_mux_num) -+ return mlxplat_post_init(priv); -+ -+ return 0; - } - - static int mlxplat_i2c_mux_topolgy_init(struct mlxplat_priv *priv) -@@ -6578,17 +6611,33 @@ static int mlxplat_i2c_mux_topolgy_init(struct mlxplat_priv *priv) - - priv->i2c_main_init_status = MLXPLAT_I2C_MAIN_BUS_HANDLE_CREATED; - for (i = 0; i < mlxplat_mux_num; i++) { -- priv->pdev_mux[i] = platform_device_register_resndata(&priv->pdev_i2c->dev, -- "i2c-mux-reg", i, NULL, 0, -- &mlxplat_mux_data[i], -- sizeof(mlxplat_mux_data[i])); -+ if (mlxplat_mux_data) { -+ priv->pdev_mux[i] = -+ platform_device_register_resndata(&priv->pdev_i2c->dev, -+ "i2c-mux-reg", i, NULL, 0, -+ &mlxplat_mux_data[i], -+ sizeof(mlxplat_mux_data[i])); -+ } else { -+ mlxplat_mux_regmap_data[i].handle = priv; -+ mlxplat_mux_regmap_data[i].regmap = priv->regmap; -+ mlxplat_mux_regmap_data[i].completion_notify = -+ mlxplat_i2c_mux_complition_notify; -+ priv->pdev_mux[i] = -+ platform_device_register_resndata(&priv->pdev_i2c->dev, -+ "i2c-mux-regmap", i, NULL, 0, -+ &mlxplat_mux_regmap_data[i], -+ sizeof(mlxplat_mux_regmap_data[i])); -+ } - if (IS_ERR(priv->pdev_mux[i])) { - err = PTR_ERR(priv->pdev_mux[i]); - goto fail_platform_mux_register; - } - } - -- return mlxplat_i2c_mux_complition_notify(priv, NULL, NULL); -+ if (mlxplat_mux_regmap_data && mlxplat_mux_regmap_data->completion_notify) -+ return 0; -+ -+ return mlxplat_post_init(priv); - - fail_platform_mux_register: - while (--i >= 0) --- -2.20.1 - diff --git a/platform/mellanox/non-upstream-patches/patches/0197-platform-mellanox-Add-initial-support-for-PCIe-based.patch b/platform/mellanox/non-upstream-patches/patches/0197-platform-mellanox-Add-initial-support-for-PCIe-based.patch deleted file mode 100644 index ae18a952d79a..000000000000 --- a/platform/mellanox/non-upstream-patches/patches/0197-platform-mellanox-Add-initial-support-for-PCIe-based.patch +++ /dev/null @@ -1,186 +0,0 @@ -From e831f971fd9895b74c0966b3cf3cd2e18c2f8fca Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Thu, 10 Nov 2022 08:53:49 +0200 -Subject: [PATCH backport 5.10 085/150] platform: mellanox: Add initial support - for PCIe based programming logic device - -Extend driver to support logic implemented by FPGA device connected -through PCIe bus. - -The motivation two support new generation of Nvidia COME module, based -on ARM64 architecture, and equipped with Lattice LFD2NX-40 FPGA device. - -In order to support new Nvidia COME module FPGA device driver -initialization flow is modified. In case FPGA device is detected, -system resources are to be mapped to this device, otherwise system -resources are to be mapped same as it has been done before for Lattice -LPC based CPLD. - -Signed-off-by: Vadim Pasternak ---- - drivers/platform/mellanox/mlx-platform.c | 106 ++++++++++++++++++++++- - 1 file changed, 105 insertions(+), 1 deletion(-) - -diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c -index 773d110c9..f3df56c41 100644 ---- a/drivers/platform/mellanox/mlx-platform.c -+++ b/drivers/platform/mellanox/mlx-platform.c -@@ -12,6 +12,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -315,6 +316,7 @@ - #define MLXPLAT_CPLD_WD_MAX_DEVS 2 - - #define MLXPLAT_CPLD_LPC_SYSIRQ 17 -+#define MLXPLAT_FPGA_PCIE_SYSIRQ 17 - - /* Minimum power required for turning on Ethernet modular system (WATT) */ - #define MLXPLAT_CPLD_ETH_MODULAR_PWR_MIN 50 -@@ -325,6 +327,11 @@ - #define MLXPLAT_I2C_MAIN_BUS_NOTIFIED 0x01 - #define MLXPLAT_I2C_MAIN_BUS_HANDLE_CREATED 0x02 - -+/* Lattice FPGA PCI configuration */ -+#define PCI_VENDOR_ID_LATTICE 0x1204 -+#define PCI_DEVICE_ID_LATTICE_LFD2NX40 0x9c1d -+#define MLXPLAT_FPGA_PCI_BAR0_SIZE 0x4000 -+ - /* mlxplat_priv - platform private data - * @pdev_i2c - i2c controller platform device - * @pdev_mux - array of mux platform devices -@@ -5793,6 +5800,11 @@ static struct resource mlxplat_mlxcpld_resources[] = { - [0] = DEFINE_RES_IRQ_NAMED(MLXPLAT_CPLD_LPC_SYSIRQ, "mlxreg-hotplug"), - }; - -+static struct resource mlxplat_mlxfpga_resources[] = { -+ [0] = DEFINE_RES_IRQ_NAMED(MLXPLAT_FPGA_PCIE_SYSIRQ, "mlxreg-hotplug"), -+}; -+ -+static struct platform_device *mlxplat_dev; - static struct mlxreg_core_hotplug_platform_data *mlxplat_i2c; - static struct mlxreg_core_hotplug_platform_data *mlxplat_hotplug; - static struct mlxreg_core_platform_data *mlxplat_led; -@@ -5802,6 +5814,7 @@ static struct mlxreg_core_platform_data - *mlxplat_wd_data[MLXPLAT_CPLD_WD_MAX_DEVS]; - static const struct regmap_config *mlxplat_regmap_config; - static struct spi_board_info *mlxplat_spi; -+static struct pci_dev *fpga_dev; - - /* Platform default poweroff function */ - static void mlxplat_poweroff(void) -@@ -6443,15 +6456,106 @@ static void mlxplat_lpc_cpld_device_exit(void) - platform_device_unregister(mlxplat_dev); - } - -+static int -+mlxplat_pci_fpga_device_init(struct resource **hotplug_resources, -+ unsigned int *hotplug_resources_size, struct pci_dev **fpga_dev) -+{ -+ struct pci_dev *pci_dev; -+ int err; -+ -+ pci_dev = pci_get_device(PCI_VENDOR_ID_LATTICE, PCI_DEVICE_ID_LATTICE_LFD2NX40, NULL); -+ if (!pci_dev) -+ return -ENODEV; -+ -+ err = pci_enable_device(pci_dev); -+ if (err) { -+ dev_err(&mlxplat_dev->dev, "pci_enable_device failed\n"); -+ goto fail_pci_enable_device; -+ } -+ -+ err = pci_request_regions(pci_dev, "mlx-patform"); -+ if (err) { -+ dev_err(&mlxplat_dev->dev, "pci_request_regions failed\n"); -+ goto fail_pci_request_regions; -+ } -+ -+ err = dma_set_mask_and_coherent(&mlxplat_dev->dev, DMA_BIT_MASK(64)); -+ if (err) { -+ err = dma_set_mask(&mlxplat_dev->dev, DMA_BIT_MASK(32)); -+ if (err) { -+ dev_err(&mlxplat_dev->dev, "dma_set_mask failed\n"); -+ goto fail_pci_set_dma_mask; -+ } -+ } -+ -+ if (pci_resource_len(pci_dev, 0) < MLXPLAT_FPGA_PCI_BAR0_SIZE) { -+ dev_err(&mlxplat_dev->dev, "invalid PCI region size\n"); -+ err = -EINVAL; -+ goto fail_pci_resource_len_check; -+ } -+ -+ mlxplat_mlxcpld_regmap_ctx.base = devm_ioremap(&mlxplat_dev->dev, -+ pci_resource_start(pci_dev, 0), -+ pci_resource_len(pci_dev, 0)); -+ if (!mlxplat_mlxcpld_regmap_ctx.base) { -+ dev_err(&mlxplat_dev->dev, "ioremap failed\n"); -+ err = -EIO; -+ goto fail_ioremap; -+ } -+ pci_set_master(pci_dev); -+ -+ mlxplat_dev = platform_device_register_simple(MLX_PLAT_DEVICE_NAME, PLATFORM_DEVID_NONE, -+ NULL, 0); -+ if (IS_ERR(mlxplat_dev)) { -+ err = PTR_ERR(mlxplat_dev); -+ goto fail_platform_device_register_simple; -+ } -+ -+ *hotplug_resources = mlxplat_mlxfpga_resources; -+ *hotplug_resources_size = ARRAY_SIZE(mlxplat_mlxfpga_resources); -+ *fpga_dev = pci_dev; -+ -+ return 0; -+ -+fail_platform_device_register_simple: -+fail_ioremap: -+fail_pci_resource_len_check: -+fail_pci_set_dma_mask: -+ pci_release_regions(pci_dev); -+fail_pci_request_regions: -+ pci_disable_device(pci_dev); -+fail_pci_enable_device: -+ return err; -+} -+ -+static void mlxplat_pci_fpga_device_exit(void) -+{ -+ platform_device_unregister(mlxplat_dev); -+ iounmap(mlxplat_mlxcpld_regmap_ctx.base); -+ pci_release_regions(fpga_dev); -+ pci_disable_device(fpga_dev); -+} -+ - static int - mlxplat_pre_init(struct resource **hotplug_resources, unsigned int *hotplug_resources_size) - { -+ int err; -+ -+ err = mlxplat_pci_fpga_device_init(hotplug_resources, hotplug_resources_size, &fpga_dev); -+ if (!err) -+ return 0; -+ else if (err != -ENODEV) -+ return err; -+ - return mlxplat_lpc_cpld_device_init(hotplug_resources, hotplug_resources_size); - } - - static void mlxplat_post_exit(void) - { -- mlxplat_lpc_cpld_device_exit(); -+ if (fpga_dev) -+ mlxplat_pci_fpga_device_exit(); -+ else -+ mlxplat_lpc_cpld_device_exit(); - } - - static int mlxplat_post_init(struct mlxplat_priv *priv) --- -2.20.1 - diff --git a/platform/mellanox/non-upstream-patches/patches/0198-platform-mellanox-Introduce-support-for-switches-bas.patch b/platform/mellanox/non-upstream-patches/patches/0198-platform-mellanox-Introduce-support-for-switches-bas.patch deleted file mode 100644 index 1c24c54d6faf..000000000000 --- a/platform/mellanox/non-upstream-patches/patches/0198-platform-mellanox-Introduce-support-for-switches-bas.patch +++ /dev/null @@ -1,253 +0,0 @@ -From bcdfc7d1d106889fa9af3404f252fb1260f5a0fd Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Tue, 15 Nov 2022 11:51:47 +0200 -Subject: [PATCH backport 5.10 086/150] platform: mellanox: Introduce support - for switches based on BlueField-3/ARM64 COMe -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add support for Nvidia MQM97xx family switches providing a -high-performance solution by delivering high bandwidth with low latency -to Enterprise Data Centers. - -These switches are based on previous generation of MQM97xx switches, -excepting CFL based COMe module is replaced by new BlueField®-3 COMe -module. - -Switches of this class are equipped with: -- Nvidia Quantum™-2 ASIC, providing up to 64x400GB/s (IB) full - bidirectional bandwidth per port using PAM-4 modulation. -- Com-Express type 7 module, based on Nvidia NVIDIA® BlueField®-3 - processing unit and equipped with LATTICE LFD2NX40 Certus™-NX FPGA - secured device with fail safe - mechanism, connected by PCIe bus. -- Switch board with two Lattice LCMXO3D-9400HC secured with fail safe - mechanism, connected by PCEi-to-LPC bridge. -- Fan board to supporting 7 fans. -- 2x power extender boards. -- 7x FRU fans. -- 2x 2000W AC/DC PSU (FRU). - -New switches platform configuration is based on the new VMOD0016 -class. Configuration is extended to support new register map with -callbacks supporting indirect addressing for PCIe-to-LPC bridge. -This bridge provides interface between FPAG at COMe board (directly -connected to CPU PCIe root complex) to CPLDs on switch board (which -cannot be connected directly to PCIe root complex). - -Signed-off-by: Vadim Pasternak ---- - drivers/platform/mellanox/mlx-platform.c | 147 ++++++++++++++++++++++- - 1 file changed, 146 insertions(+), 1 deletion(-) - -diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c -index f3df56c41..b1c8632d6 100644 ---- a/drivers/platform/mellanox/mlx-platform.c -+++ b/drivers/platform/mellanox/mlx-platform.c -@@ -270,6 +270,7 @@ - /* Maximum number of possible physical buses equipped on system */ - #define MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM 16 - #define MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM 24 -+#define MLXPLAT_CPLD_DEFAULT_MUX_HOTPLUG_VECTOR 0 - - /* Number of channels in group */ - #define MLXPLAT_CPLD_GRP_CHNL_NUM 8 -@@ -331,6 +332,17 @@ - #define PCI_VENDOR_ID_LATTICE 0x1204 - #define PCI_DEVICE_ID_LATTICE_LFD2NX40 0x9c1d - #define MLXPLAT_FPGA_PCI_BAR0_SIZE 0x4000 -+#define MLXPLAT_FPGA_PCI_BASE_OFFSET 0x00000000 -+#define MLXPLAT_FPGA_PCI_ADDR_OFFSET MLXPLAT_FPGA_PCI_BASE_OFFSET -+#define MLXPLAT_FPGA_PCI_DATA_OFFSET (MLXPLAT_FPGA_PCI_BASE_OFFSET + 0x02) -+#define MLXPLAT_FPGA_PCI_CTRL_OFFSET (MLXPLAT_FPGA_PCI_BASE_OFFSET + 0x04) -+#define MLXPLAT_FPGA_PCI_STAT_OFFSET (MLXPLAT_FPGA_PCI_BASE_OFFSET + 0x06) -+#define MLXPLAT_FPGA_PCI_I2C_LPC_OFFSET (MLXPLAT_FPGA_PCI_BASE_OFFSET + 0x400) -+ -+#define MLXPLAT_FPGA_PCI_CTRL_READ BIT(0) -+#define MLXPLAT_FPGA_PCI_CTRL_WRITE BIT(1) -+#define MLXPLAT_FPGA_PCI_COMPLETED BIT(0) -+#define MLXPLAT_FPGA_PCI_TO 50 /* usec */ - - /* mlxplat_priv - platform private data - * @pdev_i2c - i2c controller platform device -@@ -443,6 +455,28 @@ static struct i2c_mux_reg_platform_data mlxplat_default_mux_data[] = { - - }; - -+/* Default channels vector for regmap mux. */ -+static int mlxplat_default_regmap_mux_chan[] = { 1, 2, 3, 4, 5, 6, 7, 8 }; -+ -+/* Platform regmap mux data */ -+static struct i2c_mux_regmap_platform_data mlxplat_default_regmap_mux_data[] = { -+ { -+ .parent = 1, -+ .chan_ids = mlxplat_default_regmap_mux_chan, -+ .num_adaps = ARRAY_SIZE(mlxplat_default_regmap_mux_chan), -+ .sel_reg_addr = MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET, -+ .reg_size = 1, -+ }, -+ { -+ .parent = 1, -+ .chan_ids = mlxplat_default_regmap_mux_chan, -+ .num_adaps = ARRAY_SIZE(mlxplat_default_regmap_mux_chan), -+ .sel_reg_addr = MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET, -+ .reg_size = 1, -+ }, -+ -+}; -+ - /* Platform mux configuration variables */ - static int mlxplat_max_adap_num; - static int mlxplat_mux_num; -@@ -5796,6 +5830,84 @@ static const struct regmap_config mlxplat_mlxcpld_regmap_config_eth_modular = { - .reg_write = mlxplat_mlxcpld_reg_write, - }; - -+/* Wait completion routine for indirect access for register map */ -+static int mlxplat_fpga_completion_wait(struct mlxplat_mlxcpld_regmap_context *ctx) -+{ -+ unsigned long end; -+ u16 status; -+ -+ end = jiffies + msecs_to_jiffies(MLXPLAT_FPGA_PCI_TO); -+ do { -+ status = ioread16(ctx->base + MLXPLAT_FPGA_PCI_STAT_OFFSET); -+ if (status & MLXPLAT_FPGA_PCI_COMPLETED) -+ return 0; -+ cond_resched(); -+ } while (time_before(jiffies, end)); -+ -+ return -EIO; -+} -+ -+/* Read callback for indirect register map access */ -+static int mlxplat_fpga_reg_read(void *context, unsigned int reg, unsigned int *val) -+{ -+ struct mlxplat_mlxcpld_regmap_context *ctx = context; -+ int err; -+ -+ /* Verify there is no pending transactions */ -+ err = mlxplat_fpga_completion_wait(ctx); -+ if (err) -+ return err; -+ -+ /* Set address in register space */ -+ iowrite16(reg, ctx->base + MLXPLAT_FPGA_PCI_ADDR_OFFSET); -+ /* Activate read operation */ -+ iowrite16(MLXPLAT_FPGA_PCI_CTRL_READ, ctx->base + MLXPLAT_FPGA_PCI_CTRL_OFFSET); -+ /* Verify transaction completion */ -+ err = mlxplat_fpga_completion_wait(ctx); -+ if (err) -+ return err; -+ -+ /* Read data */ -+ *val = ioread16(ctx->base + MLXPLAT_FPGA_PCI_DATA_OFFSET); -+ -+ return 0; -+} -+ -+/* Write callback for indirect register map access */ -+static int mlxplat_fpga_reg_write(void *context, unsigned int reg, unsigned int val) -+{ -+ struct mlxplat_mlxcpld_regmap_context *ctx = context; -+ int err; -+ -+ /* Verify there is no pending transactions */ -+ err = mlxplat_fpga_completion_wait(ctx); -+ if (err) -+ return err; -+ -+ /* Set address in register space */ -+ iowrite16(reg, ctx->base + MLXPLAT_FPGA_PCI_ADDR_OFFSET); -+ /* Set data to be written */ -+ iowrite16(val, ctx->base + MLXPLAT_FPGA_PCI_DATA_OFFSET); -+ /* Activate write operation */ -+ iowrite16(MLXPLAT_FPGA_PCI_CTRL_WRITE, ctx->base + MLXPLAT_FPGA_PCI_CTRL_OFFSET); -+ -+ return 0; -+} -+ -+static const struct regmap_config mlxplat_fpga_regmap_config_bf3_comex_default = { -+ .reg_bits = 16, -+ .val_bits = 8, -+ .max_register = 512, -+ .cache_type = REGCACHE_FLAT, -+ .writeable_reg = mlxplat_mlxcpld_writeable_reg, -+ .readable_reg = mlxplat_mlxcpld_readable_reg, -+ .volatile_reg = mlxplat_mlxcpld_volatile_reg, -+ .reg_defaults = mlxplat_mlxcpld_regmap_ng400, -+ .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_ng400), -+ .reg_read = mlxplat_fpga_reg_read, -+ .reg_write = mlxplat_fpga_reg_write, -+}; -+ - static struct resource mlxplat_mlxcpld_resources[] = { - [0] = DEFINE_RES_IRQ_NAMED(MLXPLAT_CPLD_LPC_SYSIRQ, "mlxreg-hotplug"), - }; -@@ -6175,6 +6287,29 @@ static int __init mlxplat_dmi_l1_switch_matched(const struct dmi_system_id *dmi) - return 1; - } - -+static int __init mlxplat_dmi_bf3_comex_default_matched(const struct dmi_system_id *dmi) -+{ -+ int i; -+ -+ mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; -+ mlxplat_mux_hotplug_num = MLXPLAT_CPLD_DEFAULT_MUX_HOTPLUG_VECTOR; -+ mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_regmap_mux_data); -+ mlxplat_mux_regmap_data = mlxplat_default_regmap_mux_data; -+ mlxplat_hotplug = &mlxplat_mlxcpld_ext_data; -+ mlxplat_hotplug->deferred_nr = -+ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; -+ mlxplat_led = &mlxplat_default_ng_led_data; -+ mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; -+ mlxplat_fan = &mlxplat_default_fan_data; -+ for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) -+ mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; -+ mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; -+ mlxplat_regmap_config = &mlxplat_fpga_regmap_config_bf3_comex_default; -+ pm_power_off = mlxplat_poweroff; -+ -+ return 1; -+} -+ - static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { - { - .callback = mlxplat_dmi_default_wc_matched, -@@ -6270,6 +6405,12 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { - DMI_MATCH(DMI_BOARD_NAME, "VMOD0015"), - }, - }, -+ { -+ .callback = mlxplat_dmi_bf3_comex_default_matched, -+ .matches = { -+ DMI_MATCH(DMI_BOARD_NAME, "VMOD0016"), -+ }, -+ }, - { - .callback = mlxplat_dmi_l1_switch_matched, - .matches = { -@@ -6502,6 +6643,11 @@ mlxplat_pci_fpga_device_init(struct resource **hotplug_resources, - err = -EIO; - goto fail_ioremap; - } -+ -+ /* Set mapped base address of I2C-LPC bridge over PCIe */ -+ mlxplat_i2c->addr = mlxplat_mlxcpld_regmap_ctx.base + -+ MLXPLAT_FPGA_PCI_I2C_LPC_OFFSET; -+ - pci_set_master(pci_dev); - - mlxplat_dev = platform_device_register_simple(MLX_PLAT_DEVICE_NAME, PLATFORM_DEVID_NONE, -@@ -6782,7 +6928,6 @@ static int mlxplat_i2c_main_init(struct mlxplat_priv *priv) - nr = (nr == mlxplat_max_adap_num) ? -1 : nr; - mlxplat_i2c->regmap = priv->regmap; - mlxplat_i2c->handle = priv; -- - priv->pdev_i2c = platform_device_register_resndata(&mlxplat_dev->dev, "i2c_mlxcpld", - nr, priv->hotplug_resources, - priv->hotplug_resources_size, --- -2.20.1 - diff --git a/platform/mellanox/non-upstream-patches/patches/0199-platform-mellanox-mlx-platform-Add-reset-and-extend-.patch b/platform/mellanox/non-upstream-patches/patches/0199-platform-mellanox-mlx-platform-Add-reset-and-extend-.patch deleted file mode 100644 index f9079db493ce..000000000000 --- a/platform/mellanox/non-upstream-patches/patches/0199-platform-mellanox-mlx-platform-Add-reset-and-extend-.patch +++ /dev/null @@ -1,138 +0,0 @@ -From a556177a2359c784e063f0914049ffd7f8d8852d Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Tue, 22 Nov 2022 21:20:49 +0200 -Subject: [PATCH backport 5.10 087/150] platform: mellanox: mlx-platform: Add - reset and extend poweroff callbacks - -On ARM based systems reset and poweroff flow should include special -actions against CPLD device for performing graceful operations. -For reset it is necessary to toggle special PLATFORM_RESET# signal, for -poweroff special HALT# signal. - -In order to support such flows relevant actions are provided. - -Signed-off-by: Vadim Pasternak ---- - drivers/platform/mellanox/mlx-platform.c | 35 ++++++++++++++++++++++++ - 1 file changed, 35 insertions(+) - -diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c -index b1c8632d6..849fdf5de 100644 ---- a/drivers/platform/mellanox/mlx-platform.c -+++ b/drivers/platform/mellanox/mlx-platform.c -@@ -43,6 +43,7 @@ - #define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET 0x1d - #define MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET 0x1e - #define MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET 0x1f -+#define MLXPLAT_CPLD_LPC_REG_PG_RST_OFFSET 0x19 - #define MLXPLAT_CPLD_LPC_REG_LED1_OFFSET 0x20 - #define MLXPLAT_CPLD_LPC_REG_LED2_OFFSET 0x21 - #define MLXPLAT_CPLD_LPC_REG_LED3_OFFSET 0x22 -@@ -263,6 +264,7 @@ - #define MLXPLAT_CPLD_LPC_LC_MASK GENMASK(7, 0) - - #define MLXPLAT_CPLD_HALT_MASK BIT(3) -+#define MLXPLAT_CPLD_RESET_MASK 0xfe - - /* Default I2C parent bus number */ - #define MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR 1 -@@ -483,6 +485,7 @@ static int mlxplat_mux_num; - static int mlxplat_mux_hotplug_num; - static struct i2c_mux_reg_platform_data *mlxplat_mux_data; - static struct i2c_mux_regmap_platform_data *mlxplat_mux_regmap_data; -+static struct notifier_block *mlxplat_reboot_nb; - - /* Platform extended mux data */ - static struct i2c_mux_reg_platform_data mlxplat_extended_mux_data[] = { -@@ -5280,6 +5283,7 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) - switch (reg) { - case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: - case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_PG_RST_OFFSET: - case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET: - case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET: - case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET: -@@ -5387,6 +5391,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET: - case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_PG_RST_OFFSET: - case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET: - case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET: - case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET: -@@ -5546,6 +5551,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET: - case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_PG_RST_OFFSET: - case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET: - case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET: - case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET: -@@ -5928,12 +5934,31 @@ static const struct regmap_config *mlxplat_regmap_config; - static struct spi_board_info *mlxplat_spi; - static struct pci_dev *fpga_dev; - -+/* Platform default reset function */ -+static int mlxplat_reboot_notifier(struct notifier_block *nb, unsigned long action, void *unused) -+{ -+ struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev); -+ -+ if (action == SYS_RESTART) -+ regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_PG_RST_OFFSET, -+ MLXPLAT_CPLD_RESET_MASK); -+ -+ return NOTIFY_DONE; -+} -+ -+static struct notifier_block mlxplat_reboot_default_nb = { -+ .notifier_call = mlxplat_reboot_notifier, -+}; -+ - /* Platform default poweroff function */ - static void mlxplat_poweroff(void) - { - struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev); - -+ if (mlxplat_reboot_nb) -+ unregister_reboot_notifier(mlxplat_reboot_nb); - regmap_write(priv->regmap, MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, MLXPLAT_CPLD_HALT_MASK); -+ kernel_halt(); - } - - static int __init mlxplat_dmi_default_matched(const struct dmi_system_id *dmi) -@@ -6305,6 +6330,7 @@ static int __init mlxplat_dmi_bf3_comex_default_matched(const struct dmi_system_ - mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; - mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; - mlxplat_regmap_config = &mlxplat_fpga_regmap_config_bf3_comex_default; -+ mlxplat_reboot_nb = &mlxplat_reboot_default_nb; - pm_power_off = mlxplat_poweroff; - - return 1; -@@ -7012,8 +7038,15 @@ static int __init mlxplat_init(void) - if (err) - goto fail_regcache_sync; - -+ if (mlxplat_reboot_nb) { -+ err = register_reboot_notifier(mlxplat_reboot_nb); -+ if (err) -+ goto fail_register_reboot_notifier; -+ } -+ - return 0; - -+fail_register_reboot_notifier: - fail_regcache_sync: - mlxplat_pre_exit(priv); - fail_mlxplat_i2c_main_init: -@@ -7031,6 +7064,8 @@ static void __exit mlxplat_exit(void) - - if (pm_power_off) - pm_power_off = NULL; -+ if (mlxplat_reboot_nb) -+ unregister_reboot_notifier(mlxplat_reboot_nb); - mlxplat_pre_exit(priv); - mlxplat_i2c_main_exit(priv); - } --- -2.20.1 - diff --git a/platform/mellanox/non-upstream-patches/patches/0212-platform-mellanox-mlxbf-pmc-Add-Mellanox-BlueField-P.patch b/platform/mellanox/non-upstream-patches/patches/0212-platform-mellanox-mlxbf-pmc-Add-Mellanox-BlueField-P.patch index 03e53f059051..a7b97a234dc3 100644 --- a/platform/mellanox/non-upstream-patches/patches/0212-platform-mellanox-mlxbf-pmc-Add-Mellanox-BlueField-P.patch +++ b/platform/mellanox/non-upstream-patches/patches/0212-platform-mellanox-mlxbf-pmc-Add-Mellanox-BlueField-P.patch @@ -60,12 +60,12 @@ index 5bd6ddd42..b0d2c3343 100644 tristate "Nvidia SN2201 platform driver support" depends on REGMAP diff --git a/drivers/platform/mellanox/Makefile b/drivers/platform/mellanox/Makefile -index 23919e56a..ba56485cb 100644 +index 499623ccf2fe..000ddaa74c98 100644 --- a/drivers/platform/mellanox/Makefile +++ b/drivers/platform/mellanox/Makefile -@@ -5,6 +5,7 @@ +@@ -4,6 +4,7 @@ + # Mellanox Platform-Specific Drivers # - obj-$(CONFIG_MLX_PLATFORM) += mlx-platform.o obj-$(CONFIG_MLXBF_BOOTCTL) += mlxbf-bootctl.o +obj-$(CONFIG_MLXBF_PMC) += mlxbf-pmc.o obj-$(CONFIG_MLXBF_TMFIFO) += mlxbf-tmfifo.o diff --git a/platform/mellanox/non-upstream-patches/patches/0218-UBUNTU-SAUCE-platform-mellanox-Add-mlx-trio-driver.patch b/platform/mellanox/non-upstream-patches/patches/0218-UBUNTU-SAUCE-platform-mellanox-Add-mlx-trio-driver.patch index 104c33198caf..582c3e27d38b 100644 --- a/platform/mellanox/non-upstream-patches/patches/0218-UBUNTU-SAUCE-platform-mellanox-Add-mlx-trio-driver.patch +++ b/platform/mellanox/non-upstream-patches/patches/0218-UBUNTU-SAUCE-platform-mellanox-Add-mlx-trio-driver.patch @@ -40,17 +40,16 @@ index b0d2c3343..5d329350a 100644 tristate "Nvidia SN2201 platform driver support" depends on REGMAP diff --git a/drivers/platform/mellanox/Makefile b/drivers/platform/mellanox/Makefile -index ba56485cb..161fad566 100644 +index 000ddaa74c98..837b748db1f6 100644 --- a/drivers/platform/mellanox/Makefile +++ b/drivers/platform/mellanox/Makefile -@@ -7,6 +7,7 @@ obj-$(CONFIG_MLX_PLATFORM) += mlx-platform.o +@@ -6,5 +6,6 @@ obj-$(CONFIG_MLXBF_BOOTCTL) += mlxbf-bootctl.o obj-$(CONFIG_MLXBF_PMC) += mlxbf-pmc.o obj-$(CONFIG_MLXBF_TMFIFO) += mlxbf-tmfifo.o +obj-$(CONFIG_MLXBF_TRIO) += mlx-trio.o obj-$(CONFIG_MLXREG_HOTPLUG) += mlxreg-hotplug.o obj-$(CONFIG_MLXREG_IO) += mlxreg-io.o - obj-$(CONFIG_MLXREG_LC) += mlxreg-lc.o diff --git a/drivers/platform/mellanox/mlx-trio.c b/drivers/platform/mellanox/mlx-trio.c new file mode 100644 index 000000000..849006e9c diff --git a/platform/mellanox/non-upstream-patches/patches/0220-UBUNTU-SAUCE-pka-Add-pka-driver.patch b/platform/mellanox/non-upstream-patches/patches/0220-UBUNTU-SAUCE-pka-Add-pka-driver.patch index 875083ea0234..9cf8e26254d1 100644 --- a/platform/mellanox/non-upstream-patches/patches/0220-UBUNTU-SAUCE-pka-Add-pka-driver.patch +++ b/platform/mellanox/non-upstream-patches/patches/0220-UBUNTU-SAUCE-pka-Add-pka-driver.patch @@ -57,14 +57,16 @@ index 5d329350a..946bc2375 100644 tristate "Nvidia SN2201 platform driver support" depends on REGMAP diff --git a/drivers/platform/mellanox/Makefile b/drivers/platform/mellanox/Makefile -index 161fad566..046347d3a 100644 +index a0a073adb..d89931e36 100644 --- a/drivers/platform/mellanox/Makefile +++ b/drivers/platform/mellanox/Makefile -@@ -12,3 +12,4 @@ obj-$(CONFIG_MLXREG_HOTPLUG) += mlxreg-hotplug.o +@@ -9,5 +9,6 @@ obj-$(CONFIG_MLXBF_TMFIFO) += mlxbf-tmfifo.o + obj-$(CONFIG_MLXBF_TRIO) += mlx-trio.o + obj-$(CONFIG_MLXREG_HOTPLUG) += mlxreg-hotplug.o obj-$(CONFIG_MLXREG_IO) += mlxreg-io.o ++obj-$(CONFIG_MLXBF_PKA) += mlxbf_pka/ obj-$(CONFIG_MLXREG_LC) += mlxreg-lc.o obj-$(CONFIG_NVSW_SN2201) += nvsw-sn2201.o -+obj-$(CONFIG_MLXBF_PKA) += mlxbf_pka/ diff --git a/drivers/platform/mellanox/mlxbf_pka/Kconfig b/drivers/platform/mellanox/mlxbf_pka/Kconfig new file mode 100644 index 000000000..ebc038ec7 diff --git a/platform/mellanox/non-upstream-patches/patches/0221-UBUNTU-SAUCE-platform-mellanox-Add-mlxbf-livefish-dr.patch b/platform/mellanox/non-upstream-patches/patches/0221-UBUNTU-SAUCE-platform-mellanox-Add-mlxbf-livefish-dr.patch index 8f9c4430e57d..d83c31b778d4 100644 --- a/platform/mellanox/non-upstream-patches/patches/0221-UBUNTU-SAUCE-platform-mellanox-Add-mlxbf-livefish-dr.patch +++ b/platform/mellanox/non-upstream-patches/patches/0221-UBUNTU-SAUCE-platform-mellanox-Add-mlxbf-livefish-dr.patch @@ -39,17 +39,16 @@ index 946bc2375..a5231c23a 100644 tristate "Mellanox BlueField Performance Monitoring Counters driver" depends on ARM64 diff --git a/drivers/platform/mellanox/Makefile b/drivers/platform/mellanox/Makefile -index 046347d3a..7c6393ebe 100644 +index 837b748db1f6..be5b83bd765e 100644 --- a/drivers/platform/mellanox/Makefile +++ b/drivers/platform/mellanox/Makefile -@@ -8,6 +8,7 @@ obj-$(CONFIG_MLXBF_BOOTCTL) += mlxbf-bootctl.o +@@ -7,5 +7,6 @@ obj-$(CONFIG_MLXBF_BOOTCTL) += mlxbf-bootctl.o obj-$(CONFIG_MLXBF_PMC) += mlxbf-pmc.o obj-$(CONFIG_MLXBF_TMFIFO) += mlxbf-tmfifo.o obj-$(CONFIG_MLXBF_TRIO) += mlx-trio.o +obj-$(CONFIG_MLXBF_LIVEFISH) += mlxbf-livefish.o obj-$(CONFIG_MLXREG_HOTPLUG) += mlxreg-hotplug.o obj-$(CONFIG_MLXREG_IO) += mlxreg-io.o - obj-$(CONFIG_MLXREG_LC) += mlxreg-lc.o diff --git a/drivers/platform/mellanox/mlxbf-livefish.c b/drivers/platform/mellanox/mlxbf-livefish.c new file mode 100644 index 000000000..c6150117d diff --git a/platform/mellanox/non-upstream-patches/patches/0234-UBUNTU-SAUCE-mlxbf_gige-add-validation-of-ACPI-table.patch b/platform/mellanox/non-upstream-patches/patches/0234-UBUNTU-SAUCE-mlxbf_gige-add-validation-of-ACPI-table.patch deleted file mode 100644 index 3d6cbb213472..000000000000 --- a/platform/mellanox/non-upstream-patches/patches/0234-UBUNTU-SAUCE-mlxbf_gige-add-validation-of-ACPI-table.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 8c7dd66540096a636aa35406cdb023dd549e2755 Mon Sep 17 00:00:00 2001 -From: David Thompson -Date: Wed, 20 Jul 2022 18:17:09 -0400 -Subject: [PATCH backport 5.10 35/63] UBUNTU: SAUCE: mlxbf_gige: add validation - of ACPI table version - -BugLink: https://bugs.launchpad.net/bugs/1982427 - -This patch checks the "version" property in the OOB ACPI table, -ensuring that the driver probe will only succeed if the expected -version is found. - -Change-Id: I8dc1f877338f9b23ab3560c0315a1727e144dd57 -Signed-off-by: David Thompson -Signed-off-by: Ike Panhc ---- - .../mellanox/mlxbf_gige/mlxbf_gige_main.c | 19 +++++++++++++++++++ - 1 file changed, 19 insertions(+) - -diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c -index e8f9290a8..c9176a2e6 100644 ---- a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c -+++ b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c -@@ -19,6 +19,11 @@ - #include "mlxbf_gige.h" - #include "mlxbf_gige_regs.h" - -+/* This setting defines the version of the ACPI table -+ * content that is compatible with this driver version. -+ */ -+#define MLXBF_GIGE_ACPI_TABLE_VERSION 2 -+ - /* Allocate SKB whose payload pointer aligns with the Bluefield - * hardware DMA limitation, i.e. DMA operation can't cross - * a 4KB boundary. A maximum packet size of 2KB is assumed in the -@@ -282,9 +287,23 @@ static int mlxbf_gige_probe(struct platform_device *pdev) - void __iomem *plu_base; - void __iomem *base; - int addr, phy_irq; -+ u32 version; - u64 control; - int err; - -+ version = 0; -+ err = device_property_read_u32(&pdev->dev, "version", &version); -+ if (err) { -+ dev_err(&pdev->dev, "ACPI table version not found\n"); -+ return -EINVAL; -+ } -+ -+ if (version != MLXBF_GIGE_ACPI_TABLE_VERSION) { -+ dev_err(&pdev->dev, "ACPI table version mismatch: expected %d found %d\n", -+ MLXBF_GIGE_ACPI_TABLE_VERSION, version); -+ return -EINVAL; -+ } -+ - mac_res = platform_get_resource(pdev, IORESOURCE_MEM, MLXBF_GIGE_RES_MAC); - if (!mac_res) - return -ENXIO; --- -2.20.1 - diff --git a/platform/mellanox/non-upstream-patches/patches/0235-UBUNTU-SAUCE-mlxbf_gige-set-driver-version-to-1.27.patch b/platform/mellanox/non-upstream-patches/patches/0235-UBUNTU-SAUCE-mlxbf_gige-set-driver-version-to-1.27.patch deleted file mode 100644 index 1f0fcabc871c..000000000000 --- a/platform/mellanox/non-upstream-patches/patches/0235-UBUNTU-SAUCE-mlxbf_gige-set-driver-version-to-1.27.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 438c36fd4f5ca577d03d50d0d037e44a2d25edd1 Mon Sep 17 00:00:00 2001 -From: David Thompson -Date: Wed, 20 Jul 2022 18:59:14 -0400 -Subject: [PATCH backport 5.10 36/63] UBUNTU: SAUCE: mlxbf_gige: set driver - version to 1.27 - -BugLink: https://bugs.launchpad.net/bugs/1982431 - -This patch adds logic to specify the driver version -via MODULE_VERSION() and sets the value to 1.27 - -Change-Id: I91f775df119877ad6d6eeaa5e5f93dcf1b55c8d2 -Signed-off-by: David Thompson -Signed-off-by: Ike Panhc ---- - drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c | 3 +++ - 1 file changed, 3 insertions(+) - -diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c -index c9176a2e6..66a50e35f 100644 ---- a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c -+++ b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c -@@ -19,6 +19,8 @@ - #include "mlxbf_gige.h" - #include "mlxbf_gige_regs.h" - -+#define DRV_VERSION 1.27 -+ - /* This setting defines the version of the ACPI table - * content that is compatible with this driver version. - */ -@@ -470,3 +472,4 @@ MODULE_DESCRIPTION("Mellanox BlueField SoC Gigabit Ethernet Driver"); - MODULE_AUTHOR("David Thompson "); - MODULE_AUTHOR("Asmaa Mnebhi "); - MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_VERSION(__stringify(DRV_VERSION)); --- -2.20.1 - diff --git a/platform/mellanox/non-upstream-patches/patches/0241-UBUNTU-SAUCE-mlxbf_gige-add-BlueField-3-Serdes-confi.patch b/platform/mellanox/non-upstream-patches/patches/0241-UBUNTU-SAUCE-mlxbf_gige-add-BlueField-3-Serdes-confi.patch deleted file mode 100644 index bdeef431bc85..000000000000 --- a/platform/mellanox/non-upstream-patches/patches/0241-UBUNTU-SAUCE-mlxbf_gige-add-BlueField-3-Serdes-confi.patch +++ /dev/null @@ -1,1865 +0,0 @@ -From e2017fcee49f8d2b36a59d5d6076259f4e4feeac Mon Sep 17 00:00:00 2001 -From: David Thompson -Date: Tue, 25 Oct 2022 18:24:01 -0400 -Subject: [PATCH backport 5.10 42/63] UBUNTU: SAUCE: mlxbf_gige: add - BlueField-3 Serdes configuration - -BugLink: https://bugs.launchpad.net/bugs/1995148 - -The BlueField-3 out-of-band Ethernet interface requires -SerDes configuration. There are two aspects to this: - -Configuration of PLL: - 1) Initialize UPHY registers to values dependent on p1clk clock - 2) Load PLL best known values via the gateway register - 3) Set the fuses to tune up the SerDes voltage - 4) Lock the PLL - 5) Get the lanes out of functional reset. - 6) Configure the UPHY microcontroller via gateway reads/writes - -Configuration of lanes: - 1) Configure and open TX lanes - 2) Configure and open RX lanes - -Signed-off-by: David Thompson -Signed-off-by: Asmaa Mnebhi ---- - .../net/ethernet/mellanox/mlxbf_gige/Makefile | 3 +- - .../ethernet/mellanox/mlxbf_gige/mlxbf_gige.h | 4 +- - .../mellanox/mlxbf_gige/mlxbf_gige_main.c | 76 +- - .../mellanox/mlxbf_gige/mlxbf_gige_mdio.c | 36 - - .../mellanox/mlxbf_gige/mlxbf_gige_uphy.c | 1191 +++++++++++++++++ - .../mellanox/mlxbf_gige/mlxbf_gige_uphy.h | 398 ++++++ - 6 files changed, 1645 insertions(+), 63 deletions(-) - create mode 100644 drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_uphy.c - create mode 100644 drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_uphy.h - -diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/Makefile b/drivers/net/ethernet/mellanox/mlxbf_gige/Makefile -index a97c2bef8..524af17ca 100644 ---- a/drivers/net/ethernet/mellanox/mlxbf_gige/Makefile -+++ b/drivers/net/ethernet/mellanox/mlxbf_gige/Makefile -@@ -7,4 +7,5 @@ mlxbf_gige-y := mlxbf_gige_ethtool.o \ - mlxbf_gige_main.o \ - mlxbf_gige_mdio.o \ - mlxbf_gige_rx.o \ -- mlxbf_gige_tx.o -+ mlxbf_gige_tx.o \ -+ mlxbf_gige_uphy.o -diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h -index a453b9cd9..e9bd09ee0 100644 ---- a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h -+++ b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h -@@ -100,6 +100,7 @@ struct mlxbf_gige { - struct platform_device *pdev; - void __iomem *mdio_io; - void __iomem *clk_io; -+ void __iomem *fuse_gw_io; - struct mii_bus *mdiobus; - spinlock_t lock; /* for packet processing indices */ - u16 rx_q_entries; -@@ -166,7 +167,8 @@ enum mlxbf_gige_res { - MLXBF_GIGE_RES_GPIO0, - MLXBF_GIGE_RES_LLU, - MLXBF_GIGE_RES_PLU, -- MLXBF_GIGE_RES_CLK -+ MLXBF_GIGE_RES_CLK, -+ MLXBF_GIGE_RES_FUSE_GW - }; - - /* Version of register data returned by mlxbf_gige_get_regs() */ -diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c -index 106b83bd6..f97e49670 100644 ---- a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c -+++ b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c -@@ -18,13 +18,25 @@ - - #include "mlxbf_gige.h" - #include "mlxbf_gige_regs.h" -+#include "mlxbf_gige_uphy.h" - --#define DRV_VERSION 1.27 -+#define MLXBF_GIGE_BF2_COREPLL_ADDR 0x02800c30 -+#define MLXBF_GIGE_BF2_COREPLL_SIZE 0x0000000c -+#define MLXBF_GIGE_BF3_COREPLL_ADDR 0x13409824 -+#define MLXBF_GIGE_BF3_COREPLL_SIZE 0x00000020 - --/* This setting defines the version of the ACPI table -- * content that is compatible with this driver version. -- */ --#define MLXBF_GIGE_ACPI_TABLE_VERSION 2 -+static struct resource corepll_params[] = { -+ [MLXBF_GIGE_VERSION_BF2] = { -+ .start = MLXBF_GIGE_BF2_COREPLL_ADDR, -+ .end = MLXBF_GIGE_BF2_COREPLL_ADDR + MLXBF_GIGE_BF2_COREPLL_SIZE - 1, -+ .name = "COREPLL_RES" -+ }, -+ [MLXBF_GIGE_VERSION_BF3] = { -+ .start = MLXBF_GIGE_BF3_COREPLL_ADDR, -+ .end = MLXBF_GIGE_BF3_COREPLL_ADDR + MLXBF_GIGE_BF3_COREPLL_SIZE - 1, -+ .name = "COREPLL_RES" -+ } -+}; - - /* Allocate SKB whose payload pointer aligns with the Bluefield - * hardware DMA limitation, i.e. DMA operation can't cross -@@ -371,31 +383,20 @@ static int mlxbf_gige_probe(struct platform_device *pdev) - { - struct phy_device *phydev; - struct net_device *netdev; -+ struct resource *clk_res; - struct resource *mac_res; - struct resource *llu_res; - struct resource *plu_res; - struct mlxbf_gige *priv; - void __iomem *llu_base; - void __iomem *plu_base; -+ void __iomem *clk_io; - void __iomem *base; - int addr, phy_irq; -- u32 version; -+ u64 soc_version; - u64 control; - int err; - -- version = 0; -- err = device_property_read_u32(&pdev->dev, "version", &version); -- if (err) { -- dev_err(&pdev->dev, "ACPI table version not found\n"); -- return -EINVAL; -- } -- -- if (version != MLXBF_GIGE_ACPI_TABLE_VERSION) { -- dev_err(&pdev->dev, "ACPI table version mismatch: expected %d found %d\n", -- MLXBF_GIGE_ACPI_TABLE_VERSION, version); -- return -EINVAL; -- } -- - mac_res = platform_get_resource(pdev, IORESOURCE_MEM, MLXBF_GIGE_RES_MAC); - if (!mac_res) - return -ENXIO; -@@ -404,6 +405,25 @@ static int mlxbf_gige_probe(struct platform_device *pdev) - if (IS_ERR(base)) - return PTR_ERR(base); - -+ soc_version = readq(base + MLXBF_GIGE_VERSION); -+ if (soc_version > MLXBF_GIGE_VERSION_BF3) -+ return -ENODEV; -+ -+ /* clk resource shared with other drivers so cannot use -+ * devm_platform_ioremap_resource -+ */ -+ clk_res = platform_get_resource(pdev, IORESOURCE_MEM, MLXBF_GIGE_RES_CLK); -+ if (!clk_res) { -+ /* For backward compatibility with older ACPI tables, also keep -+ * CLK resource internal to the driver. -+ */ -+ clk_res = &corepll_params[soc_version]; -+ } -+ -+ clk_io = devm_ioremap(&pdev->dev, clk_res->start, resource_size(clk_res)); -+ if (!clk_io) -+ return -ENOMEM; -+ - llu_res = platform_get_resource(pdev, IORESOURCE_MEM, MLXBF_GIGE_RES_LLU); - if (!llu_res) - return -ENXIO; -@@ -441,17 +461,23 @@ static int mlxbf_gige_probe(struct platform_device *pdev) - - spin_lock_init(&priv->lock); - -- priv->hw_version = readq(base + MLXBF_GIGE_VERSION); -+ priv->clk_io = clk_io; -+ priv->base = base; -+ priv->llu_base = llu_base; -+ priv->plu_base = plu_base; -+ priv->hw_version = soc_version; -+ -+ if (priv->hw_version == MLXBF_GIGE_VERSION_BF3) { -+ err = mlxbf_gige_config_uphy(priv); -+ if (err) -+ return err; -+ } - - /* Attach MDIO device */ - err = mlxbf_gige_mdio_probe(pdev, priv); - if (err) - return err; - -- priv->base = base; -- priv->llu_base = llu_base; -- priv->plu_base = plu_base; -- - priv->rx_q_entries = MLXBF_GIGE_DEFAULT_RXQ_SZ; - priv->tx_q_entries = MLXBF_GIGE_DEFAULT_TXQ_SZ; - -@@ -553,4 +579,4 @@ MODULE_DESCRIPTION("Mellanox BlueField SoC Gigabit Ethernet Driver"); - MODULE_AUTHOR("David Thompson "); - MODULE_AUTHOR("Asmaa Mnebhi "); - MODULE_LICENSE("Dual BSD/GPL"); --MODULE_VERSION(__stringify(DRV_VERSION)); -+ -diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio.c b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio.c -index 4ee3df30c..21acdcea3 100644 ---- a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio.c -+++ b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_mdio.c -@@ -113,24 +113,6 @@ static struct mlxbf_gige_mdio_gw mlxbf_gige_mdio_gw_t[] = { - /* Busy bit is set by software and cleared by hardware */ - #define MLXBF_GIGE_MDIO_SET_BUSY 0x1 - --#define MLXBF_GIGE_BF2_COREPLL_ADDR 0x02800c30 --#define MLXBF_GIGE_BF2_COREPLL_SIZE 0x0000000c --#define MLXBF_GIGE_BF3_COREPLL_ADDR 0x13409824 --#define MLXBF_GIGE_BF3_COREPLL_SIZE 0x00000010 -- --static struct resource corepll_params[] = { -- [MLXBF_GIGE_VERSION_BF2] = { -- .start = MLXBF_GIGE_BF2_COREPLL_ADDR, -- .end = MLXBF_GIGE_BF2_COREPLL_ADDR + MLXBF_GIGE_BF2_COREPLL_SIZE - 1, -- .name = "COREPLL_RES" -- }, -- [MLXBF_GIGE_VERSION_BF3] = { -- .start = MLXBF_GIGE_BF3_COREPLL_ADDR, -- .end = MLXBF_GIGE_BF3_COREPLL_ADDR + MLXBF_GIGE_BF3_COREPLL_SIZE - 1, -- .name = "COREPLL_RES" -- } --}; -- - /* Returns core clock i1clk in Hz */ - static u64 calculate_i1clk(struct mlxbf_gige *priv) - { -@@ -297,9 +279,6 @@ int mlxbf_gige_mdio_probe(struct platform_device *pdev, struct mlxbf_gige *priv) - struct resource *res; - int ret; - -- if (priv->hw_version > MLXBF_GIGE_VERSION_BF3) -- return -ENODEV; -- - res = platform_get_resource(pdev, IORESOURCE_MEM, MLXBF_GIGE_RES_MDIO9); - if (!res) - return -ENODEV; -@@ -308,21 +287,6 @@ int mlxbf_gige_mdio_probe(struct platform_device *pdev, struct mlxbf_gige *priv) - if (IS_ERR(priv->mdio_io)) - return PTR_ERR(priv->mdio_io); - -- /* clk resource shared with other drivers so cannot use -- * devm_platform_ioremap_resource -- */ -- res = platform_get_resource(pdev, IORESOURCE_MEM, MLXBF_GIGE_RES_CLK); -- if (!res) { -- /* For backward compatibility with older ACPI tables, also keep -- * CLK resource internal to the driver. -- */ -- res = &corepll_params[priv->hw_version]; -- } -- -- priv->clk_io = devm_ioremap(dev, res->start, resource_size(res)); -- if (!priv->clk_io) -- return -ENOMEM; -- - priv->mdio_gw = &mlxbf_gige_mdio_gw_t[priv->hw_version]; - - mlxbf_gige_mdio_cfg(priv); -diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_uphy.c b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_uphy.c -new file mode 100644 -index 000000000..9d64eb886 ---- /dev/null -+++ b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_uphy.c -@@ -0,0 +1,1191 @@ -+// SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause -+ -+/* UPHY support for Nvidia Gigabit Ethernet driver -+ * -+ * Copyright (C) 2022 NVIDIA CORPORATION & AFFILIATES -+ */ -+ -+#include -+#include -+#include -+ -+#include "mlxbf_gige.h" -+#include "mlxbf_gige_uphy.h" -+ -+static const struct mlxbf_gige_uphy_cfg_reg -+mlxbf_gige_clm_init[] = { -+ {.addr = 0x001, .wdata = 0x0105}, -+ {.addr = 0x008, .wdata = 0x0001}, -+ {.addr = 0x00B, .wdata = 0x8420}, -+ {.addr = 0x00E, .wdata = 0x0110}, -+ {.addr = 0x010, .wdata = 0x3010}, -+ {.addr = 0x027, .wdata = 0x0104}, -+ {.addr = 0x02F, .wdata = 0x09EA}, -+ {.addr = 0x055, .wdata = 0x0008}, -+ {.addr = 0x058, .wdata = 0x0088}, -+ {.addr = 0x072, .wdata = 0x3222}, -+ {.addr = 0x073, .wdata = 0x7654}, -+ {.addr = 0x074, .wdata = 0xBA98}, -+ {.addr = 0x075, .wdata = 0xDDDC} -+}; -+ -+#define MLXBF_GIGE_UPHY_CLM_INIT_NUM_ENTRIES \ -+ (sizeof(mlxbf_gige_clm_init) / sizeof(struct mlxbf_gige_uphy_cfg_reg)) -+ -+static const struct mlxbf_gige_uphy_cfg_reg -+mlxbf_gige_dlm_imem_init[] = { -+ {.addr = 0x39C, .wdata = 0x0000}, -+ {.addr = 0x39D, .wdata = 0x0095}, -+ {.addr = 0x3BF, .wdata = 0x9027}, -+ {.addr = 0x39E, .wdata = 0xA8F6}, -+ {.addr = 0x39F, .wdata = 0xAA10}, -+ {.addr = 0x3A0, .wdata = 0xA8D4}, -+ {.addr = 0x3A1, .wdata = 0xA7AE}, -+ {.addr = 0x3A2, .wdata = 0xA7CC}, -+ {.addr = 0x3A3, .wdata = 0x9BE4}, -+ {.addr = 0x3A4, .wdata = 0xB2D2}, -+ {.addr = 0x3A5, .wdata = 0xB1F2}, -+ {.addr = 0x3AE, .wdata = 0x7C38}, -+ {.addr = 0x3AF, .wdata = 0x7C4A}, -+ {.addr = 0x3B0, .wdata = 0x7C25}, -+ {.addr = 0x3B1, .wdata = 0x7C74}, -+ {.addr = 0x3B2, .wdata = 0x3C00}, -+ {.addr = 0x3B3, .wdata = 0x3C11}, -+ {.addr = 0x3B4, .wdata = 0x3C5D}, -+ {.addr = 0x3B5, .wdata = 0x3C5D} -+}; -+ -+#define MLXBF_GIGE_UPHY_DLM_IMEM_INIT_NUM_ENTRIES \ -+ (sizeof(mlxbf_gige_dlm_imem_init) / sizeof(struct mlxbf_gige_uphy_cfg_reg)) -+ -+static const struct mlxbf_gige_uphy_cfg_reg -+mlxbf_gige_dlm_seq_imem_wr_en_init = { -+ .addr = 0x39A, .wdata = 0x0001 -+}; -+ -+static const struct mlxbf_gige_uphy_cfg_reg -+mlxbf_gige_dlm_seq_imem_wr_dis_init = { -+ .addr = 0x39A, .wdata = 0x0000 -+}; -+ -+static const struct mlxbf_gige_uphy_cfg_reg -+mlxbf_gige_dlm_imem_data[] = { -+ { /* .iaddr = 0x0000 */ .wdata = 0x02DF}, -+ { /* .iaddr = 0x0001 */ .wdata = 0xEEC0}, -+ { /* .iaddr = 0x0002 */ .wdata = 0xD508}, -+ { /* .iaddr = 0x0003 */ .wdata = 0x022F}, -+ { /* .iaddr = 0x0004 */ .wdata = 0xC401}, -+ { /* .iaddr = 0x0005 */ .wdata = 0xD341}, -+ { /* .iaddr = 0x0006 */ .wdata = 0xC402}, -+ { /* .iaddr = 0x0007 */ .wdata = 0xD342}, -+ { /* .iaddr = 0x0008 */ .wdata = 0xC403}, -+ { /* .iaddr = 0x0009 */ .wdata = 0xD343}, -+ { /* .iaddr = 0x000A */ .wdata = 0xC404}, -+ { /* .iaddr = 0x000B */ .wdata = 0xD344}, -+ { /* .iaddr = 0x000C */ .wdata = 0xC417}, -+ { /* .iaddr = 0x000D */ .wdata = 0xD355}, -+ { /* .iaddr = 0x000E */ .wdata = 0xC418}, -+ { /* .iaddr = 0x000F */ .wdata = 0xD356}, -+ { /* .iaddr = 0x0010 */ .wdata = 0xF021}, -+ { /* .iaddr = 0x0011 */ .wdata = 0xF003}, -+ { /* .iaddr = 0x0012 */ .wdata = 0xE224}, -+ { /* .iaddr = 0x0013 */ .wdata = 0x0DA9}, -+ { /* .iaddr = 0x0014 */ .wdata = 0xF003}, -+ { /* .iaddr = 0x0015 */ .wdata = 0xE21C}, -+ { /* .iaddr = 0x0016 */ .wdata = 0xEEC1}, -+ { /* .iaddr = 0x0017 */ .wdata = 0x0D87}, -+ { /* .iaddr = 0x0018 */ .wdata = 0xEEC1}, -+ { /* .iaddr = 0x0019 */ .wdata = 0xE806}, -+ { /* .iaddr = 0x001A */ .wdata = 0xC3C5}, -+ { /* .iaddr = 0x001B */ .wdata = 0xD306}, -+ { /* .iaddr = 0x001C */ .wdata = 0xEEDF}, -+ { /* .iaddr = 0x001D */ .wdata = 0xE806}, -+ { /* .iaddr = 0x001E */ .wdata = 0xC3C6}, -+ { /* .iaddr = 0x001F */ .wdata = 0xD306}, -+ { /* .iaddr = 0x0020 */ .wdata = 0xF002}, -+ { /* .iaddr = 0x0021 */ .wdata = 0xC3C8}, -+ { /* .iaddr = 0x0022 */ .wdata = 0x409A}, -+ { /* .iaddr = 0x0023 */ .wdata = 0xF021}, -+ { /* .iaddr = 0x0024 */ .wdata = 0xEEE0}, -+ { /* .iaddr = 0x0025 */ .wdata = 0xEEC0}, -+ { /* .iaddr = 0x0026 */ .wdata = 0xD70D}, -+ { /* .iaddr = 0x0027 */ .wdata = 0xC305}, -+ { /* .iaddr = 0x0028 */ .wdata = 0xD328}, -+ { /* .iaddr = 0x0029 */ .wdata = 0xC300}, -+ { /* .iaddr = 0x002A */ .wdata = 0xD314}, -+ { /* .iaddr = 0x002B */ .wdata = 0xC301}, -+ { /* .iaddr = 0x002C */ .wdata = 0xD318}, -+ { /* .iaddr = 0x002D */ .wdata = 0xC303}, -+ { /* .iaddr = 0x002E */ .wdata = 0xD320}, -+ { /* .iaddr = 0x002F */ .wdata = 0xC302}, -+ { /* .iaddr = 0x0030 */ .wdata = 0xD31C}, -+ { /* .iaddr = 0x0031 */ .wdata = 0xC304}, -+ { /* .iaddr = 0x0032 */ .wdata = 0xD324}, -+ { /* .iaddr = 0x0033 */ .wdata = 0xC358}, -+ { /* .iaddr = 0x0034 */ .wdata = 0xD330}, -+ { /* .iaddr = 0x0035 */ .wdata = 0xC307}, -+ { /* .iaddr = 0x0036 */ .wdata = 0xD115}, -+ { /* .iaddr = 0x0037 */ .wdata = 0xF021}, -+ { /* .iaddr = 0x0038 */ .wdata = 0xD70D}, -+ { /* .iaddr = 0x0039 */ .wdata = 0xC305}, -+ { /* .iaddr = 0x003A */ .wdata = 0xD328}, -+ { /* .iaddr = 0x003B */ .wdata = 0xC300}, -+ { /* .iaddr = 0x003C */ .wdata = 0xD314}, -+ { /* .iaddr = 0x003D */ .wdata = 0xC301}, -+ { /* .iaddr = 0x003E */ .wdata = 0xD318}, -+ { /* .iaddr = 0x003F */ .wdata = 0xC303}, -+ { /* .iaddr = 0x0040 */ .wdata = 0xD320}, -+ { /* .iaddr = 0x0041 */ .wdata = 0xC302}, -+ { /* .iaddr = 0x0042 */ .wdata = 0xD31C}, -+ { /* .iaddr = 0x0043 */ .wdata = 0xC304}, -+ { /* .iaddr = 0x0044 */ .wdata = 0xD324}, -+ { /* .iaddr = 0x0045 */ .wdata = 0xC358}, -+ { /* .iaddr = 0x0046 */ .wdata = 0xD330}, -+ { /* .iaddr = 0x0047 */ .wdata = 0xC307}, -+ { /* .iaddr = 0x0048 */ .wdata = 0xD115}, -+ { /* .iaddr = 0x0049 */ .wdata = 0xF021}, -+ { /* .iaddr = 0x004A */ .wdata = 0xC70D}, -+ { /* .iaddr = 0x004B */ .wdata = 0xD70F}, -+ { /* .iaddr = 0x004C */ .wdata = 0xC328}, -+ { /* .iaddr = 0x004D */ .wdata = 0xD305}, -+ { /* .iaddr = 0x004E */ .wdata = 0xC314}, -+ { /* .iaddr = 0x004F */ .wdata = 0xD300}, -+ { /* .iaddr = 0x0050 */ .wdata = 0xC318}, -+ { /* .iaddr = 0x0051 */ .wdata = 0xD301}, -+ { /* .iaddr = 0x0052 */ .wdata = 0xC320}, -+ { /* .iaddr = 0x0053 */ .wdata = 0xD303}, -+ { /* .iaddr = 0x0054 */ .wdata = 0xC31C}, -+ { /* .iaddr = 0x0055 */ .wdata = 0xD302}, -+ { /* .iaddr = 0x0056 */ .wdata = 0xC324}, -+ { /* .iaddr = 0x0057 */ .wdata = 0xD304}, -+ { /* .iaddr = 0x0058 */ .wdata = 0xC330}, -+ { /* .iaddr = 0x0059 */ .wdata = 0xD358}, -+ { /* .iaddr = 0x005A */ .wdata = 0xC115}, -+ { /* .iaddr = 0x005B */ .wdata = 0xD307}, -+ { /* .iaddr = 0x005C */ .wdata = 0xF021}, -+ { /* .iaddr = 0x005D */ .wdata = 0x0249}, -+ { /* .iaddr = 0x005E */ .wdata = 0x0362}, -+ { /* .iaddr = 0x005F */ .wdata = 0x023D}, -+ { /* .iaddr = 0x0060 */ .wdata = 0xEEC1}, -+ { /* .iaddr = 0x0061 */ .wdata = 0x0369}, -+ { /* .iaddr = 0x0062 */ .wdata = 0xEEC1}, -+ { /* .iaddr = 0x0063 */ .wdata = 0x0CEA}, -+ { /* .iaddr = 0x0064 */ .wdata = 0xEEC2}, -+ { /* .iaddr = 0x0065 */ .wdata = 0xD701}, -+ { /* .iaddr = 0x0066 */ .wdata = 0x02C8}, -+ { /* .iaddr = 0x0067 */ .wdata = 0xC3C3}, -+ { /* .iaddr = 0x0068 */ .wdata = 0xD306}, -+ { /* .iaddr = 0x0069 */ .wdata = 0xC3C8}, -+ { /* .iaddr = 0x006A */ .wdata = 0x009A}, -+ { /* .iaddr = 0x006B */ .wdata = 0xC3D1}, -+ { /* .iaddr = 0x006C */ .wdata = 0xD309}, -+ { /* .iaddr = 0x006D */ .wdata = 0x0C46}, -+ { /* .iaddr = 0x006E */ .wdata = 0x0DE7}, -+ { /* .iaddr = 0x006F */ .wdata = 0xEEC0}, -+ { /* .iaddr = 0x0070 */ .wdata = 0xC3D9}, -+ { /* .iaddr = 0x0071 */ .wdata = 0x0DDE}, -+ { /* .iaddr = 0x0072 */ .wdata = 0x02D7}, -+ { /* .iaddr = 0x0073 */ .wdata = 0xF021}, -+ { /* .iaddr = 0x0074 */ .wdata = 0x1441}, -+ { /* .iaddr = 0x0075 */ .wdata = 0xF003}, -+ { /* .iaddr = 0x0076 */ .wdata = 0xC03F}, -+ { /* .iaddr = 0x0077 */ .wdata = 0xF704}, -+ { /* .iaddr = 0x0078 */ .wdata = 0xF009}, -+ { /* .iaddr = 0x0079 */ .wdata = 0xE21A}, -+ { /* .iaddr = 0x007A */ .wdata = 0xF002}, -+ { /* .iaddr = 0x007B */ .wdata = 0x0C52}, -+ { /* .iaddr = 0x007C */ .wdata = 0xE206}, -+ { /* .iaddr = 0x007D */ .wdata = 0xEEC1}, -+ { /* .iaddr = 0x007E */ .wdata = 0xD01A}, -+ { /* .iaddr = 0x007F */ .wdata = 0x3C5D}, -+ { /* .iaddr = 0x0080 */ .wdata = 0xEEC0}, -+ { /* .iaddr = 0x0081 */ .wdata = 0xD01A}, -+ { /* .iaddr = 0x0082 */ .wdata = 0x0E12}, -+ { /* .iaddr = 0x0083 */ .wdata = 0xEEC0}, -+ { /* .iaddr = 0x0084 */ .wdata = 0x13E1}, -+ { /* .iaddr = 0x0085 */ .wdata = 0x1441}, -+ { /* .iaddr = 0x0086 */ .wdata = 0xEEC1}, -+ { /* .iaddr = 0x0087 */ .wdata = 0xD70E}, -+ { /* .iaddr = 0x0088 */ .wdata = 0xD70F}, -+ { /* .iaddr = 0x0089 */ .wdata = 0xEEC0}, -+ { /* .iaddr = 0x008A */ .wdata = 0xD70E}, -+ { /* .iaddr = 0x008B */ .wdata = 0xC458}, -+ { /* .iaddr = 0x008C */ .wdata = 0x13BE}, -+ { /* .iaddr = 0x008D */ .wdata = 0xEEC0}, -+ { /* .iaddr = 0x008E */ .wdata = 0xF29B}, -+ { /* .iaddr = 0x008F */ .wdata = 0xE20A}, -+ { /* .iaddr = 0x0090 */ .wdata = 0xEEC1}, -+ { /* .iaddr = 0x0091 */ .wdata = 0xD01D}, -+ { /* .iaddr = 0x0092 */ .wdata = 0xEEC1}, -+ { /* .iaddr = 0x0093 */ .wdata = 0xD3FD}, -+ { /* .iaddr = 0x0094 */ .wdata = 0xF021} -+}; -+ -+#define MLXBF_GIGE_UPHY_DLM_IMEM_DATA_NUM_ENTRIES \ -+ (sizeof(mlxbf_gige_dlm_imem_data) / sizeof(struct mlxbf_gige_uphy_cfg_reg)) -+ -+static const struct mlxbf_gige_uphy_cfg_reg -+mlxbf_gige_dlm_seq_imem_csum_en = { -+ .addr = 0x39A, .wdata = 0x0004 -+}; -+ -+static const struct mlxbf_gige_uphy_cfg_reg -+mlxbf_gige_dlm_seq_imem_csum_dis = { -+ .addr = 0x39A, .wdata = 0x0000 -+}; -+ -+static const struct mlxbf_gige_uphy_cfg_reg -+mlxbf_gige_dlm_seq_imem_bmap_clr[] = { -+ {.addr = 0x39E, .wdata = 0x0000}, -+ {.addr = 0x39F, .wdata = 0x0000}, -+ {.addr = 0x3A0, .wdata = 0x0000}, -+ {.addr = 0x3A1, .wdata = 0x0000}, -+ {.addr = 0x3A2, .wdata = 0x0000}, -+ {.addr = 0x3A3, .wdata = 0x0000}, -+ {.addr = 0x3A4, .wdata = 0x0000}, -+ {.addr = 0x3A5, .wdata = 0x0000}, -+ {.addr = 0x3A6, .wdata = 0x0000}, -+ {.addr = 0x3A7, .wdata = 0x0000}, -+ {.addr = 0x3A8, .wdata = 0x0000}, -+ {.addr = 0x3A9, .wdata = 0x0000}, -+ {.addr = 0x3AA, .wdata = 0x0000}, -+ {.addr = 0x3AB, .wdata = 0x0000}, -+ {.addr = 0x3AC, .wdata = 0x0000}, -+ {.addr = 0x3AD, .wdata = 0x0000}, -+ {.addr = 0x3AE, .wdata = 0x0000}, -+ {.addr = 0x3AF, .wdata = 0x0000}, -+ {.addr = 0x3B0, .wdata = 0x0000}, -+ {.addr = 0x3B1, .wdata = 0x0000}, -+ {.addr = 0x3B2, .wdata = 0x0000}, -+ {.addr = 0x3B3, .wdata = 0x0000}, -+ {.addr = 0x3B4, .wdata = 0x0000}, -+ {.addr = 0x3B5, .wdata = 0x0000}, -+ {.addr = 0x3B6, .wdata = 0x0000}, -+ {.addr = 0x3B7, .wdata = 0x0000}, -+ {.addr = 0x3B8, .wdata = 0x0000}, -+ {.addr = 0x3B9, .wdata = 0x0000}, -+ {.addr = 0x3BA, .wdata = 0x0000}, -+ {.addr = 0x3BB, .wdata = 0x0000}, -+ {.addr = 0x3BC, .wdata = 0x0000}, -+ {.addr = 0x3BD, .wdata = 0x0000} -+}; -+ -+#define MLXBF_GIGE_DLM_SEQ_IMEM_BMAP_CLR_NUM_ENTRIES \ -+ (sizeof(mlxbf_gige_dlm_seq_imem_bmap_clr) / sizeof(struct mlxbf_gige_uphy_cfg_reg)) -+ -+static const struct mlxbf_gige_uphy_cfg_reg -+mlxbf_gige_dlm_tx_init[] = { -+ {.addr = 0x002, .wdata = 0x5125}, -+ {.addr = 0x01C, .wdata = 0x0018}, -+ {.addr = 0x01E, .wdata = 0x0E00}, -+ {.addr = 0x01F, .wdata = 0xC200}, -+ {.addr = 0x023, .wdata = 0x0277}, -+ {.addr = 0x024, .wdata = 0x026B}, -+ {.addr = 0x053, .wdata = 0x0700}, -+ {.addr = 0x059, .wdata = 0x1011}, -+ {.addr = 0x060, .wdata = 0x0000}, -+ {.addr = 0x062, .wdata = 0x0135}, -+ {.addr = 0x063, .wdata = 0x0443}, -+ {.addr = 0x064, .wdata = 0x0000}, -+ {.addr = 0x066, .wdata = 0x0061}, -+ {.addr = 0x067, .wdata = 0x0042}, -+ {.addr = 0x06A, .wdata = 0x1212}, -+ {.addr = 0x06B, .wdata = 0x1515}, -+ {.addr = 0x06C, .wdata = 0x011A}, -+ {.addr = 0x06D, .wdata = 0x0132}, -+ {.addr = 0x06E, .wdata = 0x0632}, -+ {.addr = 0x06F, .wdata = 0x0643}, -+ {.addr = 0x070, .wdata = 0x0233}, -+ {.addr = 0x071, .wdata = 0x0433}, -+ {.addr = 0x07E, .wdata = 0x6A08}, -+ {.addr = 0x08D, .wdata = 0x2101}, -+ {.addr = 0x093, .wdata = 0x0015}, -+ {.addr = 0x096, .wdata = 0x7555}, -+ {.addr = 0x0A9, .wdata = 0xE754}, -+ {.addr = 0x0AA, .wdata = 0x7ED1}, -+ {.addr = 0x3FF, .wdata = 0x0000}, -+ {.addr = 0x3FF, .wdata = 0x0000}, -+ {.addr = 0x3FF, .wdata = 0x0000}, -+ {.addr = 0x3FF, .wdata = 0x0000}, -+ {.addr = 0x3FF, .wdata = 0x0000}, -+ {.addr = 0x3FF, .wdata = 0x0000}, -+ {.addr = 0x3FF, .wdata = 0x0000}, -+ {.addr = 0x3FF, .wdata = 0x0000}, -+ {.addr = 0x3FF, .wdata = 0x0000}, -+ {.addr = 0x3FF, .wdata = 0x0000}, -+ {.addr = 0x3FF, .wdata = 0x0000}, -+ {.addr = 0x3FF, .wdata = 0x0000} -+}; -+ -+#define MLXBF_GIGE_DLM_TX_NUM_ENTRIES \ -+ (sizeof(mlxbf_gige_dlm_tx_init) / sizeof(struct mlxbf_gige_uphy_cfg_reg)) -+ -+static const struct mlxbf_gige_uphy_cfg_reg -+mlxbf_gige_dlm_rx_init[] = { -+ {.addr = 0x003, .wdata = 0x5125}, -+ {.addr = 0x01D, .wdata = 0x0004}, -+ {.addr = 0x028, .wdata = 0x1000}, -+ {.addr = 0x029, .wdata = 0x1001}, -+ {.addr = 0x02E, .wdata = 0x0004}, -+ {.addr = 0x053, .wdata = 0x0700}, -+ {.addr = 0x057, .wdata = 0x5044}, -+ {.addr = 0x05B, .wdata = 0x1011}, -+ {.addr = 0x0D2, .wdata = 0x0002}, -+ {.addr = 0x0D9, .wdata = 0x0000}, -+ {.addr = 0x0DA, .wdata = 0x0000}, -+ {.addr = 0x0DB, .wdata = 0x0000}, -+ {.addr = 0x0E2, .wdata = 0x0000}, -+ {.addr = 0x0E7, .wdata = 0xBB10}, -+ {.addr = 0x0E8, .wdata = 0xBB10}, -+ {.addr = 0x0EC, .wdata = 0x0111}, -+ {.addr = 0x0ED, .wdata = 0x1C00}, -+ {.addr = 0x0F5, .wdata = 0x0000}, -+ {.addr = 0x102, .wdata = 0x0CA6}, -+ {.addr = 0x107, .wdata = 0x0020}, -+ {.addr = 0x10C, .wdata = 0x1E31}, -+ {.addr = 0x10D, .wdata = 0x1D29}, -+ {.addr = 0x111, .wdata = 0x00E7}, -+ {.addr = 0x112, .wdata = 0x5202}, -+ {.addr = 0x117, .wdata = 0x0493}, -+ {.addr = 0x11B, .wdata = 0x0148}, -+ {.addr = 0x120, .wdata = 0x23DE}, -+ {.addr = 0x121, .wdata = 0x2294}, -+ {.addr = 0x125, .wdata = 0x03FF}, -+ {.addr = 0x126, .wdata = 0x25F0}, -+ {.addr = 0x12B, .wdata = 0xC633}, -+ {.addr = 0x136, .wdata = 0x0F6A}, -+ {.addr = 0x143, .wdata = 0x0000}, -+ {.addr = 0x148, .wdata = 0x0001}, -+ {.addr = 0x14E, .wdata = 0x0000}, -+ {.addr = 0x155, .wdata = 0x2003}, -+ {.addr = 0x15C, .wdata = 0x099B}, -+ {.addr = 0x161, .wdata = 0x0088}, -+ {.addr = 0x16B, .wdata = 0x0433}, -+ {.addr = 0x172, .wdata = 0x099B}, -+ {.addr = 0x17C, .wdata = 0x045D}, -+ {.addr = 0x17D, .wdata = 0x006A}, -+ {.addr = 0x181, .wdata = 0x0000}, -+ {.addr = 0x189, .wdata = 0x1590}, -+ {.addr = 0x18E, .wdata = 0x0080}, -+ {.addr = 0x18F, .wdata = 0x90EC}, -+ {.addr = 0x191, .wdata = 0x79F8}, -+ {.addr = 0x194, .wdata = 0x000A}, -+ {.addr = 0x195, .wdata = 0x000A}, -+ {.addr = 0x1EB, .wdata = 0x0133}, -+ {.addr = 0x1F0, .wdata = 0x0030}, -+ {.addr = 0x1F1, .wdata = 0x0030}, -+ {.addr = 0x1F5, .wdata = 0x3737}, -+ {.addr = 0x1F6, .wdata = 0x3737}, -+ {.addr = 0x1FA, .wdata = 0x2C00}, -+ {.addr = 0x1FF, .wdata = 0x0516}, -+ {.addr = 0x200, .wdata = 0x0516}, -+ {.addr = 0x204, .wdata = 0x3010}, -+ {.addr = 0x209, .wdata = 0x0429}, -+ {.addr = 0x20E, .wdata = 0x0010}, -+ {.addr = 0x213, .wdata = 0x005A}, -+ {.addr = 0x214, .wdata = 0x0000}, -+ {.addr = 0x216, .wdata = 0x0000}, -+ {.addr = 0x218, .wdata = 0x0000}, -+ {.addr = 0x225, .wdata = 0x0000}, -+ {.addr = 0x22A, .wdata = 0x0000}, -+ {.addr = 0x22B, .wdata = 0x0000}, -+ {.addr = 0x231, .wdata = 0x0000}, -+ {.addr = 0x232, .wdata = 0x0000}, -+ {.addr = 0x233, .wdata = 0x0000}, -+ {.addr = 0x245, .wdata = 0x0300}, -+ {.addr = 0x24A, .wdata = 0x0000}, -+ {.addr = 0x24F, .wdata = 0xFFF3}, -+ {.addr = 0x254, .wdata = 0x0000}, -+ {.addr = 0x259, .wdata = 0x0000}, -+ {.addr = 0x25E, .wdata = 0x0000}, -+ {.addr = 0x265, .wdata = 0x0009}, -+ {.addr = 0x267, .wdata = 0x0174}, -+ {.addr = 0x271, .wdata = 0x01F0}, -+ {.addr = 0x273, .wdata = 0x0170}, -+ {.addr = 0x275, .wdata = 0x7828}, -+ {.addr = 0x279, .wdata = 0x3E3A}, -+ {.addr = 0x27D, .wdata = 0x8468}, -+ {.addr = 0x283, .wdata = 0x000C}, -+ {.addr = 0x285, .wdata = 0x7777}, -+ {.addr = 0x288, .wdata = 0x5503}, -+ {.addr = 0x28C, .wdata = 0x0030}, -+ {.addr = 0x28E, .wdata = 0xBBBB}, -+ {.addr = 0x290, .wdata = 0xBBBB}, -+ {.addr = 0x293, .wdata = 0x0021}, -+ {.addr = 0x2FA, .wdata = 0x3B40}, -+ {.addr = 0x2FB, .wdata = 0x7777}, -+ {.addr = 0x30A, .wdata = 0x8022}, -+ {.addr = 0x319, .wdata = 0x205E}, -+ {.addr = 0x31B, .wdata = 0x0000}, -+ {.addr = 0x31D, .wdata = 0x6004}, -+ {.addr = 0x320, .wdata = 0x3014}, -+ {.addr = 0x322, .wdata = 0x6004}, -+ {.addr = 0x326, .wdata = 0x6004}, -+ {.addr = 0x32A, .wdata = 0x5000}, -+ {.addr = 0x32E, .wdata = 0x5000}, -+ {.addr = 0x332, .wdata = 0x6004}, -+ {.addr = 0x336, .wdata = 0x6063}, -+ {.addr = 0x389, .wdata = 0x0310}, -+ {.addr = 0x3FF, .wdata = 0x0000}, -+ {.addr = 0x3FF, .wdata = 0x0000}, -+ {.addr = 0x3FF, .wdata = 0x0000}, -+ {.addr = 0x3FF, .wdata = 0x0000}, -+ {.addr = 0x3FF, .wdata = 0x0000}, -+ {.addr = 0x3FF, .wdata = 0x0000}, -+ {.addr = 0x3FF, .wdata = 0x0000}, -+ {.addr = 0x3FF, .wdata = 0x0000}, -+ {.addr = 0x3FF, .wdata = 0x0000}, -+ {.addr = 0x3FF, .wdata = 0x0000}, -+ {.addr = 0x3FF, .wdata = 0x0000}, -+ {.addr = 0x3FF, .wdata = 0x0000}, -+ {.addr = 0x3FF, .wdata = 0x0000}, -+ {.addr = 0x3FF, .wdata = 0x0000}, -+ {.addr = 0x3FF, .wdata = 0x0000}, -+ {.addr = 0x3FF, .wdata = 0x0000} -+}; -+ -+#define MLXBF_GIGE_DLM_RX_NUM_ENTRIES \ -+ (sizeof(mlxbf_gige_dlm_rx_init) / sizeof(struct mlxbf_gige_uphy_cfg_reg)) -+ -+/* returns plu clock p1clk in Hz */ -+static u64 mlxbf_gige_calculate_p1clk(struct mlxbf_gige *priv) -+{ -+ u8 core_od, core_r; -+ u64 freq_output; -+ u32 reg1, reg2; -+ u32 core_f; -+ -+ reg1 = readl(priv->clk_io + MLXBF_GIGE_P1CLK_REG1); -+ reg2 = readl(priv->clk_io + MLXBF_GIGE_P1CLK_REG2); -+ -+ core_f = (reg1 & MLXBF_GIGE_P1_CORE_F_MASK) >> -+ MLXBF_GIGE_P1_CORE_F_SHIFT; -+ core_r = (reg1 & MLXBF_GIGE_P1_CORE_R_MASK) >> -+ MLXBF_GIGE_P1_CORE_R_SHIFT; -+ core_od = (reg2 & MLXBF_GIGE_P1_CORE_OD_MASK) >> -+ MLXBF_GIGE_P1_CORE_OD_SHIFT; -+ -+ /* Compute PLL output frequency as follow: -+ * -+ * CORE_F / 16384 -+ * freq_output = freq_reference * ---------------------------- -+ * (CORE_R + 1) * (CORE_OD + 1) -+ */ -+ freq_output = div_u64(MLXBF_GIGE_P1_FREQ_REFERENCE * core_f, -+ MLXBF_GIGE_P1_CLK_CONST); -+ freq_output = div_u64(freq_output, (core_r + 1) * (core_od + 1)); -+ -+ return freq_output; -+} -+ -+static void mlxbf_gige_ugl_static_config(struct mlxbf_gige *priv) -+{ -+ u32 val, p1clk_mhz; -+ u32 const_factor; -+ u64 p1clk; -+ -+ /* p1clk is the PLU clock in Hz */ -+ p1clk = mlxbf_gige_calculate_p1clk(priv); -+ -+ /* get p1clk in MHz */ -+ p1clk_mhz = div_u64(p1clk, 1000000); -+ -+ /* Multiply the p1clk clock by 12 according to HW requirements */ -+ const_factor = p1clk_mhz * MLXBF_GIGE_P1CLK_MULT_FACTOR; -+ -+ /* ugl_cr_bridge_desc */ -+ val = readl(priv->plu_base + MLXBF_GIGE_UGL_CR_BRIDGE_DESC); -+ val &= ~MLXBF_GIGE_UGL_CR_BRIDGE_ALL_MASK; -+ val |= FIELD_PREP(MLXBF_GIGE_UGL_CR_BRIDGE_SETUP_MASK, -+ MLXBF_GIGE_UGL_CR_BRIDGE_SETUP_VAL(const_factor)); -+ val |= FIELD_PREP(MLXBF_GIGE_UGL_CR_BRIDGE_PULSE_MASK, -+ MLXBF_GIGE_UGL_CR_BRIDGE_PULSE_VAL(const_factor)); -+ val |= FIELD_PREP(MLXBF_GIGE_UGL_CR_BRIDGE_HOLD_MASK, -+ MLXBF_GIGE_UGL_CR_BRIDGE_HOLD_VAL(const_factor)); -+ writel(val, priv->plu_base + MLXBF_GIGE_UGL_CR_BRIDGE_DESC); -+ -+ /* pll1x_fsm_counters */ -+ val = MLXBF_GIGE_PLL1X_FSM_DEFAULT_VAL(const_factor); -+ writel(val, priv->plu_base + MLXBF_GIGE_PLL1X_FSM_DEFAULT_CYCLES); -+ -+ val = MLXBF_GIGE_PLL1X_FSM_SLEEP_VAL(const_factor); -+ writel(val, priv->plu_base + MLXBF_GIGE_PLL1X_FSM_SLEEP_CYCLES); -+ -+ val = MLXBF_GIGE_PLL1X_FSM_RCAL_FLOW_VAL(const_factor); -+ writel(val, priv->plu_base + MLXBF_GIGE_PLL1X_FSM_RCAL_FLOW_CYCLES); -+ -+ val = MLXBF_GIGE_PLL1X_FSM_CAL_FLOW_VAL(const_factor); -+ writel(val, priv->plu_base + MLXBF_GIGE_PLL1X_FSM_CAL_FLOW_CYCLES); -+ -+ val = readl(priv->plu_base + MLXBF_GIGE_PLL1X_FSM_LOCKDET_STS_CYCLES); -+ val &= ~MLXBF_GIGE_PLL1X_FSM_LOCKDET_STS_MASK; -+ val |= FIELD_PREP(MLXBF_GIGE_PLL1X_FSM_LOCKDET_STS_MASK, -+ MLXBF_GIGE_PLL1X_FSM_LOCKDET_STS_VAL(const_factor)); -+ writel(val, priv->plu_base + MLXBF_GIGE_PLL1X_FSM_LOCKDET_STS_CYCLES); -+ -+ /* tx_fsm_counters */ -+ val = MLXBF_GIGE_TX_FSM_DEFAULT_VAL(const_factor); -+ writel(val, priv->plu_base + MLXBF_GIGE_TX_FSM_DEFAULT_CYCLES); -+ -+ val = MLXBF_GIGE_TX_FSM_SLEEP_VAL(const_factor); -+ writel(val, priv->plu_base + MLXBF_GIGE_TX_FSM_SLEEP_CYCLES); -+ -+ val = MLXBF_GIGE_TX_FSM_POWERUP_VAL(const_factor); -+ writel(val, priv->plu_base + MLXBF_GIGE_TX_FSM_POWERUP_CYCLES); -+ -+ val = MLXBF_GIGE_TX_FSM_CAL_FLOW_VAL(const_factor); -+ writel(val, priv->plu_base + MLXBF_GIGE_TX_FSM_CAL_FLOW_CYCLES); -+ -+ val = readl(priv->plu_base + MLXBF_GIGE_TX_FSM_CAL_ABORT_CYCLES); -+ val &= ~MLXBF_GIGE_TX_FSM_CAL_ABORT_MASK; -+ val |= FIELD_PREP(MLXBF_GIGE_TX_FSM_CAL_ABORT_MASK, -+ MLXBF_GIGE_TX_FSM_CAL_ABORT_VAL(const_factor)); -+ writel(val, priv->plu_base + MLXBF_GIGE_TX_FSM_CAL_ABORT_CYCLES); -+ -+ /* rx_fsm_counters */ -+ val = MLXBF_GIGE_RX_FSM_DEFAULT_VAL(const_factor); -+ writel(val, priv->plu_base + MLXBF_GIGE_RX_FSM_DEFAULT_CYCLES); -+ -+ val = MLXBF_GIGE_RX_FSM_SLEEP_VAL(const_factor); -+ writel(val, priv->plu_base + MLXBF_GIGE_RX_FSM_SLEEP_CYCLES); -+ -+ val = MLXBF_GIGE_RX_FSM_POWERUP_VAL(const_factor); -+ writel(val, priv->plu_base + MLXBF_GIGE_RX_FSM_POWERUP_CYCLES); -+ -+ val = MLXBF_GIGE_RX_FSM_TERM_VAL(const_factor); -+ writel(val, priv->plu_base + MLXBF_GIGE_RX_FSM_TERM_CYCLES); -+ -+ val = MLXBF_GIGE_RX_FSM_CAL_FLOW_VAL(const_factor); -+ writel(val, priv->plu_base + MLXBF_GIGE_RX_FSM_CAL_FLOW_CYCLES); -+ -+ val = MLXBF_GIGE_RX_FSM_CAL_ABORT_VAL(const_factor); -+ writel(val, priv->plu_base + MLXBF_GIGE_RX_FSM_CAL_ABORT_CYCLES); -+ -+ val = MLXBF_GIGE_RX_FSM_EQ_FLOW_VAL(const_factor); -+ writel(val, priv->plu_base + MLXBF_GIGE_RX_FSM_EQ_FLOW_CYCLES); -+ -+ val = MLXBF_GIGE_RX_FSM_EQ_ABORT_VAL(const_factor); -+ writel(val, priv->plu_base + MLXBF_GIGE_RX_FSM_EQ_ABORT_CYCLES); -+ -+ val = MLXBF_GIGE_RX_FSM_EOM_FLOW_VAL(const_factor); -+ writel(val, priv->plu_base + MLXBF_GIGE_RX_FSM_EOM_FLOW_CYCLES); -+ -+ val = readl(priv->plu_base + MLXBF_GIGE_RX_FSM_CDR_LOCK_CYCLES); -+ val &= ~MLXBF_GIGE_RX_FSM_CDR_LOCK_MASK; -+ val |= FIELD_PREP(MLXBF_GIGE_RX_FSM_CDR_LOCK_MASK, -+ MLXBF_GIGE_RX_FSM_CDR_LOCK_VAL(const_factor)); -+ writel(val, priv->plu_base + MLXBF_GIGE_RX_FSM_CDR_LOCK_CYCLES); -+ -+ /* periodic_flows_timer_max_value */ -+ val = readl(priv->plu_base + MLXBF_GIGE_PERIOD_FLOWS_TIMER_MAX); -+ val &= ~MLXBF_GIGE_PERIOD_FLOWS_TIMER_MAX_MASK; -+ val |= FIELD_PREP(MLXBF_GIGE_PERIOD_FLOWS_TIMER_MAX_MASK, -+ MLXBF_GIGE_PERIOD_FLOWS_TIMER_MAX_VAL(const_factor)); -+ writel(val, priv->plu_base + MLXBF_GIGE_PERIOD_FLOWS_TIMER_MAX); -+ -+ /* plltop.center.iddq_cycles */ -+ val = readl(priv->plu_base + MLXBF_GIGE_PLL_IDDQ_CYCLES); -+ val &= ~MLXBF_GIGE_PLL_IDDQ_CYCLES_MASK; -+ val |= FIELD_PREP(MLXBF_GIGE_PLL_IDDQ_CYCLES_MASK, -+ MLXBF_GIGE_PLL_IDDQ_CYCLES_VAL(const_factor)); -+ writel(val, priv->plu_base + MLXBF_GIGE_PLL_IDDQ_CYCLES); -+ -+ /* lanetop.center.iddq_cycles */ -+ val = readl(priv->plu_base + MLXBF_GIGE_LANE_IDDQ_CYCLES); -+ val &= ~MLXBF_GIGE_LANE_IDDQ_CYCLES_MASK; -+ val |= FIELD_PREP(MLXBF_GIGE_LANE_IDDQ_CYCLES_MASK, -+ MLXBF_GIGE_LANE_IDDQ_CYCLES_VAL(const_factor)); -+ writel(val, priv->plu_base + MLXBF_GIGE_LANE_IDDQ_CYCLES); -+ -+ /* lanetop.center.power_governor0 */ -+ val = FIELD_PREP(MLXBF_GIGE_LANE_PWR_GOV0_RISE_MASK, -+ MLXBF_GIGE_LANE_PWR_GOV0_RISE_VAL(const_factor)); -+ val |= FIELD_PREP(MLXBF_GIGE_LANE_PWR_GOV0_FALL_MASK, -+ MLXBF_GIGE_LANE_PWR_GOV0_FALL_VAL(const_factor)); -+ writel(val, priv->plu_base + MLXBF_GIGE_LANE_PWR_GOV0); -+} -+ -+static int mlxbf_gige_uphy_gw_write(struct mlxbf_gige *priv, u16 addr, -+ u16 data, bool is_pll) -+{ -+ u32 cmd, val; -+ int ret; -+ -+ cmd = MLXBF_GIGE_UPHY_GW_CREATE_CMD(addr, data, 0, is_pll); -+ -+ /* Send PLL or lane GW write request */ -+ writel(cmd, priv->plu_base + MLXBF_GIGE_UPHY_GW(is_pll)); -+ -+ /* If the poll times out, drop the request */ -+ ret = readl_poll_timeout_atomic(priv->plu_base + -+ MLXBF_GIGE_UPHY_GW(is_pll), -+ val, -+ !(val & MLXBF_GIGE_UPHY_GW_BUSY_MASK(is_pll)), -+ 5, 1000000); -+ if (ret) -+ dev_dbg(priv->dev, "Failed to send GW write request\n"); -+ -+ return ret; -+} -+ -+static int mlxbf_gige_uphy_gw_read(struct mlxbf_gige *priv, u16 addr, -+ bool is_pll) -+{ -+ u32 cmd, val; -+ int ret; -+ -+ cmd = MLXBF_GIGE_UPHY_GW_CREATE_CMD(addr, 0, 1, is_pll); -+ -+ /* Send PLL or lane GW read request */ -+ writel(cmd, priv->plu_base + MLXBF_GIGE_UPHY_GW(is_pll)); -+ -+ /* If the poll times out, drop the request */ -+ ret = readl_poll_timeout_atomic(priv->plu_base + -+ MLXBF_GIGE_UPHY_GW(is_pll), -+ val, -+ !(val & MLXBF_GIGE_UPHY_GW_BUSY_MASK(is_pll)), -+ 5, 1000000); -+ if (ret) { -+ dev_dbg(priv->dev, "Failed to send GW read request\n"); -+ return ret; -+ } -+ -+ val = readl(priv->plu_base + MLXBF_GIGE_UPHY_GW_DESC0(is_pll)); -+ val &= MLXBF_GIGE_UPHY_GW_DESC0_DATA_MASK(is_pll); -+ -+ return val; -+} -+ -+static int mlxbf_gige_load_uphy_clm_init_pkg(struct mlxbf_gige *priv) -+{ -+ int ret = 0; -+ int i; -+ -+ for (i = 0; i < MLXBF_GIGE_UPHY_CLM_INIT_NUM_ENTRIES; i++) { -+ ret = mlxbf_gige_uphy_gw_write(priv, -+ mlxbf_gige_clm_init[i].addr, -+ mlxbf_gige_clm_init[i].wdata, -+ true); -+ if (ret) { -+ dev_dbg(priv->dev, "Failed to load clm init pkg\n"); -+ return ret; -+ } -+ } -+ -+ return ret; -+} -+ -+static int mlxbf_gige_load_clm_production_fuses(struct mlxbf_gige *priv) -+{ -+ u8 bg_trim_room; -+ u8 cvb_trim_room; -+ u8 speedo_room; -+ int ret; -+ u32 val; -+ -+ val = readl(priv->fuse_gw_io); -+ bg_trim_room = (val & MLXBF_GIGE_YU_BG_TRIM_ROOM_MASK) >> -+ MLXBF_GIGE_YU_BG_TRIM_ROOM_SHIFT; -+ cvb_trim_room = (val & MLXBF_GIGE_YU_CVB_TRIM_ROOM_MASK) >> -+ MLXBF_GIGE_YU_CVB_TRIM_ROOM_SHIFT; -+ speedo_room = (val & MLXBF_GIGE_YU_SPEEDO_ROOM_MASK) >> -+ MLXBF_GIGE_YU_SPEEDO_ROOM_SHIFT; -+ -+ val = ((bg_trim_room >> MLXBF_GIGE_YU_FUSE_VALID_SHIFT) << -+ MLXBF_GIGE_PLL_MGMT_BGAP_FUSE_CTRL_BG_TRIM_VLD_SHIFT); -+ val |= ((cvb_trim_room >> MLXBF_GIGE_YU_FUSE_VALID_SHIFT) << -+ MLXBF_GIGE_PLL_MGMT_BGAP_FUSE_CTRL_CVB_TRIM_VLD_SHIFT); -+ val |= ((speedo_room >> MLXBF_GIGE_YU_FUSE_VALID_SHIFT) << -+ MLXBF_GIGE_PLL_MGMT_BGAP_FUSE_CTRL_SPEEDO_VLD_SHIFT); -+ val |= ((bg_trim_room & MLXBF_GIGE_YU_FUSE_MASK) << -+ MLXBF_GIGE_PLL_MGMT_BGAP_FUSE_CTRL_BG_TRIM_SHIFT); -+ val |= ((cvb_trim_room & MLXBF_GIGE_YU_FUSE_MASK) << -+ MLXBF_GIGE_PLL_MGMT_BGAP_FUSE_CTRL_CVB_TRIM_SHIFT); -+ val |= ((speedo_room & MLXBF_GIGE_YU_FUSE_MASK) << -+ MLXBF_GIGE_PLL_MGMT_BGAP_FUSE_CTRL_SPEEDO_SHIFT); -+ -+ ret = mlxbf_gige_uphy_gw_write(priv, MLXBF_GIGE_MGMT_BGAP_FUSE_CTRL_ADDR, val, true); -+ if (ret) -+ dev_dbg(priv->dev, "Failed to load clm production fuses\n"); -+ -+ return ret; -+} -+ -+static int mlxbf_gige_init_pll(struct mlxbf_gige *priv) -+{ -+ int ret; -+ -+ ret = mlxbf_gige_load_uphy_clm_init_pkg(priv); -+ if (ret) -+ return ret; -+ -+ ret = mlxbf_gige_load_clm_production_fuses(priv); -+ -+ return ret; -+} -+ -+static int mlxbf_gige_lock_pll(struct mlxbf_gige *priv) -+{ -+ int ret; -+ u32 val; -+ -+ /* plltop.center.uphy_pll_rst_reg_ */ -+ val = readl(priv->plu_base + MLXBF_GIGE_UPHY_PLL_RST_REG); -+ val |= MLXBF_GIGE_UPHY_PLL_RST_REG_MASK; -+ writel(val, priv->plu_base + MLXBF_GIGE_UPHY_PLL_RST_REG); -+ -+ /* cause_or.clrcause.bulk */ -+ val = readl(priv->plu_base + MLXBF_GIGE_PLL1X_CAUSE_CLRCAUSE_BULK); -+ val |= MLXBF_GIGE_PLL1X_CAUSE_CLRCAUSE_BULK_MASK; -+ writel(val, priv->plu_base + MLXBF_GIGE_PLL1X_CAUSE_CLRCAUSE_BULK); -+ -+ writel(0, priv->plu_base + MLXBF_GIGE_PLL_CAL); -+ -+ /* Stop polling when fsm state is UGL_PLL1X_FSM_STATE_SLEEP */ -+ ret = readl_poll_timeout_atomic(priv->plu_base + -+ MLXBF_GIGE_PLL_FSM_CTRL, -+ val, (val == MLXBF_GIGE_UGL_PLL1X_FSM_STATE_SLEEP), -+ 5, 1000000); -+ if (ret) { -+ dev_dbg(priv->dev, "Polling timeout on fsm state sleep\n"); -+ return ret; -+ } -+ -+ udelay(MLXBF_GIGE_PLL_STAB_TIME); -+ -+ val = readl(priv->plu_base + MLXBF_GIGE_PLL_SLEEP_FW); -+ val |= MLXBF_GIGE_PLL_SLEEP_FW_MASK; -+ writel(val, priv->plu_base + MLXBF_GIGE_PLL_SLEEP_FW); -+ -+ udelay(MLXBF_GIGE_PLL_STAB_TIME); -+ writel(MLXBF_GIGE_PLL_RCAL_MASK, priv->plu_base + MLXBF_GIGE_PLL_RCAL); -+ -+ /* Stop polling when fsm state is UGL_PLL1X_FSM_STATE_IDLE */ -+ ret = readl_poll_timeout_atomic(priv->plu_base + -+ MLXBF_GIGE_PLL_FSM_CTRL, -+ val, (val == MLXBF_GIGE_UGL_PLL1X_FSM_STATE_IDLE), -+ 5, 1000000); -+ if (ret) { -+ dev_dbg(priv->dev, "Polling timeout on fsm state idle\n"); -+ return ret; -+ } -+ -+ val = readl(priv->plu_base + MLXBF_GIGE_PLL_SLEEP_FW); -+ val &= ~MLXBF_GIGE_PLL_SLEEP_FW_MASK; -+ writel(val, priv->plu_base + MLXBF_GIGE_PLL_SLEEP_FW); -+ -+ writel(MLXBF_GIGE_PLL_CAL_MASK, priv->plu_base + MLXBF_GIGE_PLL_CAL); -+ -+ /* Stop polling when cal_valid is different from 0 */ -+ ret = readl_poll_timeout_atomic(priv->plu_base + MLXBF_GIGE_PLL_CAL_VLD, -+ val, !!(val & MLXBF_GIGE_PLL_CAL_VLD_MASK), -+ 5, 1000000); -+ if (ret) { -+ dev_dbg(priv->dev, "Polling timeout on cal_valid\n"); -+ return ret; -+ } -+ -+ /* pll_enable */ -+ val = readl(priv->plu_base + MLXBF_GIGE_PLL_ENABLE); -+ val |= MLXBF_GIGE_PLL_ENABLE_MASK; -+ writel(val, priv->plu_base + MLXBF_GIGE_PLL_ENABLE); -+ -+ return ret; -+} -+ -+static void mlxbf_gige_get_lane_out_of_rst(struct mlxbf_gige *priv) -+{ -+ u32 val; -+ -+ val = readl(priv->plu_base + MLXBF_GIGE_LANE_RST_REG); -+ val |= MLXBF_GIGE_LANE_RST_REG_MASK; -+ writel(val, priv->plu_base + MLXBF_GIGE_LANE_RST_REG); -+} -+ -+static int mlxbf_gige_load_imem(struct mlxbf_gige *priv) -+{ -+ u16 csum_status; -+ int ret = 0; -+ int i; -+ -+ for (i = 0; i < MLXBF_GIGE_UPHY_DLM_IMEM_INIT_NUM_ENTRIES; i++) { -+ ret = mlxbf_gige_uphy_gw_write(priv, -+ mlxbf_gige_dlm_imem_init[i].addr, -+ mlxbf_gige_dlm_imem_init[i].wdata, -+ false); -+ if (ret) -+ return ret; -+ } -+ -+ /* Resets the internal counter for MLXBF_GIGE_DLM_IMEM_DATA_ADDR to base address */ -+ ret = mlxbf_gige_uphy_gw_write(priv, -+ mlxbf_gige_dlm_seq_imem_wr_en_init.addr, -+ mlxbf_gige_dlm_seq_imem_wr_en_init.wdata, -+ false); -+ if (ret) -+ return ret; -+ -+ /* HW increments the address MLXBF_GIGE_DLM_IMEM_DATA_ADDR internally. */ -+ for (i = 0; i < MLXBF_GIGE_UPHY_DLM_IMEM_DATA_NUM_ENTRIES; i++) { -+ ret = mlxbf_gige_uphy_gw_write(priv, -+ MLXBF_GIGE_LANE_IMEM_DATA_ADDR, -+ mlxbf_gige_dlm_imem_data[i].wdata, -+ false); -+ if (ret) -+ return ret; -+ } -+ -+ ret = mlxbf_gige_uphy_gw_write(priv, -+ mlxbf_gige_dlm_seq_imem_wr_dis_init.addr, -+ mlxbf_gige_dlm_seq_imem_wr_dis_init.wdata, -+ false); -+ if (ret) -+ return ret; -+ -+ ret = mlxbf_gige_uphy_gw_write(priv, -+ mlxbf_gige_dlm_seq_imem_csum_en.addr, -+ mlxbf_gige_dlm_seq_imem_csum_en.wdata, -+ false); -+ if (ret) -+ return ret; -+ -+ udelay(MLXBF_GIGE_PLL_DLM_IMEM_CSUM_TIMEOUT); -+ -+ ret = mlxbf_gige_uphy_gw_read(priv, MLXBF_GIGE_LANE_CSUM_STS_ADDR, false); -+ if (ret < 0) -+ return ret; -+ -+ csum_status = ((ret & MLXBF_GIGE_IMEM_CSUM_STATUS_MASK) >> -+ MLXBF_GIGE_IMEM_CSUM_STATUS_SHIFT); -+ -+ ret = mlxbf_gige_uphy_gw_write(priv, -+ mlxbf_gige_dlm_seq_imem_csum_dis.addr, -+ mlxbf_gige_dlm_seq_imem_csum_dis.wdata, -+ false); -+ if (ret) -+ return ret; -+ -+ if (csum_status != MLXBF_GIGE_IMEM_CSUM_RUN_AND_VALID) { -+ dev_err(priv->dev, "%s: invalid checksum\n", __func__); -+ -+ /* recovery flow */ -+ for (i = 0; i < MLXBF_GIGE_DLM_SEQ_IMEM_BMAP_CLR_NUM_ENTRIES; i++) { -+ mlxbf_gige_uphy_gw_write(priv, -+ mlxbf_gige_dlm_seq_imem_bmap_clr[i].addr, -+ mlxbf_gige_dlm_seq_imem_bmap_clr[i].wdata, -+ false); -+ } -+ -+ return MLXBF_GIGE_INVALID_IMEM_CSUM; -+ } -+ -+ return ret; -+} -+ -+static int mlxbf_gige_plu_tx_power_ctrl(struct mlxbf_gige *priv, bool is_pwr_on) -+{ -+ int ret = 0; -+ u32 val; -+ -+ val = readl(priv->plu_base + MLXBF_GIGE_LANE_TX_RATE_ID0_SPEED); -+ val &= ~MLXBF_GIGE_LANE_TX_SLEEP_VAL_MASK; -+ writel(val, priv->plu_base + MLXBF_GIGE_LANE_TX_RATE_ID0_SPEED); -+ -+ if (is_pwr_on) { -+ val = readl(priv->plu_base + MLXBF_GIGE_LANE_TX_DATA_EN); -+ val &= ~MLXBF_GIGE_LANE_TX_IDDQ_VAL_MASK; -+ writel(val, priv->plu_base + MLXBF_GIGE_LANE_TX_DATA_EN); -+ -+ val = readl(priv->plu_base + MLXBF_GIGE_PLU_POWERUP); -+ val |= MLXBF_GIGE_PLU_TX_POWERUP_MASK; -+ writel(val, priv->plu_base + MLXBF_GIGE_PLU_POWERUP); -+ } else { -+ val = readl(priv->plu_base + MLXBF_GIGE_PLU_POWERUP); -+ val &= ~MLXBF_GIGE_PLU_TX_POWERUP_MASK; -+ writel(val, priv->plu_base + MLXBF_GIGE_PLU_POWERUP); -+ -+ val = readl(priv->plu_base + MLXBF_GIGE_LANE_TX_DATA_EN); -+ val |= MLXBF_GIGE_LANE_TX_IDDQ_VAL_MASK; -+ writel(val, priv->plu_base + MLXBF_GIGE_LANE_TX_DATA_EN); -+ -+ ret = readl_poll_timeout_atomic(priv->plu_base + -+ MLXBF_GIGE_LANE_TX_FSM_CTRL, val, -+ ((val & MLXBF_GIGE_LANE_TX_FSM_PS_MASK) == MLXBF_GIGE_TX_FSM_IDDQ), -+ 5, 1000000); -+ if (ret) -+ dev_dbg(priv->dev, "Polling timeout on tx fsm iddq state\n"); -+ } -+ -+ return ret; -+} -+ -+static int mlxbf_gige_dlm_tx_init_pkg(struct mlxbf_gige *priv) -+{ -+ int ret = 0; -+ int i; -+ -+ for (i = 0; i < MLXBF_GIGE_DLM_TX_NUM_ENTRIES; i++) { -+ ret = mlxbf_gige_uphy_gw_write(priv, -+ mlxbf_gige_dlm_tx_init[i].addr, -+ mlxbf_gige_dlm_tx_init[i].wdata, -+ false); -+ if (ret) { -+ dev_dbg(priv->dev, "Failed to load dlm tx init pkg\n"); -+ return ret; -+ } -+ } -+ -+ return ret; -+} -+ -+static int mlxbf_gige_tx_lane_open(struct mlxbf_gige *priv) -+{ -+ u32 val; -+ int ret; -+ -+ /* Prepare the TX lane before opening it */ -+ -+ ret = mlxbf_gige_plu_tx_power_ctrl(priv, false); -+ if (ret) -+ return ret; -+ -+ /* Calibration of TX elastic buffer */ -+ val = readl(priv->plu_base + MLXBF_GIGE_LANE_TX_BITS_SWAP); -+ val &= ~MLXBF_GIGE_TX_EB_BLOCK_PUSH_DIST_MASK_MASK; -+ val |= MLXBF_GIGE_TX_EB_BLOCK_PUSH_DIST_MASK_VAL; -+ writel(val, priv->plu_base + MLXBF_GIGE_LANE_TX_BITS_SWAP); -+ -+ val = readl(priv->plu_base + MLXBF_GIGE_LANE_TX_DATA_EN); -+ val |= MLXBF_GIGE_LANE_TX_DATA_EN_MASK; -+ writel(val, priv->plu_base + MLXBF_GIGE_LANE_TX_DATA_EN); -+ -+ writel(MLXBF_GIGE_LANE_TX_CAL_MASK, priv->plu_base + MLXBF_GIGE_LANE_TX_CAL); -+ -+ val = readl(priv->plu_base + MLXBF_GIGE_LANE_TX_DATA_EN); -+ val &= ~MLXBF_GIGE_LANE_TX_RATE_ID_MASK; -+ writel(val, priv->plu_base + MLXBF_GIGE_LANE_TX_DATA_EN); -+ -+ val = readl(priv->plu_base + MLXBF_GIGE_LANE_TX_RATE_ID0_SPEED); -+ val &= ~MLXBF_GIGE_LANE_TX_RATE_ID0_SPEED_MASK; -+ writel(val, priv->plu_base + MLXBF_GIGE_LANE_TX_RATE_ID0_SPEED); -+ -+ /* Loading the DLM tx init package should be done before lane power on */ -+ ret = mlxbf_gige_dlm_tx_init_pkg(priv); -+ if (ret) -+ return ret; -+ -+ val = readl(priv->plu_base + MLXBF_GIGE_LANE_TX_BITS_SWAP); -+ val &= ~MLXBF_GIGE_LANE_TX_BITS_SWAP_MASK; -+ writel(val, priv->plu_base + MLXBF_GIGE_LANE_TX_BITS_SWAP); -+ -+ ret = mlxbf_gige_plu_tx_power_ctrl(priv, true); -+ if (ret) -+ return ret; -+ -+ /* After preparing the TX lane, open it for data transmission */ -+ -+ val = readl(priv->plu_base + MLXBF_GIGE_LANE_TX_BITS_SWAP); -+ val &= ~MLXBF_GIGE_TX_EB_BLOCK_PUSH_DIST_MASK_MASK; -+ writel(val, priv->plu_base + MLXBF_GIGE_LANE_TX_BITS_SWAP); -+ -+ ret = readl_poll_timeout_atomic(priv->plu_base + -+ MLXBF_GIGE_LANE_TX_FSM_CTRL, val, -+ ((val & MLXBF_GIGE_LANE_TX_FSM_PS_MASK) == MLXBF_GIGE_TX_DATA_EN), -+ 5, 1000000); -+ if (ret) { -+ dev_dbg(priv->dev, "Polling timeout on fsm tx data enable state\n"); -+ return ret; -+ } -+ -+ val = readl(priv->plu_base + MLXBF_GIGE_LANE_TX_DATA_EN); -+ val |= MLXBF_GIGE_LANE_TX_PERIODIC_CAL_EN_MASK; -+ writel(val, priv->plu_base + MLXBF_GIGE_LANE_TX_DATA_EN); -+ -+ return ret; -+} -+ -+static int mlxbf_gige_dlm_rx_init_pkg(struct mlxbf_gige *priv) -+{ -+ int ret = 0; -+ int i; -+ -+ for (i = 0; i < MLXBF_GIGE_DLM_RX_NUM_ENTRIES; i++) { -+ ret = mlxbf_gige_uphy_gw_write(priv, -+ mlxbf_gige_dlm_rx_init[i].addr, -+ mlxbf_gige_dlm_rx_init[i].wdata, -+ false); -+ if (ret) { -+ dev_dbg(priv->dev, "Failed to load dlm rx init pkg\n"); -+ return ret; -+ } -+ } -+ -+ return ret; -+} -+ -+static int mlxbf_gige_plu_rx_power_ctrl(struct mlxbf_gige *priv, bool is_pwr_on) -+{ -+ int ret = 0; -+ u32 val; -+ -+ val = readl(priv->plu_base + MLXBF_GIGE_LANE_RX_RATE_ID); -+ val &= ~MLXBF_GIGE_LANE_RX_SLEEP_VAL_MASK; -+ writel(val, priv->plu_base + MLXBF_GIGE_LANE_RX_RATE_ID); -+ -+ if (is_pwr_on) { -+ val = readl(priv->plu_base + MLXBF_GIGE_LANE_RX_RATE_ID); -+ val &= ~MLXBF_GIGE_LANE_RX_IDDQ_VAL_MASK; -+ writel(val, priv->plu_base + MLXBF_GIGE_LANE_RX_RATE_ID); -+ -+ val = readl(priv->plu_base + MLXBF_GIGE_PLU_POWERUP); -+ val |= MLXBF_GIGE_PLU_RX_POWERUP_MASK; -+ writel(val, priv->plu_base + MLXBF_GIGE_PLU_POWERUP); -+ } else { -+ /* Enable HW watchdogs. */ -+ val = readl(priv->plu_base + MLXBF_GIGE_LANE_RX_EQ_DONE_TIMER_EN); -+ val |= MLXBF_GIGE_LANE_RX_EQ_DONE_TIMER_EN_MASK; -+ val |= MLXBF_GIGE_LANE_RX_CAL_DONE_TIMER_EN_MASK; -+ writel(val, priv->plu_base + MLXBF_GIGE_LANE_RX_EQ_DONE_TIMER_EN); -+ -+ val = readl(priv->plu_base + MLXBF_GIGE_PLU_POWERUP); -+ val &= ~MLXBF_GIGE_PLU_RX_POWERUP_MASK; -+ writel(val, priv->plu_base + MLXBF_GIGE_PLU_POWERUP); -+ -+ val = readl(priv->plu_base + MLXBF_GIGE_LANE_RX_RATE_ID); -+ val |= MLXBF_GIGE_LANE_RX_IDDQ_VAL_MASK; -+ writel(val, priv->plu_base + MLXBF_GIGE_LANE_RX_RATE_ID); -+ -+ ret = readl_poll_timeout_atomic(priv->plu_base + -+ MLXBF_GIGE_LANE_RX_FSM_CTRL, val, -+ ((val & MLXBF_GIGE_LANE_RX_FSM_PS_MASK) == MLXBF_GIGE_RX_FSM_IDDQ), -+ 5, 1000000); -+ if (ret) { -+ dev_dbg(priv->dev, "Polling timeout on rx fsm iddq state\n"); -+ return ret; -+ } -+ -+ val = readl(priv->plu_base + MLXBF_GIGE_LANE_RX_EQ_DONE_TIMER_EN); -+ val &= ~MLXBF_GIGE_LANE_RX_EQ_DONE_TIMER_EN_MASK; -+ val &= ~MLXBF_GIGE_LANE_RX_CAL_DONE_TIMER_EN_MASK; -+ writel(val, priv->plu_base + MLXBF_GIGE_LANE_RX_EQ_DONE_TIMER_EN); -+ } -+ -+ return ret; -+} -+ -+static int mlxbf_gige_rx_lane_open(struct mlxbf_gige *priv) -+{ -+ u32 val; -+ int ret; -+ -+ ret = mlxbf_gige_plu_rx_power_ctrl(priv, false); -+ if (ret) -+ return ret; -+ -+ val = readl(priv->plu_base + MLXBF_GIGE_LANE_RX_RATE_ID); -+ val &= ~MLXBF_GIGE_LANE_RX_RATE_ID_MASK; -+ writel(val, priv->plu_base + MLXBF_GIGE_LANE_RX_RATE_ID); -+ -+ val = readl(priv->plu_base + MLXBF_GIGE_LANE_RX_SYNC_FIFO_POP); -+ val &= ~MLXBF_GIGE_LANE_RX_SYNC_FIFO_POP_RDY_CHICKEN_MASK; -+ val &= ~MLXBF_GIGE_LANE_RX_DATA_SPLIT_LSB_VLD_CHICKEN_MASK; -+ writel(val, priv->plu_base + MLXBF_GIGE_LANE_RX_SYNC_FIFO_POP); -+ -+ val = readl(priv->plu_base + MLXBF_GIGE_LANE_RX_RATE_ID); -+ val &= ~MLXBF_GIGE_LANE_RX_RATE_ID0_SPEED_MASK; -+ writel(val, priv->plu_base + MLXBF_GIGE_LANE_RX_RATE_ID); -+ -+ ret = mlxbf_gige_dlm_rx_init_pkg(priv); -+ if (ret) -+ return ret; -+ -+ writel(MLXBF_GIGE_LANE_RX_CAL_MASK, priv->plu_base + MLXBF_GIGE_LANE_RX_CAL); -+ -+ val = readl(priv->plu_base + MLXBF_GIGE_LANE_RX_SYNC_FIFO_POP); -+ val &= ~MLXBF_GIGE_LANE_RX_CDR_RESET_REG_MASK; -+ val |= MLXBF_GIGE_LANE_RX_CDR_EN_MASK; -+ val |= MLXBF_GIGE_LANE_RX_DATA_EN_MASK; -+ writel(val, priv->plu_base + MLXBF_GIGE_LANE_RX_SYNC_FIFO_POP); -+ -+ val = readl(priv->plu_base + MLXBF_GIGE_LANE_RX_EQ_TRAIN); -+ val &= ~MLXBF_GIGE_LANE_RX_EQ_TRAIN_MASK; -+ val |= MLXBF_GIGE_LANE_RX_EQ_TRAIN_VAL; -+ writel(val, priv->plu_base + MLXBF_GIGE_LANE_RX_EQ_TRAIN); -+ -+ ret = mlxbf_gige_plu_rx_power_ctrl(priv, true); -+ if (ret) -+ return ret; -+ -+ ret = readl_poll_timeout_atomic(priv->plu_base + -+ MLXBF_GIGE_LANE_RX_FSM_CTRL, val, -+ ((val & MLXBF_GIGE_LANE_RX_FSM_PS_MASK) == MLXBF_GIGE_RX_FSM_ACTIVE), -+ 5, 1000000); -+ if (ret) -+ dev_dbg(priv->dev, "Polling timeout on rx fsm active state\n"); -+ -+ return ret; -+} -+ -+static bool mlxbf_gige_is_uphy_ready(struct mlxbf_gige *priv) -+{ -+ u32 val; -+ -+ val = readl(priv->plu_base + MLXBF_GIGE_LANE_TX_FSM_CTRL); -+ if ((val & MLXBF_GIGE_LANE_TX_FSM_PS_MASK) != MLXBF_GIGE_TX_DATA_EN) -+ return false; -+ -+ val = readl(priv->plu_base + MLXBF_GIGE_LANE_RX_FSM_CTRL); -+ if ((val & MLXBF_GIGE_LANE_RX_FSM_PS_MASK) != MLXBF_GIGE_RX_FSM_ACTIVE) -+ return false; -+ -+ return true; -+} -+ -+int mlxbf_gige_config_uphy(struct mlxbf_gige *priv) -+{ -+ struct platform_device *pdev = priv->pdev; -+ struct device *dev = &pdev->dev; -+ int ret = 0; -+ -+ priv->fuse_gw_io = devm_platform_ioremap_resource(pdev, MLXBF_GIGE_RES_FUSE_GW); -+ if (IS_ERR(priv->fuse_gw_io)) -+ return PTR_ERR(priv->fuse_gw_io); -+ -+ if (mlxbf_gige_is_uphy_ready(priv)) -+ return 0; -+ -+ mlxbf_gige_ugl_static_config(priv); -+ ret = mlxbf_gige_init_pll(priv); -+ if (ret) { -+ dev_err(dev, "%s: Failed to initialize PLL\n", __func__); -+ return ret; -+ } -+ -+ ret = mlxbf_gige_lock_pll(priv); -+ if (ret) { -+ dev_err(dev, "%s: Failed to lock PLL\n", __func__); -+ return ret; -+ } -+ -+ /* Due to hardware design issue, we need to get the lanes out of reset -+ * before configuring the imem. -+ */ -+ mlxbf_gige_get_lane_out_of_rst(priv); -+ ret = mlxbf_gige_load_imem(priv); -+ if (ret) { -+ dev_err(dev, "%s: Failed to load imem\n", __func__); -+ return ret; -+ } -+ -+ ret = mlxbf_gige_tx_lane_open(priv); -+ if (ret) { -+ dev_err(dev, "%s: Failed to open tx lane\n", __func__); -+ return ret; -+ } -+ -+ ret = mlxbf_gige_rx_lane_open(priv); -+ if (ret) -+ dev_err(dev, "%s: Failed to open rx lane\n", __func__); -+ -+ return ret; -+} -diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_uphy.h b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_uphy.h -new file mode 100644 -index 000000000..a32be2407 ---- /dev/null -+++ b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_uphy.h -@@ -0,0 +1,398 @@ -+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */ -+ -+/* UPHY support for Mellanox Gigabit Ethernet driver -+ * -+ * Copyright (C) 2022 NVIDIA CORPORATION & AFFILIATES -+ */ -+ -+#ifndef __MLXBF_GIGE_UPHY_H__ -+#define __MLXBF_GIGE_UPHY_H__ -+ -+#include -+ -+/* Some registers' values depend on the p1clk clock. The following -+ * formula applies: -+ * ((time_in_ns*const_factor)/MLXBF_GIGE_TIME_FACTOR_TO_USEC) -+ */ -+#define MLXBF_GIGE_TIME_FACTOR_TO_USEC 10000 -+ -+/* All addresses represent the offset from the base PLU address */ -+ -+#define MLXBF_GIGE_PLU_POWERUP 0x488 -+#define MLXBF_GIGE_PLU_TX_POWERUP_MASK GENMASK(28, 28) -+#define MLXBF_GIGE_PLU_RX_POWERUP_MASK GENMASK(27, 27) -+ -+#define MLXBF_GIGE_LANE_CFG_FLAT0_BASE 0x23000 -+#define MLXBF_GIGE_AE_SYS_IMEM_RAM_DATA_CTRL_WDATA 0x23ef8 -+#define MLXBF_GIGE_AE_SYS_IMEM_RAM_STAT_IMEM_CSUM_STS 0x23f00 -+#define MLXBF_GIGE_IMEM_CSUM_STATUS_MASK GENMASK(6, 5) -+#define MLXBF_GIGE_IMEM_CSUM_STATUS_SHIFT 5 -+ -+#define MLXBF_GIGE_PLL_CFG_FLAT0_BASE 0x25000 -+#define MLXBF_GIGE_PLL_CFG_FLAT0_MGMT_BGAP_FUSE_CTRL 0x251d8 -+#define MLXBF_GIGE_PLL_MGMT_BGAP_FUSE_CTRL_BG_TRIM_SHIFT 0 -+#define MLXBF_GIGE_PLL_MGMT_BGAP_FUSE_CTRL_CVB_TRIM_SHIFT 4 -+#define MLXBF_GIGE_PLL_MGMT_BGAP_FUSE_CTRL_SPEEDO_SHIFT 8 -+#define MLXBF_GIGE_PLL_MGMT_BGAP_FUSE_CTRL_BG_TRIM_VLD_SHIFT 12 -+#define MLXBF_GIGE_PLL_MGMT_BGAP_FUSE_CTRL_CVB_TRIM_VLD_SHIFT 13 -+#define MLXBF_GIGE_PLL_MGMT_BGAP_FUSE_CTRL_SPEEDO_VLD_SHIFT 14 -+ -+#define MLXBF_GIGE_LANE_TX_FSM_CTRL 0x26000 -+#define MLXBF_GIGE_LANE_TX_FSM_PS_MASK GENMASK(3, 0) -+ -+#define MLXBF_GIGE_LANE_TX_BITS_SWAP 0x2600c -+#define MLXBF_GIGE_TX_EB_BLOCK_PUSH_DIST_MASK_MASK GENMASK(20, 16) -+#define MLXBF_GIGE_TX_EB_BLOCK_PUSH_DIST_MASK_VAL \ -+ FIELD_PREP(MLXBF_GIGE_TX_EB_BLOCK_PUSH_DIST_MASK_MASK, 0x3) -+#define MLXBF_GIGE_LANE_TX_BITS_SWAP_MASK GENMASK(0, 0) -+ -+#define MLXBF_GIGE_LANE_TX_DATA_EN 0x26010 -+#define MLXBF_GIGE_LANE_TX_RATE_ID_MASK GENMASK(30, 28) -+#define MLXBF_GIGE_LANE_TX_DATA_EN_MASK GENMASK(23, 23) -+#define MLXBF_GIGE_LANE_TX_IDDQ_VAL_MASK GENMASK(21, 21) -+#define MLXBF_GIGE_LANE_TX_PERIODIC_CAL_EN_MASK GENMASK(17, 17) -+ -+#define MLXBF_GIGE_LANE_TX_RATE_ID0_SPEED 0x26014 -+#define MLXBF_GIGE_LANE_TX_SLEEP_VAL_MASK GENMASK(9, 8) -+#define MLXBF_GIGE_LANE_TX_RATE_ID0_SPEED_MASK GENMASK(2, 0) -+ -+#define MLXBF_GIGE_LANE_TX_CAL 0x26018 -+#define MLXBF_GIGE_LANE_TX_CAL_MASK GENMASK(0, 0) -+ -+#define MLXBF_GIGE_LANE_RX_FSM_CTRL 0x26040 -+#define MLXBF_GIGE_LANE_RX_FSM_PS_MASK GENMASK(3, 0) -+ -+#define MLXBF_GIGE_LANE_RX_EQ_DONE_TIMER_EN 0x26054 -+#define MLXBF_GIGE_LANE_RX_EQ_DONE_TIMER_EN_MASK GENMASK(31, 31) -+#define MLXBF_GIGE_LANE_RX_CAL_DONE_TIMER_EN_MASK GENMASK(30, 30) -+ -+#define MLXBF_GIGE_LANE_RX_RATE_ID 0x26058 -+#define MLXBF_GIGE_LANE_RX_RATE_ID0_SPEED_MASK GENMASK(18, 16) -+#define MLXBF_GIGE_LANE_RX_RATE_ID_MASK GENMASK(14, 12) -+#define MLXBF_GIGE_LANE_RX_SLEEP_VAL_MASK GENMASK(7, 6) -+#define MLXBF_GIGE_LANE_RX_IDDQ_VAL_MASK GENMASK(4, 4) -+ -+#define MLXBF_GIGE_LANE_RX_CAL 0x2605c -+#define MLXBF_GIGE_LANE_RX_CAL_MASK GENMASK(0, 0) -+ -+#define MLXBF_GIGE_LANE_RX_SYNC_FIFO_POP 0x26060 -+#define MLXBF_GIGE_LANE_RX_DATA_SPLIT_LSB_VLD_CHICKEN_MASK GENMASK(5, 5) -+#define MLXBF_GIGE_LANE_RX_SYNC_FIFO_POP_RDY_CHICKEN_MASK GENMASK(4, 4) -+#define MLXBF_GIGE_LANE_RX_CDR_RESET_REG_MASK GENMASK(3, 3) -+#define MLXBF_GIGE_LANE_RX_CDR_EN_MASK GENMASK(2, 2) -+#define MLXBF_GIGE_LANE_RX_DATA_EN_MASK GENMASK(1, 1) -+ -+#define MLXBF_GIGE_LANE_RX_EQ_TRAIN 0x26064 -+#define MLXBF_GIGE_LANE_RX_EQ_TRAIN_MASK GENMASK(2, 0) -+#define MLXBF_GIGE_LANE_RX_EQ_TRAIN_VAL \ -+ FIELD_PREP(MLXBF_GIGE_LANE_RX_EQ_TRAIN_MASK, 0x3) -+ -+#define MLXBF_GIGE_LANE_GW 0x26100 -+#define MLXBF_GIGE_LANE_GW_ADDR_MASK GENMASK(10, 1) -+#define MLXBF_GIGE_LANE_GW_RW_MASK GENMASK(11, 11) -+#define MLXBF_GIGE_LANE_GW_DATA_MASK GENMASK(27, 12) -+#define MLXBF_GIGE_LANE_GW_DATA_EN_MASK GENMASK(28, 28) -+#define MLXBF_GIGE_LANE_GW_BUSY_MASK GENMASK(30, 30) -+#define MLXBF_GIGE_LANE_GW_ADDR_SHIFT 1 -+#define MLXBF_GIGE_LANE_GW_DESC0 0x2610c -+#define MLXBF_GIGE_LANE_GW_DESC0_DATA_MASK GENMASK(15, 0) -+ -+#define MLXBF_GIGE_TX_FSM_DEFAULT_CYCLES 0x26600 -+#define MLXBF_GIGE_TX_FSM_DEFAULT_VAL(const_factor) \ -+ ((200 * (const_factor)) / MLXBF_GIGE_TIME_FACTOR_TO_USEC) -+ -+#define MLXBF_GIGE_TX_FSM_SLEEP_CYCLES 0x26604 -+#define MLXBF_GIGE_TX_FSM_SLEEP_VAL(const_factor) \ -+ ((1000 * (const_factor)) / MLXBF_GIGE_TIME_FACTOR_TO_USEC) -+ -+#define MLXBF_GIGE_TX_FSM_POWERUP_CYCLES 0x26608 -+#define MLXBF_GIGE_TX_FSM_POWERUP_VAL(const_factor) \ -+ ((10000 * (const_factor)) / MLXBF_GIGE_TIME_FACTOR_TO_USEC) -+ -+#define MLXBF_GIGE_TX_FSM_CAL_FLOW_CYCLES 0x2660c -+#define MLXBF_GIGE_TX_FSM_CAL_FLOW_VAL(const_factor) \ -+ ((200000 * (const_factor)) / MLXBF_GIGE_TIME_FACTOR_TO_USEC) -+ -+#define MLXBF_GIGE_TX_FSM_CAL_ABORT_CYCLES 0x26610 -+#define MLXBF_GIGE_TX_FSM_CAL_ABORT_VAL(const_factor) \ -+ ((4000 * (const_factor)) / MLXBF_GIGE_TIME_FACTOR_TO_USEC) -+#define MLXBF_GIGE_TX_FSM_CAL_ABORT_MASK GENMASK(18, 0) -+ -+#define MLXBF_GIGE_RX_FSM_DEFAULT_CYCLES 0x26614 -+#define MLXBF_GIGE_RX_FSM_DEFAULT_VAL(const_factor) \ -+ ((200 * (const_factor)) / MLXBF_GIGE_TIME_FACTOR_TO_USEC) -+ -+#define MLXBF_GIGE_RX_FSM_SLEEP_CYCLES 0x26618 -+#define MLXBF_GIGE_RX_FSM_SLEEP_VAL(const_factor) \ -+ ((1000 * (const_factor)) / MLXBF_GIGE_TIME_FACTOR_TO_USEC) -+ -+#define MLXBF_GIGE_RX_FSM_POWERUP_CYCLES 0x2661c -+#define MLXBF_GIGE_RX_FSM_POWERUP_VAL(const_factor) \ -+ ((10000 * (const_factor)) / MLXBF_GIGE_TIME_FACTOR_TO_USEC) -+ -+#define MLXBF_GIGE_RX_FSM_TERM_CYCLES 0x26620 -+#define MLXBF_GIGE_RX_FSM_TERM_VAL(const_factor) \ -+ ((200000 * (const_factor)) / MLXBF_GIGE_TIME_FACTOR_TO_USEC) -+ -+#define MLXBF_GIGE_RX_FSM_CAL_FLOW_CYCLES 0x26624 -+#define MLXBF_GIGE_RX_FSM_CAL_FLOW_VAL(const_factor) \ -+ ((200000 * (const_factor)) / MLXBF_GIGE_TIME_FACTOR_TO_USEC) -+ -+#define MLXBF_GIGE_RX_FSM_CAL_ABORT_CYCLES 0x26628 -+#define MLXBF_GIGE_RX_FSM_CAL_ABORT_VAL(const_factor) \ -+ ((4000 * (const_factor)) / MLXBF_GIGE_TIME_FACTOR_TO_USEC) -+ -+#define MLXBF_GIGE_RX_FSM_EQ_FLOW_CYCLES 0x2662c -+#define MLXBF_GIGE_RX_FSM_EQ_FLOW_VAL(const_factor) \ -+ ((48000000 / MLXBF_GIGE_TIME_FACTOR_TO_USEC) * (const_factor)) -+ -+#define MLXBF_GIGE_RX_FSM_EQ_ABORT_CYCLES 0x26630 -+#define MLXBF_GIGE_RX_FSM_EQ_ABORT_VAL(const_factor) \ -+ ((4000 * (const_factor)) / MLXBF_GIGE_TIME_FACTOR_TO_USEC) -+ -+#define MLXBF_GIGE_RX_FSM_EOM_FLOW_CYCLES 0x26634 -+#define MLXBF_GIGE_RX_FSM_EOM_FLOW_VAL(const_factor) \ -+ ((4000000 / MLXBF_GIGE_TIME_FACTOR_TO_USEC) * (const_factor)) -+ -+#define MLXBF_GIGE_RX_FSM_CDR_LOCK_CYCLES 0x26638 -+#define MLXBF_GIGE_RX_FSM_CDR_LOCK_VAL(const_factor) \ -+ ((30000 * (const_factor)) / MLXBF_GIGE_TIME_FACTOR_TO_USEC) -+#define MLXBF_GIGE_RX_FSM_CDR_LOCK_MASK GENMASK(20, 0) -+ -+#define MLXBF_GIGE_LANE_PWR_GOV0 0x26650 -+#define MLXBF_GIGE_LANE_PWR_GOV0_FALL_VAL(const_factor) \ -+ ((5000 * (const_factor)) / MLXBF_GIGE_TIME_FACTOR_TO_USEC) -+#define MLXBF_GIGE_LANE_PWR_GOV0_FALL_MASK GENMASK(31, 16) -+#define MLXBF_GIGE_LANE_PWR_GOV0_RISE_VAL(const_factor) \ -+ ((5000 * (const_factor)) / MLXBF_GIGE_TIME_FACTOR_TO_USEC) -+#define MLXBF_GIGE_LANE_PWR_GOV0_RISE_MASK GENMASK(15, 0) -+ -+#define MLXBF_GIGE_LANE_IDDQ_CYCLES 0x26660 -+#define MLXBF_GIGE_LANE_IDDQ_CYCLES_VAL(const_factor) \ -+ ((2000 * (const_factor)) / MLXBF_GIGE_TIME_FACTOR_TO_USEC) -+#define MLXBF_GIGE_LANE_IDDQ_CYCLES_MASK GENMASK(28, 16) -+ -+#define MLXBF_GIGE_LANE_RST_REG 0x26660 -+#define MLXBF_GIGE_LANE_RST_REG_MASK GENMASK(7, 6) -+ -+#define MLXBF_GIGE_PERIOD_FLOWS_TIMER_MAX 0x26668 -+#define MLXBF_GIGE_PERIOD_FLOWS_TIMER_MAX_VAL(const_factor) \ -+ ((2500000 / (MLXBF_GIGE_TIME_FACTOR_TO_USEC * 8)) * (const_factor)) -+#define MLXBF_GIGE_PERIOD_FLOWS_TIMER_MAX_MASK GENMASK(22, 0) -+ -+#define MLXBF_GIGE_PLL_FSM_CTRL 0x26800 -+#define MLXBF_GIGE_PLL_FSM_PS_MASK GENMASK(3, 0) -+ -+#define MLXBF_GIGE_PLL_GW 0x26810 -+#define MLXBF_GIGE_PLL_GW_ADDR_MASK GENMASK(10, 1) -+#define MLXBF_GIGE_PLL_GW_RW_MASK GENMASK(11, 11) -+#define MLXBF_GIGE_PLL_GW_DATA_MASK GENMASK(27, 12) -+#define MLXBF_GIGE_PLL_GW_DATA_EN_MASK GENMASK(28, 28) -+#define MLXBF_GIGE_PLL_GW_BUSY_MASK GENMASK(30, 30) -+#define MLXBF_GIGE_PLL_GW_ADDR_SHIFT 1 -+#define MLXBF_GIGE_PLL_GW_DESC0 0x2681c -+#define MLXBF_GIGE_PLL_GW_DESC0_DATA_MASK GENMASK(15, 0) -+ -+#define MLXBF_GIGE_PLL_SLEEP_FW 0x26820 -+#define MLXBF_GIGE_PLL_SLEEP_FW_MASK GENMASK(14, 14) -+ -+#define MLXBF_GIGE_PLL_ENABLE 0x26820 -+#define MLXBF_GIGE_PLL_ENABLE_MASK GENMASK(1, 1) -+ -+#define MLXBF_GIGE_PLL_RCAL 0x26828 -+#define MLXBF_GIGE_PLL_RCAL_MASK GENMASK(0, 0) -+ -+#define MLXBF_GIGE_PLL_CAL_VLD 0x2682c -+#define MLXBF_GIGE_PLL_CAL_VLD_MASK GENMASK(1, 0) -+ -+#define MLXBF_GIGE_PLL_CAL 0x26830 -+#define MLXBF_GIGE_PLL_CAL_MASK GENMASK(0, 0) -+ -+#define MLXBF_GIGE_PLL1X_CAUSE_CLRCAUSE_BULK 0x26878 -+#define MLXBF_GIGE_PLL1X_CAUSE_CLRCAUSE_BULK_MASK GENMASK(16, 0) -+ -+#define MLXBF_GIGE_PLL1X_FSM_DEFAULT_CYCLES 0x26900 -+#define MLXBF_GIGE_PLL1X_FSM_DEFAULT_VAL(const_factor) \ -+ ((250 * (const_factor)) / MLXBF_GIGE_TIME_FACTOR_TO_USEC) -+ -+#define MLXBF_GIGE_PLL1X_FSM_SLEEP_CYCLES 0x26904 -+#define MLXBF_GIGE_PLL1X_FSM_SLEEP_VAL(const_factor) \ -+ ((5000 * (const_factor)) / MLXBF_GIGE_TIME_FACTOR_TO_USEC) -+ -+#define MLXBF_GIGE_PLL1X_FSM_RCAL_FLOW_CYCLES 0x26908 -+#define MLXBF_GIGE_PLL1X_FSM_RCAL_FLOW_VAL(const_factor) \ -+ ((40000 * (const_factor)) / MLXBF_GIGE_TIME_FACTOR_TO_USEC) -+ -+#define MLXBF_GIGE_PLL1X_FSM_CAL_FLOW_CYCLES 0x2690c -+#define MLXBF_GIGE_PLL1X_FSM_CAL_FLOW_VAL(const_factor) \ -+ ((300000 * (const_factor)) / MLXBF_GIGE_TIME_FACTOR_TO_USEC) -+ -+#define MLXBF_GIGE_PLL1X_FSM_LOCKDET_STS_CYCLES 0x26910 -+#define MLXBF_GIGE_PLL1X_FSM_LOCKDET_STS_VAL(const_factor) \ -+ ((100000 * (const_factor)) / MLXBF_GIGE_TIME_FACTOR_TO_USEC) -+#define MLXBF_GIGE_PLL1X_FSM_LOCKDET_STS_MASK GENMASK(18, 0) -+ -+#define MLXBF_GIGE_PLL_IDDQ_CYCLES 0x26914 -+#define MLXBF_GIGE_PLL_IDDQ_CYCLES_VAL(const_factor) \ -+ ((2000 * (const_factor)) / MLXBF_GIGE_TIME_FACTOR_TO_USEC) -+#define MLXBF_GIGE_PLL_IDDQ_CYCLES_MASK GENMASK(28, 16) -+ -+#define MLXBF_GIGE_UPHY_PLL_RST_REG 0x26914 -+#define MLXBF_GIGE_UPHY_PLL_RST_REG_MASK GENMASK(2, 2) -+ -+#define MLXBF_GIGE_UGL_CR_BRIDGE_DESC 0x26a90 -+#define MLXBF_GIGE_UGL_CR_BRIDGE_SETUP_MASK GENMASK(5, 0) -+#define MLXBF_GIGE_UGL_CR_BRIDGE_PULSE_MASK GENMASK(13, 8) -+#define MLXBF_GIGE_UGL_CR_BRIDGE_HOLD_MASK GENMASK(21, 16) -+#define MLXBF_GIGE_UGL_CR_BRIDGE_ALL_MASK \ -+ (MLXBF_GIGE_UGL_CR_BRIDGE_SETUP_MASK | \ -+ MLXBF_GIGE_UGL_CR_BRIDGE_PULSE_MASK | \ -+ MLXBF_GIGE_UGL_CR_BRIDGE_HOLD_MASK) -+ -+#define MLXBF_GIGE_UGL_CR_BRIDGE_SETUP_VAL(const_factor) \ -+ ((10 * (const_factor)) / MLXBF_GIGE_TIME_FACTOR_TO_USEC) -+#define MLXBF_GIGE_UGL_CR_BRIDGE_PULSE_VAL(const_factor) \ -+ ((30 * (const_factor)) / MLXBF_GIGE_TIME_FACTOR_TO_USEC) -+#define MLXBF_GIGE_UGL_CR_BRIDGE_HOLD_VAL(const_factor) \ -+ ((10 * (const_factor)) / MLXBF_GIGE_TIME_FACTOR_TO_USEC) -+ -+/* rw = 0 for write and 1 for read. -+ * data_en should be set to 1 only for a write transaction. -+ */ -+#define MLXBF_GIGE_PLL_GW_CREATE_CMD(addr, data, rw) \ -+ ((((addr) << MLXBF_GIGE_PLL_GW_ADDR_SHIFT) & MLXBF_GIGE_PLL_GW_ADDR_MASK) | \ -+ FIELD_PREP(MLXBF_GIGE_PLL_GW_RW_MASK, rw) | \ -+ FIELD_PREP(MLXBF_GIGE_PLL_GW_DATA_MASK, data) | \ -+ FIELD_PREP(MLXBF_GIGE_PLL_GW_DATA_EN_MASK, !rw) | \ -+ FIELD_PREP(MLXBF_GIGE_PLL_GW_BUSY_MASK, 1)) -+ -+#define MLXBF_GIGE_LANE_GW_CREATE_CMD(addr, data, rw) \ -+ ((((addr) << MLXBF_GIGE_LANE_GW_ADDR_SHIFT) & MLXBF_GIGE_LANE_GW_ADDR_MASK) | \ -+ FIELD_PREP(MLXBF_GIGE_LANE_GW_RW_MASK, rw) | \ -+ FIELD_PREP(MLXBF_GIGE_LANE_GW_DATA_MASK, data) | \ -+ FIELD_PREP(MLXBF_GIGE_LANE_GW_DATA_EN_MASK, !rw) | \ -+ FIELD_PREP(MLXBF_GIGE_LANE_GW_BUSY_MASK, 1)) -+ -+#define MLXBF_GIGE_UPHY_GW_CREATE_CMD(addr, data, rw, is_pll) \ -+ ((is_pll) ? MLXBF_GIGE_PLL_GW_CREATE_CMD(addr, data, rw) : \ -+ MLXBF_GIGE_LANE_GW_CREATE_CMD(addr, data, rw)) -+ -+#define MLXBF_GIGE_UPHY_GW(is_pll) \ -+ ((is_pll) ? MLXBF_GIGE_PLL_GW : MLXBF_GIGE_LANE_GW) -+ -+#define MLXBF_GIGE_UPHY_GW_DESC0(is_pll) \ -+ ((is_pll) ? MLXBF_GIGE_PLL_GW_DESC0 : MLXBF_GIGE_LANE_GW_DESC0) -+ -+#define MLXBF_GIGE_UPHY_GW_DESC0_DATA_MASK(is_pll) \ -+ ((is_pll) ? MLXBF_GIGE_PLL_GW_DESC0_DATA_MASK : \ -+ MLXBF_GIGE_LANE_GW_DESC0_DATA_MASK) -+ -+#define MLXBF_GIGE_UPHY_GW_BUSY_MASK(is_pll) \ -+ ((is_pll) ? MLXBF_GIGE_PLL_GW_BUSY_MASK : \ -+ MLXBF_GIGE_LANE_GW_BUSY_MASK) -+ -+/* bootrecord p1clk */ -+#define MLXBF_GIGE_P1CLK_REG1 0x14 -+#define MLXBF_GIGE_P1CLK_REG2 0x18 -+#define MLXBF_GIGE_P1_CORE_F_SHIFT 0 -+#define MLXBF_GIGE_P1_CORE_F_MASK GENMASK(25, 0) -+#define MLXBF_GIGE_P1_CORE_R_SHIFT 26 -+#define MLXBF_GIGE_P1_CORE_R_MASK GENMASK(31, 26) -+#define MLXBF_GIGE_P1_CORE_OD_SHIFT 0 -+#define MLXBF_GIGE_P1_CORE_OD_MASK GENMASK(3, 0) -+ -+#define MLXBF_GIGE_P1CLK_MULT_FACTOR 12 -+#define MLXBF_GIGE_P1_FREQ_REFERENCE 156250000ULL -+#define MLXBF_GIGE_P1_CLK_CONST 16384ULL -+ -+/* There is a 32-bit crspace to 16-bit UPHY address encoding. -+ * The 16-bit address can be accessed via the GW register. -+ * Subtract the crspace region base address from the actual -+ * address that needs to be accessed via the gw. -+ * Then divide it by 4 since crspace registers are 4 bit aligned -+ */ -+#define MLXBF_GIGE_32B_TO_16B_ADDR(addr, base) (((addr) - (base)) >> 2) -+ -+#define MLXBF_GIGE_LANE_CSUM_STS_ADDR \ -+ MLXBF_GIGE_32B_TO_16B_ADDR( \ -+ MLXBF_GIGE_AE_SYS_IMEM_RAM_STAT_IMEM_CSUM_STS, \ -+ MLXBF_GIGE_LANE_CFG_FLAT0_BASE) -+ -+#define MLXBF_GIGE_IMEM_CSUM_RUN_AND_VALID 0x3 -+#define MLXBF_GIGE_INVALID_IMEM_CSUM -1 -+ -+#define MLXBF_GIGE_LANE_IMEM_DATA_ADDR \ -+ MLXBF_GIGE_32B_TO_16B_ADDR( \ -+ MLXBF_GIGE_AE_SYS_IMEM_RAM_DATA_CTRL_WDATA, \ -+ MLXBF_GIGE_LANE_CFG_FLAT0_BASE) -+ -+#define MLXBF_GIGE_MGMT_BGAP_FUSE_CTRL_ADDR \ -+ MLXBF_GIGE_32B_TO_16B_ADDR( \ -+ MLXBF_GIGE_PLL_CFG_FLAT0_MGMT_BGAP_FUSE_CTRL, \ -+ MLXBF_GIGE_PLL_CFG_FLAT0_BASE) -+ -+#define MLXBF_GIGE_YU_BG_TRIM_ROOM_MASK GENMASK(4, 0) -+#define MLXBF_GIGE_YU_BG_TRIM_ROOM_SHIFT 0 -+#define MLXBF_GIGE_YU_CVB_TRIM_ROOM_MASK GENMASK(9, 5) -+#define MLXBF_GIGE_YU_CVB_TRIM_ROOM_SHIFT 5 -+#define MLXBF_GIGE_YU_SPEEDO_ROOM_MASK GENMASK(14, 10) -+#define MLXBF_GIGE_YU_SPEEDO_ROOM_SHIFT 10 -+#define MLXBF_GIGE_YU_FUSE_VALID_SHIFT 4 -+/* Fuse mask without valid bit */ -+#define MLXBF_GIGE_YU_FUSE_MASK 0xf -+ -+enum { -+ MLXBF_GIGE_UGL_PLL1X_FSM_STATE_IDDQ, -+ MLXBF_GIGE_UGL_PLL1X_FSM_STATE_SLEEP, -+ MLXBF_GIGE_UGL_PLL1X_FSM_STATE_RCAL_DONE_WAIT1, -+ MLXBF_GIGE_UGL_PLL1X_FSM_STATE_RCAL_DONE_WAIT0, -+ MLXBF_GIGE_UGL_PLL1X_FSM_STATE_IDLE, -+ MLXBF_GIGE_UGL_PLL1X_FSM_STATE_CAL_DONE_WAIT1, -+ MLXBF_GIGE_UGL_PLL1X_FSM_STATE_CAL_DONE_WAIT0, -+ MLXBF_GIGE_UGL_PLL1X_FSM_STATE_ACTIVE, -+ MLXBF_GIGE_UGL_PLL1X_FSM_STATE_LOCK, -+ MLXBF_GIGE_UGL_PLL1X_FSM_STATE_SPEED_CHANGE -+}; -+ -+enum { -+ MLXBF_GIGE_TX_FSM_IDDQ, -+ MLXBF_GIGE_TX_FSM_SLEEP, -+ MLXBF_GIGE_TX_FSM_SPEED_CHANGE, -+ MLXBF_GIGE_TX_FSM_POWERUP, -+ MLXBF_GIGE_TX_UGL_TX_POWERUP, -+ MLXBF_GIGE_TX_CAL_DONE_WAIT1, -+ MLXBF_GIGE_TX_CAL_ABORT, -+ MLXBF_GIGE_TX_CAL_ABORT_DONE_WAIT1, -+ MLXBF_GIGE_TX_CAL_DONE_WAIT0, -+ MLXBF_GIGE_TX_CAL_DONE, -+ MLXBF_GIGE_TX_DATA_READY, -+ MLXBF_GIGE_TX_DATA_EN_RDY, -+ MLXBF_GIGE_TX_DATA_EN -+}; -+ -+enum { -+ MLXBF_GIGE_RX_FSM_IDDQ, -+ MLXBF_GIGE_RX_FSM_SLEEP, -+ MLXBF_GIGE_RX_FSM_SPEED_CHANGE, -+ MLXBF_GIGE_RX_FSM_POWERUP, -+ MLXBF_GIGE_RX_FSM_CAL, -+ MLXBF_GIGE_RX_FSM_WAIT_TERM, -+ MLXBF_GIGE_RX_FSM_DATA_EN_RDY, -+ MLXBF_GIGE_RX_FSM_DATA_EN, -+ MLXBF_GIGE_RX_FSM_CDR_EN, -+ MLXBF_GIGE_RX_FSM_ACTIVE, -+ MLXBF_GIGE_RX_FSM_EQ, -+ MLXBF_GIGE_RX_FSM_EOM -+}; -+ -+#define MLXBF_GIGE_PLL_STAB_TIME 6 /* us */ -+#define MLXBF_GIGE_PLL_DLM_IMEM_CSUM_TIMEOUT 15 /* us */ -+ -+struct mlxbf_gige_uphy_cfg_reg { -+ u16 addr; -+ u16 wdata; -+}; -+ -+int mlxbf_gige_config_uphy(struct mlxbf_gige *priv); -+ -+#endif /* __MLXBF_GIGE_UPHY_H__ */ --- -2.20.1 - diff --git a/platform/mellanox/non-upstream-patches/patches/0242-UBUNTU-SAUCE-mlxbf_gige-add-BlueField-3-ethtool_ops.patch b/platform/mellanox/non-upstream-patches/patches/0242-UBUNTU-SAUCE-mlxbf_gige-add-BlueField-3-ethtool_ops.patch deleted file mode 100644 index d08aafb30154..000000000000 --- a/platform/mellanox/non-upstream-patches/patches/0242-UBUNTU-SAUCE-mlxbf_gige-add-BlueField-3-ethtool_ops.patch +++ /dev/null @@ -1,95 +0,0 @@ -From 33acf11a1ea46d88fbb27afff1537bdf5dd0e822 Mon Sep 17 00:00:00 2001 -From: David Thompson -Date: Fri, 28 Oct 2022 18:08:46 -0400 -Subject: [PATCH backport 5.10 43/63] UBUNTU: SAUCE: mlxbf_gige: add - BlueField-3 ethtool_ops - -BugLink: https://bugs.launchpad.net/bugs/1995148 - -This patch adds logic to support initialization of a -BlueField-3 specific "ethtool_ops" data structure. The -BlueField-3 data structure supports the "set_link_ksettings" -callback, while the BlueField-2 data structure does not. - -Signed-off-by: David Thompson -Signed-off-by: Asmaa Mnebhi ---- - .../ethernet/mellanox/mlxbf_gige/mlxbf_gige.h | 3 ++- - .../mellanox/mlxbf_gige/mlxbf_gige_ethtool.c | 17 ++++++++++++++++- - .../mellanox/mlxbf_gige/mlxbf_gige_main.c | 4 +++- - 3 files changed, 21 insertions(+), 3 deletions(-) - -diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h -index e9bd09ee0..cbabdac3e 100644 ---- a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h -+++ b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h -@@ -200,7 +200,8 @@ struct sk_buff *mlxbf_gige_alloc_skb(struct mlxbf_gige *priv, - int mlxbf_gige_request_irqs(struct mlxbf_gige *priv); - void mlxbf_gige_free_irqs(struct mlxbf_gige *priv); - int mlxbf_gige_poll(struct napi_struct *napi, int budget); --extern const struct ethtool_ops mlxbf_gige_ethtool_ops; -+extern const struct ethtool_ops mlxbf_gige_bf2_ethtool_ops; -+extern const struct ethtool_ops mlxbf_gige_bf3_ethtool_ops; - void mlxbf_gige_update_tx_wqe_next(struct mlxbf_gige *priv); - - #endif /* !defined(__MLXBF_GIGE_H__) */ -diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_ethtool.c b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_ethtool.c -index 257724323..3156ef064 100644 ---- a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_ethtool.c -+++ b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_ethtool.c -@@ -158,7 +158,7 @@ static void mlxbf_gige_get_pauseparam(struct net_device *netdev, - pause->tx_pause = 1; - } - --const struct ethtool_ops mlxbf_gige_ethtool_ops = { -+const struct ethtool_ops mlxbf_gige_bf2_ethtool_ops = { - .get_link = ethtool_op_get_link, - .get_ringparam = mlxbf_gige_get_ringparam, - .set_ringparam = mlxbf_gige_set_ringparam, -@@ -171,3 +171,18 @@ const struct ethtool_ops mlxbf_gige_ethtool_ops = { - .get_pauseparam = mlxbf_gige_get_pauseparam, - .get_link_ksettings = phy_ethtool_get_link_ksettings, - }; -+ -+const struct ethtool_ops mlxbf_gige_bf3_ethtool_ops = { -+ .get_link = ethtool_op_get_link, -+ .get_ringparam = mlxbf_gige_get_ringparam, -+ .set_ringparam = mlxbf_gige_set_ringparam, -+ .get_regs_len = mlxbf_gige_get_regs_len, -+ .get_regs = mlxbf_gige_get_regs, -+ .get_strings = mlxbf_gige_get_strings, -+ .get_sset_count = mlxbf_gige_get_sset_count, -+ .get_ethtool_stats = mlxbf_gige_get_ethtool_stats, -+ .nway_reset = phy_ethtool_nway_reset, -+ .get_pauseparam = mlxbf_gige_get_pauseparam, -+ .get_link_ksettings = phy_ethtool_get_link_ksettings, -+ .set_link_ksettings = phy_ethtool_set_link_ksettings, -+}; -diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c -index f97e49670..197ec8ccb 100644 ---- a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c -+++ b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c -@@ -451,7 +451,6 @@ static int mlxbf_gige_probe(struct platform_device *pdev) - - SET_NETDEV_DEV(netdev, &pdev->dev); - netdev->netdev_ops = &mlxbf_gige_netdev_ops; -- netdev->ethtool_ops = &mlxbf_gige_ethtool_ops; - priv = netdev_priv(netdev); - priv->netdev = netdev; - -@@ -468,9 +467,12 @@ static int mlxbf_gige_probe(struct platform_device *pdev) - priv->hw_version = soc_version; - - if (priv->hw_version == MLXBF_GIGE_VERSION_BF3) { -+ netdev->ethtool_ops = &mlxbf_gige_bf3_ethtool_ops; - err = mlxbf_gige_config_uphy(priv); - if (err) - return err; -+ } else { -+ netdev->ethtool_ops = &mlxbf_gige_bf2_ethtool_ops; - } - - /* Attach MDIO device */ --- -2.20.1 - diff --git a/platform/mellanox/non-upstream-patches/patches/0261-mlxbf-ptm-power-and-thermal-management-debugfs-drive.patch b/platform/mellanox/non-upstream-patches/patches/0261-mlxbf-ptm-power-and-thermal-management-debugfs-drive.patch index a58881c4a721..7328cbfdf048 100644 --- a/platform/mellanox/non-upstream-patches/patches/0261-mlxbf-ptm-power-and-thermal-management-debugfs-drive.patch +++ b/platform/mellanox/non-upstream-patches/patches/0261-mlxbf-ptm-power-and-thermal-management-debugfs-drive.patch @@ -39,17 +39,17 @@ index a5231c23a..48bd61f61 100644 config NVSW_SN2201 diff --git a/drivers/platform/mellanox/Makefile b/drivers/platform/mellanox/Makefile -index 7c6393ebe..6aa0ab157 100644 +index 7a4b90ed5..d30483021 100644 --- a/drivers/platform/mellanox/Makefile +++ b/drivers/platform/mellanox/Makefile -@@ -9,6 +9,7 @@ obj-$(CONFIG_MLXBF_PMC) += mlxbf-pmc.o +@@ -8,6 +8,7 @@ obj-$(CONFIG_MLXBF_PMC) += mlxbf-pmc.o obj-$(CONFIG_MLXBF_TMFIFO) += mlxbf-tmfifo.o obj-$(CONFIG_MLXBF_TRIO) += mlx-trio.o obj-$(CONFIG_MLXBF_LIVEFISH) += mlxbf-livefish.o +obj-$(CONFIG_MLXBF_PTM) += mlxbf-ptm.o obj-$(CONFIG_MLXREG_HOTPLUG) += mlxreg-hotplug.o obj-$(CONFIG_MLXREG_IO) += mlxreg-io.o - obj-$(CONFIG_MLXREG_LC) += mlxreg-lc.o + obj-$(CONFIG_MLXBF_PKA) += mlxbf_pka/ diff --git a/drivers/platform/mellanox/mlxbf-ptm.c b/drivers/platform/mellanox/mlxbf-ptm.c new file mode 100644 index 000000000..307ba1f33 diff --git a/platform/mellanox/non-upstream-patches/patches/0269-platform-mellanox-Cosmetic-changes.patch b/platform/mellanox/non-upstream-patches/patches/0269-platform-mellanox-Cosmetic-changes.patch deleted file mode 100644 index 18dc177ede3f..000000000000 --- a/platform/mellanox/non-upstream-patches/patches/0269-platform-mellanox-Cosmetic-changes.patch +++ /dev/null @@ -1,74 +0,0 @@ -From da7c9365e155de2a038cbc1cded3a56ea9a363aa Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Mon, 27 Feb 2023 15:24:43 +0000 -Subject: [PATCH backport 5.10 1/3] platform: mellanox: Cosmetic changes - -Fix routines and labels names by s/topology/topology. - -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych ---- - drivers/platform/mellanox/mlx-platform.c | 14 +++++++------- - 1 file changed, 7 insertions(+), 7 deletions(-) - -diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c -index 849fdf5de..656056089 100644 ---- a/drivers/platform/mellanox/mlx-platform.c -+++ b/drivers/platform/mellanox/mlx-platform.c -@@ -6876,7 +6876,7 @@ mlxplat_i2c_mux_complition_notify(void *handle, struct i2c_adapter *parent, - return 0; - } - --static int mlxplat_i2c_mux_topolgy_init(struct mlxplat_priv *priv) -+static int mlxplat_i2c_mux_topology_init(struct mlxplat_priv *priv) - { - int i, err; - -@@ -6921,7 +6921,7 @@ static int mlxplat_i2c_mux_topolgy_init(struct mlxplat_priv *priv) - return err; - } - --static void mlxplat_i2c_mux_topolgy_exit(struct mlxplat_priv *priv) -+static void mlxplat_i2c_mux_topology_exit(struct mlxplat_priv *priv) - { - int i; - -@@ -6937,7 +6937,7 @@ static int mlxplat_i2c_main_complition_notify(void *handle, int id) - { - struct mlxplat_priv *priv = handle; - -- return mlxplat_i2c_mux_topolgy_init(priv); -+ return mlxplat_i2c_mux_topology_init(priv); - } - - static int mlxplat_i2c_main_init(struct mlxplat_priv *priv) -@@ -6964,14 +6964,14 @@ static int mlxplat_i2c_main_init(struct mlxplat_priv *priv) - } - - if (priv->i2c_main_init_status == MLXPLAT_I2C_MAIN_BUS_NOTIFIED) { -- err = mlxplat_i2c_mux_topolgy_init(priv); -+ err = mlxplat_i2c_mux_topology_init(priv); - if (err) -- goto fail_mlxplat_i2c_mux_topolgy_init; -+ goto fail_mlxplat_i2c_mux_topology_init; - } - - return 0; - --fail_mlxplat_i2c_mux_topolgy_init: -+fail_mlxplat_i2c_mux_topology_init: - fail_platform_i2c_register: - fail_mlxplat_mlxcpld_verify_bus_topology: - return err; -@@ -6979,7 +6979,7 @@ static int mlxplat_i2c_main_init(struct mlxplat_priv *priv) - - static void mlxplat_i2c_main_exit(struct mlxplat_priv *priv) - { -- mlxplat_i2c_mux_topolgy_exit(priv); -+ mlxplat_i2c_mux_topology_exit(priv); - if (priv->pdev_i2c) - platform_device_unregister(priv->pdev_i2c); - } --- -2.20.1 - diff --git a/platform/mellanox/non-upstream-patches/patches/0270-platform-mellanox-Fix-order-in-exit-flow.patch b/platform/mellanox/non-upstream-patches/patches/0270-platform-mellanox-Fix-order-in-exit-flow.patch deleted file mode 100644 index 4bbbe389aaa8..000000000000 --- a/platform/mellanox/non-upstream-patches/patches/0270-platform-mellanox-Fix-order-in-exit-flow.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 89d0e497e62b90e8faa2b67c298cedeab47b8f8b Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Mon, 27 Feb 2023 16:09:17 +0000 -Subject: [PATCH backport 5.10 2/3] platform: mellanox: Fix order in exit flow - -Fix exit flow order: call mlxplat_post_exit() after -mlxplat_i2c_main_exit() in order to unregister main i2c driver before -to "mlxplat" driver. - -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych ---- - drivers/platform/mellanox/mlx-platform.c | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - -diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c -index 656056089..42fd7e4e0 100644 ---- a/drivers/platform/mellanox/mlx-platform.c -+++ b/drivers/platform/mellanox/mlx-platform.c -@@ -6929,8 +6929,6 @@ static void mlxplat_i2c_mux_topology_exit(struct mlxplat_priv *priv) - if (priv->pdev_mux[i]) - platform_device_unregister(priv->pdev_mux[i]); - } -- -- mlxplat_post_exit(); - } - - static int mlxplat_i2c_main_complition_notify(void *handle, int id) -@@ -7068,6 +7066,7 @@ static void __exit mlxplat_exit(void) - unregister_reboot_notifier(mlxplat_reboot_nb); - mlxplat_pre_exit(priv); - mlxplat_i2c_main_exit(priv); -+ mlxplat_post_exit(); - } - module_exit(mlxplat_exit); - --- -2.20.1 - diff --git a/platform/mellanox/non-upstream-patches/patches/0271-platform-mellanox-Add-new-attributes.patch b/platform/mellanox/non-upstream-patches/patches/0271-platform-mellanox-Add-new-attributes.patch deleted file mode 100644 index 92044c45bfad..000000000000 --- a/platform/mellanox/non-upstream-patches/patches/0271-platform-mellanox-Add-new-attributes.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 6cb8f4e432f8209a3775877d690a979a2e786afc Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Mon, 27 Feb 2023 18:56:09 +0000 -Subject: [PATCH backport 5.10 3/3] platform: mellanox: Add new attributes - -Add two new attributes: -"lid_open" - to indicate system intrusion detection. -"reset_long_pwr_pb" - to indicate that system has been reset due to -long press of power button. - -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych ---- - drivers/platform/mellanox/mlx-platform.c | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - -diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c -index 42fd7e4e0..4eb327720 100644 ---- a/drivers/platform/mellanox/mlx-platform.c -+++ b/drivers/platform/mellanox/mlx-platform.c -@@ -4067,6 +4067,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { - .mask = GENMASK(7, 0) & ~BIT(1), - .mode = 0444, - }, -+ { -+ .label = "lid_open", -+ .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(2), -+ .mode = 0444, -+ }, - { - .label = "clk_brd1_boot_fail", - .reg = MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET, -@@ -4706,6 +4712,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_chassis_blade_regs_io_data[] = { - .mask = GENMASK(7, 0) & ~BIT(6), - .mode = 0444, - }, -+ { -+ .label = "reset_long_pwr_pb", -+ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(7), -+ .mode = 0444, -+ }, - { - .label = "pwr_cycle", - .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, --- -2.20.1 - diff --git a/platform/mellanox/non-upstream-patches/patches/0272-platform-mellanox-Change-register-offset-addresses.patch b/platform/mellanox/non-upstream-patches/patches/0272-platform-mellanox-Change-register-offset-addresses.patch deleted file mode 100644 index a5596171c962..000000000000 --- a/platform/mellanox/non-upstream-patches/patches/0272-platform-mellanox-Change-register-offset-addresses.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 020ab13e16f943bb66da221507f83634a7d9ca05 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Wed, 1 Mar 2023 17:21:48 +0000 -Subject: [PATCH backport 5.10 4/5] platform: mellanox: Change register offset - addresses - -Move debug register offsets to different location due to hardware changes. - -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych ---- - drivers/platform/mellanox/mlx-platform.c | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - -diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c -index 4eb327720..b5d51673f 100644 ---- a/drivers/platform/mellanox/mlx-platform.c -+++ b/drivers/platform/mellanox/mlx-platform.c -@@ -66,10 +66,6 @@ - #define MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET 0x37 - #define MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET 0x3a - #define MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET 0x3b --#define MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET 0x3c --#define MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET 0x3d --#define MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET 0x3e --#define MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET 0x3f - #define MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET 0x40 - #define MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET 0x41 - #define MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET 0x42 -@@ -130,6 +126,10 @@ - #define MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET 0xaa - #define MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET 0xab - #define MLXPLAT_CPLD_LPC_REG_LC_PWR_ON 0xb2 -+#define MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET 0xb6 -+#define MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET 0xb7 -+#define MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET 0xb8 -+#define MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET 0xb9 - #define MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET 0xc2 - #define MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT 0xc3 - #define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET 0xc7 --- -2.20.1 - diff --git a/platform/mellanox/non-upstream-patches/patches/0273-platform-mellanox-Add-field-upgrade-capability-regis.patch b/platform/mellanox/non-upstream-patches/patches/0273-platform-mellanox-Add-field-upgrade-capability-regis.patch deleted file mode 100644 index 0e1c1b469c7c..000000000000 --- a/platform/mellanox/non-upstream-patches/patches/0273-platform-mellanox-Add-field-upgrade-capability-regis.patch +++ /dev/null @@ -1,72 +0,0 @@ -From 96de5181b880adf2fd65fa85fbc3e0c74f976788 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Wed, 1 Mar 2023 17:49:08 +0000 -Subject: [PATCH backport 5.10 5/6] platform: mellanox: Add field upgrade - capability register - -Add new register to indicate the method of FPGA/CPLD field upgrade -supported on the specific system. -Currently two masks are available: -b00 - field upgrade through LPC gateway (new method introduced to - accelerate field upgrade process). -b11 - field upgrade through CPU GPIO pins (old method). - -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych ---- - drivers/platform/mellanox/mlx-platform.c | 11 +++++++++++ - 1 file changed, 11 insertions(+) - -diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c -index b5d51673f..f674d9173 100644 ---- a/drivers/platform/mellanox/mlx-platform.c -+++ b/drivers/platform/mellanox/mlx-platform.c -@@ -66,6 +66,7 @@ - #define MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET 0x37 - #define MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET 0x3a - #define MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET 0x3b -+#define MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET 0x3c - #define MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET 0x40 - #define MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET 0x41 - #define MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET 0x42 -@@ -241,6 +242,7 @@ - #define MLXPLAT_CPLD_VOLTREG_UPD_MASK GENMASK(5, 4) - #define MLXPLAT_CPLD_GWP_MASK GENMASK(0, 0) - #define MLXPLAT_CPLD_EROT_MASK GENMASK(1, 0) -+#define MLXPLAT_CPLD_FU_CAP_MASK GENMASK(1, 0) - #define MLXPLAT_CPLD_PWR_BUTTON_MASK BIT(0) - #define MLXPLAT_CPLD_LATCH_RST_MASK BIT(5) - #define MLXPLAT_CPLD_THERMAL1_PDB_MASK BIT(3) -@@ -3956,6 +3958,13 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { - .mask = GENMASK(7, 0) & ~BIT(5), - .mode = 0200, - }, -+ { -+ .label = "jtag_cap", -+ .reg = MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET, -+ .mask = MLXPLAT_CPLD_FU_CAP_MASK, -+ .bit = 1, -+ .mode = 0444, -+ }, - { - .label = "jtag_enable", - .reg = MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, -@@ -5424,6 +5433,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET: - case MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET: - case MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET: -@@ -5582,6 +5592,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET: - case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET: - case MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET: - case MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET: --- -2.20.1 - diff --git a/platform/mellanox/non-upstream-patches/patches/0274-platform-mellanox-Modify-reset-causes-description.patch b/platform/mellanox/non-upstream-patches/patches/0274-platform-mellanox-Modify-reset-causes-description.patch deleted file mode 100644 index 62b5635661b9..000000000000 --- a/platform/mellanox/non-upstream-patches/patches/0274-platform-mellanox-Modify-reset-causes-description.patch +++ /dev/null @@ -1,53 +0,0 @@ -From f8a0954053e6e06070ed399e1810bea089ba36bd Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Thu, 2 Mar 2023 12:28:11 +0000 -Subject: [PATCH backport v.5.10 4/8] platform: mellanox: Modify reset causes - description - -Link: https://patchwork.kernel.org/project/platform-driver-x86/patch/20230814203406.12399-4-vadimp@nvidia.com/ - -For system of classes VMOD0005, VMOD0010: -- remove "reset_from_comex", since this cause doesn't define specific - reason. -- add more speicific reason "reset_sw_reset", which is set along with - removed "reset_from_comex". - -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych ---- - drivers/platform/mellanox/mlx-platform.c | 12 ++++++------ - 1 file changed, 6 insertions(+), 6 deletions(-) - -diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c -index 486a3e8da..67865636e 100644 ---- a/drivers/platform/mellanox/mlx-platform.c -+++ b/drivers/platform/mellanox/mlx-platform.c -@@ -3832,12 +3832,6 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { - .mask = GENMASK(7, 0) & ~BIT(2), - .mode = 0444, - }, -- { -- .label = "reset_from_comex", -- .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, -- .mask = GENMASK(7, 0) & ~BIT(4), -- .mode = 0444, -- }, - { - .label = "reset_from_asic", - .reg = MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET, -@@ -3856,6 +3850,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { - .mask = GENMASK(7, 0) & ~BIT(7), - .mode = 0444, - }, -+ { -+ .label = "reset_sw_reset", -+ .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, -+ .mask = GENMASK(7, 0) & ~BIT(0), -+ .mode = 0444, -+ }, - { - .label = "reset_comex_pwr_fail", - .reg = MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET, --- -2.20.1 - diff --git a/platform/mellanox/non-upstream-patches/patches/0278-platform-mellanox-mlx-platform-Modify-graceful-shutd.patch b/platform/mellanox/non-upstream-patches/patches/0278-platform-mellanox-mlx-platform-Modify-graceful-shutd.patch deleted file mode 100644 index 72e4b19bb381..000000000000 --- a/platform/mellanox/non-upstream-patches/patches/0278-platform-mellanox-mlx-platform-Modify-graceful-shutd.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 8b83fb501ac77d60e1cc30fac63e71f469ba0992 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Fri, 10 Mar 2023 09:15:35 +0000 -Subject: [PATCH backport v.5.10 1/1] platform: mellanox: mlx-platform: Modify - graceful shutdown callback and power down mask - -Use kernel_power_off() instead of kernel_halt() to pass through -machine_power_off() -> pm_power_off(), otherwise axillary power does -not go off. - -Change "power down" bitmask. - -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych ---- - drivers/platform/mellanox/mlx-platform.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c -index 67865636e..55afb4c90 100644 ---- a/drivers/platform/mellanox/mlx-platform.c -+++ b/drivers/platform/mellanox/mlx-platform.c -@@ -227,7 +227,7 @@ - MLXPLAT_CPLD_AGGR_MASK_LC_SDWN) - #define MLXPLAT_CPLD_LOW_AGGR_MASK_LOW 0xc1 - #define MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2 BIT(2) --#define MLXPLAT_CPLD_LOW_AGGR_MASK_PWR_BUT BIT(4) -+#define MLXPLAT_CPLD_LOW_AGGR_MASK_PWR_BUT GENMASK(5,4) - #define MLXPLAT_CPLD_LOW_AGGR_MASK_I2C BIT(6) - #define MLXPLAT_CPLD_PSU_MASK GENMASK(1, 0) - #define MLXPLAT_CPLD_PWR_MASK GENMASK(1, 0) -@@ -2509,7 +2509,7 @@ mlxplat_mlxcpld_l1_switch_pwr_events_handler(void *handle, enum mlxreg_hotplug_k - u8 action) - { - dev_info(&mlxplat_dev->dev, "System shutdown due to short press of power button"); -- kernel_halt(); -+ kernel_power_off(); - return 0; - } - --- -2.20.1 - diff --git a/platform/mellanox/non-upstream-patches/patches/0279-platform-mellanox-mlx-platform-Fix-signals-polarity-.patch b/platform/mellanox/non-upstream-patches/patches/0279-platform-mellanox-mlx-platform-Fix-signals-polarity-.patch deleted file mode 100644 index 6cd5cddd155d..000000000000 --- a/platform/mellanox/non-upstream-patches/patches/0279-platform-mellanox-mlx-platform-Fix-signals-polarity-.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 6720a3b49d3c0bb26d18bfe651bd9101dde34fc8 Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Wed, 15 Mar 2023 19:23:20 +0000 -Subject: [PATCH backport v.5.10 1/3] platform: mellanox: mlx-platform: Fix - signals polarity and latch mask - -Change polarity of chassis health and power signals and fix latch reset -mask for L1 switch. - -Fixes: dd635e33b5c9 ("platform: mellanox: Introduce support of new Nvidia L1 switch") -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych ---- - drivers/platform/mellanox/mlx-platform.c | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - -diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c -index fa2e539b6..2bc3720a4 100644 ---- a/drivers/platform/mellanox/mlx-platform.c -+++ b/drivers/platform/mellanox/mlx-platform.c -@@ -244,7 +244,7 @@ - #define MLXPLAT_CPLD_EROT_MASK GENMASK(1, 0) - #define MLXPLAT_CPLD_FU_CAP_MASK GENMASK(1, 0) - #define MLXPLAT_CPLD_PWR_BUTTON_MASK BIT(0) --#define MLXPLAT_CPLD_LATCH_RST_MASK BIT(5) -+#define MLXPLAT_CPLD_LATCH_RST_MASK BIT(6) - #define MLXPLAT_CPLD_THERMAL1_PDB_MASK BIT(3) - #define MLXPLAT_CPLD_THERMAL2_PDB_MASK BIT(4) - #define MLXPLAT_CPLD_INTRUSION_MASK BIT(6) -@@ -2631,7 +2631,7 @@ static struct mlxreg_core_item mlxplat_mlxcpld_l1_switch_events_items[] = { - .reg = MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET, - .mask = MLXPLAT_CPLD_PWR_BUTTON_MASK, - .count = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_pwr_events_items_data), -- .inversed = 0, -+ .inversed = 1, - .health = false, - }, - { -@@ -2640,7 +2640,7 @@ static struct mlxreg_core_item mlxplat_mlxcpld_l1_switch_events_items[] = { - .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, - .mask = MLXPLAT_CPLD_L1_CHA_HEALTH_MASK, - .count = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_health_events_items_data), -- .inversed = 0, -+ .inversed = 1, - .health = false, - .ind = 8, - }, -@@ -3958,7 +3958,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { - { - .label = "latch_reset", - .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, -- .mask = GENMASK(7, 0) & ~BIT(5), -+ .mask = GENMASK(7, 0) & ~BIT(6), - .mode = 0200, - }, - { --- -2.20.1 - diff --git a/platform/mellanox/non-upstream-patches/patches/0280-platform-mellanox-mlxreg-hotplug-Extend-condition-fo.patch b/platform/mellanox/non-upstream-patches/patches/0280-platform-mellanox-mlxreg-hotplug-Extend-condition-fo.patch deleted file mode 100644 index 68f8a792dfd5..000000000000 --- a/platform/mellanox/non-upstream-patches/patches/0280-platform-mellanox-mlxreg-hotplug-Extend-condition-fo.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 6531f28d37beb20fb423f4835eab47beaaf002bb Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Sun, 19 Mar 2023 15:04:26 +0000 -Subject: [PATCH backport v.5.10 2/3] platform/mellanox: mlxreg-hotplug: Extend - condition for notification callback processing - -Allow processing of notification callback in routine -mlxreg_hotplug_device_create() in case hotplug object is configured -with action "MLXREG_HOTPLUG_DEVICE_NO_ACTION" in case no I2C parent bus -is specified. - -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych ---- - drivers/platform/mellanox/mlxreg-hotplug.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/drivers/platform/mellanox/mlxreg-hotplug.c b/drivers/platform/mellanox/mlxreg-hotplug.c -index b7dcc64cd..c5abedd35 100644 ---- a/drivers/platform/mellanox/mlxreg-hotplug.c -+++ b/drivers/platform/mellanox/mlxreg-hotplug.c -@@ -113,7 +113,7 @@ static int mlxreg_hotplug_device_create(struct mlxreg_hotplug_priv_data *priv, - * Return if adapter number is negative. It could be in case hotplug - * event is not associated with hotplug device. - */ -- if (data->hpdev.nr < 0) -+ if (data->hpdev.nr < 0 && data->hpdev.action != MLXREG_HOTPLUG_DEVICE_NO_ACTION) - return 0; - - pdata = dev_get_platdata(&priv->pdev->dev); --- -2.20.1 - diff --git a/platform/mellanox/non-upstream-patches/patches/0281-platform-mellanox-mlx-platform-Modify-health-and-pow.patch b/platform/mellanox/non-upstream-patches/patches/0281-platform-mellanox-mlx-platform-Modify-health-and-pow.patch deleted file mode 100644 index f6b38f971250..000000000000 --- a/platform/mellanox/non-upstream-patches/patches/0281-platform-mellanox-mlx-platform-Modify-health-and-pow.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 718681c7948f3191fe7ab7cc0a5f96b6454c3a0b Mon Sep 17 00:00:00 2001 -From: Vadim Pasternak -Date: Sun, 19 Mar 2023 15:36:19 +0000 -Subject: [PATCH backport v.5.10 3/3] platform: mellanox: mlx-platform: Modify - health and power hotplug action - -Set explicitly hotplug event action for health and power signals for -L1 switch as "MLXREG_HOTPLUG_DEVICE_NO_ACTION" in order to allow -processing of notification callback even I2C parent bus is not -specified. - -Signed-off-by: Vadim Pasternak -Reviewed-by: Michael Shych ---- - drivers/platform/mellanox/mlx-platform.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c -index 2bc3720a4..605d57e95 100644 ---- a/drivers/platform/mellanox/mlx-platform.c -+++ b/drivers/platform/mellanox/mlx-platform.c -@@ -2527,6 +2527,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_pwr_events_items_data[] - .reg = MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET, - .mask = MLXPLAT_CPLD_PWR_BUTTON_MASK, - .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, - .hpdev.notifier = &mlxplat_mlxcpld_l1_switch_pwr_events_notifier, - }, - }; -@@ -2587,6 +2588,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_health_events_items_dat - .reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET, - .mask = MLXPLAT_CPLD_INTRUSION_MASK, - .hpdev.nr = MLXPLAT_CPLD_NR_NONE, -+ .hpdev.action = MLXREG_HOTPLUG_DEVICE_NO_ACTION, - .hpdev.notifier = &mlxplat_mlxcpld_l1_switch_intrusion_events_notifier, - }, - { --- -2.20.1 - diff --git a/platform/mellanox/non-upstream-patches/patches/0282-platform-mellanox-mlx-platform-add-support-of-5th-CP.patch b/platform/mellanox/non-upstream-patches/patches/0282-platform-mellanox-mlx-platform-add-support-of-5th-CP.patch deleted file mode 100644 index 24f024a822a6..000000000000 --- a/platform/mellanox/non-upstream-patches/patches/0282-platform-mellanox-mlx-platform-add-support-of-5th-CP.patch +++ /dev/null @@ -1,129 +0,0 @@ -From b37820018a651f9f8bfe3a9c3fe0e90e49add58b Mon Sep 17 00:00:00 2001 -From: Michael Shych -Date: Tue, 9 May 2023 11:06:39 +0000 -Subject: [PATCH v1 1/1] platform: mellanox: mlx-platform: add support of 5th - CPLD. - -Add 5th CPLD version, PN and minimal version registers. - -Signed-off-by: Michael Shych ---- - drivers/platform/mellanox/mlx-platform.c | 33 ++++++++++++++++++++++++++++++-- - 1 file changed, 31 insertions(+), 2 deletions(-) - -diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c -index 605d57e95..dc6b7ad2c 100644 ---- a/drivers/platform/mellanox/mlx-platform.c -+++ b/drivers/platform/mellanox/mlx-platform.c -@@ -99,6 +99,9 @@ - #define MLXPLAT_CPLD_LPC_REG_FAN_OFFSET 0x88 - #define MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET 0x89 - #define MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET 0x8a -+#define MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET 0x8e -+#define MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET 0x8f -+#define MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET 0x90 - #define MLXPLAT_CPLD_LPC_REG_EROT_OFFSET 0x91 - #define MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET 0x92 - #define MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET 0x93 -@@ -133,6 +136,7 @@ - #define MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET 0xb9 - #define MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET 0xc2 - #define MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT 0xc3 -+#define MLXPLAT_CPLD_LPC_REG_CPLD5_MVER_OFFSET 0xc4 - #define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET 0xc7 - #define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET 0xc8 - #define MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET 0xc9 -@@ -3713,6 +3717,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { - .bit = GENMASK(7, 0), - .mode = 0444, - }, -+ { -+ .label = "cpld5_version", -+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0444, -+ }, - { - .label = "cpld1_pn", - .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, -@@ -3741,6 +3751,13 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { - .mode = 0444, - .regnum = 2, - }, -+ { -+ .label = "cpld5_pn", -+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET, -+ .bit = GENMASK(15, 0), -+ .mode = 0444, -+ .regnum = 2, -+ }, - { - .label = "cpld1_version_min", - .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, -@@ -3765,6 +3782,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { - .bit = GENMASK(7, 0), - .mode = 0444, - }, -+ { -+ .label = "cpld5_version_min", -+ .reg = MLXPLAT_CPLD_LPC_REG_CPLD5_MVER_OFFSET, -+ .bit = GENMASK(7, 0), -+ .mode = 0444, -+ }, - { - .label = "asic_reset", - .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, -@@ -5404,6 +5427,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET: -@@ -5412,6 +5436,8 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: - case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET: - case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET: -@@ -5524,6 +5550,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_CPLD5_MVER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET: -@@ -5565,14 +5592,15 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD2_PN1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET: -- case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET: -- case MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: - case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET: - case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET: -@@ -5677,6 +5705,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_CPLD5_MVER_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET: - case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET: --- -2.14.1 - diff --git a/platform/mellanox/non-upstream-patches/patches/0284-platform-mellanox-mlx-platform-fix-CPLD4-PN-report.patch b/platform/mellanox/non-upstream-patches/patches/0284-platform-mellanox-mlx-platform-fix-CPLD4-PN-report.patch deleted file mode 100644 index 72f021eee44a..000000000000 --- a/platform/mellanox/non-upstream-patches/patches/0284-platform-mellanox-mlx-platform-fix-CPLD4-PN-report.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 21cafe13f2452a7c41c623dc63af9cbaa301108d Mon Sep 17 00:00:00 2001 -From: Michael Shych -Date: Wed, 28 Jun 2023 12:23:43 +0000 -Subject: [PATCH v1 1/1] platform: mellanox: mlx-platform: fix CPLD4 PN report. - -Add two lines from upstream commits: -[9045512ca6cdb221cd1ed32d483eac3c30c53bed] -[ae1aabf44bd672a07c4fa3ef56f069ed7daa7823] - -Fix PN report of CPLD4. - -Signed-off-by: Michael Shych ---- - drivers/platform/mellanox/mlx-platform.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c -index 00e62366b..641e7fe1f 100644 ---- a/drivers/platform/mellanox/mlx-platform.c -+++ b/drivers/platform/mellanox/mlx-platform.c -@@ -5605,6 +5605,8 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) - case MLXPLAT_CPLD_LPC_REG_CPLD2_PN1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET: -+ case MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET: - case MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET: - case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: --- -2.14.1 - diff --git a/platform/mellanox/non-upstream-patches/patches/0285-UBUNTU-SAUCE-mlxbf-gige-Fix-intermittent-no-ip-issue.patch b/platform/mellanox/non-upstream-patches/patches/0285-UBUNTU-SAUCE-mlxbf-gige-Fix-intermittent-no-ip-issue.patch new file mode 100644 index 000000000000..90023e1ab3ba --- /dev/null +++ b/platform/mellanox/non-upstream-patches/patches/0285-UBUNTU-SAUCE-mlxbf-gige-Fix-intermittent-no-ip-issue.patch @@ -0,0 +1,85 @@ +From c87bfec5830d104e564d536a2f5ff19f46eabf89 Mon Sep 17 00:00:00 2001 +From: Asmaa Mnebhi +Date: Tue, 28 Feb 2023 18:03:12 -0500 +Subject: [PATCH backport v5.10 30/70] UBUNTU: SAUCE: mlxbf-gige: Fix + intermittent no ip issue + +BugLink: https://bugs.launchpad.net/bugs/2008833 + +During the reboot test, the OOB might not get an ip assigned. +This is due to a race condition between phy_startcall and the +RX DMA being enabled and depends on the amount of background +traffic received by the OOB. Enable the RX DMA after teh phy +is started. + +Signed-off-by: Asmaa Mnebhi +Acked-by: Tim Gardner +Acked-by: Bartlomiej Zolnierkiewicz +Signed-off-by: Bartlomiej Zolnierkiewicz +--- + .../ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c | 14 +++++++------- + .../ethernet/mellanox/mlxbf_gige/mlxbf_gige_rx.c | 6 +++--- + 2 files changed, 10 insertions(+), 10 deletions(-) + +diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c +index e8f9290a8..085240890 100644 +--- a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c ++++ b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c +@@ -147,14 +147,14 @@ static int mlxbf_gige_open(struct net_device *netdev) + */ + priv->valid_polarity = 0; + +- err = mlxbf_gige_rx_init(priv); ++ phy_start(phydev); ++ ++ err = mlxbf_gige_tx_init(priv); + if (err) + goto free_irqs; +- err = mlxbf_gige_tx_init(priv); ++ err = mlxbf_gige_rx_init(priv); + if (err) +- goto rx_deinit; +- +- phy_start(phydev); ++ goto tx_deinit; + + netif_napi_add(netdev, &priv->napi, mlxbf_gige_poll, NAPI_POLL_WEIGHT); + napi_enable(&priv->napi); +@@ -176,8 +176,8 @@ static int mlxbf_gige_open(struct net_device *netdev) + + return 0; + +-rx_deinit: +- mlxbf_gige_rx_deinit(priv); ++tx_deinit: ++ mlxbf_gige_tx_deinit(priv); + + free_irqs: + mlxbf_gige_free_irqs(priv); +diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_rx.c b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_rx.c +index 96230763c..f21dafde4 100644 +--- a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_rx.c ++++ b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_rx.c +@@ -142,6 +142,9 @@ int mlxbf_gige_rx_init(struct mlxbf_gige *priv) + writeq(MLXBF_GIGE_RX_MAC_FILTER_COUNT_PASS_EN, + priv->base + MLXBF_GIGE_RX_MAC_FILTER_COUNT_PASS); + ++ writeq(ilog2(priv->rx_q_entries), ++ priv->base + MLXBF_GIGE_RX_WQE_SIZE_LOG2); ++ + /* Clear MLXBF_GIGE_INT_MASK 'receive pkt' bit to + * indicate readiness to receive interrupts + */ +@@ -154,9 +157,6 @@ int mlxbf_gige_rx_init(struct mlxbf_gige *priv) + data |= MLXBF_GIGE_RX_DMA_EN; + writeq(data, priv->base + MLXBF_GIGE_RX_DMA); + +- writeq(ilog2(priv->rx_q_entries), +- priv->base + MLXBF_GIGE_RX_WQE_SIZE_LOG2); +- + return 0; + + free_wqe_and_skb: +-- +2.20.1 + diff --git a/platform/mellanox/non-upstream-patches/patches/0286-pinctrl-Introduce-struct-pinfunction-and-PINCTRL_PIN.patch b/platform/mellanox/non-upstream-patches/patches/0286-pinctrl-Introduce-struct-pinfunction-and-PINCTRL_PIN.patch new file mode 100644 index 000000000000..c9ca8fc23f0a --- /dev/null +++ b/platform/mellanox/non-upstream-patches/patches/0286-pinctrl-Introduce-struct-pinfunction-and-PINCTRL_PIN.patch @@ -0,0 +1,60 @@ +From 6f90ee9b22030be2aaa4e753aa9813adbb6c9814 Mon Sep 17 00:00:00 2001 +From: Andy Shevchenko +Date: Mon, 19 Dec 2022 14:42:33 +0200 +Subject: [PATCH 74/77] pinctrl: Introduce struct pinfunction and + PINCTRL_PINFUNCTION() macro +X-NVConfidentiality: public + +BugLink: https://bugs.launchpad.net/bugs/2012743 + +There are many pin control drivers define their own data type for +pin function representation which is the same or embed the same data +as newly introduced one. Provide the data type and convenient macro +for all pin control drivers. + +Signed-off-by: Andy Shevchenko +Reviewed-by: Linus Walleij +Acked-by: Mika Westerberg +(cherry picked from commit 443a0a0f0cf4f432c7af6654b7f2f920d411d379) +Signed-off-by: Asmaa Mnebhi +Acked-by: Tim Gardner +Acked-by: Bartlomiej Zolnierkiewicz +Signed-off-by: Bartlomiej Zolnierkiewicz +--- + include/linux/pinctrl/pinctrl.h | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + +diff --git a/include/linux/pinctrl/pinctrl.h b/include/linux/pinctrl/pinctrl.h +index 2aef59df9..dce7402cd 100644 +--- a/include/linux/pinctrl/pinctrl.h ++++ b/include/linux/pinctrl/pinctrl.h +@@ -186,6 +186,26 @@ extern int pinctrl_get_group_pins(struct pinctrl_dev *pctldev, + const char *pin_group, const unsigned **pins, + unsigned *num_pins); + ++/** ++ * struct pinfunction - Description about a function ++ * @name: Name of the function ++ * @groups: An array of groups for this function ++ * @ngroups: Number of groups in @groups ++ */ ++struct pinfunction { ++ const char *name; ++ const char * const *groups; ++ size_t ngroups; ++}; ++ ++/* Convenience macro to define a single named pinfunction */ ++#define PINCTRL_PINFUNCTION(_name, _groups, _ngroups) \ ++(struct pinfunction) { \ ++ .name = (_name), \ ++ .groups = (_groups), \ ++ .ngroups = (_ngroups), \ ++ } ++ + #if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_PINCTRL) + extern struct pinctrl_dev *of_pinctrl_get(struct device_node *np); + #else +-- +2.14.1 + diff --git a/platform/mellanox/non-upstream-patches/patches/0287-pinctrl-mlxbf3-Add-pinctrl-driver-support.patch b/platform/mellanox/non-upstream-patches/patches/0287-pinctrl-mlxbf3-Add-pinctrl-driver-support.patch new file mode 100644 index 000000000000..0350d311dd87 --- /dev/null +++ b/platform/mellanox/non-upstream-patches/patches/0287-pinctrl-mlxbf3-Add-pinctrl-driver-support.patch @@ -0,0 +1,393 @@ +From cbef04cdf39fe364158d0f67053e326c755085ad Mon Sep 17 00:00:00 2001 +From: Asmaa Mnebhi +Date: Wed, 15 Mar 2023 17:50:27 -0400 +Subject: [PATCH 75/77] pinctrl: mlxbf3: Add pinctrl driver support +X-NVConfidentiality: public + +BugLink: https://bugs.launchpad.net/bugs/2012743 + +NVIDIA BlueField-3 SoC has a few pins that can be used as GPIOs +or take the default hardware functionality. Add a driver for +the pin muxing. + +Signed-off-by: Asmaa Mnebhi +Reviewed-by: Andy Shevchenko +Link: https://lore.kernel.org/r/20230315215027.30685-3-asmaa@nvidia.com +Signed-off-by: Linus Walleij +(cherry picked from commit d11f932808dc689717e409bbc81b5093e7902fc9 linux-next) +Signed-off-by: Asmaa Mnebhi +Acked-by: Tim Gardner +Acked-by: Bartlomiej Zolnierkiewicz +Signed-off-by: Bartlomiej Zolnierkiewicz +--- + drivers/pinctrl/Kconfig | 13 ++ + drivers/pinctrl/Makefile | 1 + + drivers/pinctrl/pinctrl-mlxbf3.c | 320 +++++++++++++++++++++++++++++++++++++++ + 3 files changed, 334 insertions(+) + create mode 100644 drivers/pinctrl/pinctrl-mlxbf3.c + +diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig +index 815095326..43dbf5942 100644 +--- a/drivers/pinctrl/Kconfig ++++ b/drivers/pinctrl/Kconfig +@@ -374,6 +374,19 @@ config PINCTRL_OCELOT + select OF_GPIO + select REGMAP_MMIO + ++config PINCTRL_MLXBF3 ++ tristate "NVIDIA BlueField-3 SoC Pinctrl driver" ++ depends on (MELLANOX_PLATFORM && ARM64) || COMPILE_TEST ++ select PINMUX ++ select GPIOLIB ++ select GPIOLIB_IRQCHIP ++ select GPIO_MLXBF3 ++ help ++ Say Y to select the pinctrl driver for BlueField-3 SoCs. ++ This pin controller allows selecting the mux function for ++ each pin. This driver can also be built as a module called ++ pinctrl-mlxbf3. ++ + source "drivers/pinctrl/actions/Kconfig" + source "drivers/pinctrl/aspeed/Kconfig" + source "drivers/pinctrl/bcm/Kconfig" +diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile +index f53933b2f..52c0cdc40 100644 +--- a/drivers/pinctrl/Makefile ++++ b/drivers/pinctrl/Makefile +@@ -25,6 +25,7 @@ obj-$(CONFIG_PINCTRL_MCP23S08_I2C) += pinctrl-mcp23s08_i2c.o + obj-$(CONFIG_PINCTRL_MCP23S08_SPI) += pinctrl-mcp23s08_spi.o + obj-$(CONFIG_PINCTRL_MCP23S08) += pinctrl-mcp23s08.o + obj-$(CONFIG_PINCTRL_MESON) += meson/ ++obj-$(CONFIG_PINCTRL_MLXBF3) += pinctrl-mlxbf3.o + obj-$(CONFIG_PINCTRL_OXNAS) += pinctrl-oxnas.o + obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o + obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o +diff --git a/drivers/pinctrl/pinctrl-mlxbf3.c b/drivers/pinctrl/pinctrl-mlxbf3.c +new file mode 100644 +index 000000000..3698f7bbd +--- /dev/null ++++ b/drivers/pinctrl/pinctrl-mlxbf3.c +@@ -0,0 +1,320 @@ ++// SPDX-License-Identifier: GPL-2.0-only or BSD-3-Clause ++/* Copyright (C) 2022 NVIDIA CORPORATION & AFFILIATES */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#define MLXBF3_NGPIOS_GPIO0 32 ++#define MLXBF3_MAX_GPIO_PINS 56 ++ ++enum { ++ MLXBF3_GPIO_HW_MODE, ++ MLXBF3_GPIO_SW_MODE, ++}; ++ ++struct mlxbf3_pinctrl { ++ void __iomem *fw_ctrl_set0; ++ void __iomem *fw_ctrl_clr0; ++ void __iomem *fw_ctrl_set1; ++ void __iomem *fw_ctrl_clr1; ++ struct device *dev; ++ struct pinctrl_dev *pctl; ++ struct pinctrl_gpio_range gpio_range; ++}; ++ ++#define MLXBF3_GPIO_RANGE(_id, _pinbase, _gpiobase, _npins) \ ++ { \ ++ .name = "mlxbf3_gpio_range", \ ++ .id = _id, \ ++ .base = _gpiobase, \ ++ .pin_base = _pinbase, \ ++ .npins = _npins, \ ++ } ++ ++static struct pinctrl_gpio_range mlxbf3_pinctrl_gpio_ranges[] = { ++ MLXBF3_GPIO_RANGE(0, 0, 480, 32), ++ MLXBF3_GPIO_RANGE(1, 32, 456, 24), ++}; ++ ++static const struct pinctrl_pin_desc mlxbf3_pins[] = { ++ PINCTRL_PIN(0, "gpio0"), ++ PINCTRL_PIN(1, "gpio1"), ++ PINCTRL_PIN(2, "gpio2"), ++ PINCTRL_PIN(3, "gpio3"), ++ PINCTRL_PIN(4, "gpio4"), ++ PINCTRL_PIN(5, "gpio5"), ++ PINCTRL_PIN(6, "gpio6"), ++ PINCTRL_PIN(7, "gpio7"), ++ PINCTRL_PIN(8, "gpio8"), ++ PINCTRL_PIN(9, "gpio9"), ++ PINCTRL_PIN(10, "gpio10"), ++ PINCTRL_PIN(11, "gpio11"), ++ PINCTRL_PIN(12, "gpio12"), ++ PINCTRL_PIN(13, "gpio13"), ++ PINCTRL_PIN(14, "gpio14"), ++ PINCTRL_PIN(15, "gpio15"), ++ PINCTRL_PIN(16, "gpio16"), ++ PINCTRL_PIN(17, "gpio17"), ++ PINCTRL_PIN(18, "gpio18"), ++ PINCTRL_PIN(19, "gpio19"), ++ PINCTRL_PIN(20, "gpio20"), ++ PINCTRL_PIN(21, "gpio21"), ++ PINCTRL_PIN(22, "gpio22"), ++ PINCTRL_PIN(23, "gpio23"), ++ PINCTRL_PIN(24, "gpio24"), ++ PINCTRL_PIN(25, "gpio25"), ++ PINCTRL_PIN(26, "gpio26"), ++ PINCTRL_PIN(27, "gpio27"), ++ PINCTRL_PIN(28, "gpio28"), ++ PINCTRL_PIN(29, "gpio29"), ++ PINCTRL_PIN(30, "gpio30"), ++ PINCTRL_PIN(31, "gpio31"), ++ PINCTRL_PIN(32, "gpio32"), ++ PINCTRL_PIN(33, "gpio33"), ++ PINCTRL_PIN(34, "gpio34"), ++ PINCTRL_PIN(35, "gpio35"), ++ PINCTRL_PIN(36, "gpio36"), ++ PINCTRL_PIN(37, "gpio37"), ++ PINCTRL_PIN(38, "gpio38"), ++ PINCTRL_PIN(39, "gpio39"), ++ PINCTRL_PIN(40, "gpio40"), ++ PINCTRL_PIN(41, "gpio41"), ++ PINCTRL_PIN(42, "gpio42"), ++ PINCTRL_PIN(43, "gpio43"), ++ PINCTRL_PIN(44, "gpio44"), ++ PINCTRL_PIN(45, "gpio45"), ++ PINCTRL_PIN(46, "gpio46"), ++ PINCTRL_PIN(47, "gpio47"), ++ PINCTRL_PIN(48, "gpio48"), ++ PINCTRL_PIN(49, "gpio49"), ++ PINCTRL_PIN(50, "gpio50"), ++ PINCTRL_PIN(51, "gpio51"), ++ PINCTRL_PIN(52, "gpio52"), ++ PINCTRL_PIN(53, "gpio53"), ++ PINCTRL_PIN(54, "gpio54"), ++ PINCTRL_PIN(55, "gpio55"), ++}; ++ ++/* ++ * All single-pin functions can be mapped to any GPIO, however pinmux applies ++ * functions to pin groups and only those groups declared as supporting that ++ * function. To make this work we must put each pin in its own dummy group so ++ * that the functions can be described as applying to all pins. ++ * We use the same name as in the datasheet. ++ */ ++static const char * const mlxbf3_pinctrl_single_group_names[] = { ++ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", ++ "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", ++ "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", ++ "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", ++ "gpio32", "gpio33", "gpio34", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", ++ "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", ++ "gpio48", "gpio49", "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", ++}; ++ ++static int mlxbf3_get_groups_count(struct pinctrl_dev *pctldev) ++{ ++ /* Number single-pin groups */ ++ return MLXBF3_MAX_GPIO_PINS; ++} ++ ++static const char *mlxbf3_get_group_name(struct pinctrl_dev *pctldev, ++ unsigned int selector) ++{ ++ return mlxbf3_pinctrl_single_group_names[selector]; ++} ++ ++static int mlxbf3_get_group_pins(struct pinctrl_dev *pctldev, ++ unsigned int selector, ++ const unsigned int **pins, ++ unsigned int *num_pins) ++{ ++ /* return the dummy group for a single pin */ ++ *pins = &selector; ++ *num_pins = 1; ++ ++ return 0; ++} ++ ++static const struct pinctrl_ops mlxbf3_pinctrl_group_ops = { ++ .get_groups_count = mlxbf3_get_groups_count, ++ .get_group_name = mlxbf3_get_group_name, ++ .get_group_pins = mlxbf3_get_group_pins, ++}; ++ ++/* ++ * Only 2 functions are supported and they apply to all pins: ++ * 1) Default hardware functionality ++ * 2) Software controlled GPIO ++ */ ++static const char * const mlxbf3_gpiofunc_group_names[] = { "swctrl" }; ++static const char * const mlxbf3_hwfunc_group_names[] = { "hwctrl" }; ++ ++struct pinfunction mlxbf3_pmx_funcs[] = { ++ PINCTRL_PINFUNCTION("hwfunc", mlxbf3_hwfunc_group_names, 1), ++ PINCTRL_PINFUNCTION("gpiofunc", mlxbf3_gpiofunc_group_names, 1), ++}; ++ ++static int mlxbf3_pmx_get_funcs_count(struct pinctrl_dev *pctldev) ++{ ++ return ARRAY_SIZE(mlxbf3_pmx_funcs); ++} ++ ++static const char *mlxbf3_pmx_get_func_name(struct pinctrl_dev *pctldev, ++ unsigned int selector) ++{ ++ return mlxbf3_pmx_funcs[selector].name; ++} ++ ++static int mlxbf3_pmx_get_groups(struct pinctrl_dev *pctldev, ++ unsigned int selector, ++ const char * const **groups, ++ unsigned int * const num_groups) ++{ ++ *groups = mlxbf3_pmx_funcs[selector].groups; ++ *num_groups = MLXBF3_MAX_GPIO_PINS; ++ ++ return 0; ++} ++ ++static int mlxbf3_pmx_set(struct pinctrl_dev *pctldev, ++ unsigned int selector, ++ unsigned int group) ++{ ++ struct mlxbf3_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); ++ ++ if (selector == MLXBF3_GPIO_HW_MODE) { ++ if (group < MLXBF3_NGPIOS_GPIO0) ++ writel(BIT(group), priv->fw_ctrl_clr0); ++ else ++ writel(BIT(group % MLXBF3_NGPIOS_GPIO0), priv->fw_ctrl_clr1); ++ } ++ ++ if (selector == MLXBF3_GPIO_SW_MODE) { ++ if (group < MLXBF3_NGPIOS_GPIO0) ++ writel(BIT(group), priv->fw_ctrl_set0); ++ else ++ writel(BIT(group % MLXBF3_NGPIOS_GPIO0), priv->fw_ctrl_set1); ++ } ++ ++ return 0; ++} ++ ++static int mlxbf3_gpio_request_enable(struct pinctrl_dev *pctldev, ++ struct pinctrl_gpio_range *range, ++ unsigned int offset) ++{ ++ struct mlxbf3_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); ++ ++ if (offset < MLXBF3_NGPIOS_GPIO0) ++ writel(BIT(offset), priv->fw_ctrl_set0); ++ else ++ writel(BIT(offset % MLXBF3_NGPIOS_GPIO0), priv->fw_ctrl_set1); ++ ++ return 0; ++} ++ ++static void mlxbf3_gpio_disable_free(struct pinctrl_dev *pctldev, ++ struct pinctrl_gpio_range *range, ++ unsigned int offset) ++{ ++ struct mlxbf3_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); ++ ++ /* disable GPIO functionality by giving control back to hardware */ ++ if (offset < MLXBF3_NGPIOS_GPIO0) ++ writel(BIT(offset), priv->fw_ctrl_clr0); ++ else ++ writel(BIT(offset % MLXBF3_NGPIOS_GPIO0), priv->fw_ctrl_clr1); ++} ++ ++static const struct pinmux_ops mlxbf3_pmx_ops = { ++ .get_functions_count = mlxbf3_pmx_get_funcs_count, ++ .get_function_name = mlxbf3_pmx_get_func_name, ++ .get_function_groups = mlxbf3_pmx_get_groups, ++ .set_mux = mlxbf3_pmx_set, ++ .gpio_request_enable = mlxbf3_gpio_request_enable, ++ .gpio_disable_free = mlxbf3_gpio_disable_free, ++}; ++ ++static struct pinctrl_desc mlxbf3_pin_desc = { ++ .name = "pinctrl-mlxbf3", ++ .pins = mlxbf3_pins, ++ .npins = ARRAY_SIZE(mlxbf3_pins), ++ .pctlops = &mlxbf3_pinctrl_group_ops, ++ .pmxops = &mlxbf3_pmx_ops, ++ .owner = THIS_MODULE, ++}; ++ ++static_assert(ARRAY_SIZE(mlxbf3_pinctrl_single_group_names) == MLXBF3_MAX_GPIO_PINS); ++ ++static int mlxbf3_pinctrl_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct mlxbf3_pinctrl *priv; ++ int ret; ++ ++ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ priv->dev = &pdev->dev; ++ ++ priv->fw_ctrl_set0 = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(priv->fw_ctrl_set0)) ++ return PTR_ERR(priv->fw_ctrl_set0); ++ ++ priv->fw_ctrl_clr0 = devm_platform_ioremap_resource(pdev, 1); ++ if (IS_ERR(priv->fw_ctrl_set0)) ++ return PTR_ERR(priv->fw_ctrl_set0); ++ ++ priv->fw_ctrl_set1 = devm_platform_ioremap_resource(pdev, 2); ++ if (IS_ERR(priv->fw_ctrl_set0)) ++ return PTR_ERR(priv->fw_ctrl_set0); ++ ++ priv->fw_ctrl_clr1 = devm_platform_ioremap_resource(pdev, 3); ++ if (IS_ERR(priv->fw_ctrl_set0)) ++ return PTR_ERR(priv->fw_ctrl_set0); ++ ++ ret = devm_pinctrl_register_and_init(dev, ++ &mlxbf3_pin_desc, ++ priv, ++ &priv->pctl); ++ if (ret) ++ return dev_err_probe(dev, ret, "Failed to register pinctrl\n"); ++ ++ ret = pinctrl_enable(priv->pctl); ++ if (ret) ++ return dev_err_probe(dev, ret, "Failed to enable pinctrl\n"); ++ ++ pinctrl_add_gpio_ranges(priv->pctl, mlxbf3_pinctrl_gpio_ranges, 2); ++ ++ return 0; ++} ++ ++static const struct acpi_device_id mlxbf3_pinctrl_acpi_ids[] = { ++ { "MLNXBF34", 0 }, ++ {} ++}; ++MODULE_DEVICE_TABLE(acpi, mlxbf3_pinctrl_acpi_ids); ++ ++static struct platform_driver mlxbf3_pinctrl_driver = { ++ .driver = { ++ .name = "pinctrl-mlxbf3", ++ .acpi_match_table = mlxbf3_pinctrl_acpi_ids, ++ }, ++ .probe = mlxbf3_pinctrl_probe, ++}; ++module_platform_driver(mlxbf3_pinctrl_driver); ++ ++MODULE_DESCRIPTION("NVIDIA pinctrl driver"); ++MODULE_AUTHOR("Asmaa Mnebhi "); ++MODULE_LICENSE("Dual BSD/GPL"); +-- +2.14.1 + diff --git a/platform/mellanox/non-upstream-patches/patches/0288-UBUNTU-SAUCE-gpio-mmio-handle-ngpios-properly-in-bgp.patch b/platform/mellanox/non-upstream-patches/patches/0288-UBUNTU-SAUCE-gpio-mmio-handle-ngpios-properly-in-bgp.patch new file mode 100644 index 000000000000..560ab260d602 --- /dev/null +++ b/platform/mellanox/non-upstream-patches/patches/0288-UBUNTU-SAUCE-gpio-mmio-handle-ngpios-properly-in-bgp.patch @@ -0,0 +1,125 @@ +From 99a91873f7fe56dcdb4dc68b5a0766b63465ccbb Mon Sep 17 00:00:00 2001 +From: Asmaa Mnebhi +Date: Thu, 30 Mar 2023 12:25:27 -0400 +Subject: [PATCH 76/77] UBUNTU: SAUCE: gpio: mmio: handle "ngpios" properly in + bgpio_init() +X-NVConfidentiality: public + +BugLink: https://bugs.launchpad.net/bugs/2012743 + +bgpio_init() uses "sz" argument to populate ngpio, which is not +accurate. Instead, read the "ngpios" property from the DT and if it +doesn't exist, use the "sz" argument. With this change, drivers no +longer need to overwrite the ngpio variable after calling bgpio_init(). + +This change has already been approved for upstreaming but has not been +integrated into the linux-next branch yet (or any other branch as a matter +of fact). +There are 2 commits involved: +gpio: mmio: handle "ngpios" properly in bgpio_init() - +gpio: mmio: fix calculation of bgpio_bits + +There is no point in separating these 2 commits into 2 SAUCE patches since +they target the same functionality and will be reverted soon anyways to +cherry-pick the linux-next commits. + +Signed-off-by: Asmaa Mnebhi +Acked-by: Tim Gardner +Acked-by: Bartlomiej Zolnierkiewicz +Signed-off-by: Bartlomiej Zolnierkiewicz +--- + drivers/gpio/gpio-mmio.c | 9 ++++++++- + drivers/gpio/gpiolib.c | 34 ++++++++++++++++++++++++++++++++++ + drivers/gpio/gpiolib.h | 1 + + 3 files changed, 43 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpio/gpio-mmio.c b/drivers/gpio/gpio-mmio.c +index c335a0309..ababc4091 100644 +--- a/drivers/gpio/gpio-mmio.c ++++ b/drivers/gpio/gpio-mmio.c +@@ -60,6 +60,8 @@ o ` ~~~~\___/~~~~ ` controller in FPGA is ,.` + #include + #include + ++#include "gpiolib.h" ++ + static void bgpio_write8(void __iomem *reg, unsigned long data) + { + writeb(data, reg); +@@ -614,10 +616,15 @@ int bgpio_init(struct gpio_chip *gc, struct device *dev, + gc->parent = dev; + gc->label = dev_name(dev); + gc->base = -1; +- gc->ngpio = gc->bgpio_bits; + gc->request = bgpio_request; + gc->be_bits = !!(flags & BGPIOF_BIG_ENDIAN); + ++ ret = gpiochip_get_ngpios(gc, dev); ++ if (ret) ++ gc->ngpio = gc->bgpio_bits; ++ else ++ gc->bgpio_bits = roundup_pow_of_two(round_up(gc->ngpio, 8)); ++ + ret = bgpio_setup_io(gc, dat, set, clr, flags); + if (ret) + return ret; +diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c +index 3e01a3ac6..964f27f4d 100644 +--- a/drivers/gpio/gpiolib.c ++++ b/drivers/gpio/gpiolib.c +@@ -550,6 +550,40 @@ static void machine_gpiochip_add(struct gpio_chip *gc) + mutex_unlock(&gpio_machine_hogs_mutex); + } + ++int gpiochip_get_ngpios(struct gpio_chip *gc, struct device *dev) ++{ ++ u32 ngpios = gc->ngpio; ++ int ret; ++ ++ if (ngpios == 0) { ++ ret = device_property_read_u32(dev, "ngpios", &ngpios); ++ if (ret == -ENODATA) ++ /* ++ * -ENODATA means that there is no property found and ++ * we want to issue the error message to the user. ++ * Besides that, we want to return different error code ++ * to state that supplied value is not valid. ++ */ ++ ngpios = 0; ++ else if (ret) ++ return ret; ++ ++ gc->ngpio = ngpios; ++ } ++ ++ if (gc->ngpio == 0) { ++ chip_err(gc, "tried to insert a GPIO chip with zero lines\n"); ++ return -EINVAL; ++ } ++ ++ if (gc->ngpio > FASTPATH_NGPIO) ++ chip_warn(gc, "line cnt %u is greater than fast path cnt %u\n", ++ gc->ngpio, FASTPATH_NGPIO); ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(gpiochip_get_ngpios); ++ + static void gpiochip_setup_devs(void) + { + struct gpio_device *gdev; +diff --git a/drivers/gpio/gpiolib.h b/drivers/gpio/gpiolib.h +index b674b5bb9..7c26a0060 100644 +--- a/drivers/gpio/gpiolib.h ++++ b/drivers/gpio/gpiolib.h +@@ -136,6 +136,7 @@ int gpiod_configure_flags(struct gpio_desc *desc, const char *con_id, + unsigned long lflags, enum gpiod_flags dflags); + int gpiod_hog(struct gpio_desc *desc, const char *name, + unsigned long lflags, enum gpiod_flags dflags); ++int gpiochip_get_ngpios(struct gpio_chip *gc, struct device *dev); + + /* + * Return the GPIO number of the passed descriptor relative to its chip +-- +2.14.1 + diff --git a/platform/mellanox/non-upstream-patches/patches/0289-UBUNTU-SAUCE-gpio-mlxbf3-Add-gpio-driver-support.patch b/platform/mellanox/non-upstream-patches/patches/0289-UBUNTU-SAUCE-gpio-mlxbf3-Add-gpio-driver-support.patch new file mode 100644 index 000000000000..c5c2096917af --- /dev/null +++ b/platform/mellanox/non-upstream-patches/patches/0289-UBUNTU-SAUCE-gpio-mlxbf3-Add-gpio-driver-support.patch @@ -0,0 +1,488 @@ +From d189171aa3b9e01b2e2d022f375f999a4a68d525 Mon Sep 17 00:00:00 2001 +From: Asmaa Mnebhi +Date: Thu, 30 Mar 2023 12:38:19 -0400 +Subject: [PATCH 77/77] UBUNTU: SAUCE: gpio: mlxbf3: Add gpio driver support +X-NVConfidentiality: public + +BugLink: https://bugs.launchpad.net/bugs/2012743 + +Add support for the BlueField-3 SoC GPIO driver. +This driver configures and handles GPIO interrupts. It also enables +a user to manipulate certain GPIO pins via libgpiod tools or other kernel drivers. + +The gpio-mlxbf3.c driver has already been approved for upstreaming +but is not yet available for cherry-picking. + +Signed-off-by: Asmaa Mnebhi +Acked-by: Tim Gardner +Acked-by: Bartlomiej Zolnierkiewicz +Signed-off-by: Bartlomiej Zolnierkiewicz +--- + drivers/gpio/Kconfig | 10 +- + drivers/gpio/gpio-mlxbf3.c | 285 +++++++++++++++++---------------------------- + 2 files changed, 116 insertions(+), 179 deletions(-) + +diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig +index bf1b2b787..a31b7ffea 100644 +--- a/drivers/gpio/Kconfig ++++ b/drivers/gpio/Kconfig +@@ -1461,10 +1461,16 @@ config GPIO_MLXBF2 + + config GPIO_MLXBF3 + tristate "Mellanox BlueField 3 SoC GPIO" +- depends on (MELLANOX_PLATFORM && ARM64 && ACPI) || (64BIT && COMPILE_TEST) ++ depends on (MELLANOX_PLATFORM && ARM64) || COMPILE_TEST + select GPIO_GENERIC ++ select GPIOLIB_IRQCHIP + help +- Say Y here if you want GPIO support on Mellanox BlueField 3 SoC. ++ Say Y if you want GPIO support on Mellanox BlueField 3 SoC. ++ This GPIO controller supports interrupt handling and enables the ++ manipulation of certain GPIO pins. ++ This controller should be used in parallel with pinctrl-mlxbf3 to ++ control the desired GPIOs. ++ This driver can also be built as a module called mlxbf3-gpio. + + config GPIO_ML_IOH + tristate "OKI SEMICONDUCTOR ML7213 IOH GPIO support" +diff --git a/drivers/gpio/gpio-mlxbf3.c b/drivers/gpio/gpio-mlxbf3.c +index 45f0946ac..51dce3ae1 100644 +--- a/drivers/gpio/gpio-mlxbf3.c ++++ b/drivers/gpio/gpio-mlxbf3.c +@@ -1,27 +1,20 @@ + // SPDX-License-Identifier: GPL-2.0-only or BSD-3-Clause ++/* Copyright (C) 2021-2023 NVIDIA CORPORATION & AFFILIATES */ + +-/* +- * Copyright (C) 2020-2021 NVIDIA CORPORATION & AFFILIATES +- */ +- +-#include + #include + #include + #include ++#include + #include + #include + #include +-#include +-#include +-#include + #include + #include +-#include +-#include + #include + #include ++#include + +-#define DRV_VERSION "1.0" ++#define DRV_VERSION "2.0" + + /* + * There are 2 YU GPIO blocks: +@@ -33,103 +26,51 @@ + /* + * fw_gpio[x] block registers and their offset + */ +-#define YU_GPIO_FW_CONTROL_SET 0x00 +-#define YU_GPIO_FW_OUTPUT_ENABLE_SET 0x04 +-#define YU_GPIO_FW_DATA_OUT_SET 0x08 +-#define YU_GPIO_FW_CONTROL_CLEAR 0x14 +-#define YU_GPIO_FW_OUTPUT_ENABLE_CLEAR 0x18 +-#define YU_GPIO_FW_DATA_OUT_CLEAR 0x1c +-#define YU_GPIO_CAUSE_RISE_EN 0x28 +-#define YU_GPIO_CAUSE_FALL_EN 0x2c +-#define YU_GPIO_READ_DATA_IN 0x30 +-#define YU_GPIO_READ_OUTPUT_ENABLE 0x34 +-#define YU_GPIO_READ_DATA_OUT 0x38 +-#define YU_GPIO_READ_FW_CONTROL 0x44 +- +-#define YU_GPIO_CAUSE_OR_CAUSE_EVTEN0 0x00 +-#define YU_GPIO_CAUSE_OR_EVTEN0 0x14 +-#define YU_GPIO_CAUSE_OR_CLRCAUSE 0x18 +- +-/* BlueField-3 gpio block context structure. */ ++#define MLXBF_GPIO_FW_OUTPUT_ENABLE_SET 0x00 ++#define MLXBF_GPIO_FW_DATA_OUT_SET 0x04 ++ ++#define MLXBF_GPIO_FW_OUTPUT_ENABLE_CLEAR 0x00 ++#define MLXBF_GPIO_FW_DATA_OUT_CLEAR 0x04 ++ ++#define MLXBF_GPIO_CAUSE_RISE_EN 0x00 ++#define MLXBF_GPIO_CAUSE_FALL_EN 0x04 ++#define MLXBF_GPIO_READ_DATA_IN 0x08 ++ ++#define MLXBF_GPIO_CAUSE_OR_CAUSE_EVTEN0 0x00 ++#define MLXBF_GPIO_CAUSE_OR_EVTEN0 0x14 ++#define MLXBF_GPIO_CAUSE_OR_CLRCAUSE 0x18 ++ + struct mlxbf3_gpio_context { + struct gpio_chip gc; +- struct irq_chip irq_chip; + +- /* YU GPIO blocks address */ ++ /* YU GPIO block address */ ++ void __iomem *gpio_set_io; ++ void __iomem *gpio_clr_io; + void __iomem *gpio_io; + + /* YU GPIO cause block address */ + void __iomem *gpio_cause_io; + +- uint32_t ctrl_gpio_mask; ++ /* Mask of valid gpios that can be accessed by software */ ++ unsigned int valid_mask; + }; + +-static void mlxbf3_gpio_set(struct gpio_chip *chip, unsigned int offset, int val) +-{ +- struct mlxbf3_gpio_context *gs = gpiochip_get_data(chip); +- +- /* Software can only control GPIO pins defined by ctrl_gpio_mask */ +- if (!(BIT(offset) & gs->ctrl_gpio_mask)) +- return; +- +- if (val) { +- writel(BIT(offset), gs->gpio_io + YU_GPIO_FW_DATA_OUT_SET); +- } else { +- writel(BIT(offset), gs->gpio_io + YU_GPIO_FW_DATA_OUT_CLEAR); +- } +- +- wmb(); +- +- /* This needs to be done last to avoid glitches */ +- writel(BIT(offset), gs->gpio_io + YU_GPIO_FW_CONTROL_SET); +-} +- +-static int mlxbf3_gpio_direction_input(struct gpio_chip *chip, +- unsigned int offset) +-{ +- struct mlxbf3_gpio_context *gs = gpiochip_get_data(chip); +- unsigned long flags; +- +- spin_lock_irqsave(&gs->gc.bgpio_lock, flags); +- +- writel(BIT(offset), gs->gpio_io + YU_GPIO_FW_OUTPUT_ENABLE_CLEAR); +- writel(BIT(offset), gs->gpio_io + YU_GPIO_FW_CONTROL_CLEAR); +- +- spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); +- +- return 0; +-} +- +-static int mlxbf3_gpio_direction_output(struct gpio_chip *chip, +- unsigned int offset, +- int value) +-{ +- struct mlxbf3_gpio_context *gs = gpiochip_get_data(chip); +- unsigned long flags; +- +- spin_lock_irqsave(&gs->gc.bgpio_lock, flags); +- +- writel(BIT(offset), gs->gpio_io + YU_GPIO_FW_OUTPUT_ENABLE_SET); +- +- spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); +- +- return 0; +-} +- + static void mlxbf3_gpio_irq_enable(struct irq_data *irqd) + { + struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); + struct mlxbf3_gpio_context *gs = gpiochip_get_data(gc); +- int offset = irqd_to_hwirq(irqd); ++ irq_hw_number_t offset = irqd_to_hwirq(irqd); + unsigned long flags; + u32 val; + ++ gpiochip_enable_irq(gc, offset); ++ + spin_lock_irqsave(&gs->gc.bgpio_lock, flags); +- writel(BIT(offset), gs->gpio_cause_io + YU_GPIO_CAUSE_OR_CLRCAUSE); ++ writel(BIT(offset), gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE); + +- val = readl(gs->gpio_cause_io + YU_GPIO_CAUSE_OR_EVTEN0); ++ val = readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0); + val |= BIT(offset); +- writel(val, gs->gpio_cause_io + YU_GPIO_CAUSE_OR_EVTEN0); ++ writel(val, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0); + spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); + } + +@@ -137,15 +78,17 @@ static void mlxbf3_gpio_irq_disable(struct irq_data *irqd) + { + struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); + struct mlxbf3_gpio_context *gs = gpiochip_get_data(gc); +- int offset = irqd_to_hwirq(irqd); ++ irq_hw_number_t offset = irqd_to_hwirq(irqd); + unsigned long flags; + u32 val; + + spin_lock_irqsave(&gs->gc.bgpio_lock, flags); +- val = readl(gs->gpio_cause_io + YU_GPIO_CAUSE_OR_EVTEN0); ++ val = readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0); + val &= ~BIT(offset); +- writel(val, gs->gpio_cause_io + YU_GPIO_CAUSE_OR_EVTEN0); ++ writel(val, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0); + spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); ++ ++ gpiochip_disable_irq(gc, offset); + } + + static irqreturn_t mlxbf3_gpio_irq_handler(int irq, void *ptr) +@@ -155,8 +98,8 @@ static irqreturn_t mlxbf3_gpio_irq_handler(int irq, void *ptr) + unsigned long pending; + u32 level; + +- pending = readl(gs->gpio_cause_io + YU_GPIO_CAUSE_OR_CAUSE_EVTEN0); +- writel(pending, gs->gpio_cause_io + YU_GPIO_CAUSE_OR_CLRCAUSE); ++ pending = readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CAUSE_EVTEN0); ++ writel(pending, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE); + + for_each_set_bit(level, &pending, gc->ngpio) { + int gpio_irq = irq_find_mapping(gc->irq.domain, level); +@@ -171,155 +114,145 @@ mlxbf3_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) + { + struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); + struct mlxbf3_gpio_context *gs = gpiochip_get_data(gc); +- int offset = irqd_to_hwirq(irqd); ++ irq_hw_number_t offset = irqd_to_hwirq(irqd); + unsigned long flags; +- bool fall = false; +- bool rise = false; + u32 val; + ++ spin_lock_irqsave(&gs->gc.bgpio_lock, flags); ++ + switch (type & IRQ_TYPE_SENSE_MASK) { + case IRQ_TYPE_EDGE_BOTH: +- fall = true; +- rise = true; ++ val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN); ++ val |= BIT(offset); ++ writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN); ++ val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN); ++ val |= BIT(offset); ++ writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN); + break; + case IRQ_TYPE_EDGE_RISING: +- rise = true; ++ val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN); ++ val |= BIT(offset); ++ writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_RISE_EN); + break; + case IRQ_TYPE_EDGE_FALLING: +- fall = true; ++ val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN); ++ val |= BIT(offset); ++ writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN); + break; + default: ++ spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); + return -EINVAL; + } + +- spin_lock_irqsave(&gs->gc.bgpio_lock, flags); +- if (fall) { +- val = readl(gs->gpio_io + YU_GPIO_CAUSE_FALL_EN); +- val |= BIT(offset); +- writel(val, gs->gpio_io + YU_GPIO_CAUSE_FALL_EN); +- } +- +- if (rise) { +- val = readl(gs->gpio_io + YU_GPIO_CAUSE_RISE_EN); +- val |= BIT(offset); +- writel(val, gs->gpio_io + YU_GPIO_CAUSE_RISE_EN); +- } + spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags); + ++ irq_set_handler_locked(irqd, handle_edge_irq); ++ + return 0; + } + +-/* BlueField-3 GPIO driver initialization routine. */ +-static int +-mlxbf3_gpio_probe(struct platform_device *pdev) ++/* This function needs to be defined for handle_edge_irq() */ ++static void mlxbf3_gpio_irq_ack(struct irq_data *data) ++{ ++} ++ ++static int mlxbf3_gpio_init_valid_mask(struct gpio_chip *gc, ++ unsigned long *valid_mask, ++ unsigned int ngpios) ++{ ++ struct mlxbf3_gpio_context *gs = gpiochip_get_data(gc); ++ ++ *valid_mask = gs->valid_mask; ++ ++ return 0; ++} ++ ++static struct irq_chip gpio_mlxbf3_irqchip = { ++ .name = "MLNXBF33", ++ .irq_ack = mlxbf3_gpio_irq_ack, ++ .irq_set_type = mlxbf3_gpio_irq_set_type, ++ .irq_enable = mlxbf3_gpio_irq_enable, ++ .irq_disable = mlxbf3_gpio_irq_disable, ++}; ++ ++static int mlxbf3_gpio_probe(struct platform_device *pdev) + { +- struct mlxbf3_gpio_context *gs; + struct device *dev = &pdev->dev; ++ struct mlxbf3_gpio_context *gs; + struct gpio_irq_chip *girq; + struct gpio_chip *gc; +- unsigned int npins; +- const char *name; + int ret, irq; + +- name = dev_name(dev); +- + gs = devm_kzalloc(dev, sizeof(*gs), GFP_KERNEL); + if (!gs) + return -ENOMEM; + +- /* YU GPIO block address */ + gs->gpio_io = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(gs->gpio_io)) + return PTR_ERR(gs->gpio_io); + +- /* YU GPIO block address */ + gs->gpio_cause_io = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(gs->gpio_cause_io)) + return PTR_ERR(gs->gpio_cause_io); + +- if (device_property_read_u32(dev, "npins", &npins)) +- npins = MLXBF3_GPIO_MAX_PINS_PER_BLOCK; ++ gs->gpio_set_io = devm_platform_ioremap_resource(pdev, 2); ++ if (IS_ERR(gs->gpio_set_io)) ++ return PTR_ERR(gs->gpio_set_io); + +- if (device_property_read_u32(dev, "ctrl_gpio_mask", &gs->ctrl_gpio_mask)) +- gs->ctrl_gpio_mask = 0x0; ++ gs->gpio_clr_io = devm_platform_ioremap_resource(pdev, 3); ++ if (IS_ERR(gs->gpio_clr_io)) ++ return PTR_ERR(gs->gpio_clr_io); ++ ++ gs->valid_mask = 0x0; ++ device_property_read_u32(dev, "valid_mask", &gs->valid_mask); + + gc = &gs->gc; + +- /* To set the direction to input, just give control to HW by setting +- * YU_GPIO_FW_CONTROL_CLEAR. +- * If the GPIO is controlled by HW, read its value via read_data_in register. +- * +- * When the direction = output, the GPIO is controlled by SW and +- * datain=dataout. If software modifies the value of the GPIO pin, +- * the value can be read from read_data_in without changing the direction. +- */ + ret = bgpio_init(gc, dev, 4, +- gs->gpio_io + YU_GPIO_READ_DATA_IN, +- NULL, +- NULL, +- NULL, +- NULL, +- 0); +- +- gc->set = mlxbf3_gpio_set; +- gc->direction_input = mlxbf3_gpio_direction_input; +- gc->direction_output = mlxbf3_gpio_direction_output; +- +- gc->ngpio = npins; ++ gs->gpio_io + MLXBF_GPIO_READ_DATA_IN, ++ gs->gpio_set_io + MLXBF_GPIO_FW_DATA_OUT_SET, ++ gs->gpio_clr_io + MLXBF_GPIO_FW_DATA_OUT_CLEAR, ++ gs->gpio_set_io + MLXBF_GPIO_FW_OUTPUT_ENABLE_SET, ++ gs->gpio_clr_io + MLXBF_GPIO_FW_OUTPUT_ENABLE_CLEAR, 0); ++ ++ gc->request = gpiochip_generic_request; ++ gc->free = gpiochip_generic_free; + gc->owner = THIS_MODULE; ++ gc->init_valid_mask = mlxbf3_gpio_init_valid_mask; + + irq = platform_get_irq(pdev, 0); + if (irq >= 0) { +- gs->irq_chip.name = name; +- gs->irq_chip.irq_set_type = mlxbf3_gpio_irq_set_type; +- gs->irq_chip.irq_enable = mlxbf3_gpio_irq_enable; +- gs->irq_chip.irq_disable = mlxbf3_gpio_irq_disable; +- + girq = &gs->gc.irq; +- girq->chip = &gs->irq_chip; +- girq->handler = handle_simple_irq; ++ girq->chip = &gpio_mlxbf3_irqchip; + girq->default_type = IRQ_TYPE_NONE; + /* This will let us handle the parent IRQ in the driver */ + girq->num_parents = 0; + girq->parents = NULL; + girq->parent_handler = NULL; ++ girq->handler = handle_bad_irq; + + /* + * Directly request the irq here instead of passing + * a flow-handler because the irq is shared. + */ + ret = devm_request_irq(dev, irq, mlxbf3_gpio_irq_handler, +- IRQF_SHARED, name, gs); +- if (ret) { +- dev_err(dev, "failed to request IRQ"); +- return ret; +- } ++ IRQF_SHARED, dev_name(dev), gs); ++ if (ret) ++ return dev_err_probe(dev, ret, "failed to request IRQ"); + } + + platform_set_drvdata(pdev, gs); + + ret = devm_gpiochip_add_data(dev, &gs->gc, gs); +- if (ret) { +- dev_err(dev, "Failed adding memory mapped gpiochip\n"); +- return ret; +- } +- +- return 0; +-} +- +-static int mlxbf3_gpio_remove(struct platform_device *pdev) +-{ +- struct mlxbf3_gpio_context *gs = platform_get_drvdata(pdev); +- +- /* Set the GPIO control back to HW */ +- writel(gs->ctrl_gpio_mask, gs->gpio_io + YU_GPIO_FW_CONTROL_CLEAR); ++ if (ret) ++ dev_err_probe(dev, ret, "Failed adding memory mapped gpiochip\n"); + + return 0; + } + +-static const struct acpi_device_id __maybe_unused mlxbf3_gpio_acpi_match[] = { ++static const struct acpi_device_id mlxbf3_gpio_acpi_match[] = { + { "MLNXBF33", 0 }, +- {}, ++ {} + }; + MODULE_DEVICE_TABLE(acpi, mlxbf3_gpio_acpi_match); + +@@ -329,12 +262,10 @@ static struct platform_driver mlxbf3_gpio_driver = { + .acpi_match_table = mlxbf3_gpio_acpi_match, + }, + .probe = mlxbf3_gpio_probe, +- .remove = mlxbf3_gpio_remove, + }; +- + module_platform_driver(mlxbf3_gpio_driver); + +-MODULE_DESCRIPTION("Mellanox BlueField-3 GPIO Driver"); ++MODULE_DESCRIPTION("NVIDIA BlueField-3 GPIO Driver"); + MODULE_AUTHOR("Asmaa Mnebhi "); + MODULE_LICENSE("Dual BSD/GPL"); + MODULE_VERSION(DRV_VERSION); +-- +2.14.1 + diff --git a/platform/mellanox/non-upstream-patches/patches/0283-mlxsw-core_hwmon-Align-modules-label-name-assignment.patch b/platform/mellanox/non-upstream-patches/patches/0291-mlxsw-core_hwmon-Align-modules-label-name-assignment.patch similarity index 93% rename from platform/mellanox/non-upstream-patches/patches/0283-mlxsw-core_hwmon-Align-modules-label-name-assignment.patch rename to platform/mellanox/non-upstream-patches/patches/0291-mlxsw-core_hwmon-Align-modules-label-name-assignment.patch index 15d55ab0c345..e19583d193d8 100644 --- a/platform/mellanox/non-upstream-patches/patches/0283-mlxsw-core_hwmon-Align-modules-label-name-assignment.patch +++ b/platform/mellanox/non-upstream-patches/patches/0291-mlxsw-core_hwmon-Align-modules-label-name-assignment.patch @@ -17,8 +17,8 @@ For example, temperatures for module#1, module#2 will be exposed like: front panel 002: +37.0°C (crit = +70.0°C, emerg = +75.0°C) front panel 003: +47.0°C (crit = +70.0°C, emerg = +75.0°C) instead of: -front panel 001: +37.0°C (crit = +70.0°C, emerg = +75.0°C) -front panel 002: +47.0°C (crit = +70.0°C, emerg = +75.0°C) +front panel 002: +37.0°C (crit = +70.0°C, emerg = +75.0°C) +front panel 003: +47.0°C (crit = +70.0°C, emerg = +75.0°C) Set 'index' used in label name according to the 'sensor_count' value. diff --git a/platform/mellanox/non-upstream-patches/patches/0292-mlxsw-i2c-Limit-single-transaction-buffer-size.patch b/platform/mellanox/non-upstream-patches/patches/0292-mlxsw-i2c-Limit-single-transaction-buffer-size.patch new file mode 100644 index 000000000000..1fffd92e5964 --- /dev/null +++ b/platform/mellanox/non-upstream-patches/patches/0292-mlxsw-i2c-Limit-single-transaction-buffer-size.patch @@ -0,0 +1,45 @@ +From 3363b3f15f1f65c5b33c464c1bb9d71fc044d3a8 Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Thu, 6 Jul 2023 04:51:52 +0000 +Subject: [PATH backport 1/2] mlxsw: i2c: Limit single transaction buffer size + +Maximum size of buffer is obtained from underlying I2C adapter and in +case adapter allows I2C transaction buffer size greater than 100 bytes, +transaction will fail due to firmware limitation. +Limit the maximum size of transaction buffer by 100 bytes to fit to +firmware. + +Fixes: 3029a693beda ("mlxsw: i2c: Allow flexible setting of I2C transactions size") +Signed-off-by: Vadim Pasternak +--- + drivers/net/ethernet/mellanox/mlxsw/i2c.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/drivers/net/ethernet/mellanox/mlxsw/i2c.c b/drivers/net/ethernet/mellanox/mlxsw/i2c.c +index e04557afc..9fe03dd9e 100644 +--- a/drivers/net/ethernet/mellanox/mlxsw/i2c.c ++++ b/drivers/net/ethernet/mellanox/mlxsw/i2c.c +@@ -48,6 +48,7 @@ + #define MLXSW_I2C_MBOX_SIZE_BITS 12 + #define MLXSW_I2C_ADDR_BUF_SIZE 4 + #define MLXSW_I2C_BLK_DEF 32 ++#define MLXSW_I2C_BLK_MAX 100 + #define MLXSW_I2C_RETRY 5 + #define MLXSW_I2C_TIMEOUT_MSECS 5000 + #define MLXSW_I2C_MAX_DATA_SIZE 256 +@@ -700,9 +701,10 @@ static int mlxsw_i2c_probe(struct i2c_client *client, + return -EOPNOTSUPP; + } + +- mlxsw_i2c->block_size = max_t(u16, MLXSW_I2C_BLK_DEF, ++ mlxsw_i2c->block_size = min_t(u16, MLXSW_I2C_BLK_MAX, ++ max_t(u16, MLXSW_I2C_BLK_DEF, + min_t(u16, quirks->max_read_len, +- quirks->max_write_len)); ++ quirks->max_write_len))); + } else { + mlxsw_i2c->block_size = MLXSW_I2C_BLK_DEF; + } +-- +2.20.1 + diff --git a/platform/mellanox/non-upstream-patches/patches/0293-mlxsw-reg-Limit-MTBR-register-records-buffer-by-one-.patch b/platform/mellanox/non-upstream-patches/patches/0293-mlxsw-reg-Limit-MTBR-register-records-buffer-by-one-.patch new file mode 100644 index 000000000000..ebbdb451d113 --- /dev/null +++ b/platform/mellanox/non-upstream-patches/patches/0293-mlxsw-reg-Limit-MTBR-register-records-buffer-by-one-.patch @@ -0,0 +1,33 @@ +From d11192c5d4622552cd399194bf90af03ea2495a5 Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Thu, 6 Jul 2023 07:40:34 +0000 +Subject: [PATH backport 2/2] mlxsw: reg: Limit MTBR register records buffer by + one record + +The MTBR register is used to obtain specific cable status, so just only +one data record is required in transaction. + +Limit size of MTBR register to avoid sending redundant size of buffer +to firmware. + +Signed-off-by: Vadim Pasternak +--- + drivers/net/ethernet/mellanox/mlxsw/reg.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h +index f8c828e05..81b4278fc 100644 +--- a/drivers/net/ethernet/mellanox/mlxsw/reg.h ++++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h +@@ -8771,7 +8771,7 @@ MLXSW_ITEM_BIT_ARRAY(reg, mtwe, sensor_warning, 0x0, 0x10, 1); + #define MLXSW_REG_MTBR_ID 0x900F + #define MLXSW_REG_MTBR_BASE_LEN 0x10 /* base length, without records */ + #define MLXSW_REG_MTBR_REC_LEN 0x04 /* record length */ +-#define MLXSW_REG_MTBR_REC_MAX_COUNT 47 /* firmware limitation */ ++#define MLXSW_REG_MTBR_REC_MAX_COUNT 1 + #define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN + \ + MLXSW_REG_MTBR_REC_LEN * \ + MLXSW_REG_MTBR_REC_MAX_COUNT) +-- +2.20.1 + diff --git a/platform/mellanox/non-upstream-patches/patches/0296-UBUNTU-SAUCE-mmc-sdhci-of-dwcmshc-Add-runtime-PM-ope.patch b/platform/mellanox/non-upstream-patches/patches/0296-UBUNTU-SAUCE-mmc-sdhci-of-dwcmshc-Add-runtime-PM-ope.patch new file mode 100644 index 000000000000..00f87c6050fa --- /dev/null +++ b/platform/mellanox/non-upstream-patches/patches/0296-UBUNTU-SAUCE-mmc-sdhci-of-dwcmshc-Add-runtime-PM-ope.patch @@ -0,0 +1,159 @@ +From 48ac30096b7a3993f8711c0c3e09a0f06ea9639d Mon Sep 17 00:00:00 2001 +From: Liming Sun +Date: Tue, 4 Apr 2023 19:30:00 -0400 +Subject: [PATCH] UBUNTU: SAUCE: mmc: sdhci-of-dwcmshc: Add runtime PM + operations for BlueField-3 +X-NVConfidentiality: public + +BugLink: https://bugs.launchpad.net/bugs/2015307 + +This commit implements the runtime PM operations For BlueField-3 SoC +to disable eMMC card clock when idle. + +Reviewed-by: Khalil Blaiech +Signed-off-by: Liming Sun +Acked-by: Bartlomiej Zolnierkiewicz +Acked-by: Andrei Gherzan +[bzolnier: use a short URL version for BugLink] +Signed-off-by: Bartlomiej Zolnierkiewicz +--- + drivers/mmc/host/sdhci-of-dwcmshc.c | 102 +++++++++++++++++++++++++++++++++++- + 1 file changed, 101 insertions(+), 1 deletion(-) + +diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c +index af995dc30..cc6b948d4 100644 +--- a/drivers/mmc/host/sdhci-of-dwcmshc.c ++++ b/drivers/mmc/host/sdhci-of-dwcmshc.c +@@ -16,6 +16,7 @@ + #include + #include + #include ++#include + + #include "sdhci-pltfm.h" + +@@ -72,6 +73,21 @@ struct dwcmshc_priv { + void *priv; /* pointer to SoC private stuff */ + }; + ++/* Last jiffies when entering idle state */ ++static uint64_t idle_last_jiffies; ++ ++/* Total jiffies in idle state */ ++static uint64_t idle_total_jiffies; ++ ++/* Total idle time */ ++static int idle_time; ++module_param(idle_time, int, 0444); ++MODULE_PARM_DESC(idle_time, "idle time (seconds)"); ++ ++/* The current idle state */ ++static int idle_state; ++module_param(idle_state, int, 0444); ++MODULE_PARM_DESC(idle_state, "idle state (0: not idle, 1: idle)"); + /* + * If DMA addr spans 128MB boundary, we split the DMA transfer into two + * so that each DMA transfer doesn't exceed the boundary. +@@ -432,6 +448,7 @@ static int dwcmshc_probe(struct platform_device *pdev) + #ifdef CONFIG_ACPI + if (pltfm_data == &sdhci_dwcmshc_bf3_pdata) { + sdhci_enable_v4_mode(host); ++ pm_runtime_enable(dev); + } + #endif + +@@ -526,7 +543,90 @@ static int dwcmshc_resume(struct device *dev) + } + #endif + +-static SIMPLE_DEV_PM_OPS(dwcmshc_pmops, dwcmshc_suspend, dwcmshc_resume); ++#ifdef CONFIG_PM ++ ++#ifdef CONFIG_ACPI ++static void dwcmshc_enable_card_clk(struct sdhci_host *host) ++{ ++ u16 ctrl; ++ ++ ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); ++ ctrl |= SDHCI_CLOCK_CARD_EN; ++ sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); ++} ++ ++static void dwcmshc_disable_card_clk(struct sdhci_host *host) ++{ ++ u16 ctrl; ++ ++ ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); ++ ctrl &= ~SDHCI_CLOCK_CARD_EN; ++ sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); ++} ++#endif ++ ++static int dwcmshc_runtime_suspend(struct device *dev) ++{ ++ struct sdhci_host *host = dev_get_drvdata(dev); ++ const struct sdhci_pltfm_data *pltfm_data; ++ int ret = 0; ++ ++ pltfm_data = device_get_match_data(dev); ++ if (!pltfm_data) ++ return -ENODEV; ++ ++#ifdef CONFIG_ACPI ++ if (pltfm_data == &sdhci_dwcmshc_bf3_pdata) { ++ ret = sdhci_runtime_suspend_host(host); ++ if (!ret) { ++ dwcmshc_disable_card_clk(host); ++ ++ if (!idle_state) { ++ idle_state = 1; ++ idle_last_jiffies = jiffies; ++ } ++ } ++ } ++#endif ++ ++ return ret; ++} ++ ++static int dwcmshc_runtime_resume(struct device *dev) ++{ ++ struct sdhci_host *host = dev_get_drvdata(dev); ++ const struct sdhci_pltfm_data *pltfm_data; ++ int ret = 0; ++ ++ pltfm_data = device_get_match_data(dev); ++ if (!pltfm_data) ++ return -ENODEV; ++ ++#ifdef CONFIG_ACPI ++ if (pltfm_data == &sdhci_dwcmshc_bf3_pdata) { ++ dwcmshc_enable_card_clk(host); ++ ++ if (idle_state) { ++ idle_state = 0; ++ idle_total_jiffies = jiffies - idle_last_jiffies; ++ idle_time += jiffies_to_msecs( ++ idle_total_jiffies) / 1000; ++ } ++ ++ ret = sdhci_runtime_resume_host(host, 0); ++ } ++#endif ++ ++ return ret; ++} ++ ++#endif ++ ++static const struct dev_pm_ops dwcmshc_pmops = { ++ SET_SYSTEM_SLEEP_PM_OPS(dwcmshc_suspend, dwcmshc_resume) ++ SET_RUNTIME_PM_OPS(dwcmshc_runtime_suspend, ++ dwcmshc_runtime_resume, NULL) ++}; + + static struct platform_driver sdhci_dwcmshc_driver = { + .driver = { +-- +2.14.1 + diff --git a/platform/mellanox/non-upstream-patches/patches/0298-UBUNTU-SAUCE-mlxbf-ptm-use-0444-instead-of-S_IRUGO.patch b/platform/mellanox/non-upstream-patches/patches/0298-UBUNTU-SAUCE-mlxbf-ptm-use-0444-instead-of-S_IRUGO.patch new file mode 100644 index 000000000000..ce0a48ea7e2b --- /dev/null +++ b/platform/mellanox/non-upstream-patches/patches/0298-UBUNTU-SAUCE-mlxbf-ptm-use-0444-instead-of-S_IRUGO.patch @@ -0,0 +1,64 @@ +From 6066741b9491d990cea962e7e56c0d3d4f7bc393 Mon Sep 17 00:00:00 2001 +From: Jitendra Lanka +Date: Wed, 22 Mar 2023 11:39:55 -0400 +Subject: [PATCH] UBUNTU: SAUCE: mlxbf-ptm: use 0444 instead of S_IRUGO +X-NVConfidentiality: public + +BugLink: https://bugs.launchpad.net/bugs/2011738 + +As recommended by checkscript, change S_IRUGO to 0444 + +Signed-off-by: Jitendra Lanka +Acked-by: Tim Gardner +Acked-by: Bartlomiej Zolnierkiewicz +Signed-off-by: Bartlomiej Zolnierkiewicz +--- + drivers/platform/mellanox/mlxbf-ptm.c | 22 +++++++++++----------- + 1 file changed, 11 insertions(+), 11 deletions(-) + +diff --git a/drivers/platform/mellanox/mlxbf-ptm.c b/drivers/platform/mellanox/mlxbf-ptm.c +index 79c3e2902..aeb68dc42 100644 +--- a/drivers/platform/mellanox/mlxbf-ptm.c ++++ b/drivers/platform/mellanox/mlxbf-ptm.c +@@ -154,27 +154,27 @@ static int __init mlxbf_ptm_init(void) + monitors = debugfs_create_dir("monitors", ptm_root); + status = debugfs_create_dir("status", monitors); + +- debugfs_create_file("vr0_power", S_IRUGO, status, NULL, ++ debugfs_create_file("vr0_power", 0444, status, NULL, + &vr0_power_fops); +- debugfs_create_file("vr1_power", S_IRUGO, status, NULL, ++ debugfs_create_file("vr1_power", 0444, status, NULL, + &vr1_power_fops); +- debugfs_create_file("total_power", S_IRUGO, status, NULL, ++ debugfs_create_file("total_power", 0444, status, NULL, + &total_power_fops); +- debugfs_create_file("ddr_temp", S_IRUGO, status, ++ debugfs_create_file("ddr_temp", 0444, status, + NULL, &ddr_thld_fops); +- debugfs_create_file("core_temp", S_IRUGO, status, ++ debugfs_create_file("core_temp", 0444, status, + NULL, &core_temp_fops); +- debugfs_create_file("power_throttling_event_count", S_IRUGO, status, ++ debugfs_create_file("power_throttling_event_count", 0444, status, + NULL, &pwr_evt_counter_fops); +- debugfs_create_file("thermal_throttling_event_count", S_IRUGO, status, ++ debugfs_create_file("thermal_throttling_event_count", 0444, status, + NULL, &temp_evt_counter_fops); +- debugfs_create_file("throttling_state", S_IRUGO, status, ++ debugfs_create_file("throttling_state", 0444, status, + NULL, &throttling_state_fops); +- debugfs_create_file("power_throttling_state", S_IRUGO, status, ++ debugfs_create_file("power_throttling_state", 0444, status, + NULL, &pthrottling_state_fops); +- debugfs_create_file("thermal_throttling_state", S_IRUGO, status, ++ debugfs_create_file("thermal_throttling_state", 0444, status, + NULL, &tthrottling_state_fops); +- debugfs_create_file("error_state", S_IRUGO, status, ++ debugfs_create_file("error_state", 0444, status, + NULL, &error_status_fops); + + return 0; +-- +2.14.1 + diff --git a/platform/mellanox/non-upstream-patches/patches/0299-UBUNTU-SAUCE-mlxbf-ptm-add-atx-debugfs-nodes.patch b/platform/mellanox/non-upstream-patches/patches/0299-UBUNTU-SAUCE-mlxbf-ptm-add-atx-debugfs-nodes.patch new file mode 100644 index 000000000000..dad2943f0586 --- /dev/null +++ b/platform/mellanox/non-upstream-patches/patches/0299-UBUNTU-SAUCE-mlxbf-ptm-add-atx-debugfs-nodes.patch @@ -0,0 +1,83 @@ +From e6e21f6d79e1ccd2a88817c982f8350e5a1dfa92 Mon Sep 17 00:00:00 2001 +From: Jitendra Lanka +Date: Wed, 22 Mar 2023 11:39:56 -0400 +Subject: [PATCH] UBUNTU: SAUCE: mlxbf-ptm: add atx debugfs nodes +X-NVConfidentiality: public + +BugLink: https://bugs.launchpad.net/bugs/2011738 + +Add additional debugfs nodes that provide ATX status and +power profile data. + +Signed-off-by: Jitendra Lanka +Acked-by: Tim Gardner +Acked-by: Bartlomiej Zolnierkiewicz +Signed-off-by: Bartlomiej Zolnierkiewicz +--- + drivers/platform/mellanox/mlxbf-ptm.c | 36 +++++++++++++++++++++++++++++++++++ + 1 file changed, 36 insertions(+) + +diff --git a/drivers/platform/mellanox/mlxbf-ptm.c b/drivers/platform/mellanox/mlxbf-ptm.c +index aeb68dc42..a2845aa57 100644 +--- a/drivers/platform/mellanox/mlxbf-ptm.c ++++ b/drivers/platform/mellanox/mlxbf-ptm.c +@@ -23,6 +23,9 @@ + #define MLNX_PTM_GET_MAX_TEMP 0x82000108 + #define MLNX_PTM_GET_PWR_EVT_CNT 0x82000109 + #define MLNX_PTM_GET_TEMP_EVT_CNT 0x8200010A ++#define MLNX_PTM_GET_POWER_ENVELOPE 0x8200010B ++#define MLNX_PTM_GET_ATX_PWR_STATE 0x8200010C ++#define MLNX_PTM_GET_CUR_PPROFILE 0x8200010D + + #define MLNX_POWER_ERROR 300 + +@@ -142,6 +145,33 @@ static int error_status_show(void *data, u64 *val) + DEFINE_SIMPLE_ATTRIBUTE(error_status_fops, + error_status_show, NULL, "%llu\n"); + ++static int power_envelope_show(void *data, u64 *val) ++{ ++ *val = smc_call0(MLNX_PTM_GET_POWER_ENVELOPE); ++ ++ return 0; ++} ++DEFINE_SIMPLE_ATTRIBUTE(power_envelope_fops, ++ power_envelope_show, NULL, "%llu\n"); ++ ++static int atx_status_show(void *data, u64 *val) ++{ ++ *val = smc_call0(MLNX_PTM_GET_ATX_PWR_STATE); ++ ++ return 0; ++} ++DEFINE_SIMPLE_ATTRIBUTE(atx_status_fops, ++ atx_status_show, NULL, "%lld\n"); ++ ++static int current_pprofile_show(void *data, u64 *val) ++{ ++ *val = smc_call0(MLNX_PTM_GET_CUR_PPROFILE); ++ ++ return 0; ++} ++DEFINE_SIMPLE_ATTRIBUTE(current_pprofile_fops, ++ current_pprofile_show, NULL, "%llu\n"); ++ + + static int __init mlxbf_ptm_init(void) + { +@@ -176,6 +206,12 @@ static int __init mlxbf_ptm_init(void) + NULL, &tthrottling_state_fops); + debugfs_create_file("error_state", 0444, status, + NULL, &error_status_fops); ++ debugfs_create_file("power_envelope", 0444, status, ++ NULL, &power_envelope_fops); ++ debugfs_create_file("atx_power_available", 0444, status, ++ NULL, &atx_status_fops); ++ debugfs_create_file("active_power_profile", 0444, status, ++ NULL, ¤t_pprofile_fops); + + return 0; + } +-- +2.14.1 + diff --git a/platform/mellanox/non-upstream-patches/patches/0300-UBUNTU-SAUCE-mlxbf-ptm-update-module-version.patch b/platform/mellanox/non-upstream-patches/patches/0300-UBUNTU-SAUCE-mlxbf-ptm-update-module-version.patch new file mode 100644 index 000000000000..1ff594df611d --- /dev/null +++ b/platform/mellanox/non-upstream-patches/patches/0300-UBUNTU-SAUCE-mlxbf-ptm-update-module-version.patch @@ -0,0 +1,31 @@ +From 83e12ab298ef4c328ae0b410412abc9c5bf40678 Mon Sep 17 00:00:00 2001 +From: Jitendra Lanka +Date: Wed, 22 Mar 2023 11:39:57 -0400 +Subject: [PATCH] UBUNTU: SAUCE: mlxbf-ptm: update module version +X-NVConfidentiality: public + +BugLink: https://bugs.launchpad.net/bugs/2011738 + +update module version + +Signed-off-by: Jitendra Lanka +Acked-by: Tim Gardner +Acked-by: Bartlomiej Zolnierkiewicz +Signed-off-by: Bartlomiej Zolnierkiewicz +--- + drivers/platform/mellanox/mlxbf-ptm.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/platform/mellanox/mlxbf-ptm.c b/drivers/platform/mellanox/mlxbf-ptm.c +index a2845aa57..eb4460cb0 100644 +--- a/drivers/platform/mellanox/mlxbf-ptm.c ++++ b/drivers/platform/mellanox/mlxbf-ptm.c +@@ -227,4 +227,4 @@ module_exit(mlxbf_ptm_exit); + MODULE_AUTHOR("Jitendra Lanka "); + MODULE_DESCRIPTION("Nvidia Bluefield power and thermal debugfs driver"); + MODULE_LICENSE("Dual BSD/GPL"); +-MODULE_VERSION("1.0"); ++MODULE_VERSION("1.1"); +-- +2.14.1 + diff --git a/platform/mellanox/non-upstream-patches/patches/0301-UBUNTU-SAUCE-mlxbf-gige-Fix-kernel-panic-at-shutdown.patch b/platform/mellanox/non-upstream-patches/patches/0301-UBUNTU-SAUCE-mlxbf-gige-Fix-kernel-panic-at-shutdown.patch new file mode 100644 index 000000000000..3f98aa9e723a --- /dev/null +++ b/platform/mellanox/non-upstream-patches/patches/0301-UBUNTU-SAUCE-mlxbf-gige-Fix-kernel-panic-at-shutdown.patch @@ -0,0 +1,48 @@ +From 4da66721a3e397268fd5070080d44399101ef9e9 Mon Sep 17 00:00:00 2001 +From: Asmaa Mnebhi +Date: Fri, 2 Jun 2023 13:04:25 -0400 +Subject: [PATCH] UBUNTU: SAUCE: mlxbf-gige: Fix kernel panic at shutdown +X-NVConfidentiality: public + +BugLink: https://bugs.launchpad.net/bugs/2022370 + +We occasionally see a race condition (once every 350 reboots) where napi is still +running (mlxbf_gige_poll) while a shutdown has been initiated through "reboot". +Since mlxbf_gige_poll is still running, it tries to access a NULL pointer and as +a result causes a kernel panic. + +The fix is to explicitly disable napi and dequeue it during shutdown. +mlxbf_gige_remove already calls: +unregister_netdev->unregister_netdevice->unregister_netdev_queue-> +rollback_registered->rollback_registered_many->dev_close_many-> +__dev_close_many->ndo_stop->mlxbf_gige_stop which stops napi + +So use mlxbf_gige_remove in place of the existing shutdown logic. + +Signed-off-by: Asmaa Mnebhi +Acked-by: Bartlomiej Zolnierkiewicz +Acked-by: Tim Gardner +Signed-off-by: Bartlomiej Zolnierkiewicz +--- + drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c | 5 +---- + 1 file changed, 1 insertion(+), 4 deletions(-) + +diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c +index 602260f2b..b7c1a10c4 100644 +--- a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c ++++ b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c +@@ -500,10 +500,7 @@ static int mlxbf_gige_remove(struct platform_device *pdev) + + static void mlxbf_gige_shutdown(struct platform_device *pdev) + { +- struct mlxbf_gige *priv = platform_get_drvdata(pdev); +- +- writeq(0, priv->base + MLXBF_GIGE_INT_EN); +- mlxbf_gige_clean_port(priv); ++ mlxbf_gige_remove(pdev); + } + + static const struct acpi_device_id __maybe_unused mlxbf_gige_acpi_match[] = { +-- +2.14.1 + diff --git a/platform/mellanox/non-upstream-patches/patches/0302-UBUNTU-SAUCE-mlxbf-bootctl-support-SMC-call-for-sett.patch b/platform/mellanox/non-upstream-patches/patches/0302-UBUNTU-SAUCE-mlxbf-bootctl-support-SMC-call-for-sett.patch new file mode 100644 index 000000000000..e2aae0c0d4f2 --- /dev/null +++ b/platform/mellanox/non-upstream-patches/patches/0302-UBUNTU-SAUCE-mlxbf-bootctl-support-SMC-call-for-sett.patch @@ -0,0 +1,94 @@ +From 76ed90858f09e7be6601053d0654872ab0018379 Mon Sep 17 00:00:00 2001 +From: Asmaa Mnebhi +Date: Thu, 30 Mar 2023 14:42:33 -0400 +Subject: [PATCH] UBUNTU: SAUCE: mlxbf-bootctl: support SMC call for setting + ARM boot state +X-NVConfidentiality: public + +BugLink: https://bugs.launchpad.net/bugs/2013383 + +Add a new SMC call which allows setting the ARM boot progress state to "OS is up". + +Signed-off-by: Asmaa Mnebhi +Acked-by: Tim Gardner +Acked-by: Bartlomiej Zolnierkiewicz +Signed-off-by: Bartlomiej Zolnierkiewicz +--- + drivers/platform/mellanox/mlxbf-bootctl.c | 23 +++++++++++++++++++++++ + drivers/platform/mellanox/mlxbf-bootctl.h | 5 +++++ + 2 files changed, 28 insertions(+) + +diff --git a/drivers/platform/mellanox/mlxbf-bootctl.c b/drivers/platform/mellanox/mlxbf-bootctl.c +index e8877a19d..a68bf5b27 100644 +--- a/drivers/platform/mellanox/mlxbf-bootctl.c ++++ b/drivers/platform/mellanox/mlxbf-bootctl.c +@@ -105,6 +105,7 @@ enum { + /* This mutex is used to serialize MFG write and lock operations. */ + static DEFINE_MUTEX(mfg_ops_lock); + static DEFINE_MUTEX(icm_ops_lock); ++static DEFINE_MUTEX(os_up_lock); + + #define MLNX_MFG_OOB_MAC_LEN ETH_ALEN + #define MLNX_MFG_OPN_VAL_LEN 24 +@@ -747,6 +748,26 @@ static ssize_t mfg_lock_store(struct device_driver *drv, const char *buf, + return count; + } + ++static ssize_t os_up_store(struct device_driver *drv, const char *buf, ++ size_t count) ++{ ++ unsigned long val; ++ int err; ++ ++ err = kstrtoul(buf, 10, &val); ++ if (err) ++ return err; ++ ++ if (val != 1) ++ return -EINVAL; ++ ++ mutex_lock(&os_up_lock); ++ smc_call0(MLNX_HANDLE_OS_UP); ++ mutex_unlock(&os_up_lock); ++ ++ return count; ++} ++ + /* Log header format. */ + #define RSH_LOG_TYPE_SHIFT 56 + #define RSH_LOG_LEN_SHIFT 48 +@@ -1209,6 +1230,7 @@ static DRIVER_ATTR_RW(rev); + static DRIVER_ATTR_WO(mfg_lock); + static DRIVER_ATTR_RW(rsh_log); + static DRIVER_ATTR_RW(large_icm); ++static DRIVER_ATTR_WO(os_up); + + static struct attribute *mbc_dev_attrs[] = { + &driver_attr_post_reset_wdog.attr, +@@ -1227,6 +1249,7 @@ static struct attribute *mbc_dev_attrs[] = { + &driver_attr_mfg_lock.attr, + &driver_attr_rsh_log.attr, + &driver_attr_large_icm.attr, ++ &driver_attr_os_up.attr, + NULL + }; + +diff --git a/drivers/platform/mellanox/mlxbf-bootctl.h b/drivers/platform/mellanox/mlxbf-bootctl.h +index c70204770..dc73f7e88 100644 +--- a/drivers/platform/mellanox/mlxbf-bootctl.h ++++ b/drivers/platform/mellanox/mlxbf-bootctl.h +@@ -102,6 +102,11 @@ + #define MLNX_HANDLE_SET_ICM_INFO 0x82000012 + #define MLNX_HANDLE_GET_ICM_INFO 0x82000013 + ++/* ++ * SMC function ID to set the ARM boot state to up ++ */ ++#define MLNX_HANDLE_OS_UP 0x82000014 ++ + #define MAX_ICM_BUFFER_SIZE 10 + + /* SMC function IDs for SiP Service queries */ +-- +2.14.1 + diff --git a/platform/mellanox/non-upstream-patches/patches/0303-UBUNTU-SAUCE-Add-BF3-related-ACPI-config-and-Ring-de.patch b/platform/mellanox/non-upstream-patches/patches/0303-UBUNTU-SAUCE-Add-BF3-related-ACPI-config-and-Ring-de.patch new file mode 100644 index 000000000000..d73e70262a2a --- /dev/null +++ b/platform/mellanox/non-upstream-patches/patches/0303-UBUNTU-SAUCE-Add-BF3-related-ACPI-config-and-Ring-de.patch @@ -0,0 +1,135 @@ +From 8660928fa01c363f1aa826d392de2c6ef4924dcf Mon Sep 17 00:00:00 2001 +From: Shih-Yi Chen +Date: Wed, 5 Apr 2023 14:41:27 -0400 +Subject: [PATCH] UBUNTU: SAUCE: Add BF3 related ACPI config and Ring device + creation code +X-NVConfidentiality: public + +BugLink: https://bugs.launchpad.net/bugs/2015292 + +Fixed Missing ACPI device info in mlxbf_pka module. Added configuration info +and associated code to provision PKA ring devices. + +Signed-off-by: Shih-Yi Chen +Reviewed-by: Khalil Blaiech +Acked-by: Bartlomiej Zolnierkiewicz +Acked-by: Andrei Gherzan +Signed-off-by: Bartlomiej Zolnierkiewicz +--- + .../platform/mellanox/mlxbf_pka/mlxbf_pka_config.h | 9 ++++++--- + .../platform/mellanox/mlxbf_pka/mlxbf_pka_drv.c | 23 +++++++++++++++++++--- + 2 files changed, 26 insertions(+), 6 deletions(-) + +diff --git a/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_config.h b/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_config.h +index 5b69d55be..c9543416b 100644 +--- a/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_config.h ++++ b/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_config.h +@@ -37,7 +37,7 @@ + #include "mlxbf_pka_addrs.h" + + // The maximum number of PKA shims refered to as IO blocks. +-#define PKA_MAX_NUM_IO_BLOCKS 8 ++#define PKA_MAX_NUM_IO_BLOCKS 24 + // The maximum number of Rings supported by IO block (shim). + #define PKA_MAX_NUM_IO_BLOCK_RINGS 4 + +@@ -72,8 +72,11 @@ + #define PKA_WINDOW_RAM_RING_MEM_SIZE 0x0800 // 2KB + #define PKA_WINDOW_RAM_DATA_MEM_SIZE 0x3800 // 14KB + +-// Offset mask, common to both Window and Alternate Window RAM. +-#define PKA_WINDOW_RAM_OFFSET_MASK1 0x730000 ++// Window RAM/Alternate Window RAM offset mask for BF1 and BF2 ++#define PKA_WINDOW_RAM_OFFSET_MASK1 0x730000 ++// ++// Window RAM/Alternate Window RAM offset mask for BF3 ++#define PKA_WINDOW_RAM_OFFSET_MASK2 0x70000 + + // Macro for mapping PKA Ring address into Window RAM address. It converts the + // ring address, either physical address or virtual address, to valid address +diff --git a/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_drv.c b/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_drv.c +index 9e26ccf21..6b171b2a6 100644 +--- a/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_drv.c ++++ b/drivers/platform/mellanox/mlxbf_pka/mlxbf_pka_drv.c +@@ -34,6 +34,9 @@ + #define PKA_DEVICE_ACPIHID_BF2 "MLNXBF20" + #define PKA_RING_DEVICE_ACPIHID_BF2 "MLNXBF21" + ++#define PKA_DEVICE_ACPIHID_BF3 "MLNXBF51" ++#define PKA_RING_DEVICE_ACPIHID_BF3 "MLNXBF52" ++ + #define PKA_DEVICE_ACCESS_MODE 0666 + + #define PKA_DEVICE_RES_CNT 7 +@@ -49,7 +52,8 @@ enum pka_mem_res_idx { + + enum pka_plat_type { + PKA_PLAT_TYPE_BF1 = 0, /* Platform type Bluefield-1 */ +- PKA_PLAT_TYPE_BF2 /* Platform type Bluefield-2 */ ++ PKA_PLAT_TYPE_BF2, /* Platform type Bluefield-2 */ ++ PKA_PLAT_TYPE_BF3 /* Platform type Bluefield-3 */ + }; + + static DEFINE_MUTEX(pka_drv_lock); +@@ -66,6 +70,9 @@ const char pka_ring_acpihid_bf1[] = PKA_RING_DEVICE_ACPIHID_BF1; + const char pka_acpihid_bf2[] = PKA_DEVICE_ACPIHID_BF2; + const char pka_ring_acpihid_bf2[] = PKA_RING_DEVICE_ACPIHID_BF2; + ++const char pka_acpihid_bf3[] = PKA_DEVICE_ACPIHID_BF3; ++const char pka_ring_acpihid_bf3[] = PKA_RING_DEVICE_ACPIHID_BF3; ++ + struct pka_drv_plat_info { + enum pka_plat_type type; + uint8_t fw_id; +@@ -79,6 +86,10 @@ static struct pka_drv_plat_info pka_drv_plat[] = { + [PKA_PLAT_TYPE_BF2] = { + .type = PKA_PLAT_TYPE_BF2, + .fw_id = PKA_FIRMWARE_IMAGE_2_ID ++ }, ++ [PKA_PLAT_TYPE_BF3] = { ++ .type = PKA_PLAT_TYPE_BF3, ++ .fw_id = PKA_FIRMWARE_IMAGE_2_ID + } + }; + +@@ -87,6 +98,8 @@ static const struct acpi_device_id pka_drv_acpi_ids[] = { + { PKA_RING_DEVICE_ACPIHID_BF1, 0 }, + { PKA_DEVICE_ACPIHID_BF2, (kernel_ulong_t)&pka_drv_plat[PKA_PLAT_TYPE_BF2] }, + { PKA_RING_DEVICE_ACPIHID_BF2, 0 }, ++ { PKA_DEVICE_ACPIHID_BF3, (kernel_ulong_t)&pka_drv_plat[PKA_PLAT_TYPE_BF3] }, ++ { PKA_RING_DEVICE_ACPIHID_BF3, 0 }, + {}, + }; + +@@ -967,6 +980,8 @@ static int pka_drv_probe_device(struct pka_info *info) + plat_info = (struct pka_drv_plat_info *)aid->driver_data; + if (plat_info->type <= PKA_PLAT_TYPE_BF2) { + wndw_ram_off_mask = PKA_WINDOW_RAM_OFFSET_MASK1; ++ } else if (plat_info->type <= PKA_PLAT_TYPE_BF3) { ++ wndw_ram_off_mask = PKA_WINDOW_RAM_OFFSET_MASK2; + } else { + PKA_ERROR(PKA_DRIVER, "Invalid platform type: %d\n", + (int)plat_info->type); +@@ -1210,7 +1225,8 @@ static int pka_drv_acpi_probe(struct platform_device *pdev, + return -EINVAL; + + if (!strcmp(info->acpihid, pka_ring_acpihid_bf1) +- || !strcmp(info->acpihid, pka_ring_acpihid_bf2)) { ++ || !strcmp(info->acpihid, pka_ring_acpihid_bf2) ++ || !strcmp(info->acpihid, pka_ring_acpihid_bf3)) { + error = pka_drv_probe_ring_device(info); + if (error) { + PKA_DEBUG(PKA_DRIVER, +@@ -1222,7 +1238,8 @@ static int pka_drv_acpi_probe(struct platform_device *pdev, + pdev->name); + + } else if (!strcmp(info->acpihid, pka_acpihid_bf1) +- || !strcmp(info->acpihid, pka_acpihid_bf2)) { ++ || !strcmp(info->acpihid, pka_acpihid_bf2) ++ || !strcmp(info->acpihid, pka_acpihid_bf3)) { + error = pka_drv_probe_device(info); + if (error) { + PKA_DEBUG(PKA_DRIVER, +-- +2.14.1 + diff --git a/platform/mellanox/non-upstream-patches/patches/0306-dt-bindings-trivial-devices-Add-infineon-xdpe1a2g7.patch b/platform/mellanox/non-upstream-patches/patches/0306-dt-bindings-trivial-devices-Add-infineon-xdpe1a2g7.patch new file mode 100644 index 000000000000..509520e0997f --- /dev/null +++ b/platform/mellanox/non-upstream-patches/patches/0306-dt-bindings-trivial-devices-Add-infineon-xdpe1a2g7.patch @@ -0,0 +1,29 @@ +From 752f09e963ed92cf6ba69930a26dc4cba674bdd3 Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Mon, 17 Jul 2023 16:24:58 +0000 +Subject: [PATCH hwmon-next 2/2] dt-bindings: trivial-devices: Add + infineon,xdpe1a2g7 + +Add new Infineon Multi-phase Digital VR Controller xdpe1a2g7 + +Signed-off-by: Vadim Pasternak +--- + Documentation/devicetree/bindings/trivial-devices.yaml | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml +index adec3a0f6..aa1fa8414 100644 +--- a/Documentation/devicetree/bindings/trivial-devices.yaml ++++ b/Documentation/devicetree/bindings/trivial-devices.yaml +@@ -98,6 +98,8 @@ properties: + - infineon,slb9645tt + # Infineon TLV493D-A1B6 I2C 3D Magnetic Sensor + - infineon,tlv493d-a1b6 ++ # Infineon Multi-phase Digital VR Controller xdpe1a2g7 ++ - infineon,xdpe1a2g7 + # Infineon Multi-phase Digital VR Controller xdpe12254 + - infineon,xdpe12254 + # Infineon Multi-phase Digital VR Controller xdpe12284 +-- +2.20.1 + diff --git a/platform/mellanox/non-upstream-patches/patches/0307-leds-mlxreg-Add-support-for-new-flavour-of-capabilit.patch b/platform/mellanox/non-upstream-patches/patches/0307-leds-mlxreg-Add-support-for-new-flavour-of-capabilit.patch new file mode 100644 index 000000000000..5ef9bf48369d --- /dev/null +++ b/platform/mellanox/non-upstream-patches/patches/0307-leds-mlxreg-Add-support-for-new-flavour-of-capabilit.patch @@ -0,0 +1,53 @@ +From 6f745b2a6cfd48e1e5ab0276665ac1583df263d2 Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Thu, 20 Jul 2023 11:01:56 +0000 +Subject: [PATCH] leds: mlxreg: Add support for new flavour of capability + register +X-NVConfidentiality: public + +LED platform data is common across the various systems, while LED +driver should be able to apply only the LED instances relevant +to specific system. + +For example, platform data might contain descriptions for fan1, +fan2, ..., fan{n} LEDs, while some systems equipped with all 'n' fan +LEDs, others with less. + +For detection of the real number of equipped LEDs special capability +register is used. +This register used to indicate presence of LED through the bitmap. + +For some new big modular systems this register will provide presence +data by counter. + +Use slot parameter to distinct whether capability register contains +bitmask or counter. + +Signed-off-by: Vadim Pasternak +--- + drivers/leds/leds-mlxreg.c | 9 ++++++++- + 1 file changed, 8 insertions(+), 1 deletion(-) + +diff --git a/drivers/leds/leds-mlxreg.c b/drivers/leds/leds-mlxreg.c +index 6241a3407..e6b205d31 100644 +--- a/drivers/leds/leds-mlxreg.c ++++ b/drivers/leds/leds-mlxreg.c +@@ -243,7 +243,14 @@ static int mlxreg_led_config(struct mlxreg_led_priv_data *priv) + dev_err(&priv->pdev->dev, "Failed to query capability register\n"); + return err; + } +- if (!(regval & data->bit)) ++ /* ++ * If slot is specified - validate if slot is equipped on system. ++ * In case slot is specified in platform data, capability register ++ * contains the counter of untits. ++ */ ++ if (data->slot && data->slot > regval) ++ continue; ++ else if (!(regval & data->bit) && !data->slot) + continue; + /* + * Field "bit" can contain one capability bit in 0 byte +-- +2.14.1 + diff --git a/platform/mellanox/non-upstream-patches/patches/0308-leds-mlxreg-Remove-code-for-amber-LED-colour.patch b/platform/mellanox/non-upstream-patches/patches/0308-leds-mlxreg-Remove-code-for-amber-LED-colour.patch new file mode 100644 index 000000000000..690c44b07349 --- /dev/null +++ b/platform/mellanox/non-upstream-patches/patches/0308-leds-mlxreg-Remove-code-for-amber-LED-colour.patch @@ -0,0 +1,50 @@ +From 76dc17f264b5d1530f110187220923dc8f7db0a4 Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Sun, 23 Jul 2023 10:07:15 +0000 +Subject: [PATCH backport 5.10.179 2/2] leds: mlxreg: Remove code for amber LED + colour + +Remove unused code for amber LED colour. + +In case system LED color is "green", "orange" or "amber" same code is +to be used for colour setting. + +Signed-off-by: Vadim Pasternak +--- + drivers/leds/leds-mlxreg.c | 10 ++-------- + 1 file changed, 2 insertions(+), 8 deletions(-) + +diff --git a/drivers/leds/leds-mlxreg.c b/drivers/leds/leds-mlxreg.c +index e6b205d31..26039e187 100644 +--- a/drivers/leds/leds-mlxreg.c ++++ b/drivers/leds/leds-mlxreg.c +@@ -22,7 +22,6 @@ + #define MLXREG_LED_RED_SOLID 0x05 /* Solid red or orange */ + #define MLXREG_LED_GREEN_SOLID_HW 0x09 /* Solid green by hardware */ + #define MLXREG_LED_GREEN_SOLID 0x0D /* Solid green */ +-#define MLXREG_LED_AMBER_SOLID 0x09 /* Solid amber */ + #define MLXREG_LED_BLINK_3HZ 167 /* ~167 msec off/on - HW support */ + #define MLXREG_LED_BLINK_6HZ 83 /* ~83 msec off/on - HW support */ + #define MLXREG_LED_CAPABILITY_CLEAR GENMASK(31, 8) /* Clear mask */ +@@ -262,16 +261,11 @@ static int mlxreg_led_config(struct mlxreg_led_priv_data *priv) + + led_cdev = &led_data->led_cdev; + led_data->data_parent = priv; +- if (strstr(data->label, "red")) { +- brightness = LED_OFF; +- led_data->base_color = MLXREG_LED_RED_SOLID; +- } else if (strstr(data->label, "orange")) { ++ if (strstr(data->label, "red") || strstr(data->label, "orange") || ++ strstr(data->label, "amber")) { + brightness = LED_OFF; + led_data->base_color = MLXREG_LED_RED_SOLID; + led_data->base_color_hw = MLXREG_LED_RED_SOLID_HW; +- } else if (strstr(data->label, "amber")) { +- brightness = LED_OFF; +- led_data->base_color = MLXREG_LED_AMBER_SOLID; + } else { + brightness = LED_OFF; + led_data->base_color = MLXREG_LED_GREEN_SOLID; +-- +2.20.1 + diff --git a/platform/mellanox/non-upstream-patches/patches/0308-platform_data-mlxreg-Add-capability-bit-and-mask-fie.patch b/platform/mellanox/non-upstream-patches/patches/0308-platform_data-mlxreg-Add-capability-bit-and-mask-fie.patch new file mode 100644 index 000000000000..dee10dc70a37 --- /dev/null +++ b/platform/mellanox/non-upstream-patches/patches/0308-platform_data-mlxreg-Add-capability-bit-and-mask-fie.patch @@ -0,0 +1,60 @@ +From 3abc15462d81d65a70734cebbca3f0a4f35a7328 Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Thu, 24 Aug 2023 13:20:54 +0000 +Subject: [PATCH] platform_data/mlxreg: Add capability bit and mask fields +X-NVConfidentiality: public + +Some 'capability' registers can be shared between different resources. +Add new fields 'capability_bit' and 'capability_mask' to structs +'mlxreg_core_data' and and 'mlxreg_core_item' for getting only relevant +capability bits. + +Signed-off-by: Vadim Pasternak +Reviewed-by: Felix Radensky +--- + include/linux/platform_data/mlxreg.h | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/include/linux/platform_data/mlxreg.h b/include/linux/platform_data/mlxreg.h +index 0b9f81a6f..d9f679752 100644 +--- a/include/linux/platform_data/mlxreg.h ++++ b/include/linux/platform_data/mlxreg.h +@@ -118,6 +118,8 @@ struct mlxreg_hotplug_device { + * @mask: attribute access mask; + * @bit: attribute effective bit; + * @capability: attribute capability register; ++ * @capability_bit: started bit in attribute capability register; ++ * @capability_mask: mask in attribute capability register; + * @reg_prsnt: attribute presence register; + * @reg_sync: attribute synch register; + * @reg_pwr: attribute power register; +@@ -138,6 +140,8 @@ struct mlxreg_core_data { + u32 mask; + u32 bit; + u32 capability; ++ u32 capability_bit; ++ u32 capability_mask; + u32 reg_prsnt; + u32 reg_sync; + u32 reg_pwr; +@@ -162,6 +166,8 @@ struct mlxreg_core_data { + * @reg: group interrupt status register; + * @mask: group interrupt mask; + * @capability: group capability register; ++ * @capability_bit: started bit in attribute capability register; ++ * @capability_mask: mask in attribute capability register; + * @cache: last status value for elements fro the same group; + * @count: number of available elements in the group; + * @ind: element's index inside the group; +@@ -175,6 +181,8 @@ struct mlxreg_core_item { + u32 reg; + u32 mask; + u32 capability; ++ u32 capability_bit; ++ u32 capability_mask; + u32 cache; + u8 count; + u8 ind; +-- +2.14.1 + diff --git a/platform/mellanox/non-upstream-patches/patches/0309-hwmon-mlxreg-fan-Add-support-for-new-flavour-of-capa.patch b/platform/mellanox/non-upstream-patches/patches/0309-hwmon-mlxreg-fan-Add-support-for-new-flavour-of-capa.patch new file mode 100644 index 000000000000..acf9c1730cda --- /dev/null +++ b/platform/mellanox/non-upstream-patches/patches/0309-hwmon-mlxreg-fan-Add-support-for-new-flavour-of-capa.patch @@ -0,0 +1,101 @@ +From 582264258aa3e95f87e33221ff9026899e02d529 Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Sun, 23 Jul 2023 06:26:09 +0000 +Subject: [PATCH] hwmon: (mlxreg-fan) Add support for new flavour of capability + register +X-NVConfidentiality: public + +FAN platform data is common across the various systems, while fan +driver should be able to apply only the fan instances relevant +to specific system. + +For example, platform data might contain descriptions for fan1, +fan2, ..., fan{n}, while some systems equipped with all 'n' fans, +others with less. +Also, on some systems fan drawer can be equipped with several +tachometers and on others only with one. + +For detection of the real number of equipped drawers and tachometers +special capability registers are used. +These registers used to indicate presence of drawers and tachometers +through the bitmap. + +For some new big modular systems this register will provide presence +data by counter. + +Use slot parameter to distinct whether capability register contains +bitmask or counter. + +Signed-off-by: Vadim Pasternak +--- + drivers/hwmon/mlxreg-fan.c | 19 ++++++++++++++++--- + 1 file changed, 16 insertions(+), 3 deletions(-) + +diff --git a/drivers/hwmon/mlxreg-fan.c b/drivers/hwmon/mlxreg-fan.c +index acba9d688..c0b42821f 100644 +--- a/drivers/hwmon/mlxreg-fan.c ++++ b/drivers/hwmon/mlxreg-fan.c +@@ -72,12 +72,14 @@ struct mlxreg_fan; + * @reg: register offset; + * @mask: fault mask; + * @prsnt: present register offset; ++ * @shift: tacho presence bit shift; + */ + struct mlxreg_fan_tacho { + bool connected; + u32 reg; + u32 mask; + u32 prsnt; ++ u32 shift; + }; + + /* +@@ -146,8 +148,10 @@ mlxreg_fan_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, + /* + * Map channel to presence bit - drawer can be equipped with + * one or few FANs, while presence is indicated per drawer. ++ * Shift channel value if necessary to align with register value. + */ +- if (BIT(channel / fan->tachos_per_drwr) & regval) { ++ if (BIT(rol32(channel, tacho->shift) / fan->tachos_per_drwr) & ++ regval) { + /* FAN is not connected - return zero for FAN speed. */ + *val = 0; + return 0; +@@ -411,7 +415,7 @@ static int mlxreg_fan_connect_verify(struct mlxreg_fan *fan, + return err; + } + +- return !!(regval & data->bit); ++ return data->slot ? (data->slot <= regval ? 1 : 0) : !!(regval & data->bit); + } + + static int mlxreg_pwm_connect_verify(struct mlxreg_fan *fan, +@@ -486,6 +490,7 @@ static int mlxreg_fan_config(struct mlxreg_fan *fan, + fan->tacho[tacho_num].reg = data->reg; + fan->tacho[tacho_num].mask = data->mask; + fan->tacho[tacho_num].prsnt = data->reg_prsnt; ++ fan->tacho[tacho_num].shift = data->capability_bit; + fan->tacho[tacho_num++].connected = true; + tacho_avail++; + } else if (strnstr(data->label, "pwm", sizeof(data->label))) { +@@ -548,7 +553,15 @@ static int mlxreg_fan_config(struct mlxreg_fan *fan, + return err; + } + +- drwr_avail = hweight32(regval); ++ /* ++ * The number of drawers could be specified in registers by counters for newer ++ * systems, or by bitmasks for older systems. In case the data is provided by ++ * counter, it is indicated through 'version' field. ++ */ ++ if (pdata->version) ++ drwr_avail = regval; ++ else ++ drwr_avail = hweight32(regval); + if (!tacho_avail || !drwr_avail || tacho_avail < drwr_avail) { + dev_err(fan->dev, "Configuration is invalid: drawers num %d tachos num %d\n", + drwr_avail, tacho_avail); +-- +2.14.1 + diff --git a/platform/mellanox/non-upstream-patches/patches/0310-hwmon-mlxreg-fan-Extend-number-of-supporetd-fans.patch b/platform/mellanox/non-upstream-patches/patches/0310-hwmon-mlxreg-fan-Extend-number-of-supporetd-fans.patch new file mode 100644 index 000000000000..b46961465f48 --- /dev/null +++ b/platform/mellanox/non-upstream-patches/patches/0310-hwmon-mlxreg-fan-Extend-number-of-supporetd-fans.patch @@ -0,0 +1,47 @@ +From bfd3600fe51e7f2fe5f5777936b308c18220b85c Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Sun, 23 Jul 2023 06:49:01 +0000 +Subject: [PATCH] hwmon: (mlxreg-fan) Extend number of supporetd fans +X-NVConfidentiality: public + +Some new big modular systems can be equipped with up to 24 fans. +Extend maximum number of fans accordingly. + +Signed-off-by: Vadim Pasternak +--- + drivers/hwmon/mlxreg-fan.c | 12 +++++++++++- + 1 file changed, 11 insertions(+), 1 deletion(-) + +diff --git a/drivers/hwmon/mlxreg-fan.c b/drivers/hwmon/mlxreg-fan.c +index c0b42821f..298af1d9b 100644 +--- a/drivers/hwmon/mlxreg-fan.c ++++ b/drivers/hwmon/mlxreg-fan.c +@@ -12,7 +12,7 @@ + #include + #include + +-#define MLXREG_FAN_MAX_TACHO 14 ++#define MLXREG_FAN_MAX_TACHO 24 + #define MLXREG_FAN_MAX_PWM 4 + #define MLXREG_FAN_PWM_NOT_CONNECTED 0xff + #define MLXREG_FAN_MAX_STATE 10 +@@ -276,6 +276,16 @@ static char *mlxreg_fan_name[] = { + + static const struct hwmon_channel_info *mlxreg_fan_hwmon_info[] = { + HWMON_CHANNEL_INFO(fan, ++ HWMON_F_INPUT | HWMON_F_FAULT, ++ HWMON_F_INPUT | HWMON_F_FAULT, ++ HWMON_F_INPUT | HWMON_F_FAULT, ++ HWMON_F_INPUT | HWMON_F_FAULT, ++ HWMON_F_INPUT | HWMON_F_FAULT, ++ HWMON_F_INPUT | HWMON_F_FAULT, ++ HWMON_F_INPUT | HWMON_F_FAULT, ++ HWMON_F_INPUT | HWMON_F_FAULT, ++ HWMON_F_INPUT | HWMON_F_FAULT, ++ HWMON_F_INPUT | HWMON_F_FAULT, + HWMON_F_INPUT | HWMON_F_FAULT, + HWMON_F_INPUT | HWMON_F_FAULT, + HWMON_F_INPUT | HWMON_F_FAULT, +-- +2.14.1 + diff --git a/platform/mellanox/non-upstream-patches/patches/0317-platform-mellanox-Introduce-support-for-switches-equ.patch b/platform/mellanox/non-upstream-patches/patches/0317-platform-mellanox-Introduce-support-for-switches-equ.patch new file mode 100644 index 000000000000..dec533c3a272 --- /dev/null +++ b/platform/mellanox/non-upstream-patches/patches/0317-platform-mellanox-Introduce-support-for-switches-equ.patch @@ -0,0 +1,312 @@ +From 6e7badaa478c42acfaef111d799f56ace64783fd Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Mon, 24 Jul 2023 11:10:50 +0000 +Subject: [PATCH backport 5.10.179 25/26] platform: mellanox: Introduce support + for switches equipped with new FPGA device + +Add support for Nvidia MQM97xx and MSN47xx family switches equipped with +new FPGA device. + +These switches are based on previous generation of MQM97xx and MSN47xx +switches, but COMe module uses new FPGA device. + +Platform configuration for new switches is based on the new VMOD0016 +class. Configuration is extended to support new register map with +callbacks supporting indirect addressing for PCIe-to-LPC bridge. +This bridge provides interface between FPGA at COMe board (directly +connected to CPU PCIe root complex) to CPLDs on switch board (which +cannot be connected directly to PCIe root complex). + +Signed-off-by: Vadim Pasternak +Reviewed-by: Michael Shych +--- + drivers/platform/x86/mlx-platform.c | 196 ++++++++++++++++++++++++++++ + 1 file changed, 196 insertions(+) + +diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/x86/mlx-platform.c +index c4a4afff7..e303b8e5a 100644 +--- a/drivers/platform/x86/mlx-platform.c ++++ b/drivers/platform/x86/mlx-platform.c +@@ -184,6 +184,9 @@ + #define MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET 0xfb + #define MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET 0xfc + #define MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET 0xfd ++#define MLXPLAT_CPLD_LPC_REG_EXT_MIN_OFFSET 0x100 ++#define MLXPLAT_CPLD_LPC_REG_EXT_MID_OFFSET 0x195 ++#define MLXPLAT_CPLD_LPC_REG_EXT_MAX_OFFSET 0x1ff + #define MLXPLAT_CPLD_LPC_IO_RANGE 0x100 + + #define MLXPLAT_CPLD_LPC_PIO_OFFSET 0x10000UL +@@ -278,6 +281,7 @@ + /* Maximum number of possible physical buses equipped on system */ + #define MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM 16 + #define MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM 24 ++#define MLXPLAT_CPLD_DEFAULT_MUX_HOTPLUG_VECTOR 0 + + /* Number of channels in group */ + #define MLXPLAT_CPLD_GRP_CHNL_NUM 8 +@@ -339,6 +343,21 @@ + #define PCI_DEVICE_ID_LATTICE_I2C_BRIDGE 0x9c2f + #define PCI_DEVICE_ID_LATTICE_JTAG_BRIDGE 0x9c30 + #define PCI_DEVICE_ID_LATTICE_LPC_BRIDGE 0x9c32 ++#define MLXPLAT_FPGA_PCI_BAR0_SIZE 0x4000 ++#define MLXPLAT_FPGA_PCI_BASE_OFFSET 0x00000000 ++#define MLXPLAT_FPGA_PCI_MSB_ADDR 0x25 ++#define MLXPLAT_FPGA_PCI_MSB_EXT_ADDR 0x20 ++#define MLXPLAT_FPGA_PCI_LSB_ADDR_OFFSET MLXPLAT_FPGA_PCI_BASE_OFFSET ++#define MLXPLAT_FPGA_PCI_MSB_ADDR_OFFSET (MLXPLAT_FPGA_PCI_BASE_OFFSET + 0x01) ++#define MLXPLAT_FPGA_PCI_DATA_OUT_OFFSET (MLXPLAT_FPGA_PCI_BASE_OFFSET + 0x02) ++#define MLXPLAT_FPGA_PCI_DATA_IN_OFFSET (MLXPLAT_FPGA_PCI_BASE_OFFSET + 0x03) ++#define MLXPLAT_FPGA_PCI_CTRL_OFFSET (MLXPLAT_FPGA_PCI_BASE_OFFSET + 0x04) ++#define MLXPLAT_FPGA_PCI_STAT_OFFSET (MLXPLAT_FPGA_PCI_BASE_OFFSET + 0x05) ++ ++#define MLXPLAT_FPGA_PCI_CTRL_READ BIT(0) ++#define MLXPLAT_FPGA_PCI_CTRL_WRITE BIT(1) ++#define MLXPLAT_FPGA_PCI_COMPLETED GENMASK(1, 0) ++#define MLXPLAT_FPGA_PCI_TO 50 /* usec */ + + /* mlxplat_priv - platform private data + * @pdev_i2c - i2c controller platform device +@@ -454,6 +473,28 @@ static struct i2c_mux_reg_platform_data mlxplat_default_mux_data[] = { + + }; + ++/* Default channels vector for regmap mux. */ ++static int mlxplat_default_regmap_mux_chan[] = { 1, 2, 3, 4, 5, 6, 7, 8 }; ++ ++/* Platform regmap mux data */ ++static struct i2c_mux_regmap_platform_data mlxplat_default_regmap_mux_data[] = { ++ { ++ .parent = 1, ++ .chan_ids = mlxplat_default_regmap_mux_chan, ++ .num_adaps = ARRAY_SIZE(mlxplat_default_regmap_mux_chan), ++ .sel_reg_addr = MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET, ++ .reg_size = 1, ++ }, ++ { ++ .parent = 1, ++ .chan_ids = mlxplat_default_regmap_mux_chan, ++ .num_adaps = ARRAY_SIZE(mlxplat_default_regmap_mux_chan), ++ .sel_reg_addr = MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET, ++ .reg_size = 1, ++ }, ++ ++}; ++ + /* Platform mux configuration variables */ + static int mlxplat_max_adap_num; + static int mlxplat_mux_num; +@@ -3769,6 +3810,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { + .mask = GENMASK(7, 0) & ~BIT(2), + .mode = 0444, + }, ++ { ++ .label = "kexec_activated", ++ .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0644, ++ }, + { + .label = "erot1_reset", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, +@@ -5391,6 +5438,7 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_EXT_MIN_OFFSET ... MLXPLAT_CPLD_LPC_REG_EXT_MAX_OFFSET: + return true; + } + return false; +@@ -5556,6 +5604,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET: + case MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET: + case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_EXT_MIN_OFFSET ... MLXPLAT_CPLD_LPC_REG_EXT_MAX_OFFSET: + return true; + } + return false; +@@ -5713,6 +5762,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET: + case MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET: + case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_EXT_MIN_OFFSET ... MLXPLAT_CPLD_LPC_REG_EXT_MAX_OFFSET: + return true; + } + return false; +@@ -5743,6 +5793,14 @@ static const struct reg_default mlxplat_mlxcpld_regmap_ng400[] = { + { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 }, + }; + ++static const struct reg_default mlxplat_mlxcpld_regmap_bf3[] = { ++ { MLXPLAT_CPLD_LPC_REG_GP2_OFFSET, 0xc1 }, ++ { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, 0x00 }, ++ { MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 }, ++ { MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET, 0x00 }, ++ { MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET, 0x00 }, ++}; ++ + static const struct reg_default mlxplat_mlxcpld_regmap_rack_switch[] = { + { MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET, MLXPLAT_REGMAP_NVSWITCH_PWM_DEFAULT }, + { MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET, 0x00 }, +@@ -5871,6 +5929,114 @@ static const struct regmap_config mlxplat_mlxcpld_regmap_config_eth_modular = { + .reg_write = mlxplat_mlxcpld_reg_write, + }; + ++/* Wait completion routine for indirect access for register map */ ++static int mlxplat_fpga_completion_wait(struct mlxplat_mlxcpld_regmap_context *ctx) ++{ ++ unsigned long end; ++ u8 status; ++ ++ end = jiffies + msecs_to_jiffies(MLXPLAT_FPGA_PCI_TO); ++ do { ++ status = ioread8(ctx->base + MLXPLAT_FPGA_PCI_STAT_OFFSET); ++ if (!(status & MLXPLAT_FPGA_PCI_COMPLETED)) ++ return 0; ++ cond_resched(); ++ } while (time_before(jiffies, end)); ++ ++ return -EIO; ++} ++ ++/* Read callback for indirect register map access */ ++static int mlxplat_fpga_reg_read(void *context, unsigned int reg, unsigned int *val) ++{ ++ struct mlxplat_mlxcpld_regmap_context *ctx = context; ++ unsigned int msb_off = MLXPLAT_FPGA_PCI_MSB_ADDR; ++ int err; ++ ++ if (reg >= MLXPLAT_CPLD_LPC_REG_EXT_MIN_OFFSET) { ++ if (reg <= MLXPLAT_CPLD_LPC_REG_EXT_MID_OFFSET) { ++ /* Access to 2-nd FPGA bank */ ++ *val = ioread8(i2c_bridge_addr + reg - ++ MLXPLAT_CPLD_LPC_REG_EXT_MIN_OFFSET); ++ return 0; ++ } ++ /* Access to 3-rd FPGA bank */ ++ reg -= MLXPLAT_CPLD_LPC_REG_EXT_MIN_OFFSET; ++ msb_off = MLXPLAT_FPGA_PCI_MSB_EXT_ADDR; ++ } ++ ++ /* Verify there is no pending transactions */ ++ err = mlxplat_fpga_completion_wait(ctx); ++ if (err) ++ return err; ++ ++ /* Set address in register space */ ++ iowrite8(msb_off, ctx->base + MLXPLAT_FPGA_PCI_MSB_ADDR_OFFSET); ++ iowrite8(reg, ctx->base + MLXPLAT_FPGA_PCI_LSB_ADDR_OFFSET); ++ /* Activate read operation */ ++ iowrite8(MLXPLAT_FPGA_PCI_CTRL_READ, ctx->base + MLXPLAT_FPGA_PCI_CTRL_OFFSET); ++ /* Verify transaction completion */ ++ err = mlxplat_fpga_completion_wait(ctx); ++ if (err) ++ return err; ++ ++ /* Read data */ ++ *val = ioread8(ctx->base + MLXPLAT_FPGA_PCI_DATA_IN_OFFSET); ++ ++ return 0; ++} ++ ++/* Write callback for indirect register map access */ ++static int mlxplat_fpga_reg_write(void *context, unsigned int reg, unsigned int val) ++{ ++ struct mlxplat_mlxcpld_regmap_context *ctx = context; ++ unsigned int msb_off = MLXPLAT_FPGA_PCI_MSB_ADDR; ++ int err; ++ ++ if (reg >= MLXPLAT_CPLD_LPC_REG_EXT_MIN_OFFSET) { ++ if (reg <= MLXPLAT_CPLD_LPC_REG_EXT_MID_OFFSET) { ++ /* Access to 2-nd FPGA bank */ ++ iowrite8(val, i2c_bridge_addr + reg - MLXPLAT_CPLD_LPC_REG_EXT_MIN_OFFSET); ++ /* Flush modification */ ++ wmb(); ++ return 0; ++ } ++ ++ /* Access to 3-rd FPGA bank */ ++ reg -= MLXPLAT_CPLD_LPC_REG_EXT_MIN_OFFSET; ++ msb_off = MLXPLAT_FPGA_PCI_MSB_EXT_ADDR; ++ } ++ ++ /* Verify there is no pending transactions */ ++ err = mlxplat_fpga_completion_wait(ctx); ++ if (err) ++ return err; ++ ++ /* Set address in register space */ ++ iowrite8(msb_off, ctx->base + MLXPLAT_FPGA_PCI_MSB_ADDR_OFFSET); ++ iowrite8(reg, ctx->base + MLXPLAT_FPGA_PCI_LSB_ADDR_OFFSET); ++ /* Set data to be written */ ++ iowrite8(val, ctx->base + MLXPLAT_FPGA_PCI_DATA_OUT_OFFSET); ++ /* Activate write operation */ ++ iowrite8(MLXPLAT_FPGA_PCI_CTRL_WRITE, ctx->base + MLXPLAT_FPGA_PCI_CTRL_OFFSET); ++ ++ return mlxplat_fpga_completion_wait(ctx); ++} ++ ++static const struct regmap_config mlxplat_fpga_regmap_config_bf3_comex_default = { ++ .reg_bits = 9, ++ .val_bits = 8, ++ .max_register = 511, ++ .cache_type = REGCACHE_FLAT, ++ .writeable_reg = mlxplat_mlxcpld_writeable_reg, ++ .readable_reg = mlxplat_mlxcpld_readable_reg, ++ .volatile_reg = mlxplat_mlxcpld_volatile_reg, ++ .reg_defaults = mlxplat_mlxcpld_regmap_bf3, ++ .num_reg_defaults = ARRAY_SIZE(mlxplat_mlxcpld_regmap_bf3), ++ .reg_read = mlxplat_fpga_reg_read, ++ .reg_write = mlxplat_fpga_reg_write, ++}; ++ + static struct resource mlxplat_mlxcpld_resources[] = { + [0] = DEFINE_RES_IRQ_NAMED(MLXPLAT_CPLD_LPC_SYSIRQ, "mlxreg-hotplug"), + }; +@@ -6282,6 +6448,30 @@ static int __init mlxplat_dmi_l1_switch_matched(const struct dmi_system_id *dmi) + return mlxplat_register_platform_device(); + } + ++static int __init mlxplat_dmi_bf3_comex_default_matched(const struct dmi_system_id *dmi) ++{ ++ int i; ++ ++ mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; ++ mlxplat_mux_hotplug_num = MLXPLAT_CPLD_DEFAULT_MUX_HOTPLUG_VECTOR; ++ mlxplat_mux_num = ARRAY_SIZE(mlxplat_default_regmap_mux_data); ++ mlxplat_mux_regmap_data = mlxplat_default_regmap_mux_data; ++ mlxplat_hotplug = &mlxplat_mlxcpld_ext_data; ++ mlxplat_hotplug->deferred_nr = ++ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; ++ mlxplat_led = &mlxplat_default_ng_led_data; ++ mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; ++ mlxplat_fan = &mlxplat_default_fan_data; ++ for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) ++ mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; ++ mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; ++ mlxplat_regmap_config = &mlxplat_fpga_regmap_config_bf3_comex_default; ++ mlxplat_reboot_nb = &mlxplat_reboot_default_nb; ++ pm_power_off = mlxplat_poweroff; ++ ++ return 1; ++} ++ + static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { + { + .callback = mlxplat_dmi_default_wc_matched, +@@ -6377,6 +6567,12 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { + DMI_MATCH(DMI_BOARD_NAME, "VMOD0015"), + }, + }, ++ { ++ .callback = mlxplat_dmi_bf3_comex_default_matched, ++ .matches = { ++ DMI_MATCH(DMI_BOARD_NAME, "VMOD0016"), ++ }, ++ }, + { + .callback = mlxplat_dmi_l1_switch_matched, + .matches = { +-- +2.20.1 + diff --git a/platform/mellanox/non-upstream-patches/patches/0196-platform-mellanox-Relocate-mlx-platform-driver.patch b/platform/mellanox/non-upstream-patches/patches/0318-mellanox-Relocate-mlx-platform-driver.patch similarity index 85% rename from platform/mellanox/non-upstream-patches/patches/0196-platform-mellanox-Relocate-mlx-platform-driver.patch rename to platform/mellanox/non-upstream-patches/patches/0318-mellanox-Relocate-mlx-platform-driver.patch index 473be771db09..4f8a1127bad2 100644 --- a/platform/mellanox/non-upstream-patches/patches/0196-platform-mellanox-Relocate-mlx-platform-driver.patch +++ b/platform/mellanox/non-upstream-patches/patches/0318-mellanox-Relocate-mlx-platform-driver.patch @@ -1,35 +1,34 @@ -From 723dacff3d93f270a52195c895e2ddf233b146d7 Mon Sep 17 00:00:00 2001 +From e56aebff93c7c72dab4958e56d518c17057344ff Mon Sep 17 00:00:00 2001 From: Vadim Pasternak -Date: Mon, 7 Nov 2022 11:52:34 +0200 -Subject: [PATCH backport 5.10 084/150] platform: mellanox: Relocate - mlx-platform driver +Date: Mon, 24 Jul 2023 11:52:56 +0000 +Subject: [PATCH backport 5.10 100/100] mellanox: Relocate mlx-platform driver Move 'mlx-platform' driver 'x86' to 'mellanox' folder. Motivation to allow running it on systems with ARM architecture. Signed-off-by: Vadim Pasternak +Reviewed-by: Michael Shych --- drivers/platform/mellanox/Kconfig | 12 ++++++++++++ drivers/platform/mellanox/Makefile | 1 + drivers/platform/{x86 => mellanox}/mlx-platform.c | 0 - drivers/platform/x86/Kconfig | 12 ------------ + drivers/platform/x86/Kconfig | 13 ------------- drivers/platform/x86/Makefile | 1 - - 5 files changed, 13 insertions(+), 13 deletions(-) + 5 files changed, 13 insertions(+), 14 deletions(-) rename drivers/platform/{x86 => mellanox}/mlx-platform.c (100%) diff --git a/drivers/platform/mellanox/Kconfig b/drivers/platform/mellanox/Kconfig -index 75e2bee17..ff8267329 100644 +index d54d36d92..dfa29127e 100644 --- a/drivers/platform/mellanox/Kconfig +++ b/drivers/platform/mellanox/Kconfig -@@ -14,6 +14,19 @@ menuconfig MELLANOX_PLATFORM +@@ -14,6 +14,18 @@ menuconfig MELLANOX_PLATFORM if MELLANOX_PLATFORM +config MLX_PLATFORM + tristate "Mellanox Technologies platform support" -+ depends on I2C -+ select REGMAP ++ depends on I2C && REGMAP + help + This option enables system support for the Mellanox Technologies + platform. The Mellanox systems provide data center networking @@ -43,7 +42,7 @@ index 75e2bee17..ff8267329 100644 tristate "Mellanox platform hotplug driver support" depends on REGMAP diff --git a/drivers/platform/mellanox/Makefile b/drivers/platform/mellanox/Makefile -index 6af37ee88..23919e56a 100644 +index 51a56ea1b..58ddeab43 100644 --- a/drivers/platform/mellanox/Makefile +++ b/drivers/platform/mellanox/Makefile @@ -3,6 +3,7 @@ @@ -52,14 +51,14 @@ index 6af37ee88..23919e56a 100644 # +obj-$(CONFIG_MLX_PLATFORM) += mlx-platform.o obj-$(CONFIG_MLXBF_BOOTCTL) += mlxbf-bootctl.o + obj-$(CONFIG_MLXBF_PMC) += mlxbf-pmc.o obj-$(CONFIG_MLXBF_TMFIFO) += mlxbf-tmfifo.o - obj-$(CONFIG_MLXREG_HOTPLUG) += mlxreg-hotplug.o diff --git a/drivers/platform/x86/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c similarity index 100% rename from drivers/platform/x86/mlx-platform.c rename to drivers/platform/mellanox/mlx-platform.c diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig -index a1858689d..4270d4c17 100644 +index 84c5b922f..4270d4c17 100644 --- a/drivers/platform/x86/Kconfig +++ b/drivers/platform/x86/Kconfig @@ -1193,19 +1193,6 @@ config I2C_MULTI_INSTANTIATE diff --git a/platform/mellanox/non-upstream-patches/patches/0319-UBUNTU-SAUCE-mlxbf-tmfifo-fix-potential-race.patch b/platform/mellanox/non-upstream-patches/patches/0319-UBUNTU-SAUCE-mlxbf-tmfifo-fix-potential-race.patch new file mode 100644 index 000000000000..868a458630d1 --- /dev/null +++ b/platform/mellanox/non-upstream-patches/patches/0319-UBUNTU-SAUCE-mlxbf-tmfifo-fix-potential-race.patch @@ -0,0 +1,63 @@ +From 0a853a02d268ae7355e559043e4dea1a1b2be9a5 Mon Sep 17 00:00:00 2001 +From: Liming Sun +Date: Thu, 13 Apr 2023 08:32:24 -0400 +Subject: [PATCH] UBUNTU: SAUCE: mlxbf-tmfifo: fix potential race +X-NVConfidentiality: public + +BugLink: https://bugs.launchpad.net/bugs/2016039 + +The fix adds memory barrier for the 'is_ready' flag and the 'vq' +pointer in mlxbf_tmfifo_virtio_find_vqs() to avoid potential race +due to out-of-order memory write. + +Signed-off-by: Liming Sun +Acked-by: Bartlomiej Zolnierkiewicz +Acked-by: Tim Gardner +[bzolnier: this patch also contains a fix for mlxbf_tmfifo_create_vdev() + failure case] +Signed-off-by: Bartlomiej Zolnierkiewicz +--- + drivers/platform/mellanox/mlxbf-tmfifo.c | 11 +++++++++-- + 1 file changed, 9 insertions(+), 2 deletions(-) + +diff --git a/drivers/platform/mellanox/mlxbf-tmfifo.c b/drivers/platform/mellanox/mlxbf-tmfifo.c +index 97956c9c9d4c..19d539fc99ae 100644 +--- a/drivers/platform/mellanox/mlxbf-tmfifo.c ++++ b/drivers/platform/mellanox/mlxbf-tmfifo.c +@@ -922,7 +922,7 @@ static void mlxbf_tmfifo_rxtx(struct mlxbf_tmfifo_vring *vring, bool is_rx) + fifo = vring->fifo; + + /* Return if vdev is not ready. */ +- if (!fifo->vdev[devid]) ++ if (!fifo || !fifo->vdev[devid]) + return; + + /* Return if another vring is running. */ +@@ -1119,9 +1119,13 @@ static int mlxbf_tmfifo_virtio_find_vqs(struct virtio_device *vdev, + goto error; + } + ++ vq->priv = vring; ++ ++ /* Make vq update visible before using it. */ ++ virtio_mb(false); ++ + vqs[i] = vq; + vring->vq = vq; +- vq->priv = vring; + } + + return 0; +@@ -1426,6 +1430,9 @@ static int mlxbf_tmfifo_probe(struct platform_device *pdev) + + mod_timer(&fifo->timer, jiffies + MLXBF_TMFIFO_TIMER_INTERVAL); + ++ /* Make all updates visible before the 'is_ready' flag. */ ++ virtio_mb(false); ++ + fifo->is_ready = 1; + return 0; + +-- +2.14.1 + diff --git a/platform/mellanox/non-upstream-patches/patches/0320-UBUNTU-SAUCE-mlxbf-tmfifo-Drop-the-Rx-packet-if-no-m.patch b/platform/mellanox/non-upstream-patches/patches/0320-UBUNTU-SAUCE-mlxbf-tmfifo-Drop-the-Rx-packet-if-no-m.patch new file mode 100644 index 000000000000..591ab5ea6176 --- /dev/null +++ b/platform/mellanox/non-upstream-patches/patches/0320-UBUNTU-SAUCE-mlxbf-tmfifo-Drop-the-Rx-packet-if-no-m.patch @@ -0,0 +1,177 @@ +From fda66dd5619067846d24d3b30398f7406b10af69 Mon Sep 17 00:00:00 2001 +From: Liming Sun +Date: Sun, 4 Jun 2023 10:28:14 -0400 +Subject: [PATCH] UBUNTU: SAUCE: mlxbf-tmfifo: Drop the Rx packet if no more + descriptors +X-NVConfidentiality: public + +BugLink: https://bugs.launchpad.net/bugs/2021749 + +This commit fixes tmfifo console stuck issue when the virtual +networking interface is in down state. In such case, the network +Rx descriptors runs out which causes the network packet stays +in the tmfifo and couldn't be popped out thus blocking the console +packets. The fix is to drop the receiving packet when no more Rx +descriptors. + +Signed-off-by: Liming Sun +Acked-by: Tim Gardner +Acked-by: Bartlomiej Zolnierkiewicz +Signed-off-by: Bartlomiej Zolnierkiewicz +--- + drivers/platform/mellanox/mlxbf-tmfifo.c | 65 ++++++++++++++++++++++---------- + 1 file changed, 46 insertions(+), 19 deletions(-) + +diff --git a/drivers/platform/mellanox/mlxbf-tmfifo.c b/drivers/platform/mellanox/mlxbf-tmfifo.c +index 19d539fc99ae..88610f45456b 100644 +--- a/drivers/platform/mellanox/mlxbf-tmfifo.c ++++ b/drivers/platform/mellanox/mlxbf-tmfifo.c +@@ -59,6 +59,7 @@ struct mlxbf_tmfifo; + * @vq: pointer to the virtio virtqueue + * @desc: current descriptor of the pending packet + * @desc_head: head descriptor of the pending packet ++ * @drop_desc: dummy desc for packet dropping + * @cur_len: processed length of the current descriptor + * @rem_len: remaining length of the pending packet + * @pkt_len: total length of the pending packet +@@ -75,6 +76,7 @@ struct mlxbf_tmfifo_vring { + struct virtqueue *vq; + struct vring_desc *desc; + struct vring_desc *desc_head; ++ struct vring_desc drop_desc; + int cur_len; + int rem_len; + u32 pkt_len; +@@ -86,6 +88,11 @@ struct mlxbf_tmfifo_vring { + struct mlxbf_tmfifo *fifo; + }; + ++/* Check whether vring is in drop mode. */ ++#define IS_VRING_DROP(_r) ({ \ ++ typeof(_r) (r) = (_r); \ ++ (r->desc_head == &r->drop_desc ? true : false); }) ++ + /* Interrupt types. */ + enum { + MLXBF_TM_RX_LWM_IRQ, +@@ -275,6 +282,7 @@ static int mlxbf_tmfifo_alloc_vrings(struct mlxbf_tmfifo *fifo, + vring->align = SMP_CACHE_BYTES; + vring->index = i; + vring->vdev_id = tm_vdev->vdev.id.device; ++ vring->drop_desc.len = 0xffff; + dev = &tm_vdev->vdev.dev; + + size = vring_size(vring->num, vring->align); +@@ -380,7 +388,7 @@ static u32 mlxbf_tmfifo_get_pkt_len(struct mlxbf_tmfifo_vring *vring, + return len; + } + +-static void mlxbf_tmfifo_release_pending_pkt(struct mlxbf_tmfifo_vring *vring) ++static void mlxbf_tmfifo_release_pkt(struct mlxbf_tmfifo_vring *vring) + { + struct vring_desc *desc_head; + u32 len = 0; +@@ -508,8 +516,6 @@ static int mlxbf_tmfifo_get_rx_avail(struct mlxbf_tmfifo *fifo) + return FIELD_GET(MLXBF_TMFIFO_RX_STS__COUNT_MASK, sts); + } + +- +- + /* Get the number of available words in the TmFifo for sending. */ + static int mlxbf_tmfifo_get_tx_avail(struct mlxbf_tmfifo *fifo, int vdev_id) + { +@@ -732,19 +738,25 @@ static void mlxbf_tmfifo_rxtx_word(struct mlxbf_tmfifo_vring *vring, + + if (vring->cur_len + sizeof(u64) <= len) { + /* The whole word. */ +- if (is_rx) +- memcpy(addr + vring->cur_len, &data, sizeof(u64)); +- else +- memcpy(&data, addr + vring->cur_len, sizeof(u64)); ++ if (!IS_VRING_DROP(vring)) { ++ if (is_rx) ++ memcpy(addr + vring->cur_len, &data, ++ sizeof(u64)); ++ else ++ memcpy(&data, addr + vring->cur_len, ++ sizeof(u64)); ++ } + vring->cur_len += sizeof(u64); + } else { + /* Leftover bytes. */ +- if (is_rx) +- memcpy(addr + vring->cur_len, &data, +- len - vring->cur_len); +- else +- memcpy(&data, addr + vring->cur_len, +- len - vring->cur_len); ++ if (!IS_VRING_DROP(vring)) { ++ if (is_rx) ++ memcpy(addr + vring->cur_len, &data, ++ len - vring->cur_len); ++ else ++ memcpy(&data, addr + vring->cur_len, ++ len - vring->cur_len); ++ } + vring->cur_len = len; + } + +@@ -847,8 +859,16 @@ static bool mlxbf_tmfifo_rxtx_one_desc(struct mlxbf_tmfifo_vring *vring, + /* Get the descriptor of the next packet. */ + if (!vring->desc) { + desc = mlxbf_tmfifo_get_next_pkt(vring, is_rx); +- if (!desc) +- return false; ++ if (!desc) { ++ /* Drop next Rx packet to avoid stuck. */ ++ if (is_rx) { ++ desc = &vring->drop_desc; ++ vring->desc_head = desc; ++ vring->desc = desc; ++ } else { ++ return false; ++ } ++ } + } else { + desc = vring->desc; + } +@@ -881,17 +901,24 @@ static bool mlxbf_tmfifo_rxtx_one_desc(struct mlxbf_tmfifo_vring *vring, + vring->rem_len -= len; + + /* Get the next desc on the chain. */ +- if (vring->rem_len > 0 && ++ if (!IS_VRING_DROP(vring) && vring->rem_len > 0 && + (virtio16_to_cpu(vdev, desc->flags) & VRING_DESC_F_NEXT)) { + idx = virtio16_to_cpu(vdev, desc->next); + desc = &vr->desc[idx]; + goto mlxbf_tmfifo_desc_done; + } + +- /* Done and release the pending packet. */ +- mlxbf_tmfifo_release_pending_pkt(vring); ++ /* Done and release the packet. */ + desc = NULL; + fifo->vring[is_rx] = NULL; ++ if (!IS_VRING_DROP(vring)) { ++ mlxbf_tmfifo_release_pkt(vring); ++ } else { ++ vring->pkt_len = 0; ++ vring->desc_head = NULL; ++ vring->desc = NULL; ++ return false; ++ } + + /* + * Make sure the load/store are in order before +@@ -1073,7 +1100,7 @@ static void mlxbf_tmfifo_virtio_del_vqs(struct virtio_device *vdev) + + /* Release the pending packet. */ + if (vring->desc) +- mlxbf_tmfifo_release_pending_pkt(vring); ++ mlxbf_tmfifo_release_pkt(vring); + vq = vring->vq; + if (vq) { + vring->vq = NULL; +-- +2.14.1 + diff --git a/platform/mellanox/non-upstream-patches/patches/0321-UBUNTU-SAUCE-mlxbf-tmfifo-Drop-jumbo-frames.patch b/platform/mellanox/non-upstream-patches/patches/0321-UBUNTU-SAUCE-mlxbf-tmfifo-Drop-jumbo-frames.patch new file mode 100644 index 000000000000..df0e01e79feb --- /dev/null +++ b/platform/mellanox/non-upstream-patches/patches/0321-UBUNTU-SAUCE-mlxbf-tmfifo-Drop-jumbo-frames.patch @@ -0,0 +1,100 @@ +From a72d23ea2daedf011b2a3239c7f1dbfe28d36e7d Mon Sep 17 00:00:00 2001 +From: Liming Sun +Date: Sun, 4 Jun 2023 10:28:15 -0400 +Subject: [PATCH] UBUNTU: SAUCE: mlxbf-tmfifo: Drop jumbo frames +X-NVConfidentiality: public + +BugLink: https://bugs.launchpad.net/bugs/2021749 + +This commit drops over-sized network packets to avoid tmfifo +queue stuck. + +Signed-off-by: Liming Sun +Acked-by: Tim Gardner +Acked-by: Bartlomiej Zolnierkiewicz +[bzolnier: removed Change-Id from the commit description] +Signed-off-by: Bartlomiej Zolnierkiewicz +--- + drivers/platform/mellanox/mlxbf-tmfifo.c | 24 +++++++++++++++++------- + 1 file changed, 17 insertions(+), 7 deletions(-) + +diff --git a/drivers/platform/mellanox/mlxbf-tmfifo.c b/drivers/platform/mellanox/mlxbf-tmfifo.c +index 88610f45456b..4f3226007e32 100644 +--- a/drivers/platform/mellanox/mlxbf-tmfifo.c ++++ b/drivers/platform/mellanox/mlxbf-tmfifo.c +@@ -234,7 +234,7 @@ static u8 mlxbf_tmfifo_net_default_mac[ETH_ALEN] = { + static efi_char16_t mlxbf_tmfifo_efi_name[] = L"RshimMacAddr"; + + /* Maximum L2 header length. */ +-#define MLXBF_TMFIFO_NET_L2_OVERHEAD 36 ++#define MLXBF_TMFIFO_NET_L2_OVERHEAD (ETH_HLEN + VLAN_HLEN) + + /* Supported virtio-net features. */ + #define MLXBF_TMFIFO_NET_FEATURES \ +@@ -773,13 +773,14 @@ static void mlxbf_tmfifo_rxtx_word(struct mlxbf_tmfifo_vring *vring, + * flag is set. + */ + static void mlxbf_tmfifo_rxtx_header(struct mlxbf_tmfifo_vring *vring, +- struct vring_desc *desc, ++ struct vring_desc **desc, + bool is_rx, bool *vring_change) + { + struct mlxbf_tmfifo *fifo = vring->fifo; + struct virtio_net_config *config; + struct mlxbf_tmfifo_msg_hdr hdr; + int vdev_id, hdr_len; ++ bool drop_rx = false; + + /* Read/Write packet header. */ + if (is_rx) { +@@ -801,8 +802,8 @@ static void mlxbf_tmfifo_rxtx_header(struct mlxbf_tmfifo_vring *vring, + if (ntohs(hdr.len) > + __virtio16_to_cpu(virtio_legacy_is_little_endian(), + config->mtu) + +- MLXBF_TMFIFO_NET_L2_OVERHEAD) +- return; ++ MLXBF_TMFIFO_NET_L2_OVERHEAD) ++ drop_rx = true; + } else { + vdev_id = VIRTIO_ID_CONSOLE; + hdr_len = 0; +@@ -817,16 +818,25 @@ static void mlxbf_tmfifo_rxtx_header(struct mlxbf_tmfifo_vring *vring, + + if (!tm_dev2) + return; +- vring->desc = desc; ++ vring->desc = *desc; + vring = &tm_dev2->vrings[MLXBF_TMFIFO_VRING_RX]; + *vring_change = true; + } ++ ++ if (drop_rx && !IS_VRING_DROP(vring)) { ++ if (vring->desc_head) ++ mlxbf_tmfifo_release_pkt(vring); ++ *desc = &vring->drop_desc; ++ vring->desc_head = *desc; ++ vring->desc = *desc; ++ } ++ + vring->pkt_len = ntohs(hdr.len) + hdr_len; + } else { + /* Network virtio has an extra header. */ + hdr_len = (vring->vdev_id == VIRTIO_ID_NET) ? + sizeof(struct virtio_net_hdr) : 0; +- vring->pkt_len = mlxbf_tmfifo_get_pkt_len(vring, desc); ++ vring->pkt_len = mlxbf_tmfifo_get_pkt_len(vring, *desc); + hdr.type = (vring->vdev_id == VIRTIO_ID_NET) ? + VIRTIO_ID_NET : VIRTIO_ID_CONSOLE; + hdr.len = htons(vring->pkt_len - hdr_len); +@@ -875,7 +885,7 @@ static bool mlxbf_tmfifo_rxtx_one_desc(struct mlxbf_tmfifo_vring *vring, + + /* Beginning of a packet. Start to Rx/Tx packet header. */ + if (vring->pkt_len == 0) { +- mlxbf_tmfifo_rxtx_header(vring, desc, is_rx, &vring_change); ++ mlxbf_tmfifo_rxtx_header(vring, &desc, is_rx, &vring_change); + (*avail)--; + + /* Return if new packet is for another ring. */ +-- +2.14.1 + diff --git a/platform/mellanox/non-upstream-patches/patches/0322-UBUNTU-SAUCE-mlxbf-tmfifo.c-Amend-previous-tmfifo-pa.patch b/platform/mellanox/non-upstream-patches/patches/0322-UBUNTU-SAUCE-mlxbf-tmfifo.c-Amend-previous-tmfifo-pa.patch new file mode 100644 index 000000000000..1e26f7f8d5d4 --- /dev/null +++ b/platform/mellanox/non-upstream-patches/patches/0322-UBUNTU-SAUCE-mlxbf-tmfifo.c-Amend-previous-tmfifo-pa.patch @@ -0,0 +1,37 @@ +From b23bb194dc1dbad104f2afce1a8ed202d182b73b Mon Sep 17 00:00:00 2001 +From: Shih-Yi Chen +Date: Thu, 20 Jul 2023 16:39:40 -0400 +Subject: [PATCH] UBUNTU: SAUCE: mlxbf-tmfifo.c: Amend previous tmfifo patch w/ + regard to schedule_work +X-NVConfidentiality: public + +BugLink: https://bugs.launchpad.net/bugs/2028197 + +Fix rshim console output got cutoff due to tmfifo driver not processing all virtio console notifications. + +Signed-off-by: Shih-Yi Chen +Reviewed-by: Liming Sun +Acked-by: Bartlomiej Zolnierkiewicz +Acked-by: Tim Gardner +[bzolnier: use a short URL version for BugLink] +Signed-off-by: Bartlomiej Zolnierkiewicz +--- + drivers/platform/mellanox/mlxbf-tmfifo.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/platform/mellanox/mlxbf-tmfifo.c b/drivers/platform/mellanox/mlxbf-tmfifo.c +index 4f3226007e32..36b87d5d8baf 100644 +--- a/drivers/platform/mellanox/mlxbf-tmfifo.c ++++ b/drivers/platform/mellanox/mlxbf-tmfifo.c +@@ -1065,6 +1065,8 @@ static bool mlxbf_tmfifo_virtio_notify(struct virtqueue *vq) + tm_vdev = fifo->vdev[VIRTIO_ID_CONSOLE]; + mlxbf_tmfifo_console_output(tm_vdev, vring); + spin_unlock_irqrestore(&fifo->spin_lock[0], flags); ++ test_and_set_bit(MLXBF_TM_TX_LWM_IRQ, ++ &fifo->pend_events); + } else if (test_and_set_bit(MLXBF_TM_TX_LWM_IRQ, + &fifo->pend_events)) { + return true; +-- +2.14.1 + diff --git a/platform/mellanox/non-upstream-patches/patches/0323-mlxbf_gige-add-set_link_ksettings-ethtool-callback.patch b/platform/mellanox/non-upstream-patches/patches/0323-mlxbf_gige-add-set_link_ksettings-ethtool-callback.patch new file mode 100644 index 000000000000..5198d6e54f4a --- /dev/null +++ b/platform/mellanox/non-upstream-patches/patches/0323-mlxbf_gige-add-set_link_ksettings-ethtool-callback.patch @@ -0,0 +1,39 @@ +From 29ebd6bb4afdf9f4aad3019c0ca9892b69dbff40 Mon Sep 17 00:00:00 2001 +From: David Thompson +Date: Thu, 12 Jan 2023 15:26:08 -0500 +Subject: [PATCH] mlxbf_gige: add "set_link_ksettings" ethtool callback +X-NVConfidentiality: public + +BugLink: https://bugs.launchpad.net/bugs/2012649 + +This patch extends the "ethtool_ops" data structure to +include the "set_link_ksettings" callback. This change +enables configuration of the various interface speeds +that the BlueField-3 supports (10Mbps, 100Mbps, and 1Gbps). + +Signed-off-by: David Thompson +Signed-off-by: Asmaa Mnebhi +Reviewed-by: Andrew Lunn +Signed-off-by: Jakub Kicinski +(cherry picked from commit cedd97737a1f302b3d0493d7054a35e0c5997b99) +Signed-off-by: David Thompson +Acked-by: Tim Gardner +Acked-by: Bartlomiej Zolnierkiewicz +Signed-off-by: Bartlomiej Zolnierkiewicz +--- + drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_ethtool.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_ethtool.c b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_ethtool.c +index 257724323..602537f62 100644 +--- a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_ethtool.c ++++ b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_ethtool.c +@@ -170,4 +170,5 @@ const struct ethtool_ops mlxbf_gige_ethtool_ops = { + .nway_reset = phy_ethtool_nway_reset, + .get_pauseparam = mlxbf_gige_get_pauseparam, + .get_link_ksettings = phy_ethtool_get_link_ksettings, ++ .set_link_ksettings = phy_ethtool_set_link_ksettings, + }; +-- +2.14.1 + diff --git a/platform/mellanox/non-upstream-patches/patches/0324-mlxbf_gige-fix-white-space-in-mlxbf_gige_eth_ioctl.patch b/platform/mellanox/non-upstream-patches/patches/0324-mlxbf_gige-fix-white-space-in-mlxbf_gige_eth_ioctl.patch new file mode 100644 index 000000000000..b24dc636a5fd --- /dev/null +++ b/platform/mellanox/non-upstream-patches/patches/0324-mlxbf_gige-fix-white-space-in-mlxbf_gige_eth_ioctl.patch @@ -0,0 +1,41 @@ +From dc7c16946141474dad808f7bef9c00a547ed0db6 Mon Sep 17 00:00:00 2001 +From: David Thompson +Date: Thu, 12 Jan 2023 15:26:09 -0500 +Subject: [PATCH] mlxbf_gige: fix white space in mlxbf_gige_eth_ioctl +X-NVConfidentiality: public + +BugLink: https://bugs.launchpad.net/bugs/2012649 + +This patch fixes the white space issue raised by checkpatch: +CHECK: Alignment should match open parenthesis ++static int mlxbf_gige_eth_ioctl(struct net_device *netdev, ++ struct ifreq *ifr, int cmd) + +Signed-off-by: David Thompson +Signed-off-by: Asmaa Mnebhi +Signed-off-by: Jakub Kicinski +(cherry picked from commit e1cc8ce46200b3f3026e546053458c6f8046ef27) +Signed-off-by: David Thompson +Acked-by: Tim Gardner +Acked-by: Bartlomiej Zolnierkiewicz +Signed-off-by: Bartlomiej Zolnierkiewicz +--- + drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c +index 867248e3c..602260f2b 100644 +--- a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c ++++ b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_main.c +@@ -205,7 +205,7 @@ static int mlxbf_gige_stop(struct net_device *netdev) + } + + static int mlxbf_gige_do_ioctl(struct net_device *netdev, +- struct ifreq *ifr, int cmd) ++ struct ifreq *ifr, int cmd) + { + if (!(netif_running(netdev))) + return -EINVAL; +-- +2.14.1 + diff --git a/platform/mellanox/non-upstream-patches/patches/0325-UBUNTU-SAUCE-mlxbf-bootctl-Fix-kernel-panic-due-to-b.patch b/platform/mellanox/non-upstream-patches/patches/0325-UBUNTU-SAUCE-mlxbf-bootctl-Fix-kernel-panic-due-to-b.patch new file mode 100644 index 000000000000..f867f38cf679 --- /dev/null +++ b/platform/mellanox/non-upstream-patches/patches/0325-UBUNTU-SAUCE-mlxbf-bootctl-Fix-kernel-panic-due-to-b.patch @@ -0,0 +1,57 @@ +From aaad0c7201b7f3908e30c529fb5ab83dc9851c83 Mon Sep 17 00:00:00 2001 +From: Asmaa Mnebhi +Date: Thu, 20 Jul 2023 16:37:37 -0400 +Subject: [PATCH] UBUNTU: SAUCE: mlxbf-bootctl: Fix kernel panic due to buffer + overflow +X-NVConfidentiality: public + +BugLink: https://bugs.launchpad.net/bugs/2028309 + +Running the following LTP (linux-test-project) script, causes +a kernel panic and a reboot of the DPU: +ltp/testcases/bin/read_all -d /sys -q -r 10 + +The above test reads all directory and files under /sys. +Reading the sysfs entry "large_icm" causes the kernel panic +due to a garbage value returned via i2c read. That garbage +value causes a buffer overflow in sprintf. + +Replace sprintf with snprintf. And also add missing lock and +increase the buffer size to PAGE_SIZE. + +Signed-off-by: Asmaa Mnebhi +Acked-by: Bartlomiej Zolnierkiewicz +Acked-by: Tim Gardner +Signed-off-by: Bartlomiej Zolnierkiewicz +--- + drivers/platform/mellanox/mlxbf-bootctl.c | 7 +++---- + 1 file changed, 3 insertions(+), 4 deletions(-) + +diff --git a/drivers/platform/mellanox/mlxbf-bootctl.c b/drivers/platform/mellanox/mlxbf-bootctl.c +index a68bf5b27013..52666ee360b2 100644 +--- a/drivers/platform/mellanox/mlxbf-bootctl.c ++++ b/drivers/platform/mellanox/mlxbf-bootctl.c +@@ -387,17 +387,16 @@ static ssize_t oob_mac_store(struct device_driver *drv, const char *buf, + + static ssize_t large_icm_show(struct device_driver *drv, char *buf) + { +- char icm_str[MAX_ICM_BUFFER_SIZE] = { 0 }; + struct arm_smccc_res res; + ++ mutex_lock(&icm_ops_lock); + arm_smccc_smc(MLNX_HANDLE_GET_ICM_INFO, 0, 0, 0, 0, + 0, 0, 0, &res); ++ mutex_unlock(&icm_ops_lock); + if (res.a0) + return -EPERM; + +- sprintf(icm_str, "0x%lx", res.a1); +- +- return snprintf(buf, sizeof(icm_str), "%s", icm_str); ++ return snprintf(buf, PAGE_SIZE, "0x%lx", res.a1); + } + + static ssize_t large_icm_store(struct device_driver *drv, const char *buf, +-- +2.14.1 + diff --git a/platform/mellanox/non-upstream-patches/patches/0326-platform-mellanox-mlxreg-hotplug-Add-support-for-new.patch b/platform/mellanox/non-upstream-patches/patches/0326-platform-mellanox-mlxreg-hotplug-Add-support-for-new.patch new file mode 100644 index 000000000000..3905bd494ddd --- /dev/null +++ b/platform/mellanox/non-upstream-patches/patches/0326-platform-mellanox-mlxreg-hotplug-Add-support-for-new.patch @@ -0,0 +1,88 @@ +From b9d89fb53b5361df87974a223cb4b423a647bc2f Mon Sep 17 00:00:00 2001 +From: Vadim Pasternak +Date: Thu, 24 Aug 2023 11:47:54 +0000 +Subject: [PATCH] platform/mellanox: mlxreg-hotplug: Add support for new flavor + of capability registers +X-NVConfidentiality: public + +Hotplug platform data is common across the various systems, while +hotplug driver should be able to configure only the instances relevant +to specific system. + +For example, platform hoptplug data might contain descriptions for fan1, +fan2, ..., fan{n}, while some systems equipped with all 'n' fans, +others with less. +Same for power units, power controllers, ASICs and so on. + +For detection of the real number of equipped devices capability +registers are used. +These registers used to indicate presence of hotplug devices through +the bitmap. + +For some new big modular systems, these registers will provide presence +by counters. + +Use slot parameter to determine whether capability register contains +bitmask or counter. + +Some 'capability' registers can be shared between different resources. +Use fields 'capability_bit' and 'capability_mask' for getting only +relevant capability bits. + +Signed-off-by: Vadim Pasternak +Reviewed-by: Felix Radensky +--- + drivers/platform/mellanox/mlxreg-hotplug.c | 23 +++++++++++++++++++++-- + 1 file changed, 21 insertions(+), 2 deletions(-) + +diff --git a/drivers/platform/mellanox/mlxreg-hotplug.c b/drivers/platform/mellanox/mlxreg-hotplug.c +index c5abedd35..3737af0d3 100644 +--- a/drivers/platform/mellanox/mlxreg-hotplug.c ++++ b/drivers/platform/mellanox/mlxreg-hotplug.c +@@ -275,6 +275,13 @@ static int mlxreg_hotplug_attr_init(struct mlxreg_hotplug_priv_data *priv) + if (ret) + return ret; + ++ if (!regval) ++ continue; ++ ++ /* Remove non-relevant bits. */ ++ if (item->capability_mask) ++ regval = rol32(regval & item->capability_mask, ++ item->capability_bit); + item->mask = GENMASK((regval & item->mask) - 1, 0); + } + +@@ -295,7 +302,19 @@ static int mlxreg_hotplug_attr_init(struct mlxreg_hotplug_priv_data *priv) + if (ret) + return ret; + +- if (!(regval & data->bit)) { ++ /* ++ * In case slot field is provided, capability ++ * register contains counter, otherwise bitmask. ++ * Skip non-relevant entries if slot set and ++ * exceeds counter. Othewise validate entry by ++ * matching bitmask. ++ */ ++ if (data->capability_mask) ++ regval = rol32(regval & data->capability_mask, ++ data->capability_bit); ++ if (data->slot > regval) { ++ break; ++ } else if (!(regval & data->bit) && !data->slot) { + data++; + continue; + } +@@ -626,7 +645,7 @@ static int mlxreg_hotplug_set_irq(struct mlxreg_hotplug_priv_data *priv) + if (ret) + goto out; + +- if (!(regval & data->bit)) ++ if (!(regval & data->bit) && !data->slot) + item->mask &= ~BIT(j); + } + } +-- +2.14.1 + diff --git a/platform/mellanox/non-upstream-patches/patches/0327-platform-mellanox-mlx-platform-Change-register-name.patch b/platform/mellanox/non-upstream-patches/patches/0327-platform-mellanox-mlx-platform-Change-register-name.patch new file mode 100644 index 000000000000..7953c4149461 --- /dev/null +++ b/platform/mellanox/non-upstream-patches/patches/0327-platform-mellanox-mlx-platform-Change-register-name.patch @@ -0,0 +1,57 @@ +From 45cc492edbf7dc36e20a166355840a5cce0841c9 Mon Sep 17 00:00:00 2001 +From: Felix Radensky +Date: Thu, 21 Sep 2023 05:53:11 +0000 +Subject: [PATCH] platform: mellanox: mlx-platform: Change register name +X-NVConfidentiality: public + +Register 0xd9 was repurposed on new systems. Change its name +to correctly reflect the new functionality. + +Signed-off-by: Felix Radensky +Reviewed-by: Vadim Pasternak +--- + drivers/platform/mellanox/mlx-platform.c | 7 +++---- + 1 file changed, 3 insertions(+), 4 deletions(-) + +diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c +index 20211d28c..4efd06eaf 100644 +--- a/drivers/platform/mellanox/mlx-platform.c ++++ b/drivers/platform/mellanox/mlx-platform.c +@@ -147,7 +147,7 @@ + #define MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET 0xd1 + #define MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET 0xd2 + #define MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET 0xd3 +-#define MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET 0xd9 ++#define MLXPLAT_CPLD_LPC_REG_CPLD6_MVER_OFFSET 0xd9 + #define MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET 0xdb + #define MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET 0xda + #define MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET 0xdc +@@ -5428,7 +5428,6 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: + case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET: +- case MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET: + case MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET: + case MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET: + case MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET: +@@ -5565,7 +5564,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: + case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET: +- case MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_CPLD6_MVER_OFFSET: + case MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET: + case MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET: + case MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET: +@@ -5723,7 +5722,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET: + case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET: +- case MLXPLAT_CPLD_LPC_REG_DBG_CTRL_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_CPLD6_MVER_OFFSET: + case MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET: + case MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET: + case MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET: +-- +2.14.1 + diff --git a/platform/mellanox/non-upstream-patches/patches/0328-platform-mellanox-mlx-platform-Add-support-for-new-X.patch b/platform/mellanox/non-upstream-patches/patches/0328-platform-mellanox-mlx-platform-Add-support-for-new-X.patch new file mode 100644 index 000000000000..ad38b1555460 --- /dev/null +++ b/platform/mellanox/non-upstream-patches/patches/0328-platform-mellanox-mlx-platform-Add-support-for-new-X.patch @@ -0,0 +1,1383 @@ +From e1431c088b27f877747f9a74e07c8b158db7ec66 Mon Sep 17 00:00:00 2001 +From: Felix Radensky +Date: Mon, 4 Sep 2023 18:28:37 +0000 +Subject: [PATCH 1/4] From f25ad1918eb613aa315805717603a0960f42e6df Mon Sep 17 + 00:00:00 2001 Subject: [PATCH] platform: mellanox: mlx-platform: Add support + for new XDR systems X-NVConfidentiality: public +X-NVConfidentiality: public + +Add support for QM3400 and QM3000, Nvidia XDR switches. + +QM3400 is a 57.6Tbps switch based on Nvidia Quantum-3 ASIC. +It provides up-to 800Gbps full bidirectional bandwidth per port. +The system supports 36 OSFP cages and fits into standard 2U racks. + +QM3400 Features: + - 36 OSFP ports supporting 2.5Gbps - 800Gbps speeds. + - Air-cooled with 4 + 1 redundant fan units. + - 2 + 2 redundant 2000W PSUs. + - System management board based on Intel Coffee Lake CPU + with secure-boot support. + +QM3000 is a 115.2Tbps switch based on Nvidia Quantum-3 ASIC. +It provides up-to 800Gbps full bidirectional bandwidth per port. +The system supports 72 OSFP cages and fits into standard 4U racks. + +QM3000 Features: + - 72 OSFP ports or 144 aggregated XDR ports supporting 800Gbps speeds. + - Air-cooled with 9 + 1 redundant fan units. + - 4 + 4 redundant 2000W PSUs. + - System management board based on Intel Coffee Lake CPU + with secure-boot support. + +Signed-off-by: Felix Radensky +Reviewed-by: Vadim Pasternak +--- + drivers/platform/mellanox/mlx-platform.c | 1057 +++++++++++++++++++++++++++++- + 1 file changed, 1037 insertions(+), 20 deletions(-) + +diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c +index 20211d28c..66b1f32f5 100644 +--- a/drivers/platform/mellanox/mlx-platform.c ++++ b/drivers/platform/mellanox/mlx-platform.c +@@ -51,6 +51,7 @@ + #define MLXPLAT_CPLD_LPC_REG_LED5_OFFSET 0x24 + #define MLXPLAT_CPLD_LPC_REG_LED6_OFFSET 0x25 + #define MLXPLAT_CPLD_LPC_REG_LED7_OFFSET 0x26 ++#define MLXPLAT_CPLD_LPC_REG_LED8_OFFSET 0x27 + #define MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION 0x2a + #define MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET 0x2b + #define MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET 0x2d +@@ -96,9 +97,21 @@ + #define MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET 0x70 + #define MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET 0x71 + #define MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET 0x72 ++#define MLXPLAT_CPLD_LPC_REG_CPLD6_VER_OFFSET 0x7c ++#define MLXPLAT_CPLD_LPC_REG_CPLD6_PN_OFFSET 0x7d ++#define MLXPLAT_CPLD_LPC_REG_CPLD6_PN1_OFFSET 0x7e ++#define MLXPLAT_CPLD_LPC_REG_ASIC3_HEALTH_OFFSET 0x82 ++#define MLXPLAT_CPLD_LPC_REG_ASIC3_EVENT_OFFSET 0x83 ++#define MLXPLAT_CPLD_LPC_REG_ASIC3_MASK_OFFSET 0x84 ++#define MLXPLAT_CPLD_LPC_REG_ASIC4_HEALTH_OFFSET 0x85 ++#define MLXPLAT_CPLD_LPC_REG_ASIC4_EVENT_OFFSET 0x86 ++#define MLXPLAT_CPLD_LPC_REG_ASIC4_MASK_OFFSET 0x87 + #define MLXPLAT_CPLD_LPC_REG_FAN_OFFSET 0x88 + #define MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET 0x89 + #define MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET 0x8a ++#define MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET 0x8b ++#define MLXPLAT_CPLD_LPC_REG_FAN2_EVENT_OFFSET 0x8c ++#define MLXPLAT_CPLD_LPC_REG_FAN2_MASK_OFFSET 0x8d + #define MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET 0x8e + #define MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET 0x8f + #define MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET 0x90 +@@ -130,10 +143,15 @@ + #define MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET 0xaa + #define MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET 0xab + #define MLXPLAT_CPLD_LPC_REG_LC_PWR_ON 0xb2 ++#define MLXPLAT_CPLD_LPC_REG_TACHO19_OFFSET 0xb4 ++#define MLXPLAT_CPLD_LPC_REG_TACHO20_OFFSET 0xb5 + #define MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET 0xb6 + #define MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET 0xb7 + #define MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET 0xb8 + #define MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET 0xb9 ++#define MLXPLAT_CPLD_LPC_REG_TACHO17_OFFSET 0xba ++#define MLXPLAT_CPLD_LPC_REG_TACHO18_OFFSET 0xbb ++#define MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET 0xc1 + #define MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET 0xc2 + #define MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT 0xc3 + #define MLXPLAT_CPLD_LPC_REG_CPLD5_MVER_OFFSET 0xc4 +@@ -184,6 +202,8 @@ + #define MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET 0xfb + #define MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET 0xfc + #define MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET 0xfd ++#define MLXPLAT_CPLD_LPC_REG_TACHO15_OFFSET 0xfe ++#define MLXPLAT_CPLD_LPC_REG_TACHO16_OFFSET 0xff + #define MLXPLAT_CPLD_LPC_REG_EXT_MIN_OFFSET 0x100 + #define MLXPLAT_CPLD_LPC_REG_EXT_MID_OFFSET 0x195 + #define MLXPLAT_CPLD_LPC_REG_EXT_MAX_OFFSET 0x1ff +@@ -236,20 +256,30 @@ + #define MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2 BIT(2) + #define MLXPLAT_CPLD_LOW_AGGR_MASK_PWR_BUT GENMASK(5, 4) + #define MLXPLAT_CPLD_LOW_AGGR_MASK_I2C BIT(6) ++#define MLXPLAT_CPLD_LOW_AGGR_MASK_MULTI_ASICS GENMASK(3, 0) ++#define MLXPLAT_CPLD_LOW_AGGR_MASK_FRU BIT(7) + #define MLXPLAT_CPLD_PSU_MASK GENMASK(1, 0) + #define MLXPLAT_CPLD_PWR_MASK GENMASK(1, 0) + #define MLXPLAT_CPLD_PSU_EXT_MASK GENMASK(3, 0) + #define MLXPLAT_CPLD_PWR_EXT_MASK GENMASK(3, 0) ++#define MLXPLAT_CPLD_PSU_XDR_MASK GENMASK(7, 0) ++#define MLXPLAT_CPLD_PWR_XDR_MASK GENMASK(7, 0) + #define MLXPLAT_CPLD_FAN_MASK GENMASK(3, 0) + #define MLXPLAT_CPLD_ASIC_MASK GENMASK(1, 0) ++#define MLXPLAT_CPLD_ASIC_XDR_MASK GENMASK(3, 0) + #define MLXPLAT_CPLD_FAN_NG_MASK GENMASK(6, 0) + #define MLXPLAT_CPLD_FAN_QMB8700_MASK GENMASK(5, 0) ++#define MLXPLAT_CPLD_FAN_XDR_MASK GENMASK(7, 0) ++#define MLXPLAT_CPLD_FAN_XDR_EXT_MASK GENMASK(1, 0) + #define MLXPLAT_CPLD_LED_LO_NIBBLE_MASK GENMASK(7, 4) + #define MLXPLAT_CPLD_LED_HI_NIBBLE_MASK GENMASK(3, 0) + #define MLXPLAT_CPLD_VOLTREG_UPD_MASK GENMASK(5, 4) + #define MLXPLAT_CPLD_GWP_MASK GENMASK(0, 0) + #define MLXPLAT_CPLD_EROT_MASK GENMASK(1, 0) + #define MLXPLAT_CPLD_FU_CAP_MASK GENMASK(1, 0) ++#define MLXPLAT_CPLD_PSU_CAP_MASK GENMASK(3, 0) ++#define MLXPLAT_CPLD_FAN_CAP_MASK GENMASK(7, 0) ++#define MLXPLAT_CPLD_ASIC_CAP_MASK GENMASK(7, 0) + #define MLXPLAT_CPLD_PWR_BUTTON_MASK BIT(0) + #define MLXPLAT_CPLD_LATCH_RST_MASK BIT(6) + #define MLXPLAT_CPLD_THERMAL1_PDB_MASK BIT(3) +@@ -295,6 +325,7 @@ + #define MLXPLAT_CPLD_CH4_ETH_MODULAR 51 + #define MLXPLAT_CPLD_CH2_RACK_SWITCH 18 + #define MLXPLAT_CPLD_CH2_NG800 34 ++#define MLXPLAT_CPLD_CH2_XDR 66 + + /* Number of LPC attached MUX platform devices */ + #define MLXPLAT_CPLD_LPC_MUX_DEVS 4 +@@ -303,6 +334,7 @@ + #define MLXPLAT_CPLD_NR_NONE -1 + #define MLXPLAT_CPLD_PSU_DEFAULT_NR 10 + #define MLXPLAT_CPLD_PSU_MSNXXXX_NR 4 ++#define MLXPLAT_CPLD_PSU_XDR_NR 3 + #define MLXPLAT_CPLD_FAN1_DEFAULT_NR 11 + #define MLXPLAT_CPLD_FAN2_DEFAULT_NR 12 + #define MLXPLAT_CPLD_FAN3_DEFAULT_NR 13 +@@ -645,6 +677,38 @@ static struct i2c_mux_reg_platform_data mlxplat_ng800_mux_data[] = { + + }; + ++/* Platform channels for XDR system family */ ++static const int mlxplat_xdr_channels[] = { ++ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, ++ 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, ++ 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, ++ 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64 ++}; ++ ++/* Platform XDR mux data */ ++static struct i2c_mux_reg_platform_data mlxplat_xdr_mux_data[] = { ++ { ++ .parent = 1, ++ .base_nr = MLXPLAT_CPLD_CH1, ++ .write_only = 1, ++ .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG1, ++ .reg_size = 1, ++ .idle_in_use = 1, ++ .values = mlxplat_xdr_channels, ++ .n_values = ARRAY_SIZE(mlxplat_xdr_channels), ++ }, ++ { ++ .parent = 1, ++ .base_nr = MLXPLAT_CPLD_CH2_XDR, ++ .write_only = 1, ++ .reg = (void __iomem *)MLXPLAT_CPLD_LPC_REG2, ++ .reg_size = 1, ++ .idle_in_use = 1, ++ .values = mlxplat_msn21xx_channels, ++ .n_values = ARRAY_SIZE(mlxplat_msn21xx_channels), ++ }, ++}; ++ + /* Platform hotplug devices */ + static struct i2c_board_info mlxplat_mlxcpld_pwr[] = { + { +@@ -664,6 +728,21 @@ static struct i2c_board_info mlxplat_mlxcpld_ext_pwr[] = { + }, + }; + ++static struct i2c_board_info mlxplat_mlxcpld_xdr_pwr[] = { ++ { ++ I2C_BOARD_INFO("dps460", 0x5d), ++ }, ++ { ++ I2C_BOARD_INFO("dps460", 0x5c), ++ }, ++ { ++ I2C_BOARD_INFO("dps460", 0x5e), ++ }, ++ { ++ I2C_BOARD_INFO("dps460", 0x5f), ++ }, ++}; ++ + static struct i2c_board_info mlxplat_mlxcpld_pwr_ng800[] = { + { + I2C_BOARD_INFO("dps460", 0x59), +@@ -1533,6 +1612,430 @@ static struct mlxreg_core_item mlxplat_mlxcpld_ng800_items[] = { + }, + }; + ++/* Platform hotplug XDR system family data */ ++static struct mlxreg_core_data mlxplat_mlxcpld_xdr_psu_items_data[] = { ++ { ++ .label = "psu1", ++ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, ++ .mask = BIT(0), ++ .slot = 1, ++ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, ++ }, ++ { ++ .label = "psu2", ++ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, ++ .mask = BIT(1), ++ .slot = 2, ++ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, ++ }, ++ { ++ .label = "psu3", ++ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, ++ .mask = BIT(2), ++ .slot = 3, ++ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, ++ }, ++ { ++ .label = "psu4", ++ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, ++ .mask = BIT(3), ++ .slot = 4, ++ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, ++ }, ++ { ++ .label = "psu5", ++ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, ++ .mask = BIT(4), ++ .slot = 5, ++ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, ++ }, ++ { ++ .label = "psu6", ++ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, ++ .mask = BIT(5), ++ .slot = 6, ++ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, ++ }, ++ { ++ .label = "psu7", ++ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, ++ .mask = BIT(6), ++ .slot = 7, ++ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, ++ }, ++ { ++ .label = "psu8", ++ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, ++ .mask = BIT(7), ++ .slot = 8, ++ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, ++ }, ++}; ++ ++static struct mlxreg_core_data mlxplat_mlxcpld_xdr_pwr_items_data[] = { ++ { ++ .label = "pwr1", ++ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, ++ .mask = BIT(0), ++ .slot = 1, ++ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, ++ .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[0], ++ .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, ++ }, ++ { ++ .label = "pwr2", ++ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, ++ .mask = BIT(1), ++ .slot = 2, ++ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, ++ .hpdev.brdinfo = &mlxplat_mlxcpld_pwr[1], ++ .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, ++ }, ++ { ++ .label = "pwr3", ++ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, ++ .mask = BIT(2), ++ .slot = 3, ++ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, ++ .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[0], ++ .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, ++ }, ++ { ++ .label = "pwr4", ++ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, ++ .mask = BIT(3), ++ .slot = 4, ++ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, ++ .hpdev.brdinfo = &mlxplat_mlxcpld_ext_pwr[1], ++ .hpdev.nr = MLXPLAT_CPLD_PSU_MSNXXXX_NR, ++ }, ++ { ++ .label = "pwr5", ++ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, ++ .mask = BIT(4), ++ .slot = 5, ++ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, ++ .hpdev.brdinfo = &mlxplat_mlxcpld_xdr_pwr[0], ++ .hpdev.nr = MLXPLAT_CPLD_PSU_XDR_NR, ++ }, ++ { ++ .label = "pwr6", ++ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, ++ .mask = BIT(5), ++ .slot = 6, ++ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, ++ .hpdev.brdinfo = &mlxplat_mlxcpld_xdr_pwr[1], ++ .hpdev.nr = MLXPLAT_CPLD_PSU_XDR_NR, ++ }, ++ { ++ .label = "pwr7", ++ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, ++ .mask = BIT(6), ++ .slot = 7, ++ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, ++ .hpdev.brdinfo = &mlxplat_mlxcpld_xdr_pwr[2], ++ .hpdev.nr = MLXPLAT_CPLD_PSU_XDR_NR, ++ }, ++ { ++ .label = "pwr8", ++ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, ++ .mask = BIT(7), ++ .slot = 8, ++ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, ++ .hpdev.brdinfo = &mlxplat_mlxcpld_xdr_pwr[3], ++ .hpdev.nr = MLXPLAT_CPLD_PSU_XDR_NR, ++ }, ++}; ++ ++static struct mlxreg_core_data mlxplat_mlxcpld_xdr_fan_items_data[] = { ++ { ++ .label = "fan1", ++ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ .mask = BIT(0), ++ .slot = 1, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, ++ .bit = BIT(0), ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, ++ }, ++ { ++ .label = "fan2", ++ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ .mask = BIT(1), ++ .slot = 2, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, ++ .bit = BIT(1), ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, ++ }, ++ { ++ .label = "fan3", ++ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ .mask = BIT(2), ++ .slot = 3, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, ++ .bit = BIT(2), ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, ++ }, ++ { ++ .label = "fan4", ++ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ .mask = BIT(3), ++ .slot = 4, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, ++ .bit = BIT(3), ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, ++ }, ++ { ++ .label = "fan5", ++ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ .mask = BIT(4), ++ .slot = 5, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, ++ .bit = BIT(4), ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, ++ }, ++ { ++ .label = "fan6", ++ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ .mask = BIT(5), ++ .slot = 6, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, ++ .bit = BIT(5), ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, ++ }, ++ { ++ .label = "fan7", ++ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ .mask = BIT(6), ++ .slot = 7, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, ++ .bit = BIT(6), ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, ++ }, ++ { ++ .label = "fan8", ++ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ .mask = BIT(7), ++ .slot = 8, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, ++ .bit = BIT(7), ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, ++ }, ++}; ++ ++static struct mlxreg_core_data mlxplat_mlxcpld_xdr_ext_fan_items_data[] = { ++ { ++ .label = "fan9", ++ .reg = MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET, ++ .mask = BIT(0), ++ .slot = 9, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, ++ .bit = BIT(0), ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, ++ }, ++ { ++ .label = "fan10", ++ .reg = MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET, ++ .mask = BIT(1), ++ .slot = 10, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, ++ .bit = BIT(1), ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, ++ }, ++ { ++ .label = "fan11", ++ .reg = MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET, ++ .mask = BIT(2), ++ .slot = 11, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, ++ .bit = BIT(2), ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, ++ }, ++ { ++ .label = "fan12", ++ .reg = MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET, ++ .mask = BIT(3), ++ .slot = 12, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_FAN_XDR_MASK, ++ .bit = BIT(3), ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, ++ }, ++}; ++ ++static struct mlxreg_core_data mlxplat_mlxcpld_xdr_asic1_items_data[] = { ++ { ++ .label = "asic1", ++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, ++ .mask = MLXPLAT_CPLD_ASIC_MASK, ++ .slot = 1, ++ .capability = MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_ASIC_XDR_MASK, ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, ++ } ++}; ++ ++static struct mlxreg_core_data mlxplat_mlxcpld_xdr_asic2_items_data[] = { ++ { ++ .label = "asic2", ++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET, ++ .mask = MLXPLAT_CPLD_ASIC_MASK, ++ .slot = 2, ++ .capability = MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_ASIC_CAP_MASK, ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, ++ } ++}; ++ ++static struct mlxreg_core_data mlxplat_mlxcpld_xdr_asic3_items_data[] = { ++ { ++ .label = "asic3", ++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC3_HEALTH_OFFSET, ++ .mask = MLXPLAT_CPLD_ASIC_MASK, ++ .slot = 3, ++ .capability = MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_ASIC_CAP_MASK, ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, ++ } ++}; ++ ++static struct mlxreg_core_data mlxplat_mlxcpld_xdr_asic4_items_data[] = { ++ { ++ .label = "asic4", ++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC4_HEALTH_OFFSET, ++ .mask = MLXPLAT_CPLD_ASIC_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_ASIC_CAP_MASK, ++ .slot = 4, ++ .hpdev.nr = MLXPLAT_CPLD_NR_NONE, ++ } ++}; ++ ++static struct mlxreg_core_item mlxplat_mlxcpld_xdr_items[] = { ++ { ++ .data = mlxplat_mlxcpld_xdr_psu_items_data, ++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, ++ .reg = MLXPLAT_CPLD_LPC_REG_PSU_OFFSET, ++ .mask = MLXPLAT_CPLD_PSU_XDR_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_psu_items_data), ++ .inversed = 1, ++ .health = false, ++ }, ++ { ++ .data = mlxplat_mlxcpld_xdr_pwr_items_data, ++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, ++ .reg = MLXPLAT_CPLD_LPC_REG_PWR_OFFSET, ++ .mask = MLXPLAT_CPLD_PWR_XDR_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_PSU_CAP_MASK, ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_pwr_items_data), ++ .inversed = 0, ++ .health = false, ++ }, ++ { ++ .data = mlxplat_mlxcpld_xdr_fan_items_data, ++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, ++ .reg = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ .mask = MLXPLAT_CPLD_FAN_XDR_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_FAN_CAP_MASK, ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_fan_items_data), ++ .inversed = 1, ++ .health = false, ++ }, ++ { ++ .data = mlxplat_mlxcpld_xdr_ext_fan_items_data, ++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, ++ .reg = MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET, ++ .mask = MLXPLAT_CPLD_FAN_XDR_EXT_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_FAN_CAP_MASK, ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_ext_fan_items_data), ++ .inversed = 1, ++ .health = false, ++ }, ++ { ++ .data = mlxplat_mlxcpld_xdr_asic1_items_data, ++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, ++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET, ++ .mask = MLXPLAT_CPLD_ASIC_XDR_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_ASIC_CAP_MASK, ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_asic1_items_data), ++ .inversed = 0, ++ .health = true, ++ }, ++ { ++ .data = mlxplat_mlxcpld_xdr_asic2_items_data, ++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, ++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET, ++ .mask = MLXPLAT_CPLD_ASIC_XDR_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_ASIC_CAP_MASK, ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_asic2_items_data), ++ .inversed = 0, ++ .health = true, ++ }, ++ { ++ .data = mlxplat_mlxcpld_xdr_asic3_items_data, ++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, ++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC3_HEALTH_OFFSET, ++ .mask = MLXPLAT_CPLD_ASIC_XDR_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_ASIC_XDR_MASK, ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_asic3_items_data), ++ .inversed = 0, ++ .health = true, ++ }, ++ { ++ .data = mlxplat_mlxcpld_xdr_asic4_items_data, ++ .aggr_mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF, ++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC4_HEALTH_OFFSET, ++ .mask = MLXPLAT_CPLD_ASIC_XDR_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET, ++ .capability_mask = MLXPLAT_CPLD_ASIC_XDR_MASK, ++ .count = ARRAY_SIZE(mlxplat_mlxcpld_xdr_asic4_items_data), ++ .inversed = 0, ++ .health = true, ++ }, ++}; ++ + static + struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ext_data = { + .items = mlxplat_mlxcpld_ext_items, +@@ -1553,6 +2056,16 @@ struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ng800_data = { + .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_LOW | MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2, + }; + ++static ++struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_xdr_data = { ++ .items = mlxplat_mlxcpld_xdr_items, ++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_xdr_items), ++ .cell = MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET, ++ .mask = MLXPLAT_CPLD_AGGR_MASK_NG_DEF | MLXPLAT_CPLD_AGGR_MASK_COMEX, ++ .cell_low = MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET, ++ .mask_low = MLXPLAT_CPLD_LOW_AGGR_MASK_FRU | MLXPLAT_CPLD_LOW_AGGR_MASK_MULTI_ASICS, ++}; ++ + static struct mlxreg_core_data mlxplat_mlxcpld_modular_pwr_items_data[] = { + { + .label = "pwr1", +@@ -3395,35 +3908,209 @@ static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_led_data[] = { + .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, +- .bit = BIT(3), ++ .bit = BIT(3), ++ }, ++ { ++ .label = "fan5:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .bit = BIT(4), ++ }, ++ { ++ .label = "fan5:orange", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .bit = BIT(4), ++ }, ++ { ++ .label = "fan6:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .bit = BIT(5), ++ }, ++ { ++ .label = "fan6:orange", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .bit = BIT(5), ++ }, ++ { ++ .label = "uid:blue", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED5_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ }, ++}; ++ ++static struct mlxreg_core_platform_data mlxplat_l1_switch_led_data = { ++ .data = mlxplat_mlxcpld_l1_switch_led_data, ++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_led_data), ++}; ++ ++/* Platform led data for XDR systems */ ++static struct mlxreg_core_data mlxplat_mlxcpld_xdr_led_data[] = { ++ { ++ .label = "status:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ }, ++ { ++ .label = "status:amber", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK ++ }, ++ { ++ .label = "psu:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ }, ++ { ++ .label = "psu:amber", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED1_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ }, ++ { ++ .label = "fan1:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .slot = 1, ++ }, ++ { ++ .label = "fan1:amber", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .slot = 1, ++ }, ++ { ++ .label = "fan2:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .slot = 2, ++ }, ++ { ++ .label = "fan2:amber", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED2_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .slot = 2, ++ }, ++ { ++ .label = "fan3:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .slot = 3, ++ }, ++ { ++ .label = "fan3:amber", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .slot = 3, ++ }, ++ { ++ .label = "fan4:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .slot = 4, ++ }, ++ { ++ .label = "fan4:amber", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED3_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .slot = 4, ++ }, ++ { ++ .label = "fan5:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .slot = 5, ++ }, ++ { ++ .label = "fan5:amber", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .slot = 5, ++ }, ++ { ++ .label = "fan6:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .slot = 6, ++ }, ++ { ++ .label = "fan6:amber", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .slot = 6, ++ }, ++ { ++ .label = "fan7:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .slot = 7, ++ }, ++ { ++ .label = "fan7:amber", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED6_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .slot = 7, + }, + { +- .label = "fan5:green", +- .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, ++ .label = "fan8:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, +- .bit = BIT(4), ++ .slot = 8, + }, + { +- .label = "fan5:orange", +- .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, ++ .label = "fan8:amber", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, + .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, +- .bit = BIT(4), ++ .slot = 8, + }, + { +- .label = "fan6:green", +- .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, ++ .label = "fan9:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, +- .bit = BIT(5), ++ .slot = 9, + }, + { +- .label = "fan6:orange", +- .reg = MLXPLAT_CPLD_LPC_REG_LED4_OFFSET, ++ .label = "fan9:amber", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED7_OFFSET, + .mask = MLXPLAT_CPLD_LED_HI_NIBBLE_MASK, + .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, +- .bit = BIT(5), ++ .slot = 9, ++ }, ++ { ++ .label = "fan10:green", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED8_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .slot = 10, ++ }, ++ { ++ .label = "fan10:amber", ++ .reg = MLXPLAT_CPLD_LPC_REG_LED8_OFFSET, ++ .mask = MLXPLAT_CPLD_LED_LO_NIBBLE_MASK, ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .slot = 10, + }, + { + .label = "uid:blue", +@@ -3432,9 +4119,9 @@ static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_led_data[] = { + }, + }; + +-static struct mlxreg_core_platform_data mlxplat_l1_switch_led_data = { +- .data = mlxplat_mlxcpld_l1_switch_led_data, +- .counter = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_led_data), ++static struct mlxreg_core_platform_data mlxplat_xdr_led_data = { ++ .data = mlxplat_mlxcpld_xdr_led_data, ++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_xdr_led_data), + }; + + /* Platform register access default */ +@@ -3733,6 +4420,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { + .bit = GENMASK(7, 0), + .mode = 0444, + }, ++ { ++ .label = "cpld6_version", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD6_VER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, + { + .label = "cpld1_pn", + .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET, +@@ -3768,6 +4461,13 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { + .mode = 0444, + .regnum = 2, + }, ++ { ++ .label = "cpld6_pn", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD6_PN_OFFSET, ++ .bit = GENMASK(15, 0), ++ .mode = 0444, ++ .regnum = 2, ++ }, + { + .label = "cpld1_version_min", + .reg = MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET, +@@ -3798,6 +4498,12 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { + .bit = GENMASK(7, 0), + .mode = 0444, + }, ++ { ++ .label = "cpld6_version_min", ++ .reg = MLXPLAT_CPLD_LPC_REG_CPLD6_MVER_OFFSET, ++ .bit = GENMASK(7, 0), ++ .mode = 0444, ++ }, + { + .label = "asic_reset", + .reg = MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET, +@@ -3984,6 +4690,43 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { + .mask = GENMASK(7, 0) & ~BIT(1), + .mode = 0200, + }, ++ { ++ .label = "psu3_on", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(4), ++ .mode = 0200, ++ }, ++ { ++ .label = "psu4_on", ++ .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(7), ++ .mode = 0200, ++ }, ++ { ++ .label = "psu5_on", ++ .reg = MLXPLAT_CPLD_LPC_REG_WP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(0), ++ .mode = 0200, ++ }, ++ ++ { ++ .label = "psu6_on", ++ .reg = MLXPLAT_CPLD_LPC_REG_WP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(1), ++ .mode = 0200, ++ }, ++ { ++ .label = "psu7_on", ++ .reg = MLXPLAT_CPLD_LPC_REG_WP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(2), ++ .mode = 0200, ++ }, ++ { ++ .label = "psu8_on", ++ .reg = MLXPLAT_CPLD_LPC_REG_WP1_OFFSET, ++ .mask = GENMASK(7, 0) & ~BIT(3), ++ .mode = 0200, ++ }, + { + .label = "pwr_cycle", + .reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET, +@@ -4059,6 +4802,20 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = { + .bit = 1, + .mode = 0444, + }, ++ { ++ .label = "asic3_health", ++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC3_HEALTH_OFFSET, ++ .mask = MLXPLAT_CPLD_ASIC_MASK, ++ .bit = 1, ++ .mode = 0444, ++ }, ++ { ++ .label = "asic4_health", ++ .reg = MLXPLAT_CPLD_LPC_REG_ASIC4_HEALTH_OFFSET, ++ .mask = MLXPLAT_CPLD_ASIC_MASK, ++ .bit = 1, ++ .mode = 0444, ++ }, + { + .label = "fan_dir", + .reg = MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION, +@@ -5129,6 +5886,193 @@ static struct mlxreg_core_platform_data mlxplat_qmb8700_fan_data = { + .counter = ARRAY_SIZE(mlxplat_mlxcpld_qmb8700_fan_data), + }; + ++/* XDR platform fan data */ ++static struct mlxreg_core_data mlxplat_mlxcpld_xdr_fan_data[] = { ++ { ++ .label = "pwm1", ++ .reg = MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET, ++ }, ++ { ++ .label = "pwm2", ++ .reg = MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET, ++ }, ++ { ++ .label = "pwm3", ++ .reg = MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET, ++ }, ++ { ++ .label = "pwm4", ++ .reg = MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET, ++ }, ++ { ++ .label = "tacho1", ++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, ++ .slot = 1, ++ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho2", ++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, ++ .slot = 2, ++ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho3", ++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, ++ .slot = 3, ++ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho4", ++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, ++ .slot = 4, ++ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho5", ++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, ++ .slot = 5, ++ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho6", ++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, ++ .slot = 6, ++ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho7", ++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, ++ .slot = 7, ++ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho8", ++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, ++ .slot = 8, ++ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho9", ++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, ++ .slot = 9, ++ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho10", ++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, ++ .slot = 10, ++ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho11", ++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, ++ .slot = 11, ++ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho12", ++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, ++ .slot = 12, ++ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho13", ++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, ++ .slot = 13, ++ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho14", ++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, ++ .slot = 14, ++ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho15", ++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO15_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, ++ .slot = 15, ++ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho16", ++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO16_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, ++ .slot = 16, ++ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN_OFFSET, ++ }, ++ { ++ .label = "tacho17", ++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO17_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, ++ .slot = 17, ++ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET, ++ }, ++ { ++ .label = "tacho18", ++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO18_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, ++ .slot = 18, ++ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET, ++ }, ++ { ++ .label = "tacho19", ++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO19_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, ++ .slot = 19, ++ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET, ++ }, ++ { ++ .label = "tacho20", ++ .reg = MLXPLAT_CPLD_LPC_REG_TACHO20_OFFSET, ++ .mask = GENMASK(7, 0), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET, ++ .slot = 20, ++ .reg_prsnt = MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET, ++ }, ++}; ++ ++static struct mlxreg_core_platform_data mlxplat_xdr_fan_data = { ++ .data = mlxplat_mlxcpld_xdr_fan_data, ++ .counter = ARRAY_SIZE(mlxplat_mlxcpld_xdr_fan_data), ++ .capability = MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET, ++ .version = 1, ++}; ++ + /* Watchdog type1: hardware implementation version1 + * (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140 systems). + */ +@@ -5361,6 +6305,7 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_LED8_OFFSET: + case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET: + case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET: + case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET: +@@ -5388,12 +6333,18 @@ static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_ASIC3_EVENT_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_ASIC3_MASK_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_ASIC4_EVENT_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_ASIC4_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_FAN2_EVENT_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_FAN2_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET: +@@ -5452,6 +6402,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET: + case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET: + case MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_CPLD6_VER_OFFSET: + case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET: + case MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET: + case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET: +@@ -5462,6 +6413,8 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET: + case MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET: + case MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_CPLD6_PN_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_CPLD6_PN1_OFFSET: + case MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET: + case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: + case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET: +@@ -5474,6 +6427,7 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_LED8_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION: + case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET: + case MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET: +@@ -5511,6 +6465,12 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET: + case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_ASIC3_HEALTH_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_ASIC3_EVENT_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_ASIC3_MASK_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_ASIC4_HEALTH_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_ASIC4_EVENT_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_ASIC4_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: +@@ -5520,6 +6480,9 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_FAN2_EVENT_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_FAN2_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_EROT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET: +@@ -5593,6 +6556,13 @@ static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET: + case MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET: + case MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_TACHO15_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_TACHO16_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_TACHO17_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_TACHO18_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_TACHO19_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_TACHO20_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET: +@@ -5618,6 +6588,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET: + case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET: + case MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_CPLD6_VER_OFFSET: + case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET: + case MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET: + case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET: +@@ -5628,6 +6599,8 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET: + case MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET: + case MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_CPLD6_PN_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_CPLD6_PN1_OFFSET: + case MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET: + case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET: + case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET: +@@ -5640,6 +6613,7 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET: + case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_LED8_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION: + case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET: + case MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET: +@@ -5675,6 +6649,12 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET: + case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_ASIC3_HEALTH_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_ASIC3_EVENT_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_ASIC3_MASK_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_ASIC4_HEALTH_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_ASIC4_EVENT_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_ASIC4_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET: +@@ -5684,6 +6664,9 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_FAN2_EVENT_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_FAN2_MASK_OFFSET: + case MLXPLAT_CPLD_LPC_REG_EROT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET: + case MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET: +@@ -5751,6 +6734,13 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg) + case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET: + case MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET: + case MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_TACHO15_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_TACHO16_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_TACHO17_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_TACHO18_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_TACHO19_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_TACHO20_OFFSET: ++ case MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET: + case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET: + case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET: +@@ -6472,6 +7462,27 @@ static int __init mlxplat_dmi_bf3_comex_default_matched(const struct dmi_system_ + return 1; + } + ++static int __init mlxplat_dmi_xdr_matched(const struct dmi_system_id *dmi) ++{ ++ int i; ++ ++ mlxplat_max_adap_num = MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM; ++ mlxplat_mux_num = ARRAY_SIZE(mlxplat_xdr_mux_data); ++ mlxplat_mux_data = mlxplat_xdr_mux_data; ++ mlxplat_hotplug = &mlxplat_mlxcpld_xdr_data; ++ mlxplat_hotplug->deferred_nr = ++ mlxplat_msn21xx_channels[MLXPLAT_CPLD_GRP_CHNL_NUM - 1]; ++ mlxplat_led = &mlxplat_xdr_led_data; ++ mlxplat_regs_io = &mlxplat_default_ng_regs_io_data; ++ mlxplat_fan = &mlxplat_xdr_fan_data; ++ for (i = 0; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++) ++ mlxplat_wd_data[i] = &mlxplat_mlxcpld_wd_set_type2[i]; ++ mlxplat_i2c = &mlxplat_mlxcpld_i2c_ng_data; ++ mlxplat_regmap_config = &mlxplat_mlxcpld_regmap_config_ng400; ++ ++ return mlxplat_register_platform_device(); ++} ++ + static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { + { + .callback = mlxplat_dmi_default_wc_matched, +@@ -6579,6 +7590,12 @@ static const struct dmi_system_id mlxplat_dmi_table[] __initconst = { + DMI_MATCH(DMI_BOARD_NAME, "VMOD0017"), + }, + }, ++ { ++ .callback = mlxplat_dmi_xdr_matched, ++ .matches = { ++ DMI_MATCH(DMI_BOARD_NAME, "VMOD0018"), ++ }, ++ }, + { + .callback = mlxplat_dmi_msn274x_matched, + .matches = { +-- +2.14.1 +