-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathvivado.log
261 lines (259 loc) · 21.4 KB
/
vivado.log
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
#-----------------------------------------------------------
# Vivado v2020.2 (64-bit)
# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
# IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
# Start of session at: Mon Apr 5 17:53:21 2021
# Process ID: 8072
# Current directory: C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent4908 C:\Users\mathe\Desktop\Facul\vivado\PEDproj\somador_subtrator4bits\somador_subtrator4bits.xpr
# Log file: C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/vivado.log
# Journal file: C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits\vivado.jou
#-----------------------------------------------------------
start_gui
open_project C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.xpr
WARNING: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.gen/sources_1'.
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2020.2/data/ip'.
update_compile_order -fileset sources_1
update_compile_order -fileset sources_1
update_compile_order -fileset sim_1
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'Soma4_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj Soma4_tb_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.srcs/sources_1/new/Soma1.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'Soma1'
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.srcs/sources_1/new/Soma4.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'Soma4'
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.srcs/sim_1/new/Soma4_tb.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'Soma4_tb'
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.sim/sim_1/behav/xsim'
"xelab -wto 97f9aef94e85417f91406d9e8908a592 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Soma4_tb_behav xil_defaultlib.Soma4_tb -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: D:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 97f9aef94e85417f91406d9e8908a592 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Soma4_tb_behav xil_defaultlib.Soma4_tb -log elaborate.log
Using 2 slave threads.
Starting static elaboration
ERROR: [VRFC 10-3311] expression has 4 elements ; formal 'b4' expects 1 [C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.srcs/sim_1/new/Soma4_tb.vhd:24]
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit soma4_tb in library work failed.
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
INFO: [USF-XSim-99] Step results log file:'C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.sim/sim_1/behav/xsim/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.sim/sim_1/behav/xsim/elaborate.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'Soma4_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj Soma4_tb_vhdl.prj"
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.sim/sim_1/behav/xsim'
"xelab -wto 97f9aef94e85417f91406d9e8908a592 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Soma4_tb_behav xil_defaultlib.Soma4_tb -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: D:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 97f9aef94e85417f91406d9e8908a592 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Soma4_tb_behav xil_defaultlib.Soma4_tb -log elaborate.log
Using 2 slave threads.
Starting static elaboration
ERROR: [VRFC 10-3311] expression has 4 elements ; formal 'b4' expects 1 [C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.srcs/sim_1/new/Soma4_tb.vhd:24]
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit soma4_tb in library work failed.
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
INFO: [USF-XSim-99] Step results log file:'C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.sim/sim_1/behav/xsim/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.sim/sim_1/behav/xsim/elaborate.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'Soma4_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj Soma4_tb_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.srcs/sim_1/new/Soma4_tb.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'Soma4_tb'
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.sim/sim_1/behav/xsim'
"xelab -wto 97f9aef94e85417f91406d9e8908a592 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Soma4_tb_behav xil_defaultlib.Soma4_tb -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: D:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 97f9aef94e85417f91406d9e8908a592 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Soma4_tb_behav xil_defaultlib.Soma4_tb -log elaborate.log
Using 2 slave threads.
Starting static elaboration
ERROR: [VRFC 10-3311] expression has 4 elements ; formal 'b4' expects 1 [C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.srcs/sim_1/new/Soma4_tb.vhd:24]
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit soma4_tb in library work failed.
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
INFO: [USF-XSim-99] Step results log file:'C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.sim/sim_1/behav/xsim/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.sim/sim_1/behav/xsim/elaborate.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'Soma4_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj Soma4_tb_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.srcs/sim_1/new/Soma4_tb.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'Soma4_tb'
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.sim/sim_1/behav/xsim'
"xelab -wto 97f9aef94e85417f91406d9e8908a592 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Soma4_tb_behav xil_defaultlib.Soma4_tb -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: D:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 97f9aef94e85417f91406d9e8908a592 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Soma4_tb_behav xil_defaultlib.Soma4_tb -log elaborate.log
Using 2 slave threads.
Starting static elaboration
ERROR: [VRFC 10-3311] expression has 4 elements ; formal 'b4' expects 1 [C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.srcs/sim_1/new/Soma4_tb.vhd:24]
ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit soma4_tb in library work failed.
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
INFO: [USF-XSim-99] Step results log file:'C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.sim/sim_1/behav/xsim/elaborate.log'
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.sim/sim_1/behav/xsim/elaborate.log' file for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'Soma4_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj Soma4_tb_vhdl.prj"
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.srcs/sources_1/new/Soma4.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'Soma4'
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.srcs/sim_1/new/Soma4_tb.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'Soma4_tb'
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.sim/sim_1/behav/xsim'
"xelab -wto 97f9aef94e85417f91406d9e8908a592 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Soma4_tb_behav xil_defaultlib.Soma4_tb -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: D:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 97f9aef94e85417f91406d9e8908a592 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Soma4_tb_behav xil_defaultlib.Soma4_tb -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling architecture behavioral of entity xil_defaultlib.Soma1 [soma1_default]
Compiling architecture behavioral of entity xil_defaultlib.Soma4 [soma4_default]
Compiling architecture behavioral of entity xil_defaultlib.soma4_tb
Built simulation snapshot Soma4_tb_behav
****** Webtalk v2020.2 (64-bit)
**** SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
**** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
source C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.sim/sim_1/behav/xsim/xsim.dir/Soma4_tb_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-186] 'C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.sim/sim_1/behav/xsim/xsim.dir/Soma4_tb_behav/webtalk/usage_statistics_ext_xsim.xml' has been successfully sent to Xilinx on Mon Apr 5 18:58:54 2021. For additional details about this file, please refer to the WebTalk help file at D:/Xilinx/Vivado/2020.2/doc/webtalk_introduction.html.
INFO: [Common 17-206] Exiting Webtalk at Mon Apr 5 18:58:54 2021...
run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:12 . Memory (MB): peak = 1014.770 ; gain = 0.000
INFO: [USF-XSim-69] 'elaborate' step finished in '12' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "Soma4_tb_behav -key {Behavioral:sim_1:Functional:Soma4_tb} -tclbatch {Soma4_tb.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2020.2
Time resolution is 1 ps
source Soma4_tb.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
INFO: [USF-XSim-96] XSim completed. Design snapshot 'Soma4_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:16 . Memory (MB): peak = 1014.770 ; gain = 0.000
relaunch_sim
suspend_sim: Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 1014.770 ; gain = 0.000
Command: launch_simulation -simset sim_1 -mode behavioral
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'Soma4_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj Soma4_tb_vhdl.prj"
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
Command: launch_simulation -simset sim_1 -mode behavioral
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.sim/sim_1/behav/xsim'
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.sim/sim_1/behav/xsim'
"xelab -wto 97f9aef94e85417f91406d9e8908a592 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Soma4_tb_behav xil_defaultlib.Soma4_tb -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: D:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 97f9aef94e85417f91406d9e8908a592 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Soma4_tb_behav xil_defaultlib.Soma4_tb -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
Vivado Simulator 2020.2
Time resolution is 1 ps
relaunch_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:11 . Memory (MB): peak = 1014.770 ; gain = 0.000
relaunch_sim
Command: launch_simulation -simset sim_1 -mode behavioral
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-54] Inspecting design source files for 'Soma4_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.sim/sim_1/behav/xsim'
"xvhdl --incr --relax -prj Soma4_tb_vhdl.prj"
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
Command: launch_simulation -simset sim_1 -mode behavioral
INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.sim/sim_1/behav/xsim'
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/mathe/Desktop/Facul/vivado/PEDproj/somador_subtrator4bits/somador_subtrator4bits.sim/sim_1/behav/xsim'
"xelab -wto 97f9aef94e85417f91406d9e8908a592 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Soma4_tb_behav xil_defaultlib.Soma4_tb -log elaborate.log"
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: D:/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 97f9aef94e85417f91406d9e8908a592 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Soma4_tb_behav xil_defaultlib.Soma4_tb -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
Vivado Simulator 2020.2
Time resolution is 1 ps
relaunch_sim: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 1014.770 ; gain = 0.000
close_sim
INFO: [Simtcl 6-16] Simulation closed
exit
INFO: [Common 17-206] Exiting Vivado at Mon Apr 5 19:29:40 2021...