From ef79b81455d01925c4383f5b09e6a27859b9065b Mon Sep 17 00:00:00 2001
From: Geoffrey Guindine <geoffreyguindine@Geoffreys-MacBook-Air.local>
Date: Fri, 5 Apr 2024 17:44:01 -0400
Subject: [PATCH] design: working on memory sub

---
 rtl/ahb/devices/SubMemCtrl.sv | 69 +++++++++++++++++++++++++++++++++--
 1 file changed, 65 insertions(+), 4 deletions(-)

diff --git a/rtl/ahb/devices/SubMemCtrl.sv b/rtl/ahb/devices/SubMemCtrl.sv
index 0d29b4c..65dedbf 100644
--- a/rtl/ahb/devices/SubMemCtrl.sv
+++ b/rtl/ahb/devices/SubMemCtrl.sv
@@ -4,10 +4,71 @@
   @note See https://github.com/NYU-Processor-Design/nyu-mem
 */
 
-module SubMemCtrl(
-  AHBCommon_if.subordinate sub,
-  MemCommon_if.memCtrl mem
+/**
+  @brief Subordinate to interface witht he memory controller
+
+  @note See https://github.com/NYU-Processor-Design/nyu-mem
+*/
+
+module SubMemCtrl #(
+    parameter ADDR_WIDTH = 32,  // Address width
+    parameter DATA_WIDTH = 32   // Data width
+)(
+    input wire                       HCLK,       // clock
+    input wire                       HRESETn,    // reset
+    input wire [ADDR_WIDTH-1:0]      HADDR,      // address
+    input wire                       HWRITE,     // write
+    input wire [1:0]                 HTRANS,     // transfer
+    input wire [2:0]                 HSIZE,      // tranfer size
+    input wire [DATA_WIDTH-1:0]      HWDATA,     // write data
+    output wire [DATA_WIDTH-1:0]     HRDATA,     // read data
+    output wire                      HREADY,     // transfer ready
+    output wire [1:0]                HRESP,      // transfer response
+    // Memory Controller Interface
+    output wire [ADDR_WIDTH-1:0]     MemAddr,    // Memory address
+    output wire                      MemWrite,   // Memory write enable
+    output wire [DATA_WIDTH-1:0]     MemWData,   // Memory write data
+    input wire [DATA_WIDTH-1:0]      MemRData,   // Memory read data
+    output wire                      MemReq,     // Memory request signal
+    input wire                       MemReady    // Memory ready signal
 );
-  // General subordinate logic follows
+
+    reg [DATA_WIDTH-1:0] internalRData;
+    reg                   internalReady;
+    reg [1:0]             internalResp;
+
+    assign HRDATA = internalRData;
+    assign HREADY = internalReady;
+    assign HRESP = internalResp;
+    
+    assign MemAddr = HADDR;
+    assign MemWrite = HWRITE && (HTRANS[1] && HREADY);  // init write
+    assign MemWData = HWDATA;
+    assign MemReq = HTRANS[1] && HREADY;  // Transfer request signal
+
+    // AHB to Memory Controller Interface Logic
+    always @(posedge HCLK or negedge HRESETn) begin
+        if (!HRESETn) begin
+            internalRData <= 0;
+            internalReady <= 0;
+            internalResp <= 2'b00; // OKAY
+        end else begin
+            internalReady <= MemReady;
+            if (MemReady) begin
+                if (HWRITE) begin
+                    // handle write
+                    internalResp <= 2'b00; // OKAY
+                end else begin
+                    // handle read
+                    internalRData <= MemRData;
+                    internalResp <= 2'b00; // OKAY
+                end
+            end else begin
+                internalResp <= 2'b01; // WAIT state
+            end
+        end
+    end
 
 endmodule
+
+