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docs(dn): Ben 3-10-2024
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src/design_notebooks/2024fall/zf2179.md

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@@ -16,4 +16,13 @@ The work enviorment was pretty struggling and especially how to getting used to
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Project work:
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* [onboarding lab 2](https://github.com/BenFeng666/onboarding-lab-2): working on it.
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There is a project for my electronics course and I spent most of my week on it. I just finished exercise 1 in the lab 2, and expecting to finish them next week.
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There is a project for my electronics course and I spent most of my week on it. I just finished exercise 1 in the lab 2, and expecting to finish them next week.
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## week 5 of 3 October 2024
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Project work:
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* [onboarding lab 2](https://github.com/BenFeng666/onboarding-lab-2/tree/main): finished
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I finished lab 2 this week, and review some basic verilog content like how to use clock to indicate when will the program start and how to assign output based on the what the input is.
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The verilog grammar struggle me for a while since I haven't touch it for the entire summer so I have to look up in the internet to check how to write the correct verilog code. Also, I spent some time with understanding what the question is asking for, and eventually I think I figure it out? Maybe.

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